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4562236b HW |
1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | #ifndef DC_TYPES_H_ | |
26 | #define DC_TYPES_H_ | |
27 | ||
0417df16 BZ |
28 | /* AND EdidUtility only needs a portion |
29 | * of this file, including the rest only | |
30 | * causes additional issues. | |
31 | */ | |
eb0e5154 | 32 | #include "os_types.h" |
4562236b HW |
33 | #include "fixed31_32.h" |
34 | #include "irq_types.h" | |
5ca38a18 | 35 | #include "dc_ddc_types.h" |
4562236b | 36 | #include "dc_dp_types.h" |
a98cdd8c | 37 | #include "dc_hdmi_types.h" |
4562236b HW |
38 | #include "dc_hw_types.h" |
39 | #include "dal_types.h" | |
9f72f51d | 40 | #include "grph_object_defs.h" |
7ae1dbe6 | 41 | #include "grph_object_ctrl_defs.h" |
4562236b | 42 | |
d462fcf5 | 43 | #include "dm_cp_psp.h" |
d462fcf5 | 44 | |
4562236b | 45 | /* forward declarations */ |
c9614aeb | 46 | struct dc_plane_state; |
0971c40e | 47 | struct dc_stream_state; |
4562236b HW |
48 | struct dc_link; |
49 | struct dc_sink; | |
50 | struct dal; | |
3a1627b0 | 51 | struct dc_dmub_srv; |
4562236b HW |
52 | |
53 | /******************************** | |
54 | * Environment definitions | |
55 | ********************************/ | |
56 | enum dce_environment { | |
57 | DCE_ENV_PRODUCTION_DRV = 0, | |
58 | /* Emulation on FPGA, in "Maximus" System. | |
59 | * This environment enforces that *only* DC registers accessed. | |
60 | * (access to non-DC registers will hang FPGA) */ | |
61 | DCE_ENV_FPGA_MAXIMUS, | |
62 | /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces | |
63 | * requirements of Diagnostics team. */ | |
68c0fca5 JL |
64 | DCE_ENV_DIAG, |
65 | /* | |
66 | * Guest VM system, DC HW may exist but is not virtualized and | |
67 | * should not be used. SW support for VDI only. | |
68 | */ | |
69 | DCE_ENV_VIRTUAL_HW | |
4562236b HW |
70 | }; |
71 | ||
0cf5eb76 DF |
72 | struct dc_perf_trace { |
73 | unsigned long read_count; | |
74 | unsigned long write_count; | |
75 | unsigned long last_entry_read; | |
76 | unsigned long last_entry_write; | |
77 | }; | |
78 | ||
3cfd03b7 | 79 | #define MAX_SURFACE_NUM 6 |
4562236b | 80 | #define NUM_PIXEL_FORMATS 10 |
4562236b HW |
81 | |
82 | enum tiling_mode { | |
83 | TILING_MODE_INVALID, | |
84 | TILING_MODE_LINEAR, | |
85 | TILING_MODE_TILED, | |
86 | TILING_MODE_COUNT | |
87 | }; | |
88 | ||
89 | enum view_3d_format { | |
90 | VIEW_3D_FORMAT_NONE = 0, | |
91 | VIEW_3D_FORMAT_FRAME_SEQUENTIAL, | |
92 | VIEW_3D_FORMAT_SIDE_BY_SIDE, | |
93 | VIEW_3D_FORMAT_TOP_AND_BOTTOM, | |
94 | VIEW_3D_FORMAT_COUNT, | |
95 | VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL | |
96 | }; | |
97 | ||
98 | enum plane_stereo_format { | |
99 | PLANE_STEREO_FORMAT_NONE = 0, | |
100 | PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, | |
101 | PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, | |
102 | PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, | |
103 | PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, | |
104 | PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, | |
105 | PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 | |
106 | }; | |
107 | ||
108 | /* TODO: Find way to calculate number of bits | |
109 | * Please increase if pixel_format enum increases | |
110 | * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 | |
111 | */ | |
112 | ||
113 | enum dc_edid_connector_type { | |
8de94233 RA |
114 | DC_EDID_CONNECTOR_UNKNOWN = 0, |
115 | DC_EDID_CONNECTOR_ANALOG = 1, | |
116 | DC_EDID_CONNECTOR_DIGITAL = 10, | |
117 | DC_EDID_CONNECTOR_DVI = 11, | |
118 | DC_EDID_CONNECTOR_HDMIA = 12, | |
119 | DC_EDID_CONNECTOR_MDDI = 14, | |
120 | DC_EDID_CONNECTOR_DISPLAYPORT = 15 | |
4562236b HW |
121 | }; |
122 | ||
123 | enum dc_edid_status { | |
124 | EDID_OK, | |
125 | EDID_BAD_INPUT, | |
126 | EDID_NO_RESPONSE, | |
127 | EDID_BAD_CHECKSUM, | |
7d58e721 | 128 | EDID_THE_SAME, |
07c8176e | 129 | EDID_FALL_BACK, |
906fbba2 | 130 | EDID_PARTIAL_VALID, |
4562236b HW |
131 | }; |
132 | ||
48af9b91 AL |
133 | enum act_return_status { |
134 | ACT_SUCCESS, | |
135 | ACT_LINK_LOST, | |
136 | ACT_FAILED | |
137 | }; | |
138 | ||
4562236b HW |
139 | /* audio capability from EDID*/ |
140 | struct dc_cea_audio_mode { | |
141 | uint8_t format_code; /* ucData[0] [6:3]*/ | |
142 | uint8_t channel_count; /* ucData[0] [2:0]*/ | |
143 | uint8_t sample_rate; /* ucData[1]*/ | |
144 | union { | |
145 | uint8_t sample_size; /* for LPCM*/ | |
146 | /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ | |
147 | uint8_t max_bit_rate; | |
148 | uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ | |
149 | }; | |
150 | }; | |
151 | ||
152 | struct dc_edid { | |
153 | uint32_t length; | |
8de94233 | 154 | uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; |
4562236b HW |
155 | }; |
156 | ||
157 | /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION | |
158 | * is used. In this case we assume speaker location are: front left, front | |
159 | * right and front center. */ | |
160 | #define DEFAULT_SPEAKER_LOCATION 5 | |
161 | ||
162 | #define DC_MAX_AUDIO_DESC_COUNT 16 | |
163 | ||
164 | #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 | |
165 | ||
50e27654 ZF |
166 | union display_content_support { |
167 | unsigned int raw; | |
168 | struct { | |
169 | unsigned int valid_content_type :1; | |
170 | unsigned int game_content :1; | |
171 | unsigned int cinema_content :1; | |
172 | unsigned int photo_content :1; | |
173 | unsigned int graphics_content :1; | |
174 | unsigned int reserved :27; | |
175 | } bits; | |
176 | }; | |
177 | ||
243c46c5 | 178 | struct dc_panel_patch { |
b686ee20 | 179 | unsigned int dppowerup_delay; |
ff587987 | 180 | unsigned int extra_t12_ms; |
a4f1d2b8 | 181 | unsigned int extra_delay_backlight_off; |
88eac241 | 182 | unsigned int extra_t7_ms; |
a760fc1b | 183 | unsigned int skip_scdc_overwrite; |
dc326f61 | 184 | unsigned int delay_ignore_msa; |
8151306b | 185 | unsigned int disable_fec; |
6798d042 | 186 | unsigned int extra_t3_ms; |
9abdf392 | 187 | unsigned int max_dsc_target_bpp_limit; |
00fa7f03 RS |
188 | unsigned int embedded_tiled_slave; |
189 | unsigned int disable_fams; | |
74d021b5 | 190 | unsigned int skip_avmute; |
8bc3812d | 191 | unsigned int mst_start_top_delay; |
9fa8cc0c | 192 | unsigned int delay_disable_aux_intercept_ms; |
243c46c5 JB |
193 | }; |
194 | ||
4562236b HW |
195 | struct dc_edid_caps { |
196 | /* sink identification */ | |
197 | uint16_t manufacturer_id; | |
198 | uint16_t product_id; | |
199 | uint32_t serial_number; | |
200 | uint8_t manufacture_week; | |
201 | uint8_t manufacture_year; | |
202 | uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; | |
203 | ||
204 | /* audio caps */ | |
205 | uint8_t speaker_flags; | |
206 | uint32_t audio_mode_count; | |
207 | struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; | |
208 | uint32_t audio_latency; | |
209 | uint32_t video_latency; | |
210 | ||
50e27654 ZF |
211 | union display_content_support content_support; |
212 | ||
213 | uint8_t qs_bit; | |
214 | uint8_t qy_bit; | |
215 | ||
c04bd16e DZ |
216 | uint32_t max_tmds_clk_mhz; |
217 | ||
4562236b HW |
218 | /*HDMI 2.0 caps*/ |
219 | bool lte_340mcsc_scramble; | |
220 | ||
221 | bool edid_hdmi; | |
506ab334 | 222 | bool hdr_supported; |
243c46c5 JB |
223 | |
224 | struct dc_panel_patch panel_patch; | |
4562236b HW |
225 | }; |
226 | ||
4562236b HW |
227 | struct dc_mode_flags { |
228 | /* note: part of refresh rate flag*/ | |
229 | uint32_t INTERLACE :1; | |
230 | /* native display timing*/ | |
231 | uint32_t NATIVE :1; | |
232 | /* preferred is the recommended mode, one per display */ | |
233 | uint32_t PREFERRED :1; | |
234 | /* true if this mode should use reduced blanking timings | |
235 | *_not_ related to the Reduced Blanking adjustment*/ | |
236 | uint32_t REDUCED_BLANKING :1; | |
237 | /* note: part of refreshrate flag*/ | |
238 | uint32_t VIDEO_OPTIMIZED_RATE :1; | |
239 | /* should be reported to upper layers as mode_flags*/ | |
240 | uint32_t PACKED_PIXEL_FORMAT :1; | |
241 | /*< preferred view*/ | |
242 | uint32_t PREFERRED_VIEW :1; | |
243 | /* this timing should be used only in tiled mode*/ | |
244 | uint32_t TILED_MODE :1; | |
245 | uint32_t DSE_MODE :1; | |
246 | /* Refresh rate divider when Miracast sink is using a | |
247 | different rate than the output display device | |
248 | Must be zero for wired displays and non-zero for | |
249 | Miracast displays*/ | |
250 | uint32_t MIRACAST_REFRESH_DIVIDER; | |
251 | }; | |
252 | ||
253 | ||
254 | enum dc_timing_source { | |
255 | TIMING_SOURCE_UNDEFINED, | |
256 | ||
257 | /* explicitly specifed by user, most important*/ | |
258 | TIMING_SOURCE_USER_FORCED, | |
259 | TIMING_SOURCE_USER_OVERRIDE, | |
260 | TIMING_SOURCE_CUSTOM, | |
261 | TIMING_SOURCE_EXPLICIT, | |
262 | ||
263 | /* explicitly specified by the display device, more important*/ | |
264 | TIMING_SOURCE_EDID_CEA_SVD_3D, | |
265 | TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, | |
266 | TIMING_SOURCE_EDID_CEA_SVD_420, | |
267 | TIMING_SOURCE_EDID_DETAILED, | |
268 | TIMING_SOURCE_EDID_ESTABLISHED, | |
269 | TIMING_SOURCE_EDID_STANDARD, | |
270 | TIMING_SOURCE_EDID_CEA_SVD, | |
271 | TIMING_SOURCE_EDID_CVT_3BYTE, | |
272 | TIMING_SOURCE_EDID_4BYTE, | |
427a60c1 CP |
273 | TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, |
274 | TIMING_SOURCE_EDID_CEA_RID, | |
4562236b HW |
275 | TIMING_SOURCE_VBIOS, |
276 | TIMING_SOURCE_CV, | |
277 | TIMING_SOURCE_TV, | |
278 | TIMING_SOURCE_HDMI_VIC, | |
279 | ||
280 | /* implicitly specified by display device, still safe but less important*/ | |
281 | TIMING_SOURCE_DEFAULT, | |
282 | ||
283 | /* only used for custom base modes */ | |
284 | TIMING_SOURCE_CUSTOM_BASE, | |
285 | ||
286 | /* these timing might not work, least important*/ | |
287 | TIMING_SOURCE_RANGELIMIT, | |
288 | TIMING_SOURCE_OS_FORCED, | |
289 | TIMING_SOURCE_IMPLICIT, | |
290 | ||
291 | /* only used by default mode list*/ | |
292 | TIMING_SOURCE_BASICMODE, | |
293 | ||
294 | TIMING_SOURCE_COUNT | |
295 | }; | |
296 | ||
b6d6103b VP |
297 | |
298 | struct stereo_3d_features { | |
299 | bool supported ; | |
300 | bool allTimings ; | |
301 | bool cloneMode ; | |
302 | bool scaling ; | |
303 | bool singleFrameSWPacked; | |
304 | }; | |
305 | ||
4562236b HW |
306 | enum dc_timing_support_method { |
307 | TIMING_SUPPORT_METHOD_UNDEFINED, | |
308 | TIMING_SUPPORT_METHOD_EXPLICIT, | |
309 | TIMING_SUPPORT_METHOD_IMPLICIT, | |
310 | TIMING_SUPPORT_METHOD_NATIVE | |
311 | }; | |
312 | ||
313 | struct dc_mode_info { | |
314 | uint32_t pixel_width; | |
315 | uint32_t pixel_height; | |
316 | uint32_t field_rate; | |
317 | /* Vertical refresh rate for progressive modes. | |
318 | * Field rate for interlaced modes.*/ | |
319 | ||
320 | enum dc_timing_standard timing_standard; | |
321 | enum dc_timing_source timing_source; | |
322 | struct dc_mode_flags flags; | |
323 | }; | |
324 | ||
325 | enum dc_power_state { | |
326 | DC_POWER_STATE_ON = 1, | |
327 | DC_POWER_STATE_STANDBY, | |
328 | DC_POWER_STATE_SUSPEND, | |
329 | DC_POWER_STATE_OFF | |
330 | }; | |
331 | ||
332 | /* DC PowerStates */ | |
333 | enum dc_video_power_state { | |
334 | DC_VIDEO_POWER_UNSPECIFIED = 0, | |
335 | DC_VIDEO_POWER_ON = 1, | |
336 | DC_VIDEO_POWER_STANDBY, | |
337 | DC_VIDEO_POWER_SUSPEND, | |
338 | DC_VIDEO_POWER_OFF, | |
339 | DC_VIDEO_POWER_HIBERNATE, | |
340 | DC_VIDEO_POWER_SHUTDOWN, | |
341 | DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ | |
342 | DC_VIDEO_POWER_AFTER_RESET, | |
343 | DC_VIDEO_POWER_MAXIMUM | |
344 | }; | |
345 | ||
346 | enum dc_acpi_cm_power_state { | |
347 | DC_ACPI_CM_POWER_STATE_D0 = 1, | |
348 | DC_ACPI_CM_POWER_STATE_D1 = 2, | |
349 | DC_ACPI_CM_POWER_STATE_D2 = 4, | |
350 | DC_ACPI_CM_POWER_STATE_D3 = 8 | |
351 | }; | |
352 | ||
353 | enum dc_connection_type { | |
354 | dc_connection_none, | |
355 | dc_connection_single, | |
356 | dc_connection_mst_branch, | |
36c9137b | 357 | dc_connection_sst_branch |
4562236b HW |
358 | }; |
359 | ||
360 | struct dc_csc_adjustments { | |
361 | struct fixed31_32 contrast; | |
362 | struct fixed31_32 saturation; | |
363 | struct fixed31_32 brightness; | |
364 | struct fixed31_32 hue; | |
365 | }; | |
366 | ||
4562236b HW |
367 | /* Scaling format */ |
368 | enum scaling_transformation { | |
369 | SCALING_TRANSFORMATION_UNINITIALIZED, | |
370 | SCALING_TRANSFORMATION_IDENTITY = 0x0001, | |
371 | SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, | |
372 | SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, | |
373 | SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, | |
374 | SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, | |
375 | SCALING_TRANSFORMATION_INVALID = 0x80000000, | |
376 | ||
377 | /* Flag the first and last */ | |
378 | SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, | |
379 | SCALING_TRANSFORMATION_END = | |
380 | SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE | |
381 | }; | |
382 | ||
50e27654 ZF |
383 | enum display_content_type { |
384 | DISPLAY_CONTENT_TYPE_NO_DATA = 0, | |
385 | DISPLAY_CONTENT_TYPE_GRAPHICS = 1, | |
386 | DISPLAY_CONTENT_TYPE_PHOTO = 2, | |
387 | DISPLAY_CONTENT_TYPE_CINEMA = 4, | |
388 | DISPLAY_CONTENT_TYPE_GAME = 8 | |
389 | }; | |
390 | ||
8993dee0 BL |
391 | enum cm_gamut_adjust_type { |
392 | CM_GAMUT_ADJUST_TYPE_BYPASS = 0, | |
393 | CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ | |
394 | CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ | |
395 | }; | |
396 | ||
397 | struct cm_grph_csc_adjustment { | |
398 | struct fixed31_32 temperature_matrix[12]; | |
399 | enum cm_gamut_adjust_type gamut_adjust_type; | |
400 | enum cm_gamut_coef_format gamut_coef_format; | |
401 | }; | |
20f2ffe5 | 402 | |
345429a6 | 403 | /* writeback */ |
9796b713 TD |
404 | struct dwb_stereo_params { |
405 | bool stereo_enabled; /* false: normal mode, true: 3D stereo */ | |
406 | enum dwb_stereo_type stereo_type; /* indicates stereo format */ | |
407 | bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ | |
408 | enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ | |
409 | }; | |
410 | ||
345429a6 HW |
411 | struct dc_dwb_cnv_params { |
412 | unsigned int src_width; /* input active width */ | |
413 | unsigned int src_height; /* input active height (half-active height in interlaced mode) */ | |
414 | unsigned int crop_width; /* cropped window width at cnv output */ | |
415 | bool crop_en; /* window cropping enable in cnv */ | |
416 | unsigned int crop_height; /* cropped window height at cnv output */ | |
417 | unsigned int crop_x; /* cropped window start x value at cnv output */ | |
418 | unsigned int crop_y; /* cropped window start y value at cnv output */ | |
419 | enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ | |
8993dee0 BL |
420 | enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ |
421 | enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ | |
422 | unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ | |
423 | unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ | |
345429a6 HW |
424 | }; |
425 | ||
426 | struct dc_dwb_params { | |
8993dee0 BL |
427 | unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ |
428 | unsigned int hdr_mult; /* must be in FP1.6.12 */ | |
429 | struct cm_grph_csc_adjustment csc_params; | |
430 | struct dwb_stereo_params stereo_params; | |
345429a6 HW |
431 | struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ |
432 | unsigned int dest_width; /* Destination width */ | |
433 | unsigned int dest_height; /* Destination height */ | |
434 | enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ | |
435 | enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ | |
436 | enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ | |
437 | struct scaling_taps scaler_taps; /* Scaling taps */ | |
438 | enum dwb_subsample_position subsample_position; | |
439 | struct dc_transfer_func *out_transfer_func; | |
440 | }; | |
345429a6 | 441 | |
4562236b HW |
442 | /* audio*/ |
443 | ||
444 | union audio_sample_rates { | |
445 | struct sample_rates { | |
446 | uint8_t RATE_32:1; | |
447 | uint8_t RATE_44_1:1; | |
448 | uint8_t RATE_48:1; | |
449 | uint8_t RATE_88_2:1; | |
450 | uint8_t RATE_96:1; | |
451 | uint8_t RATE_176_4:1; | |
452 | uint8_t RATE_192:1; | |
453 | } rate; | |
454 | ||
455 | uint8_t all; | |
456 | }; | |
457 | ||
458 | struct audio_speaker_flags { | |
5667ff5c DA |
459 | uint32_t FL_FR:1; |
460 | uint32_t LFE:1; | |
461 | uint32_t FC:1; | |
462 | uint32_t RL_RR:1; | |
463 | uint32_t RC:1; | |
464 | uint32_t FLC_FRC:1; | |
465 | uint32_t RLC_RRC:1; | |
466 | uint32_t SUPPORT_AI:1; | |
4562236b HW |
467 | }; |
468 | ||
469 | struct audio_speaker_info { | |
470 | uint32_t ALLSPEAKERS:7; | |
471 | uint32_t SUPPORT_AI:1; | |
472 | }; | |
473 | ||
474 | ||
475 | struct audio_info_flags { | |
476 | ||
477 | union { | |
478 | ||
479 | struct audio_speaker_flags speaker_flags; | |
480 | struct audio_speaker_info info; | |
481 | ||
482 | uint8_t all; | |
483 | }; | |
484 | }; | |
485 | ||
486 | enum audio_format_code { | |
487 | AUDIO_FORMAT_CODE_FIRST = 1, | |
488 | AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, | |
489 | ||
490 | AUDIO_FORMAT_CODE_AC3, | |
491 | /*Layers 1 & 2 */ | |
492 | AUDIO_FORMAT_CODE_MPEG1, | |
493 | /*MPEG1 Layer 3 */ | |
494 | AUDIO_FORMAT_CODE_MP3, | |
495 | /*multichannel */ | |
496 | AUDIO_FORMAT_CODE_MPEG2, | |
497 | AUDIO_FORMAT_CODE_AAC, | |
498 | AUDIO_FORMAT_CODE_DTS, | |
499 | AUDIO_FORMAT_CODE_ATRAC, | |
500 | AUDIO_FORMAT_CODE_1BITAUDIO, | |
501 | AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, | |
502 | AUDIO_FORMAT_CODE_DTS_HD, | |
503 | AUDIO_FORMAT_CODE_MAT_MLP, | |
504 | AUDIO_FORMAT_CODE_DST, | |
505 | AUDIO_FORMAT_CODE_WMAPRO, | |
506 | AUDIO_FORMAT_CODE_LAST, | |
507 | AUDIO_FORMAT_CODE_COUNT = | |
508 | AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST | |
509 | }; | |
510 | ||
511 | struct audio_mode { | |
512 | /* ucData[0] [6:3] */ | |
513 | enum audio_format_code format_code; | |
514 | /* ucData[0] [2:0] */ | |
515 | uint8_t channel_count; | |
516 | /* ucData[1] */ | |
517 | union audio_sample_rates sample_rates; | |
518 | union { | |
519 | /* for LPCM */ | |
520 | uint8_t sample_size; | |
521 | /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ | |
522 | uint8_t max_bit_rate; | |
523 | /* for Audio Formats 9-15 */ | |
524 | uint8_t vendor_specific; | |
525 | }; | |
526 | }; | |
527 | ||
528 | struct audio_info { | |
529 | struct audio_info_flags flags; | |
530 | uint32_t video_latency; | |
531 | uint32_t audio_latency; | |
532 | uint32_t display_index; | |
533 | uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; | |
534 | uint32_t manufacture_id; | |
535 | uint32_t product_id; | |
536 | /* PortID used for ContainerID when defined */ | |
537 | uint32_t port_id[2]; | |
538 | uint32_t mode_count; | |
539 | /* this field must be last in this struct */ | |
540 | struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; | |
541 | }; | |
3ab4cc65 CL |
542 | struct audio_check { |
543 | unsigned int audio_packet_type; | |
544 | unsigned int max_audiosample_rate; | |
545 | unsigned int acat; | |
546 | }; | |
98e6436d AK |
547 | enum dc_infoframe_type { |
548 | DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, | |
549 | DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, | |
550 | DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, | |
551 | DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, | |
97bda032 | 552 | DC_DP_INFOFRAME_TYPE_PPS = 0x10, |
64ed6a2e AK |
553 | }; |
554 | ||
e09b6473 AK |
555 | struct dc_info_packet { |
556 | bool valid; | |
557 | uint8_t hb0; | |
558 | uint8_t hb1; | |
559 | uint8_t hb2; | |
560 | uint8_t hb3; | |
561 | uint8_t sb[32]; | |
562 | }; | |
563 | ||
f82c916c CL |
564 | struct dc_info_packet_128 { |
565 | bool valid; | |
566 | uint8_t hb0; | |
567 | uint8_t hb1; | |
568 | uint8_t hb2; | |
569 | uint8_t hb3; | |
570 | uint8_t sb[128]; | |
571 | }; | |
a6132cb1 | 572 | |
64ed6a2e AK |
573 | #define DC_PLANE_UPDATE_TIMES_MAX 10 |
574 | ||
575 | struct dc_plane_flip_time { | |
576 | unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; | |
577 | unsigned int index; | |
578 | unsigned int prev_update_time_in_us; | |
579 | }; | |
580 | ||
1d496907 KK |
581 | enum dc_psr_state { |
582 | PSR_STATE0 = 0x0, | |
583 | PSR_STATE1, | |
584 | PSR_STATE1a, | |
585 | PSR_STATE2, | |
586 | PSR_STATE2a, | |
a35e5c5b | 587 | PSR_STATE2b, |
1d496907 KK |
588 | PSR_STATE3, |
589 | PSR_STATE3Init, | |
590 | PSR_STATE4, | |
591 | PSR_STATE4a, | |
592 | PSR_STATE4b, | |
593 | PSR_STATE4c, | |
594 | PSR_STATE4d, | |
6cc5c773 DZ |
595 | PSR_STATE4_FULL_FRAME, |
596 | PSR_STATE4a_FULL_FRAME, | |
597 | PSR_STATE4b_FULL_FRAME, | |
598 | PSR_STATE4c_FULL_FRAME, | |
599 | PSR_STATE4_FULL_FRAME_POWERUP, | |
e8c49e9e | 600 | PSR_STATE4_FULL_FRAME_HW_LOCK, |
1d496907 KK |
601 | PSR_STATE5, |
602 | PSR_STATE5a, | |
603 | PSR_STATE5b, | |
04f3c88f | 604 | PSR_STATE5c, |
6cc5c773 DZ |
605 | PSR_STATE_HWLOCK_MGR, |
606 | PSR_STATE_POLLVUPDATE, | |
04f3c88f | 607 | PSR_STATE_INVALID = 0xFF |
1d496907 KK |
608 | }; |
609 | ||
94267b3d ST |
610 | struct psr_config { |
611 | unsigned char psr_version; | |
612 | unsigned int psr_rfb_setup_time; | |
613 | bool psr_exit_link_training_required; | |
94267b3d ST |
614 | bool psr_frame_capture_indication_req; |
615 | unsigned int psr_sdp_transmit_line_num_deadline; | |
5d87a3fd | 616 | bool allow_smu_optimizations; |
175f0971 | 617 | bool allow_multi_disp_optimizations; |
a35806b3 DZ |
618 | /* Panel self refresh 2 selective update granularity required */ |
619 | bool su_granularity_required; | |
620 | /* psr2 selective update y granularity capability */ | |
621 | uint8_t su_y_granularity; | |
32c453f1 | 622 | unsigned int line_time_in_us; |
6651875a | 623 | uint8_t rate_control_caps; |
c84ff24a | 624 | uint16_t dsc_slice_height; |
94267b3d ST |
625 | }; |
626 | ||
9f72f51d AZ |
627 | union dmcu_psr_level { |
628 | struct { | |
629 | unsigned int SKIP_CRC:1; | |
630 | unsigned int SKIP_DP_VID_STREAM_DISABLE:1; | |
631 | unsigned int SKIP_PHY_POWER_DOWN:1; | |
632 | unsigned int SKIP_AUX_ACK_CHECK:1; | |
633 | unsigned int SKIP_CRTC_DISABLE:1; | |
634 | unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; | |
635 | unsigned int SKIP_SMU_NOTIFICATION:1; | |
636 | unsigned int SKIP_AUTO_STATE_ADVANCE:1; | |
637 | unsigned int DISABLE_PSR_ENTRY_ABORT:1; | |
ee356d8f | 638 | unsigned int SKIP_SINGLE_OTG_DISABLE:1; |
c7eac19e DZ |
639 | unsigned int DISABLE_ALPM:1; |
640 | unsigned int ALPM_DEFAULT_PD_MODE:1; | |
641 | unsigned int RESERVED:20; | |
9f72f51d AZ |
642 | } bits; |
643 | unsigned int u32all; | |
644 | }; | |
645 | ||
646 | enum physical_phy_id { | |
647 | PHYLD_0, | |
648 | PHYLD_1, | |
649 | PHYLD_2, | |
650 | PHYLD_3, | |
651 | PHYLD_4, | |
652 | PHYLD_5, | |
653 | PHYLD_6, | |
654 | PHYLD_7, | |
655 | PHYLD_8, | |
656 | PHYLD_9, | |
657 | PHYLD_COUNT, | |
658 | PHYLD_UNKNOWN = (-1L) | |
659 | }; | |
660 | ||
661 | enum phy_type { | |
662 | PHY_TYPE_UNKNOWN = 1, | |
663 | PHY_TYPE_PCIE_PHY = 2, | |
664 | PHY_TYPE_UNIPHY = 3, | |
665 | }; | |
666 | ||
667 | struct psr_context { | |
668 | /* ddc line */ | |
669 | enum channel_id channel; | |
670 | /* Transmitter id */ | |
671 | enum transmitter transmitterId; | |
672 | /* Engine Id is used for Dig Be source select */ | |
673 | enum engine_id engineId; | |
674 | /* Controller Id used for Dig Fe source select */ | |
675 | enum controller_id controllerId; | |
676 | /* Pcie or Uniphy */ | |
677 | enum phy_type phyType; | |
678 | /* Physical PHY Id used by SMU interpretation */ | |
679 | enum physical_phy_id smuPhyId; | |
680 | /* Vertical total pixels from crtc timing. | |
681 | * This is used for static screen detection. | |
682 | * ie. If we want to detect half a frame, | |
683 | * we use this to determine the hyst lines. | |
684 | */ | |
685 | unsigned int crtcTimingVerticalTotal; | |
686 | /* PSR supported from panel capabilities and | |
687 | * current display configuration | |
688 | */ | |
689 | bool psrSupportedDisplayConfig; | |
690 | /* Whether fast link training is supported by the panel */ | |
691 | bool psrExitLinkTrainingRequired; | |
692 | /* If RFB setup time is greater than the total VBLANK time, | |
693 | * it is not possible for the sink to capture the video frame | |
694 | * in the same frame the SDP is sent. In this case, | |
695 | * the frame capture indication bit should be set and an extra | |
696 | * static frame should be transmitted to the sink. | |
697 | */ | |
698 | bool psrFrameCaptureIndicationReq; | |
699 | /* Set the last possible line SDP may be transmitted without violating | |
700 | * the RFB setup time or entering the active video frame. | |
701 | */ | |
702 | unsigned int sdpTransmitLineNumDeadline; | |
703 | /* The VSync rate in Hz used to calculate the | |
704 | * step size for smooth brightness feature | |
705 | */ | |
5b5abe95 | 706 | unsigned int vsync_rate_hz; |
9f72f51d AZ |
707 | unsigned int skipPsrWaitForPllLock; |
708 | unsigned int numberOfControllers; | |
709 | /* Unused, for future use. To indicate that first changed frame from | |
710 | * state3 shouldn't result in psr_inactive, but rather to perform | |
711 | * an automatic single frame rfb_update. | |
712 | */ | |
713 | bool rfb_update_auto_en; | |
714 | /* Number of frame before entering static screen */ | |
715 | unsigned int timehyst_frames; | |
716 | /* Partial frames before entering static screen */ | |
717 | unsigned int hyst_lines; | |
718 | /* # of repeated AUX transaction attempts to make before | |
719 | * indicating failure to the driver | |
720 | */ | |
721 | unsigned int aux_repeats; | |
722 | /* Controls hw blocks to power down during PSR active state */ | |
723 | union dmcu_psr_level psr_level; | |
724 | /* Controls additional delay after remote frame capture before | |
725 | * continuing powerd own | |
726 | */ | |
727 | unsigned int frame_delay; | |
5d87a3fd | 728 | bool allow_smu_optimizations; |
175f0971 | 729 | bool allow_multi_disp_optimizations; |
a35806b3 DZ |
730 | /* Panel self refresh 2 selective update granularity required */ |
731 | bool su_granularity_required; | |
732 | /* psr2 selective update y granularity capability */ | |
733 | uint8_t su_y_granularity; | |
32c453f1 | 734 | unsigned int line_time_in_us; |
6651875a | 735 | uint8_t rate_control_caps; |
c84ff24a | 736 | uint16_t dsc_slice_height; |
9f72f51d AZ |
737 | }; |
738 | ||
4562236b HW |
739 | struct colorspace_transform { |
740 | struct fixed31_32 matrix[12]; | |
741 | bool enable_remap; | |
742 | }; | |
743 | ||
7c7f5b15 AG |
744 | enum i2c_mot_mode { |
745 | I2C_MOT_UNDEF, | |
746 | I2C_MOT_TRUE, | |
747 | I2C_MOT_FALSE | |
748 | }; | |
749 | ||
8ab2180f EB |
750 | struct AsicStateEx { |
751 | unsigned int memoryClock; | |
752 | unsigned int displayClock; | |
753 | unsigned int engineClock; | |
754 | unsigned int maxSupportedDppClock; | |
755 | unsigned int dppClock; | |
756 | unsigned int socClock; | |
757 | unsigned int dcfClockDeepSleep; | |
758 | unsigned int fClock; | |
759 | unsigned int phyClock; | |
760 | }; | |
761 | ||
925f566c CL |
762 | |
763 | enum dc_clock_type { | |
764 | DC_CLOCK_TYPE_DISPCLK = 0, | |
765 | DC_CLOCK_TYPE_DPPCLK = 1, | |
766 | }; | |
767 | ||
768 | struct dc_clock_config { | |
769 | uint32_t max_clock_khz; | |
770 | uint32_t min_clock_khz; | |
771 | uint32_t bw_requirequired_clock_khz; | |
772 | uint32_t current_clock_khz;/*current clock in use*/ | |
773 | }; | |
774 | ||
91a9ead0 MM |
775 | struct hw_asic_id { |
776 | uint32_t chip_id; | |
777 | uint32_t chip_family; | |
778 | uint32_t pci_revision_id; | |
779 | uint32_t hw_internal_rev; | |
780 | uint32_t vram_type; | |
781 | uint32_t vram_width; | |
782 | uint32_t feature_flags; | |
783 | uint32_t fake_paths_num; | |
784 | void *atombios_base_address; | |
785 | }; | |
786 | ||
787 | struct dc_context { | |
788 | struct dc *dc; | |
789 | ||
790 | void *driver_context; /* e.g. amdgpu_device */ | |
791 | struct dc_perf_trace *perf_trace; | |
792 | void *cgs_device; | |
793 | ||
794 | enum dce_environment dce_environment; | |
795 | struct hw_asic_id asic_id; | |
796 | ||
797 | /* todo: below should probably move to dc. to facilitate removal | |
798 | * of AS we will store these here | |
799 | */ | |
800 | enum dce_version dce_version; | |
801 | struct dc_bios *dc_bios; | |
802 | bool created_bios; | |
803 | struct gpio_service *gpio_service; | |
804 | uint32_t dc_sink_id_count; | |
805 | uint32_t dc_stream_id_count; | |
806 | uint32_t dc_edp_id_count; | |
807 | uint64_t fbc_gpu_addr; | |
808 | struct dc_dmub_srv *dmub_srv; | |
91a9ead0 | 809 | struct cp_psp cp_psp; |
e5028e9f | 810 | uint32_t *dcn_reg_offsets; |
2a93292f | 811 | uint32_t *nbio_reg_offsets; |
91a9ead0 MM |
812 | }; |
813 | ||
97bda032 HW |
814 | /* DSC DPCD capabilities */ |
815 | union dsc_slice_caps1 { | |
816 | struct { | |
817 | uint8_t NUM_SLICES_1 : 1; | |
818 | uint8_t NUM_SLICES_2 : 1; | |
819 | uint8_t RESERVED : 1; | |
820 | uint8_t NUM_SLICES_4 : 1; | |
821 | uint8_t NUM_SLICES_6 : 1; | |
822 | uint8_t NUM_SLICES_8 : 1; | |
823 | uint8_t NUM_SLICES_10 : 1; | |
824 | uint8_t NUM_SLICES_12 : 1; | |
825 | } bits; | |
826 | uint8_t raw; | |
827 | }; | |
828 | ||
829 | union dsc_slice_caps2 { | |
830 | struct { | |
831 | uint8_t NUM_SLICES_16 : 1; | |
832 | uint8_t NUM_SLICES_20 : 1; | |
833 | uint8_t NUM_SLICES_24 : 1; | |
834 | uint8_t RESERVED : 5; | |
835 | } bits; | |
836 | uint8_t raw; | |
837 | }; | |
838 | ||
839 | union dsc_color_formats { | |
840 | struct { | |
841 | uint8_t RGB : 1; | |
842 | uint8_t YCBCR_444 : 1; | |
843 | uint8_t YCBCR_SIMPLE_422 : 1; | |
844 | uint8_t YCBCR_NATIVE_422 : 1; | |
845 | uint8_t YCBCR_NATIVE_420 : 1; | |
846 | uint8_t RESERVED : 3; | |
847 | } bits; | |
848 | uint8_t raw; | |
849 | }; | |
850 | ||
851 | union dsc_color_depth { | |
852 | struct { | |
853 | uint8_t RESERVED1 : 1; | |
854 | uint8_t COLOR_DEPTH_8_BPC : 1; | |
855 | uint8_t COLOR_DEPTH_10_BPC : 1; | |
856 | uint8_t COLOR_DEPTH_12_BPC : 1; | |
857 | uint8_t RESERVED2 : 3; | |
858 | } bits; | |
859 | uint8_t raw; | |
860 | }; | |
861 | ||
862 | struct dsc_dec_dpcd_caps { | |
863 | bool is_dsc_supported; | |
864 | uint8_t dsc_version; | |
865 | int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ | |
866 | union dsc_slice_caps1 slice_caps1; | |
867 | union dsc_slice_caps2 slice_caps2; | |
868 | int32_t lb_bit_depth; | |
869 | bool is_block_pred_supported; | |
870 | int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ | |
871 | union dsc_color_formats color_formats; | |
872 | union dsc_color_depth color_depth; | |
873 | int32_t throughput_mode_0_mps; /* In MPs */ | |
874 | int32_t throughput_mode_1_mps; /* In MPs */ | |
875 | int32_t max_slice_width; | |
876 | uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ | |
f446489a NC |
877 | |
878 | /* Extended DSC caps */ | |
879 | uint32_t branch_overall_throughput_0_mps; /* In MPs */ | |
880 | uint32_t branch_overall_throughput_1_mps; /* In MPs */ | |
881 | uint32_t branch_max_line_width; | |
df0a271c | 882 | bool is_dp; |
97bda032 | 883 | }; |
0417df16 | 884 | |
6224220d IK |
885 | struct dc_golden_table { |
886 | uint16_t dc_golden_table_ver; | |
887 | uint32_t aux_dphy_rx_control0_val; | |
888 | uint32_t aux_dphy_tx_control_val; | |
889 | uint32_t aux_dphy_rx_control1_val; | |
890 | uint32_t dc_gpio_aux_ctrl_0_val; | |
891 | uint32_t dc_gpio_aux_ctrl_1_val; | |
892 | uint32_t dc_gpio_aux_ctrl_2_val; | |
893 | uint32_t dc_gpio_aux_ctrl_3_val; | |
894 | uint32_t dc_gpio_aux_ctrl_4_val; | |
895 | uint32_t dc_gpio_aux_ctrl_5_val; | |
896 | }; | |
897 | ||
79037324 BL |
898 | enum dc_gpu_mem_alloc_type { |
899 | DC_MEM_ALLOC_TYPE_GART, | |
900 | DC_MEM_ALLOC_TYPE_FRAME_BUFFER, | |
901 | DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, | |
902 | DC_MEM_ALLOC_TYPE_AGP | |
903 | }; | |
904 | ||
1cfbbdde AK |
905 | enum dc_psr_version { |
906 | DC_PSR_VERSION_1 = 0, | |
cd9a0d02 | 907 | DC_PSR_VERSION_SU_1 = 1, |
1cfbbdde AK |
908 | DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, |
909 | }; | |
910 | ||
f42ef862 JK |
911 | /* Possible values of display_endpoint_id.endpoint */ |
912 | enum display_endpoint_type { | |
913 | DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ | |
698d0a6f | 914 | DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ |
f42ef862 JK |
915 | DISPLAY_ENDPOINT_UNKNOWN = -1 |
916 | }; | |
917 | ||
918 | /* Extends graphics_object_id with an additional member 'ep_type' for | |
919 | * distinguishing between physical endpoints (with entries in BIOS connector table) and | |
920 | * logical endpoints. | |
921 | */ | |
922 | struct display_endpoint_id { | |
923 | struct graphics_object_id link_id; | |
924 | enum display_endpoint_type ep_type; | |
925 | }; | |
926 | ||
c0459bdd | 927 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
c0459bdd AL |
928 | struct otg_phy_mux { |
929 | uint8_t phy_output_num; | |
930 | uint8_t otg_output_num; | |
931 | }; | |
932 | #endif | |
933 | ||
5ca38a18 WL |
934 | enum dc_detect_reason { |
935 | DETECT_REASON_BOOT, | |
936 | DETECT_REASON_RESUMEFROMS3S4, | |
937 | DETECT_REASON_HPD, | |
938 | DETECT_REASON_HPDRX, | |
939 | DETECT_REASON_FALLBACK, | |
940 | DETECT_REASON_RETRAIN, | |
941 | DETECT_REASON_TDR, | |
942 | }; | |
943 | ||
944 | struct dc_link_status { | |
945 | bool link_active; | |
946 | struct dpcd_caps *dpcd_caps; | |
947 | }; | |
948 | ||
5ca38a18 WL |
949 | union hdcp_rx_caps { |
950 | struct { | |
951 | uint8_t version; | |
952 | uint8_t reserved; | |
953 | struct { | |
954 | uint8_t repeater : 1; | |
955 | uint8_t hdcp_capable : 1; | |
956 | uint8_t reserved : 6; | |
957 | } byte0; | |
958 | } fields; | |
959 | uint8_t raw[3]; | |
960 | }; | |
961 | ||
962 | union hdcp_bcaps { | |
963 | struct { | |
964 | uint8_t HDCP_CAPABLE:1; | |
965 | uint8_t REPEATER:1; | |
966 | uint8_t RESERVED:6; | |
967 | } bits; | |
968 | uint8_t raw; | |
969 | }; | |
970 | ||
971 | struct hdcp_caps { | |
972 | union hdcp_rx_caps rx_caps; | |
973 | union hdcp_bcaps bcaps; | |
974 | }; | |
7ae1dbe6 WL |
975 | |
976 | /* DP MST stream allocation (payload bandwidth number) */ | |
977 | struct link_mst_stream_allocation { | |
978 | /* DIG front */ | |
979 | const struct stream_encoder *stream_enc; | |
980 | /* HPO DP Stream Encoder */ | |
981 | const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; | |
982 | /* associate DRM payload table with DC stream encoder */ | |
983 | uint8_t vcp_id; | |
984 | /* number of slots required for the DP stream in transport packet */ | |
985 | uint8_t slot_count; | |
986 | }; | |
987 | ||
988 | #define MAX_CONTROLLER_NUM 6 | |
989 | ||
990 | /* DP MST stream allocation table */ | |
991 | struct link_mst_stream_allocation_table { | |
992 | /* number of DP video streams */ | |
993 | int stream_count; | |
994 | /* array of stream allocations */ | |
995 | struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; | |
996 | }; | |
997 | ||
998 | /* PSR feature flags */ | |
999 | struct psr_settings { | |
1000 | bool psr_feature_enabled; // PSR is supported by sink | |
1001 | bool psr_allow_active; // PSR is currently active | |
1002 | enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD | |
1003 | bool psr_vtotal_control_support; // Vtotal control is supported by sink | |
1004 | unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU | |
1005 | ||
1006 | /* These parameters are calculated in Driver, | |
1007 | * based on display timing and Sink capabilities. | |
1008 | * If VBLANK region is too small and Sink takes a long time | |
1009 | * to set up RFB, it may take an extra frame to enter PSR state. | |
1010 | */ | |
1011 | bool psr_frame_capture_indication_req; | |
1012 | unsigned int psr_sdp_transmit_line_num_deadline; | |
1013 | uint8_t force_ffu_mode; | |
1014 | unsigned int psr_power_opt; | |
1015 | }; | |
1016 | ||
1017 | /* To split out "global" and "per-panel" config settings. | |
1018 | * Add a struct dc_panel_config under dc_link | |
1019 | */ | |
1020 | struct dc_panel_config { | |
1021 | /* extra panel power sequence parameters */ | |
1022 | struct pps { | |
1023 | unsigned int extra_t3_ms; | |
1024 | unsigned int extra_t7_ms; | |
1025 | unsigned int extra_delay_backlight_off; | |
1026 | unsigned int extra_post_t7_ms; | |
1027 | unsigned int extra_pre_t11_ms; | |
1028 | unsigned int extra_t12_ms; | |
1029 | unsigned int extra_post_OUI_ms; | |
1030 | } pps; | |
1031 | /* nit brightness */ | |
1032 | struct nits_brightness { | |
1033 | unsigned int peak; /* nits */ | |
1034 | unsigned int max_avg; /* nits */ | |
1035 | unsigned int min; /* 1/10000 nits */ | |
1036 | unsigned int max_nonboost_brightness_millinits; | |
1037 | unsigned int min_brightness_millinits; | |
1038 | } nits_brightness; | |
1039 | /* PSR */ | |
1040 | struct psr { | |
1041 | bool disable_psr; | |
1042 | bool disallow_psrsu; | |
1043 | bool rc_disable; | |
1044 | bool rc_allow_static_screen; | |
1045 | bool rc_allow_fullscreen_VPB; | |
1046 | } psr; | |
1047 | /* ABM */ | |
1048 | struct varib { | |
1049 | unsigned int varibright_feature_enable; | |
1050 | unsigned int def_varibright_level; | |
1051 | unsigned int abm_config_setting; | |
1052 | } varib; | |
1053 | /* edp DSC */ | |
1054 | struct dsc { | |
1055 | bool disable_dsc_edp; | |
1056 | unsigned int force_dsc_edp_policy; | |
1057 | } dsc; | |
1058 | /* eDP ILR */ | |
1059 | struct ilr { | |
1060 | bool optimize_edp_link_rate; /* eDP ILR */ | |
1061 | } ilr; | |
1062 | }; | |
1063 | ||
1064 | /* | |
1065 | * USB4 DPIA BW ALLOCATION STRUCTS | |
1066 | */ | |
1067 | struct dc_dpia_bw_alloc { | |
1068 | int sink_verified_bw; // The Verified BW that sink can allocated and use that has been verified already | |
1069 | int sink_allocated_bw; // The Actual Allocated BW that sink currently allocated | |
1070 | int sink_max_bw; // The Max BW that sink can require/support | |
1071 | int estimated_bw; // The estimated available BW for this DPIA | |
1072 | int bw_granularity; // BW Granularity | |
1073 | bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM | |
1074 | bool response_ready; // Response ready from the CM side | |
1075 | }; | |
1076 | ||
1077 | #define MAX_SINKS_PER_LINK 4 | |
eeefe7c4 RC |
1078 | |
1079 | enum dc_hpd_enable_select { | |
1080 | HPD_EN_FOR_ALL_EDP = 0, | |
1081 | HPD_EN_FOR_PRIMARY_EDP_ONLY, | |
1082 | HPD_EN_FOR_SECONDARY_EDP_ONLY, | |
1083 | }; | |
1084 | ||
4562236b | 1085 | #endif /* DC_TYPES_H_ */ |