Commit | Line | Data |
---|---|---|
4562236b HW |
1 | /* |
2 | * Copyright 2012-14 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #ifndef DC_INTERFACE_H_ | |
27 | #define DC_INTERFACE_H_ | |
28 | ||
29 | #include "dc_types.h" | |
4562236b HW |
30 | #include "grph_object_defs.h" |
31 | #include "logger_types.h" | |
fe8db3bc BL |
32 | #if defined(CONFIG_DRM_AMD_DC_HDCP) |
33 | #include "hdcp_types.h" | |
34 | #endif | |
4562236b HW |
35 | #include "gpio_types.h" |
36 | #include "link_service_types.h" | |
d0778ebf | 37 | #include "grph_object_ctrl_defs.h" |
4fa086b9 | 38 | #include <inc/hw/opp.h> |
4562236b | 39 | |
fb3466a4 | 40 | #include "inc/hw_sequencer.h" |
be7c97f6 | 41 | #include "inc/compressor.h" |
bbf854dc | 42 | #include "inc/hw/dmcu.h" |
fb3466a4 BL |
43 | #include "dml/display_mode_lib.h" |
44 | ||
4f8e37db MS |
45 | /* forward declaration */ |
46 | struct aux_payload; | |
71af9d46 MS |
47 | struct set_config_cmd_payload; |
48 | struct dmub_notification; | |
4f8e37db | 49 | |
dc597268 | 50 | #define DC_VER "3.2.191" |
fb3466a4 | 51 | |
091a97e5 | 52 | #define MAX_SURFACES 3 |
e5c41970 | 53 | #define MAX_PLANES 6 |
ab2541b6 | 54 | #define MAX_STREAMS 6 |
4562236b | 55 | #define MAX_SINKS_PER_LINK 4 |
40d916a2 | 56 | #define MIN_VIEWPORT_SIZE 12 |
45a1261b | 57 | #define MAX_NUM_EDP 2 |
4562236b HW |
58 | |
59 | /******************************************************************************* | |
60 | * Display Core Interfaces | |
61 | ******************************************************************************/ | |
e923a355 AK |
62 | struct dc_versions { |
63 | const char *dc_ver; | |
64 | struct dmcu_version dmcu_version; | |
65 | }; | |
66 | ||
8d623f86 AK |
67 | enum dp_protocol_version { |
68 | DP_VERSION_1_4, | |
69 | }; | |
70 | ||
e5c41970 NK |
71 | enum dc_plane_type { |
72 | DC_PLANE_TYPE_INVALID, | |
73 | DC_PLANE_TYPE_DCE_RGB, | |
74 | DC_PLANE_TYPE_DCE_UNDERLAY, | |
75 | DC_PLANE_TYPE_DCN_UNIVERSAL, | |
76 | }; | |
77 | ||
f3edefce MS |
78 | // Sizes defined as multiples of 64KB |
79 | enum det_size { | |
80 | DET_SIZE_DEFAULT = 0, | |
81 | DET_SIZE_192KB = 3, | |
82 | DET_SIZE_256KB = 4, | |
83 | DET_SIZE_320KB = 5, | |
84 | DET_SIZE_384KB = 6 | |
85 | }; | |
86 | ||
87 | ||
e5c41970 NK |
88 | struct dc_plane_cap { |
89 | enum dc_plane_type type; | |
90 | uint32_t blends_with_above : 1; | |
91 | uint32_t blends_with_below : 1; | |
92 | uint32_t per_pixel_alpha : 1; | |
ea36ad34 JL |
93 | struct { |
94 | uint32_t argb8888 : 1; | |
95 | uint32_t nv12 : 1; | |
96 | uint32_t fp16 : 1; | |
971ff2b4 CL |
97 | uint32_t p010 : 1; |
98 | uint32_t ayuv : 1; | |
ea36ad34 JL |
99 | } pixel_format_support; |
100 | // max upscaling factor x1000 | |
101 | // upscaling factors are always >= 1 | |
102 | // for example, 1080p -> 8K is 4.0, or 4000 raw value | |
103 | struct { | |
104 | uint32_t argb8888; | |
105 | uint32_t nv12; | |
106 | uint32_t fp16; | |
107 | } max_upscale_factor; | |
108 | // max downscale factor x1000 | |
109 | // downscale factors are always <= 1 | |
110 | // for example, 8K -> 1080p is 0.25, or 250 raw value | |
111 | struct { | |
112 | uint32_t argb8888; | |
113 | uint32_t nv12; | |
114 | uint32_t fp16; | |
115 | } max_downscale_factor; | |
3b26ca2d IK |
116 | // minimal width/height |
117 | uint32_t min_width; | |
118 | uint32_t min_height; | |
e5c41970 NK |
119 | }; |
120 | ||
a8bf7164 KK |
121 | // Color management caps (DPP and MPC) |
122 | struct rom_curve_caps { | |
123 | uint16_t srgb : 1; | |
124 | uint16_t bt2020 : 1; | |
125 | uint16_t gamma2_2 : 1; | |
126 | uint16_t pq : 1; | |
127 | uint16_t hlg : 1; | |
128 | }; | |
129 | ||
130 | struct dpp_color_caps { | |
131 | uint16_t dcn_arch : 1; // all DCE generations treated the same | |
132 | // input lut is different than most LUTs, just plain 256-entry lookup | |
133 | uint16_t input_lut_shared : 1; // shared with DGAM | |
134 | uint16_t icsc : 1; | |
135 | uint16_t dgam_ram : 1; | |
136 | uint16_t post_csc : 1; // before gamut remap | |
137 | uint16_t gamma_corr : 1; | |
138 | ||
139 | // hdr_mult and gamut remap always available in DPP (in that order) | |
140 | // 3d lut implies shaper LUT, | |
141 | // it may be shared with MPC - check MPC:shared_3d_lut flag | |
142 | uint16_t hw_3d_lut : 1; | |
143 | uint16_t ogam_ram : 1; // blnd gam | |
144 | uint16_t ocsc : 1; | |
c6160900 | 145 | uint16_t dgam_rom_for_yuv : 1; |
a8bf7164 KK |
146 | struct rom_curve_caps dgam_rom_caps; |
147 | struct rom_curve_caps ogam_rom_caps; | |
148 | }; | |
149 | ||
150 | struct mpc_color_caps { | |
151 | uint16_t gamut_remap : 1; | |
152 | uint16_t ogam_ram : 1; | |
153 | uint16_t ocsc : 1; | |
154 | uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT | |
155 | uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance | |
156 | ||
157 | struct rom_curve_caps ogam_rom_caps; | |
158 | }; | |
159 | ||
160 | struct dc_color_caps { | |
161 | struct dpp_color_caps dpp; | |
162 | struct mpc_color_caps mpc; | |
163 | }; | |
164 | ||
d3dfceb5 AP |
165 | struct dc_dmub_caps { |
166 | bool psr; | |
167 | }; | |
168 | ||
4562236b | 169 | struct dc_caps { |
ab2541b6 | 170 | uint32_t max_streams; |
4562236b HW |
171 | uint32_t max_links; |
172 | uint32_t max_audios; | |
173 | uint32_t max_slave_planes; | |
ae030570 AK |
174 | uint32_t max_slave_yuv_planes; |
175 | uint32_t max_slave_rgb_planes; | |
3be5262e | 176 | uint32_t max_planes; |
4562236b HW |
177 | uint32_t max_downscale_ratio; |
178 | uint32_t i2c_speed_in_khz; | |
b15cde19 | 179 | uint32_t i2c_speed_in_khz_hdcp; |
4ea20907 | 180 | uint32_t dmdata_alloc_size; |
a37656b9 | 181 | unsigned int max_cursor_size; |
8e7095b9 | 182 | unsigned int max_video_width; |
9248681f | 183 | unsigned int min_horizontal_blanking_period; |
746673c7 | 184 | int linear_pitch_alignment; |
a32a7708 | 185 | bool dcc_const_color; |
4176664b | 186 | bool dynamic_audio; |
553aae12 | 187 | bool is_apu; |
7e98ab10 | 188 | bool dual_link_dvi; |
07049507 | 189 | bool post_blend_color_processing; |
9315e239 | 190 | bool force_dp_tps4_for_cp2520; |
3e27e10e | 191 | bool disable_dp_clk_share; |
1e1dbd6f | 192 | bool psp_setup_panel_mode; |
f6040a43 | 193 | bool extended_aux_timeout_support; |
3a1627b0 | 194 | bool dmcub_support; |
e5fc7825 | 195 | bool zstate_support; |
30bdf50b | 196 | uint32_t num_of_internal_disp; |
8d623f86 | 197 | enum dp_protocol_version max_dp_protocol_version; |
e74c8a46 JA |
198 | unsigned int mall_size_per_mem_channel; |
199 | unsigned int mall_size_total; | |
200 | unsigned int cursor_cache_size; | |
e5c41970 | 201 | struct dc_plane_cap planes[MAX_PLANES]; |
a8bf7164 | 202 | struct dc_color_caps color; |
d3dfceb5 | 203 | struct dc_dmub_caps dmub_caps; |
f01ee019 | 204 | bool dp_hpo; |
c022375a | 205 | bool hdmi_frl_pcon_support; |
2665f63a | 206 | bool edp_dsc_support; |
ba18f235 WC |
207 | bool vbios_lttpr_aware; |
208 | bool vbios_lttpr_enable; | |
de95753c | 209 | uint32_t max_otg_num; |
d3dfceb5 AP |
210 | uint32_t max_cab_allocation_bytes; |
211 | uint32_t cache_line_size; | |
212 | uint32_t cache_num_ways; | |
213 | uint16_t subvp_fw_processing_delay_us; | |
214 | uint16_t subvp_prefetch_end_to_mall_start_us; | |
215 | uint16_t subvp_pstate_allow_width_us; | |
216 | uint16_t subvp_vertical_int_margin_us; | |
2d017189 | 217 | bool seamless_odm; |
4562236b HW |
218 | }; |
219 | ||
6fbefb84 HW |
220 | struct dc_bug_wa { |
221 | bool no_connect_phy_config; | |
222 | bool dedcn20_305_wa; | |
37495fbd | 223 | bool skip_clock_update; |
82054678 | 224 | bool lt_early_cr_pattern; |
6fbefb84 | 225 | }; |
6fbefb84 | 226 | |
4562236b | 227 | struct dc_dcc_surface_param { |
4562236b | 228 | struct dc_size surface_size; |
ebf055f9 | 229 | enum surface_pixel_format format; |
2c8ad2d5 | 230 | enum swizzle_mode_values swizzle_mode; |
4562236b HW |
231 | enum dc_scan_direction scan; |
232 | }; | |
233 | ||
234 | struct dc_dcc_setting { | |
235 | unsigned int max_compressed_blk_size; | |
236 | unsigned int max_uncompressed_blk_size; | |
237 | bool independent_64b_blks; | |
ffd89aa9 | 238 | //These bitfields to be used starting with DCN |
8f712e3e | 239 | struct { |
ffd89aa9 AO |
240 | uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) |
241 | uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN | |
242 | uint32_t dcc_256_128_128 : 1; //available starting with DCN | |
243 | uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) | |
8f712e3e | 244 | } dcc_controls; |
4562236b HW |
245 | }; |
246 | ||
247 | struct dc_surface_dcc_cap { | |
4562236b HW |
248 | union { |
249 | struct { | |
250 | struct dc_dcc_setting rgb; | |
251 | } grph; | |
252 | ||
253 | struct { | |
254 | struct dc_dcc_setting luma; | |
255 | struct dc_dcc_setting chroma; | |
256 | } video; | |
257 | }; | |
ebf055f9 AK |
258 | |
259 | bool capable; | |
260 | bool const_color_support; | |
4562236b HW |
261 | }; |
262 | ||
5b5abe95 AK |
263 | struct dc_static_screen_params { |
264 | struct { | |
265 | bool force_trigger; | |
266 | bool cursor_update; | |
267 | bool surface_update; | |
268 | bool overlay_update; | |
269 | } triggers; | |
270 | unsigned int num_frames; | |
94267b3d ST |
271 | }; |
272 | ||
19ec320e AJ |
273 | |
274 | /* Surface update type is used by dc_update_surfaces_and_stream | |
275 | * The update type is determined at the very beginning of the function based | |
276 | * on parameters passed in and decides how much programming (or updating) is | |
277 | * going to be done during the call. | |
278 | * | |
279 | * UPDATE_TYPE_FAST is used for really fast updates that do not require much | |
280 | * logical calculations or hardware register programming. This update MUST be | |
281 | * ISR safe on windows. Currently fast update will only be used to flip surface | |
282 | * address. | |
283 | * | |
284 | * UPDATE_TYPE_MED is used for slower updates which require significant hw | |
285 | * re-programming however do not affect bandwidth consumption or clock | |
286 | * requirements. At present, this is the level at which front end updates | |
287 | * that do not require us to run bw_calcs happen. These are in/out transfer func | |
288 | * updates, viewport offset changes, recout size changes and pixel depth changes. | |
289 | * This update can be done at ISR, but we want to minimize how often this happens. | |
290 | * | |
291 | * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our | |
292 | * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front | |
293 | * end related. Any time viewport dimensions, recout dimensions, scaling ratios or | |
294 | * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do | |
295 | * a full update. This cannot be done at ISR level and should be a rare event. | |
296 | * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting | |
297 | * underscan we don't expect to see this call at all. | |
298 | */ | |
299 | ||
300 | enum surface_update_type { | |
301 | UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ | |
302 | UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ | |
303 | UPDATE_TYPE_FULL, /* may need to shuffle resources */ | |
304 | }; | |
305 | ||
4562236b HW |
306 | /* Forward declaration*/ |
307 | struct dc; | |
c9614aeb | 308 | struct dc_plane_state; |
608ac7bb | 309 | struct dc_state; |
4562236b | 310 | |
7c0c9672 | 311 | |
4562236b | 312 | struct dc_cap_funcs { |
ff5ef992 AD |
313 | bool (*get_dcc_compression_cap)(const struct dc *dc, |
314 | const struct dc_dcc_surface_param *input, | |
315 | struct dc_surface_dcc_cap *output); | |
4562236b HW |
316 | }; |
317 | ||
4562236b HW |
318 | struct link_training_settings; |
319 | ||
f01ee019 FZ |
320 | union allow_lttpr_non_transparent_mode { |
321 | struct { | |
322 | bool DP1_4A : 1; | |
323 | bool DP2_0 : 1; | |
324 | } bits; | |
325 | unsigned char raw; | |
326 | }; | |
d9eb8fea | 327 | |
4562236b HW |
328 | /* Structure to hold configuration flags set by dm at dc creation. */ |
329 | struct dc_config { | |
330 | bool gpu_vm_support; | |
331 | bool disable_disp_pll_sharing; | |
f332822a | 332 | bool fbc_support; |
3be0a0b8 | 333 | bool disable_fractional_pwm; |
46570f09 | 334 | bool allow_seamless_boot_optimization; |
7aba117a | 335 | bool seamless_boot_edp_requested; |
8dea4960 | 336 | bool edp_not_connected; |
a5148245 | 337 | bool edp_no_power_sequencing; |
22631bb8 | 338 | bool force_enum_edp; |
a6465d1f | 339 | bool forced_clocks; |
f01ee019 | 340 | union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; |
d99f38ae | 341 | bool multi_mon_pp_mclk_switch; |
501b4026 | 342 | bool disable_dmcu; |
65d68369 | 343 | bool enable_4to1MPC; |
7db581d6 | 344 | bool enable_windowed_mpo_odm; |
ab144f0b | 345 | uint32_t allow_edp_hotplug_detection; |
5dba4991 | 346 | bool clamp_min_dcfclk; |
77a2b726 VS |
347 | uint64_t vblank_alignment_dto_params; |
348 | uint8_t vblank_alignment_max_frame_time_diff; | |
132c894e HH |
349 | bool is_asymmetric_memory; |
350 | bool is_single_rank_dimm; | |
a896f870 | 351 | bool use_pipe_ctx_sync_logic; |
382aceb3 | 352 | bool ignore_dpref_ss; |
a8201902 | 353 | bool enable_mipi_converter_optimization; |
4562236b HW |
354 | }; |
355 | ||
bf53769d GL |
356 | enum visual_confirm { |
357 | VISUAL_CONFIRM_DISABLE = 0, | |
358 | VISUAL_CONFIRM_SURFACE = 1, | |
359 | VISUAL_CONFIRM_HDR = 2, | |
123c53a9 | 360 | VISUAL_CONFIRM_MPCTREE = 4, |
bccbf13d | 361 | VISUAL_CONFIRM_PSR = 5, |
793c82ee | 362 | VISUAL_CONFIRM_SWIZZLE = 9, |
bf53769d GL |
363 | }; |
364 | ||
e5dfcd27 RC |
365 | enum dc_psr_power_opts { |
366 | psr_power_opt_invalid = 0x0, | |
367 | psr_power_opt_smu_opt_static_screen = 0x1, | |
368 | psr_power_opt_z10_static_screen = 0x10, | |
5f5d08b7 | 369 | psr_power_opt_ds_disable_allow = 0x100, |
e5dfcd27 RC |
370 | }; |
371 | ||
4a0caac0 MS |
372 | enum dml_hostvm_override_opts { |
373 | DML_HOSTVM_NO_OVERRIDE = 0x0, | |
374 | DML_HOSTVM_OVERRIDE_FALSE = 0x1, | |
375 | DML_HOSTVM_OVERRIDE_TRUE = 0x2, | |
376 | }; | |
377 | ||
a32a7708 TC |
378 | enum dcc_option { |
379 | DCC_ENABLE = 0, | |
380 | DCC_DISABLE = 1, | |
381 | DCC_HALF_REQ_DISALBE = 2, | |
382 | }; | |
383 | ||
db64fbe7 TC |
384 | enum pipe_split_policy { |
385 | MPC_SPLIT_DYNAMIC = 0, | |
386 | MPC_SPLIT_AVOID = 1, | |
387 | MPC_SPLIT_AVOID_MULT_DISP = 2, | |
388 | }; | |
389 | ||
441ad741 EY |
390 | enum wm_report_mode { |
391 | WM_REPORT_DEFAULT = 0, | |
392 | WM_REPORT_OVERRIDE = 1, | |
393 | }; | |
ce10a0f3 CL |
394 | enum dtm_pstate{ |
395 | dtm_level_p0 = 0,/*highest voltage*/ | |
396 | dtm_level_p1, | |
397 | dtm_level_p2, | |
398 | dtm_level_p3, | |
399 | dtm_level_p4,/*when active_display_count = 0*/ | |
400 | }; | |
441ad741 | 401 | |
9ae1b27f | 402 | enum dcn_pwr_state { |
6f29c358 YS |
403 | DCN_PWR_STATE_UNKNOWN = -1, |
404 | DCN_PWR_STATE_MISSION_MODE = 0, | |
405 | DCN_PWR_STATE_LOW_POWER = 3, | |
9ae1b27f JG |
406 | }; |
407 | ||
550ff7ad EY |
408 | enum dcn_zstate_support_state { |
409 | DCN_ZSTATE_SUPPORT_UNKNOWN, | |
410 | DCN_ZSTATE_SUPPORT_ALLOW, | |
b4c55e52 | 411 | DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, |
550ff7ad | 412 | DCN_ZSTATE_SUPPORT_DISALLOW, |
118a3315 | 413 | }; |
765b2683 DL |
414 | /* |
415 | * For any clocks that may differ per pipe | |
416 | * only the max is stored in this structure | |
417 | */ | |
15cf3974 DL |
418 | struct dc_clocks { |
419 | int dispclk_khz; | |
4b0b1d05 | 420 | int actual_dispclk_khz; |
17ac5036 | 421 | int dppclk_khz; |
4b0b1d05 | 422 | int actual_dppclk_khz; |
b4d5ce7a | 423 | int disp_dpp_voltage_level_khz; |
15cf3974 DL |
424 | int dcfclk_khz; |
425 | int socclk_khz; | |
426 | int dcfclk_deep_sleep_khz; | |
427 | int fclk_khz; | |
765b2683 | 428 | int phyclk_khz; |
8ab2180f | 429 | int dramclk_khz; |
33e0a445 | 430 | bool p_state_change_support; |
550ff7ad | 431 | enum dcn_zstate_support_state zstate_support; |
118a3315 | 432 | bool dtbclk_en; |
0ec74408 | 433 | int ref_dtbclk_khz; |
265280b9 | 434 | bool fclk_p_state_change_support; |
9ae1b27f | 435 | enum dcn_pwr_state pwr_state; |
057fc695 JL |
436 | /* |
437 | * Elements below are not compared for the purposes of | |
438 | * optimization required | |
439 | */ | |
440 | bool prev_p_state_change_support; | |
265280b9 | 441 | bool fclk_prev_p_state_change_support; |
d3dfceb5 AP |
442 | int num_ways; |
443 | int prev_num_ways; | |
ce10a0f3 | 444 | enum dtm_pstate dtm_level; |
3a4d180d WC |
445 | int max_supported_dppclk_khz; |
446 | int max_supported_dispclk_khz; | |
447 | int bw_dppclk_khz; /*a copy of dppclk_khz*/ | |
448 | int bw_dispclk_khz; | |
15cf3974 DL |
449 | }; |
450 | ||
f55be0be JA |
451 | struct dc_bw_validation_profile { |
452 | bool enable; | |
453 | ||
454 | unsigned long long total_ticks; | |
455 | unsigned long long voltage_level_ticks; | |
456 | unsigned long long watermark_ticks; | |
457 | unsigned long long rq_dlg_ticks; | |
458 | ||
459 | unsigned long long total_count; | |
460 | unsigned long long skip_fast_count; | |
461 | unsigned long long skip_pass_count; | |
462 | unsigned long long skip_fail_count; | |
463 | }; | |
464 | ||
465 | #define BW_VAL_TRACE_SETUP() \ | |
466 | unsigned long long end_tick = 0; \ | |
467 | unsigned long long voltage_level_tick = 0; \ | |
468 | unsigned long long watermark_tick = 0; \ | |
469 | unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ | |
470 | dm_get_timestamp(dc->ctx) : 0 | |
471 | ||
472 | #define BW_VAL_TRACE_COUNT() \ | |
473 | if (dc->debug.bw_val_profile.enable) \ | |
474 | dc->debug.bw_val_profile.total_count++ | |
475 | ||
476 | #define BW_VAL_TRACE_SKIP(status) \ | |
477 | if (dc->debug.bw_val_profile.enable) { \ | |
478 | if (!voltage_level_tick) \ | |
479 | voltage_level_tick = dm_get_timestamp(dc->ctx); \ | |
480 | dc->debug.bw_val_profile.skip_ ## status ## _count++; \ | |
481 | } | |
482 | ||
483 | #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ | |
484 | if (dc->debug.bw_val_profile.enable) \ | |
485 | voltage_level_tick = dm_get_timestamp(dc->ctx) | |
486 | ||
487 | #define BW_VAL_TRACE_END_WATERMARKS() \ | |
488 | if (dc->debug.bw_val_profile.enable) \ | |
489 | watermark_tick = dm_get_timestamp(dc->ctx) | |
490 | ||
491 | #define BW_VAL_TRACE_FINISH() \ | |
492 | if (dc->debug.bw_val_profile.enable) { \ | |
493 | end_tick = dm_get_timestamp(dc->ctx); \ | |
494 | dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ | |
495 | dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ | |
496 | if (watermark_tick) { \ | |
497 | dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ | |
498 | dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ | |
499 | } \ | |
500 | } | |
15cf3974 | 501 | |
cae78e03 JL |
502 | union mem_low_power_enable_options { |
503 | struct { | |
64b1d0e8 | 504 | bool vga: 1; |
af435e3f | 505 | bool i2c: 1; |
96879ad3 | 506 | bool dmcu: 1; |
d0274aba | 507 | bool dscl: 1; |
96879ad3 | 508 | bool cm: 1; |
cae78e03 JL |
509 | bool mpc: 1; |
510 | bool optc: 1; | |
18b4f1a0 MS |
511 | bool vpg: 1; |
512 | bool afmt: 1; | |
cae78e03 JL |
513 | } bits; |
514 | uint32_t u32All; | |
515 | }; | |
516 | ||
8017ecb1 JW |
517 | union root_clock_optimization_options { |
518 | struct { | |
519 | bool dpp: 1; | |
520 | bool dsc: 1; | |
521 | bool hdmistream: 1; | |
522 | bool hdmichar: 1; | |
523 | bool dpstream: 1; | |
524 | bool symclk32_se: 1; | |
525 | bool symclk32_le: 1; | |
526 | bool symclk_fe: 1; | |
527 | bool physymclk: 1; | |
528 | bool dpiasymclk: 1; | |
529 | uint32_t reserved: 22; | |
530 | } bits; | |
531 | uint32_t u32All; | |
532 | }; | |
533 | ||
b0ce6272 MS |
534 | union dpia_debug_options { |
535 | struct { | |
31d64b82 JK |
536 | uint32_t disable_dpia:1; /* bit 0 */ |
537 | uint32_t force_non_lttpr:1; /* bit 1 */ | |
538 | uint32_t extend_aux_rd_interval:1; /* bit 2 */ | |
539 | uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ | |
540 | uint32_t hpd_delay_in_ms:12; /* bits 4-15 */ | |
541 | uint32_t disable_force_tbt3_work_around:1; /* bit 16 */ | |
542 | uint32_t reserved:15; | |
b0ce6272 MS |
543 | } bits; |
544 | uint32_t raw; | |
545 | }; | |
546 | ||
bb90786f JK |
547 | /* AUX wake work around options |
548 | * 0: enable/disable work around | |
549 | * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS | |
550 | * 15-2: reserved | |
551 | * 31-16: timeout in ms | |
552 | */ | |
553 | union aux_wake_wa_options { | |
554 | struct { | |
555 | uint32_t enable_wa : 1; | |
556 | uint32_t use_default_timeout : 1; | |
557 | uint32_t rsvd: 14; | |
558 | uint32_t timeout_ms : 16; | |
559 | } bits; | |
560 | uint32_t raw; | |
561 | }; | |
562 | ||
91a9ead0 MM |
563 | struct dc_debug_data { |
564 | uint32_t ltFailCount; | |
565 | uint32_t i2cErrorCount; | |
566 | uint32_t auxErrorCount; | |
567 | }; | |
568 | ||
569 | struct dc_phy_addr_space_config { | |
570 | struct { | |
571 | uint64_t start_addr; | |
572 | uint64_t end_addr; | |
573 | uint64_t fb_top; | |
574 | uint64_t fb_offset; | |
575 | uint64_t fb_base; | |
576 | uint64_t agp_top; | |
577 | uint64_t agp_bot; | |
578 | uint64_t agp_base; | |
579 | } system_aperture; | |
580 | ||
581 | struct { | |
582 | uint64_t page_table_start_addr; | |
583 | uint64_t page_table_end_addr; | |
584 | uint64_t page_table_base_addr; | |
585 | bool base_addr_is_mc_addr; | |
586 | } gart_config; | |
587 | ||
588 | bool valid; | |
589 | bool is_hvm_enabled; | |
590 | uint64_t page_table_default_page_addr; | |
591 | }; | |
592 | ||
593 | struct dc_virtual_addr_space_config { | |
594 | uint64_t page_table_base_addr; | |
595 | uint64_t page_table_start_addr; | |
596 | uint64_t page_table_end_addr; | |
597 | uint32_t page_table_block_size_in_bytes; | |
598 | uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid | |
599 | }; | |
600 | ||
601 | struct dc_bounding_box_overrides { | |
602 | int sr_exit_time_ns; | |
603 | int sr_enter_plus_exit_time_ns; | |
604 | int urgent_latency_ns; | |
605 | int percent_of_ideal_drambw; | |
606 | int dram_clock_change_latency_ns; | |
607 | int dummy_clock_change_latency_ns; | |
608 | /* This forces a hard min on the DCFCLK we use | |
609 | * for DML. Unlike the debug option for forcing | |
610 | * DCFCLK, this override affects watermark calculations | |
611 | */ | |
612 | int min_dcfclk_mhz; | |
613 | }; | |
614 | ||
615 | struct dc_state; | |
616 | struct resource_pool; | |
617 | struct dce_hwseq; | |
618 | ||
cfd84fd3 | 619 | struct dc_debug_options { |
91a9ead0 MM |
620 | bool native422_support; |
621 | bool disable_dsc; | |
bf53769d | 622 | enum visual_confirm visual_confirm; |
21f45a23 | 623 | int visual_confirm_rect_height; |
624 | ||
2b13d7d3 | 625 | bool sanity_checks; |
4562236b | 626 | bool max_disp_clk; |
4562236b | 627 | bool surface_trace; |
9474980a | 628 | bool timing_trace; |
c9742685 | 629 | bool clock_trace; |
4562236b | 630 | bool validation_trace; |
1249acef | 631 | bool bandwidth_calcs_trace; |
3f460907 | 632 | int max_downscale_src_width; |
966869d0 TC |
633 | |
634 | /* stutter efficiency related */ | |
4562236b | 635 | bool disable_stutter; |
966869d0 | 636 | bool use_max_lb; |
a32a7708 | 637 | enum dcc_option disable_dcc; |
966869d0 TC |
638 | enum pipe_split_policy pipe_split_policy; |
639 | bool force_single_disp_pipe_split; | |
6512387a | 640 | bool voltage_align_fclk; |
ad0d8ebc | 641 | bool disable_min_fclk; |
966869d0 | 642 | |
4562236b | 643 | bool disable_dfs_bypass; |
ff5ef992 AD |
644 | bool disable_dpp_power_gate; |
645 | bool disable_hubp_power_gate; | |
97bda032 | 646 | bool disable_dsc_power_gate; |
b5cf0647 | 647 | int dsc_min_slice_height_override; |
2af0f378 | 648 | int dsc_bpp_increment_div; |
ff5ef992 | 649 | bool disable_pplib_wm_range; |
441ad741 | 650 | enum wm_report_mode pplib_wm_report_mode; |
4f4ee686 | 651 | unsigned int min_disp_clk_khz; |
e9bcc1e0 | 652 | unsigned int min_dpp_clk_khz; |
ba9012fc | 653 | unsigned int min_dram_clk_khz; |
139cb65c DL |
654 | int sr_exit_time_dpm0_ns; |
655 | int sr_enter_plus_exit_time_dpm0_ns; | |
ff5ef992 AD |
656 | int sr_exit_time_ns; |
657 | int sr_enter_plus_exit_time_ns; | |
658 | int urgent_latency_ns; | |
1a7d296d | 659 | uint32_t underflow_assert_delay_us; |
ff5ef992 AD |
660 | int percent_of_ideal_drambw; |
661 | int dram_clock_change_latency_ns; | |
f3efec54 | 662 | bool optimized_watermark; |
e73b59b7 | 663 | int always_scale; |
2c8ad2d5 | 664 | bool disable_pplib_clock_request; |
4562236b | 665 | bool disable_clock_gate; |
cc493508 | 666 | bool disable_mem_low_power; |
118a3315 | 667 | bool pstate_enabled; |
aa66df58 | 668 | bool disable_dmcu; |
29eba8e8 | 669 | bool disable_psr; |
70814f6f | 670 | bool force_abm_enable; |
73fb63e7 | 671 | bool disable_stereo_support; |
f6cb588a | 672 | bool vsr_support; |
215a6f05 | 673 | bool performance_trace; |
7c357e61 | 674 | bool az_endpoint_mute_only; |
a771c1f2 | 675 | bool always_use_regamma; |
3ba43a59 | 676 | bool recovery_enabled; |
91f191c7 | 677 | bool avoid_vbios_exec_table; |
e0d85b20 | 678 | bool scl_reset_length10; |
8fc0a0d4 | 679 | bool hdmi20_disable; |
aafded88 | 680 | bool skip_detection_link_training; |
f1e1f272 | 681 | uint32_t edid_read_retry_times; |
291ac8fb | 682 | bool remove_disconnect_edp; |
49782c63 | 683 | unsigned int force_odm_combine; //bit vector based on otg inst |
663d2dae | 684 | unsigned int seamless_boot_odm_combine; |
5dba4991 | 685 | unsigned int force_odm_combine_4to1; //bit vector based on otg inst |
2083640f | 686 | bool disable_z9_mpc; |
51ba137e | 687 | unsigned int force_fclk_khz; |
091018a5 | 688 | bool enable_tri_buf; |
3a1627b0 NK |
689 | bool dmub_offload_enabled; |
690 | bool dmcub_emulation; | |
4d55b0dd | 691 | bool disable_idle_power_optimizations; |
e74c8a46 | 692 | unsigned int mall_size_override; |
ea7154d8 BL |
693 | unsigned int mall_additional_timer_percent; |
694 | bool mall_error_as_fatal; | |
3a1627b0 | 695 | bool dmub_command_table; /* for testing only */ |
f55be0be | 696 | struct dc_bw_validation_profile bw_val_profile; |
97bda032 | 697 | bool disable_fec; |
aa919167 | 698 | bool disable_48mhz_pwrdwn; |
2131f655 JL |
699 | /* This forces a hard min on the DCFCLK requested to SMU/PP |
700 | * watermarks are not affected. | |
701 | */ | |
702 | unsigned int force_min_dcfclk_mhz; | |
5dba4991 | 703 | int dwb_fi_phase; |
70f1476a | 704 | bool disable_timing_sync; |
290129c2 | 705 | bool cm_in_bypass; |
39bca359 | 706 | int force_clock_mode;/*every mode change.*/ |
1cad8ff7 | 707 | |
5622b2d6 | 708 | bool disable_dram_clock_change_vactive_support; |
b9fe5151 | 709 | bool validate_dml_output; |
8c019253 | 710 | bool enable_dmcub_surface_flip; |
ee765924 | 711 | bool usbc_combo_phy_reset_wa; |
2665f63a ML |
712 | bool disable_dsc_edp; |
713 | unsigned int force_dsc_edp_policy; | |
f00889dc | 714 | bool enable_dram_clock_change_one_display_vactive; |
f01ee019 FZ |
715 | /* TODO - remove once tested */ |
716 | bool legacy_dp2_lt; | |
05692bb0 | 717 | bool set_mst_en_for_sst; |
3d38a583 | 718 | bool disable_uhbr; |
800de20b | 719 | bool force_dp2_lt_fallback_method; |
4a3ad932 | 720 | bool ignore_cable_id; |
cae78e03 | 721 | union mem_low_power_enable_options enable_mem_low_power; |
8017ecb1 | 722 | union root_clock_optimization_options root_clock_optimization; |
0a068b68 | 723 | bool hpo_optimization; |
77a2b726 | 724 | bool force_vblank_alignment; |
4f8e37db MS |
725 | |
726 | /* Enable dmub aux for legacy ddc */ | |
727 | bool enable_dmub_aux_for_legacy_ddc; | |
66611a72 | 728 | bool optimize_edp_link_rate; /* eDP ILR */ |
8cf9575d MH |
729 | /* FEC/PSR1 sequence enable delay in 100us */ |
730 | uint8_t fec_enable_delay_in100us; | |
3550d622 | 731 | bool enable_driver_sequence_debug; |
f3edefce MS |
732 | enum det_size crb_alloc_policy; |
733 | int crb_alloc_policy_min_disp_count; | |
2083640f | 734 | bool disable_z10; |
b5d9a483 | 735 | bool enable_z9_disable_interface; |
2083640f | 736 | bool enable_sw_cntl_psr; |
b0ce6272 | 737 | union dpia_debug_options dpia_debug; |
0bbd1c7d GS |
738 | bool disable_fixed_vs_aux_timeout_wa; |
739 | uint32_t fixed_vs_aux_delay_config_wa; | |
d3dfceb5 AP |
740 | bool force_disable_subvp; |
741 | bool force_subvp_mclk_switch; | |
742 | bool force_usr_allow; | |
405bb9ee AL |
743 | /* uses value at boot and disables switch */ |
744 | bool disable_dtb_ref_clk_switch; | |
e5fc7825 | 745 | bool extended_blank_optimization; |
bb90786f | 746 | union aux_wake_wa_options aux_wake_wa; |
b5175966 | 747 | uint8_t psr_power_use_phy_fsm; |
4a0caac0 | 748 | enum dml_hostvm_override_opts dml_hostvm_override; |
d445dd7b | 749 | bool use_legacy_soc_bb_mechanism; |
a141d208 | 750 | bool exit_idle_opt_for_cursor_updates; |
cfd84fd3 | 751 | }; |
3ba43a59 | 752 | |
48321c3d | 753 | struct gpu_info_soc_bounding_box_v1_0; |
4562236b | 754 | struct dc { |
91a9ead0 | 755 | struct dc_debug_options debug; |
e923a355 | 756 | struct dc_versions versions; |
4562236b HW |
757 | struct dc_caps caps; |
758 | struct dc_cap_funcs cap_funcs; | |
4562236b | 759 | struct dc_config config; |
6649f19a | 760 | struct dc_bounding_box_overrides bb_overrides; |
6fbefb84 | 761 | struct dc_bug_wa work_arounds; |
fb3466a4 | 762 | struct dc_context *ctx; |
bda9afda | 763 | struct dc_phy_addr_space_config vm_pa_config; |
fb3466a4 BL |
764 | |
765 | uint8_t link_count; | |
766 | struct dc_link *links[MAX_PIPES * 2]; | |
767 | ||
608ac7bb | 768 | struct dc_state *current_state; |
fb3466a4 BL |
769 | struct resource_pool *res_pool; |
770 | ||
dc88b4a6 EY |
771 | struct clk_mgr *clk_mgr; |
772 | ||
fb3466a4 BL |
773 | /* Display Engine Clock levels */ |
774 | struct dm_pp_clock_levels sclk_lvls; | |
775 | ||
776 | /* Inputs into BW and WM calculations. */ | |
777 | struct bw_calcs_dceip *bw_dceip; | |
778 | struct bw_calcs_vbios *bw_vbios; | |
fb3466a4 BL |
779 | struct dcn_soc_bounding_box *dcn_soc; |
780 | struct dcn_ip_params *dcn_ip; | |
781 | struct display_mode_lib dml; | |
fb3466a4 BL |
782 | |
783 | /* HW functions */ | |
784 | struct hw_sequencer_funcs hwss; | |
785 | struct dce_hwseq *hwseq; | |
786 | ||
46570f09 | 787 | /* Require to optimize clocks and bandwidth for added/removed planes */ |
0aa63a33 | 788 | bool optimized_required; |
89e94bc5 | 789 | bool wm_optimized_required; |
4d55b0dd | 790 | bool idle_optimizations_allowed; |
ffd89aa9 | 791 | bool enable_c20_dtm_b0; |
40104725 | 792 | |
46570f09 | 793 | /* Require to maintain clocks and bandwidth for UEFI enabled HW */ |
46570f09 | 794 | |
fb3466a4 | 795 | /* FBC compressor */ |
fb3466a4 | 796 | struct compressor *fbc_compressor; |
cfd84fd3 JL |
797 | |
798 | struct dc_debug_data debug_data; | |
0136684f | 799 | struct dpcd_vendor_signature vendor_signature; |
be61df57 JL |
800 | |
801 | const char *build_id; | |
6fbefb84 | 802 | struct vm_helper *vm_helper; |
4562236b HW |
803 | }; |
804 | ||
2c8ad2d5 AD |
805 | enum frame_buffer_mode { |
806 | FRAME_BUFFER_MODE_LOCAL_ONLY = 0, | |
807 | FRAME_BUFFER_MODE_ZFB_ONLY, | |
808 | FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, | |
809 | } ; | |
810 | ||
811 | struct dchub_init_data { | |
2c8ad2d5 AD |
812 | int64_t zfb_phys_addr_base; |
813 | int64_t zfb_mc_base_addr; | |
814 | uint64_t zfb_size_in_byte; | |
815 | enum frame_buffer_mode fb_mode; | |
ebf055f9 AK |
816 | bool dchub_initialzied; |
817 | bool dchub_info_valid; | |
2c8ad2d5 | 818 | }; |
2c8ad2d5 | 819 | |
4562236b HW |
820 | struct dc_init_data { |
821 | struct hw_asic_id asic_id; | |
822 | void *driver; /* ctx */ | |
823 | struct cgs_device *cgs_device; | |
6649f19a | 824 | struct dc_bounding_box_overrides bb_overrides; |
4562236b HW |
825 | |
826 | int num_virtual_links; | |
827 | /* | |
828 | * If 'vbios_override' not NULL, it will be called instead | |
829 | * of the real VBIOS. Intended use is Diagnostics on FPGA. | |
830 | */ | |
831 | struct dc_bios *vbios_override; | |
832 | enum dce_environment dce_environment; | |
833 | ||
3a1627b0 NK |
834 | struct dmub_offload_funcs *dmub_if; |
835 | struct dc_reg_helper_state *dmub_offload; | |
2200eb9e | 836 | |
4562236b | 837 | struct dc_config flags; |
04ad71bd DG |
838 | uint64_t log_mask; |
839 | ||
0136684f | 840 | struct dpcd_vendor_signature vendor_signature; |
4d55b0dd | 841 | bool force_smu_not_present; |
4562236b HW |
842 | }; |
843 | ||
d5cf79ee | 844 | struct dc_callback_init { |
d462fcf5 BL |
845 | #ifdef CONFIG_DRM_AMD_DC_HDCP |
846 | struct cp_psp cp_psp; | |
847 | #else | |
d5cf79ee | 848 | uint8_t reserved; |
d462fcf5 | 849 | #endif |
d5cf79ee | 850 | }; |
4562236b | 851 | |
d5cf79ee | 852 | struct dc *dc_create(const struct dc_init_data *init_params); |
98bf2f52 JP |
853 | void dc_hardware_init(struct dc *dc); |
854 | ||
bda9afda | 855 | int dc_get_vmid_use_vector(struct dc *dc); |
bda9afda DL |
856 | void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); |
857 | /* Returns the number of vmids supported */ | |
858 | int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); | |
d5cf79ee WL |
859 | void dc_init_callbacks(struct dc *dc, |
860 | const struct dc_callback_init *init_params); | |
d462fcf5 | 861 | void dc_deinit_callbacks(struct dc *dc); |
4562236b HW |
862 | void dc_destroy(struct dc **dc); |
863 | ||
4562236b HW |
864 | /******************************************************************************* |
865 | * Surface Interfaces | |
866 | ******************************************************************************/ | |
867 | ||
868 | enum { | |
fb735a9f | 869 | TRANSFER_FUNC_POINTS = 1025 |
4562236b HW |
870 | }; |
871 | ||
1646a6fe | 872 | struct dc_hdr_static_metadata { |
1646a6fe AW |
873 | /* display chromaticities and white point in units of 0.00001 */ |
874 | unsigned int chromaticity_green_x; | |
875 | unsigned int chromaticity_green_y; | |
876 | unsigned int chromaticity_blue_x; | |
877 | unsigned int chromaticity_blue_y; | |
878 | unsigned int chromaticity_red_x; | |
879 | unsigned int chromaticity_red_y; | |
880 | unsigned int chromaticity_white_point_x; | |
881 | unsigned int chromaticity_white_point_y; | |
882 | ||
883 | uint32_t min_luminance; | |
884 | uint32_t max_luminance; | |
885 | uint32_t maximum_content_light_level; | |
886 | uint32_t maximum_frame_average_light_level; | |
887 | }; | |
888 | ||
fb735a9f AK |
889 | enum dc_transfer_func_type { |
890 | TF_TYPE_PREDEFINED, | |
891 | TF_TYPE_DISTRIBUTED_POINTS, | |
b6295960 | 892 | TF_TYPE_BYPASS, |
74167ad6 | 893 | TF_TYPE_HWPWL |
fb735a9f AK |
894 | }; |
895 | ||
896 | struct dc_transfer_func_distributed_points { | |
fcd2f4bf AZ |
897 | struct fixed31_32 red[TRANSFER_FUNC_POINTS]; |
898 | struct fixed31_32 green[TRANSFER_FUNC_POINTS]; | |
899 | struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; | |
900 | ||
fb735a9f | 901 | uint16_t end_exponent; |
fcd2f4bf AZ |
902 | uint16_t x_point_at_y1_red; |
903 | uint16_t x_point_at_y1_green; | |
904 | uint16_t x_point_at_y1_blue; | |
fb735a9f AK |
905 | }; |
906 | ||
907 | enum dc_transfer_func_predefined { | |
908 | TRANSFER_FUNCTION_SRGB, | |
909 | TRANSFER_FUNCTION_BT709, | |
90e508ba | 910 | TRANSFER_FUNCTION_PQ, |
fb735a9f | 911 | TRANSFER_FUNCTION_LINEAR, |
79086a55 | 912 | TRANSFER_FUNCTION_UNITY, |
43610a9b | 913 | TRANSFER_FUNCTION_HLG, |
bf53769d | 914 | TRANSFER_FUNCTION_HLG12, |
1ee299b9 VP |
915 | TRANSFER_FUNCTION_GAMMA22, |
916 | TRANSFER_FUNCTION_GAMMA24, | |
917 | TRANSFER_FUNCTION_GAMMA26 | |
fb735a9f AK |
918 | }; |
919 | ||
1ee299b9 | 920 | |
fb735a9f | 921 | struct dc_transfer_func { |
93052132 | 922 | struct kref refcount; |
fb735a9f AK |
923 | enum dc_transfer_func_type type; |
924 | enum dc_transfer_func_predefined tf; | |
6d9ac917 KK |
925 | /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ |
926 | uint32_t sdr_ref_white_level; | |
74167ad6 VP |
927 | union { |
928 | struct pwl_params pwl; | |
929 | struct dc_transfer_func_distributed_points tf_pts; | |
930 | }; | |
fb735a9f AK |
931 | }; |
932 | ||
6fbefb84 | 933 | |
a2080098 VP |
934 | union dc_3dlut_state { |
935 | struct { | |
936 | uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ | |
937 | uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ | |
938 | uint32_t rmu_mux_num:3; /*index of mux to use*/ | |
939 | uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ | |
940 | uint32_t mpc_rmu1_mux:4; | |
941 | uint32_t mpc_rmu2_mux:4; | |
942 | uint32_t reserved:15; | |
943 | } bits; | |
944 | uint32_t raw; | |
945 | }; | |
946 | ||
6fbefb84 HW |
947 | |
948 | struct dc_3dlut { | |
949 | struct kref refcount; | |
950 | struct tetrahedral_params lut_3d; | |
46250a0c | 951 | struct fixed31_32 hdr_multiplier; |
a2080098 | 952 | union dc_3dlut_state state; |
6fbefb84 | 953 | }; |
e12cfcb1 HW |
954 | /* |
955 | * This structure is filled in by dc_surface_get_status and contains | |
956 | * the last requested address and the currently active address so the called | |
957 | * can determine if there are any outstanding flips | |
958 | */ | |
3be5262e | 959 | struct dc_plane_status { |
e12cfcb1 HW |
960 | struct dc_plane_address requested_address; |
961 | struct dc_plane_address current_address; | |
962 | bool is_flip_pending; | |
963 | bool is_right_eye; | |
964 | }; | |
965 | ||
19ec320e AJ |
966 | union surface_update_flags { |
967 | ||
968 | struct { | |
24c18794 | 969 | uint32_t addr_update:1; |
19ec320e | 970 | /* Medium updates */ |
e9dd9223 | 971 | uint32_t dcc_change:1; |
19ec320e | 972 | uint32_t color_space_change:1; |
19ec320e AJ |
973 | uint32_t horizontal_mirror_change:1; |
974 | uint32_t per_pixel_alpha_change:1; | |
94a4ffd1 | 975 | uint32_t global_alpha_change:1; |
46250a0c | 976 | uint32_t hdr_mult:1; |
19ec320e AJ |
977 | uint32_t rotation_change:1; |
978 | uint32_t swizzle_change:1; | |
979 | uint32_t scaling_change:1; | |
980 | uint32_t position_change:1; | |
405c50a0 | 981 | uint32_t in_transfer_func_change:1; |
19ec320e | 982 | uint32_t input_csc_change:1; |
35ad2254 | 983 | uint32_t coeff_reduction_change:1; |
6d9ac917 | 984 | uint32_t output_tf_change:1; |
3aa0cadd | 985 | uint32_t pixel_format_change:1; |
ebd084cd | 986 | uint32_t plane_size_change:1; |
5c41c023 | 987 | uint32_t gamut_remap_change:1; |
19ec320e AJ |
988 | |
989 | /* Full updates */ | |
990 | uint32_t new_plane:1; | |
991 | uint32_t bpp_change:1; | |
405c50a0 | 992 | uint32_t gamma_change:1; |
19ec320e AJ |
993 | uint32_t bandwidth_change:1; |
994 | uint32_t clock_change:1; | |
995 | uint32_t stereo_format_change:1; | |
fbde44bc | 996 | uint32_t lut_3d:1; |
27b89313 | 997 | uint32_t full_update:1; |
19ec320e AJ |
998 | } bits; |
999 | ||
1000 | uint32_t raw; | |
1001 | }; | |
1002 | ||
c9614aeb | 1003 | struct dc_plane_state { |
4562236b | 1004 | struct dc_plane_address address; |
64ed6a2e | 1005 | struct dc_plane_flip_time time; |
6fbefb84 | 1006 | bool triplebuffer_flips; |
4562236b HW |
1007 | struct scaling_taps scaling_quality; |
1008 | struct rect src_rect; | |
1009 | struct rect dst_rect; | |
1010 | struct rect clip_rect; | |
1011 | ||
12e2b2d4 | 1012 | struct plane_size plane_size; |
4562236b | 1013 | union dc_tiling_info tiling_info; |
ebf055f9 | 1014 | |
4562236b | 1015 | struct dc_plane_dcc_param dcc; |
ebf055f9 | 1016 | |
7a6c4af6 | 1017 | struct dc_gamma *gamma_correction; |
7b0c470f | 1018 | struct dc_transfer_func *in_transfer_func; |
de4a2967 | 1019 | struct dc_bias_and_scale *bias_and_scale; |
586f27a3 | 1020 | struct dc_csc_transform input_csc_color_matrix; |
de4a2967 | 1021 | struct fixed31_32 coeff_reduction_factor; |
46250a0c | 1022 | struct fixed31_32 hdr_mult; |
5c41c023 | 1023 | struct colorspace_transform gamut_remap_matrix; |
4562236b | 1024 | |
56ef6ed9 AK |
1025 | // TODO: No longer used, remove |
1026 | struct dc_hdr_static_metadata hdr_static_ctx; | |
2938bbb6 | 1027 | |
ebf055f9 | 1028 | enum dc_color_space color_space; |
56ef6ed9 | 1029 | |
6fbefb84 HW |
1030 | struct dc_3dlut *lut3d_func; |
1031 | struct dc_transfer_func *in_shaper_func; | |
1032 | struct dc_transfer_func *blend_tf; | |
6fbefb84 | 1033 | |
5dba4991 | 1034 | struct dc_transfer_func *gamcor_tf; |
4562236b HW |
1035 | enum surface_pixel_format format; |
1036 | enum dc_rotation_angle rotation; | |
4562236b HW |
1037 | enum plane_stereo_format stereo_format; |
1038 | ||
ee016c4b | 1039 | bool is_tiling_rotated; |
ebf055f9 | 1040 | bool per_pixel_alpha; |
76818cdd | 1041 | bool pre_multiplied_alpha; |
94a4ffd1 GL |
1042 | bool global_alpha; |
1043 | int global_alpha_value; | |
ebf055f9 AK |
1044 | bool visible; |
1045 | bool flip_immediate; | |
1046 | bool horizontal_mirror; | |
6d83a32d | 1047 | int layer_index; |
e12cfcb1 | 1048 | |
19ec320e | 1049 | union surface_update_flags update_flags; |
0c66824b | 1050 | bool flip_int_enabled; |
41ef8fbb AC |
1051 | bool skip_manual_trigger; |
1052 | ||
e12cfcb1 | 1053 | /* private to DC core */ |
3be5262e | 1054 | struct dc_plane_status status; |
e12cfcb1 HW |
1055 | struct dc_context *ctx; |
1056 | ||
c238bfe0 DF |
1057 | /* HACK: Workaround for forcing full reprogramming under some conditions */ |
1058 | bool force_full_update; | |
1059 | ||
e12cfcb1 HW |
1060 | /* private to dc_surface.c */ |
1061 | enum dc_irq_source irq_source; | |
4d090f0f | 1062 | struct kref refcount; |
4562236b HW |
1063 | }; |
1064 | ||
1065 | struct dc_plane_info { | |
12e2b2d4 | 1066 | struct plane_size plane_size; |
4562236b | 1067 | union dc_tiling_info tiling_info; |
9cd09bfe | 1068 | struct dc_plane_dcc_param dcc; |
4562236b HW |
1069 | enum surface_pixel_format format; |
1070 | enum dc_rotation_angle rotation; | |
4562236b | 1071 | enum plane_stereo_format stereo_format; |
56ef6ed9 | 1072 | enum dc_color_space color_space; |
ebf055f9 | 1073 | bool horizontal_mirror; |
4562236b | 1074 | bool visible; |
ebf055f9 | 1075 | bool per_pixel_alpha; |
76818cdd | 1076 | bool pre_multiplied_alpha; |
94a4ffd1 GL |
1077 | bool global_alpha; |
1078 | int global_alpha_value; | |
de4a2967 | 1079 | bool input_csc_enabled; |
6d83a32d | 1080 | int layer_index; |
4562236b HW |
1081 | }; |
1082 | ||
1083 | struct dc_scaling_info { | |
ebf055f9 AK |
1084 | struct rect src_rect; |
1085 | struct rect dst_rect; | |
1086 | struct rect clip_rect; | |
1087 | struct scaling_taps scaling_quality; | |
4562236b HW |
1088 | }; |
1089 | ||
1090 | struct dc_surface_update { | |
c9614aeb | 1091 | struct dc_plane_state *surface; |
4562236b HW |
1092 | |
1093 | /* isr safe update parameters. null means no updates */ | |
109ece8d JL |
1094 | const struct dc_flip_addrs *flip_addr; |
1095 | const struct dc_plane_info *plane_info; | |
1096 | const struct dc_scaling_info *scaling_info; | |
46250a0c | 1097 | struct fixed31_32 hdr_mult; |
4562236b HW |
1098 | /* following updates require alloc/sleep/spin that is not isr safe, |
1099 | * null means no updates | |
1100 | */ | |
109ece8d JL |
1101 | const struct dc_gamma *gamma; |
1102 | const struct dc_transfer_func *in_transfer_func; | |
de4a2967 | 1103 | |
109ece8d JL |
1104 | const struct dc_csc_transform *input_csc_color_matrix; |
1105 | const struct fixed31_32 *coeff_reduction_factor; | |
6fbefb84 HW |
1106 | const struct dc_transfer_func *func_shaper; |
1107 | const struct dc_3dlut *lut3d_func; | |
f99b6f4f | 1108 | const struct dc_transfer_func *blend_tf; |
5c41c023 | 1109 | const struct colorspace_transform *gamut_remap_matrix; |
4562236b | 1110 | }; |
4562236b HW |
1111 | |
1112 | /* | |
1113 | * Create a new surface with default parameters; | |
1114 | */ | |
fb3466a4 | 1115 | struct dc_plane_state *dc_create_plane_state(struct dc *dc); |
3be5262e HW |
1116 | const struct dc_plane_status *dc_plane_get_status( |
1117 | const struct dc_plane_state *plane_state); | |
4562236b | 1118 | |
3be5262e HW |
1119 | void dc_plane_state_retain(struct dc_plane_state *plane_state); |
1120 | void dc_plane_state_release(struct dc_plane_state *plane_state); | |
4562236b | 1121 | |
7a6c4af6 HW |
1122 | void dc_gamma_retain(struct dc_gamma *dc_gamma); |
1123 | void dc_gamma_release(struct dc_gamma **dc_gamma); | |
4562236b HW |
1124 | struct dc_gamma *dc_create_gamma(void); |
1125 | ||
7b0c470f LSL |
1126 | void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); |
1127 | void dc_transfer_func_release(struct dc_transfer_func *dc_tf); | |
90e508ba | 1128 | struct dc_transfer_func *dc_create_transfer_func(void); |
fb735a9f | 1129 | |
6fbefb84 HW |
1130 | struct dc_3dlut *dc_create_3dlut_func(void); |
1131 | void dc_3dlut_func_release(struct dc_3dlut *lut); | |
1132 | void dc_3dlut_func_retain(struct dc_3dlut *lut); | |
4562236b | 1133 | |
4fbb3ae2 | 1134 | void dc_post_update_surfaces_to_stream( |
4562236b HW |
1135 | struct dc *dc); |
1136 | ||
7c0c9672 | 1137 | #include "dc_stream.h" |
1dc90497 | 1138 | |
4562236b | 1139 | /* |
ab2541b6 | 1140 | * Structure to store surface/stream associations for validation |
4562236b HW |
1141 | */ |
1142 | struct dc_validation_set { | |
0971c40e | 1143 | struct dc_stream_state *stream; |
3be5262e HW |
1144 | struct dc_plane_state *plane_states[MAX_SURFACES]; |
1145 | uint8_t plane_count; | |
4562236b HW |
1146 | }; |
1147 | ||
98ea24e6 | 1148 | bool dc_validate_boot_timing(const struct dc *dc, |
68f1a00c AK |
1149 | const struct dc_sink *sink, |
1150 | struct dc_crtc_timing *crtc_timing); | |
1151 | ||
62c933f9 | 1152 | enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); |
1dc90497 | 1153 | |
8ab2180f EB |
1154 | void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); |
1155 | ||
c2cd9d04 ML |
1156 | bool dc_set_generic_gpio_for_stereo(bool enable, |
1157 | struct gpio_service *gpio_service); | |
1158 | ||
afcd526b JA |
1159 | /* |
1160 | * fast_validate: we return after determining if we can support the new state, | |
1161 | * but before we populate the programming info | |
1162 | */ | |
e750d56d | 1163 | enum dc_status dc_validate_global_state( |
1dc90497 | 1164 | struct dc *dc, |
afcd526b JA |
1165 | struct dc_state *new_ctx, |
1166 | bool fast_validate); | |
07d72b39 | 1167 | |
ab8db3e1 AG |
1168 | |
1169 | void dc_resource_state_construct( | |
1170 | const struct dc *dc, | |
1171 | struct dc_state *dst_ctx); | |
1172 | ||
5dba4991 BL |
1173 | bool dc_acquire_release_mpc_3dlut( |
1174 | struct dc *dc, bool acquire, | |
1175 | struct dc_stream_state *stream, | |
1176 | struct dc_3dlut **lut, | |
1177 | struct dc_transfer_func **shaper); | |
5dba4991 | 1178 | |
f36cc577 | 1179 | void dc_resource_state_copy_construct( |
608ac7bb JZ |
1180 | const struct dc_state *src_ctx, |
1181 | struct dc_state *dst_ctx); | |
8122a253 | 1182 | |
f36cc577 | 1183 | void dc_resource_state_copy_construct_current( |
1dc90497 | 1184 | const struct dc *dc, |
608ac7bb | 1185 | struct dc_state *dst_ctx); |
1dc90497 | 1186 | |
f36cc577 | 1187 | void dc_resource_state_destruct(struct dc_state *context); |
8122a253 | 1188 | |
6d822156 NC |
1189 | bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); |
1190 | ||
7cf2c840 HW |
1191 | /* |
1192 | * TODO update to make it about validation sets | |
1193 | * Set up streams and links associated to drive sinks | |
1194 | * The streams parameter is an absolute set of all active streams. | |
1195 | * | |
1196 | * After this call: | |
1197 | * Phy, Encoder, Timing Generator are programmed and enabled. | |
1198 | * New streams are enabled with blank stream; no memory read. | |
1199 | */ | |
608ac7bb | 1200 | bool dc_commit_state(struct dc *dc, struct dc_state *context); |
7cf2c840 | 1201 | |
813d20dc AW |
1202 | struct dc_state *dc_create_state(struct dc *dc); |
1203 | struct dc_state *dc_copy_state(struct dc_state *src_ctx); | |
608ac7bb JZ |
1204 | void dc_retain_state(struct dc_state *context); |
1205 | void dc_release_state(struct dc_state *context); | |
8a76708e | 1206 | |
4562236b HW |
1207 | /******************************************************************************* |
1208 | * Link Interfaces | |
1209 | ******************************************************************************/ | |
1210 | ||
d0778ebf HW |
1211 | struct dpcd_caps { |
1212 | union dpcd_rev dpcd_rev; | |
1213 | union max_lane_count max_ln_count; | |
1214 | union max_down_spread max_down_spread; | |
3c7dd2cb | 1215 | union dprx_feature dprx_feature; |
d0778ebf | 1216 | |
8628d02f JP |
1217 | /* valid only for eDP v1.4 or higher*/ |
1218 | uint8_t edp_supported_link_rates_count; | |
1219 | enum dc_link_rate edp_supported_link_rates[8]; | |
d0778ebf HW |
1220 | |
1221 | /* dongle type (DP converter, CV smart dongle) */ | |
1222 | enum display_dongle_type dongle_type; | |
4a897de1 | 1223 | bool is_dongle_type_one; |
a504ad26 HH |
1224 | /* branch device or sink device */ |
1225 | bool is_branch_dev; | |
d0778ebf HW |
1226 | /* Dongle's downstream count. */ |
1227 | union sink_count sink_count; | |
c282d951 | 1228 | bool is_mst_capable; |
d0778ebf HW |
1229 | /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, |
1230 | indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ | |
1231 | struct dc_dongle_caps dongle_caps; | |
1232 | ||
1233 | uint32_t sink_dev_id; | |
4b99affb A |
1234 | int8_t sink_dev_id_str[6]; |
1235 | int8_t sink_hw_revision; | |
1236 | int8_t sink_fw_revision[2]; | |
1237 | ||
d0778ebf HW |
1238 | uint32_t branch_dev_id; |
1239 | int8_t branch_dev_name[6]; | |
1240 | int8_t branch_hw_revision; | |
4b99affb | 1241 | int8_t branch_fw_revision[2]; |
d0778ebf HW |
1242 | |
1243 | bool allow_invalid_MSA_timing_param; | |
1244 | bool panel_mode_edp; | |
9799624a | 1245 | bool dpcd_display_control_capable; |
3c7dd2cb | 1246 | bool ext_receiver_cap_field_present; |
06f2f777 | 1247 | bool set_power_state_capable_edp; |
65e870df | 1248 | bool dynamic_backlight_capable_edp; |
39a4eb85 WL |
1249 | union dpcd_fec_capability fec_cap; |
1250 | struct dpcd_dsc_capabilities dsc_caps; | |
8e5100a5 | 1251 | struct dc_lttpr_caps lttpr_caps; |
e8536806 | 1252 | struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; |
8e5100a5 | 1253 | |
f01ee019 FZ |
1254 | union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; |
1255 | union dp_main_line_channel_coding_cap channel_coding_cap; | |
1256 | union dp_sink_video_fallback_formats fallback_formats; | |
1257 | union dp_fec_capability1 fec_cap1; | |
c595fb05 | 1258 | union dp_cable_id cable_id; |
3e6084ae PTC |
1259 | uint8_t edp_rev; |
1260 | union edp_alpm_caps alpm_caps; | |
1261 | struct edp_psr_info psr_info; | |
d0778ebf HW |
1262 | }; |
1263 | ||
96577cf8 HW |
1264 | union dpcd_sink_ext_caps { |
1265 | struct { | |
1266 | /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode | |
1267 | * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. | |
1268 | */ | |
1269 | uint8_t sdr_aux_backlight_control : 1; | |
1270 | uint8_t hdr_aux_backlight_control : 1; | |
1271 | uint8_t reserved_1 : 2; | |
1272 | uint8_t oled : 1; | |
1273 | uint8_t reserved : 3; | |
1274 | } bits; | |
1275 | uint8_t raw; | |
1276 | }; | |
1277 | ||
fe8db3bc BL |
1278 | #if defined(CONFIG_DRM_AMD_DC_HDCP) |
1279 | union hdcp_rx_caps { | |
1280 | struct { | |
1281 | uint8_t version; | |
1282 | uint8_t reserved; | |
1283 | struct { | |
1284 | uint8_t repeater : 1; | |
1285 | uint8_t hdcp_capable : 1; | |
1286 | uint8_t reserved : 6; | |
1287 | } byte0; | |
1288 | } fields; | |
1289 | uint8_t raw[3]; | |
1290 | }; | |
1291 | ||
1292 | union hdcp_bcaps { | |
1293 | struct { | |
1294 | uint8_t HDCP_CAPABLE:1; | |
1295 | uint8_t REPEATER:1; | |
1296 | uint8_t RESERVED:6; | |
1297 | } bits; | |
1298 | uint8_t raw; | |
1299 | }; | |
1300 | ||
1301 | struct hdcp_caps { | |
1302 | union hdcp_rx_caps rx_caps; | |
1303 | union hdcp_bcaps bcaps; | |
1304 | }; | |
1305 | #endif | |
1306 | ||
2e5fa5ba | 1307 | #include "dc_link.h" |
4562236b | 1308 | |
5dba4991 BL |
1309 | uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); |
1310 | ||
4562236b HW |
1311 | /******************************************************************************* |
1312 | * Sink Interfaces - A sink corresponds to a display output device | |
1313 | ******************************************************************************/ | |
1314 | ||
8c895313 | 1315 | struct dc_container_id { |
1316 | // 128bit GUID in binary form | |
1317 | unsigned char guid[16]; | |
1318 | // 8 byte port ID -> ELD.PortID | |
1319 | unsigned int portId[2]; | |
1320 | // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName | |
1321 | unsigned short manufacturerName; | |
1322 | // 2 byte product code -> ELD.ProductCode | |
1323 | unsigned short productCode; | |
1324 | }; | |
1325 | ||
b6d6103b | 1326 | |
39a4eb85 WL |
1327 | struct dc_sink_dsc_caps { |
1328 | // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), | |
1329 | // 'false' if they are sink's DSC caps | |
1330 | bool is_virtual_dpcd_dsc; | |
c022375a FZ |
1331 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
1332 | // 'true' if MST topology supports DSC passthrough for sink | |
1333 | // 'false' if MST topology does not support DSC passthrough | |
1334 | bool is_dsc_passthrough_supported; | |
1335 | #endif | |
39a4eb85 WL |
1336 | struct dsc_dec_dpcd_caps dsc_dec_caps; |
1337 | }; | |
9edba557 | 1338 | |
e6b11b43 WL |
1339 | struct dc_sink_fec_caps { |
1340 | bool is_rx_fec_supported; | |
1341 | bool is_topology_fec_supported; | |
1342 | }; | |
1343 | ||
4562236b HW |
1344 | /* |
1345 | * The sink structure contains EDID and other display device properties | |
1346 | */ | |
1347 | struct dc_sink { | |
1348 | enum signal_type sink_signal; | |
1349 | struct dc_edid dc_edid; /* raw edid */ | |
1350 | struct dc_edid_caps edid_caps; /* parse display caps */ | |
8c895313 | 1351 | struct dc_container_id *dc_container_id; |
4a9a5d62 | 1352 | uint32_t dongle_max_pix_clk; |
5c4e9806 | 1353 | void *priv; |
9edba557 | 1354 | struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; |
ebf055f9 | 1355 | bool converter_disable_audio; |
a2540e34 | 1356 | |
e6b11b43 WL |
1357 | struct dc_sink_dsc_caps dsc_caps; |
1358 | struct dc_sink_fec_caps fec_caps; | |
6fbefb84 | 1359 | |
c38cc677 MT |
1360 | bool is_vsc_sdp_colorimetry_supported; |
1361 | ||
b73a22d3 HW |
1362 | /* private to DC core */ |
1363 | struct dc_link *link; | |
1364 | struct dc_context *ctx; | |
1365 | ||
ce3f6e82 A |
1366 | uint32_t sink_id; |
1367 | ||
b73a22d3 | 1368 | /* private to dc_sink.c */ |
ce3f6e82 A |
1369 | // refcount must be the last member in dc_sink, since we want the |
1370 | // sink structure to be logically cloneable up to (but not including) | |
1371 | // refcount | |
cb56acea | 1372 | struct kref refcount; |
4562236b HW |
1373 | }; |
1374 | ||
b73a22d3 HW |
1375 | void dc_sink_retain(struct dc_sink *sink); |
1376 | void dc_sink_release(struct dc_sink *sink); | |
4562236b | 1377 | |
4562236b HW |
1378 | struct dc_sink_init_data { |
1379 | enum signal_type sink_signal; | |
d0778ebf | 1380 | struct dc_link *link; |
4562236b HW |
1381 | uint32_t dongle_max_pix_clk; |
1382 | bool converter_disable_audio; | |
1383 | }; | |
1384 | ||
e5fc7825 GT |
1385 | bool dc_extended_blank_supported(struct dc *dc); |
1386 | ||
4562236b HW |
1387 | struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); |
1388 | ||
4562236b HW |
1389 | /* Newer interfaces */ |
1390 | struct dc_cursor { | |
1391 | struct dc_plane_address address; | |
1392 | struct dc_cursor_attributes attributes; | |
1393 | }; | |
1394 | ||
28177772 | 1395 | |
4562236b HW |
1396 | /******************************************************************************* |
1397 | * Interrupt interfaces | |
1398 | ******************************************************************************/ | |
1399 | enum dc_irq_source dc_interrupt_to_irq_source( | |
1400 | struct dc *dc, | |
1401 | uint32_t src_id, | |
1402 | uint32_t ext_id); | |
a0e30392 | 1403 | bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); |
4562236b HW |
1404 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); |
1405 | enum dc_irq_source dc_get_hpd_irq_source_at_index( | |
1406 | struct dc *dc, uint32_t link_index); | |
1407 | ||
b629a824 EY |
1408 | void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); |
1409 | ||
4562236b HW |
1410 | /******************************************************************************* |
1411 | * Power Interfaces | |
1412 | ******************************************************************************/ | |
1413 | ||
1414 | void dc_set_power_state( | |
1415 | struct dc *dc, | |
a3621485 | 1416 | enum dc_acpi_cm_power_state power_state); |
fb3466a4 | 1417 | void dc_resume(struct dc *dc); |
f284975e | 1418 | |
ca751df2 SL |
1419 | void dc_power_down_on_boot(struct dc *dc); |
1420 | ||
fe8db3bc BL |
1421 | #if defined(CONFIG_DRM_AMD_DC_HDCP) |
1422 | /* | |
1423 | * HDCP Interfaces | |
1424 | */ | |
1425 | enum hdcp_message_status dc_process_hdcp_msg( | |
1426 | enum signal_type signal, | |
1427 | struct dc_link *link, | |
1428 | struct hdcp_protection_message *message_info); | |
1429 | #endif | |
c1ee92f9 | 1430 | bool dc_is_dmcu_initialized(struct dc *dc); |
4562236b | 1431 | |
925f566c CL |
1432 | enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); |
1433 | void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); | |
4d55b0dd | 1434 | |
7fc75382 BL |
1435 | bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, |
1436 | struct dc_cursor_attributes *cursor_attr); | |
4b675aad | 1437 | |
4d55b0dd BL |
1438 | void dc_allow_idle_optimizations(struct dc *dc, bool allow); |
1439 | ||
ba8b4604 | 1440 | /* set min and max memory clock to lowest and highest DPM level, respectively */ |
4d55b0dd BL |
1441 | void dc_unlock_memory_clock_frequency(struct dc *dc); |
1442 | ||
ba8b4604 | 1443 | /* set min memory clock to the min required for current mode, max to maxDPM */ |
4d55b0dd BL |
1444 | void dc_lock_memory_clock_frequency(struct dc *dc); |
1445 | ||
4866b0bf ML |
1446 | /* set soft max for memclk, to be used for AC/DC switching clock limitations */ |
1447 | void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); | |
1448 | ||
3e190955 JA |
1449 | /* cleanup on driver unload */ |
1450 | void dc_hardware_release(struct dc *dc); | |
1451 | ||
6ee90e88 | 1452 | bool dc_set_psr_allow_active(struct dc *dc, bool enable); |
ac02dc34 | 1453 | void dc_z10_restore(const struct dc *dc); |
f586fea8 | 1454 | void dc_z10_save_init(struct dc *dc); |
6ee90e88 | 1455 | |
ed720870 | 1456 | bool dc_is_dmub_outbox_supported(struct dc *dc); |
4f8e37db MS |
1457 | bool dc_enable_dmub_notifications(struct dc *dc); |
1458 | ||
ed720870 MS |
1459 | void dc_enable_dmub_outbox(struct dc *dc); |
1460 | ||
4f8e37db MS |
1461 | bool dc_process_dmub_aux_transfer_async(struct dc *dc, |
1462 | uint32_t link_index, | |
1463 | struct aux_payload *payload); | |
1464 | ||
892b74a6 MS |
1465 | /* Get dc link index from dpia port index */ |
1466 | uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, | |
1467 | uint8_t dpia_port_index); | |
71af9d46 MS |
1468 | |
1469 | bool dc_process_dmub_set_config_async(struct dc *dc, | |
1470 | uint32_t link_index, | |
1471 | struct set_config_cmd_payload *payload, | |
1472 | struct dmub_notification *notify); | |
139a3311 MS |
1473 | |
1474 | enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, | |
1475 | uint32_t link_index, | |
1476 | uint8_t mst_alloc_slots, | |
1477 | uint8_t *mst_slots_in_use); | |
1478 | ||
97bda032 HW |
1479 | /******************************************************************************* |
1480 | * DSC Interfaces | |
1481 | ******************************************************************************/ | |
1482 | #include "dc_dsc.h" | |
1c5ea40c YW |
1483 | |
1484 | /******************************************************************************* | |
1485 | * Disable acc mode Interfaces | |
1486 | ******************************************************************************/ | |
1487 | void dc_disable_accelerated_mode(struct dc *dc); | |
1488 | ||
4562236b | 1489 | #endif /* DC_INTERFACE_H_ */ |