drm/amd/display: fix array-bounds error in dc_stream_remove_writeback() [take 2]
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_stream.c
CommitLineData
4562236b
HW
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
78c77382 27#include "basics/dc_common.h"
4562236b
HW
28#include "dc.h"
29#include "core_types.h"
30#include "resource.h"
ab2541b6
AC
31#include "ipp.h"
32#include "timing_generator.h"
e18d9839 33#include "dc_dmub_srv.h"
4562236b 34
e1cb3e48
NK
35#define DC_LOGGER dc->ctx->logger
36
4562236b
HW
37/*******************************************************************************
38 * Private functions
39 ******************************************************************************/
ceb3dbb4 40void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
96313f1b 41{
ceb3dbb4
JL
42 if (sink->sink_signal == SIGNAL_TYPE_NONE)
43 stream->signal = stream->link->connector_signal;
e14ca957 44 else
ceb3dbb4 45 stream->signal = sink->sink_signal;
96313f1b
JZ
46
47 if (dc_is_dvi_signal(stream->signal)) {
7e98ab10 48 if (stream->ctx->dc->caps.dual_link_dvi &&
40df2f80
CL
49 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
50 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
96313f1b
JZ
51 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
52 else
53 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
54 }
55}
4562236b 56
4462282a 57static bool dc_stream_construct(struct dc_stream_state *stream,
b73a22d3 58 struct dc_sink *dc_sink_data)
4562236b
HW
59{
60 uint32_t i = 0;
61
b73a22d3 62 stream->sink = dc_sink_data;
4562236b
HW
63 dc_sink_retain(dc_sink_data);
64
ceb3dbb4
JL
65 stream->ctx = dc_sink_data->ctx;
66 stream->link = dc_sink_data->link;
67 stream->sink_patches = dc_sink_data->edid_caps.panel_patch;
68 stream->converter_disable_audio = dc_sink_data->converter_disable_audio;
69 stream->qs_bit = dc_sink_data->edid_caps.qs_bit;
70 stream->qy_bit = dc_sink_data->edid_caps.qy_bit;
71
4562236b
HW
72 /* Copy audio modes */
73 /* TODO - Remove this translation */
74 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
75 {
4fa086b9
LSL
76 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
77 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
78 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
79 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
4562236b 80 }
4fa086b9
LSL
81 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
82 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
83 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
4562236b 84 memmove(
4fa086b9 85 stream->audio_info.display_name,
4562236b
HW
86 dc_sink_data->edid_caps.display_name,
87 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
4fa086b9
LSL
88 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
89 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
90 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
4562236b 91
8c895313 92 if (dc_sink_data->dc_container_id != NULL) {
93 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
94
4fa086b9
LSL
95 stream->audio_info.port_id[0] = dc_container_id->portId[0];
96 stream->audio_info.port_id[1] = dc_container_id->portId[1];
8c895313 97 } else {
98 /* TODO - WindowDM has implemented,
99 other DMs need Unhardcode port_id */
4fa086b9
LSL
100 stream->audio_info.port_id[0] = 0x5558859e;
101 stream->audio_info.port_id[1] = 0xd989449;
8c895313 102 }
4562236b
HW
103
104 /* EDID CAP translation for HDMI 2.0 */
4fa086b9 105 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
4562236b 106
97bda032
HW
107 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
108 stream->timing.dsc_cfg.num_slices_h = 0;
109 stream->timing.dsc_cfg.num_slices_v = 0;
110 stream->timing.dsc_cfg.bits_per_pixel = 128;
111 stream->timing.dsc_cfg.block_pred_enable = 1;
112 stream->timing.dsc_cfg.linebuf_depth = 9;
113 stream->timing.dsc_cfg.version_minor = 2;
114 stream->timing.dsc_cfg.ycbcr422_simple = 0;
6fbefb84 115
ceb3dbb4 116 update_stream_signal(stream, dc_sink_data);
e43a432c
AK
117
118 stream->out_transfer_func = dc_create_transfer_func();
4462282a
JP
119 if (stream->out_transfer_func == NULL) {
120 dc_sink_release(dc_sink_data);
121 return false;
122 }
e43a432c 123 stream->out_transfer_func->type = TF_TYPE_BYPASS;
04a789be
JL
124
125 stream->stream_id = stream->ctx->dc_stream_id_count;
126 stream->ctx->dc_stream_id_count++;
4462282a
JP
127
128 return true;
4562236b
HW
129}
130
d9e32672 131static void dc_stream_destruct(struct dc_stream_state *stream)
4562236b 132{
b73a22d3 133 dc_sink_release(stream->sink);
4fa086b9 134 if (stream->out_transfer_func != NULL) {
e43a432c 135 dc_transfer_func_release(stream->out_transfer_func);
4fa086b9 136 stream->out_transfer_func = NULL;
80bd2096 137 }
4562236b
HW
138}
139
0971c40e 140void dc_stream_retain(struct dc_stream_state *stream)
4562236b 141{
bfe0feb1
DA
142 kref_get(&stream->refcount);
143}
144
145static void dc_stream_free(struct kref *kref)
146{
147 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
148
d9e32672 149 dc_stream_destruct(stream);
bfe0feb1 150 kfree(stream);
4562236b
HW
151}
152
0971c40e 153void dc_stream_release(struct dc_stream_state *stream)
4562236b 154{
a989ab08 155 if (stream != NULL) {
bfe0feb1 156 kref_put(&stream->refcount, dc_stream_free);
4562236b
HW
157 }
158}
159
0971c40e 160struct dc_stream_state *dc_create_stream_for_sink(
b73a22d3 161 struct dc_sink *sink)
4562236b 162{
0971c40e 163 struct dc_stream_state *stream;
4562236b
HW
164
165 if (sink == NULL)
db6c3bdc 166 return NULL;
4562236b 167
2004f45e 168 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
db6c3bdc 169 if (stream == NULL)
4462282a 170 goto alloc_fail;
4562236b 171
4462282a
JP
172 if (dc_stream_construct(stream, sink) == false)
173 goto construct_fail;
4562236b 174
bfe0feb1 175 kref_init(&stream->refcount);
4562236b 176
a989ab08 177 return stream;
4462282a
JP
178
179construct_fail:
180 kfree(stream);
181
182alloc_fail:
183 return NULL;
4562236b 184}
ab2541b6 185
43e3ac83
WL
186struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
187{
188 struct dc_stream_state *new_stream;
189
d12c2022 190 new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL);
11f874c0 191 if (!new_stream)
43e3ac83
WL
192 return NULL;
193
43e3ac83
WL
194 if (new_stream->sink)
195 dc_sink_retain(new_stream->sink);
196
197 if (new_stream->out_transfer_func)
198 dc_transfer_func_retain(new_stream->out_transfer_func);
199
b1432fcb
WL
200 new_stream->stream_id = new_stream->ctx->dc_stream_id_count;
201 new_stream->ctx->dc_stream_id_count++;
202
4a0dc87f
JK
203 /* If using dynamic encoder assignment, wait till stream committed to assign encoder. */
204 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign)
205 new_stream->link_enc = NULL;
206
43e3ac83
WL
207 kref_init(&new_stream->refcount);
208
209 return new_stream;
210}
211
09f609c3
LL
212/**
213 * dc_stream_get_status_from_state - Get stream status from given dc state
214 * @state: DC state to find the stream status in
215 * @stream: The stream to get the stream status for
216 *
217 * The given stream is expected to exist in the given dc state. Otherwise, NULL
218 * will be returned.
219 */
220struct dc_stream_status *dc_stream_get_status_from_state(
221 struct dc_state *state,
0971c40e 222 struct dc_stream_state *stream)
ab2541b6
AC
223{
224 uint8_t i;
ab2541b6 225
0713921b
W
226 if (state == NULL)
227 return NULL;
228
09f609c3
LL
229 for (i = 0; i < state->stream_count; i++) {
230 if (stream == state->streams[i])
231 return &state->stream_status[i];
e2c7bb12 232 }
ab2541b6
AC
233
234 return NULL;
235}
236
09f609c3
LL
237/**
238 * dc_stream_get_status() - Get current stream status of the given stream state
239 * @stream: The stream to get the stream status for.
240 *
241 * The given stream is expected to exist in dc->current_state. Otherwise, NULL
242 * will be returned.
243 */
244struct dc_stream_status *dc_stream_get_status(
245 struct dc_stream_state *stream)
246{
247 struct dc *dc = stream->ctx->dc;
248 return dc_stream_get_status_from_state(dc->current_state, stream);
249}
250
4fd771ea
RC
251static void program_cursor_attributes(
252 struct dc *dc,
253 struct dc_stream_state *stream,
254 const struct dc_cursor_attributes *attributes)
255{
256 int i;
257 struct resource_context *res_ctx;
258 struct pipe_ctx *pipe_to_program = NULL;
259
260 if (!stream)
261 return;
262
263 res_ctx = &dc->current_state->res_ctx;
264
265 for (i = 0; i < MAX_PIPES; i++) {
266 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
267
268 if (pipe_ctx->stream != stream)
269 continue;
270
271 if (!pipe_to_program) {
272 pipe_to_program = pipe_ctx;
273 dc->hwss.cursor_lock(dc, pipe_to_program, true);
e0adbe73
PH
274 if (pipe_to_program->next_odm_pipe)
275 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true);
4fd771ea
RC
276 }
277
278 dc->hwss.set_cursor_attribute(pipe_ctx);
b73353f7
MT
279
280 dc_send_update_cursor_info_to_dmu(pipe_ctx, i);
4fd771ea
RC
281 if (dc->hwss.set_cursor_sdr_white_level)
282 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
283 }
284
e0adbe73 285 if (pipe_to_program) {
4fd771ea 286 dc->hwss.cursor_lock(dc, pipe_to_program, false);
e0adbe73
PH
287 if (pipe_to_program->next_odm_pipe)
288 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false);
289 }
4fd771ea
RC
290}
291
831010da 292#ifndef TRIM_FSFT
ef6f9b71 293/*
cc0f379d 294 * dc_optimize_timing_for_fsft() - dc to optimize timing
831010da 295 */
cc0f379d
RA
296bool dc_optimize_timing_for_fsft(
297 struct dc_stream_state *pStream,
831010da
RA
298 unsigned int max_input_rate_in_khz)
299{
cc0f379d 300 struct dc *dc;
831010da 301
cc0f379d
RA
302 dc = pStream->ctx->dc;
303
304 return (dc->hwss.optimize_timing_for_fsft &&
305 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz));
831010da
RA
306}
307#endif
308
ef6f9b71 309/*
2119aa17 310 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
ab2541b6
AC
311 */
312bool dc_stream_set_cursor_attributes(
067c878a 313 struct dc_stream_state *stream,
ab2541b6
AC
314 const struct dc_cursor_attributes *attributes)
315{
2b77dcc5 316 struct dc *dc;
4d55b0dd 317 bool reset_idle_optimizations = false;
ab2541b6 318
4fa086b9 319 if (NULL == stream) {
ab2541b6 320 dm_error("DC: dc_stream is NULL!\n");
bf5563ed 321 return false;
ab2541b6
AC
322 }
323 if (NULL == attributes) {
324 dm_error("DC: attributes is NULL!\n");
bf5563ed 325 return false;
ab2541b6
AC
326 }
327
067c878a 328 if (attributes->address.quad_part == 0) {
b0f8d4e9 329 dm_output_to_console("DC: Cursor address is 0!\n");
067c878a
YS
330 return false;
331 }
332
2b77dcc5 333 dc = stream->ctx->dc;
fe77d95f
AL
334
335 if (dc->debug.allow_sw_cursor_fallback && attributes->height * attributes->width * 4 > 16384)
336 if (stream->mall_stream_config.type == SUBVP_MAIN)
337 return false;
338
33fd17d9 339 stream->cursor_attributes = *attributes;
ab2541b6 340
bae1f0b8 341 dc_z10_restore(dc);
4d55b0dd
BL
342 /* disable idle optimizations while updating cursor */
343 if (dc->idle_optimizations_allowed) {
4b675aad 344 dc_allow_idle_optimizations(dc, false);
4d55b0dd
BL
345 reset_idle_optimizations = true;
346 }
347
4fd771ea
RC
348 program_cursor_attributes(dc, stream, attributes);
349
4fd771ea
RC
350 /* re-enable idle optimizations if necessary */
351 if (reset_idle_optimizations)
352 dc_allow_idle_optimizations(dc, true);
353
4fd771ea
RC
354 return true;
355}
356
357static void program_cursor_position(
358 struct dc *dc,
359 struct dc_stream_state *stream,
360 const struct dc_cursor_position *position)
361{
362 int i;
363 struct resource_context *res_ctx;
364 struct pipe_ctx *pipe_to_program = NULL;
365
366 if (!stream)
367 return;
368
369 res_ctx = &dc->current_state->res_ctx;
4d55b0dd 370
ab2541b6
AC
371 for (i = 0; i < MAX_PIPES; i++) {
372 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
373
4fd771ea
RC
374 if (pipe_ctx->stream != stream ||
375 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||
376 !pipe_ctx->plane_state ||
377 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
378 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
beb16b6a 379 continue;
ab2541b6 380
3bff0796
MT
381 if (!pipe_to_program) {
382 pipe_to_program = pipe_ctx;
1e461c37 383 dc->hwss.cursor_lock(dc, pipe_to_program, true);
3bff0796 384 }
b87d78d6 385
4fd771ea 386 dc->hwss.set_cursor_position(pipe_ctx);
b73353f7
MT
387
388 dc_send_update_cursor_info_to_dmu(pipe_ctx, i);
ab2541b6 389 }
3bff0796
MT
390
391 if (pipe_to_program)
1e461c37 392 dc->hwss.cursor_lock(dc, pipe_to_program, false);
ab2541b6
AC
393}
394
395bool dc_stream_set_cursor_position(
0971c40e 396 struct dc_stream_state *stream,
beb16b6a 397 const struct dc_cursor_position *position)
ab2541b6 398{
a141d208 399 struct dc *dc = stream->ctx->dc;
4d55b0dd 400 bool reset_idle_optimizations = false;
ab2541b6 401
4fa086b9 402 if (NULL == stream) {
ab2541b6
AC
403 dm_error("DC: dc_stream is NULL!\n");
404 return false;
405 }
406
407 if (NULL == position) {
408 dm_error("DC: cursor position is NULL!\n");
409 return false;
410 }
411
2b77dcc5 412 dc = stream->ctx->dc;
bae1f0b8 413 dc_z10_restore(dc);
4d55b0dd
BL
414
415 /* disable idle optimizations if enabling cursor */
a141d208
AL
416 if (dc->idle_optimizations_allowed && (!stream->cursor_position.enable || dc->debug.exit_idle_opt_for_cursor_updates)
417 && position->enable) {
4b675aad 418 dc_allow_idle_optimizations(dc, false);
4d55b0dd
BL
419 reset_idle_optimizations = true;
420 }
421
33fd17d9 422 stream->cursor_position = *position;
ab2541b6 423
4fd771ea 424 program_cursor_position(dc, stream, position);
4d55b0dd
BL
425 /* re-enable idle optimizations if necessary */
426 if (reset_idle_optimizations)
4b675aad 427 dc_allow_idle_optimizations(dc, true);
4d55b0dd 428
beb16b6a 429 return true;
ab2541b6
AC
430}
431
6fbefb84
HW
432bool dc_stream_add_writeback(struct dc *dc,
433 struct dc_stream_state *stream,
434 struct dc_writeback_info *wb_info)
435{
436 bool isDrc = false;
437 int i = 0;
c3ec8ba5 438 struct dwbc *dwb;
6fbefb84
HW
439
440 if (stream == NULL) {
441 dm_error("DC: dc_stream is NULL!\n");
442 return false;
443 }
444
445 if (wb_info == NULL) {
446 dm_error("DC: dc_writeback_info is NULL!\n");
447 return false;
448 }
449
450 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
451 dm_error("DC: writeback pipe is invalid!\n");
452 return false;
453 }
454
455 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
456
c3ec8ba5
CL
457 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
458 dwb->dwb_is_drc = false;
6fbefb84
HW
459
460 /* recalculate and apply DML parameters */
461
462 for (i = 0; i < stream->num_wb_info; i++) {
463 /*dynamic update*/
464 if (stream->writeback_info[i].wb_enabled &&
465 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
466 stream->writeback_info[i] = *wb_info;
467 isDrc = true;
468 }
469 }
470
471 if (!isDrc) {
472 stream->writeback_info[stream->num_wb_info++] = *wb_info;
473 }
474
6fbefb84
HW
475 if (dc->hwss.enable_writeback) {
476 struct dc_stream_status *stream_status = dc_stream_get_status(stream);
477 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
6a652f6d
CL
478 dwb->otg_inst = stream_status->primary_otg_inst;
479 }
480 if (IS_DIAG_DC(dc->ctx->dce_environment)) {
481 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
482 dm_error("DC: update_bandwidth failed!\n");
483 return false;
484 }
6fbefb84 485
6a652f6d
CL
486 /* enable writeback */
487 if (dc->hwss.enable_writeback) {
488 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
489
490 if (dwb->funcs->is_enabled(dwb)) {
491 /* writeback pipe already enabled, only need to update */
492 dc->hwss.update_writeback(dc, wb_info, dc->current_state);
493 } else {
494 /* Enable writeback pipe from scratch*/
495 dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
496 }
6fbefb84
HW
497 }
498 }
6fbefb84
HW
499 return true;
500}
501
502bool dc_stream_remove_writeback(struct dc *dc,
503 struct dc_stream_state *stream,
504 uint32_t dwb_pipe_inst)
505{
506 int i = 0, j = 0;
507 if (stream == NULL) {
508 dm_error("DC: dc_stream is NULL!\n");
509 return false;
510 }
511
512 if (dwb_pipe_inst >= MAX_DWB_PIPES) {
513 dm_error("DC: writeback pipe is invalid!\n");
514 return false;
515 }
516
517// stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
518 for (i = 0; i < stream->num_wb_info; i++) {
519 /*dynamic update*/
520 if (stream->writeback_info[i].wb_enabled &&
521 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) {
522 stream->writeback_info[i].wb_enabled = false;
523 }
524 }
525
526 /* remove writeback info for disabled writeback pipes from stream */
faf4d8e0 527 for (i = 0, j = 0; i < stream->num_wb_info; i++) {
6fbefb84 528 if (stream->writeback_info[i].wb_enabled) {
faf4d8e0 529 if (j < i)
6fbefb84
HW
530 /* trim the array */
531 stream->writeback_info[j] = stream->writeback_info[i];
532 j++;
533 }
534 }
535 stream->num_wb_info = j;
536
6a652f6d
CL
537 if (IS_DIAG_DC(dc->ctx->dce_environment)) {
538 /* recalculate and apply DML parameters */
539 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
540 dm_error("DC: update_bandwidth failed!\n");
541 return false;
542 }
6fbefb84 543
6a652f6d
CL
544 /* disable writeback */
545 if (dc->hwss.disable_writeback)
546 dc->hwss.disable_writeback(dc, dwb_pipe_inst);
547 }
6fbefb84
HW
548 return true;
549}
6fbefb84 550
6a652f6d
CL
551bool dc_stream_warmup_writeback(struct dc *dc,
552 int num_dwb,
553 struct dc_writeback_info *wb_info)
554{
555 if (dc->hwss.mmhubbub_warmup)
556 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
557 else
558 return false;
559}
0971c40e 560uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
ab2541b6
AC
561{
562 uint8_t i;
2b77dcc5 563 struct dc *dc = stream->ctx->dc;
ab2541b6 564 struct resource_context *res_ctx =
2b77dcc5 565 &dc->current_state->res_ctx;
ab2541b6
AC
566
567 for (i = 0; i < MAX_PIPES; i++) {
6b670fa9 568 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
ab2541b6
AC
569
570 if (res_ctx->pipe_ctx[i].stream != stream)
571 continue;
572
573 return tg->funcs->get_frame_count(tg);
574 }
575
576 return 0;
577}
578
d5f90f3a
LHM
579bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
580 const uint8_t *custom_sdp_message,
581 unsigned int sdp_message_size)
582{
583 int i;
88ccdf1d 584 struct dc *dc;
d5f90f3a
LHM
585 struct resource_context *res_ctx;
586
587 if (stream == NULL) {
588 dm_error("DC: dc_stream is NULL!\n");
589 return false;
590 }
591
88ccdf1d
LHM
592 dc = stream->ctx->dc;
593 res_ctx = &dc->current_state->res_ctx;
d5f90f3a
LHM
594
595 for (i = 0; i < MAX_PIPES; i++) {
596 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
597
598 if (pipe_ctx->stream != stream)
599 continue;
600
88ccdf1d
LHM
601 if (dc->hwss.send_immediate_sdp_message != NULL)
602 dc->hwss.send_immediate_sdp_message(pipe_ctx,
603 custom_sdp_message,
604 sdp_message_size);
605 else
606 DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n",
607 __func__);
d5f90f3a 608
d5f90f3a
LHM
609 }
610
611 return true;
612}
613
0971c40e 614bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
81c50963
ST
615 uint32_t *v_blank_start,
616 uint32_t *v_blank_end,
617 uint32_t *h_position,
618 uint32_t *v_position)
ab2541b6
AC
619{
620 uint8_t i;
81c50963 621 bool ret = false;
2b77dcc5 622 struct dc *dc = stream->ctx->dc;
ab2541b6 623 struct resource_context *res_ctx =
2b77dcc5 624 &dc->current_state->res_ctx;
ab2541b6
AC
625
626 for (i = 0; i < MAX_PIPES; i++) {
6b670fa9 627 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
ab2541b6
AC
628
629 if (res_ctx->pipe_ctx[i].stream != stream)
630 continue;
631
81c50963
ST
632 tg->funcs->get_scanoutpos(tg,
633 v_blank_start,
634 v_blank_end,
635 h_position,
636 v_position);
637
638 ret = true;
639 break;
ab2541b6
AC
640 }
641
81c50963 642 return ret;
ab2541b6 643}
f591344e 644
6fbefb84
HW
645bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
646{
6fbefb84
HW
647 struct pipe_ctx *pipe = NULL;
648 int i;
649
650 if (!dc->hwss.dmdata_status_done)
651 return false;
652
653 for (i = 0; i < MAX_PIPES; i++) {
654 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
655 if (pipe->stream == stream)
656 break;
657 }
658 /* Stream not found, by default we'll assume HUBP fetched dm data */
659 if (i == MAX_PIPES)
660 return true;
661
b7436197 662 return dc->hwss.dmdata_status_done(pipe);
6fbefb84
HW
663}
664
665bool dc_stream_set_dynamic_metadata(struct dc *dc,
666 struct dc_stream_state *stream,
667 struct dc_dmdata_attributes *attr)
668{
669 struct pipe_ctx *pipe_ctx = NULL;
670 struct hubp *hubp;
671 int i;
672
f591344e
JP
673 /* Dynamic metadata is only supported on HDMI or DP */
674 if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal))
675 return false;
676
677 /* Check hardware support */
678 if (!dc->hwss.program_dmdata_engine)
679 return false;
680
6fbefb84
HW
681 for (i = 0; i < MAX_PIPES; i++) {
682 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
683 if (pipe_ctx->stream == stream)
684 break;
685 }
686
687 if (i == MAX_PIPES)
688 return false;
689
690 hubp = pipe_ctx->plane_res.hubp;
691 if (hubp == NULL)
692 return false;
693
694 pipe_ctx->stream->dmdata_address = attr->address;
695
f591344e 696 dc->hwss.program_dmdata_engine(pipe_ctx);
6fbefb84
HW
697
698 if (hubp->funcs->dmdata_set_attributes != NULL &&
699 pipe_ctx->stream->dmdata_address.quad_part != 0) {
700 hubp->funcs->dmdata_set_attributes(hubp, attr);
701 }
702
703 return true;
704}
ab2541b6 705
b4f71c8c
AP
706enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
707 struct dc_state *state,
708 struct dc_stream_state *stream)
709{
710 if (dc->res_pool->funcs->add_dsc_to_stream_resource) {
711 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream);
712 } else {
713 return DC_NO_DSC_RESOURCE;
714 }
715}
716
10499e40
LHM
717struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream)
718{
719 int i = 0;
720
721 for (i = 0; i < MAX_PIPES; i++) {
722 struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i];
723
724 if (pipe->stream == stream)
725 return pipe;
726 }
727
728 return NULL;
729}
730
e1cb3e48 731void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
ab2541b6 732{
e1cb3e48
NK
733 DC_LOG_DC(
734 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
4fa086b9
LSL
735 stream,
736 stream->src.x,
737 stream->src.y,
738 stream->src.width,
739 stream->src.height,
740 stream->dst.x,
741 stream->dst.y,
742 stream->dst.width,
743 stream->dst.height,
744 stream->output_color_space);
e1cb3e48 745 DC_LOG_DC(
4b679bc3 746 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
380604e2 747 stream->timing.pix_clk_100hz / 10,
4fa086b9
LSL
748 stream->timing.h_total,
749 stream->timing.v_total,
750 stream->timing.pixel_encoding,
751 stream->timing.display_color_depth);
e1cb3e48 752 DC_LOG_DC(
ab2541b6 753 "\tlink: %d\n",
ceb3dbb4 754 stream->link->link_index);
fa39f936
HW
755
756 DC_LOG_DC(
757 "\tdsc: %d, mst_pbn: %d\n",
758 stream->timing.flags.DSC,
759 stream->timing.dsc_cfg.mst_pbn);
760
761 if (stream->sink) {
762 if (stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
763 stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
764
765 DC_LOG_DC(
766 "\tdispname: %s signal: %x\n",
767 stream->sink->edid_caps.display_name,
768 stream->signal);
769 }
770 }
ab2541b6 771}
ccc87505 772