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drm/amd/display: Enable DP YCbCr420 mode support for DCN10
[linux-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
CommitLineData
4562236b
HW		 1/* Copyright 2015 Advanced Micro Devices, Inc. */
2#include "dm_services.h"
3#include "dc.h"
4#include "dc_link_dp.h"
5#include "dm_helpers.h"
7f93c1de 6#include "opp.h"
97bda032 7#include "dsc.h"
6fbefb84 8#include "resource.h"
4562236b
HW		 9
10#include "inc/core_types.h"
11#include "link_hwss.h"
12#include "dc_link_ddc.h"
13#include "core_status.h"
14#include "dpcd_defs.h"
dc6e2448
WW		 15#include "dc_dmub_srv.h"
16#include "dce/dmub_hw_lock_mgr.h"
4562236b 17
1296423b
BL		 18#define DC_LOGGER \
19 link->ctx->logger
4562236b 20
8e5100a5 21
64c12b73 22#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
8e5100a5 23
4562236b
HW		 24/* maximum pre emphasis level allowed for each voltage swing level*/
25static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
26 PRE_EMPHASIS_LEVEL3,
27 PRE_EMPHASIS_LEVEL2,
28 PRE_EMPHASIS_LEVEL1,
29 PRE_EMPHASIS_DISABLED };
30
31enum {
32 POST_LT_ADJ_REQ_LIMIT = 6,
33 POST_LT_ADJ_REQ_TIMEOUT = 200
34};
35
36enum {
37 LINK_TRAINING_MAX_RETRY_COUNT = 5,
38 /* to avoid infinite loop where-in the receiver
39 * switches between different VS
40 */
41 LINK_TRAINING_MAX_CR_RETRY = 100
42};
43
04e21292
DA		 44static bool decide_fallback_link_setting(
45 struct dc_link_settings initial_link_settings,
46 struct dc_link_settings *current_link_setting,
47 enum link_training_result training_result);
9a6a8075 48static struct dc_link_settings get_common_supported_link_settings(
04e21292
DA		 49 struct dc_link_settings link_setting_a,
50 struct dc_link_settings link_setting_b);
51
3fb068c3 52static uint32_t get_eq_training_aux_rd_interval(
d0778ebf 53 struct dc_link *link,
3fb068c3 54 const struct dc_link_settings *link_settings)
4562236b 55{
d6d36b55 56 union training_aux_rd_interval training_rd_interval;
3fb068c3 57 uint32_t wait_in_micro_secs = 400;
d6d36b55
NC		 58
59 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
4562236b
HW		 60 /* overwrite the delay if rev > 1.1*/
61 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
62 /* DP 1.2 or later - retrieve delay through
63 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
64 core_link_read_dpcd(
65 link,
3a340294 66 DP_TRAINING_AUX_RD_INTERVAL,
4562236b
HW		 67 (uint8_t *)&training_rd_interval,
68 sizeof(training_rd_interval));
69
70 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
3fb068c3 71 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
4562236b
HW		 72 }
73
3fb068c3 74 return wait_in_micro_secs;
e0a6440a
DG		 75}
76
77static void wait_for_training_aux_rd_interval(
78 struct dc_link *link,
79 uint32_t wait_in_micro_secs)
80{
81 udelay(wait_in_micro_secs);
4562236b 82
1296423b 83 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
4562236b 84 __func__,
e0a6440a 85 wait_in_micro_secs);
4562236b
HW		 86}
87
88static void dpcd_set_training_pattern(
d0778ebf 89 struct dc_link *link,
4562236b
HW		 90 union dpcd_training_pattern dpcd_pattern)
91{
92 core_link_write_dpcd(
93 link,
3a340294 94 DP_TRAINING_PATTERN_SET,
4562236b
HW		 95 &dpcd_pattern.raw,
96 1);
97
1296423b 98 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
4562236b 99 __func__,
3a340294 100 DP_TRAINING_PATTERN_SET,
4562236b
HW		 101 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
102}
103
ce17ce17
WL		 104static enum dc_dp_training_pattern decide_cr_training_pattern(
105 const struct dc_link_settings *link_settings)
106{
107 enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
108
109 return pattern;
110}
111
112static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
113 const struct dc_link_settings *link_settings)
16b6253a 114{
e0a6440a 115 enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
16b6253a 116 struct encoder_feature_support *features = &link->link_enc->features;
117 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
118
119 if (features->flags.bits.IS_TPS3_CAPABLE)
e0a6440a 120 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
16b6253a 121
122 if (features->flags.bits.IS_TPS4_CAPABLE)
e0a6440a 123 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
16b6253a 124
125 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
e0a6440a
DG		 126 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
127 return DP_TRAINING_PATTERN_SEQUENCE_4;
16b6253a 128
129 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
e0a6440a
DG		 130 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
131 return DP_TRAINING_PATTERN_SEQUENCE_3;
16b6253a 132
e0a6440a 133 return DP_TRAINING_PATTERN_SEQUENCE_2;
16b6253a 134}
135
4562236b 136static void dpcd_set_link_settings(
d0778ebf 137 struct dc_link *link,
4562236b
HW		 138 const struct link_training_settings *lt_settings)
139{
8628d02f 140 uint8_t rate;
4562236b 141
9a6a8075
HW		 142 union down_spread_ctrl downspread = { {0} };
143 union lane_count_set lane_count_set = { {0} };
4562236b
HW		 144
145 downspread.raw = (uint8_t)
146 (lt_settings->link_settings.link_spread);
147
148 lane_count_set.bits.LANE_COUNT_SET =
149 lt_settings->link_settings.lane_count;
150
e0a6440a 151 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
16b6253a 152 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
153
e0a6440a 154
ce17ce17 155 if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
16b6253a 156 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
157 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
158 }
4562236b 159
3a340294 160 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
e0a6440a 161 &downspread.raw, sizeof(downspread));
4562236b 162
8628d02f 163 core_link_write_dpcd(link, DP_LANE_COUNT_SET,
e0a6440a 164 &lane_count_set.raw, 1);
8628d02f 165
b03a599b 166 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
8628d02f
JP		 167 lt_settings->link_settings.use_link_rate_set == true) {
168 rate = 0;
169 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
b03a599b 170 core_link_write_dpcd(link, DP_LINK_RATE_SET,
8628d02f
JP		 171 &lt_settings->link_settings.link_rate_set, 1);
172 } else {
173 rate = (uint8_t) (lt_settings->link_settings.link_rate);
174 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
b03a599b
DL		 175 }
176
8628d02f 177 if (rate) {
e0a6440a 178 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
8628d02f
JP		 179 __func__,
180 DP_LINK_BW_SET,
181 lt_settings->link_settings.link_rate,
182 DP_LANE_COUNT_SET,
183 lt_settings->link_settings.lane_count,
e0a6440a 184 lt_settings->enhanced_framing,
8628d02f
JP		 185 DP_DOWNSPREAD_CTRL,
186 lt_settings->link_settings.link_spread);
187 } else {
e0a6440a 188 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
8628d02f
JP		 189 __func__,
190 DP_LINK_RATE_SET,
191 lt_settings->link_settings.link_rate_set,
192 DP_LANE_COUNT_SET,
193 lt_settings->link_settings.lane_count,
e0a6440a 194 lt_settings->enhanced_framing,
8628d02f
JP		 195 DP_DOWNSPREAD_CTRL,
196 lt_settings->link_settings.link_spread);
197 }
4562236b
HW		 198}
199
200static enum dpcd_training_patterns
e0a6440a 201 dc_dp_training_pattern_to_dpcd_training_pattern(
d0778ebf 202 struct dc_link *link,
e0a6440a 203 enum dc_dp_training_pattern pattern)
4562236b
HW		 204{
205 enum dpcd_training_patterns dpcd_tr_pattern =
206 DPCD_TRAINING_PATTERN_VIDEOIDLE;
207
208 switch (pattern) {
e0a6440a 209 case DP_TRAINING_PATTERN_SEQUENCE_1:
4562236b
HW		 210 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
211 break;
e0a6440a 212 case DP_TRAINING_PATTERN_SEQUENCE_2:
4562236b
HW		 213 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
214 break;
e0a6440a 215 case DP_TRAINING_PATTERN_SEQUENCE_3:
4562236b
HW		 216 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
217 break;
e0a6440a 218 case DP_TRAINING_PATTERN_SEQUENCE_4:
4562236b
HW		 219 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
220 break;
221 default:
222 ASSERT(0);
1296423b 223 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
4562236b
HW		 224 __func__, pattern);
225 break;
226 }
227
228 return dpcd_tr_pattern;
4562236b
HW		 229}
230
7d1ee78f
VS		 231static uint8_t dc_dp_initialize_scrambling_data_symbols(
232 struct dc_link *link,
233 enum dc_dp_training_pattern pattern)
234{
235 uint8_t disable_scrabled_data_symbols = 0;
236
237 switch (pattern) {
238 case DP_TRAINING_PATTERN_SEQUENCE_1:
239 case DP_TRAINING_PATTERN_SEQUENCE_2:
240 case DP_TRAINING_PATTERN_SEQUENCE_3:
241 disable_scrabled_data_symbols = 1;
242 break;
243 case DP_TRAINING_PATTERN_SEQUENCE_4:
244 disable_scrabled_data_symbols = 0;
245 break;
246 default:
247 ASSERT(0);
248 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
249 __func__, pattern);
250 break;
251 }
252 return disable_scrabled_data_symbols;
253}
254
64c12b73 255static inline bool is_repeater(struct dc_link *link, uint32_t offset)
256{
c797ede0 257 return (link->lttpr_non_transparent_mode && offset != 0);
64c12b73 258}
259
4562236b 260static void dpcd_set_lt_pattern_and_lane_settings(
d0778ebf 261 struct dc_link *link,
4562236b 262 const struct link_training_settings *lt_settings,
64c12b73 263 enum dc_dp_training_pattern pattern,
264 uint32_t offset)
4562236b 265{
9a6a8075 266 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
64c12b73 267
268 uint32_t dpcd_base_lt_offset;
269
4562236b 270 uint8_t dpcd_lt_buffer[5] = {0};
9a6a8075 271 union dpcd_training_pattern dpcd_pattern = { {0} };
4562236b
HW		 272 uint32_t lane;
273 uint32_t size_in_bytes;
274 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
64c12b73 275 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
276
277 if (is_repeater(link, offset))
278 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
279 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b
HW		 280
281 /*****************************************************************
282 * DpcdAddress_TrainingPatternSet
283 *****************************************************************/
284 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
e0a6440a 285 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
4562236b 286
7d1ee78f
VS		 287 dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
288 dc_dp_initialize_scrambling_data_symbols(link, pattern);
289
64c12b73 290 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
4562236b
HW		 291 = dpcd_pattern.raw;
292
460adc6b 293 if (is_repeater(link, offset)) {
294 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
295 __func__,
296 offset,
297 dpcd_base_lt_offset,
298 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
299 } else {
300 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
301 __func__,
302 dpcd_base_lt_offset,
303 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
304 }
4562236b
HW		 305 /*****************************************************************
306 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
307 *****************************************************************/
308 for (lane = 0; lane <
309 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
310
311 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
312 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
313 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
314 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
315
316 dpcd_lane[lane].bits.MAX_SWING_REACHED =
317 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
318 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
319 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
320 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
321 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
322 }
323
64c12b73 324 /* concatenate everything into one buffer*/
4562236b
HW		 325
326 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
327
328 // 0x00103 - 0x00102
329 memmove(
64c12b73 330 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
4562236b
HW		 331 dpcd_lane,
332 size_in_bytes);
333
460adc6b 334 if (is_repeater(link, offset)) {
335 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
336 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
337 __func__,
338 offset,
339 dpcd_base_lt_offset,
340 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
341 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
342 dpcd_lane[0].bits.MAX_SWING_REACHED,
343 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
344 } else {
345 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
346 __func__,
347 dpcd_base_lt_offset,
348 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
349 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
350 dpcd_lane[0].bits.MAX_SWING_REACHED,
351 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
352 }
4562236b
HW		 353 if (edp_workaround) {
354 /* for eDP write in 2 parts because the 5-byte burst is
355 * causing issues on some eDP panels (EPR#366724)
356 */
357 core_link_write_dpcd(
358 link,
3a340294 359 DP_TRAINING_PATTERN_SET,
4562236b 360 &dpcd_pattern.raw,
9a6a8075 361 sizeof(dpcd_pattern.raw));
4562236b
HW		 362
363 core_link_write_dpcd(
364 link,
3a340294 365 DP_TRAINING_LANE0_SET,
4562236b
HW		 366 (uint8_t *)(dpcd_lane),
367 size_in_bytes);
368
369 } else
370 /* write it all in (1 + number-of-lanes)-byte burst*/
371 core_link_write_dpcd(
372 link,
373 dpcd_base_lt_offset,
374 dpcd_lt_buffer,
9a6a8075 375 size_in_bytes + sizeof(dpcd_pattern.raw));
4562236b 376
d0778ebf 377 link->cur_lane_setting = lt_settings->lane_settings[0];
4562236b
HW		 378}
379
380static bool is_cr_done(enum dc_lane_count ln_count,
381 union lane_status *dpcd_lane_status)
382{
4562236b
HW		 383 uint32_t lane;
384 /*LANEx_CR_DONE bits All 1's?*/
385 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
386 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
d56b83f7 387 return false;
4562236b 388 }
d56b83f7 389 return true;
4562236b
HW		 390}
391
392static bool is_ch_eq_done(enum dc_lane_count ln_count,
393 union lane_status *dpcd_lane_status,
394 union lane_align_status_updated *lane_status_updated)
395{
4562236b
HW		 396 uint32_t lane;
397 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
d56b83f7 398 return false;
4562236b
HW		 399 else {
400 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
401 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
402 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
d56b83f7 403 return false;
4562236b
HW		 404 }
405 }
d56b83f7 406 return true;
4562236b
HW		 407}
408
409static void update_drive_settings(
410 struct link_training_settings *dest,
411 struct link_training_settings src)
412{
413 uint32_t lane;
414 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
e0a6440a
DG		 415 if (dest->voltage_swing == NULL)
416 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
417 else
418 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
419
420 if (dest->pre_emphasis == NULL)
421 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
422 else
423 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
424
425 if (dest->post_cursor2 == NULL)
426 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
427 else
428 dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
4562236b
HW		 429 }
430}
431
432static uint8_t get_nibble_at_index(const uint8_t *buf,
433 uint32_t index)
434{
435 uint8_t nibble;
436 nibble = buf[index / 2];
437
438 if (index % 2)
439 nibble >>= 4;
440 else
441 nibble &= 0x0F;
442
443 return nibble;
444}
445
446static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
447 enum dc_voltage_swing voltage)
448{
449 enum dc_pre_emphasis pre_emphasis;
450 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
451
452 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
453 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
454
455 return pre_emphasis;
456
457}
458
459static void find_max_drive_settings(
460 const struct link_training_settings *link_training_setting,
461 struct link_training_settings *max_lt_setting)
462{
463 uint32_t lane;
464 struct dc_lane_settings max_requested;
465
466 max_requested.VOLTAGE_SWING =
467 link_training_setting->
468 lane_settings[0].VOLTAGE_SWING;
469 max_requested.PRE_EMPHASIS =
470 link_training_setting->
471 lane_settings[0].PRE_EMPHASIS;
472 /*max_requested.postCursor2 =
473 * link_training_setting->laneSettings[0].postCursor2;*/
474
475 /* Determine what the maximum of the requested settings are*/
476 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
477 lane++) {
478 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
479 max_requested.VOLTAGE_SWING)
480
481 max_requested.VOLTAGE_SWING =
482 link_training_setting->
483 lane_settings[lane].VOLTAGE_SWING;
484
485 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
486 max_requested.PRE_EMPHASIS)
487 max_requested.PRE_EMPHASIS =
488 link_training_setting->
489 lane_settings[lane].PRE_EMPHASIS;
490
491 /*
492 if (link_training_setting->laneSettings[lane].postCursor2 >
493 max_requested.postCursor2)
494 {
495 max_requested.postCursor2 =
496 link_training_setting->laneSettings[lane].postCursor2;
497 }
498 */
499 }
500
501 /* make sure the requested settings are
502 * not higher than maximum settings*/
503 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
504 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
505
506 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
507 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
508 /*
509 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
510 max_requested.postCursor2 = PostCursor2_MaxLevel;
511 */
512
513 /* make sure the pre-emphasis matches the voltage swing*/
514 if (max_requested.PRE_EMPHASIS >
515 get_max_pre_emphasis_for_voltage_swing(
516 max_requested.VOLTAGE_SWING))
517 max_requested.PRE_EMPHASIS =
518 get_max_pre_emphasis_for_voltage_swing(
519 max_requested.VOLTAGE_SWING);
520
521 /*
522 * Post Cursor2 levels are completely independent from
523 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
524 * can only be applied to each allowable combination of voltage
525 * swing and pre-emphasis levels */
526 /* if ( max_requested.postCursor2 >
527 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
528 * max_requested.postCursor2 =
529 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
530 */
531
532 max_lt_setting->link_settings.link_rate =
533 link_training_setting->link_settings.link_rate;
534 max_lt_setting->link_settings.lane_count =
535 link_training_setting->link_settings.lane_count;
536 max_lt_setting->link_settings.link_spread =
537 link_training_setting->link_settings.link_spread;
538
539 for (lane = 0; lane <
540 link_training_setting->link_settings.lane_count;
541 lane++) {
542 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
543 max_requested.VOLTAGE_SWING;
544 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
545 max_requested.PRE_EMPHASIS;
546 /*max_lt_setting->laneSettings[lane].postCursor2 =
547 * max_requested.postCursor2;
548 */
549 }
550
551}
552
553static void get_lane_status_and_drive_settings(
d0778ebf 554 struct dc_link *link,
4562236b
HW		 555 const struct link_training_settings *link_training_setting,
556 union lane_status *ln_status,
557 union lane_align_status_updated *ln_status_updated,
64c12b73 558 struct link_training_settings *req_settings,
559 uint32_t offset)
4562236b 560{
64c12b73 561 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
562 uint8_t lane_adjust_offset = 4;
563 unsigned int lane01_adjust_address;
4562236b 564 uint8_t dpcd_buf[6] = {0};
9a6a8075
HW		 565 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
566 struct link_training_settings request_settings = { {0} };
4562236b
HW		 567 uint32_t lane;
568
569 memset(req_settings, '\0', sizeof(struct link_training_settings));
570
64c12b73 571 if (is_repeater(link, offset)) {
572 lane01_status_address =
573 DP_LANE0_1_STATUS_PHY_REPEATER1 +
574 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
575 lane_adjust_offset = 3;
576 }
577
4562236b
HW		 578 core_link_read_dpcd(
579 link,
64c12b73 580 lane01_status_address,
4562236b
HW		 581 (uint8_t *)(dpcd_buf),
582 sizeof(dpcd_buf));
583
584 for (lane = 0; lane <
585 (uint32_t)(link_training_setting->link_settings.lane_count);
586 lane++) {
587
588 ln_status[lane].raw =
589 get_nibble_at_index(&dpcd_buf[0], lane);
590 dpcd_lane_adjust[lane].raw =
64c12b73 591 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
4562236b
HW		 592 }
593
594 ln_status_updated->raw = dpcd_buf[2];
595
460adc6b 596 if (is_repeater(link, offset)) {
597 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
598 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
599 __func__,
600 offset,
601 lane01_status_address, dpcd_buf[0],
602 lane01_status_address + 1, dpcd_buf[1]);
603 } else {
604 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
605 __func__,
606 lane01_status_address, dpcd_buf[0],
607 lane01_status_address + 1, dpcd_buf[1]);
608 }
64c12b73 609 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
610
611 if (is_repeater(link, offset))
612 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
613 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b 614
460adc6b 615 if (is_repeater(link, offset)) {
616 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
617 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
618 __func__,
619 offset,
620 lane01_adjust_address,
621 dpcd_buf[lane_adjust_offset],
622 lane01_adjust_address + 1,
623 dpcd_buf[lane_adjust_offset + 1]);
624 } else {
625 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
626 __func__,
627 lane01_adjust_address,
628 dpcd_buf[lane_adjust_offset],
629 lane01_adjust_address + 1,
630 dpcd_buf[lane_adjust_offset + 1]);
631 }
4562236b
HW		 632
633 /*copy to req_settings*/
634 request_settings.link_settings.lane_count =
635 link_training_setting->link_settings.lane_count;
636 request_settings.link_settings.link_rate =
637 link_training_setting->link_settings.link_rate;
638 request_settings.link_settings.link_spread =
639 link_training_setting->link_settings.link_spread;
640
641 for (lane = 0; lane <
642 (uint32_t)(link_training_setting->link_settings.lane_count);
643 lane++) {
644
645 request_settings.lane_settings[lane].VOLTAGE_SWING =
646 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
647 VOLTAGE_SWING_LANE);
648 request_settings.lane_settings[lane].PRE_EMPHASIS =
649 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
650 PRE_EMPHASIS_LANE);
651 }
652
653 /*Note: for postcursor2, read adjusted
654 * postcursor2 settings from*/
655 /*DpcdAddress_AdjustRequestPostCursor2 =
656 *0x020C (not implemented yet)*/
657
658 /* we find the maximum of the requested settings across all lanes*/
659 /* and set this maximum for all lanes*/
660 find_max_drive_settings(&request_settings, req_settings);
661
662 /* if post cursor 2 is needed in the future,
663 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
664 */
665
666}
667
668static void dpcd_set_lane_settings(
d0778ebf 669 struct dc_link *link,
64c12b73 670 const struct link_training_settings *link_training_setting,
671 uint32_t offset)
4562236b
HW		 672{
673 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
674 uint32_t lane;
64c12b73 675 unsigned int lane0_set_address;
676
677 lane0_set_address = DP_TRAINING_LANE0_SET;
678
679 if (is_repeater(link, offset))
680 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
681 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b
HW		 682
683 for (lane = 0; lane <
684 (uint32_t)(link_training_setting->
685 link_settings.lane_count);
686 lane++) {
687 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
688 (uint8_t)(link_training_setting->
689 lane_settings[lane].VOLTAGE_SWING);
690 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
691 (uint8_t)(link_training_setting->
692 lane_settings[lane].PRE_EMPHASIS);
693 dpcd_lane[lane].bits.MAX_SWING_REACHED =
694 (link_training_setting->
695 lane_settings[lane].VOLTAGE_SWING ==
696 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
697 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
698 (link_training_setting->
699 lane_settings[lane].PRE_EMPHASIS ==
700 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
701 }
702
703 core_link_write_dpcd(link,
64c12b73 704 lane0_set_address,
4562236b
HW		 705 (uint8_t *)(dpcd_lane),
706 link_training_setting->link_settings.lane_count);
707
708 /*
709 if (LTSettings.link.rate == LinkRate_High2)
710 {
711 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
712 for ( uint32_t lane = 0;
713 lane < lane_count_DPMax; lane++)
714 {
715 dpcd_lane2[lane].bits.post_cursor2_set =
716 static_cast<unsigned char>(
717 LTSettings.laneSettings[lane].postCursor2);
718 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
719 }
720 m_pDpcdAccessSrv->WriteDpcdData(
721 DpcdAddress_Lane0Set2,
722 reinterpret_cast<unsigned char*>(dpcd_lane2),
723 LTSettings.link.lanes);
724 }
725 */
726
460adc6b 727 if (is_repeater(link, offset)) {
728 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
729 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
730 __func__,
731 offset,
732 lane0_set_address,
733 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
734 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
735 dpcd_lane[0].bits.MAX_SWING_REACHED,
736 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
4562236b 737
460adc6b 738 } else {
739 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
740 __func__,
741 lane0_set_address,
742 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
743 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
744 dpcd_lane[0].bits.MAX_SWING_REACHED,
745 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
746 }
d0778ebf 747 link->cur_lane_setting = link_training_setting->lane_settings[0];
4562236b
HW		 748
749}
750
751static bool is_max_vs_reached(
752 const struct link_training_settings *lt_settings)
753{
754 uint32_t lane;
755 for (lane = 0; lane <
756 (uint32_t)(lt_settings->link_settings.lane_count);
757 lane++) {
758 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
759 == VOLTAGE_SWING_MAX_LEVEL)
760 return true;
761 }
762 return false;
763
764}
765
4562236b 766static bool perform_post_lt_adj_req_sequence(
d0778ebf 767 struct dc_link *link,
4562236b
HW		 768 struct link_training_settings *lt_settings)
769{
770 enum dc_lane_count lane_count =
771 lt_settings->link_settings.lane_count;
772
773 uint32_t adj_req_count;
774 uint32_t adj_req_timer;
775 bool req_drv_setting_changed;
776 uint32_t lane;
777
778 req_drv_setting_changed = false;
779 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
780 adj_req_count++) {
781
782 req_drv_setting_changed = false;
783
784 for (adj_req_timer = 0;
785 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
786 adj_req_timer++) {
787
788 struct link_training_settings req_settings;
789 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
790 union lane_align_status_updated
791 dpcd_lane_status_updated;
792
793 get_lane_status_and_drive_settings(
794 link,
795 lt_settings,
796 dpcd_lane_status,
797 &dpcd_lane_status_updated,
64c12b73 798 &req_settings,
799 DPRX);
4562236b
HW		 800
801 if (dpcd_lane_status_updated.bits.
802 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
803 return true;
804
805 if (!is_cr_done(lane_count, dpcd_lane_status))
806 return false;
807
808 if (!is_ch_eq_done(
809 lane_count,
810 dpcd_lane_status,
811 &dpcd_lane_status_updated))
812 return false;
813
814 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
815
816 if (lt_settings->
817 lane_settings[lane].VOLTAGE_SWING !=
818 req_settings.lane_settings[lane].
819 VOLTAGE_SWING ||
820 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
821 req_settings.lane_settings[lane].PRE_EMPHASIS) {
822
823 req_drv_setting_changed = true;
824 break;
825 }
826 }
827
828 if (req_drv_setting_changed) {
829 update_drive_settings(
9a6a8075 830 lt_settings, req_settings);
4562236b 831
d0778ebf 832 dc_link_dp_set_drive_settings(link,
4562236b
HW		 833 lt_settings);
834 break;
835 }
836
837 msleep(1);
838 }
839
840 if (!req_drv_setting_changed) {
1296423b 841 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
4562236b
HW		 842 __func__);
843
844 ASSERT(0);
845 return true;
846 }
847 }
1296423b 848 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
4562236b
HW		 849 __func__);
850
851 ASSERT(0);
852 return true;
853
854}
855
64c12b73 856/* Only used for channel equalization */
857static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
858{
859 unsigned int aux_rd_interval_us = 400;
860
861 switch (dpcd_aux_read_interval) {
862 case 0x01:
863 aux_rd_interval_us = 400;
864 break;
865 case 0x02:
866 aux_rd_interval_us = 4000;
867 break;
868 case 0x03:
869 aux_rd_interval_us = 8000;
870 break;
871 case 0x04:
872 aux_rd_interval_us = 16000;
873 break;
874 default:
875 break;
876 }
877
878 return aux_rd_interval_us;
879}
880
94405cf6
WL		 881static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
882 union lane_status *dpcd_lane_status)
883{
884 enum link_training_result result = LINK_TRAINING_SUCCESS;
885
886 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
887 result = LINK_TRAINING_CR_FAIL_LANE0;
888 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
889 result = LINK_TRAINING_CR_FAIL_LANE1;
890 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
891 result = LINK_TRAINING_CR_FAIL_LANE23;
892 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
893 result = LINK_TRAINING_CR_FAIL_LANE23;
894 return result;
895}
896
820e3935 897static enum link_training_result perform_channel_equalization_sequence(
d0778ebf 898 struct dc_link *link,
64c12b73 899 struct link_training_settings *lt_settings,
900 uint32_t offset)
4562236b
HW		 901{
902 struct link_training_settings req_settings;
e0a6440a 903 enum dc_dp_training_pattern tr_pattern;
4562236b 904 uint32_t retries_ch_eq;
64c12b73 905 uint32_t wait_time_microsec;
4562236b 906 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
9a6a8075
HW		 907 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
908 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
4562236b 909
64c12b73 910 /* Note: also check that TPS4 is a supported feature*/
911
e0a6440a 912 tr_pattern = lt_settings->pattern_for_eq;
4562236b 913
64c12b73 914 if (is_repeater(link, offset))
915 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
916
917 dp_set_hw_training_pattern(link, tr_pattern, offset);
4562236b
HW		 918
919 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
920 retries_ch_eq++) {
921
64c12b73 922 dp_set_hw_lane_settings(link, lt_settings, offset);
4562236b
HW		 923
924 /* 2. update DPCD*/
925 if (!retries_ch_eq)
926 /* EPR #361076 - write as a 5-byte burst,
64c12b73 927 * but only for the 1-st iteration
928 */
929
4562236b
HW		 930 dpcd_set_lt_pattern_and_lane_settings(
931 link,
932 lt_settings,
64c12b73 933 tr_pattern, offset);
4562236b 934 else
64c12b73 935 dpcd_set_lane_settings(link, lt_settings, offset);
4562236b
HW		 936
937 /* 3. wait for receiver to lock-on*/
64c12b73 938 wait_time_microsec = lt_settings->eq_pattern_time;
939
5fd21b39 940 if (is_repeater(link, offset))
64c12b73 941 wait_time_microsec =
942 translate_training_aux_read_interval(
5fd21b39 943 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
64c12b73 944
945 wait_for_training_aux_rd_interval(
946 link,
947 wait_time_microsec);
4562236b
HW		 948
949 /* 4. Read lane status and requested
950 * drive settings as set by the sink*/
951
952 get_lane_status_and_drive_settings(
953 link,
954 lt_settings,
955 dpcd_lane_status,
956 &dpcd_lane_status_updated,
64c12b73 957 &req_settings,
958 offset);
4562236b
HW		 959
960 /* 5. check CR done*/
961 if (!is_cr_done(lane_count, dpcd_lane_status))
820e3935 962 return LINK_TRAINING_EQ_FAIL_CR;
4562236b
HW		 963
964 /* 6. check CHEQ done*/
965 if (is_ch_eq_done(lane_count,
966 dpcd_lane_status,
967 &dpcd_lane_status_updated))
820e3935 968 return LINK_TRAINING_SUCCESS;
4562236b
HW		 969
970 /* 7. update VS/PE/PC2 in lt_settings*/
971 update_drive_settings(lt_settings, req_settings);
972 }
973
820e3935 974 return LINK_TRAINING_EQ_FAIL_EQ;
4562236b
HW		 975
976}
64c12b73 977#define TRAINING_AUX_RD_INTERVAL 100 //us
4562236b 978
b01f22ec
DG		 979static void start_clock_recovery_pattern_early(struct dc_link *link,
980 struct link_training_settings *lt_settings,
981 uint32_t offset)
982{
983 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
984 __func__);
ce17ce17 985 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
b01f22ec
DG		 986 dp_set_hw_lane_settings(link, lt_settings, offset);
987 udelay(400);
988}
989
94405cf6 990static enum link_training_result perform_clock_recovery_sequence(
d0778ebf 991 struct dc_link *link,
64c12b73 992 struct link_training_settings *lt_settings,
993 uint32_t offset)
4562236b
HW		 994{
995 uint32_t retries_cr;
996 uint32_t retry_count;
64c12b73 997 uint32_t wait_time_microsec;
4562236b 998 struct link_training_settings req_settings;
e0a6440a 999 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
4562236b
HW		 1000 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1001 union lane_align_status_updated dpcd_lane_status_updated;
1002
1003 retries_cr = 0;
1004 retry_count = 0;
4562236b 1005
82054678 1006 if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
ce17ce17 1007 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
4562236b
HW		 1008
1009 /* najeeb - The synaptics MST hub can put the LT in
1010 * infinite loop by switching the VS
1011 */
1012 /* between level 0 and level 1 continuously, here
1013 * we try for CR lock for LinkTrainingMaxCRRetry count*/
1014 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
e0a6440a 1015 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
4562236b
HW		 1016
1017 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1018 memset(&dpcd_lane_status_updated, '\0',
1019 sizeof(dpcd_lane_status_updated));
1020
1021 /* 1. call HWSS to set lane settings*/
1022 dp_set_hw_lane_settings(
1023 link,
64c12b73 1024 lt_settings,
1025 offset);
4562236b
HW		 1026
1027 /* 2. update DPCD of the receiver*/
50d2c602 1028 if (!retry_count)
4562236b
HW		 1029 /* EPR #361076 - write as a 5-byte burst,
1030 * but only for the 1-st iteration.*/
1031 dpcd_set_lt_pattern_and_lane_settings(
1032 link,
1033 lt_settings,
ce17ce17 1034 lt_settings->pattern_for_cr,
64c12b73 1035 offset);
4562236b
HW		 1036 else
1037 dpcd_set_lane_settings(
1038 link,
64c12b73 1039 lt_settings,
1040 offset);
4562236b
HW		 1041
1042 /* 3. wait receiver to lock-on*/
64c12b73 1043 wait_time_microsec = lt_settings->cr_pattern_time;
1044
c797ede0 1045 if (link->lttpr_non_transparent_mode)
64c12b73 1046 wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1047
4562236b
HW		 1048 wait_for_training_aux_rd_interval(
1049 link,
64c12b73 1050 wait_time_microsec);
4562236b
HW		 1051
1052 /* 4. Read lane status and requested drive
1053 * settings as set by the sink
1054 */
1055 get_lane_status_and_drive_settings(
1056 link,
1057 lt_settings,
1058 dpcd_lane_status,
1059 &dpcd_lane_status_updated,
64c12b73 1060 &req_settings,
1061 offset);
4562236b
HW		 1062
1063 /* 5. check CR done*/
1064 if (is_cr_done(lane_count, dpcd_lane_status))
94405cf6 1065 return LINK_TRAINING_SUCCESS;
4562236b
HW		 1066
1067 /* 6. max VS reached*/
1068 if (is_max_vs_reached(lt_settings))
94405cf6 1069 break;
4562236b
HW		 1070
1071 /* 7. same voltage*/
1072 /* Note: VS same for all lanes,
1073 * so comparing first lane is sufficient*/
1074 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
1075 req_settings.lane_settings[0].VOLTAGE_SWING)
1076 retries_cr++;
1077 else
1078 retries_cr = 0;
1079
1080 /* 8. update VS/PE/PC2 in lt_settings*/
1081 update_drive_settings(lt_settings, req_settings);
1082
1083 retry_count++;
1084 }
1085
1086 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1087 ASSERT(0);
1296423b 1088 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
4f42a2dd 1089 __func__,
4562236b
HW		 1090 LINK_TRAINING_MAX_CR_RETRY);
1091
1092 }
1093
94405cf6 1094 return get_cr_failure(lane_count, dpcd_lane_status);
4562236b
HW		 1095}
1096
94405cf6 1097static inline enum link_training_result perform_link_training_int(
d0778ebf 1098 struct dc_link *link,
4562236b 1099 struct link_training_settings *lt_settings,
94405cf6 1100 enum link_training_result status)
4562236b
HW		 1101{
1102 union lane_count_set lane_count_set = { {0} };
1103 union dpcd_training_pattern dpcd_pattern = { {0} };
1104
1105 /* 3. set training not in progress*/
1106 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1107 dpcd_set_training_pattern(link, dpcd_pattern);
1108
1109 /* 4. mainlink output idle pattern*/
1110 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1111
1112 /*
1113 * 5. post training adjust if required
1114 * If the upstream DPTX and downstream DPRX both support TPS4,
1115 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1116 */
c30267f5 1117 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
ce17ce17 1118 lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4)
4562236b
HW		 1119 return status;
1120
94405cf6 1121 if (status == LINK_TRAINING_SUCCESS &&
4562236b 1122 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
94405cf6 1123 status = LINK_TRAINING_LQA_FAIL;
4562236b
HW		 1124
1125 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
e0a6440a 1126 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
4562236b
HW		 1127 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1128
1129 core_link_write_dpcd(
1130 link,
3a340294 1131 DP_LANE_COUNT_SET,
4562236b
HW		 1132 &lane_count_set.raw,
1133 sizeof(lane_count_set));
1134
1135 return status;
1136}
1137
b246f90a
MT		 1138static enum link_training_result check_link_loss_status(
1139 struct dc_link *link,
1140 const struct link_training_settings *link_training_setting)
1141{
1142 enum link_training_result status = LINK_TRAINING_SUCCESS;
b246f90a 1143 union lane_status lane_status;
d9b91b1e 1144 uint8_t dpcd_buf[6] = {0};
b246f90a
MT		 1145 uint32_t lane;
1146
1147 core_link_read_dpcd(
d9b91b1e
AC		 1148 link,
1149 DP_SINK_COUNT,
1150 (uint8_t *)(dpcd_buf),
1151 sizeof(dpcd_buf));
b246f90a
MT		 1152
1153 /*parse lane status*/
1154 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1155 /*
1156 * check lanes status
1157 */
d9b91b1e 1158 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
b246f90a
MT		 1159
1160 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1161 !lane_status.bits.CR_DONE_0 ||
1162 !lane_status.bits.SYMBOL_LOCKED_0) {
1163 /* if one of the channel equalization, clock
1164 * recovery or symbol lock is dropped
1165 * consider it as (link has been
1166 * dropped) dp sink status has changed
1167 */
1168 status = LINK_TRAINING_LINK_LOSS;
1169 break;
1170 }
1171 }
1172
1173 return status;
1174}
1175
e0a6440a
DG		 1176static void initialize_training_settings(
1177 struct dc_link *link,
4562236b 1178 const struct dc_link_settings *link_setting,
0b226322 1179 const struct dc_link_training_overrides *overrides,
e0a6440a 1180 struct link_training_settings *lt_settings)
4562236b 1181{
e0a6440a 1182 uint32_t lane;
4562236b 1183
e0a6440a 1184 memset(lt_settings, '\0', sizeof(struct link_training_settings));
94405cf6 1185
e0a6440a
DG		 1186 /* Initialize link settings */
1187 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1188 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
4562236b 1189
e0a6440a
DG		 1190 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1191 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1192 else
1193 lt_settings->link_settings.link_rate = link_setting->link_rate;
4562236b 1194
e0a6440a
DG		 1195 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1196 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1197 else
1198 lt_settings->link_settings.lane_count = link_setting->lane_count;
4562236b
HW		 1199
1200 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1201
1202 /* TODO hard coded to SS for now
1203 * lt_settings.link_settings.link_spread =
1204 * dal_display_path_is_ss_supported(
1205 * path_mode->display_path) ?
1206 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1207 * LINK_SPREAD_DISABLED;
1208 */
e0a6440a 1209 /* Initialize link spread */
ad830e7a 1210 if (link->dp_ss_off)
e0a6440a 1211 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
0b226322 1212 else if (overrides->downspread != NULL)
e0a6440a 1213 lt_settings->link_settings.link_spread
0b226322 1214 = *overrides->downspread
e0a6440a
DG		 1215 ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1216 : LINK_SPREAD_DISABLED;
ad830e7a 1217 else
e0a6440a 1218 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
4562236b 1219
e0a6440a 1220 /* Initialize lane settings overrides */
0b226322
DG		 1221 if (overrides->voltage_swing != NULL)
1222 lt_settings->voltage_swing = overrides->voltage_swing;
4562236b 1223
0b226322
DG		 1224 if (overrides->pre_emphasis != NULL)
1225 lt_settings->pre_emphasis = overrides->pre_emphasis;
4562236b 1226
0b226322
DG		 1227 if (overrides->post_cursor2 != NULL)
1228 lt_settings->post_cursor2 = overrides->post_cursor2;
e0a6440a
DG		 1229
1230 /* Initialize lane settings (VS/PE/PC2) */
1231 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1232 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1233 lt_settings->voltage_swing != NULL ?
1234 *lt_settings->voltage_swing :
1235 VOLTAGE_SWING_LEVEL0;
1236 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1237 lt_settings->pre_emphasis != NULL ?
1238 *lt_settings->pre_emphasis
1239 : PRE_EMPHASIS_DISABLED;
1240 lt_settings->lane_settings[lane].POST_CURSOR2 =
1241 lt_settings->post_cursor2 != NULL ?
1242 *lt_settings->post_cursor2
1243 : POST_CURSOR2_DISABLED;
820e3935 1244 }
4562236b 1245
e0a6440a 1246 /* Initialize training timings */
0b226322
DG		 1247 if (overrides->cr_pattern_time != NULL)
1248 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
e0a6440a 1249 else
3fb068c3 1250 lt_settings->cr_pattern_time = 100;
e0a6440a 1251
0b226322
DG		 1252 if (overrides->eq_pattern_time != NULL)
1253 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
e0a6440a 1254 else
3fb068c3 1255 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
e0a6440a 1256
ce17ce17
WL		 1257 if (overrides->pattern_for_cr != NULL)
1258 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1259 else
1260 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
0b226322
DG		 1261 if (overrides->pattern_for_eq != NULL)
1262 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
e0a6440a 1263 else
ce17ce17 1264 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
e0a6440a 1265
0b226322
DG		 1266 if (overrides->enhanced_framing != NULL)
1267 lt_settings->enhanced_framing = *overrides->enhanced_framing;
e0a6440a
DG		 1268 else
1269 lt_settings->enhanced_framing = 1;
1270}
1271
64c12b73 1272static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
1273{
1274 switch (lttpr_repeater_count) {
1275 case 0x80: // 1 lttpr repeater
1276 return 1;
1277 case 0x40: // 2 lttpr repeaters
1278 return 2;
1279 case 0x20: // 3 lttpr repeaters
1280 return 3;
1281 case 0x10: // 4 lttpr repeaters
1282 return 4;
1283 case 0x08: // 5 lttpr repeaters
1284 return 5;
1285 case 0x04: // 6 lttpr repeaters
1286 return 6;
1287 case 0x02: // 7 lttpr repeaters
1288 return 7;
1289 case 0x01: // 8 lttpr repeaters
1290 return 8;
1291 default:
1292 break;
1293 }
1294 return 0; // invalid value
1295}
1296
bad7ab0b 1297static void configure_lttpr_mode(struct dc_link *link)
1298{
1299 /* aux timeout is already set to extended */
1300 /* RESET/SET lttpr mode to enable non transparent mode */
64c12b73 1301 uint8_t repeater_cnt;
1302 uint32_t aux_interval_address;
1303 uint8_t repeater_id;
a166f86e 1304 enum dc_status result = DC_ERROR_UNEXPECTED;
61aa7a6f 1305 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
bad7ab0b 1306
c14f2507 1307 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
a166f86e 1308 result = core_link_write_dpcd(link,
bad7ab0b 1309 DP_PHY_REPEATER_MODE,
1310 (uint8_t *)&repeater_mode,
1311 sizeof(repeater_mode));
1312
a166f86e 1313 if (result == DC_OK) {
1314 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1315 }
1316
c797ede0 1317 if (link->lttpr_non_transparent_mode) {
460adc6b 1318
c14f2507 1319 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
460adc6b 1320
61aa7a6f 1321 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
a166f86e 1322 result = core_link_write_dpcd(link,
bad7ab0b 1323 DP_PHY_REPEATER_MODE,
1324 (uint8_t *)&repeater_mode,
1325 sizeof(repeater_mode));
64c12b73 1326
a166f86e 1327 if (result == DC_OK) {
1328 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1329 }
1330
64c12b73 1331 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1332 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1333 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1334 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1335 core_link_read_dpcd(
1336 link,
1337 aux_interval_address,
1338 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1339 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1340 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1341 }
bad7ab0b 1342 }
1343}
1344
64c12b73 1345static void repeater_training_done(struct dc_link *link, uint32_t offset)
1346{
1347 union dpcd_training_pattern dpcd_pattern = { {0} };
1348
1349 const uint32_t dpcd_base_lt_offset =
1350 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1351 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1352 /* Set training not in progress*/
1353 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1354
1355 core_link_write_dpcd(
1356 link,
1357 dpcd_base_lt_offset,
1358 &dpcd_pattern.raw,
1359 1);
1360
460adc6b 1361 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
64c12b73 1362 __func__,
460adc6b 1363 offset,
64c12b73 1364 dpcd_base_lt_offset,
1365 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1366}
1367
e0a6440a
DG		 1368static void print_status_message(
1369 struct dc_link *link,
1370 const struct link_training_settings *lt_settings,
1371 enum link_training_result status)
1372{
1373 char *link_rate = "Unknown";
1374 char *lt_result = "Unknown";
1375 char *lt_spread = "Disabled";
4562236b 1376
e0a6440a 1377 switch (lt_settings->link_settings.link_rate) {
4562236b
HW		 1378 case LINK_RATE_LOW:
1379 link_rate = "RBR";
1380 break;
1381 case LINK_RATE_HIGH:
1382 link_rate = "HBR";
1383 break;
1384 case LINK_RATE_HIGH2:
1385 link_rate = "HBR2";
1386 break;
1387 case LINK_RATE_RBR2:
1388 link_rate = "RBR2";
1389 break;
1390 case LINK_RATE_HIGH3:
1391 link_rate = "HBR3";
1392 break;
1393 default:
1394 break;
1395 }
1396
94405cf6
WL		 1397 switch (status) {
1398 case LINK_TRAINING_SUCCESS:
1399 lt_result = "pass";
1400 break;
1401 case LINK_TRAINING_CR_FAIL_LANE0:
1402 lt_result = "CR failed lane0";
1403 break;
1404 case LINK_TRAINING_CR_FAIL_LANE1:
1405 lt_result = "CR failed lane1";
1406 break;
1407 case LINK_TRAINING_CR_FAIL_LANE23:
1408 lt_result = "CR failed lane23";
1409 break;
1410 case LINK_TRAINING_EQ_FAIL_CR:
1411 lt_result = "CR failed in EQ";
1412 break;
1413 case LINK_TRAINING_EQ_FAIL_EQ:
1414 lt_result = "EQ failed";
1415 break;
1416 case LINK_TRAINING_LQA_FAIL:
1417 lt_result = "LQA failed";
1418 break;
b246f90a
MT		 1419 case LINK_TRAINING_LINK_LOSS:
1420 lt_result = "Link loss";
1421 break;
94405cf6
WL		 1422 default:
1423 break;
1424 }
1425
e0a6440a
DG		 1426 switch (lt_settings->link_settings.link_spread) {
1427 case LINK_SPREAD_DISABLED:
1428 lt_spread = "Disabled";
1429 break;
1430 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1431 lt_spread = "0.5% 30KHz";
1432 break;
1433 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1434 lt_spread = "0.5% 33KHz";
1435 break;
1436 default:
1437 break;
1438 }
1439
4562236b 1440 /* Connectivity log: link training */
e0a6440a
DG		 1441 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1442 link_rate,
1443 lt_settings->link_settings.lane_count,
1444 lt_result,
1445 lt_settings->lane_settings[0].VOLTAGE_SWING,
1446 lt_settings->lane_settings[0].PRE_EMPHASIS,
1447 lt_spread);
1448}
1449
64c12b73 1450void dc_link_dp_set_drive_settings(
1451 struct dc_link *link,
1452 struct link_training_settings *lt_settings)
1453{
1454 /* program ASIC PHY settings*/
1455 dp_set_hw_lane_settings(link, lt_settings, DPRX);
1456
1457 /* Notify DP sink the PHY settings from source */
1458 dpcd_set_lane_settings(link, lt_settings, DPRX);
1459}
1460
e0a6440a
DG		 1461bool dc_link_dp_perform_link_training_skip_aux(
1462 struct dc_link *link,
1463 const struct dc_link_settings *link_setting)
1464{
1465 struct link_training_settings lt_settings;
e0a6440a 1466
0b226322
DG		 1467 initialize_training_settings(
1468 link,
1469 link_setting,
1470 &link->preferred_training_settings,
1471 &lt_settings);
e0a6440a
DG		 1472
1473 /* 1. Perform_clock_recovery_sequence. */
1474
1475 /* transmit training pattern for clock recovery */
ce17ce17 1476 dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
e0a6440a
DG		 1477
1478 /* call HWSS to set lane settings*/
64c12b73 1479 dp_set_hw_lane_settings(link, &lt_settings, DPRX);
e0a6440a
DG		 1480
1481 /* wait receiver to lock-on*/
1482 wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1483
1484 /* 2. Perform_channel_equalization_sequence. */
1485
1486 /* transmit training pattern for channel equalization. */
64c12b73 1487 dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
e0a6440a
DG		 1488
1489 /* call HWSS to set lane settings*/
64c12b73 1490 dp_set_hw_lane_settings(link, &lt_settings, DPRX);
e0a6440a
DG		 1491
1492 /* wait receiver to lock-on. */
1493 wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1494
1495 /* 3. Perform_link_training_int. */
1496
1497 /* Mainlink output idle pattern. */
1498 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1499
1500 print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1501
1502 return true;
1503}
1504
1505enum link_training_result dc_link_dp_perform_link_training(
1506 struct dc_link *link,
1507 const struct dc_link_settings *link_setting,
1508 bool skip_video_pattern)
1509{
1510 enum link_training_result status = LINK_TRAINING_SUCCESS;
e0a6440a 1511 struct link_training_settings lt_settings;
64c12b73 1512
008a4016 1513 bool fec_enable;
64c12b73 1514 uint8_t repeater_cnt;
1515 uint8_t repeater_id;
e0a6440a 1516
0b226322
DG		 1517 initialize_training_settings(
1518 link,
1519 link_setting,
1520 &link->preferred_training_settings,
1521 &lt_settings);
e0a6440a 1522
bcc5042a 1523 /* Configure lttpr mode */
c797ede0 1524 if (link->lttpr_non_transparent_mode)
bcc5042a 1525 configure_lttpr_mode(link);
1526
82054678
ML		 1527 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1528 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
834a9a9f
ML		 1529
1530 /* 1. set link rate, lane count and spread. */
1531 dpcd_set_link_settings(link, &lt_settings);
e0a6440a 1532
008a4016
NC		 1533 if (link->preferred_training_settings.fec_enable != NULL)
1534 fec_enable = *link->preferred_training_settings.fec_enable;
1535 else
1536 fec_enable = true;
1537
1538 dp_set_fec_ready(link, fec_enable);
008a4016 1539
c797ede0 1540 if (link->lttpr_non_transparent_mode) {
008a4016 1541
64c12b73 1542 /* 2. perform link training (set link training done
1543 * to false is done as well)
1544 */
1545 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1546
1547 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1548 repeater_id--) {
1549 status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
1550
1551 if (status != LINK_TRAINING_SUCCESS)
1552 break;
1553
1554 status = perform_channel_equalization_sequence(link,
1555 &lt_settings,
1556 repeater_id);
1557
1558 if (status != LINK_TRAINING_SUCCESS)
1559 break;
1560
1561 repeater_training_done(link, repeater_id);
1562 }
1563 }
1564
1565 if (status == LINK_TRAINING_SUCCESS) {
1566 status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
e0a6440a
DG		 1567 if (status == LINK_TRAINING_SUCCESS) {
1568 status = perform_channel_equalization_sequence(link,
64c12b73 1569 &lt_settings,
1570 DPRX);
1571 }
e0a6440a
DG		 1572 }
1573
1574 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1575 status = perform_link_training_int(link,
1576 &lt_settings,
1577 status);
1578 }
1579
b246f90a
MT		 1580 /* delay 5ms after Main Link output idle pattern and then check
1581 * DPCD 0202h.
1582 */
1583 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1584 msleep(5);
1585 status = check_link_loss_status(link, &lt_settings);
1586 }
1587
e0a6440a
DG		 1588 /* 6. print status message*/
1589 print_status_message(link, &lt_settings, status);
4562236b 1590
d6e75df4 1591 if (status != LINK_TRAINING_SUCCESS)
cfd84fd3 1592 link->ctx->dc->debug_data.ltFailCount++;
d6e75df4 1593
4562236b
HW		 1594 return status;
1595}
1596
4562236b 1597bool perform_link_training_with_retries(
4562236b
HW		 1598 const struct dc_link_settings *link_setting,
1599 bool skip_video_pattern,
832aa63b
PH		 1600 int attempts,
1601 struct pipe_ctx *pipe_ctx,
1602 enum signal_type signal)
4562236b
HW		 1603{
1604 uint8_t j;
1605 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
832aa63b
PH		 1606 struct dc_stream_state *stream = pipe_ctx->stream;
1607 struct dc_link *link = stream->link;
1608 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
4562236b 1609
eec3303d
AC		 1610 /* We need to do this before the link training to ensure the idle pattern in SST
1611 * mode will be sent right after the link training
1612 */
1613 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
1614 pipe_ctx->stream_res.stream_enc->id, true);
1615
4562236b
HW		 1616 for (j = 0; j < attempts; ++j) {
1617
172c9b77
AT		 1618 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1619 __func__, (unsigned int)j + 1, attempts);
1620
832aa63b
PH		 1621 dp_enable_link_phy(
1622 link,
1623 signal,
1624 pipe_ctx->clock_source->id,
1625 link_setting);
1626
eec3303d
AC		 1627 if (stream->sink_patches.dppowerup_delay > 0) {
1628 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1629
832aa63b
PH		 1630 msleep(delay_dp_power_up_in_ms);
1631 }
1632
1633 dp_set_panel_mode(link, panel_mode);
1634
832aa63b
PH		 1635 if (link->aux_access_disabled) {
1636 dc_link_dp_perform_link_training_skip_aux(link, link_setting);
1637 return true;
1638 } else if (dc_link_dp_perform_link_training(
d0778ebf 1639 link,
4562236b 1640 link_setting,
820e3935 1641 skip_video_pattern) == LINK_TRAINING_SUCCESS)
4562236b
HW		 1642 return true;
1643
832aa63b
PH		 1644 /* latest link training still fail, skip delay and keep PHY on
1645 */
1646 if (j == (attempts - 1))
1647 break;
1648
172c9b77
AT		 1649 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1650 __func__, (unsigned int)j + 1, attempts);
1651
832aa63b
PH		 1652 dp_disable_link_phy(link, signal);
1653
4562236b 1654 msleep(delay_between_attempts);
832aa63b 1655
4562236b
HW		 1656 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1657 }
1658
1659 return false;
1660}
1661
0b226322
DG		 1662static enum clock_source_id get_clock_source_id(struct dc_link *link)
1663{
1664 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1665 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1666
1667 if (dp_cs != NULL) {
1668 dp_cs_id = dp_cs->id;
1669 } else {
1670 /*
1671 * dp clock source is not initialized for some reason.
1672 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1673 */
1674 ASSERT(dp_cs);
1675 }
1676
1677 return dp_cs_id;
1678}
1679
1680static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1681{
1682 if (mst_enable == false &&
1683 link->type == dc_connection_mst_branch) {
1684 /* Disable MST on link. Use only local sink. */
1685 dp_disable_link_phy_mst(link, link->connector_signal);
1686
1687 link->type = dc_connection_single;
1688 link->local_sink = link->remote_sinks[0];
1689 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1690 } else if (mst_enable == true &&
1691 link->type == dc_connection_single &&
1692 link->remote_sinks[0] != NULL) {
1693 /* Re-enable MST on link. */
1694 dp_disable_link_phy(link, link->connector_signal);
1695 dp_enable_mst_on_sink(link, true);
1696
1697 link->type = dc_connection_mst_branch;
1698 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1699 }
1700}
1701
1702bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1703{
1704 /* Begin Sync LT. During this time,
1705 * DPCD:600h must not be powered down.
1706 */
1707 link->sync_lt_in_progress = true;
1708
1709 /*Clear any existing preferred settings.*/
1710 memset(&link->preferred_training_settings, 0,
1711 sizeof(struct dc_link_training_overrides));
1712 memset(&link->preferred_link_setting, 0,
1713 sizeof(struct dc_link_settings));
1714
1715 return true;
1716}
1717
1718enum link_training_result dc_link_dp_sync_lt_attempt(
1719 struct dc_link *link,
1720 struct dc_link_settings *link_settings,
1721 struct dc_link_training_overrides *lt_overrides)
1722{
1723 struct link_training_settings lt_settings;
1724 enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1725 enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1726 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
0b226322 1727 bool fec_enable = false;
0b226322
DG		 1728
1729 initialize_training_settings(
1730 link,
1731 link_settings,
1732 lt_overrides,
1733 &lt_settings);
1734
1735 /* Setup MST Mode */
1736 if (lt_overrides->mst_enable)
1737 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1738
1739 /* Disable link */
1740 dp_disable_link_phy(link, link->connector_signal);
1741
1742 /* Enable link */
1743 dp_cs_id = get_clock_source_id(link);
1744 dp_enable_link_phy(link, link->connector_signal,
1745 dp_cs_id, link_settings);
1746
0b226322
DG		 1747 /* Set FEC enable */
1748 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1749 dp_set_fec_ready(link, fec_enable);
0b226322
DG		 1750
1751 if (lt_overrides->alternate_scrambler_reset) {
1752 if (*lt_overrides->alternate_scrambler_reset)
1753 panel_mode = DP_PANEL_MODE_EDP;
1754 else
1755 panel_mode = DP_PANEL_MODE_DEFAULT;
1756 } else
1757 panel_mode = dp_get_panel_mode(link);
1758
1759 dp_set_panel_mode(link, panel_mode);
1760
1761 /* Attempt to train with given link training settings */
82054678
ML		 1762 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1763 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
834a9a9f
ML		 1764
1765 /* Set link rate, lane count and spread. */
1766 dpcd_set_link_settings(link, &lt_settings);
0b226322
DG		 1767
1768 /* 2. perform link training (set link training done
1769 * to false is done as well)
1770 */
64c12b73 1771 lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
0b226322
DG		 1772 if (lt_status == LINK_TRAINING_SUCCESS) {
1773 lt_status = perform_channel_equalization_sequence(link,
64c12b73 1774 &lt_settings,
1775 DPRX);
0b226322
DG		 1776 }
1777
1778 /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1779 /* 4. print status message*/
1780 print_status_message(link, &lt_settings, lt_status);
1781
1782 return lt_status;
1783}
1784
1785bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1786{
1787 /* If input parameter is set, shut down phy.
1788 * Still shouldn't turn off dp_receiver (DPCD:600h)
1789 */
1790 if (link_down == true) {
1791 dp_disable_link_phy(link, link->connector_signal);
0b226322 1792 dp_set_fec_ready(link, false);
0b226322
DG		 1793 }
1794
1795 link->sync_lt_in_progress = false;
1796 return true;
1797}
1798
d0778ebf 1799static struct dc_link_settings get_max_link_cap(struct dc_link *link)
4562236b 1800{
8ccf0e20 1801 struct dc_link_settings max_link_cap = {0};
4562236b 1802
8ccf0e20
WL		 1803 /* get max link encoder capability */
1804 link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
f537d474 1805
4562236b 1806 /* Lower link settings based on sink's link cap */
d0778ebf 1807 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
4562236b 1808 max_link_cap.lane_count =
d0778ebf
HW		 1809 link->reported_link_cap.lane_count;
1810 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
4562236b 1811 max_link_cap.link_rate =
d0778ebf
HW		 1812 link->reported_link_cap.link_rate;
1813 if (link->reported_link_cap.link_spread <
4562236b
HW		 1814 max_link_cap.link_spread)
1815 max_link_cap.link_spread =
d0778ebf 1816 link->reported_link_cap.link_spread;
bad7ab0b 1817 /*
1818 * account for lttpr repeaters cap
1819 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1820 */
c797ede0 1821 if (link->lttpr_non_transparent_mode) {
bad7ab0b 1822 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1823 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1824
1825 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1826 max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
460adc6b 1827
1828 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
1829 __func__,
1830 max_link_cap.lane_count,
1831 max_link_cap.link_rate);
bad7ab0b 1832 }
4562236b
HW		 1833 return max_link_cap;
1834}
1835
1ae62f31
WL		 1836static enum dc_status read_hpd_rx_irq_data(
1837 struct dc_link *link,
1838 union hpd_irq_data *irq_data)
1839{
1840 static enum dc_status retval;
1841
1842 /* The HW reads 16 bytes from 200h on HPD,
1843 * but if we get an AUX_DEFER, the HW cannot retry
1844 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1845 * fail, so we now explicitly read 6 bytes which is
1846 * the req from the above mentioned test cases.
1847 *
1848 * For DP 1.4 we need to read those from 2002h range.
1849 */
1850 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1851 retval = core_link_read_dpcd(
1852 link,
1853 DP_SINK_COUNT,
1854 irq_data->raw,
1855 sizeof(union hpd_irq_data));
1856 else {
1857 /* Read 14 bytes in a single read and then copy only the required fields.
1858 * This is more efficient than doing it in two separate AUX reads. */
1859
1860 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1861
1862 retval = core_link_read_dpcd(
1863 link,
1864 DP_SINK_COUNT_ESI,
1865 tmp,
1866 sizeof(tmp));
1867
1868 if (retval != DC_OK)
1869 return retval;
1870
1871 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1872 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1873 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1874 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1875 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1876 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1877 }
1878
1879 return retval;
1880}
1881
1882static bool hpd_rx_irq_check_link_loss_status(
1883 struct dc_link *link,
1884 union hpd_irq_data *hpd_irq_dpcd_data)
1885{
1886 uint8_t irq_reg_rx_power_state = 0;
1887 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1888 union lane_status lane_status;
1889 uint32_t lane;
1890 bool sink_status_changed;
1891 bool return_code;
1892
1893 sink_status_changed = false;
1894 return_code = false;
1895
1896 if (link->cur_link_settings.lane_count == 0)
1897 return return_code;
1898
1899 /*1. Check that Link Status changed, before re-training.*/
1900
1901 /*parse lane status*/
1902 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1903 /* check status of lanes 0,1
1904 * changed DpcdAddress_Lane01Status (0x202)
1905 */
1906 lane_status.raw = get_nibble_at_index(
1907 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1908 lane);
1909
1910 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1911 !lane_status.bits.CR_DONE_0 ||
1912 !lane_status.bits.SYMBOL_LOCKED_0) {
1913 /* if one of the channel equalization, clock
1914 * recovery or symbol lock is dropped
1915 * consider it as (link has been
1916 * dropped) dp sink status has changed
1917 */
1918 sink_status_changed = true;
1919 break;
1920 }
1921 }
1922
1923 /* Check interlane align.*/
1924 if (sink_status_changed ||
1925 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1926
1927 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1928
1929 return_code = true;
1930
1931 /*2. Check that we can handle interrupt: Not in FS DOS,
1932 * Not in "Display Timeout" state, Link is trained.
1933 */
1934 dpcd_result = core_link_read_dpcd(link,
1935 DP_SET_POWER,
1936 &irq_reg_rx_power_state,
1937 sizeof(irq_reg_rx_power_state));
1938
1939 if (dpcd_result != DC_OK) {
1940 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1941 __func__);
1942 } else {
1943 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1944 return_code = false;
1945 }
1946 }
1947
1948 return return_code;
1949}
1950
aafded88 1951bool dp_verify_link_cap(
d0778ebf 1952 struct dc_link *link,
824474ba
BL		 1953 struct dc_link_settings *known_limit_link_setting,
1954 int *fail_count)
4562236b
HW		 1955{
1956 struct dc_link_settings max_link_cap = {0};
820e3935
DW		 1957 struct dc_link_settings cur_link_setting = {0};
1958 struct dc_link_settings *cur = &cur_link_setting;
1959 struct dc_link_settings initial_link_settings = {0};
4562236b
HW		 1960 bool success;
1961 bool skip_link_training;
4562236b 1962 bool skip_video_pattern;
4562236b 1963 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
820e3935 1964 enum link_training_result status;
1ae62f31 1965 union hpd_irq_data irq_data;
4562236b 1966
aafded88
TC		 1967 if (link->dc->debug.skip_detection_link_training) {
1968 link->verified_link_cap = *known_limit_link_setting;
1969 return true;
1970 }
1971
1ae62f31 1972 memset(&irq_data, 0, sizeof(irq_data));
4562236b
HW		 1973 success = false;
1974 skip_link_training = false;
1975
1976 max_link_cap = get_max_link_cap(link);
1977
bad7ab0b 1978 /* Grant extended timeout request */
c797ede0 1979 if (link->lttpr_non_transparent_mode && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
bad7ab0b 1980 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
1981
1982 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
1983 }
1984
4562236b
HW		 1985 /* TODO implement override and monitor patch later */
1986
1987 /* try to train the link from high to low to
1988 * find the physical link capability
1989 */
1990 /* disable PHY done possible by BIOS, will be done by driver itself */
d0778ebf 1991 dp_disable_link_phy(link, link->connector_signal);
4562236b 1992
b3282738
GS		 1993 dp_cs_id = get_clock_source_id(link);
1994
1995 /* link training starts with the maximum common settings
1996 * supported by both sink and ASIC.
1997 */
1998 initial_link_settings = get_common_supported_link_settings(
1999 *known_limit_link_setting,
2000 max_link_cap);
2001 cur_link_setting = initial_link_settings;
2002
ee765924
GS		 2003 /* Temporary Renoir-specific workaround for SWDEV-215184;
2004 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2005 * so add extra cycle of enabling and disabling the PHY before first link training.
2006 */
2007 if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2008 link->dc->debug.usbc_combo_phy_reset_wa) {
2009 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2010 dp_disable_link_phy(link, link->connector_signal);
2011 }
2012
820e3935 2013 do {
4562236b 2014 skip_video_pattern = true;
820e3935 2015
4562236b
HW		 2016 if (cur->link_rate == LINK_RATE_LOW)
2017 skip_video_pattern = false;
2018
2019 dp_enable_link_phy(
2020 link,
d0778ebf 2021 link->connector_signal,
4562236b
HW		 2022 dp_cs_id,
2023 cur);
2024
94405cf6 2025
4562236b
HW		 2026 if (skip_link_training)
2027 success = true;
2028 else {
820e3935 2029 status = dc_link_dp_perform_link_training(
d0778ebf 2030 link,
4562236b
HW		 2031 cur,
2032 skip_video_pattern);
820e3935
DW		 2033 if (status == LINK_TRAINING_SUCCESS)
2034 success = true;
824474ba
BL		 2035 else
2036 (*fail_count)++;
4562236b
HW		 2037 }
2038
1ae62f31 2039 if (success) {
d0778ebf 2040 link->verified_link_cap = *cur;
1ae62f31
WL		 2041 udelay(1000);
2042 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2043 if (hpd_rx_irq_check_link_loss_status(
2044 link,
2045 &irq_data))
2046 (*fail_count)++;
2047 }
4562236b
HW		 2048 /* always disable the link before trying another
2049 * setting or before returning we'll enable it later
2050 * based on the actual mode we're driving
2051 */
d0778ebf 2052 dp_disable_link_phy(link, link->connector_signal);
820e3935
DW		 2053 } while (!success && decide_fallback_link_setting(
2054 initial_link_settings, cur, status));
4562236b
HW		 2055
2056 /* Link Training failed for all Link Settings
2057 * (Lane Count is still unknown)
2058 */
2059 if (!success) {
2060 /* If all LT fails for all settings,
2061 * set verified = failed safe (1 lane low)
2062 */
d0778ebf
HW		 2063 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2064 link->verified_link_cap.link_rate = LINK_RATE_LOW;
4562236b 2065
d0778ebf 2066 link->verified_link_cap.link_spread =
4562236b
HW		 2067 LINK_SPREAD_DISABLED;
2068 }
2069
4562236b
HW		 2070
2071 return success;
2072}
2073
e7f2c80c
WL		 2074bool dp_verify_link_cap_with_retries(
2075 struct dc_link *link,
2076 struct dc_link_settings *known_limit_link_setting,
2077 int attempts)
2078{
2079 uint8_t i = 0;
2080 bool success = false;
2081
2082 for (i = 0; i < attempts; i++) {
2083 int fail_count = 0;
82db2e3c 2084 enum dc_connection_type type = dc_connection_none;
e7f2c80c
WL		 2085
2086 memset(&link->verified_link_cap, 0,
2087 sizeof(struct dc_link_settings));
82db2e3c
SK		 2088 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2089 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2090 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2091 link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
e7f2c80c
WL		 2092 break;
2093 } else if (dp_verify_link_cap(link,
2094 &link->reported_link_cap,
2095 &fail_count) && fail_count == 0) {
2096 success = true;
2097 break;
2098 }
2099 msleep(10);
2100 }
2101 return success;
2102}
2103
f537d474
LH		 2104bool dp_verify_mst_link_cap(
2105 struct dc_link *link)
2106{
2107 struct dc_link_settings max_link_cap = {0};
2108
2109 max_link_cap = get_max_link_cap(link);
2110 link->verified_link_cap = get_common_supported_link_settings(
2111 link->reported_link_cap,
2112 max_link_cap);
2113
2114 return true;
2115}
2116
9a6a8075 2117static struct dc_link_settings get_common_supported_link_settings(
820e3935
DW		 2118 struct dc_link_settings link_setting_a,
2119 struct dc_link_settings link_setting_b)
2120{
2121 struct dc_link_settings link_settings = {0};
2122
2123 link_settings.lane_count =
2124 (link_setting_a.lane_count <=
2125 link_setting_b.lane_count) ?
2126 link_setting_a.lane_count :
2127 link_setting_b.lane_count;
2128 link_settings.link_rate =
2129 (link_setting_a.link_rate <=
2130 link_setting_b.link_rate) ?
2131 link_setting_a.link_rate :
2132 link_setting_b.link_rate;
2133 link_settings.link_spread = LINK_SPREAD_DISABLED;
2134
2135 /* in DP compliance test, DPR-120 may have
2136 * a random value in its MAX_LINK_BW dpcd field.
2137 * We map it to the maximum supported link rate that
2138 * is smaller than MAX_LINK_BW in this case.
2139 */
2140 if (link_settings.link_rate > LINK_RATE_HIGH3) {
2141 link_settings.link_rate = LINK_RATE_HIGH3;
2142 } else if (link_settings.link_rate < LINK_RATE_HIGH3
2143 && link_settings.link_rate > LINK_RATE_HIGH2) {
2144 link_settings.link_rate = LINK_RATE_HIGH2;
2145 } else if (link_settings.link_rate < LINK_RATE_HIGH2
2146 && link_settings.link_rate > LINK_RATE_HIGH) {
2147 link_settings.link_rate = LINK_RATE_HIGH;
2148 } else if (link_settings.link_rate < LINK_RATE_HIGH
2149 && link_settings.link_rate > LINK_RATE_LOW) {
2150 link_settings.link_rate = LINK_RATE_LOW;
2151 } else if (link_settings.link_rate < LINK_RATE_LOW) {
2152 link_settings.link_rate = LINK_RATE_UNKNOWN;
2153 }
2154
2155 return link_settings;
2156}
2157
450619d3 2158static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 2159{
2160 return lane_count <= LANE_COUNT_ONE;
2161}
2162
450619d3 2163static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 2164{
2165 return link_rate <= LINK_RATE_LOW;
2166}
2167
44858055 2168static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 2169{
2170 switch (lane_count) {
2171 case LANE_COUNT_FOUR:
2172 return LANE_COUNT_TWO;
2173 case LANE_COUNT_TWO:
2174 return LANE_COUNT_ONE;
2175 case LANE_COUNT_ONE:
2176 return LANE_COUNT_UNKNOWN;
2177 default:
2178 return LANE_COUNT_UNKNOWN;
2179 }
2180}
2181
04e21292 2182static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 2183{
2184 switch (link_rate) {
2185 case LINK_RATE_HIGH3:
2186 return LINK_RATE_HIGH2;
2187 case LINK_RATE_HIGH2:
2188 return LINK_RATE_HIGH;
2189 case LINK_RATE_HIGH:
2190 return LINK_RATE_LOW;
2191 case LINK_RATE_LOW:
2192 return LINK_RATE_UNKNOWN;
2193 default:
2194 return LINK_RATE_UNKNOWN;
2195 }
2196}
2197
04e21292 2198static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
8c4abe0b
DW		 2199{
2200 switch (lane_count) {
2201 case LANE_COUNT_ONE:
2202 return LANE_COUNT_TWO;
2203 case LANE_COUNT_TWO:
2204 return LANE_COUNT_FOUR;
2205 default:
2206 return LANE_COUNT_UNKNOWN;
2207 }
2208}
2209
04e21292 2210static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
8c4abe0b
DW		 2211{
2212 switch (link_rate) {
2213 case LINK_RATE_LOW:
2214 return LINK_RATE_HIGH;
2215 case LINK_RATE_HIGH:
2216 return LINK_RATE_HIGH2;
2217 case LINK_RATE_HIGH2:
2218 return LINK_RATE_HIGH3;
2219 default:
2220 return LINK_RATE_UNKNOWN;
2221 }
2222}
2223
820e3935
DW		 2224/*
2225 * function: set link rate and lane count fallback based
2226 * on current link setting and last link training result
2227 * return value:
2228 * true - link setting could be set
2229 * false - has reached minimum setting
2230 * and no further fallback could be done
2231 */
04e21292 2232static bool decide_fallback_link_setting(
820e3935
DW		 2233 struct dc_link_settings initial_link_settings,
2234 struct dc_link_settings *current_link_setting,
2235 enum link_training_result training_result)
2236{
2237 if (!current_link_setting)
2238 return false;
2239
2240 switch (training_result) {
94405cf6
WL		 2241 case LINK_TRAINING_CR_FAIL_LANE0:
2242 case LINK_TRAINING_CR_FAIL_LANE1:
2243 case LINK_TRAINING_CR_FAIL_LANE23:
2244 case LINK_TRAINING_LQA_FAIL:
820e3935
DW		 2245 {
2246 if (!reached_minimum_link_rate
2247 (current_link_setting->link_rate)) {
2248 current_link_setting->link_rate =
2249 reduce_link_rate(
2250 current_link_setting->link_rate);
2251 } else if (!reached_minimum_lane_count
2252 (current_link_setting->lane_count)) {
2253 current_link_setting->link_rate =
2254 initial_link_settings.link_rate;
94405cf6
WL		 2255 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2256 return false;
2257 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2258 current_link_setting->lane_count =
2259 LANE_COUNT_ONE;
2260 else if (training_result ==
2261 LINK_TRAINING_CR_FAIL_LANE23)
2262 current_link_setting->lane_count =
2263 LANE_COUNT_TWO;
2264 else
2265 current_link_setting->lane_count =
2266 reduce_lane_count(
820e3935
DW		 2267 current_link_setting->lane_count);
2268 } else {
2269 return false;
2270 }
2271 break;
2272 }
2273 case LINK_TRAINING_EQ_FAIL_EQ:
2274 {
2275 if (!reached_minimum_lane_count
2276 (current_link_setting->lane_count)) {
2277 current_link_setting->lane_count =
2278 reduce_lane_count(
2279 current_link_setting->lane_count);
2280 } else if (!reached_minimum_link_rate
2281 (current_link_setting->link_rate)) {
820e3935
DW		 2282 current_link_setting->link_rate =
2283 reduce_link_rate(
2284 current_link_setting->link_rate);
2285 } else {
2286 return false;
2287 }
2288 break;
2289 }
2290 case LINK_TRAINING_EQ_FAIL_CR:
2291 {
2292 if (!reached_minimum_link_rate
2293 (current_link_setting->link_rate)) {
2294 current_link_setting->link_rate =
2295 reduce_link_rate(
2296 current_link_setting->link_rate);
2297 } else {
2298 return false;
2299 }
2300 break;
2301 }
2302 default:
2303 return false;
2304 }
2305 return true;
2306}
2307
4562236b 2308bool dp_validate_mode_timing(
d0778ebf 2309 struct dc_link *link,
4562236b
HW		 2310 const struct dc_crtc_timing *timing)
2311{
2312 uint32_t req_bw;
2313 uint32_t max_bw;
2314
2315 const struct dc_link_settings *link_setting;
2316
2317 /*always DP fail safe mode*/
380604e2 2318 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
9a6a8075
HW		 2319 timing->h_addressable == (uint32_t) 640 &&
2320 timing->v_addressable == (uint32_t) 480)
4562236b
HW		 2321 return true;
2322
5ac4619b 2323 link_setting = dc_link_get_link_cap(link);
4562236b
HW		 2324
2325 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2326 /*if (flags.DYNAMIC_VALIDATION == 1 &&
d0778ebf
HW		 2327 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2328 link_setting = &link->verified_link_cap;
4562236b
HW		 2329 */
2330
e49f6936 2331 req_bw = dc_bandwidth_in_kbps_from_timing(timing);
332c1191 2332 max_bw = dc_link_bandwidth_kbps(link, link_setting);
4562236b
HW		 2333
2334 if (req_bw <= max_bw) {
2335 /* remember the biggest mode here, during
2336 * initial link training (to get
2337 * verified_link_cap), LS sends event about
2338 * cannot train at reported cap to upper
2339 * layer and upper layer will re-enumerate modes.
2340 * this is not necessary if the lower
2341 * verified_link_cap is enough to drive
2342 * all the modes */
2343
2344 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2345 /* if (flags.DYNAMIC_VALIDATION == 1)
2346 dpsst->max_req_bw_for_verified_linkcap = dal_max(
2347 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2348 return true;
2349 } else
2350 return false;
2351}
2352
8628d02f 2353static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
4562236b 2354{
8c4abe0b 2355 struct dc_link_settings initial_link_setting = {
8628d02f 2356 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
8c4abe0b
DW		 2357 struct dc_link_settings current_link_setting =
2358 initial_link_setting;
4562236b 2359 uint32_t link_bw;
4562236b 2360
8628d02f
JP		 2361 /* search for the minimum link setting that:
2362 * 1. is supported according to the link training result
2363 * 2. could support the b/w requested by the timing
4562236b 2364 */
8628d02f
JP		 2365 while (current_link_setting.link_rate <=
2366 link->verified_link_cap.link_rate) {
332c1191
NC		 2367 link_bw = dc_link_bandwidth_kbps(
2368 link,
8628d02f
JP		 2369 &current_link_setting);
2370 if (req_bw <= link_bw) {
2371 *link_setting = current_link_setting;
2372 return true;
2373 }
4562236b 2374
8628d02f
JP		 2375 if (current_link_setting.lane_count <
2376 link->verified_link_cap.lane_count) {
2377 current_link_setting.lane_count =
2378 increase_lane_count(
2379 current_link_setting.lane_count);
2380 } else {
2381 current_link_setting.link_rate =
2382 increase_link_rate(
2383 current_link_setting.link_rate);
2384 current_link_setting.lane_count =
2385 initial_link_setting.lane_count;
2386 }
3f1f74f4
JZ		 2387 }
2388
8628d02f
JP		 2389 return false;
2390}
2391
2392static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2393{
2394 struct dc_link_settings initial_link_setting;
2395 struct dc_link_settings current_link_setting;
2396 uint32_t link_bw;
2397
2398 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
53c81fc7 2399 link->dpcd_caps.edp_supported_link_rates_count == 0) {
4d2f22d1 2400 *link_setting = link->verified_link_cap;
8628d02f 2401 return true;
4d2f22d1
HH		 2402 }
2403
8628d02f
JP		 2404 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2405 initial_link_setting.lane_count = LANE_COUNT_ONE;
2406 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2407 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2408 initial_link_setting.use_link_rate_set = true;
2409 initial_link_setting.link_rate_set = 0;
2410 current_link_setting = initial_link_setting;
2411
5667ff5c
DA		 2412 /* search for the minimum link setting that:
2413 * 1. is supported according to the link training result
2414 * 2. could support the b/w requested by the timing
2415 */
8c4abe0b 2416 while (current_link_setting.link_rate <=
4654a2f7 2417 link->verified_link_cap.link_rate) {
332c1191
NC		 2418 link_bw = dc_link_bandwidth_kbps(
2419 link,
8c4abe0b
DW		 2420 &current_link_setting);
2421 if (req_bw <= link_bw) {
2422 *link_setting = current_link_setting;
8628d02f 2423 return true;
4562236b 2424 }
4562236b 2425
8c4abe0b 2426 if (current_link_setting.lane_count <
4654a2f7 2427 link->verified_link_cap.lane_count) {
8c4abe0b
DW		 2428 current_link_setting.lane_count =
2429 increase_lane_count(
2430 current_link_setting.lane_count);
2431 } else {
8628d02f
JP		 2432 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2433 current_link_setting.link_rate_set++;
2434 current_link_setting.link_rate =
2435 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2436 current_link_setting.lane_count =
2437 initial_link_setting.lane_count;
2438 } else
2439 break;
4562236b
HW		 2440 }
2441 }
8628d02f
JP		 2442 return false;
2443}
2444
c08321cb
WL		 2445static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2446{
2447 *link_setting = link->verified_link_cap;
2448 return true;
2449}
2450
8628d02f
JP		 2451void decide_link_settings(struct dc_stream_state *stream,
2452 struct dc_link_settings *link_setting)
2453{
2454 struct dc_link *link;
2455 uint32_t req_bw;
2456
e49f6936 2457 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
8628d02f
JP		 2458
2459 link = stream->link;
2460
2461 /* if preferred is specified through AMDDP, use it, if it's enough
2462 * to drive the mode
2463 */
2464 if (link->preferred_link_setting.lane_count !=
2465 LANE_COUNT_UNKNOWN &&
2466 link->preferred_link_setting.link_rate !=
2467 LINK_RATE_UNKNOWN) {
2468 *link_setting = link->preferred_link_setting;
2469 return;
2470 }
2471
2472 /* MST doesn't perform link training for now
2473 * TODO: add MST specific link training routine
2474 */
2475 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
c08321cb
WL		 2476 if (decide_mst_link_settings(link, link_setting))
2477 return;
2478 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
8628d02f
JP		 2479 if (decide_edp_link_settings(link, link_setting, req_bw))
2480 return;
2481 } else if (decide_dp_link_settings(link, link_setting, req_bw))
2482 return;
4562236b
HW		 2483
2484 BREAK_TO_DEBUGGER();
d0778ebf 2485 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
4562236b 2486
d0778ebf 2487 *link_setting = link->verified_link_cap;
4562236b
HW		 2488}
2489
2490/*************************Short Pulse IRQ***************************/
d0778ebf 2491static bool allow_hpd_rx_irq(const struct dc_link *link)
4562236b
HW		 2492{
2493 /*
2494 * Don't handle RX IRQ unless one of following is met:
2495 * 1) The link is established (cur_link_settings != unknown)
2496 * 2) We kicked off MST detection
2497 * 3) We know we're dealing with an active dongle
2498 */
2499
d0778ebf
HW		 2500 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2501 (link->type == dc_connection_mst_branch) ||
4562236b
HW		 2502 is_dp_active_dongle(link))
2503 return true;
2504
2505 return false;
2506}
2507
ab4a4072 2508static bool handle_hpd_irq_psr_sink(struct dc_link *link)
4562236b
HW		 2509{
2510 union dpcd_psr_configuration psr_configuration;
2511
d1ebfdd8 2512 if (!link->psr_settings.psr_feature_enabled)
4562236b
HW		 2513 return false;
2514
7c7f5b15
AG		 2515 dm_helpers_dp_read_dpcd(
2516 link->ctx,
d0778ebf 2517 link,
7c7f5b15
AG		 2518 368,/*DpcdAddress_PSR_Enable_Cfg*/
2519 &psr_configuration.raw,
2520 sizeof(psr_configuration.raw));
2521
4562236b
HW		 2522
2523 if (psr_configuration.bits.ENABLE) {
2524 unsigned char dpcdbuf[3] = {0};
2525 union psr_error_status psr_error_status;
2526 union psr_sink_psr_status psr_sink_psr_status;
2527
7c7f5b15
AG		 2528 dm_helpers_dp_read_dpcd(
2529 link->ctx,
d0778ebf 2530 link,
7c7f5b15
AG		 2531 0x2006, /*DpcdAddress_PSR_Error_Status*/
2532 (unsigned char *) dpcdbuf,
2533 sizeof(dpcdbuf));
4562236b
HW		 2534
2535 /*DPCD 2006h ERROR STATUS*/
2536 psr_error_status.raw = dpcdbuf[0];
2537 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
2538 psr_sink_psr_status.raw = dpcdbuf[2];
2539
2540 if (psr_error_status.bits.LINK_CRC_ERROR ||
2541 psr_error_status.bits.RFB_STORAGE_ERROR) {
2542 /* Acknowledge and clear error bits */
7c7f5b15
AG		 2543 dm_helpers_dp_write_dpcd(
2544 link->ctx,
d0778ebf 2545 link,
7c7f5b15 2546 8198,/*DpcdAddress_PSR_Error_Status*/
4562236b
HW		 2547 &psr_error_status.raw,
2548 sizeof(psr_error_status.raw));
2549
2550 /* PSR error, disable and re-enable PSR */
ab4a4072
EY		 2551 dc_link_set_psr_allow_active(link, false, true);
2552 dc_link_set_psr_allow_active(link, true, true);
4562236b
HW		 2553
2554 return true;
2555 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2556 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2557 /* No error is detect, PSR is active.
2558 * We should return with IRQ_HPD handled without
2559 * checking for loss of sync since PSR would have
2560 * powered down main link.
2561 */
2562 return true;
2563 }
2564 }
2565 return false;
2566}
2567
d0778ebf 2568static void dp_test_send_link_training(struct dc_link *link)
4562236b 2569{
73c72602 2570 struct dc_link_settings link_settings = {0};
4562236b
HW		 2571
2572 core_link_read_dpcd(
2573 link,
3a340294 2574 DP_TEST_LANE_COUNT,
4562236b
HW		 2575 (unsigned char *)(&link_settings.lane_count),
2576 1);
2577 core_link_read_dpcd(
2578 link,
3a340294 2579 DP_TEST_LINK_RATE,
4562236b
HW		 2580 (unsigned char *)(&link_settings.link_rate),
2581 1);
2582
2583 /* Set preferred link settings */
d0778ebf
HW		 2584 link->verified_link_cap.lane_count = link_settings.lane_count;
2585 link->verified_link_cap.link_rate = link_settings.link_rate;
4562236b 2586
73c72602 2587 dp_retrain_link_dp_test(link, &link_settings, false);
4562236b
HW		 2588}
2589
9315e239 2590/* TODO Raven hbr2 compliance eye output is unstable
25bab0da
WL		 2591 * (toggling on and off) with debugger break
2592 * This caueses intermittent PHY automation failure
2593 * Need to look into the root cause */
d0778ebf 2594static void dp_test_send_phy_test_pattern(struct dc_link *link)
4562236b
HW		 2595{
2596 union phy_test_pattern dpcd_test_pattern;
2597 union lane_adjust dpcd_lane_adjustment[2];
2598 unsigned char dpcd_post_cursor_2_adjustment = 0;
2599 unsigned char test_80_bit_pattern[
3a340294
DA		 2600 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2601 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
4562236b
HW		 2602 enum dp_test_pattern test_pattern;
2603 struct dc_link_training_settings link_settings;
2604 union lane_adjust dpcd_lane_adjust;
2605 unsigned int lane;
2606 struct link_training_settings link_training_settings;
2607 int i = 0;
2608
2609 dpcd_test_pattern.raw = 0;
2610 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2611 memset(&link_settings, 0, sizeof(link_settings));
2612
2613 /* get phy test pattern and pattern parameters from DP receiver */
2614 core_link_read_dpcd(
2615 link,
8811d9eb 2616 DP_PHY_TEST_PATTERN,
4562236b
HW		 2617 &dpcd_test_pattern.raw,
2618 sizeof(dpcd_test_pattern));
2619 core_link_read_dpcd(
2620 link,
3a340294 2621 DP_ADJUST_REQUEST_LANE0_1,
4562236b
HW		 2622 &dpcd_lane_adjustment[0].raw,
2623 sizeof(dpcd_lane_adjustment));
2624
2625 /*get post cursor 2 parameters
2626 * For DP 1.1a or eariler, this DPCD register's value is 0
2627 * For DP 1.2 or later:
2628 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2629 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2630 */
2631 core_link_read_dpcd(
2632 link,
3a340294 2633 DP_ADJUST_REQUEST_POST_CURSOR2,
4562236b
HW		 2634 &dpcd_post_cursor_2_adjustment,
2635 sizeof(dpcd_post_cursor_2_adjustment));
2636
2637 /* translate request */
2638 switch (dpcd_test_pattern.bits.PATTERN) {
2639 case PHY_TEST_PATTERN_D10_2:
2640 test_pattern = DP_TEST_PATTERN_D102;
0e19401f 2641 break;
4562236b
HW		 2642 case PHY_TEST_PATTERN_SYMBOL_ERROR:
2643 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 2644 break;
4562236b
HW		 2645 case PHY_TEST_PATTERN_PRBS7:
2646 test_pattern = DP_TEST_PATTERN_PRBS7;
0e19401f 2647 break;
4562236b
HW		 2648 case PHY_TEST_PATTERN_80BIT_CUSTOM:
2649 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 2650 break;
2651 case PHY_TEST_PATTERN_CP2520_1:
25bab0da 2652 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 2653 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 2654 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2655 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 2656 break;
2657 case PHY_TEST_PATTERN_CP2520_2:
25bab0da 2658 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 2659 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 2660 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2661 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 2662 break;
2663 case PHY_TEST_PATTERN_CP2520_3:
78e685f9 2664 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
0e19401f 2665 break;
4562236b
HW		 2666 default:
2667 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2668 break;
2669 }
2670
2671 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2672 core_link_read_dpcd(
2673 link,
3a340294 2674 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
4562236b
HW		 2675 test_80_bit_pattern,
2676 sizeof(test_80_bit_pattern));
2677
2678 /* prepare link training settings */
d0778ebf 2679 link_settings.link = link->cur_link_settings;
4562236b
HW		 2680
2681 for (lane = 0; lane <
d0778ebf 2682 (unsigned int)(link->cur_link_settings.lane_count);
4562236b
HW		 2683 lane++) {
2684 dpcd_lane_adjust.raw =
2685 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2686 link_settings.lane_settings[lane].VOLTAGE_SWING =
2687 (enum dc_voltage_swing)
2688 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2689 link_settings.lane_settings[lane].PRE_EMPHASIS =
2690 (enum dc_pre_emphasis)
2691 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2692 link_settings.lane_settings[lane].POST_CURSOR2 =
2693 (enum dc_post_cursor2)
2694 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2695 }
2696
2697 for (i = 0; i < 4; i++)
2698 link_training_settings.lane_settings[i] =
2699 link_settings.lane_settings[i];
2700 link_training_settings.link_settings = link_settings.link;
2701 link_training_settings.allow_invalid_msa_timing_param = false;
2702 /*Usage: Measure DP physical lane signal
2703 * by DP SI test equipment automatically.
2704 * PHY test pattern request is generated by equipment via HPD interrupt.
2705 * HPD needs to be active all the time. HPD should be active
2706 * all the time. Do not touch it.
2707 * forward request to DS
2708 */
2709 dc_link_dp_set_test_pattern(
d0778ebf 2710 link,
4562236b 2711 test_pattern,
2057b7e1 2712 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
4562236b
HW		 2713 &link_training_settings,
2714 test_80_bit_pattern,
3a340294
DA		 2715 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2716 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
4562236b
HW		 2717}
2718
d0778ebf 2719static void dp_test_send_link_test_pattern(struct dc_link *link)
4562236b
HW		 2720{
2721 union link_test_pattern dpcd_test_pattern;
2722 union test_misc dpcd_test_params;
2723 enum dp_test_pattern test_pattern;
2057b7e1
WL		 2724 enum dp_test_pattern_color_space test_pattern_color_space =
2725 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
4562236b
HW		 2726
2727 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2728 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2729
2730 /* get link test pattern and pattern parameters */
2731 core_link_read_dpcd(
2732 link,
3a340294 2733 DP_TEST_PATTERN,
4562236b
HW		 2734 &dpcd_test_pattern.raw,
2735 sizeof(dpcd_test_pattern));
2736 core_link_read_dpcd(
2737 link,
3a340294 2738 DP_TEST_MISC0,
4562236b
HW		 2739 &dpcd_test_params.raw,
2740 sizeof(dpcd_test_params));
2741
2742 switch (dpcd_test_pattern.bits.PATTERN) {
2743 case LINK_TEST_PATTERN_COLOR_RAMP:
2744 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2745 break;
2746 case LINK_TEST_PATTERN_VERTICAL_BARS:
2747 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2748 break; /* black and white */
2749 case LINK_TEST_PATTERN_COLOR_SQUARES:
2750 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2751 TEST_DYN_RANGE_VESA ?
2752 DP_TEST_PATTERN_COLOR_SQUARES :
2753 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2754 break;
2755 default:
2756 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2757 break;
2758 }
2759
ef65c702
JFZ		 2760 if (dpcd_test_params.bits.CLR_FORMAT == 0)
2761 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2762 else
2763 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2764 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2765 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2057b7e1 2766
4562236b 2767 dc_link_dp_set_test_pattern(
d0778ebf 2768 link,
4562236b 2769 test_pattern,
2057b7e1 2770 test_pattern_color_space,
4562236b
HW		 2771 NULL,
2772 NULL,
2773 0);
2774}
2775
8c8048f2 2776static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
2777{
2778 union audio_test_mode dpcd_test_mode = {0};
2779 struct audio_test_pattern_type dpcd_pattern_type = {0};
2780 union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
2781 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2782
2783 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2784 struct pipe_ctx *pipe_ctx = &pipes[0];
2785 unsigned int channel_count;
2786 unsigned int channel = 0;
2787 unsigned int modes = 0;
2788 unsigned int sampling_rate_in_hz = 0;
2789
2790 // get audio test mode and test pattern parameters
2791 core_link_read_dpcd(
2792 link,
2793 DP_TEST_AUDIO_MODE,
2794 &dpcd_test_mode.raw,
2795 sizeof(dpcd_test_mode));
2796
2797 core_link_read_dpcd(
2798 link,
2799 DP_TEST_AUDIO_PATTERN_TYPE,
2800 &dpcd_pattern_type.value,
2801 sizeof(dpcd_pattern_type));
2802
2803 channel_count = dpcd_test_mode.bits.channel_count + 1;
2804
2805 // read pattern periods for requested channels when sawTooth pattern is requested
2806 if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
2807 dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
2808
2809 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
2810 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2811 // read period for each channel
2812 for (channel = 0; channel < channel_count; channel++) {
2813 core_link_read_dpcd(
2814 link,
2815 DP_TEST_AUDIO_PERIOD_CH1 + channel,
2816 &dpcd_pattern_period[channel].raw,
2817 sizeof(dpcd_pattern_period[channel]));
2818 }
2819 }
2820
2821 // translate sampling rate
2822 switch (dpcd_test_mode.bits.sampling_rate) {
2823 case AUDIO_SAMPLING_RATE_32KHZ:
2824 sampling_rate_in_hz = 32000;
2825 break;
2826 case AUDIO_SAMPLING_RATE_44_1KHZ:
2827 sampling_rate_in_hz = 44100;
2828 break;
2829 case AUDIO_SAMPLING_RATE_48KHZ:
2830 sampling_rate_in_hz = 48000;
2831 break;
2832 case AUDIO_SAMPLING_RATE_88_2KHZ:
2833 sampling_rate_in_hz = 88200;
2834 break;
2835 case AUDIO_SAMPLING_RATE_96KHZ:
2836 sampling_rate_in_hz = 96000;
2837 break;
2838 case AUDIO_SAMPLING_RATE_176_4KHZ:
2839 sampling_rate_in_hz = 176400;
2840 break;
2841 case AUDIO_SAMPLING_RATE_192KHZ:
2842 sampling_rate_in_hz = 192000;
2843 break;
2844 default:
2845 sampling_rate_in_hz = 0;
2846 break;
2847 }
2848
2849 link->audio_test_data.flags.test_requested = 1;
2850 link->audio_test_data.flags.disable_video = disable_video;
2851 link->audio_test_data.sampling_rate = sampling_rate_in_hz;
2852 link->audio_test_data.channel_count = channel_count;
2853 link->audio_test_data.pattern_type = test_pattern;
2854
2855 if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
2856 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
2857 link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
2858 }
2859 }
2860}
2861
d0778ebf 2862static void handle_automated_test(struct dc_link *link)
4562236b
HW		 2863{
2864 union test_request test_request;
2865 union test_response test_response;
2866
2867 memset(&test_request, 0, sizeof(test_request));
2868 memset(&test_response, 0, sizeof(test_response));
2869
2870 core_link_read_dpcd(
2871 link,
3a340294 2872 DP_TEST_REQUEST,
4562236b
HW		 2873 &test_request.raw,
2874 sizeof(union test_request));
2875 if (test_request.bits.LINK_TRAINING) {
2876 /* ACK first to let DP RX test box monitor LT sequence */
2877 test_response.bits.ACK = 1;
2878 core_link_write_dpcd(
2879 link,
3a340294 2880 DP_TEST_RESPONSE,
4562236b
HW		 2881 &test_response.raw,
2882 sizeof(test_response));
2883 dp_test_send_link_training(link);
2884 /* no acknowledge request is needed again */
2885 test_response.bits.ACK = 0;
2886 }
2887 if (test_request.bits.LINK_TEST_PATTRN) {
2888 dp_test_send_link_test_pattern(link);
75a74755 2889 test_response.bits.ACK = 1;
4562236b 2890 }
8c8048f2 2891
2892 if (test_request.bits.AUDIO_TEST_PATTERN) {
2893 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
2894 test_response.bits.ACK = 1;
2895 }
2896
4562236b
HW		 2897 if (test_request.bits.PHY_TEST_PATTERN) {
2898 dp_test_send_phy_test_pattern(link);
2899 test_response.bits.ACK = 1;
2900 }
a6729a5a 2901
4562236b
HW		 2902 /* send request acknowledgment */
2903 if (test_response.bits.ACK)
2904 core_link_write_dpcd(
2905 link,
3a340294 2906 DP_TEST_RESPONSE,
4562236b
HW		 2907 &test_response.raw,
2908 sizeof(test_response));
2909}
2910
4e18814e 2911bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
4562236b 2912{
9a6a8075 2913 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
c2e218dd 2914 union device_service_irq device_service_clear = { { 0 } };
d6258eaa 2915 enum dc_status result;
4562236b 2916 bool status = false;
48af9b91
AL		 2917 struct pipe_ctx *pipe_ctx;
2918 int i;
4e18814e
FD		 2919
2920 if (out_link_loss)
2921 *out_link_loss = false;
4562236b
HW		 2922 /* For use cases related to down stream connection status change,
2923 * PSR and device auto test, refer to function handle_sst_hpd_irq
2924 * in DAL2.1*/
2925
1296423b 2926 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
d0778ebf 2927 __func__, link->link_index);
4562236b 2928
8ee65d7c 2929
4562236b
HW		 2930 /* All the "handle_hpd_irq_xxx()" methods
2931 * should be called only after
2932 * dal_dpsst_ls_read_hpd_irq_data
2933 * Order of calls is important too
2934 */
2935 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
8ee65d7c
WL		 2936 if (out_hpd_irq_dpcd_data)
2937 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4562236b
HW		 2938
2939 if (result != DC_OK) {
1296423b 2940 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
4562236b
HW		 2941 __func__);
2942 return false;
2943 }
2944
2945 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2946 device_service_clear.bits.AUTOMATED_TEST = 1;
2947 core_link_write_dpcd(
2948 link,
3a340294 2949 DP_DEVICE_SERVICE_IRQ_VECTOR,
4562236b
HW		 2950 &device_service_clear.raw,
2951 sizeof(device_service_clear.raw));
2952 device_service_clear.raw = 0;
2953 handle_automated_test(link);
2954 return false;
2955 }
2956
2957 if (!allow_hpd_rx_irq(link)) {
1296423b 2958 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
d0778ebf 2959 __func__, link->link_index);
4562236b
HW		 2960 return false;
2961 }
2962
2963 if (handle_hpd_irq_psr_sink(link))
2964 /* PSR-related error was detected and handled */
2965 return true;
2966
2967 /* If PSR-related error handled, Main link may be off,
2968 * so do not handle as a normal sink status change interrupt.
2969 */
2970
aaa15026
WL		 2971 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2972 return true;
2973
4562236b 2974 /* check if we have MST msg and return since we poll for it */
aaa15026 2975 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
4562236b
HW		 2976 return false;
2977
2978 /* For now we only handle 'Downstream port status' case.
2979 * If we got sink count changed it means
2980 * Downstream port status changed,
e97ed496
AK		 2981 * then DM should call DC to do the detection.
2982 * NOTE: Do not handle link loss on eDP since it is internal link*/
2983 if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
2984 hpd_rx_irq_check_link_loss_status(
2985 link,
2986 &hpd_irq_dpcd_data)) {
4562236b
HW		 2987 /* Connectivity log: link loss */
2988 CONN_DATA_LINK_LOSS(link,
2989 hpd_irq_dpcd_data.raw,
2990 sizeof(hpd_irq_dpcd_data),
2991 "Status: ");
2992
48af9b91
AL		 2993 for (i = 0; i < MAX_PIPES; i++) {
2994 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
832aa63b
PH		 2995 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2996 break;
2997 }
2998
2999 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3000 return false;
3001
832aa63b 3002
68423dab
AC		 3003 for (i = 0; i < MAX_PIPES; i++) {
3004 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3005 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3006 pipe_ctx->stream->link == link)
3007 core_link_disable_stream(pipe_ctx);
3008 }
48af9b91 3009
422d9091
XY		 3010 for (i = 0; i < MAX_PIPES; i++) {
3011 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
68423dab
AC		 3012 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3013 pipe_ctx->stream->link == link)
3014 core_link_enable_stream(link->dc->current_state, pipe_ctx);
422d9091
XY		 3015 }
3016
4562236b 3017 status = false;
4e18814e
FD		 3018 if (out_link_loss)
3019 *out_link_loss = true;
4562236b
HW		 3020 }
3021
d0778ebf 3022 if (link->type == dc_connection_active_dongle &&
4562236b
HW		 3023 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3024 != link->dpcd_sink_count)
3025 status = true;
3026
3027 /* reasons for HPD RX:
3028 * 1. Link Loss - ie Re-train the Link
3029 * 2. MST sideband message
3030 * 3. Automated Test - ie. Internal Commit
3031 * 4. CP (copy protection) - (not interesting for DM???)
3032 * 5. DRR
3033 * 6. Downstream Port status changed
3034 * -ie. Detect - this the only one
3035 * which is interesting for DM because
3036 * it must call dc_link_detect.
3037 */
3038 return status;
3039}
3040
3041/*query dpcd for version and mst cap addresses*/
d0778ebf 3042bool is_mst_supported(struct dc_link *link)
4562236b
HW		 3043{
3044 bool mst = false;
3045 enum dc_status st = DC_OK;
3046 union dpcd_rev rev;
3047 union mstm_cap cap;
3048
0b226322
DG		 3049 if (link->preferred_training_settings.mst_enable &&
3050 *link->preferred_training_settings.mst_enable == false) {
3051 return false;
3052 }
3053
4562236b
HW		 3054 rev.raw = 0;
3055 cap.raw = 0;
3056
3a340294 3057 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4562236b
HW		 3058 sizeof(rev));
3059
3060 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3061
3a340294 3062 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4562236b
HW		 3063 &cap.raw, sizeof(cap));
3064 if (st == DC_OK && cap.bits.MST_CAP == 1)
3065 mst = true;
3066 }
3067 return mst;
3068
3069}
3070
d0778ebf 3071bool is_dp_active_dongle(const struct dc_link *link)
4562236b 3072{
a504ad26 3073 return link->dpcd_caps.is_branch_dev;
4562236b
HW		 3074}
3075
6bffebc9
EY		 3076static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3077{
3078 switch (bpc) {
3079 case DOWN_STREAM_MAX_8BPC:
3080 return 8;
3081 case DOWN_STREAM_MAX_10BPC:
3082 return 10;
3083 case DOWN_STREAM_MAX_12BPC:
3084 return 12;
3085 case DOWN_STREAM_MAX_16BPC:
3086 return 16;
3087 default:
3088 break;
3089 }
3090
3091 return -1;
3092}
3093
ee13cea9
JB		 3094static void read_dp_device_vendor_id(struct dc_link *link)
3095{
3096 struct dp_device_vendor_id dp_id;
3097
3098 /* read IEEE branch device id */
3099 core_link_read_dpcd(
3100 link,
3101 DP_BRANCH_OUI,
3102 (uint8_t *)&dp_id,
3103 sizeof(dp_id));
3104
3105 link->dpcd_caps.branch_dev_id =
3106 (dp_id.ieee_oui[0] << 16) +
3107 (dp_id.ieee_oui[1] << 8) +
3108 dp_id.ieee_oui[2];
3109
3110 memmove(
3111 link->dpcd_caps.branch_dev_name,
3112 dp_id.ieee_device_id,
3113 sizeof(dp_id.ieee_device_id));
3114}
3115
3116
3117
4562236b 3118static void get_active_converter_info(
d0778ebf 3119 uint8_t data, struct dc_link *link)
4562236b
HW		 3120{
3121 union dp_downstream_port_present ds_port = { .byte = data };
dd998291 3122 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
4562236b
HW		 3123
3124 /* decode converter info*/
3125 if (!ds_port.fields.PORT_PRESENT) {
3126 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
d0778ebf 3127 ddc_service_set_dongle_type(link->ddc,
4562236b 3128 link->dpcd_caps.dongle_type);
ac3d76e0 3129 link->dpcd_caps.is_branch_dev = false;
4562236b
HW		 3130 return;
3131 }
3132
a504ad26 3133 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
ac3d76e0
HT		 3134 if (ds_port.fields.PORT_TYPE == DOWNSTREAM_DP) {
3135 link->dpcd_caps.is_branch_dev = false;
3136 }
3137
3138 else {
3139 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3140 }
a504ad26 3141
4562236b
HW		 3142 switch (ds_port.fields.PORT_TYPE) {
3143 case DOWNSTREAM_VGA:
3144 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3145 break;
7a83645a
DZ		 3146 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3147 /* At this point we don't know is it DVI or HDMI or DP++,
4562236b
HW		 3148 * assume DVI.*/
3149 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3150 break;
3151 default:
3152 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3153 break;
3154 }
3155
ac0e562c 3156 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
242b0c8f 3157 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
4562236b
HW		 3158 union dwnstream_port_caps_byte0 *port_caps =
3159 (union dwnstream_port_caps_byte0 *)det_caps;
5aedc7bc 3160 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3161 det_caps, sizeof(det_caps)) == DC_OK) {
4562236b 3162
5aedc7bc 3163 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3164 /*Handle DP case as DONGLE_NONE*/
3165 case DOWN_STREAM_DETAILED_DP:
3166 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3167 break;
3168 case DOWN_STREAM_DETAILED_VGA:
3169 link->dpcd_caps.dongle_type =
3170 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3171 break;
3172 case DOWN_STREAM_DETAILED_DVI:
3173 link->dpcd_caps.dongle_type =
3174 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3175 break;
3176 case DOWN_STREAM_DETAILED_HDMI:
3177 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3178 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3179 link->dpcd_caps.dongle_type =
3180 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3181
3182 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3183 if (ds_port.fields.DETAILED_CAPS) {
3184
3185 union dwnstream_port_caps_byte3_hdmi
3186 hdmi_caps = {.raw = det_caps[3] };
3187 union dwnstream_port_caps_byte2
3188 hdmi_color_caps = {.raw = det_caps[2] };
3189 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3190 det_caps[1] * 2500;
3191
3192 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3193 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3194 /*YCBCR capability only for HDMI case*/
3195 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3196 == DOWN_STREAM_DETAILED_HDMI) {
3197 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3198 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3199 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3200 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3201 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3202 hdmi_caps.bits.YCrCr422_CONVERSION;
3203 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3204 hdmi_caps.bits.YCrCr420_CONVERSION;
3205 }
3206
3207 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3208 translate_dpcd_max_bpc(
3209 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3210
3211 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3212 link->dpcd_caps.dongle_caps.extendedCapValid = true;
7a83645a 3213 }
03f5c686 3214
5aedc7bc 3215 break;
4562236b 3216 }
4562236b
HW		 3217 }
3218 }
3219
d0778ebf 3220 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4562236b 3221
4562236b
HW		 3222 {
3223 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3224
3225 core_link_read_dpcd(
3226 link,
3a340294 3227 DP_BRANCH_REVISION_START,
4562236b
HW		 3228 (uint8_t *)&dp_hw_fw_revision,
3229 sizeof(dp_hw_fw_revision));
3230
3231 link->dpcd_caps.branch_hw_revision =
3232 dp_hw_fw_revision.ieee_hw_rev;
4b99affb
A		 3233
3234 memmove(
3235 link->dpcd_caps.branch_fw_revision,
3236 dp_hw_fw_revision.ieee_fw_rev,
3237 sizeof(dp_hw_fw_revision.ieee_fw_rev));
4562236b
HW		 3238 }
3239}
3240
d0778ebf 3241static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4562236b
HW		 3242 int length)
3243{
3244 int retry = 0;
4562236b
HW		 3245
3246 if (!link->dpcd_caps.dpcd_rev.raw) {
3247 do {
3248 dp_receiver_power_ctrl(link, true);
3a340294 3249 core_link_read_dpcd(link, DP_DPCD_REV,
4562236b
HW		 3250 dpcd_data, length);
3251 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3a340294
DA		 3252 DP_DPCD_REV -
3253 DP_DPCD_REV];
4562236b
HW		 3254 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3255 }
3256
4562236b
HW		 3257 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3258 switch (link->dpcd_caps.branch_dev_id) {
df3b7e32 3259 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
4562236b
HW		 3260 * all internal circuits including AUX communication preventing
3261 * reading DPCD table and EDID (spec violation).
3262 * Encoder will skip DP RX power down on disable_output to
3263 * keep receiver powered all the time.*/
df3b7e32
QZ		 3264 case DP_BRANCH_DEVICE_ID_0010FA:
3265 case DP_BRANCH_DEVICE_ID_0080E1:
566b4252 3266 case DP_BRANCH_DEVICE_ID_00E04C:
4562236b
HW		 3267 link->wa_flags.dp_keep_receiver_powered = true;
3268 break;
3269
3270 /* TODO: May need work around for other dongles. */
3271 default:
3272 link->wa_flags.dp_keep_receiver_powered = false;
3273 break;
3274 }
3275 } else
3276 link->wa_flags.dp_keep_receiver_powered = false;
3277}
3278
96577cf8
HW		 3279/* Read additional sink caps defined in source specific DPCD area
3280 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3281 */
3282static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3283{
3284 uint8_t dpcd_data;
3285
3286 if (!link)
3287 return false;
3288
3289 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3290 return false;
3291
3292 link->dpcd_sink_ext_caps.raw = dpcd_data;
3293 return true;
3294}
3295
cdb39798 3296static bool retrieve_link_cap(struct dc_link *link)
4562236b 3297{
61aa7a6f 3298 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3299 * which means size 16 will be good for both of those DPCD register block reads
3300 */
3301 uint8_t dpcd_data[16];
3302 uint8_t lttpr_dpcd_data[6];
4562236b 3303
3c7dd2cb
HT		 3304 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3305 */
3306 uint8_t dpcd_dprx_data = '\0';
8633d96d 3307 uint8_t dpcd_power_state = '\0';
3c7dd2cb 3308
8ca80900 3309 struct dp_device_vendor_id sink_id;
4562236b
HW		 3310 union down_stream_port_count down_strm_port_count;
3311 union edp_configuration_cap edp_config_cap;
3312 union dp_downstream_port_present ds_port = { 0 };
cdb39798 3313 enum dc_status status = DC_ERROR_UNEXPECTED;
3c1a312a
YS		 3314 uint32_t read_dpcd_retry_cnt = 3;
3315 int i;
4b99affb 3316 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
c797ede0
WL		 3317 bool is_lttpr_present = false;
3318 const uint32_t post_oui_delay = 30; // 30ms
8e5100a5 3319
4562236b 3320 memset(dpcd_data, '\0', sizeof(dpcd_data));
61aa7a6f 3321 memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
4562236b
HW		 3322 memset(&down_strm_port_count,
3323 '\0', sizeof(union down_stream_port_count));
3324 memset(&edp_config_cap, '\0',
3325 sizeof(union edp_configuration_cap));
3326
c797ede0
WL		 3327 /* if extended timeout is supported in hardware,
3328 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3329 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3330 */
3331 dc_link_aux_try_to_configure_timeout(link->ddc,
3332 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3333
8633d96d
AK		 3334 status = core_link_read_dpcd(link, DP_SET_POWER,
3335 &dpcd_power_state, sizeof(dpcd_power_state));
3336
3337 /* Delay 1 ms if AUX CH is in power down state. Based on spec
3338 * section 2.3.1.2, if AUX CH may be powered down due to
3339 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3340 * signal and may need up to 1 ms before being able to reply.
3341 */
3342 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3343 udelay(1000);
3344
c797ede0
WL		 3345 dpcd_set_source_specific_data(link);
3346 /* Sink may need to configure internals based on vendor, so allow some
3347 * time before proceeding with possibly vendor specific transactions
3348 */
3349 msleep(post_oui_delay);
3350
3c1a312a
YS		 3351 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3352 status = core_link_read_dpcd(
3353 link,
3354 DP_DPCD_REV,
3355 dpcd_data,
3356 sizeof(dpcd_data));
3357 if (status == DC_OK)
3358 break;
3359 }
cdb39798
YS		 3360
3361 if (status != DC_OK) {
3362 dm_error("%s: Read dpcd data failed.\n", __func__);
3363 return false;
3364 }
4562236b 3365
c797ede0
WL		 3366 if (link->dc->caps.extended_aux_timeout_support &&
3367 link->dc->config.allow_lttpr_non_transparent_mode) {
3368 /* By reading LTTPR capability, RX assumes that we will enable
3369 * LTTPR non transparent if LTTPR is present.
3370 * Therefore, only query LTTPR capability when both LTTPR
3371 * extended aux timeout and
3372 * non transparent mode is supported by hardware
3373 */
8e5100a5 3374 status = core_link_read_dpcd(
3375 link,
61aa7a6f 3376 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3377 lttpr_dpcd_data,
3378 sizeof(lttpr_dpcd_data));
3379
3380 link->dpcd_caps.lttpr_caps.revision.raw =
3381 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3382 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3383
3384 link->dpcd_caps.lttpr_caps.max_link_rate =
3385 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3386 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3387
3388 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3389 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3390 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3391
3392 link->dpcd_caps.lttpr_caps.max_lane_count =
3393 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3394 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3395
3396 link->dpcd_caps.lttpr_caps.mode =
3397 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3398 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3399
3400 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3401 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3402 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3403
c797ede0 3404 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
61aa7a6f 3405 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3406 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
c797ede0
WL		 3407 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3408 if (is_lttpr_present)
3409 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
a1500a62 3410 }
fb8cf277 3411
c797ede0
WL		 3412 /* decide lttpr non transparent mode */
3413 link->lttpr_non_transparent_mode = is_lttpr_present;
3414
3415 if (!is_lttpr_present)
3416 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3417
3418
4562236b
HW		 3419 {
3420 union training_aux_rd_interval aux_rd_interval;
3421
3422 aux_rd_interval.raw =
3a340294 3423 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
4562236b 3424
3c7dd2cb 3425 link->dpcd_caps.ext_receiver_cap_field_present =
b239b59b 3426 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3c7dd2cb
HT		 3427
3428 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
818832bf
XY		 3429 uint8_t ext_cap_data[16];
3430
3431 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3432 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3433 status = core_link_read_dpcd(
4562236b 3434 link,
3a340294 3435 DP_DP13_DPCD_REV,
818832bf
XY		 3436 ext_cap_data,
3437 sizeof(ext_cap_data));
3438 if (status == DC_OK) {
3439 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3440 break;
3441 }
3442 }
3443 if (status != DC_OK)
3444 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
4562236b
HW		 3445 }
3446 }
3447
3c7dd2cb
HT		 3448 link->dpcd_caps.dpcd_rev.raw =
3449 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3450
7715fdf3 3451 if (link->dpcd_caps.ext_receiver_cap_field_present) {
3c7dd2cb
HT		 3452 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3453 status = core_link_read_dpcd(
3454 link,
3455 DP_DPRX_FEATURE_ENUMERATION_LIST,
3456 &dpcd_dprx_data,
3457 sizeof(dpcd_dprx_data));
3458 if (status == DC_OK)
3459 break;
3460 }
3461
3462 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3463
3464 if (status != DC_OK)
3465 dm_error("%s: Read DPRX caps data failed.\n", __func__);
3466 }
3467
3468 else {
3469 link->dpcd_caps.dprx_feature.raw = 0;
3470 }
3471
3472
07d6a199
AK		 3473 /* Error condition checking...
3474 * It is impossible for Sink to report Max Lane Count = 0.
3475 * It is possible for Sink to report Max Link Rate = 0, if it is
3476 * an eDP device that is reporting specialized link rates in the
3477 * SUPPORTED_LINK_RATE table.
3478 */
3479 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3480 return false;
3481
3a340294
DA		 3482 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3483 DP_DPCD_REV];
4562236b 3484
ee13cea9
JB		 3485 read_dp_device_vendor_id(link);
3486
4562236b
HW		 3487 get_active_converter_info(ds_port.byte, link);
3488
3489 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3490
98e6436d
AK		 3491 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3492 DP_DPCD_REV];
3493
4562236b
HW		 3494 link->dpcd_caps.allow_invalid_MSA_timing_param =
3495 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3496
3497 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3a340294 3498 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4562236b
HW		 3499
3500 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3a340294 3501 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4562236b 3502
d0778ebf 3503 link->reported_link_cap.lane_count =
4562236b 3504 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
d0778ebf 3505 link->reported_link_cap.link_rate = dpcd_data[
3a340294 3506 DP_MAX_LINK_RATE - DP_DPCD_REV];
d0778ebf 3507 link->reported_link_cap.link_spread =
4562236b
HW		 3508 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3509 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3510
3511 edp_config_cap.raw = dpcd_data[
3a340294 3512 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4562236b
HW		 3513 link->dpcd_caps.panel_mode_edp =
3514 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
9799624a
WL		 3515 link->dpcd_caps.dpcd_display_control_capable =
3516 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4562236b 3517
d0778ebf
HW		 3518 link->test_pattern_enabled = false;
3519 link->compliance_test_state.raw = 0;
4562236b 3520
4562236b
HW		 3521 /* read sink count */
3522 core_link_read_dpcd(link,
3a340294 3523 DP_SINK_COUNT,
4562236b
HW		 3524 &link->dpcd_caps.sink_count.raw,
3525 sizeof(link->dpcd_caps.sink_count.raw));
3526
8ca80900
AK		 3527 /* read sink ieee oui */
3528 core_link_read_dpcd(link,
3529 DP_SINK_OUI,
3530 (uint8_t *)(&sink_id),
3531 sizeof(sink_id));
3532
3533 link->dpcd_caps.sink_dev_id =
3534 (sink_id.ieee_oui[0] << 16) +
3535 (sink_id.ieee_oui[1] << 8) +
3536 (sink_id.ieee_oui[2]);
3537
4b99affb
A		 3538 memmove(
3539 link->dpcd_caps.sink_dev_id_str,
3540 sink_id.ieee_device_id,
3541 sizeof(sink_id.ieee_device_id));
3542
473e3f77
MK		 3543 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3544 {
3545 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3546
3547 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3548 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3549 sizeof(str_mbp_2017))) {
3550 link->reported_link_cap.link_rate = 0x0c;
3551 }
3552 }
3553
4b99affb
A		 3554 core_link_read_dpcd(
3555 link,
3556 DP_SINK_HW_REVISION_START,
3557 (uint8_t *)&dp_hw_fw_revision,
3558 sizeof(dp_hw_fw_revision));
3559
3560 link->dpcd_caps.sink_hw_revision =
3561 dp_hw_fw_revision.ieee_hw_rev;
3562
3563 memmove(
3564 link->dpcd_caps.sink_fw_revision,
3565 dp_hw_fw_revision.ieee_fw_rev,
3566 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3567
39a4eb85
WL		 3568 memset(&link->dpcd_caps.dsc_caps, '\0',
3569 sizeof(link->dpcd_caps.dsc_caps));
97bda032
HW		 3570 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3571 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3572 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
97bda032
HW		 3573 status = core_link_read_dpcd(
3574 link,
3575 DP_FEC_CAPABILITY,
3576 &link->dpcd_caps.fec_cap.raw,
3577 sizeof(link->dpcd_caps.fec_cap.raw));
39a4eb85
WL		 3578 status = core_link_read_dpcd(
3579 link,
3580 DP_DSC_SUPPORT,
3581 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3582 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3583 status = core_link_read_dpcd(
3584 link,
3585 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
6d824ed5
WL		 3586 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3587 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
97bda032 3588 }
6fbefb84 3589
96577cf8
HW		 3590 if (!dpcd_read_sink_ext_caps(link))
3591 link->dpcd_sink_ext_caps.raw = 0;
3592
4562236b
HW		 3593 /* Connectivity log: detection */
3594 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
cdb39798
YS		 3595
3596 return true;
4562236b
HW		 3597}
3598
8547058b
LH		 3599bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3600{
3601 uint8_t dpcd_data[16];
3602 uint32_t read_dpcd_retry_cnt = 3;
3603 enum dc_status status = DC_ERROR_UNEXPECTED;
3604 union dp_downstream_port_present ds_port = { 0 };
3605 union down_stream_port_count down_strm_port_count;
3606 union edp_configuration_cap edp_config_cap;
3607
3608 int i;
3609
3610 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3611 status = core_link_read_dpcd(
3612 link,
3613 DP_DPCD_REV,
3614 dpcd_data,
3615 sizeof(dpcd_data));
3616 if (status == DC_OK)
3617 break;
3618 }
3619
3620 link->dpcd_caps.dpcd_rev.raw =
3621 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3622
3623 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3624 return false;
3625
3626 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3627 DP_DPCD_REV];
3628
3629 get_active_converter_info(ds_port.byte, link);
3630
3631 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3632 DP_DPCD_REV];
3633
3634 link->dpcd_caps.allow_invalid_MSA_timing_param =
3635 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3636
3637 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3638 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3639
3640 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3641 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3642
3643 link->reported_link_cap.lane_count =
3644 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3645 link->reported_link_cap.link_rate = dpcd_data[
3646 DP_MAX_LINK_RATE - DP_DPCD_REV];
3647 link->reported_link_cap.link_spread =
3648 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3649 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3650
3651 edp_config_cap.raw = dpcd_data[
3652 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3653 link->dpcd_caps.panel_mode_edp =
3654 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3655 link->dpcd_caps.dpcd_display_control_capable =
3656 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3657
3658 return true;
3659}
3660
cdb39798 3661bool detect_dp_sink_caps(struct dc_link *link)
4562236b 3662{
cdb39798 3663 return retrieve_link_cap(link);
4562236b
HW		 3664
3665 /* dc init_hw has power encoder using default
3666 * signal for connector. For native DP, no
3667 * need to power up encoder again. If not native
3668 * DP, hw_init may need check signal or power up
3669 * encoder here.
3670 */
4562236b
HW		 3671 /* TODO save sink caps in link->sink */
3672}
3673
b03a599b
DL		 3674enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3675{
3676 enum dc_link_rate link_rate;
3677 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3678 switch (link_rate_in_khz) {
3679 case 1620000:
3680 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
3681 break;
3682 case 2160000:
3683 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
3684 break;
3685 case 2430000:
3686 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
3687 break;
3688 case 2700000:
3689 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
3690 break;
3691 case 3240000:
3692 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
3693 break;
3694 case 4320000:
3695 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
3696 break;
3697 case 5400000:
3698 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
3699 break;
3700 case 8100000:
3701 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
3702 break;
3703 default:
3704 link_rate = LINK_RATE_UNKNOWN;
3705 break;
3706 }
3707 return link_rate;
3708}
3709
4654a2f7
RL		 3710void detect_edp_sink_caps(struct dc_link *link)
3711{
8628d02f 3712 uint8_t supported_link_rates[16];
b03a599b
DL		 3713 uint32_t entry;
3714 uint32_t link_rate_in_khz;
3715 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
48231fd5 3716
b03a599b 3717 retrieve_link_cap(link);
8628d02f
JP		 3718 link->dpcd_caps.edp_supported_link_rates_count = 0;
3719 memset(supported_link_rates, 0, sizeof(supported_link_rates));
48231fd5 3720
8628d02f 3721 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
53c81fc7
WC		 3722 (link->dc->config.optimize_edp_link_rate ||
3723 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
b03a599b
DL		 3724 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3725 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
3726 supported_link_rates, sizeof(supported_link_rates));
3727
b03a599b
DL		 3728 for (entry = 0; entry < 16; entry += 2) {
3729 // DPCD register reports per-lane link rate = 16-bit link rate capability
8628d02f 3730 // value X 200 kHz. Need multiplier to find link rate in kHz.
b03a599b
DL		 3731 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3732 supported_link_rates[entry]) * 200;
3733
3734 if (link_rate_in_khz != 0) {
3735 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
8628d02f
JP		 3736 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
3737 link->dpcd_caps.edp_supported_link_rates_count++;
53c81fc7
WC		 3738
3739 if (link->reported_link_cap.link_rate < link_rate)
3740 link->reported_link_cap.link_rate = link_rate;
b03a599b
DL		 3741 }
3742 }
3743 }
4654a2f7 3744 link->verified_link_cap = link->reported_link_cap;
96577cf8
HW		 3745
3746 dc_link_set_default_brightness_aux(link);
4654a2f7
RL		 3747}
3748
4562236b
HW		 3749void dc_link_dp_enable_hpd(const struct dc_link *link)
3750{
d0778ebf 3751 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 3752
3753 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3754 encoder->funcs->enable_hpd(encoder);
3755}
3756
3757void dc_link_dp_disable_hpd(const struct dc_link *link)
3758{
d0778ebf 3759 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 3760
3761 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3762 encoder->funcs->disable_hpd(encoder);
3763}
3764
3765static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
3766{
0e19401f
TC		 3767 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
3768 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
3769 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4562236b
HW		 3770 return true;
3771 else
3772 return false;
3773}
3774
d0778ebf 3775static void set_crtc_test_pattern(struct dc_link *link,
4562236b 3776 struct pipe_ctx *pipe_ctx,
2057b7e1
WL		 3777 enum dp_test_pattern test_pattern,
3778 enum dp_test_pattern_color_space test_pattern_color_space)
4562236b
HW		 3779{
3780 enum controller_dp_test_pattern controller_test_pattern;
3781 enum dc_color_depth color_depth = pipe_ctx->
4fa086b9 3782 stream->timing.display_color_depth;
4562236b 3783 struct bit_depth_reduction_params params;
661a8cd9 3784 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
6fbefb84
HW		 3785 int width = pipe_ctx->stream->timing.h_addressable +
3786 pipe_ctx->stream->timing.h_border_left +
3787 pipe_ctx->stream->timing.h_border_right;
3788 int height = pipe_ctx->stream->timing.v_addressable +
3789 pipe_ctx->stream->timing.v_border_bottom +
3790 pipe_ctx->stream->timing.v_border_top;
4562236b
HW		 3791
3792 memset(&params, 0, sizeof(params));
3793
3794 switch (test_pattern) {
3795 case DP_TEST_PATTERN_COLOR_SQUARES:
3796 controller_test_pattern =
3797 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
3798 break;
3799 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3800 controller_test_pattern =
3801 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
3802 break;
3803 case DP_TEST_PATTERN_VERTICAL_BARS:
3804 controller_test_pattern =
3805 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
3806 break;
3807 case DP_TEST_PATTERN_HORIZONTAL_BARS:
3808 controller_test_pattern =
3809 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
3810 break;
3811 case DP_TEST_PATTERN_COLOR_RAMP:
3812 controller_test_pattern =
3813 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
3814 break;
3815 default:
3816 controller_test_pattern =
3817 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
3818 break;
3819 }
3820
3821 switch (test_pattern) {
3822 case DP_TEST_PATTERN_COLOR_SQUARES:
3823 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3824 case DP_TEST_PATTERN_VERTICAL_BARS:
3825 case DP_TEST_PATTERN_HORIZONTAL_BARS:
3826 case DP_TEST_PATTERN_COLOR_RAMP:
3827 {
3828 /* disable bit depth reduction */
3829 pipe_ctx->stream->bit_depth_params = params;
661a8cd9 3830 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
7f93c1de
CL		 3831 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3832 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b 3833 controller_test_pattern, color_depth);
6fbefb84 3834 else if (opp->funcs->opp_set_disp_pattern_generator) {
b1f6d01c 3835 struct pipe_ctx *odm_pipe;
2057b7e1 3836 enum controller_dp_color_space controller_color_space;
b1f6d01c 3837 int opp_cnt = 1;
10b4e64e
WL		 3838 int offset = 0;
3839 int dpg_width = width;
6fbefb84 3840
2057b7e1
WL		 3841 switch (test_pattern_color_space) {
3842 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
3843 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
3844 break;
3845 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
3846 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
3847 break;
3848 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
3849 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
3850 break;
3851 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
3852 default:
3853 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
3854 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
3855 ASSERT(0);
3856 break;
3857 }
3858
b1f6d01c
DL		 3859 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3860 opp_cnt++;
10b4e64e
WL		 3861 dpg_width = width / opp_cnt;
3862 offset = dpg_width;
6fbefb84 3863
10b4e64e
WL		 3864 opp->funcs->opp_set_disp_pattern_generator(opp,
3865 controller_test_pattern,
3866 controller_color_space,
3867 color_depth,
3868 NULL,
3869 dpg_width,
3870 height,
3871 0);
b1f6d01c
DL		 3872
3873 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3874 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
b1f6d01c
DL		 3875 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
3876 odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
6fbefb84 3877 controller_test_pattern,
2057b7e1 3878 controller_color_space,
6fbefb84
HW		 3879 color_depth,
3880 NULL,
10b4e64e
WL		 3881 dpg_width,
3882 height,
3883 offset);
3884 offset += offset;
6fbefb84 3885 }
6fbefb84 3886 }
4562236b
HW		 3887 }
3888 break;
3889 case DP_TEST_PATTERN_VIDEO_MODE:
3890 {
3891 /* restore bitdepth reduction */
661a8cd9 3892 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4562236b 3893 pipe_ctx->stream->bit_depth_params = params;
661a8cd9 3894 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
7f93c1de
CL		 3895 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3896 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 3897 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3898 color_depth);
6fbefb84 3899 else if (opp->funcs->opp_set_disp_pattern_generator) {
b1f6d01c
DL		 3900 struct pipe_ctx *odm_pipe;
3901 int opp_cnt = 1;
10b4e64e 3902 int dpg_width = width;
b1f6d01c
DL		 3903
3904 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3905 opp_cnt++;
6fbefb84 3906
10b4e64e 3907 dpg_width = width / opp_cnt;
b1f6d01c
DL		 3908 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3909 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
6fbefb84 3910
b1f6d01c
DL		 3911 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
3912 odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
6fbefb84 3913 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2057b7e1 3914 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
6fbefb84
HW		 3915 color_depth,
3916 NULL,
10b4e64e
WL		 3917 dpg_width,
3918 height,
3919 0);
6fbefb84
HW		 3920 }
3921 opp->funcs->opp_set_disp_pattern_generator(opp,
3922 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2057b7e1 3923 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
6fbefb84
HW		 3924 color_depth,
3925 NULL,
10b4e64e
WL		 3926 dpg_width,
3927 height,
3928 0);
6fbefb84 3929 }
4562236b
HW		 3930 }
3931 break;
3932
3933 default:
3934 break;
3935 }
3936}
3937
3938bool dc_link_dp_set_test_pattern(
d0778ebf 3939 struct dc_link *link,
4562236b 3940 enum dp_test_pattern test_pattern,
2057b7e1 3941 enum dp_test_pattern_color_space test_pattern_color_space,
4562236b
HW		 3942 const struct link_training_settings *p_link_settings,
3943 const unsigned char *p_custom_pattern,
3944 unsigned int cust_pattern_size)
3945{
608ac7bb 3946 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
0a8f43ff 3947 struct pipe_ctx *pipe_ctx = &pipes[0];
4562236b
HW		 3948 unsigned int lane;
3949 unsigned int i;
3950 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
3951 union dpcd_training_pattern training_pattern;
4562236b
HW		 3952 enum dpcd_phy_test_patterns pattern;
3953
3954 memset(&training_pattern, 0, sizeof(training_pattern));
4562236b
HW		 3955
3956 for (i = 0; i < MAX_PIPES; i++) {
24d01c9b 3957 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
0a8f43ff 3958 pipe_ctx = &pipes[i];
4562236b
HW		 3959 break;
3960 }
3961 }
3962
3963 /* Reset CRTC Test Pattern if it is currently running and request
3964 * is VideoMode Reset DP Phy Test Pattern if it is currently running
3965 * and request is VideoMode
3966 */
d0778ebf 3967 if (link->test_pattern_enabled && test_pattern ==
4562236b
HW		 3968 DP_TEST_PATTERN_VIDEO_MODE) {
3969 /* Set CRTC Test Pattern */
2057b7e1 3970 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
d0778ebf 3971 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 3972 (uint8_t *)p_custom_pattern,
3973 (uint32_t)cust_pattern_size);
3974
3975 /* Unblank Stream */
d0778ebf 3976 link->dc->hwss.unblank_stream(
0a8f43ff 3977 pipe_ctx,
d0778ebf 3978 &link->verified_link_cap);
4562236b
HW		 3979 /* TODO:m_pHwss->MuteAudioEndpoint
3980 * (pPathMode->pDisplayPath, false);
3981 */
3982
3983 /* Reset Test Pattern state */
d0778ebf 3984 link->test_pattern_enabled = false;
4562236b
HW		 3985
3986 return true;
3987 }
3988
3989 /* Check for PHY Test Patterns */
3990 if (is_dp_phy_pattern(test_pattern)) {
3991 /* Set DPCD Lane Settings before running test pattern */
3992 if (p_link_settings != NULL) {
64c12b73 3993 dp_set_hw_lane_settings(link, p_link_settings, DPRX);
3994 dpcd_set_lane_settings(link, p_link_settings, DPRX);
4562236b
HW		 3995 }
3996
3997 /* Blank stream if running test pattern */
3998 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3999 /*TODO:
4000 * m_pHwss->
4001 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4002 */
4003 /* Blank stream */
8e9c4c8c 4004 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4562236b
HW		 4005 }
4006
d0778ebf 4007 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 4008 (uint8_t *)p_custom_pattern,
4009 (uint32_t)cust_pattern_size);
4010
4011 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4012 /* Set Test Pattern state */
d0778ebf 4013 link->test_pattern_enabled = true;
4562236b 4014 if (p_link_settings != NULL)
d0778ebf 4015 dpcd_set_link_settings(link,
4562236b
HW		 4016 p_link_settings);
4017 }
4018
4019 switch (test_pattern) {
4020 case DP_TEST_PATTERN_VIDEO_MODE:
4021 pattern = PHY_TEST_PATTERN_NONE;
0e19401f 4022 break;
4562236b
HW		 4023 case DP_TEST_PATTERN_D102:
4024 pattern = PHY_TEST_PATTERN_D10_2;
0e19401f 4025 break;
4562236b
HW		 4026 case DP_TEST_PATTERN_SYMBOL_ERROR:
4027 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 4028 break;
4562236b
HW		 4029 case DP_TEST_PATTERN_PRBS7:
4030 pattern = PHY_TEST_PATTERN_PRBS7;
0e19401f 4031 break;
4562236b
HW		 4032 case DP_TEST_PATTERN_80BIT_CUSTOM:
4033 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 4034 break;
4035 case DP_TEST_PATTERN_CP2520_1:
4036 pattern = PHY_TEST_PATTERN_CP2520_1;
4037 break;
4038 case DP_TEST_PATTERN_CP2520_2:
4039 pattern = PHY_TEST_PATTERN_CP2520_2;
4040 break;
4041 case DP_TEST_PATTERN_CP2520_3:
4042 pattern = PHY_TEST_PATTERN_CP2520_3;
4043 break;
4562236b
HW		 4044 default:
4045 return false;
4046 }
4047
4048 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4049 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4050 return false;
4051
d0778ebf 4052 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 4053 /* tell receiver that we are sending qualification
4054 * pattern DP 1.2 or later - DP receiver's link quality
4055 * pattern is set using DPCD LINK_QUAL_LANEx_SET
4056 * register (0x10B~0x10E)\
4057 */
4058 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4059 link_qual_pattern[lane] =
4060 (unsigned char)(pattern);
4061
d0778ebf 4062 core_link_write_dpcd(link,
3a340294 4063 DP_LINK_QUAL_LANE0_SET,
4562236b
HW		 4064 link_qual_pattern,
4065 sizeof(link_qual_pattern));
d0778ebf
HW		 4066 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4067 link->dpcd_caps.dpcd_rev.raw == 0) {
4562236b
HW		 4068 /* tell receiver that we are sending qualification
4069 * pattern DP 1.1a or earlier - DP receiver's link
4070 * quality pattern is set using
4071 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4072 * register (0x102). We will use v_1.3 when we are
4073 * setting test pattern for DP 1.1.
4074 */
d0778ebf
HW		 4075 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4076 &training_pattern.raw,
4077 sizeof(training_pattern));
4562236b 4078 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
d0778ebf
HW		 4079 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4080 &training_pattern.raw,
4081 sizeof(training_pattern));
4562236b
HW		 4082 }
4083 } else {
43563bc2 4084 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
43563bc2
WL		 4085
4086 switch (test_pattern_color_space) {
4087 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4088 color_space = COLOR_SPACE_SRGB;
4089 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4090 color_space = COLOR_SPACE_SRGB_LIMITED;
4091 break;
4092
4093 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4094 color_space = COLOR_SPACE_YCBCR601;
4095 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4096 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4097 break;
4098 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4099 color_space = COLOR_SPACE_YCBCR709;
4100 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4101 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4102 break;
4103 default:
4104 break;
4105 }
e8f9ecf2 4106
dc6e2448
WW		 4107 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4108 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4109 union dmub_hw_lock_flags hw_locks = { 0 };
4110 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4111
4112 hw_locks.bits.lock_dig = 1;
4113 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4114
4115 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4116 true,
4117 &hw_locks,
4118 &inst_flags);
4119 } else
4120 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4121 pipe_ctx->stream_res.tg);
4122 }
4123
e8f9ecf2 4124 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
43563bc2
WL		 4125 /* update MSA to requested color space */
4126 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4127 &pipe_ctx->stream->timing,
23bc5f34
WL		 4128 color_space,
4129 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4130 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
43563bc2 4131
e8f9ecf2
WL		 4132 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4133 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4134 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4135 else
4136 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4137 resource_build_info_frame(pipe_ctx);
4138 link->dc->hwss.update_info_frame(pipe_ctx);
4139 }
4140
43563bc2 4141 /* CRTC Patterns */
2057b7e1 4142 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
e8f9ecf2
WL		 4143 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4144 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4145 CRTC_STATE_VACTIVE);
4146 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4147 CRTC_STATE_VBLANK);
4148 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4149 CRTC_STATE_VACTIVE);
dc6e2448
WW		 4150
4151 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4152 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4153 union dmub_hw_lock_flags hw_locks = { 0 };
4154 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4155
4156 hw_locks.bits.lock_dig = 1;
4157 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4158
4159 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4160 false,
4161 &hw_locks,
4162 &inst_flags);
4163 } else
4164 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4165 pipe_ctx->stream_res.tg);
4166 }
4167
4562236b 4168 /* Set Test Pattern state */
d0778ebf 4169 link->test_pattern_enabled = true;
4562236b
HW		 4170 }
4171
4172 return true;
4173}
07c84c7a 4174
d0778ebf 4175void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
07c84c7a
DW		 4176{
4177 unsigned char mstmCntl;
4178
4179 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4180 if (enable)
4181 mstmCntl |= DP_MST_EN;
4182 else
4183 mstmCntl &= (~DP_MST_EN);
4184
4185 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4186}
6fbefb84 4187
0b226322
DG		 4188void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4189{
4190 union dpcd_edp_config edp_config_set;
4191 bool panel_mode_edp = false;
4192
4193 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4194
4195 if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4196
4197 switch (panel_mode) {
4198 case DP_PANEL_MODE_EDP:
4199 case DP_PANEL_MODE_SPECIAL:
4200 panel_mode_edp = true;
4201 break;
4202
4203 default:
4204 break;
4205 }
4206
4207 /*set edp panel mode in receiver*/
4208 core_link_read_dpcd(
4209 link,
4210 DP_EDP_CONFIGURATION_SET,
4211 &edp_config_set.raw,
4212 sizeof(edp_config_set.raw));
4213
4214 if (edp_config_set.bits.PANEL_MODE_EDP
4215 != panel_mode_edp) {
4216 enum ddc_result result = DDC_RESULT_UNKNOWN;
4217
4218 edp_config_set.bits.PANEL_MODE_EDP =
4219 panel_mode_edp;
4220 result = core_link_write_dpcd(
4221 link,
4222 DP_EDP_CONFIGURATION_SET,
4223 &edp_config_set.raw,
4224 sizeof(edp_config_set.raw));
4225
4226 ASSERT(result == DDC_RESULT_SUCESSFULL);
4227 }
4228 }
4229 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4230 "eDP panel mode enabled: %d \n",
4231 link->link_index,
4232 link->dpcd_caps.panel_mode_edp,
4233 panel_mode_edp);
4234}
4235
4236enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4237{
4238 /* We need to explicitly check that connector
4239 * is not DP. Some Travis_VGA get reported
4240 * by video bios as DP.
4241 */
4242 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4243
4244 switch (link->dpcd_caps.branch_dev_id) {
df3b7e32
QZ		 4245 case DP_BRANCH_DEVICE_ID_0022B9:
4246 /* alternate scrambler reset is required for Travis
4247 * for the case when external chip does not
4248 * provide sink device id, alternate scrambler
4249 * scheme will be overriden later by querying
4250 * Encoder features
4251 */
0b226322
DG		 4252 if (strncmp(
4253 link->dpcd_caps.branch_dev_name,
4254 DP_VGA_LVDS_CONVERTER_ID_2,
4255 sizeof(
4256 link->dpcd_caps.
4257 branch_dev_name)) == 0) {
4258 return DP_PANEL_MODE_SPECIAL;
4259 }
4260 break;
df3b7e32
QZ		 4261 case DP_BRANCH_DEVICE_ID_00001A:
4262 /* alternate scrambler reset is required for Travis
4263 * for the case when external chip does not provide
4264 * sink device id, alternate scrambler scheme will
4265 * be overriden later by querying Encoder feature
4266 */
0b226322
DG		 4267 if (strncmp(link->dpcd_caps.branch_dev_name,
4268 DP_VGA_LVDS_CONVERTER_ID_3,
4269 sizeof(
4270 link->dpcd_caps.
4271 branch_dev_name)) == 0) {
4272 return DP_PANEL_MODE_SPECIAL;
4273 }
4274 break;
4275 default:
4276 break;
4277 }
4278 }
4279
4280 if (link->dpcd_caps.panel_mode_edp) {
4281 return DP_PANEL_MODE_EDP;
4282 }
4283
4284 return DP_PANEL_MODE_DEFAULT;
4285}
4286
97bda032
HW		 4287void dp_set_fec_ready(struct dc_link *link, bool ready)
4288{
4289 /* FEC has to be "set ready" before the link training.
4290 * The policy is to always train with FEC
4291 * if the sink supports it and leave it enabled on link.
4292 * If FEC is not supported, disable it.
4293 */
4294 struct link_encoder *link_enc = link->link_enc;
4295 uint8_t fec_config = 0;
4296
e6b11b43 4297 if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
97bda032
HW		 4298 return;
4299
4300 if (link_enc->funcs->fec_set_ready &&
4301 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
008a4016 4302 if (ready) {
97bda032
HW		 4303 fec_config = 1;
4304 if (core_link_write_dpcd(link,
4305 DP_FEC_CONFIGURATION,
4306 &fec_config,
4307 sizeof(fec_config)) == DC_OK) {
4308 link_enc->funcs->fec_set_ready(link_enc, true);
4309 link->fec_state = dc_link_fec_ready;
4310 } else {
d68a7454
NC		 4311 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4312 link->fec_state = dc_link_fec_not_ready;
97bda032
HW		 4313 dm_error("dpcd write failed to set fec_ready");
4314 }
008a4016 4315 } else if (link->fec_state == dc_link_fec_ready) {
97bda032
HW		 4316 fec_config = 0;
4317 core_link_write_dpcd(link,
4318 DP_FEC_CONFIGURATION,
4319 &fec_config,
4320 sizeof(fec_config));
4321 link->link_enc->funcs->fec_set_ready(
4322 link->link_enc, false);
4323 link->fec_state = dc_link_fec_not_ready;
4324 }
4325 }
4326}
4327
4328void dp_set_fec_enable(struct dc_link *link, bool enable)
4329{
4330 struct link_encoder *link_enc = link->link_enc;
4331
e6b11b43 4332 if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
97bda032
HW		 4333 return;
4334
4335 if (link_enc->funcs->fec_set_enable &&
4336 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4337 if (link->fec_state == dc_link_fec_ready && enable) {
fa11d3c9
LHM		 4338 /* Accord to DP spec, FEC enable sequence can first
4339 * be transmitted anytime after 1000 LL codes have
4340 * been transmitted on the link after link training
4341 * completion. Using 1 lane RBR should have the maximum
4342 * time for transmitting 1000 LL codes which is 6.173 us.
4343 * So use 7 microseconds delay instead.
4344 */
4345 udelay(7);
97bda032
HW		 4346 link_enc->funcs->fec_set_enable(link_enc, true);
4347 link->fec_state = dc_link_fec_enabled;
4348 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4349 link_enc->funcs->fec_set_enable(link_enc, false);
4350 link->fec_state = dc_link_fec_ready;
4351 }
4352 }
4353}
6fbefb84 4354
96577cf8
HW		 4355void dpcd_set_source_specific_data(struct dc_link *link)
4356{
0136684f
CH		 4357 if (!link->dc->vendor_signature.is_valid) {
4358 struct dpcd_amd_signature amd_signature;
4359 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4360 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4361 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4362 amd_signature.device_id_byte1 =
4363 (uint8_t)(link->ctx->asic_id.chip_id);
4364 amd_signature.device_id_byte2 =
4365 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4366 memset(&amd_signature.zero, 0, 4);
4367 amd_signature.dce_version =
4368 (uint8_t)(link->ctx->dce_version);
4369 amd_signature.dal_version_byte1 = 0x0; // needed? where to get?
4370 amd_signature.dal_version_byte2 = 0x0; // needed? where to get?
4371
4372 core_link_write_dpcd(link, DP_SOURCE_OUI,
4373 (uint8_t *)(&amd_signature),
4374 sizeof(amd_signature));
4375
4376 } else {
4377 core_link_write_dpcd(link, DP_SOURCE_OUI,
4378 link->dc->vendor_signature.data.raw,
4379 sizeof(link->dc->vendor_signature.data.raw));
4380 }
96577cf8
HW		 4381}
4382
4383bool dc_link_set_backlight_level_nits(struct dc_link *link,
4384 bool isHDR,
4385 uint32_t backlight_millinits,
4386 uint32_t transition_time_in_ms)
4387{
4388 struct dpcd_source_backlight_set dpcd_backlight_set;
4389 uint8_t backlight_control = isHDR ? 1 : 0;
4390
4391 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4392 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4393 return false;
4394
4395 // OLEDs have no PWM, they can only use AUX
4396 if (link->dpcd_sink_ext_caps.bits.oled == 1)
4397 backlight_control = 1;
4398
4399 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4400 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4401
4402
4403 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4404 (uint8_t *)(&dpcd_backlight_set),
4405 sizeof(dpcd_backlight_set)) != DC_OK)
4406 return false;
4407
4408 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4409 &backlight_control, 1) != DC_OK)
4410 return false;
4411
4412 return true;
4413}
4414
4415bool dc_link_get_backlight_level_nits(struct dc_link *link,
4416 uint32_t *backlight_millinits_avg,
4417 uint32_t *backlight_millinits_peak)
4418{
4419 union dpcd_source_backlight_get dpcd_backlight_get;
4420
4421 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4422
4423 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4424 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4425 return false;
4426
16697cf3 4427 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
96577cf8 4428 dpcd_backlight_get.raw,
16697cf3 4429 sizeof(union dpcd_source_backlight_get)) != DC_OK)
96577cf8
HW		 4430 return false;
4431
4432 *backlight_millinits_avg =
4433 dpcd_backlight_get.bytes.backlight_millinits_avg;
4434 *backlight_millinits_peak =
4435 dpcd_backlight_get.bytes.backlight_millinits_peak;
4436
4437 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4438 if (*backlight_millinits_avg == 0 ||
4439 *backlight_millinits_avg > *backlight_millinits_peak)
4440 return false;
4441
4442 return true;
4443}
4444
4445bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4446{
4447 uint8_t backlight_enable = enable ? 1 : 0;
4448
4449 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4450 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4451 return false;
4452
4453 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4454 &backlight_enable, 1) != DC_OK)
4455 return false;
4456
4457 return true;
4458}
4459
4460// we read default from 0x320 because we expect BIOS wrote it there
4461// regular get_backlight_nit reads from panel set at 0x326
4462bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4463{
4464 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4465 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4466 return false;
4467
16697cf3 4468 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
96577cf8 4469 (uint8_t *) backlight_millinits,
16697cf3 4470 sizeof(uint32_t)) != DC_OK)
96577cf8
HW		 4471 return false;
4472
4473 return true;
4474}
4475
4476bool dc_link_set_default_brightness_aux(struct dc_link *link)
4477{
4478 uint32_t default_backlight;
4479
4480 if (link &&
4481 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4482 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4483 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4484 default_backlight = 150000;
4485 // if < 5 nits or > 5000, it might be wrong readback
4486 if (default_backlight < 5000 || default_backlight > 5000000)
4487 default_backlight = 150000; //
4488
4489 return dc_link_set_backlight_level_nits(link, true,
4490 default_backlight, 0);
4491 }
4492 return false;
4493}
Linux 6.x block layer and io_uring tree(s)