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4562236b HW |
1 | /* Copyright 2015 Advanced Micro Devices, Inc. */ |
2 | #include "dm_services.h" | |
3 | #include "dc.h" | |
4 | #include "dc_link_dp.h" | |
5 | #include "dm_helpers.h" | |
7f93c1de | 6 | #include "opp.h" |
97bda032 | 7 | #include "dsc.h" |
6fbefb84 | 8 | #include "resource.h" |
4562236b HW |
9 | |
10 | #include "inc/core_types.h" | |
11 | #include "link_hwss.h" | |
12 | #include "dc_link_ddc.h" | |
13 | #include "core_status.h" | |
14 | #include "dpcd_defs.h" | |
15 | ||
529cad0f | 16 | #include "resource.h" |
1296423b BL |
17 | #define DC_LOGGER \ |
18 | link->ctx->logger | |
4562236b | 19 | |
8e5100a5 | 20 | |
64c12b73 | 21 | #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 |
8e5100a5 | 22 | |
4562236b HW |
23 | /* maximum pre emphasis level allowed for each voltage swing level*/ |
24 | static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = { | |
25 | PRE_EMPHASIS_LEVEL3, | |
26 | PRE_EMPHASIS_LEVEL2, | |
27 | PRE_EMPHASIS_LEVEL1, | |
28 | PRE_EMPHASIS_DISABLED }; | |
29 | ||
30 | enum { | |
31 | POST_LT_ADJ_REQ_LIMIT = 6, | |
32 | POST_LT_ADJ_REQ_TIMEOUT = 200 | |
33 | }; | |
34 | ||
35 | enum { | |
36 | LINK_TRAINING_MAX_RETRY_COUNT = 5, | |
37 | /* to avoid infinite loop where-in the receiver | |
38 | * switches between different VS | |
39 | */ | |
40 | LINK_TRAINING_MAX_CR_RETRY = 100 | |
41 | }; | |
42 | ||
04e21292 DA |
43 | static bool decide_fallback_link_setting( |
44 | struct dc_link_settings initial_link_settings, | |
45 | struct dc_link_settings *current_link_setting, | |
46 | enum link_training_result training_result); | |
9a6a8075 | 47 | static struct dc_link_settings get_common_supported_link_settings( |
04e21292 DA |
48 | struct dc_link_settings link_setting_a, |
49 | struct dc_link_settings link_setting_b); | |
50 | ||
e0a6440a | 51 | static uint32_t get_training_aux_rd_interval( |
d0778ebf | 52 | struct dc_link *link, |
4562236b HW |
53 | uint32_t default_wait_in_micro_secs) |
54 | { | |
d6d36b55 NC |
55 | union training_aux_rd_interval training_rd_interval; |
56 | ||
57 | memset(&training_rd_interval, 0, sizeof(training_rd_interval)); | |
4562236b HW |
58 | |
59 | /* overwrite the delay if rev > 1.1*/ | |
60 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { | |
61 | /* DP 1.2 or later - retrieve delay through | |
62 | * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */ | |
63 | core_link_read_dpcd( | |
64 | link, | |
3a340294 | 65 | DP_TRAINING_AUX_RD_INTERVAL, |
4562236b HW |
66 | (uint8_t *)&training_rd_interval, |
67 | sizeof(training_rd_interval)); | |
68 | ||
69 | if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL) | |
e0a6440a | 70 | default_wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000; |
4562236b HW |
71 | } |
72 | ||
e0a6440a DG |
73 | return default_wait_in_micro_secs; |
74 | } | |
75 | ||
76 | static void wait_for_training_aux_rd_interval( | |
77 | struct dc_link *link, | |
78 | uint32_t wait_in_micro_secs) | |
79 | { | |
80 | udelay(wait_in_micro_secs); | |
4562236b | 81 | |
1296423b | 82 | DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n", |
4562236b | 83 | __func__, |
e0a6440a | 84 | wait_in_micro_secs); |
4562236b HW |
85 | } |
86 | ||
87 | static void dpcd_set_training_pattern( | |
d0778ebf | 88 | struct dc_link *link, |
4562236b HW |
89 | union dpcd_training_pattern dpcd_pattern) |
90 | { | |
91 | core_link_write_dpcd( | |
92 | link, | |
3a340294 | 93 | DP_TRAINING_PATTERN_SET, |
4562236b HW |
94 | &dpcd_pattern.raw, |
95 | 1); | |
96 | ||
1296423b | 97 | DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n", |
4562236b | 98 | __func__, |
3a340294 | 99 | DP_TRAINING_PATTERN_SET, |
4562236b HW |
100 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET); |
101 | } | |
102 | ||
e0a6440a | 103 | static enum dc_dp_training_pattern get_supported_tp(struct dc_link *link) |
16b6253a | 104 | { |
e0a6440a | 105 | enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2; |
16b6253a | 106 | struct encoder_feature_support *features = &link->link_enc->features; |
107 | struct dpcd_caps *dpcd_caps = &link->dpcd_caps; | |
108 | ||
109 | if (features->flags.bits.IS_TPS3_CAPABLE) | |
e0a6440a | 110 | highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3; |
16b6253a | 111 | |
112 | if (features->flags.bits.IS_TPS4_CAPABLE) | |
e0a6440a | 113 | highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4; |
16b6253a | 114 | |
115 | if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED && | |
e0a6440a DG |
116 | highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4) |
117 | return DP_TRAINING_PATTERN_SEQUENCE_4; | |
16b6253a | 118 | |
119 | if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED && | |
e0a6440a DG |
120 | highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3) |
121 | return DP_TRAINING_PATTERN_SEQUENCE_3; | |
16b6253a | 122 | |
e0a6440a | 123 | return DP_TRAINING_PATTERN_SEQUENCE_2; |
16b6253a | 124 | } |
125 | ||
4562236b | 126 | static void dpcd_set_link_settings( |
d0778ebf | 127 | struct dc_link *link, |
4562236b HW |
128 | const struct link_training_settings *lt_settings) |
129 | { | |
8628d02f | 130 | uint8_t rate; |
4562236b | 131 | |
9a6a8075 HW |
132 | union down_spread_ctrl downspread = { {0} }; |
133 | union lane_count_set lane_count_set = { {0} }; | |
e0a6440a | 134 | enum dc_dp_training_pattern dp_tr_pattern; |
4562236b HW |
135 | |
136 | downspread.raw = (uint8_t) | |
137 | (lt_settings->link_settings.link_spread); | |
138 | ||
139 | lane_count_set.bits.LANE_COUNT_SET = | |
140 | lt_settings->link_settings.lane_count; | |
141 | ||
e0a6440a | 142 | lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing; |
16b6253a | 143 | lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0; |
144 | ||
e0a6440a DG |
145 | dp_tr_pattern = get_supported_tp(link); |
146 | ||
147 | if (dp_tr_pattern != DP_TRAINING_PATTERN_SEQUENCE_4) { | |
16b6253a | 148 | lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = |
149 | link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED; | |
150 | } | |
4562236b | 151 | |
3a340294 | 152 | core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, |
e0a6440a | 153 | &downspread.raw, sizeof(downspread)); |
4562236b | 154 | |
8628d02f | 155 | core_link_write_dpcd(link, DP_LANE_COUNT_SET, |
e0a6440a | 156 | &lane_count_set.raw, 1); |
8628d02f | 157 | |
b03a599b | 158 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 && |
8628d02f JP |
159 | lt_settings->link_settings.use_link_rate_set == true) { |
160 | rate = 0; | |
161 | core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1); | |
b03a599b | 162 | core_link_write_dpcd(link, DP_LINK_RATE_SET, |
8628d02f JP |
163 | <_settings->link_settings.link_rate_set, 1); |
164 | } else { | |
165 | rate = (uint8_t) (lt_settings->link_settings.link_rate); | |
166 | core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1); | |
b03a599b DL |
167 | } |
168 | ||
8628d02f | 169 | if (rate) { |
e0a6440a | 170 | DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n", |
8628d02f JP |
171 | __func__, |
172 | DP_LINK_BW_SET, | |
173 | lt_settings->link_settings.link_rate, | |
174 | DP_LANE_COUNT_SET, | |
175 | lt_settings->link_settings.lane_count, | |
e0a6440a | 176 | lt_settings->enhanced_framing, |
8628d02f JP |
177 | DP_DOWNSPREAD_CTRL, |
178 | lt_settings->link_settings.link_spread); | |
179 | } else { | |
e0a6440a | 180 | DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n", |
8628d02f JP |
181 | __func__, |
182 | DP_LINK_RATE_SET, | |
183 | lt_settings->link_settings.link_rate_set, | |
184 | DP_LANE_COUNT_SET, | |
185 | lt_settings->link_settings.lane_count, | |
e0a6440a | 186 | lt_settings->enhanced_framing, |
8628d02f JP |
187 | DP_DOWNSPREAD_CTRL, |
188 | lt_settings->link_settings.link_spread); | |
189 | } | |
4562236b HW |
190 | } |
191 | ||
192 | static enum dpcd_training_patterns | |
e0a6440a | 193 | dc_dp_training_pattern_to_dpcd_training_pattern( |
d0778ebf | 194 | struct dc_link *link, |
e0a6440a | 195 | enum dc_dp_training_pattern pattern) |
4562236b HW |
196 | { |
197 | enum dpcd_training_patterns dpcd_tr_pattern = | |
198 | DPCD_TRAINING_PATTERN_VIDEOIDLE; | |
199 | ||
200 | switch (pattern) { | |
e0a6440a | 201 | case DP_TRAINING_PATTERN_SEQUENCE_1: |
4562236b HW |
202 | dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1; |
203 | break; | |
e0a6440a | 204 | case DP_TRAINING_PATTERN_SEQUENCE_2: |
4562236b HW |
205 | dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2; |
206 | break; | |
e0a6440a | 207 | case DP_TRAINING_PATTERN_SEQUENCE_3: |
4562236b HW |
208 | dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3; |
209 | break; | |
e0a6440a | 210 | case DP_TRAINING_PATTERN_SEQUENCE_4: |
4562236b HW |
211 | dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4; |
212 | break; | |
213 | default: | |
214 | ASSERT(0); | |
1296423b | 215 | DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n", |
4562236b HW |
216 | __func__, pattern); |
217 | break; | |
218 | } | |
219 | ||
220 | return dpcd_tr_pattern; | |
4562236b HW |
221 | } |
222 | ||
64c12b73 | 223 | static inline bool is_repeater(struct dc_link *link, uint32_t offset) |
224 | { | |
225 | return (!link->is_lttpr_mode_transparent && offset != 0); | |
226 | } | |
227 | ||
4562236b | 228 | static void dpcd_set_lt_pattern_and_lane_settings( |
d0778ebf | 229 | struct dc_link *link, |
4562236b | 230 | const struct link_training_settings *lt_settings, |
64c12b73 | 231 | enum dc_dp_training_pattern pattern, |
232 | uint32_t offset) | |
4562236b | 233 | { |
9a6a8075 | 234 | union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } }; |
64c12b73 | 235 | |
236 | uint32_t dpcd_base_lt_offset; | |
237 | ||
4562236b | 238 | uint8_t dpcd_lt_buffer[5] = {0}; |
9a6a8075 | 239 | union dpcd_training_pattern dpcd_pattern = { {0} }; |
4562236b HW |
240 | uint32_t lane; |
241 | uint32_t size_in_bytes; | |
242 | bool edp_workaround = false; /* TODO link_prop.INTERNAL */ | |
64c12b73 | 243 | dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET; |
244 | ||
245 | if (is_repeater(link, offset)) | |
246 | dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 + | |
247 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); | |
4562236b HW |
248 | |
249 | /***************************************************************** | |
250 | * DpcdAddress_TrainingPatternSet | |
251 | *****************************************************************/ | |
252 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET = | |
e0a6440a | 253 | dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern); |
4562236b | 254 | |
64c12b73 | 255 | dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET] |
4562236b HW |
256 | = dpcd_pattern.raw; |
257 | ||
460adc6b | 258 | if (is_repeater(link, offset)) { |
259 | DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n", | |
260 | __func__, | |
261 | offset, | |
262 | dpcd_base_lt_offset, | |
263 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET); | |
264 | } else { | |
265 | DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n", | |
266 | __func__, | |
267 | dpcd_base_lt_offset, | |
268 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET); | |
269 | } | |
4562236b HW |
270 | /***************************************************************** |
271 | * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set | |
272 | *****************************************************************/ | |
273 | for (lane = 0; lane < | |
274 | (uint32_t)(lt_settings->link_settings.lane_count); lane++) { | |
275 | ||
276 | dpcd_lane[lane].bits.VOLTAGE_SWING_SET = | |
277 | (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING); | |
278 | dpcd_lane[lane].bits.PRE_EMPHASIS_SET = | |
279 | (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS); | |
280 | ||
281 | dpcd_lane[lane].bits.MAX_SWING_REACHED = | |
282 | (lt_settings->lane_settings[lane].VOLTAGE_SWING == | |
283 | VOLTAGE_SWING_MAX_LEVEL ? 1 : 0); | |
284 | dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED = | |
285 | (lt_settings->lane_settings[lane].PRE_EMPHASIS == | |
286 | PRE_EMPHASIS_MAX_LEVEL ? 1 : 0); | |
287 | } | |
288 | ||
64c12b73 | 289 | /* concatenate everything into one buffer*/ |
4562236b HW |
290 | |
291 | size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]); | |
292 | ||
293 | // 0x00103 - 0x00102 | |
294 | memmove( | |
64c12b73 | 295 | &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET], |
4562236b HW |
296 | dpcd_lane, |
297 | size_in_bytes); | |
298 | ||
460adc6b | 299 | if (is_repeater(link, offset)) { |
300 | DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" | |
301 | " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", | |
302 | __func__, | |
303 | offset, | |
304 | dpcd_base_lt_offset, | |
305 | dpcd_lane[0].bits.VOLTAGE_SWING_SET, | |
306 | dpcd_lane[0].bits.PRE_EMPHASIS_SET, | |
307 | dpcd_lane[0].bits.MAX_SWING_REACHED, | |
308 | dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); | |
309 | } else { | |
310 | DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", | |
311 | __func__, | |
312 | dpcd_base_lt_offset, | |
313 | dpcd_lane[0].bits.VOLTAGE_SWING_SET, | |
314 | dpcd_lane[0].bits.PRE_EMPHASIS_SET, | |
315 | dpcd_lane[0].bits.MAX_SWING_REACHED, | |
316 | dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); | |
317 | } | |
4562236b HW |
318 | if (edp_workaround) { |
319 | /* for eDP write in 2 parts because the 5-byte burst is | |
320 | * causing issues on some eDP panels (EPR#366724) | |
321 | */ | |
322 | core_link_write_dpcd( | |
323 | link, | |
3a340294 | 324 | DP_TRAINING_PATTERN_SET, |
4562236b | 325 | &dpcd_pattern.raw, |
9a6a8075 | 326 | sizeof(dpcd_pattern.raw)); |
4562236b HW |
327 | |
328 | core_link_write_dpcd( | |
329 | link, | |
3a340294 | 330 | DP_TRAINING_LANE0_SET, |
4562236b HW |
331 | (uint8_t *)(dpcd_lane), |
332 | size_in_bytes); | |
333 | ||
334 | } else | |
335 | /* write it all in (1 + number-of-lanes)-byte burst*/ | |
336 | core_link_write_dpcd( | |
337 | link, | |
338 | dpcd_base_lt_offset, | |
339 | dpcd_lt_buffer, | |
9a6a8075 | 340 | size_in_bytes + sizeof(dpcd_pattern.raw)); |
4562236b | 341 | |
d0778ebf | 342 | link->cur_lane_setting = lt_settings->lane_settings[0]; |
4562236b HW |
343 | } |
344 | ||
345 | static bool is_cr_done(enum dc_lane_count ln_count, | |
346 | union lane_status *dpcd_lane_status) | |
347 | { | |
348 | bool done = true; | |
349 | uint32_t lane; | |
350 | /*LANEx_CR_DONE bits All 1's?*/ | |
351 | for (lane = 0; lane < (uint32_t)(ln_count); lane++) { | |
352 | if (!dpcd_lane_status[lane].bits.CR_DONE_0) | |
353 | done = false; | |
354 | } | |
355 | return done; | |
356 | ||
357 | } | |
358 | ||
359 | static bool is_ch_eq_done(enum dc_lane_count ln_count, | |
360 | union lane_status *dpcd_lane_status, | |
361 | union lane_align_status_updated *lane_status_updated) | |
362 | { | |
363 | bool done = true; | |
364 | uint32_t lane; | |
365 | if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE) | |
366 | done = false; | |
367 | else { | |
368 | for (lane = 0; lane < (uint32_t)(ln_count); lane++) { | |
369 | if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 || | |
370 | !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0) | |
371 | done = false; | |
372 | } | |
373 | } | |
374 | return done; | |
375 | ||
376 | } | |
377 | ||
378 | static void update_drive_settings( | |
379 | struct link_training_settings *dest, | |
380 | struct link_training_settings src) | |
381 | { | |
382 | uint32_t lane; | |
383 | for (lane = 0; lane < src.link_settings.lane_count; lane++) { | |
e0a6440a DG |
384 | if (dest->voltage_swing == NULL) |
385 | dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING; | |
386 | else | |
387 | dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing; | |
388 | ||
389 | if (dest->pre_emphasis == NULL) | |
390 | dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS; | |
391 | else | |
392 | dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis; | |
393 | ||
394 | if (dest->post_cursor2 == NULL) | |
395 | dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2; | |
396 | else | |
397 | dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2; | |
4562236b HW |
398 | } |
399 | } | |
400 | ||
401 | static uint8_t get_nibble_at_index(const uint8_t *buf, | |
402 | uint32_t index) | |
403 | { | |
404 | uint8_t nibble; | |
405 | nibble = buf[index / 2]; | |
406 | ||
407 | if (index % 2) | |
408 | nibble >>= 4; | |
409 | else | |
410 | nibble &= 0x0F; | |
411 | ||
412 | return nibble; | |
413 | } | |
414 | ||
415 | static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing( | |
416 | enum dc_voltage_swing voltage) | |
417 | { | |
418 | enum dc_pre_emphasis pre_emphasis; | |
419 | pre_emphasis = PRE_EMPHASIS_MAX_LEVEL; | |
420 | ||
421 | if (voltage <= VOLTAGE_SWING_MAX_LEVEL) | |
422 | pre_emphasis = voltage_swing_to_pre_emphasis[voltage]; | |
423 | ||
424 | return pre_emphasis; | |
425 | ||
426 | } | |
427 | ||
428 | static void find_max_drive_settings( | |
429 | const struct link_training_settings *link_training_setting, | |
430 | struct link_training_settings *max_lt_setting) | |
431 | { | |
432 | uint32_t lane; | |
433 | struct dc_lane_settings max_requested; | |
434 | ||
435 | max_requested.VOLTAGE_SWING = | |
436 | link_training_setting-> | |
437 | lane_settings[0].VOLTAGE_SWING; | |
438 | max_requested.PRE_EMPHASIS = | |
439 | link_training_setting-> | |
440 | lane_settings[0].PRE_EMPHASIS; | |
441 | /*max_requested.postCursor2 = | |
442 | * link_training_setting->laneSettings[0].postCursor2;*/ | |
443 | ||
444 | /* Determine what the maximum of the requested settings are*/ | |
445 | for (lane = 1; lane < link_training_setting->link_settings.lane_count; | |
446 | lane++) { | |
447 | if (link_training_setting->lane_settings[lane].VOLTAGE_SWING > | |
448 | max_requested.VOLTAGE_SWING) | |
449 | ||
450 | max_requested.VOLTAGE_SWING = | |
451 | link_training_setting-> | |
452 | lane_settings[lane].VOLTAGE_SWING; | |
453 | ||
454 | if (link_training_setting->lane_settings[lane].PRE_EMPHASIS > | |
455 | max_requested.PRE_EMPHASIS) | |
456 | max_requested.PRE_EMPHASIS = | |
457 | link_training_setting-> | |
458 | lane_settings[lane].PRE_EMPHASIS; | |
459 | ||
460 | /* | |
461 | if (link_training_setting->laneSettings[lane].postCursor2 > | |
462 | max_requested.postCursor2) | |
463 | { | |
464 | max_requested.postCursor2 = | |
465 | link_training_setting->laneSettings[lane].postCursor2; | |
466 | } | |
467 | */ | |
468 | } | |
469 | ||
470 | /* make sure the requested settings are | |
471 | * not higher than maximum settings*/ | |
472 | if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL) | |
473 | max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL; | |
474 | ||
475 | if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL) | |
476 | max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL; | |
477 | /* | |
478 | if (max_requested.postCursor2 > PostCursor2_MaxLevel) | |
479 | max_requested.postCursor2 = PostCursor2_MaxLevel; | |
480 | */ | |
481 | ||
482 | /* make sure the pre-emphasis matches the voltage swing*/ | |
483 | if (max_requested.PRE_EMPHASIS > | |
484 | get_max_pre_emphasis_for_voltage_swing( | |
485 | max_requested.VOLTAGE_SWING)) | |
486 | max_requested.PRE_EMPHASIS = | |
487 | get_max_pre_emphasis_for_voltage_swing( | |
488 | max_requested.VOLTAGE_SWING); | |
489 | ||
490 | /* | |
491 | * Post Cursor2 levels are completely independent from | |
492 | * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels | |
493 | * can only be applied to each allowable combination of voltage | |
494 | * swing and pre-emphasis levels */ | |
495 | /* if ( max_requested.postCursor2 > | |
496 | * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing)) | |
497 | * max_requested.postCursor2 = | |
498 | * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing); | |
499 | */ | |
500 | ||
501 | max_lt_setting->link_settings.link_rate = | |
502 | link_training_setting->link_settings.link_rate; | |
503 | max_lt_setting->link_settings.lane_count = | |
504 | link_training_setting->link_settings.lane_count; | |
505 | max_lt_setting->link_settings.link_spread = | |
506 | link_training_setting->link_settings.link_spread; | |
507 | ||
508 | for (lane = 0; lane < | |
509 | link_training_setting->link_settings.lane_count; | |
510 | lane++) { | |
511 | max_lt_setting->lane_settings[lane].VOLTAGE_SWING = | |
512 | max_requested.VOLTAGE_SWING; | |
513 | max_lt_setting->lane_settings[lane].PRE_EMPHASIS = | |
514 | max_requested.PRE_EMPHASIS; | |
515 | /*max_lt_setting->laneSettings[lane].postCursor2 = | |
516 | * max_requested.postCursor2; | |
517 | */ | |
518 | } | |
519 | ||
520 | } | |
521 | ||
522 | static void get_lane_status_and_drive_settings( | |
d0778ebf | 523 | struct dc_link *link, |
4562236b HW |
524 | const struct link_training_settings *link_training_setting, |
525 | union lane_status *ln_status, | |
526 | union lane_align_status_updated *ln_status_updated, | |
64c12b73 | 527 | struct link_training_settings *req_settings, |
528 | uint32_t offset) | |
4562236b | 529 | { |
64c12b73 | 530 | unsigned int lane01_status_address = DP_LANE0_1_STATUS; |
531 | uint8_t lane_adjust_offset = 4; | |
532 | unsigned int lane01_adjust_address; | |
4562236b | 533 | uint8_t dpcd_buf[6] = {0}; |
9a6a8075 HW |
534 | union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; |
535 | struct link_training_settings request_settings = { {0} }; | |
4562236b HW |
536 | uint32_t lane; |
537 | ||
538 | memset(req_settings, '\0', sizeof(struct link_training_settings)); | |
539 | ||
64c12b73 | 540 | if (is_repeater(link, offset)) { |
541 | lane01_status_address = | |
542 | DP_LANE0_1_STATUS_PHY_REPEATER1 + | |
543 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); | |
544 | lane_adjust_offset = 3; | |
545 | } | |
546 | ||
4562236b HW |
547 | core_link_read_dpcd( |
548 | link, | |
64c12b73 | 549 | lane01_status_address, |
4562236b HW |
550 | (uint8_t *)(dpcd_buf), |
551 | sizeof(dpcd_buf)); | |
552 | ||
553 | for (lane = 0; lane < | |
554 | (uint32_t)(link_training_setting->link_settings.lane_count); | |
555 | lane++) { | |
556 | ||
557 | ln_status[lane].raw = | |
558 | get_nibble_at_index(&dpcd_buf[0], lane); | |
559 | dpcd_lane_adjust[lane].raw = | |
64c12b73 | 560 | get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane); |
4562236b HW |
561 | } |
562 | ||
563 | ln_status_updated->raw = dpcd_buf[2]; | |
564 | ||
460adc6b | 565 | if (is_repeater(link, offset)) { |
566 | DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" | |
567 | " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ", | |
568 | __func__, | |
569 | offset, | |
570 | lane01_status_address, dpcd_buf[0], | |
571 | lane01_status_address + 1, dpcd_buf[1]); | |
572 | } else { | |
573 | DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ", | |
574 | __func__, | |
575 | lane01_status_address, dpcd_buf[0], | |
576 | lane01_status_address + 1, dpcd_buf[1]); | |
577 | } | |
64c12b73 | 578 | lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1; |
579 | ||
580 | if (is_repeater(link, offset)) | |
581 | lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 + | |
582 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); | |
4562236b | 583 | |
460adc6b | 584 | if (is_repeater(link, offset)) { |
585 | DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" | |
586 | " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n", | |
587 | __func__, | |
588 | offset, | |
589 | lane01_adjust_address, | |
590 | dpcd_buf[lane_adjust_offset], | |
591 | lane01_adjust_address + 1, | |
592 | dpcd_buf[lane_adjust_offset + 1]); | |
593 | } else { | |
594 | DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n", | |
595 | __func__, | |
596 | lane01_adjust_address, | |
597 | dpcd_buf[lane_adjust_offset], | |
598 | lane01_adjust_address + 1, | |
599 | dpcd_buf[lane_adjust_offset + 1]); | |
600 | } | |
4562236b HW |
601 | |
602 | /*copy to req_settings*/ | |
603 | request_settings.link_settings.lane_count = | |
604 | link_training_setting->link_settings.lane_count; | |
605 | request_settings.link_settings.link_rate = | |
606 | link_training_setting->link_settings.link_rate; | |
607 | request_settings.link_settings.link_spread = | |
608 | link_training_setting->link_settings.link_spread; | |
609 | ||
610 | for (lane = 0; lane < | |
611 | (uint32_t)(link_training_setting->link_settings.lane_count); | |
612 | lane++) { | |
613 | ||
614 | request_settings.lane_settings[lane].VOLTAGE_SWING = | |
615 | (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits. | |
616 | VOLTAGE_SWING_LANE); | |
617 | request_settings.lane_settings[lane].PRE_EMPHASIS = | |
618 | (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits. | |
619 | PRE_EMPHASIS_LANE); | |
620 | } | |
621 | ||
622 | /*Note: for postcursor2, read adjusted | |
623 | * postcursor2 settings from*/ | |
624 | /*DpcdAddress_AdjustRequestPostCursor2 = | |
625 | *0x020C (not implemented yet)*/ | |
626 | ||
627 | /* we find the maximum of the requested settings across all lanes*/ | |
628 | /* and set this maximum for all lanes*/ | |
629 | find_max_drive_settings(&request_settings, req_settings); | |
630 | ||
631 | /* if post cursor 2 is needed in the future, | |
632 | * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C | |
633 | */ | |
634 | ||
635 | } | |
636 | ||
637 | static void dpcd_set_lane_settings( | |
d0778ebf | 638 | struct dc_link *link, |
64c12b73 | 639 | const struct link_training_settings *link_training_setting, |
640 | uint32_t offset) | |
4562236b HW |
641 | { |
642 | union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}}; | |
643 | uint32_t lane; | |
64c12b73 | 644 | unsigned int lane0_set_address; |
645 | ||
646 | lane0_set_address = DP_TRAINING_LANE0_SET; | |
647 | ||
648 | if (is_repeater(link, offset)) | |
649 | lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 + | |
650 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); | |
4562236b HW |
651 | |
652 | for (lane = 0; lane < | |
653 | (uint32_t)(link_training_setting-> | |
654 | link_settings.lane_count); | |
655 | lane++) { | |
656 | dpcd_lane[lane].bits.VOLTAGE_SWING_SET = | |
657 | (uint8_t)(link_training_setting-> | |
658 | lane_settings[lane].VOLTAGE_SWING); | |
659 | dpcd_lane[lane].bits.PRE_EMPHASIS_SET = | |
660 | (uint8_t)(link_training_setting-> | |
661 | lane_settings[lane].PRE_EMPHASIS); | |
662 | dpcd_lane[lane].bits.MAX_SWING_REACHED = | |
663 | (link_training_setting-> | |
664 | lane_settings[lane].VOLTAGE_SWING == | |
665 | VOLTAGE_SWING_MAX_LEVEL ? 1 : 0); | |
666 | dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED = | |
667 | (link_training_setting-> | |
668 | lane_settings[lane].PRE_EMPHASIS == | |
669 | PRE_EMPHASIS_MAX_LEVEL ? 1 : 0); | |
670 | } | |
671 | ||
672 | core_link_write_dpcd(link, | |
64c12b73 | 673 | lane0_set_address, |
4562236b HW |
674 | (uint8_t *)(dpcd_lane), |
675 | link_training_setting->link_settings.lane_count); | |
676 | ||
677 | /* | |
678 | if (LTSettings.link.rate == LinkRate_High2) | |
679 | { | |
680 | DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0}; | |
681 | for ( uint32_t lane = 0; | |
682 | lane < lane_count_DPMax; lane++) | |
683 | { | |
684 | dpcd_lane2[lane].bits.post_cursor2_set = | |
685 | static_cast<unsigned char>( | |
686 | LTSettings.laneSettings[lane].postCursor2); | |
687 | dpcd_lane2[lane].bits.max_post_cursor2_reached = 0; | |
688 | } | |
689 | m_pDpcdAccessSrv->WriteDpcdData( | |
690 | DpcdAddress_Lane0Set2, | |
691 | reinterpret_cast<unsigned char*>(dpcd_lane2), | |
692 | LTSettings.link.lanes); | |
693 | } | |
694 | */ | |
695 | ||
460adc6b | 696 | if (is_repeater(link, offset)) { |
697 | DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n" | |
698 | " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", | |
699 | __func__, | |
700 | offset, | |
701 | lane0_set_address, | |
702 | dpcd_lane[0].bits.VOLTAGE_SWING_SET, | |
703 | dpcd_lane[0].bits.PRE_EMPHASIS_SET, | |
704 | dpcd_lane[0].bits.MAX_SWING_REACHED, | |
705 | dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); | |
4562236b | 706 | |
460adc6b | 707 | } else { |
708 | DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", | |
709 | __func__, | |
710 | lane0_set_address, | |
711 | dpcd_lane[0].bits.VOLTAGE_SWING_SET, | |
712 | dpcd_lane[0].bits.PRE_EMPHASIS_SET, | |
713 | dpcd_lane[0].bits.MAX_SWING_REACHED, | |
714 | dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); | |
715 | } | |
d0778ebf | 716 | link->cur_lane_setting = link_training_setting->lane_settings[0]; |
4562236b HW |
717 | |
718 | } | |
719 | ||
720 | static bool is_max_vs_reached( | |
721 | const struct link_training_settings *lt_settings) | |
722 | { | |
723 | uint32_t lane; | |
724 | for (lane = 0; lane < | |
725 | (uint32_t)(lt_settings->link_settings.lane_count); | |
726 | lane++) { | |
727 | if (lt_settings->lane_settings[lane].VOLTAGE_SWING | |
728 | == VOLTAGE_SWING_MAX_LEVEL) | |
729 | return true; | |
730 | } | |
731 | return false; | |
732 | ||
733 | } | |
734 | ||
4562236b | 735 | static bool perform_post_lt_adj_req_sequence( |
d0778ebf | 736 | struct dc_link *link, |
4562236b HW |
737 | struct link_training_settings *lt_settings) |
738 | { | |
739 | enum dc_lane_count lane_count = | |
740 | lt_settings->link_settings.lane_count; | |
741 | ||
742 | uint32_t adj_req_count; | |
743 | uint32_t adj_req_timer; | |
744 | bool req_drv_setting_changed; | |
745 | uint32_t lane; | |
746 | ||
747 | req_drv_setting_changed = false; | |
748 | for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT; | |
749 | adj_req_count++) { | |
750 | ||
751 | req_drv_setting_changed = false; | |
752 | ||
753 | for (adj_req_timer = 0; | |
754 | adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT; | |
755 | adj_req_timer++) { | |
756 | ||
757 | struct link_training_settings req_settings; | |
758 | union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; | |
759 | union lane_align_status_updated | |
760 | dpcd_lane_status_updated; | |
761 | ||
762 | get_lane_status_and_drive_settings( | |
763 | link, | |
764 | lt_settings, | |
765 | dpcd_lane_status, | |
766 | &dpcd_lane_status_updated, | |
64c12b73 | 767 | &req_settings, |
768 | DPRX); | |
4562236b HW |
769 | |
770 | if (dpcd_lane_status_updated.bits. | |
771 | POST_LT_ADJ_REQ_IN_PROGRESS == 0) | |
772 | return true; | |
773 | ||
774 | if (!is_cr_done(lane_count, dpcd_lane_status)) | |
775 | return false; | |
776 | ||
777 | if (!is_ch_eq_done( | |
778 | lane_count, | |
779 | dpcd_lane_status, | |
780 | &dpcd_lane_status_updated)) | |
781 | return false; | |
782 | ||
783 | for (lane = 0; lane < (uint32_t)(lane_count); lane++) { | |
784 | ||
785 | if (lt_settings-> | |
786 | lane_settings[lane].VOLTAGE_SWING != | |
787 | req_settings.lane_settings[lane]. | |
788 | VOLTAGE_SWING || | |
789 | lt_settings->lane_settings[lane].PRE_EMPHASIS != | |
790 | req_settings.lane_settings[lane].PRE_EMPHASIS) { | |
791 | ||
792 | req_drv_setting_changed = true; | |
793 | break; | |
794 | } | |
795 | } | |
796 | ||
797 | if (req_drv_setting_changed) { | |
798 | update_drive_settings( | |
9a6a8075 | 799 | lt_settings, req_settings); |
4562236b | 800 | |
d0778ebf | 801 | dc_link_dp_set_drive_settings(link, |
4562236b HW |
802 | lt_settings); |
803 | break; | |
804 | } | |
805 | ||
806 | msleep(1); | |
807 | } | |
808 | ||
809 | if (!req_drv_setting_changed) { | |
1296423b | 810 | DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n", |
4562236b HW |
811 | __func__); |
812 | ||
813 | ASSERT(0); | |
814 | return true; | |
815 | } | |
816 | } | |
1296423b | 817 | DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n", |
4562236b HW |
818 | __func__); |
819 | ||
820 | ASSERT(0); | |
821 | return true; | |
822 | ||
823 | } | |
824 | ||
64c12b73 | 825 | /* Only used for channel equalization */ |
826 | static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval) | |
827 | { | |
828 | unsigned int aux_rd_interval_us = 400; | |
829 | ||
830 | switch (dpcd_aux_read_interval) { | |
831 | case 0x01: | |
832 | aux_rd_interval_us = 400; | |
833 | break; | |
834 | case 0x02: | |
835 | aux_rd_interval_us = 4000; | |
836 | break; | |
837 | case 0x03: | |
838 | aux_rd_interval_us = 8000; | |
839 | break; | |
840 | case 0x04: | |
841 | aux_rd_interval_us = 16000; | |
842 | break; | |
843 | default: | |
844 | break; | |
845 | } | |
846 | ||
847 | return aux_rd_interval_us; | |
848 | } | |
849 | ||
94405cf6 WL |
850 | static enum link_training_result get_cr_failure(enum dc_lane_count ln_count, |
851 | union lane_status *dpcd_lane_status) | |
852 | { | |
853 | enum link_training_result result = LINK_TRAINING_SUCCESS; | |
854 | ||
855 | if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0) | |
856 | result = LINK_TRAINING_CR_FAIL_LANE0; | |
857 | else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0) | |
858 | result = LINK_TRAINING_CR_FAIL_LANE1; | |
859 | else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0) | |
860 | result = LINK_TRAINING_CR_FAIL_LANE23; | |
861 | else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0) | |
862 | result = LINK_TRAINING_CR_FAIL_LANE23; | |
863 | return result; | |
864 | } | |
865 | ||
820e3935 | 866 | static enum link_training_result perform_channel_equalization_sequence( |
d0778ebf | 867 | struct dc_link *link, |
64c12b73 | 868 | struct link_training_settings *lt_settings, |
869 | uint32_t offset) | |
4562236b HW |
870 | { |
871 | struct link_training_settings req_settings; | |
e0a6440a | 872 | enum dc_dp_training_pattern tr_pattern; |
4562236b | 873 | uint32_t retries_ch_eq; |
64c12b73 | 874 | uint32_t wait_time_microsec; |
4562236b | 875 | enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; |
9a6a8075 HW |
876 | union lane_align_status_updated dpcd_lane_status_updated = { {0} }; |
877 | union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } }; | |
4562236b | 878 | |
64c12b73 | 879 | /* Note: also check that TPS4 is a supported feature*/ |
880 | ||
e0a6440a | 881 | tr_pattern = lt_settings->pattern_for_eq; |
4562236b | 882 | |
64c12b73 | 883 | if (is_repeater(link, offset)) |
884 | tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4; | |
885 | ||
886 | dp_set_hw_training_pattern(link, tr_pattern, offset); | |
4562236b HW |
887 | |
888 | for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT; | |
889 | retries_ch_eq++) { | |
890 | ||
64c12b73 | 891 | dp_set_hw_lane_settings(link, lt_settings, offset); |
4562236b HW |
892 | |
893 | /* 2. update DPCD*/ | |
894 | if (!retries_ch_eq) | |
895 | /* EPR #361076 - write as a 5-byte burst, | |
64c12b73 | 896 | * but only for the 1-st iteration |
897 | */ | |
898 | ||
4562236b HW |
899 | dpcd_set_lt_pattern_and_lane_settings( |
900 | link, | |
901 | lt_settings, | |
64c12b73 | 902 | tr_pattern, offset); |
4562236b | 903 | else |
64c12b73 | 904 | dpcd_set_lane_settings(link, lt_settings, offset); |
4562236b HW |
905 | |
906 | /* 3. wait for receiver to lock-on*/ | |
64c12b73 | 907 | wait_time_microsec = lt_settings->eq_pattern_time; |
908 | ||
5fd21b39 | 909 | if (is_repeater(link, offset)) |
64c12b73 | 910 | wait_time_microsec = |
911 | translate_training_aux_read_interval( | |
5fd21b39 | 912 | link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]); |
64c12b73 | 913 | |
914 | wait_for_training_aux_rd_interval( | |
915 | link, | |
916 | wait_time_microsec); | |
4562236b HW |
917 | |
918 | /* 4. Read lane status and requested | |
919 | * drive settings as set by the sink*/ | |
920 | ||
921 | get_lane_status_and_drive_settings( | |
922 | link, | |
923 | lt_settings, | |
924 | dpcd_lane_status, | |
925 | &dpcd_lane_status_updated, | |
64c12b73 | 926 | &req_settings, |
927 | offset); | |
4562236b HW |
928 | |
929 | /* 5. check CR done*/ | |
930 | if (!is_cr_done(lane_count, dpcd_lane_status)) | |
820e3935 | 931 | return LINK_TRAINING_EQ_FAIL_CR; |
4562236b HW |
932 | |
933 | /* 6. check CHEQ done*/ | |
934 | if (is_ch_eq_done(lane_count, | |
935 | dpcd_lane_status, | |
936 | &dpcd_lane_status_updated)) | |
820e3935 | 937 | return LINK_TRAINING_SUCCESS; |
4562236b HW |
938 | |
939 | /* 7. update VS/PE/PC2 in lt_settings*/ | |
940 | update_drive_settings(lt_settings, req_settings); | |
941 | } | |
942 | ||
820e3935 | 943 | return LINK_TRAINING_EQ_FAIL_EQ; |
4562236b HW |
944 | |
945 | } | |
64c12b73 | 946 | #define TRAINING_AUX_RD_INTERVAL 100 //us |
4562236b | 947 | |
b01f22ec DG |
948 | static void start_clock_recovery_pattern_early(struct dc_link *link, |
949 | struct link_training_settings *lt_settings, | |
950 | uint32_t offset) | |
951 | { | |
952 | DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n", | |
953 | __func__); | |
954 | dp_set_hw_training_pattern(link, DP_TRAINING_PATTERN_SEQUENCE_1, offset); | |
955 | dp_set_hw_lane_settings(link, lt_settings, offset); | |
956 | udelay(400); | |
957 | } | |
958 | ||
94405cf6 | 959 | static enum link_training_result perform_clock_recovery_sequence( |
d0778ebf | 960 | struct dc_link *link, |
64c12b73 | 961 | struct link_training_settings *lt_settings, |
962 | uint32_t offset) | |
4562236b HW |
963 | { |
964 | uint32_t retries_cr; | |
965 | uint32_t retry_count; | |
64c12b73 | 966 | uint32_t wait_time_microsec; |
4562236b | 967 | struct link_training_settings req_settings; |
e0a6440a DG |
968 | enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; |
969 | enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1; | |
4562236b HW |
970 | union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; |
971 | union lane_align_status_updated dpcd_lane_status_updated; | |
972 | ||
973 | retries_cr = 0; | |
974 | retry_count = 0; | |
4562236b | 975 | |
82054678 | 976 | if (!link->ctx->dc->work_arounds.lt_early_cr_pattern) |
b01f22ec | 977 | dp_set_hw_training_pattern(link, tr_pattern, offset); |
4562236b HW |
978 | |
979 | /* najeeb - The synaptics MST hub can put the LT in | |
980 | * infinite loop by switching the VS | |
981 | */ | |
982 | /* between level 0 and level 1 continuously, here | |
983 | * we try for CR lock for LinkTrainingMaxCRRetry count*/ | |
984 | while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) && | |
e0a6440a | 985 | (retry_count < LINK_TRAINING_MAX_CR_RETRY)) { |
4562236b HW |
986 | |
987 | memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status)); | |
988 | memset(&dpcd_lane_status_updated, '\0', | |
989 | sizeof(dpcd_lane_status_updated)); | |
990 | ||
991 | /* 1. call HWSS to set lane settings*/ | |
992 | dp_set_hw_lane_settings( | |
993 | link, | |
64c12b73 | 994 | lt_settings, |
995 | offset); | |
4562236b HW |
996 | |
997 | /* 2. update DPCD of the receiver*/ | |
50d2c602 | 998 | if (!retry_count) |
4562236b HW |
999 | /* EPR #361076 - write as a 5-byte burst, |
1000 | * but only for the 1-st iteration.*/ | |
1001 | dpcd_set_lt_pattern_and_lane_settings( | |
1002 | link, | |
1003 | lt_settings, | |
64c12b73 | 1004 | tr_pattern, |
1005 | offset); | |
4562236b HW |
1006 | else |
1007 | dpcd_set_lane_settings( | |
1008 | link, | |
64c12b73 | 1009 | lt_settings, |
1010 | offset); | |
4562236b HW |
1011 | |
1012 | /* 3. wait receiver to lock-on*/ | |
64c12b73 | 1013 | wait_time_microsec = lt_settings->cr_pattern_time; |
1014 | ||
1015 | if (!link->is_lttpr_mode_transparent) | |
1016 | wait_time_microsec = TRAINING_AUX_RD_INTERVAL; | |
1017 | ||
4562236b HW |
1018 | wait_for_training_aux_rd_interval( |
1019 | link, | |
64c12b73 | 1020 | wait_time_microsec); |
4562236b HW |
1021 | |
1022 | /* 4. Read lane status and requested drive | |
1023 | * settings as set by the sink | |
1024 | */ | |
1025 | get_lane_status_and_drive_settings( | |
1026 | link, | |
1027 | lt_settings, | |
1028 | dpcd_lane_status, | |
1029 | &dpcd_lane_status_updated, | |
64c12b73 | 1030 | &req_settings, |
1031 | offset); | |
4562236b HW |
1032 | |
1033 | /* 5. check CR done*/ | |
1034 | if (is_cr_done(lane_count, dpcd_lane_status)) | |
94405cf6 | 1035 | return LINK_TRAINING_SUCCESS; |
4562236b HW |
1036 | |
1037 | /* 6. max VS reached*/ | |
1038 | if (is_max_vs_reached(lt_settings)) | |
94405cf6 | 1039 | break; |
4562236b HW |
1040 | |
1041 | /* 7. same voltage*/ | |
1042 | /* Note: VS same for all lanes, | |
1043 | * so comparing first lane is sufficient*/ | |
1044 | if (lt_settings->lane_settings[0].VOLTAGE_SWING == | |
1045 | req_settings.lane_settings[0].VOLTAGE_SWING) | |
1046 | retries_cr++; | |
1047 | else | |
1048 | retries_cr = 0; | |
1049 | ||
1050 | /* 8. update VS/PE/PC2 in lt_settings*/ | |
1051 | update_drive_settings(lt_settings, req_settings); | |
1052 | ||
1053 | retry_count++; | |
1054 | } | |
1055 | ||
1056 | if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) { | |
1057 | ASSERT(0); | |
1296423b | 1058 | DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue", |
4f42a2dd | 1059 | __func__, |
4562236b HW |
1060 | LINK_TRAINING_MAX_CR_RETRY); |
1061 | ||
1062 | } | |
1063 | ||
94405cf6 | 1064 | return get_cr_failure(lane_count, dpcd_lane_status); |
4562236b HW |
1065 | } |
1066 | ||
94405cf6 | 1067 | static inline enum link_training_result perform_link_training_int( |
d0778ebf | 1068 | struct dc_link *link, |
4562236b | 1069 | struct link_training_settings *lt_settings, |
94405cf6 | 1070 | enum link_training_result status) |
4562236b HW |
1071 | { |
1072 | union lane_count_set lane_count_set = { {0} }; | |
1073 | union dpcd_training_pattern dpcd_pattern = { {0} }; | |
1074 | ||
1075 | /* 3. set training not in progress*/ | |
1076 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE; | |
1077 | dpcd_set_training_pattern(link, dpcd_pattern); | |
1078 | ||
1079 | /* 4. mainlink output idle pattern*/ | |
1080 | dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0); | |
1081 | ||
1082 | /* | |
1083 | * 5. post training adjust if required | |
1084 | * If the upstream DPTX and downstream DPRX both support TPS4, | |
1085 | * TPS4 must be used instead of POST_LT_ADJ_REQ. | |
1086 | */ | |
c30267f5 | 1087 | if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 || |
e0a6440a | 1088 | get_supported_tp(link) == DP_TRAINING_PATTERN_SEQUENCE_4) |
4562236b HW |
1089 | return status; |
1090 | ||
94405cf6 | 1091 | if (status == LINK_TRAINING_SUCCESS && |
4562236b | 1092 | perform_post_lt_adj_req_sequence(link, lt_settings) == false) |
94405cf6 | 1093 | status = LINK_TRAINING_LQA_FAIL; |
4562236b HW |
1094 | |
1095 | lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count; | |
e0a6440a | 1096 | lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing; |
4562236b HW |
1097 | lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0; |
1098 | ||
1099 | core_link_write_dpcd( | |
1100 | link, | |
3a340294 | 1101 | DP_LANE_COUNT_SET, |
4562236b HW |
1102 | &lane_count_set.raw, |
1103 | sizeof(lane_count_set)); | |
1104 | ||
1105 | return status; | |
1106 | } | |
1107 | ||
e0a6440a DG |
1108 | static void initialize_training_settings( |
1109 | struct dc_link *link, | |
4562236b | 1110 | const struct dc_link_settings *link_setting, |
0b226322 | 1111 | const struct dc_link_training_overrides *overrides, |
e0a6440a | 1112 | struct link_training_settings *lt_settings) |
4562236b | 1113 | { |
e0a6440a | 1114 | uint32_t lane; |
4562236b | 1115 | |
e0a6440a | 1116 | memset(lt_settings, '\0', sizeof(struct link_training_settings)); |
94405cf6 | 1117 | |
e0a6440a DG |
1118 | /* Initialize link settings */ |
1119 | lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set; | |
1120 | lt_settings->link_settings.link_rate_set = link_setting->link_rate_set; | |
4562236b | 1121 | |
e0a6440a DG |
1122 | if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) |
1123 | lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate; | |
1124 | else | |
1125 | lt_settings->link_settings.link_rate = link_setting->link_rate; | |
4562236b | 1126 | |
e0a6440a DG |
1127 | if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN) |
1128 | lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count; | |
1129 | else | |
1130 | lt_settings->link_settings.lane_count = link_setting->lane_count; | |
4562236b HW |
1131 | |
1132 | /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/ | |
1133 | ||
1134 | /* TODO hard coded to SS for now | |
1135 | * lt_settings.link_settings.link_spread = | |
1136 | * dal_display_path_is_ss_supported( | |
1137 | * path_mode->display_path) ? | |
1138 | * LINK_SPREAD_05_DOWNSPREAD_30KHZ : | |
1139 | * LINK_SPREAD_DISABLED; | |
1140 | */ | |
e0a6440a | 1141 | /* Initialize link spread */ |
ad830e7a | 1142 | if (link->dp_ss_off) |
e0a6440a | 1143 | lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED; |
0b226322 | 1144 | else if (overrides->downspread != NULL) |
e0a6440a | 1145 | lt_settings->link_settings.link_spread |
0b226322 | 1146 | = *overrides->downspread |
e0a6440a DG |
1147 | ? LINK_SPREAD_05_DOWNSPREAD_30KHZ |
1148 | : LINK_SPREAD_DISABLED; | |
ad830e7a | 1149 | else |
e0a6440a | 1150 | lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ; |
4562236b | 1151 | |
e0a6440a | 1152 | /* Initialize lane settings overrides */ |
0b226322 DG |
1153 | if (overrides->voltage_swing != NULL) |
1154 | lt_settings->voltage_swing = overrides->voltage_swing; | |
4562236b | 1155 | |
0b226322 DG |
1156 | if (overrides->pre_emphasis != NULL) |
1157 | lt_settings->pre_emphasis = overrides->pre_emphasis; | |
4562236b | 1158 | |
0b226322 DG |
1159 | if (overrides->post_cursor2 != NULL) |
1160 | lt_settings->post_cursor2 = overrides->post_cursor2; | |
e0a6440a DG |
1161 | |
1162 | /* Initialize lane settings (VS/PE/PC2) */ | |
1163 | for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { | |
1164 | lt_settings->lane_settings[lane].VOLTAGE_SWING = | |
1165 | lt_settings->voltage_swing != NULL ? | |
1166 | *lt_settings->voltage_swing : | |
1167 | VOLTAGE_SWING_LEVEL0; | |
1168 | lt_settings->lane_settings[lane].PRE_EMPHASIS = | |
1169 | lt_settings->pre_emphasis != NULL ? | |
1170 | *lt_settings->pre_emphasis | |
1171 | : PRE_EMPHASIS_DISABLED; | |
1172 | lt_settings->lane_settings[lane].POST_CURSOR2 = | |
1173 | lt_settings->post_cursor2 != NULL ? | |
1174 | *lt_settings->post_cursor2 | |
1175 | : POST_CURSOR2_DISABLED; | |
820e3935 | 1176 | } |
4562236b | 1177 | |
e0a6440a | 1178 | /* Initialize training timings */ |
0b226322 DG |
1179 | if (overrides->cr_pattern_time != NULL) |
1180 | lt_settings->cr_pattern_time = *overrides->cr_pattern_time; | |
e0a6440a | 1181 | else |
0b226322 | 1182 | lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100); |
e0a6440a | 1183 | |
0b226322 DG |
1184 | if (overrides->eq_pattern_time != NULL) |
1185 | lt_settings->eq_pattern_time = *overrides->eq_pattern_time; | |
e0a6440a DG |
1186 | else |
1187 | lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400); | |
1188 | ||
0b226322 DG |
1189 | if (overrides->pattern_for_eq != NULL) |
1190 | lt_settings->pattern_for_eq = *overrides->pattern_for_eq; | |
e0a6440a DG |
1191 | else |
1192 | lt_settings->pattern_for_eq = get_supported_tp(link); | |
1193 | ||
0b226322 DG |
1194 | if (overrides->enhanced_framing != NULL) |
1195 | lt_settings->enhanced_framing = *overrides->enhanced_framing; | |
e0a6440a DG |
1196 | else |
1197 | lt_settings->enhanced_framing = 1; | |
1198 | } | |
1199 | ||
64c12b73 | 1200 | static uint8_t convert_to_count(uint8_t lttpr_repeater_count) |
1201 | { | |
1202 | switch (lttpr_repeater_count) { | |
1203 | case 0x80: // 1 lttpr repeater | |
1204 | return 1; | |
1205 | case 0x40: // 2 lttpr repeaters | |
1206 | return 2; | |
1207 | case 0x20: // 3 lttpr repeaters | |
1208 | return 3; | |
1209 | case 0x10: // 4 lttpr repeaters | |
1210 | return 4; | |
1211 | case 0x08: // 5 lttpr repeaters | |
1212 | return 5; | |
1213 | case 0x04: // 6 lttpr repeaters | |
1214 | return 6; | |
1215 | case 0x02: // 7 lttpr repeaters | |
1216 | return 7; | |
1217 | case 0x01: // 8 lttpr repeaters | |
1218 | return 8; | |
1219 | default: | |
1220 | break; | |
1221 | } | |
1222 | return 0; // invalid value | |
1223 | } | |
1224 | ||
bad7ab0b | 1225 | static void configure_lttpr_mode(struct dc_link *link) |
1226 | { | |
1227 | /* aux timeout is already set to extended */ | |
1228 | /* RESET/SET lttpr mode to enable non transparent mode */ | |
64c12b73 | 1229 | uint8_t repeater_cnt; |
1230 | uint32_t aux_interval_address; | |
1231 | uint8_t repeater_id; | |
a166f86e | 1232 | enum dc_status result = DC_ERROR_UNEXPECTED; |
61aa7a6f | 1233 | uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT; |
bad7ab0b | 1234 | |
c14f2507 | 1235 | DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__); |
a166f86e | 1236 | result = core_link_write_dpcd(link, |
bad7ab0b | 1237 | DP_PHY_REPEATER_MODE, |
1238 | (uint8_t *)&repeater_mode, | |
1239 | sizeof(repeater_mode)); | |
1240 | ||
a166f86e | 1241 | if (result == DC_OK) { |
1242 | link->dpcd_caps.lttpr_caps.mode = repeater_mode; | |
1243 | } | |
1244 | ||
bad7ab0b | 1245 | if (!link->is_lttpr_mode_transparent) { |
460adc6b | 1246 | |
c14f2507 | 1247 | DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__); |
460adc6b | 1248 | |
61aa7a6f | 1249 | repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT; |
a166f86e | 1250 | result = core_link_write_dpcd(link, |
bad7ab0b | 1251 | DP_PHY_REPEATER_MODE, |
1252 | (uint8_t *)&repeater_mode, | |
1253 | sizeof(repeater_mode)); | |
64c12b73 | 1254 | |
a166f86e | 1255 | if (result == DC_OK) { |
1256 | link->dpcd_caps.lttpr_caps.mode = repeater_mode; | |
1257 | } | |
1258 | ||
64c12b73 | 1259 | repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); |
1260 | for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) { | |
1261 | aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 + | |
1262 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1)); | |
1263 | core_link_read_dpcd( | |
1264 | link, | |
1265 | aux_interval_address, | |
1266 | (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1], | |
1267 | sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1])); | |
1268 | link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F; | |
1269 | } | |
bad7ab0b | 1270 | } |
1271 | } | |
1272 | ||
64c12b73 | 1273 | static void repeater_training_done(struct dc_link *link, uint32_t offset) |
1274 | { | |
1275 | union dpcd_training_pattern dpcd_pattern = { {0} }; | |
1276 | ||
1277 | const uint32_t dpcd_base_lt_offset = | |
1278 | DP_TRAINING_PATTERN_SET_PHY_REPEATER1 + | |
1279 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); | |
1280 | /* Set training not in progress*/ | |
1281 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE; | |
1282 | ||
1283 | core_link_write_dpcd( | |
1284 | link, | |
1285 | dpcd_base_lt_offset, | |
1286 | &dpcd_pattern.raw, | |
1287 | 1); | |
1288 | ||
460adc6b | 1289 | DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n", |
64c12b73 | 1290 | __func__, |
460adc6b | 1291 | offset, |
64c12b73 | 1292 | dpcd_base_lt_offset, |
1293 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET); | |
1294 | } | |
1295 | ||
e0a6440a DG |
1296 | static void print_status_message( |
1297 | struct dc_link *link, | |
1298 | const struct link_training_settings *lt_settings, | |
1299 | enum link_training_result status) | |
1300 | { | |
1301 | char *link_rate = "Unknown"; | |
1302 | char *lt_result = "Unknown"; | |
1303 | char *lt_spread = "Disabled"; | |
4562236b | 1304 | |
e0a6440a | 1305 | switch (lt_settings->link_settings.link_rate) { |
4562236b HW |
1306 | case LINK_RATE_LOW: |
1307 | link_rate = "RBR"; | |
1308 | break; | |
1309 | case LINK_RATE_HIGH: | |
1310 | link_rate = "HBR"; | |
1311 | break; | |
1312 | case LINK_RATE_HIGH2: | |
1313 | link_rate = "HBR2"; | |
1314 | break; | |
1315 | case LINK_RATE_RBR2: | |
1316 | link_rate = "RBR2"; | |
1317 | break; | |
1318 | case LINK_RATE_HIGH3: | |
1319 | link_rate = "HBR3"; | |
1320 | break; | |
1321 | default: | |
1322 | break; | |
1323 | } | |
1324 | ||
94405cf6 WL |
1325 | switch (status) { |
1326 | case LINK_TRAINING_SUCCESS: | |
1327 | lt_result = "pass"; | |
1328 | break; | |
1329 | case LINK_TRAINING_CR_FAIL_LANE0: | |
1330 | lt_result = "CR failed lane0"; | |
1331 | break; | |
1332 | case LINK_TRAINING_CR_FAIL_LANE1: | |
1333 | lt_result = "CR failed lane1"; | |
1334 | break; | |
1335 | case LINK_TRAINING_CR_FAIL_LANE23: | |
1336 | lt_result = "CR failed lane23"; | |
1337 | break; | |
1338 | case LINK_TRAINING_EQ_FAIL_CR: | |
1339 | lt_result = "CR failed in EQ"; | |
1340 | break; | |
1341 | case LINK_TRAINING_EQ_FAIL_EQ: | |
1342 | lt_result = "EQ failed"; | |
1343 | break; | |
1344 | case LINK_TRAINING_LQA_FAIL: | |
1345 | lt_result = "LQA failed"; | |
1346 | break; | |
1347 | default: | |
1348 | break; | |
1349 | } | |
1350 | ||
e0a6440a DG |
1351 | switch (lt_settings->link_settings.link_spread) { |
1352 | case LINK_SPREAD_DISABLED: | |
1353 | lt_spread = "Disabled"; | |
1354 | break; | |
1355 | case LINK_SPREAD_05_DOWNSPREAD_30KHZ: | |
1356 | lt_spread = "0.5% 30KHz"; | |
1357 | break; | |
1358 | case LINK_SPREAD_05_DOWNSPREAD_33KHZ: | |
1359 | lt_spread = "0.5% 33KHz"; | |
1360 | break; | |
1361 | default: | |
1362 | break; | |
1363 | } | |
1364 | ||
4562236b | 1365 | /* Connectivity log: link training */ |
e0a6440a DG |
1366 | CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s", |
1367 | link_rate, | |
1368 | lt_settings->link_settings.lane_count, | |
1369 | lt_result, | |
1370 | lt_settings->lane_settings[0].VOLTAGE_SWING, | |
1371 | lt_settings->lane_settings[0].PRE_EMPHASIS, | |
1372 | lt_spread); | |
1373 | } | |
1374 | ||
64c12b73 | 1375 | void dc_link_dp_set_drive_settings( |
1376 | struct dc_link *link, | |
1377 | struct link_training_settings *lt_settings) | |
1378 | { | |
1379 | /* program ASIC PHY settings*/ | |
1380 | dp_set_hw_lane_settings(link, lt_settings, DPRX); | |
1381 | ||
1382 | /* Notify DP sink the PHY settings from source */ | |
1383 | dpcd_set_lane_settings(link, lt_settings, DPRX); | |
1384 | } | |
1385 | ||
e0a6440a DG |
1386 | bool dc_link_dp_perform_link_training_skip_aux( |
1387 | struct dc_link *link, | |
1388 | const struct dc_link_settings *link_setting) | |
1389 | { | |
1390 | struct link_training_settings lt_settings; | |
1391 | enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1; | |
1392 | ||
0b226322 DG |
1393 | initialize_training_settings( |
1394 | link, | |
1395 | link_setting, | |
1396 | &link->preferred_training_settings, | |
1397 | <_settings); | |
e0a6440a DG |
1398 | |
1399 | /* 1. Perform_clock_recovery_sequence. */ | |
1400 | ||
1401 | /* transmit training pattern for clock recovery */ | |
64c12b73 | 1402 | dp_set_hw_training_pattern(link, pattern_for_cr, DPRX); |
e0a6440a DG |
1403 | |
1404 | /* call HWSS to set lane settings*/ | |
64c12b73 | 1405 | dp_set_hw_lane_settings(link, <_settings, DPRX); |
e0a6440a DG |
1406 | |
1407 | /* wait receiver to lock-on*/ | |
1408 | wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time); | |
1409 | ||
1410 | /* 2. Perform_channel_equalization_sequence. */ | |
1411 | ||
1412 | /* transmit training pattern for channel equalization. */ | |
64c12b73 | 1413 | dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX); |
e0a6440a DG |
1414 | |
1415 | /* call HWSS to set lane settings*/ | |
64c12b73 | 1416 | dp_set_hw_lane_settings(link, <_settings, DPRX); |
e0a6440a DG |
1417 | |
1418 | /* wait receiver to lock-on. */ | |
1419 | wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time); | |
1420 | ||
1421 | /* 3. Perform_link_training_int. */ | |
1422 | ||
1423 | /* Mainlink output idle pattern. */ | |
1424 | dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0); | |
1425 | ||
1426 | print_status_message(link, <_settings, LINK_TRAINING_SUCCESS); | |
1427 | ||
1428 | return true; | |
1429 | } | |
1430 | ||
1431 | enum link_training_result dc_link_dp_perform_link_training( | |
1432 | struct dc_link *link, | |
1433 | const struct dc_link_settings *link_setting, | |
1434 | bool skip_video_pattern) | |
1435 | { | |
1436 | enum link_training_result status = LINK_TRAINING_SUCCESS; | |
e0a6440a | 1437 | struct link_training_settings lt_settings; |
64c12b73 | 1438 | |
008a4016 | 1439 | bool fec_enable; |
64c12b73 | 1440 | uint8_t repeater_cnt; |
1441 | uint8_t repeater_id; | |
e0a6440a | 1442 | |
0b226322 DG |
1443 | initialize_training_settings( |
1444 | link, | |
1445 | link_setting, | |
1446 | &link->preferred_training_settings, | |
1447 | <_settings); | |
e0a6440a | 1448 | |
bcc5042a | 1449 | /* Configure lttpr mode */ |
1450 | if (!link->is_lttpr_mode_transparent) | |
1451 | configure_lttpr_mode(link); | |
1452 | ||
82054678 ML |
1453 | if (link->ctx->dc->work_arounds.lt_early_cr_pattern) |
1454 | start_clock_recovery_pattern_early(link, <_settings, DPRX); | |
834a9a9f ML |
1455 | |
1456 | /* 1. set link rate, lane count and spread. */ | |
1457 | dpcd_set_link_settings(link, <_settings); | |
e0a6440a | 1458 | |
008a4016 NC |
1459 | if (link->preferred_training_settings.fec_enable != NULL) |
1460 | fec_enable = *link->preferred_training_settings.fec_enable; | |
1461 | else | |
1462 | fec_enable = true; | |
1463 | ||
1464 | dp_set_fec_ready(link, fec_enable); | |
008a4016 | 1465 | |
64c12b73 | 1466 | if (!link->is_lttpr_mode_transparent) { |
008a4016 | 1467 | |
64c12b73 | 1468 | /* 2. perform link training (set link training done |
1469 | * to false is done as well) | |
1470 | */ | |
1471 | repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); | |
1472 | ||
1473 | for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS); | |
1474 | repeater_id--) { | |
1475 | status = perform_clock_recovery_sequence(link, <_settings, repeater_id); | |
1476 | ||
1477 | if (status != LINK_TRAINING_SUCCESS) | |
1478 | break; | |
1479 | ||
1480 | status = perform_channel_equalization_sequence(link, | |
1481 | <_settings, | |
1482 | repeater_id); | |
1483 | ||
1484 | if (status != LINK_TRAINING_SUCCESS) | |
1485 | break; | |
1486 | ||
1487 | repeater_training_done(link, repeater_id); | |
1488 | } | |
1489 | } | |
1490 | ||
1491 | if (status == LINK_TRAINING_SUCCESS) { | |
1492 | status = perform_clock_recovery_sequence(link, <_settings, DPRX); | |
e0a6440a DG |
1493 | if (status == LINK_TRAINING_SUCCESS) { |
1494 | status = perform_channel_equalization_sequence(link, | |
64c12b73 | 1495 | <_settings, |
1496 | DPRX); | |
1497 | } | |
e0a6440a DG |
1498 | } |
1499 | ||
1500 | if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) { | |
1501 | status = perform_link_training_int(link, | |
1502 | <_settings, | |
1503 | status); | |
1504 | } | |
1505 | ||
1506 | /* 6. print status message*/ | |
1507 | print_status_message(link, <_settings, status); | |
4562236b | 1508 | |
d6e75df4 | 1509 | if (status != LINK_TRAINING_SUCCESS) |
cfd84fd3 | 1510 | link->ctx->dc->debug_data.ltFailCount++; |
d6e75df4 | 1511 | |
4562236b HW |
1512 | return status; |
1513 | } | |
1514 | ||
4562236b | 1515 | bool perform_link_training_with_retries( |
4562236b HW |
1516 | const struct dc_link_settings *link_setting, |
1517 | bool skip_video_pattern, | |
832aa63b PH |
1518 | int attempts, |
1519 | struct pipe_ctx *pipe_ctx, | |
1520 | enum signal_type signal) | |
4562236b HW |
1521 | { |
1522 | uint8_t j; | |
1523 | uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY; | |
832aa63b PH |
1524 | struct dc_stream_state *stream = pipe_ctx->stream; |
1525 | struct dc_link *link = stream->link; | |
1526 | enum dp_panel_mode panel_mode = dp_get_panel_mode(link); | |
4562236b HW |
1527 | |
1528 | for (j = 0; j < attempts; ++j) { | |
1529 | ||
832aa63b PH |
1530 | dp_enable_link_phy( |
1531 | link, | |
1532 | signal, | |
1533 | pipe_ctx->clock_source->id, | |
1534 | link_setting); | |
1535 | ||
1536 | if (stream->sink_patches.dppowerup_delay > 0) { | |
1537 | int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay; | |
1538 | ||
1539 | msleep(delay_dp_power_up_in_ms); | |
1540 | } | |
1541 | ||
1542 | dp_set_panel_mode(link, panel_mode); | |
1543 | ||
1544 | /* We need to do this before the link training to ensure the idle pattern in SST | |
1545 | * mode will be sent right after the link training | |
1546 | */ | |
1547 | link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, | |
1548 | pipe_ctx->stream_res.stream_enc->id, true); | |
1549 | ||
1550 | if (link->aux_access_disabled) { | |
1551 | dc_link_dp_perform_link_training_skip_aux(link, link_setting); | |
1552 | return true; | |
1553 | } else if (dc_link_dp_perform_link_training( | |
d0778ebf | 1554 | link, |
4562236b | 1555 | link_setting, |
820e3935 | 1556 | skip_video_pattern) == LINK_TRAINING_SUCCESS) |
4562236b HW |
1557 | return true; |
1558 | ||
832aa63b PH |
1559 | /* latest link training still fail, skip delay and keep PHY on |
1560 | */ | |
1561 | if (j == (attempts - 1)) | |
1562 | break; | |
1563 | ||
1564 | dp_disable_link_phy(link, signal); | |
1565 | ||
4562236b | 1566 | msleep(delay_between_attempts); |
832aa63b | 1567 | |
4562236b HW |
1568 | delay_between_attempts += LINK_TRAINING_RETRY_DELAY; |
1569 | } | |
1570 | ||
1571 | return false; | |
1572 | } | |
1573 | ||
0b226322 DG |
1574 | static enum clock_source_id get_clock_source_id(struct dc_link *link) |
1575 | { | |
1576 | enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED; | |
1577 | struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; | |
1578 | ||
1579 | if (dp_cs != NULL) { | |
1580 | dp_cs_id = dp_cs->id; | |
1581 | } else { | |
1582 | /* | |
1583 | * dp clock source is not initialized for some reason. | |
1584 | * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used | |
1585 | */ | |
1586 | ASSERT(dp_cs); | |
1587 | } | |
1588 | ||
1589 | return dp_cs_id; | |
1590 | } | |
1591 | ||
1592 | static void set_dp_mst_mode(struct dc_link *link, bool mst_enable) | |
1593 | { | |
1594 | if (mst_enable == false && | |
1595 | link->type == dc_connection_mst_branch) { | |
1596 | /* Disable MST on link. Use only local sink. */ | |
1597 | dp_disable_link_phy_mst(link, link->connector_signal); | |
1598 | ||
1599 | link->type = dc_connection_single; | |
1600 | link->local_sink = link->remote_sinks[0]; | |
1601 | link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT; | |
1602 | } else if (mst_enable == true && | |
1603 | link->type == dc_connection_single && | |
1604 | link->remote_sinks[0] != NULL) { | |
1605 | /* Re-enable MST on link. */ | |
1606 | dp_disable_link_phy(link, link->connector_signal); | |
1607 | dp_enable_mst_on_sink(link, true); | |
1608 | ||
1609 | link->type = dc_connection_mst_branch; | |
1610 | link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST; | |
1611 | } | |
1612 | } | |
1613 | ||
1614 | bool dc_link_dp_sync_lt_begin(struct dc_link *link) | |
1615 | { | |
1616 | /* Begin Sync LT. During this time, | |
1617 | * DPCD:600h must not be powered down. | |
1618 | */ | |
1619 | link->sync_lt_in_progress = true; | |
1620 | ||
1621 | /*Clear any existing preferred settings.*/ | |
1622 | memset(&link->preferred_training_settings, 0, | |
1623 | sizeof(struct dc_link_training_overrides)); | |
1624 | memset(&link->preferred_link_setting, 0, | |
1625 | sizeof(struct dc_link_settings)); | |
1626 | ||
1627 | return true; | |
1628 | } | |
1629 | ||
1630 | enum link_training_result dc_link_dp_sync_lt_attempt( | |
1631 | struct dc_link *link, | |
1632 | struct dc_link_settings *link_settings, | |
1633 | struct dc_link_training_overrides *lt_overrides) | |
1634 | { | |
1635 | struct link_training_settings lt_settings; | |
1636 | enum link_training_result lt_status = LINK_TRAINING_SUCCESS; | |
1637 | enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT; | |
1638 | enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL; | |
0b226322 | 1639 | bool fec_enable = false; |
0b226322 DG |
1640 | |
1641 | initialize_training_settings( | |
1642 | link, | |
1643 | link_settings, | |
1644 | lt_overrides, | |
1645 | <_settings); | |
1646 | ||
1647 | /* Setup MST Mode */ | |
1648 | if (lt_overrides->mst_enable) | |
1649 | set_dp_mst_mode(link, *lt_overrides->mst_enable); | |
1650 | ||
1651 | /* Disable link */ | |
1652 | dp_disable_link_phy(link, link->connector_signal); | |
1653 | ||
1654 | /* Enable link */ | |
1655 | dp_cs_id = get_clock_source_id(link); | |
1656 | dp_enable_link_phy(link, link->connector_signal, | |
1657 | dp_cs_id, link_settings); | |
1658 | ||
0b226322 DG |
1659 | /* Set FEC enable */ |
1660 | fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable; | |
1661 | dp_set_fec_ready(link, fec_enable); | |
0b226322 DG |
1662 | |
1663 | if (lt_overrides->alternate_scrambler_reset) { | |
1664 | if (*lt_overrides->alternate_scrambler_reset) | |
1665 | panel_mode = DP_PANEL_MODE_EDP; | |
1666 | else | |
1667 | panel_mode = DP_PANEL_MODE_DEFAULT; | |
1668 | } else | |
1669 | panel_mode = dp_get_panel_mode(link); | |
1670 | ||
1671 | dp_set_panel_mode(link, panel_mode); | |
1672 | ||
1673 | /* Attempt to train with given link training settings */ | |
82054678 ML |
1674 | if (link->ctx->dc->work_arounds.lt_early_cr_pattern) |
1675 | start_clock_recovery_pattern_early(link, <_settings, DPRX); | |
834a9a9f ML |
1676 | |
1677 | /* Set link rate, lane count and spread. */ | |
1678 | dpcd_set_link_settings(link, <_settings); | |
0b226322 DG |
1679 | |
1680 | /* 2. perform link training (set link training done | |
1681 | * to false is done as well) | |
1682 | */ | |
64c12b73 | 1683 | lt_status = perform_clock_recovery_sequence(link, <_settings, DPRX); |
0b226322 DG |
1684 | if (lt_status == LINK_TRAINING_SUCCESS) { |
1685 | lt_status = perform_channel_equalization_sequence(link, | |
64c12b73 | 1686 | <_settings, |
1687 | DPRX); | |
0b226322 DG |
1688 | } |
1689 | ||
1690 | /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/ | |
1691 | /* 4. print status message*/ | |
1692 | print_status_message(link, <_settings, lt_status); | |
1693 | ||
1694 | return lt_status; | |
1695 | } | |
1696 | ||
1697 | bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down) | |
1698 | { | |
1699 | /* If input parameter is set, shut down phy. | |
1700 | * Still shouldn't turn off dp_receiver (DPCD:600h) | |
1701 | */ | |
1702 | if (link_down == true) { | |
1703 | dp_disable_link_phy(link, link->connector_signal); | |
0b226322 | 1704 | dp_set_fec_ready(link, false); |
0b226322 DG |
1705 | } |
1706 | ||
1707 | link->sync_lt_in_progress = false; | |
1708 | return true; | |
1709 | } | |
1710 | ||
d0778ebf | 1711 | static struct dc_link_settings get_max_link_cap(struct dc_link *link) |
4562236b HW |
1712 | { |
1713 | /* Set Default link settings */ | |
1714 | struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, | |
8628d02f | 1715 | LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0}; |
4562236b HW |
1716 | |
1717 | /* Higher link settings based on feature supported */ | |
1718 | if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE) | |
1719 | max_link_cap.link_rate = LINK_RATE_HIGH2; | |
1720 | ||
1721 | if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE) | |
1722 | max_link_cap.link_rate = LINK_RATE_HIGH3; | |
1723 | ||
f537d474 LH |
1724 | if (link->link_enc->funcs->get_max_link_cap) |
1725 | link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap); | |
1726 | ||
4562236b | 1727 | /* Lower link settings based on sink's link cap */ |
d0778ebf | 1728 | if (link->reported_link_cap.lane_count < max_link_cap.lane_count) |
4562236b | 1729 | max_link_cap.lane_count = |
d0778ebf HW |
1730 | link->reported_link_cap.lane_count; |
1731 | if (link->reported_link_cap.link_rate < max_link_cap.link_rate) | |
4562236b | 1732 | max_link_cap.link_rate = |
d0778ebf HW |
1733 | link->reported_link_cap.link_rate; |
1734 | if (link->reported_link_cap.link_spread < | |
4562236b HW |
1735 | max_link_cap.link_spread) |
1736 | max_link_cap.link_spread = | |
d0778ebf | 1737 | link->reported_link_cap.link_spread; |
bad7ab0b | 1738 | /* |
1739 | * account for lttpr repeaters cap | |
1740 | * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3). | |
1741 | */ | |
1742 | if (!link->is_lttpr_mode_transparent) { | |
1743 | if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count) | |
1744 | max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count; | |
1745 | ||
1746 | if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate) | |
1747 | max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate; | |
460adc6b | 1748 | |
1749 | DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n", | |
1750 | __func__, | |
1751 | max_link_cap.lane_count, | |
1752 | max_link_cap.link_rate); | |
bad7ab0b | 1753 | } |
4562236b HW |
1754 | return max_link_cap; |
1755 | } | |
1756 | ||
1ae62f31 WL |
1757 | static enum dc_status read_hpd_rx_irq_data( |
1758 | struct dc_link *link, | |
1759 | union hpd_irq_data *irq_data) | |
1760 | { | |
1761 | static enum dc_status retval; | |
1762 | ||
1763 | /* The HW reads 16 bytes from 200h on HPD, | |
1764 | * but if we get an AUX_DEFER, the HW cannot retry | |
1765 | * and this causes the CTS tests 4.3.2.1 - 3.2.4 to | |
1766 | * fail, so we now explicitly read 6 bytes which is | |
1767 | * the req from the above mentioned test cases. | |
1768 | * | |
1769 | * For DP 1.4 we need to read those from 2002h range. | |
1770 | */ | |
1771 | if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14) | |
1772 | retval = core_link_read_dpcd( | |
1773 | link, | |
1774 | DP_SINK_COUNT, | |
1775 | irq_data->raw, | |
1776 | sizeof(union hpd_irq_data)); | |
1777 | else { | |
1778 | /* Read 14 bytes in a single read and then copy only the required fields. | |
1779 | * This is more efficient than doing it in two separate AUX reads. */ | |
1780 | ||
1781 | uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1]; | |
1782 | ||
1783 | retval = core_link_read_dpcd( | |
1784 | link, | |
1785 | DP_SINK_COUNT_ESI, | |
1786 | tmp, | |
1787 | sizeof(tmp)); | |
1788 | ||
1789 | if (retval != DC_OK) | |
1790 | return retval; | |
1791 | ||
1792 | irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI]; | |
1793 | irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI]; | |
1794 | irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI]; | |
1795 | irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI]; | |
1796 | irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI]; | |
1797 | irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI]; | |
1798 | } | |
1799 | ||
1800 | return retval; | |
1801 | } | |
1802 | ||
1803 | static bool hpd_rx_irq_check_link_loss_status( | |
1804 | struct dc_link *link, | |
1805 | union hpd_irq_data *hpd_irq_dpcd_data) | |
1806 | { | |
1807 | uint8_t irq_reg_rx_power_state = 0; | |
1808 | enum dc_status dpcd_result = DC_ERROR_UNEXPECTED; | |
1809 | union lane_status lane_status; | |
1810 | uint32_t lane; | |
1811 | bool sink_status_changed; | |
1812 | bool return_code; | |
1813 | ||
1814 | sink_status_changed = false; | |
1815 | return_code = false; | |
1816 | ||
1817 | if (link->cur_link_settings.lane_count == 0) | |
1818 | return return_code; | |
1819 | ||
1820 | /*1. Check that Link Status changed, before re-training.*/ | |
1821 | ||
1822 | /*parse lane status*/ | |
1823 | for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { | |
1824 | /* check status of lanes 0,1 | |
1825 | * changed DpcdAddress_Lane01Status (0x202) | |
1826 | */ | |
1827 | lane_status.raw = get_nibble_at_index( | |
1828 | &hpd_irq_dpcd_data->bytes.lane01_status.raw, | |
1829 | lane); | |
1830 | ||
1831 | if (!lane_status.bits.CHANNEL_EQ_DONE_0 || | |
1832 | !lane_status.bits.CR_DONE_0 || | |
1833 | !lane_status.bits.SYMBOL_LOCKED_0) { | |
1834 | /* if one of the channel equalization, clock | |
1835 | * recovery or symbol lock is dropped | |
1836 | * consider it as (link has been | |
1837 | * dropped) dp sink status has changed | |
1838 | */ | |
1839 | sink_status_changed = true; | |
1840 | break; | |
1841 | } | |
1842 | } | |
1843 | ||
1844 | /* Check interlane align.*/ | |
1845 | if (sink_status_changed || | |
1846 | !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) { | |
1847 | ||
1848 | DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__); | |
1849 | ||
1850 | return_code = true; | |
1851 | ||
1852 | /*2. Check that we can handle interrupt: Not in FS DOS, | |
1853 | * Not in "Display Timeout" state, Link is trained. | |
1854 | */ | |
1855 | dpcd_result = core_link_read_dpcd(link, | |
1856 | DP_SET_POWER, | |
1857 | &irq_reg_rx_power_state, | |
1858 | sizeof(irq_reg_rx_power_state)); | |
1859 | ||
1860 | if (dpcd_result != DC_OK) { | |
1861 | DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n", | |
1862 | __func__); | |
1863 | } else { | |
1864 | if (irq_reg_rx_power_state != DP_SET_POWER_D0) | |
1865 | return_code = false; | |
1866 | } | |
1867 | } | |
1868 | ||
1869 | return return_code; | |
1870 | } | |
1871 | ||
aafded88 | 1872 | bool dp_verify_link_cap( |
d0778ebf | 1873 | struct dc_link *link, |
824474ba BL |
1874 | struct dc_link_settings *known_limit_link_setting, |
1875 | int *fail_count) | |
4562236b HW |
1876 | { |
1877 | struct dc_link_settings max_link_cap = {0}; | |
820e3935 DW |
1878 | struct dc_link_settings cur_link_setting = {0}; |
1879 | struct dc_link_settings *cur = &cur_link_setting; | |
1880 | struct dc_link_settings initial_link_settings = {0}; | |
4562236b HW |
1881 | bool success; |
1882 | bool skip_link_training; | |
4562236b | 1883 | bool skip_video_pattern; |
4562236b | 1884 | enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL; |
820e3935 | 1885 | enum link_training_result status; |
1ae62f31 | 1886 | union hpd_irq_data irq_data; |
4562236b | 1887 | |
aafded88 TC |
1888 | if (link->dc->debug.skip_detection_link_training) { |
1889 | link->verified_link_cap = *known_limit_link_setting; | |
1890 | return true; | |
1891 | } | |
1892 | ||
1ae62f31 | 1893 | memset(&irq_data, 0, sizeof(irq_data)); |
4562236b HW |
1894 | success = false; |
1895 | skip_link_training = false; | |
1896 | ||
1897 | max_link_cap = get_max_link_cap(link); | |
1898 | ||
bad7ab0b | 1899 | /* Grant extended timeout request */ |
1900 | if (!link->is_lttpr_mode_transparent && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) { | |
1901 | uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80; | |
1902 | ||
1903 | core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant)); | |
1904 | } | |
1905 | ||
4562236b HW |
1906 | /* TODO implement override and monitor patch later */ |
1907 | ||
1908 | /* try to train the link from high to low to | |
1909 | * find the physical link capability | |
1910 | */ | |
1911 | /* disable PHY done possible by BIOS, will be done by driver itself */ | |
d0778ebf | 1912 | dp_disable_link_phy(link, link->connector_signal); |
4562236b | 1913 | |
b3282738 GS |
1914 | dp_cs_id = get_clock_source_id(link); |
1915 | ||
1916 | /* link training starts with the maximum common settings | |
1917 | * supported by both sink and ASIC. | |
1918 | */ | |
1919 | initial_link_settings = get_common_supported_link_settings( | |
1920 | *known_limit_link_setting, | |
1921 | max_link_cap); | |
1922 | cur_link_setting = initial_link_settings; | |
1923 | ||
ee765924 GS |
1924 | /* Temporary Renoir-specific workaround for SWDEV-215184; |
1925 | * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle, | |
1926 | * so add extra cycle of enabling and disabling the PHY before first link training. | |
1927 | */ | |
1928 | if (link->link_enc->features.flags.bits.DP_IS_USB_C && | |
1929 | link->dc->debug.usbc_combo_phy_reset_wa) { | |
1930 | dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur); | |
1931 | dp_disable_link_phy(link, link->connector_signal); | |
1932 | } | |
1933 | ||
820e3935 | 1934 | do { |
4562236b | 1935 | skip_video_pattern = true; |
820e3935 | 1936 | |
4562236b HW |
1937 | if (cur->link_rate == LINK_RATE_LOW) |
1938 | skip_video_pattern = false; | |
1939 | ||
1940 | dp_enable_link_phy( | |
1941 | link, | |
d0778ebf | 1942 | link->connector_signal, |
4562236b HW |
1943 | dp_cs_id, |
1944 | cur); | |
1945 | ||
94405cf6 | 1946 | |
4562236b HW |
1947 | if (skip_link_training) |
1948 | success = true; | |
1949 | else { | |
820e3935 | 1950 | status = dc_link_dp_perform_link_training( |
d0778ebf | 1951 | link, |
4562236b HW |
1952 | cur, |
1953 | skip_video_pattern); | |
820e3935 DW |
1954 | if (status == LINK_TRAINING_SUCCESS) |
1955 | success = true; | |
824474ba BL |
1956 | else |
1957 | (*fail_count)++; | |
4562236b HW |
1958 | } |
1959 | ||
1ae62f31 | 1960 | if (success) { |
d0778ebf | 1961 | link->verified_link_cap = *cur; |
1ae62f31 WL |
1962 | udelay(1000); |
1963 | if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK) | |
1964 | if (hpd_rx_irq_check_link_loss_status( | |
1965 | link, | |
1966 | &irq_data)) | |
1967 | (*fail_count)++; | |
1968 | } | |
4562236b HW |
1969 | /* always disable the link before trying another |
1970 | * setting or before returning we'll enable it later | |
1971 | * based on the actual mode we're driving | |
1972 | */ | |
d0778ebf | 1973 | dp_disable_link_phy(link, link->connector_signal); |
820e3935 DW |
1974 | } while (!success && decide_fallback_link_setting( |
1975 | initial_link_settings, cur, status)); | |
4562236b HW |
1976 | |
1977 | /* Link Training failed for all Link Settings | |
1978 | * (Lane Count is still unknown) | |
1979 | */ | |
1980 | if (!success) { | |
1981 | /* If all LT fails for all settings, | |
1982 | * set verified = failed safe (1 lane low) | |
1983 | */ | |
d0778ebf HW |
1984 | link->verified_link_cap.lane_count = LANE_COUNT_ONE; |
1985 | link->verified_link_cap.link_rate = LINK_RATE_LOW; | |
4562236b | 1986 | |
d0778ebf | 1987 | link->verified_link_cap.link_spread = |
4562236b HW |
1988 | LINK_SPREAD_DISABLED; |
1989 | } | |
1990 | ||
4562236b HW |
1991 | |
1992 | return success; | |
1993 | } | |
1994 | ||
e7f2c80c WL |
1995 | bool dp_verify_link_cap_with_retries( |
1996 | struct dc_link *link, | |
1997 | struct dc_link_settings *known_limit_link_setting, | |
1998 | int attempts) | |
1999 | { | |
2000 | uint8_t i = 0; | |
2001 | bool success = false; | |
2002 | ||
2003 | for (i = 0; i < attempts; i++) { | |
2004 | int fail_count = 0; | |
82db2e3c | 2005 | enum dc_connection_type type = dc_connection_none; |
e7f2c80c WL |
2006 | |
2007 | memset(&link->verified_link_cap, 0, | |
2008 | sizeof(struct dc_link_settings)); | |
82db2e3c SK |
2009 | if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) { |
2010 | link->verified_link_cap.lane_count = LANE_COUNT_ONE; | |
2011 | link->verified_link_cap.link_rate = LINK_RATE_LOW; | |
2012 | link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED; | |
e7f2c80c WL |
2013 | break; |
2014 | } else if (dp_verify_link_cap(link, | |
2015 | &link->reported_link_cap, | |
2016 | &fail_count) && fail_count == 0) { | |
2017 | success = true; | |
2018 | break; | |
2019 | } | |
2020 | msleep(10); | |
2021 | } | |
2022 | return success; | |
2023 | } | |
2024 | ||
f537d474 LH |
2025 | bool dp_verify_mst_link_cap( |
2026 | struct dc_link *link) | |
2027 | { | |
2028 | struct dc_link_settings max_link_cap = {0}; | |
2029 | ||
2030 | max_link_cap = get_max_link_cap(link); | |
2031 | link->verified_link_cap = get_common_supported_link_settings( | |
2032 | link->reported_link_cap, | |
2033 | max_link_cap); | |
2034 | ||
2035 | return true; | |
2036 | } | |
2037 | ||
9a6a8075 | 2038 | static struct dc_link_settings get_common_supported_link_settings( |
820e3935 DW |
2039 | struct dc_link_settings link_setting_a, |
2040 | struct dc_link_settings link_setting_b) | |
2041 | { | |
2042 | struct dc_link_settings link_settings = {0}; | |
2043 | ||
2044 | link_settings.lane_count = | |
2045 | (link_setting_a.lane_count <= | |
2046 | link_setting_b.lane_count) ? | |
2047 | link_setting_a.lane_count : | |
2048 | link_setting_b.lane_count; | |
2049 | link_settings.link_rate = | |
2050 | (link_setting_a.link_rate <= | |
2051 | link_setting_b.link_rate) ? | |
2052 | link_setting_a.link_rate : | |
2053 | link_setting_b.link_rate; | |
2054 | link_settings.link_spread = LINK_SPREAD_DISABLED; | |
2055 | ||
2056 | /* in DP compliance test, DPR-120 may have | |
2057 | * a random value in its MAX_LINK_BW dpcd field. | |
2058 | * We map it to the maximum supported link rate that | |
2059 | * is smaller than MAX_LINK_BW in this case. | |
2060 | */ | |
2061 | if (link_settings.link_rate > LINK_RATE_HIGH3) { | |
2062 | link_settings.link_rate = LINK_RATE_HIGH3; | |
2063 | } else if (link_settings.link_rate < LINK_RATE_HIGH3 | |
2064 | && link_settings.link_rate > LINK_RATE_HIGH2) { | |
2065 | link_settings.link_rate = LINK_RATE_HIGH2; | |
2066 | } else if (link_settings.link_rate < LINK_RATE_HIGH2 | |
2067 | && link_settings.link_rate > LINK_RATE_HIGH) { | |
2068 | link_settings.link_rate = LINK_RATE_HIGH; | |
2069 | } else if (link_settings.link_rate < LINK_RATE_HIGH | |
2070 | && link_settings.link_rate > LINK_RATE_LOW) { | |
2071 | link_settings.link_rate = LINK_RATE_LOW; | |
2072 | } else if (link_settings.link_rate < LINK_RATE_LOW) { | |
2073 | link_settings.link_rate = LINK_RATE_UNKNOWN; | |
2074 | } | |
2075 | ||
2076 | return link_settings; | |
2077 | } | |
2078 | ||
450619d3 | 2079 | static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) |
820e3935 DW |
2080 | { |
2081 | return lane_count <= LANE_COUNT_ONE; | |
2082 | } | |
2083 | ||
450619d3 | 2084 | static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate) |
820e3935 DW |
2085 | { |
2086 | return link_rate <= LINK_RATE_LOW; | |
2087 | } | |
2088 | ||
44858055 | 2089 | static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) |
820e3935 DW |
2090 | { |
2091 | switch (lane_count) { | |
2092 | case LANE_COUNT_FOUR: | |
2093 | return LANE_COUNT_TWO; | |
2094 | case LANE_COUNT_TWO: | |
2095 | return LANE_COUNT_ONE; | |
2096 | case LANE_COUNT_ONE: | |
2097 | return LANE_COUNT_UNKNOWN; | |
2098 | default: | |
2099 | return LANE_COUNT_UNKNOWN; | |
2100 | } | |
2101 | } | |
2102 | ||
04e21292 | 2103 | static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate) |
820e3935 DW |
2104 | { |
2105 | switch (link_rate) { | |
2106 | case LINK_RATE_HIGH3: | |
2107 | return LINK_RATE_HIGH2; | |
2108 | case LINK_RATE_HIGH2: | |
2109 | return LINK_RATE_HIGH; | |
2110 | case LINK_RATE_HIGH: | |
2111 | return LINK_RATE_LOW; | |
2112 | case LINK_RATE_LOW: | |
2113 | return LINK_RATE_UNKNOWN; | |
2114 | default: | |
2115 | return LINK_RATE_UNKNOWN; | |
2116 | } | |
2117 | } | |
2118 | ||
04e21292 | 2119 | static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) |
8c4abe0b DW |
2120 | { |
2121 | switch (lane_count) { | |
2122 | case LANE_COUNT_ONE: | |
2123 | return LANE_COUNT_TWO; | |
2124 | case LANE_COUNT_TWO: | |
2125 | return LANE_COUNT_FOUR; | |
2126 | default: | |
2127 | return LANE_COUNT_UNKNOWN; | |
2128 | } | |
2129 | } | |
2130 | ||
04e21292 | 2131 | static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate) |
8c4abe0b DW |
2132 | { |
2133 | switch (link_rate) { | |
2134 | case LINK_RATE_LOW: | |
2135 | return LINK_RATE_HIGH; | |
2136 | case LINK_RATE_HIGH: | |
2137 | return LINK_RATE_HIGH2; | |
2138 | case LINK_RATE_HIGH2: | |
2139 | return LINK_RATE_HIGH3; | |
2140 | default: | |
2141 | return LINK_RATE_UNKNOWN; | |
2142 | } | |
2143 | } | |
2144 | ||
820e3935 DW |
2145 | /* |
2146 | * function: set link rate and lane count fallback based | |
2147 | * on current link setting and last link training result | |
2148 | * return value: | |
2149 | * true - link setting could be set | |
2150 | * false - has reached minimum setting | |
2151 | * and no further fallback could be done | |
2152 | */ | |
04e21292 | 2153 | static bool decide_fallback_link_setting( |
820e3935 DW |
2154 | struct dc_link_settings initial_link_settings, |
2155 | struct dc_link_settings *current_link_setting, | |
2156 | enum link_training_result training_result) | |
2157 | { | |
2158 | if (!current_link_setting) | |
2159 | return false; | |
2160 | ||
2161 | switch (training_result) { | |
94405cf6 WL |
2162 | case LINK_TRAINING_CR_FAIL_LANE0: |
2163 | case LINK_TRAINING_CR_FAIL_LANE1: | |
2164 | case LINK_TRAINING_CR_FAIL_LANE23: | |
2165 | case LINK_TRAINING_LQA_FAIL: | |
820e3935 DW |
2166 | { |
2167 | if (!reached_minimum_link_rate | |
2168 | (current_link_setting->link_rate)) { | |
2169 | current_link_setting->link_rate = | |
2170 | reduce_link_rate( | |
2171 | current_link_setting->link_rate); | |
2172 | } else if (!reached_minimum_lane_count | |
2173 | (current_link_setting->lane_count)) { | |
2174 | current_link_setting->link_rate = | |
2175 | initial_link_settings.link_rate; | |
94405cf6 WL |
2176 | if (training_result == LINK_TRAINING_CR_FAIL_LANE0) |
2177 | return false; | |
2178 | else if (training_result == LINK_TRAINING_CR_FAIL_LANE1) | |
2179 | current_link_setting->lane_count = | |
2180 | LANE_COUNT_ONE; | |
2181 | else if (training_result == | |
2182 | LINK_TRAINING_CR_FAIL_LANE23) | |
2183 | current_link_setting->lane_count = | |
2184 | LANE_COUNT_TWO; | |
2185 | else | |
2186 | current_link_setting->lane_count = | |
2187 | reduce_lane_count( | |
820e3935 DW |
2188 | current_link_setting->lane_count); |
2189 | } else { | |
2190 | return false; | |
2191 | } | |
2192 | break; | |
2193 | } | |
2194 | case LINK_TRAINING_EQ_FAIL_EQ: | |
2195 | { | |
2196 | if (!reached_minimum_lane_count | |
2197 | (current_link_setting->lane_count)) { | |
2198 | current_link_setting->lane_count = | |
2199 | reduce_lane_count( | |
2200 | current_link_setting->lane_count); | |
2201 | } else if (!reached_minimum_link_rate | |
2202 | (current_link_setting->link_rate)) { | |
820e3935 DW |
2203 | current_link_setting->link_rate = |
2204 | reduce_link_rate( | |
2205 | current_link_setting->link_rate); | |
2206 | } else { | |
2207 | return false; | |
2208 | } | |
2209 | break; | |
2210 | } | |
2211 | case LINK_TRAINING_EQ_FAIL_CR: | |
2212 | { | |
2213 | if (!reached_minimum_link_rate | |
2214 | (current_link_setting->link_rate)) { | |
2215 | current_link_setting->link_rate = | |
2216 | reduce_link_rate( | |
2217 | current_link_setting->link_rate); | |
2218 | } else { | |
2219 | return false; | |
2220 | } | |
2221 | break; | |
2222 | } | |
2223 | default: | |
2224 | return false; | |
2225 | } | |
2226 | return true; | |
2227 | } | |
2228 | ||
4562236b | 2229 | bool dp_validate_mode_timing( |
d0778ebf | 2230 | struct dc_link *link, |
4562236b HW |
2231 | const struct dc_crtc_timing *timing) |
2232 | { | |
2233 | uint32_t req_bw; | |
2234 | uint32_t max_bw; | |
2235 | ||
2236 | const struct dc_link_settings *link_setting; | |
2237 | ||
2238 | /*always DP fail safe mode*/ | |
380604e2 | 2239 | if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 && |
9a6a8075 HW |
2240 | timing->h_addressable == (uint32_t) 640 && |
2241 | timing->v_addressable == (uint32_t) 480) | |
4562236b HW |
2242 | return true; |
2243 | ||
5ac4619b | 2244 | link_setting = dc_link_get_link_cap(link); |
4562236b HW |
2245 | |
2246 | /* TODO: DYNAMIC_VALIDATION needs to be implemented */ | |
2247 | /*if (flags.DYNAMIC_VALIDATION == 1 && | |
d0778ebf HW |
2248 | link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) |
2249 | link_setting = &link->verified_link_cap; | |
4562236b HW |
2250 | */ |
2251 | ||
e49f6936 | 2252 | req_bw = dc_bandwidth_in_kbps_from_timing(timing); |
332c1191 | 2253 | max_bw = dc_link_bandwidth_kbps(link, link_setting); |
4562236b HW |
2254 | |
2255 | if (req_bw <= max_bw) { | |
2256 | /* remember the biggest mode here, during | |
2257 | * initial link training (to get | |
2258 | * verified_link_cap), LS sends event about | |
2259 | * cannot train at reported cap to upper | |
2260 | * layer and upper layer will re-enumerate modes. | |
2261 | * this is not necessary if the lower | |
2262 | * verified_link_cap is enough to drive | |
2263 | * all the modes */ | |
2264 | ||
2265 | /* TODO: DYNAMIC_VALIDATION needs to be implemented */ | |
2266 | /* if (flags.DYNAMIC_VALIDATION == 1) | |
2267 | dpsst->max_req_bw_for_verified_linkcap = dal_max( | |
2268 | dpsst->max_req_bw_for_verified_linkcap, req_bw); */ | |
2269 | return true; | |
2270 | } else | |
2271 | return false; | |
2272 | } | |
2273 | ||
8628d02f | 2274 | static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw) |
4562236b | 2275 | { |
8c4abe0b | 2276 | struct dc_link_settings initial_link_setting = { |
8628d02f | 2277 | LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0}; |
8c4abe0b DW |
2278 | struct dc_link_settings current_link_setting = |
2279 | initial_link_setting; | |
4562236b | 2280 | uint32_t link_bw; |
4562236b | 2281 | |
8628d02f JP |
2282 | /* search for the minimum link setting that: |
2283 | * 1. is supported according to the link training result | |
2284 | * 2. could support the b/w requested by the timing | |
4562236b | 2285 | */ |
8628d02f JP |
2286 | while (current_link_setting.link_rate <= |
2287 | link->verified_link_cap.link_rate) { | |
332c1191 NC |
2288 | link_bw = dc_link_bandwidth_kbps( |
2289 | link, | |
8628d02f JP |
2290 | ¤t_link_setting); |
2291 | if (req_bw <= link_bw) { | |
2292 | *link_setting = current_link_setting; | |
2293 | return true; | |
2294 | } | |
4562236b | 2295 | |
8628d02f JP |
2296 | if (current_link_setting.lane_count < |
2297 | link->verified_link_cap.lane_count) { | |
2298 | current_link_setting.lane_count = | |
2299 | increase_lane_count( | |
2300 | current_link_setting.lane_count); | |
2301 | } else { | |
2302 | current_link_setting.link_rate = | |
2303 | increase_link_rate( | |
2304 | current_link_setting.link_rate); | |
2305 | current_link_setting.lane_count = | |
2306 | initial_link_setting.lane_count; | |
2307 | } | |
3f1f74f4 JZ |
2308 | } |
2309 | ||
8628d02f JP |
2310 | return false; |
2311 | } | |
2312 | ||
2313 | static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw) | |
2314 | { | |
2315 | struct dc_link_settings initial_link_setting; | |
2316 | struct dc_link_settings current_link_setting; | |
2317 | uint32_t link_bw; | |
2318 | ||
2319 | if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 || | |
53c81fc7 | 2320 | link->dpcd_caps.edp_supported_link_rates_count == 0) { |
4d2f22d1 | 2321 | *link_setting = link->verified_link_cap; |
8628d02f | 2322 | return true; |
4d2f22d1 HH |
2323 | } |
2324 | ||
8628d02f JP |
2325 | memset(&initial_link_setting, 0, sizeof(initial_link_setting)); |
2326 | initial_link_setting.lane_count = LANE_COUNT_ONE; | |
2327 | initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0]; | |
2328 | initial_link_setting.link_spread = LINK_SPREAD_DISABLED; | |
2329 | initial_link_setting.use_link_rate_set = true; | |
2330 | initial_link_setting.link_rate_set = 0; | |
2331 | current_link_setting = initial_link_setting; | |
2332 | ||
5667ff5c DA |
2333 | /* search for the minimum link setting that: |
2334 | * 1. is supported according to the link training result | |
2335 | * 2. could support the b/w requested by the timing | |
2336 | */ | |
8c4abe0b | 2337 | while (current_link_setting.link_rate <= |
4654a2f7 | 2338 | link->verified_link_cap.link_rate) { |
332c1191 NC |
2339 | link_bw = dc_link_bandwidth_kbps( |
2340 | link, | |
8c4abe0b DW |
2341 | ¤t_link_setting); |
2342 | if (req_bw <= link_bw) { | |
2343 | *link_setting = current_link_setting; | |
8628d02f | 2344 | return true; |
4562236b | 2345 | } |
4562236b | 2346 | |
8c4abe0b | 2347 | if (current_link_setting.lane_count < |
4654a2f7 | 2348 | link->verified_link_cap.lane_count) { |
8c4abe0b DW |
2349 | current_link_setting.lane_count = |
2350 | increase_lane_count( | |
2351 | current_link_setting.lane_count); | |
2352 | } else { | |
8628d02f JP |
2353 | if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { |
2354 | current_link_setting.link_rate_set++; | |
2355 | current_link_setting.link_rate = | |
2356 | link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; | |
2357 | current_link_setting.lane_count = | |
2358 | initial_link_setting.lane_count; | |
2359 | } else | |
2360 | break; | |
4562236b HW |
2361 | } |
2362 | } | |
8628d02f JP |
2363 | return false; |
2364 | } | |
2365 | ||
2366 | void decide_link_settings(struct dc_stream_state *stream, | |
2367 | struct dc_link_settings *link_setting) | |
2368 | { | |
2369 | struct dc_link *link; | |
2370 | uint32_t req_bw; | |
2371 | ||
e49f6936 | 2372 | req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing); |
8628d02f JP |
2373 | |
2374 | link = stream->link; | |
2375 | ||
2376 | /* if preferred is specified through AMDDP, use it, if it's enough | |
2377 | * to drive the mode | |
2378 | */ | |
2379 | if (link->preferred_link_setting.lane_count != | |
2380 | LANE_COUNT_UNKNOWN && | |
2381 | link->preferred_link_setting.link_rate != | |
2382 | LINK_RATE_UNKNOWN) { | |
2383 | *link_setting = link->preferred_link_setting; | |
2384 | return; | |
2385 | } | |
2386 | ||
2387 | /* MST doesn't perform link training for now | |
2388 | * TODO: add MST specific link training routine | |
2389 | */ | |
2390 | if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { | |
2391 | *link_setting = link->verified_link_cap; | |
2392 | return; | |
2393 | } | |
2394 | ||
2395 | if (link->connector_signal == SIGNAL_TYPE_EDP) { | |
2396 | if (decide_edp_link_settings(link, link_setting, req_bw)) | |
2397 | return; | |
2398 | } else if (decide_dp_link_settings(link, link_setting, req_bw)) | |
2399 | return; | |
4562236b HW |
2400 | |
2401 | BREAK_TO_DEBUGGER(); | |
d0778ebf | 2402 | ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN); |
4562236b | 2403 | |
d0778ebf | 2404 | *link_setting = link->verified_link_cap; |
4562236b HW |
2405 | } |
2406 | ||
2407 | /*************************Short Pulse IRQ***************************/ | |
d0778ebf | 2408 | static bool allow_hpd_rx_irq(const struct dc_link *link) |
4562236b HW |
2409 | { |
2410 | /* | |
2411 | * Don't handle RX IRQ unless one of following is met: | |
2412 | * 1) The link is established (cur_link_settings != unknown) | |
2413 | * 2) We kicked off MST detection | |
2414 | * 3) We know we're dealing with an active dongle | |
2415 | */ | |
2416 | ||
d0778ebf HW |
2417 | if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || |
2418 | (link->type == dc_connection_mst_branch) || | |
4562236b HW |
2419 | is_dp_active_dongle(link)) |
2420 | return true; | |
2421 | ||
2422 | return false; | |
2423 | } | |
2424 | ||
ab4a4072 | 2425 | static bool handle_hpd_irq_psr_sink(struct dc_link *link) |
4562236b HW |
2426 | { |
2427 | union dpcd_psr_configuration psr_configuration; | |
2428 | ||
ab4a4072 | 2429 | if (!link->psr_feature_enabled) |
4562236b HW |
2430 | return false; |
2431 | ||
7c7f5b15 AG |
2432 | dm_helpers_dp_read_dpcd( |
2433 | link->ctx, | |
d0778ebf | 2434 | link, |
7c7f5b15 AG |
2435 | 368,/*DpcdAddress_PSR_Enable_Cfg*/ |
2436 | &psr_configuration.raw, | |
2437 | sizeof(psr_configuration.raw)); | |
2438 | ||
4562236b HW |
2439 | |
2440 | if (psr_configuration.bits.ENABLE) { | |
2441 | unsigned char dpcdbuf[3] = {0}; | |
2442 | union psr_error_status psr_error_status; | |
2443 | union psr_sink_psr_status psr_sink_psr_status; | |
2444 | ||
7c7f5b15 AG |
2445 | dm_helpers_dp_read_dpcd( |
2446 | link->ctx, | |
d0778ebf | 2447 | link, |
7c7f5b15 AG |
2448 | 0x2006, /*DpcdAddress_PSR_Error_Status*/ |
2449 | (unsigned char *) dpcdbuf, | |
2450 | sizeof(dpcdbuf)); | |
4562236b HW |
2451 | |
2452 | /*DPCD 2006h ERROR STATUS*/ | |
2453 | psr_error_status.raw = dpcdbuf[0]; | |
2454 | /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/ | |
2455 | psr_sink_psr_status.raw = dpcdbuf[2]; | |
2456 | ||
2457 | if (psr_error_status.bits.LINK_CRC_ERROR || | |
2458 | psr_error_status.bits.RFB_STORAGE_ERROR) { | |
2459 | /* Acknowledge and clear error bits */ | |
7c7f5b15 AG |
2460 | dm_helpers_dp_write_dpcd( |
2461 | link->ctx, | |
d0778ebf | 2462 | link, |
7c7f5b15 | 2463 | 8198,/*DpcdAddress_PSR_Error_Status*/ |
4562236b HW |
2464 | &psr_error_status.raw, |
2465 | sizeof(psr_error_status.raw)); | |
2466 | ||
2467 | /* PSR error, disable and re-enable PSR */ | |
ab4a4072 EY |
2468 | dc_link_set_psr_allow_active(link, false, true); |
2469 | dc_link_set_psr_allow_active(link, true, true); | |
4562236b HW |
2470 | |
2471 | return true; | |
2472 | } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS == | |
2473 | PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){ | |
2474 | /* No error is detect, PSR is active. | |
2475 | * We should return with IRQ_HPD handled without | |
2476 | * checking for loss of sync since PSR would have | |
2477 | * powered down main link. | |
2478 | */ | |
2479 | return true; | |
2480 | } | |
2481 | } | |
2482 | return false; | |
2483 | } | |
2484 | ||
d0778ebf | 2485 | static void dp_test_send_link_training(struct dc_link *link) |
4562236b | 2486 | { |
73c72602 | 2487 | struct dc_link_settings link_settings = {0}; |
4562236b HW |
2488 | |
2489 | core_link_read_dpcd( | |
2490 | link, | |
3a340294 | 2491 | DP_TEST_LANE_COUNT, |
4562236b HW |
2492 | (unsigned char *)(&link_settings.lane_count), |
2493 | 1); | |
2494 | core_link_read_dpcd( | |
2495 | link, | |
3a340294 | 2496 | DP_TEST_LINK_RATE, |
4562236b HW |
2497 | (unsigned char *)(&link_settings.link_rate), |
2498 | 1); | |
2499 | ||
2500 | /* Set preferred link settings */ | |
d0778ebf HW |
2501 | link->verified_link_cap.lane_count = link_settings.lane_count; |
2502 | link->verified_link_cap.link_rate = link_settings.link_rate; | |
4562236b | 2503 | |
73c72602 | 2504 | dp_retrain_link_dp_test(link, &link_settings, false); |
4562236b HW |
2505 | } |
2506 | ||
9315e239 | 2507 | /* TODO Raven hbr2 compliance eye output is unstable |
25bab0da WL |
2508 | * (toggling on and off) with debugger break |
2509 | * This caueses intermittent PHY automation failure | |
2510 | * Need to look into the root cause */ | |
d0778ebf | 2511 | static void dp_test_send_phy_test_pattern(struct dc_link *link) |
4562236b HW |
2512 | { |
2513 | union phy_test_pattern dpcd_test_pattern; | |
2514 | union lane_adjust dpcd_lane_adjustment[2]; | |
2515 | unsigned char dpcd_post_cursor_2_adjustment = 0; | |
2516 | unsigned char test_80_bit_pattern[ | |
3a340294 DA |
2517 | (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 - |
2518 | DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0}; | |
4562236b HW |
2519 | enum dp_test_pattern test_pattern; |
2520 | struct dc_link_training_settings link_settings; | |
2521 | union lane_adjust dpcd_lane_adjust; | |
2522 | unsigned int lane; | |
2523 | struct link_training_settings link_training_settings; | |
2524 | int i = 0; | |
2525 | ||
2526 | dpcd_test_pattern.raw = 0; | |
2527 | memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment)); | |
2528 | memset(&link_settings, 0, sizeof(link_settings)); | |
2529 | ||
2530 | /* get phy test pattern and pattern parameters from DP receiver */ | |
2531 | core_link_read_dpcd( | |
2532 | link, | |
3a340294 | 2533 | DP_TEST_PHY_PATTERN, |
4562236b HW |
2534 | &dpcd_test_pattern.raw, |
2535 | sizeof(dpcd_test_pattern)); | |
2536 | core_link_read_dpcd( | |
2537 | link, | |
3a340294 | 2538 | DP_ADJUST_REQUEST_LANE0_1, |
4562236b HW |
2539 | &dpcd_lane_adjustment[0].raw, |
2540 | sizeof(dpcd_lane_adjustment)); | |
2541 | ||
2542 | /*get post cursor 2 parameters | |
2543 | * For DP 1.1a or eariler, this DPCD register's value is 0 | |
2544 | * For DP 1.2 or later: | |
2545 | * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1 | |
2546 | * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3 | |
2547 | */ | |
2548 | core_link_read_dpcd( | |
2549 | link, | |
3a340294 | 2550 | DP_ADJUST_REQUEST_POST_CURSOR2, |
4562236b HW |
2551 | &dpcd_post_cursor_2_adjustment, |
2552 | sizeof(dpcd_post_cursor_2_adjustment)); | |
2553 | ||
2554 | /* translate request */ | |
2555 | switch (dpcd_test_pattern.bits.PATTERN) { | |
2556 | case PHY_TEST_PATTERN_D10_2: | |
2557 | test_pattern = DP_TEST_PATTERN_D102; | |
0e19401f | 2558 | break; |
4562236b HW |
2559 | case PHY_TEST_PATTERN_SYMBOL_ERROR: |
2560 | test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR; | |
0e19401f | 2561 | break; |
4562236b HW |
2562 | case PHY_TEST_PATTERN_PRBS7: |
2563 | test_pattern = DP_TEST_PATTERN_PRBS7; | |
0e19401f | 2564 | break; |
4562236b HW |
2565 | case PHY_TEST_PATTERN_80BIT_CUSTOM: |
2566 | test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM; | |
0e19401f TC |
2567 | break; |
2568 | case PHY_TEST_PATTERN_CP2520_1: | |
25bab0da | 2569 | /* CP2520 pattern is unstable, temporarily use TPS4 instead */ |
9315e239 | 2570 | test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ? |
25bab0da WL |
2571 | DP_TEST_PATTERN_TRAINING_PATTERN4 : |
2572 | DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE; | |
0e19401f TC |
2573 | break; |
2574 | case PHY_TEST_PATTERN_CP2520_2: | |
25bab0da | 2575 | /* CP2520 pattern is unstable, temporarily use TPS4 instead */ |
9315e239 | 2576 | test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ? |
25bab0da WL |
2577 | DP_TEST_PATTERN_TRAINING_PATTERN4 : |
2578 | DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE; | |
0e19401f TC |
2579 | break; |
2580 | case PHY_TEST_PATTERN_CP2520_3: | |
78e685f9 | 2581 | test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4; |
0e19401f | 2582 | break; |
4562236b HW |
2583 | default: |
2584 | test_pattern = DP_TEST_PATTERN_VIDEO_MODE; | |
2585 | break; | |
2586 | } | |
2587 | ||
2588 | if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) | |
2589 | core_link_read_dpcd( | |
2590 | link, | |
3a340294 | 2591 | DP_TEST_80BIT_CUSTOM_PATTERN_7_0, |
4562236b HW |
2592 | test_80_bit_pattern, |
2593 | sizeof(test_80_bit_pattern)); | |
2594 | ||
2595 | /* prepare link training settings */ | |
d0778ebf | 2596 | link_settings.link = link->cur_link_settings; |
4562236b HW |
2597 | |
2598 | for (lane = 0; lane < | |
d0778ebf | 2599 | (unsigned int)(link->cur_link_settings.lane_count); |
4562236b HW |
2600 | lane++) { |
2601 | dpcd_lane_adjust.raw = | |
2602 | get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane); | |
2603 | link_settings.lane_settings[lane].VOLTAGE_SWING = | |
2604 | (enum dc_voltage_swing) | |
2605 | (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE); | |
2606 | link_settings.lane_settings[lane].PRE_EMPHASIS = | |
2607 | (enum dc_pre_emphasis) | |
2608 | (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE); | |
2609 | link_settings.lane_settings[lane].POST_CURSOR2 = | |
2610 | (enum dc_post_cursor2) | |
2611 | ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03); | |
2612 | } | |
2613 | ||
2614 | for (i = 0; i < 4; i++) | |
2615 | link_training_settings.lane_settings[i] = | |
2616 | link_settings.lane_settings[i]; | |
2617 | link_training_settings.link_settings = link_settings.link; | |
2618 | link_training_settings.allow_invalid_msa_timing_param = false; | |
2619 | /*Usage: Measure DP physical lane signal | |
2620 | * by DP SI test equipment automatically. | |
2621 | * PHY test pattern request is generated by equipment via HPD interrupt. | |
2622 | * HPD needs to be active all the time. HPD should be active | |
2623 | * all the time. Do not touch it. | |
2624 | * forward request to DS | |
2625 | */ | |
2626 | dc_link_dp_set_test_pattern( | |
d0778ebf | 2627 | link, |
4562236b | 2628 | test_pattern, |
2057b7e1 | 2629 | DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED, |
4562236b HW |
2630 | &link_training_settings, |
2631 | test_80_bit_pattern, | |
3a340294 DA |
2632 | (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 - |
2633 | DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1); | |
4562236b HW |
2634 | } |
2635 | ||
d0778ebf | 2636 | static void dp_test_send_link_test_pattern(struct dc_link *link) |
4562236b HW |
2637 | { |
2638 | union link_test_pattern dpcd_test_pattern; | |
2639 | union test_misc dpcd_test_params; | |
2640 | enum dp_test_pattern test_pattern; | |
2057b7e1 WL |
2641 | enum dp_test_pattern_color_space test_pattern_color_space = |
2642 | DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; | |
4562236b HW |
2643 | |
2644 | memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern)); | |
2645 | memset(&dpcd_test_params, 0, sizeof(dpcd_test_params)); | |
2646 | ||
2647 | /* get link test pattern and pattern parameters */ | |
2648 | core_link_read_dpcd( | |
2649 | link, | |
3a340294 | 2650 | DP_TEST_PATTERN, |
4562236b HW |
2651 | &dpcd_test_pattern.raw, |
2652 | sizeof(dpcd_test_pattern)); | |
2653 | core_link_read_dpcd( | |
2654 | link, | |
3a340294 | 2655 | DP_TEST_MISC0, |
4562236b HW |
2656 | &dpcd_test_params.raw, |
2657 | sizeof(dpcd_test_params)); | |
2658 | ||
2659 | switch (dpcd_test_pattern.bits.PATTERN) { | |
2660 | case LINK_TEST_PATTERN_COLOR_RAMP: | |
2661 | test_pattern = DP_TEST_PATTERN_COLOR_RAMP; | |
2662 | break; | |
2663 | case LINK_TEST_PATTERN_VERTICAL_BARS: | |
2664 | test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; | |
2665 | break; /* black and white */ | |
2666 | case LINK_TEST_PATTERN_COLOR_SQUARES: | |
2667 | test_pattern = (dpcd_test_params.bits.DYN_RANGE == | |
2668 | TEST_DYN_RANGE_VESA ? | |
2669 | DP_TEST_PATTERN_COLOR_SQUARES : | |
2670 | DP_TEST_PATTERN_COLOR_SQUARES_CEA); | |
2671 | break; | |
2672 | default: | |
2673 | test_pattern = DP_TEST_PATTERN_VIDEO_MODE; | |
2674 | break; | |
2675 | } | |
2676 | ||
2057b7e1 WL |
2677 | test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? |
2678 | DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : | |
2679 | DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; | |
2680 | ||
4562236b | 2681 | dc_link_dp_set_test_pattern( |
d0778ebf | 2682 | link, |
4562236b | 2683 | test_pattern, |
2057b7e1 | 2684 | test_pattern_color_space, |
4562236b HW |
2685 | NULL, |
2686 | NULL, | |
2687 | 0); | |
2688 | } | |
2689 | ||
8c8048f2 | 2690 | static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video) |
2691 | { | |
2692 | union audio_test_mode dpcd_test_mode = {0}; | |
2693 | struct audio_test_pattern_type dpcd_pattern_type = {0}; | |
2694 | union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0}; | |
2695 | enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED; | |
2696 | ||
2697 | struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; | |
2698 | struct pipe_ctx *pipe_ctx = &pipes[0]; | |
2699 | unsigned int channel_count; | |
2700 | unsigned int channel = 0; | |
2701 | unsigned int modes = 0; | |
2702 | unsigned int sampling_rate_in_hz = 0; | |
2703 | ||
2704 | // get audio test mode and test pattern parameters | |
2705 | core_link_read_dpcd( | |
2706 | link, | |
2707 | DP_TEST_AUDIO_MODE, | |
2708 | &dpcd_test_mode.raw, | |
2709 | sizeof(dpcd_test_mode)); | |
2710 | ||
2711 | core_link_read_dpcd( | |
2712 | link, | |
2713 | DP_TEST_AUDIO_PATTERN_TYPE, | |
2714 | &dpcd_pattern_type.value, | |
2715 | sizeof(dpcd_pattern_type)); | |
2716 | ||
2717 | channel_count = dpcd_test_mode.bits.channel_count + 1; | |
2718 | ||
2719 | // read pattern periods for requested channels when sawTooth pattern is requested | |
2720 | if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH || | |
2721 | dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) { | |
2722 | ||
2723 | test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ? | |
2724 | DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED; | |
2725 | // read period for each channel | |
2726 | for (channel = 0; channel < channel_count; channel++) { | |
2727 | core_link_read_dpcd( | |
2728 | link, | |
2729 | DP_TEST_AUDIO_PERIOD_CH1 + channel, | |
2730 | &dpcd_pattern_period[channel].raw, | |
2731 | sizeof(dpcd_pattern_period[channel])); | |
2732 | } | |
2733 | } | |
2734 | ||
2735 | // translate sampling rate | |
2736 | switch (dpcd_test_mode.bits.sampling_rate) { | |
2737 | case AUDIO_SAMPLING_RATE_32KHZ: | |
2738 | sampling_rate_in_hz = 32000; | |
2739 | break; | |
2740 | case AUDIO_SAMPLING_RATE_44_1KHZ: | |
2741 | sampling_rate_in_hz = 44100; | |
2742 | break; | |
2743 | case AUDIO_SAMPLING_RATE_48KHZ: | |
2744 | sampling_rate_in_hz = 48000; | |
2745 | break; | |
2746 | case AUDIO_SAMPLING_RATE_88_2KHZ: | |
2747 | sampling_rate_in_hz = 88200; | |
2748 | break; | |
2749 | case AUDIO_SAMPLING_RATE_96KHZ: | |
2750 | sampling_rate_in_hz = 96000; | |
2751 | break; | |
2752 | case AUDIO_SAMPLING_RATE_176_4KHZ: | |
2753 | sampling_rate_in_hz = 176400; | |
2754 | break; | |
2755 | case AUDIO_SAMPLING_RATE_192KHZ: | |
2756 | sampling_rate_in_hz = 192000; | |
2757 | break; | |
2758 | default: | |
2759 | sampling_rate_in_hz = 0; | |
2760 | break; | |
2761 | } | |
2762 | ||
2763 | link->audio_test_data.flags.test_requested = 1; | |
2764 | link->audio_test_data.flags.disable_video = disable_video; | |
2765 | link->audio_test_data.sampling_rate = sampling_rate_in_hz; | |
2766 | link->audio_test_data.channel_count = channel_count; | |
2767 | link->audio_test_data.pattern_type = test_pattern; | |
2768 | ||
2769 | if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) { | |
2770 | for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) { | |
2771 | link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period; | |
2772 | } | |
2773 | } | |
2774 | } | |
2775 | ||
d0778ebf | 2776 | static void handle_automated_test(struct dc_link *link) |
4562236b HW |
2777 | { |
2778 | union test_request test_request; | |
2779 | union test_response test_response; | |
2780 | ||
2781 | memset(&test_request, 0, sizeof(test_request)); | |
2782 | memset(&test_response, 0, sizeof(test_response)); | |
2783 | ||
2784 | core_link_read_dpcd( | |
2785 | link, | |
3a340294 | 2786 | DP_TEST_REQUEST, |
4562236b HW |
2787 | &test_request.raw, |
2788 | sizeof(union test_request)); | |
2789 | if (test_request.bits.LINK_TRAINING) { | |
2790 | /* ACK first to let DP RX test box monitor LT sequence */ | |
2791 | test_response.bits.ACK = 1; | |
2792 | core_link_write_dpcd( | |
2793 | link, | |
3a340294 | 2794 | DP_TEST_RESPONSE, |
4562236b HW |
2795 | &test_response.raw, |
2796 | sizeof(test_response)); | |
2797 | dp_test_send_link_training(link); | |
2798 | /* no acknowledge request is needed again */ | |
2799 | test_response.bits.ACK = 0; | |
2800 | } | |
2801 | if (test_request.bits.LINK_TEST_PATTRN) { | |
2802 | dp_test_send_link_test_pattern(link); | |
75a74755 | 2803 | test_response.bits.ACK = 1; |
4562236b | 2804 | } |
8c8048f2 | 2805 | |
2806 | if (test_request.bits.AUDIO_TEST_PATTERN) { | |
2807 | dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO); | |
2808 | test_response.bits.ACK = 1; | |
2809 | } | |
2810 | ||
4562236b HW |
2811 | if (test_request.bits.PHY_TEST_PATTERN) { |
2812 | dp_test_send_phy_test_pattern(link); | |
2813 | test_response.bits.ACK = 1; | |
2814 | } | |
a6729a5a | 2815 | |
4562236b HW |
2816 | /* send request acknowledgment */ |
2817 | if (test_response.bits.ACK) | |
2818 | core_link_write_dpcd( | |
2819 | link, | |
3a340294 | 2820 | DP_TEST_RESPONSE, |
4562236b HW |
2821 | &test_response.raw, |
2822 | sizeof(test_response)); | |
2823 | } | |
2824 | ||
4e18814e | 2825 | bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss) |
4562236b | 2826 | { |
9a6a8075 | 2827 | union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } }; |
c2e218dd | 2828 | union device_service_irq device_service_clear = { { 0 } }; |
d6258eaa | 2829 | enum dc_status result; |
4562236b | 2830 | bool status = false; |
48af9b91 | 2831 | struct pipe_ctx *pipe_ctx; |
99218d12 | 2832 | struct dc_link_settings previous_link_settings; |
48af9b91 | 2833 | int i; |
4e18814e FD |
2834 | |
2835 | if (out_link_loss) | |
2836 | *out_link_loss = false; | |
4562236b HW |
2837 | /* For use cases related to down stream connection status change, |
2838 | * PSR and device auto test, refer to function handle_sst_hpd_irq | |
2839 | * in DAL2.1*/ | |
2840 | ||
1296423b | 2841 | DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n", |
d0778ebf | 2842 | __func__, link->link_index); |
4562236b | 2843 | |
8ee65d7c | 2844 | |
4562236b HW |
2845 | /* All the "handle_hpd_irq_xxx()" methods |
2846 | * should be called only after | |
2847 | * dal_dpsst_ls_read_hpd_irq_data | |
2848 | * Order of calls is important too | |
2849 | */ | |
2850 | result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data); | |
8ee65d7c WL |
2851 | if (out_hpd_irq_dpcd_data) |
2852 | *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data; | |
4562236b HW |
2853 | |
2854 | if (result != DC_OK) { | |
1296423b | 2855 | DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n", |
4562236b HW |
2856 | __func__); |
2857 | return false; | |
2858 | } | |
2859 | ||
2860 | if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { | |
2861 | device_service_clear.bits.AUTOMATED_TEST = 1; | |
2862 | core_link_write_dpcd( | |
2863 | link, | |
3a340294 | 2864 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4562236b HW |
2865 | &device_service_clear.raw, |
2866 | sizeof(device_service_clear.raw)); | |
2867 | device_service_clear.raw = 0; | |
2868 | handle_automated_test(link); | |
2869 | return false; | |
2870 | } | |
2871 | ||
2872 | if (!allow_hpd_rx_irq(link)) { | |
1296423b | 2873 | DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n", |
d0778ebf | 2874 | __func__, link->link_index); |
4562236b HW |
2875 | return false; |
2876 | } | |
2877 | ||
2878 | if (handle_hpd_irq_psr_sink(link)) | |
2879 | /* PSR-related error was detected and handled */ | |
2880 | return true; | |
2881 | ||
2882 | /* If PSR-related error handled, Main link may be off, | |
2883 | * so do not handle as a normal sink status change interrupt. | |
2884 | */ | |
2885 | ||
aaa15026 WL |
2886 | if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY) |
2887 | return true; | |
2888 | ||
4562236b | 2889 | /* check if we have MST msg and return since we poll for it */ |
aaa15026 | 2890 | if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) |
4562236b HW |
2891 | return false; |
2892 | ||
2893 | /* For now we only handle 'Downstream port status' case. | |
2894 | * If we got sink count changed it means | |
2895 | * Downstream port status changed, | |
e97ed496 AK |
2896 | * then DM should call DC to do the detection. |
2897 | * NOTE: Do not handle link loss on eDP since it is internal link*/ | |
2898 | if ((link->connector_signal != SIGNAL_TYPE_EDP) && | |
2899 | hpd_rx_irq_check_link_loss_status( | |
2900 | link, | |
2901 | &hpd_irq_dpcd_data)) { | |
4562236b HW |
2902 | /* Connectivity log: link loss */ |
2903 | CONN_DATA_LINK_LOSS(link, | |
2904 | hpd_irq_dpcd_data.raw, | |
2905 | sizeof(hpd_irq_dpcd_data), | |
2906 | "Status: "); | |
2907 | ||
48af9b91 AL |
2908 | for (i = 0; i < MAX_PIPES; i++) { |
2909 | pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; | |
832aa63b PH |
2910 | if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link) |
2911 | break; | |
2912 | } | |
2913 | ||
2914 | if (pipe_ctx == NULL || pipe_ctx->stream == NULL) | |
2915 | return false; | |
2916 | ||
99218d12 | 2917 | previous_link_settings = link->cur_link_settings; |
832aa63b | 2918 | |
99218d12 | 2919 | perform_link_training_with_retries(&previous_link_settings, |
832aa63b PH |
2920 | true, LINK_TRAINING_ATTEMPTS, |
2921 | pipe_ctx, | |
2922 | pipe_ctx->stream->signal); | |
2923 | ||
ffdaeb1f PH |
2924 | if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) |
2925 | dc_link_reallocate_mst_payload(link); | |
48af9b91 | 2926 | |
4562236b | 2927 | status = false; |
4e18814e FD |
2928 | if (out_link_loss) |
2929 | *out_link_loss = true; | |
4562236b HW |
2930 | } |
2931 | ||
d0778ebf | 2932 | if (link->type == dc_connection_active_dongle && |
4562236b HW |
2933 | hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT |
2934 | != link->dpcd_sink_count) | |
2935 | status = true; | |
2936 | ||
2937 | /* reasons for HPD RX: | |
2938 | * 1. Link Loss - ie Re-train the Link | |
2939 | * 2. MST sideband message | |
2940 | * 3. Automated Test - ie. Internal Commit | |
2941 | * 4. CP (copy protection) - (not interesting for DM???) | |
2942 | * 5. DRR | |
2943 | * 6. Downstream Port status changed | |
2944 | * -ie. Detect - this the only one | |
2945 | * which is interesting for DM because | |
2946 | * it must call dc_link_detect. | |
2947 | */ | |
2948 | return status; | |
2949 | } | |
2950 | ||
2951 | /*query dpcd for version and mst cap addresses*/ | |
d0778ebf | 2952 | bool is_mst_supported(struct dc_link *link) |
4562236b HW |
2953 | { |
2954 | bool mst = false; | |
2955 | enum dc_status st = DC_OK; | |
2956 | union dpcd_rev rev; | |
2957 | union mstm_cap cap; | |
2958 | ||
0b226322 DG |
2959 | if (link->preferred_training_settings.mst_enable && |
2960 | *link->preferred_training_settings.mst_enable == false) { | |
2961 | return false; | |
2962 | } | |
2963 | ||
4562236b HW |
2964 | rev.raw = 0; |
2965 | cap.raw = 0; | |
2966 | ||
3a340294 | 2967 | st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw, |
4562236b HW |
2968 | sizeof(rev)); |
2969 | ||
2970 | if (st == DC_OK && rev.raw >= DPCD_REV_12) { | |
2971 | ||
3a340294 | 2972 | st = core_link_read_dpcd(link, DP_MSTM_CAP, |
4562236b HW |
2973 | &cap.raw, sizeof(cap)); |
2974 | if (st == DC_OK && cap.bits.MST_CAP == 1) | |
2975 | mst = true; | |
2976 | } | |
2977 | return mst; | |
2978 | ||
2979 | } | |
2980 | ||
d0778ebf | 2981 | bool is_dp_active_dongle(const struct dc_link *link) |
4562236b | 2982 | { |
a504ad26 | 2983 | return link->dpcd_caps.is_branch_dev; |
4562236b HW |
2984 | } |
2985 | ||
6bffebc9 EY |
2986 | static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc) |
2987 | { | |
2988 | switch (bpc) { | |
2989 | case DOWN_STREAM_MAX_8BPC: | |
2990 | return 8; | |
2991 | case DOWN_STREAM_MAX_10BPC: | |
2992 | return 10; | |
2993 | case DOWN_STREAM_MAX_12BPC: | |
2994 | return 12; | |
2995 | case DOWN_STREAM_MAX_16BPC: | |
2996 | return 16; | |
2997 | default: | |
2998 | break; | |
2999 | } | |
3000 | ||
3001 | return -1; | |
3002 | } | |
3003 | ||
ee13cea9 JB |
3004 | static void read_dp_device_vendor_id(struct dc_link *link) |
3005 | { | |
3006 | struct dp_device_vendor_id dp_id; | |
3007 | ||
3008 | /* read IEEE branch device id */ | |
3009 | core_link_read_dpcd( | |
3010 | link, | |
3011 | DP_BRANCH_OUI, | |
3012 | (uint8_t *)&dp_id, | |
3013 | sizeof(dp_id)); | |
3014 | ||
3015 | link->dpcd_caps.branch_dev_id = | |
3016 | (dp_id.ieee_oui[0] << 16) + | |
3017 | (dp_id.ieee_oui[1] << 8) + | |
3018 | dp_id.ieee_oui[2]; | |
3019 | ||
3020 | memmove( | |
3021 | link->dpcd_caps.branch_dev_name, | |
3022 | dp_id.ieee_device_id, | |
3023 | sizeof(dp_id.ieee_device_id)); | |
3024 | } | |
3025 | ||
3026 | ||
3027 | ||
4562236b | 3028 | static void get_active_converter_info( |
d0778ebf | 3029 | uint8_t data, struct dc_link *link) |
4562236b HW |
3030 | { |
3031 | union dp_downstream_port_present ds_port = { .byte = data }; | |
dd998291 | 3032 | memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps)); |
4562236b HW |
3033 | |
3034 | /* decode converter info*/ | |
3035 | if (!ds_port.fields.PORT_PRESENT) { | |
3036 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; | |
d0778ebf | 3037 | ddc_service_set_dongle_type(link->ddc, |
4562236b | 3038 | link->dpcd_caps.dongle_type); |
ac3d76e0 | 3039 | link->dpcd_caps.is_branch_dev = false; |
4562236b HW |
3040 | return; |
3041 | } | |
3042 | ||
a504ad26 | 3043 | /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */ |
ac3d76e0 HT |
3044 | if (ds_port.fields.PORT_TYPE == DOWNSTREAM_DP) { |
3045 | link->dpcd_caps.is_branch_dev = false; | |
3046 | } | |
3047 | ||
3048 | else { | |
3049 | link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT; | |
3050 | } | |
a504ad26 | 3051 | |
4562236b HW |
3052 | switch (ds_port.fields.PORT_TYPE) { |
3053 | case DOWNSTREAM_VGA: | |
3054 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER; | |
3055 | break; | |
7a83645a DZ |
3056 | case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS: |
3057 | /* At this point we don't know is it DVI or HDMI or DP++, | |
4562236b HW |
3058 | * assume DVI.*/ |
3059 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER; | |
3060 | break; | |
3061 | default: | |
3062 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; | |
3063 | break; | |
3064 | } | |
3065 | ||
ac0e562c | 3066 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) { |
242b0c8f | 3067 | uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/ |
4562236b HW |
3068 | union dwnstream_port_caps_byte0 *port_caps = |
3069 | (union dwnstream_port_caps_byte0 *)det_caps; | |
3a340294 | 3070 | core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0, |
4562236b HW |
3071 | det_caps, sizeof(det_caps)); |
3072 | ||
3073 | switch (port_caps->bits.DWN_STRM_PORTX_TYPE) { | |
7a83645a DZ |
3074 | /*Handle DP case as DONGLE_NONE*/ |
3075 | case DOWN_STREAM_DETAILED_DP: | |
3076 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; | |
3077 | break; | |
4562236b HW |
3078 | case DOWN_STREAM_DETAILED_VGA: |
3079 | link->dpcd_caps.dongle_type = | |
3080 | DISPLAY_DONGLE_DP_VGA_CONVERTER; | |
3081 | break; | |
3082 | case DOWN_STREAM_DETAILED_DVI: | |
3083 | link->dpcd_caps.dongle_type = | |
3084 | DISPLAY_DONGLE_DP_DVI_CONVERTER; | |
3085 | break; | |
3086 | case DOWN_STREAM_DETAILED_HDMI: | |
7a83645a DZ |
3087 | case DOWN_STREAM_DETAILED_DP_PLUS_PLUS: |
3088 | /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/ | |
4562236b HW |
3089 | link->dpcd_caps.dongle_type = |
3090 | DISPLAY_DONGLE_DP_HDMI_CONVERTER; | |
3091 | ||
03f5c686 | 3092 | link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type; |
4562236b HW |
3093 | if (ds_port.fields.DETAILED_CAPS) { |
3094 | ||
3095 | union dwnstream_port_caps_byte3_hdmi | |
3096 | hdmi_caps = {.raw = det_caps[3] }; | |
7d8d90d8 | 3097 | union dwnstream_port_caps_byte2 |
03f5c686 | 3098 | hdmi_color_caps = {.raw = det_caps[2] }; |
e5490464 S |
3099 | link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz = |
3100 | det_caps[1] * 2500; | |
4562236b | 3101 | |
03f5c686 | 3102 | link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter = |
4562236b | 3103 | hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK; |
7a83645a DZ |
3104 | /*YCBCR capability only for HDMI case*/ |
3105 | if (port_caps->bits.DWN_STRM_PORTX_TYPE | |
3106 | == DOWN_STREAM_DETAILED_HDMI) { | |
3107 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through = | |
3108 | hdmi_caps.bits.YCrCr422_PASS_THROUGH; | |
3109 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through = | |
3110 | hdmi_caps.bits.YCrCr420_PASS_THROUGH; | |
3111 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter = | |
3112 | hdmi_caps.bits.YCrCr422_CONVERSION; | |
3113 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter = | |
3114 | hdmi_caps.bits.YCrCr420_CONVERSION; | |
3115 | } | |
03f5c686 CL |
3116 | |
3117 | link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc = | |
6bffebc9 EY |
3118 | translate_dpcd_max_bpc( |
3119 | hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); | |
03f5c686 | 3120 | |
e5490464 | 3121 | if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) |
99b922f9 | 3122 | link->dpcd_caps.dongle_caps.extendedCapValid = true; |
4562236b | 3123 | } |
03f5c686 | 3124 | |
4562236b HW |
3125 | break; |
3126 | } | |
3127 | } | |
3128 | ||
d0778ebf | 3129 | ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type); |
4562236b | 3130 | |
4562236b HW |
3131 | { |
3132 | struct dp_sink_hw_fw_revision dp_hw_fw_revision; | |
3133 | ||
3134 | core_link_read_dpcd( | |
3135 | link, | |
3a340294 | 3136 | DP_BRANCH_REVISION_START, |
4562236b HW |
3137 | (uint8_t *)&dp_hw_fw_revision, |
3138 | sizeof(dp_hw_fw_revision)); | |
3139 | ||
3140 | link->dpcd_caps.branch_hw_revision = | |
3141 | dp_hw_fw_revision.ieee_hw_rev; | |
4b99affb A |
3142 | |
3143 | memmove( | |
3144 | link->dpcd_caps.branch_fw_revision, | |
3145 | dp_hw_fw_revision.ieee_fw_rev, | |
3146 | sizeof(dp_hw_fw_revision.ieee_fw_rev)); | |
4562236b HW |
3147 | } |
3148 | } | |
3149 | ||
d0778ebf | 3150 | static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data, |
4562236b HW |
3151 | int length) |
3152 | { | |
3153 | int retry = 0; | |
4562236b HW |
3154 | |
3155 | if (!link->dpcd_caps.dpcd_rev.raw) { | |
3156 | do { | |
3157 | dp_receiver_power_ctrl(link, true); | |
3a340294 | 3158 | core_link_read_dpcd(link, DP_DPCD_REV, |
4562236b HW |
3159 | dpcd_data, length); |
3160 | link->dpcd_caps.dpcd_rev.raw = dpcd_data[ | |
3a340294 DA |
3161 | DP_DPCD_REV - |
3162 | DP_DPCD_REV]; | |
4562236b HW |
3163 | } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw); |
3164 | } | |
3165 | ||
4562236b HW |
3166 | if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) { |
3167 | switch (link->dpcd_caps.branch_dev_id) { | |
df3b7e32 | 3168 | /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down |
4562236b HW |
3169 | * all internal circuits including AUX communication preventing |
3170 | * reading DPCD table and EDID (spec violation). | |
3171 | * Encoder will skip DP RX power down on disable_output to | |
3172 | * keep receiver powered all the time.*/ | |
df3b7e32 QZ |
3173 | case DP_BRANCH_DEVICE_ID_0010FA: |
3174 | case DP_BRANCH_DEVICE_ID_0080E1: | |
566b4252 | 3175 | case DP_BRANCH_DEVICE_ID_00E04C: |
4562236b HW |
3176 | link->wa_flags.dp_keep_receiver_powered = true; |
3177 | break; | |
3178 | ||
3179 | /* TODO: May need work around for other dongles. */ | |
3180 | default: | |
3181 | link->wa_flags.dp_keep_receiver_powered = false; | |
3182 | break; | |
3183 | } | |
3184 | } else | |
3185 | link->wa_flags.dp_keep_receiver_powered = false; | |
3186 | } | |
3187 | ||
96577cf8 HW |
3188 | /* Read additional sink caps defined in source specific DPCD area |
3189 | * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP) | |
3190 | */ | |
3191 | static bool dpcd_read_sink_ext_caps(struct dc_link *link) | |
3192 | { | |
3193 | uint8_t dpcd_data; | |
3194 | ||
3195 | if (!link) | |
3196 | return false; | |
3197 | ||
3198 | if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK) | |
3199 | return false; | |
3200 | ||
3201 | link->dpcd_sink_ext_caps.raw = dpcd_data; | |
3202 | return true; | |
3203 | } | |
3204 | ||
cdb39798 | 3205 | static bool retrieve_link_cap(struct dc_link *link) |
4562236b | 3206 | { |
61aa7a6f | 3207 | /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16, |
3208 | * which means size 16 will be good for both of those DPCD register block reads | |
3209 | */ | |
3210 | uint8_t dpcd_data[16]; | |
3211 | uint8_t lttpr_dpcd_data[6]; | |
4562236b | 3212 | |
3c7dd2cb HT |
3213 | /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST. |
3214 | */ | |
3215 | uint8_t dpcd_dprx_data = '\0'; | |
8633d96d | 3216 | uint8_t dpcd_power_state = '\0'; |
3c7dd2cb | 3217 | |
8ca80900 | 3218 | struct dp_device_vendor_id sink_id; |
4562236b HW |
3219 | union down_stream_port_count down_strm_port_count; |
3220 | union edp_configuration_cap edp_config_cap; | |
3221 | union dp_downstream_port_present ds_port = { 0 }; | |
cdb39798 | 3222 | enum dc_status status = DC_ERROR_UNEXPECTED; |
3c1a312a YS |
3223 | uint32_t read_dpcd_retry_cnt = 3; |
3224 | int i; | |
4b99affb | 3225 | struct dp_sink_hw_fw_revision dp_hw_fw_revision; |
4562236b | 3226 | |
8e5100a5 | 3227 | /* Set default timeout to 3.2ms and read LTTPR capabilities */ |
3228 | bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support && | |
3229 | !link->dc->config.disable_extended_timeout_support; | |
bad7ab0b | 3230 | |
903e859b | 3231 | link->is_lttpr_mode_transparent = true; |
3232 | ||
8e5100a5 | 3233 | if (ext_timeout_support) { |
61aa7a6f | 3234 | dc_link_aux_configure_timeout(link->ddc, |
3235 | LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD); | |
8e5100a5 | 3236 | } |
3237 | ||
4562236b | 3238 | memset(dpcd_data, '\0', sizeof(dpcd_data)); |
61aa7a6f | 3239 | memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data)); |
4562236b HW |
3240 | memset(&down_strm_port_count, |
3241 | '\0', sizeof(union down_stream_port_count)); | |
3242 | memset(&edp_config_cap, '\0', | |
3243 | sizeof(union edp_configuration_cap)); | |
3244 | ||
8633d96d AK |
3245 | status = core_link_read_dpcd(link, DP_SET_POWER, |
3246 | &dpcd_power_state, sizeof(dpcd_power_state)); | |
3247 | ||
3248 | /* Delay 1 ms if AUX CH is in power down state. Based on spec | |
3249 | * section 2.3.1.2, if AUX CH may be powered down due to | |
3250 | * write to DPCD 600h = 2. Sink AUX CH is monitoring differential | |
3251 | * signal and may need up to 1 ms before being able to reply. | |
3252 | */ | |
3253 | if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) | |
3254 | udelay(1000); | |
3255 | ||
3c1a312a YS |
3256 | for (i = 0; i < read_dpcd_retry_cnt; i++) { |
3257 | status = core_link_read_dpcd( | |
3258 | link, | |
3259 | DP_DPCD_REV, | |
3260 | dpcd_data, | |
3261 | sizeof(dpcd_data)); | |
3262 | if (status == DC_OK) | |
3263 | break; | |
3264 | } | |
cdb39798 YS |
3265 | |
3266 | if (status != DC_OK) { | |
3267 | dm_error("%s: Read dpcd data failed.\n", __func__); | |
3268 | return false; | |
3269 | } | |
4562236b | 3270 | |
9bffd080 | 3271 | if (ext_timeout_support) { |
61aa7a6f | 3272 | |
8e5100a5 | 3273 | status = core_link_read_dpcd( |
3274 | link, | |
61aa7a6f | 3275 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, |
3276 | lttpr_dpcd_data, | |
3277 | sizeof(lttpr_dpcd_data)); | |
3278 | ||
3279 | link->dpcd_caps.lttpr_caps.revision.raw = | |
3280 | lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV - | |
3281 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3282 | ||
3283 | link->dpcd_caps.lttpr_caps.max_link_rate = | |
3284 | lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER - | |
3285 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3286 | ||
3287 | link->dpcd_caps.lttpr_caps.phy_repeater_cnt = | |
3288 | lttpr_dpcd_data[DP_PHY_REPEATER_CNT - | |
3289 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3290 | ||
3291 | link->dpcd_caps.lttpr_caps.max_lane_count = | |
3292 | lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER - | |
3293 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3294 | ||
3295 | link->dpcd_caps.lttpr_caps.mode = | |
3296 | lttpr_dpcd_data[DP_PHY_REPEATER_MODE - | |
3297 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3298 | ||
3299 | link->dpcd_caps.lttpr_caps.max_ext_timeout = | |
3300 | lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT - | |
3301 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3302 | ||
3303 | if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 && | |
3304 | link->dpcd_caps.lttpr_caps.max_lane_count > 0 && | |
3305 | link->dpcd_caps.lttpr_caps.max_lane_count <= 4 && | |
3306 | link->dpcd_caps.lttpr_caps.revision.raw >= 0x14) { | |
8e5100a5 | 3307 | link->is_lttpr_mode_transparent = false; |
8e5100a5 | 3308 | } else { |
61aa7a6f | 3309 | /*No lttpr reset timeout to its default value*/ |
3310 | link->is_lttpr_mode_transparent = true; | |
3311 | dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); | |
8e5100a5 | 3312 | } |
460adc6b | 3313 | |
3314 | CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); | |
8e5100a5 | 3315 | } |
3316 | ||
4562236b HW |
3317 | { |
3318 | union training_aux_rd_interval aux_rd_interval; | |
3319 | ||
3320 | aux_rd_interval.raw = | |
3a340294 | 3321 | dpcd_data[DP_TRAINING_AUX_RD_INTERVAL]; |
4562236b | 3322 | |
3c7dd2cb | 3323 | link->dpcd_caps.ext_receiver_cap_field_present = |
b239b59b | 3324 | aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1; |
3c7dd2cb HT |
3325 | |
3326 | if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) { | |
818832bf XY |
3327 | uint8_t ext_cap_data[16]; |
3328 | ||
3329 | memset(ext_cap_data, '\0', sizeof(ext_cap_data)); | |
3330 | for (i = 0; i < read_dpcd_retry_cnt; i++) { | |
3331 | status = core_link_read_dpcd( | |
4562236b | 3332 | link, |
3a340294 | 3333 | DP_DP13_DPCD_REV, |
818832bf XY |
3334 | ext_cap_data, |
3335 | sizeof(ext_cap_data)); | |
3336 | if (status == DC_OK) { | |
3337 | memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data)); | |
3338 | break; | |
3339 | } | |
3340 | } | |
3341 | if (status != DC_OK) | |
3342 | dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__); | |
4562236b HW |
3343 | } |
3344 | } | |
3345 | ||
3c7dd2cb HT |
3346 | link->dpcd_caps.dpcd_rev.raw = |
3347 | dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; | |
3348 | ||
3349 | if (link->dpcd_caps.dpcd_rev.raw >= 0x14) { | |
3350 | for (i = 0; i < read_dpcd_retry_cnt; i++) { | |
3351 | status = core_link_read_dpcd( | |
3352 | link, | |
3353 | DP_DPRX_FEATURE_ENUMERATION_LIST, | |
3354 | &dpcd_dprx_data, | |
3355 | sizeof(dpcd_dprx_data)); | |
3356 | if (status == DC_OK) | |
3357 | break; | |
3358 | } | |
3359 | ||
3360 | link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data; | |
3361 | ||
3362 | if (status != DC_OK) | |
3363 | dm_error("%s: Read DPRX caps data failed.\n", __func__); | |
3364 | } | |
3365 | ||
3366 | else { | |
3367 | link->dpcd_caps.dprx_feature.raw = 0; | |
3368 | } | |
3369 | ||
3370 | ||
07d6a199 AK |
3371 | /* Error condition checking... |
3372 | * It is impossible for Sink to report Max Lane Count = 0. | |
3373 | * It is possible for Sink to report Max Link Rate = 0, if it is | |
3374 | * an eDP device that is reporting specialized link rates in the | |
3375 | * SUPPORTED_LINK_RATE table. | |
3376 | */ | |
3377 | if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) | |
3378 | return false; | |
3379 | ||
3a340294 DA |
3380 | ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT - |
3381 | DP_DPCD_REV]; | |
4562236b | 3382 | |
ee13cea9 JB |
3383 | read_dp_device_vendor_id(link); |
3384 | ||
4562236b HW |
3385 | get_active_converter_info(ds_port.byte, link); |
3386 | ||
3387 | dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data)); | |
3388 | ||
98e6436d AK |
3389 | down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT - |
3390 | DP_DPCD_REV]; | |
3391 | ||
4562236b HW |
3392 | link->dpcd_caps.allow_invalid_MSA_timing_param = |
3393 | down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; | |
3394 | ||
3395 | link->dpcd_caps.max_ln_count.raw = dpcd_data[ | |
3a340294 | 3396 | DP_MAX_LANE_COUNT - DP_DPCD_REV]; |
4562236b HW |
3397 | |
3398 | link->dpcd_caps.max_down_spread.raw = dpcd_data[ | |
3a340294 | 3399 | DP_MAX_DOWNSPREAD - DP_DPCD_REV]; |
4562236b | 3400 | |
d0778ebf | 3401 | link->reported_link_cap.lane_count = |
4562236b | 3402 | link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; |
d0778ebf | 3403 | link->reported_link_cap.link_rate = dpcd_data[ |
3a340294 | 3404 | DP_MAX_LINK_RATE - DP_DPCD_REV]; |
d0778ebf | 3405 | link->reported_link_cap.link_spread = |
4562236b HW |
3406 | link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? |
3407 | LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; | |
3408 | ||
3409 | edp_config_cap.raw = dpcd_data[ | |
3a340294 | 3410 | DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV]; |
4562236b HW |
3411 | link->dpcd_caps.panel_mode_edp = |
3412 | edp_config_cap.bits.ALT_SCRAMBLER_RESET; | |
9799624a WL |
3413 | link->dpcd_caps.dpcd_display_control_capable = |
3414 | edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE; | |
4562236b | 3415 | |
d0778ebf HW |
3416 | link->test_pattern_enabled = false; |
3417 | link->compliance_test_state.raw = 0; | |
4562236b | 3418 | |
4562236b HW |
3419 | /* read sink count */ |
3420 | core_link_read_dpcd(link, | |
3a340294 | 3421 | DP_SINK_COUNT, |
4562236b HW |
3422 | &link->dpcd_caps.sink_count.raw, |
3423 | sizeof(link->dpcd_caps.sink_count.raw)); | |
3424 | ||
8ca80900 AK |
3425 | /* read sink ieee oui */ |
3426 | core_link_read_dpcd(link, | |
3427 | DP_SINK_OUI, | |
3428 | (uint8_t *)(&sink_id), | |
3429 | sizeof(sink_id)); | |
3430 | ||
3431 | link->dpcd_caps.sink_dev_id = | |
3432 | (sink_id.ieee_oui[0] << 16) + | |
3433 | (sink_id.ieee_oui[1] << 8) + | |
3434 | (sink_id.ieee_oui[2]); | |
3435 | ||
4b99affb A |
3436 | memmove( |
3437 | link->dpcd_caps.sink_dev_id_str, | |
3438 | sink_id.ieee_device_id, | |
3439 | sizeof(sink_id.ieee_device_id)); | |
3440 | ||
3441 | core_link_read_dpcd( | |
3442 | link, | |
3443 | DP_SINK_HW_REVISION_START, | |
3444 | (uint8_t *)&dp_hw_fw_revision, | |
3445 | sizeof(dp_hw_fw_revision)); | |
3446 | ||
3447 | link->dpcd_caps.sink_hw_revision = | |
3448 | dp_hw_fw_revision.ieee_hw_rev; | |
3449 | ||
3450 | memmove( | |
3451 | link->dpcd_caps.sink_fw_revision, | |
3452 | dp_hw_fw_revision.ieee_fw_rev, | |
3453 | sizeof(dp_hw_fw_revision.ieee_fw_rev)); | |
3454 | ||
39a4eb85 WL |
3455 | memset(&link->dpcd_caps.dsc_caps, '\0', |
3456 | sizeof(link->dpcd_caps.dsc_caps)); | |
97bda032 HW |
3457 | memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); |
3458 | /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */ | |
3459 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) { | |
97bda032 HW |
3460 | status = core_link_read_dpcd( |
3461 | link, | |
3462 | DP_FEC_CAPABILITY, | |
3463 | &link->dpcd_caps.fec_cap.raw, | |
3464 | sizeof(link->dpcd_caps.fec_cap.raw)); | |
39a4eb85 WL |
3465 | status = core_link_read_dpcd( |
3466 | link, | |
3467 | DP_DSC_SUPPORT, | |
3468 | link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, | |
3469 | sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw)); | |
3470 | status = core_link_read_dpcd( | |
3471 | link, | |
3472 | DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, | |
3473 | link->dpcd_caps.dsc_caps.dsc_ext_caps.raw, | |
3474 | sizeof(link->dpcd_caps.dsc_caps.dsc_ext_caps.raw)); | |
97bda032 | 3475 | } |
6fbefb84 | 3476 | |
96577cf8 HW |
3477 | if (!dpcd_read_sink_ext_caps(link)) |
3478 | link->dpcd_sink_ext_caps.raw = 0; | |
3479 | ||
4562236b HW |
3480 | /* Connectivity log: detection */ |
3481 | CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: "); | |
cdb39798 YS |
3482 | |
3483 | return true; | |
4562236b HW |
3484 | } |
3485 | ||
8547058b LH |
3486 | bool dp_overwrite_extended_receiver_cap(struct dc_link *link) |
3487 | { | |
3488 | uint8_t dpcd_data[16]; | |
3489 | uint32_t read_dpcd_retry_cnt = 3; | |
3490 | enum dc_status status = DC_ERROR_UNEXPECTED; | |
3491 | union dp_downstream_port_present ds_port = { 0 }; | |
3492 | union down_stream_port_count down_strm_port_count; | |
3493 | union edp_configuration_cap edp_config_cap; | |
3494 | ||
3495 | int i; | |
3496 | ||
3497 | for (i = 0; i < read_dpcd_retry_cnt; i++) { | |
3498 | status = core_link_read_dpcd( | |
3499 | link, | |
3500 | DP_DPCD_REV, | |
3501 | dpcd_data, | |
3502 | sizeof(dpcd_data)); | |
3503 | if (status == DC_OK) | |
3504 | break; | |
3505 | } | |
3506 | ||
3507 | link->dpcd_caps.dpcd_rev.raw = | |
3508 | dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; | |
3509 | ||
3510 | if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) | |
3511 | return false; | |
3512 | ||
3513 | ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT - | |
3514 | DP_DPCD_REV]; | |
3515 | ||
3516 | get_active_converter_info(ds_port.byte, link); | |
3517 | ||
3518 | down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT - | |
3519 | DP_DPCD_REV]; | |
3520 | ||
3521 | link->dpcd_caps.allow_invalid_MSA_timing_param = | |
3522 | down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; | |
3523 | ||
3524 | link->dpcd_caps.max_ln_count.raw = dpcd_data[ | |
3525 | DP_MAX_LANE_COUNT - DP_DPCD_REV]; | |
3526 | ||
3527 | link->dpcd_caps.max_down_spread.raw = dpcd_data[ | |
3528 | DP_MAX_DOWNSPREAD - DP_DPCD_REV]; | |
3529 | ||
3530 | link->reported_link_cap.lane_count = | |
3531 | link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; | |
3532 | link->reported_link_cap.link_rate = dpcd_data[ | |
3533 | DP_MAX_LINK_RATE - DP_DPCD_REV]; | |
3534 | link->reported_link_cap.link_spread = | |
3535 | link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? | |
3536 | LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; | |
3537 | ||
3538 | edp_config_cap.raw = dpcd_data[ | |
3539 | DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV]; | |
3540 | link->dpcd_caps.panel_mode_edp = | |
3541 | edp_config_cap.bits.ALT_SCRAMBLER_RESET; | |
3542 | link->dpcd_caps.dpcd_display_control_capable = | |
3543 | edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE; | |
3544 | ||
3545 | return true; | |
3546 | } | |
3547 | ||
cdb39798 | 3548 | bool detect_dp_sink_caps(struct dc_link *link) |
4562236b | 3549 | { |
cdb39798 | 3550 | return retrieve_link_cap(link); |
4562236b HW |
3551 | |
3552 | /* dc init_hw has power encoder using default | |
3553 | * signal for connector. For native DP, no | |
3554 | * need to power up encoder again. If not native | |
3555 | * DP, hw_init may need check signal or power up | |
3556 | * encoder here. | |
3557 | */ | |
4562236b HW |
3558 | /* TODO save sink caps in link->sink */ |
3559 | } | |
3560 | ||
b03a599b DL |
3561 | enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) |
3562 | { | |
3563 | enum dc_link_rate link_rate; | |
3564 | // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation. | |
3565 | switch (link_rate_in_khz) { | |
3566 | case 1620000: | |
3567 | link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane | |
3568 | break; | |
3569 | case 2160000: | |
3570 | link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane | |
3571 | break; | |
3572 | case 2430000: | |
3573 | link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane | |
3574 | break; | |
3575 | case 2700000: | |
3576 | link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane | |
3577 | break; | |
3578 | case 3240000: | |
3579 | link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane | |
3580 | break; | |
3581 | case 4320000: | |
3582 | link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane | |
3583 | break; | |
3584 | case 5400000: | |
3585 | link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane | |
3586 | break; | |
3587 | case 8100000: | |
3588 | link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane | |
3589 | break; | |
3590 | default: | |
3591 | link_rate = LINK_RATE_UNKNOWN; | |
3592 | break; | |
3593 | } | |
3594 | return link_rate; | |
3595 | } | |
3596 | ||
4654a2f7 RL |
3597 | void detect_edp_sink_caps(struct dc_link *link) |
3598 | { | |
8628d02f | 3599 | uint8_t supported_link_rates[16]; |
b03a599b DL |
3600 | uint32_t entry; |
3601 | uint32_t link_rate_in_khz; | |
3602 | enum dc_link_rate link_rate = LINK_RATE_UNKNOWN; | |
48231fd5 | 3603 | |
b03a599b | 3604 | retrieve_link_cap(link); |
8628d02f JP |
3605 | link->dpcd_caps.edp_supported_link_rates_count = 0; |
3606 | memset(supported_link_rates, 0, sizeof(supported_link_rates)); | |
48231fd5 | 3607 | |
8628d02f | 3608 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 && |
53c81fc7 WC |
3609 | (link->dc->config.optimize_edp_link_rate || |
3610 | link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) { | |
b03a599b DL |
3611 | // Read DPCD 00010h - 0001Fh 16 bytes at one shot |
3612 | core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES, | |
3613 | supported_link_rates, sizeof(supported_link_rates)); | |
3614 | ||
b03a599b DL |
3615 | for (entry = 0; entry < 16; entry += 2) { |
3616 | // DPCD register reports per-lane link rate = 16-bit link rate capability | |
8628d02f | 3617 | // value X 200 kHz. Need multiplier to find link rate in kHz. |
b03a599b DL |
3618 | link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + |
3619 | supported_link_rates[entry]) * 200; | |
3620 | ||
3621 | if (link_rate_in_khz != 0) { | |
3622 | link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz); | |
8628d02f JP |
3623 | link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate; |
3624 | link->dpcd_caps.edp_supported_link_rates_count++; | |
53c81fc7 WC |
3625 | |
3626 | if (link->reported_link_cap.link_rate < link_rate) | |
3627 | link->reported_link_cap.link_rate = link_rate; | |
b03a599b DL |
3628 | } |
3629 | } | |
3630 | } | |
4654a2f7 | 3631 | link->verified_link_cap = link->reported_link_cap; |
96577cf8 HW |
3632 | |
3633 | dc_link_set_default_brightness_aux(link); | |
4654a2f7 RL |
3634 | } |
3635 | ||
4562236b HW |
3636 | void dc_link_dp_enable_hpd(const struct dc_link *link) |
3637 | { | |
d0778ebf | 3638 | struct link_encoder *encoder = link->link_enc; |
4562236b HW |
3639 | |
3640 | if (encoder != NULL && encoder->funcs->enable_hpd != NULL) | |
3641 | encoder->funcs->enable_hpd(encoder); | |
3642 | } | |
3643 | ||
3644 | void dc_link_dp_disable_hpd(const struct dc_link *link) | |
3645 | { | |
d0778ebf | 3646 | struct link_encoder *encoder = link->link_enc; |
4562236b HW |
3647 | |
3648 | if (encoder != NULL && encoder->funcs->enable_hpd != NULL) | |
3649 | encoder->funcs->disable_hpd(encoder); | |
3650 | } | |
3651 | ||
3652 | static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern) | |
3653 | { | |
0e19401f TC |
3654 | if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern && |
3655 | test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) || | |
3656 | test_pattern == DP_TEST_PATTERN_VIDEO_MODE) | |
4562236b HW |
3657 | return true; |
3658 | else | |
3659 | return false; | |
3660 | } | |
3661 | ||
d0778ebf | 3662 | static void set_crtc_test_pattern(struct dc_link *link, |
4562236b | 3663 | struct pipe_ctx *pipe_ctx, |
2057b7e1 WL |
3664 | enum dp_test_pattern test_pattern, |
3665 | enum dp_test_pattern_color_space test_pattern_color_space) | |
4562236b HW |
3666 | { |
3667 | enum controller_dp_test_pattern controller_test_pattern; | |
3668 | enum dc_color_depth color_depth = pipe_ctx-> | |
4fa086b9 | 3669 | stream->timing.display_color_depth; |
4562236b | 3670 | struct bit_depth_reduction_params params; |
661a8cd9 | 3671 | struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; |
6fbefb84 HW |
3672 | int width = pipe_ctx->stream->timing.h_addressable + |
3673 | pipe_ctx->stream->timing.h_border_left + | |
3674 | pipe_ctx->stream->timing.h_border_right; | |
3675 | int height = pipe_ctx->stream->timing.v_addressable + | |
3676 | pipe_ctx->stream->timing.v_border_bottom + | |
3677 | pipe_ctx->stream->timing.v_border_top; | |
4562236b HW |
3678 | |
3679 | memset(¶ms, 0, sizeof(params)); | |
3680 | ||
3681 | switch (test_pattern) { | |
3682 | case DP_TEST_PATTERN_COLOR_SQUARES: | |
3683 | controller_test_pattern = | |
3684 | CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; | |
3685 | break; | |
3686 | case DP_TEST_PATTERN_COLOR_SQUARES_CEA: | |
3687 | controller_test_pattern = | |
3688 | CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA; | |
3689 | break; | |
3690 | case DP_TEST_PATTERN_VERTICAL_BARS: | |
3691 | controller_test_pattern = | |
3692 | CONTROLLER_DP_TEST_PATTERN_VERTICALBARS; | |
3693 | break; | |
3694 | case DP_TEST_PATTERN_HORIZONTAL_BARS: | |
3695 | controller_test_pattern = | |
3696 | CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS; | |
3697 | break; | |
3698 | case DP_TEST_PATTERN_COLOR_RAMP: | |
3699 | controller_test_pattern = | |
3700 | CONTROLLER_DP_TEST_PATTERN_COLORRAMP; | |
3701 | break; | |
3702 | default: | |
3703 | controller_test_pattern = | |
3704 | CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; | |
3705 | break; | |
3706 | } | |
3707 | ||
3708 | switch (test_pattern) { | |
3709 | case DP_TEST_PATTERN_COLOR_SQUARES: | |
3710 | case DP_TEST_PATTERN_COLOR_SQUARES_CEA: | |
3711 | case DP_TEST_PATTERN_VERTICAL_BARS: | |
3712 | case DP_TEST_PATTERN_HORIZONTAL_BARS: | |
3713 | case DP_TEST_PATTERN_COLOR_RAMP: | |
3714 | { | |
3715 | /* disable bit depth reduction */ | |
3716 | pipe_ctx->stream->bit_depth_params = params; | |
661a8cd9 | 3717 | opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms); |
7f93c1de CL |
3718 | if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) |
3719 | pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, | |
4562236b | 3720 | controller_test_pattern, color_depth); |
6fbefb84 | 3721 | else if (opp->funcs->opp_set_disp_pattern_generator) { |
b1f6d01c | 3722 | struct pipe_ctx *odm_pipe; |
2057b7e1 | 3723 | enum controller_dp_color_space controller_color_space; |
b1f6d01c | 3724 | int opp_cnt = 1; |
10b4e64e WL |
3725 | int offset = 0; |
3726 | int dpg_width = width; | |
6fbefb84 | 3727 | |
2057b7e1 WL |
3728 | switch (test_pattern_color_space) { |
3729 | case DP_TEST_PATTERN_COLOR_SPACE_RGB: | |
3730 | controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; | |
3731 | break; | |
3732 | case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601: | |
3733 | controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601; | |
3734 | break; | |
3735 | case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709: | |
3736 | controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709; | |
3737 | break; | |
3738 | case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED: | |
3739 | default: | |
3740 | controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; | |
3741 | DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__); | |
3742 | ASSERT(0); | |
3743 | break; | |
3744 | } | |
3745 | ||
b1f6d01c DL |
3746 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) |
3747 | opp_cnt++; | |
10b4e64e WL |
3748 | dpg_width = width / opp_cnt; |
3749 | offset = dpg_width; | |
6fbefb84 | 3750 | |
10b4e64e WL |
3751 | opp->funcs->opp_set_disp_pattern_generator(opp, |
3752 | controller_test_pattern, | |
3753 | controller_color_space, | |
3754 | color_depth, | |
3755 | NULL, | |
3756 | dpg_width, | |
3757 | height, | |
3758 | 0); | |
b1f6d01c DL |
3759 | |
3760 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { | |
3761 | struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; | |
b1f6d01c DL |
3762 | odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms); |
3763 | odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp, | |
6fbefb84 | 3764 | controller_test_pattern, |
2057b7e1 | 3765 | controller_color_space, |
6fbefb84 HW |
3766 | color_depth, |
3767 | NULL, | |
10b4e64e WL |
3768 | dpg_width, |
3769 | height, | |
3770 | offset); | |
3771 | offset += offset; | |
6fbefb84 | 3772 | } |
6fbefb84 | 3773 | } |
4562236b HW |
3774 | } |
3775 | break; | |
3776 | case DP_TEST_PATTERN_VIDEO_MODE: | |
3777 | { | |
3778 | /* restore bitdepth reduction */ | |
661a8cd9 | 3779 | resource_build_bit_depth_reduction_params(pipe_ctx->stream, ¶ms); |
4562236b | 3780 | pipe_ctx->stream->bit_depth_params = params; |
661a8cd9 | 3781 | opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms); |
7f93c1de CL |
3782 | if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) |
3783 | pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, | |
4562236b HW |
3784 | CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, |
3785 | color_depth); | |
6fbefb84 | 3786 | else if (opp->funcs->opp_set_disp_pattern_generator) { |
b1f6d01c DL |
3787 | struct pipe_ctx *odm_pipe; |
3788 | int opp_cnt = 1; | |
10b4e64e | 3789 | int dpg_width = width; |
b1f6d01c DL |
3790 | |
3791 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) | |
3792 | opp_cnt++; | |
6fbefb84 | 3793 | |
10b4e64e | 3794 | dpg_width = width / opp_cnt; |
b1f6d01c DL |
3795 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { |
3796 | struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; | |
6fbefb84 | 3797 | |
b1f6d01c DL |
3798 | odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms); |
3799 | odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp, | |
6fbefb84 | 3800 | CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, |
2057b7e1 | 3801 | CONTROLLER_DP_COLOR_SPACE_UDEFINED, |
6fbefb84 HW |
3802 | color_depth, |
3803 | NULL, | |
10b4e64e WL |
3804 | dpg_width, |
3805 | height, | |
3806 | 0); | |
6fbefb84 HW |
3807 | } |
3808 | opp->funcs->opp_set_disp_pattern_generator(opp, | |
3809 | CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, | |
2057b7e1 | 3810 | CONTROLLER_DP_COLOR_SPACE_UDEFINED, |
6fbefb84 HW |
3811 | color_depth, |
3812 | NULL, | |
10b4e64e WL |
3813 | dpg_width, |
3814 | height, | |
3815 | 0); | |
6fbefb84 | 3816 | } |
4562236b HW |
3817 | } |
3818 | break; | |
3819 | ||
3820 | default: | |
3821 | break; | |
3822 | } | |
3823 | } | |
3824 | ||
3825 | bool dc_link_dp_set_test_pattern( | |
d0778ebf | 3826 | struct dc_link *link, |
4562236b | 3827 | enum dp_test_pattern test_pattern, |
2057b7e1 | 3828 | enum dp_test_pattern_color_space test_pattern_color_space, |
4562236b HW |
3829 | const struct link_training_settings *p_link_settings, |
3830 | const unsigned char *p_custom_pattern, | |
3831 | unsigned int cust_pattern_size) | |
3832 | { | |
608ac7bb | 3833 | struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; |
0a8f43ff | 3834 | struct pipe_ctx *pipe_ctx = &pipes[0]; |
4562236b HW |
3835 | unsigned int lane; |
3836 | unsigned int i; | |
3837 | unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0}; | |
3838 | union dpcd_training_pattern training_pattern; | |
4562236b HW |
3839 | enum dpcd_phy_test_patterns pattern; |
3840 | ||
3841 | memset(&training_pattern, 0, sizeof(training_pattern)); | |
4562236b HW |
3842 | |
3843 | for (i = 0; i < MAX_PIPES; i++) { | |
24d01c9b | 3844 | if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) { |
0a8f43ff | 3845 | pipe_ctx = &pipes[i]; |
4562236b HW |
3846 | break; |
3847 | } | |
3848 | } | |
3849 | ||
3850 | /* Reset CRTC Test Pattern if it is currently running and request | |
3851 | * is VideoMode Reset DP Phy Test Pattern if it is currently running | |
3852 | * and request is VideoMode | |
3853 | */ | |
d0778ebf | 3854 | if (link->test_pattern_enabled && test_pattern == |
4562236b HW |
3855 | DP_TEST_PATTERN_VIDEO_MODE) { |
3856 | /* Set CRTC Test Pattern */ | |
2057b7e1 | 3857 | set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space); |
d0778ebf | 3858 | dp_set_hw_test_pattern(link, test_pattern, |
4562236b HW |
3859 | (uint8_t *)p_custom_pattern, |
3860 | (uint32_t)cust_pattern_size); | |
3861 | ||
3862 | /* Unblank Stream */ | |
d0778ebf | 3863 | link->dc->hwss.unblank_stream( |
0a8f43ff | 3864 | pipe_ctx, |
d0778ebf | 3865 | &link->verified_link_cap); |
4562236b HW |
3866 | /* TODO:m_pHwss->MuteAudioEndpoint |
3867 | * (pPathMode->pDisplayPath, false); | |
3868 | */ | |
3869 | ||
3870 | /* Reset Test Pattern state */ | |
d0778ebf | 3871 | link->test_pattern_enabled = false; |
4562236b HW |
3872 | |
3873 | return true; | |
3874 | } | |
3875 | ||
3876 | /* Check for PHY Test Patterns */ | |
3877 | if (is_dp_phy_pattern(test_pattern)) { | |
3878 | /* Set DPCD Lane Settings before running test pattern */ | |
3879 | if (p_link_settings != NULL) { | |
64c12b73 | 3880 | dp_set_hw_lane_settings(link, p_link_settings, DPRX); |
3881 | dpcd_set_lane_settings(link, p_link_settings, DPRX); | |
4562236b HW |
3882 | } |
3883 | ||
3884 | /* Blank stream if running test pattern */ | |
3885 | if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { | |
3886 | /*TODO: | |
3887 | * m_pHwss-> | |
3888 | * MuteAudioEndpoint(pPathMode->pDisplayPath, true); | |
3889 | */ | |
3890 | /* Blank stream */ | |
8e9c4c8c | 3891 | pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); |
4562236b HW |
3892 | } |
3893 | ||
d0778ebf | 3894 | dp_set_hw_test_pattern(link, test_pattern, |
4562236b HW |
3895 | (uint8_t *)p_custom_pattern, |
3896 | (uint32_t)cust_pattern_size); | |
3897 | ||
3898 | if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { | |
3899 | /* Set Test Pattern state */ | |
d0778ebf | 3900 | link->test_pattern_enabled = true; |
4562236b | 3901 | if (p_link_settings != NULL) |
d0778ebf | 3902 | dpcd_set_link_settings(link, |
4562236b HW |
3903 | p_link_settings); |
3904 | } | |
3905 | ||
3906 | switch (test_pattern) { | |
3907 | case DP_TEST_PATTERN_VIDEO_MODE: | |
3908 | pattern = PHY_TEST_PATTERN_NONE; | |
0e19401f | 3909 | break; |
4562236b HW |
3910 | case DP_TEST_PATTERN_D102: |
3911 | pattern = PHY_TEST_PATTERN_D10_2; | |
0e19401f | 3912 | break; |
4562236b HW |
3913 | case DP_TEST_PATTERN_SYMBOL_ERROR: |
3914 | pattern = PHY_TEST_PATTERN_SYMBOL_ERROR; | |
0e19401f | 3915 | break; |
4562236b HW |
3916 | case DP_TEST_PATTERN_PRBS7: |
3917 | pattern = PHY_TEST_PATTERN_PRBS7; | |
0e19401f | 3918 | break; |
4562236b HW |
3919 | case DP_TEST_PATTERN_80BIT_CUSTOM: |
3920 | pattern = PHY_TEST_PATTERN_80BIT_CUSTOM; | |
0e19401f TC |
3921 | break; |
3922 | case DP_TEST_PATTERN_CP2520_1: | |
3923 | pattern = PHY_TEST_PATTERN_CP2520_1; | |
3924 | break; | |
3925 | case DP_TEST_PATTERN_CP2520_2: | |
3926 | pattern = PHY_TEST_PATTERN_CP2520_2; | |
3927 | break; | |
3928 | case DP_TEST_PATTERN_CP2520_3: | |
3929 | pattern = PHY_TEST_PATTERN_CP2520_3; | |
3930 | break; | |
4562236b HW |
3931 | default: |
3932 | return false; | |
3933 | } | |
3934 | ||
3935 | if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE | |
3936 | /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/) | |
3937 | return false; | |
3938 | ||
d0778ebf | 3939 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { |
4562236b HW |
3940 | /* tell receiver that we are sending qualification |
3941 | * pattern DP 1.2 or later - DP receiver's link quality | |
3942 | * pattern is set using DPCD LINK_QUAL_LANEx_SET | |
3943 | * register (0x10B~0x10E)\ | |
3944 | */ | |
3945 | for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) | |
3946 | link_qual_pattern[lane] = | |
3947 | (unsigned char)(pattern); | |
3948 | ||
d0778ebf | 3949 | core_link_write_dpcd(link, |
3a340294 | 3950 | DP_LINK_QUAL_LANE0_SET, |
4562236b HW |
3951 | link_qual_pattern, |
3952 | sizeof(link_qual_pattern)); | |
d0778ebf HW |
3953 | } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 || |
3954 | link->dpcd_caps.dpcd_rev.raw == 0) { | |
4562236b HW |
3955 | /* tell receiver that we are sending qualification |
3956 | * pattern DP 1.1a or earlier - DP receiver's link | |
3957 | * quality pattern is set using | |
3958 | * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET | |
3959 | * register (0x102). We will use v_1.3 when we are | |
3960 | * setting test pattern for DP 1.1. | |
3961 | */ | |
d0778ebf HW |
3962 | core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET, |
3963 | &training_pattern.raw, | |
3964 | sizeof(training_pattern)); | |
4562236b | 3965 | training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern; |
d0778ebf HW |
3966 | core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET, |
3967 | &training_pattern.raw, | |
3968 | sizeof(training_pattern)); | |
4562236b HW |
3969 | } |
3970 | } else { | |
43563bc2 | 3971 | enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; |
43563bc2 WL |
3972 | |
3973 | switch (test_pattern_color_space) { | |
3974 | case DP_TEST_PATTERN_COLOR_SPACE_RGB: | |
3975 | color_space = COLOR_SPACE_SRGB; | |
3976 | if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA) | |
3977 | color_space = COLOR_SPACE_SRGB_LIMITED; | |
3978 | break; | |
3979 | ||
3980 | case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601: | |
3981 | color_space = COLOR_SPACE_YCBCR601; | |
3982 | if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA) | |
3983 | color_space = COLOR_SPACE_YCBCR601_LIMITED; | |
3984 | break; | |
3985 | case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709: | |
3986 | color_space = COLOR_SPACE_YCBCR709; | |
3987 | if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA) | |
3988 | color_space = COLOR_SPACE_YCBCR709_LIMITED; | |
3989 | break; | |
3990 | default: | |
3991 | break; | |
3992 | } | |
e8f9ecf2 WL |
3993 | |
3994 | if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) | |
3995 | pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable( | |
3996 | pipe_ctx->stream_res.tg); | |
3997 | pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); | |
43563bc2 WL |
3998 | /* update MSA to requested color space */ |
3999 | pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc, | |
4000 | &pipe_ctx->stream->timing, | |
23bc5f34 WL |
4001 | color_space, |
4002 | pipe_ctx->stream->use_vsc_sdp_for_colorimetry, | |
4003 | link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP); | |
43563bc2 | 4004 | |
e8f9ecf2 WL |
4005 | if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) { |
4006 | if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA) | |
4007 | pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range | |
4008 | else | |
4009 | pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7); | |
4010 | resource_build_info_frame(pipe_ctx); | |
4011 | link->dc->hwss.update_info_frame(pipe_ctx); | |
4012 | } | |
4013 | ||
43563bc2 | 4014 | /* CRTC Patterns */ |
2057b7e1 | 4015 | set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space); |
e8f9ecf2 WL |
4016 | pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); |
4017 | pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, | |
4018 | CRTC_STATE_VACTIVE); | |
4019 | pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, | |
4020 | CRTC_STATE_VBLANK); | |
4021 | pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, | |
4022 | CRTC_STATE_VACTIVE); | |
4023 | if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) | |
4024 | pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable( | |
4025 | pipe_ctx->stream_res.tg); | |
4562236b | 4026 | /* Set Test Pattern state */ |
d0778ebf | 4027 | link->test_pattern_enabled = true; |
4562236b HW |
4028 | } |
4029 | ||
4030 | return true; | |
4031 | } | |
07c84c7a | 4032 | |
d0778ebf | 4033 | void dp_enable_mst_on_sink(struct dc_link *link, bool enable) |
07c84c7a DW |
4034 | { |
4035 | unsigned char mstmCntl; | |
4036 | ||
4037 | core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); | |
4038 | if (enable) | |
4039 | mstmCntl |= DP_MST_EN; | |
4040 | else | |
4041 | mstmCntl &= (~DP_MST_EN); | |
4042 | ||
4043 | core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); | |
4044 | } | |
6fbefb84 | 4045 | |
0b226322 DG |
4046 | void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode) |
4047 | { | |
4048 | union dpcd_edp_config edp_config_set; | |
4049 | bool panel_mode_edp = false; | |
4050 | ||
4051 | memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config)); | |
4052 | ||
4053 | if (panel_mode != DP_PANEL_MODE_DEFAULT) { | |
4054 | ||
4055 | switch (panel_mode) { | |
4056 | case DP_PANEL_MODE_EDP: | |
4057 | case DP_PANEL_MODE_SPECIAL: | |
4058 | panel_mode_edp = true; | |
4059 | break; | |
4060 | ||
4061 | default: | |
4062 | break; | |
4063 | } | |
4064 | ||
4065 | /*set edp panel mode in receiver*/ | |
4066 | core_link_read_dpcd( | |
4067 | link, | |
4068 | DP_EDP_CONFIGURATION_SET, | |
4069 | &edp_config_set.raw, | |
4070 | sizeof(edp_config_set.raw)); | |
4071 | ||
4072 | if (edp_config_set.bits.PANEL_MODE_EDP | |
4073 | != panel_mode_edp) { | |
4074 | enum ddc_result result = DDC_RESULT_UNKNOWN; | |
4075 | ||
4076 | edp_config_set.bits.PANEL_MODE_EDP = | |
4077 | panel_mode_edp; | |
4078 | result = core_link_write_dpcd( | |
4079 | link, | |
4080 | DP_EDP_CONFIGURATION_SET, | |
4081 | &edp_config_set.raw, | |
4082 | sizeof(edp_config_set.raw)); | |
4083 | ||
4084 | ASSERT(result == DDC_RESULT_SUCESSFULL); | |
4085 | } | |
4086 | } | |
4087 | DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d " | |
4088 | "eDP panel mode enabled: %d \n", | |
4089 | link->link_index, | |
4090 | link->dpcd_caps.panel_mode_edp, | |
4091 | panel_mode_edp); | |
4092 | } | |
4093 | ||
4094 | enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) | |
4095 | { | |
4096 | /* We need to explicitly check that connector | |
4097 | * is not DP. Some Travis_VGA get reported | |
4098 | * by video bios as DP. | |
4099 | */ | |
4100 | if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { | |
4101 | ||
4102 | switch (link->dpcd_caps.branch_dev_id) { | |
df3b7e32 QZ |
4103 | case DP_BRANCH_DEVICE_ID_0022B9: |
4104 | /* alternate scrambler reset is required for Travis | |
4105 | * for the case when external chip does not | |
4106 | * provide sink device id, alternate scrambler | |
4107 | * scheme will be overriden later by querying | |
4108 | * Encoder features | |
4109 | */ | |
0b226322 DG |
4110 | if (strncmp( |
4111 | link->dpcd_caps.branch_dev_name, | |
4112 | DP_VGA_LVDS_CONVERTER_ID_2, | |
4113 | sizeof( | |
4114 | link->dpcd_caps. | |
4115 | branch_dev_name)) == 0) { | |
4116 | return DP_PANEL_MODE_SPECIAL; | |
4117 | } | |
4118 | break; | |
df3b7e32 QZ |
4119 | case DP_BRANCH_DEVICE_ID_00001A: |
4120 | /* alternate scrambler reset is required for Travis | |
4121 | * for the case when external chip does not provide | |
4122 | * sink device id, alternate scrambler scheme will | |
4123 | * be overriden later by querying Encoder feature | |
4124 | */ | |
0b226322 DG |
4125 | if (strncmp(link->dpcd_caps.branch_dev_name, |
4126 | DP_VGA_LVDS_CONVERTER_ID_3, | |
4127 | sizeof( | |
4128 | link->dpcd_caps. | |
4129 | branch_dev_name)) == 0) { | |
4130 | return DP_PANEL_MODE_SPECIAL; | |
4131 | } | |
4132 | break; | |
4133 | default: | |
4134 | break; | |
4135 | } | |
4136 | } | |
4137 | ||
4138 | if (link->dpcd_caps.panel_mode_edp) { | |
4139 | return DP_PANEL_MODE_EDP; | |
4140 | } | |
4141 | ||
4142 | return DP_PANEL_MODE_DEFAULT; | |
4143 | } | |
4144 | ||
97bda032 HW |
4145 | void dp_set_fec_ready(struct dc_link *link, bool ready) |
4146 | { | |
4147 | /* FEC has to be "set ready" before the link training. | |
4148 | * The policy is to always train with FEC | |
4149 | * if the sink supports it and leave it enabled on link. | |
4150 | * If FEC is not supported, disable it. | |
4151 | */ | |
4152 | struct link_encoder *link_enc = link->link_enc; | |
4153 | uint8_t fec_config = 0; | |
4154 | ||
c14b726e | 4155 | if (!dc_link_is_fec_supported(link)) |
97bda032 HW |
4156 | return; |
4157 | ||
4158 | if (link_enc->funcs->fec_set_ready && | |
4159 | link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { | |
008a4016 | 4160 | if (ready) { |
97bda032 HW |
4161 | fec_config = 1; |
4162 | if (core_link_write_dpcd(link, | |
4163 | DP_FEC_CONFIGURATION, | |
4164 | &fec_config, | |
4165 | sizeof(fec_config)) == DC_OK) { | |
4166 | link_enc->funcs->fec_set_ready(link_enc, true); | |
4167 | link->fec_state = dc_link_fec_ready; | |
4168 | } else { | |
d68a7454 NC |
4169 | link->link_enc->funcs->fec_set_ready(link->link_enc, false); |
4170 | link->fec_state = dc_link_fec_not_ready; | |
97bda032 HW |
4171 | dm_error("dpcd write failed to set fec_ready"); |
4172 | } | |
008a4016 | 4173 | } else if (link->fec_state == dc_link_fec_ready) { |
97bda032 HW |
4174 | fec_config = 0; |
4175 | core_link_write_dpcd(link, | |
4176 | DP_FEC_CONFIGURATION, | |
4177 | &fec_config, | |
4178 | sizeof(fec_config)); | |
4179 | link->link_enc->funcs->fec_set_ready( | |
4180 | link->link_enc, false); | |
4181 | link->fec_state = dc_link_fec_not_ready; | |
4182 | } | |
4183 | } | |
4184 | } | |
4185 | ||
4186 | void dp_set_fec_enable(struct dc_link *link, bool enable) | |
4187 | { | |
4188 | struct link_encoder *link_enc = link->link_enc; | |
4189 | ||
c14b726e | 4190 | if (!dc_link_is_fec_supported(link)) |
97bda032 HW |
4191 | return; |
4192 | ||
4193 | if (link_enc->funcs->fec_set_enable && | |
4194 | link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { | |
4195 | if (link->fec_state == dc_link_fec_ready && enable) { | |
fa11d3c9 LHM |
4196 | /* Accord to DP spec, FEC enable sequence can first |
4197 | * be transmitted anytime after 1000 LL codes have | |
4198 | * been transmitted on the link after link training | |
4199 | * completion. Using 1 lane RBR should have the maximum | |
4200 | * time for transmitting 1000 LL codes which is 6.173 us. | |
4201 | * So use 7 microseconds delay instead. | |
4202 | */ | |
4203 | udelay(7); | |
97bda032 HW |
4204 | link_enc->funcs->fec_set_enable(link_enc, true); |
4205 | link->fec_state = dc_link_fec_enabled; | |
4206 | } else if (link->fec_state == dc_link_fec_enabled && !enable) { | |
4207 | link_enc->funcs->fec_set_enable(link_enc, false); | |
4208 | link->fec_state = dc_link_fec_ready; | |
4209 | } | |
4210 | } | |
4211 | } | |
6fbefb84 | 4212 | |
96577cf8 HW |
4213 | void dpcd_set_source_specific_data(struct dc_link *link) |
4214 | { | |
96577cf8 HW |
4215 | const uint32_t post_oui_delay = 30; // 30ms |
4216 | ||
0136684f CH |
4217 | if (!link->dc->vendor_signature.is_valid) { |
4218 | struct dpcd_amd_signature amd_signature; | |
4219 | amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0; | |
4220 | amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0; | |
4221 | amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A; | |
4222 | amd_signature.device_id_byte1 = | |
4223 | (uint8_t)(link->ctx->asic_id.chip_id); | |
4224 | amd_signature.device_id_byte2 = | |
4225 | (uint8_t)(link->ctx->asic_id.chip_id >> 8); | |
4226 | memset(&amd_signature.zero, 0, 4); | |
4227 | amd_signature.dce_version = | |
4228 | (uint8_t)(link->ctx->dce_version); | |
4229 | amd_signature.dal_version_byte1 = 0x0; // needed? where to get? | |
4230 | amd_signature.dal_version_byte2 = 0x0; // needed? where to get? | |
4231 | ||
4232 | core_link_write_dpcd(link, DP_SOURCE_OUI, | |
4233 | (uint8_t *)(&amd_signature), | |
4234 | sizeof(amd_signature)); | |
4235 | ||
4236 | } else { | |
4237 | core_link_write_dpcd(link, DP_SOURCE_OUI, | |
4238 | link->dc->vendor_signature.data.raw, | |
4239 | sizeof(link->dc->vendor_signature.data.raw)); | |
4240 | } | |
96577cf8 HW |
4241 | |
4242 | // Sink may need to configure internals based on vendor, so allow some | |
4243 | // time before proceeding with possibly vendor specific transactions | |
4244 | msleep(post_oui_delay); | |
4245 | } | |
4246 | ||
4247 | bool dc_link_set_backlight_level_nits(struct dc_link *link, | |
4248 | bool isHDR, | |
4249 | uint32_t backlight_millinits, | |
4250 | uint32_t transition_time_in_ms) | |
4251 | { | |
4252 | struct dpcd_source_backlight_set dpcd_backlight_set; | |
4253 | uint8_t backlight_control = isHDR ? 1 : 0; | |
4254 | ||
4255 | if (!link || (link->connector_signal != SIGNAL_TYPE_EDP && | |
4256 | link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)) | |
4257 | return false; | |
4258 | ||
4259 | // OLEDs have no PWM, they can only use AUX | |
4260 | if (link->dpcd_sink_ext_caps.bits.oled == 1) | |
4261 | backlight_control = 1; | |
4262 | ||
4263 | *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits; | |
4264 | *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms; | |
4265 | ||
4266 | ||
4267 | if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL, | |
4268 | (uint8_t *)(&dpcd_backlight_set), | |
4269 | sizeof(dpcd_backlight_set)) != DC_OK) | |
4270 | return false; | |
4271 | ||
4272 | if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL, | |
4273 | &backlight_control, 1) != DC_OK) | |
4274 | return false; | |
4275 | ||
4276 | return true; | |
4277 | } | |
4278 | ||
4279 | bool dc_link_get_backlight_level_nits(struct dc_link *link, | |
4280 | uint32_t *backlight_millinits_avg, | |
4281 | uint32_t *backlight_millinits_peak) | |
4282 | { | |
4283 | union dpcd_source_backlight_get dpcd_backlight_get; | |
4284 | ||
4285 | memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get)); | |
4286 | ||
4287 | if (!link || (link->connector_signal != SIGNAL_TYPE_EDP && | |
4288 | link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)) | |
4289 | return false; | |
4290 | ||
4291 | if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK, | |
4292 | dpcd_backlight_get.raw, | |
4293 | sizeof(union dpcd_source_backlight_get))) | |
4294 | return false; | |
4295 | ||
4296 | *backlight_millinits_avg = | |
4297 | dpcd_backlight_get.bytes.backlight_millinits_avg; | |
4298 | *backlight_millinits_peak = | |
4299 | dpcd_backlight_get.bytes.backlight_millinits_peak; | |
4300 | ||
4301 | /* On non-supported panels dpcd_read usually succeeds with 0 returned */ | |
4302 | if (*backlight_millinits_avg == 0 || | |
4303 | *backlight_millinits_avg > *backlight_millinits_peak) | |
4304 | return false; | |
4305 | ||
4306 | return true; | |
4307 | } | |
4308 | ||
4309 | bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable) | |
4310 | { | |
4311 | uint8_t backlight_enable = enable ? 1 : 0; | |
4312 | ||
4313 | if (!link || (link->connector_signal != SIGNAL_TYPE_EDP && | |
4314 | link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)) | |
4315 | return false; | |
4316 | ||
4317 | if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE, | |
4318 | &backlight_enable, 1) != DC_OK) | |
4319 | return false; | |
4320 | ||
4321 | return true; | |
4322 | } | |
4323 | ||
4324 | // we read default from 0x320 because we expect BIOS wrote it there | |
4325 | // regular get_backlight_nit reads from panel set at 0x326 | |
4326 | bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits) | |
4327 | { | |
4328 | if (!link || (link->connector_signal != SIGNAL_TYPE_EDP && | |
4329 | link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)) | |
4330 | return false; | |
4331 | ||
4332 | if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL, | |
4333 | (uint8_t *) backlight_millinits, | |
4334 | sizeof(uint32_t))) | |
4335 | return false; | |
4336 | ||
4337 | return true; | |
4338 | } | |
4339 | ||
4340 | bool dc_link_set_default_brightness_aux(struct dc_link *link) | |
4341 | { | |
4342 | uint32_t default_backlight; | |
4343 | ||
4344 | if (link && | |
4345 | (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || | |
4346 | link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) { | |
4347 | if (!dc_link_read_default_bl_aux(link, &default_backlight)) | |
4348 | default_backlight = 150000; | |
4349 | // if < 5 nits or > 5000, it might be wrong readback | |
4350 | if (default_backlight < 5000 || default_backlight > 5000000) | |
4351 | default_backlight = 150000; // | |
4352 | ||
4353 | return dc_link_set_backlight_level_nits(link, true, | |
4354 | default_backlight, 0); | |
4355 | } | |
4356 | return false; | |
4357 | } |