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drm/amd/display: Read LTTPR caps first on bootup
[linux-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
CommitLineData
4562236b
HW		 1/* Copyright 2015 Advanced Micro Devices, Inc. */
2#include "dm_services.h"
3#include "dc.h"
4#include "dc_link_dp.h"
5#include "dm_helpers.h"
7f93c1de 6#include "opp.h"
97bda032 7#include "dsc.h"
6fbefb84 8#include "resource.h"
4562236b
HW		 9
10#include "inc/core_types.h"
11#include "link_hwss.h"
12#include "dc_link_ddc.h"
13#include "core_status.h"
14#include "dpcd_defs.h"
dc6e2448
WW		 15#include "dc_dmub_srv.h"
16#include "dce/dmub_hw_lock_mgr.h"
ede4f6da 17#include "inc/link_enc_cfg.h"
4562236b 18
8dfcb24e
LJ		 19/*Travis*/
20static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
21/*Nutmeg*/
22static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
23
1296423b
BL		 24#define DC_LOGGER \
25 link->ctx->logger
9248681f 26#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
8e5100a5 27
9248681f
AT		 28 /* maximum pre emphasis level allowed for each voltage swing level*/
29 static const enum dc_pre_emphasis
30 voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
31 PRE_EMPHASIS_LEVEL2,
32 PRE_EMPHASIS_LEVEL1,
33 PRE_EMPHASIS_DISABLED };
4562236b
HW		 34
35enum {
36 POST_LT_ADJ_REQ_LIMIT = 6,
37 POST_LT_ADJ_REQ_TIMEOUT = 200
38};
39
04e21292
DA		 40static bool decide_fallback_link_setting(
41 struct dc_link_settings initial_link_settings,
42 struct dc_link_settings *current_link_setting,
43 enum link_training_result training_result);
9a6a8075 44static struct dc_link_settings get_common_supported_link_settings(
04e21292
DA		 45 struct dc_link_settings link_setting_a,
46 struct dc_link_settings link_setting_b);
47
b50d5551
WL		 48static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
49 const struct dc_link_settings *link_settings)
50{
51 union training_aux_rd_interval training_rd_interval;
52 uint32_t wait_in_micro_secs = 100;
53
54 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
55 core_link_read_dpcd(
56 link,
57 DP_TRAINING_AUX_RD_INTERVAL,
58 (uint8_t *)&training_rd_interval,
59 sizeof(training_rd_interval));
60 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
61 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
62 return wait_in_micro_secs;
63}
64
3fb068c3 65static uint32_t get_eq_training_aux_rd_interval(
d0778ebf 66 struct dc_link *link,
3fb068c3 67 const struct dc_link_settings *link_settings)
4562236b 68{
d6d36b55 69 union training_aux_rd_interval training_rd_interval;
3fb068c3 70 uint32_t wait_in_micro_secs = 400;
d6d36b55
NC		 71
72 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
4562236b
HW		 73 /* overwrite the delay if rev > 1.1*/
74 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
75 /* DP 1.2 or later - retrieve delay through
76 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
77 core_link_read_dpcd(
78 link,
3a340294 79 DP_TRAINING_AUX_RD_INTERVAL,
4562236b
HW		 80 (uint8_t *)&training_rd_interval,
81 sizeof(training_rd_interval));
82
83 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
3fb068c3 84 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
4562236b
HW		 85 }
86
3fb068c3 87 return wait_in_micro_secs;
e0a6440a
DG		 88}
89
e84ecdc5 90void dp_wait_for_training_aux_rd_interval(
e0a6440a
DG		 91 struct dc_link *link,
92 uint32_t wait_in_micro_secs)
93{
94 udelay(wait_in_micro_secs);
4562236b 95
1296423b 96 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
4562236b 97 __func__,
e0a6440a 98 wait_in_micro_secs);
4562236b
HW		 99}
100
e84ecdc5 101enum dpcd_training_patterns
ebc22cbd
WL		 102 dc_dp_training_pattern_to_dpcd_training_pattern(
103 struct dc_link *link,
104 enum dc_dp_training_pattern pattern)
105{
106 enum dpcd_training_patterns dpcd_tr_pattern =
107 DPCD_TRAINING_PATTERN_VIDEOIDLE;
108
109 switch (pattern) {
110 case DP_TRAINING_PATTERN_SEQUENCE_1:
111 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
112 break;
113 case DP_TRAINING_PATTERN_SEQUENCE_2:
114 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
115 break;
116 case DP_TRAINING_PATTERN_SEQUENCE_3:
117 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
118 break;
119 case DP_TRAINING_PATTERN_SEQUENCE_4:
120 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
121 break;
122 case DP_TRAINING_PATTERN_VIDEOIDLE:
123 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
124 break;
125 default:
126 ASSERT(0);
127 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
128 __func__, pattern);
129 break;
130 }
131
132 return dpcd_tr_pattern;
133}
134
4562236b 135static void dpcd_set_training_pattern(
d0778ebf 136 struct dc_link *link,
ebc22cbd 137 enum dc_dp_training_pattern training_pattern)
4562236b 138{
ebc22cbd
WL		 139 union dpcd_training_pattern dpcd_pattern = { {0} };
140
141 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
142 dc_dp_training_pattern_to_dpcd_training_pattern(
143 link, training_pattern);
144
4562236b
HW		 145 core_link_write_dpcd(
146 link,
3a340294 147 DP_TRAINING_PATTERN_SET,
4562236b
HW		 148 &dpcd_pattern.raw,
149 1);
150
1296423b 151 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
4562236b 152 __func__,
3a340294 153 DP_TRAINING_PATTERN_SET,
4562236b
HW		 154 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
155}
156
ce17ce17
WL		 157static enum dc_dp_training_pattern decide_cr_training_pattern(
158 const struct dc_link_settings *link_settings)
159{
4b1d6831 160 return DP_TRAINING_PATTERN_SEQUENCE_1;
ce17ce17
WL		 161}
162
163static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
164 const struct dc_link_settings *link_settings)
16b6253a 165{
ede4f6da 166 struct link_encoder *link_enc;
e0a6440a 167 enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
ede4f6da 168 struct encoder_feature_support *features;
16b6253a 169 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
170
ede4f6da
JK		 171 /* Access link encoder capability based on whether it is statically
172 * or dynamically assigned to a link.
173 */
174 if (link->is_dig_mapping_flexible &&
175 link->dc->res_pool->funcs->link_encs_assign)
176 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
177 else
178 link_enc = link->link_enc;
179 ASSERT(link_enc);
180 features = &link_enc->features;
181
16b6253a 182 if (features->flags.bits.IS_TPS3_CAPABLE)
e0a6440a 183 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
16b6253a 184
185 if (features->flags.bits.IS_TPS4_CAPABLE)
e0a6440a 186 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
16b6253a 187
188 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
e0a6440a
DG		 189 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
190 return DP_TRAINING_PATTERN_SEQUENCE_4;
16b6253a 191
192 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
e0a6440a
DG		 193 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
194 return DP_TRAINING_PATTERN_SEQUENCE_3;
16b6253a 195
e0a6440a 196 return DP_TRAINING_PATTERN_SEQUENCE_2;
16b6253a 197}
198
7211b605 199enum dc_status dpcd_set_link_settings(
d0778ebf 200 struct dc_link *link,
4562236b
HW		 201 const struct link_training_settings *lt_settings)
202{
8628d02f 203 uint8_t rate;
7211b605 204 enum dc_status status;
4562236b 205
9a6a8075
HW		 206 union down_spread_ctrl downspread = { {0} };
207 union lane_count_set lane_count_set = { {0} };
4562236b
HW		 208
209 downspread.raw = (uint8_t)
210 (lt_settings->link_settings.link_spread);
211
212 lane_count_set.bits.LANE_COUNT_SET =
213 lt_settings->link_settings.lane_count;
214
e0a6440a 215 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
16b6253a 216 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
217
e0a6440a 218
7211b605
JK		 219 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
220 lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
16b6253a 221 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
222 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
223 }
4562236b 224
7211b605 225 status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
e0a6440a 226 &downspread.raw, sizeof(downspread));
4562236b 227
7211b605 228 status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
e0a6440a 229 &lane_count_set.raw, 1);
8628d02f 230
b03a599b 231 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
8628d02f
JP		 232 lt_settings->link_settings.use_link_rate_set == true) {
233 rate = 0;
8edb9456
DZ		 234 /* WA for some MUX chips that will power down with eDP and lose supported
235 * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
236 * MUX chip gets link rate set back before link training.
237 */
238 if (link->connector_signal == SIGNAL_TYPE_EDP) {
239 uint8_t supported_link_rates[16];
240
241 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
242 supported_link_rates, sizeof(supported_link_rates));
243 }
7211b605
JK		 244 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
245 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
8628d02f
JP		 246 &lt_settings->link_settings.link_rate_set, 1);
247 } else {
248 rate = (uint8_t) (lt_settings->link_settings.link_rate);
7211b605 249 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
b03a599b
DL		 250 }
251
8628d02f 252 if (rate) {
e0a6440a 253 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
8628d02f
JP		 254 __func__,
255 DP_LINK_BW_SET,
256 lt_settings->link_settings.link_rate,
257 DP_LANE_COUNT_SET,
258 lt_settings->link_settings.lane_count,
e0a6440a 259 lt_settings->enhanced_framing,
8628d02f
JP		 260 DP_DOWNSPREAD_CTRL,
261 lt_settings->link_settings.link_spread);
262 } else {
e0a6440a 263 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
8628d02f
JP		 264 __func__,
265 DP_LINK_RATE_SET,
266 lt_settings->link_settings.link_rate_set,
267 DP_LANE_COUNT_SET,
268 lt_settings->link_settings.lane_count,
e0a6440a 269 lt_settings->enhanced_framing,
8628d02f
JP		 270 DP_DOWNSPREAD_CTRL,
271 lt_settings->link_settings.link_spread);
272 }
7211b605
JK		 273
274 return status;
4562236b
HW		 275}
276
e84ecdc5 277uint8_t dc_dp_initialize_scrambling_data_symbols(
7d1ee78f
VS		 278 struct dc_link *link,
279 enum dc_dp_training_pattern pattern)
280{
281 uint8_t disable_scrabled_data_symbols = 0;
282
283 switch (pattern) {
284 case DP_TRAINING_PATTERN_SEQUENCE_1:
285 case DP_TRAINING_PATTERN_SEQUENCE_2:
286 case DP_TRAINING_PATTERN_SEQUENCE_3:
287 disable_scrabled_data_symbols = 1;
288 break;
289 case DP_TRAINING_PATTERN_SEQUENCE_4:
290 disable_scrabled_data_symbols = 0;
291 break;
292 default:
293 ASSERT(0);
294 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
295 __func__, pattern);
296 break;
297 }
298 return disable_scrabled_data_symbols;
299}
300
64c12b73 301static inline bool is_repeater(struct dc_link *link, uint32_t offset)
302{
3128b285 303 return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
64c12b73 304}
305
4562236b 306static void dpcd_set_lt_pattern_and_lane_settings(
d0778ebf 307 struct dc_link *link,
4562236b 308 const struct link_training_settings *lt_settings,
64c12b73 309 enum dc_dp_training_pattern pattern,
310 uint32_t offset)
4562236b 311{
9a6a8075 312 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
64c12b73 313
314 uint32_t dpcd_base_lt_offset;
315
4562236b 316 uint8_t dpcd_lt_buffer[5] = {0};
9a6a8075 317 union dpcd_training_pattern dpcd_pattern = { {0} };
4562236b
HW		 318 uint32_t lane;
319 uint32_t size_in_bytes;
320 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
64c12b73 321 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
322
323 if (is_repeater(link, offset))
324 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
325 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b
HW		 326
327 /*****************************************************************
328 * DpcdAddress_TrainingPatternSet
329 *****************************************************************/
330 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
e0a6440a 331 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
4562236b 332
7d1ee78f
VS		 333 dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
334 dc_dp_initialize_scrambling_data_symbols(link, pattern);
335
64c12b73 336 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
4562236b
HW		 337 = dpcd_pattern.raw;
338
460adc6b 339 if (is_repeater(link, offset)) {
340 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
341 __func__,
342 offset,
343 dpcd_base_lt_offset,
344 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
345 } else {
346 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
347 __func__,
348 dpcd_base_lt_offset,
349 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
350 }
4562236b
HW		 351 /*****************************************************************
352 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
353 *****************************************************************/
354 for (lane = 0; lane <
355 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
356
357 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
358 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
359 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
360 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
361
362 dpcd_lane[lane].bits.MAX_SWING_REACHED =
363 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
364 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
365 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
366 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
367 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
368 }
369
64c12b73 370 /* concatenate everything into one buffer*/
4562236b
HW		 371
372 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
373
374 // 0x00103 - 0x00102
375 memmove(
64c12b73 376 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
4562236b
HW		 377 dpcd_lane,
378 size_in_bytes);
379
460adc6b 380 if (is_repeater(link, offset)) {
381 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
382 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
383 __func__,
384 offset,
385 dpcd_base_lt_offset,
386 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
387 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
388 dpcd_lane[0].bits.MAX_SWING_REACHED,
389 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
390 } else {
391 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
392 __func__,
393 dpcd_base_lt_offset,
394 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
395 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
396 dpcd_lane[0].bits.MAX_SWING_REACHED,
397 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
398 }
4562236b
HW		 399 if (edp_workaround) {
400 /* for eDP write in 2 parts because the 5-byte burst is
401 * causing issues on some eDP panels (EPR#366724)
402 */
403 core_link_write_dpcd(
404 link,
3a340294 405 DP_TRAINING_PATTERN_SET,
4562236b 406 &dpcd_pattern.raw,
9a6a8075 407 sizeof(dpcd_pattern.raw));
4562236b
HW		 408
409 core_link_write_dpcd(
410 link,
3a340294 411 DP_TRAINING_LANE0_SET,
4562236b
HW		 412 (uint8_t *)(dpcd_lane),
413 size_in_bytes);
414
415 } else
416 /* write it all in (1 + number-of-lanes)-byte burst*/
417 core_link_write_dpcd(
418 link,
419 dpcd_base_lt_offset,
420 dpcd_lt_buffer,
9a6a8075 421 size_in_bytes + sizeof(dpcd_pattern.raw));
4562236b 422
d0778ebf 423 link->cur_lane_setting = lt_settings->lane_settings[0];
4562236b
HW		 424}
425
e84ecdc5 426bool dp_is_cr_done(enum dc_lane_count ln_count,
4562236b
HW		 427 union lane_status *dpcd_lane_status)
428{
4562236b
HW		 429 uint32_t lane;
430 /*LANEx_CR_DONE bits All 1's?*/
431 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
432 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
d56b83f7 433 return false;
4562236b 434 }
d56b83f7 435 return true;
4562236b
HW		 436}
437
0cb15885 438bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
ebc22cbd 439 union lane_status *dpcd_lane_status)
4562236b 440{
ebc22cbd 441 bool done = true;
4562236b 442 uint32_t lane;
ebc22cbd
WL		 443 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
444 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
445 done = false;
446 return done;
447}
448
0cb15885 449bool dp_is_symbol_locked(enum dc_lane_count ln_count,
ebc22cbd
WL		 450 union lane_status *dpcd_lane_status)
451{
452 bool locked = true;
453 uint32_t lane;
454 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
455 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
456 locked = false;
457 return locked;
458}
459
0cb15885 460bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
ebc22cbd
WL		 461{
462 return align_status.bits.INTERLANE_ALIGN_DONE == 1;
4562236b
HW		 463}
464
e84ecdc5 465void dp_update_drive_settings(
4562236b
HW		 466 struct link_training_settings *dest,
467 struct link_training_settings src)
468{
469 uint32_t lane;
470 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
e0a6440a
DG		 471 if (dest->voltage_swing == NULL)
472 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
473 else
474 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
475
476 if (dest->pre_emphasis == NULL)
477 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
478 else
479 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
480
481 if (dest->post_cursor2 == NULL)
482 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
483 else
484 dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
4562236b
HW		 485 }
486}
487
488static uint8_t get_nibble_at_index(const uint8_t *buf,
489 uint32_t index)
490{
491 uint8_t nibble;
492 nibble = buf[index / 2];
493
494 if (index % 2)
495 nibble >>= 4;
496 else
497 nibble &= 0x0F;
498
499 return nibble;
500}
501
502static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
503 enum dc_voltage_swing voltage)
504{
505 enum dc_pre_emphasis pre_emphasis;
506 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
507
508 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
509 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
510
511 return pre_emphasis;
512
513}
514
515static void find_max_drive_settings(
516 const struct link_training_settings *link_training_setting,
517 struct link_training_settings *max_lt_setting)
518{
519 uint32_t lane;
520 struct dc_lane_settings max_requested;
521
522 max_requested.VOLTAGE_SWING =
523 link_training_setting->
524 lane_settings[0].VOLTAGE_SWING;
525 max_requested.PRE_EMPHASIS =
526 link_training_setting->
527 lane_settings[0].PRE_EMPHASIS;
528 /*max_requested.postCursor2 =
529 * link_training_setting->laneSettings[0].postCursor2;*/
530
531 /* Determine what the maximum of the requested settings are*/
532 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
533 lane++) {
534 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
535 max_requested.VOLTAGE_SWING)
536
537 max_requested.VOLTAGE_SWING =
538 link_training_setting->
539 lane_settings[lane].VOLTAGE_SWING;
540
541 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
542 max_requested.PRE_EMPHASIS)
543 max_requested.PRE_EMPHASIS =
544 link_training_setting->
545 lane_settings[lane].PRE_EMPHASIS;
546
547 /*
548 if (link_training_setting->laneSettings[lane].postCursor2 >
549 max_requested.postCursor2)
550 {
551 max_requested.postCursor2 =
552 link_training_setting->laneSettings[lane].postCursor2;
553 }
554 */
555 }
556
557 /* make sure the requested settings are
558 * not higher than maximum settings*/
559 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
560 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
561
562 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
563 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
564 /*
565 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
566 max_requested.postCursor2 = PostCursor2_MaxLevel;
567 */
568
569 /* make sure the pre-emphasis matches the voltage swing*/
570 if (max_requested.PRE_EMPHASIS >
571 get_max_pre_emphasis_for_voltage_swing(
572 max_requested.VOLTAGE_SWING))
573 max_requested.PRE_EMPHASIS =
574 get_max_pre_emphasis_for_voltage_swing(
575 max_requested.VOLTAGE_SWING);
576
577 /*
578 * Post Cursor2 levels are completely independent from
579 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
580 * can only be applied to each allowable combination of voltage
581 * swing and pre-emphasis levels */
582 /* if ( max_requested.postCursor2 >
583 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
584 * max_requested.postCursor2 =
585 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
586 */
587
588 max_lt_setting->link_settings.link_rate =
589 link_training_setting->link_settings.link_rate;
590 max_lt_setting->link_settings.lane_count =
591 link_training_setting->link_settings.lane_count;
592 max_lt_setting->link_settings.link_spread =
593 link_training_setting->link_settings.link_spread;
594
595 for (lane = 0; lane <
596 link_training_setting->link_settings.lane_count;
597 lane++) {
598 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
599 max_requested.VOLTAGE_SWING;
600 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
601 max_requested.PRE_EMPHASIS;
602 /*max_lt_setting->laneSettings[lane].postCursor2 =
603 * max_requested.postCursor2;
604 */
605 }
606
607}
608
e84ecdc5 609enum dc_status dp_get_lane_status_and_drive_settings(
d0778ebf 610 struct dc_link *link,
4562236b
HW		 611 const struct link_training_settings *link_training_setting,
612 union lane_status *ln_status,
613 union lane_align_status_updated *ln_status_updated,
64c12b73 614 struct link_training_settings *req_settings,
615 uint32_t offset)
4562236b 616{
64c12b73 617 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
618 uint8_t lane_adjust_offset = 4;
619 unsigned int lane01_adjust_address;
4562236b 620 uint8_t dpcd_buf[6] = {0};
9a6a8075
HW		 621 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
622 struct link_training_settings request_settings = { {0} };
4562236b 623 uint32_t lane;
e84ecdc5 624 enum dc_status status;
4562236b
HW		 625
626 memset(req_settings, '\0', sizeof(struct link_training_settings));
627
64c12b73 628 if (is_repeater(link, offset)) {
629 lane01_status_address =
630 DP_LANE0_1_STATUS_PHY_REPEATER1 +
631 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
632 lane_adjust_offset = 3;
633 }
634
e84ecdc5 635 status = core_link_read_dpcd(
4562236b 636 link,
64c12b73 637 lane01_status_address,
4562236b
HW		 638 (uint8_t *)(dpcd_buf),
639 sizeof(dpcd_buf));
640
641 for (lane = 0; lane <
642 (uint32_t)(link_training_setting->link_settings.lane_count);
643 lane++) {
644
645 ln_status[lane].raw =
646 get_nibble_at_index(&dpcd_buf[0], lane);
647 dpcd_lane_adjust[lane].raw =
64c12b73 648 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
4562236b
HW		 649 }
650
651 ln_status_updated->raw = dpcd_buf[2];
652
460adc6b 653 if (is_repeater(link, offset)) {
654 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
655 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
656 __func__,
657 offset,
658 lane01_status_address, dpcd_buf[0],
659 lane01_status_address + 1, dpcd_buf[1]);
660 } else {
661 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
662 __func__,
663 lane01_status_address, dpcd_buf[0],
664 lane01_status_address + 1, dpcd_buf[1]);
665 }
64c12b73 666 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
667
668 if (is_repeater(link, offset))
669 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
670 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b 671
460adc6b 672 if (is_repeater(link, offset)) {
673 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
674 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
675 __func__,
676 offset,
677 lane01_adjust_address,
678 dpcd_buf[lane_adjust_offset],
679 lane01_adjust_address + 1,
680 dpcd_buf[lane_adjust_offset + 1]);
681 } else {
682 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
683 __func__,
684 lane01_adjust_address,
685 dpcd_buf[lane_adjust_offset],
686 lane01_adjust_address + 1,
687 dpcd_buf[lane_adjust_offset + 1]);
688 }
4562236b
HW		 689
690 /*copy to req_settings*/
691 request_settings.link_settings.lane_count =
692 link_training_setting->link_settings.lane_count;
693 request_settings.link_settings.link_rate =
694 link_training_setting->link_settings.link_rate;
695 request_settings.link_settings.link_spread =
696 link_training_setting->link_settings.link_spread;
697
698 for (lane = 0; lane <
699 (uint32_t)(link_training_setting->link_settings.lane_count);
700 lane++) {
701
702 request_settings.lane_settings[lane].VOLTAGE_SWING =
703 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
704 VOLTAGE_SWING_LANE);
705 request_settings.lane_settings[lane].PRE_EMPHASIS =
706 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
707 PRE_EMPHASIS_LANE);
708 }
709
710 /*Note: for postcursor2, read adjusted
711 * postcursor2 settings from*/
712 /*DpcdAddress_AdjustRequestPostCursor2 =
713 *0x020C (not implemented yet)*/
714
715 /* we find the maximum of the requested settings across all lanes*/
716 /* and set this maximum for all lanes*/
717 find_max_drive_settings(&request_settings, req_settings);
718
719 /* if post cursor 2 is needed in the future,
720 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
721 */
722
e84ecdc5 723 return status;
4562236b
HW		 724}
725
e84ecdc5 726enum dc_status dpcd_set_lane_settings(
d0778ebf 727 struct dc_link *link,
64c12b73 728 const struct link_training_settings *link_training_setting,
729 uint32_t offset)
4562236b
HW		 730{
731 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
732 uint32_t lane;
64c12b73 733 unsigned int lane0_set_address;
e84ecdc5 734 enum dc_status status;
64c12b73 735
736 lane0_set_address = DP_TRAINING_LANE0_SET;
737
738 if (is_repeater(link, offset))
739 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
740 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b
HW		 741
742 for (lane = 0; lane <
743 (uint32_t)(link_training_setting->
744 link_settings.lane_count);
745 lane++) {
746 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
747 (uint8_t)(link_training_setting->
748 lane_settings[lane].VOLTAGE_SWING);
749 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
750 (uint8_t)(link_training_setting->
751 lane_settings[lane].PRE_EMPHASIS);
752 dpcd_lane[lane].bits.MAX_SWING_REACHED =
753 (link_training_setting->
754 lane_settings[lane].VOLTAGE_SWING ==
755 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
756 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
757 (link_training_setting->
758 lane_settings[lane].PRE_EMPHASIS ==
759 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
760 }
761
e84ecdc5 762 status = core_link_write_dpcd(link,
64c12b73 763 lane0_set_address,
4562236b
HW		 764 (uint8_t *)(dpcd_lane),
765 link_training_setting->link_settings.lane_count);
766
767 /*
768 if (LTSettings.link.rate == LinkRate_High2)
769 {
770 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
771 for ( uint32_t lane = 0;
772 lane < lane_count_DPMax; lane++)
773 {
774 dpcd_lane2[lane].bits.post_cursor2_set =
775 static_cast<unsigned char>(
776 LTSettings.laneSettings[lane].postCursor2);
777 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
778 }
779 m_pDpcdAccessSrv->WriteDpcdData(
780 DpcdAddress_Lane0Set2,
781 reinterpret_cast<unsigned char*>(dpcd_lane2),
782 LTSettings.link.lanes);
783 }
784 */
785
460adc6b 786 if (is_repeater(link, offset)) {
787 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
788 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
789 __func__,
790 offset,
791 lane0_set_address,
792 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
793 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
794 dpcd_lane[0].bits.MAX_SWING_REACHED,
795 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
4562236b 796
460adc6b 797 } else {
798 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
799 __func__,
800 lane0_set_address,
801 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
802 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
803 dpcd_lane[0].bits.MAX_SWING_REACHED,
804 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
805 }
d0778ebf 806 link->cur_lane_setting = link_training_setting->lane_settings[0];
4562236b 807
e84ecdc5 808 return status;
4562236b
HW		 809}
810
e84ecdc5 811bool dp_is_max_vs_reached(
4562236b
HW		 812 const struct link_training_settings *lt_settings)
813{
814 uint32_t lane;
815 for (lane = 0; lane <
816 (uint32_t)(lt_settings->link_settings.lane_count);
817 lane++) {
818 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
819 == VOLTAGE_SWING_MAX_LEVEL)
820 return true;
821 }
822 return false;
823
824}
825
4562236b 826static bool perform_post_lt_adj_req_sequence(
d0778ebf 827 struct dc_link *link,
4562236b
HW		 828 struct link_training_settings *lt_settings)
829{
830 enum dc_lane_count lane_count =
831 lt_settings->link_settings.lane_count;
832
833 uint32_t adj_req_count;
834 uint32_t adj_req_timer;
835 bool req_drv_setting_changed;
836 uint32_t lane;
837
838 req_drv_setting_changed = false;
839 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
840 adj_req_count++) {
841
842 req_drv_setting_changed = false;
843
844 for (adj_req_timer = 0;
845 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
846 adj_req_timer++) {
847
848 struct link_training_settings req_settings;
849 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
850 union lane_align_status_updated
851 dpcd_lane_status_updated;
852
e84ecdc5
JK		 853 dp_get_lane_status_and_drive_settings(
854 link,
855 lt_settings,
856 dpcd_lane_status,
857 &dpcd_lane_status_updated,
858 &req_settings,
859 DPRX);
4562236b
HW		 860
861 if (dpcd_lane_status_updated.bits.
862 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
863 return true;
864
e84ecdc5 865 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
4562236b
HW		 866 return false;
867
0cb15885
JK		 868 if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
869 !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
870 !dp_is_interlane_aligned(dpcd_lane_status_updated))
4562236b
HW		 871 return false;
872
873 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
874
875 if (lt_settings->
876 lane_settings[lane].VOLTAGE_SWING !=
877 req_settings.lane_settings[lane].
878 VOLTAGE_SWING ||
879 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
880 req_settings.lane_settings[lane].PRE_EMPHASIS) {
881
882 req_drv_setting_changed = true;
883 break;
884 }
885 }
886
887 if (req_drv_setting_changed) {
e84ecdc5 888 dp_update_drive_settings(
9a6a8075 889 lt_settings, req_settings);
4562236b 890
d0778ebf 891 dc_link_dp_set_drive_settings(link,
4562236b
HW		 892 lt_settings);
893 break;
894 }
895
896 msleep(1);
897 }
898
899 if (!req_drv_setting_changed) {
1296423b 900 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
4562236b
HW		 901 __func__);
902
903 ASSERT(0);
904 return true;
905 }
906 }
1296423b 907 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
4562236b
HW		 908 __func__);
909
910 ASSERT(0);
911 return true;
912
913}
914
64c12b73 915/* Only used for channel equalization */
0cb15885 916uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
64c12b73 917{
918 unsigned int aux_rd_interval_us = 400;
919
920 switch (dpcd_aux_read_interval) {
921 case 0x01:
a71c76ac 922 aux_rd_interval_us = 4000;
64c12b73 923 break;
924 case 0x02:
a71c76ac 925 aux_rd_interval_us = 8000;
64c12b73 926 break;
927 case 0x03:
a71c76ac 928 aux_rd_interval_us = 12000;
64c12b73 929 break;
930 case 0x04:
931 aux_rd_interval_us = 16000;
932 break;
933 default:
934 break;
935 }
936
937 return aux_rd_interval_us;
938}
939
e84ecdc5 940enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
94405cf6
WL		 941 union lane_status *dpcd_lane_status)
942{
943 enum link_training_result result = LINK_TRAINING_SUCCESS;
944
945 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
946 result = LINK_TRAINING_CR_FAIL_LANE0;
947 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
948 result = LINK_TRAINING_CR_FAIL_LANE1;
949 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
950 result = LINK_TRAINING_CR_FAIL_LANE23;
951 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
952 result = LINK_TRAINING_CR_FAIL_LANE23;
953 return result;
954}
955
820e3935 956static enum link_training_result perform_channel_equalization_sequence(
d0778ebf 957 struct dc_link *link,
64c12b73 958 struct link_training_settings *lt_settings,
959 uint32_t offset)
4562236b
HW		 960{
961 struct link_training_settings req_settings;
e0a6440a 962 enum dc_dp_training_pattern tr_pattern;
4562236b 963 uint32_t retries_ch_eq;
64c12b73 964 uint32_t wait_time_microsec;
4562236b 965 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
9a6a8075
HW		 966 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
967 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
4562236b 968
64c12b73 969 /* Note: also check that TPS4 is a supported feature*/
970
e0a6440a 971 tr_pattern = lt_settings->pattern_for_eq;
4562236b 972
64c12b73 973 if (is_repeater(link, offset))
974 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
975
976 dp_set_hw_training_pattern(link, tr_pattern, offset);
4562236b
HW		 977
978 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
979 retries_ch_eq++) {
980
64c12b73 981 dp_set_hw_lane_settings(link, lt_settings, offset);
4562236b
HW		 982
983 /* 2. update DPCD*/
984 if (!retries_ch_eq)
985 /* EPR #361076 - write as a 5-byte burst,
64c12b73 986 * but only for the 1-st iteration
987 */
988
4562236b
HW		 989 dpcd_set_lt_pattern_and_lane_settings(
990 link,
991 lt_settings,
64c12b73 992 tr_pattern, offset);
4562236b 993 else
64c12b73 994 dpcd_set_lane_settings(link, lt_settings, offset);
4562236b
HW		 995
996 /* 3. wait for receiver to lock-on*/
64c12b73 997 wait_time_microsec = lt_settings->eq_pattern_time;
998
5fd21b39 999 if (is_repeater(link, offset))
64c12b73 1000 wait_time_microsec =
0cb15885 1001 dp_translate_training_aux_read_interval(
5fd21b39 1002 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
64c12b73 1003
e84ecdc5 1004 dp_wait_for_training_aux_rd_interval(
64c12b73 1005 link,
1006 wait_time_microsec);
4562236b
HW		 1007
1008 /* 4. Read lane status and requested
1009 * drive settings as set by the sink*/
1010
e84ecdc5 1011 dp_get_lane_status_and_drive_settings(
4562236b
HW		 1012 link,
1013 lt_settings,
1014 dpcd_lane_status,
1015 &dpcd_lane_status_updated,
64c12b73 1016 &req_settings,
1017 offset);
4562236b
HW		 1018
1019 /* 5. check CR done*/
e84ecdc5 1020 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
820e3935 1021 return LINK_TRAINING_EQ_FAIL_CR;
4562236b
HW		 1022
1023 /* 6. check CHEQ done*/
0cb15885
JK		 1024 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
1025 dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
1026 dp_is_interlane_aligned(dpcd_lane_status_updated))
820e3935 1027 return LINK_TRAINING_SUCCESS;
4562236b
HW		 1028
1029 /* 7. update VS/PE/PC2 in lt_settings*/
e84ecdc5 1030 dp_update_drive_settings(lt_settings, req_settings);
4562236b
HW		 1031 }
1032
820e3935 1033 return LINK_TRAINING_EQ_FAIL_EQ;
4562236b
HW		 1034
1035}
1036
b01f22ec
DG		 1037static void start_clock_recovery_pattern_early(struct dc_link *link,
1038 struct link_training_settings *lt_settings,
1039 uint32_t offset)
1040{
1041 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1042 __func__);
ce17ce17 1043 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
b01f22ec
DG		 1044 dp_set_hw_lane_settings(link, lt_settings, offset);
1045 udelay(400);
1046}
1047
94405cf6 1048static enum link_training_result perform_clock_recovery_sequence(
d0778ebf 1049 struct dc_link *link,
64c12b73 1050 struct link_training_settings *lt_settings,
1051 uint32_t offset)
4562236b
HW		 1052{
1053 uint32_t retries_cr;
1054 uint32_t retry_count;
64c12b73 1055 uint32_t wait_time_microsec;
4562236b 1056 struct link_training_settings req_settings;
e0a6440a 1057 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
4562236b
HW		 1058 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1059 union lane_align_status_updated dpcd_lane_status_updated;
1060
1061 retries_cr = 0;
1062 retry_count = 0;
4562236b 1063
82054678 1064 if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
ce17ce17 1065 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
4562236b
HW		 1066
1067 /* najeeb - The synaptics MST hub can put the LT in
1068 * infinite loop by switching the VS
1069 */
1070 /* between level 0 and level 1 continuously, here
1071 * we try for CR lock for LinkTrainingMaxCRRetry count*/
1072 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
e0a6440a 1073 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
4562236b
HW		 1074
1075 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1076 memset(&dpcd_lane_status_updated, '\0',
1077 sizeof(dpcd_lane_status_updated));
1078
1079 /* 1. call HWSS to set lane settings*/
1080 dp_set_hw_lane_settings(
1081 link,
64c12b73 1082 lt_settings,
1083 offset);
4562236b
HW		 1084
1085 /* 2. update DPCD of the receiver*/
50d2c602 1086 if (!retry_count)
4562236b
HW		 1087 /* EPR #361076 - write as a 5-byte burst,
1088 * but only for the 1-st iteration.*/
1089 dpcd_set_lt_pattern_and_lane_settings(
1090 link,
1091 lt_settings,
ce17ce17 1092 lt_settings->pattern_for_cr,
64c12b73 1093 offset);
4562236b
HW		 1094 else
1095 dpcd_set_lane_settings(
1096 link,
64c12b73 1097 lt_settings,
1098 offset);
4562236b
HW		 1099
1100 /* 3. wait receiver to lock-on*/
64c12b73 1101 wait_time_microsec = lt_settings->cr_pattern_time;
1102
3128b285 1103 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
64c12b73 1104 wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1105
e84ecdc5 1106 dp_wait_for_training_aux_rd_interval(
4562236b 1107 link,
64c12b73 1108 wait_time_microsec);
4562236b
HW		 1109
1110 /* 4. Read lane status and requested drive
1111 * settings as set by the sink
1112 */
e84ecdc5 1113 dp_get_lane_status_and_drive_settings(
4562236b
HW		 1114 link,
1115 lt_settings,
1116 dpcd_lane_status,
1117 &dpcd_lane_status_updated,
64c12b73 1118 &req_settings,
1119 offset);
4562236b
HW		 1120
1121 /* 5. check CR done*/
e84ecdc5 1122 if (dp_is_cr_done(lane_count, dpcd_lane_status))
94405cf6 1123 return LINK_TRAINING_SUCCESS;
4562236b
HW		 1124
1125 /* 6. max VS reached*/
e84ecdc5 1126 if (dp_is_max_vs_reached(lt_settings))
94405cf6 1127 break;
4562236b 1128
3d223c55
DG		 1129 /* 7. same lane settings*/
1130 /* Note: settings are the same for all lanes,
1131 * so comparing first lane is sufficient*/
1132 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
4562236b 1133 req_settings.lane_settings[0].VOLTAGE_SWING)
3d223c55
DG		 1134 && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1135 req_settings.lane_settings[0].PRE_EMPHASIS))
4562236b
HW		 1136 retries_cr++;
1137 else
1138 retries_cr = 0;
1139
1140 /* 8. update VS/PE/PC2 in lt_settings*/
e84ecdc5 1141 dp_update_drive_settings(lt_settings, req_settings);
4562236b
HW		 1142
1143 retry_count++;
1144 }
1145
1146 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1147 ASSERT(0);
1296423b 1148 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
4f42a2dd 1149 __func__,
4562236b
HW		 1150 LINK_TRAINING_MAX_CR_RETRY);
1151
1152 }
1153
e84ecdc5 1154 return dp_get_cr_failure(lane_count, dpcd_lane_status);
4562236b
HW		 1155}
1156
37f270c6 1157static inline enum link_training_result dp_transition_to_video_idle(
d0778ebf 1158 struct dc_link *link,
4562236b 1159 struct link_training_settings *lt_settings,
94405cf6 1160 enum link_training_result status)
4562236b
HW		 1161{
1162 union lane_count_set lane_count_set = { {0} };
4562236b
HW		 1163
1164 /* 4. mainlink output idle pattern*/
1165 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1166
1167 /*
1168 * 5. post training adjust if required
1169 * If the upstream DPTX and downstream DPRX both support TPS4,
1170 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1171 */
c30267f5 1172 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
cd6a9a1c
WL		 1173 lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
1174 /* delay 5ms after Main Link output idle pattern and then check
1175 * DPCD 0202h.
1176 */
1177 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1178 msleep(5);
1179 status = dp_check_link_loss_status(link, lt_settings);
1180 }
4562236b 1181 return status;
cd6a9a1c 1182 }
4562236b 1183
94405cf6 1184 if (status == LINK_TRAINING_SUCCESS &&
4562236b 1185 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
94405cf6 1186 status = LINK_TRAINING_LQA_FAIL;
4562236b
HW		 1187
1188 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
e0a6440a 1189 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
4562236b
HW		 1190 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1191
1192 core_link_write_dpcd(
1193 link,
3a340294 1194 DP_LANE_COUNT_SET,
4562236b
HW		 1195 &lane_count_set.raw,
1196 sizeof(lane_count_set));
1197
1198 return status;
1199}
1200
573a0a03 1201enum link_training_result dp_check_link_loss_status(
b246f90a
MT		 1202 struct dc_link *link,
1203 const struct link_training_settings *link_training_setting)
1204{
1205 enum link_training_result status = LINK_TRAINING_SUCCESS;
b246f90a 1206 union lane_status lane_status;
d9b91b1e 1207 uint8_t dpcd_buf[6] = {0};
b246f90a
MT		 1208 uint32_t lane;
1209
1210 core_link_read_dpcd(
d9b91b1e
AC		 1211 link,
1212 DP_SINK_COUNT,
1213 (uint8_t *)(dpcd_buf),
1214 sizeof(dpcd_buf));
b246f90a
MT		 1215
1216 /*parse lane status*/
1217 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1218 /*
1219 * check lanes status
1220 */
d9b91b1e 1221 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
b246f90a
MT		 1222
1223 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1224 !lane_status.bits.CR_DONE_0 ||
1225 !lane_status.bits.SYMBOL_LOCKED_0) {
1226 /* if one of the channel equalization, clock
1227 * recovery or symbol lock is dropped
1228 * consider it as (link has been
1229 * dropped) dp sink status has changed
1230 */
1231 status = LINK_TRAINING_LINK_LOSS;
1232 break;
1233 }
1234 }
1235
1236 return status;
1237}
1238
4c247f8c 1239static inline void decide_8b_10b_training_settings(
e0a6440a 1240 struct dc_link *link,
4562236b 1241 const struct dc_link_settings *link_setting,
0b226322 1242 const struct dc_link_training_overrides *overrides,
e0a6440a 1243 struct link_training_settings *lt_settings)
4562236b 1244{
e0a6440a 1245 uint32_t lane;
4562236b 1246
e0a6440a 1247 memset(lt_settings, '\0', sizeof(struct link_training_settings));
94405cf6 1248
e0a6440a
DG		 1249 /* Initialize link settings */
1250 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1251 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
4562236b 1252
e0a6440a
DG		 1253 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1254 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1255 else
1256 lt_settings->link_settings.link_rate = link_setting->link_rate;
4562236b 1257
e0a6440a
DG		 1258 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1259 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1260 else
1261 lt_settings->link_settings.lane_count = link_setting->lane_count;
4562236b
HW		 1262
1263 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1264
1265 /* TODO hard coded to SS for now
1266 * lt_settings.link_settings.link_spread =
1267 * dal_display_path_is_ss_supported(
1268 * path_mode->display_path) ?
1269 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1270 * LINK_SPREAD_DISABLED;
1271 */
e0a6440a 1272 /* Initialize link spread */
ad830e7a 1273 if (link->dp_ss_off)
e0a6440a 1274 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
0b226322 1275 else if (overrides->downspread != NULL)
e0a6440a 1276 lt_settings->link_settings.link_spread
0b226322 1277 = *overrides->downspread
e0a6440a
DG		 1278 ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1279 : LINK_SPREAD_DISABLED;
ad830e7a 1280 else
e0a6440a 1281 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
4562236b 1282
f1900a9b
WL		 1283 lt_settings->lttpr_mode = link->lttpr_mode;
1284
e0a6440a 1285 /* Initialize lane settings overrides */
0b226322
DG		 1286 if (overrides->voltage_swing != NULL)
1287 lt_settings->voltage_swing = overrides->voltage_swing;
4562236b 1288
0b226322
DG		 1289 if (overrides->pre_emphasis != NULL)
1290 lt_settings->pre_emphasis = overrides->pre_emphasis;
4562236b 1291
0b226322
DG		 1292 if (overrides->post_cursor2 != NULL)
1293 lt_settings->post_cursor2 = overrides->post_cursor2;
e0a6440a
DG		 1294
1295 /* Initialize lane settings (VS/PE/PC2) */
1296 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1297 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1298 lt_settings->voltage_swing != NULL ?
1299 *lt_settings->voltage_swing :
1300 VOLTAGE_SWING_LEVEL0;
1301 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1302 lt_settings->pre_emphasis != NULL ?
1303 *lt_settings->pre_emphasis
1304 : PRE_EMPHASIS_DISABLED;
1305 lt_settings->lane_settings[lane].POST_CURSOR2 =
1306 lt_settings->post_cursor2 != NULL ?
1307 *lt_settings->post_cursor2
1308 : POST_CURSOR2_DISABLED;
820e3935 1309 }
4562236b 1310
e0a6440a 1311 /* Initialize training timings */
0b226322
DG		 1312 if (overrides->cr_pattern_time != NULL)
1313 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
e0a6440a 1314 else
b50d5551 1315 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
e0a6440a 1316
0b226322
DG		 1317 if (overrides->eq_pattern_time != NULL)
1318 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
e0a6440a 1319 else
3fb068c3 1320 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
e0a6440a 1321
ce17ce17
WL		 1322 if (overrides->pattern_for_cr != NULL)
1323 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1324 else
1325 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
0b226322
DG		 1326 if (overrides->pattern_for_eq != NULL)
1327 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
e0a6440a 1328 else
ce17ce17 1329 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
e0a6440a 1330
0b226322
DG		 1331 if (overrides->enhanced_framing != NULL)
1332 lt_settings->enhanced_framing = *overrides->enhanced_framing;
e0a6440a
DG		 1333 else
1334 lt_settings->enhanced_framing = 1;
3df21257
WL		 1335
1336 if (link->preferred_training_settings.fec_enable != NULL)
1337 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
1338 else
1339 lt_settings->should_set_fec_ready = true;
e0a6440a
DG		 1340}
1341
7211b605 1342void dp_decide_training_settings(
4c247f8c
WL		 1343 struct dc_link *link,
1344 const struct dc_link_settings *link_settings,
1345 const struct dc_link_training_overrides *overrides,
1346 struct link_training_settings *lt_settings)
1347{
1348 if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1349 decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings);
1350}
1351
1352
573a0a03 1353uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
64c12b73 1354{
1355 switch (lttpr_repeater_count) {
1356 case 0x80: // 1 lttpr repeater
1357 return 1;
1358 case 0x40: // 2 lttpr repeaters
1359 return 2;
1360 case 0x20: // 3 lttpr repeaters
1361 return 3;
1362 case 0x10: // 4 lttpr repeaters
1363 return 4;
1364 case 0x08: // 5 lttpr repeaters
1365 return 5;
1366 case 0x04: // 6 lttpr repeaters
1367 return 6;
1368 case 0x02: // 7 lttpr repeaters
1369 return 7;
1370 case 0x01: // 8 lttpr repeaters
1371 return 8;
1372 default:
1373 break;
1374 }
1375 return 0; // invalid value
1376}
1377
7211b605 1378enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
3128b285
WC		 1379{
1380 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1381
f1900a9b 1382 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
7211b605 1383 return core_link_write_dpcd(link,
3128b285
WC		 1384 DP_PHY_REPEATER_MODE,
1385 (uint8_t *)&repeater_mode,
1386 sizeof(repeater_mode));
1387}
1388
7211b605 1389enum dc_status configure_lttpr_mode_non_transparent(
f1900a9b
WL		 1390 struct dc_link *link,
1391 const struct link_training_settings *lt_settings)
bad7ab0b 1392{
1393 /* aux timeout is already set to extended */
1394 /* RESET/SET lttpr mode to enable non transparent mode */
64c12b73 1395 uint8_t repeater_cnt;
1396 uint32_t aux_interval_address;
1397 uint8_t repeater_id;
a166f86e 1398 enum dc_status result = DC_ERROR_UNEXPECTED;
61aa7a6f 1399 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
bad7ab0b 1400
f1900a9b
WL		 1401 enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);
1402
1403 if (encoding == DP_8b_10b_ENCODING) {
1404 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1405 result = core_link_write_dpcd(link,
1406 DP_PHY_REPEATER_MODE,
1407 (uint8_t *)&repeater_mode,
1408 sizeof(repeater_mode));
1409
1410 }
bad7ab0b 1411
a166f86e 1412 if (result == DC_OK) {
1413 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1414 }
1415
3128b285 1416 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
460adc6b 1417
c14f2507 1418 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
460adc6b 1419
61aa7a6f 1420 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
a166f86e 1421 result = core_link_write_dpcd(link,
bad7ab0b 1422 DP_PHY_REPEATER_MODE,
1423 (uint8_t *)&repeater_mode,
1424 sizeof(repeater_mode));
64c12b73 1425
a166f86e 1426 if (result == DC_OK) {
1427 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1428 }
1429
f1900a9b
WL		 1430 if (encoding == DP_8b_10b_ENCODING) {
1431 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1432 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1433 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1434 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1435 core_link_read_dpcd(
1436 link,
1437 aux_interval_address,
1438 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1439 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1440 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1441 }
64c12b73 1442 }
bad7ab0b 1443 }
7211b605
JK		 1444
1445 return result;
bad7ab0b 1446}
1447
64c12b73 1448static void repeater_training_done(struct dc_link *link, uint32_t offset)
1449{
1450 union dpcd_training_pattern dpcd_pattern = { {0} };
1451
1452 const uint32_t dpcd_base_lt_offset =
1453 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1454 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1455 /* Set training not in progress*/
1456 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1457
1458 core_link_write_dpcd(
1459 link,
1460 dpcd_base_lt_offset,
1461 &dpcd_pattern.raw,
1462 1);
1463
460adc6b 1464 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
64c12b73 1465 __func__,
460adc6b 1466 offset,
64c12b73 1467 dpcd_base_lt_offset,
1468 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1469}
1470
e0a6440a
DG		 1471static void print_status_message(
1472 struct dc_link *link,
1473 const struct link_training_settings *lt_settings,
1474 enum link_training_result status)
1475{
1476 char *link_rate = "Unknown";
1477 char *lt_result = "Unknown";
1478 char *lt_spread = "Disabled";
4562236b 1479
e0a6440a 1480 switch (lt_settings->link_settings.link_rate) {
4562236b
HW		 1481 case LINK_RATE_LOW:
1482 link_rate = "RBR";
1483 break;
5c8a6c71
JZ		 1484 case LINK_RATE_RATE_2:
1485 link_rate = "R2";
1486 break;
1487 case LINK_RATE_RATE_3:
1488 link_rate = "R3";
1489 break;
4562236b
HW		 1490 case LINK_RATE_HIGH:
1491 link_rate = "HBR";
1492 break;
4562236b
HW		 1493 case LINK_RATE_RBR2:
1494 link_rate = "RBR2";
1495 break;
5c8a6c71
JZ		 1496 case LINK_RATE_RATE_6:
1497 link_rate = "R6";
1498 break;
1499 case LINK_RATE_HIGH2:
1500 link_rate = "HBR2";
1501 break;
4562236b
HW		 1502 case LINK_RATE_HIGH3:
1503 link_rate = "HBR3";
1504 break;
1505 default:
1506 break;
1507 }
1508
94405cf6
WL		 1509 switch (status) {
1510 case LINK_TRAINING_SUCCESS:
1511 lt_result = "pass";
1512 break;
1513 case LINK_TRAINING_CR_FAIL_LANE0:
1514 lt_result = "CR failed lane0";
1515 break;
1516 case LINK_TRAINING_CR_FAIL_LANE1:
1517 lt_result = "CR failed lane1";
1518 break;
1519 case LINK_TRAINING_CR_FAIL_LANE23:
1520 lt_result = "CR failed lane23";
1521 break;
1522 case LINK_TRAINING_EQ_FAIL_CR:
1523 lt_result = "CR failed in EQ";
1524 break;
1525 case LINK_TRAINING_EQ_FAIL_EQ:
1526 lt_result = "EQ failed";
1527 break;
1528 case LINK_TRAINING_LQA_FAIL:
1529 lt_result = "LQA failed";
1530 break;
b246f90a
MT		 1531 case LINK_TRAINING_LINK_LOSS:
1532 lt_result = "Link loss";
1533 break;
94405cf6
WL		 1534 default:
1535 break;
1536 }
1537
e0a6440a
DG		 1538 switch (lt_settings->link_settings.link_spread) {
1539 case LINK_SPREAD_DISABLED:
1540 lt_spread = "Disabled";
1541 break;
1542 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1543 lt_spread = "0.5% 30KHz";
1544 break;
1545 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1546 lt_spread = "0.5% 33KHz";
1547 break;
1548 default:
1549 break;
1550 }
1551
4562236b 1552 /* Connectivity log: link training */
e0a6440a
DG		 1553 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1554 link_rate,
1555 lt_settings->link_settings.lane_count,
1556 lt_result,
1557 lt_settings->lane_settings[0].VOLTAGE_SWING,
1558 lt_settings->lane_settings[0].PRE_EMPHASIS,
1559 lt_spread);
1560}
1561
64c12b73 1562void dc_link_dp_set_drive_settings(
1563 struct dc_link *link,
1564 struct link_training_settings *lt_settings)
1565{
1566 /* program ASIC PHY settings*/
1567 dp_set_hw_lane_settings(link, lt_settings, DPRX);
1568
1569 /* Notify DP sink the PHY settings from source */
1570 dpcd_set_lane_settings(link, lt_settings, DPRX);
1571}
1572
e0a6440a
DG		 1573bool dc_link_dp_perform_link_training_skip_aux(
1574 struct dc_link *link,
1575 const struct dc_link_settings *link_setting)
1576{
1577 struct link_training_settings lt_settings;
e0a6440a 1578
7211b605 1579 dp_decide_training_settings(
0b226322
DG		 1580 link,
1581 link_setting,
1582 &link->preferred_training_settings,
1583 &lt_settings);
e0a6440a
DG		 1584
1585 /* 1. Perform_clock_recovery_sequence. */
1586
1587 /* transmit training pattern for clock recovery */
ce17ce17 1588 dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
e0a6440a
DG		 1589
1590 /* call HWSS to set lane settings*/
64c12b73 1591 dp_set_hw_lane_settings(link, &lt_settings, DPRX);
e0a6440a
DG		 1592
1593 /* wait receiver to lock-on*/
e84ecdc5 1594 dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
e0a6440a
DG		 1595
1596 /* 2. Perform_channel_equalization_sequence. */
1597
1598 /* transmit training pattern for channel equalization. */
64c12b73 1599 dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
e0a6440a
DG		 1600
1601 /* call HWSS to set lane settings*/
64c12b73 1602 dp_set_hw_lane_settings(link, &lt_settings, DPRX);
e0a6440a
DG		 1603
1604 /* wait receiver to lock-on. */
e84ecdc5 1605 dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
e0a6440a
DG		 1606
1607 /* 3. Perform_link_training_int. */
1608
1609 /* Mainlink output idle pattern. */
1610 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1611
1612 print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1613
1614 return true;
1615}
1616
7211b605
JK		 1617enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
1618{
1619 enum dc_status status = DC_OK;
1620
1621 if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
1622 status = configure_lttpr_mode_transparent(link);
1623
1624 else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1625 status = configure_lttpr_mode_non_transparent(link, lt_settings);
1626
1627 return status;
1628}
1629
3df21257
WL		 1630static void dpcd_exit_training_mode(struct dc_link *link)
1631{
3df21257
WL		 1632
1633 /* clear training pattern set */
cd6a9a1c 1634 dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
3df21257
WL		 1635}
1636
1637enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1638 struct link_training_settings *lt_settings)
1639{
1640 enum dp_link_encoding encoding =
1641 dp_get_link_encoding_format(
1642 &lt_settings->link_settings);
1643 enum dc_status status;
1644
1645 status = core_link_write_dpcd(
1646 link,
1647 DP_MAIN_LINK_CHANNEL_CODING_SET,
1648 (uint8_t *) &encoding,
1649 1);
1650 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1651 __func__,
1652 DP_MAIN_LINK_CHANNEL_CODING_SET,
1653 encoding);
1654
1655 return status;
1656}
1657
cd6a9a1c
WL		 1658static enum link_training_result dp_perform_8b_10b_link_training(
1659 struct dc_link *link,
1660 struct link_training_settings *lt_settings)
e0a6440a
DG		 1661{
1662 enum link_training_result status = LINK_TRAINING_SUCCESS;
e0a6440a 1663
cd6a9a1c
WL		 1664 uint8_t repeater_cnt;
1665 uint8_t repeater_id;
bcc5042a 1666
82054678 1667 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
cd6a9a1c 1668 start_clock_recovery_pattern_early(link, lt_settings, DPRX);
834a9a9f
ML		 1669
1670 /* 1. set link rate, lane count and spread. */
cd6a9a1c 1671 dpcd_set_link_settings(link, lt_settings);
e0a6440a 1672
3128b285 1673 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
008a4016 1674
64c12b73 1675 /* 2. perform link training (set link training done
1676 * to false is done as well)
1677 */
573a0a03 1678 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
64c12b73 1679
1680 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1681 repeater_id--) {
cd6a9a1c 1682 status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
64c12b73 1683
1684 if (status != LINK_TRAINING_SUCCESS)
1685 break;
1686
1687 status = perform_channel_equalization_sequence(link,
cd6a9a1c 1688 lt_settings,
64c12b73 1689 repeater_id);
1690
1691 if (status != LINK_TRAINING_SUCCESS)
1692 break;
1693
1694 repeater_training_done(link, repeater_id);
1695 }
1696 }
1697
1698 if (status == LINK_TRAINING_SUCCESS) {
cd6a9a1c 1699 status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
e0a6440a
DG		 1700 if (status == LINK_TRAINING_SUCCESS) {
1701 status = perform_channel_equalization_sequence(link,
cd6a9a1c 1702 lt_settings,
64c12b73 1703 DPRX);
1704 }
e0a6440a
DG		 1705 }
1706
cd6a9a1c
WL		 1707 return status;
1708}
1709
1710enum link_training_result dc_link_dp_perform_link_training(
1711 struct dc_link *link,
1712 const struct dc_link_settings *link_settings,
1713 bool skip_video_pattern)
1714{
1715 enum link_training_result status = LINK_TRAINING_SUCCESS;
1716 struct link_training_settings lt_settings;
1717 enum dp_link_encoding encoding =
1718 dp_get_link_encoding_format(link_settings);
1719
1720 /* decide training settings */
1721 dp_decide_training_settings(
1722 link,
1723 link_settings,
1724 &link->preferred_training_settings,
1725 &lt_settings);
1726
1727 /* reset previous training states */
1728 dpcd_exit_training_mode(link);
1729
1730 /* configure link prior to entering training mode */
1731 dpcd_configure_lttpr_mode(link, &lt_settings);
1732 dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
1733 dpcd_configure_channel_coding(link, &lt_settings);
1734
1735 /* enter training mode:
1736 * Per DP specs starting from here, DPTX device shall not issue
1737 * Non-LT AUX transactions inside training mode.
1738 */
1739 if (encoding == DP_8b_10b_ENCODING)
1740 status = dp_perform_8b_10b_link_training(link, &lt_settings);
1741 else
1742 ASSERT(0);
1743
1744 /* exit training mode and switch to video idle */
1745 dpcd_exit_training_mode(link);
1746 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
37f270c6 1747 status = dp_transition_to_video_idle(link,
e0a6440a
DG		 1748 &lt_settings,
1749 status);
e0a6440a 1750
cd6a9a1c 1751 /* dump debug data */
e0a6440a 1752 print_status_message(link, &lt_settings, status);
d6e75df4 1753 if (status != LINK_TRAINING_SUCCESS)
cfd84fd3 1754 link->ctx->dc->debug_data.ltFailCount++;
4562236b
HW		 1755 return status;
1756}
1757
9127daa0
SW		 1758static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
1759{
1760 struct dc_link *link = stream->link;
1761 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1762#ifdef CONFIG_DRM_AMD_DC_HDCP
1763 struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1764#endif
1765
1766 /* ASSR must be supported on the panel */
1767 if (panel_mode == DP_PANEL_MODE_DEFAULT)
1768 return panel_mode;
1769
1770 /* eDP or internal DP only */
1771 if (link->connector_signal != SIGNAL_TYPE_EDP &&
1772 !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1773 link->is_internal_display))
1774 return DP_PANEL_MODE_DEFAULT;
1775
1776#ifdef CONFIG_DRM_AMD_DC_HDCP
1777 if (cp_psp && cp_psp->funcs.enable_assr) {
1778 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1779 /* since eDP implies ASSR on, change panel
1780 * mode to disable ASSR
1781 */
1782 panel_mode = DP_PANEL_MODE_DEFAULT;
1783 }
1784 } else
1785 panel_mode = DP_PANEL_MODE_DEFAULT;
1786
1787#else
1788 /* turn off ASSR if the implementation is not compiled in */
1789 panel_mode = DP_PANEL_MODE_DEFAULT;
1790#endif
1791 return panel_mode;
1792}
1793
4562236b 1794bool perform_link_training_with_retries(
4562236b
HW		 1795 const struct dc_link_settings *link_setting,
1796 bool skip_video_pattern,
832aa63b
PH		 1797 int attempts,
1798 struct pipe_ctx *pipe_ctx,
82253671
JK		 1799 enum signal_type signal,
1800 bool do_fallback)
4562236b
HW		 1801{
1802 uint8_t j;
1803 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
832aa63b
PH		 1804 struct dc_stream_state *stream = pipe_ctx->stream;
1805 struct dc_link *link = stream->link;
9127daa0 1806 enum dp_panel_mode panel_mode;
82253671
JK		 1807 struct link_encoder *link_enc;
1808 enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
f7115198 1809 struct dc_link_settings current_setting = *link_setting;
82253671
JK		 1810
1811 /* Dynamically assigned link encoders associated with stream rather than
1812 * link.
1813 */
1814 if (link->dc->res_pool->funcs->link_encs_assign)
1815 link_enc = stream->link_enc;
1816 else
1817 link_enc = link->link_enc;
1818 ASSERT(link_enc);
4562236b 1819
eec3303d
AC		 1820 /* We need to do this before the link training to ensure the idle pattern in SST
1821 * mode will be sent right after the link training
1822 */
82253671 1823 link_enc->funcs->connect_dig_be_to_fe(link_enc,
eec3303d
AC		 1824 pipe_ctx->stream_res.stream_enc->id, true);
1825
4562236b
HW		 1826 for (j = 0; j < attempts; ++j) {
1827
172c9b77
AT		 1828 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1829 __func__, (unsigned int)j + 1, attempts);
1830
832aa63b
PH		 1831 dp_enable_link_phy(
1832 link,
1833 signal,
1834 pipe_ctx->clock_source->id,
f7115198 1835 &current_setting);
832aa63b 1836
eec3303d
AC		 1837 if (stream->sink_patches.dppowerup_delay > 0) {
1838 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1839
832aa63b
PH		 1840 msleep(delay_dp_power_up_in_ms);
1841 }
1842
9127daa0 1843 panel_mode = try_enable_assr(stream);
832aa63b 1844 dp_set_panel_mode(link, panel_mode);
9127daa0
SW		 1845 DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
1846 link->link_index,
1847 panel_mode != DP_PANEL_MODE_DEFAULT);
832aa63b 1848
832aa63b 1849 if (link->aux_access_disabled) {
f7115198 1850 dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
832aa63b 1851 return true;
79ed7354 1852 } else {
79ed7354
JK		 1853 status = dc_link_dp_perform_link_training(
1854 link,
f7115198 1855 &current_setting,
79ed7354
JK		 1856 skip_video_pattern);
1857 if (status == LINK_TRAINING_SUCCESS)
1858 return true;
1859 }
4562236b 1860
832aa63b
PH		 1861 /* latest link training still fail, skip delay and keep PHY on
1862 */
82253671 1863 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
832aa63b
PH		 1864 break;
1865
172c9b77
AT		 1866 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1867 __func__, (unsigned int)j + 1, attempts);
1868
832aa63b
PH		 1869 dp_disable_link_phy(link, signal);
1870
82253671
JK		 1871 /* Abort link training if failure due to sink being unplugged. */
1872 if (status == LINK_TRAINING_ABORT)
1873 break;
1874 else if (do_fallback) {
f7115198 1875 decide_fallback_link_setting(*link_setting, &current_setting, status);
82253671
JK		 1876 /* Fail link training if reduced link bandwidth no longer meets
1877 * stream requirements.
1878 */
1879 if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
f7115198 1880 dc_link_bandwidth_kbps(link, &current_setting))
82253671
JK		 1881 break;
1882 }
1883
4562236b 1884 msleep(delay_between_attempts);
832aa63b 1885
4562236b
HW		 1886 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1887 }
1888
1889 return false;
1890}
1891
0b226322
DG		 1892static enum clock_source_id get_clock_source_id(struct dc_link *link)
1893{
1894 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1895 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1896
1897 if (dp_cs != NULL) {
1898 dp_cs_id = dp_cs->id;
1899 } else {
1900 /*
1901 * dp clock source is not initialized for some reason.
1902 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1903 */
1904 ASSERT(dp_cs);
1905 }
1906
1907 return dp_cs_id;
1908}
1909
1910static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1911{
1912 if (mst_enable == false &&
1913 link->type == dc_connection_mst_branch) {
1914 /* Disable MST on link. Use only local sink. */
1915 dp_disable_link_phy_mst(link, link->connector_signal);
1916
1917 link->type = dc_connection_single;
1918 link->local_sink = link->remote_sinks[0];
1919 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
3f8518b6
VS		 1920 dc_sink_retain(link->local_sink);
1921 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
0b226322
DG		 1922 } else if (mst_enable == true &&
1923 link->type == dc_connection_single &&
1924 link->remote_sinks[0] != NULL) {
1925 /* Re-enable MST on link. */
1926 dp_disable_link_phy(link, link->connector_signal);
1927 dp_enable_mst_on_sink(link, true);
1928
1929 link->type = dc_connection_mst_branch;
1930 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1931 }
1932}
1933
1934bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1935{
1936 /* Begin Sync LT. During this time,
1937 * DPCD:600h must not be powered down.
1938 */
1939 link->sync_lt_in_progress = true;
1940
1941 /*Clear any existing preferred settings.*/
1942 memset(&link->preferred_training_settings, 0,
1943 sizeof(struct dc_link_training_overrides));
1944 memset(&link->preferred_link_setting, 0,
1945 sizeof(struct dc_link_settings));
1946
1947 return true;
1948}
1949
1950enum link_training_result dc_link_dp_sync_lt_attempt(
1951 struct dc_link *link,
1952 struct dc_link_settings *link_settings,
1953 struct dc_link_training_overrides *lt_overrides)
1954{
1955 struct link_training_settings lt_settings;
1956 enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1957 enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1958 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
0b226322 1959 bool fec_enable = false;
0b226322 1960
7211b605 1961 dp_decide_training_settings(
0b226322
DG		 1962 link,
1963 link_settings,
1964 lt_overrides,
1965 &lt_settings);
1966
1967 /* Setup MST Mode */
1968 if (lt_overrides->mst_enable)
1969 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1970
1971 /* Disable link */
1972 dp_disable_link_phy(link, link->connector_signal);
1973
1974 /* Enable link */
1975 dp_cs_id = get_clock_source_id(link);
1976 dp_enable_link_phy(link, link->connector_signal,
1977 dp_cs_id, link_settings);
1978
0b226322
DG		 1979 /* Set FEC enable */
1980 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1981 dp_set_fec_ready(link, fec_enable);
0b226322
DG		 1982
1983 if (lt_overrides->alternate_scrambler_reset) {
1984 if (*lt_overrides->alternate_scrambler_reset)
1985 panel_mode = DP_PANEL_MODE_EDP;
1986 else
1987 panel_mode = DP_PANEL_MODE_DEFAULT;
1988 } else
1989 panel_mode = dp_get_panel_mode(link);
1990
1991 dp_set_panel_mode(link, panel_mode);
1992
1993 /* Attempt to train with given link training settings */
82054678
ML		 1994 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1995 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
834a9a9f
ML		 1996
1997 /* Set link rate, lane count and spread. */
1998 dpcd_set_link_settings(link, &lt_settings);
0b226322
DG		 1999
2000 /* 2. perform link training (set link training done
2001 * to false is done as well)
2002 */
64c12b73 2003 lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
0b226322
DG		 2004 if (lt_status == LINK_TRAINING_SUCCESS) {
2005 lt_status = perform_channel_equalization_sequence(link,
64c12b73 2006 &lt_settings,
2007 DPRX);
0b226322
DG		 2008 }
2009
2010 /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
2011 /* 4. print status message*/
2012 print_status_message(link, &lt_settings, lt_status);
2013
2014 return lt_status;
2015}
2016
2017bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
2018{
2019 /* If input parameter is set, shut down phy.
2020 * Still shouldn't turn off dp_receiver (DPCD:600h)
2021 */
2022 if (link_down == true) {
2023 dp_disable_link_phy(link, link->connector_signal);
0b226322 2024 dp_set_fec_ready(link, false);
0b226322
DG		 2025 }
2026
2027 link->sync_lt_in_progress = false;
2028 return true;
2029}
2030
98025a62
NC		 2031bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2032{
2033 if (!max_link_enc_cap) {
2034 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2035 return false;
2036 }
2037
2038 if (link->link_enc->funcs->get_max_link_cap) {
2039 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
2040 return true;
2041 }
2042
2043 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2044 max_link_enc_cap->lane_count = 1;
2045 max_link_enc_cap->link_rate = 6;
2046 return false;
2047}
2048
d0778ebf 2049static struct dc_link_settings get_max_link_cap(struct dc_link *link)
4562236b 2050{
8ccf0e20 2051 struct dc_link_settings max_link_cap = {0};
4562236b 2052
8ccf0e20
WL		 2053 /* get max link encoder capability */
2054 link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
f537d474 2055
4562236b 2056 /* Lower link settings based on sink's link cap */
d0778ebf 2057 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
4562236b 2058 max_link_cap.lane_count =
d0778ebf
HW		 2059 link->reported_link_cap.lane_count;
2060 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
4562236b 2061 max_link_cap.link_rate =
d0778ebf
HW		 2062 link->reported_link_cap.link_rate;
2063 if (link->reported_link_cap.link_spread <
4562236b
HW		 2064 max_link_cap.link_spread)
2065 max_link_cap.link_spread =
d0778ebf 2066 link->reported_link_cap.link_spread;
bad7ab0b 2067 /*
2068 * account for lttpr repeaters cap
2069 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2070 */
3128b285 2071 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
bad7ab0b 2072 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2073 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2074
2075 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2076 max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
460adc6b 2077
2078 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
2079 __func__,
2080 max_link_cap.lane_count,
2081 max_link_cap.link_rate);
bad7ab0b 2082 }
4562236b
HW		 2083 return max_link_cap;
2084}
2085
3083a984 2086enum dc_status read_hpd_rx_irq_data(
1ae62f31
WL		 2087 struct dc_link *link,
2088 union hpd_irq_data *irq_data)
2089{
2090 static enum dc_status retval;
2091
2092 /* The HW reads 16 bytes from 200h on HPD,
2093 * but if we get an AUX_DEFER, the HW cannot retry
2094 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2095 * fail, so we now explicitly read 6 bytes which is
2096 * the req from the above mentioned test cases.
2097 *
2098 * For DP 1.4 we need to read those from 2002h range.
2099 */
2100 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2101 retval = core_link_read_dpcd(
2102 link,
2103 DP_SINK_COUNT,
2104 irq_data->raw,
2105 sizeof(union hpd_irq_data));
2106 else {
2107 /* Read 14 bytes in a single read and then copy only the required fields.
2108 * This is more efficient than doing it in two separate AUX reads. */
2109
2110 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2111
2112 retval = core_link_read_dpcd(
2113 link,
2114 DP_SINK_COUNT_ESI,
2115 tmp,
2116 sizeof(tmp));
2117
2118 if (retval != DC_OK)
2119 return retval;
2120
2121 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2122 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2123 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2124 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2125 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2126 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2127 }
2128
2129 return retval;
2130}
2131
d2aa1356 2132bool hpd_rx_irq_check_link_loss_status(
1ae62f31
WL		 2133 struct dc_link *link,
2134 union hpd_irq_data *hpd_irq_dpcd_data)
2135{
2136 uint8_t irq_reg_rx_power_state = 0;
2137 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2138 union lane_status lane_status;
2139 uint32_t lane;
2140 bool sink_status_changed;
2141 bool return_code;
2142
2143 sink_status_changed = false;
2144 return_code = false;
2145
2146 if (link->cur_link_settings.lane_count == 0)
2147 return return_code;
2148
2149 /*1. Check that Link Status changed, before re-training.*/
2150
2151 /*parse lane status*/
2152 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2153 /* check status of lanes 0,1
2154 * changed DpcdAddress_Lane01Status (0x202)
2155 */
2156 lane_status.raw = get_nibble_at_index(
2157 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2158 lane);
2159
2160 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2161 !lane_status.bits.CR_DONE_0 ||
2162 !lane_status.bits.SYMBOL_LOCKED_0) {
2163 /* if one of the channel equalization, clock
2164 * recovery or symbol lock is dropped
2165 * consider it as (link has been
2166 * dropped) dp sink status has changed
2167 */
2168 sink_status_changed = true;
2169 break;
2170 }
2171 }
2172
2173 /* Check interlane align.*/
2174 if (sink_status_changed ||
2175 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2176
2177 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2178
2179 return_code = true;
2180
2181 /*2. Check that we can handle interrupt: Not in FS DOS,
2182 * Not in "Display Timeout" state, Link is trained.
2183 */
2184 dpcd_result = core_link_read_dpcd(link,
2185 DP_SET_POWER,
2186 &irq_reg_rx_power_state,
2187 sizeof(irq_reg_rx_power_state));
2188
2189 if (dpcd_result != DC_OK) {
2190 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2191 __func__);
2192 } else {
2193 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2194 return_code = false;
2195 }
2196 }
2197
2198 return return_code;
2199}
2200
aafded88 2201bool dp_verify_link_cap(
d0778ebf 2202 struct dc_link *link,
824474ba
BL		 2203 struct dc_link_settings *known_limit_link_setting,
2204 int *fail_count)
4562236b
HW		 2205{
2206 struct dc_link_settings max_link_cap = {0};
820e3935
DW		 2207 struct dc_link_settings cur_link_setting = {0};
2208 struct dc_link_settings *cur = &cur_link_setting;
2209 struct dc_link_settings initial_link_settings = {0};
4562236b
HW		 2210 bool success;
2211 bool skip_link_training;
4562236b 2212 bool skip_video_pattern;
4562236b 2213 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
820e3935 2214 enum link_training_result status;
1ae62f31 2215 union hpd_irq_data irq_data;
4562236b 2216
aafded88
TC		 2217 if (link->dc->debug.skip_detection_link_training) {
2218 link->verified_link_cap = *known_limit_link_setting;
2219 return true;
2220 }
2221
1ae62f31 2222 memset(&irq_data, 0, sizeof(irq_data));
4562236b
HW		 2223 success = false;
2224 skip_link_training = false;
2225
2226 max_link_cap = get_max_link_cap(link);
2227
bad7ab0b 2228 /* Grant extended timeout request */
3128b285 2229 if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
bad7ab0b 2230 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2231
2232 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2233 }
2234
4562236b
HW		 2235 /* TODO implement override and monitor patch later */
2236
2237 /* try to train the link from high to low to
2238 * find the physical link capability
2239 */
2240 /* disable PHY done possible by BIOS, will be done by driver itself */
d0778ebf 2241 dp_disable_link_phy(link, link->connector_signal);
4562236b 2242
b3282738
GS		 2243 dp_cs_id = get_clock_source_id(link);
2244
2245 /* link training starts with the maximum common settings
2246 * supported by both sink and ASIC.
2247 */
2248 initial_link_settings = get_common_supported_link_settings(
2249 *known_limit_link_setting,
2250 max_link_cap);
2251 cur_link_setting = initial_link_settings;
2252
ee765924
GS		 2253 /* Temporary Renoir-specific workaround for SWDEV-215184;
2254 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2255 * so add extra cycle of enabling and disabling the PHY before first link training.
2256 */
2257 if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2258 link->dc->debug.usbc_combo_phy_reset_wa) {
2259 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2260 dp_disable_link_phy(link, link->connector_signal);
2261 }
2262
820e3935 2263 do {
4562236b 2264 skip_video_pattern = true;
820e3935 2265
4562236b
HW		 2266 if (cur->link_rate == LINK_RATE_LOW)
2267 skip_video_pattern = false;
2268
2269 dp_enable_link_phy(
2270 link,
d0778ebf 2271 link->connector_signal,
4562236b
HW		 2272 dp_cs_id,
2273 cur);
2274
94405cf6 2275
4562236b
HW		 2276 if (skip_link_training)
2277 success = true;
2278 else {
820e3935 2279 status = dc_link_dp_perform_link_training(
d0778ebf 2280 link,
4562236b
HW		 2281 cur,
2282 skip_video_pattern);
820e3935
DW		 2283 if (status == LINK_TRAINING_SUCCESS)
2284 success = true;
824474ba
BL		 2285 else
2286 (*fail_count)++;
4562236b
HW		 2287 }
2288
1ae62f31 2289 if (success) {
d0778ebf 2290 link->verified_link_cap = *cur;
1ae62f31
WL		 2291 udelay(1000);
2292 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2293 if (hpd_rx_irq_check_link_loss_status(
2294 link,
2295 &irq_data))
2296 (*fail_count)++;
2297 }
4562236b
HW		 2298 /* always disable the link before trying another
2299 * setting or before returning we'll enable it later
2300 * based on the actual mode we're driving
2301 */
d0778ebf 2302 dp_disable_link_phy(link, link->connector_signal);
820e3935
DW		 2303 } while (!success && decide_fallback_link_setting(
2304 initial_link_settings, cur, status));
4562236b
HW		 2305
2306 /* Link Training failed for all Link Settings
2307 * (Lane Count is still unknown)
2308 */
2309 if (!success) {
2310 /* If all LT fails for all settings,
2311 * set verified = failed safe (1 lane low)
2312 */
d0778ebf
HW		 2313 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2314 link->verified_link_cap.link_rate = LINK_RATE_LOW;
4562236b 2315
d0778ebf 2316 link->verified_link_cap.link_spread =
4562236b
HW		 2317 LINK_SPREAD_DISABLED;
2318 }
2319
4562236b
HW		 2320
2321 return success;
2322}
2323
e7f2c80c
WL		 2324bool dp_verify_link_cap_with_retries(
2325 struct dc_link *link,
2326 struct dc_link_settings *known_limit_link_setting,
2327 int attempts)
2328{
2329 uint8_t i = 0;
2330 bool success = false;
2331
2332 for (i = 0; i < attempts; i++) {
2333 int fail_count = 0;
82db2e3c 2334 enum dc_connection_type type = dc_connection_none;
e7f2c80c
WL		 2335
2336 memset(&link->verified_link_cap, 0,
2337 sizeof(struct dc_link_settings));
82db2e3c
SK		 2338 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2339 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2340 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2341 link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
e7f2c80c
WL		 2342 break;
2343 } else if (dp_verify_link_cap(link,
2344 &link->reported_link_cap,
2345 &fail_count) && fail_count == 0) {
2346 success = true;
2347 break;
2348 }
2349 msleep(10);
2350 }
2351 return success;
2352}
2353
f537d474
LH		 2354bool dp_verify_mst_link_cap(
2355 struct dc_link *link)
2356{
2357 struct dc_link_settings max_link_cap = {0};
2358
2359 max_link_cap = get_max_link_cap(link);
2360 link->verified_link_cap = get_common_supported_link_settings(
2361 link->reported_link_cap,
2362 max_link_cap);
2363
2364 return true;
2365}
2366
9a6a8075 2367static struct dc_link_settings get_common_supported_link_settings(
820e3935
DW		 2368 struct dc_link_settings link_setting_a,
2369 struct dc_link_settings link_setting_b)
2370{
2371 struct dc_link_settings link_settings = {0};
2372
2373 link_settings.lane_count =
2374 (link_setting_a.lane_count <=
2375 link_setting_b.lane_count) ?
2376 link_setting_a.lane_count :
2377 link_setting_b.lane_count;
2378 link_settings.link_rate =
2379 (link_setting_a.link_rate <=
2380 link_setting_b.link_rate) ?
2381 link_setting_a.link_rate :
2382 link_setting_b.link_rate;
2383 link_settings.link_spread = LINK_SPREAD_DISABLED;
2384
2385 /* in DP compliance test, DPR-120 may have
2386 * a random value in its MAX_LINK_BW dpcd field.
2387 * We map it to the maximum supported link rate that
2388 * is smaller than MAX_LINK_BW in this case.
2389 */
2390 if (link_settings.link_rate > LINK_RATE_HIGH3) {
2391 link_settings.link_rate = LINK_RATE_HIGH3;
2392 } else if (link_settings.link_rate < LINK_RATE_HIGH3
2393 && link_settings.link_rate > LINK_RATE_HIGH2) {
2394 link_settings.link_rate = LINK_RATE_HIGH2;
2395 } else if (link_settings.link_rate < LINK_RATE_HIGH2
2396 && link_settings.link_rate > LINK_RATE_HIGH) {
2397 link_settings.link_rate = LINK_RATE_HIGH;
2398 } else if (link_settings.link_rate < LINK_RATE_HIGH
2399 && link_settings.link_rate > LINK_RATE_LOW) {
2400 link_settings.link_rate = LINK_RATE_LOW;
2401 } else if (link_settings.link_rate < LINK_RATE_LOW) {
2402 link_settings.link_rate = LINK_RATE_UNKNOWN;
2403 }
2404
2405 return link_settings;
2406}
2407
450619d3 2408static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 2409{
2410 return lane_count <= LANE_COUNT_ONE;
2411}
2412
450619d3 2413static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 2414{
2415 return link_rate <= LINK_RATE_LOW;
2416}
2417
44858055 2418static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 2419{
2420 switch (lane_count) {
2421 case LANE_COUNT_FOUR:
2422 return LANE_COUNT_TWO;
2423 case LANE_COUNT_TWO:
2424 return LANE_COUNT_ONE;
2425 case LANE_COUNT_ONE:
2426 return LANE_COUNT_UNKNOWN;
2427 default:
2428 return LANE_COUNT_UNKNOWN;
2429 }
2430}
2431
04e21292 2432static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 2433{
2434 switch (link_rate) {
2435 case LINK_RATE_HIGH3:
2436 return LINK_RATE_HIGH2;
2437 case LINK_RATE_HIGH2:
2438 return LINK_RATE_HIGH;
2439 case LINK_RATE_HIGH:
2440 return LINK_RATE_LOW;
2441 case LINK_RATE_LOW:
2442 return LINK_RATE_UNKNOWN;
2443 default:
2444 return LINK_RATE_UNKNOWN;
2445 }
2446}
2447
04e21292 2448static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
8c4abe0b
DW		 2449{
2450 switch (lane_count) {
2451 case LANE_COUNT_ONE:
2452 return LANE_COUNT_TWO;
2453 case LANE_COUNT_TWO:
2454 return LANE_COUNT_FOUR;
2455 default:
2456 return LANE_COUNT_UNKNOWN;
2457 }
2458}
2459
04e21292 2460static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
8c4abe0b
DW		 2461{
2462 switch (link_rate) {
2463 case LINK_RATE_LOW:
2464 return LINK_RATE_HIGH;
2465 case LINK_RATE_HIGH:
2466 return LINK_RATE_HIGH2;
2467 case LINK_RATE_HIGH2:
2468 return LINK_RATE_HIGH3;
2469 default:
2470 return LINK_RATE_UNKNOWN;
2471 }
2472}
2473
820e3935
DW		 2474/*
2475 * function: set link rate and lane count fallback based
2476 * on current link setting and last link training result
2477 * return value:
2478 * true - link setting could be set
2479 * false - has reached minimum setting
2480 * and no further fallback could be done
2481 */
04e21292 2482static bool decide_fallback_link_setting(
820e3935
DW		 2483 struct dc_link_settings initial_link_settings,
2484 struct dc_link_settings *current_link_setting,
2485 enum link_training_result training_result)
2486{
2487 if (!current_link_setting)
2488 return false;
2489
2490 switch (training_result) {
94405cf6
WL		 2491 case LINK_TRAINING_CR_FAIL_LANE0:
2492 case LINK_TRAINING_CR_FAIL_LANE1:
2493 case LINK_TRAINING_CR_FAIL_LANE23:
2494 case LINK_TRAINING_LQA_FAIL:
820e3935
DW		 2495 {
2496 if (!reached_minimum_link_rate
2497 (current_link_setting->link_rate)) {
2498 current_link_setting->link_rate =
2499 reduce_link_rate(
2500 current_link_setting->link_rate);
2501 } else if (!reached_minimum_lane_count
2502 (current_link_setting->lane_count)) {
2503 current_link_setting->link_rate =
2504 initial_link_settings.link_rate;
94405cf6
WL		 2505 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2506 return false;
2507 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2508 current_link_setting->lane_count =
2509 LANE_COUNT_ONE;
2510 else if (training_result ==
2511 LINK_TRAINING_CR_FAIL_LANE23)
2512 current_link_setting->lane_count =
2513 LANE_COUNT_TWO;
2514 else
2515 current_link_setting->lane_count =
2516 reduce_lane_count(
820e3935
DW		 2517 current_link_setting->lane_count);
2518 } else {
2519 return false;
2520 }
2521 break;
2522 }
2523 case LINK_TRAINING_EQ_FAIL_EQ:
2524 {
2525 if (!reached_minimum_lane_count
2526 (current_link_setting->lane_count)) {
2527 current_link_setting->lane_count =
2528 reduce_lane_count(
2529 current_link_setting->lane_count);
2530 } else if (!reached_minimum_link_rate
2531 (current_link_setting->link_rate)) {
820e3935
DW		 2532 current_link_setting->link_rate =
2533 reduce_link_rate(
2534 current_link_setting->link_rate);
2535 } else {
2536 return false;
2537 }
2538 break;
2539 }
2540 case LINK_TRAINING_EQ_FAIL_CR:
2541 {
2542 if (!reached_minimum_link_rate
2543 (current_link_setting->link_rate)) {
2544 current_link_setting->link_rate =
2545 reduce_link_rate(
2546 current_link_setting->link_rate);
2547 } else {
2548 return false;
2549 }
2550 break;
2551 }
2552 default:
2553 return false;
2554 }
2555 return true;
2556}
2557
4562236b 2558bool dp_validate_mode_timing(
d0778ebf 2559 struct dc_link *link,
4562236b
HW		 2560 const struct dc_crtc_timing *timing)
2561{
2562 uint32_t req_bw;
2563 uint32_t max_bw;
2564
2565 const struct dc_link_settings *link_setting;
2566
05e62b6b
GS		 2567 /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2568 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2569 !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2570 dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2571 return false;
2572
4562236b 2573 /*always DP fail safe mode*/
380604e2 2574 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
9a6a8075
HW		 2575 timing->h_addressable == (uint32_t) 640 &&
2576 timing->v_addressable == (uint32_t) 480)
4562236b
HW		 2577 return true;
2578
5ac4619b 2579 link_setting = dc_link_get_link_cap(link);
4562236b
HW		 2580
2581 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2582 /*if (flags.DYNAMIC_VALIDATION == 1 &&
d0778ebf
HW		 2583 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2584 link_setting = &link->verified_link_cap;
4562236b
HW		 2585 */
2586
e49f6936 2587 req_bw = dc_bandwidth_in_kbps_from_timing(timing);
332c1191 2588 max_bw = dc_link_bandwidth_kbps(link, link_setting);
4562236b
HW		 2589
2590 if (req_bw <= max_bw) {
2591 /* remember the biggest mode here, during
2592 * initial link training (to get
2593 * verified_link_cap), LS sends event about
2594 * cannot train at reported cap to upper
2595 * layer and upper layer will re-enumerate modes.
2596 * this is not necessary if the lower
2597 * verified_link_cap is enough to drive
2598 * all the modes */
2599
2600 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2601 /* if (flags.DYNAMIC_VALIDATION == 1)
2602 dpsst->max_req_bw_for_verified_linkcap = dal_max(
2603 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2604 return true;
2605 } else
2606 return false;
2607}
2608
8628d02f 2609static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
4562236b 2610{
8c4abe0b 2611 struct dc_link_settings initial_link_setting = {
8628d02f 2612 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
8c4abe0b
DW		 2613 struct dc_link_settings current_link_setting =
2614 initial_link_setting;
4562236b 2615 uint32_t link_bw;
4562236b 2616
69d5c7f3
BG		 2617 if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2618 return false;
2619
8628d02f
JP		 2620 /* search for the minimum link setting that:
2621 * 1. is supported according to the link training result
2622 * 2. could support the b/w requested by the timing
4562236b 2623 */
8628d02f
JP		 2624 while (current_link_setting.link_rate <=
2625 link->verified_link_cap.link_rate) {
332c1191
NC		 2626 link_bw = dc_link_bandwidth_kbps(
2627 link,
8628d02f
JP		 2628 &current_link_setting);
2629 if (req_bw <= link_bw) {
2630 *link_setting = current_link_setting;
2631 return true;
2632 }
4562236b 2633
8628d02f
JP		 2634 if (current_link_setting.lane_count <
2635 link->verified_link_cap.lane_count) {
2636 current_link_setting.lane_count =
2637 increase_lane_count(
2638 current_link_setting.lane_count);
2639 } else {
2640 current_link_setting.link_rate =
2641 increase_link_rate(
2642 current_link_setting.link_rate);
2643 current_link_setting.lane_count =
2644 initial_link_setting.lane_count;
2645 }
3f1f74f4
JZ		 2646 }
2647
8628d02f
JP		 2648 return false;
2649}
2650
8efd0f5a 2651bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
8628d02f
JP		 2652{
2653 struct dc_link_settings initial_link_setting;
2654 struct dc_link_settings current_link_setting;
2655 uint32_t link_bw;
2656
67c268a5
ZL		 2657 /*
2658 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2659 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2660 */
2661 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
53c81fc7 2662 link->dpcd_caps.edp_supported_link_rates_count == 0) {
4d2f22d1 2663 *link_setting = link->verified_link_cap;
8628d02f 2664 return true;
4d2f22d1
HH		 2665 }
2666
8628d02f
JP		 2667 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2668 initial_link_setting.lane_count = LANE_COUNT_ONE;
2669 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2670 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2671 initial_link_setting.use_link_rate_set = true;
2672 initial_link_setting.link_rate_set = 0;
2673 current_link_setting = initial_link_setting;
2674
5667ff5c
DA		 2675 /* search for the minimum link setting that:
2676 * 1. is supported according to the link training result
2677 * 2. could support the b/w requested by the timing
2678 */
8c4abe0b 2679 while (current_link_setting.link_rate <=
4654a2f7 2680 link->verified_link_cap.link_rate) {
332c1191
NC		 2681 link_bw = dc_link_bandwidth_kbps(
2682 link,
8c4abe0b
DW		 2683 &current_link_setting);
2684 if (req_bw <= link_bw) {
2685 *link_setting = current_link_setting;
8628d02f 2686 return true;
4562236b 2687 }
4562236b 2688
8c4abe0b 2689 if (current_link_setting.lane_count <
4654a2f7 2690 link->verified_link_cap.lane_count) {
8c4abe0b
DW		 2691 current_link_setting.lane_count =
2692 increase_lane_count(
2693 current_link_setting.lane_count);
2694 } else {
8628d02f
JP		 2695 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2696 current_link_setting.link_rate_set++;
2697 current_link_setting.link_rate =
2698 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2699 current_link_setting.lane_count =
2700 initial_link_setting.lane_count;
2701 } else
2702 break;
4562236b
HW		 2703 }
2704 }
8628d02f
JP		 2705 return false;
2706}
2707
c08321cb
WL		 2708static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2709{
2710 *link_setting = link->verified_link_cap;
2711 return true;
2712}
2713
8628d02f
JP		 2714void decide_link_settings(struct dc_stream_state *stream,
2715 struct dc_link_settings *link_setting)
2716{
2717 struct dc_link *link;
2718 uint32_t req_bw;
2719
e49f6936 2720 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
8628d02f
JP		 2721
2722 link = stream->link;
2723
2724 /* if preferred is specified through AMDDP, use it, if it's enough
2725 * to drive the mode
2726 */
2727 if (link->preferred_link_setting.lane_count !=
2728 LANE_COUNT_UNKNOWN &&
2729 link->preferred_link_setting.link_rate !=
2730 LINK_RATE_UNKNOWN) {
2731 *link_setting = link->preferred_link_setting;
2732 return;
2733 }
2734
2735 /* MST doesn't perform link training for now
2736 * TODO: add MST specific link training routine
2737 */
2738 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
c08321cb
WL		 2739 if (decide_mst_link_settings(link, link_setting))
2740 return;
2741 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
8628d02f
JP		 2742 if (decide_edp_link_settings(link, link_setting, req_bw))
2743 return;
2744 } else if (decide_dp_link_settings(link, link_setting, req_bw))
2745 return;
4562236b
HW		 2746
2747 BREAK_TO_DEBUGGER();
d0778ebf 2748 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
4562236b 2749
d0778ebf 2750 *link_setting = link->verified_link_cap;
4562236b
HW		 2751}
2752
2753/*************************Short Pulse IRQ***************************/
d0778ebf 2754static bool allow_hpd_rx_irq(const struct dc_link *link)
4562236b
HW		 2755{
2756 /*
2757 * Don't handle RX IRQ unless one of following is met:
2758 * 1) The link is established (cur_link_settings != unknown)
36c9137b 2759 * 2) We know we're dealing with a branch device, SST or MST
4562236b
HW		 2760 */
2761
d0778ebf 2762 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
36c9137b 2763 is_dp_branch_device(link))
4562236b
HW		 2764 return true;
2765
2766 return false;
2767}
2768
ab4a4072 2769static bool handle_hpd_irq_psr_sink(struct dc_link *link)
4562236b
HW		 2770{
2771 union dpcd_psr_configuration psr_configuration;
2772
d1ebfdd8 2773 if (!link->psr_settings.psr_feature_enabled)
4562236b
HW		 2774 return false;
2775
7c7f5b15
AG		 2776 dm_helpers_dp_read_dpcd(
2777 link->ctx,
d0778ebf 2778 link,
7c7f5b15
AG		 2779 368,/*DpcdAddress_PSR_Enable_Cfg*/
2780 &psr_configuration.raw,
2781 sizeof(psr_configuration.raw));
2782
4562236b
HW		 2783
2784 if (psr_configuration.bits.ENABLE) {
2785 unsigned char dpcdbuf[3] = {0};
2786 union psr_error_status psr_error_status;
2787 union psr_sink_psr_status psr_sink_psr_status;
2788
7c7f5b15
AG		 2789 dm_helpers_dp_read_dpcd(
2790 link->ctx,
d0778ebf 2791 link,
7c7f5b15
AG		 2792 0x2006, /*DpcdAddress_PSR_Error_Status*/
2793 (unsigned char *) dpcdbuf,
2794 sizeof(dpcdbuf));
4562236b
HW		 2795
2796 /*DPCD 2006h ERROR STATUS*/
2797 psr_error_status.raw = dpcdbuf[0];
2798 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
2799 psr_sink_psr_status.raw = dpcdbuf[2];
2800
2801 if (psr_error_status.bits.LINK_CRC_ERROR ||
63c954a1
WW		 2802 psr_error_status.bits.RFB_STORAGE_ERROR ||
2803 psr_error_status.bits.VSC_SDP_ERROR) {
4562236b 2804 /* Acknowledge and clear error bits */
7c7f5b15
AG		 2805 dm_helpers_dp_write_dpcd(
2806 link->ctx,
d0778ebf 2807 link,
7c7f5b15 2808 8198,/*DpcdAddress_PSR_Error_Status*/
4562236b
HW		 2809 &psr_error_status.raw,
2810 sizeof(psr_error_status.raw));
2811
2812 /* PSR error, disable and re-enable PSR */
1d496907
KK		 2813 dc_link_set_psr_allow_active(link, false, true, false);
2814 dc_link_set_psr_allow_active(link, true, true, false);
4562236b
HW		 2815
2816 return true;
2817 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2818 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2819 /* No error is detect, PSR is active.
2820 * We should return with IRQ_HPD handled without
2821 * checking for loss of sync since PSR would have
2822 * powered down main link.
2823 */
2824 return true;
2825 }
2826 }
2827 return false;
2828}
2829
d0778ebf 2830static void dp_test_send_link_training(struct dc_link *link)
4562236b 2831{
73c72602 2832 struct dc_link_settings link_settings = {0};
4562236b
HW		 2833
2834 core_link_read_dpcd(
2835 link,
3a340294 2836 DP_TEST_LANE_COUNT,
4562236b
HW		 2837 (unsigned char *)(&link_settings.lane_count),
2838 1);
2839 core_link_read_dpcd(
2840 link,
3a340294 2841 DP_TEST_LINK_RATE,
4562236b
HW		 2842 (unsigned char *)(&link_settings.link_rate),
2843 1);
2844
2845 /* Set preferred link settings */
d0778ebf
HW		 2846 link->verified_link_cap.lane_count = link_settings.lane_count;
2847 link->verified_link_cap.link_rate = link_settings.link_rate;
4562236b 2848
73c72602 2849 dp_retrain_link_dp_test(link, &link_settings, false);
4562236b
HW		 2850}
2851
9315e239 2852/* TODO Raven hbr2 compliance eye output is unstable
25bab0da
WL		 2853 * (toggling on and off) with debugger break
2854 * This caueses intermittent PHY automation failure
2855 * Need to look into the root cause */
d0778ebf 2856static void dp_test_send_phy_test_pattern(struct dc_link *link)
4562236b
HW		 2857{
2858 union phy_test_pattern dpcd_test_pattern;
2859 union lane_adjust dpcd_lane_adjustment[2];
2860 unsigned char dpcd_post_cursor_2_adjustment = 0;
5e9ff159 2861 unsigned char test_pattern_buffer[
3a340294
DA		 2862 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2863 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
5e9ff159 2864 unsigned int test_pattern_size = 0;
4562236b
HW		 2865 enum dp_test_pattern test_pattern;
2866 struct dc_link_training_settings link_settings;
2867 union lane_adjust dpcd_lane_adjust;
2868 unsigned int lane;
2869 struct link_training_settings link_training_settings;
2870 int i = 0;
2871
2872 dpcd_test_pattern.raw = 0;
2873 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2874 memset(&link_settings, 0, sizeof(link_settings));
2875
2876 /* get phy test pattern and pattern parameters from DP receiver */
2877 core_link_read_dpcd(
2878 link,
8811d9eb 2879 DP_PHY_TEST_PATTERN,
4562236b
HW		 2880 &dpcd_test_pattern.raw,
2881 sizeof(dpcd_test_pattern));
2882 core_link_read_dpcd(
2883 link,
3a340294 2884 DP_ADJUST_REQUEST_LANE0_1,
4562236b
HW		 2885 &dpcd_lane_adjustment[0].raw,
2886 sizeof(dpcd_lane_adjustment));
2887
2888 /*get post cursor 2 parameters
2889 * For DP 1.1a or eariler, this DPCD register's value is 0
2890 * For DP 1.2 or later:
2891 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2892 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2893 */
2894 core_link_read_dpcd(
2895 link,
3a340294 2896 DP_ADJUST_REQUEST_POST_CURSOR2,
4562236b
HW		 2897 &dpcd_post_cursor_2_adjustment,
2898 sizeof(dpcd_post_cursor_2_adjustment));
2899
2900 /* translate request */
2901 switch (dpcd_test_pattern.bits.PATTERN) {
2902 case PHY_TEST_PATTERN_D10_2:
2903 test_pattern = DP_TEST_PATTERN_D102;
0e19401f 2904 break;
4562236b
HW		 2905 case PHY_TEST_PATTERN_SYMBOL_ERROR:
2906 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 2907 break;
4562236b
HW		 2908 case PHY_TEST_PATTERN_PRBS7:
2909 test_pattern = DP_TEST_PATTERN_PRBS7;
0e19401f 2910 break;
4562236b
HW		 2911 case PHY_TEST_PATTERN_80BIT_CUSTOM:
2912 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 2913 break;
2914 case PHY_TEST_PATTERN_CP2520_1:
25bab0da 2915 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 2916 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 2917 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2918 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 2919 break;
2920 case PHY_TEST_PATTERN_CP2520_2:
25bab0da 2921 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 2922 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 2923 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2924 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 2925 break;
2926 case PHY_TEST_PATTERN_CP2520_3:
78e685f9 2927 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
0e19401f 2928 break;
4562236b
HW		 2929 default:
2930 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2931 break;
2932 }
2933
5e9ff159
GS		 2934 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2935 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2936 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
4562236b
HW		 2937 core_link_read_dpcd(
2938 link,
3a340294 2939 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
5e9ff159
GS		 2940 test_pattern_buffer,
2941 test_pattern_size);
2942 }
4562236b
HW		 2943
2944 /* prepare link training settings */
d0778ebf 2945 link_settings.link = link->cur_link_settings;
4562236b
HW		 2946
2947 for (lane = 0; lane <
d0778ebf 2948 (unsigned int)(link->cur_link_settings.lane_count);
4562236b
HW		 2949 lane++) {
2950 dpcd_lane_adjust.raw =
2951 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2952 link_settings.lane_settings[lane].VOLTAGE_SWING =
2953 (enum dc_voltage_swing)
2954 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2955 link_settings.lane_settings[lane].PRE_EMPHASIS =
2956 (enum dc_pre_emphasis)
2957 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2958 link_settings.lane_settings[lane].POST_CURSOR2 =
2959 (enum dc_post_cursor2)
2960 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2961 }
2962
2963 for (i = 0; i < 4; i++)
2964 link_training_settings.lane_settings[i] =
2965 link_settings.lane_settings[i];
2966 link_training_settings.link_settings = link_settings.link;
2967 link_training_settings.allow_invalid_msa_timing_param = false;
2968 /*Usage: Measure DP physical lane signal
2969 * by DP SI test equipment automatically.
2970 * PHY test pattern request is generated by equipment via HPD interrupt.
2971 * HPD needs to be active all the time. HPD should be active
2972 * all the time. Do not touch it.
2973 * forward request to DS
2974 */
2975 dc_link_dp_set_test_pattern(
d0778ebf 2976 link,
4562236b 2977 test_pattern,
2057b7e1 2978 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
4562236b 2979 &link_training_settings,
5e9ff159
GS		 2980 test_pattern_buffer,
2981 test_pattern_size);
4562236b
HW		 2982}
2983
d0778ebf 2984static void dp_test_send_link_test_pattern(struct dc_link *link)
4562236b
HW		 2985{
2986 union link_test_pattern dpcd_test_pattern;
2987 union test_misc dpcd_test_params;
2988 enum dp_test_pattern test_pattern;
2057b7e1
WL		 2989 enum dp_test_pattern_color_space test_pattern_color_space =
2990 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
ac3a4fa1
QZ		 2991 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2992 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2993 struct pipe_ctx *pipe_ctx = NULL;
2994 int i;
4562236b
HW		 2995
2996 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2997 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2998
ac3a4fa1
QZ		 2999 for (i = 0; i < MAX_PIPES; i++) {
3000 if (pipes[i].stream == NULL)
3001 continue;
3002
3003 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
3004 pipe_ctx = &pipes[i];
3005 break;
3006 }
3007 }
3008
3009 if (pipe_ctx == NULL)
3010 return;
3011
4562236b
HW		 3012 /* get link test pattern and pattern parameters */
3013 core_link_read_dpcd(
3014 link,
3a340294 3015 DP_TEST_PATTERN,
4562236b
HW		 3016 &dpcd_test_pattern.raw,
3017 sizeof(dpcd_test_pattern));
3018 core_link_read_dpcd(
3019 link,
3a340294 3020 DP_TEST_MISC0,
4562236b
HW		 3021 &dpcd_test_params.raw,
3022 sizeof(dpcd_test_params));
3023
3024 switch (dpcd_test_pattern.bits.PATTERN) {
3025 case LINK_TEST_PATTERN_COLOR_RAMP:
3026 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
3027 break;
3028 case LINK_TEST_PATTERN_VERTICAL_BARS:
3029 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
3030 break; /* black and white */
3031 case LINK_TEST_PATTERN_COLOR_SQUARES:
3032 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
3033 TEST_DYN_RANGE_VESA ?
3034 DP_TEST_PATTERN_COLOR_SQUARES :
3035 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
3036 break;
3037 default:
3038 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3039 break;
3040 }
3041
ef65c702
JFZ		 3042 if (dpcd_test_params.bits.CLR_FORMAT == 0)
3043 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
3044 else
3045 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
3046 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
3047 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2057b7e1 3048
ac3a4fa1
QZ		 3049 switch (dpcd_test_params.bits.BPC) {
3050 case 0: // 6 bits
3051 requestColorDepth = COLOR_DEPTH_666;
3052 break;
3053 case 1: // 8 bits
3054 requestColorDepth = COLOR_DEPTH_888;
3055 break;
3056 case 2: // 10 bits
3057 requestColorDepth = COLOR_DEPTH_101010;
3058 break;
3059 case 3: // 12 bits
3060 requestColorDepth = COLOR_DEPTH_121212;
3061 break;
3062 default:
3063 break;
3064 }
3065
98ad74c6
IB		 3066 switch (dpcd_test_params.bits.CLR_FORMAT) {
3067 case 0:
3068 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3069 break;
3070 case 1:
3071 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
3072 break;
3073 case 2:
3074 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
3075 break;
3076 default:
3077 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3078 break;
3079 }
3080
3081
ac3a4fa1
QZ		 3082 if (requestColorDepth != COLOR_DEPTH_UNDEFINED
3083 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
92589020
QZ		 3084 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
3085 __func__,
3086 pipe_ctx->stream->timing.display_color_depth,
3087 requestColorDepth);
ac3a4fa1 3088 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
ac3a4fa1
QZ		 3089 }
3090
98ad74c6
IB		 3091 dp_update_dsc_config(pipe_ctx);
3092
4562236b 3093 dc_link_dp_set_test_pattern(
d0778ebf 3094 link,
4562236b 3095 test_pattern,
2057b7e1 3096 test_pattern_color_space,
4562236b
HW		 3097 NULL,
3098 NULL,
3099 0);
3100}
3101
8c8048f2 3102static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3103{
3104 union audio_test_mode dpcd_test_mode = {0};
3105 struct audio_test_pattern_type dpcd_pattern_type = {0};
3106 union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3107 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3108
3109 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3110 struct pipe_ctx *pipe_ctx = &pipes[0];
3111 unsigned int channel_count;
3112 unsigned int channel = 0;
3113 unsigned int modes = 0;
3114 unsigned int sampling_rate_in_hz = 0;
3115
3116 // get audio test mode and test pattern parameters
3117 core_link_read_dpcd(
3118 link,
3119 DP_TEST_AUDIO_MODE,
3120 &dpcd_test_mode.raw,
3121 sizeof(dpcd_test_mode));
3122
3123 core_link_read_dpcd(
3124 link,
3125 DP_TEST_AUDIO_PATTERN_TYPE,
3126 &dpcd_pattern_type.value,
3127 sizeof(dpcd_pattern_type));
3128
3129 channel_count = dpcd_test_mode.bits.channel_count + 1;
3130
3131 // read pattern periods for requested channels when sawTooth pattern is requested
3132 if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3133 dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3134
3135 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3136 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3137 // read period for each channel
3138 for (channel = 0; channel < channel_count; channel++) {
3139 core_link_read_dpcd(
3140 link,
3141 DP_TEST_AUDIO_PERIOD_CH1 + channel,
3142 &dpcd_pattern_period[channel].raw,
3143 sizeof(dpcd_pattern_period[channel]));
3144 }
3145 }
3146
3147 // translate sampling rate
3148 switch (dpcd_test_mode.bits.sampling_rate) {
3149 case AUDIO_SAMPLING_RATE_32KHZ:
3150 sampling_rate_in_hz = 32000;
3151 break;
3152 case AUDIO_SAMPLING_RATE_44_1KHZ:
3153 sampling_rate_in_hz = 44100;
3154 break;
3155 case AUDIO_SAMPLING_RATE_48KHZ:
3156 sampling_rate_in_hz = 48000;
3157 break;
3158 case AUDIO_SAMPLING_RATE_88_2KHZ:
3159 sampling_rate_in_hz = 88200;
3160 break;
3161 case AUDIO_SAMPLING_RATE_96KHZ:
3162 sampling_rate_in_hz = 96000;
3163 break;
3164 case AUDIO_SAMPLING_RATE_176_4KHZ:
3165 sampling_rate_in_hz = 176400;
3166 break;
3167 case AUDIO_SAMPLING_RATE_192KHZ:
3168 sampling_rate_in_hz = 192000;
3169 break;
3170 default:
3171 sampling_rate_in_hz = 0;
3172 break;
3173 }
3174
3175 link->audio_test_data.flags.test_requested = 1;
3176 link->audio_test_data.flags.disable_video = disable_video;
3177 link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3178 link->audio_test_data.channel_count = channel_count;
3179 link->audio_test_data.pattern_type = test_pattern;
3180
3181 if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3182 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3183 link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3184 }
3185 }
3186}
3187
d0778ebf 3188static void handle_automated_test(struct dc_link *link)
4562236b
HW		 3189{
3190 union test_request test_request;
3191 union test_response test_response;
3192
3193 memset(&test_request, 0, sizeof(test_request));
3194 memset(&test_response, 0, sizeof(test_response));
3195
3196 core_link_read_dpcd(
3197 link,
3a340294 3198 DP_TEST_REQUEST,
4562236b
HW		 3199 &test_request.raw,
3200 sizeof(union test_request));
3201 if (test_request.bits.LINK_TRAINING) {
3202 /* ACK first to let DP RX test box monitor LT sequence */
3203 test_response.bits.ACK = 1;
3204 core_link_write_dpcd(
3205 link,
3a340294 3206 DP_TEST_RESPONSE,
4562236b
HW		 3207 &test_response.raw,
3208 sizeof(test_response));
3209 dp_test_send_link_training(link);
3210 /* no acknowledge request is needed again */
3211 test_response.bits.ACK = 0;
3212 }
3213 if (test_request.bits.LINK_TEST_PATTRN) {
3214 dp_test_send_link_test_pattern(link);
75a74755 3215 test_response.bits.ACK = 1;
4562236b 3216 }
8c8048f2 3217
3218 if (test_request.bits.AUDIO_TEST_PATTERN) {
3219 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3220 test_response.bits.ACK = 1;
3221 }
3222
4562236b
HW		 3223 if (test_request.bits.PHY_TEST_PATTERN) {
3224 dp_test_send_phy_test_pattern(link);
3225 test_response.bits.ACK = 1;
3226 }
a6729a5a 3227
4562236b
HW		 3228 /* send request acknowledgment */
3229 if (test_response.bits.ACK)
3230 core_link_write_dpcd(
3231 link,
3a340294 3232 DP_TEST_RESPONSE,
4562236b
HW		 3233 &test_response.raw,
3234 sizeof(test_response));
3235}
3236
4e18814e 3237bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
4562236b 3238{
9a6a8075 3239 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
c2e218dd 3240 union device_service_irq device_service_clear = { { 0 } };
d6258eaa 3241 enum dc_status result;
4562236b 3242 bool status = false;
48af9b91
AL		 3243 struct pipe_ctx *pipe_ctx;
3244 int i;
4e18814e
FD		 3245
3246 if (out_link_loss)
3247 *out_link_loss = false;
4562236b
HW		 3248 /* For use cases related to down stream connection status change,
3249 * PSR and device auto test, refer to function handle_sst_hpd_irq
3250 * in DAL2.1*/
3251
1296423b 3252 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
d0778ebf 3253 __func__, link->link_index);
4562236b 3254
8ee65d7c 3255
4562236b
HW		 3256 /* All the "handle_hpd_irq_xxx()" methods
3257 * should be called only after
3258 * dal_dpsst_ls_read_hpd_irq_data
3259 * Order of calls is important too
3260 */
3261 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
8ee65d7c
WL		 3262 if (out_hpd_irq_dpcd_data)
3263 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4562236b
HW		 3264
3265 if (result != DC_OK) {
1296423b 3266 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
4562236b
HW		 3267 __func__);
3268 return false;
3269 }
3270
3271 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3272 device_service_clear.bits.AUTOMATED_TEST = 1;
3273 core_link_write_dpcd(
3274 link,
3a340294 3275 DP_DEVICE_SERVICE_IRQ_VECTOR,
4562236b
HW		 3276 &device_service_clear.raw,
3277 sizeof(device_service_clear.raw));
3278 device_service_clear.raw = 0;
3279 handle_automated_test(link);
3280 return false;
3281 }
3282
3283 if (!allow_hpd_rx_irq(link)) {
1296423b 3284 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
d0778ebf 3285 __func__, link->link_index);
4562236b
HW		 3286 return false;
3287 }
3288
3289 if (handle_hpd_irq_psr_sink(link))
3290 /* PSR-related error was detected and handled */
3291 return true;
3292
3293 /* If PSR-related error handled, Main link may be off,
3294 * so do not handle as a normal sink status change interrupt.
3295 */
3296
aaa15026
WL		 3297 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3298 return true;
3299
4562236b 3300 /* check if we have MST msg and return since we poll for it */
aaa15026 3301 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
4562236b
HW		 3302 return false;
3303
3304 /* For now we only handle 'Downstream port status' case.
3305 * If we got sink count changed it means
3306 * Downstream port status changed,
e97ed496
AK		 3307 * then DM should call DC to do the detection.
3308 * NOTE: Do not handle link loss on eDP since it is internal link*/
3309 if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3310 hpd_rx_irq_check_link_loss_status(
3311 link,
3312 &hpd_irq_dpcd_data)) {
4562236b
HW		 3313 /* Connectivity log: link loss */
3314 CONN_DATA_LINK_LOSS(link,
3315 hpd_irq_dpcd_data.raw,
3316 sizeof(hpd_irq_dpcd_data),
3317 "Status: ");
3318
48af9b91
AL		 3319 for (i = 0; i < MAX_PIPES; i++) {
3320 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
832aa63b
PH		 3321 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3322 break;
3323 }
3324
3325 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3326 return false;
3327
832aa63b 3328
68423dab
AC		 3329 for (i = 0; i < MAX_PIPES; i++) {
3330 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3331 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
617ab854 3332 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
68423dab
AC		 3333 core_link_disable_stream(pipe_ctx);
3334 }
48af9b91 3335
422d9091
XY		 3336 for (i = 0; i < MAX_PIPES; i++) {
3337 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
68423dab 3338 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
617ab854 3339 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
68423dab 3340 core_link_enable_stream(link->dc->current_state, pipe_ctx);
422d9091
XY		 3341 }
3342
4562236b 3343 status = false;
4e18814e
FD		 3344 if (out_link_loss)
3345 *out_link_loss = true;
4562236b
HW		 3346 }
3347
36c9137b 3348 if (link->type == dc_connection_sst_branch &&
4562236b
HW		 3349 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3350 != link->dpcd_sink_count)
3351 status = true;
3352
3353 /* reasons for HPD RX:
3354 * 1. Link Loss - ie Re-train the Link
3355 * 2. MST sideband message
3356 * 3. Automated Test - ie. Internal Commit
3357 * 4. CP (copy protection) - (not interesting for DM???)
3358 * 5. DRR
3359 * 6. Downstream Port status changed
3360 * -ie. Detect - this the only one
3361 * which is interesting for DM because
3362 * it must call dc_link_detect.
3363 */
3364 return status;
3365}
3366
3367/*query dpcd for version and mst cap addresses*/
d0778ebf 3368bool is_mst_supported(struct dc_link *link)
4562236b
HW		 3369{
3370 bool mst = false;
3371 enum dc_status st = DC_OK;
3372 union dpcd_rev rev;
3373 union mstm_cap cap;
3374
0b226322
DG		 3375 if (link->preferred_training_settings.mst_enable &&
3376 *link->preferred_training_settings.mst_enable == false) {
3377 return false;
3378 }
3379
4562236b
HW		 3380 rev.raw = 0;
3381 cap.raw = 0;
3382
3a340294 3383 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4562236b
HW		 3384 sizeof(rev));
3385
3386 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3387
3a340294 3388 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4562236b
HW		 3389 &cap.raw, sizeof(cap));
3390 if (st == DC_OK && cap.bits.MST_CAP == 1)
3391 mst = true;
3392 }
3393 return mst;
3394
3395}
3396
d0778ebf 3397bool is_dp_active_dongle(const struct dc_link *link)
36c9137b
DZ		 3398{
3399 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3400 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3401}
3402
3403bool is_dp_branch_device(const struct dc_link *link)
4562236b 3404{
a504ad26 3405 return link->dpcd_caps.is_branch_dev;
4562236b
HW		 3406}
3407
6bffebc9
EY		 3408static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3409{
3410 switch (bpc) {
3411 case DOWN_STREAM_MAX_8BPC:
3412 return 8;
3413 case DOWN_STREAM_MAX_10BPC:
3414 return 10;
3415 case DOWN_STREAM_MAX_12BPC:
3416 return 12;
3417 case DOWN_STREAM_MAX_16BPC:
3418 return 16;
3419 default:
3420 break;
3421 }
3422
3423 return -1;
3424}
3425
ee13cea9
JB		 3426static void read_dp_device_vendor_id(struct dc_link *link)
3427{
3428 struct dp_device_vendor_id dp_id;
3429
3430 /* read IEEE branch device id */
3431 core_link_read_dpcd(
3432 link,
3433 DP_BRANCH_OUI,
3434 (uint8_t *)&dp_id,
3435 sizeof(dp_id));
3436
3437 link->dpcd_caps.branch_dev_id =
3438 (dp_id.ieee_oui[0] << 16) +
3439 (dp_id.ieee_oui[1] << 8) +
3440 dp_id.ieee_oui[2];
3441
3442 memmove(
3443 link->dpcd_caps.branch_dev_name,
3444 dp_id.ieee_device_id,
3445 sizeof(dp_id.ieee_device_id));
3446}
3447
3448
3449
4562236b 3450static void get_active_converter_info(
d0778ebf 3451 uint8_t data, struct dc_link *link)
4562236b
HW		 3452{
3453 union dp_downstream_port_present ds_port = { .byte = data };
dd998291 3454 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
4562236b
HW		 3455
3456 /* decode converter info*/
3457 if (!ds_port.fields.PORT_PRESENT) {
3458 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
d0778ebf 3459 ddc_service_set_dongle_type(link->ddc,
4562236b 3460 link->dpcd_caps.dongle_type);
ac3d76e0 3461 link->dpcd_caps.is_branch_dev = false;
4562236b
HW		 3462 return;
3463 }
3464
a504ad26 3465 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
9413b23f 3466 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
a504ad26 3467
4562236b
HW		 3468 switch (ds_port.fields.PORT_TYPE) {
3469 case DOWNSTREAM_VGA:
3470 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3471 break;
7a83645a
DZ		 3472 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3473 /* At this point we don't know is it DVI or HDMI or DP++,
4562236b
HW		 3474 * assume DVI.*/
3475 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3476 break;
3477 default:
3478 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3479 break;
3480 }
3481
ac0e562c 3482 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
242b0c8f 3483 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
4562236b
HW		 3484 union dwnstream_port_caps_byte0 *port_caps =
3485 (union dwnstream_port_caps_byte0 *)det_caps;
5aedc7bc 3486 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3487 det_caps, sizeof(det_caps)) == DC_OK) {
4562236b 3488
5aedc7bc 3489 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3490 /*Handle DP case as DONGLE_NONE*/
3491 case DOWN_STREAM_DETAILED_DP:
3492 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3493 break;
3494 case DOWN_STREAM_DETAILED_VGA:
3495 link->dpcd_caps.dongle_type =
3496 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3497 break;
3498 case DOWN_STREAM_DETAILED_DVI:
3499 link->dpcd_caps.dongle_type =
3500 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3501 break;
3502 case DOWN_STREAM_DETAILED_HDMI:
3503 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3504 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3505 link->dpcd_caps.dongle_type =
3506 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3507
3508 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3509 if (ds_port.fields.DETAILED_CAPS) {
3510
3511 union dwnstream_port_caps_byte3_hdmi
3512 hdmi_caps = {.raw = det_caps[3] };
3513 union dwnstream_port_caps_byte2
3514 hdmi_color_caps = {.raw = det_caps[2] };
3515 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3516 det_caps[1] * 2500;
3517
3518 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3519 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3520 /*YCBCR capability only for HDMI case*/
3521 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3522 == DOWN_STREAM_DETAILED_HDMI) {
3523 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3524 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3525 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3526 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3527 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3528 hdmi_caps.bits.YCrCr422_CONVERSION;
3529 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3530 hdmi_caps.bits.YCrCr420_CONVERSION;
3531 }
3532
3533 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3534 translate_dpcd_max_bpc(
3535 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3536
3537 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3538 link->dpcd_caps.dongle_caps.extendedCapValid = true;
7a83645a 3539 }
03f5c686 3540
5aedc7bc 3541 break;
4562236b 3542 }
4562236b
HW		 3543 }
3544 }
3545
d0778ebf 3546 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4562236b 3547
4562236b
HW		 3548 {
3549 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3550
3551 core_link_read_dpcd(
3552 link,
3a340294 3553 DP_BRANCH_REVISION_START,
4562236b
HW		 3554 (uint8_t *)&dp_hw_fw_revision,
3555 sizeof(dp_hw_fw_revision));
3556
3557 link->dpcd_caps.branch_hw_revision =
3558 dp_hw_fw_revision.ieee_hw_rev;
4b99affb
A		 3559
3560 memmove(
3561 link->dpcd_caps.branch_fw_revision,
3562 dp_hw_fw_revision.ieee_fw_rev,
3563 sizeof(dp_hw_fw_revision.ieee_fw_rev));
4562236b
HW		 3564 }
3565}
3566
d0778ebf 3567static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4562236b
HW		 3568 int length)
3569{
3570 int retry = 0;
4562236b
HW		 3571
3572 if (!link->dpcd_caps.dpcd_rev.raw) {
3573 do {
3574 dp_receiver_power_ctrl(link, true);
3a340294 3575 core_link_read_dpcd(link, DP_DPCD_REV,
4562236b
HW		 3576 dpcd_data, length);
3577 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3a340294
DA		 3578 DP_DPCD_REV -
3579 DP_DPCD_REV];
4562236b
HW		 3580 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3581 }
3582
4562236b
HW		 3583 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3584 switch (link->dpcd_caps.branch_dev_id) {
df3b7e32 3585 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
4562236b
HW		 3586 * all internal circuits including AUX communication preventing
3587 * reading DPCD table and EDID (spec violation).
3588 * Encoder will skip DP RX power down on disable_output to
3589 * keep receiver powered all the time.*/
df3b7e32
QZ		 3590 case DP_BRANCH_DEVICE_ID_0010FA:
3591 case DP_BRANCH_DEVICE_ID_0080E1:
566b4252 3592 case DP_BRANCH_DEVICE_ID_00E04C:
4562236b
HW		 3593 link->wa_flags.dp_keep_receiver_powered = true;
3594 break;
3595
3596 /* TODO: May need work around for other dongles. */
3597 default:
3598 link->wa_flags.dp_keep_receiver_powered = false;
3599 break;
3600 }
3601 } else
3602 link->wa_flags.dp_keep_receiver_powered = false;
3603}
3604
96577cf8
HW		 3605/* Read additional sink caps defined in source specific DPCD area
3606 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3607 */
3608static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3609{
3610 uint8_t dpcd_data;
3611
3612 if (!link)
3613 return false;
3614
3615 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3616 return false;
3617
3618 link->dpcd_sink_ext_caps.raw = dpcd_data;
3619 return true;
3620}
3621
ee9b1992 3622bool dp_retrieve_lttpr_cap(struct dc_link *link)
4562236b 3623{
61aa7a6f 3624 uint8_t lttpr_dpcd_data[6];
7809fc00
WC		 3625 bool vbios_lttpr_enable = false;
3626 bool vbios_lttpr_interop = false;
3627 struct dc_bios *bios = link->dc->ctx->dc_bios;
ee9b1992
WC		 3628 enum dc_status status = DC_ERROR_UNEXPECTED;
3629 bool is_lttpr_present = false;
8e5100a5 3630
61aa7a6f 3631 memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
7809fc00
WC		 3632 /* Query BIOS to determine if LTTPR functionality is forced on by system */
3633 if (bios->funcs->get_lttpr_caps) {
3634 enum bp_result bp_query_result;
3635 uint8_t is_vbios_lttpr_enable = 0;
3636
3637 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3638 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3639 }
3640
3641 if (bios->funcs->get_lttpr_interop) {
3642 enum bp_result bp_query_result;
3643 uint8_t is_vbios_interop_enabled = 0;
3644
3645 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3646 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3647 }
3648
3649 /*
3650 * Logic to determine LTTPR mode
3651 */
3652 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3653 if (vbios_lttpr_enable && vbios_lttpr_interop)
3654 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3655 else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3656 if (link->dc->config.allow_lttpr_non_transparent_mode)
3657 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3658 else
3659 link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3660 } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3661 if (!link->dc->config.allow_lttpr_non_transparent_mode
3662 || !link->dc->caps.extended_aux_timeout_support)
3663 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3664 else
3665 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3666 }
3667
3668 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
c797ede0 3669 /* By reading LTTPR capability, RX assumes that we will enable
7809fc00 3670 * LTTPR extended aux timeout if LTTPR is present.
c797ede0 3671 */
8e5100a5 3672 status = core_link_read_dpcd(
3673 link,
61aa7a6f 3674 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3675 lttpr_dpcd_data,
3676 sizeof(lttpr_dpcd_data));
3677
3678 link->dpcd_caps.lttpr_caps.revision.raw =
3679 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3680 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3681
3682 link->dpcd_caps.lttpr_caps.max_link_rate =
3683 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3684 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3685
3686 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3687 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3688 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3689
3690 link->dpcd_caps.lttpr_caps.max_lane_count =
3691 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3692 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3693
3694 link->dpcd_caps.lttpr_caps.mode =
3695 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3696 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3697
3698 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3699 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3700 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3701
ede4f6da 3702 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
c797ede0 3703 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
ede4f6da 3704 link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff &&
61aa7a6f 3705 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3706 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
c797ede0
WL		 3707 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3708 if (is_lttpr_present)
3709 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
fab85801
WC		 3710 else
3711 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
a1500a62 3712 }
ee9b1992
WC		 3713 return is_lttpr_present;
3714}
3715
3716static bool retrieve_link_cap(struct dc_link *link)
3717{
3718 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3719 * which means size 16 will be good for both of those DPCD register block reads
3720 */
3721 uint8_t dpcd_data[16];
3722 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3723 */
3724 uint8_t dpcd_dprx_data = '\0';
3725 uint8_t dpcd_power_state = '\0';
3726
3727 struct dp_device_vendor_id sink_id;
3728 union down_stream_port_count down_strm_port_count;
3729 union edp_configuration_cap edp_config_cap;
3730 union dp_downstream_port_present ds_port = { 0 };
3731 enum dc_status status = DC_ERROR_UNEXPECTED;
3732 uint32_t read_dpcd_retry_cnt = 3;
3733 int i;
3734 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3735 const uint32_t post_oui_delay = 30; // 30ms
3736 bool is_lttpr_present = false;
3737
3738 memset(dpcd_data, '\0', sizeof(dpcd_data));
3739 memset(&down_strm_port_count,
3740 '\0', sizeof(union down_stream_port_count));
3741 memset(&edp_config_cap, '\0',
3742 sizeof(union edp_configuration_cap));
3743
3744 /* if extended timeout is supported in hardware,
3745 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3746 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3747 */
3748 dc_link_aux_try_to_configure_timeout(link->ddc,
3749 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
fb8cf277 3750
ee9b1992 3751 is_lttpr_present = dp_retrieve_lttpr_cap(link);
c797ede0
WL		 3752 if (!is_lttpr_present)
3753 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3754
3755
0abda674
WC		 3756 status = core_link_read_dpcd(link, DP_SET_POWER,
3757 &dpcd_power_state, sizeof(dpcd_power_state));
3758
3759 /* Delay 1 ms if AUX CH is in power down state. Based on spec
3760 * section 2.3.1.2, if AUX CH may be powered down due to
3761 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3762 * signal and may need up to 1 ms before being able to reply.
3763 */
3764 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3765 udelay(1000);
3766
3767 dpcd_set_source_specific_data(link);
3768 /* Sink may need to configure internals based on vendor, so allow some
3769 * time before proceeding with possibly vendor specific transactions
3770 */
3771 msleep(post_oui_delay);
3772
3773 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3774 status = core_link_read_dpcd(
3775 link,
3776 DP_DPCD_REV,
3777 dpcd_data,
3778 sizeof(dpcd_data));
3779 if (status == DC_OK)
3780 break;
3781 }
3782
3783
3784 if (status != DC_OK) {
3785 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
3786 return false;
3787 }
3788
4562236b
HW		 3789 {
3790 union training_aux_rd_interval aux_rd_interval;
3791
3792 aux_rd_interval.raw =
3a340294 3793 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
4562236b 3794
3c7dd2cb 3795 link->dpcd_caps.ext_receiver_cap_field_present =
b239b59b 3796 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3c7dd2cb
HT		 3797
3798 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
818832bf
XY		 3799 uint8_t ext_cap_data[16];
3800
3801 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3802 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3803 status = core_link_read_dpcd(
4562236b 3804 link,
3a340294 3805 DP_DP13_DPCD_REV,
818832bf
XY		 3806 ext_cap_data,
3807 sizeof(ext_cap_data));
3808 if (status == DC_OK) {
3809 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3810 break;
3811 }
3812 }
3813 if (status != DC_OK)
3814 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
4562236b
HW		 3815 }
3816 }
3817
3c7dd2cb
HT		 3818 link->dpcd_caps.dpcd_rev.raw =
3819 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3820
7715fdf3 3821 if (link->dpcd_caps.ext_receiver_cap_field_present) {
3c7dd2cb
HT		 3822 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3823 status = core_link_read_dpcd(
3824 link,
3825 DP_DPRX_FEATURE_ENUMERATION_LIST,
3826 &dpcd_dprx_data,
3827 sizeof(dpcd_dprx_data));
3828 if (status == DC_OK)
3829 break;
3830 }
3831
3832 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3833
3834 if (status != DC_OK)
3835 dm_error("%s: Read DPRX caps data failed.\n", __func__);
3836 }
3837
3838 else {
3839 link->dpcd_caps.dprx_feature.raw = 0;
3840 }
3841
3842
07d6a199
AK		 3843 /* Error condition checking...
3844 * It is impossible for Sink to report Max Lane Count = 0.
3845 * It is possible for Sink to report Max Link Rate = 0, if it is
3846 * an eDP device that is reporting specialized link rates in the
3847 * SUPPORTED_LINK_RATE table.
3848 */
3849 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3850 return false;
3851
3a340294
DA		 3852 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3853 DP_DPCD_REV];
4562236b 3854
ee13cea9
JB		 3855 read_dp_device_vendor_id(link);
3856
4562236b
HW		 3857 get_active_converter_info(ds_port.byte, link);
3858
3859 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3860
98e6436d
AK		 3861 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3862 DP_DPCD_REV];
3863
4562236b
HW		 3864 link->dpcd_caps.allow_invalid_MSA_timing_param =
3865 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3866
3867 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3a340294 3868 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4562236b
HW		 3869
3870 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3a340294 3871 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4562236b 3872
d0778ebf 3873 link->reported_link_cap.lane_count =
4562236b 3874 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
d0778ebf 3875 link->reported_link_cap.link_rate = dpcd_data[
3a340294 3876 DP_MAX_LINK_RATE - DP_DPCD_REV];
d0778ebf 3877 link->reported_link_cap.link_spread =
4562236b
HW		 3878 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3879 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3880
3881 edp_config_cap.raw = dpcd_data[
3a340294 3882 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4562236b
HW		 3883 link->dpcd_caps.panel_mode_edp =
3884 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
9799624a
WL		 3885 link->dpcd_caps.dpcd_display_control_capable =
3886 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4562236b 3887
d0778ebf
HW		 3888 link->test_pattern_enabled = false;
3889 link->compliance_test_state.raw = 0;
4562236b 3890
4562236b
HW		 3891 /* read sink count */
3892 core_link_read_dpcd(link,
3a340294 3893 DP_SINK_COUNT,
4562236b
HW		 3894 &link->dpcd_caps.sink_count.raw,
3895 sizeof(link->dpcd_caps.sink_count.raw));
3896
8ca80900
AK		 3897 /* read sink ieee oui */
3898 core_link_read_dpcd(link,
3899 DP_SINK_OUI,
3900 (uint8_t *)(&sink_id),
3901 sizeof(sink_id));
3902
3903 link->dpcd_caps.sink_dev_id =
3904 (sink_id.ieee_oui[0] << 16) +
3905 (sink_id.ieee_oui[1] << 8) +
3906 (sink_id.ieee_oui[2]);
3907
4b99affb
A		 3908 memmove(
3909 link->dpcd_caps.sink_dev_id_str,
3910 sink_id.ieee_device_id,
3911 sizeof(sink_id.ieee_device_id));
3912
473e3f77
MK		 3913 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3914 {
3915 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3916
3917 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3918 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3919 sizeof(str_mbp_2017))) {
3920 link->reported_link_cap.link_rate = 0x0c;
3921 }
3922 }
3923
4b99affb
A		 3924 core_link_read_dpcd(
3925 link,
3926 DP_SINK_HW_REVISION_START,
3927 (uint8_t *)&dp_hw_fw_revision,
3928 sizeof(dp_hw_fw_revision));
3929
3930 link->dpcd_caps.sink_hw_revision =
3931 dp_hw_fw_revision.ieee_hw_rev;
3932
3933 memmove(
3934 link->dpcd_caps.sink_fw_revision,
3935 dp_hw_fw_revision.ieee_fw_rev,
3936 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3937
39a4eb85
WL		 3938 memset(&link->dpcd_caps.dsc_caps, '\0',
3939 sizeof(link->dpcd_caps.dsc_caps));
97bda032
HW		 3940 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3941 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3942 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
97bda032
HW		 3943 status = core_link_read_dpcd(
3944 link,
3945 DP_FEC_CAPABILITY,
3946 &link->dpcd_caps.fec_cap.raw,
3947 sizeof(link->dpcd_caps.fec_cap.raw));
39a4eb85
WL		 3948 status = core_link_read_dpcd(
3949 link,
3950 DP_DSC_SUPPORT,
3951 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3952 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3953 status = core_link_read_dpcd(
3954 link,
3955 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
6d824ed5
WL		 3956 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3957 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
97bda032 3958 }
6fbefb84 3959
96577cf8
HW		 3960 if (!dpcd_read_sink_ext_caps(link))
3961 link->dpcd_sink_ext_caps.raw = 0;
3962
4562236b
HW		 3963 /* Connectivity log: detection */
3964 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
cdb39798
YS		 3965
3966 return true;
4562236b
HW		 3967}
3968
8547058b
LH		 3969bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3970{
3971 uint8_t dpcd_data[16];
3972 uint32_t read_dpcd_retry_cnt = 3;
3973 enum dc_status status = DC_ERROR_UNEXPECTED;
3974 union dp_downstream_port_present ds_port = { 0 };
3975 union down_stream_port_count down_strm_port_count;
3976 union edp_configuration_cap edp_config_cap;
3977
3978 int i;
3979
3980 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3981 status = core_link_read_dpcd(
3982 link,
3983 DP_DPCD_REV,
3984 dpcd_data,
3985 sizeof(dpcd_data));
3986 if (status == DC_OK)
3987 break;
3988 }
3989
3990 link->dpcd_caps.dpcd_rev.raw =
3991 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3992
3993 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3994 return false;
3995
3996 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3997 DP_DPCD_REV];
3998
3999 get_active_converter_info(ds_port.byte, link);
4000
4001 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
4002 DP_DPCD_REV];
4003
4004 link->dpcd_caps.allow_invalid_MSA_timing_param =
4005 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
4006
4007 link->dpcd_caps.max_ln_count.raw = dpcd_data[
4008 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4009
4010 link->dpcd_caps.max_down_spread.raw = dpcd_data[
4011 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4012
4013 link->reported_link_cap.lane_count =
4014 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
4015 link->reported_link_cap.link_rate = dpcd_data[
4016 DP_MAX_LINK_RATE - DP_DPCD_REV];
4017 link->reported_link_cap.link_spread =
4018 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
4019 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
4020
4021 edp_config_cap.raw = dpcd_data[
4022 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4023 link->dpcd_caps.panel_mode_edp =
4024 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
4025 link->dpcd_caps.dpcd_display_control_capable =
4026 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4027
4028 return true;
4029}
4030
cdb39798 4031bool detect_dp_sink_caps(struct dc_link *link)
4562236b 4032{
cdb39798 4033 return retrieve_link_cap(link);
4562236b
HW		 4034
4035 /* dc init_hw has power encoder using default
4036 * signal for connector. For native DP, no
4037 * need to power up encoder again. If not native
4038 * DP, hw_init may need check signal or power up
4039 * encoder here.
4040 */
4562236b
HW		 4041 /* TODO save sink caps in link->sink */
4042}
4043
d308d0b4 4044static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
b03a599b
DL		 4045{
4046 enum dc_link_rate link_rate;
4047 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
4048 switch (link_rate_in_khz) {
4049 case 1620000:
4050 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
4051 break;
4052 case 2160000:
4053 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
4054 break;
4055 case 2430000:
4056 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
4057 break;
4058 case 2700000:
4059 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
4060 break;
4061 case 3240000:
4062 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
4063 break;
4064 case 4320000:
4065 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
4066 break;
4067 case 5400000:
4068 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
4069 break;
4070 case 8100000:
4071 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
4072 break;
4073 default:
4074 link_rate = LINK_RATE_UNKNOWN;
4075 break;
4076 }
4077 return link_rate;
4078}
4079
4654a2f7
RL		 4080void detect_edp_sink_caps(struct dc_link *link)
4081{
8628d02f 4082 uint8_t supported_link_rates[16];
b03a599b
DL		 4083 uint32_t entry;
4084 uint32_t link_rate_in_khz;
4085 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
65e870df 4086 uint8_t backlight_adj_cap;
48231fd5 4087
b03a599b 4088 retrieve_link_cap(link);
8628d02f
JP		 4089 link->dpcd_caps.edp_supported_link_rates_count = 0;
4090 memset(supported_link_rates, 0, sizeof(supported_link_rates));
48231fd5 4091
67c268a5
ZL		 4092 /*
4093 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
4094 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
4095 */
4096 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
66611a72 4097 (link->dc->debug.optimize_edp_link_rate ||
53c81fc7 4098 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
b03a599b
DL		 4099 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4100 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4101 supported_link_rates, sizeof(supported_link_rates));
4102
b03a599b
DL		 4103 for (entry = 0; entry < 16; entry += 2) {
4104 // DPCD register reports per-lane link rate = 16-bit link rate capability
8628d02f 4105 // value X 200 kHz. Need multiplier to find link rate in kHz.
b03a599b
DL		 4106 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4107 supported_link_rates[entry]) * 200;
4108
4109 if (link_rate_in_khz != 0) {
4110 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
8628d02f
JP		 4111 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4112 link->dpcd_caps.edp_supported_link_rates_count++;
53c81fc7
WC		 4113
4114 if (link->reported_link_cap.link_rate < link_rate)
4115 link->reported_link_cap.link_rate = link_rate;
b03a599b
DL		 4116 }
4117 }
4118 }
4654a2f7 4119 link->verified_link_cap = link->reported_link_cap;
96577cf8 4120
65e870df
RC		 4121 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4122 &backlight_adj_cap, sizeof(backlight_adj_cap));
4123
4124 link->dpcd_caps.dynamic_backlight_capable_edp =
4125 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4126
96577cf8 4127 dc_link_set_default_brightness_aux(link);
4654a2f7
RL		 4128}
4129
4562236b
HW		 4130void dc_link_dp_enable_hpd(const struct dc_link *link)
4131{
d0778ebf 4132 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 4133
4134 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4135 encoder->funcs->enable_hpd(encoder);
4136}
4137
4138void dc_link_dp_disable_hpd(const struct dc_link *link)
4139{
d0778ebf 4140 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 4141
4142 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4143 encoder->funcs->disable_hpd(encoder);
4144}
4145
4146static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4147{
0e19401f
TC		 4148 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4149 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4150 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4562236b
HW		 4151 return true;
4152 else
4153 return false;
4154}
4155
d0778ebf 4156static void set_crtc_test_pattern(struct dc_link *link,
4562236b 4157 struct pipe_ctx *pipe_ctx,
2057b7e1
WL		 4158 enum dp_test_pattern test_pattern,
4159 enum dp_test_pattern_color_space test_pattern_color_space)
4562236b
HW		 4160{
4161 enum controller_dp_test_pattern controller_test_pattern;
4162 enum dc_color_depth color_depth = pipe_ctx->
4fa086b9 4163 stream->timing.display_color_depth;
4562236b 4164 struct bit_depth_reduction_params params;
661a8cd9 4165 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
6fbefb84
HW		 4166 int width = pipe_ctx->stream->timing.h_addressable +
4167 pipe_ctx->stream->timing.h_border_left +
4168 pipe_ctx->stream->timing.h_border_right;
4169 int height = pipe_ctx->stream->timing.v_addressable +
4170 pipe_ctx->stream->timing.v_border_bottom +
4171 pipe_ctx->stream->timing.v_border_top;
4562236b
HW		 4172
4173 memset(&params, 0, sizeof(params));
4174
4175 switch (test_pattern) {
4176 case DP_TEST_PATTERN_COLOR_SQUARES:
4177 controller_test_pattern =
4178 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4179 break;
4180 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4181 controller_test_pattern =
4182 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4183 break;
4184 case DP_TEST_PATTERN_VERTICAL_BARS:
4185 controller_test_pattern =
4186 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4187 break;
4188 case DP_TEST_PATTERN_HORIZONTAL_BARS:
4189 controller_test_pattern =
4190 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4191 break;
4192 case DP_TEST_PATTERN_COLOR_RAMP:
4193 controller_test_pattern =
4194 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4195 break;
4196 default:
4197 controller_test_pattern =
4198 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4199 break;
4200 }
4201
4202 switch (test_pattern) {
4203 case DP_TEST_PATTERN_COLOR_SQUARES:
4204 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4205 case DP_TEST_PATTERN_VERTICAL_BARS:
4206 case DP_TEST_PATTERN_HORIZONTAL_BARS:
4207 case DP_TEST_PATTERN_COLOR_RAMP:
4208 {
4209 /* disable bit depth reduction */
4210 pipe_ctx->stream->bit_depth_params = params;
661a8cd9 4211 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
7f93c1de
CL		 4212 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4213 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b 4214 controller_test_pattern, color_depth);
dbf5256b 4215 else if (link->dc->hwss.set_disp_pattern_generator) {
b1f6d01c 4216 struct pipe_ctx *odm_pipe;
2057b7e1 4217 enum controller_dp_color_space controller_color_space;
b1f6d01c 4218 int opp_cnt = 1;
10b4e64e
WL		 4219 int offset = 0;
4220 int dpg_width = width;
6fbefb84 4221
2057b7e1
WL		 4222 switch (test_pattern_color_space) {
4223 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4224 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4225 break;
4226 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4227 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4228 break;
4229 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4230 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4231 break;
4232 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4233 default:
4234 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4235 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4236 ASSERT(0);
4237 break;
4238 }
4239
b1f6d01c
DL		 4240 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4241 opp_cnt++;
10b4e64e
WL		 4242 dpg_width = width / opp_cnt;
4243 offset = dpg_width;
6fbefb84 4244
dbf5256b
JA		 4245 link->dc->hwss.set_disp_pattern_generator(link->dc,
4246 pipe_ctx,
6fbefb84 4247 controller_test_pattern,
2057b7e1 4248 controller_color_space,
6fbefb84
HW		 4249 color_depth,
4250 NULL,
10b4e64e
WL		 4251 dpg_width,
4252 height,
dbf5256b
JA		 4253 0);
4254
4255 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4256 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4257
4258 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4259 link->dc->hwss.set_disp_pattern_generator(link->dc,
4260 odm_pipe,
4261 controller_test_pattern,
4262 controller_color_space,
4263 color_depth,
4264 NULL,
4265 dpg_width,
4266 height,
4267 offset);
10b4e64e 4268 offset += offset;
6fbefb84 4269 }
6fbefb84 4270 }
4562236b
HW		 4271 }
4272 break;
4273 case DP_TEST_PATTERN_VIDEO_MODE:
4274 {
4275 /* restore bitdepth reduction */
661a8cd9 4276 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4562236b 4277 pipe_ctx->stream->bit_depth_params = params;
661a8cd9 4278 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
7f93c1de
CL		 4279 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4280 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 4281 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4282 color_depth);
dbf5256b 4283 else if (link->dc->hwss.set_disp_pattern_generator) {
b1f6d01c
DL		 4284 struct pipe_ctx *odm_pipe;
4285 int opp_cnt = 1;
10b4e64e 4286 int dpg_width = width;
b1f6d01c
DL		 4287
4288 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4289 opp_cnt++;
6fbefb84 4290
10b4e64e 4291 dpg_width = width / opp_cnt;
b1f6d01c
DL		 4292 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4293 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
6fbefb84 4294
b1f6d01c 4295 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
dbf5256b
JA		 4296 link->dc->hwss.set_disp_pattern_generator(link->dc,
4297 odm_pipe,
4298 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4299 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4300 color_depth,
4301 NULL,
4302 dpg_width,
4303 height,
4304 0);
4305 }
4306 link->dc->hwss.set_disp_pattern_generator(link->dc,
4307 pipe_ctx,
6fbefb84 4308 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2057b7e1 4309 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
6fbefb84
HW		 4310 color_depth,
4311 NULL,
10b4e64e
WL		 4312 dpg_width,
4313 height,
4314 0);
6fbefb84 4315 }
4562236b
HW		 4316 }
4317 break;
4318
4319 default:
4320 break;
4321 }
4322}
4323
4324bool dc_link_dp_set_test_pattern(
d0778ebf 4325 struct dc_link *link,
4562236b 4326 enum dp_test_pattern test_pattern,
2057b7e1 4327 enum dp_test_pattern_color_space test_pattern_color_space,
4562236b
HW		 4328 const struct link_training_settings *p_link_settings,
4329 const unsigned char *p_custom_pattern,
4330 unsigned int cust_pattern_size)
4331{
608ac7bb 4332 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
33fd9cb8 4333 struct pipe_ctx *pipe_ctx = NULL;
4562236b
HW		 4334 unsigned int lane;
4335 unsigned int i;
4336 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4337 union dpcd_training_pattern training_pattern;
4562236b
HW		 4338 enum dpcd_phy_test_patterns pattern;
4339
4340 memset(&training_pattern, 0, sizeof(training_pattern));
4562236b
HW		 4341
4342 for (i = 0; i < MAX_PIPES; i++) {
33fd9cb8
QZ		 4343 if (pipes[i].stream == NULL)
4344 continue;
4345
24d01c9b 4346 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
0a8f43ff 4347 pipe_ctx = &pipes[i];
4562236b
HW		 4348 break;
4349 }
4350 }
4351
33fd9cb8
QZ		 4352 if (pipe_ctx == NULL)
4353 return false;
4354
dbf5256b 4355 /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
d0778ebf 4356 if (link->test_pattern_enabled && test_pattern ==
4562236b
HW		 4357 DP_TEST_PATTERN_VIDEO_MODE) {
4358 /* Set CRTC Test Pattern */
2057b7e1 4359 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
d0778ebf 4360 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 4361 (uint8_t *)p_custom_pattern,
4362 (uint32_t)cust_pattern_size);
4363
4364 /* Unblank Stream */
d0778ebf 4365 link->dc->hwss.unblank_stream(
0a8f43ff 4366 pipe_ctx,
d0778ebf 4367 &link->verified_link_cap);
4562236b
HW		 4368 /* TODO:m_pHwss->MuteAudioEndpoint
4369 * (pPathMode->pDisplayPath, false);
4370 */
4371
4372 /* Reset Test Pattern state */
d0778ebf 4373 link->test_pattern_enabled = false;
4562236b
HW		 4374
4375 return true;
4376 }
4377
4378 /* Check for PHY Test Patterns */
4379 if (is_dp_phy_pattern(test_pattern)) {
4380 /* Set DPCD Lane Settings before running test pattern */
4381 if (p_link_settings != NULL) {
64c12b73 4382 dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4383 dpcd_set_lane_settings(link, p_link_settings, DPRX);
4562236b
HW		 4384 }
4385
4386 /* Blank stream if running test pattern */
4387 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4388 /*TODO:
4389 * m_pHwss->
4390 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4391 */
4392 /* Blank stream */
8e9c4c8c 4393 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4562236b
HW		 4394 }
4395
d0778ebf 4396 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 4397 (uint8_t *)p_custom_pattern,
4398 (uint32_t)cust_pattern_size);
4399
4400 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4401 /* Set Test Pattern state */
d0778ebf 4402 link->test_pattern_enabled = true;
4562236b 4403 if (p_link_settings != NULL)
d0778ebf 4404 dpcd_set_link_settings(link,
4562236b
HW		 4405 p_link_settings);
4406 }
4407
4408 switch (test_pattern) {
4409 case DP_TEST_PATTERN_VIDEO_MODE:
4410 pattern = PHY_TEST_PATTERN_NONE;
0e19401f 4411 break;
4562236b
HW		 4412 case DP_TEST_PATTERN_D102:
4413 pattern = PHY_TEST_PATTERN_D10_2;
0e19401f 4414 break;
4562236b
HW		 4415 case DP_TEST_PATTERN_SYMBOL_ERROR:
4416 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 4417 break;
4562236b
HW		 4418 case DP_TEST_PATTERN_PRBS7:
4419 pattern = PHY_TEST_PATTERN_PRBS7;
0e19401f 4420 break;
4562236b
HW		 4421 case DP_TEST_PATTERN_80BIT_CUSTOM:
4422 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 4423 break;
4424 case DP_TEST_PATTERN_CP2520_1:
4425 pattern = PHY_TEST_PATTERN_CP2520_1;
4426 break;
4427 case DP_TEST_PATTERN_CP2520_2:
4428 pattern = PHY_TEST_PATTERN_CP2520_2;
4429 break;
4430 case DP_TEST_PATTERN_CP2520_3:
4431 pattern = PHY_TEST_PATTERN_CP2520_3;
4432 break;
4562236b
HW		 4433 default:
4434 return false;
4435 }
4436
4437 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4438 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4439 return false;
4440
d0778ebf 4441 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 4442 /* tell receiver that we are sending qualification
4443 * pattern DP 1.2 or later - DP receiver's link quality
4444 * pattern is set using DPCD LINK_QUAL_LANEx_SET
4445 * register (0x10B~0x10E)\
4446 */
4447 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4448 link_qual_pattern[lane] =
4449 (unsigned char)(pattern);
4450
d0778ebf 4451 core_link_write_dpcd(link,
3a340294 4452 DP_LINK_QUAL_LANE0_SET,
4562236b
HW		 4453 link_qual_pattern,
4454 sizeof(link_qual_pattern));
d0778ebf
HW		 4455 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4456 link->dpcd_caps.dpcd_rev.raw == 0) {
4562236b
HW		 4457 /* tell receiver that we are sending qualification
4458 * pattern DP 1.1a or earlier - DP receiver's link
4459 * quality pattern is set using
4460 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4461 * register (0x102). We will use v_1.3 when we are
4462 * setting test pattern for DP 1.1.
4463 */
d0778ebf
HW		 4464 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4465 &training_pattern.raw,
4466 sizeof(training_pattern));
4562236b 4467 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
d0778ebf
HW		 4468 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4469 &training_pattern.raw,
4470 sizeof(training_pattern));
4562236b
HW		 4471 }
4472 } else {
43563bc2 4473 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
43563bc2
WL		 4474
4475 switch (test_pattern_color_space) {
4476 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4477 color_space = COLOR_SPACE_SRGB;
4478 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4479 color_space = COLOR_SPACE_SRGB_LIMITED;
4480 break;
4481
4482 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4483 color_space = COLOR_SPACE_YCBCR601;
4484 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4485 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4486 break;
4487 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4488 color_space = COLOR_SPACE_YCBCR709;
4489 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4490 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4491 break;
4492 default:
4493 break;
4494 }
e8f9ecf2 4495
dc6e2448
WW		 4496 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4497 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4498 union dmub_hw_lock_flags hw_locks = { 0 };
4499 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4500
4501 hw_locks.bits.lock_dig = 1;
4502 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4503
4504 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4505 true,
4506 &hw_locks,
4507 &inst_flags);
4508 } else
4509 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4510 pipe_ctx->stream_res.tg);
4511 }
4512
e8f9ecf2 4513 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
43563bc2
WL		 4514 /* update MSA to requested color space */
4515 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4516 &pipe_ctx->stream->timing,
23bc5f34
WL		 4517 color_space,
4518 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4519 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
43563bc2 4520
e8f9ecf2
WL		 4521 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4522 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4523 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4524 else
4525 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4526 resource_build_info_frame(pipe_ctx);
4527 link->dc->hwss.update_info_frame(pipe_ctx);
4528 }
4529
43563bc2 4530 /* CRTC Patterns */
2057b7e1 4531 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
e8f9ecf2
WL		 4532 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4533 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4534 CRTC_STATE_VACTIVE);
4535 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4536 CRTC_STATE_VBLANK);
4537 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4538 CRTC_STATE_VACTIVE);
dc6e2448
WW		 4539
4540 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4541 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4542 union dmub_hw_lock_flags hw_locks = { 0 };
4543 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4544
4545 hw_locks.bits.lock_dig = 1;
4546 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4547
4548 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4549 false,
4550 &hw_locks,
4551 &inst_flags);
4552 } else
4553 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4554 pipe_ctx->stream_res.tg);
4555 }
4556
4562236b 4557 /* Set Test Pattern state */
d0778ebf 4558 link->test_pattern_enabled = true;
4562236b
HW		 4559 }
4560
4561 return true;
4562}
07c84c7a 4563
d0778ebf 4564void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
07c84c7a
DW		 4565{
4566 unsigned char mstmCntl;
4567
4568 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4569 if (enable)
4570 mstmCntl |= DP_MST_EN;
4571 else
4572 mstmCntl &= (~DP_MST_EN);
4573
4574 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4575}
6fbefb84 4576
0b226322
DG		 4577void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4578{
4579 union dpcd_edp_config edp_config_set;
4580 bool panel_mode_edp = false;
4581
4582 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4583
4584 if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4585
4586 switch (panel_mode) {
4587 case DP_PANEL_MODE_EDP:
4588 case DP_PANEL_MODE_SPECIAL:
4589 panel_mode_edp = true;
4590 break;
4591
4592 default:
4593 break;
4594 }
4595
4596 /*set edp panel mode in receiver*/
4597 core_link_read_dpcd(
4598 link,
4599 DP_EDP_CONFIGURATION_SET,
4600 &edp_config_set.raw,
4601 sizeof(edp_config_set.raw));
4602
4603 if (edp_config_set.bits.PANEL_MODE_EDP
4604 != panel_mode_edp) {
140b93eb 4605 enum dc_status result;
0b226322
DG		 4606
4607 edp_config_set.bits.PANEL_MODE_EDP =
4608 panel_mode_edp;
4609 result = core_link_write_dpcd(
4610 link,
4611 DP_EDP_CONFIGURATION_SET,
4612 &edp_config_set.raw,
4613 sizeof(edp_config_set.raw));
4614
a110f375 4615 ASSERT(result == DC_OK);
0b226322
DG		 4616 }
4617 }
4618 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4619 "eDP panel mode enabled: %d \n",
4620 link->link_index,
4621 link->dpcd_caps.panel_mode_edp,
4622 panel_mode_edp);
4623}
4624
4625enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4626{
4627 /* We need to explicitly check that connector
4628 * is not DP. Some Travis_VGA get reported
4629 * by video bios as DP.
4630 */
4631 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4632
4633 switch (link->dpcd_caps.branch_dev_id) {
df3b7e32
QZ		 4634 case DP_BRANCH_DEVICE_ID_0022B9:
4635 /* alternate scrambler reset is required for Travis
4636 * for the case when external chip does not
4637 * provide sink device id, alternate scrambler
4638 * scheme will be overriden later by querying
4639 * Encoder features
4640 */
0b226322
DG		 4641 if (strncmp(
4642 link->dpcd_caps.branch_dev_name,
4643 DP_VGA_LVDS_CONVERTER_ID_2,
4644 sizeof(
4645 link->dpcd_caps.
4646 branch_dev_name)) == 0) {
4647 return DP_PANEL_MODE_SPECIAL;
4648 }
4649 break;
df3b7e32
QZ		 4650 case DP_BRANCH_DEVICE_ID_00001A:
4651 /* alternate scrambler reset is required for Travis
4652 * for the case when external chip does not provide
4653 * sink device id, alternate scrambler scheme will
4654 * be overriden later by querying Encoder feature
4655 */
0b226322
DG		 4656 if (strncmp(link->dpcd_caps.branch_dev_name,
4657 DP_VGA_LVDS_CONVERTER_ID_3,
4658 sizeof(
4659 link->dpcd_caps.
4660 branch_dev_name)) == 0) {
4661 return DP_PANEL_MODE_SPECIAL;
4662 }
4663 break;
4664 default:
4665 break;
4666 }
4667 }
4668
4669 if (link->dpcd_caps.panel_mode_edp) {
4670 return DP_PANEL_MODE_EDP;
4671 }
4672
4673 return DP_PANEL_MODE_DEFAULT;
4674}
4675
7211b605 4676enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
97bda032
HW		 4677{
4678 /* FEC has to be "set ready" before the link training.
4679 * The policy is to always train with FEC
4680 * if the sink supports it and leave it enabled on link.
4681 * If FEC is not supported, disable it.
4682 */
7211b605
JK		 4683 struct link_encoder *link_enc = NULL;
4684 enum dc_status status = DC_OK;
97bda032
HW		 4685 uint8_t fec_config = 0;
4686
7211b605
JK		 4687 /* Access link encoder based on whether it is statically
4688 * or dynamically assigned to a link.
4689 */
4690 if (link->is_dig_mapping_flexible &&
4691 link->dc->res_pool->funcs->link_encs_assign)
4692 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
4693 else
4694 link_enc = link->link_enc;
4695 ASSERT(link_enc);
4696
89c7dfa9 4697 if (!dc_link_should_enable_fec(link))
7211b605 4698 return status;
97bda032
HW		 4699
4700 if (link_enc->funcs->fec_set_ready &&
4701 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
008a4016 4702 if (ready) {
97bda032 4703 fec_config = 1;
7211b605 4704 status = core_link_write_dpcd(link,
97bda032
HW		 4705 DP_FEC_CONFIGURATION,
4706 &fec_config,
7211b605
JK		 4707 sizeof(fec_config));
4708 if (status == DC_OK) {
97bda032
HW		 4709 link_enc->funcs->fec_set_ready(link_enc, true);
4710 link->fec_state = dc_link_fec_ready;
4711 } else {
7211b605 4712 link_enc->funcs->fec_set_ready(link->link_enc, false);
d68a7454 4713 link->fec_state = dc_link_fec_not_ready;
97bda032
HW		 4714 dm_error("dpcd write failed to set fec_ready");
4715 }
008a4016 4716 } else if (link->fec_state == dc_link_fec_ready) {
97bda032 4717 fec_config = 0;
7211b605 4718 status = core_link_write_dpcd(link,
97bda032
HW		 4719 DP_FEC_CONFIGURATION,
4720 &fec_config,
4721 sizeof(fec_config));
7211b605 4722 link_enc->funcs->fec_set_ready(link_enc, false);
97bda032
HW		 4723 link->fec_state = dc_link_fec_not_ready;
4724 }
4725 }
7211b605
JK		 4726
4727 return status;
97bda032
HW		 4728}
4729
4730void dp_set_fec_enable(struct dc_link *link, bool enable)
4731{
7211b605
JK		 4732 struct link_encoder *link_enc = NULL;
4733
4734 /* Access link encoder based on whether it is statically
4735 * or dynamically assigned to a link.
4736 */
4737 if (link->is_dig_mapping_flexible &&
4738 link->dc->res_pool->funcs->link_encs_assign)
4739 link_enc = link_enc_cfg_get_link_enc_used_by_link(
4740 link->dc->current_state, link);
4741 else
4742 link_enc = link->link_enc;
4743 ASSERT(link_enc);
97bda032 4744
89c7dfa9 4745 if (!dc_link_should_enable_fec(link))
97bda032
HW		 4746 return;
4747
4748 if (link_enc->funcs->fec_set_enable &&
4749 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4750 if (link->fec_state == dc_link_fec_ready && enable) {
fa11d3c9
LHM		 4751 /* Accord to DP spec, FEC enable sequence can first
4752 * be transmitted anytime after 1000 LL codes have
4753 * been transmitted on the link after link training
4754 * completion. Using 1 lane RBR should have the maximum
4755 * time for transmitting 1000 LL codes which is 6.173 us.
4756 * So use 7 microseconds delay instead.
4757 */
4758 udelay(7);
97bda032
HW		 4759 link_enc->funcs->fec_set_enable(link_enc, true);
4760 link->fec_state = dc_link_fec_enabled;
4761 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4762 link_enc->funcs->fec_set_enable(link_enc, false);
4763 link->fec_state = dc_link_fec_ready;
4764 }
4765 }
4766}
6fbefb84 4767
96577cf8
HW		 4768void dpcd_set_source_specific_data(struct dc_link *link)
4769{
0136684f 4770 if (!link->dc->vendor_signature.is_valid) {
61f02424 4771 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
29d5ac56
YS		 4772 struct dpcd_amd_signature amd_signature = {0};
4773 struct dpcd_amd_device_id amd_device_id = {0};
4774
4775 amd_device_id.device_id_byte1 =
0136684f 4776 (uint8_t)(link->ctx->asic_id.chip_id);
29d5ac56 4777 amd_device_id.device_id_byte2 =
0136684f 4778 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
29d5ac56 4779 amd_device_id.dce_version =
0136684f 4780 (uint8_t)(link->ctx->dce_version);
29d5ac56
YS		 4781 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4782 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4783
4784 core_link_read_dpcd(link, DP_SOURCE_OUI,
4785 (uint8_t *)(&amd_signature),
4786 sizeof(amd_signature));
0136684f 4787
29d5ac56
YS		 4788 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4789 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4790 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4791
4792 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4793 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4794 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4795
4796 core_link_write_dpcd(link, DP_SOURCE_OUI,
0136684f
CH		 4797 (uint8_t *)(&amd_signature),
4798 sizeof(amd_signature));
29d5ac56
YS		 4799 }
4800
4801 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4802 (uint8_t *)(&amd_device_id),
4803 sizeof(amd_device_id));
0136684f 4804
9248681f
AT		 4805 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4806 link->dc->caps.min_horizontal_blanking_period != 0) {
4807
4808 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4809
4810 result_write_min_hblank = core_link_write_dpcd(link,
4811 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4812 sizeof(hblank_size));
4813 }
4814 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4815 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4816 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4817 result_write_min_hblank,
4818 link->link_index,
4819 link->ctx->dce_version,
4820 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4821 link->dc->caps.min_horizontal_blanking_period,
4822 link->dpcd_caps.branch_dev_id,
4823 link->dpcd_caps.branch_dev_name[0],
4824 link->dpcd_caps.branch_dev_name[1],
4825 link->dpcd_caps.branch_dev_name[2],
4826 link->dpcd_caps.branch_dev_name[3],
4827 link->dpcd_caps.branch_dev_name[4],
4828 link->dpcd_caps.branch_dev_name[5]);
0136684f
CH		 4829 } else {
4830 core_link_write_dpcd(link, DP_SOURCE_OUI,
4831 link->dc->vendor_signature.data.raw,
4832 sizeof(link->dc->vendor_signature.data.raw));
4833 }
96577cf8
HW		 4834}
4835
4836bool dc_link_set_backlight_level_nits(struct dc_link *link,
4837 bool isHDR,
4838 uint32_t backlight_millinits,
4839 uint32_t transition_time_in_ms)
4840{
4841 struct dpcd_source_backlight_set dpcd_backlight_set;
4842 uint8_t backlight_control = isHDR ? 1 : 0;
4843
4844 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4845 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4846 return false;
4847
4848 // OLEDs have no PWM, they can only use AUX
4849 if (link->dpcd_sink_ext_caps.bits.oled == 1)
4850 backlight_control = 1;
4851
4852 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4853 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4854
4855
4856 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4857 (uint8_t *)(&dpcd_backlight_set),
4858 sizeof(dpcd_backlight_set)) != DC_OK)
4859 return false;
4860
4861 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4862 &backlight_control, 1) != DC_OK)
4863 return false;
4864
4865 return true;
4866}
4867
4868bool dc_link_get_backlight_level_nits(struct dc_link *link,
4869 uint32_t *backlight_millinits_avg,
4870 uint32_t *backlight_millinits_peak)
4871{
4872 union dpcd_source_backlight_get dpcd_backlight_get;
4873
4874 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4875
4876 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4877 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4878 return false;
4879
16697cf3 4880 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
96577cf8 4881 dpcd_backlight_get.raw,
16697cf3 4882 sizeof(union dpcd_source_backlight_get)) != DC_OK)
96577cf8
HW		 4883 return false;
4884
4885 *backlight_millinits_avg =
4886 dpcd_backlight_get.bytes.backlight_millinits_avg;
4887 *backlight_millinits_peak =
4888 dpcd_backlight_get.bytes.backlight_millinits_peak;
4889
4890 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4891 if (*backlight_millinits_avg == 0 ||
4892 *backlight_millinits_avg > *backlight_millinits_peak)
4893 return false;
4894
4895 return true;
4896}
4897
4898bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4899{
4900 uint8_t backlight_enable = enable ? 1 : 0;
4901
4902 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4903 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4904 return false;
4905
4906 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4907 &backlight_enable, 1) != DC_OK)
4908 return false;
4909
4910 return true;
4911}
4912
4913// we read default from 0x320 because we expect BIOS wrote it there
4914// regular get_backlight_nit reads from panel set at 0x326
4915bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4916{
4917 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4918 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4919 return false;
4920
16697cf3 4921 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
96577cf8 4922 (uint8_t *) backlight_millinits,
16697cf3 4923 sizeof(uint32_t)) != DC_OK)
96577cf8
HW		 4924 return false;
4925
4926 return true;
4927}
4928
4929bool dc_link_set_default_brightness_aux(struct dc_link *link)
4930{
4931 uint32_t default_backlight;
4932
4933 if (link &&
4934 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4935 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4936 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4937 default_backlight = 150000;
4938 // if < 5 nits or > 5000, it might be wrong readback
4939 if (default_backlight < 5000 || default_backlight > 5000000)
4940 default_backlight = 150000; //
4941
4942 return dc_link_set_backlight_level_nits(link, true,
4943 default_backlight, 0);
4944 }
4945 return false;
4946}
f9fc6f39
MS		 4947
4948bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4949{
4950 struct dc_link_settings link_setting;
4951 uint8_t link_bw_set;
4952 uint8_t link_rate_set;
4953 uint32_t req_bw;
4954 union lane_count_set lane_count_set = { {0} };
4955
4956 ASSERT(link || crtc_timing); // invalid input
4957
4958 if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4959 !link->dc->debug.optimize_edp_link_rate)
4960 return false;
4961
4962
4963 // Read DPCD 00100h to find if standard link rates are set
4964 core_link_read_dpcd(link, DP_LINK_BW_SET,
4965 &link_bw_set, sizeof(link_bw_set));
4966
0eda55ca
MS		 4967 if (link_bw_set) {
4968 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
f9fc6f39 4969 return true;
0eda55ca 4970 }
f9fc6f39
MS		 4971
4972 // Read DPCD 00115h to find the edp link rate set used
4973 core_link_read_dpcd(link, DP_LINK_RATE_SET,
4974 &link_rate_set, sizeof(link_rate_set));
4975
4976 // Read DPCD 00101h to find out the number of lanes currently set
4977 core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4978 &lane_count_set.raw, sizeof(lane_count_set));
4979
4980 req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4981
4982 decide_edp_link_settings(link, &link_setting, req_bw);
4983
4984 if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
0eda55ca
MS		 4985 lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4986 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
f9fc6f39 4987 return true;
0eda55ca 4988 }
f9fc6f39 4989
0eda55ca 4990 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
f9fc6f39
MS		 4991 return false;
4992}
4993
55bac4a7
WL		 4994enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4995{
4996 if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4997 (link_settings->link_rate <= LINK_RATE_HIGH3))
4998 return DP_8b_10b_ENCODING;
4999 return DP_UNKNOWN_ENCODING;
5000}
f9fc6f39 5001
Linux 6.x block layer and io_uring tree(s)