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drm/amd/display: Update ABM crtc state on non-modeset
[linux-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
CommitLineData
4562236b
HW		 1/* Copyright 2015 Advanced Micro Devices, Inc. */
2#include "dm_services.h"
3#include "dc.h"
4#include "dc_link_dp.h"
5#include "dm_helpers.h"
7f93c1de 6#include "opp.h"
4562236b
HW		 7
8#include "inc/core_types.h"
9#include "link_hwss.h"
10#include "dc_link_ddc.h"
11#include "core_status.h"
12#include "dpcd_defs.h"
13
529cad0f 14#include "resource.h"
1296423b
BL		 15#define DC_LOGGER \
16 link->ctx->logger
4562236b
HW		 17
18/* maximum pre emphasis level allowed for each voltage swing level*/
19static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
20 PRE_EMPHASIS_LEVEL3,
21 PRE_EMPHASIS_LEVEL2,
22 PRE_EMPHASIS_LEVEL1,
23 PRE_EMPHASIS_DISABLED };
24
25enum {
26 POST_LT_ADJ_REQ_LIMIT = 6,
27 POST_LT_ADJ_REQ_TIMEOUT = 200
28};
29
30enum {
31 LINK_TRAINING_MAX_RETRY_COUNT = 5,
32 /* to avoid infinite loop where-in the receiver
33 * switches between different VS
34 */
35 LINK_TRAINING_MAX_CR_RETRY = 100
36};
37
04e21292
DA		 38static bool decide_fallback_link_setting(
39 struct dc_link_settings initial_link_settings,
40 struct dc_link_settings *current_link_setting,
41 enum link_training_result training_result);
9a6a8075 42static struct dc_link_settings get_common_supported_link_settings(
04e21292
DA		 43 struct dc_link_settings link_setting_a,
44 struct dc_link_settings link_setting_b);
45
4562236b 46static void wait_for_training_aux_rd_interval(
d0778ebf 47 struct dc_link *link,
4562236b
HW		 48 uint32_t default_wait_in_micro_secs)
49{
d6d36b55
NC		 50 union training_aux_rd_interval training_rd_interval;
51
52 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
4562236b
HW		 53
54 /* overwrite the delay if rev > 1.1*/
55 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
56 /* DP 1.2 or later - retrieve delay through
57 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
58 core_link_read_dpcd(
59 link,
3a340294 60 DP_TRAINING_AUX_RD_INTERVAL,
4562236b
HW		 61 (uint8_t *)&training_rd_interval,
62 sizeof(training_rd_interval));
63
64 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
65 default_wait_in_micro_secs =
66 training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
67 }
68
69 udelay(default_wait_in_micro_secs);
70
1296423b 71 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
4562236b
HW		 72 __func__,
73 default_wait_in_micro_secs);
74}
75
76static void dpcd_set_training_pattern(
d0778ebf 77 struct dc_link *link,
4562236b
HW		 78 union dpcd_training_pattern dpcd_pattern)
79{
80 core_link_write_dpcd(
81 link,
3a340294 82 DP_TRAINING_PATTERN_SET,
4562236b
HW		 83 &dpcd_pattern.raw,
84 1);
85
1296423b 86 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
4562236b 87 __func__,
3a340294 88 DP_TRAINING_PATTERN_SET,
4562236b
HW		 89 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
90}
91
92static void dpcd_set_link_settings(
d0778ebf 93 struct dc_link *link,
4562236b
HW		 94 const struct link_training_settings *lt_settings)
95{
8628d02f 96 uint8_t rate;
4562236b 97
9a6a8075
HW		 98 union down_spread_ctrl downspread = { {0} };
99 union lane_count_set lane_count_set = { {0} };
4562236b
HW		 100
101 downspread.raw = (uint8_t)
102 (lt_settings->link_settings.link_spread);
103
104 lane_count_set.bits.LANE_COUNT_SET =
105 lt_settings->link_settings.lane_count;
106
107 lane_count_set.bits.ENHANCED_FRAMING = 1;
108
109 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
110 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
111
3a340294 112 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
4562236b
HW		 113 &downspread.raw, sizeof(downspread));
114
8628d02f
JP		 115 core_link_write_dpcd(link, DP_LANE_COUNT_SET,
116 &lane_count_set.raw, 1);
117
b03a599b 118 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
8628d02f
JP		 119 lt_settings->link_settings.use_link_rate_set == true) {
120 rate = 0;
121 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
b03a599b 122 core_link_write_dpcd(link, DP_LINK_RATE_SET,
8628d02f
JP		 123 &lt_settings->link_settings.link_rate_set, 1);
124 } else {
125 rate = (uint8_t) (lt_settings->link_settings.link_rate);
126 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
b03a599b
DL		 127 }
128
8628d02f
JP		 129 if (rate) {
130 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
131 __func__,
132 DP_LINK_BW_SET,
133 lt_settings->link_settings.link_rate,
134 DP_LANE_COUNT_SET,
135 lt_settings->link_settings.lane_count,
136 DP_DOWNSPREAD_CTRL,
137 lt_settings->link_settings.link_spread);
138 } else {
139 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x\n %x spread = %x\n",
140 __func__,
141 DP_LINK_RATE_SET,
142 lt_settings->link_settings.link_rate_set,
143 DP_LANE_COUNT_SET,
144 lt_settings->link_settings.lane_count,
145 DP_DOWNSPREAD_CTRL,
146 lt_settings->link_settings.link_spread);
147 }
4562236b
HW		 148
149}
150
151static enum dpcd_training_patterns
152 hw_training_pattern_to_dpcd_training_pattern(
d0778ebf 153 struct dc_link *link,
4562236b
HW		 154 enum hw_dp_training_pattern pattern)
155{
156 enum dpcd_training_patterns dpcd_tr_pattern =
157 DPCD_TRAINING_PATTERN_VIDEOIDLE;
158
159 switch (pattern) {
160 case HW_DP_TRAINING_PATTERN_1:
161 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
162 break;
163 case HW_DP_TRAINING_PATTERN_2:
164 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
165 break;
166 case HW_DP_TRAINING_PATTERN_3:
167 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
168 break;
169 case HW_DP_TRAINING_PATTERN_4:
170 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
171 break;
172 default:
173 ASSERT(0);
1296423b 174 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
4562236b
HW		 175 __func__, pattern);
176 break;
177 }
178
179 return dpcd_tr_pattern;
180
181}
182
183static void dpcd_set_lt_pattern_and_lane_settings(
d0778ebf 184 struct dc_link *link,
4562236b
HW		 185 const struct link_training_settings *lt_settings,
186 enum hw_dp_training_pattern pattern)
187{
9a6a8075 188 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
4562236b 189 const uint32_t dpcd_base_lt_offset =
3a340294 190 DP_TRAINING_PATTERN_SET;
4562236b 191 uint8_t dpcd_lt_buffer[5] = {0};
9a6a8075 192 union dpcd_training_pattern dpcd_pattern = { {0} };
4562236b
HW		 193 uint32_t lane;
194 uint32_t size_in_bytes;
195 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
196
197 /*****************************************************************
198 * DpcdAddress_TrainingPatternSet
199 *****************************************************************/
200 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
201 hw_training_pattern_to_dpcd_training_pattern(link, pattern);
202
3a340294 203 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
4562236b
HW		 204 = dpcd_pattern.raw;
205
1296423b 206 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
4562236b 207 __func__,
3a340294 208 DP_TRAINING_PATTERN_SET,
4562236b
HW		 209 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
210
211 /*****************************************************************
212 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
213 *****************************************************************/
214 for (lane = 0; lane <
215 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
216
217 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
218 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
219 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
220 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
221
222 dpcd_lane[lane].bits.MAX_SWING_REACHED =
223 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
224 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
225 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
226 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
227 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
228 }
229
230 /* concatinate everything into one buffer*/
231
232 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
233
234 // 0x00103 - 0x00102
235 memmove(
3a340294 236 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
4562236b
HW		 237 dpcd_lane,
238 size_in_bytes);
239
1296423b 240 DC_LOG_HW_LINK_TRAINING("%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
4562236b 241 __func__,
3a340294 242 DP_TRAINING_LANE0_SET,
4562236b
HW		 243 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
244 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
245 dpcd_lane[0].bits.MAX_SWING_REACHED,
246 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
247
248 if (edp_workaround) {
249 /* for eDP write in 2 parts because the 5-byte burst is
250 * causing issues on some eDP panels (EPR#366724)
251 */
252 core_link_write_dpcd(
253 link,
3a340294 254 DP_TRAINING_PATTERN_SET,
4562236b 255 &dpcd_pattern.raw,
9a6a8075 256 sizeof(dpcd_pattern.raw));
4562236b
HW		 257
258 core_link_write_dpcd(
259 link,
3a340294 260 DP_TRAINING_LANE0_SET,
4562236b
HW		 261 (uint8_t *)(dpcd_lane),
262 size_in_bytes);
263
264 } else
265 /* write it all in (1 + number-of-lanes)-byte burst*/
266 core_link_write_dpcd(
267 link,
268 dpcd_base_lt_offset,
269 dpcd_lt_buffer,
9a6a8075 270 size_in_bytes + sizeof(dpcd_pattern.raw));
4562236b 271
d0778ebf 272 link->cur_lane_setting = lt_settings->lane_settings[0];
4562236b
HW		 273}
274
275static bool is_cr_done(enum dc_lane_count ln_count,
276 union lane_status *dpcd_lane_status)
277{
278 bool done = true;
279 uint32_t lane;
280 /*LANEx_CR_DONE bits All 1's?*/
281 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
282 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
283 done = false;
284 }
285 return done;
286
287}
288
289static bool is_ch_eq_done(enum dc_lane_count ln_count,
290 union lane_status *dpcd_lane_status,
291 union lane_align_status_updated *lane_status_updated)
292{
293 bool done = true;
294 uint32_t lane;
295 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
296 done = false;
297 else {
298 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
299 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
300 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
301 done = false;
302 }
303 }
304 return done;
305
306}
307
308static void update_drive_settings(
309 struct link_training_settings *dest,
310 struct link_training_settings src)
311{
312 uint32_t lane;
313 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
314 dest->lane_settings[lane].VOLTAGE_SWING =
315 src.lane_settings[lane].VOLTAGE_SWING;
316 dest->lane_settings[lane].PRE_EMPHASIS =
317 src.lane_settings[lane].PRE_EMPHASIS;
318 dest->lane_settings[lane].POST_CURSOR2 =
319 src.lane_settings[lane].POST_CURSOR2;
320 }
321}
322
323static uint8_t get_nibble_at_index(const uint8_t *buf,
324 uint32_t index)
325{
326 uint8_t nibble;
327 nibble = buf[index / 2];
328
329 if (index % 2)
330 nibble >>= 4;
331 else
332 nibble &= 0x0F;
333
334 return nibble;
335}
336
337static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
338 enum dc_voltage_swing voltage)
339{
340 enum dc_pre_emphasis pre_emphasis;
341 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
342
343 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
344 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
345
346 return pre_emphasis;
347
348}
349
350static void find_max_drive_settings(
351 const struct link_training_settings *link_training_setting,
352 struct link_training_settings *max_lt_setting)
353{
354 uint32_t lane;
355 struct dc_lane_settings max_requested;
356
357 max_requested.VOLTAGE_SWING =
358 link_training_setting->
359 lane_settings[0].VOLTAGE_SWING;
360 max_requested.PRE_EMPHASIS =
361 link_training_setting->
362 lane_settings[0].PRE_EMPHASIS;
363 /*max_requested.postCursor2 =
364 * link_training_setting->laneSettings[0].postCursor2;*/
365
366 /* Determine what the maximum of the requested settings are*/
367 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
368 lane++) {
369 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
370 max_requested.VOLTAGE_SWING)
371
372 max_requested.VOLTAGE_SWING =
373 link_training_setting->
374 lane_settings[lane].VOLTAGE_SWING;
375
376 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
377 max_requested.PRE_EMPHASIS)
378 max_requested.PRE_EMPHASIS =
379 link_training_setting->
380 lane_settings[lane].PRE_EMPHASIS;
381
382 /*
383 if (link_training_setting->laneSettings[lane].postCursor2 >
384 max_requested.postCursor2)
385 {
386 max_requested.postCursor2 =
387 link_training_setting->laneSettings[lane].postCursor2;
388 }
389 */
390 }
391
392 /* make sure the requested settings are
393 * not higher than maximum settings*/
394 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
395 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
396
397 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
398 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
399 /*
400 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
401 max_requested.postCursor2 = PostCursor2_MaxLevel;
402 */
403
404 /* make sure the pre-emphasis matches the voltage swing*/
405 if (max_requested.PRE_EMPHASIS >
406 get_max_pre_emphasis_for_voltage_swing(
407 max_requested.VOLTAGE_SWING))
408 max_requested.PRE_EMPHASIS =
409 get_max_pre_emphasis_for_voltage_swing(
410 max_requested.VOLTAGE_SWING);
411
412 /*
413 * Post Cursor2 levels are completely independent from
414 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
415 * can only be applied to each allowable combination of voltage
416 * swing and pre-emphasis levels */
417 /* if ( max_requested.postCursor2 >
418 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
419 * max_requested.postCursor2 =
420 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
421 */
422
423 max_lt_setting->link_settings.link_rate =
424 link_training_setting->link_settings.link_rate;
425 max_lt_setting->link_settings.lane_count =
426 link_training_setting->link_settings.lane_count;
427 max_lt_setting->link_settings.link_spread =
428 link_training_setting->link_settings.link_spread;
429
430 for (lane = 0; lane <
431 link_training_setting->link_settings.lane_count;
432 lane++) {
433 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
434 max_requested.VOLTAGE_SWING;
435 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
436 max_requested.PRE_EMPHASIS;
437 /*max_lt_setting->laneSettings[lane].postCursor2 =
438 * max_requested.postCursor2;
439 */
440 }
441
442}
443
444static void get_lane_status_and_drive_settings(
d0778ebf 445 struct dc_link *link,
4562236b
HW		 446 const struct link_training_settings *link_training_setting,
447 union lane_status *ln_status,
448 union lane_align_status_updated *ln_status_updated,
449 struct link_training_settings *req_settings)
450{
451 uint8_t dpcd_buf[6] = {0};
9a6a8075
HW		 452 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
453 struct link_training_settings request_settings = { {0} };
4562236b
HW		 454 uint32_t lane;
455
456 memset(req_settings, '\0', sizeof(struct link_training_settings));
457
458 core_link_read_dpcd(
459 link,
3a340294 460 DP_LANE0_1_STATUS,
4562236b
HW		 461 (uint8_t *)(dpcd_buf),
462 sizeof(dpcd_buf));
463
464 for (lane = 0; lane <
465 (uint32_t)(link_training_setting->link_settings.lane_count);
466 lane++) {
467
468 ln_status[lane].raw =
469 get_nibble_at_index(&dpcd_buf[0], lane);
470 dpcd_lane_adjust[lane].raw =
471 get_nibble_at_index(&dpcd_buf[4], lane);
472 }
473
474 ln_status_updated->raw = dpcd_buf[2];
475
1296423b 476 DC_LOG_HW_LINK_TRAINING("%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
4562236b 477 __func__,
3a340294
DA		 478 DP_LANE0_1_STATUS, dpcd_buf[0],
479 DP_LANE2_3_STATUS, dpcd_buf[1]);
4562236b 480
1296423b 481 DC_LOG_HW_LINK_TRAINING("%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
4562236b 482 __func__,
3a340294 483 DP_ADJUST_REQUEST_LANE0_1,
4562236b 484 dpcd_buf[4],
3a340294 485 DP_ADJUST_REQUEST_LANE2_3,
4562236b
HW		 486 dpcd_buf[5]);
487
488 /*copy to req_settings*/
489 request_settings.link_settings.lane_count =
490 link_training_setting->link_settings.lane_count;
491 request_settings.link_settings.link_rate =
492 link_training_setting->link_settings.link_rate;
493 request_settings.link_settings.link_spread =
494 link_training_setting->link_settings.link_spread;
495
496 for (lane = 0; lane <
497 (uint32_t)(link_training_setting->link_settings.lane_count);
498 lane++) {
499
500 request_settings.lane_settings[lane].VOLTAGE_SWING =
501 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
502 VOLTAGE_SWING_LANE);
503 request_settings.lane_settings[lane].PRE_EMPHASIS =
504 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
505 PRE_EMPHASIS_LANE);
506 }
507
508 /*Note: for postcursor2, read adjusted
509 * postcursor2 settings from*/
510 /*DpcdAddress_AdjustRequestPostCursor2 =
511 *0x020C (not implemented yet)*/
512
513 /* we find the maximum of the requested settings across all lanes*/
514 /* and set this maximum for all lanes*/
515 find_max_drive_settings(&request_settings, req_settings);
516
517 /* if post cursor 2 is needed in the future,
518 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
519 */
520
521}
522
523static void dpcd_set_lane_settings(
d0778ebf 524 struct dc_link *link,
4562236b
HW		 525 const struct link_training_settings *link_training_setting)
526{
527 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
528 uint32_t lane;
529
530 for (lane = 0; lane <
531 (uint32_t)(link_training_setting->
532 link_settings.lane_count);
533 lane++) {
534 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
535 (uint8_t)(link_training_setting->
536 lane_settings[lane].VOLTAGE_SWING);
537 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
538 (uint8_t)(link_training_setting->
539 lane_settings[lane].PRE_EMPHASIS);
540 dpcd_lane[lane].bits.MAX_SWING_REACHED =
541 (link_training_setting->
542 lane_settings[lane].VOLTAGE_SWING ==
543 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
544 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
545 (link_training_setting->
546 lane_settings[lane].PRE_EMPHASIS ==
547 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
548 }
549
550 core_link_write_dpcd(link,
3a340294 551 DP_TRAINING_LANE0_SET,
4562236b
HW		 552 (uint8_t *)(dpcd_lane),
553 link_training_setting->link_settings.lane_count);
554
555 /*
556 if (LTSettings.link.rate == LinkRate_High2)
557 {
558 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
559 for ( uint32_t lane = 0;
560 lane < lane_count_DPMax; lane++)
561 {
562 dpcd_lane2[lane].bits.post_cursor2_set =
563 static_cast<unsigned char>(
564 LTSettings.laneSettings[lane].postCursor2);
565 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
566 }
567 m_pDpcdAccessSrv->WriteDpcdData(
568 DpcdAddress_Lane0Set2,
569 reinterpret_cast<unsigned char*>(dpcd_lane2),
570 LTSettings.link.lanes);
571 }
572 */
573
1296423b 574 DC_LOG_HW_LINK_TRAINING("%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
4562236b 575 __func__,
3a340294 576 DP_TRAINING_LANE0_SET,
4562236b
HW		 577 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
578 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
579 dpcd_lane[0].bits.MAX_SWING_REACHED,
580 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
581
d0778ebf 582 link->cur_lane_setting = link_training_setting->lane_settings[0];
4562236b
HW		 583
584}
585
586static bool is_max_vs_reached(
587 const struct link_training_settings *lt_settings)
588{
589 uint32_t lane;
590 for (lane = 0; lane <
591 (uint32_t)(lt_settings->link_settings.lane_count);
592 lane++) {
593 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
594 == VOLTAGE_SWING_MAX_LEVEL)
595 return true;
596 }
597 return false;
598
599}
600
601void dc_link_dp_set_drive_settings(
d0778ebf 602 struct dc_link *link,
4562236b
HW		 603 struct link_training_settings *lt_settings)
604{
4562236b 605 /* program ASIC PHY settings*/
d0778ebf 606 dp_set_hw_lane_settings(link, lt_settings);
4562236b
HW		 607
608 /* Notify DP sink the PHY settings from source */
d0778ebf 609 dpcd_set_lane_settings(link, lt_settings);
4562236b
HW		 610}
611
612static bool perform_post_lt_adj_req_sequence(
d0778ebf 613 struct dc_link *link,
4562236b
HW		 614 struct link_training_settings *lt_settings)
615{
616 enum dc_lane_count lane_count =
617 lt_settings->link_settings.lane_count;
618
619 uint32_t adj_req_count;
620 uint32_t adj_req_timer;
621 bool req_drv_setting_changed;
622 uint32_t lane;
623
624 req_drv_setting_changed = false;
625 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
626 adj_req_count++) {
627
628 req_drv_setting_changed = false;
629
630 for (adj_req_timer = 0;
631 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
632 adj_req_timer++) {
633
634 struct link_training_settings req_settings;
635 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
636 union lane_align_status_updated
637 dpcd_lane_status_updated;
638
639 get_lane_status_and_drive_settings(
640 link,
641 lt_settings,
642 dpcd_lane_status,
643 &dpcd_lane_status_updated,
644 &req_settings);
645
646 if (dpcd_lane_status_updated.bits.
647 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
648 return true;
649
650 if (!is_cr_done(lane_count, dpcd_lane_status))
651 return false;
652
653 if (!is_ch_eq_done(
654 lane_count,
655 dpcd_lane_status,
656 &dpcd_lane_status_updated))
657 return false;
658
659 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
660
661 if (lt_settings->
662 lane_settings[lane].VOLTAGE_SWING !=
663 req_settings.lane_settings[lane].
664 VOLTAGE_SWING ||
665 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
666 req_settings.lane_settings[lane].PRE_EMPHASIS) {
667
668 req_drv_setting_changed = true;
669 break;
670 }
671 }
672
673 if (req_drv_setting_changed) {
674 update_drive_settings(
9a6a8075 675 lt_settings, req_settings);
4562236b 676
d0778ebf 677 dc_link_dp_set_drive_settings(link,
4562236b
HW		 678 lt_settings);
679 break;
680 }
681
682 msleep(1);
683 }
684
685 if (!req_drv_setting_changed) {
1296423b 686 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
4562236b
HW		 687 __func__);
688
689 ASSERT(0);
690 return true;
691 }
692 }
1296423b 693 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
4562236b
HW		 694 __func__);
695
696 ASSERT(0);
697 return true;
698
699}
700
d0778ebf 701static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
4562236b
HW		 702{
703 enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
704 struct encoder_feature_support *features = &link->link_enc->features;
705 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
706
707 if (features->flags.bits.IS_TPS3_CAPABLE)
708 highest_tp = HW_DP_TRAINING_PATTERN_3;
709
710 if (features->flags.bits.IS_TPS4_CAPABLE)
711 highest_tp = HW_DP_TRAINING_PATTERN_4;
712
713 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
714 highest_tp >= HW_DP_TRAINING_PATTERN_4)
715 return HW_DP_TRAINING_PATTERN_4;
716
717 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
718 highest_tp >= HW_DP_TRAINING_PATTERN_3)
719 return HW_DP_TRAINING_PATTERN_3;
720
721 return HW_DP_TRAINING_PATTERN_2;
722}
723
94405cf6
WL		 724static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
725 union lane_status *dpcd_lane_status)
726{
727 enum link_training_result result = LINK_TRAINING_SUCCESS;
728
729 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
730 result = LINK_TRAINING_CR_FAIL_LANE0;
731 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
732 result = LINK_TRAINING_CR_FAIL_LANE1;
733 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
734 result = LINK_TRAINING_CR_FAIL_LANE23;
735 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
736 result = LINK_TRAINING_CR_FAIL_LANE23;
737 return result;
738}
739
820e3935 740static enum link_training_result perform_channel_equalization_sequence(
d0778ebf 741 struct dc_link *link,
4562236b
HW		 742 struct link_training_settings *lt_settings)
743{
744 struct link_training_settings req_settings;
745 enum hw_dp_training_pattern hw_tr_pattern;
746 uint32_t retries_ch_eq;
747 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
9a6a8075
HW		 748 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
749 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
4562236b
HW		 750
751 hw_tr_pattern = get_supported_tp(link);
752
753 dp_set_hw_training_pattern(link, hw_tr_pattern);
754
755 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
756 retries_ch_eq++) {
757
758 dp_set_hw_lane_settings(link, lt_settings);
759
760 /* 2. update DPCD*/
761 if (!retries_ch_eq)
762 /* EPR #361076 - write as a 5-byte burst,
763 * but only for the 1-st iteration*/
764 dpcd_set_lt_pattern_and_lane_settings(
765 link,
766 lt_settings,
767 hw_tr_pattern);
768 else
769 dpcd_set_lane_settings(link, lt_settings);
770
771 /* 3. wait for receiver to lock-on*/
772 wait_for_training_aux_rd_interval(link, 400);
773
774 /* 4. Read lane status and requested
775 * drive settings as set by the sink*/
776
777 get_lane_status_and_drive_settings(
778 link,
779 lt_settings,
780 dpcd_lane_status,
781 &dpcd_lane_status_updated,
782 &req_settings);
783
784 /* 5. check CR done*/
785 if (!is_cr_done(lane_count, dpcd_lane_status))
820e3935 786 return LINK_TRAINING_EQ_FAIL_CR;
4562236b
HW		 787
788 /* 6. check CHEQ done*/
789 if (is_ch_eq_done(lane_count,
790 dpcd_lane_status,
791 &dpcd_lane_status_updated))
820e3935 792 return LINK_TRAINING_SUCCESS;
4562236b
HW		 793
794 /* 7. update VS/PE/PC2 in lt_settings*/
795 update_drive_settings(lt_settings, req_settings);
796 }
797
820e3935 798 return LINK_TRAINING_EQ_FAIL_EQ;
4562236b
HW		 799
800}
801
94405cf6 802static enum link_training_result perform_clock_recovery_sequence(
d0778ebf 803 struct dc_link *link,
4562236b
HW		 804 struct link_training_settings *lt_settings)
805{
806 uint32_t retries_cr;
807 uint32_t retry_count;
808 uint32_t lane;
809 struct link_training_settings req_settings;
810 enum dc_lane_count lane_count =
811 lt_settings->link_settings.lane_count;
812 enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
813 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
814 union lane_align_status_updated dpcd_lane_status_updated;
815
816 retries_cr = 0;
817 retry_count = 0;
818 /* initial drive setting (VS/PE/PC2)*/
819 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
820 lt_settings->lane_settings[lane].VOLTAGE_SWING =
821 VOLTAGE_SWING_LEVEL0;
822 lt_settings->lane_settings[lane].PRE_EMPHASIS =
823 PRE_EMPHASIS_DISABLED;
824 lt_settings->lane_settings[lane].POST_CURSOR2 =
825 POST_CURSOR2_DISABLED;
826 }
827
828 dp_set_hw_training_pattern(link, hw_tr_pattern);
829
830 /* najeeb - The synaptics MST hub can put the LT in
831 * infinite loop by switching the VS
832 */
833 /* between level 0 and level 1 continuously, here
834 * we try for CR lock for LinkTrainingMaxCRRetry count*/
835 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
836 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
837
838 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
839 memset(&dpcd_lane_status_updated, '\0',
840 sizeof(dpcd_lane_status_updated));
841
842 /* 1. call HWSS to set lane settings*/
843 dp_set_hw_lane_settings(
844 link,
845 lt_settings);
846
847 /* 2. update DPCD of the receiver*/
848 if (!retries_cr)
849 /* EPR #361076 - write as a 5-byte burst,
850 * but only for the 1-st iteration.*/
851 dpcd_set_lt_pattern_and_lane_settings(
852 link,
853 lt_settings,
854 hw_tr_pattern);
855 else
856 dpcd_set_lane_settings(
857 link,
858 lt_settings);
859
860 /* 3. wait receiver to lock-on*/
861 wait_for_training_aux_rd_interval(
862 link,
863 100);
864
865 /* 4. Read lane status and requested drive
866 * settings as set by the sink
867 */
868 get_lane_status_and_drive_settings(
869 link,
870 lt_settings,
871 dpcd_lane_status,
872 &dpcd_lane_status_updated,
873 &req_settings);
874
875 /* 5. check CR done*/
876 if (is_cr_done(lane_count, dpcd_lane_status))
94405cf6 877 return LINK_TRAINING_SUCCESS;
4562236b
HW		 878
879 /* 6. max VS reached*/
880 if (is_max_vs_reached(lt_settings))
94405cf6 881 break;
4562236b
HW		 882
883 /* 7. same voltage*/
884 /* Note: VS same for all lanes,
885 * so comparing first lane is sufficient*/
886 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
887 req_settings.lane_settings[0].VOLTAGE_SWING)
888 retries_cr++;
889 else
890 retries_cr = 0;
891
892 /* 8. update VS/PE/PC2 in lt_settings*/
893 update_drive_settings(lt_settings, req_settings);
894
895 retry_count++;
896 }
897
898 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
899 ASSERT(0);
1296423b 900 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
4f42a2dd 901 __func__,
4562236b
HW		 902 LINK_TRAINING_MAX_CR_RETRY);
903
904 }
905
94405cf6 906 return get_cr_failure(lane_count, dpcd_lane_status);
4562236b
HW		 907}
908
94405cf6 909static inline enum link_training_result perform_link_training_int(
d0778ebf 910 struct dc_link *link,
4562236b 911 struct link_training_settings *lt_settings,
94405cf6 912 enum link_training_result status)
4562236b
HW		 913{
914 union lane_count_set lane_count_set = { {0} };
915 union dpcd_training_pattern dpcd_pattern = { {0} };
916
917 /* 3. set training not in progress*/
918 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
919 dpcd_set_training_pattern(link, dpcd_pattern);
920
921 /* 4. mainlink output idle pattern*/
922 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
923
924 /*
925 * 5. post training adjust if required
926 * If the upstream DPTX and downstream DPRX both support TPS4,
927 * TPS4 must be used instead of POST_LT_ADJ_REQ.
928 */
c30267f5
CL		 929 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
930 get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
4562236b
HW		 931 return status;
932
94405cf6 933 if (status == LINK_TRAINING_SUCCESS &&
4562236b 934 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
94405cf6 935 status = LINK_TRAINING_LQA_FAIL;
4562236b
HW		 936
937 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
938 lane_count_set.bits.ENHANCED_FRAMING = 1;
939 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
940
941 core_link_write_dpcd(
942 link,
3a340294 943 DP_LANE_COUNT_SET,
4562236b
HW		 944 &lane_count_set.raw,
945 sizeof(lane_count_set));
946
947 return status;
948}
949
820e3935 950enum link_training_result dc_link_dp_perform_link_training(
4562236b
HW		 951 struct dc_link *link,
952 const struct dc_link_settings *link_setting,
953 bool skip_video_pattern)
954{
820e3935 955 enum link_training_result status = LINK_TRAINING_SUCCESS;
4562236b
HW		 956
957 char *link_rate = "Unknown";
94405cf6
WL		 958 char *lt_result = "Unknown";
959
4562236b
HW		 960 struct link_training_settings lt_settings;
961
4562236b
HW		 962 memset(&lt_settings, '\0', sizeof(lt_settings));
963
964 lt_settings.link_settings.link_rate = link_setting->link_rate;
965 lt_settings.link_settings.lane_count = link_setting->lane_count;
8628d02f
JP		 966 lt_settings.link_settings.use_link_rate_set = link_setting->use_link_rate_set;
967 lt_settings.link_settings.link_rate_set = link_setting->link_rate_set;
4562236b
HW		 968
969 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
970
971 /* TODO hard coded to SS for now
972 * lt_settings.link_settings.link_spread =
973 * dal_display_path_is_ss_supported(
974 * path_mode->display_path) ?
975 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
976 * LINK_SPREAD_DISABLED;
977 */
ad830e7a
DL		 978 if (link->dp_ss_off)
979 lt_settings.link_settings.link_spread = LINK_SPREAD_DISABLED;
980 else
981 lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
4562236b
HW		 982
983 /* 1. set link rate, lane count and spread*/
d0778ebf 984 dpcd_set_link_settings(link, &lt_settings);
4562236b
HW		 985
986 /* 2. perform link training (set link training done
987 * to false is done as well)*/
94405cf6
WL		 988 status = perform_clock_recovery_sequence(link, &lt_settings);
989 if (status == LINK_TRAINING_SUCCESS) {
d0778ebf 990 status = perform_channel_equalization_sequence(link,
820e3935 991 &lt_settings);
4562236b
HW		 992 }
993
820e3935 994 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
94405cf6 995 status = perform_link_training_int(link,
820e3935 996 &lt_settings,
94405cf6 997 status);
820e3935 998 }
4562236b
HW		 999
1000 /* 6. print status message*/
1001 switch (lt_settings.link_settings.link_rate) {
1002
1003 case LINK_RATE_LOW:
1004 link_rate = "RBR";
1005 break;
1006 case LINK_RATE_HIGH:
1007 link_rate = "HBR";
1008 break;
1009 case LINK_RATE_HIGH2:
1010 link_rate = "HBR2";
1011 break;
1012 case LINK_RATE_RBR2:
1013 link_rate = "RBR2";
1014 break;
1015 case LINK_RATE_HIGH3:
1016 link_rate = "HBR3";
1017 break;
1018 default:
1019 break;
1020 }
1021
94405cf6
WL		 1022 switch (status) {
1023 case LINK_TRAINING_SUCCESS:
1024 lt_result = "pass";
1025 break;
1026 case LINK_TRAINING_CR_FAIL_LANE0:
1027 lt_result = "CR failed lane0";
1028 break;
1029 case LINK_TRAINING_CR_FAIL_LANE1:
1030 lt_result = "CR failed lane1";
1031 break;
1032 case LINK_TRAINING_CR_FAIL_LANE23:
1033 lt_result = "CR failed lane23";
1034 break;
1035 case LINK_TRAINING_EQ_FAIL_CR:
1036 lt_result = "CR failed in EQ";
1037 break;
1038 case LINK_TRAINING_EQ_FAIL_EQ:
1039 lt_result = "EQ failed";
1040 break;
1041 case LINK_TRAINING_LQA_FAIL:
1042 lt_result = "LQA failed";
1043 break;
1044 default:
1045 break;
1046 }
1047
4562236b 1048 /* Connectivity log: link training */
d0778ebf 1049 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
4562236b
HW		 1050 link_rate,
1051 lt_settings.link_settings.lane_count,
94405cf6 1052 lt_result,
4562236b
HW		 1053 lt_settings.lane_settings[0].VOLTAGE_SWING,
1054 lt_settings.lane_settings[0].PRE_EMPHASIS);
1055
d6e75df4 1056 if (status != LINK_TRAINING_SUCCESS)
cfd84fd3 1057 link->ctx->dc->debug_data.ltFailCount++;
d6e75df4 1058
4562236b
HW		 1059 return status;
1060}
1061
1062
1063bool perform_link_training_with_retries(
d0778ebf 1064 struct dc_link *link,
4562236b
HW		 1065 const struct dc_link_settings *link_setting,
1066 bool skip_video_pattern,
1067 int attempts)
1068{
1069 uint8_t j;
1070 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1071
1072 for (j = 0; j < attempts; ++j) {
1073
1074 if (dc_link_dp_perform_link_training(
d0778ebf 1075 link,
4562236b 1076 link_setting,
820e3935 1077 skip_video_pattern) == LINK_TRAINING_SUCCESS)
4562236b
HW		 1078 return true;
1079
1080 msleep(delay_between_attempts);
1081 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1082 }
1083
1084 return false;
1085}
1086
d0778ebf 1087static struct dc_link_settings get_max_link_cap(struct dc_link *link)
4562236b
HW		 1088{
1089 /* Set Default link settings */
1090 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
8628d02f 1091 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
4562236b
HW		 1092
1093 /* Higher link settings based on feature supported */
1094 if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1095 max_link_cap.link_rate = LINK_RATE_HIGH2;
1096
1097 if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1098 max_link_cap.link_rate = LINK_RATE_HIGH3;
1099
1100 /* Lower link settings based on sink's link cap */
d0778ebf 1101 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
4562236b 1102 max_link_cap.lane_count =
d0778ebf
HW		 1103 link->reported_link_cap.lane_count;
1104 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
4562236b 1105 max_link_cap.link_rate =
d0778ebf
HW		 1106 link->reported_link_cap.link_rate;
1107 if (link->reported_link_cap.link_spread <
4562236b
HW		 1108 max_link_cap.link_spread)
1109 max_link_cap.link_spread =
d0778ebf 1110 link->reported_link_cap.link_spread;
4562236b
HW		 1111 return max_link_cap;
1112}
1113
1ae62f31
WL		 1114static enum dc_status read_hpd_rx_irq_data(
1115 struct dc_link *link,
1116 union hpd_irq_data *irq_data)
1117{
1118 static enum dc_status retval;
1119
1120 /* The HW reads 16 bytes from 200h on HPD,
1121 * but if we get an AUX_DEFER, the HW cannot retry
1122 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1123 * fail, so we now explicitly read 6 bytes which is
1124 * the req from the above mentioned test cases.
1125 *
1126 * For DP 1.4 we need to read those from 2002h range.
1127 */
1128 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1129 retval = core_link_read_dpcd(
1130 link,
1131 DP_SINK_COUNT,
1132 irq_data->raw,
1133 sizeof(union hpd_irq_data));
1134 else {
1135 /* Read 14 bytes in a single read and then copy only the required fields.
1136 * This is more efficient than doing it in two separate AUX reads. */
1137
1138 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1139
1140 retval = core_link_read_dpcd(
1141 link,
1142 DP_SINK_COUNT_ESI,
1143 tmp,
1144 sizeof(tmp));
1145
1146 if (retval != DC_OK)
1147 return retval;
1148
1149 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1150 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1151 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1152 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1153 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1154 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1155 }
1156
1157 return retval;
1158}
1159
1160static bool hpd_rx_irq_check_link_loss_status(
1161 struct dc_link *link,
1162 union hpd_irq_data *hpd_irq_dpcd_data)
1163{
1164 uint8_t irq_reg_rx_power_state = 0;
1165 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1166 union lane_status lane_status;
1167 uint32_t lane;
1168 bool sink_status_changed;
1169 bool return_code;
1170
1171 sink_status_changed = false;
1172 return_code = false;
1173
1174 if (link->cur_link_settings.lane_count == 0)
1175 return return_code;
1176
1177 /*1. Check that Link Status changed, before re-training.*/
1178
1179 /*parse lane status*/
1180 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1181 /* check status of lanes 0,1
1182 * changed DpcdAddress_Lane01Status (0x202)
1183 */
1184 lane_status.raw = get_nibble_at_index(
1185 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1186 lane);
1187
1188 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1189 !lane_status.bits.CR_DONE_0 ||
1190 !lane_status.bits.SYMBOL_LOCKED_0) {
1191 /* if one of the channel equalization, clock
1192 * recovery or symbol lock is dropped
1193 * consider it as (link has been
1194 * dropped) dp sink status has changed
1195 */
1196 sink_status_changed = true;
1197 break;
1198 }
1199 }
1200
1201 /* Check interlane align.*/
1202 if (sink_status_changed ||
1203 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1204
1205 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1206
1207 return_code = true;
1208
1209 /*2. Check that we can handle interrupt: Not in FS DOS,
1210 * Not in "Display Timeout" state, Link is trained.
1211 */
1212 dpcd_result = core_link_read_dpcd(link,
1213 DP_SET_POWER,
1214 &irq_reg_rx_power_state,
1215 sizeof(irq_reg_rx_power_state));
1216
1217 if (dpcd_result != DC_OK) {
1218 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1219 __func__);
1220 } else {
1221 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1222 return_code = false;
1223 }
1224 }
1225
1226 return return_code;
1227}
1228
aafded88 1229bool dp_verify_link_cap(
d0778ebf 1230 struct dc_link *link,
824474ba
BL		 1231 struct dc_link_settings *known_limit_link_setting,
1232 int *fail_count)
4562236b
HW		 1233{
1234 struct dc_link_settings max_link_cap = {0};
820e3935
DW		 1235 struct dc_link_settings cur_link_setting = {0};
1236 struct dc_link_settings *cur = &cur_link_setting;
1237 struct dc_link_settings initial_link_settings = {0};
4562236b
HW		 1238 bool success;
1239 bool skip_link_training;
4562236b 1240 bool skip_video_pattern;
4562236b
HW		 1241 struct clock_source *dp_cs;
1242 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
820e3935 1243 enum link_training_result status;
1ae62f31 1244 union hpd_irq_data irq_data;
4562236b 1245
aafded88
TC		 1246 if (link->dc->debug.skip_detection_link_training) {
1247 link->verified_link_cap = *known_limit_link_setting;
1248 return true;
1249 }
1250
1ae62f31 1251 memset(&irq_data, 0, sizeof(irq_data));
4562236b
HW		 1252 success = false;
1253 skip_link_training = false;
1254
1255 max_link_cap = get_max_link_cap(link);
1256
1257 /* TODO implement override and monitor patch later */
1258
1259 /* try to train the link from high to low to
1260 * find the physical link capability
1261 */
1262 /* disable PHY done possible by BIOS, will be done by driver itself */
d0778ebf 1263 dp_disable_link_phy(link, link->connector_signal);
4562236b
HW		 1264
1265 dp_cs = link->dc->res_pool->dp_clock_source;
1266
1267 if (dp_cs)
1268 dp_cs_id = dp_cs->id;
1269 else {
1270 /*
1271 * dp clock source is not initialized for some reason.
1272 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1273 */
1274 ASSERT(dp_cs);
1275 }
1276
820e3935
DW		 1277 /* link training starts with the maximum common settings
1278 * supported by both sink and ASIC.
1279 */
1280 initial_link_settings = get_common_supported_link_settings(
1281 *known_limit_link_setting,
1282 max_link_cap);
1283 cur_link_setting = initial_link_settings;
1284 do {
4562236b 1285 skip_video_pattern = true;
820e3935 1286
4562236b
HW		 1287 if (cur->link_rate == LINK_RATE_LOW)
1288 skip_video_pattern = false;
1289
1290 dp_enable_link_phy(
1291 link,
d0778ebf 1292 link->connector_signal,
4562236b
HW		 1293 dp_cs_id,
1294 cur);
1295
94405cf6 1296
4562236b
HW		 1297 if (skip_link_training)
1298 success = true;
1299 else {
820e3935 1300 status = dc_link_dp_perform_link_training(
d0778ebf 1301 link,
4562236b
HW		 1302 cur,
1303 skip_video_pattern);
820e3935
DW		 1304 if (status == LINK_TRAINING_SUCCESS)
1305 success = true;
824474ba
BL		 1306 else
1307 (*fail_count)++;
4562236b
HW		 1308 }
1309
1ae62f31 1310 if (success) {
d0778ebf 1311 link->verified_link_cap = *cur;
1ae62f31
WL		 1312 udelay(1000);
1313 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
1314 if (hpd_rx_irq_check_link_loss_status(
1315 link,
1316 &irq_data))
1317 (*fail_count)++;
1318 }
4562236b
HW		 1319 /* always disable the link before trying another
1320 * setting or before returning we'll enable it later
1321 * based on the actual mode we're driving
1322 */
d0778ebf 1323 dp_disable_link_phy(link, link->connector_signal);
820e3935
DW		 1324 } while (!success && decide_fallback_link_setting(
1325 initial_link_settings, cur, status));
4562236b
HW		 1326
1327 /* Link Training failed for all Link Settings
1328 * (Lane Count is still unknown)
1329 */
1330 if (!success) {
1331 /* If all LT fails for all settings,
1332 * set verified = failed safe (1 lane low)
1333 */
d0778ebf
HW		 1334 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1335 link->verified_link_cap.link_rate = LINK_RATE_LOW;
4562236b 1336
d0778ebf 1337 link->verified_link_cap.link_spread =
4562236b
HW		 1338 LINK_SPREAD_DISABLED;
1339 }
1340
4562236b
HW		 1341
1342 return success;
1343}
1344
9a6a8075 1345static struct dc_link_settings get_common_supported_link_settings(
820e3935
DW		 1346 struct dc_link_settings link_setting_a,
1347 struct dc_link_settings link_setting_b)
1348{
1349 struct dc_link_settings link_settings = {0};
1350
1351 link_settings.lane_count =
1352 (link_setting_a.lane_count <=
1353 link_setting_b.lane_count) ?
1354 link_setting_a.lane_count :
1355 link_setting_b.lane_count;
1356 link_settings.link_rate =
1357 (link_setting_a.link_rate <=
1358 link_setting_b.link_rate) ?
1359 link_setting_a.link_rate :
1360 link_setting_b.link_rate;
1361 link_settings.link_spread = LINK_SPREAD_DISABLED;
1362
1363 /* in DP compliance test, DPR-120 may have
1364 * a random value in its MAX_LINK_BW dpcd field.
1365 * We map it to the maximum supported link rate that
1366 * is smaller than MAX_LINK_BW in this case.
1367 */
1368 if (link_settings.link_rate > LINK_RATE_HIGH3) {
1369 link_settings.link_rate = LINK_RATE_HIGH3;
1370 } else if (link_settings.link_rate < LINK_RATE_HIGH3
1371 && link_settings.link_rate > LINK_RATE_HIGH2) {
1372 link_settings.link_rate = LINK_RATE_HIGH2;
1373 } else if (link_settings.link_rate < LINK_RATE_HIGH2
1374 && link_settings.link_rate > LINK_RATE_HIGH) {
1375 link_settings.link_rate = LINK_RATE_HIGH;
1376 } else if (link_settings.link_rate < LINK_RATE_HIGH
1377 && link_settings.link_rate > LINK_RATE_LOW) {
1378 link_settings.link_rate = LINK_RATE_LOW;
1379 } else if (link_settings.link_rate < LINK_RATE_LOW) {
1380 link_settings.link_rate = LINK_RATE_UNKNOWN;
1381 }
1382
1383 return link_settings;
1384}
1385
450619d3 1386static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 1387{
1388 return lane_count <= LANE_COUNT_ONE;
1389}
1390
450619d3 1391static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 1392{
1393 return link_rate <= LINK_RATE_LOW;
1394}
1395
44858055 1396static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 1397{
1398 switch (lane_count) {
1399 case LANE_COUNT_FOUR:
1400 return LANE_COUNT_TWO;
1401 case LANE_COUNT_TWO:
1402 return LANE_COUNT_ONE;
1403 case LANE_COUNT_ONE:
1404 return LANE_COUNT_UNKNOWN;
1405 default:
1406 return LANE_COUNT_UNKNOWN;
1407 }
1408}
1409
04e21292 1410static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 1411{
1412 switch (link_rate) {
1413 case LINK_RATE_HIGH3:
1414 return LINK_RATE_HIGH2;
1415 case LINK_RATE_HIGH2:
1416 return LINK_RATE_HIGH;
1417 case LINK_RATE_HIGH:
1418 return LINK_RATE_LOW;
1419 case LINK_RATE_LOW:
1420 return LINK_RATE_UNKNOWN;
1421 default:
1422 return LINK_RATE_UNKNOWN;
1423 }
1424}
1425
04e21292 1426static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
8c4abe0b
DW		 1427{
1428 switch (lane_count) {
1429 case LANE_COUNT_ONE:
1430 return LANE_COUNT_TWO;
1431 case LANE_COUNT_TWO:
1432 return LANE_COUNT_FOUR;
1433 default:
1434 return LANE_COUNT_UNKNOWN;
1435 }
1436}
1437
04e21292 1438static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
8c4abe0b
DW		 1439{
1440 switch (link_rate) {
1441 case LINK_RATE_LOW:
1442 return LINK_RATE_HIGH;
1443 case LINK_RATE_HIGH:
1444 return LINK_RATE_HIGH2;
1445 case LINK_RATE_HIGH2:
1446 return LINK_RATE_HIGH3;
1447 default:
1448 return LINK_RATE_UNKNOWN;
1449 }
1450}
1451
820e3935
DW		 1452/*
1453 * function: set link rate and lane count fallback based
1454 * on current link setting and last link training result
1455 * return value:
1456 * true - link setting could be set
1457 * false - has reached minimum setting
1458 * and no further fallback could be done
1459 */
04e21292 1460static bool decide_fallback_link_setting(
820e3935
DW		 1461 struct dc_link_settings initial_link_settings,
1462 struct dc_link_settings *current_link_setting,
1463 enum link_training_result training_result)
1464{
1465 if (!current_link_setting)
1466 return false;
1467
1468 switch (training_result) {
94405cf6
WL		 1469 case LINK_TRAINING_CR_FAIL_LANE0:
1470 case LINK_TRAINING_CR_FAIL_LANE1:
1471 case LINK_TRAINING_CR_FAIL_LANE23:
1472 case LINK_TRAINING_LQA_FAIL:
820e3935
DW		 1473 {
1474 if (!reached_minimum_link_rate
1475 (current_link_setting->link_rate)) {
1476 current_link_setting->link_rate =
1477 reduce_link_rate(
1478 current_link_setting->link_rate);
1479 } else if (!reached_minimum_lane_count
1480 (current_link_setting->lane_count)) {
1481 current_link_setting->link_rate =
1482 initial_link_settings.link_rate;
94405cf6
WL		 1483 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
1484 return false;
1485 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
1486 current_link_setting->lane_count =
1487 LANE_COUNT_ONE;
1488 else if (training_result ==
1489 LINK_TRAINING_CR_FAIL_LANE23)
1490 current_link_setting->lane_count =
1491 LANE_COUNT_TWO;
1492 else
1493 current_link_setting->lane_count =
1494 reduce_lane_count(
820e3935
DW		 1495 current_link_setting->lane_count);
1496 } else {
1497 return false;
1498 }
1499 break;
1500 }
1501 case LINK_TRAINING_EQ_FAIL_EQ:
1502 {
1503 if (!reached_minimum_lane_count
1504 (current_link_setting->lane_count)) {
1505 current_link_setting->lane_count =
1506 reduce_lane_count(
1507 current_link_setting->lane_count);
1508 } else if (!reached_minimum_link_rate
1509 (current_link_setting->link_rate)) {
820e3935
DW		 1510 current_link_setting->link_rate =
1511 reduce_link_rate(
1512 current_link_setting->link_rate);
1513 } else {
1514 return false;
1515 }
1516 break;
1517 }
1518 case LINK_TRAINING_EQ_FAIL_CR:
1519 {
1520 if (!reached_minimum_link_rate
1521 (current_link_setting->link_rate)) {
1522 current_link_setting->link_rate =
1523 reduce_link_rate(
1524 current_link_setting->link_rate);
1525 } else {
1526 return false;
1527 }
1528 break;
1529 }
1530 default:
1531 return false;
1532 }
1533 return true;
1534}
1535
4562236b
HW		 1536static uint32_t bandwidth_in_kbps_from_timing(
1537 const struct dc_crtc_timing *timing)
1538{
1539 uint32_t bits_per_channel = 0;
1540 uint32_t kbps;
4562236b 1541
50834eb4
HW		 1542 switch (timing->display_color_depth) {
1543 case COLOR_DEPTH_666:
1544 bits_per_channel = 6;
1545 break;
1546 case COLOR_DEPTH_888:
1547 bits_per_channel = 8;
1548 break;
1549 case COLOR_DEPTH_101010:
1550 bits_per_channel = 10;
1551 break;
1552 case COLOR_DEPTH_121212:
4562236b 1553 bits_per_channel = 12;
50834eb4
HW		 1554 break;
1555 case COLOR_DEPTH_141414:
1556 bits_per_channel = 14;
1557 break;
1558 case COLOR_DEPTH_161616:
1559 bits_per_channel = 16;
1560 break;
1561 default:
1562 break;
4562236b 1563 }
50834eb4 1564
4562236b
HW		 1565 ASSERT(bits_per_channel != 0);
1566
380604e2 1567 kbps = timing->pix_clk_100hz / 10;
4562236b
HW		 1568 kbps *= bits_per_channel;
1569
cf65ebeb 1570 if (timing->flags.Y_ONLY != 1) {
4562236b
HW		 1571 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
1572 kbps *= 3;
cf65ebeb
EY		 1573 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1574 kbps /= 2;
1575 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1576 kbps = kbps * 2 / 3;
1577 }
4562236b
HW		 1578
1579 return kbps;
1580
1581}
1582
1583static uint32_t bandwidth_in_kbps_from_link_settings(
1584 const struct dc_link_settings *link_setting)
1585{
1586 uint32_t link_rate_in_kbps = link_setting->link_rate *
1587 LINK_RATE_REF_FREQ_IN_KHZ;
1588
1589 uint32_t lane_count = link_setting->lane_count;
1590 uint32_t kbps = link_rate_in_kbps;
9a6a8075 1591
4562236b
HW		 1592 kbps *= lane_count;
1593 kbps *= 8; /* 8 bits per byte*/
1594
1595 return kbps;
1596
1597}
1598
1599bool dp_validate_mode_timing(
d0778ebf 1600 struct dc_link *link,
4562236b
HW		 1601 const struct dc_crtc_timing *timing)
1602{
1603 uint32_t req_bw;
1604 uint32_t max_bw;
1605
1606 const struct dc_link_settings *link_setting;
1607
1608 /*always DP fail safe mode*/
380604e2 1609 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
9a6a8075
HW		 1610 timing->h_addressable == (uint32_t) 640 &&
1611 timing->v_addressable == (uint32_t) 480)
4562236b
HW		 1612 return true;
1613
1614 /* We always use verified link settings */
d0778ebf 1615 link_setting = &link->verified_link_cap;
4562236b
HW		 1616
1617 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1618 /*if (flags.DYNAMIC_VALIDATION == 1 &&
d0778ebf
HW		 1619 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
1620 link_setting = &link->verified_link_cap;
4562236b
HW		 1621 */
1622
1623 req_bw = bandwidth_in_kbps_from_timing(timing);
1624 max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
1625
1626 if (req_bw <= max_bw) {
1627 /* remember the biggest mode here, during
1628 * initial link training (to get
1629 * verified_link_cap), LS sends event about
1630 * cannot train at reported cap to upper
1631 * layer and upper layer will re-enumerate modes.
1632 * this is not necessary if the lower
1633 * verified_link_cap is enough to drive
1634 * all the modes */
1635
1636 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1637 /* if (flags.DYNAMIC_VALIDATION == 1)
1638 dpsst->max_req_bw_for_verified_linkcap = dal_max(
1639 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
1640 return true;
1641 } else
1642 return false;
1643}
1644
8628d02f 1645static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
4562236b 1646{
8c4abe0b 1647 struct dc_link_settings initial_link_setting = {
8628d02f 1648 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
8c4abe0b
DW		 1649 struct dc_link_settings current_link_setting =
1650 initial_link_setting;
4562236b 1651 uint32_t link_bw;
4562236b 1652
8628d02f
JP		 1653 /* search for the minimum link setting that:
1654 * 1. is supported according to the link training result
1655 * 2. could support the b/w requested by the timing
4562236b 1656 */
8628d02f
JP		 1657 while (current_link_setting.link_rate <=
1658 link->verified_link_cap.link_rate) {
1659 link_bw = bandwidth_in_kbps_from_link_settings(
1660 &current_link_setting);
1661 if (req_bw <= link_bw) {
1662 *link_setting = current_link_setting;
1663 return true;
1664 }
4562236b 1665
8628d02f
JP		 1666 if (current_link_setting.lane_count <
1667 link->verified_link_cap.lane_count) {
1668 current_link_setting.lane_count =
1669 increase_lane_count(
1670 current_link_setting.lane_count);
1671 } else {
1672 current_link_setting.link_rate =
1673 increase_link_rate(
1674 current_link_setting.link_rate);
1675 current_link_setting.lane_count =
1676 initial_link_setting.lane_count;
1677 }
3f1f74f4
JZ		 1678 }
1679
8628d02f
JP		 1680 return false;
1681}
1682
1683static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
1684{
1685 struct dc_link_settings initial_link_setting;
1686 struct dc_link_settings current_link_setting;
1687 uint32_t link_bw;
1688
1689 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
1690 link->dpcd_caps.edp_supported_link_rates_count == 0 ||
1691 link->dc->config.optimize_edp_link_rate == false) {
4d2f22d1 1692 *link_setting = link->verified_link_cap;
8628d02f 1693 return true;
4d2f22d1
HH		 1694 }
1695
8628d02f
JP		 1696 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
1697 initial_link_setting.lane_count = LANE_COUNT_ONE;
1698 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
1699 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
1700 initial_link_setting.use_link_rate_set = true;
1701 initial_link_setting.link_rate_set = 0;
1702 current_link_setting = initial_link_setting;
1703
5667ff5c
DA		 1704 /* search for the minimum link setting that:
1705 * 1. is supported according to the link training result
1706 * 2. could support the b/w requested by the timing
1707 */
8c4abe0b 1708 while (current_link_setting.link_rate <=
4654a2f7 1709 link->verified_link_cap.link_rate) {
4562236b 1710 link_bw = bandwidth_in_kbps_from_link_settings(
8c4abe0b
DW		 1711 &current_link_setting);
1712 if (req_bw <= link_bw) {
1713 *link_setting = current_link_setting;
8628d02f 1714 return true;
4562236b 1715 }
4562236b 1716
8c4abe0b 1717 if (current_link_setting.lane_count <
4654a2f7 1718 link->verified_link_cap.lane_count) {
8c4abe0b
DW		 1719 current_link_setting.lane_count =
1720 increase_lane_count(
1721 current_link_setting.lane_count);
1722 } else {
8628d02f
JP		 1723 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
1724 current_link_setting.link_rate_set++;
1725 current_link_setting.link_rate =
1726 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
1727 current_link_setting.lane_count =
1728 initial_link_setting.lane_count;
1729 } else
1730 break;
4562236b
HW		 1731 }
1732 }
8628d02f
JP		 1733 return false;
1734}
1735
1736void decide_link_settings(struct dc_stream_state *stream,
1737 struct dc_link_settings *link_setting)
1738{
1739 struct dc_link *link;
1740 uint32_t req_bw;
1741
1742 req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
1743
1744 link = stream->link;
1745
1746 /* if preferred is specified through AMDDP, use it, if it's enough
1747 * to drive the mode
1748 */
1749 if (link->preferred_link_setting.lane_count !=
1750 LANE_COUNT_UNKNOWN &&
1751 link->preferred_link_setting.link_rate !=
1752 LINK_RATE_UNKNOWN) {
1753 *link_setting = link->preferred_link_setting;
1754 return;
1755 }
1756
1757 /* MST doesn't perform link training for now
1758 * TODO: add MST specific link training routine
1759 */
1760 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1761 *link_setting = link->verified_link_cap;
1762 return;
1763 }
1764
1765 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1766 if (decide_edp_link_settings(link, link_setting, req_bw))
1767 return;
1768 } else if (decide_dp_link_settings(link, link_setting, req_bw))
1769 return;
4562236b
HW		 1770
1771 BREAK_TO_DEBUGGER();
d0778ebf 1772 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
4562236b 1773
d0778ebf 1774 *link_setting = link->verified_link_cap;
4562236b
HW		 1775}
1776
1777/*************************Short Pulse IRQ***************************/
d0778ebf 1778static bool allow_hpd_rx_irq(const struct dc_link *link)
4562236b
HW		 1779{
1780 /*
1781 * Don't handle RX IRQ unless one of following is met:
1782 * 1) The link is established (cur_link_settings != unknown)
1783 * 2) We kicked off MST detection
1784 * 3) We know we're dealing with an active dongle
1785 */
1786
d0778ebf
HW		 1787 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1788 (link->type == dc_connection_mst_branch) ||
4562236b
HW		 1789 is_dp_active_dongle(link))
1790 return true;
1791
1792 return false;
1793}
1794
d0778ebf 1795static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
4562236b
HW		 1796{
1797 union dpcd_psr_configuration psr_configuration;
1798
94267b3d 1799 if (!link->psr_enabled)
4562236b
HW		 1800 return false;
1801
7c7f5b15
AG		 1802 dm_helpers_dp_read_dpcd(
1803 link->ctx,
d0778ebf 1804 link,
7c7f5b15
AG		 1805 368,/*DpcdAddress_PSR_Enable_Cfg*/
1806 &psr_configuration.raw,
1807 sizeof(psr_configuration.raw));
1808
4562236b
HW		 1809
1810 if (psr_configuration.bits.ENABLE) {
1811 unsigned char dpcdbuf[3] = {0};
1812 union psr_error_status psr_error_status;
1813 union psr_sink_psr_status psr_sink_psr_status;
1814
7c7f5b15
AG		 1815 dm_helpers_dp_read_dpcd(
1816 link->ctx,
d0778ebf 1817 link,
7c7f5b15
AG		 1818 0x2006, /*DpcdAddress_PSR_Error_Status*/
1819 (unsigned char *) dpcdbuf,
1820 sizeof(dpcdbuf));
4562236b
HW		 1821
1822 /*DPCD 2006h ERROR STATUS*/
1823 psr_error_status.raw = dpcdbuf[0];
1824 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
1825 psr_sink_psr_status.raw = dpcdbuf[2];
1826
1827 if (psr_error_status.bits.LINK_CRC_ERROR ||
1828 psr_error_status.bits.RFB_STORAGE_ERROR) {
1829 /* Acknowledge and clear error bits */
7c7f5b15
AG		 1830 dm_helpers_dp_write_dpcd(
1831 link->ctx,
d0778ebf 1832 link,
7c7f5b15 1833 8198,/*DpcdAddress_PSR_Error_Status*/
4562236b
HW		 1834 &psr_error_status.raw,
1835 sizeof(psr_error_status.raw));
1836
1837 /* PSR error, disable and re-enable PSR */
c7299705
CL		 1838 dc_link_set_psr_enable(link, false, true);
1839 dc_link_set_psr_enable(link, true, true);
4562236b
HW		 1840
1841 return true;
1842 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
1843 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
1844 /* No error is detect, PSR is active.
1845 * We should return with IRQ_HPD handled without
1846 * checking for loss of sync since PSR would have
1847 * powered down main link.
1848 */
1849 return true;
1850 }
1851 }
1852 return false;
1853}
1854
d0778ebf 1855static void dp_test_send_link_training(struct dc_link *link)
4562236b 1856{
73c72602 1857 struct dc_link_settings link_settings = {0};
4562236b
HW		 1858
1859 core_link_read_dpcd(
1860 link,
3a340294 1861 DP_TEST_LANE_COUNT,
4562236b
HW		 1862 (unsigned char *)(&link_settings.lane_count),
1863 1);
1864 core_link_read_dpcd(
1865 link,
3a340294 1866 DP_TEST_LINK_RATE,
4562236b
HW		 1867 (unsigned char *)(&link_settings.link_rate),
1868 1);
1869
1870 /* Set preferred link settings */
d0778ebf
HW		 1871 link->verified_link_cap.lane_count = link_settings.lane_count;
1872 link->verified_link_cap.link_rate = link_settings.link_rate;
4562236b 1873
73c72602 1874 dp_retrain_link_dp_test(link, &link_settings, false);
4562236b
HW		 1875}
1876
9315e239 1877/* TODO Raven hbr2 compliance eye output is unstable
25bab0da
WL		 1878 * (toggling on and off) with debugger break
1879 * This caueses intermittent PHY automation failure
1880 * Need to look into the root cause */
d0778ebf 1881static void dp_test_send_phy_test_pattern(struct dc_link *link)
4562236b
HW		 1882{
1883 union phy_test_pattern dpcd_test_pattern;
1884 union lane_adjust dpcd_lane_adjustment[2];
1885 unsigned char dpcd_post_cursor_2_adjustment = 0;
1886 unsigned char test_80_bit_pattern[
3a340294
DA		 1887 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1888 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
4562236b
HW		 1889 enum dp_test_pattern test_pattern;
1890 struct dc_link_training_settings link_settings;
1891 union lane_adjust dpcd_lane_adjust;
1892 unsigned int lane;
1893 struct link_training_settings link_training_settings;
1894 int i = 0;
1895
1896 dpcd_test_pattern.raw = 0;
1897 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
1898 memset(&link_settings, 0, sizeof(link_settings));
1899
1900 /* get phy test pattern and pattern parameters from DP receiver */
1901 core_link_read_dpcd(
1902 link,
3a340294 1903 DP_TEST_PHY_PATTERN,
4562236b
HW		 1904 &dpcd_test_pattern.raw,
1905 sizeof(dpcd_test_pattern));
1906 core_link_read_dpcd(
1907 link,
3a340294 1908 DP_ADJUST_REQUEST_LANE0_1,
4562236b
HW		 1909 &dpcd_lane_adjustment[0].raw,
1910 sizeof(dpcd_lane_adjustment));
1911
1912 /*get post cursor 2 parameters
1913 * For DP 1.1a or eariler, this DPCD register's value is 0
1914 * For DP 1.2 or later:
1915 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
1916 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
1917 */
1918 core_link_read_dpcd(
1919 link,
3a340294 1920 DP_ADJUST_REQUEST_POST_CURSOR2,
4562236b
HW		 1921 &dpcd_post_cursor_2_adjustment,
1922 sizeof(dpcd_post_cursor_2_adjustment));
1923
1924 /* translate request */
1925 switch (dpcd_test_pattern.bits.PATTERN) {
1926 case PHY_TEST_PATTERN_D10_2:
1927 test_pattern = DP_TEST_PATTERN_D102;
0e19401f 1928 break;
4562236b
HW		 1929 case PHY_TEST_PATTERN_SYMBOL_ERROR:
1930 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 1931 break;
4562236b
HW		 1932 case PHY_TEST_PATTERN_PRBS7:
1933 test_pattern = DP_TEST_PATTERN_PRBS7;
0e19401f 1934 break;
4562236b
HW		 1935 case PHY_TEST_PATTERN_80BIT_CUSTOM:
1936 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 1937 break;
1938 case PHY_TEST_PATTERN_CP2520_1:
25bab0da 1939 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 1940 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 1941 DP_TEST_PATTERN_TRAINING_PATTERN4 :
1942 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 1943 break;
1944 case PHY_TEST_PATTERN_CP2520_2:
25bab0da 1945 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 1946 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 1947 DP_TEST_PATTERN_TRAINING_PATTERN4 :
1948 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 1949 break;
1950 case PHY_TEST_PATTERN_CP2520_3:
78e685f9 1951 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
0e19401f 1952 break;
4562236b
HW		 1953 default:
1954 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1955 break;
1956 }
1957
1958 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
1959 core_link_read_dpcd(
1960 link,
3a340294 1961 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
4562236b
HW		 1962 test_80_bit_pattern,
1963 sizeof(test_80_bit_pattern));
1964
1965 /* prepare link training settings */
d0778ebf 1966 link_settings.link = link->cur_link_settings;
4562236b
HW		 1967
1968 for (lane = 0; lane <
d0778ebf 1969 (unsigned int)(link->cur_link_settings.lane_count);
4562236b
HW		 1970 lane++) {
1971 dpcd_lane_adjust.raw =
1972 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
1973 link_settings.lane_settings[lane].VOLTAGE_SWING =
1974 (enum dc_voltage_swing)
1975 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
1976 link_settings.lane_settings[lane].PRE_EMPHASIS =
1977 (enum dc_pre_emphasis)
1978 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
1979 link_settings.lane_settings[lane].POST_CURSOR2 =
1980 (enum dc_post_cursor2)
1981 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
1982 }
1983
1984 for (i = 0; i < 4; i++)
1985 link_training_settings.lane_settings[i] =
1986 link_settings.lane_settings[i];
1987 link_training_settings.link_settings = link_settings.link;
1988 link_training_settings.allow_invalid_msa_timing_param = false;
1989 /*Usage: Measure DP physical lane signal
1990 * by DP SI test equipment automatically.
1991 * PHY test pattern request is generated by equipment via HPD interrupt.
1992 * HPD needs to be active all the time. HPD should be active
1993 * all the time. Do not touch it.
1994 * forward request to DS
1995 */
1996 dc_link_dp_set_test_pattern(
d0778ebf 1997 link,
4562236b
HW		 1998 test_pattern,
1999 &link_training_settings,
2000 test_80_bit_pattern,
3a340294
DA		 2001 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2002 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
4562236b
HW		 2003}
2004
d0778ebf 2005static void dp_test_send_link_test_pattern(struct dc_link *link)
4562236b
HW		 2006{
2007 union link_test_pattern dpcd_test_pattern;
2008 union test_misc dpcd_test_params;
2009 enum dp_test_pattern test_pattern;
2010
2011 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2012 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2013
2014 /* get link test pattern and pattern parameters */
2015 core_link_read_dpcd(
2016 link,
3a340294 2017 DP_TEST_PATTERN,
4562236b
HW		 2018 &dpcd_test_pattern.raw,
2019 sizeof(dpcd_test_pattern));
2020 core_link_read_dpcd(
2021 link,
3a340294 2022 DP_TEST_MISC0,
4562236b
HW		 2023 &dpcd_test_params.raw,
2024 sizeof(dpcd_test_params));
2025
2026 switch (dpcd_test_pattern.bits.PATTERN) {
2027 case LINK_TEST_PATTERN_COLOR_RAMP:
2028 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2029 break;
2030 case LINK_TEST_PATTERN_VERTICAL_BARS:
2031 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2032 break; /* black and white */
2033 case LINK_TEST_PATTERN_COLOR_SQUARES:
2034 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2035 TEST_DYN_RANGE_VESA ?
2036 DP_TEST_PATTERN_COLOR_SQUARES :
2037 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2038 break;
2039 default:
2040 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2041 break;
2042 }
2043
2044 dc_link_dp_set_test_pattern(
d0778ebf 2045 link,
4562236b
HW		 2046 test_pattern,
2047 NULL,
2048 NULL,
2049 0);
2050}
2051
d0778ebf 2052static void handle_automated_test(struct dc_link *link)
4562236b
HW		 2053{
2054 union test_request test_request;
2055 union test_response test_response;
2056
2057 memset(&test_request, 0, sizeof(test_request));
2058 memset(&test_response, 0, sizeof(test_response));
2059
2060 core_link_read_dpcd(
2061 link,
3a340294 2062 DP_TEST_REQUEST,
4562236b
HW		 2063 &test_request.raw,
2064 sizeof(union test_request));
2065 if (test_request.bits.LINK_TRAINING) {
2066 /* ACK first to let DP RX test box monitor LT sequence */
2067 test_response.bits.ACK = 1;
2068 core_link_write_dpcd(
2069 link,
3a340294 2070 DP_TEST_RESPONSE,
4562236b
HW		 2071 &test_response.raw,
2072 sizeof(test_response));
2073 dp_test_send_link_training(link);
2074 /* no acknowledge request is needed again */
2075 test_response.bits.ACK = 0;
2076 }
2077 if (test_request.bits.LINK_TEST_PATTRN) {
2078 dp_test_send_link_test_pattern(link);
75a74755 2079 test_response.bits.ACK = 1;
4562236b
HW		 2080 }
2081 if (test_request.bits.PHY_TEST_PATTERN) {
2082 dp_test_send_phy_test_pattern(link);
2083 test_response.bits.ACK = 1;
2084 }
a6729a5a 2085
4562236b
HW		 2086 /* send request acknowledgment */
2087 if (test_response.bits.ACK)
2088 core_link_write_dpcd(
2089 link,
3a340294 2090 DP_TEST_RESPONSE,
4562236b
HW		 2091 &test_response.raw,
2092 sizeof(test_response));
2093}
2094
4e18814e 2095bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
4562236b 2096{
9a6a8075 2097 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
c2e218dd 2098 union device_service_irq device_service_clear = { { 0 } };
d6258eaa 2099 enum dc_status result;
4e18814e 2100
4562236b 2101 bool status = false;
4e18814e
FD		 2102
2103 if (out_link_loss)
2104 *out_link_loss = false;
4562236b
HW		 2105 /* For use cases related to down stream connection status change,
2106 * PSR and device auto test, refer to function handle_sst_hpd_irq
2107 * in DAL2.1*/
2108
1296423b 2109 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
d0778ebf 2110 __func__, link->link_index);
4562236b 2111
8ee65d7c 2112
4562236b
HW		 2113 /* All the "handle_hpd_irq_xxx()" methods
2114 * should be called only after
2115 * dal_dpsst_ls_read_hpd_irq_data
2116 * Order of calls is important too
2117 */
2118 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
8ee65d7c
WL		 2119 if (out_hpd_irq_dpcd_data)
2120 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4562236b
HW		 2121
2122 if (result != DC_OK) {
1296423b 2123 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
4562236b
HW		 2124 __func__);
2125 return false;
2126 }
2127
2128 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2129 device_service_clear.bits.AUTOMATED_TEST = 1;
2130 core_link_write_dpcd(
2131 link,
3a340294 2132 DP_DEVICE_SERVICE_IRQ_VECTOR,
4562236b
HW		 2133 &device_service_clear.raw,
2134 sizeof(device_service_clear.raw));
2135 device_service_clear.raw = 0;
2136 handle_automated_test(link);
2137 return false;
2138 }
2139
2140 if (!allow_hpd_rx_irq(link)) {
1296423b 2141 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
d0778ebf 2142 __func__, link->link_index);
4562236b
HW		 2143 return false;
2144 }
2145
2146 if (handle_hpd_irq_psr_sink(link))
2147 /* PSR-related error was detected and handled */
2148 return true;
2149
2150 /* If PSR-related error handled, Main link may be off,
2151 * so do not handle as a normal sink status change interrupt.
2152 */
2153
aaa15026
WL		 2154 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2155 return true;
2156
4562236b 2157 /* check if we have MST msg and return since we poll for it */
aaa15026 2158 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
4562236b
HW		 2159 return false;
2160
2161 /* For now we only handle 'Downstream port status' case.
2162 * If we got sink count changed it means
2163 * Downstream port status changed,
2164 * then DM should call DC to do the detection. */
2165 if (hpd_rx_irq_check_link_loss_status(
2166 link,
2167 &hpd_irq_dpcd_data)) {
2168 /* Connectivity log: link loss */
2169 CONN_DATA_LINK_LOSS(link,
2170 hpd_irq_dpcd_data.raw,
2171 sizeof(hpd_irq_dpcd_data),
2172 "Status: ");
2173
2174 perform_link_training_with_retries(link,
d0778ebf 2175 &link->cur_link_settings,
4562236b
HW		 2176 true, LINK_TRAINING_ATTEMPTS);
2177
2178 status = false;
4e18814e
FD		 2179 if (out_link_loss)
2180 *out_link_loss = true;
4562236b
HW		 2181 }
2182
d0778ebf 2183 if (link->type == dc_connection_active_dongle &&
4562236b
HW		 2184 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
2185 != link->dpcd_sink_count)
2186 status = true;
2187
2188 /* reasons for HPD RX:
2189 * 1. Link Loss - ie Re-train the Link
2190 * 2. MST sideband message
2191 * 3. Automated Test - ie. Internal Commit
2192 * 4. CP (copy protection) - (not interesting for DM???)
2193 * 5. DRR
2194 * 6. Downstream Port status changed
2195 * -ie. Detect - this the only one
2196 * which is interesting for DM because
2197 * it must call dc_link_detect.
2198 */
2199 return status;
2200}
2201
2202/*query dpcd for version and mst cap addresses*/
d0778ebf 2203bool is_mst_supported(struct dc_link *link)
4562236b
HW		 2204{
2205 bool mst = false;
2206 enum dc_status st = DC_OK;
2207 union dpcd_rev rev;
2208 union mstm_cap cap;
2209
2210 rev.raw = 0;
2211 cap.raw = 0;
2212
3a340294 2213 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4562236b
HW		 2214 sizeof(rev));
2215
2216 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2217
3a340294 2218 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4562236b
HW		 2219 &cap.raw, sizeof(cap));
2220 if (st == DC_OK && cap.bits.MST_CAP == 1)
2221 mst = true;
2222 }
2223 return mst;
2224
2225}
2226
d0778ebf 2227bool is_dp_active_dongle(const struct dc_link *link)
4562236b
HW		 2228{
2229 enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
2230
2231 return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
2232 (dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
2233 (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
2234}
2235
6bffebc9
EY		 2236static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
2237{
2238 switch (bpc) {
2239 case DOWN_STREAM_MAX_8BPC:
2240 return 8;
2241 case DOWN_STREAM_MAX_10BPC:
2242 return 10;
2243 case DOWN_STREAM_MAX_12BPC:
2244 return 12;
2245 case DOWN_STREAM_MAX_16BPC:
2246 return 16;
2247 default:
2248 break;
2249 }
2250
2251 return -1;
2252}
2253
4562236b 2254static void get_active_converter_info(
d0778ebf 2255 uint8_t data, struct dc_link *link)
4562236b
HW		 2256{
2257 union dp_downstream_port_present ds_port = { .byte = data };
2258
2259 /* decode converter info*/
2260 if (!ds_port.fields.PORT_PRESENT) {
2261 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
d0778ebf 2262 ddc_service_set_dongle_type(link->ddc,
4562236b
HW		 2263 link->dpcd_caps.dongle_type);
2264 return;
2265 }
2266
2267 switch (ds_port.fields.PORT_TYPE) {
2268 case DOWNSTREAM_VGA:
2269 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
2270 break;
2271 case DOWNSTREAM_DVI_HDMI:
2272 /* At this point we don't know is it DVI or HDMI,
2273 * assume DVI.*/
2274 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
2275 break;
2276 default:
2277 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2278 break;
2279 }
2280
ac0e562c 2281 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
242b0c8f 2282 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
4562236b
HW		 2283 union dwnstream_port_caps_byte0 *port_caps =
2284 (union dwnstream_port_caps_byte0 *)det_caps;
3a340294 2285 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
4562236b
HW		 2286 det_caps, sizeof(det_caps));
2287
2288 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
2289 case DOWN_STREAM_DETAILED_VGA:
2290 link->dpcd_caps.dongle_type =
2291 DISPLAY_DONGLE_DP_VGA_CONVERTER;
2292 break;
2293 case DOWN_STREAM_DETAILED_DVI:
2294 link->dpcd_caps.dongle_type =
2295 DISPLAY_DONGLE_DP_DVI_CONVERTER;
2296 break;
2297 case DOWN_STREAM_DETAILED_HDMI:
2298 link->dpcd_caps.dongle_type =
2299 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
2300
03f5c686 2301 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
4562236b
HW		 2302 if (ds_port.fields.DETAILED_CAPS) {
2303
2304 union dwnstream_port_caps_byte3_hdmi
2305 hdmi_caps = {.raw = det_caps[3] };
7d8d90d8 2306 union dwnstream_port_caps_byte2
03f5c686
CL		 2307 hdmi_color_caps = {.raw = det_caps[2] };
2308 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
2309 det_caps[1] * 25000;
4562236b 2310
03f5c686 2311 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
4562236b 2312 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
03f5c686
CL		 2313 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
2314 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
2315 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
2316 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
2317 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
2318 hdmi_caps.bits.YCrCr422_CONVERSION;
2319 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
2320 hdmi_caps.bits.YCrCr420_CONVERSION;
2321
2322 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
6bffebc9
EY		 2323 translate_dpcd_max_bpc(
2324 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
03f5c686 2325
99b922f9
WL		 2326 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk != 0)
2327 link->dpcd_caps.dongle_caps.extendedCapValid = true;
4562236b 2328 }
03f5c686 2329
4562236b
HW		 2330 break;
2331 }
2332 }
2333
d0778ebf 2334 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4562236b
HW		 2335
2336 {
2337 struct dp_device_vendor_id dp_id;
2338
2339 /* read IEEE branch device id */
2340 core_link_read_dpcd(
2341 link,
3a340294 2342 DP_BRANCH_OUI,
4562236b
HW		 2343 (uint8_t *)&dp_id,
2344 sizeof(dp_id));
2345
2346 link->dpcd_caps.branch_dev_id =
2347 (dp_id.ieee_oui[0] << 16) +
2348 (dp_id.ieee_oui[1] << 8) +
2349 dp_id.ieee_oui[2];
2350
2351 memmove(
2352 link->dpcd_caps.branch_dev_name,
2353 dp_id.ieee_device_id,
2354 sizeof(dp_id.ieee_device_id));
2355 }
2356
2357 {
2358 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2359
2360 core_link_read_dpcd(
2361 link,
3a340294 2362 DP_BRANCH_REVISION_START,
4562236b
HW		 2363 (uint8_t *)&dp_hw_fw_revision,
2364 sizeof(dp_hw_fw_revision));
2365
2366 link->dpcd_caps.branch_hw_revision =
2367 dp_hw_fw_revision.ieee_hw_rev;
4b99affb
A		 2368
2369 memmove(
2370 link->dpcd_caps.branch_fw_revision,
2371 dp_hw_fw_revision.ieee_fw_rev,
2372 sizeof(dp_hw_fw_revision.ieee_fw_rev));
4562236b
HW		 2373 }
2374}
2375
d0778ebf 2376static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4562236b
HW		 2377 int length)
2378{
2379 int retry = 0;
2380 union dp_downstream_port_present ds_port = { 0 };
2381
2382 if (!link->dpcd_caps.dpcd_rev.raw) {
2383 do {
2384 dp_receiver_power_ctrl(link, true);
3a340294 2385 core_link_read_dpcd(link, DP_DPCD_REV,
4562236b
HW		 2386 dpcd_data, length);
2387 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3a340294
DA		 2388 DP_DPCD_REV -
2389 DP_DPCD_REV];
4562236b
HW		 2390 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
2391 }
2392
3a340294
DA		 2393 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2394 DP_DPCD_REV];
4562236b
HW		 2395
2396 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
2397 switch (link->dpcd_caps.branch_dev_id) {
2398 /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
2399 * all internal circuits including AUX communication preventing
2400 * reading DPCD table and EDID (spec violation).
2401 * Encoder will skip DP RX power down on disable_output to
2402 * keep receiver powered all the time.*/
2403 case DP_BRANCH_DEVICE_ID_1:
2404 case DP_BRANCH_DEVICE_ID_4:
2405 link->wa_flags.dp_keep_receiver_powered = true;
2406 break;
2407
2408 /* TODO: May need work around for other dongles. */
2409 default:
2410 link->wa_flags.dp_keep_receiver_powered = false;
2411 break;
2412 }
2413 } else
2414 link->wa_flags.dp_keep_receiver_powered = false;
2415}
2416
cdb39798 2417static bool retrieve_link_cap(struct dc_link *link)
4562236b 2418{
794550c6 2419 uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
4562236b 2420
8ca80900 2421 struct dp_device_vendor_id sink_id;
4562236b
HW		 2422 union down_stream_port_count down_strm_port_count;
2423 union edp_configuration_cap edp_config_cap;
2424 union dp_downstream_port_present ds_port = { 0 };
cdb39798 2425 enum dc_status status = DC_ERROR_UNEXPECTED;
3c1a312a
YS		 2426 uint32_t read_dpcd_retry_cnt = 3;
2427 int i;
4b99affb 2428 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
4562236b
HW		 2429
2430 memset(dpcd_data, '\0', sizeof(dpcd_data));
2431 memset(&down_strm_port_count,
2432 '\0', sizeof(union down_stream_port_count));
2433 memset(&edp_config_cap, '\0',
2434 sizeof(union edp_configuration_cap));
2435
3c1a312a
YS		 2436 for (i = 0; i < read_dpcd_retry_cnt; i++) {
2437 status = core_link_read_dpcd(
2438 link,
2439 DP_DPCD_REV,
2440 dpcd_data,
2441 sizeof(dpcd_data));
2442 if (status == DC_OK)
2443 break;
2444 }
cdb39798
YS		 2445
2446 if (status != DC_OK) {
2447 dm_error("%s: Read dpcd data failed.\n", __func__);
2448 return false;
2449 }
4562236b 2450
4562236b
HW		 2451 {
2452 union training_aux_rd_interval aux_rd_interval;
2453
2454 aux_rd_interval.raw =
3a340294 2455 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
4562236b
HW		 2456
2457 if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
818832bf
XY		 2458 uint8_t ext_cap_data[16];
2459
2460 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
2461 for (i = 0; i < read_dpcd_retry_cnt; i++) {
2462 status = core_link_read_dpcd(
4562236b 2463 link,
3a340294 2464 DP_DP13_DPCD_REV,
818832bf
XY		 2465 ext_cap_data,
2466 sizeof(ext_cap_data));
2467 if (status == DC_OK) {
2468 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
2469 break;
2470 }
2471 }
2472 if (status != DC_OK)
2473 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
4562236b
HW		 2474 }
2475 }
2476
07d6a199
AK		 2477 /* Error condition checking...
2478 * It is impossible for Sink to report Max Lane Count = 0.
2479 * It is possible for Sink to report Max Link Rate = 0, if it is
2480 * an eDP device that is reporting specialized link rates in the
2481 * SUPPORTED_LINK_RATE table.
2482 */
2483 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
2484 return false;
2485
cc04bf7e
TC		 2486 link->dpcd_caps.dpcd_rev.raw =
2487 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
2488
3a340294
DA		 2489 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2490 DP_DPCD_REV];
4562236b
HW		 2491
2492 get_active_converter_info(ds_port.byte, link);
2493
2494 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2495
98e6436d
AK		 2496 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
2497 DP_DPCD_REV];
2498
4562236b
HW		 2499 link->dpcd_caps.allow_invalid_MSA_timing_param =
2500 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2501
2502 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3a340294 2503 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4562236b
HW		 2504
2505 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3a340294 2506 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4562236b 2507
d0778ebf 2508 link->reported_link_cap.lane_count =
4562236b 2509 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
d0778ebf 2510 link->reported_link_cap.link_rate = dpcd_data[
3a340294 2511 DP_MAX_LINK_RATE - DP_DPCD_REV];
d0778ebf 2512 link->reported_link_cap.link_spread =
4562236b
HW		 2513 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
2514 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
2515
2516 edp_config_cap.raw = dpcd_data[
3a340294 2517 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4562236b
HW		 2518 link->dpcd_caps.panel_mode_edp =
2519 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
9799624a
WL		 2520 link->dpcd_caps.dpcd_display_control_capable =
2521 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4562236b 2522
d0778ebf
HW		 2523 link->test_pattern_enabled = false;
2524 link->compliance_test_state.raw = 0;
4562236b 2525
4562236b
HW		 2526 /* read sink count */
2527 core_link_read_dpcd(link,
3a340294 2528 DP_SINK_COUNT,
4562236b
HW		 2529 &link->dpcd_caps.sink_count.raw,
2530 sizeof(link->dpcd_caps.sink_count.raw));
2531
8ca80900
AK		 2532 /* read sink ieee oui */
2533 core_link_read_dpcd(link,
2534 DP_SINK_OUI,
2535 (uint8_t *)(&sink_id),
2536 sizeof(sink_id));
2537
2538 link->dpcd_caps.sink_dev_id =
2539 (sink_id.ieee_oui[0] << 16) +
2540 (sink_id.ieee_oui[1] << 8) +
2541 (sink_id.ieee_oui[2]);
2542
4b99affb
A		 2543 memmove(
2544 link->dpcd_caps.sink_dev_id_str,
2545 sink_id.ieee_device_id,
2546 sizeof(sink_id.ieee_device_id));
2547
2548 core_link_read_dpcd(
2549 link,
2550 DP_SINK_HW_REVISION_START,
2551 (uint8_t *)&dp_hw_fw_revision,
2552 sizeof(dp_hw_fw_revision));
2553
2554 link->dpcd_caps.sink_hw_revision =
2555 dp_hw_fw_revision.ieee_hw_rev;
2556
2557 memmove(
2558 link->dpcd_caps.sink_fw_revision,
2559 dp_hw_fw_revision.ieee_fw_rev,
2560 sizeof(dp_hw_fw_revision.ieee_fw_rev));
2561
4562236b
HW		 2562 /* Connectivity log: detection */
2563 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
cdb39798
YS		 2564
2565 return true;
4562236b
HW		 2566}
2567
cdb39798 2568bool detect_dp_sink_caps(struct dc_link *link)
4562236b 2569{
cdb39798 2570 return retrieve_link_cap(link);
4562236b
HW		 2571
2572 /* dc init_hw has power encoder using default
2573 * signal for connector. For native DP, no
2574 * need to power up encoder again. If not native
2575 * DP, hw_init may need check signal or power up
2576 * encoder here.
2577 */
4562236b
HW		 2578 /* TODO save sink caps in link->sink */
2579}
2580
b03a599b
DL		 2581enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
2582{
2583 enum dc_link_rate link_rate;
2584 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
2585 switch (link_rate_in_khz) {
2586 case 1620000:
2587 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
2588 break;
2589 case 2160000:
2590 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
2591 break;
2592 case 2430000:
2593 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
2594 break;
2595 case 2700000:
2596 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
2597 break;
2598 case 3240000:
2599 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
2600 break;
2601 case 4320000:
2602 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
2603 break;
2604 case 5400000:
2605 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
2606 break;
2607 case 8100000:
2608 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
2609 break;
2610 default:
2611 link_rate = LINK_RATE_UNKNOWN;
2612 break;
2613 }
2614 return link_rate;
2615}
2616
4654a2f7
RL		 2617void detect_edp_sink_caps(struct dc_link *link)
2618{
8628d02f 2619 uint8_t supported_link_rates[16];
b03a599b
DL		 2620 uint32_t entry;
2621 uint32_t link_rate_in_khz;
2622 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
48231fd5 2623
b03a599b 2624 retrieve_link_cap(link);
8628d02f
JP		 2625 link->dpcd_caps.edp_supported_link_rates_count = 0;
2626 memset(supported_link_rates, 0, sizeof(supported_link_rates));
48231fd5 2627
8628d02f
JP		 2628 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
2629 link->dc->config.optimize_edp_link_rate) {
b03a599b
DL		 2630 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
2631 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
2632 supported_link_rates, sizeof(supported_link_rates));
2633
b03a599b
DL		 2634 for (entry = 0; entry < 16; entry += 2) {
2635 // DPCD register reports per-lane link rate = 16-bit link rate capability
8628d02f 2636 // value X 200 kHz. Need multiplier to find link rate in kHz.
b03a599b
DL		 2637 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2638 supported_link_rates[entry]) * 200;
2639
2640 if (link_rate_in_khz != 0) {
2641 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
8628d02f
JP		 2642 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
2643 link->dpcd_caps.edp_supported_link_rates_count++;
b03a599b
DL		 2644 }
2645 }
2646 }
4654a2f7
RL		 2647 link->verified_link_cap = link->reported_link_cap;
2648}
2649
4562236b
HW		 2650void dc_link_dp_enable_hpd(const struct dc_link *link)
2651{
d0778ebf 2652 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2653
2654 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2655 encoder->funcs->enable_hpd(encoder);
2656}
2657
2658void dc_link_dp_disable_hpd(const struct dc_link *link)
2659{
d0778ebf 2660 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2661
2662 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2663 encoder->funcs->disable_hpd(encoder);
2664}
2665
2666static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
2667{
0e19401f
TC		 2668 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
2669 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
2670 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4562236b
HW		 2671 return true;
2672 else
2673 return false;
2674}
2675
d0778ebf 2676static void set_crtc_test_pattern(struct dc_link *link,
4562236b
HW		 2677 struct pipe_ctx *pipe_ctx,
2678 enum dp_test_pattern test_pattern)
2679{
2680 enum controller_dp_test_pattern controller_test_pattern;
2681 enum dc_color_depth color_depth = pipe_ctx->
4fa086b9 2682 stream->timing.display_color_depth;
4562236b
HW		 2683 struct bit_depth_reduction_params params;
2684
2685 memset(&params, 0, sizeof(params));
2686
2687 switch (test_pattern) {
2688 case DP_TEST_PATTERN_COLOR_SQUARES:
2689 controller_test_pattern =
2690 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2691 break;
2692 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2693 controller_test_pattern =
2694 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
2695 break;
2696 case DP_TEST_PATTERN_VERTICAL_BARS:
2697 controller_test_pattern =
2698 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
2699 break;
2700 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2701 controller_test_pattern =
2702 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
2703 break;
2704 case DP_TEST_PATTERN_COLOR_RAMP:
2705 controller_test_pattern =
2706 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
2707 break;
2708 default:
2709 controller_test_pattern =
2710 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
2711 break;
2712 }
2713
2714 switch (test_pattern) {
2715 case DP_TEST_PATTERN_COLOR_SQUARES:
2716 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2717 case DP_TEST_PATTERN_VERTICAL_BARS:
2718 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2719 case DP_TEST_PATTERN_COLOR_RAMP:
2720 {
2721 /* disable bit depth reduction */
2722 pipe_ctx->stream->bit_depth_params = params;
a6a6cb34
HW		 2723 pipe_ctx->stream_res.opp->funcs->
2724 opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
7f93c1de
CL		 2725 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2726 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 2727 controller_test_pattern, color_depth);
2728 }
2729 break;
2730 case DP_TEST_PATTERN_VIDEO_MODE:
2731 {
2732 /* restore bitdepth reduction */
529cad0f 2733 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
4562236b
HW		 2734 &params);
2735 pipe_ctx->stream->bit_depth_params = params;
a6a6cb34
HW		 2736 pipe_ctx->stream_res.opp->funcs->
2737 opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
7f93c1de
CL		 2738 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2739 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 2740 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2741 color_depth);
2742 }
2743 break;
2744
2745 default:
2746 break;
2747 }
2748}
2749
2750bool dc_link_dp_set_test_pattern(
d0778ebf 2751 struct dc_link *link,
4562236b
HW		 2752 enum dp_test_pattern test_pattern,
2753 const struct link_training_settings *p_link_settings,
2754 const unsigned char *p_custom_pattern,
2755 unsigned int cust_pattern_size)
2756{
608ac7bb 2757 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
0a8f43ff 2758 struct pipe_ctx *pipe_ctx = &pipes[0];
4562236b
HW		 2759 unsigned int lane;
2760 unsigned int i;
2761 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
2762 union dpcd_training_pattern training_pattern;
4562236b
HW		 2763 enum dpcd_phy_test_patterns pattern;
2764
2765 memset(&training_pattern, 0, sizeof(training_pattern));
4562236b
HW		 2766
2767 for (i = 0; i < MAX_PIPES; i++) {
ceb3dbb4 2768 if (pipes[i].stream->link == link) {
0a8f43ff 2769 pipe_ctx = &pipes[i];
4562236b
HW		 2770 break;
2771 }
2772 }
2773
2774 /* Reset CRTC Test Pattern if it is currently running and request
2775 * is VideoMode Reset DP Phy Test Pattern if it is currently running
2776 * and request is VideoMode
2777 */
d0778ebf 2778 if (link->test_pattern_enabled && test_pattern ==
4562236b
HW		 2779 DP_TEST_PATTERN_VIDEO_MODE) {
2780 /* Set CRTC Test Pattern */
0a8f43ff 2781 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
d0778ebf 2782 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 2783 (uint8_t *)p_custom_pattern,
2784 (uint32_t)cust_pattern_size);
2785
2786 /* Unblank Stream */
d0778ebf 2787 link->dc->hwss.unblank_stream(
0a8f43ff 2788 pipe_ctx,
d0778ebf 2789 &link->verified_link_cap);
4562236b
HW		 2790 /* TODO:m_pHwss->MuteAudioEndpoint
2791 * (pPathMode->pDisplayPath, false);
2792 */
2793
2794 /* Reset Test Pattern state */
d0778ebf 2795 link->test_pattern_enabled = false;
4562236b
HW		 2796
2797 return true;
2798 }
2799
2800 /* Check for PHY Test Patterns */
2801 if (is_dp_phy_pattern(test_pattern)) {
2802 /* Set DPCD Lane Settings before running test pattern */
2803 if (p_link_settings != NULL) {
d0778ebf
HW		 2804 dp_set_hw_lane_settings(link, p_link_settings);
2805 dpcd_set_lane_settings(link, p_link_settings);
4562236b
HW		 2806 }
2807
2808 /* Blank stream if running test pattern */
2809 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2810 /*TODO:
2811 * m_pHwss->
2812 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
2813 */
2814 /* Blank stream */
8e9c4c8c 2815 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4562236b
HW		 2816 }
2817
d0778ebf 2818 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 2819 (uint8_t *)p_custom_pattern,
2820 (uint32_t)cust_pattern_size);
2821
2822 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2823 /* Set Test Pattern state */
d0778ebf 2824 link->test_pattern_enabled = true;
4562236b 2825 if (p_link_settings != NULL)
d0778ebf 2826 dpcd_set_link_settings(link,
4562236b
HW		 2827 p_link_settings);
2828 }
2829
2830 switch (test_pattern) {
2831 case DP_TEST_PATTERN_VIDEO_MODE:
2832 pattern = PHY_TEST_PATTERN_NONE;
0e19401f 2833 break;
4562236b
HW		 2834 case DP_TEST_PATTERN_D102:
2835 pattern = PHY_TEST_PATTERN_D10_2;
0e19401f 2836 break;
4562236b
HW		 2837 case DP_TEST_PATTERN_SYMBOL_ERROR:
2838 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 2839 break;
4562236b
HW		 2840 case DP_TEST_PATTERN_PRBS7:
2841 pattern = PHY_TEST_PATTERN_PRBS7;
0e19401f 2842 break;
4562236b
HW		 2843 case DP_TEST_PATTERN_80BIT_CUSTOM:
2844 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 2845 break;
2846 case DP_TEST_PATTERN_CP2520_1:
2847 pattern = PHY_TEST_PATTERN_CP2520_1;
2848 break;
2849 case DP_TEST_PATTERN_CP2520_2:
2850 pattern = PHY_TEST_PATTERN_CP2520_2;
2851 break;
2852 case DP_TEST_PATTERN_CP2520_3:
2853 pattern = PHY_TEST_PATTERN_CP2520_3;
2854 break;
4562236b
HW		 2855 default:
2856 return false;
2857 }
2858
2859 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
2860 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
2861 return false;
2862
d0778ebf 2863 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 2864 /* tell receiver that we are sending qualification
2865 * pattern DP 1.2 or later - DP receiver's link quality
2866 * pattern is set using DPCD LINK_QUAL_LANEx_SET
2867 * register (0x10B~0x10E)\
2868 */
2869 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
2870 link_qual_pattern[lane] =
2871 (unsigned char)(pattern);
2872
d0778ebf 2873 core_link_write_dpcd(link,
3a340294 2874 DP_LINK_QUAL_LANE0_SET,
4562236b
HW		 2875 link_qual_pattern,
2876 sizeof(link_qual_pattern));
d0778ebf
HW		 2877 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
2878 link->dpcd_caps.dpcd_rev.raw == 0) {
4562236b
HW		 2879 /* tell receiver that we are sending qualification
2880 * pattern DP 1.1a or earlier - DP receiver's link
2881 * quality pattern is set using
2882 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
2883 * register (0x102). We will use v_1.3 when we are
2884 * setting test pattern for DP 1.1.
2885 */
d0778ebf
HW		 2886 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
2887 &training_pattern.raw,
2888 sizeof(training_pattern));
4562236b 2889 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
d0778ebf
HW		 2890 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
2891 &training_pattern.raw,
2892 sizeof(training_pattern));
4562236b
HW		 2893 }
2894 } else {
2895 /* CRTC Patterns */
0a8f43ff 2896 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
4562236b 2897 /* Set Test Pattern state */
d0778ebf 2898 link->test_pattern_enabled = true;
4562236b
HW		 2899 }
2900
2901 return true;
2902}
07c84c7a 2903
d0778ebf 2904void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
07c84c7a
DW		 2905{
2906 unsigned char mstmCntl;
2907
2908 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2909 if (enable)
2910 mstmCntl |= DP_MST_EN;
2911 else
2912 mstmCntl &= (~DP_MST_EN);
2913
2914 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2915}
Linux 6.x block layer and io_uring tree(s)