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4562236b HW |
1 | /* Copyright 2015 Advanced Micro Devices, Inc. */ |
2 | #include "dm_services.h" | |
3 | #include "dc.h" | |
4 | #include "dc_link_dp.h" | |
5 | #include "dm_helpers.h" | |
7f93c1de | 6 | #include "opp.h" |
97bda032 | 7 | #include "dsc.h" |
6fbefb84 | 8 | #include "resource.h" |
4562236b HW |
9 | |
10 | #include "inc/core_types.h" | |
11 | #include "link_hwss.h" | |
12 | #include "dc_link_ddc.h" | |
13 | #include "core_status.h" | |
14 | #include "dpcd_defs.h" | |
dc6e2448 WW |
15 | #include "dc_dmub_srv.h" |
16 | #include "dce/dmub_hw_lock_mgr.h" | |
ede4f6da | 17 | #include "inc/link_enc_cfg.h" |
4562236b | 18 | |
8dfcb24e LJ |
19 | /*Travis*/ |
20 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; | |
21 | /*Nutmeg*/ | |
22 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; | |
23 | ||
1296423b BL |
24 | #define DC_LOGGER \ |
25 | link->ctx->logger | |
9248681f | 26 | #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ |
8e5100a5 | 27 | |
9248681f AT |
28 | /* maximum pre emphasis level allowed for each voltage swing level*/ |
29 | static const enum dc_pre_emphasis | |
30 | voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3, | |
31 | PRE_EMPHASIS_LEVEL2, | |
32 | PRE_EMPHASIS_LEVEL1, | |
33 | PRE_EMPHASIS_DISABLED }; | |
4562236b HW |
34 | |
35 | enum { | |
36 | POST_LT_ADJ_REQ_LIMIT = 6, | |
37 | POST_LT_ADJ_REQ_TIMEOUT = 200 | |
38 | }; | |
39 | ||
04e21292 DA |
40 | static bool decide_fallback_link_setting( |
41 | struct dc_link_settings initial_link_settings, | |
42 | struct dc_link_settings *current_link_setting, | |
43 | enum link_training_result training_result); | |
9a6a8075 | 44 | static struct dc_link_settings get_common_supported_link_settings( |
04e21292 DA |
45 | struct dc_link_settings link_setting_a, |
46 | struct dc_link_settings link_setting_b); | |
47 | ||
b50d5551 WL |
48 | static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link, |
49 | const struct dc_link_settings *link_settings) | |
50 | { | |
51 | union training_aux_rd_interval training_rd_interval; | |
52 | uint32_t wait_in_micro_secs = 100; | |
53 | ||
54 | memset(&training_rd_interval, 0, sizeof(training_rd_interval)); | |
55 | core_link_read_dpcd( | |
56 | link, | |
57 | DP_TRAINING_AUX_RD_INTERVAL, | |
58 | (uint8_t *)&training_rd_interval, | |
59 | sizeof(training_rd_interval)); | |
60 | if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL) | |
61 | wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000; | |
62 | return wait_in_micro_secs; | |
63 | } | |
64 | ||
3fb068c3 | 65 | static uint32_t get_eq_training_aux_rd_interval( |
d0778ebf | 66 | struct dc_link *link, |
3fb068c3 | 67 | const struct dc_link_settings *link_settings) |
4562236b | 68 | { |
d6d36b55 | 69 | union training_aux_rd_interval training_rd_interval; |
3fb068c3 | 70 | uint32_t wait_in_micro_secs = 400; |
d6d36b55 NC |
71 | |
72 | memset(&training_rd_interval, 0, sizeof(training_rd_interval)); | |
4562236b HW |
73 | /* overwrite the delay if rev > 1.1*/ |
74 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { | |
75 | /* DP 1.2 or later - retrieve delay through | |
76 | * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */ | |
77 | core_link_read_dpcd( | |
78 | link, | |
3a340294 | 79 | DP_TRAINING_AUX_RD_INTERVAL, |
4562236b HW |
80 | (uint8_t *)&training_rd_interval, |
81 | sizeof(training_rd_interval)); | |
82 | ||
83 | if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL) | |
3fb068c3 | 84 | wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000; |
4562236b HW |
85 | } |
86 | ||
3fb068c3 | 87 | return wait_in_micro_secs; |
e0a6440a DG |
88 | } |
89 | ||
e84ecdc5 | 90 | void dp_wait_for_training_aux_rd_interval( |
e0a6440a DG |
91 | struct dc_link *link, |
92 | uint32_t wait_in_micro_secs) | |
93 | { | |
94 | udelay(wait_in_micro_secs); | |
4562236b | 95 | |
1296423b | 96 | DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n", |
4562236b | 97 | __func__, |
e0a6440a | 98 | wait_in_micro_secs); |
4562236b HW |
99 | } |
100 | ||
e84ecdc5 | 101 | enum dpcd_training_patterns |
ebc22cbd WL |
102 | dc_dp_training_pattern_to_dpcd_training_pattern( |
103 | struct dc_link *link, | |
104 | enum dc_dp_training_pattern pattern) | |
105 | { | |
106 | enum dpcd_training_patterns dpcd_tr_pattern = | |
107 | DPCD_TRAINING_PATTERN_VIDEOIDLE; | |
108 | ||
109 | switch (pattern) { | |
110 | case DP_TRAINING_PATTERN_SEQUENCE_1: | |
111 | dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1; | |
112 | break; | |
113 | case DP_TRAINING_PATTERN_SEQUENCE_2: | |
114 | dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2; | |
115 | break; | |
116 | case DP_TRAINING_PATTERN_SEQUENCE_3: | |
117 | dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3; | |
118 | break; | |
119 | case DP_TRAINING_PATTERN_SEQUENCE_4: | |
120 | dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4; | |
121 | break; | |
122 | case DP_TRAINING_PATTERN_VIDEOIDLE: | |
123 | dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE; | |
124 | break; | |
125 | default: | |
126 | ASSERT(0); | |
127 | DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n", | |
128 | __func__, pattern); | |
129 | break; | |
130 | } | |
131 | ||
132 | return dpcd_tr_pattern; | |
133 | } | |
134 | ||
4562236b | 135 | static void dpcd_set_training_pattern( |
d0778ebf | 136 | struct dc_link *link, |
ebc22cbd | 137 | enum dc_dp_training_pattern training_pattern) |
4562236b | 138 | { |
ebc22cbd WL |
139 | union dpcd_training_pattern dpcd_pattern = { {0} }; |
140 | ||
141 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET = | |
142 | dc_dp_training_pattern_to_dpcd_training_pattern( | |
143 | link, training_pattern); | |
144 | ||
4562236b HW |
145 | core_link_write_dpcd( |
146 | link, | |
3a340294 | 147 | DP_TRAINING_PATTERN_SET, |
4562236b HW |
148 | &dpcd_pattern.raw, |
149 | 1); | |
150 | ||
1296423b | 151 | DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n", |
4562236b | 152 | __func__, |
3a340294 | 153 | DP_TRAINING_PATTERN_SET, |
4562236b HW |
154 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET); |
155 | } | |
156 | ||
ce17ce17 WL |
157 | static enum dc_dp_training_pattern decide_cr_training_pattern( |
158 | const struct dc_link_settings *link_settings) | |
159 | { | |
4b1d6831 | 160 | return DP_TRAINING_PATTERN_SEQUENCE_1; |
ce17ce17 WL |
161 | } |
162 | ||
163 | static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link, | |
164 | const struct dc_link_settings *link_settings) | |
16b6253a | 165 | { |
ede4f6da | 166 | struct link_encoder *link_enc; |
e0a6440a | 167 | enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2; |
ede4f6da | 168 | struct encoder_feature_support *features; |
16b6253a | 169 | struct dpcd_caps *dpcd_caps = &link->dpcd_caps; |
170 | ||
ede4f6da JK |
171 | /* Access link encoder capability based on whether it is statically |
172 | * or dynamically assigned to a link. | |
173 | */ | |
174 | if (link->is_dig_mapping_flexible && | |
175 | link->dc->res_pool->funcs->link_encs_assign) | |
176 | link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link); | |
177 | else | |
178 | link_enc = link->link_enc; | |
179 | ASSERT(link_enc); | |
180 | features = &link_enc->features; | |
181 | ||
16b6253a | 182 | if (features->flags.bits.IS_TPS3_CAPABLE) |
e0a6440a | 183 | highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3; |
16b6253a | 184 | |
185 | if (features->flags.bits.IS_TPS4_CAPABLE) | |
e0a6440a | 186 | highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4; |
16b6253a | 187 | |
188 | if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED && | |
e0a6440a DG |
189 | highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4) |
190 | return DP_TRAINING_PATTERN_SEQUENCE_4; | |
16b6253a | 191 | |
192 | if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED && | |
e0a6440a DG |
193 | highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3) |
194 | return DP_TRAINING_PATTERN_SEQUENCE_3; | |
16b6253a | 195 | |
e0a6440a | 196 | return DP_TRAINING_PATTERN_SEQUENCE_2; |
16b6253a | 197 | } |
198 | ||
7211b605 | 199 | enum dc_status dpcd_set_link_settings( |
d0778ebf | 200 | struct dc_link *link, |
4562236b HW |
201 | const struct link_training_settings *lt_settings) |
202 | { | |
8628d02f | 203 | uint8_t rate; |
7211b605 | 204 | enum dc_status status; |
4562236b | 205 | |
9a6a8075 HW |
206 | union down_spread_ctrl downspread = { {0} }; |
207 | union lane_count_set lane_count_set = { {0} }; | |
4562236b HW |
208 | |
209 | downspread.raw = (uint8_t) | |
210 | (lt_settings->link_settings.link_spread); | |
211 | ||
212 | lane_count_set.bits.LANE_COUNT_SET = | |
213 | lt_settings->link_settings.lane_count; | |
214 | ||
e0a6440a | 215 | lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing; |
16b6253a | 216 | lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0; |
217 | ||
e0a6440a | 218 | |
7211b605 JK |
219 | if (link->ep_type == DISPLAY_ENDPOINT_PHY && |
220 | lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) { | |
16b6253a | 221 | lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = |
222 | link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED; | |
223 | } | |
4562236b | 224 | |
7211b605 | 225 | status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, |
e0a6440a | 226 | &downspread.raw, sizeof(downspread)); |
4562236b | 227 | |
7211b605 | 228 | status = core_link_write_dpcd(link, DP_LANE_COUNT_SET, |
e0a6440a | 229 | &lane_count_set.raw, 1); |
8628d02f | 230 | |
b03a599b | 231 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 && |
8628d02f JP |
232 | lt_settings->link_settings.use_link_rate_set == true) { |
233 | rate = 0; | |
8edb9456 DZ |
234 | /* WA for some MUX chips that will power down with eDP and lose supported |
235 | * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure | |
236 | * MUX chip gets link rate set back before link training. | |
237 | */ | |
238 | if (link->connector_signal == SIGNAL_TYPE_EDP) { | |
239 | uint8_t supported_link_rates[16]; | |
240 | ||
241 | core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES, | |
242 | supported_link_rates, sizeof(supported_link_rates)); | |
243 | } | |
7211b605 JK |
244 | status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1); |
245 | status = core_link_write_dpcd(link, DP_LINK_RATE_SET, | |
8628d02f JP |
246 | <_settings->link_settings.link_rate_set, 1); |
247 | } else { | |
248 | rate = (uint8_t) (lt_settings->link_settings.link_rate); | |
7211b605 | 249 | status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1); |
b03a599b DL |
250 | } |
251 | ||
8628d02f | 252 | if (rate) { |
e0a6440a | 253 | DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n", |
8628d02f JP |
254 | __func__, |
255 | DP_LINK_BW_SET, | |
256 | lt_settings->link_settings.link_rate, | |
257 | DP_LANE_COUNT_SET, | |
258 | lt_settings->link_settings.lane_count, | |
e0a6440a | 259 | lt_settings->enhanced_framing, |
8628d02f JP |
260 | DP_DOWNSPREAD_CTRL, |
261 | lt_settings->link_settings.link_spread); | |
262 | } else { | |
e0a6440a | 263 | DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n", |
8628d02f JP |
264 | __func__, |
265 | DP_LINK_RATE_SET, | |
266 | lt_settings->link_settings.link_rate_set, | |
267 | DP_LANE_COUNT_SET, | |
268 | lt_settings->link_settings.lane_count, | |
e0a6440a | 269 | lt_settings->enhanced_framing, |
8628d02f JP |
270 | DP_DOWNSPREAD_CTRL, |
271 | lt_settings->link_settings.link_spread); | |
272 | } | |
7211b605 JK |
273 | |
274 | return status; | |
4562236b HW |
275 | } |
276 | ||
e84ecdc5 | 277 | uint8_t dc_dp_initialize_scrambling_data_symbols( |
7d1ee78f VS |
278 | struct dc_link *link, |
279 | enum dc_dp_training_pattern pattern) | |
280 | { | |
281 | uint8_t disable_scrabled_data_symbols = 0; | |
282 | ||
283 | switch (pattern) { | |
284 | case DP_TRAINING_PATTERN_SEQUENCE_1: | |
285 | case DP_TRAINING_PATTERN_SEQUENCE_2: | |
286 | case DP_TRAINING_PATTERN_SEQUENCE_3: | |
287 | disable_scrabled_data_symbols = 1; | |
288 | break; | |
289 | case DP_TRAINING_PATTERN_SEQUENCE_4: | |
290 | disable_scrabled_data_symbols = 0; | |
291 | break; | |
292 | default: | |
293 | ASSERT(0); | |
294 | DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n", | |
295 | __func__, pattern); | |
296 | break; | |
297 | } | |
298 | return disable_scrabled_data_symbols; | |
299 | } | |
300 | ||
64c12b73 | 301 | static inline bool is_repeater(struct dc_link *link, uint32_t offset) |
302 | { | |
3128b285 | 303 | return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0); |
64c12b73 | 304 | } |
305 | ||
4562236b | 306 | static void dpcd_set_lt_pattern_and_lane_settings( |
d0778ebf | 307 | struct dc_link *link, |
4562236b | 308 | const struct link_training_settings *lt_settings, |
64c12b73 | 309 | enum dc_dp_training_pattern pattern, |
310 | uint32_t offset) | |
4562236b | 311 | { |
9a6a8075 | 312 | union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } }; |
64c12b73 | 313 | |
314 | uint32_t dpcd_base_lt_offset; | |
315 | ||
4562236b | 316 | uint8_t dpcd_lt_buffer[5] = {0}; |
9a6a8075 | 317 | union dpcd_training_pattern dpcd_pattern = { {0} }; |
4562236b HW |
318 | uint32_t lane; |
319 | uint32_t size_in_bytes; | |
320 | bool edp_workaround = false; /* TODO link_prop.INTERNAL */ | |
64c12b73 | 321 | dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET; |
322 | ||
323 | if (is_repeater(link, offset)) | |
324 | dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 + | |
325 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); | |
4562236b HW |
326 | |
327 | /***************************************************************** | |
328 | * DpcdAddress_TrainingPatternSet | |
329 | *****************************************************************/ | |
330 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET = | |
e0a6440a | 331 | dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern); |
4562236b | 332 | |
7d1ee78f VS |
333 | dpcd_pattern.v1_4.SCRAMBLING_DISABLE = |
334 | dc_dp_initialize_scrambling_data_symbols(link, pattern); | |
335 | ||
64c12b73 | 336 | dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET] |
4562236b HW |
337 | = dpcd_pattern.raw; |
338 | ||
460adc6b | 339 | if (is_repeater(link, offset)) { |
340 | DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n", | |
341 | __func__, | |
342 | offset, | |
343 | dpcd_base_lt_offset, | |
344 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET); | |
345 | } else { | |
346 | DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n", | |
347 | __func__, | |
348 | dpcd_base_lt_offset, | |
349 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET); | |
350 | } | |
4562236b HW |
351 | /***************************************************************** |
352 | * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set | |
353 | *****************************************************************/ | |
354 | for (lane = 0; lane < | |
355 | (uint32_t)(lt_settings->link_settings.lane_count); lane++) { | |
356 | ||
357 | dpcd_lane[lane].bits.VOLTAGE_SWING_SET = | |
358 | (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING); | |
359 | dpcd_lane[lane].bits.PRE_EMPHASIS_SET = | |
360 | (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS); | |
361 | ||
362 | dpcd_lane[lane].bits.MAX_SWING_REACHED = | |
363 | (lt_settings->lane_settings[lane].VOLTAGE_SWING == | |
364 | VOLTAGE_SWING_MAX_LEVEL ? 1 : 0); | |
365 | dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED = | |
366 | (lt_settings->lane_settings[lane].PRE_EMPHASIS == | |
367 | PRE_EMPHASIS_MAX_LEVEL ? 1 : 0); | |
368 | } | |
369 | ||
64c12b73 | 370 | /* concatenate everything into one buffer*/ |
4562236b HW |
371 | |
372 | size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]); | |
373 | ||
374 | // 0x00103 - 0x00102 | |
375 | memmove( | |
64c12b73 | 376 | &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET], |
4562236b HW |
377 | dpcd_lane, |
378 | size_in_bytes); | |
379 | ||
460adc6b | 380 | if (is_repeater(link, offset)) { |
381 | DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" | |
382 | " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", | |
383 | __func__, | |
384 | offset, | |
385 | dpcd_base_lt_offset, | |
386 | dpcd_lane[0].bits.VOLTAGE_SWING_SET, | |
387 | dpcd_lane[0].bits.PRE_EMPHASIS_SET, | |
388 | dpcd_lane[0].bits.MAX_SWING_REACHED, | |
389 | dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); | |
390 | } else { | |
391 | DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", | |
392 | __func__, | |
393 | dpcd_base_lt_offset, | |
394 | dpcd_lane[0].bits.VOLTAGE_SWING_SET, | |
395 | dpcd_lane[0].bits.PRE_EMPHASIS_SET, | |
396 | dpcd_lane[0].bits.MAX_SWING_REACHED, | |
397 | dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); | |
398 | } | |
4562236b HW |
399 | if (edp_workaround) { |
400 | /* for eDP write in 2 parts because the 5-byte burst is | |
401 | * causing issues on some eDP panels (EPR#366724) | |
402 | */ | |
403 | core_link_write_dpcd( | |
404 | link, | |
3a340294 | 405 | DP_TRAINING_PATTERN_SET, |
4562236b | 406 | &dpcd_pattern.raw, |
9a6a8075 | 407 | sizeof(dpcd_pattern.raw)); |
4562236b HW |
408 | |
409 | core_link_write_dpcd( | |
410 | link, | |
3a340294 | 411 | DP_TRAINING_LANE0_SET, |
4562236b HW |
412 | (uint8_t *)(dpcd_lane), |
413 | size_in_bytes); | |
414 | ||
415 | } else | |
416 | /* write it all in (1 + number-of-lanes)-byte burst*/ | |
417 | core_link_write_dpcd( | |
418 | link, | |
419 | dpcd_base_lt_offset, | |
420 | dpcd_lt_buffer, | |
9a6a8075 | 421 | size_in_bytes + sizeof(dpcd_pattern.raw)); |
4562236b | 422 | |
d0778ebf | 423 | link->cur_lane_setting = lt_settings->lane_settings[0]; |
4562236b HW |
424 | } |
425 | ||
e84ecdc5 | 426 | bool dp_is_cr_done(enum dc_lane_count ln_count, |
4562236b HW |
427 | union lane_status *dpcd_lane_status) |
428 | { | |
4562236b HW |
429 | uint32_t lane; |
430 | /*LANEx_CR_DONE bits All 1's?*/ | |
431 | for (lane = 0; lane < (uint32_t)(ln_count); lane++) { | |
432 | if (!dpcd_lane_status[lane].bits.CR_DONE_0) | |
d56b83f7 | 433 | return false; |
4562236b | 434 | } |
d56b83f7 | 435 | return true; |
4562236b HW |
436 | } |
437 | ||
438 | static bool is_ch_eq_done(enum dc_lane_count ln_count, | |
ebc22cbd | 439 | union lane_status *dpcd_lane_status) |
4562236b | 440 | { |
ebc22cbd | 441 | bool done = true; |
4562236b | 442 | uint32_t lane; |
ebc22cbd WL |
443 | for (lane = 0; lane < (uint32_t)(ln_count); lane++) |
444 | if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0) | |
445 | done = false; | |
446 | return done; | |
447 | } | |
448 | ||
449 | static bool is_symbol_locked(enum dc_lane_count ln_count, | |
450 | union lane_status *dpcd_lane_status) | |
451 | { | |
452 | bool locked = true; | |
453 | uint32_t lane; | |
454 | for (lane = 0; lane < (uint32_t)(ln_count); lane++) | |
455 | if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0) | |
456 | locked = false; | |
457 | return locked; | |
458 | } | |
459 | ||
460 | static inline bool is_interlane_aligned(union lane_align_status_updated align_status) | |
461 | { | |
462 | return align_status.bits.INTERLANE_ALIGN_DONE == 1; | |
4562236b HW |
463 | } |
464 | ||
e84ecdc5 | 465 | void dp_update_drive_settings( |
4562236b HW |
466 | struct link_training_settings *dest, |
467 | struct link_training_settings src) | |
468 | { | |
469 | uint32_t lane; | |
470 | for (lane = 0; lane < src.link_settings.lane_count; lane++) { | |
e0a6440a DG |
471 | if (dest->voltage_swing == NULL) |
472 | dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING; | |
473 | else | |
474 | dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing; | |
475 | ||
476 | if (dest->pre_emphasis == NULL) | |
477 | dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS; | |
478 | else | |
479 | dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis; | |
480 | ||
481 | if (dest->post_cursor2 == NULL) | |
482 | dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2; | |
483 | else | |
484 | dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2; | |
4562236b HW |
485 | } |
486 | } | |
487 | ||
488 | static uint8_t get_nibble_at_index(const uint8_t *buf, | |
489 | uint32_t index) | |
490 | { | |
491 | uint8_t nibble; | |
492 | nibble = buf[index / 2]; | |
493 | ||
494 | if (index % 2) | |
495 | nibble >>= 4; | |
496 | else | |
497 | nibble &= 0x0F; | |
498 | ||
499 | return nibble; | |
500 | } | |
501 | ||
502 | static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing( | |
503 | enum dc_voltage_swing voltage) | |
504 | { | |
505 | enum dc_pre_emphasis pre_emphasis; | |
506 | pre_emphasis = PRE_EMPHASIS_MAX_LEVEL; | |
507 | ||
508 | if (voltage <= VOLTAGE_SWING_MAX_LEVEL) | |
509 | pre_emphasis = voltage_swing_to_pre_emphasis[voltage]; | |
510 | ||
511 | return pre_emphasis; | |
512 | ||
513 | } | |
514 | ||
515 | static void find_max_drive_settings( | |
516 | const struct link_training_settings *link_training_setting, | |
517 | struct link_training_settings *max_lt_setting) | |
518 | { | |
519 | uint32_t lane; | |
520 | struct dc_lane_settings max_requested; | |
521 | ||
522 | max_requested.VOLTAGE_SWING = | |
523 | link_training_setting-> | |
524 | lane_settings[0].VOLTAGE_SWING; | |
525 | max_requested.PRE_EMPHASIS = | |
526 | link_training_setting-> | |
527 | lane_settings[0].PRE_EMPHASIS; | |
528 | /*max_requested.postCursor2 = | |
529 | * link_training_setting->laneSettings[0].postCursor2;*/ | |
530 | ||
531 | /* Determine what the maximum of the requested settings are*/ | |
532 | for (lane = 1; lane < link_training_setting->link_settings.lane_count; | |
533 | lane++) { | |
534 | if (link_training_setting->lane_settings[lane].VOLTAGE_SWING > | |
535 | max_requested.VOLTAGE_SWING) | |
536 | ||
537 | max_requested.VOLTAGE_SWING = | |
538 | link_training_setting-> | |
539 | lane_settings[lane].VOLTAGE_SWING; | |
540 | ||
541 | if (link_training_setting->lane_settings[lane].PRE_EMPHASIS > | |
542 | max_requested.PRE_EMPHASIS) | |
543 | max_requested.PRE_EMPHASIS = | |
544 | link_training_setting-> | |
545 | lane_settings[lane].PRE_EMPHASIS; | |
546 | ||
547 | /* | |
548 | if (link_training_setting->laneSettings[lane].postCursor2 > | |
549 | max_requested.postCursor2) | |
550 | { | |
551 | max_requested.postCursor2 = | |
552 | link_training_setting->laneSettings[lane].postCursor2; | |
553 | } | |
554 | */ | |
555 | } | |
556 | ||
557 | /* make sure the requested settings are | |
558 | * not higher than maximum settings*/ | |
559 | if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL) | |
560 | max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL; | |
561 | ||
562 | if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL) | |
563 | max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL; | |
564 | /* | |
565 | if (max_requested.postCursor2 > PostCursor2_MaxLevel) | |
566 | max_requested.postCursor2 = PostCursor2_MaxLevel; | |
567 | */ | |
568 | ||
569 | /* make sure the pre-emphasis matches the voltage swing*/ | |
570 | if (max_requested.PRE_EMPHASIS > | |
571 | get_max_pre_emphasis_for_voltage_swing( | |
572 | max_requested.VOLTAGE_SWING)) | |
573 | max_requested.PRE_EMPHASIS = | |
574 | get_max_pre_emphasis_for_voltage_swing( | |
575 | max_requested.VOLTAGE_SWING); | |
576 | ||
577 | /* | |
578 | * Post Cursor2 levels are completely independent from | |
579 | * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels | |
580 | * can only be applied to each allowable combination of voltage | |
581 | * swing and pre-emphasis levels */ | |
582 | /* if ( max_requested.postCursor2 > | |
583 | * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing)) | |
584 | * max_requested.postCursor2 = | |
585 | * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing); | |
586 | */ | |
587 | ||
588 | max_lt_setting->link_settings.link_rate = | |
589 | link_training_setting->link_settings.link_rate; | |
590 | max_lt_setting->link_settings.lane_count = | |
591 | link_training_setting->link_settings.lane_count; | |
592 | max_lt_setting->link_settings.link_spread = | |
593 | link_training_setting->link_settings.link_spread; | |
594 | ||
595 | for (lane = 0; lane < | |
596 | link_training_setting->link_settings.lane_count; | |
597 | lane++) { | |
598 | max_lt_setting->lane_settings[lane].VOLTAGE_SWING = | |
599 | max_requested.VOLTAGE_SWING; | |
600 | max_lt_setting->lane_settings[lane].PRE_EMPHASIS = | |
601 | max_requested.PRE_EMPHASIS; | |
602 | /*max_lt_setting->laneSettings[lane].postCursor2 = | |
603 | * max_requested.postCursor2; | |
604 | */ | |
605 | } | |
606 | ||
607 | } | |
608 | ||
e84ecdc5 | 609 | enum dc_status dp_get_lane_status_and_drive_settings( |
d0778ebf | 610 | struct dc_link *link, |
4562236b HW |
611 | const struct link_training_settings *link_training_setting, |
612 | union lane_status *ln_status, | |
613 | union lane_align_status_updated *ln_status_updated, | |
64c12b73 | 614 | struct link_training_settings *req_settings, |
615 | uint32_t offset) | |
4562236b | 616 | { |
64c12b73 | 617 | unsigned int lane01_status_address = DP_LANE0_1_STATUS; |
618 | uint8_t lane_adjust_offset = 4; | |
619 | unsigned int lane01_adjust_address; | |
4562236b | 620 | uint8_t dpcd_buf[6] = {0}; |
9a6a8075 HW |
621 | union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; |
622 | struct link_training_settings request_settings = { {0} }; | |
4562236b | 623 | uint32_t lane; |
e84ecdc5 | 624 | enum dc_status status; |
4562236b HW |
625 | |
626 | memset(req_settings, '\0', sizeof(struct link_training_settings)); | |
627 | ||
64c12b73 | 628 | if (is_repeater(link, offset)) { |
629 | lane01_status_address = | |
630 | DP_LANE0_1_STATUS_PHY_REPEATER1 + | |
631 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); | |
632 | lane_adjust_offset = 3; | |
633 | } | |
634 | ||
e84ecdc5 | 635 | status = core_link_read_dpcd( |
4562236b | 636 | link, |
64c12b73 | 637 | lane01_status_address, |
4562236b HW |
638 | (uint8_t *)(dpcd_buf), |
639 | sizeof(dpcd_buf)); | |
640 | ||
641 | for (lane = 0; lane < | |
642 | (uint32_t)(link_training_setting->link_settings.lane_count); | |
643 | lane++) { | |
644 | ||
645 | ln_status[lane].raw = | |
646 | get_nibble_at_index(&dpcd_buf[0], lane); | |
647 | dpcd_lane_adjust[lane].raw = | |
64c12b73 | 648 | get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane); |
4562236b HW |
649 | } |
650 | ||
651 | ln_status_updated->raw = dpcd_buf[2]; | |
652 | ||
460adc6b | 653 | if (is_repeater(link, offset)) { |
654 | DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" | |
655 | " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ", | |
656 | __func__, | |
657 | offset, | |
658 | lane01_status_address, dpcd_buf[0], | |
659 | lane01_status_address + 1, dpcd_buf[1]); | |
660 | } else { | |
661 | DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ", | |
662 | __func__, | |
663 | lane01_status_address, dpcd_buf[0], | |
664 | lane01_status_address + 1, dpcd_buf[1]); | |
665 | } | |
64c12b73 | 666 | lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1; |
667 | ||
668 | if (is_repeater(link, offset)) | |
669 | lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 + | |
670 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); | |
4562236b | 671 | |
460adc6b | 672 | if (is_repeater(link, offset)) { |
673 | DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" | |
674 | " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n", | |
675 | __func__, | |
676 | offset, | |
677 | lane01_adjust_address, | |
678 | dpcd_buf[lane_adjust_offset], | |
679 | lane01_adjust_address + 1, | |
680 | dpcd_buf[lane_adjust_offset + 1]); | |
681 | } else { | |
682 | DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n", | |
683 | __func__, | |
684 | lane01_adjust_address, | |
685 | dpcd_buf[lane_adjust_offset], | |
686 | lane01_adjust_address + 1, | |
687 | dpcd_buf[lane_adjust_offset + 1]); | |
688 | } | |
4562236b HW |
689 | |
690 | /*copy to req_settings*/ | |
691 | request_settings.link_settings.lane_count = | |
692 | link_training_setting->link_settings.lane_count; | |
693 | request_settings.link_settings.link_rate = | |
694 | link_training_setting->link_settings.link_rate; | |
695 | request_settings.link_settings.link_spread = | |
696 | link_training_setting->link_settings.link_spread; | |
697 | ||
698 | for (lane = 0; lane < | |
699 | (uint32_t)(link_training_setting->link_settings.lane_count); | |
700 | lane++) { | |
701 | ||
702 | request_settings.lane_settings[lane].VOLTAGE_SWING = | |
703 | (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits. | |
704 | VOLTAGE_SWING_LANE); | |
705 | request_settings.lane_settings[lane].PRE_EMPHASIS = | |
706 | (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits. | |
707 | PRE_EMPHASIS_LANE); | |
708 | } | |
709 | ||
710 | /*Note: for postcursor2, read adjusted | |
711 | * postcursor2 settings from*/ | |
712 | /*DpcdAddress_AdjustRequestPostCursor2 = | |
713 | *0x020C (not implemented yet)*/ | |
714 | ||
715 | /* we find the maximum of the requested settings across all lanes*/ | |
716 | /* and set this maximum for all lanes*/ | |
717 | find_max_drive_settings(&request_settings, req_settings); | |
718 | ||
719 | /* if post cursor 2 is needed in the future, | |
720 | * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C | |
721 | */ | |
722 | ||
e84ecdc5 | 723 | return status; |
4562236b HW |
724 | } |
725 | ||
e84ecdc5 | 726 | enum dc_status dpcd_set_lane_settings( |
d0778ebf | 727 | struct dc_link *link, |
64c12b73 | 728 | const struct link_training_settings *link_training_setting, |
729 | uint32_t offset) | |
4562236b HW |
730 | { |
731 | union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}}; | |
732 | uint32_t lane; | |
64c12b73 | 733 | unsigned int lane0_set_address; |
e84ecdc5 | 734 | enum dc_status status; |
64c12b73 | 735 | |
736 | lane0_set_address = DP_TRAINING_LANE0_SET; | |
737 | ||
738 | if (is_repeater(link, offset)) | |
739 | lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 + | |
740 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); | |
4562236b HW |
741 | |
742 | for (lane = 0; lane < | |
743 | (uint32_t)(link_training_setting-> | |
744 | link_settings.lane_count); | |
745 | lane++) { | |
746 | dpcd_lane[lane].bits.VOLTAGE_SWING_SET = | |
747 | (uint8_t)(link_training_setting-> | |
748 | lane_settings[lane].VOLTAGE_SWING); | |
749 | dpcd_lane[lane].bits.PRE_EMPHASIS_SET = | |
750 | (uint8_t)(link_training_setting-> | |
751 | lane_settings[lane].PRE_EMPHASIS); | |
752 | dpcd_lane[lane].bits.MAX_SWING_REACHED = | |
753 | (link_training_setting-> | |
754 | lane_settings[lane].VOLTAGE_SWING == | |
755 | VOLTAGE_SWING_MAX_LEVEL ? 1 : 0); | |
756 | dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED = | |
757 | (link_training_setting-> | |
758 | lane_settings[lane].PRE_EMPHASIS == | |
759 | PRE_EMPHASIS_MAX_LEVEL ? 1 : 0); | |
760 | } | |
761 | ||
e84ecdc5 | 762 | status = core_link_write_dpcd(link, |
64c12b73 | 763 | lane0_set_address, |
4562236b HW |
764 | (uint8_t *)(dpcd_lane), |
765 | link_training_setting->link_settings.lane_count); | |
766 | ||
767 | /* | |
768 | if (LTSettings.link.rate == LinkRate_High2) | |
769 | { | |
770 | DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0}; | |
771 | for ( uint32_t lane = 0; | |
772 | lane < lane_count_DPMax; lane++) | |
773 | { | |
774 | dpcd_lane2[lane].bits.post_cursor2_set = | |
775 | static_cast<unsigned char>( | |
776 | LTSettings.laneSettings[lane].postCursor2); | |
777 | dpcd_lane2[lane].bits.max_post_cursor2_reached = 0; | |
778 | } | |
779 | m_pDpcdAccessSrv->WriteDpcdData( | |
780 | DpcdAddress_Lane0Set2, | |
781 | reinterpret_cast<unsigned char*>(dpcd_lane2), | |
782 | LTSettings.link.lanes); | |
783 | } | |
784 | */ | |
785 | ||
460adc6b | 786 | if (is_repeater(link, offset)) { |
787 | DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n" | |
788 | " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", | |
789 | __func__, | |
790 | offset, | |
791 | lane0_set_address, | |
792 | dpcd_lane[0].bits.VOLTAGE_SWING_SET, | |
793 | dpcd_lane[0].bits.PRE_EMPHASIS_SET, | |
794 | dpcd_lane[0].bits.MAX_SWING_REACHED, | |
795 | dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); | |
4562236b | 796 | |
460adc6b | 797 | } else { |
798 | DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", | |
799 | __func__, | |
800 | lane0_set_address, | |
801 | dpcd_lane[0].bits.VOLTAGE_SWING_SET, | |
802 | dpcd_lane[0].bits.PRE_EMPHASIS_SET, | |
803 | dpcd_lane[0].bits.MAX_SWING_REACHED, | |
804 | dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED); | |
805 | } | |
d0778ebf | 806 | link->cur_lane_setting = link_training_setting->lane_settings[0]; |
4562236b | 807 | |
e84ecdc5 | 808 | return status; |
4562236b HW |
809 | } |
810 | ||
e84ecdc5 | 811 | bool dp_is_max_vs_reached( |
4562236b HW |
812 | const struct link_training_settings *lt_settings) |
813 | { | |
814 | uint32_t lane; | |
815 | for (lane = 0; lane < | |
816 | (uint32_t)(lt_settings->link_settings.lane_count); | |
817 | lane++) { | |
818 | if (lt_settings->lane_settings[lane].VOLTAGE_SWING | |
819 | == VOLTAGE_SWING_MAX_LEVEL) | |
820 | return true; | |
821 | } | |
822 | return false; | |
823 | ||
824 | } | |
825 | ||
4562236b | 826 | static bool perform_post_lt_adj_req_sequence( |
d0778ebf | 827 | struct dc_link *link, |
4562236b HW |
828 | struct link_training_settings *lt_settings) |
829 | { | |
830 | enum dc_lane_count lane_count = | |
831 | lt_settings->link_settings.lane_count; | |
832 | ||
833 | uint32_t adj_req_count; | |
834 | uint32_t adj_req_timer; | |
835 | bool req_drv_setting_changed; | |
836 | uint32_t lane; | |
837 | ||
838 | req_drv_setting_changed = false; | |
839 | for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT; | |
840 | adj_req_count++) { | |
841 | ||
842 | req_drv_setting_changed = false; | |
843 | ||
844 | for (adj_req_timer = 0; | |
845 | adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT; | |
846 | adj_req_timer++) { | |
847 | ||
848 | struct link_training_settings req_settings; | |
849 | union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; | |
850 | union lane_align_status_updated | |
851 | dpcd_lane_status_updated; | |
852 | ||
e84ecdc5 JK |
853 | dp_get_lane_status_and_drive_settings( |
854 | link, | |
855 | lt_settings, | |
856 | dpcd_lane_status, | |
857 | &dpcd_lane_status_updated, | |
858 | &req_settings, | |
859 | DPRX); | |
4562236b HW |
860 | |
861 | if (dpcd_lane_status_updated.bits. | |
862 | POST_LT_ADJ_REQ_IN_PROGRESS == 0) | |
863 | return true; | |
864 | ||
e84ecdc5 | 865 | if (!dp_is_cr_done(lane_count, dpcd_lane_status)) |
4562236b HW |
866 | return false; |
867 | ||
ebc22cbd WL |
868 | if (!is_ch_eq_done(lane_count, dpcd_lane_status) || |
869 | !is_symbol_locked(lane_count, dpcd_lane_status) || | |
870 | !is_interlane_aligned(dpcd_lane_status_updated)) | |
4562236b HW |
871 | return false; |
872 | ||
873 | for (lane = 0; lane < (uint32_t)(lane_count); lane++) { | |
874 | ||
875 | if (lt_settings-> | |
876 | lane_settings[lane].VOLTAGE_SWING != | |
877 | req_settings.lane_settings[lane]. | |
878 | VOLTAGE_SWING || | |
879 | lt_settings->lane_settings[lane].PRE_EMPHASIS != | |
880 | req_settings.lane_settings[lane].PRE_EMPHASIS) { | |
881 | ||
882 | req_drv_setting_changed = true; | |
883 | break; | |
884 | } | |
885 | } | |
886 | ||
887 | if (req_drv_setting_changed) { | |
e84ecdc5 | 888 | dp_update_drive_settings( |
9a6a8075 | 889 | lt_settings, req_settings); |
4562236b | 890 | |
d0778ebf | 891 | dc_link_dp_set_drive_settings(link, |
4562236b HW |
892 | lt_settings); |
893 | break; | |
894 | } | |
895 | ||
896 | msleep(1); | |
897 | } | |
898 | ||
899 | if (!req_drv_setting_changed) { | |
1296423b | 900 | DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n", |
4562236b HW |
901 | __func__); |
902 | ||
903 | ASSERT(0); | |
904 | return true; | |
905 | } | |
906 | } | |
1296423b | 907 | DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n", |
4562236b HW |
908 | __func__); |
909 | ||
910 | ASSERT(0); | |
911 | return true; | |
912 | ||
913 | } | |
914 | ||
64c12b73 | 915 | /* Only used for channel equalization */ |
916 | static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval) | |
917 | { | |
918 | unsigned int aux_rd_interval_us = 400; | |
919 | ||
920 | switch (dpcd_aux_read_interval) { | |
921 | case 0x01: | |
a71c76ac | 922 | aux_rd_interval_us = 4000; |
64c12b73 | 923 | break; |
924 | case 0x02: | |
a71c76ac | 925 | aux_rd_interval_us = 8000; |
64c12b73 | 926 | break; |
927 | case 0x03: | |
a71c76ac | 928 | aux_rd_interval_us = 12000; |
64c12b73 | 929 | break; |
930 | case 0x04: | |
931 | aux_rd_interval_us = 16000; | |
932 | break; | |
933 | default: | |
934 | break; | |
935 | } | |
936 | ||
937 | return aux_rd_interval_us; | |
938 | } | |
939 | ||
e84ecdc5 | 940 | enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count, |
94405cf6 WL |
941 | union lane_status *dpcd_lane_status) |
942 | { | |
943 | enum link_training_result result = LINK_TRAINING_SUCCESS; | |
944 | ||
945 | if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0) | |
946 | result = LINK_TRAINING_CR_FAIL_LANE0; | |
947 | else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0) | |
948 | result = LINK_TRAINING_CR_FAIL_LANE1; | |
949 | else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0) | |
950 | result = LINK_TRAINING_CR_FAIL_LANE23; | |
951 | else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0) | |
952 | result = LINK_TRAINING_CR_FAIL_LANE23; | |
953 | return result; | |
954 | } | |
955 | ||
820e3935 | 956 | static enum link_training_result perform_channel_equalization_sequence( |
d0778ebf | 957 | struct dc_link *link, |
64c12b73 | 958 | struct link_training_settings *lt_settings, |
959 | uint32_t offset) | |
4562236b HW |
960 | { |
961 | struct link_training_settings req_settings; | |
e0a6440a | 962 | enum dc_dp_training_pattern tr_pattern; |
4562236b | 963 | uint32_t retries_ch_eq; |
64c12b73 | 964 | uint32_t wait_time_microsec; |
4562236b | 965 | enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; |
9a6a8075 HW |
966 | union lane_align_status_updated dpcd_lane_status_updated = { {0} }; |
967 | union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } }; | |
4562236b | 968 | |
64c12b73 | 969 | /* Note: also check that TPS4 is a supported feature*/ |
970 | ||
e0a6440a | 971 | tr_pattern = lt_settings->pattern_for_eq; |
4562236b | 972 | |
64c12b73 | 973 | if (is_repeater(link, offset)) |
974 | tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4; | |
975 | ||
976 | dp_set_hw_training_pattern(link, tr_pattern, offset); | |
4562236b HW |
977 | |
978 | for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT; | |
979 | retries_ch_eq++) { | |
980 | ||
64c12b73 | 981 | dp_set_hw_lane_settings(link, lt_settings, offset); |
4562236b HW |
982 | |
983 | /* 2. update DPCD*/ | |
984 | if (!retries_ch_eq) | |
985 | /* EPR #361076 - write as a 5-byte burst, | |
64c12b73 | 986 | * but only for the 1-st iteration |
987 | */ | |
988 | ||
4562236b HW |
989 | dpcd_set_lt_pattern_and_lane_settings( |
990 | link, | |
991 | lt_settings, | |
64c12b73 | 992 | tr_pattern, offset); |
4562236b | 993 | else |
64c12b73 | 994 | dpcd_set_lane_settings(link, lt_settings, offset); |
4562236b HW |
995 | |
996 | /* 3. wait for receiver to lock-on*/ | |
64c12b73 | 997 | wait_time_microsec = lt_settings->eq_pattern_time; |
998 | ||
5fd21b39 | 999 | if (is_repeater(link, offset)) |
64c12b73 | 1000 | wait_time_microsec = |
1001 | translate_training_aux_read_interval( | |
5fd21b39 | 1002 | link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]); |
64c12b73 | 1003 | |
e84ecdc5 | 1004 | dp_wait_for_training_aux_rd_interval( |
64c12b73 | 1005 | link, |
1006 | wait_time_microsec); | |
4562236b HW |
1007 | |
1008 | /* 4. Read lane status and requested | |
1009 | * drive settings as set by the sink*/ | |
1010 | ||
e84ecdc5 | 1011 | dp_get_lane_status_and_drive_settings( |
4562236b HW |
1012 | link, |
1013 | lt_settings, | |
1014 | dpcd_lane_status, | |
1015 | &dpcd_lane_status_updated, | |
64c12b73 | 1016 | &req_settings, |
1017 | offset); | |
4562236b HW |
1018 | |
1019 | /* 5. check CR done*/ | |
e84ecdc5 | 1020 | if (!dp_is_cr_done(lane_count, dpcd_lane_status)) |
820e3935 | 1021 | return LINK_TRAINING_EQ_FAIL_CR; |
4562236b HW |
1022 | |
1023 | /* 6. check CHEQ done*/ | |
ebc22cbd WL |
1024 | if (is_ch_eq_done(lane_count, dpcd_lane_status) && |
1025 | is_symbol_locked(lane_count, dpcd_lane_status) && | |
1026 | is_interlane_aligned(dpcd_lane_status_updated)) | |
820e3935 | 1027 | return LINK_TRAINING_SUCCESS; |
4562236b HW |
1028 | |
1029 | /* 7. update VS/PE/PC2 in lt_settings*/ | |
e84ecdc5 | 1030 | dp_update_drive_settings(lt_settings, req_settings); |
4562236b HW |
1031 | } |
1032 | ||
820e3935 | 1033 | return LINK_TRAINING_EQ_FAIL_EQ; |
4562236b HW |
1034 | |
1035 | } | |
1036 | ||
b01f22ec DG |
1037 | static void start_clock_recovery_pattern_early(struct dc_link *link, |
1038 | struct link_training_settings *lt_settings, | |
1039 | uint32_t offset) | |
1040 | { | |
1041 | DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n", | |
1042 | __func__); | |
ce17ce17 | 1043 | dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset); |
b01f22ec DG |
1044 | dp_set_hw_lane_settings(link, lt_settings, offset); |
1045 | udelay(400); | |
1046 | } | |
1047 | ||
94405cf6 | 1048 | static enum link_training_result perform_clock_recovery_sequence( |
d0778ebf | 1049 | struct dc_link *link, |
64c12b73 | 1050 | struct link_training_settings *lt_settings, |
1051 | uint32_t offset) | |
4562236b HW |
1052 | { |
1053 | uint32_t retries_cr; | |
1054 | uint32_t retry_count; | |
64c12b73 | 1055 | uint32_t wait_time_microsec; |
4562236b | 1056 | struct link_training_settings req_settings; |
e0a6440a | 1057 | enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; |
4562236b HW |
1058 | union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; |
1059 | union lane_align_status_updated dpcd_lane_status_updated; | |
1060 | ||
1061 | retries_cr = 0; | |
1062 | retry_count = 0; | |
4562236b | 1063 | |
82054678 | 1064 | if (!link->ctx->dc->work_arounds.lt_early_cr_pattern) |
ce17ce17 | 1065 | dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset); |
4562236b HW |
1066 | |
1067 | /* najeeb - The synaptics MST hub can put the LT in | |
1068 | * infinite loop by switching the VS | |
1069 | */ | |
1070 | /* between level 0 and level 1 continuously, here | |
1071 | * we try for CR lock for LinkTrainingMaxCRRetry count*/ | |
1072 | while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) && | |
e0a6440a | 1073 | (retry_count < LINK_TRAINING_MAX_CR_RETRY)) { |
4562236b HW |
1074 | |
1075 | memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status)); | |
1076 | memset(&dpcd_lane_status_updated, '\0', | |
1077 | sizeof(dpcd_lane_status_updated)); | |
1078 | ||
1079 | /* 1. call HWSS to set lane settings*/ | |
1080 | dp_set_hw_lane_settings( | |
1081 | link, | |
64c12b73 | 1082 | lt_settings, |
1083 | offset); | |
4562236b HW |
1084 | |
1085 | /* 2. update DPCD of the receiver*/ | |
50d2c602 | 1086 | if (!retry_count) |
4562236b HW |
1087 | /* EPR #361076 - write as a 5-byte burst, |
1088 | * but only for the 1-st iteration.*/ | |
1089 | dpcd_set_lt_pattern_and_lane_settings( | |
1090 | link, | |
1091 | lt_settings, | |
ce17ce17 | 1092 | lt_settings->pattern_for_cr, |
64c12b73 | 1093 | offset); |
4562236b HW |
1094 | else |
1095 | dpcd_set_lane_settings( | |
1096 | link, | |
64c12b73 | 1097 | lt_settings, |
1098 | offset); | |
4562236b HW |
1099 | |
1100 | /* 3. wait receiver to lock-on*/ | |
64c12b73 | 1101 | wait_time_microsec = lt_settings->cr_pattern_time; |
1102 | ||
3128b285 | 1103 | if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) |
64c12b73 | 1104 | wait_time_microsec = TRAINING_AUX_RD_INTERVAL; |
1105 | ||
e84ecdc5 | 1106 | dp_wait_for_training_aux_rd_interval( |
4562236b | 1107 | link, |
64c12b73 | 1108 | wait_time_microsec); |
4562236b HW |
1109 | |
1110 | /* 4. Read lane status and requested drive | |
1111 | * settings as set by the sink | |
1112 | */ | |
e84ecdc5 | 1113 | dp_get_lane_status_and_drive_settings( |
4562236b HW |
1114 | link, |
1115 | lt_settings, | |
1116 | dpcd_lane_status, | |
1117 | &dpcd_lane_status_updated, | |
64c12b73 | 1118 | &req_settings, |
1119 | offset); | |
4562236b HW |
1120 | |
1121 | /* 5. check CR done*/ | |
e84ecdc5 | 1122 | if (dp_is_cr_done(lane_count, dpcd_lane_status)) |
94405cf6 | 1123 | return LINK_TRAINING_SUCCESS; |
4562236b HW |
1124 | |
1125 | /* 6. max VS reached*/ | |
e84ecdc5 | 1126 | if (dp_is_max_vs_reached(lt_settings)) |
94405cf6 | 1127 | break; |
4562236b | 1128 | |
3d223c55 DG |
1129 | /* 7. same lane settings*/ |
1130 | /* Note: settings are the same for all lanes, | |
1131 | * so comparing first lane is sufficient*/ | |
1132 | if ((lt_settings->lane_settings[0].VOLTAGE_SWING == | |
4562236b | 1133 | req_settings.lane_settings[0].VOLTAGE_SWING) |
3d223c55 DG |
1134 | && (lt_settings->lane_settings[0].PRE_EMPHASIS == |
1135 | req_settings.lane_settings[0].PRE_EMPHASIS)) | |
4562236b HW |
1136 | retries_cr++; |
1137 | else | |
1138 | retries_cr = 0; | |
1139 | ||
1140 | /* 8. update VS/PE/PC2 in lt_settings*/ | |
e84ecdc5 | 1141 | dp_update_drive_settings(lt_settings, req_settings); |
4562236b HW |
1142 | |
1143 | retry_count++; | |
1144 | } | |
1145 | ||
1146 | if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) { | |
1147 | ASSERT(0); | |
1296423b | 1148 | DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue", |
4f42a2dd | 1149 | __func__, |
4562236b HW |
1150 | LINK_TRAINING_MAX_CR_RETRY); |
1151 | ||
1152 | } | |
1153 | ||
e84ecdc5 | 1154 | return dp_get_cr_failure(lane_count, dpcd_lane_status); |
4562236b HW |
1155 | } |
1156 | ||
37f270c6 | 1157 | static inline enum link_training_result dp_transition_to_video_idle( |
d0778ebf | 1158 | struct dc_link *link, |
4562236b | 1159 | struct link_training_settings *lt_settings, |
94405cf6 | 1160 | enum link_training_result status) |
4562236b HW |
1161 | { |
1162 | union lane_count_set lane_count_set = { {0} }; | |
4562236b HW |
1163 | |
1164 | /* 4. mainlink output idle pattern*/ | |
1165 | dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0); | |
1166 | ||
1167 | /* | |
1168 | * 5. post training adjust if required | |
1169 | * If the upstream DPTX and downstream DPRX both support TPS4, | |
1170 | * TPS4 must be used instead of POST_LT_ADJ_REQ. | |
1171 | */ | |
c30267f5 | 1172 | if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 || |
cd6a9a1c WL |
1173 | lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) { |
1174 | /* delay 5ms after Main Link output idle pattern and then check | |
1175 | * DPCD 0202h. | |
1176 | */ | |
1177 | if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) { | |
1178 | msleep(5); | |
1179 | status = dp_check_link_loss_status(link, lt_settings); | |
1180 | } | |
4562236b | 1181 | return status; |
cd6a9a1c | 1182 | } |
4562236b | 1183 | |
94405cf6 | 1184 | if (status == LINK_TRAINING_SUCCESS && |
4562236b | 1185 | perform_post_lt_adj_req_sequence(link, lt_settings) == false) |
94405cf6 | 1186 | status = LINK_TRAINING_LQA_FAIL; |
4562236b HW |
1187 | |
1188 | lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count; | |
e0a6440a | 1189 | lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing; |
4562236b HW |
1190 | lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0; |
1191 | ||
1192 | core_link_write_dpcd( | |
1193 | link, | |
3a340294 | 1194 | DP_LANE_COUNT_SET, |
4562236b HW |
1195 | &lane_count_set.raw, |
1196 | sizeof(lane_count_set)); | |
1197 | ||
1198 | return status; | |
1199 | } | |
1200 | ||
573a0a03 | 1201 | enum link_training_result dp_check_link_loss_status( |
b246f90a MT |
1202 | struct dc_link *link, |
1203 | const struct link_training_settings *link_training_setting) | |
1204 | { | |
1205 | enum link_training_result status = LINK_TRAINING_SUCCESS; | |
b246f90a | 1206 | union lane_status lane_status; |
d9b91b1e | 1207 | uint8_t dpcd_buf[6] = {0}; |
b246f90a MT |
1208 | uint32_t lane; |
1209 | ||
1210 | core_link_read_dpcd( | |
d9b91b1e AC |
1211 | link, |
1212 | DP_SINK_COUNT, | |
1213 | (uint8_t *)(dpcd_buf), | |
1214 | sizeof(dpcd_buf)); | |
b246f90a MT |
1215 | |
1216 | /*parse lane status*/ | |
1217 | for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { | |
1218 | /* | |
1219 | * check lanes status | |
1220 | */ | |
d9b91b1e | 1221 | lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane); |
b246f90a MT |
1222 | |
1223 | if (!lane_status.bits.CHANNEL_EQ_DONE_0 || | |
1224 | !lane_status.bits.CR_DONE_0 || | |
1225 | !lane_status.bits.SYMBOL_LOCKED_0) { | |
1226 | /* if one of the channel equalization, clock | |
1227 | * recovery or symbol lock is dropped | |
1228 | * consider it as (link has been | |
1229 | * dropped) dp sink status has changed | |
1230 | */ | |
1231 | status = LINK_TRAINING_LINK_LOSS; | |
1232 | break; | |
1233 | } | |
1234 | } | |
1235 | ||
1236 | return status; | |
1237 | } | |
1238 | ||
4c247f8c | 1239 | static inline void decide_8b_10b_training_settings( |
e0a6440a | 1240 | struct dc_link *link, |
4562236b | 1241 | const struct dc_link_settings *link_setting, |
0b226322 | 1242 | const struct dc_link_training_overrides *overrides, |
e0a6440a | 1243 | struct link_training_settings *lt_settings) |
4562236b | 1244 | { |
e0a6440a | 1245 | uint32_t lane; |
4562236b | 1246 | |
e0a6440a | 1247 | memset(lt_settings, '\0', sizeof(struct link_training_settings)); |
94405cf6 | 1248 | |
e0a6440a DG |
1249 | /* Initialize link settings */ |
1250 | lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set; | |
1251 | lt_settings->link_settings.link_rate_set = link_setting->link_rate_set; | |
4562236b | 1252 | |
e0a6440a DG |
1253 | if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) |
1254 | lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate; | |
1255 | else | |
1256 | lt_settings->link_settings.link_rate = link_setting->link_rate; | |
4562236b | 1257 | |
e0a6440a DG |
1258 | if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN) |
1259 | lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count; | |
1260 | else | |
1261 | lt_settings->link_settings.lane_count = link_setting->lane_count; | |
4562236b HW |
1262 | |
1263 | /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/ | |
1264 | ||
1265 | /* TODO hard coded to SS for now | |
1266 | * lt_settings.link_settings.link_spread = | |
1267 | * dal_display_path_is_ss_supported( | |
1268 | * path_mode->display_path) ? | |
1269 | * LINK_SPREAD_05_DOWNSPREAD_30KHZ : | |
1270 | * LINK_SPREAD_DISABLED; | |
1271 | */ | |
e0a6440a | 1272 | /* Initialize link spread */ |
ad830e7a | 1273 | if (link->dp_ss_off) |
e0a6440a | 1274 | lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED; |
0b226322 | 1275 | else if (overrides->downspread != NULL) |
e0a6440a | 1276 | lt_settings->link_settings.link_spread |
0b226322 | 1277 | = *overrides->downspread |
e0a6440a DG |
1278 | ? LINK_SPREAD_05_DOWNSPREAD_30KHZ |
1279 | : LINK_SPREAD_DISABLED; | |
ad830e7a | 1280 | else |
e0a6440a | 1281 | lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ; |
4562236b | 1282 | |
f1900a9b WL |
1283 | lt_settings->lttpr_mode = link->lttpr_mode; |
1284 | ||
e0a6440a | 1285 | /* Initialize lane settings overrides */ |
0b226322 DG |
1286 | if (overrides->voltage_swing != NULL) |
1287 | lt_settings->voltage_swing = overrides->voltage_swing; | |
4562236b | 1288 | |
0b226322 DG |
1289 | if (overrides->pre_emphasis != NULL) |
1290 | lt_settings->pre_emphasis = overrides->pre_emphasis; | |
4562236b | 1291 | |
0b226322 DG |
1292 | if (overrides->post_cursor2 != NULL) |
1293 | lt_settings->post_cursor2 = overrides->post_cursor2; | |
e0a6440a DG |
1294 | |
1295 | /* Initialize lane settings (VS/PE/PC2) */ | |
1296 | for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { | |
1297 | lt_settings->lane_settings[lane].VOLTAGE_SWING = | |
1298 | lt_settings->voltage_swing != NULL ? | |
1299 | *lt_settings->voltage_swing : | |
1300 | VOLTAGE_SWING_LEVEL0; | |
1301 | lt_settings->lane_settings[lane].PRE_EMPHASIS = | |
1302 | lt_settings->pre_emphasis != NULL ? | |
1303 | *lt_settings->pre_emphasis | |
1304 | : PRE_EMPHASIS_DISABLED; | |
1305 | lt_settings->lane_settings[lane].POST_CURSOR2 = | |
1306 | lt_settings->post_cursor2 != NULL ? | |
1307 | *lt_settings->post_cursor2 | |
1308 | : POST_CURSOR2_DISABLED; | |
820e3935 | 1309 | } |
4562236b | 1310 | |
e0a6440a | 1311 | /* Initialize training timings */ |
0b226322 DG |
1312 | if (overrides->cr_pattern_time != NULL) |
1313 | lt_settings->cr_pattern_time = *overrides->cr_pattern_time; | |
e0a6440a | 1314 | else |
b50d5551 | 1315 | lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting); |
e0a6440a | 1316 | |
0b226322 DG |
1317 | if (overrides->eq_pattern_time != NULL) |
1318 | lt_settings->eq_pattern_time = *overrides->eq_pattern_time; | |
e0a6440a | 1319 | else |
3fb068c3 | 1320 | lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting); |
e0a6440a | 1321 | |
ce17ce17 WL |
1322 | if (overrides->pattern_for_cr != NULL) |
1323 | lt_settings->pattern_for_cr = *overrides->pattern_for_cr; | |
1324 | else | |
1325 | lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting); | |
0b226322 DG |
1326 | if (overrides->pattern_for_eq != NULL) |
1327 | lt_settings->pattern_for_eq = *overrides->pattern_for_eq; | |
e0a6440a | 1328 | else |
ce17ce17 | 1329 | lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting); |
e0a6440a | 1330 | |
0b226322 DG |
1331 | if (overrides->enhanced_framing != NULL) |
1332 | lt_settings->enhanced_framing = *overrides->enhanced_framing; | |
e0a6440a DG |
1333 | else |
1334 | lt_settings->enhanced_framing = 1; | |
3df21257 WL |
1335 | |
1336 | if (link->preferred_training_settings.fec_enable != NULL) | |
1337 | lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable; | |
1338 | else | |
1339 | lt_settings->should_set_fec_ready = true; | |
e0a6440a DG |
1340 | } |
1341 | ||
7211b605 | 1342 | void dp_decide_training_settings( |
4c247f8c WL |
1343 | struct dc_link *link, |
1344 | const struct dc_link_settings *link_settings, | |
1345 | const struct dc_link_training_overrides *overrides, | |
1346 | struct link_training_settings *lt_settings) | |
1347 | { | |
1348 | if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) | |
1349 | decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings); | |
1350 | } | |
1351 | ||
1352 | ||
573a0a03 | 1353 | uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count) |
64c12b73 | 1354 | { |
1355 | switch (lttpr_repeater_count) { | |
1356 | case 0x80: // 1 lttpr repeater | |
1357 | return 1; | |
1358 | case 0x40: // 2 lttpr repeaters | |
1359 | return 2; | |
1360 | case 0x20: // 3 lttpr repeaters | |
1361 | return 3; | |
1362 | case 0x10: // 4 lttpr repeaters | |
1363 | return 4; | |
1364 | case 0x08: // 5 lttpr repeaters | |
1365 | return 5; | |
1366 | case 0x04: // 6 lttpr repeaters | |
1367 | return 6; | |
1368 | case 0x02: // 7 lttpr repeaters | |
1369 | return 7; | |
1370 | case 0x01: // 8 lttpr repeaters | |
1371 | return 8; | |
1372 | default: | |
1373 | break; | |
1374 | } | |
1375 | return 0; // invalid value | |
1376 | } | |
1377 | ||
7211b605 | 1378 | enum dc_status configure_lttpr_mode_transparent(struct dc_link *link) |
3128b285 WC |
1379 | { |
1380 | uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT; | |
1381 | ||
f1900a9b | 1382 | DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__); |
7211b605 | 1383 | return core_link_write_dpcd(link, |
3128b285 WC |
1384 | DP_PHY_REPEATER_MODE, |
1385 | (uint8_t *)&repeater_mode, | |
1386 | sizeof(repeater_mode)); | |
1387 | } | |
1388 | ||
7211b605 | 1389 | enum dc_status configure_lttpr_mode_non_transparent( |
f1900a9b WL |
1390 | struct dc_link *link, |
1391 | const struct link_training_settings *lt_settings) | |
bad7ab0b | 1392 | { |
1393 | /* aux timeout is already set to extended */ | |
1394 | /* RESET/SET lttpr mode to enable non transparent mode */ | |
64c12b73 | 1395 | uint8_t repeater_cnt; |
1396 | uint32_t aux_interval_address; | |
1397 | uint8_t repeater_id; | |
a166f86e | 1398 | enum dc_status result = DC_ERROR_UNEXPECTED; |
61aa7a6f | 1399 | uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT; |
bad7ab0b | 1400 | |
f1900a9b WL |
1401 | enum dp_link_encoding encoding = dp_get_link_encoding_format(<_settings->link_settings); |
1402 | ||
1403 | if (encoding == DP_8b_10b_ENCODING) { | |
1404 | DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__); | |
1405 | result = core_link_write_dpcd(link, | |
1406 | DP_PHY_REPEATER_MODE, | |
1407 | (uint8_t *)&repeater_mode, | |
1408 | sizeof(repeater_mode)); | |
1409 | ||
1410 | } | |
bad7ab0b | 1411 | |
a166f86e | 1412 | if (result == DC_OK) { |
1413 | link->dpcd_caps.lttpr_caps.mode = repeater_mode; | |
1414 | } | |
1415 | ||
3128b285 | 1416 | if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) { |
460adc6b | 1417 | |
c14f2507 | 1418 | DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__); |
460adc6b | 1419 | |
61aa7a6f | 1420 | repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT; |
a166f86e | 1421 | result = core_link_write_dpcd(link, |
bad7ab0b | 1422 | DP_PHY_REPEATER_MODE, |
1423 | (uint8_t *)&repeater_mode, | |
1424 | sizeof(repeater_mode)); | |
64c12b73 | 1425 | |
a166f86e | 1426 | if (result == DC_OK) { |
1427 | link->dpcd_caps.lttpr_caps.mode = repeater_mode; | |
1428 | } | |
1429 | ||
f1900a9b WL |
1430 | if (encoding == DP_8b_10b_ENCODING) { |
1431 | repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); | |
1432 | for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) { | |
1433 | aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 + | |
1434 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1)); | |
1435 | core_link_read_dpcd( | |
1436 | link, | |
1437 | aux_interval_address, | |
1438 | (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1], | |
1439 | sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1])); | |
1440 | link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F; | |
1441 | } | |
64c12b73 | 1442 | } |
bad7ab0b | 1443 | } |
7211b605 JK |
1444 | |
1445 | return result; | |
bad7ab0b | 1446 | } |
1447 | ||
64c12b73 | 1448 | static void repeater_training_done(struct dc_link *link, uint32_t offset) |
1449 | { | |
1450 | union dpcd_training_pattern dpcd_pattern = { {0} }; | |
1451 | ||
1452 | const uint32_t dpcd_base_lt_offset = | |
1453 | DP_TRAINING_PATTERN_SET_PHY_REPEATER1 + | |
1454 | ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1)); | |
1455 | /* Set training not in progress*/ | |
1456 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE; | |
1457 | ||
1458 | core_link_write_dpcd( | |
1459 | link, | |
1460 | dpcd_base_lt_offset, | |
1461 | &dpcd_pattern.raw, | |
1462 | 1); | |
1463 | ||
460adc6b | 1464 | DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n", |
64c12b73 | 1465 | __func__, |
460adc6b | 1466 | offset, |
64c12b73 | 1467 | dpcd_base_lt_offset, |
1468 | dpcd_pattern.v1_4.TRAINING_PATTERN_SET); | |
1469 | } | |
1470 | ||
e0a6440a DG |
1471 | static void print_status_message( |
1472 | struct dc_link *link, | |
1473 | const struct link_training_settings *lt_settings, | |
1474 | enum link_training_result status) | |
1475 | { | |
1476 | char *link_rate = "Unknown"; | |
1477 | char *lt_result = "Unknown"; | |
1478 | char *lt_spread = "Disabled"; | |
4562236b | 1479 | |
e0a6440a | 1480 | switch (lt_settings->link_settings.link_rate) { |
4562236b HW |
1481 | case LINK_RATE_LOW: |
1482 | link_rate = "RBR"; | |
1483 | break; | |
5c8a6c71 JZ |
1484 | case LINK_RATE_RATE_2: |
1485 | link_rate = "R2"; | |
1486 | break; | |
1487 | case LINK_RATE_RATE_3: | |
1488 | link_rate = "R3"; | |
1489 | break; | |
4562236b HW |
1490 | case LINK_RATE_HIGH: |
1491 | link_rate = "HBR"; | |
1492 | break; | |
4562236b HW |
1493 | case LINK_RATE_RBR2: |
1494 | link_rate = "RBR2"; | |
1495 | break; | |
5c8a6c71 JZ |
1496 | case LINK_RATE_RATE_6: |
1497 | link_rate = "R6"; | |
1498 | break; | |
1499 | case LINK_RATE_HIGH2: | |
1500 | link_rate = "HBR2"; | |
1501 | break; | |
4562236b HW |
1502 | case LINK_RATE_HIGH3: |
1503 | link_rate = "HBR3"; | |
1504 | break; | |
1505 | default: | |
1506 | break; | |
1507 | } | |
1508 | ||
94405cf6 WL |
1509 | switch (status) { |
1510 | case LINK_TRAINING_SUCCESS: | |
1511 | lt_result = "pass"; | |
1512 | break; | |
1513 | case LINK_TRAINING_CR_FAIL_LANE0: | |
1514 | lt_result = "CR failed lane0"; | |
1515 | break; | |
1516 | case LINK_TRAINING_CR_FAIL_LANE1: | |
1517 | lt_result = "CR failed lane1"; | |
1518 | break; | |
1519 | case LINK_TRAINING_CR_FAIL_LANE23: | |
1520 | lt_result = "CR failed lane23"; | |
1521 | break; | |
1522 | case LINK_TRAINING_EQ_FAIL_CR: | |
1523 | lt_result = "CR failed in EQ"; | |
1524 | break; | |
1525 | case LINK_TRAINING_EQ_FAIL_EQ: | |
1526 | lt_result = "EQ failed"; | |
1527 | break; | |
1528 | case LINK_TRAINING_LQA_FAIL: | |
1529 | lt_result = "LQA failed"; | |
1530 | break; | |
b246f90a MT |
1531 | case LINK_TRAINING_LINK_LOSS: |
1532 | lt_result = "Link loss"; | |
1533 | break; | |
94405cf6 WL |
1534 | default: |
1535 | break; | |
1536 | } | |
1537 | ||
e0a6440a DG |
1538 | switch (lt_settings->link_settings.link_spread) { |
1539 | case LINK_SPREAD_DISABLED: | |
1540 | lt_spread = "Disabled"; | |
1541 | break; | |
1542 | case LINK_SPREAD_05_DOWNSPREAD_30KHZ: | |
1543 | lt_spread = "0.5% 30KHz"; | |
1544 | break; | |
1545 | case LINK_SPREAD_05_DOWNSPREAD_33KHZ: | |
1546 | lt_spread = "0.5% 33KHz"; | |
1547 | break; | |
1548 | default: | |
1549 | break; | |
1550 | } | |
1551 | ||
4562236b | 1552 | /* Connectivity log: link training */ |
e0a6440a DG |
1553 | CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s", |
1554 | link_rate, | |
1555 | lt_settings->link_settings.lane_count, | |
1556 | lt_result, | |
1557 | lt_settings->lane_settings[0].VOLTAGE_SWING, | |
1558 | lt_settings->lane_settings[0].PRE_EMPHASIS, | |
1559 | lt_spread); | |
1560 | } | |
1561 | ||
64c12b73 | 1562 | void dc_link_dp_set_drive_settings( |
1563 | struct dc_link *link, | |
1564 | struct link_training_settings *lt_settings) | |
1565 | { | |
1566 | /* program ASIC PHY settings*/ | |
1567 | dp_set_hw_lane_settings(link, lt_settings, DPRX); | |
1568 | ||
1569 | /* Notify DP sink the PHY settings from source */ | |
1570 | dpcd_set_lane_settings(link, lt_settings, DPRX); | |
1571 | } | |
1572 | ||
e0a6440a DG |
1573 | bool dc_link_dp_perform_link_training_skip_aux( |
1574 | struct dc_link *link, | |
1575 | const struct dc_link_settings *link_setting) | |
1576 | { | |
1577 | struct link_training_settings lt_settings; | |
e0a6440a | 1578 | |
7211b605 | 1579 | dp_decide_training_settings( |
0b226322 DG |
1580 | link, |
1581 | link_setting, | |
1582 | &link->preferred_training_settings, | |
1583 | <_settings); | |
e0a6440a DG |
1584 | |
1585 | /* 1. Perform_clock_recovery_sequence. */ | |
1586 | ||
1587 | /* transmit training pattern for clock recovery */ | |
ce17ce17 | 1588 | dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX); |
e0a6440a DG |
1589 | |
1590 | /* call HWSS to set lane settings*/ | |
64c12b73 | 1591 | dp_set_hw_lane_settings(link, <_settings, DPRX); |
e0a6440a DG |
1592 | |
1593 | /* wait receiver to lock-on*/ | |
e84ecdc5 | 1594 | dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time); |
e0a6440a DG |
1595 | |
1596 | /* 2. Perform_channel_equalization_sequence. */ | |
1597 | ||
1598 | /* transmit training pattern for channel equalization. */ | |
64c12b73 | 1599 | dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX); |
e0a6440a DG |
1600 | |
1601 | /* call HWSS to set lane settings*/ | |
64c12b73 | 1602 | dp_set_hw_lane_settings(link, <_settings, DPRX); |
e0a6440a DG |
1603 | |
1604 | /* wait receiver to lock-on. */ | |
e84ecdc5 | 1605 | dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time); |
e0a6440a DG |
1606 | |
1607 | /* 3. Perform_link_training_int. */ | |
1608 | ||
1609 | /* Mainlink output idle pattern. */ | |
1610 | dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0); | |
1611 | ||
1612 | print_status_message(link, <_settings, LINK_TRAINING_SUCCESS); | |
1613 | ||
1614 | return true; | |
1615 | } | |
1616 | ||
7211b605 JK |
1617 | enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings) |
1618 | { | |
1619 | enum dc_status status = DC_OK; | |
1620 | ||
1621 | if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT) | |
1622 | status = configure_lttpr_mode_transparent(link); | |
1623 | ||
1624 | else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) | |
1625 | status = configure_lttpr_mode_non_transparent(link, lt_settings); | |
1626 | ||
1627 | return status; | |
1628 | } | |
1629 | ||
3df21257 WL |
1630 | static void dpcd_exit_training_mode(struct dc_link *link) |
1631 | { | |
3df21257 WL |
1632 | |
1633 | /* clear training pattern set */ | |
cd6a9a1c | 1634 | dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE); |
3df21257 WL |
1635 | } |
1636 | ||
1637 | enum dc_status dpcd_configure_channel_coding(struct dc_link *link, | |
1638 | struct link_training_settings *lt_settings) | |
1639 | { | |
1640 | enum dp_link_encoding encoding = | |
1641 | dp_get_link_encoding_format( | |
1642 | <_settings->link_settings); | |
1643 | enum dc_status status; | |
1644 | ||
1645 | status = core_link_write_dpcd( | |
1646 | link, | |
1647 | DP_MAIN_LINK_CHANNEL_CODING_SET, | |
1648 | (uint8_t *) &encoding, | |
1649 | 1); | |
1650 | DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n", | |
1651 | __func__, | |
1652 | DP_MAIN_LINK_CHANNEL_CODING_SET, | |
1653 | encoding); | |
1654 | ||
1655 | return status; | |
1656 | } | |
1657 | ||
cd6a9a1c WL |
1658 | static enum link_training_result dp_perform_8b_10b_link_training( |
1659 | struct dc_link *link, | |
1660 | struct link_training_settings *lt_settings) | |
e0a6440a DG |
1661 | { |
1662 | enum link_training_result status = LINK_TRAINING_SUCCESS; | |
e0a6440a | 1663 | |
cd6a9a1c WL |
1664 | uint8_t repeater_cnt; |
1665 | uint8_t repeater_id; | |
bcc5042a | 1666 | |
82054678 | 1667 | if (link->ctx->dc->work_arounds.lt_early_cr_pattern) |
cd6a9a1c | 1668 | start_clock_recovery_pattern_early(link, lt_settings, DPRX); |
834a9a9f ML |
1669 | |
1670 | /* 1. set link rate, lane count and spread. */ | |
cd6a9a1c | 1671 | dpcd_set_link_settings(link, lt_settings); |
e0a6440a | 1672 | |
3128b285 | 1673 | if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) { |
008a4016 | 1674 | |
64c12b73 | 1675 | /* 2. perform link training (set link training done |
1676 | * to false is done as well) | |
1677 | */ | |
573a0a03 | 1678 | repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); |
64c12b73 | 1679 | |
1680 | for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS); | |
1681 | repeater_id--) { | |
cd6a9a1c | 1682 | status = perform_clock_recovery_sequence(link, lt_settings, repeater_id); |
64c12b73 | 1683 | |
1684 | if (status != LINK_TRAINING_SUCCESS) | |
1685 | break; | |
1686 | ||
1687 | status = perform_channel_equalization_sequence(link, | |
cd6a9a1c | 1688 | lt_settings, |
64c12b73 | 1689 | repeater_id); |
1690 | ||
1691 | if (status != LINK_TRAINING_SUCCESS) | |
1692 | break; | |
1693 | ||
1694 | repeater_training_done(link, repeater_id); | |
1695 | } | |
1696 | } | |
1697 | ||
1698 | if (status == LINK_TRAINING_SUCCESS) { | |
cd6a9a1c | 1699 | status = perform_clock_recovery_sequence(link, lt_settings, DPRX); |
e0a6440a DG |
1700 | if (status == LINK_TRAINING_SUCCESS) { |
1701 | status = perform_channel_equalization_sequence(link, | |
cd6a9a1c | 1702 | lt_settings, |
64c12b73 | 1703 | DPRX); |
1704 | } | |
e0a6440a DG |
1705 | } |
1706 | ||
cd6a9a1c WL |
1707 | return status; |
1708 | } | |
1709 | ||
1710 | enum link_training_result dc_link_dp_perform_link_training( | |
1711 | struct dc_link *link, | |
1712 | const struct dc_link_settings *link_settings, | |
1713 | bool skip_video_pattern) | |
1714 | { | |
1715 | enum link_training_result status = LINK_TRAINING_SUCCESS; | |
1716 | struct link_training_settings lt_settings; | |
1717 | enum dp_link_encoding encoding = | |
1718 | dp_get_link_encoding_format(link_settings); | |
1719 | ||
1720 | /* decide training settings */ | |
1721 | dp_decide_training_settings( | |
1722 | link, | |
1723 | link_settings, | |
1724 | &link->preferred_training_settings, | |
1725 | <_settings); | |
1726 | ||
1727 | /* reset previous training states */ | |
1728 | dpcd_exit_training_mode(link); | |
1729 | ||
1730 | /* configure link prior to entering training mode */ | |
1731 | dpcd_configure_lttpr_mode(link, <_settings); | |
1732 | dp_set_fec_ready(link, lt_settings.should_set_fec_ready); | |
1733 | dpcd_configure_channel_coding(link, <_settings); | |
1734 | ||
1735 | /* enter training mode: | |
1736 | * Per DP specs starting from here, DPTX device shall not issue | |
1737 | * Non-LT AUX transactions inside training mode. | |
1738 | */ | |
1739 | if (encoding == DP_8b_10b_ENCODING) | |
1740 | status = dp_perform_8b_10b_link_training(link, <_settings); | |
1741 | else | |
1742 | ASSERT(0); | |
1743 | ||
1744 | /* exit training mode and switch to video idle */ | |
1745 | dpcd_exit_training_mode(link); | |
1746 | if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) | |
37f270c6 | 1747 | status = dp_transition_to_video_idle(link, |
e0a6440a DG |
1748 | <_settings, |
1749 | status); | |
e0a6440a | 1750 | |
cd6a9a1c | 1751 | /* dump debug data */ |
e0a6440a | 1752 | print_status_message(link, <_settings, status); |
d6e75df4 | 1753 | if (status != LINK_TRAINING_SUCCESS) |
cfd84fd3 | 1754 | link->ctx->dc->debug_data.ltFailCount++; |
4562236b HW |
1755 | return status; |
1756 | } | |
1757 | ||
9127daa0 SW |
1758 | static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream) |
1759 | { | |
1760 | struct dc_link *link = stream->link; | |
1761 | enum dp_panel_mode panel_mode = dp_get_panel_mode(link); | |
1762 | #ifdef CONFIG_DRM_AMD_DC_HDCP | |
1763 | struct cp_psp *cp_psp = &stream->ctx->cp_psp; | |
1764 | #endif | |
1765 | ||
1766 | /* ASSR must be supported on the panel */ | |
1767 | if (panel_mode == DP_PANEL_MODE_DEFAULT) | |
1768 | return panel_mode; | |
1769 | ||
1770 | /* eDP or internal DP only */ | |
1771 | if (link->connector_signal != SIGNAL_TYPE_EDP && | |
1772 | !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && | |
1773 | link->is_internal_display)) | |
1774 | return DP_PANEL_MODE_DEFAULT; | |
1775 | ||
1776 | #ifdef CONFIG_DRM_AMD_DC_HDCP | |
1777 | if (cp_psp && cp_psp->funcs.enable_assr) { | |
1778 | if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) { | |
1779 | /* since eDP implies ASSR on, change panel | |
1780 | * mode to disable ASSR | |
1781 | */ | |
1782 | panel_mode = DP_PANEL_MODE_DEFAULT; | |
1783 | } | |
1784 | } else | |
1785 | panel_mode = DP_PANEL_MODE_DEFAULT; | |
1786 | ||
1787 | #else | |
1788 | /* turn off ASSR if the implementation is not compiled in */ | |
1789 | panel_mode = DP_PANEL_MODE_DEFAULT; | |
1790 | #endif | |
1791 | return panel_mode; | |
1792 | } | |
1793 | ||
4562236b | 1794 | bool perform_link_training_with_retries( |
4562236b HW |
1795 | const struct dc_link_settings *link_setting, |
1796 | bool skip_video_pattern, | |
832aa63b PH |
1797 | int attempts, |
1798 | struct pipe_ctx *pipe_ctx, | |
82253671 JK |
1799 | enum signal_type signal, |
1800 | bool do_fallback) | |
4562236b HW |
1801 | { |
1802 | uint8_t j; | |
1803 | uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY; | |
832aa63b PH |
1804 | struct dc_stream_state *stream = pipe_ctx->stream; |
1805 | struct dc_link *link = stream->link; | |
9127daa0 | 1806 | enum dp_panel_mode panel_mode; |
82253671 JK |
1807 | struct link_encoder *link_enc; |
1808 | enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0; | |
1809 | struct dc_link_settings currnet_setting = *link_setting; | |
1810 | ||
1811 | /* Dynamically assigned link encoders associated with stream rather than | |
1812 | * link. | |
1813 | */ | |
1814 | if (link->dc->res_pool->funcs->link_encs_assign) | |
1815 | link_enc = stream->link_enc; | |
1816 | else | |
1817 | link_enc = link->link_enc; | |
1818 | ASSERT(link_enc); | |
4562236b | 1819 | |
eec3303d AC |
1820 | /* We need to do this before the link training to ensure the idle pattern in SST |
1821 | * mode will be sent right after the link training | |
1822 | */ | |
82253671 | 1823 | link_enc->funcs->connect_dig_be_to_fe(link_enc, |
eec3303d AC |
1824 | pipe_ctx->stream_res.stream_enc->id, true); |
1825 | ||
4562236b HW |
1826 | for (j = 0; j < attempts; ++j) { |
1827 | ||
172c9b77 AT |
1828 | DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n", |
1829 | __func__, (unsigned int)j + 1, attempts); | |
1830 | ||
832aa63b PH |
1831 | dp_enable_link_phy( |
1832 | link, | |
1833 | signal, | |
1834 | pipe_ctx->clock_source->id, | |
82253671 | 1835 | &currnet_setting); |
832aa63b | 1836 | |
eec3303d AC |
1837 | if (stream->sink_patches.dppowerup_delay > 0) { |
1838 | int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay; | |
1839 | ||
832aa63b PH |
1840 | msleep(delay_dp_power_up_in_ms); |
1841 | } | |
1842 | ||
9127daa0 | 1843 | panel_mode = try_enable_assr(stream); |
832aa63b | 1844 | dp_set_panel_mode(link, panel_mode); |
9127daa0 SW |
1845 | DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n", |
1846 | link->link_index, | |
1847 | panel_mode != DP_PANEL_MODE_DEFAULT); | |
832aa63b | 1848 | |
832aa63b | 1849 | if (link->aux_access_disabled) { |
82253671 | 1850 | dc_link_dp_perform_link_training_skip_aux(link, &currnet_setting); |
832aa63b | 1851 | return true; |
79ed7354 | 1852 | } else { |
79ed7354 JK |
1853 | status = dc_link_dp_perform_link_training( |
1854 | link, | |
82253671 | 1855 | &currnet_setting, |
79ed7354 JK |
1856 | skip_video_pattern); |
1857 | if (status == LINK_TRAINING_SUCCESS) | |
1858 | return true; | |
1859 | } | |
4562236b | 1860 | |
832aa63b PH |
1861 | /* latest link training still fail, skip delay and keep PHY on |
1862 | */ | |
82253671 | 1863 | if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY) |
832aa63b PH |
1864 | break; |
1865 | ||
172c9b77 AT |
1866 | DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n", |
1867 | __func__, (unsigned int)j + 1, attempts); | |
1868 | ||
832aa63b PH |
1869 | dp_disable_link_phy(link, signal); |
1870 | ||
82253671 JK |
1871 | /* Abort link training if failure due to sink being unplugged. */ |
1872 | if (status == LINK_TRAINING_ABORT) | |
1873 | break; | |
1874 | else if (do_fallback) { | |
1875 | decide_fallback_link_setting(*link_setting, &currnet_setting, status); | |
1876 | /* Fail link training if reduced link bandwidth no longer meets | |
1877 | * stream requirements. | |
1878 | */ | |
1879 | if (dc_bandwidth_in_kbps_from_timing(&stream->timing) < | |
1880 | dc_link_bandwidth_kbps(link, &currnet_setting)) | |
1881 | break; | |
1882 | } | |
1883 | ||
4562236b | 1884 | msleep(delay_between_attempts); |
832aa63b | 1885 | |
4562236b HW |
1886 | delay_between_attempts += LINK_TRAINING_RETRY_DELAY; |
1887 | } | |
1888 | ||
1889 | return false; | |
1890 | } | |
1891 | ||
0b226322 DG |
1892 | static enum clock_source_id get_clock_source_id(struct dc_link *link) |
1893 | { | |
1894 | enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED; | |
1895 | struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; | |
1896 | ||
1897 | if (dp_cs != NULL) { | |
1898 | dp_cs_id = dp_cs->id; | |
1899 | } else { | |
1900 | /* | |
1901 | * dp clock source is not initialized for some reason. | |
1902 | * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used | |
1903 | */ | |
1904 | ASSERT(dp_cs); | |
1905 | } | |
1906 | ||
1907 | return dp_cs_id; | |
1908 | } | |
1909 | ||
1910 | static void set_dp_mst_mode(struct dc_link *link, bool mst_enable) | |
1911 | { | |
1912 | if (mst_enable == false && | |
1913 | link->type == dc_connection_mst_branch) { | |
1914 | /* Disable MST on link. Use only local sink. */ | |
1915 | dp_disable_link_phy_mst(link, link->connector_signal); | |
1916 | ||
1917 | link->type = dc_connection_single; | |
1918 | link->local_sink = link->remote_sinks[0]; | |
1919 | link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT; | |
1920 | } else if (mst_enable == true && | |
1921 | link->type == dc_connection_single && | |
1922 | link->remote_sinks[0] != NULL) { | |
1923 | /* Re-enable MST on link. */ | |
1924 | dp_disable_link_phy(link, link->connector_signal); | |
1925 | dp_enable_mst_on_sink(link, true); | |
1926 | ||
1927 | link->type = dc_connection_mst_branch; | |
1928 | link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST; | |
1929 | } | |
1930 | } | |
1931 | ||
1932 | bool dc_link_dp_sync_lt_begin(struct dc_link *link) | |
1933 | { | |
1934 | /* Begin Sync LT. During this time, | |
1935 | * DPCD:600h must not be powered down. | |
1936 | */ | |
1937 | link->sync_lt_in_progress = true; | |
1938 | ||
1939 | /*Clear any existing preferred settings.*/ | |
1940 | memset(&link->preferred_training_settings, 0, | |
1941 | sizeof(struct dc_link_training_overrides)); | |
1942 | memset(&link->preferred_link_setting, 0, | |
1943 | sizeof(struct dc_link_settings)); | |
1944 | ||
1945 | return true; | |
1946 | } | |
1947 | ||
1948 | enum link_training_result dc_link_dp_sync_lt_attempt( | |
1949 | struct dc_link *link, | |
1950 | struct dc_link_settings *link_settings, | |
1951 | struct dc_link_training_overrides *lt_overrides) | |
1952 | { | |
1953 | struct link_training_settings lt_settings; | |
1954 | enum link_training_result lt_status = LINK_TRAINING_SUCCESS; | |
1955 | enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT; | |
1956 | enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL; | |
0b226322 | 1957 | bool fec_enable = false; |
0b226322 | 1958 | |
7211b605 | 1959 | dp_decide_training_settings( |
0b226322 DG |
1960 | link, |
1961 | link_settings, | |
1962 | lt_overrides, | |
1963 | <_settings); | |
1964 | ||
1965 | /* Setup MST Mode */ | |
1966 | if (lt_overrides->mst_enable) | |
1967 | set_dp_mst_mode(link, *lt_overrides->mst_enable); | |
1968 | ||
1969 | /* Disable link */ | |
1970 | dp_disable_link_phy(link, link->connector_signal); | |
1971 | ||
1972 | /* Enable link */ | |
1973 | dp_cs_id = get_clock_source_id(link); | |
1974 | dp_enable_link_phy(link, link->connector_signal, | |
1975 | dp_cs_id, link_settings); | |
1976 | ||
0b226322 DG |
1977 | /* Set FEC enable */ |
1978 | fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable; | |
1979 | dp_set_fec_ready(link, fec_enable); | |
0b226322 DG |
1980 | |
1981 | if (lt_overrides->alternate_scrambler_reset) { | |
1982 | if (*lt_overrides->alternate_scrambler_reset) | |
1983 | panel_mode = DP_PANEL_MODE_EDP; | |
1984 | else | |
1985 | panel_mode = DP_PANEL_MODE_DEFAULT; | |
1986 | } else | |
1987 | panel_mode = dp_get_panel_mode(link); | |
1988 | ||
1989 | dp_set_panel_mode(link, panel_mode); | |
1990 | ||
1991 | /* Attempt to train with given link training settings */ | |
82054678 ML |
1992 | if (link->ctx->dc->work_arounds.lt_early_cr_pattern) |
1993 | start_clock_recovery_pattern_early(link, <_settings, DPRX); | |
834a9a9f ML |
1994 | |
1995 | /* Set link rate, lane count and spread. */ | |
1996 | dpcd_set_link_settings(link, <_settings); | |
0b226322 DG |
1997 | |
1998 | /* 2. perform link training (set link training done | |
1999 | * to false is done as well) | |
2000 | */ | |
64c12b73 | 2001 | lt_status = perform_clock_recovery_sequence(link, <_settings, DPRX); |
0b226322 DG |
2002 | if (lt_status == LINK_TRAINING_SUCCESS) { |
2003 | lt_status = perform_channel_equalization_sequence(link, | |
64c12b73 | 2004 | <_settings, |
2005 | DPRX); | |
0b226322 DG |
2006 | } |
2007 | ||
2008 | /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/ | |
2009 | /* 4. print status message*/ | |
2010 | print_status_message(link, <_settings, lt_status); | |
2011 | ||
2012 | return lt_status; | |
2013 | } | |
2014 | ||
2015 | bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down) | |
2016 | { | |
2017 | /* If input parameter is set, shut down phy. | |
2018 | * Still shouldn't turn off dp_receiver (DPCD:600h) | |
2019 | */ | |
2020 | if (link_down == true) { | |
2021 | dp_disable_link_phy(link, link->connector_signal); | |
0b226322 | 2022 | dp_set_fec_ready(link, false); |
0b226322 DG |
2023 | } |
2024 | ||
2025 | link->sync_lt_in_progress = false; | |
2026 | return true; | |
2027 | } | |
2028 | ||
98025a62 NC |
2029 | bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap) |
2030 | { | |
2031 | if (!max_link_enc_cap) { | |
2032 | DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__); | |
2033 | return false; | |
2034 | } | |
2035 | ||
2036 | if (link->link_enc->funcs->get_max_link_cap) { | |
2037 | link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap); | |
2038 | return true; | |
2039 | } | |
2040 | ||
2041 | DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__); | |
2042 | max_link_enc_cap->lane_count = 1; | |
2043 | max_link_enc_cap->link_rate = 6; | |
2044 | return false; | |
2045 | } | |
2046 | ||
d0778ebf | 2047 | static struct dc_link_settings get_max_link_cap(struct dc_link *link) |
4562236b | 2048 | { |
8ccf0e20 | 2049 | struct dc_link_settings max_link_cap = {0}; |
4562236b | 2050 | |
8ccf0e20 WL |
2051 | /* get max link encoder capability */ |
2052 | link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap); | |
f537d474 | 2053 | |
4562236b | 2054 | /* Lower link settings based on sink's link cap */ |
d0778ebf | 2055 | if (link->reported_link_cap.lane_count < max_link_cap.lane_count) |
4562236b | 2056 | max_link_cap.lane_count = |
d0778ebf HW |
2057 | link->reported_link_cap.lane_count; |
2058 | if (link->reported_link_cap.link_rate < max_link_cap.link_rate) | |
4562236b | 2059 | max_link_cap.link_rate = |
d0778ebf HW |
2060 | link->reported_link_cap.link_rate; |
2061 | if (link->reported_link_cap.link_spread < | |
4562236b HW |
2062 | max_link_cap.link_spread) |
2063 | max_link_cap.link_spread = | |
d0778ebf | 2064 | link->reported_link_cap.link_spread; |
bad7ab0b | 2065 | /* |
2066 | * account for lttpr repeaters cap | |
2067 | * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3). | |
2068 | */ | |
3128b285 | 2069 | if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) { |
bad7ab0b | 2070 | if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count) |
2071 | max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count; | |
2072 | ||
2073 | if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate) | |
2074 | max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate; | |
460adc6b | 2075 | |
2076 | DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n", | |
2077 | __func__, | |
2078 | max_link_cap.lane_count, | |
2079 | max_link_cap.link_rate); | |
bad7ab0b | 2080 | } |
4562236b HW |
2081 | return max_link_cap; |
2082 | } | |
2083 | ||
3083a984 | 2084 | enum dc_status read_hpd_rx_irq_data( |
1ae62f31 WL |
2085 | struct dc_link *link, |
2086 | union hpd_irq_data *irq_data) | |
2087 | { | |
2088 | static enum dc_status retval; | |
2089 | ||
2090 | /* The HW reads 16 bytes from 200h on HPD, | |
2091 | * but if we get an AUX_DEFER, the HW cannot retry | |
2092 | * and this causes the CTS tests 4.3.2.1 - 3.2.4 to | |
2093 | * fail, so we now explicitly read 6 bytes which is | |
2094 | * the req from the above mentioned test cases. | |
2095 | * | |
2096 | * For DP 1.4 we need to read those from 2002h range. | |
2097 | */ | |
2098 | if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14) | |
2099 | retval = core_link_read_dpcd( | |
2100 | link, | |
2101 | DP_SINK_COUNT, | |
2102 | irq_data->raw, | |
2103 | sizeof(union hpd_irq_data)); | |
2104 | else { | |
2105 | /* Read 14 bytes in a single read and then copy only the required fields. | |
2106 | * This is more efficient than doing it in two separate AUX reads. */ | |
2107 | ||
2108 | uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1]; | |
2109 | ||
2110 | retval = core_link_read_dpcd( | |
2111 | link, | |
2112 | DP_SINK_COUNT_ESI, | |
2113 | tmp, | |
2114 | sizeof(tmp)); | |
2115 | ||
2116 | if (retval != DC_OK) | |
2117 | return retval; | |
2118 | ||
2119 | irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI]; | |
2120 | irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI]; | |
2121 | irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI]; | |
2122 | irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI]; | |
2123 | irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI]; | |
2124 | irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI]; | |
2125 | } | |
2126 | ||
2127 | return retval; | |
2128 | } | |
2129 | ||
d2aa1356 | 2130 | bool hpd_rx_irq_check_link_loss_status( |
1ae62f31 WL |
2131 | struct dc_link *link, |
2132 | union hpd_irq_data *hpd_irq_dpcd_data) | |
2133 | { | |
2134 | uint8_t irq_reg_rx_power_state = 0; | |
2135 | enum dc_status dpcd_result = DC_ERROR_UNEXPECTED; | |
2136 | union lane_status lane_status; | |
2137 | uint32_t lane; | |
2138 | bool sink_status_changed; | |
2139 | bool return_code; | |
2140 | ||
2141 | sink_status_changed = false; | |
2142 | return_code = false; | |
2143 | ||
2144 | if (link->cur_link_settings.lane_count == 0) | |
2145 | return return_code; | |
2146 | ||
2147 | /*1. Check that Link Status changed, before re-training.*/ | |
2148 | ||
2149 | /*parse lane status*/ | |
2150 | for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { | |
2151 | /* check status of lanes 0,1 | |
2152 | * changed DpcdAddress_Lane01Status (0x202) | |
2153 | */ | |
2154 | lane_status.raw = get_nibble_at_index( | |
2155 | &hpd_irq_dpcd_data->bytes.lane01_status.raw, | |
2156 | lane); | |
2157 | ||
2158 | if (!lane_status.bits.CHANNEL_EQ_DONE_0 || | |
2159 | !lane_status.bits.CR_DONE_0 || | |
2160 | !lane_status.bits.SYMBOL_LOCKED_0) { | |
2161 | /* if one of the channel equalization, clock | |
2162 | * recovery or symbol lock is dropped | |
2163 | * consider it as (link has been | |
2164 | * dropped) dp sink status has changed | |
2165 | */ | |
2166 | sink_status_changed = true; | |
2167 | break; | |
2168 | } | |
2169 | } | |
2170 | ||
2171 | /* Check interlane align.*/ | |
2172 | if (sink_status_changed || | |
2173 | !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) { | |
2174 | ||
2175 | DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__); | |
2176 | ||
2177 | return_code = true; | |
2178 | ||
2179 | /*2. Check that we can handle interrupt: Not in FS DOS, | |
2180 | * Not in "Display Timeout" state, Link is trained. | |
2181 | */ | |
2182 | dpcd_result = core_link_read_dpcd(link, | |
2183 | DP_SET_POWER, | |
2184 | &irq_reg_rx_power_state, | |
2185 | sizeof(irq_reg_rx_power_state)); | |
2186 | ||
2187 | if (dpcd_result != DC_OK) { | |
2188 | DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n", | |
2189 | __func__); | |
2190 | } else { | |
2191 | if (irq_reg_rx_power_state != DP_SET_POWER_D0) | |
2192 | return_code = false; | |
2193 | } | |
2194 | } | |
2195 | ||
2196 | return return_code; | |
2197 | } | |
2198 | ||
aafded88 | 2199 | bool dp_verify_link_cap( |
d0778ebf | 2200 | struct dc_link *link, |
824474ba BL |
2201 | struct dc_link_settings *known_limit_link_setting, |
2202 | int *fail_count) | |
4562236b HW |
2203 | { |
2204 | struct dc_link_settings max_link_cap = {0}; | |
820e3935 DW |
2205 | struct dc_link_settings cur_link_setting = {0}; |
2206 | struct dc_link_settings *cur = &cur_link_setting; | |
2207 | struct dc_link_settings initial_link_settings = {0}; | |
4562236b HW |
2208 | bool success; |
2209 | bool skip_link_training; | |
4562236b | 2210 | bool skip_video_pattern; |
4562236b | 2211 | enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL; |
820e3935 | 2212 | enum link_training_result status; |
1ae62f31 | 2213 | union hpd_irq_data irq_data; |
4562236b | 2214 | |
aafded88 TC |
2215 | if (link->dc->debug.skip_detection_link_training) { |
2216 | link->verified_link_cap = *known_limit_link_setting; | |
2217 | return true; | |
2218 | } | |
2219 | ||
1ae62f31 | 2220 | memset(&irq_data, 0, sizeof(irq_data)); |
4562236b HW |
2221 | success = false; |
2222 | skip_link_training = false; | |
2223 | ||
2224 | max_link_cap = get_max_link_cap(link); | |
2225 | ||
bad7ab0b | 2226 | /* Grant extended timeout request */ |
3128b285 | 2227 | if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) { |
bad7ab0b | 2228 | uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80; |
2229 | ||
2230 | core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant)); | |
2231 | } | |
2232 | ||
4562236b HW |
2233 | /* TODO implement override and monitor patch later */ |
2234 | ||
2235 | /* try to train the link from high to low to | |
2236 | * find the physical link capability | |
2237 | */ | |
2238 | /* disable PHY done possible by BIOS, will be done by driver itself */ | |
d0778ebf | 2239 | dp_disable_link_phy(link, link->connector_signal); |
4562236b | 2240 | |
b3282738 GS |
2241 | dp_cs_id = get_clock_source_id(link); |
2242 | ||
2243 | /* link training starts with the maximum common settings | |
2244 | * supported by both sink and ASIC. | |
2245 | */ | |
2246 | initial_link_settings = get_common_supported_link_settings( | |
2247 | *known_limit_link_setting, | |
2248 | max_link_cap); | |
2249 | cur_link_setting = initial_link_settings; | |
2250 | ||
ee765924 GS |
2251 | /* Temporary Renoir-specific workaround for SWDEV-215184; |
2252 | * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle, | |
2253 | * so add extra cycle of enabling and disabling the PHY before first link training. | |
2254 | */ | |
2255 | if (link->link_enc->features.flags.bits.DP_IS_USB_C && | |
2256 | link->dc->debug.usbc_combo_phy_reset_wa) { | |
2257 | dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur); | |
2258 | dp_disable_link_phy(link, link->connector_signal); | |
2259 | } | |
2260 | ||
820e3935 | 2261 | do { |
4562236b | 2262 | skip_video_pattern = true; |
820e3935 | 2263 | |
4562236b HW |
2264 | if (cur->link_rate == LINK_RATE_LOW) |
2265 | skip_video_pattern = false; | |
2266 | ||
2267 | dp_enable_link_phy( | |
2268 | link, | |
d0778ebf | 2269 | link->connector_signal, |
4562236b HW |
2270 | dp_cs_id, |
2271 | cur); | |
2272 | ||
94405cf6 | 2273 | |
4562236b HW |
2274 | if (skip_link_training) |
2275 | success = true; | |
2276 | else { | |
820e3935 | 2277 | status = dc_link_dp_perform_link_training( |
d0778ebf | 2278 | link, |
4562236b HW |
2279 | cur, |
2280 | skip_video_pattern); | |
820e3935 DW |
2281 | if (status == LINK_TRAINING_SUCCESS) |
2282 | success = true; | |
824474ba BL |
2283 | else |
2284 | (*fail_count)++; | |
4562236b HW |
2285 | } |
2286 | ||
1ae62f31 | 2287 | if (success) { |
d0778ebf | 2288 | link->verified_link_cap = *cur; |
1ae62f31 WL |
2289 | udelay(1000); |
2290 | if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK) | |
2291 | if (hpd_rx_irq_check_link_loss_status( | |
2292 | link, | |
2293 | &irq_data)) | |
2294 | (*fail_count)++; | |
2295 | } | |
4562236b HW |
2296 | /* always disable the link before trying another |
2297 | * setting or before returning we'll enable it later | |
2298 | * based on the actual mode we're driving | |
2299 | */ | |
d0778ebf | 2300 | dp_disable_link_phy(link, link->connector_signal); |
820e3935 DW |
2301 | } while (!success && decide_fallback_link_setting( |
2302 | initial_link_settings, cur, status)); | |
4562236b HW |
2303 | |
2304 | /* Link Training failed for all Link Settings | |
2305 | * (Lane Count is still unknown) | |
2306 | */ | |
2307 | if (!success) { | |
2308 | /* If all LT fails for all settings, | |
2309 | * set verified = failed safe (1 lane low) | |
2310 | */ | |
d0778ebf HW |
2311 | link->verified_link_cap.lane_count = LANE_COUNT_ONE; |
2312 | link->verified_link_cap.link_rate = LINK_RATE_LOW; | |
4562236b | 2313 | |
d0778ebf | 2314 | link->verified_link_cap.link_spread = |
4562236b HW |
2315 | LINK_SPREAD_DISABLED; |
2316 | } | |
2317 | ||
4562236b HW |
2318 | |
2319 | return success; | |
2320 | } | |
2321 | ||
e7f2c80c WL |
2322 | bool dp_verify_link_cap_with_retries( |
2323 | struct dc_link *link, | |
2324 | struct dc_link_settings *known_limit_link_setting, | |
2325 | int attempts) | |
2326 | { | |
2327 | uint8_t i = 0; | |
2328 | bool success = false; | |
2329 | ||
2330 | for (i = 0; i < attempts; i++) { | |
2331 | int fail_count = 0; | |
82db2e3c | 2332 | enum dc_connection_type type = dc_connection_none; |
e7f2c80c WL |
2333 | |
2334 | memset(&link->verified_link_cap, 0, | |
2335 | sizeof(struct dc_link_settings)); | |
82db2e3c SK |
2336 | if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) { |
2337 | link->verified_link_cap.lane_count = LANE_COUNT_ONE; | |
2338 | link->verified_link_cap.link_rate = LINK_RATE_LOW; | |
2339 | link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED; | |
e7f2c80c WL |
2340 | break; |
2341 | } else if (dp_verify_link_cap(link, | |
2342 | &link->reported_link_cap, | |
2343 | &fail_count) && fail_count == 0) { | |
2344 | success = true; | |
2345 | break; | |
2346 | } | |
2347 | msleep(10); | |
2348 | } | |
2349 | return success; | |
2350 | } | |
2351 | ||
f537d474 LH |
2352 | bool dp_verify_mst_link_cap( |
2353 | struct dc_link *link) | |
2354 | { | |
2355 | struct dc_link_settings max_link_cap = {0}; | |
2356 | ||
2357 | max_link_cap = get_max_link_cap(link); | |
2358 | link->verified_link_cap = get_common_supported_link_settings( | |
2359 | link->reported_link_cap, | |
2360 | max_link_cap); | |
2361 | ||
2362 | return true; | |
2363 | } | |
2364 | ||
9a6a8075 | 2365 | static struct dc_link_settings get_common_supported_link_settings( |
820e3935 DW |
2366 | struct dc_link_settings link_setting_a, |
2367 | struct dc_link_settings link_setting_b) | |
2368 | { | |
2369 | struct dc_link_settings link_settings = {0}; | |
2370 | ||
2371 | link_settings.lane_count = | |
2372 | (link_setting_a.lane_count <= | |
2373 | link_setting_b.lane_count) ? | |
2374 | link_setting_a.lane_count : | |
2375 | link_setting_b.lane_count; | |
2376 | link_settings.link_rate = | |
2377 | (link_setting_a.link_rate <= | |
2378 | link_setting_b.link_rate) ? | |
2379 | link_setting_a.link_rate : | |
2380 | link_setting_b.link_rate; | |
2381 | link_settings.link_spread = LINK_SPREAD_DISABLED; | |
2382 | ||
2383 | /* in DP compliance test, DPR-120 may have | |
2384 | * a random value in its MAX_LINK_BW dpcd field. | |
2385 | * We map it to the maximum supported link rate that | |
2386 | * is smaller than MAX_LINK_BW in this case. | |
2387 | */ | |
2388 | if (link_settings.link_rate > LINK_RATE_HIGH3) { | |
2389 | link_settings.link_rate = LINK_RATE_HIGH3; | |
2390 | } else if (link_settings.link_rate < LINK_RATE_HIGH3 | |
2391 | && link_settings.link_rate > LINK_RATE_HIGH2) { | |
2392 | link_settings.link_rate = LINK_RATE_HIGH2; | |
2393 | } else if (link_settings.link_rate < LINK_RATE_HIGH2 | |
2394 | && link_settings.link_rate > LINK_RATE_HIGH) { | |
2395 | link_settings.link_rate = LINK_RATE_HIGH; | |
2396 | } else if (link_settings.link_rate < LINK_RATE_HIGH | |
2397 | && link_settings.link_rate > LINK_RATE_LOW) { | |
2398 | link_settings.link_rate = LINK_RATE_LOW; | |
2399 | } else if (link_settings.link_rate < LINK_RATE_LOW) { | |
2400 | link_settings.link_rate = LINK_RATE_UNKNOWN; | |
2401 | } | |
2402 | ||
2403 | return link_settings; | |
2404 | } | |
2405 | ||
450619d3 | 2406 | static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) |
820e3935 DW |
2407 | { |
2408 | return lane_count <= LANE_COUNT_ONE; | |
2409 | } | |
2410 | ||
450619d3 | 2411 | static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate) |
820e3935 DW |
2412 | { |
2413 | return link_rate <= LINK_RATE_LOW; | |
2414 | } | |
2415 | ||
44858055 | 2416 | static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) |
820e3935 DW |
2417 | { |
2418 | switch (lane_count) { | |
2419 | case LANE_COUNT_FOUR: | |
2420 | return LANE_COUNT_TWO; | |
2421 | case LANE_COUNT_TWO: | |
2422 | return LANE_COUNT_ONE; | |
2423 | case LANE_COUNT_ONE: | |
2424 | return LANE_COUNT_UNKNOWN; | |
2425 | default: | |
2426 | return LANE_COUNT_UNKNOWN; | |
2427 | } | |
2428 | } | |
2429 | ||
04e21292 | 2430 | static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate) |
820e3935 DW |
2431 | { |
2432 | switch (link_rate) { | |
2433 | case LINK_RATE_HIGH3: | |
2434 | return LINK_RATE_HIGH2; | |
2435 | case LINK_RATE_HIGH2: | |
2436 | return LINK_RATE_HIGH; | |
2437 | case LINK_RATE_HIGH: | |
2438 | return LINK_RATE_LOW; | |
2439 | case LINK_RATE_LOW: | |
2440 | return LINK_RATE_UNKNOWN; | |
2441 | default: | |
2442 | return LINK_RATE_UNKNOWN; | |
2443 | } | |
2444 | } | |
2445 | ||
04e21292 | 2446 | static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) |
8c4abe0b DW |
2447 | { |
2448 | switch (lane_count) { | |
2449 | case LANE_COUNT_ONE: | |
2450 | return LANE_COUNT_TWO; | |
2451 | case LANE_COUNT_TWO: | |
2452 | return LANE_COUNT_FOUR; | |
2453 | default: | |
2454 | return LANE_COUNT_UNKNOWN; | |
2455 | } | |
2456 | } | |
2457 | ||
04e21292 | 2458 | static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate) |
8c4abe0b DW |
2459 | { |
2460 | switch (link_rate) { | |
2461 | case LINK_RATE_LOW: | |
2462 | return LINK_RATE_HIGH; | |
2463 | case LINK_RATE_HIGH: | |
2464 | return LINK_RATE_HIGH2; | |
2465 | case LINK_RATE_HIGH2: | |
2466 | return LINK_RATE_HIGH3; | |
2467 | default: | |
2468 | return LINK_RATE_UNKNOWN; | |
2469 | } | |
2470 | } | |
2471 | ||
820e3935 DW |
2472 | /* |
2473 | * function: set link rate and lane count fallback based | |
2474 | * on current link setting and last link training result | |
2475 | * return value: | |
2476 | * true - link setting could be set | |
2477 | * false - has reached minimum setting | |
2478 | * and no further fallback could be done | |
2479 | */ | |
04e21292 | 2480 | static bool decide_fallback_link_setting( |
820e3935 DW |
2481 | struct dc_link_settings initial_link_settings, |
2482 | struct dc_link_settings *current_link_setting, | |
2483 | enum link_training_result training_result) | |
2484 | { | |
2485 | if (!current_link_setting) | |
2486 | return false; | |
2487 | ||
2488 | switch (training_result) { | |
94405cf6 WL |
2489 | case LINK_TRAINING_CR_FAIL_LANE0: |
2490 | case LINK_TRAINING_CR_FAIL_LANE1: | |
2491 | case LINK_TRAINING_CR_FAIL_LANE23: | |
2492 | case LINK_TRAINING_LQA_FAIL: | |
820e3935 DW |
2493 | { |
2494 | if (!reached_minimum_link_rate | |
2495 | (current_link_setting->link_rate)) { | |
2496 | current_link_setting->link_rate = | |
2497 | reduce_link_rate( | |
2498 | current_link_setting->link_rate); | |
2499 | } else if (!reached_minimum_lane_count | |
2500 | (current_link_setting->lane_count)) { | |
2501 | current_link_setting->link_rate = | |
2502 | initial_link_settings.link_rate; | |
94405cf6 WL |
2503 | if (training_result == LINK_TRAINING_CR_FAIL_LANE0) |
2504 | return false; | |
2505 | else if (training_result == LINK_TRAINING_CR_FAIL_LANE1) | |
2506 | current_link_setting->lane_count = | |
2507 | LANE_COUNT_ONE; | |
2508 | else if (training_result == | |
2509 | LINK_TRAINING_CR_FAIL_LANE23) | |
2510 | current_link_setting->lane_count = | |
2511 | LANE_COUNT_TWO; | |
2512 | else | |
2513 | current_link_setting->lane_count = | |
2514 | reduce_lane_count( | |
820e3935 DW |
2515 | current_link_setting->lane_count); |
2516 | } else { | |
2517 | return false; | |
2518 | } | |
2519 | break; | |
2520 | } | |
2521 | case LINK_TRAINING_EQ_FAIL_EQ: | |
2522 | { | |
2523 | if (!reached_minimum_lane_count | |
2524 | (current_link_setting->lane_count)) { | |
2525 | current_link_setting->lane_count = | |
2526 | reduce_lane_count( | |
2527 | current_link_setting->lane_count); | |
2528 | } else if (!reached_minimum_link_rate | |
2529 | (current_link_setting->link_rate)) { | |
820e3935 DW |
2530 | current_link_setting->link_rate = |
2531 | reduce_link_rate( | |
2532 | current_link_setting->link_rate); | |
2533 | } else { | |
2534 | return false; | |
2535 | } | |
2536 | break; | |
2537 | } | |
2538 | case LINK_TRAINING_EQ_FAIL_CR: | |
2539 | { | |
2540 | if (!reached_minimum_link_rate | |
2541 | (current_link_setting->link_rate)) { | |
2542 | current_link_setting->link_rate = | |
2543 | reduce_link_rate( | |
2544 | current_link_setting->link_rate); | |
2545 | } else { | |
2546 | return false; | |
2547 | } | |
2548 | break; | |
2549 | } | |
2550 | default: | |
2551 | return false; | |
2552 | } | |
2553 | return true; | |
2554 | } | |
2555 | ||
4562236b | 2556 | bool dp_validate_mode_timing( |
d0778ebf | 2557 | struct dc_link *link, |
4562236b HW |
2558 | const struct dc_crtc_timing *timing) |
2559 | { | |
2560 | uint32_t req_bw; | |
2561 | uint32_t max_bw; | |
2562 | ||
2563 | const struct dc_link_settings *link_setting; | |
2564 | ||
05e62b6b GS |
2565 | /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */ |
2566 | if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && | |
2567 | !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED && | |
2568 | dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL) | |
2569 | return false; | |
2570 | ||
4562236b | 2571 | /*always DP fail safe mode*/ |
380604e2 | 2572 | if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 && |
9a6a8075 HW |
2573 | timing->h_addressable == (uint32_t) 640 && |
2574 | timing->v_addressable == (uint32_t) 480) | |
4562236b HW |
2575 | return true; |
2576 | ||
5ac4619b | 2577 | link_setting = dc_link_get_link_cap(link); |
4562236b HW |
2578 | |
2579 | /* TODO: DYNAMIC_VALIDATION needs to be implemented */ | |
2580 | /*if (flags.DYNAMIC_VALIDATION == 1 && | |
d0778ebf HW |
2581 | link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) |
2582 | link_setting = &link->verified_link_cap; | |
4562236b HW |
2583 | */ |
2584 | ||
e49f6936 | 2585 | req_bw = dc_bandwidth_in_kbps_from_timing(timing); |
332c1191 | 2586 | max_bw = dc_link_bandwidth_kbps(link, link_setting); |
4562236b HW |
2587 | |
2588 | if (req_bw <= max_bw) { | |
2589 | /* remember the biggest mode here, during | |
2590 | * initial link training (to get | |
2591 | * verified_link_cap), LS sends event about | |
2592 | * cannot train at reported cap to upper | |
2593 | * layer and upper layer will re-enumerate modes. | |
2594 | * this is not necessary if the lower | |
2595 | * verified_link_cap is enough to drive | |
2596 | * all the modes */ | |
2597 | ||
2598 | /* TODO: DYNAMIC_VALIDATION needs to be implemented */ | |
2599 | /* if (flags.DYNAMIC_VALIDATION == 1) | |
2600 | dpsst->max_req_bw_for_verified_linkcap = dal_max( | |
2601 | dpsst->max_req_bw_for_verified_linkcap, req_bw); */ | |
2602 | return true; | |
2603 | } else | |
2604 | return false; | |
2605 | } | |
2606 | ||
8628d02f | 2607 | static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw) |
4562236b | 2608 | { |
8c4abe0b | 2609 | struct dc_link_settings initial_link_setting = { |
8628d02f | 2610 | LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0}; |
8c4abe0b DW |
2611 | struct dc_link_settings current_link_setting = |
2612 | initial_link_setting; | |
4562236b | 2613 | uint32_t link_bw; |
4562236b | 2614 | |
69d5c7f3 BG |
2615 | if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap)) |
2616 | return false; | |
2617 | ||
8628d02f JP |
2618 | /* search for the minimum link setting that: |
2619 | * 1. is supported according to the link training result | |
2620 | * 2. could support the b/w requested by the timing | |
4562236b | 2621 | */ |
8628d02f JP |
2622 | while (current_link_setting.link_rate <= |
2623 | link->verified_link_cap.link_rate) { | |
332c1191 NC |
2624 | link_bw = dc_link_bandwidth_kbps( |
2625 | link, | |
8628d02f JP |
2626 | ¤t_link_setting); |
2627 | if (req_bw <= link_bw) { | |
2628 | *link_setting = current_link_setting; | |
2629 | return true; | |
2630 | } | |
4562236b | 2631 | |
8628d02f JP |
2632 | if (current_link_setting.lane_count < |
2633 | link->verified_link_cap.lane_count) { | |
2634 | current_link_setting.lane_count = | |
2635 | increase_lane_count( | |
2636 | current_link_setting.lane_count); | |
2637 | } else { | |
2638 | current_link_setting.link_rate = | |
2639 | increase_link_rate( | |
2640 | current_link_setting.link_rate); | |
2641 | current_link_setting.lane_count = | |
2642 | initial_link_setting.lane_count; | |
2643 | } | |
3f1f74f4 JZ |
2644 | } |
2645 | ||
8628d02f JP |
2646 | return false; |
2647 | } | |
2648 | ||
8efd0f5a | 2649 | bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw) |
8628d02f JP |
2650 | { |
2651 | struct dc_link_settings initial_link_setting; | |
2652 | struct dc_link_settings current_link_setting; | |
2653 | uint32_t link_bw; | |
2654 | ||
67c268a5 ZL |
2655 | /* |
2656 | * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. | |
2657 | * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" | |
2658 | */ | |
2659 | if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 || | |
53c81fc7 | 2660 | link->dpcd_caps.edp_supported_link_rates_count == 0) { |
4d2f22d1 | 2661 | *link_setting = link->verified_link_cap; |
8628d02f | 2662 | return true; |
4d2f22d1 HH |
2663 | } |
2664 | ||
8628d02f JP |
2665 | memset(&initial_link_setting, 0, sizeof(initial_link_setting)); |
2666 | initial_link_setting.lane_count = LANE_COUNT_ONE; | |
2667 | initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0]; | |
2668 | initial_link_setting.link_spread = LINK_SPREAD_DISABLED; | |
2669 | initial_link_setting.use_link_rate_set = true; | |
2670 | initial_link_setting.link_rate_set = 0; | |
2671 | current_link_setting = initial_link_setting; | |
2672 | ||
5667ff5c DA |
2673 | /* search for the minimum link setting that: |
2674 | * 1. is supported according to the link training result | |
2675 | * 2. could support the b/w requested by the timing | |
2676 | */ | |
8c4abe0b | 2677 | while (current_link_setting.link_rate <= |
4654a2f7 | 2678 | link->verified_link_cap.link_rate) { |
332c1191 NC |
2679 | link_bw = dc_link_bandwidth_kbps( |
2680 | link, | |
8c4abe0b DW |
2681 | ¤t_link_setting); |
2682 | if (req_bw <= link_bw) { | |
2683 | *link_setting = current_link_setting; | |
8628d02f | 2684 | return true; |
4562236b | 2685 | } |
4562236b | 2686 | |
8c4abe0b | 2687 | if (current_link_setting.lane_count < |
4654a2f7 | 2688 | link->verified_link_cap.lane_count) { |
8c4abe0b DW |
2689 | current_link_setting.lane_count = |
2690 | increase_lane_count( | |
2691 | current_link_setting.lane_count); | |
2692 | } else { | |
8628d02f JP |
2693 | if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { |
2694 | current_link_setting.link_rate_set++; | |
2695 | current_link_setting.link_rate = | |
2696 | link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; | |
2697 | current_link_setting.lane_count = | |
2698 | initial_link_setting.lane_count; | |
2699 | } else | |
2700 | break; | |
4562236b HW |
2701 | } |
2702 | } | |
8628d02f JP |
2703 | return false; |
2704 | } | |
2705 | ||
c08321cb WL |
2706 | static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting) |
2707 | { | |
2708 | *link_setting = link->verified_link_cap; | |
2709 | return true; | |
2710 | } | |
2711 | ||
8628d02f JP |
2712 | void decide_link_settings(struct dc_stream_state *stream, |
2713 | struct dc_link_settings *link_setting) | |
2714 | { | |
2715 | struct dc_link *link; | |
2716 | uint32_t req_bw; | |
2717 | ||
e49f6936 | 2718 | req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing); |
8628d02f JP |
2719 | |
2720 | link = stream->link; | |
2721 | ||
2722 | /* if preferred is specified through AMDDP, use it, if it's enough | |
2723 | * to drive the mode | |
2724 | */ | |
2725 | if (link->preferred_link_setting.lane_count != | |
2726 | LANE_COUNT_UNKNOWN && | |
2727 | link->preferred_link_setting.link_rate != | |
2728 | LINK_RATE_UNKNOWN) { | |
2729 | *link_setting = link->preferred_link_setting; | |
2730 | return; | |
2731 | } | |
2732 | ||
2733 | /* MST doesn't perform link training for now | |
2734 | * TODO: add MST specific link training routine | |
2735 | */ | |
2736 | if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { | |
c08321cb WL |
2737 | if (decide_mst_link_settings(link, link_setting)) |
2738 | return; | |
2739 | } else if (link->connector_signal == SIGNAL_TYPE_EDP) { | |
8628d02f JP |
2740 | if (decide_edp_link_settings(link, link_setting, req_bw)) |
2741 | return; | |
2742 | } else if (decide_dp_link_settings(link, link_setting, req_bw)) | |
2743 | return; | |
4562236b HW |
2744 | |
2745 | BREAK_TO_DEBUGGER(); | |
d0778ebf | 2746 | ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN); |
4562236b | 2747 | |
d0778ebf | 2748 | *link_setting = link->verified_link_cap; |
4562236b HW |
2749 | } |
2750 | ||
2751 | /*************************Short Pulse IRQ***************************/ | |
d0778ebf | 2752 | static bool allow_hpd_rx_irq(const struct dc_link *link) |
4562236b HW |
2753 | { |
2754 | /* | |
2755 | * Don't handle RX IRQ unless one of following is met: | |
2756 | * 1) The link is established (cur_link_settings != unknown) | |
36c9137b | 2757 | * 2) We know we're dealing with a branch device, SST or MST |
4562236b HW |
2758 | */ |
2759 | ||
d0778ebf | 2760 | if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || |
36c9137b | 2761 | is_dp_branch_device(link)) |
4562236b HW |
2762 | return true; |
2763 | ||
2764 | return false; | |
2765 | } | |
2766 | ||
ab4a4072 | 2767 | static bool handle_hpd_irq_psr_sink(struct dc_link *link) |
4562236b HW |
2768 | { |
2769 | union dpcd_psr_configuration psr_configuration; | |
2770 | ||
d1ebfdd8 | 2771 | if (!link->psr_settings.psr_feature_enabled) |
4562236b HW |
2772 | return false; |
2773 | ||
7c7f5b15 AG |
2774 | dm_helpers_dp_read_dpcd( |
2775 | link->ctx, | |
d0778ebf | 2776 | link, |
7c7f5b15 AG |
2777 | 368,/*DpcdAddress_PSR_Enable_Cfg*/ |
2778 | &psr_configuration.raw, | |
2779 | sizeof(psr_configuration.raw)); | |
2780 | ||
4562236b HW |
2781 | |
2782 | if (psr_configuration.bits.ENABLE) { | |
2783 | unsigned char dpcdbuf[3] = {0}; | |
2784 | union psr_error_status psr_error_status; | |
2785 | union psr_sink_psr_status psr_sink_psr_status; | |
2786 | ||
7c7f5b15 AG |
2787 | dm_helpers_dp_read_dpcd( |
2788 | link->ctx, | |
d0778ebf | 2789 | link, |
7c7f5b15 AG |
2790 | 0x2006, /*DpcdAddress_PSR_Error_Status*/ |
2791 | (unsigned char *) dpcdbuf, | |
2792 | sizeof(dpcdbuf)); | |
4562236b HW |
2793 | |
2794 | /*DPCD 2006h ERROR STATUS*/ | |
2795 | psr_error_status.raw = dpcdbuf[0]; | |
2796 | /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/ | |
2797 | psr_sink_psr_status.raw = dpcdbuf[2]; | |
2798 | ||
2799 | if (psr_error_status.bits.LINK_CRC_ERROR || | |
63c954a1 WW |
2800 | psr_error_status.bits.RFB_STORAGE_ERROR || |
2801 | psr_error_status.bits.VSC_SDP_ERROR) { | |
4562236b | 2802 | /* Acknowledge and clear error bits */ |
7c7f5b15 AG |
2803 | dm_helpers_dp_write_dpcd( |
2804 | link->ctx, | |
d0778ebf | 2805 | link, |
7c7f5b15 | 2806 | 8198,/*DpcdAddress_PSR_Error_Status*/ |
4562236b HW |
2807 | &psr_error_status.raw, |
2808 | sizeof(psr_error_status.raw)); | |
2809 | ||
2810 | /* PSR error, disable and re-enable PSR */ | |
1d496907 KK |
2811 | dc_link_set_psr_allow_active(link, false, true, false); |
2812 | dc_link_set_psr_allow_active(link, true, true, false); | |
4562236b HW |
2813 | |
2814 | return true; | |
2815 | } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS == | |
2816 | PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){ | |
2817 | /* No error is detect, PSR is active. | |
2818 | * We should return with IRQ_HPD handled without | |
2819 | * checking for loss of sync since PSR would have | |
2820 | * powered down main link. | |
2821 | */ | |
2822 | return true; | |
2823 | } | |
2824 | } | |
2825 | return false; | |
2826 | } | |
2827 | ||
d0778ebf | 2828 | static void dp_test_send_link_training(struct dc_link *link) |
4562236b | 2829 | { |
73c72602 | 2830 | struct dc_link_settings link_settings = {0}; |
4562236b HW |
2831 | |
2832 | core_link_read_dpcd( | |
2833 | link, | |
3a340294 | 2834 | DP_TEST_LANE_COUNT, |
4562236b HW |
2835 | (unsigned char *)(&link_settings.lane_count), |
2836 | 1); | |
2837 | core_link_read_dpcd( | |
2838 | link, | |
3a340294 | 2839 | DP_TEST_LINK_RATE, |
4562236b HW |
2840 | (unsigned char *)(&link_settings.link_rate), |
2841 | 1); | |
2842 | ||
2843 | /* Set preferred link settings */ | |
d0778ebf HW |
2844 | link->verified_link_cap.lane_count = link_settings.lane_count; |
2845 | link->verified_link_cap.link_rate = link_settings.link_rate; | |
4562236b | 2846 | |
73c72602 | 2847 | dp_retrain_link_dp_test(link, &link_settings, false); |
4562236b HW |
2848 | } |
2849 | ||
9315e239 | 2850 | /* TODO Raven hbr2 compliance eye output is unstable |
25bab0da WL |
2851 | * (toggling on and off) with debugger break |
2852 | * This caueses intermittent PHY automation failure | |
2853 | * Need to look into the root cause */ | |
d0778ebf | 2854 | static void dp_test_send_phy_test_pattern(struct dc_link *link) |
4562236b HW |
2855 | { |
2856 | union phy_test_pattern dpcd_test_pattern; | |
2857 | union lane_adjust dpcd_lane_adjustment[2]; | |
2858 | unsigned char dpcd_post_cursor_2_adjustment = 0; | |
5e9ff159 | 2859 | unsigned char test_pattern_buffer[ |
3a340294 DA |
2860 | (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 - |
2861 | DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0}; | |
5e9ff159 | 2862 | unsigned int test_pattern_size = 0; |
4562236b HW |
2863 | enum dp_test_pattern test_pattern; |
2864 | struct dc_link_training_settings link_settings; | |
2865 | union lane_adjust dpcd_lane_adjust; | |
2866 | unsigned int lane; | |
2867 | struct link_training_settings link_training_settings; | |
2868 | int i = 0; | |
2869 | ||
2870 | dpcd_test_pattern.raw = 0; | |
2871 | memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment)); | |
2872 | memset(&link_settings, 0, sizeof(link_settings)); | |
2873 | ||
2874 | /* get phy test pattern and pattern parameters from DP receiver */ | |
2875 | core_link_read_dpcd( | |
2876 | link, | |
8811d9eb | 2877 | DP_PHY_TEST_PATTERN, |
4562236b HW |
2878 | &dpcd_test_pattern.raw, |
2879 | sizeof(dpcd_test_pattern)); | |
2880 | core_link_read_dpcd( | |
2881 | link, | |
3a340294 | 2882 | DP_ADJUST_REQUEST_LANE0_1, |
4562236b HW |
2883 | &dpcd_lane_adjustment[0].raw, |
2884 | sizeof(dpcd_lane_adjustment)); | |
2885 | ||
2886 | /*get post cursor 2 parameters | |
2887 | * For DP 1.1a or eariler, this DPCD register's value is 0 | |
2888 | * For DP 1.2 or later: | |
2889 | * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1 | |
2890 | * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3 | |
2891 | */ | |
2892 | core_link_read_dpcd( | |
2893 | link, | |
3a340294 | 2894 | DP_ADJUST_REQUEST_POST_CURSOR2, |
4562236b HW |
2895 | &dpcd_post_cursor_2_adjustment, |
2896 | sizeof(dpcd_post_cursor_2_adjustment)); | |
2897 | ||
2898 | /* translate request */ | |
2899 | switch (dpcd_test_pattern.bits.PATTERN) { | |
2900 | case PHY_TEST_PATTERN_D10_2: | |
2901 | test_pattern = DP_TEST_PATTERN_D102; | |
0e19401f | 2902 | break; |
4562236b HW |
2903 | case PHY_TEST_PATTERN_SYMBOL_ERROR: |
2904 | test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR; | |
0e19401f | 2905 | break; |
4562236b HW |
2906 | case PHY_TEST_PATTERN_PRBS7: |
2907 | test_pattern = DP_TEST_PATTERN_PRBS7; | |
0e19401f | 2908 | break; |
4562236b HW |
2909 | case PHY_TEST_PATTERN_80BIT_CUSTOM: |
2910 | test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM; | |
0e19401f TC |
2911 | break; |
2912 | case PHY_TEST_PATTERN_CP2520_1: | |
25bab0da | 2913 | /* CP2520 pattern is unstable, temporarily use TPS4 instead */ |
9315e239 | 2914 | test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ? |
25bab0da WL |
2915 | DP_TEST_PATTERN_TRAINING_PATTERN4 : |
2916 | DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE; | |
0e19401f TC |
2917 | break; |
2918 | case PHY_TEST_PATTERN_CP2520_2: | |
25bab0da | 2919 | /* CP2520 pattern is unstable, temporarily use TPS4 instead */ |
9315e239 | 2920 | test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ? |
25bab0da WL |
2921 | DP_TEST_PATTERN_TRAINING_PATTERN4 : |
2922 | DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE; | |
0e19401f TC |
2923 | break; |
2924 | case PHY_TEST_PATTERN_CP2520_3: | |
78e685f9 | 2925 | test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4; |
0e19401f | 2926 | break; |
4562236b HW |
2927 | default: |
2928 | test_pattern = DP_TEST_PATTERN_VIDEO_MODE; | |
2929 | break; | |
2930 | } | |
2931 | ||
5e9ff159 GS |
2932 | if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { |
2933 | test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 - | |
2934 | DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1; | |
4562236b HW |
2935 | core_link_read_dpcd( |
2936 | link, | |
3a340294 | 2937 | DP_TEST_80BIT_CUSTOM_PATTERN_7_0, |
5e9ff159 GS |
2938 | test_pattern_buffer, |
2939 | test_pattern_size); | |
2940 | } | |
4562236b HW |
2941 | |
2942 | /* prepare link training settings */ | |
d0778ebf | 2943 | link_settings.link = link->cur_link_settings; |
4562236b HW |
2944 | |
2945 | for (lane = 0; lane < | |
d0778ebf | 2946 | (unsigned int)(link->cur_link_settings.lane_count); |
4562236b HW |
2947 | lane++) { |
2948 | dpcd_lane_adjust.raw = | |
2949 | get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane); | |
2950 | link_settings.lane_settings[lane].VOLTAGE_SWING = | |
2951 | (enum dc_voltage_swing) | |
2952 | (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE); | |
2953 | link_settings.lane_settings[lane].PRE_EMPHASIS = | |
2954 | (enum dc_pre_emphasis) | |
2955 | (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE); | |
2956 | link_settings.lane_settings[lane].POST_CURSOR2 = | |
2957 | (enum dc_post_cursor2) | |
2958 | ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03); | |
2959 | } | |
2960 | ||
2961 | for (i = 0; i < 4; i++) | |
2962 | link_training_settings.lane_settings[i] = | |
2963 | link_settings.lane_settings[i]; | |
2964 | link_training_settings.link_settings = link_settings.link; | |
2965 | link_training_settings.allow_invalid_msa_timing_param = false; | |
2966 | /*Usage: Measure DP physical lane signal | |
2967 | * by DP SI test equipment automatically. | |
2968 | * PHY test pattern request is generated by equipment via HPD interrupt. | |
2969 | * HPD needs to be active all the time. HPD should be active | |
2970 | * all the time. Do not touch it. | |
2971 | * forward request to DS | |
2972 | */ | |
2973 | dc_link_dp_set_test_pattern( | |
d0778ebf | 2974 | link, |
4562236b | 2975 | test_pattern, |
2057b7e1 | 2976 | DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED, |
4562236b | 2977 | &link_training_settings, |
5e9ff159 GS |
2978 | test_pattern_buffer, |
2979 | test_pattern_size); | |
4562236b HW |
2980 | } |
2981 | ||
d0778ebf | 2982 | static void dp_test_send_link_test_pattern(struct dc_link *link) |
4562236b HW |
2983 | { |
2984 | union link_test_pattern dpcd_test_pattern; | |
2985 | union test_misc dpcd_test_params; | |
2986 | enum dp_test_pattern test_pattern; | |
2057b7e1 WL |
2987 | enum dp_test_pattern_color_space test_pattern_color_space = |
2988 | DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; | |
ac3a4fa1 QZ |
2989 | enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; |
2990 | struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; | |
2991 | struct pipe_ctx *pipe_ctx = NULL; | |
2992 | int i; | |
4562236b HW |
2993 | |
2994 | memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern)); | |
2995 | memset(&dpcd_test_params, 0, sizeof(dpcd_test_params)); | |
2996 | ||
ac3a4fa1 QZ |
2997 | for (i = 0; i < MAX_PIPES; i++) { |
2998 | if (pipes[i].stream == NULL) | |
2999 | continue; | |
3000 | ||
3001 | if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) { | |
3002 | pipe_ctx = &pipes[i]; | |
3003 | break; | |
3004 | } | |
3005 | } | |
3006 | ||
3007 | if (pipe_ctx == NULL) | |
3008 | return; | |
3009 | ||
4562236b HW |
3010 | /* get link test pattern and pattern parameters */ |
3011 | core_link_read_dpcd( | |
3012 | link, | |
3a340294 | 3013 | DP_TEST_PATTERN, |
4562236b HW |
3014 | &dpcd_test_pattern.raw, |
3015 | sizeof(dpcd_test_pattern)); | |
3016 | core_link_read_dpcd( | |
3017 | link, | |
3a340294 | 3018 | DP_TEST_MISC0, |
4562236b HW |
3019 | &dpcd_test_params.raw, |
3020 | sizeof(dpcd_test_params)); | |
3021 | ||
3022 | switch (dpcd_test_pattern.bits.PATTERN) { | |
3023 | case LINK_TEST_PATTERN_COLOR_RAMP: | |
3024 | test_pattern = DP_TEST_PATTERN_COLOR_RAMP; | |
3025 | break; | |
3026 | case LINK_TEST_PATTERN_VERTICAL_BARS: | |
3027 | test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; | |
3028 | break; /* black and white */ | |
3029 | case LINK_TEST_PATTERN_COLOR_SQUARES: | |
3030 | test_pattern = (dpcd_test_params.bits.DYN_RANGE == | |
3031 | TEST_DYN_RANGE_VESA ? | |
3032 | DP_TEST_PATTERN_COLOR_SQUARES : | |
3033 | DP_TEST_PATTERN_COLOR_SQUARES_CEA); | |
3034 | break; | |
3035 | default: | |
3036 | test_pattern = DP_TEST_PATTERN_VIDEO_MODE; | |
3037 | break; | |
3038 | } | |
3039 | ||
ef65c702 JFZ |
3040 | if (dpcd_test_params.bits.CLR_FORMAT == 0) |
3041 | test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; | |
3042 | else | |
3043 | test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? | |
3044 | DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : | |
3045 | DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; | |
2057b7e1 | 3046 | |
ac3a4fa1 QZ |
3047 | switch (dpcd_test_params.bits.BPC) { |
3048 | case 0: // 6 bits | |
3049 | requestColorDepth = COLOR_DEPTH_666; | |
3050 | break; | |
3051 | case 1: // 8 bits | |
3052 | requestColorDepth = COLOR_DEPTH_888; | |
3053 | break; | |
3054 | case 2: // 10 bits | |
3055 | requestColorDepth = COLOR_DEPTH_101010; | |
3056 | break; | |
3057 | case 3: // 12 bits | |
3058 | requestColorDepth = COLOR_DEPTH_121212; | |
3059 | break; | |
3060 | default: | |
3061 | break; | |
3062 | } | |
3063 | ||
98ad74c6 IB |
3064 | switch (dpcd_test_params.bits.CLR_FORMAT) { |
3065 | case 0: | |
3066 | pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB; | |
3067 | break; | |
3068 | case 1: | |
3069 | pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422; | |
3070 | break; | |
3071 | case 2: | |
3072 | pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444; | |
3073 | break; | |
3074 | default: | |
3075 | pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB; | |
3076 | break; | |
3077 | } | |
3078 | ||
3079 | ||
ac3a4fa1 QZ |
3080 | if (requestColorDepth != COLOR_DEPTH_UNDEFINED |
3081 | && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) { | |
92589020 QZ |
3082 | DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n", |
3083 | __func__, | |
3084 | pipe_ctx->stream->timing.display_color_depth, | |
3085 | requestColorDepth); | |
ac3a4fa1 | 3086 | pipe_ctx->stream->timing.display_color_depth = requestColorDepth; |
ac3a4fa1 QZ |
3087 | } |
3088 | ||
98ad74c6 IB |
3089 | dp_update_dsc_config(pipe_ctx); |
3090 | ||
4562236b | 3091 | dc_link_dp_set_test_pattern( |
d0778ebf | 3092 | link, |
4562236b | 3093 | test_pattern, |
2057b7e1 | 3094 | test_pattern_color_space, |
4562236b HW |
3095 | NULL, |
3096 | NULL, | |
3097 | 0); | |
3098 | } | |
3099 | ||
8c8048f2 | 3100 | static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video) |
3101 | { | |
3102 | union audio_test_mode dpcd_test_mode = {0}; | |
3103 | struct audio_test_pattern_type dpcd_pattern_type = {0}; | |
3104 | union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0}; | |
3105 | enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED; | |
3106 | ||
3107 | struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; | |
3108 | struct pipe_ctx *pipe_ctx = &pipes[0]; | |
3109 | unsigned int channel_count; | |
3110 | unsigned int channel = 0; | |
3111 | unsigned int modes = 0; | |
3112 | unsigned int sampling_rate_in_hz = 0; | |
3113 | ||
3114 | // get audio test mode and test pattern parameters | |
3115 | core_link_read_dpcd( | |
3116 | link, | |
3117 | DP_TEST_AUDIO_MODE, | |
3118 | &dpcd_test_mode.raw, | |
3119 | sizeof(dpcd_test_mode)); | |
3120 | ||
3121 | core_link_read_dpcd( | |
3122 | link, | |
3123 | DP_TEST_AUDIO_PATTERN_TYPE, | |
3124 | &dpcd_pattern_type.value, | |
3125 | sizeof(dpcd_pattern_type)); | |
3126 | ||
3127 | channel_count = dpcd_test_mode.bits.channel_count + 1; | |
3128 | ||
3129 | // read pattern periods for requested channels when sawTooth pattern is requested | |
3130 | if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH || | |
3131 | dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) { | |
3132 | ||
3133 | test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ? | |
3134 | DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED; | |
3135 | // read period for each channel | |
3136 | for (channel = 0; channel < channel_count; channel++) { | |
3137 | core_link_read_dpcd( | |
3138 | link, | |
3139 | DP_TEST_AUDIO_PERIOD_CH1 + channel, | |
3140 | &dpcd_pattern_period[channel].raw, | |
3141 | sizeof(dpcd_pattern_period[channel])); | |
3142 | } | |
3143 | } | |
3144 | ||
3145 | // translate sampling rate | |
3146 | switch (dpcd_test_mode.bits.sampling_rate) { | |
3147 | case AUDIO_SAMPLING_RATE_32KHZ: | |
3148 | sampling_rate_in_hz = 32000; | |
3149 | break; | |
3150 | case AUDIO_SAMPLING_RATE_44_1KHZ: | |
3151 | sampling_rate_in_hz = 44100; | |
3152 | break; | |
3153 | case AUDIO_SAMPLING_RATE_48KHZ: | |
3154 | sampling_rate_in_hz = 48000; | |
3155 | break; | |
3156 | case AUDIO_SAMPLING_RATE_88_2KHZ: | |
3157 | sampling_rate_in_hz = 88200; | |
3158 | break; | |
3159 | case AUDIO_SAMPLING_RATE_96KHZ: | |
3160 | sampling_rate_in_hz = 96000; | |
3161 | break; | |
3162 | case AUDIO_SAMPLING_RATE_176_4KHZ: | |
3163 | sampling_rate_in_hz = 176400; | |
3164 | break; | |
3165 | case AUDIO_SAMPLING_RATE_192KHZ: | |
3166 | sampling_rate_in_hz = 192000; | |
3167 | break; | |
3168 | default: | |
3169 | sampling_rate_in_hz = 0; | |
3170 | break; | |
3171 | } | |
3172 | ||
3173 | link->audio_test_data.flags.test_requested = 1; | |
3174 | link->audio_test_data.flags.disable_video = disable_video; | |
3175 | link->audio_test_data.sampling_rate = sampling_rate_in_hz; | |
3176 | link->audio_test_data.channel_count = channel_count; | |
3177 | link->audio_test_data.pattern_type = test_pattern; | |
3178 | ||
3179 | if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) { | |
3180 | for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) { | |
3181 | link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period; | |
3182 | } | |
3183 | } | |
3184 | } | |
3185 | ||
d0778ebf | 3186 | static void handle_automated_test(struct dc_link *link) |
4562236b HW |
3187 | { |
3188 | union test_request test_request; | |
3189 | union test_response test_response; | |
3190 | ||
3191 | memset(&test_request, 0, sizeof(test_request)); | |
3192 | memset(&test_response, 0, sizeof(test_response)); | |
3193 | ||
3194 | core_link_read_dpcd( | |
3195 | link, | |
3a340294 | 3196 | DP_TEST_REQUEST, |
4562236b HW |
3197 | &test_request.raw, |
3198 | sizeof(union test_request)); | |
3199 | if (test_request.bits.LINK_TRAINING) { | |
3200 | /* ACK first to let DP RX test box monitor LT sequence */ | |
3201 | test_response.bits.ACK = 1; | |
3202 | core_link_write_dpcd( | |
3203 | link, | |
3a340294 | 3204 | DP_TEST_RESPONSE, |
4562236b HW |
3205 | &test_response.raw, |
3206 | sizeof(test_response)); | |
3207 | dp_test_send_link_training(link); | |
3208 | /* no acknowledge request is needed again */ | |
3209 | test_response.bits.ACK = 0; | |
3210 | } | |
3211 | if (test_request.bits.LINK_TEST_PATTRN) { | |
3212 | dp_test_send_link_test_pattern(link); | |
75a74755 | 3213 | test_response.bits.ACK = 1; |
4562236b | 3214 | } |
8c8048f2 | 3215 | |
3216 | if (test_request.bits.AUDIO_TEST_PATTERN) { | |
3217 | dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO); | |
3218 | test_response.bits.ACK = 1; | |
3219 | } | |
3220 | ||
4562236b HW |
3221 | if (test_request.bits.PHY_TEST_PATTERN) { |
3222 | dp_test_send_phy_test_pattern(link); | |
3223 | test_response.bits.ACK = 1; | |
3224 | } | |
a6729a5a | 3225 | |
4562236b HW |
3226 | /* send request acknowledgment */ |
3227 | if (test_response.bits.ACK) | |
3228 | core_link_write_dpcd( | |
3229 | link, | |
3a340294 | 3230 | DP_TEST_RESPONSE, |
4562236b HW |
3231 | &test_response.raw, |
3232 | sizeof(test_response)); | |
3233 | } | |
3234 | ||
4e18814e | 3235 | bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss) |
4562236b | 3236 | { |
9a6a8075 | 3237 | union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } }; |
c2e218dd | 3238 | union device_service_irq device_service_clear = { { 0 } }; |
d6258eaa | 3239 | enum dc_status result; |
4562236b | 3240 | bool status = false; |
48af9b91 AL |
3241 | struct pipe_ctx *pipe_ctx; |
3242 | int i; | |
4e18814e FD |
3243 | |
3244 | if (out_link_loss) | |
3245 | *out_link_loss = false; | |
4562236b HW |
3246 | /* For use cases related to down stream connection status change, |
3247 | * PSR and device auto test, refer to function handle_sst_hpd_irq | |
3248 | * in DAL2.1*/ | |
3249 | ||
1296423b | 3250 | DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n", |
d0778ebf | 3251 | __func__, link->link_index); |
4562236b | 3252 | |
8ee65d7c | 3253 | |
4562236b HW |
3254 | /* All the "handle_hpd_irq_xxx()" methods |
3255 | * should be called only after | |
3256 | * dal_dpsst_ls_read_hpd_irq_data | |
3257 | * Order of calls is important too | |
3258 | */ | |
3259 | result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data); | |
8ee65d7c WL |
3260 | if (out_hpd_irq_dpcd_data) |
3261 | *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data; | |
4562236b HW |
3262 | |
3263 | if (result != DC_OK) { | |
1296423b | 3264 | DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n", |
4562236b HW |
3265 | __func__); |
3266 | return false; | |
3267 | } | |
3268 | ||
3269 | if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { | |
3270 | device_service_clear.bits.AUTOMATED_TEST = 1; | |
3271 | core_link_write_dpcd( | |
3272 | link, | |
3a340294 | 3273 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4562236b HW |
3274 | &device_service_clear.raw, |
3275 | sizeof(device_service_clear.raw)); | |
3276 | device_service_clear.raw = 0; | |
3277 | handle_automated_test(link); | |
3278 | return false; | |
3279 | } | |
3280 | ||
3281 | if (!allow_hpd_rx_irq(link)) { | |
1296423b | 3282 | DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n", |
d0778ebf | 3283 | __func__, link->link_index); |
4562236b HW |
3284 | return false; |
3285 | } | |
3286 | ||
3287 | if (handle_hpd_irq_psr_sink(link)) | |
3288 | /* PSR-related error was detected and handled */ | |
3289 | return true; | |
3290 | ||
3291 | /* If PSR-related error handled, Main link may be off, | |
3292 | * so do not handle as a normal sink status change interrupt. | |
3293 | */ | |
3294 | ||
aaa15026 WL |
3295 | if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY) |
3296 | return true; | |
3297 | ||
4562236b | 3298 | /* check if we have MST msg and return since we poll for it */ |
aaa15026 | 3299 | if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) |
4562236b HW |
3300 | return false; |
3301 | ||
3302 | /* For now we only handle 'Downstream port status' case. | |
3303 | * If we got sink count changed it means | |
3304 | * Downstream port status changed, | |
e97ed496 AK |
3305 | * then DM should call DC to do the detection. |
3306 | * NOTE: Do not handle link loss on eDP since it is internal link*/ | |
3307 | if ((link->connector_signal != SIGNAL_TYPE_EDP) && | |
3308 | hpd_rx_irq_check_link_loss_status( | |
3309 | link, | |
3310 | &hpd_irq_dpcd_data)) { | |
4562236b HW |
3311 | /* Connectivity log: link loss */ |
3312 | CONN_DATA_LINK_LOSS(link, | |
3313 | hpd_irq_dpcd_data.raw, | |
3314 | sizeof(hpd_irq_dpcd_data), | |
3315 | "Status: "); | |
3316 | ||
48af9b91 AL |
3317 | for (i = 0; i < MAX_PIPES; i++) { |
3318 | pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; | |
832aa63b PH |
3319 | if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link) |
3320 | break; | |
3321 | } | |
3322 | ||
3323 | if (pipe_ctx == NULL || pipe_ctx->stream == NULL) | |
3324 | return false; | |
3325 | ||
832aa63b | 3326 | |
68423dab AC |
3327 | for (i = 0; i < MAX_PIPES; i++) { |
3328 | pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; | |
3329 | if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off && | |
617ab854 | 3330 | pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) |
68423dab AC |
3331 | core_link_disable_stream(pipe_ctx); |
3332 | } | |
48af9b91 | 3333 | |
422d9091 XY |
3334 | for (i = 0; i < MAX_PIPES; i++) { |
3335 | pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; | |
68423dab | 3336 | if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off && |
617ab854 | 3337 | pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) |
68423dab | 3338 | core_link_enable_stream(link->dc->current_state, pipe_ctx); |
422d9091 XY |
3339 | } |
3340 | ||
4562236b | 3341 | status = false; |
4e18814e FD |
3342 | if (out_link_loss) |
3343 | *out_link_loss = true; | |
4562236b HW |
3344 | } |
3345 | ||
36c9137b | 3346 | if (link->type == dc_connection_sst_branch && |
4562236b HW |
3347 | hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT |
3348 | != link->dpcd_sink_count) | |
3349 | status = true; | |
3350 | ||
3351 | /* reasons for HPD RX: | |
3352 | * 1. Link Loss - ie Re-train the Link | |
3353 | * 2. MST sideband message | |
3354 | * 3. Automated Test - ie. Internal Commit | |
3355 | * 4. CP (copy protection) - (not interesting for DM???) | |
3356 | * 5. DRR | |
3357 | * 6. Downstream Port status changed | |
3358 | * -ie. Detect - this the only one | |
3359 | * which is interesting for DM because | |
3360 | * it must call dc_link_detect. | |
3361 | */ | |
3362 | return status; | |
3363 | } | |
3364 | ||
3365 | /*query dpcd for version and mst cap addresses*/ | |
d0778ebf | 3366 | bool is_mst_supported(struct dc_link *link) |
4562236b HW |
3367 | { |
3368 | bool mst = false; | |
3369 | enum dc_status st = DC_OK; | |
3370 | union dpcd_rev rev; | |
3371 | union mstm_cap cap; | |
3372 | ||
0b226322 DG |
3373 | if (link->preferred_training_settings.mst_enable && |
3374 | *link->preferred_training_settings.mst_enable == false) { | |
3375 | return false; | |
3376 | } | |
3377 | ||
4562236b HW |
3378 | rev.raw = 0; |
3379 | cap.raw = 0; | |
3380 | ||
3a340294 | 3381 | st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw, |
4562236b HW |
3382 | sizeof(rev)); |
3383 | ||
3384 | if (st == DC_OK && rev.raw >= DPCD_REV_12) { | |
3385 | ||
3a340294 | 3386 | st = core_link_read_dpcd(link, DP_MSTM_CAP, |
4562236b HW |
3387 | &cap.raw, sizeof(cap)); |
3388 | if (st == DC_OK && cap.bits.MST_CAP == 1) | |
3389 | mst = true; | |
3390 | } | |
3391 | return mst; | |
3392 | ||
3393 | } | |
3394 | ||
d0778ebf | 3395 | bool is_dp_active_dongle(const struct dc_link *link) |
36c9137b DZ |
3396 | { |
3397 | return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) && | |
3398 | (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER); | |
3399 | } | |
3400 | ||
3401 | bool is_dp_branch_device(const struct dc_link *link) | |
4562236b | 3402 | { |
a504ad26 | 3403 | return link->dpcd_caps.is_branch_dev; |
4562236b HW |
3404 | } |
3405 | ||
6bffebc9 EY |
3406 | static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc) |
3407 | { | |
3408 | switch (bpc) { | |
3409 | case DOWN_STREAM_MAX_8BPC: | |
3410 | return 8; | |
3411 | case DOWN_STREAM_MAX_10BPC: | |
3412 | return 10; | |
3413 | case DOWN_STREAM_MAX_12BPC: | |
3414 | return 12; | |
3415 | case DOWN_STREAM_MAX_16BPC: | |
3416 | return 16; | |
3417 | default: | |
3418 | break; | |
3419 | } | |
3420 | ||
3421 | return -1; | |
3422 | } | |
3423 | ||
ee13cea9 JB |
3424 | static void read_dp_device_vendor_id(struct dc_link *link) |
3425 | { | |
3426 | struct dp_device_vendor_id dp_id; | |
3427 | ||
3428 | /* read IEEE branch device id */ | |
3429 | core_link_read_dpcd( | |
3430 | link, | |
3431 | DP_BRANCH_OUI, | |
3432 | (uint8_t *)&dp_id, | |
3433 | sizeof(dp_id)); | |
3434 | ||
3435 | link->dpcd_caps.branch_dev_id = | |
3436 | (dp_id.ieee_oui[0] << 16) + | |
3437 | (dp_id.ieee_oui[1] << 8) + | |
3438 | dp_id.ieee_oui[2]; | |
3439 | ||
3440 | memmove( | |
3441 | link->dpcd_caps.branch_dev_name, | |
3442 | dp_id.ieee_device_id, | |
3443 | sizeof(dp_id.ieee_device_id)); | |
3444 | } | |
3445 | ||
3446 | ||
3447 | ||
4562236b | 3448 | static void get_active_converter_info( |
d0778ebf | 3449 | uint8_t data, struct dc_link *link) |
4562236b HW |
3450 | { |
3451 | union dp_downstream_port_present ds_port = { .byte = data }; | |
dd998291 | 3452 | memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps)); |
4562236b HW |
3453 | |
3454 | /* decode converter info*/ | |
3455 | if (!ds_port.fields.PORT_PRESENT) { | |
3456 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; | |
d0778ebf | 3457 | ddc_service_set_dongle_type(link->ddc, |
4562236b | 3458 | link->dpcd_caps.dongle_type); |
ac3d76e0 | 3459 | link->dpcd_caps.is_branch_dev = false; |
4562236b HW |
3460 | return; |
3461 | } | |
3462 | ||
a504ad26 | 3463 | /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */ |
9413b23f | 3464 | link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT; |
a504ad26 | 3465 | |
4562236b HW |
3466 | switch (ds_port.fields.PORT_TYPE) { |
3467 | case DOWNSTREAM_VGA: | |
3468 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER; | |
3469 | break; | |
7a83645a DZ |
3470 | case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS: |
3471 | /* At this point we don't know is it DVI or HDMI or DP++, | |
4562236b HW |
3472 | * assume DVI.*/ |
3473 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER; | |
3474 | break; | |
3475 | default: | |
3476 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; | |
3477 | break; | |
3478 | } | |
3479 | ||
ac0e562c | 3480 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) { |
242b0c8f | 3481 | uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/ |
4562236b HW |
3482 | union dwnstream_port_caps_byte0 *port_caps = |
3483 | (union dwnstream_port_caps_byte0 *)det_caps; | |
5aedc7bc | 3484 | if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0, |
3485 | det_caps, sizeof(det_caps)) == DC_OK) { | |
4562236b | 3486 | |
5aedc7bc | 3487 | switch (port_caps->bits.DWN_STRM_PORTX_TYPE) { |
3488 | /*Handle DP case as DONGLE_NONE*/ | |
3489 | case DOWN_STREAM_DETAILED_DP: | |
3490 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; | |
3491 | break; | |
3492 | case DOWN_STREAM_DETAILED_VGA: | |
3493 | link->dpcd_caps.dongle_type = | |
3494 | DISPLAY_DONGLE_DP_VGA_CONVERTER; | |
3495 | break; | |
3496 | case DOWN_STREAM_DETAILED_DVI: | |
3497 | link->dpcd_caps.dongle_type = | |
3498 | DISPLAY_DONGLE_DP_DVI_CONVERTER; | |
3499 | break; | |
3500 | case DOWN_STREAM_DETAILED_HDMI: | |
3501 | case DOWN_STREAM_DETAILED_DP_PLUS_PLUS: | |
3502 | /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/ | |
3503 | link->dpcd_caps.dongle_type = | |
3504 | DISPLAY_DONGLE_DP_HDMI_CONVERTER; | |
3505 | ||
3506 | link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type; | |
3507 | if (ds_port.fields.DETAILED_CAPS) { | |
3508 | ||
3509 | union dwnstream_port_caps_byte3_hdmi | |
3510 | hdmi_caps = {.raw = det_caps[3] }; | |
3511 | union dwnstream_port_caps_byte2 | |
3512 | hdmi_color_caps = {.raw = det_caps[2] }; | |
3513 | link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz = | |
3514 | det_caps[1] * 2500; | |
3515 | ||
3516 | link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter = | |
3517 | hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK; | |
3518 | /*YCBCR capability only for HDMI case*/ | |
3519 | if (port_caps->bits.DWN_STRM_PORTX_TYPE | |
3520 | == DOWN_STREAM_DETAILED_HDMI) { | |
3521 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through = | |
3522 | hdmi_caps.bits.YCrCr422_PASS_THROUGH; | |
3523 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through = | |
3524 | hdmi_caps.bits.YCrCr420_PASS_THROUGH; | |
3525 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter = | |
3526 | hdmi_caps.bits.YCrCr422_CONVERSION; | |
3527 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter = | |
3528 | hdmi_caps.bits.YCrCr420_CONVERSION; | |
3529 | } | |
3530 | ||
3531 | link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc = | |
3532 | translate_dpcd_max_bpc( | |
3533 | hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); | |
3534 | ||
3535 | if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) | |
3536 | link->dpcd_caps.dongle_caps.extendedCapValid = true; | |
7a83645a | 3537 | } |
03f5c686 | 3538 | |
5aedc7bc | 3539 | break; |
4562236b | 3540 | } |
4562236b HW |
3541 | } |
3542 | } | |
3543 | ||
d0778ebf | 3544 | ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type); |
4562236b | 3545 | |
4562236b HW |
3546 | { |
3547 | struct dp_sink_hw_fw_revision dp_hw_fw_revision; | |
3548 | ||
3549 | core_link_read_dpcd( | |
3550 | link, | |
3a340294 | 3551 | DP_BRANCH_REVISION_START, |
4562236b HW |
3552 | (uint8_t *)&dp_hw_fw_revision, |
3553 | sizeof(dp_hw_fw_revision)); | |
3554 | ||
3555 | link->dpcd_caps.branch_hw_revision = | |
3556 | dp_hw_fw_revision.ieee_hw_rev; | |
4b99affb A |
3557 | |
3558 | memmove( | |
3559 | link->dpcd_caps.branch_fw_revision, | |
3560 | dp_hw_fw_revision.ieee_fw_rev, | |
3561 | sizeof(dp_hw_fw_revision.ieee_fw_rev)); | |
4562236b HW |
3562 | } |
3563 | } | |
3564 | ||
d0778ebf | 3565 | static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data, |
4562236b HW |
3566 | int length) |
3567 | { | |
3568 | int retry = 0; | |
4562236b HW |
3569 | |
3570 | if (!link->dpcd_caps.dpcd_rev.raw) { | |
3571 | do { | |
3572 | dp_receiver_power_ctrl(link, true); | |
3a340294 | 3573 | core_link_read_dpcd(link, DP_DPCD_REV, |
4562236b HW |
3574 | dpcd_data, length); |
3575 | link->dpcd_caps.dpcd_rev.raw = dpcd_data[ | |
3a340294 DA |
3576 | DP_DPCD_REV - |
3577 | DP_DPCD_REV]; | |
4562236b HW |
3578 | } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw); |
3579 | } | |
3580 | ||
4562236b HW |
3581 | if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) { |
3582 | switch (link->dpcd_caps.branch_dev_id) { | |
df3b7e32 | 3583 | /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down |
4562236b HW |
3584 | * all internal circuits including AUX communication preventing |
3585 | * reading DPCD table and EDID (spec violation). | |
3586 | * Encoder will skip DP RX power down on disable_output to | |
3587 | * keep receiver powered all the time.*/ | |
df3b7e32 QZ |
3588 | case DP_BRANCH_DEVICE_ID_0010FA: |
3589 | case DP_BRANCH_DEVICE_ID_0080E1: | |
566b4252 | 3590 | case DP_BRANCH_DEVICE_ID_00E04C: |
4562236b HW |
3591 | link->wa_flags.dp_keep_receiver_powered = true; |
3592 | break; | |
3593 | ||
3594 | /* TODO: May need work around for other dongles. */ | |
3595 | default: | |
3596 | link->wa_flags.dp_keep_receiver_powered = false; | |
3597 | break; | |
3598 | } | |
3599 | } else | |
3600 | link->wa_flags.dp_keep_receiver_powered = false; | |
3601 | } | |
3602 | ||
96577cf8 HW |
3603 | /* Read additional sink caps defined in source specific DPCD area |
3604 | * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP) | |
3605 | */ | |
3606 | static bool dpcd_read_sink_ext_caps(struct dc_link *link) | |
3607 | { | |
3608 | uint8_t dpcd_data; | |
3609 | ||
3610 | if (!link) | |
3611 | return false; | |
3612 | ||
3613 | if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK) | |
3614 | return false; | |
3615 | ||
3616 | link->dpcd_sink_ext_caps.raw = dpcd_data; | |
3617 | return true; | |
3618 | } | |
3619 | ||
cdb39798 | 3620 | static bool retrieve_link_cap(struct dc_link *link) |
4562236b | 3621 | { |
61aa7a6f | 3622 | /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16, |
3623 | * which means size 16 will be good for both of those DPCD register block reads | |
3624 | */ | |
3625 | uint8_t dpcd_data[16]; | |
3626 | uint8_t lttpr_dpcd_data[6]; | |
4562236b | 3627 | |
3c7dd2cb HT |
3628 | /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST. |
3629 | */ | |
3630 | uint8_t dpcd_dprx_data = '\0'; | |
8633d96d | 3631 | uint8_t dpcd_power_state = '\0'; |
3c7dd2cb | 3632 | |
8ca80900 | 3633 | struct dp_device_vendor_id sink_id; |
4562236b HW |
3634 | union down_stream_port_count down_strm_port_count; |
3635 | union edp_configuration_cap edp_config_cap; | |
3636 | union dp_downstream_port_present ds_port = { 0 }; | |
cdb39798 | 3637 | enum dc_status status = DC_ERROR_UNEXPECTED; |
3c1a312a YS |
3638 | uint32_t read_dpcd_retry_cnt = 3; |
3639 | int i; | |
4b99affb | 3640 | struct dp_sink_hw_fw_revision dp_hw_fw_revision; |
c797ede0 WL |
3641 | bool is_lttpr_present = false; |
3642 | const uint32_t post_oui_delay = 30; // 30ms | |
7809fc00 WC |
3643 | bool vbios_lttpr_enable = false; |
3644 | bool vbios_lttpr_interop = false; | |
3645 | struct dc_bios *bios = link->dc->ctx->dc_bios; | |
8e5100a5 | 3646 | |
4562236b | 3647 | memset(dpcd_data, '\0', sizeof(dpcd_data)); |
61aa7a6f | 3648 | memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data)); |
4562236b HW |
3649 | memset(&down_strm_port_count, |
3650 | '\0', sizeof(union down_stream_port_count)); | |
3651 | memset(&edp_config_cap, '\0', | |
3652 | sizeof(union edp_configuration_cap)); | |
3653 | ||
c797ede0 WL |
3654 | /* if extended timeout is supported in hardware, |
3655 | * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer | |
3656 | * CTS 4.2.1.1 regression introduced by CTS specs requirement update. | |
3657 | */ | |
3658 | dc_link_aux_try_to_configure_timeout(link->ddc, | |
3659 | LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); | |
3660 | ||
8633d96d AK |
3661 | status = core_link_read_dpcd(link, DP_SET_POWER, |
3662 | &dpcd_power_state, sizeof(dpcd_power_state)); | |
3663 | ||
3664 | /* Delay 1 ms if AUX CH is in power down state. Based on spec | |
3665 | * section 2.3.1.2, if AUX CH may be powered down due to | |
3666 | * write to DPCD 600h = 2. Sink AUX CH is monitoring differential | |
3667 | * signal and may need up to 1 ms before being able to reply. | |
3668 | */ | |
3669 | if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) | |
3670 | udelay(1000); | |
3671 | ||
c797ede0 WL |
3672 | dpcd_set_source_specific_data(link); |
3673 | /* Sink may need to configure internals based on vendor, so allow some | |
3674 | * time before proceeding with possibly vendor specific transactions | |
3675 | */ | |
3676 | msleep(post_oui_delay); | |
3677 | ||
3c1a312a YS |
3678 | for (i = 0; i < read_dpcd_retry_cnt; i++) { |
3679 | status = core_link_read_dpcd( | |
3680 | link, | |
3681 | DP_DPCD_REV, | |
3682 | dpcd_data, | |
3683 | sizeof(dpcd_data)); | |
3684 | if (status == DC_OK) | |
3685 | break; | |
3686 | } | |
cdb39798 YS |
3687 | |
3688 | if (status != DC_OK) { | |
3689 | dm_error("%s: Read dpcd data failed.\n", __func__); | |
3690 | return false; | |
3691 | } | |
4562236b | 3692 | |
7809fc00 WC |
3693 | /* Query BIOS to determine if LTTPR functionality is forced on by system */ |
3694 | if (bios->funcs->get_lttpr_caps) { | |
3695 | enum bp_result bp_query_result; | |
3696 | uint8_t is_vbios_lttpr_enable = 0; | |
3697 | ||
3698 | bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable); | |
3699 | vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; | |
3700 | } | |
3701 | ||
3702 | if (bios->funcs->get_lttpr_interop) { | |
3703 | enum bp_result bp_query_result; | |
3704 | uint8_t is_vbios_interop_enabled = 0; | |
3705 | ||
3706 | bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled); | |
3707 | vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; | |
3708 | } | |
3709 | ||
3710 | /* | |
3711 | * Logic to determine LTTPR mode | |
3712 | */ | |
3713 | link->lttpr_mode = LTTPR_MODE_NON_LTTPR; | |
3714 | if (vbios_lttpr_enable && vbios_lttpr_interop) | |
3715 | link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; | |
3716 | else if (!vbios_lttpr_enable && vbios_lttpr_interop) { | |
3717 | if (link->dc->config.allow_lttpr_non_transparent_mode) | |
3718 | link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; | |
3719 | else | |
3720 | link->lttpr_mode = LTTPR_MODE_TRANSPARENT; | |
3721 | } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) { | |
3722 | if (!link->dc->config.allow_lttpr_non_transparent_mode | |
3723 | || !link->dc->caps.extended_aux_timeout_support) | |
3724 | link->lttpr_mode = LTTPR_MODE_NON_LTTPR; | |
3725 | else | |
3726 | link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; | |
3727 | } | |
3728 | ||
3729 | if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) { | |
c797ede0 | 3730 | /* By reading LTTPR capability, RX assumes that we will enable |
7809fc00 | 3731 | * LTTPR extended aux timeout if LTTPR is present. |
c797ede0 | 3732 | */ |
8e5100a5 | 3733 | status = core_link_read_dpcd( |
3734 | link, | |
61aa7a6f | 3735 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, |
3736 | lttpr_dpcd_data, | |
3737 | sizeof(lttpr_dpcd_data)); | |
3738 | ||
3739 | link->dpcd_caps.lttpr_caps.revision.raw = | |
3740 | lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV - | |
3741 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3742 | ||
3743 | link->dpcd_caps.lttpr_caps.max_link_rate = | |
3744 | lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER - | |
3745 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3746 | ||
3747 | link->dpcd_caps.lttpr_caps.phy_repeater_cnt = | |
3748 | lttpr_dpcd_data[DP_PHY_REPEATER_CNT - | |
3749 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3750 | ||
3751 | link->dpcd_caps.lttpr_caps.max_lane_count = | |
3752 | lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER - | |
3753 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3754 | ||
3755 | link->dpcd_caps.lttpr_caps.mode = | |
3756 | lttpr_dpcd_data[DP_PHY_REPEATER_MODE - | |
3757 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3758 | ||
3759 | link->dpcd_caps.lttpr_caps.max_ext_timeout = | |
3760 | lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT - | |
3761 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
3762 | ||
ede4f6da | 3763 | /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */ |
c797ede0 | 3764 | is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 && |
ede4f6da | 3765 | link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff && |
61aa7a6f | 3766 | link->dpcd_caps.lttpr_caps.max_lane_count > 0 && |
3767 | link->dpcd_caps.lttpr_caps.max_lane_count <= 4 && | |
c797ede0 WL |
3768 | link->dpcd_caps.lttpr_caps.revision.raw >= 0x14); |
3769 | if (is_lttpr_present) | |
3770 | CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); | |
fab85801 WC |
3771 | else |
3772 | link->lttpr_mode = LTTPR_MODE_NON_LTTPR; | |
a1500a62 | 3773 | } |
fb8cf277 | 3774 | |
c797ede0 WL |
3775 | if (!is_lttpr_present) |
3776 | dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); | |
3777 | ||
3778 | ||
4562236b HW |
3779 | { |
3780 | union training_aux_rd_interval aux_rd_interval; | |
3781 | ||
3782 | aux_rd_interval.raw = | |
3a340294 | 3783 | dpcd_data[DP_TRAINING_AUX_RD_INTERVAL]; |
4562236b | 3784 | |
3c7dd2cb | 3785 | link->dpcd_caps.ext_receiver_cap_field_present = |
b239b59b | 3786 | aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1; |
3c7dd2cb HT |
3787 | |
3788 | if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) { | |
818832bf XY |
3789 | uint8_t ext_cap_data[16]; |
3790 | ||
3791 | memset(ext_cap_data, '\0', sizeof(ext_cap_data)); | |
3792 | for (i = 0; i < read_dpcd_retry_cnt; i++) { | |
3793 | status = core_link_read_dpcd( | |
4562236b | 3794 | link, |
3a340294 | 3795 | DP_DP13_DPCD_REV, |
818832bf XY |
3796 | ext_cap_data, |
3797 | sizeof(ext_cap_data)); | |
3798 | if (status == DC_OK) { | |
3799 | memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data)); | |
3800 | break; | |
3801 | } | |
3802 | } | |
3803 | if (status != DC_OK) | |
3804 | dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__); | |
4562236b HW |
3805 | } |
3806 | } | |
3807 | ||
3c7dd2cb HT |
3808 | link->dpcd_caps.dpcd_rev.raw = |
3809 | dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; | |
3810 | ||
7715fdf3 | 3811 | if (link->dpcd_caps.ext_receiver_cap_field_present) { |
3c7dd2cb HT |
3812 | for (i = 0; i < read_dpcd_retry_cnt; i++) { |
3813 | status = core_link_read_dpcd( | |
3814 | link, | |
3815 | DP_DPRX_FEATURE_ENUMERATION_LIST, | |
3816 | &dpcd_dprx_data, | |
3817 | sizeof(dpcd_dprx_data)); | |
3818 | if (status == DC_OK) | |
3819 | break; | |
3820 | } | |
3821 | ||
3822 | link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data; | |
3823 | ||
3824 | if (status != DC_OK) | |
3825 | dm_error("%s: Read DPRX caps data failed.\n", __func__); | |
3826 | } | |
3827 | ||
3828 | else { | |
3829 | link->dpcd_caps.dprx_feature.raw = 0; | |
3830 | } | |
3831 | ||
3832 | ||
07d6a199 AK |
3833 | /* Error condition checking... |
3834 | * It is impossible for Sink to report Max Lane Count = 0. | |
3835 | * It is possible for Sink to report Max Link Rate = 0, if it is | |
3836 | * an eDP device that is reporting specialized link rates in the | |
3837 | * SUPPORTED_LINK_RATE table. | |
3838 | */ | |
3839 | if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) | |
3840 | return false; | |
3841 | ||
3a340294 DA |
3842 | ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT - |
3843 | DP_DPCD_REV]; | |
4562236b | 3844 | |
ee13cea9 JB |
3845 | read_dp_device_vendor_id(link); |
3846 | ||
4562236b HW |
3847 | get_active_converter_info(ds_port.byte, link); |
3848 | ||
3849 | dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data)); | |
3850 | ||
98e6436d AK |
3851 | down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT - |
3852 | DP_DPCD_REV]; | |
3853 | ||
4562236b HW |
3854 | link->dpcd_caps.allow_invalid_MSA_timing_param = |
3855 | down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; | |
3856 | ||
3857 | link->dpcd_caps.max_ln_count.raw = dpcd_data[ | |
3a340294 | 3858 | DP_MAX_LANE_COUNT - DP_DPCD_REV]; |
4562236b HW |
3859 | |
3860 | link->dpcd_caps.max_down_spread.raw = dpcd_data[ | |
3a340294 | 3861 | DP_MAX_DOWNSPREAD - DP_DPCD_REV]; |
4562236b | 3862 | |
d0778ebf | 3863 | link->reported_link_cap.lane_count = |
4562236b | 3864 | link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; |
d0778ebf | 3865 | link->reported_link_cap.link_rate = dpcd_data[ |
3a340294 | 3866 | DP_MAX_LINK_RATE - DP_DPCD_REV]; |
d0778ebf | 3867 | link->reported_link_cap.link_spread = |
4562236b HW |
3868 | link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? |
3869 | LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; | |
3870 | ||
3871 | edp_config_cap.raw = dpcd_data[ | |
3a340294 | 3872 | DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV]; |
4562236b HW |
3873 | link->dpcd_caps.panel_mode_edp = |
3874 | edp_config_cap.bits.ALT_SCRAMBLER_RESET; | |
9799624a WL |
3875 | link->dpcd_caps.dpcd_display_control_capable = |
3876 | edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE; | |
4562236b | 3877 | |
d0778ebf HW |
3878 | link->test_pattern_enabled = false; |
3879 | link->compliance_test_state.raw = 0; | |
4562236b | 3880 | |
4562236b HW |
3881 | /* read sink count */ |
3882 | core_link_read_dpcd(link, | |
3a340294 | 3883 | DP_SINK_COUNT, |
4562236b HW |
3884 | &link->dpcd_caps.sink_count.raw, |
3885 | sizeof(link->dpcd_caps.sink_count.raw)); | |
3886 | ||
8ca80900 AK |
3887 | /* read sink ieee oui */ |
3888 | core_link_read_dpcd(link, | |
3889 | DP_SINK_OUI, | |
3890 | (uint8_t *)(&sink_id), | |
3891 | sizeof(sink_id)); | |
3892 | ||
3893 | link->dpcd_caps.sink_dev_id = | |
3894 | (sink_id.ieee_oui[0] << 16) + | |
3895 | (sink_id.ieee_oui[1] << 8) + | |
3896 | (sink_id.ieee_oui[2]); | |
3897 | ||
4b99affb A |
3898 | memmove( |
3899 | link->dpcd_caps.sink_dev_id_str, | |
3900 | sink_id.ieee_device_id, | |
3901 | sizeof(sink_id.ieee_device_id)); | |
3902 | ||
473e3f77 MK |
3903 | /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */ |
3904 | { | |
3905 | uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 }; | |
3906 | ||
3907 | if ((link->dpcd_caps.sink_dev_id == 0x0010fa) && | |
3908 | !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017, | |
3909 | sizeof(str_mbp_2017))) { | |
3910 | link->reported_link_cap.link_rate = 0x0c; | |
3911 | } | |
3912 | } | |
3913 | ||
4b99affb A |
3914 | core_link_read_dpcd( |
3915 | link, | |
3916 | DP_SINK_HW_REVISION_START, | |
3917 | (uint8_t *)&dp_hw_fw_revision, | |
3918 | sizeof(dp_hw_fw_revision)); | |
3919 | ||
3920 | link->dpcd_caps.sink_hw_revision = | |
3921 | dp_hw_fw_revision.ieee_hw_rev; | |
3922 | ||
3923 | memmove( | |
3924 | link->dpcd_caps.sink_fw_revision, | |
3925 | dp_hw_fw_revision.ieee_fw_rev, | |
3926 | sizeof(dp_hw_fw_revision.ieee_fw_rev)); | |
3927 | ||
39a4eb85 WL |
3928 | memset(&link->dpcd_caps.dsc_caps, '\0', |
3929 | sizeof(link->dpcd_caps.dsc_caps)); | |
97bda032 HW |
3930 | memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); |
3931 | /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */ | |
3932 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) { | |
97bda032 HW |
3933 | status = core_link_read_dpcd( |
3934 | link, | |
3935 | DP_FEC_CAPABILITY, | |
3936 | &link->dpcd_caps.fec_cap.raw, | |
3937 | sizeof(link->dpcd_caps.fec_cap.raw)); | |
39a4eb85 WL |
3938 | status = core_link_read_dpcd( |
3939 | link, | |
3940 | DP_DSC_SUPPORT, | |
3941 | link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, | |
3942 | sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw)); | |
3943 | status = core_link_read_dpcd( | |
3944 | link, | |
3945 | DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, | |
6d824ed5 WL |
3946 | link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, |
3947 | sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw)); | |
97bda032 | 3948 | } |
6fbefb84 | 3949 | |
96577cf8 HW |
3950 | if (!dpcd_read_sink_ext_caps(link)) |
3951 | link->dpcd_sink_ext_caps.raw = 0; | |
3952 | ||
4562236b HW |
3953 | /* Connectivity log: detection */ |
3954 | CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: "); | |
cdb39798 YS |
3955 | |
3956 | return true; | |
4562236b HW |
3957 | } |
3958 | ||
8547058b LH |
3959 | bool dp_overwrite_extended_receiver_cap(struct dc_link *link) |
3960 | { | |
3961 | uint8_t dpcd_data[16]; | |
3962 | uint32_t read_dpcd_retry_cnt = 3; | |
3963 | enum dc_status status = DC_ERROR_UNEXPECTED; | |
3964 | union dp_downstream_port_present ds_port = { 0 }; | |
3965 | union down_stream_port_count down_strm_port_count; | |
3966 | union edp_configuration_cap edp_config_cap; | |
3967 | ||
3968 | int i; | |
3969 | ||
3970 | for (i = 0; i < read_dpcd_retry_cnt; i++) { | |
3971 | status = core_link_read_dpcd( | |
3972 | link, | |
3973 | DP_DPCD_REV, | |
3974 | dpcd_data, | |
3975 | sizeof(dpcd_data)); | |
3976 | if (status == DC_OK) | |
3977 | break; | |
3978 | } | |
3979 | ||
3980 | link->dpcd_caps.dpcd_rev.raw = | |
3981 | dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; | |
3982 | ||
3983 | if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) | |
3984 | return false; | |
3985 | ||
3986 | ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT - | |
3987 | DP_DPCD_REV]; | |
3988 | ||
3989 | get_active_converter_info(ds_port.byte, link); | |
3990 | ||
3991 | down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT - | |
3992 | DP_DPCD_REV]; | |
3993 | ||
3994 | link->dpcd_caps.allow_invalid_MSA_timing_param = | |
3995 | down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; | |
3996 | ||
3997 | link->dpcd_caps.max_ln_count.raw = dpcd_data[ | |
3998 | DP_MAX_LANE_COUNT - DP_DPCD_REV]; | |
3999 | ||
4000 | link->dpcd_caps.max_down_spread.raw = dpcd_data[ | |
4001 | DP_MAX_DOWNSPREAD - DP_DPCD_REV]; | |
4002 | ||
4003 | link->reported_link_cap.lane_count = | |
4004 | link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; | |
4005 | link->reported_link_cap.link_rate = dpcd_data[ | |
4006 | DP_MAX_LINK_RATE - DP_DPCD_REV]; | |
4007 | link->reported_link_cap.link_spread = | |
4008 | link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? | |
4009 | LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; | |
4010 | ||
4011 | edp_config_cap.raw = dpcd_data[ | |
4012 | DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV]; | |
4013 | link->dpcd_caps.panel_mode_edp = | |
4014 | edp_config_cap.bits.ALT_SCRAMBLER_RESET; | |
4015 | link->dpcd_caps.dpcd_display_control_capable = | |
4016 | edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE; | |
4017 | ||
4018 | return true; | |
4019 | } | |
4020 | ||
cdb39798 | 4021 | bool detect_dp_sink_caps(struct dc_link *link) |
4562236b | 4022 | { |
cdb39798 | 4023 | return retrieve_link_cap(link); |
4562236b HW |
4024 | |
4025 | /* dc init_hw has power encoder using default | |
4026 | * signal for connector. For native DP, no | |
4027 | * need to power up encoder again. If not native | |
4028 | * DP, hw_init may need check signal or power up | |
4029 | * encoder here. | |
4030 | */ | |
4562236b HW |
4031 | /* TODO save sink caps in link->sink */ |
4032 | } | |
4033 | ||
d308d0b4 | 4034 | static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) |
b03a599b DL |
4035 | { |
4036 | enum dc_link_rate link_rate; | |
4037 | // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation. | |
4038 | switch (link_rate_in_khz) { | |
4039 | case 1620000: | |
4040 | link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane | |
4041 | break; | |
4042 | case 2160000: | |
4043 | link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane | |
4044 | break; | |
4045 | case 2430000: | |
4046 | link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane | |
4047 | break; | |
4048 | case 2700000: | |
4049 | link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane | |
4050 | break; | |
4051 | case 3240000: | |
4052 | link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane | |
4053 | break; | |
4054 | case 4320000: | |
4055 | link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane | |
4056 | break; | |
4057 | case 5400000: | |
4058 | link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane | |
4059 | break; | |
4060 | case 8100000: | |
4061 | link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane | |
4062 | break; | |
4063 | default: | |
4064 | link_rate = LINK_RATE_UNKNOWN; | |
4065 | break; | |
4066 | } | |
4067 | return link_rate; | |
4068 | } | |
4069 | ||
4654a2f7 RL |
4070 | void detect_edp_sink_caps(struct dc_link *link) |
4071 | { | |
8628d02f | 4072 | uint8_t supported_link_rates[16]; |
b03a599b DL |
4073 | uint32_t entry; |
4074 | uint32_t link_rate_in_khz; | |
4075 | enum dc_link_rate link_rate = LINK_RATE_UNKNOWN; | |
65e870df | 4076 | uint8_t backlight_adj_cap; |
48231fd5 | 4077 | |
b03a599b | 4078 | retrieve_link_cap(link); |
8628d02f JP |
4079 | link->dpcd_caps.edp_supported_link_rates_count = 0; |
4080 | memset(supported_link_rates, 0, sizeof(supported_link_rates)); | |
48231fd5 | 4081 | |
67c268a5 ZL |
4082 | /* |
4083 | * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. | |
4084 | * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" | |
4085 | */ | |
4086 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 && | |
66611a72 | 4087 | (link->dc->debug.optimize_edp_link_rate || |
53c81fc7 | 4088 | link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) { |
b03a599b DL |
4089 | // Read DPCD 00010h - 0001Fh 16 bytes at one shot |
4090 | core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES, | |
4091 | supported_link_rates, sizeof(supported_link_rates)); | |
4092 | ||
b03a599b DL |
4093 | for (entry = 0; entry < 16; entry += 2) { |
4094 | // DPCD register reports per-lane link rate = 16-bit link rate capability | |
8628d02f | 4095 | // value X 200 kHz. Need multiplier to find link rate in kHz. |
b03a599b DL |
4096 | link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + |
4097 | supported_link_rates[entry]) * 200; | |
4098 | ||
4099 | if (link_rate_in_khz != 0) { | |
4100 | link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz); | |
8628d02f JP |
4101 | link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate; |
4102 | link->dpcd_caps.edp_supported_link_rates_count++; | |
53c81fc7 WC |
4103 | |
4104 | if (link->reported_link_cap.link_rate < link_rate) | |
4105 | link->reported_link_cap.link_rate = link_rate; | |
b03a599b DL |
4106 | } |
4107 | } | |
4108 | } | |
4654a2f7 | 4109 | link->verified_link_cap = link->reported_link_cap; |
96577cf8 | 4110 | |
65e870df RC |
4111 | core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP, |
4112 | &backlight_adj_cap, sizeof(backlight_adj_cap)); | |
4113 | ||
4114 | link->dpcd_caps.dynamic_backlight_capable_edp = | |
4115 | (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false; | |
4116 | ||
96577cf8 | 4117 | dc_link_set_default_brightness_aux(link); |
4654a2f7 RL |
4118 | } |
4119 | ||
4562236b HW |
4120 | void dc_link_dp_enable_hpd(const struct dc_link *link) |
4121 | { | |
d0778ebf | 4122 | struct link_encoder *encoder = link->link_enc; |
4562236b HW |
4123 | |
4124 | if (encoder != NULL && encoder->funcs->enable_hpd != NULL) | |
4125 | encoder->funcs->enable_hpd(encoder); | |
4126 | } | |
4127 | ||
4128 | void dc_link_dp_disable_hpd(const struct dc_link *link) | |
4129 | { | |
d0778ebf | 4130 | struct link_encoder *encoder = link->link_enc; |
4562236b HW |
4131 | |
4132 | if (encoder != NULL && encoder->funcs->enable_hpd != NULL) | |
4133 | encoder->funcs->disable_hpd(encoder); | |
4134 | } | |
4135 | ||
4136 | static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern) | |
4137 | { | |
0e19401f TC |
4138 | if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern && |
4139 | test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) || | |
4140 | test_pattern == DP_TEST_PATTERN_VIDEO_MODE) | |
4562236b HW |
4141 | return true; |
4142 | else | |
4143 | return false; | |
4144 | } | |
4145 | ||
d0778ebf | 4146 | static void set_crtc_test_pattern(struct dc_link *link, |
4562236b | 4147 | struct pipe_ctx *pipe_ctx, |
2057b7e1 WL |
4148 | enum dp_test_pattern test_pattern, |
4149 | enum dp_test_pattern_color_space test_pattern_color_space) | |
4562236b HW |
4150 | { |
4151 | enum controller_dp_test_pattern controller_test_pattern; | |
4152 | enum dc_color_depth color_depth = pipe_ctx-> | |
4fa086b9 | 4153 | stream->timing.display_color_depth; |
4562236b | 4154 | struct bit_depth_reduction_params params; |
661a8cd9 | 4155 | struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; |
6fbefb84 HW |
4156 | int width = pipe_ctx->stream->timing.h_addressable + |
4157 | pipe_ctx->stream->timing.h_border_left + | |
4158 | pipe_ctx->stream->timing.h_border_right; | |
4159 | int height = pipe_ctx->stream->timing.v_addressable + | |
4160 | pipe_ctx->stream->timing.v_border_bottom + | |
4161 | pipe_ctx->stream->timing.v_border_top; | |
4562236b HW |
4162 | |
4163 | memset(¶ms, 0, sizeof(params)); | |
4164 | ||
4165 | switch (test_pattern) { | |
4166 | case DP_TEST_PATTERN_COLOR_SQUARES: | |
4167 | controller_test_pattern = | |
4168 | CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; | |
4169 | break; | |
4170 | case DP_TEST_PATTERN_COLOR_SQUARES_CEA: | |
4171 | controller_test_pattern = | |
4172 | CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA; | |
4173 | break; | |
4174 | case DP_TEST_PATTERN_VERTICAL_BARS: | |
4175 | controller_test_pattern = | |
4176 | CONTROLLER_DP_TEST_PATTERN_VERTICALBARS; | |
4177 | break; | |
4178 | case DP_TEST_PATTERN_HORIZONTAL_BARS: | |
4179 | controller_test_pattern = | |
4180 | CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS; | |
4181 | break; | |
4182 | case DP_TEST_PATTERN_COLOR_RAMP: | |
4183 | controller_test_pattern = | |
4184 | CONTROLLER_DP_TEST_PATTERN_COLORRAMP; | |
4185 | break; | |
4186 | default: | |
4187 | controller_test_pattern = | |
4188 | CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; | |
4189 | break; | |
4190 | } | |
4191 | ||
4192 | switch (test_pattern) { | |
4193 | case DP_TEST_PATTERN_COLOR_SQUARES: | |
4194 | case DP_TEST_PATTERN_COLOR_SQUARES_CEA: | |
4195 | case DP_TEST_PATTERN_VERTICAL_BARS: | |
4196 | case DP_TEST_PATTERN_HORIZONTAL_BARS: | |
4197 | case DP_TEST_PATTERN_COLOR_RAMP: | |
4198 | { | |
4199 | /* disable bit depth reduction */ | |
4200 | pipe_ctx->stream->bit_depth_params = params; | |
661a8cd9 | 4201 | opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms); |
7f93c1de CL |
4202 | if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) |
4203 | pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, | |
4562236b | 4204 | controller_test_pattern, color_depth); |
dbf5256b | 4205 | else if (link->dc->hwss.set_disp_pattern_generator) { |
b1f6d01c | 4206 | struct pipe_ctx *odm_pipe; |
2057b7e1 | 4207 | enum controller_dp_color_space controller_color_space; |
b1f6d01c | 4208 | int opp_cnt = 1; |
10b4e64e WL |
4209 | int offset = 0; |
4210 | int dpg_width = width; | |
6fbefb84 | 4211 | |
2057b7e1 WL |
4212 | switch (test_pattern_color_space) { |
4213 | case DP_TEST_PATTERN_COLOR_SPACE_RGB: | |
4214 | controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; | |
4215 | break; | |
4216 | case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601: | |
4217 | controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601; | |
4218 | break; | |
4219 | case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709: | |
4220 | controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709; | |
4221 | break; | |
4222 | case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED: | |
4223 | default: | |
4224 | controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; | |
4225 | DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__); | |
4226 | ASSERT(0); | |
4227 | break; | |
4228 | } | |
4229 | ||
b1f6d01c DL |
4230 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) |
4231 | opp_cnt++; | |
10b4e64e WL |
4232 | dpg_width = width / opp_cnt; |
4233 | offset = dpg_width; | |
6fbefb84 | 4234 | |
dbf5256b JA |
4235 | link->dc->hwss.set_disp_pattern_generator(link->dc, |
4236 | pipe_ctx, | |
6fbefb84 | 4237 | controller_test_pattern, |
2057b7e1 | 4238 | controller_color_space, |
6fbefb84 HW |
4239 | color_depth, |
4240 | NULL, | |
10b4e64e WL |
4241 | dpg_width, |
4242 | height, | |
dbf5256b JA |
4243 | 0); |
4244 | ||
4245 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { | |
4246 | struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; | |
4247 | ||
4248 | odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms); | |
4249 | link->dc->hwss.set_disp_pattern_generator(link->dc, | |
4250 | odm_pipe, | |
4251 | controller_test_pattern, | |
4252 | controller_color_space, | |
4253 | color_depth, | |
4254 | NULL, | |
4255 | dpg_width, | |
4256 | height, | |
4257 | offset); | |
10b4e64e | 4258 | offset += offset; |
6fbefb84 | 4259 | } |
6fbefb84 | 4260 | } |
4562236b HW |
4261 | } |
4262 | break; | |
4263 | case DP_TEST_PATTERN_VIDEO_MODE: | |
4264 | { | |
4265 | /* restore bitdepth reduction */ | |
661a8cd9 | 4266 | resource_build_bit_depth_reduction_params(pipe_ctx->stream, ¶ms); |
4562236b | 4267 | pipe_ctx->stream->bit_depth_params = params; |
661a8cd9 | 4268 | opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms); |
7f93c1de CL |
4269 | if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) |
4270 | pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, | |
4562236b HW |
4271 | CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, |
4272 | color_depth); | |
dbf5256b | 4273 | else if (link->dc->hwss.set_disp_pattern_generator) { |
b1f6d01c DL |
4274 | struct pipe_ctx *odm_pipe; |
4275 | int opp_cnt = 1; | |
10b4e64e | 4276 | int dpg_width = width; |
b1f6d01c DL |
4277 | |
4278 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) | |
4279 | opp_cnt++; | |
6fbefb84 | 4280 | |
10b4e64e | 4281 | dpg_width = width / opp_cnt; |
b1f6d01c DL |
4282 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { |
4283 | struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; | |
6fbefb84 | 4284 | |
b1f6d01c | 4285 | odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms); |
dbf5256b JA |
4286 | link->dc->hwss.set_disp_pattern_generator(link->dc, |
4287 | odm_pipe, | |
4288 | CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, | |
4289 | CONTROLLER_DP_COLOR_SPACE_UDEFINED, | |
4290 | color_depth, | |
4291 | NULL, | |
4292 | dpg_width, | |
4293 | height, | |
4294 | 0); | |
4295 | } | |
4296 | link->dc->hwss.set_disp_pattern_generator(link->dc, | |
4297 | pipe_ctx, | |
6fbefb84 | 4298 | CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, |
2057b7e1 | 4299 | CONTROLLER_DP_COLOR_SPACE_UDEFINED, |
6fbefb84 HW |
4300 | color_depth, |
4301 | NULL, | |
10b4e64e WL |
4302 | dpg_width, |
4303 | height, | |
4304 | 0); | |
6fbefb84 | 4305 | } |
4562236b HW |
4306 | } |
4307 | break; | |
4308 | ||
4309 | default: | |
4310 | break; | |
4311 | } | |
4312 | } | |
4313 | ||
4314 | bool dc_link_dp_set_test_pattern( | |
d0778ebf | 4315 | struct dc_link *link, |
4562236b | 4316 | enum dp_test_pattern test_pattern, |
2057b7e1 | 4317 | enum dp_test_pattern_color_space test_pattern_color_space, |
4562236b HW |
4318 | const struct link_training_settings *p_link_settings, |
4319 | const unsigned char *p_custom_pattern, | |
4320 | unsigned int cust_pattern_size) | |
4321 | { | |
608ac7bb | 4322 | struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; |
33fd9cb8 | 4323 | struct pipe_ctx *pipe_ctx = NULL; |
4562236b HW |
4324 | unsigned int lane; |
4325 | unsigned int i; | |
4326 | unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0}; | |
4327 | union dpcd_training_pattern training_pattern; | |
4562236b HW |
4328 | enum dpcd_phy_test_patterns pattern; |
4329 | ||
4330 | memset(&training_pattern, 0, sizeof(training_pattern)); | |
4562236b HW |
4331 | |
4332 | for (i = 0; i < MAX_PIPES; i++) { | |
33fd9cb8 QZ |
4333 | if (pipes[i].stream == NULL) |
4334 | continue; | |
4335 | ||
24d01c9b | 4336 | if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) { |
0a8f43ff | 4337 | pipe_ctx = &pipes[i]; |
4562236b HW |
4338 | break; |
4339 | } | |
4340 | } | |
4341 | ||
33fd9cb8 QZ |
4342 | if (pipe_ctx == NULL) |
4343 | return false; | |
4344 | ||
dbf5256b | 4345 | /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */ |
d0778ebf | 4346 | if (link->test_pattern_enabled && test_pattern == |
4562236b HW |
4347 | DP_TEST_PATTERN_VIDEO_MODE) { |
4348 | /* Set CRTC Test Pattern */ | |
2057b7e1 | 4349 | set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space); |
d0778ebf | 4350 | dp_set_hw_test_pattern(link, test_pattern, |
4562236b HW |
4351 | (uint8_t *)p_custom_pattern, |
4352 | (uint32_t)cust_pattern_size); | |
4353 | ||
4354 | /* Unblank Stream */ | |
d0778ebf | 4355 | link->dc->hwss.unblank_stream( |
0a8f43ff | 4356 | pipe_ctx, |
d0778ebf | 4357 | &link->verified_link_cap); |
4562236b HW |
4358 | /* TODO:m_pHwss->MuteAudioEndpoint |
4359 | * (pPathMode->pDisplayPath, false); | |
4360 | */ | |
4361 | ||
4362 | /* Reset Test Pattern state */ | |
d0778ebf | 4363 | link->test_pattern_enabled = false; |
4562236b HW |
4364 | |
4365 | return true; | |
4366 | } | |
4367 | ||
4368 | /* Check for PHY Test Patterns */ | |
4369 | if (is_dp_phy_pattern(test_pattern)) { | |
4370 | /* Set DPCD Lane Settings before running test pattern */ | |
4371 | if (p_link_settings != NULL) { | |
64c12b73 | 4372 | dp_set_hw_lane_settings(link, p_link_settings, DPRX); |
4373 | dpcd_set_lane_settings(link, p_link_settings, DPRX); | |
4562236b HW |
4374 | } |
4375 | ||
4376 | /* Blank stream if running test pattern */ | |
4377 | if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { | |
4378 | /*TODO: | |
4379 | * m_pHwss-> | |
4380 | * MuteAudioEndpoint(pPathMode->pDisplayPath, true); | |
4381 | */ | |
4382 | /* Blank stream */ | |
8e9c4c8c | 4383 | pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); |
4562236b HW |
4384 | } |
4385 | ||
d0778ebf | 4386 | dp_set_hw_test_pattern(link, test_pattern, |
4562236b HW |
4387 | (uint8_t *)p_custom_pattern, |
4388 | (uint32_t)cust_pattern_size); | |
4389 | ||
4390 | if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { | |
4391 | /* Set Test Pattern state */ | |
d0778ebf | 4392 | link->test_pattern_enabled = true; |
4562236b | 4393 | if (p_link_settings != NULL) |
d0778ebf | 4394 | dpcd_set_link_settings(link, |
4562236b HW |
4395 | p_link_settings); |
4396 | } | |
4397 | ||
4398 | switch (test_pattern) { | |
4399 | case DP_TEST_PATTERN_VIDEO_MODE: | |
4400 | pattern = PHY_TEST_PATTERN_NONE; | |
0e19401f | 4401 | break; |
4562236b HW |
4402 | case DP_TEST_PATTERN_D102: |
4403 | pattern = PHY_TEST_PATTERN_D10_2; | |
0e19401f | 4404 | break; |
4562236b HW |
4405 | case DP_TEST_PATTERN_SYMBOL_ERROR: |
4406 | pattern = PHY_TEST_PATTERN_SYMBOL_ERROR; | |
0e19401f | 4407 | break; |
4562236b HW |
4408 | case DP_TEST_PATTERN_PRBS7: |
4409 | pattern = PHY_TEST_PATTERN_PRBS7; | |
0e19401f | 4410 | break; |
4562236b HW |
4411 | case DP_TEST_PATTERN_80BIT_CUSTOM: |
4412 | pattern = PHY_TEST_PATTERN_80BIT_CUSTOM; | |
0e19401f TC |
4413 | break; |
4414 | case DP_TEST_PATTERN_CP2520_1: | |
4415 | pattern = PHY_TEST_PATTERN_CP2520_1; | |
4416 | break; | |
4417 | case DP_TEST_PATTERN_CP2520_2: | |
4418 | pattern = PHY_TEST_PATTERN_CP2520_2; | |
4419 | break; | |
4420 | case DP_TEST_PATTERN_CP2520_3: | |
4421 | pattern = PHY_TEST_PATTERN_CP2520_3; | |
4422 | break; | |
4562236b HW |
4423 | default: |
4424 | return false; | |
4425 | } | |
4426 | ||
4427 | if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE | |
4428 | /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/) | |
4429 | return false; | |
4430 | ||
d0778ebf | 4431 | if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { |
4562236b HW |
4432 | /* tell receiver that we are sending qualification |
4433 | * pattern DP 1.2 or later - DP receiver's link quality | |
4434 | * pattern is set using DPCD LINK_QUAL_LANEx_SET | |
4435 | * register (0x10B~0x10E)\ | |
4436 | */ | |
4437 | for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) | |
4438 | link_qual_pattern[lane] = | |
4439 | (unsigned char)(pattern); | |
4440 | ||
d0778ebf | 4441 | core_link_write_dpcd(link, |
3a340294 | 4442 | DP_LINK_QUAL_LANE0_SET, |
4562236b HW |
4443 | link_qual_pattern, |
4444 | sizeof(link_qual_pattern)); | |
d0778ebf HW |
4445 | } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 || |
4446 | link->dpcd_caps.dpcd_rev.raw == 0) { | |
4562236b HW |
4447 | /* tell receiver that we are sending qualification |
4448 | * pattern DP 1.1a or earlier - DP receiver's link | |
4449 | * quality pattern is set using | |
4450 | * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET | |
4451 | * register (0x102). We will use v_1.3 when we are | |
4452 | * setting test pattern for DP 1.1. | |
4453 | */ | |
d0778ebf HW |
4454 | core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET, |
4455 | &training_pattern.raw, | |
4456 | sizeof(training_pattern)); | |
4562236b | 4457 | training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern; |
d0778ebf HW |
4458 | core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET, |
4459 | &training_pattern.raw, | |
4460 | sizeof(training_pattern)); | |
4562236b HW |
4461 | } |
4462 | } else { | |
43563bc2 | 4463 | enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; |
43563bc2 WL |
4464 | |
4465 | switch (test_pattern_color_space) { | |
4466 | case DP_TEST_PATTERN_COLOR_SPACE_RGB: | |
4467 | color_space = COLOR_SPACE_SRGB; | |
4468 | if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA) | |
4469 | color_space = COLOR_SPACE_SRGB_LIMITED; | |
4470 | break; | |
4471 | ||
4472 | case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601: | |
4473 | color_space = COLOR_SPACE_YCBCR601; | |
4474 | if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA) | |
4475 | color_space = COLOR_SPACE_YCBCR601_LIMITED; | |
4476 | break; | |
4477 | case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709: | |
4478 | color_space = COLOR_SPACE_YCBCR709; | |
4479 | if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA) | |
4480 | color_space = COLOR_SPACE_YCBCR709_LIMITED; | |
4481 | break; | |
4482 | default: | |
4483 | break; | |
4484 | } | |
e8f9ecf2 | 4485 | |
dc6e2448 WW |
4486 | if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) { |
4487 | if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) { | |
4488 | union dmub_hw_lock_flags hw_locks = { 0 }; | |
4489 | struct dmub_hw_lock_inst_flags inst_flags = { 0 }; | |
4490 | ||
4491 | hw_locks.bits.lock_dig = 1; | |
4492 | inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; | |
4493 | ||
4494 | dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv, | |
4495 | true, | |
4496 | &hw_locks, | |
4497 | &inst_flags); | |
4498 | } else | |
4499 | pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable( | |
4500 | pipe_ctx->stream_res.tg); | |
4501 | } | |
4502 | ||
e8f9ecf2 | 4503 | pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); |
43563bc2 WL |
4504 | /* update MSA to requested color space */ |
4505 | pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc, | |
4506 | &pipe_ctx->stream->timing, | |
23bc5f34 WL |
4507 | color_space, |
4508 | pipe_ctx->stream->use_vsc_sdp_for_colorimetry, | |
4509 | link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP); | |
43563bc2 | 4510 | |
e8f9ecf2 WL |
4511 | if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) { |
4512 | if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA) | |
4513 | pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range | |
4514 | else | |
4515 | pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7); | |
4516 | resource_build_info_frame(pipe_ctx); | |
4517 | link->dc->hwss.update_info_frame(pipe_ctx); | |
4518 | } | |
4519 | ||
43563bc2 | 4520 | /* CRTC Patterns */ |
2057b7e1 | 4521 | set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space); |
e8f9ecf2 WL |
4522 | pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); |
4523 | pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, | |
4524 | CRTC_STATE_VACTIVE); | |
4525 | pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, | |
4526 | CRTC_STATE_VBLANK); | |
4527 | pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, | |
4528 | CRTC_STATE_VACTIVE); | |
dc6e2448 WW |
4529 | |
4530 | if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) { | |
4531 | if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) { | |
4532 | union dmub_hw_lock_flags hw_locks = { 0 }; | |
4533 | struct dmub_hw_lock_inst_flags inst_flags = { 0 }; | |
4534 | ||
4535 | hw_locks.bits.lock_dig = 1; | |
4536 | inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; | |
4537 | ||
4538 | dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv, | |
4539 | false, | |
4540 | &hw_locks, | |
4541 | &inst_flags); | |
4542 | } else | |
4543 | pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable( | |
4544 | pipe_ctx->stream_res.tg); | |
4545 | } | |
4546 | ||
4562236b | 4547 | /* Set Test Pattern state */ |
d0778ebf | 4548 | link->test_pattern_enabled = true; |
4562236b HW |
4549 | } |
4550 | ||
4551 | return true; | |
4552 | } | |
07c84c7a | 4553 | |
d0778ebf | 4554 | void dp_enable_mst_on_sink(struct dc_link *link, bool enable) |
07c84c7a DW |
4555 | { |
4556 | unsigned char mstmCntl; | |
4557 | ||
4558 | core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); | |
4559 | if (enable) | |
4560 | mstmCntl |= DP_MST_EN; | |
4561 | else | |
4562 | mstmCntl &= (~DP_MST_EN); | |
4563 | ||
4564 | core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); | |
4565 | } | |
6fbefb84 | 4566 | |
0b226322 DG |
4567 | void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode) |
4568 | { | |
4569 | union dpcd_edp_config edp_config_set; | |
4570 | bool panel_mode_edp = false; | |
4571 | ||
4572 | memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config)); | |
4573 | ||
4574 | if (panel_mode != DP_PANEL_MODE_DEFAULT) { | |
4575 | ||
4576 | switch (panel_mode) { | |
4577 | case DP_PANEL_MODE_EDP: | |
4578 | case DP_PANEL_MODE_SPECIAL: | |
4579 | panel_mode_edp = true; | |
4580 | break; | |
4581 | ||
4582 | default: | |
4583 | break; | |
4584 | } | |
4585 | ||
4586 | /*set edp panel mode in receiver*/ | |
4587 | core_link_read_dpcd( | |
4588 | link, | |
4589 | DP_EDP_CONFIGURATION_SET, | |
4590 | &edp_config_set.raw, | |
4591 | sizeof(edp_config_set.raw)); | |
4592 | ||
4593 | if (edp_config_set.bits.PANEL_MODE_EDP | |
4594 | != panel_mode_edp) { | |
140b93eb | 4595 | enum dc_status result; |
0b226322 DG |
4596 | |
4597 | edp_config_set.bits.PANEL_MODE_EDP = | |
4598 | panel_mode_edp; | |
4599 | result = core_link_write_dpcd( | |
4600 | link, | |
4601 | DP_EDP_CONFIGURATION_SET, | |
4602 | &edp_config_set.raw, | |
4603 | sizeof(edp_config_set.raw)); | |
4604 | ||
a110f375 | 4605 | ASSERT(result == DC_OK); |
0b226322 DG |
4606 | } |
4607 | } | |
4608 | DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d " | |
4609 | "eDP panel mode enabled: %d \n", | |
4610 | link->link_index, | |
4611 | link->dpcd_caps.panel_mode_edp, | |
4612 | panel_mode_edp); | |
4613 | } | |
4614 | ||
4615 | enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) | |
4616 | { | |
4617 | /* We need to explicitly check that connector | |
4618 | * is not DP. Some Travis_VGA get reported | |
4619 | * by video bios as DP. | |
4620 | */ | |
4621 | if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { | |
4622 | ||
4623 | switch (link->dpcd_caps.branch_dev_id) { | |
df3b7e32 QZ |
4624 | case DP_BRANCH_DEVICE_ID_0022B9: |
4625 | /* alternate scrambler reset is required for Travis | |
4626 | * for the case when external chip does not | |
4627 | * provide sink device id, alternate scrambler | |
4628 | * scheme will be overriden later by querying | |
4629 | * Encoder features | |
4630 | */ | |
0b226322 DG |
4631 | if (strncmp( |
4632 | link->dpcd_caps.branch_dev_name, | |
4633 | DP_VGA_LVDS_CONVERTER_ID_2, | |
4634 | sizeof( | |
4635 | link->dpcd_caps. | |
4636 | branch_dev_name)) == 0) { | |
4637 | return DP_PANEL_MODE_SPECIAL; | |
4638 | } | |
4639 | break; | |
df3b7e32 QZ |
4640 | case DP_BRANCH_DEVICE_ID_00001A: |
4641 | /* alternate scrambler reset is required for Travis | |
4642 | * for the case when external chip does not provide | |
4643 | * sink device id, alternate scrambler scheme will | |
4644 | * be overriden later by querying Encoder feature | |
4645 | */ | |
0b226322 DG |
4646 | if (strncmp(link->dpcd_caps.branch_dev_name, |
4647 | DP_VGA_LVDS_CONVERTER_ID_3, | |
4648 | sizeof( | |
4649 | link->dpcd_caps. | |
4650 | branch_dev_name)) == 0) { | |
4651 | return DP_PANEL_MODE_SPECIAL; | |
4652 | } | |
4653 | break; | |
4654 | default: | |
4655 | break; | |
4656 | } | |
4657 | } | |
4658 | ||
4659 | if (link->dpcd_caps.panel_mode_edp) { | |
4660 | return DP_PANEL_MODE_EDP; | |
4661 | } | |
4662 | ||
4663 | return DP_PANEL_MODE_DEFAULT; | |
4664 | } | |
4665 | ||
7211b605 | 4666 | enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready) |
97bda032 HW |
4667 | { |
4668 | /* FEC has to be "set ready" before the link training. | |
4669 | * The policy is to always train with FEC | |
4670 | * if the sink supports it and leave it enabled on link. | |
4671 | * If FEC is not supported, disable it. | |
4672 | */ | |
7211b605 JK |
4673 | struct link_encoder *link_enc = NULL; |
4674 | enum dc_status status = DC_OK; | |
97bda032 HW |
4675 | uint8_t fec_config = 0; |
4676 | ||
7211b605 JK |
4677 | /* Access link encoder based on whether it is statically |
4678 | * or dynamically assigned to a link. | |
4679 | */ | |
4680 | if (link->is_dig_mapping_flexible && | |
4681 | link->dc->res_pool->funcs->link_encs_assign) | |
4682 | link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link); | |
4683 | else | |
4684 | link_enc = link->link_enc; | |
4685 | ASSERT(link_enc); | |
4686 | ||
89c7dfa9 | 4687 | if (!dc_link_should_enable_fec(link)) |
7211b605 | 4688 | return status; |
97bda032 HW |
4689 | |
4690 | if (link_enc->funcs->fec_set_ready && | |
4691 | link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { | |
008a4016 | 4692 | if (ready) { |
97bda032 | 4693 | fec_config = 1; |
7211b605 | 4694 | status = core_link_write_dpcd(link, |
97bda032 HW |
4695 | DP_FEC_CONFIGURATION, |
4696 | &fec_config, | |
7211b605 JK |
4697 | sizeof(fec_config)); |
4698 | if (status == DC_OK) { | |
97bda032 HW |
4699 | link_enc->funcs->fec_set_ready(link_enc, true); |
4700 | link->fec_state = dc_link_fec_ready; | |
4701 | } else { | |
7211b605 | 4702 | link_enc->funcs->fec_set_ready(link->link_enc, false); |
d68a7454 | 4703 | link->fec_state = dc_link_fec_not_ready; |
97bda032 HW |
4704 | dm_error("dpcd write failed to set fec_ready"); |
4705 | } | |
008a4016 | 4706 | } else if (link->fec_state == dc_link_fec_ready) { |
97bda032 | 4707 | fec_config = 0; |
7211b605 | 4708 | status = core_link_write_dpcd(link, |
97bda032 HW |
4709 | DP_FEC_CONFIGURATION, |
4710 | &fec_config, | |
4711 | sizeof(fec_config)); | |
7211b605 | 4712 | link_enc->funcs->fec_set_ready(link_enc, false); |
97bda032 HW |
4713 | link->fec_state = dc_link_fec_not_ready; |
4714 | } | |
4715 | } | |
7211b605 JK |
4716 | |
4717 | return status; | |
97bda032 HW |
4718 | } |
4719 | ||
4720 | void dp_set_fec_enable(struct dc_link *link, bool enable) | |
4721 | { | |
7211b605 JK |
4722 | struct link_encoder *link_enc = NULL; |
4723 | ||
4724 | /* Access link encoder based on whether it is statically | |
4725 | * or dynamically assigned to a link. | |
4726 | */ | |
4727 | if (link->is_dig_mapping_flexible && | |
4728 | link->dc->res_pool->funcs->link_encs_assign) | |
4729 | link_enc = link_enc_cfg_get_link_enc_used_by_link( | |
4730 | link->dc->current_state, link); | |
4731 | else | |
4732 | link_enc = link->link_enc; | |
4733 | ASSERT(link_enc); | |
97bda032 | 4734 | |
89c7dfa9 | 4735 | if (!dc_link_should_enable_fec(link)) |
97bda032 HW |
4736 | return; |
4737 | ||
4738 | if (link_enc->funcs->fec_set_enable && | |
4739 | link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { | |
4740 | if (link->fec_state == dc_link_fec_ready && enable) { | |
fa11d3c9 LHM |
4741 | /* Accord to DP spec, FEC enable sequence can first |
4742 | * be transmitted anytime after 1000 LL codes have | |
4743 | * been transmitted on the link after link training | |
4744 | * completion. Using 1 lane RBR should have the maximum | |
4745 | * time for transmitting 1000 LL codes which is 6.173 us. | |
4746 | * So use 7 microseconds delay instead. | |
4747 | */ | |
4748 | udelay(7); | |
97bda032 HW |
4749 | link_enc->funcs->fec_set_enable(link_enc, true); |
4750 | link->fec_state = dc_link_fec_enabled; | |
4751 | } else if (link->fec_state == dc_link_fec_enabled && !enable) { | |
4752 | link_enc->funcs->fec_set_enable(link_enc, false); | |
4753 | link->fec_state = dc_link_fec_ready; | |
4754 | } | |
4755 | } | |
4756 | } | |
6fbefb84 | 4757 | |
96577cf8 HW |
4758 | void dpcd_set_source_specific_data(struct dc_link *link) |
4759 | { | |
0136684f | 4760 | if (!link->dc->vendor_signature.is_valid) { |
61f02424 | 4761 | enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED; |
29d5ac56 YS |
4762 | struct dpcd_amd_signature amd_signature = {0}; |
4763 | struct dpcd_amd_device_id amd_device_id = {0}; | |
4764 | ||
4765 | amd_device_id.device_id_byte1 = | |
0136684f | 4766 | (uint8_t)(link->ctx->asic_id.chip_id); |
29d5ac56 | 4767 | amd_device_id.device_id_byte2 = |
0136684f | 4768 | (uint8_t)(link->ctx->asic_id.chip_id >> 8); |
29d5ac56 | 4769 | amd_device_id.dce_version = |
0136684f | 4770 | (uint8_t)(link->ctx->dce_version); |
29d5ac56 YS |
4771 | amd_device_id.dal_version_byte1 = 0x0; // needed? where to get? |
4772 | amd_device_id.dal_version_byte2 = 0x0; // needed? where to get? | |
4773 | ||
4774 | core_link_read_dpcd(link, DP_SOURCE_OUI, | |
4775 | (uint8_t *)(&amd_signature), | |
4776 | sizeof(amd_signature)); | |
0136684f | 4777 | |
29d5ac56 YS |
4778 | if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) && |
4779 | (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) && | |
4780 | (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) { | |
4781 | ||
4782 | amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0; | |
4783 | amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0; | |
4784 | amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A; | |
4785 | ||
4786 | core_link_write_dpcd(link, DP_SOURCE_OUI, | |
0136684f CH |
4787 | (uint8_t *)(&amd_signature), |
4788 | sizeof(amd_signature)); | |
29d5ac56 YS |
4789 | } |
4790 | ||
4791 | core_link_write_dpcd(link, DP_SOURCE_OUI+0x03, | |
4792 | (uint8_t *)(&amd_device_id), | |
4793 | sizeof(amd_device_id)); | |
0136684f | 4794 | |
9248681f AT |
4795 | if (link->ctx->dce_version >= DCN_VERSION_2_0 && |
4796 | link->dc->caps.min_horizontal_blanking_period != 0) { | |
4797 | ||
4798 | uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period; | |
4799 | ||
4800 | result_write_min_hblank = core_link_write_dpcd(link, | |
4801 | DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size), | |
4802 | sizeof(hblank_size)); | |
4803 | } | |
4804 | DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, | |
4805 | WPP_BIT_FLAG_DC_DETECTION_DP_CAPS, | |
4806 | "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'", | |
4807 | result_write_min_hblank, | |
4808 | link->link_index, | |
4809 | link->ctx->dce_version, | |
4810 | DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, | |
4811 | link->dc->caps.min_horizontal_blanking_period, | |
4812 | link->dpcd_caps.branch_dev_id, | |
4813 | link->dpcd_caps.branch_dev_name[0], | |
4814 | link->dpcd_caps.branch_dev_name[1], | |
4815 | link->dpcd_caps.branch_dev_name[2], | |
4816 | link->dpcd_caps.branch_dev_name[3], | |
4817 | link->dpcd_caps.branch_dev_name[4], | |
4818 | link->dpcd_caps.branch_dev_name[5]); | |
0136684f CH |
4819 | } else { |
4820 | core_link_write_dpcd(link, DP_SOURCE_OUI, | |
4821 | link->dc->vendor_signature.data.raw, | |
4822 | sizeof(link->dc->vendor_signature.data.raw)); | |
4823 | } | |
96577cf8 HW |
4824 | } |
4825 | ||
4826 | bool dc_link_set_backlight_level_nits(struct dc_link *link, | |
4827 | bool isHDR, | |
4828 | uint32_t backlight_millinits, | |
4829 | uint32_t transition_time_in_ms) | |
4830 | { | |
4831 | struct dpcd_source_backlight_set dpcd_backlight_set; | |
4832 | uint8_t backlight_control = isHDR ? 1 : 0; | |
4833 | ||
4834 | if (!link || (link->connector_signal != SIGNAL_TYPE_EDP && | |
4835 | link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)) | |
4836 | return false; | |
4837 | ||
4838 | // OLEDs have no PWM, they can only use AUX | |
4839 | if (link->dpcd_sink_ext_caps.bits.oled == 1) | |
4840 | backlight_control = 1; | |
4841 | ||
4842 | *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits; | |
4843 | *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms; | |
4844 | ||
4845 | ||
4846 | if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL, | |
4847 | (uint8_t *)(&dpcd_backlight_set), | |
4848 | sizeof(dpcd_backlight_set)) != DC_OK) | |
4849 | return false; | |
4850 | ||
4851 | if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL, | |
4852 | &backlight_control, 1) != DC_OK) | |
4853 | return false; | |
4854 | ||
4855 | return true; | |
4856 | } | |
4857 | ||
4858 | bool dc_link_get_backlight_level_nits(struct dc_link *link, | |
4859 | uint32_t *backlight_millinits_avg, | |
4860 | uint32_t *backlight_millinits_peak) | |
4861 | { | |
4862 | union dpcd_source_backlight_get dpcd_backlight_get; | |
4863 | ||
4864 | memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get)); | |
4865 | ||
4866 | if (!link || (link->connector_signal != SIGNAL_TYPE_EDP && | |
4867 | link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)) | |
4868 | return false; | |
4869 | ||
16697cf3 | 4870 | if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK, |
96577cf8 | 4871 | dpcd_backlight_get.raw, |
16697cf3 | 4872 | sizeof(union dpcd_source_backlight_get)) != DC_OK) |
96577cf8 HW |
4873 | return false; |
4874 | ||
4875 | *backlight_millinits_avg = | |
4876 | dpcd_backlight_get.bytes.backlight_millinits_avg; | |
4877 | *backlight_millinits_peak = | |
4878 | dpcd_backlight_get.bytes.backlight_millinits_peak; | |
4879 | ||
4880 | /* On non-supported panels dpcd_read usually succeeds with 0 returned */ | |
4881 | if (*backlight_millinits_avg == 0 || | |
4882 | *backlight_millinits_avg > *backlight_millinits_peak) | |
4883 | return false; | |
4884 | ||
4885 | return true; | |
4886 | } | |
4887 | ||
4888 | bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable) | |
4889 | { | |
4890 | uint8_t backlight_enable = enable ? 1 : 0; | |
4891 | ||
4892 | if (!link || (link->connector_signal != SIGNAL_TYPE_EDP && | |
4893 | link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)) | |
4894 | return false; | |
4895 | ||
4896 | if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE, | |
4897 | &backlight_enable, 1) != DC_OK) | |
4898 | return false; | |
4899 | ||
4900 | return true; | |
4901 | } | |
4902 | ||
4903 | // we read default from 0x320 because we expect BIOS wrote it there | |
4904 | // regular get_backlight_nit reads from panel set at 0x326 | |
4905 | bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits) | |
4906 | { | |
4907 | if (!link || (link->connector_signal != SIGNAL_TYPE_EDP && | |
4908 | link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)) | |
4909 | return false; | |
4910 | ||
16697cf3 | 4911 | if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL, |
96577cf8 | 4912 | (uint8_t *) backlight_millinits, |
16697cf3 | 4913 | sizeof(uint32_t)) != DC_OK) |
96577cf8 HW |
4914 | return false; |
4915 | ||
4916 | return true; | |
4917 | } | |
4918 | ||
4919 | bool dc_link_set_default_brightness_aux(struct dc_link *link) | |
4920 | { | |
4921 | uint32_t default_backlight; | |
4922 | ||
4923 | if (link && | |
4924 | (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || | |
4925 | link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) { | |
4926 | if (!dc_link_read_default_bl_aux(link, &default_backlight)) | |
4927 | default_backlight = 150000; | |
4928 | // if < 5 nits or > 5000, it might be wrong readback | |
4929 | if (default_backlight < 5000 || default_backlight > 5000000) | |
4930 | default_backlight = 150000; // | |
4931 | ||
4932 | return dc_link_set_backlight_level_nits(link, true, | |
4933 | default_backlight, 0); | |
4934 | } | |
4935 | return false; | |
4936 | } | |
f9fc6f39 MS |
4937 | |
4938 | bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing) | |
4939 | { | |
4940 | struct dc_link_settings link_setting; | |
4941 | uint8_t link_bw_set; | |
4942 | uint8_t link_rate_set; | |
4943 | uint32_t req_bw; | |
4944 | union lane_count_set lane_count_set = { {0} }; | |
4945 | ||
4946 | ASSERT(link || crtc_timing); // invalid input | |
4947 | ||
4948 | if (link->dpcd_caps.edp_supported_link_rates_count == 0 || | |
4949 | !link->dc->debug.optimize_edp_link_rate) | |
4950 | return false; | |
4951 | ||
4952 | ||
4953 | // Read DPCD 00100h to find if standard link rates are set | |
4954 | core_link_read_dpcd(link, DP_LINK_BW_SET, | |
4955 | &link_bw_set, sizeof(link_bw_set)); | |
4956 | ||
0eda55ca MS |
4957 | if (link_bw_set) { |
4958 | DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n"); | |
f9fc6f39 | 4959 | return true; |
0eda55ca | 4960 | } |
f9fc6f39 MS |
4961 | |
4962 | // Read DPCD 00115h to find the edp link rate set used | |
4963 | core_link_read_dpcd(link, DP_LINK_RATE_SET, | |
4964 | &link_rate_set, sizeof(link_rate_set)); | |
4965 | ||
4966 | // Read DPCD 00101h to find out the number of lanes currently set | |
4967 | core_link_read_dpcd(link, DP_LANE_COUNT_SET, | |
4968 | &lane_count_set.raw, sizeof(lane_count_set)); | |
4969 | ||
4970 | req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing); | |
4971 | ||
4972 | decide_edp_link_settings(link, &link_setting, req_bw); | |
4973 | ||
4974 | if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate || | |
0eda55ca MS |
4975 | lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) { |
4976 | DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n"); | |
f9fc6f39 | 4977 | return true; |
0eda55ca | 4978 | } |
f9fc6f39 | 4979 | |
0eda55ca | 4980 | DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n"); |
f9fc6f39 MS |
4981 | return false; |
4982 | } | |
4983 | ||
55bac4a7 WL |
4984 | enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings) |
4985 | { | |
4986 | if ((link_settings->link_rate >= LINK_RATE_LOW) && | |
4987 | (link_settings->link_rate <= LINK_RATE_HIGH3)) | |
4988 | return DP_8b_10b_ENCODING; | |
4989 | return DP_UNKNOWN_ENCODING; | |
4990 | } | |
f9fc6f39 | 4991 |