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drm/amd/display: Improve logic for is_lttpr_present
[linux-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
CommitLineData
4562236b
HW		 1/* Copyright 2015 Advanced Micro Devices, Inc. */
2#include "dm_services.h"
3#include "dc.h"
4#include "dc_link_dp.h"
5#include "dm_helpers.h"
7f93c1de 6#include "opp.h"
97bda032 7#include "dsc.h"
6fbefb84 8#include "resource.h"
4562236b
HW		 9
10#include "inc/core_types.h"
11#include "link_hwss.h"
12#include "dc_link_ddc.h"
13#include "core_status.h"
14#include "dpcd_defs.h"
dc6e2448
WW		 15#include "dc_dmub_srv.h"
16#include "dce/dmub_hw_lock_mgr.h"
ede4f6da 17#include "inc/link_enc_cfg.h"
4562236b 18
8dfcb24e
LJ		 19/*Travis*/
20static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
21/*Nutmeg*/
22static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
23
1296423b
BL		 24#define DC_LOGGER \
25 link->ctx->logger
9248681f 26#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
8e5100a5 27
9248681f
AT		 28 /* maximum pre emphasis level allowed for each voltage swing level*/
29 static const enum dc_pre_emphasis
30 voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
31 PRE_EMPHASIS_LEVEL2,
32 PRE_EMPHASIS_LEVEL1,
33 PRE_EMPHASIS_DISABLED };
4562236b
HW		 34
35enum {
36 POST_LT_ADJ_REQ_LIMIT = 6,
37 POST_LT_ADJ_REQ_TIMEOUT = 200
38};
39
04e21292
DA		 40static bool decide_fallback_link_setting(
41 struct dc_link_settings initial_link_settings,
42 struct dc_link_settings *current_link_setting,
43 enum link_training_result training_result);
9a6a8075 44static struct dc_link_settings get_common_supported_link_settings(
04e21292
DA		 45 struct dc_link_settings link_setting_a,
46 struct dc_link_settings link_setting_b);
47
b50d5551
WL		 48static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
49 const struct dc_link_settings *link_settings)
50{
51 union training_aux_rd_interval training_rd_interval;
52 uint32_t wait_in_micro_secs = 100;
53
54 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
55 core_link_read_dpcd(
56 link,
57 DP_TRAINING_AUX_RD_INTERVAL,
58 (uint8_t *)&training_rd_interval,
59 sizeof(training_rd_interval));
60 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
61 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
62 return wait_in_micro_secs;
63}
64
3fb068c3 65static uint32_t get_eq_training_aux_rd_interval(
d0778ebf 66 struct dc_link *link,
3fb068c3 67 const struct dc_link_settings *link_settings)
4562236b 68{
d6d36b55 69 union training_aux_rd_interval training_rd_interval;
3fb068c3 70 uint32_t wait_in_micro_secs = 400;
d6d36b55
NC		 71
72 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
4562236b
HW		 73 /* overwrite the delay if rev > 1.1*/
74 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
75 /* DP 1.2 or later - retrieve delay through
76 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
77 core_link_read_dpcd(
78 link,
3a340294 79 DP_TRAINING_AUX_RD_INTERVAL,
4562236b
HW		 80 (uint8_t *)&training_rd_interval,
81 sizeof(training_rd_interval));
82
83 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
3fb068c3 84 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
4562236b
HW		 85 }
86
3fb068c3 87 return wait_in_micro_secs;
e0a6440a
DG		 88}
89
e84ecdc5 90void dp_wait_for_training_aux_rd_interval(
e0a6440a
DG		 91 struct dc_link *link,
92 uint32_t wait_in_micro_secs)
93{
94 udelay(wait_in_micro_secs);
4562236b 95
1296423b 96 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
4562236b 97 __func__,
e0a6440a 98 wait_in_micro_secs);
4562236b
HW		 99}
100
e84ecdc5 101enum dpcd_training_patterns
ebc22cbd
WL		 102 dc_dp_training_pattern_to_dpcd_training_pattern(
103 struct dc_link *link,
104 enum dc_dp_training_pattern pattern)
105{
106 enum dpcd_training_patterns dpcd_tr_pattern =
107 DPCD_TRAINING_PATTERN_VIDEOIDLE;
108
109 switch (pattern) {
110 case DP_TRAINING_PATTERN_SEQUENCE_1:
111 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
112 break;
113 case DP_TRAINING_PATTERN_SEQUENCE_2:
114 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
115 break;
116 case DP_TRAINING_PATTERN_SEQUENCE_3:
117 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
118 break;
119 case DP_TRAINING_PATTERN_SEQUENCE_4:
120 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
121 break;
122 case DP_TRAINING_PATTERN_VIDEOIDLE:
123 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
124 break;
125 default:
126 ASSERT(0);
127 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
128 __func__, pattern);
129 break;
130 }
131
132 return dpcd_tr_pattern;
133}
134
4562236b 135static void dpcd_set_training_pattern(
d0778ebf 136 struct dc_link *link,
ebc22cbd 137 enum dc_dp_training_pattern training_pattern)
4562236b 138{
ebc22cbd
WL		 139 union dpcd_training_pattern dpcd_pattern = { {0} };
140
141 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
142 dc_dp_training_pattern_to_dpcd_training_pattern(
143 link, training_pattern);
144
4562236b
HW		 145 core_link_write_dpcd(
146 link,
3a340294 147 DP_TRAINING_PATTERN_SET,
4562236b
HW		 148 &dpcd_pattern.raw,
149 1);
150
1296423b 151 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
4562236b 152 __func__,
3a340294 153 DP_TRAINING_PATTERN_SET,
4562236b
HW		 154 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
155}
156
ce17ce17
WL		 157static enum dc_dp_training_pattern decide_cr_training_pattern(
158 const struct dc_link_settings *link_settings)
159{
4b1d6831 160 return DP_TRAINING_PATTERN_SEQUENCE_1;
ce17ce17
WL		 161}
162
163static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
164 const struct dc_link_settings *link_settings)
16b6253a 165{
ede4f6da 166 struct link_encoder *link_enc;
e0a6440a 167 enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
ede4f6da 168 struct encoder_feature_support *features;
16b6253a 169 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
170
ede4f6da
JK		 171 /* Access link encoder capability based on whether it is statically
172 * or dynamically assigned to a link.
173 */
174 if (link->is_dig_mapping_flexible &&
175 link->dc->res_pool->funcs->link_encs_assign)
176 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
177 else
178 link_enc = link->link_enc;
179 ASSERT(link_enc);
180 features = &link_enc->features;
181
16b6253a 182 if (features->flags.bits.IS_TPS3_CAPABLE)
e0a6440a 183 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
16b6253a 184
185 if (features->flags.bits.IS_TPS4_CAPABLE)
e0a6440a 186 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
16b6253a 187
188 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
e0a6440a
DG		 189 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
190 return DP_TRAINING_PATTERN_SEQUENCE_4;
16b6253a 191
192 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
e0a6440a
DG		 193 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
194 return DP_TRAINING_PATTERN_SEQUENCE_3;
16b6253a 195
e0a6440a 196 return DP_TRAINING_PATTERN_SEQUENCE_2;
16b6253a 197}
198
7211b605 199enum dc_status dpcd_set_link_settings(
d0778ebf 200 struct dc_link *link,
4562236b
HW		 201 const struct link_training_settings *lt_settings)
202{
8628d02f 203 uint8_t rate;
7211b605 204 enum dc_status status;
4562236b 205
9a6a8075
HW		 206 union down_spread_ctrl downspread = { {0} };
207 union lane_count_set lane_count_set = { {0} };
4562236b
HW		 208
209 downspread.raw = (uint8_t)
210 (lt_settings->link_settings.link_spread);
211
212 lane_count_set.bits.LANE_COUNT_SET =
213 lt_settings->link_settings.lane_count;
214
e0a6440a 215 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
16b6253a 216 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
217
e0a6440a 218
7211b605
JK		 219 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
220 lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
16b6253a 221 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
222 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
223 }
4562236b 224
7211b605 225 status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
e0a6440a 226 &downspread.raw, sizeof(downspread));
4562236b 227
7211b605 228 status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
e0a6440a 229 &lane_count_set.raw, 1);
8628d02f 230
b03a599b 231 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
8628d02f
JP		 232 lt_settings->link_settings.use_link_rate_set == true) {
233 rate = 0;
8edb9456
DZ		 234 /* WA for some MUX chips that will power down with eDP and lose supported
235 * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
236 * MUX chip gets link rate set back before link training.
237 */
238 if (link->connector_signal == SIGNAL_TYPE_EDP) {
239 uint8_t supported_link_rates[16];
240
241 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
242 supported_link_rates, sizeof(supported_link_rates));
243 }
7211b605
JK		 244 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
245 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
8628d02f
JP		 246 &lt_settings->link_settings.link_rate_set, 1);
247 } else {
248 rate = (uint8_t) (lt_settings->link_settings.link_rate);
7211b605 249 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
b03a599b
DL		 250 }
251
8628d02f 252 if (rate) {
e0a6440a 253 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
8628d02f
JP		 254 __func__,
255 DP_LINK_BW_SET,
256 lt_settings->link_settings.link_rate,
257 DP_LANE_COUNT_SET,
258 lt_settings->link_settings.lane_count,
e0a6440a 259 lt_settings->enhanced_framing,
8628d02f
JP		 260 DP_DOWNSPREAD_CTRL,
261 lt_settings->link_settings.link_spread);
262 } else {
e0a6440a 263 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
8628d02f
JP		 264 __func__,
265 DP_LINK_RATE_SET,
266 lt_settings->link_settings.link_rate_set,
267 DP_LANE_COUNT_SET,
268 lt_settings->link_settings.lane_count,
e0a6440a 269 lt_settings->enhanced_framing,
8628d02f
JP		 270 DP_DOWNSPREAD_CTRL,
271 lt_settings->link_settings.link_spread);
272 }
7211b605
JK		 273
274 return status;
4562236b
HW		 275}
276
e84ecdc5 277uint8_t dc_dp_initialize_scrambling_data_symbols(
7d1ee78f
VS		 278 struct dc_link *link,
279 enum dc_dp_training_pattern pattern)
280{
281 uint8_t disable_scrabled_data_symbols = 0;
282
283 switch (pattern) {
284 case DP_TRAINING_PATTERN_SEQUENCE_1:
285 case DP_TRAINING_PATTERN_SEQUENCE_2:
286 case DP_TRAINING_PATTERN_SEQUENCE_3:
287 disable_scrabled_data_symbols = 1;
288 break;
289 case DP_TRAINING_PATTERN_SEQUENCE_4:
290 disable_scrabled_data_symbols = 0;
291 break;
292 default:
293 ASSERT(0);
294 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
295 __func__, pattern);
296 break;
297 }
298 return disable_scrabled_data_symbols;
299}
300
64c12b73 301static inline bool is_repeater(struct dc_link *link, uint32_t offset)
302{
3128b285 303 return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
64c12b73 304}
305
4562236b 306static void dpcd_set_lt_pattern_and_lane_settings(
d0778ebf 307 struct dc_link *link,
4562236b 308 const struct link_training_settings *lt_settings,
64c12b73 309 enum dc_dp_training_pattern pattern,
310 uint32_t offset)
4562236b 311{
9a6a8075 312 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
64c12b73 313
314 uint32_t dpcd_base_lt_offset;
315
4562236b 316 uint8_t dpcd_lt_buffer[5] = {0};
9a6a8075 317 union dpcd_training_pattern dpcd_pattern = { {0} };
4562236b
HW		 318 uint32_t lane;
319 uint32_t size_in_bytes;
320 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
64c12b73 321 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
322
323 if (is_repeater(link, offset))
324 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
325 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b
HW		 326
327 /*****************************************************************
328 * DpcdAddress_TrainingPatternSet
329 *****************************************************************/
330 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
e0a6440a 331 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
4562236b 332
7d1ee78f
VS		 333 dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
334 dc_dp_initialize_scrambling_data_symbols(link, pattern);
335
64c12b73 336 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
4562236b
HW		 337 = dpcd_pattern.raw;
338
460adc6b 339 if (is_repeater(link, offset)) {
340 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
341 __func__,
342 offset,
343 dpcd_base_lt_offset,
344 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
345 } else {
346 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
347 __func__,
348 dpcd_base_lt_offset,
349 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
350 }
4562236b
HW		 351 /*****************************************************************
352 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
353 *****************************************************************/
354 for (lane = 0; lane <
355 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
356
357 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
358 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
359 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
360 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
361
362 dpcd_lane[lane].bits.MAX_SWING_REACHED =
363 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
364 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
365 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
366 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
367 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
368 }
369
64c12b73 370 /* concatenate everything into one buffer*/
4562236b
HW		 371
372 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
373
374 // 0x00103 - 0x00102
375 memmove(
64c12b73 376 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
4562236b
HW		 377 dpcd_lane,
378 size_in_bytes);
379
460adc6b 380 if (is_repeater(link, offset)) {
381 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
382 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
383 __func__,
384 offset,
385 dpcd_base_lt_offset,
386 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
387 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
388 dpcd_lane[0].bits.MAX_SWING_REACHED,
389 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
390 } else {
391 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
392 __func__,
393 dpcd_base_lt_offset,
394 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
395 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
396 dpcd_lane[0].bits.MAX_SWING_REACHED,
397 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
398 }
4562236b
HW		 399 if (edp_workaround) {
400 /* for eDP write in 2 parts because the 5-byte burst is
401 * causing issues on some eDP panels (EPR#366724)
402 */
403 core_link_write_dpcd(
404 link,
3a340294 405 DP_TRAINING_PATTERN_SET,
4562236b 406 &dpcd_pattern.raw,
9a6a8075 407 sizeof(dpcd_pattern.raw));
4562236b
HW		 408
409 core_link_write_dpcd(
410 link,
3a340294 411 DP_TRAINING_LANE0_SET,
4562236b
HW		 412 (uint8_t *)(dpcd_lane),
413 size_in_bytes);
414
415 } else
416 /* write it all in (1 + number-of-lanes)-byte burst*/
417 core_link_write_dpcd(
418 link,
419 dpcd_base_lt_offset,
420 dpcd_lt_buffer,
9a6a8075 421 size_in_bytes + sizeof(dpcd_pattern.raw));
4562236b 422
d0778ebf 423 link->cur_lane_setting = lt_settings->lane_settings[0];
4562236b
HW		 424}
425
e84ecdc5 426bool dp_is_cr_done(enum dc_lane_count ln_count,
4562236b
HW		 427 union lane_status *dpcd_lane_status)
428{
4562236b
HW		 429 uint32_t lane;
430 /*LANEx_CR_DONE bits All 1's?*/
431 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
432 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
d56b83f7 433 return false;
4562236b 434 }
d56b83f7 435 return true;
4562236b
HW		 436}
437
0cb15885 438bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
ebc22cbd 439 union lane_status *dpcd_lane_status)
4562236b 440{
ebc22cbd 441 bool done = true;
4562236b 442 uint32_t lane;
ebc22cbd
WL		 443 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
444 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
445 done = false;
446 return done;
447}
448
0cb15885 449bool dp_is_symbol_locked(enum dc_lane_count ln_count,
ebc22cbd
WL		 450 union lane_status *dpcd_lane_status)
451{
452 bool locked = true;
453 uint32_t lane;
454 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
455 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
456 locked = false;
457 return locked;
458}
459
0cb15885 460bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
ebc22cbd
WL		 461{
462 return align_status.bits.INTERLANE_ALIGN_DONE == 1;
4562236b
HW		 463}
464
e84ecdc5 465void dp_update_drive_settings(
4562236b
HW		 466 struct link_training_settings *dest,
467 struct link_training_settings src)
468{
469 uint32_t lane;
470 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
e0a6440a
DG		 471 if (dest->voltage_swing == NULL)
472 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
473 else
474 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
475
476 if (dest->pre_emphasis == NULL)
477 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
478 else
479 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
480
481 if (dest->post_cursor2 == NULL)
482 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
483 else
484 dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
4562236b
HW		 485 }
486}
487
488static uint8_t get_nibble_at_index(const uint8_t *buf,
489 uint32_t index)
490{
491 uint8_t nibble;
492 nibble = buf[index / 2];
493
494 if (index % 2)
495 nibble >>= 4;
496 else
497 nibble &= 0x0F;
498
499 return nibble;
500}
501
502static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
503 enum dc_voltage_swing voltage)
504{
505 enum dc_pre_emphasis pre_emphasis;
506 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
507
508 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
509 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
510
511 return pre_emphasis;
512
513}
514
515static void find_max_drive_settings(
516 const struct link_training_settings *link_training_setting,
517 struct link_training_settings *max_lt_setting)
518{
519 uint32_t lane;
520 struct dc_lane_settings max_requested;
521
522 max_requested.VOLTAGE_SWING =
523 link_training_setting->
524 lane_settings[0].VOLTAGE_SWING;
525 max_requested.PRE_EMPHASIS =
526 link_training_setting->
527 lane_settings[0].PRE_EMPHASIS;
528 /*max_requested.postCursor2 =
529 * link_training_setting->laneSettings[0].postCursor2;*/
530
531 /* Determine what the maximum of the requested settings are*/
532 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
533 lane++) {
534 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
535 max_requested.VOLTAGE_SWING)
536
537 max_requested.VOLTAGE_SWING =
538 link_training_setting->
539 lane_settings[lane].VOLTAGE_SWING;
540
541 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
542 max_requested.PRE_EMPHASIS)
543 max_requested.PRE_EMPHASIS =
544 link_training_setting->
545 lane_settings[lane].PRE_EMPHASIS;
546
547 /*
548 if (link_training_setting->laneSettings[lane].postCursor2 >
549 max_requested.postCursor2)
550 {
551 max_requested.postCursor2 =
552 link_training_setting->laneSettings[lane].postCursor2;
553 }
554 */
555 }
556
557 /* make sure the requested settings are
558 * not higher than maximum settings*/
559 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
560 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
561
562 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
563 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
564 /*
565 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
566 max_requested.postCursor2 = PostCursor2_MaxLevel;
567 */
568
569 /* make sure the pre-emphasis matches the voltage swing*/
570 if (max_requested.PRE_EMPHASIS >
571 get_max_pre_emphasis_for_voltage_swing(
572 max_requested.VOLTAGE_SWING))
573 max_requested.PRE_EMPHASIS =
574 get_max_pre_emphasis_for_voltage_swing(
575 max_requested.VOLTAGE_SWING);
576
577 /*
578 * Post Cursor2 levels are completely independent from
579 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
580 * can only be applied to each allowable combination of voltage
581 * swing and pre-emphasis levels */
582 /* if ( max_requested.postCursor2 >
583 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
584 * max_requested.postCursor2 =
585 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
586 */
587
588 max_lt_setting->link_settings.link_rate =
589 link_training_setting->link_settings.link_rate;
590 max_lt_setting->link_settings.lane_count =
591 link_training_setting->link_settings.lane_count;
592 max_lt_setting->link_settings.link_spread =
593 link_training_setting->link_settings.link_spread;
594
595 for (lane = 0; lane <
596 link_training_setting->link_settings.lane_count;
597 lane++) {
598 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
599 max_requested.VOLTAGE_SWING;
600 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
601 max_requested.PRE_EMPHASIS;
602 /*max_lt_setting->laneSettings[lane].postCursor2 =
603 * max_requested.postCursor2;
604 */
605 }
606
607}
608
e84ecdc5 609enum dc_status dp_get_lane_status_and_drive_settings(
d0778ebf 610 struct dc_link *link,
4562236b
HW		 611 const struct link_training_settings *link_training_setting,
612 union lane_status *ln_status,
613 union lane_align_status_updated *ln_status_updated,
64c12b73 614 struct link_training_settings *req_settings,
615 uint32_t offset)
4562236b 616{
64c12b73 617 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
618 uint8_t lane_adjust_offset = 4;
619 unsigned int lane01_adjust_address;
4562236b 620 uint8_t dpcd_buf[6] = {0};
9a6a8075
HW		 621 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
622 struct link_training_settings request_settings = { {0} };
4562236b 623 uint32_t lane;
e84ecdc5 624 enum dc_status status;
4562236b
HW		 625
626 memset(req_settings, '\0', sizeof(struct link_training_settings));
627
64c12b73 628 if (is_repeater(link, offset)) {
629 lane01_status_address =
630 DP_LANE0_1_STATUS_PHY_REPEATER1 +
631 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
632 lane_adjust_offset = 3;
633 }
634
e84ecdc5 635 status = core_link_read_dpcd(
4562236b 636 link,
64c12b73 637 lane01_status_address,
4562236b
HW		 638 (uint8_t *)(dpcd_buf),
639 sizeof(dpcd_buf));
640
641 for (lane = 0; lane <
642 (uint32_t)(link_training_setting->link_settings.lane_count);
643 lane++) {
644
645 ln_status[lane].raw =
646 get_nibble_at_index(&dpcd_buf[0], lane);
647 dpcd_lane_adjust[lane].raw =
64c12b73 648 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
4562236b
HW		 649 }
650
651 ln_status_updated->raw = dpcd_buf[2];
652
460adc6b 653 if (is_repeater(link, offset)) {
654 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
655 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
656 __func__,
657 offset,
658 lane01_status_address, dpcd_buf[0],
659 lane01_status_address + 1, dpcd_buf[1]);
660 } else {
661 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
662 __func__,
663 lane01_status_address, dpcd_buf[0],
664 lane01_status_address + 1, dpcd_buf[1]);
665 }
64c12b73 666 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
667
668 if (is_repeater(link, offset))
669 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
670 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b 671
460adc6b 672 if (is_repeater(link, offset)) {
673 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
674 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
675 __func__,
676 offset,
677 lane01_adjust_address,
678 dpcd_buf[lane_adjust_offset],
679 lane01_adjust_address + 1,
680 dpcd_buf[lane_adjust_offset + 1]);
681 } else {
682 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
683 __func__,
684 lane01_adjust_address,
685 dpcd_buf[lane_adjust_offset],
686 lane01_adjust_address + 1,
687 dpcd_buf[lane_adjust_offset + 1]);
688 }
4562236b
HW		 689
690 /*copy to req_settings*/
691 request_settings.link_settings.lane_count =
692 link_training_setting->link_settings.lane_count;
693 request_settings.link_settings.link_rate =
694 link_training_setting->link_settings.link_rate;
695 request_settings.link_settings.link_spread =
696 link_training_setting->link_settings.link_spread;
697
698 for (lane = 0; lane <
699 (uint32_t)(link_training_setting->link_settings.lane_count);
700 lane++) {
701
702 request_settings.lane_settings[lane].VOLTAGE_SWING =
703 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
704 VOLTAGE_SWING_LANE);
705 request_settings.lane_settings[lane].PRE_EMPHASIS =
706 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
707 PRE_EMPHASIS_LANE);
708 }
709
710 /*Note: for postcursor2, read adjusted
711 * postcursor2 settings from*/
712 /*DpcdAddress_AdjustRequestPostCursor2 =
713 *0x020C (not implemented yet)*/
714
715 /* we find the maximum of the requested settings across all lanes*/
716 /* and set this maximum for all lanes*/
717 find_max_drive_settings(&request_settings, req_settings);
718
719 /* if post cursor 2 is needed in the future,
720 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
721 */
722
e84ecdc5 723 return status;
4562236b
HW		 724}
725
e84ecdc5 726enum dc_status dpcd_set_lane_settings(
d0778ebf 727 struct dc_link *link,
64c12b73 728 const struct link_training_settings *link_training_setting,
729 uint32_t offset)
4562236b
HW		 730{
731 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
732 uint32_t lane;
64c12b73 733 unsigned int lane0_set_address;
e84ecdc5 734 enum dc_status status;
64c12b73 735
736 lane0_set_address = DP_TRAINING_LANE0_SET;
737
738 if (is_repeater(link, offset))
739 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
740 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b
HW		 741
742 for (lane = 0; lane <
743 (uint32_t)(link_training_setting->
744 link_settings.lane_count);
745 lane++) {
746 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
747 (uint8_t)(link_training_setting->
748 lane_settings[lane].VOLTAGE_SWING);
749 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
750 (uint8_t)(link_training_setting->
751 lane_settings[lane].PRE_EMPHASIS);
752 dpcd_lane[lane].bits.MAX_SWING_REACHED =
753 (link_training_setting->
754 lane_settings[lane].VOLTAGE_SWING ==
755 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
756 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
757 (link_training_setting->
758 lane_settings[lane].PRE_EMPHASIS ==
759 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
760 }
761
e84ecdc5 762 status = core_link_write_dpcd(link,
64c12b73 763 lane0_set_address,
4562236b
HW		 764 (uint8_t *)(dpcd_lane),
765 link_training_setting->link_settings.lane_count);
766
767 /*
768 if (LTSettings.link.rate == LinkRate_High2)
769 {
770 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
771 for ( uint32_t lane = 0;
772 lane < lane_count_DPMax; lane++)
773 {
774 dpcd_lane2[lane].bits.post_cursor2_set =
775 static_cast<unsigned char>(
776 LTSettings.laneSettings[lane].postCursor2);
777 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
778 }
779 m_pDpcdAccessSrv->WriteDpcdData(
780 DpcdAddress_Lane0Set2,
781 reinterpret_cast<unsigned char*>(dpcd_lane2),
782 LTSettings.link.lanes);
783 }
784 */
785
460adc6b 786 if (is_repeater(link, offset)) {
787 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
788 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
789 __func__,
790 offset,
791 lane0_set_address,
792 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
793 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
794 dpcd_lane[0].bits.MAX_SWING_REACHED,
795 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
4562236b 796
460adc6b 797 } else {
798 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
799 __func__,
800 lane0_set_address,
801 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
802 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
803 dpcd_lane[0].bits.MAX_SWING_REACHED,
804 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
805 }
d0778ebf 806 link->cur_lane_setting = link_training_setting->lane_settings[0];
4562236b 807
e84ecdc5 808 return status;
4562236b
HW		 809}
810
e84ecdc5 811bool dp_is_max_vs_reached(
4562236b
HW		 812 const struct link_training_settings *lt_settings)
813{
814 uint32_t lane;
815 for (lane = 0; lane <
816 (uint32_t)(lt_settings->link_settings.lane_count);
817 lane++) {
818 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
819 == VOLTAGE_SWING_MAX_LEVEL)
820 return true;
821 }
822 return false;
823
824}
825
4562236b 826static bool perform_post_lt_adj_req_sequence(
d0778ebf 827 struct dc_link *link,
4562236b
HW		 828 struct link_training_settings *lt_settings)
829{
830 enum dc_lane_count lane_count =
831 lt_settings->link_settings.lane_count;
832
833 uint32_t adj_req_count;
834 uint32_t adj_req_timer;
835 bool req_drv_setting_changed;
836 uint32_t lane;
837
838 req_drv_setting_changed = false;
839 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
840 adj_req_count++) {
841
842 req_drv_setting_changed = false;
843
844 for (adj_req_timer = 0;
845 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
846 adj_req_timer++) {
847
848 struct link_training_settings req_settings;
849 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
850 union lane_align_status_updated
851 dpcd_lane_status_updated;
852
e84ecdc5
JK		 853 dp_get_lane_status_and_drive_settings(
854 link,
855 lt_settings,
856 dpcd_lane_status,
857 &dpcd_lane_status_updated,
858 &req_settings,
859 DPRX);
4562236b
HW		 860
861 if (dpcd_lane_status_updated.bits.
862 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
863 return true;
864
e84ecdc5 865 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
4562236b
HW		 866 return false;
867
0cb15885
JK		 868 if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
869 !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
870 !dp_is_interlane_aligned(dpcd_lane_status_updated))
4562236b
HW		 871 return false;
872
873 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
874
875 if (lt_settings->
876 lane_settings[lane].VOLTAGE_SWING !=
877 req_settings.lane_settings[lane].
878 VOLTAGE_SWING ||
879 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
880 req_settings.lane_settings[lane].PRE_EMPHASIS) {
881
882 req_drv_setting_changed = true;
883 break;
884 }
885 }
886
887 if (req_drv_setting_changed) {
e84ecdc5 888 dp_update_drive_settings(
9a6a8075 889 lt_settings, req_settings);
4562236b 890
d0778ebf 891 dc_link_dp_set_drive_settings(link,
4562236b
HW		 892 lt_settings);
893 break;
894 }
895
896 msleep(1);
897 }
898
899 if (!req_drv_setting_changed) {
1296423b 900 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
4562236b
HW		 901 __func__);
902
903 ASSERT(0);
904 return true;
905 }
906 }
1296423b 907 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
4562236b
HW		 908 __func__);
909
910 ASSERT(0);
911 return true;
912
913}
914
64c12b73 915/* Only used for channel equalization */
0cb15885 916uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
64c12b73 917{
918 unsigned int aux_rd_interval_us = 400;
919
920 switch (dpcd_aux_read_interval) {
921 case 0x01:
a71c76ac 922 aux_rd_interval_us = 4000;
64c12b73 923 break;
924 case 0x02:
a71c76ac 925 aux_rd_interval_us = 8000;
64c12b73 926 break;
927 case 0x03:
a71c76ac 928 aux_rd_interval_us = 12000;
64c12b73 929 break;
930 case 0x04:
931 aux_rd_interval_us = 16000;
932 break;
933 default:
934 break;
935 }
936
937 return aux_rd_interval_us;
938}
939
e84ecdc5 940enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
94405cf6
WL		 941 union lane_status *dpcd_lane_status)
942{
943 enum link_training_result result = LINK_TRAINING_SUCCESS;
944
945 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
946 result = LINK_TRAINING_CR_FAIL_LANE0;
947 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
948 result = LINK_TRAINING_CR_FAIL_LANE1;
949 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
950 result = LINK_TRAINING_CR_FAIL_LANE23;
951 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
952 result = LINK_TRAINING_CR_FAIL_LANE23;
953 return result;
954}
955
820e3935 956static enum link_training_result perform_channel_equalization_sequence(
d0778ebf 957 struct dc_link *link,
64c12b73 958 struct link_training_settings *lt_settings,
959 uint32_t offset)
4562236b
HW		 960{
961 struct link_training_settings req_settings;
e0a6440a 962 enum dc_dp_training_pattern tr_pattern;
4562236b 963 uint32_t retries_ch_eq;
64c12b73 964 uint32_t wait_time_microsec;
4562236b 965 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
9a6a8075
HW		 966 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
967 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
4562236b 968
64c12b73 969 /* Note: also check that TPS4 is a supported feature*/
970
e0a6440a 971 tr_pattern = lt_settings->pattern_for_eq;
4562236b 972
64c12b73 973 if (is_repeater(link, offset))
974 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
975
976 dp_set_hw_training_pattern(link, tr_pattern, offset);
4562236b
HW		 977
978 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
979 retries_ch_eq++) {
980
64c12b73 981 dp_set_hw_lane_settings(link, lt_settings, offset);
4562236b
HW		 982
983 /* 2. update DPCD*/
984 if (!retries_ch_eq)
985 /* EPR #361076 - write as a 5-byte burst,
64c12b73 986 * but only for the 1-st iteration
987 */
988
4562236b
HW		 989 dpcd_set_lt_pattern_and_lane_settings(
990 link,
991 lt_settings,
64c12b73 992 tr_pattern, offset);
4562236b 993 else
64c12b73 994 dpcd_set_lane_settings(link, lt_settings, offset);
4562236b
HW		 995
996 /* 3. wait for receiver to lock-on*/
64c12b73 997 wait_time_microsec = lt_settings->eq_pattern_time;
998
5fd21b39 999 if (is_repeater(link, offset))
64c12b73 1000 wait_time_microsec =
0cb15885 1001 dp_translate_training_aux_read_interval(
5fd21b39 1002 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
64c12b73 1003
e84ecdc5 1004 dp_wait_for_training_aux_rd_interval(
64c12b73 1005 link,
1006 wait_time_microsec);
4562236b
HW		 1007
1008 /* 4. Read lane status and requested
1009 * drive settings as set by the sink*/
1010
e84ecdc5 1011 dp_get_lane_status_and_drive_settings(
4562236b
HW		 1012 link,
1013 lt_settings,
1014 dpcd_lane_status,
1015 &dpcd_lane_status_updated,
64c12b73 1016 &req_settings,
1017 offset);
4562236b
HW		 1018
1019 /* 5. check CR done*/
e84ecdc5 1020 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
820e3935 1021 return LINK_TRAINING_EQ_FAIL_CR;
4562236b
HW		 1022
1023 /* 6. check CHEQ done*/
0cb15885
JK		 1024 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
1025 dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
1026 dp_is_interlane_aligned(dpcd_lane_status_updated))
820e3935 1027 return LINK_TRAINING_SUCCESS;
4562236b
HW		 1028
1029 /* 7. update VS/PE/PC2 in lt_settings*/
e84ecdc5 1030 dp_update_drive_settings(lt_settings, req_settings);
4562236b
HW		 1031 }
1032
820e3935 1033 return LINK_TRAINING_EQ_FAIL_EQ;
4562236b
HW		 1034
1035}
1036
b01f22ec
DG		 1037static void start_clock_recovery_pattern_early(struct dc_link *link,
1038 struct link_training_settings *lt_settings,
1039 uint32_t offset)
1040{
1041 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1042 __func__);
ce17ce17 1043 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
b01f22ec
DG		 1044 dp_set_hw_lane_settings(link, lt_settings, offset);
1045 udelay(400);
1046}
1047
94405cf6 1048static enum link_training_result perform_clock_recovery_sequence(
d0778ebf 1049 struct dc_link *link,
64c12b73 1050 struct link_training_settings *lt_settings,
1051 uint32_t offset)
4562236b
HW		 1052{
1053 uint32_t retries_cr;
1054 uint32_t retry_count;
64c12b73 1055 uint32_t wait_time_microsec;
4562236b 1056 struct link_training_settings req_settings;
e0a6440a 1057 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
4562236b
HW		 1058 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1059 union lane_align_status_updated dpcd_lane_status_updated;
1060
1061 retries_cr = 0;
1062 retry_count = 0;
4562236b 1063
82054678 1064 if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
ce17ce17 1065 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
4562236b
HW		 1066
1067 /* najeeb - The synaptics MST hub can put the LT in
1068 * infinite loop by switching the VS
1069 */
1070 /* between level 0 and level 1 continuously, here
1071 * we try for CR lock for LinkTrainingMaxCRRetry count*/
1072 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
e0a6440a 1073 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
4562236b
HW		 1074
1075 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1076 memset(&dpcd_lane_status_updated, '\0',
1077 sizeof(dpcd_lane_status_updated));
1078
1079 /* 1. call HWSS to set lane settings*/
1080 dp_set_hw_lane_settings(
1081 link,
64c12b73 1082 lt_settings,
1083 offset);
4562236b
HW		 1084
1085 /* 2. update DPCD of the receiver*/
50d2c602 1086 if (!retry_count)
4562236b
HW		 1087 /* EPR #361076 - write as a 5-byte burst,
1088 * but only for the 1-st iteration.*/
1089 dpcd_set_lt_pattern_and_lane_settings(
1090 link,
1091 lt_settings,
ce17ce17 1092 lt_settings->pattern_for_cr,
64c12b73 1093 offset);
4562236b
HW		 1094 else
1095 dpcd_set_lane_settings(
1096 link,
64c12b73 1097 lt_settings,
1098 offset);
4562236b
HW		 1099
1100 /* 3. wait receiver to lock-on*/
64c12b73 1101 wait_time_microsec = lt_settings->cr_pattern_time;
1102
3128b285 1103 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
64c12b73 1104 wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1105
e84ecdc5 1106 dp_wait_for_training_aux_rd_interval(
4562236b 1107 link,
64c12b73 1108 wait_time_microsec);
4562236b
HW		 1109
1110 /* 4. Read lane status and requested drive
1111 * settings as set by the sink
1112 */
e84ecdc5 1113 dp_get_lane_status_and_drive_settings(
4562236b
HW		 1114 link,
1115 lt_settings,
1116 dpcd_lane_status,
1117 &dpcd_lane_status_updated,
64c12b73 1118 &req_settings,
1119 offset);
4562236b
HW		 1120
1121 /* 5. check CR done*/
e84ecdc5 1122 if (dp_is_cr_done(lane_count, dpcd_lane_status))
94405cf6 1123 return LINK_TRAINING_SUCCESS;
4562236b
HW		 1124
1125 /* 6. max VS reached*/
e84ecdc5 1126 if (dp_is_max_vs_reached(lt_settings))
94405cf6 1127 break;
4562236b 1128
3d223c55
DG		 1129 /* 7. same lane settings*/
1130 /* Note: settings are the same for all lanes,
1131 * so comparing first lane is sufficient*/
1132 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
4562236b 1133 req_settings.lane_settings[0].VOLTAGE_SWING)
3d223c55
DG		 1134 && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1135 req_settings.lane_settings[0].PRE_EMPHASIS))
4562236b
HW		 1136 retries_cr++;
1137 else
1138 retries_cr = 0;
1139
1140 /* 8. update VS/PE/PC2 in lt_settings*/
e84ecdc5 1141 dp_update_drive_settings(lt_settings, req_settings);
4562236b
HW		 1142
1143 retry_count++;
1144 }
1145
1146 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1147 ASSERT(0);
1296423b 1148 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
4f42a2dd 1149 __func__,
4562236b
HW		 1150 LINK_TRAINING_MAX_CR_RETRY);
1151
1152 }
1153
e84ecdc5 1154 return dp_get_cr_failure(lane_count, dpcd_lane_status);
4562236b
HW		 1155}
1156
37f270c6 1157static inline enum link_training_result dp_transition_to_video_idle(
d0778ebf 1158 struct dc_link *link,
4562236b 1159 struct link_training_settings *lt_settings,
94405cf6 1160 enum link_training_result status)
4562236b
HW		 1161{
1162 union lane_count_set lane_count_set = { {0} };
4562236b
HW		 1163
1164 /* 4. mainlink output idle pattern*/
1165 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1166
1167 /*
1168 * 5. post training adjust if required
1169 * If the upstream DPTX and downstream DPRX both support TPS4,
1170 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1171 */
c30267f5 1172 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
cd6a9a1c
WL		 1173 lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
1174 /* delay 5ms after Main Link output idle pattern and then check
1175 * DPCD 0202h.
1176 */
1177 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1178 msleep(5);
1179 status = dp_check_link_loss_status(link, lt_settings);
1180 }
4562236b 1181 return status;
cd6a9a1c 1182 }
4562236b 1183
94405cf6 1184 if (status == LINK_TRAINING_SUCCESS &&
4562236b 1185 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
94405cf6 1186 status = LINK_TRAINING_LQA_FAIL;
4562236b
HW		 1187
1188 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
e0a6440a 1189 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
4562236b
HW		 1190 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1191
1192 core_link_write_dpcd(
1193 link,
3a340294 1194 DP_LANE_COUNT_SET,
4562236b
HW		 1195 &lane_count_set.raw,
1196 sizeof(lane_count_set));
1197
1198 return status;
1199}
1200
573a0a03 1201enum link_training_result dp_check_link_loss_status(
b246f90a
MT		 1202 struct dc_link *link,
1203 const struct link_training_settings *link_training_setting)
1204{
1205 enum link_training_result status = LINK_TRAINING_SUCCESS;
b246f90a 1206 union lane_status lane_status;
d9b91b1e 1207 uint8_t dpcd_buf[6] = {0};
b246f90a
MT		 1208 uint32_t lane;
1209
1210 core_link_read_dpcd(
d9b91b1e
AC		 1211 link,
1212 DP_SINK_COUNT,
1213 (uint8_t *)(dpcd_buf),
1214 sizeof(dpcd_buf));
b246f90a
MT		 1215
1216 /*parse lane status*/
1217 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1218 /*
1219 * check lanes status
1220 */
d9b91b1e 1221 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
b246f90a
MT		 1222
1223 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1224 !lane_status.bits.CR_DONE_0 ||
1225 !lane_status.bits.SYMBOL_LOCKED_0) {
1226 /* if one of the channel equalization, clock
1227 * recovery or symbol lock is dropped
1228 * consider it as (link has been
1229 * dropped) dp sink status has changed
1230 */
1231 status = LINK_TRAINING_LINK_LOSS;
1232 break;
1233 }
1234 }
1235
1236 return status;
1237}
1238
4c247f8c 1239static inline void decide_8b_10b_training_settings(
e0a6440a 1240 struct dc_link *link,
4562236b 1241 const struct dc_link_settings *link_setting,
0b226322 1242 const struct dc_link_training_overrides *overrides,
e0a6440a 1243 struct link_training_settings *lt_settings)
4562236b 1244{
e0a6440a 1245 uint32_t lane;
4562236b 1246
e0a6440a 1247 memset(lt_settings, '\0', sizeof(struct link_training_settings));
94405cf6 1248
e0a6440a
DG		 1249 /* Initialize link settings */
1250 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1251 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
4562236b 1252
e0a6440a
DG		 1253 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1254 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1255 else
1256 lt_settings->link_settings.link_rate = link_setting->link_rate;
4562236b 1257
e0a6440a
DG		 1258 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1259 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1260 else
1261 lt_settings->link_settings.lane_count = link_setting->lane_count;
4562236b
HW		 1262
1263 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1264
1265 /* TODO hard coded to SS for now
1266 * lt_settings.link_settings.link_spread =
1267 * dal_display_path_is_ss_supported(
1268 * path_mode->display_path) ?
1269 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1270 * LINK_SPREAD_DISABLED;
1271 */
e0a6440a 1272 /* Initialize link spread */
ad830e7a 1273 if (link->dp_ss_off)
e0a6440a 1274 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
0b226322 1275 else if (overrides->downspread != NULL)
e0a6440a 1276 lt_settings->link_settings.link_spread
0b226322 1277 = *overrides->downspread
e0a6440a
DG		 1278 ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1279 : LINK_SPREAD_DISABLED;
ad830e7a 1280 else
e0a6440a 1281 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
4562236b 1282
f1900a9b
WL		 1283 lt_settings->lttpr_mode = link->lttpr_mode;
1284
e0a6440a 1285 /* Initialize lane settings overrides */
0b226322
DG		 1286 if (overrides->voltage_swing != NULL)
1287 lt_settings->voltage_swing = overrides->voltage_swing;
4562236b 1288
0b226322
DG		 1289 if (overrides->pre_emphasis != NULL)
1290 lt_settings->pre_emphasis = overrides->pre_emphasis;
4562236b 1291
0b226322
DG		 1292 if (overrides->post_cursor2 != NULL)
1293 lt_settings->post_cursor2 = overrides->post_cursor2;
e0a6440a
DG		 1294
1295 /* Initialize lane settings (VS/PE/PC2) */
1296 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1297 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1298 lt_settings->voltage_swing != NULL ?
1299 *lt_settings->voltage_swing :
1300 VOLTAGE_SWING_LEVEL0;
1301 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1302 lt_settings->pre_emphasis != NULL ?
1303 *lt_settings->pre_emphasis
1304 : PRE_EMPHASIS_DISABLED;
1305 lt_settings->lane_settings[lane].POST_CURSOR2 =
1306 lt_settings->post_cursor2 != NULL ?
1307 *lt_settings->post_cursor2
1308 : POST_CURSOR2_DISABLED;
820e3935 1309 }
4562236b 1310
e0a6440a 1311 /* Initialize training timings */
0b226322
DG		 1312 if (overrides->cr_pattern_time != NULL)
1313 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
e0a6440a 1314 else
b50d5551 1315 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
e0a6440a 1316
0b226322
DG		 1317 if (overrides->eq_pattern_time != NULL)
1318 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
e0a6440a 1319 else
3fb068c3 1320 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
e0a6440a 1321
ce17ce17
WL		 1322 if (overrides->pattern_for_cr != NULL)
1323 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1324 else
1325 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
0b226322
DG		 1326 if (overrides->pattern_for_eq != NULL)
1327 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
e0a6440a 1328 else
ce17ce17 1329 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
e0a6440a 1330
0b226322
DG		 1331 if (overrides->enhanced_framing != NULL)
1332 lt_settings->enhanced_framing = *overrides->enhanced_framing;
e0a6440a
DG		 1333 else
1334 lt_settings->enhanced_framing = 1;
3df21257
WL		 1335
1336 if (link->preferred_training_settings.fec_enable != NULL)
1337 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
1338 else
1339 lt_settings->should_set_fec_ready = true;
e0a6440a
DG		 1340}
1341
7211b605 1342void dp_decide_training_settings(
4c247f8c
WL		 1343 struct dc_link *link,
1344 const struct dc_link_settings *link_settings,
1345 const struct dc_link_training_overrides *overrides,
1346 struct link_training_settings *lt_settings)
1347{
1348 if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1349 decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings);
1350}
1351
1352
573a0a03 1353uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
64c12b73 1354{
1355 switch (lttpr_repeater_count) {
1356 case 0x80: // 1 lttpr repeater
1357 return 1;
1358 case 0x40: // 2 lttpr repeaters
1359 return 2;
1360 case 0x20: // 3 lttpr repeaters
1361 return 3;
1362 case 0x10: // 4 lttpr repeaters
1363 return 4;
1364 case 0x08: // 5 lttpr repeaters
1365 return 5;
1366 case 0x04: // 6 lttpr repeaters
1367 return 6;
1368 case 0x02: // 7 lttpr repeaters
1369 return 7;
1370 case 0x01: // 8 lttpr repeaters
1371 return 8;
1372 default:
1373 break;
1374 }
1375 return 0; // invalid value
1376}
1377
7211b605 1378enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
3128b285
WC		 1379{
1380 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1381
f1900a9b 1382 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
7211b605 1383 return core_link_write_dpcd(link,
3128b285
WC		 1384 DP_PHY_REPEATER_MODE,
1385 (uint8_t *)&repeater_mode,
1386 sizeof(repeater_mode));
1387}
1388
7211b605 1389enum dc_status configure_lttpr_mode_non_transparent(
f1900a9b
WL		 1390 struct dc_link *link,
1391 const struct link_training_settings *lt_settings)
bad7ab0b 1392{
1393 /* aux timeout is already set to extended */
1394 /* RESET/SET lttpr mode to enable non transparent mode */
64c12b73 1395 uint8_t repeater_cnt;
1396 uint32_t aux_interval_address;
1397 uint8_t repeater_id;
a166f86e 1398 enum dc_status result = DC_ERROR_UNEXPECTED;
61aa7a6f 1399 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
bad7ab0b 1400
f1900a9b
WL		 1401 enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);
1402
1403 if (encoding == DP_8b_10b_ENCODING) {
1404 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1405 result = core_link_write_dpcd(link,
1406 DP_PHY_REPEATER_MODE,
1407 (uint8_t *)&repeater_mode,
1408 sizeof(repeater_mode));
1409
1410 }
bad7ab0b 1411
a166f86e 1412 if (result == DC_OK) {
1413 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1414 }
1415
3128b285 1416 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
460adc6b 1417
c14f2507 1418 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
460adc6b 1419
61aa7a6f 1420 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
a166f86e 1421 result = core_link_write_dpcd(link,
bad7ab0b 1422 DP_PHY_REPEATER_MODE,
1423 (uint8_t *)&repeater_mode,
1424 sizeof(repeater_mode));
64c12b73 1425
a166f86e 1426 if (result == DC_OK) {
1427 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1428 }
1429
f1900a9b
WL		 1430 if (encoding == DP_8b_10b_ENCODING) {
1431 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1432 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1433 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1434 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1435 core_link_read_dpcd(
1436 link,
1437 aux_interval_address,
1438 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1439 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1440 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1441 }
64c12b73 1442 }
bad7ab0b 1443 }
7211b605
JK		 1444
1445 return result;
bad7ab0b 1446}
1447
64c12b73 1448static void repeater_training_done(struct dc_link *link, uint32_t offset)
1449{
1450 union dpcd_training_pattern dpcd_pattern = { {0} };
1451
1452 const uint32_t dpcd_base_lt_offset =
1453 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1454 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1455 /* Set training not in progress*/
1456 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1457
1458 core_link_write_dpcd(
1459 link,
1460 dpcd_base_lt_offset,
1461 &dpcd_pattern.raw,
1462 1);
1463
460adc6b 1464 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
64c12b73 1465 __func__,
460adc6b 1466 offset,
64c12b73 1467 dpcd_base_lt_offset,
1468 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1469}
1470
e0a6440a
DG		 1471static void print_status_message(
1472 struct dc_link *link,
1473 const struct link_training_settings *lt_settings,
1474 enum link_training_result status)
1475{
1476 char *link_rate = "Unknown";
1477 char *lt_result = "Unknown";
1478 char *lt_spread = "Disabled";
4562236b 1479
e0a6440a 1480 switch (lt_settings->link_settings.link_rate) {
4562236b
HW		 1481 case LINK_RATE_LOW:
1482 link_rate = "RBR";
1483 break;
5c8a6c71
JZ		 1484 case LINK_RATE_RATE_2:
1485 link_rate = "R2";
1486 break;
1487 case LINK_RATE_RATE_3:
1488 link_rate = "R3";
1489 break;
4562236b
HW		 1490 case LINK_RATE_HIGH:
1491 link_rate = "HBR";
1492 break;
4562236b
HW		 1493 case LINK_RATE_RBR2:
1494 link_rate = "RBR2";
1495 break;
5c8a6c71
JZ		 1496 case LINK_RATE_RATE_6:
1497 link_rate = "R6";
1498 break;
1499 case LINK_RATE_HIGH2:
1500 link_rate = "HBR2";
1501 break;
4562236b
HW		 1502 case LINK_RATE_HIGH3:
1503 link_rate = "HBR3";
1504 break;
1505 default:
1506 break;
1507 }
1508
94405cf6
WL		 1509 switch (status) {
1510 case LINK_TRAINING_SUCCESS:
1511 lt_result = "pass";
1512 break;
1513 case LINK_TRAINING_CR_FAIL_LANE0:
1514 lt_result = "CR failed lane0";
1515 break;
1516 case LINK_TRAINING_CR_FAIL_LANE1:
1517 lt_result = "CR failed lane1";
1518 break;
1519 case LINK_TRAINING_CR_FAIL_LANE23:
1520 lt_result = "CR failed lane23";
1521 break;
1522 case LINK_TRAINING_EQ_FAIL_CR:
1523 lt_result = "CR failed in EQ";
1524 break;
1525 case LINK_TRAINING_EQ_FAIL_EQ:
1526 lt_result = "EQ failed";
1527 break;
1528 case LINK_TRAINING_LQA_FAIL:
1529 lt_result = "LQA failed";
1530 break;
b246f90a
MT		 1531 case LINK_TRAINING_LINK_LOSS:
1532 lt_result = "Link loss";
1533 break;
94405cf6
WL		 1534 default:
1535 break;
1536 }
1537
e0a6440a
DG		 1538 switch (lt_settings->link_settings.link_spread) {
1539 case LINK_SPREAD_DISABLED:
1540 lt_spread = "Disabled";
1541 break;
1542 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1543 lt_spread = "0.5% 30KHz";
1544 break;
1545 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1546 lt_spread = "0.5% 33KHz";
1547 break;
1548 default:
1549 break;
1550 }
1551
4562236b 1552 /* Connectivity log: link training */
e0a6440a
DG		 1553 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1554 link_rate,
1555 lt_settings->link_settings.lane_count,
1556 lt_result,
1557 lt_settings->lane_settings[0].VOLTAGE_SWING,
1558 lt_settings->lane_settings[0].PRE_EMPHASIS,
1559 lt_spread);
1560}
1561
64c12b73 1562void dc_link_dp_set_drive_settings(
1563 struct dc_link *link,
1564 struct link_training_settings *lt_settings)
1565{
1566 /* program ASIC PHY settings*/
1567 dp_set_hw_lane_settings(link, lt_settings, DPRX);
1568
1569 /* Notify DP sink the PHY settings from source */
1570 dpcd_set_lane_settings(link, lt_settings, DPRX);
1571}
1572
e0a6440a
DG		 1573bool dc_link_dp_perform_link_training_skip_aux(
1574 struct dc_link *link,
1575 const struct dc_link_settings *link_setting)
1576{
1577 struct link_training_settings lt_settings;
e0a6440a 1578
7211b605 1579 dp_decide_training_settings(
0b226322
DG		 1580 link,
1581 link_setting,
1582 &link->preferred_training_settings,
1583 &lt_settings);
e0a6440a
DG		 1584
1585 /* 1. Perform_clock_recovery_sequence. */
1586
1587 /* transmit training pattern for clock recovery */
ce17ce17 1588 dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
e0a6440a
DG		 1589
1590 /* call HWSS to set lane settings*/
64c12b73 1591 dp_set_hw_lane_settings(link, &lt_settings, DPRX);
e0a6440a
DG		 1592
1593 /* wait receiver to lock-on*/
e84ecdc5 1594 dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
e0a6440a
DG		 1595
1596 /* 2. Perform_channel_equalization_sequence. */
1597
1598 /* transmit training pattern for channel equalization. */
64c12b73 1599 dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
e0a6440a
DG		 1600
1601 /* call HWSS to set lane settings*/
64c12b73 1602 dp_set_hw_lane_settings(link, &lt_settings, DPRX);
e0a6440a
DG		 1603
1604 /* wait receiver to lock-on. */
e84ecdc5 1605 dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
e0a6440a
DG		 1606
1607 /* 3. Perform_link_training_int. */
1608
1609 /* Mainlink output idle pattern. */
1610 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1611
1612 print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1613
1614 return true;
1615}
1616
7211b605
JK		 1617enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
1618{
1619 enum dc_status status = DC_OK;
1620
2b7605d7 1621 if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
7211b605 1622 status = configure_lttpr_mode_non_transparent(link, lt_settings);
2b7605d7
WC		 1623 else
1624 status = configure_lttpr_mode_transparent(link);
7211b605
JK		 1625
1626 return status;
1627}
1628
3df21257
WL		 1629static void dpcd_exit_training_mode(struct dc_link *link)
1630{
3df21257
WL		 1631
1632 /* clear training pattern set */
cd6a9a1c 1633 dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
3df21257
WL		 1634}
1635
1636enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1637 struct link_training_settings *lt_settings)
1638{
1639 enum dp_link_encoding encoding =
1640 dp_get_link_encoding_format(
1641 &lt_settings->link_settings);
1642 enum dc_status status;
1643
1644 status = core_link_write_dpcd(
1645 link,
1646 DP_MAIN_LINK_CHANNEL_CODING_SET,
1647 (uint8_t *) &encoding,
1648 1);
1649 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1650 __func__,
1651 DP_MAIN_LINK_CHANNEL_CODING_SET,
1652 encoding);
1653
1654 return status;
1655}
1656
cd6a9a1c
WL		 1657static enum link_training_result dp_perform_8b_10b_link_training(
1658 struct dc_link *link,
1659 struct link_training_settings *lt_settings)
e0a6440a
DG		 1660{
1661 enum link_training_result status = LINK_TRAINING_SUCCESS;
e0a6440a 1662
cd6a9a1c
WL		 1663 uint8_t repeater_cnt;
1664 uint8_t repeater_id;
bcc5042a 1665
82054678 1666 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
cd6a9a1c 1667 start_clock_recovery_pattern_early(link, lt_settings, DPRX);
834a9a9f
ML		 1668
1669 /* 1. set link rate, lane count and spread. */
cd6a9a1c 1670 dpcd_set_link_settings(link, lt_settings);
e0a6440a 1671
3128b285 1672 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
008a4016 1673
64c12b73 1674 /* 2. perform link training (set link training done
1675 * to false is done as well)
1676 */
573a0a03 1677 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
64c12b73 1678
1679 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1680 repeater_id--) {
cd6a9a1c 1681 status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
64c12b73 1682
1683 if (status != LINK_TRAINING_SUCCESS)
1684 break;
1685
1686 status = perform_channel_equalization_sequence(link,
cd6a9a1c 1687 lt_settings,
64c12b73 1688 repeater_id);
1689
1690 if (status != LINK_TRAINING_SUCCESS)
1691 break;
1692
1693 repeater_training_done(link, repeater_id);
1694 }
1695 }
1696
1697 if (status == LINK_TRAINING_SUCCESS) {
cd6a9a1c 1698 status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
e0a6440a
DG		 1699 if (status == LINK_TRAINING_SUCCESS) {
1700 status = perform_channel_equalization_sequence(link,
cd6a9a1c 1701 lt_settings,
64c12b73 1702 DPRX);
1703 }
e0a6440a
DG		 1704 }
1705
cd6a9a1c
WL		 1706 return status;
1707}
1708
1709enum link_training_result dc_link_dp_perform_link_training(
1710 struct dc_link *link,
1711 const struct dc_link_settings *link_settings,
1712 bool skip_video_pattern)
1713{
1714 enum link_training_result status = LINK_TRAINING_SUCCESS;
1715 struct link_training_settings lt_settings;
1716 enum dp_link_encoding encoding =
1717 dp_get_link_encoding_format(link_settings);
1718
1719 /* decide training settings */
1720 dp_decide_training_settings(
1721 link,
1722 link_settings,
1723 &link->preferred_training_settings,
1724 &lt_settings);
1725
1726 /* reset previous training states */
1727 dpcd_exit_training_mode(link);
1728
1729 /* configure link prior to entering training mode */
1730 dpcd_configure_lttpr_mode(link, &lt_settings);
1731 dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
1732 dpcd_configure_channel_coding(link, &lt_settings);
1733
1734 /* enter training mode:
1735 * Per DP specs starting from here, DPTX device shall not issue
1736 * Non-LT AUX transactions inside training mode.
1737 */
1738 if (encoding == DP_8b_10b_ENCODING)
1739 status = dp_perform_8b_10b_link_training(link, &lt_settings);
1740 else
1741 ASSERT(0);
1742
1743 /* exit training mode and switch to video idle */
1744 dpcd_exit_training_mode(link);
1745 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
37f270c6 1746 status = dp_transition_to_video_idle(link,
e0a6440a
DG		 1747 &lt_settings,
1748 status);
e0a6440a 1749
cd6a9a1c 1750 /* dump debug data */
e0a6440a 1751 print_status_message(link, &lt_settings, status);
d6e75df4 1752 if (status != LINK_TRAINING_SUCCESS)
cfd84fd3 1753 link->ctx->dc->debug_data.ltFailCount++;
4562236b
HW		 1754 return status;
1755}
1756
9127daa0
SW		 1757static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
1758{
1759 struct dc_link *link = stream->link;
1760 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1761#ifdef CONFIG_DRM_AMD_DC_HDCP
1762 struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1763#endif
1764
1765 /* ASSR must be supported on the panel */
1766 if (panel_mode == DP_PANEL_MODE_DEFAULT)
1767 return panel_mode;
1768
1769 /* eDP or internal DP only */
1770 if (link->connector_signal != SIGNAL_TYPE_EDP &&
1771 !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1772 link->is_internal_display))
1773 return DP_PANEL_MODE_DEFAULT;
1774
1775#ifdef CONFIG_DRM_AMD_DC_HDCP
1776 if (cp_psp && cp_psp->funcs.enable_assr) {
1777 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1778 /* since eDP implies ASSR on, change panel
1779 * mode to disable ASSR
1780 */
1781 panel_mode = DP_PANEL_MODE_DEFAULT;
1782 }
1783 } else
1784 panel_mode = DP_PANEL_MODE_DEFAULT;
1785
1786#else
1787 /* turn off ASSR if the implementation is not compiled in */
1788 panel_mode = DP_PANEL_MODE_DEFAULT;
1789#endif
1790 return panel_mode;
1791}
1792
4562236b 1793bool perform_link_training_with_retries(
4562236b
HW		 1794 const struct dc_link_settings *link_setting,
1795 bool skip_video_pattern,
832aa63b
PH		 1796 int attempts,
1797 struct pipe_ctx *pipe_ctx,
82253671
JK		 1798 enum signal_type signal,
1799 bool do_fallback)
4562236b
HW		 1800{
1801 uint8_t j;
1802 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
832aa63b
PH		 1803 struct dc_stream_state *stream = pipe_ctx->stream;
1804 struct dc_link *link = stream->link;
9127daa0 1805 enum dp_panel_mode panel_mode;
82253671
JK		 1806 struct link_encoder *link_enc;
1807 enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
f7115198 1808 struct dc_link_settings current_setting = *link_setting;
82253671
JK		 1809
1810 /* Dynamically assigned link encoders associated with stream rather than
1811 * link.
1812 */
1813 if (link->dc->res_pool->funcs->link_encs_assign)
1814 link_enc = stream->link_enc;
1815 else
1816 link_enc = link->link_enc;
1817 ASSERT(link_enc);
4562236b 1818
eec3303d
AC		 1819 /* We need to do this before the link training to ensure the idle pattern in SST
1820 * mode will be sent right after the link training
1821 */
82253671 1822 link_enc->funcs->connect_dig_be_to_fe(link_enc,
eec3303d
AC		 1823 pipe_ctx->stream_res.stream_enc->id, true);
1824
4562236b
HW		 1825 for (j = 0; j < attempts; ++j) {
1826
172c9b77
AT		 1827 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1828 __func__, (unsigned int)j + 1, attempts);
1829
832aa63b
PH		 1830 dp_enable_link_phy(
1831 link,
1832 signal,
1833 pipe_ctx->clock_source->id,
f7115198 1834 &current_setting);
832aa63b 1835
eec3303d
AC		 1836 if (stream->sink_patches.dppowerup_delay > 0) {
1837 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1838
832aa63b
PH		 1839 msleep(delay_dp_power_up_in_ms);
1840 }
1841
9127daa0 1842 panel_mode = try_enable_assr(stream);
832aa63b 1843 dp_set_panel_mode(link, panel_mode);
9127daa0
SW		 1844 DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
1845 link->link_index,
1846 panel_mode != DP_PANEL_MODE_DEFAULT);
832aa63b 1847
832aa63b 1848 if (link->aux_access_disabled) {
f7115198 1849 dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
832aa63b 1850 return true;
79ed7354 1851 } else {
79ed7354
JK		 1852 status = dc_link_dp_perform_link_training(
1853 link,
f7115198 1854 &current_setting,
79ed7354
JK		 1855 skip_video_pattern);
1856 if (status == LINK_TRAINING_SUCCESS)
1857 return true;
1858 }
4562236b 1859
832aa63b
PH		 1860 /* latest link training still fail, skip delay and keep PHY on
1861 */
82253671 1862 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
832aa63b
PH		 1863 break;
1864
172c9b77
AT		 1865 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1866 __func__, (unsigned int)j + 1, attempts);
1867
832aa63b
PH		 1868 dp_disable_link_phy(link, signal);
1869
82253671
JK		 1870 /* Abort link training if failure due to sink being unplugged. */
1871 if (status == LINK_TRAINING_ABORT)
1872 break;
1873 else if (do_fallback) {
f7115198 1874 decide_fallback_link_setting(*link_setting, &current_setting, status);
82253671
JK		 1875 /* Fail link training if reduced link bandwidth no longer meets
1876 * stream requirements.
1877 */
1878 if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
f7115198 1879 dc_link_bandwidth_kbps(link, &current_setting))
82253671
JK		 1880 break;
1881 }
1882
4562236b 1883 msleep(delay_between_attempts);
832aa63b 1884
4562236b
HW		 1885 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1886 }
1887
1888 return false;
1889}
1890
0b226322
DG		 1891static enum clock_source_id get_clock_source_id(struct dc_link *link)
1892{
1893 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1894 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1895
1896 if (dp_cs != NULL) {
1897 dp_cs_id = dp_cs->id;
1898 } else {
1899 /*
1900 * dp clock source is not initialized for some reason.
1901 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1902 */
1903 ASSERT(dp_cs);
1904 }
1905
1906 return dp_cs_id;
1907}
1908
1909static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1910{
1911 if (mst_enable == false &&
1912 link->type == dc_connection_mst_branch) {
1913 /* Disable MST on link. Use only local sink. */
1914 dp_disable_link_phy_mst(link, link->connector_signal);
1915
1916 link->type = dc_connection_single;
1917 link->local_sink = link->remote_sinks[0];
1918 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
3f8518b6
VS		 1919 dc_sink_retain(link->local_sink);
1920 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
0b226322
DG		 1921 } else if (mst_enable == true &&
1922 link->type == dc_connection_single &&
1923 link->remote_sinks[0] != NULL) {
1924 /* Re-enable MST on link. */
1925 dp_disable_link_phy(link, link->connector_signal);
1926 dp_enable_mst_on_sink(link, true);
1927
1928 link->type = dc_connection_mst_branch;
1929 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1930 }
1931}
1932
1933bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1934{
1935 /* Begin Sync LT. During this time,
1936 * DPCD:600h must not be powered down.
1937 */
1938 link->sync_lt_in_progress = true;
1939
1940 /*Clear any existing preferred settings.*/
1941 memset(&link->preferred_training_settings, 0,
1942 sizeof(struct dc_link_training_overrides));
1943 memset(&link->preferred_link_setting, 0,
1944 sizeof(struct dc_link_settings));
1945
1946 return true;
1947}
1948
1949enum link_training_result dc_link_dp_sync_lt_attempt(
1950 struct dc_link *link,
1951 struct dc_link_settings *link_settings,
1952 struct dc_link_training_overrides *lt_overrides)
1953{
1954 struct link_training_settings lt_settings;
1955 enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1956 enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1957 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
0b226322 1958 bool fec_enable = false;
0b226322 1959
7211b605 1960 dp_decide_training_settings(
0b226322
DG		 1961 link,
1962 link_settings,
1963 lt_overrides,
1964 &lt_settings);
1965
1966 /* Setup MST Mode */
1967 if (lt_overrides->mst_enable)
1968 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1969
1970 /* Disable link */
1971 dp_disable_link_phy(link, link->connector_signal);
1972
1973 /* Enable link */
1974 dp_cs_id = get_clock_source_id(link);
1975 dp_enable_link_phy(link, link->connector_signal,
1976 dp_cs_id, link_settings);
1977
0b226322
DG		 1978 /* Set FEC enable */
1979 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1980 dp_set_fec_ready(link, fec_enable);
0b226322
DG		 1981
1982 if (lt_overrides->alternate_scrambler_reset) {
1983 if (*lt_overrides->alternate_scrambler_reset)
1984 panel_mode = DP_PANEL_MODE_EDP;
1985 else
1986 panel_mode = DP_PANEL_MODE_DEFAULT;
1987 } else
1988 panel_mode = dp_get_panel_mode(link);
1989
1990 dp_set_panel_mode(link, panel_mode);
1991
1992 /* Attempt to train with given link training settings */
82054678
ML		 1993 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1994 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
834a9a9f
ML		 1995
1996 /* Set link rate, lane count and spread. */
1997 dpcd_set_link_settings(link, &lt_settings);
0b226322
DG		 1998
1999 /* 2. perform link training (set link training done
2000 * to false is done as well)
2001 */
64c12b73 2002 lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
0b226322
DG		 2003 if (lt_status == LINK_TRAINING_SUCCESS) {
2004 lt_status = perform_channel_equalization_sequence(link,
64c12b73 2005 &lt_settings,
2006 DPRX);
0b226322
DG		 2007 }
2008
2009 /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
2010 /* 4. print status message*/
2011 print_status_message(link, &lt_settings, lt_status);
2012
2013 return lt_status;
2014}
2015
2016bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
2017{
2018 /* If input parameter is set, shut down phy.
2019 * Still shouldn't turn off dp_receiver (DPCD:600h)
2020 */
2021 if (link_down == true) {
2022 dp_disable_link_phy(link, link->connector_signal);
0b226322 2023 dp_set_fec_ready(link, false);
0b226322
DG		 2024 }
2025
2026 link->sync_lt_in_progress = false;
2027 return true;
2028}
2029
98025a62
NC		 2030bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2031{
2032 if (!max_link_enc_cap) {
2033 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2034 return false;
2035 }
2036
2037 if (link->link_enc->funcs->get_max_link_cap) {
2038 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
2039 return true;
2040 }
2041
2042 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2043 max_link_enc_cap->lane_count = 1;
2044 max_link_enc_cap->link_rate = 6;
2045 return false;
2046}
2047
d0778ebf 2048static struct dc_link_settings get_max_link_cap(struct dc_link *link)
4562236b 2049{
8ccf0e20 2050 struct dc_link_settings max_link_cap = {0};
4562236b 2051
8ccf0e20
WL		 2052 /* get max link encoder capability */
2053 link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
f537d474 2054
4562236b 2055 /* Lower link settings based on sink's link cap */
d0778ebf 2056 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
4562236b 2057 max_link_cap.lane_count =
d0778ebf
HW		 2058 link->reported_link_cap.lane_count;
2059 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
4562236b 2060 max_link_cap.link_rate =
d0778ebf
HW		 2061 link->reported_link_cap.link_rate;
2062 if (link->reported_link_cap.link_spread <
4562236b
HW		 2063 max_link_cap.link_spread)
2064 max_link_cap.link_spread =
d0778ebf 2065 link->reported_link_cap.link_spread;
bad7ab0b 2066 /*
2067 * account for lttpr repeaters cap
2068 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2069 */
3128b285 2070 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
bad7ab0b 2071 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2072 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2073
2074 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2075 max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
460adc6b 2076
2077 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
2078 __func__,
2079 max_link_cap.lane_count,
2080 max_link_cap.link_rate);
bad7ab0b 2081 }
4562236b
HW		 2082 return max_link_cap;
2083}
2084
3083a984 2085enum dc_status read_hpd_rx_irq_data(
1ae62f31
WL		 2086 struct dc_link *link,
2087 union hpd_irq_data *irq_data)
2088{
2089 static enum dc_status retval;
2090
2091 /* The HW reads 16 bytes from 200h on HPD,
2092 * but if we get an AUX_DEFER, the HW cannot retry
2093 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2094 * fail, so we now explicitly read 6 bytes which is
2095 * the req from the above mentioned test cases.
2096 *
2097 * For DP 1.4 we need to read those from 2002h range.
2098 */
2099 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2100 retval = core_link_read_dpcd(
2101 link,
2102 DP_SINK_COUNT,
2103 irq_data->raw,
2104 sizeof(union hpd_irq_data));
2105 else {
2106 /* Read 14 bytes in a single read and then copy only the required fields.
2107 * This is more efficient than doing it in two separate AUX reads. */
2108
2109 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2110
2111 retval = core_link_read_dpcd(
2112 link,
2113 DP_SINK_COUNT_ESI,
2114 tmp,
2115 sizeof(tmp));
2116
2117 if (retval != DC_OK)
2118 return retval;
2119
2120 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2121 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2122 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2123 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2124 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2125 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2126 }
2127
2128 return retval;
2129}
2130
d2aa1356 2131bool hpd_rx_irq_check_link_loss_status(
1ae62f31
WL		 2132 struct dc_link *link,
2133 union hpd_irq_data *hpd_irq_dpcd_data)
2134{
2135 uint8_t irq_reg_rx_power_state = 0;
2136 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2137 union lane_status lane_status;
2138 uint32_t lane;
2139 bool sink_status_changed;
2140 bool return_code;
2141
2142 sink_status_changed = false;
2143 return_code = false;
2144
2145 if (link->cur_link_settings.lane_count == 0)
2146 return return_code;
2147
2148 /*1. Check that Link Status changed, before re-training.*/
2149
2150 /*parse lane status*/
2151 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2152 /* check status of lanes 0,1
2153 * changed DpcdAddress_Lane01Status (0x202)
2154 */
2155 lane_status.raw = get_nibble_at_index(
2156 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2157 lane);
2158
2159 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2160 !lane_status.bits.CR_DONE_0 ||
2161 !lane_status.bits.SYMBOL_LOCKED_0) {
2162 /* if one of the channel equalization, clock
2163 * recovery or symbol lock is dropped
2164 * consider it as (link has been
2165 * dropped) dp sink status has changed
2166 */
2167 sink_status_changed = true;
2168 break;
2169 }
2170 }
2171
2172 /* Check interlane align.*/
2173 if (sink_status_changed ||
2174 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2175
2176 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2177
2178 return_code = true;
2179
2180 /*2. Check that we can handle interrupt: Not in FS DOS,
2181 * Not in "Display Timeout" state, Link is trained.
2182 */
2183 dpcd_result = core_link_read_dpcd(link,
2184 DP_SET_POWER,
2185 &irq_reg_rx_power_state,
2186 sizeof(irq_reg_rx_power_state));
2187
2188 if (dpcd_result != DC_OK) {
2189 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2190 __func__);
2191 } else {
2192 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2193 return_code = false;
2194 }
2195 }
2196
2197 return return_code;
2198}
2199
aafded88 2200bool dp_verify_link_cap(
d0778ebf 2201 struct dc_link *link,
824474ba
BL		 2202 struct dc_link_settings *known_limit_link_setting,
2203 int *fail_count)
4562236b
HW		 2204{
2205 struct dc_link_settings max_link_cap = {0};
820e3935
DW		 2206 struct dc_link_settings cur_link_setting = {0};
2207 struct dc_link_settings *cur = &cur_link_setting;
2208 struct dc_link_settings initial_link_settings = {0};
4562236b
HW		 2209 bool success;
2210 bool skip_link_training;
4562236b 2211 bool skip_video_pattern;
4562236b 2212 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
820e3935 2213 enum link_training_result status;
1ae62f31 2214 union hpd_irq_data irq_data;
4562236b 2215
aafded88
TC		 2216 if (link->dc->debug.skip_detection_link_training) {
2217 link->verified_link_cap = *known_limit_link_setting;
2218 return true;
2219 }
2220
1ae62f31 2221 memset(&irq_data, 0, sizeof(irq_data));
4562236b
HW		 2222 success = false;
2223 skip_link_training = false;
2224
2225 max_link_cap = get_max_link_cap(link);
2226
bad7ab0b 2227 /* Grant extended timeout request */
3128b285 2228 if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
bad7ab0b 2229 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2230
2231 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2232 }
2233
4562236b
HW		 2234 /* TODO implement override and monitor patch later */
2235
2236 /* try to train the link from high to low to
2237 * find the physical link capability
2238 */
2239 /* disable PHY done possible by BIOS, will be done by driver itself */
d0778ebf 2240 dp_disable_link_phy(link, link->connector_signal);
4562236b 2241
b3282738
GS		 2242 dp_cs_id = get_clock_source_id(link);
2243
2244 /* link training starts with the maximum common settings
2245 * supported by both sink and ASIC.
2246 */
2247 initial_link_settings = get_common_supported_link_settings(
2248 *known_limit_link_setting,
2249 max_link_cap);
2250 cur_link_setting = initial_link_settings;
2251
ee765924
GS		 2252 /* Temporary Renoir-specific workaround for SWDEV-215184;
2253 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2254 * so add extra cycle of enabling and disabling the PHY before first link training.
2255 */
2256 if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2257 link->dc->debug.usbc_combo_phy_reset_wa) {
2258 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2259 dp_disable_link_phy(link, link->connector_signal);
2260 }
2261
820e3935 2262 do {
4562236b 2263 skip_video_pattern = true;
820e3935 2264
4562236b
HW		 2265 if (cur->link_rate == LINK_RATE_LOW)
2266 skip_video_pattern = false;
2267
2268 dp_enable_link_phy(
2269 link,
d0778ebf 2270 link->connector_signal,
4562236b
HW		 2271 dp_cs_id,
2272 cur);
2273
94405cf6 2274
4562236b
HW		 2275 if (skip_link_training)
2276 success = true;
2277 else {
820e3935 2278 status = dc_link_dp_perform_link_training(
d0778ebf 2279 link,
4562236b
HW		 2280 cur,
2281 skip_video_pattern);
820e3935
DW		 2282 if (status == LINK_TRAINING_SUCCESS)
2283 success = true;
824474ba
BL		 2284 else
2285 (*fail_count)++;
4562236b
HW		 2286 }
2287
1ae62f31 2288 if (success) {
d0778ebf 2289 link->verified_link_cap = *cur;
1ae62f31
WL		 2290 udelay(1000);
2291 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2292 if (hpd_rx_irq_check_link_loss_status(
2293 link,
2294 &irq_data))
2295 (*fail_count)++;
2296 }
4562236b
HW		 2297 /* always disable the link before trying another
2298 * setting or before returning we'll enable it later
2299 * based on the actual mode we're driving
2300 */
d0778ebf 2301 dp_disable_link_phy(link, link->connector_signal);
820e3935
DW		 2302 } while (!success && decide_fallback_link_setting(
2303 initial_link_settings, cur, status));
4562236b
HW		 2304
2305 /* Link Training failed for all Link Settings
2306 * (Lane Count is still unknown)
2307 */
2308 if (!success) {
2309 /* If all LT fails for all settings,
2310 * set verified = failed safe (1 lane low)
2311 */
d0778ebf
HW		 2312 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2313 link->verified_link_cap.link_rate = LINK_RATE_LOW;
4562236b 2314
d0778ebf 2315 link->verified_link_cap.link_spread =
4562236b
HW		 2316 LINK_SPREAD_DISABLED;
2317 }
2318
4562236b
HW		 2319
2320 return success;
2321}
2322
e7f2c80c
WL		 2323bool dp_verify_link_cap_with_retries(
2324 struct dc_link *link,
2325 struct dc_link_settings *known_limit_link_setting,
2326 int attempts)
2327{
2328 uint8_t i = 0;
2329 bool success = false;
2330
2331 for (i = 0; i < attempts; i++) {
2332 int fail_count = 0;
82db2e3c 2333 enum dc_connection_type type = dc_connection_none;
e7f2c80c
WL		 2334
2335 memset(&link->verified_link_cap, 0,
2336 sizeof(struct dc_link_settings));
82db2e3c
SK		 2337 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2338 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2339 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2340 link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
e7f2c80c
WL		 2341 break;
2342 } else if (dp_verify_link_cap(link,
2343 &link->reported_link_cap,
2344 &fail_count) && fail_count == 0) {
2345 success = true;
2346 break;
2347 }
2348 msleep(10);
2349 }
2350 return success;
2351}
2352
f537d474
LH		 2353bool dp_verify_mst_link_cap(
2354 struct dc_link *link)
2355{
2356 struct dc_link_settings max_link_cap = {0};
2357
2358 max_link_cap = get_max_link_cap(link);
2359 link->verified_link_cap = get_common_supported_link_settings(
2360 link->reported_link_cap,
2361 max_link_cap);
2362
2363 return true;
2364}
2365
9a6a8075 2366static struct dc_link_settings get_common_supported_link_settings(
820e3935
DW		 2367 struct dc_link_settings link_setting_a,
2368 struct dc_link_settings link_setting_b)
2369{
2370 struct dc_link_settings link_settings = {0};
2371
2372 link_settings.lane_count =
2373 (link_setting_a.lane_count <=
2374 link_setting_b.lane_count) ?
2375 link_setting_a.lane_count :
2376 link_setting_b.lane_count;
2377 link_settings.link_rate =
2378 (link_setting_a.link_rate <=
2379 link_setting_b.link_rate) ?
2380 link_setting_a.link_rate :
2381 link_setting_b.link_rate;
2382 link_settings.link_spread = LINK_SPREAD_DISABLED;
2383
2384 /* in DP compliance test, DPR-120 may have
2385 * a random value in its MAX_LINK_BW dpcd field.
2386 * We map it to the maximum supported link rate that
2387 * is smaller than MAX_LINK_BW in this case.
2388 */
2389 if (link_settings.link_rate > LINK_RATE_HIGH3) {
2390 link_settings.link_rate = LINK_RATE_HIGH3;
2391 } else if (link_settings.link_rate < LINK_RATE_HIGH3
2392 && link_settings.link_rate > LINK_RATE_HIGH2) {
2393 link_settings.link_rate = LINK_RATE_HIGH2;
2394 } else if (link_settings.link_rate < LINK_RATE_HIGH2
2395 && link_settings.link_rate > LINK_RATE_HIGH) {
2396 link_settings.link_rate = LINK_RATE_HIGH;
2397 } else if (link_settings.link_rate < LINK_RATE_HIGH
2398 && link_settings.link_rate > LINK_RATE_LOW) {
2399 link_settings.link_rate = LINK_RATE_LOW;
2400 } else if (link_settings.link_rate < LINK_RATE_LOW) {
2401 link_settings.link_rate = LINK_RATE_UNKNOWN;
2402 }
2403
2404 return link_settings;
2405}
2406
450619d3 2407static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 2408{
2409 return lane_count <= LANE_COUNT_ONE;
2410}
2411
450619d3 2412static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 2413{
2414 return link_rate <= LINK_RATE_LOW;
2415}
2416
44858055 2417static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 2418{
2419 switch (lane_count) {
2420 case LANE_COUNT_FOUR:
2421 return LANE_COUNT_TWO;
2422 case LANE_COUNT_TWO:
2423 return LANE_COUNT_ONE;
2424 case LANE_COUNT_ONE:
2425 return LANE_COUNT_UNKNOWN;
2426 default:
2427 return LANE_COUNT_UNKNOWN;
2428 }
2429}
2430
04e21292 2431static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 2432{
2433 switch (link_rate) {
2434 case LINK_RATE_HIGH3:
2435 return LINK_RATE_HIGH2;
2436 case LINK_RATE_HIGH2:
2437 return LINK_RATE_HIGH;
2438 case LINK_RATE_HIGH:
2439 return LINK_RATE_LOW;
2440 case LINK_RATE_LOW:
2441 return LINK_RATE_UNKNOWN;
2442 default:
2443 return LINK_RATE_UNKNOWN;
2444 }
2445}
2446
04e21292 2447static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
8c4abe0b
DW		 2448{
2449 switch (lane_count) {
2450 case LANE_COUNT_ONE:
2451 return LANE_COUNT_TWO;
2452 case LANE_COUNT_TWO:
2453 return LANE_COUNT_FOUR;
2454 default:
2455 return LANE_COUNT_UNKNOWN;
2456 }
2457}
2458
04e21292 2459static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
8c4abe0b
DW		 2460{
2461 switch (link_rate) {
2462 case LINK_RATE_LOW:
2463 return LINK_RATE_HIGH;
2464 case LINK_RATE_HIGH:
2465 return LINK_RATE_HIGH2;
2466 case LINK_RATE_HIGH2:
2467 return LINK_RATE_HIGH3;
2468 default:
2469 return LINK_RATE_UNKNOWN;
2470 }
2471}
2472
820e3935
DW		 2473/*
2474 * function: set link rate and lane count fallback based
2475 * on current link setting and last link training result
2476 * return value:
2477 * true - link setting could be set
2478 * false - has reached minimum setting
2479 * and no further fallback could be done
2480 */
04e21292 2481static bool decide_fallback_link_setting(
820e3935
DW		 2482 struct dc_link_settings initial_link_settings,
2483 struct dc_link_settings *current_link_setting,
2484 enum link_training_result training_result)
2485{
2486 if (!current_link_setting)
2487 return false;
2488
2489 switch (training_result) {
94405cf6
WL		 2490 case LINK_TRAINING_CR_FAIL_LANE0:
2491 case LINK_TRAINING_CR_FAIL_LANE1:
2492 case LINK_TRAINING_CR_FAIL_LANE23:
2493 case LINK_TRAINING_LQA_FAIL:
820e3935
DW		 2494 {
2495 if (!reached_minimum_link_rate
2496 (current_link_setting->link_rate)) {
2497 current_link_setting->link_rate =
2498 reduce_link_rate(
2499 current_link_setting->link_rate);
2500 } else if (!reached_minimum_lane_count
2501 (current_link_setting->lane_count)) {
2502 current_link_setting->link_rate =
2503 initial_link_settings.link_rate;
94405cf6
WL		 2504 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2505 return false;
2506 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2507 current_link_setting->lane_count =
2508 LANE_COUNT_ONE;
2509 else if (training_result ==
2510 LINK_TRAINING_CR_FAIL_LANE23)
2511 current_link_setting->lane_count =
2512 LANE_COUNT_TWO;
2513 else
2514 current_link_setting->lane_count =
2515 reduce_lane_count(
820e3935
DW		 2516 current_link_setting->lane_count);
2517 } else {
2518 return false;
2519 }
2520 break;
2521 }
2522 case LINK_TRAINING_EQ_FAIL_EQ:
2523 {
2524 if (!reached_minimum_lane_count
2525 (current_link_setting->lane_count)) {
2526 current_link_setting->lane_count =
2527 reduce_lane_count(
2528 current_link_setting->lane_count);
2529 } else if (!reached_minimum_link_rate
2530 (current_link_setting->link_rate)) {
820e3935
DW		 2531 current_link_setting->link_rate =
2532 reduce_link_rate(
2533 current_link_setting->link_rate);
2534 } else {
2535 return false;
2536 }
2537 break;
2538 }
2539 case LINK_TRAINING_EQ_FAIL_CR:
2540 {
2541 if (!reached_minimum_link_rate
2542 (current_link_setting->link_rate)) {
2543 current_link_setting->link_rate =
2544 reduce_link_rate(
2545 current_link_setting->link_rate);
2546 } else {
2547 return false;
2548 }
2549 break;
2550 }
2551 default:
2552 return false;
2553 }
2554 return true;
2555}
2556
4562236b 2557bool dp_validate_mode_timing(
d0778ebf 2558 struct dc_link *link,
4562236b
HW		 2559 const struct dc_crtc_timing *timing)
2560{
2561 uint32_t req_bw;
2562 uint32_t max_bw;
2563
2564 const struct dc_link_settings *link_setting;
2565
05e62b6b
GS		 2566 /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2567 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2568 !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2569 dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2570 return false;
2571
4562236b 2572 /*always DP fail safe mode*/
380604e2 2573 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
9a6a8075
HW		 2574 timing->h_addressable == (uint32_t) 640 &&
2575 timing->v_addressable == (uint32_t) 480)
4562236b
HW		 2576 return true;
2577
5ac4619b 2578 link_setting = dc_link_get_link_cap(link);
4562236b
HW		 2579
2580 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2581 /*if (flags.DYNAMIC_VALIDATION == 1 &&
d0778ebf
HW		 2582 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2583 link_setting = &link->verified_link_cap;
4562236b
HW		 2584 */
2585
e49f6936 2586 req_bw = dc_bandwidth_in_kbps_from_timing(timing);
332c1191 2587 max_bw = dc_link_bandwidth_kbps(link, link_setting);
4562236b
HW		 2588
2589 if (req_bw <= max_bw) {
2590 /* remember the biggest mode here, during
2591 * initial link training (to get
2592 * verified_link_cap), LS sends event about
2593 * cannot train at reported cap to upper
2594 * layer and upper layer will re-enumerate modes.
2595 * this is not necessary if the lower
2596 * verified_link_cap is enough to drive
2597 * all the modes */
2598
2599 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2600 /* if (flags.DYNAMIC_VALIDATION == 1)
2601 dpsst->max_req_bw_for_verified_linkcap = dal_max(
2602 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2603 return true;
2604 } else
2605 return false;
2606}
2607
8628d02f 2608static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
4562236b 2609{
8c4abe0b 2610 struct dc_link_settings initial_link_setting = {
8628d02f 2611 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
8c4abe0b
DW		 2612 struct dc_link_settings current_link_setting =
2613 initial_link_setting;
4562236b 2614 uint32_t link_bw;
4562236b 2615
69d5c7f3
BG		 2616 if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2617 return false;
2618
8628d02f
JP		 2619 /* search for the minimum link setting that:
2620 * 1. is supported according to the link training result
2621 * 2. could support the b/w requested by the timing
4562236b 2622 */
8628d02f
JP		 2623 while (current_link_setting.link_rate <=
2624 link->verified_link_cap.link_rate) {
332c1191
NC		 2625 link_bw = dc_link_bandwidth_kbps(
2626 link,
8628d02f
JP		 2627 &current_link_setting);
2628 if (req_bw <= link_bw) {
2629 *link_setting = current_link_setting;
2630 return true;
2631 }
4562236b 2632
8628d02f
JP		 2633 if (current_link_setting.lane_count <
2634 link->verified_link_cap.lane_count) {
2635 current_link_setting.lane_count =
2636 increase_lane_count(
2637 current_link_setting.lane_count);
2638 } else {
2639 current_link_setting.link_rate =
2640 increase_link_rate(
2641 current_link_setting.link_rate);
2642 current_link_setting.lane_count =
2643 initial_link_setting.lane_count;
2644 }
3f1f74f4
JZ		 2645 }
2646
8628d02f
JP		 2647 return false;
2648}
2649
8efd0f5a 2650bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
8628d02f
JP		 2651{
2652 struct dc_link_settings initial_link_setting;
2653 struct dc_link_settings current_link_setting;
2654 uint32_t link_bw;
2655
67c268a5
ZL		 2656 /*
2657 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2658 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2659 */
2660 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
53c81fc7 2661 link->dpcd_caps.edp_supported_link_rates_count == 0) {
4d2f22d1 2662 *link_setting = link->verified_link_cap;
8628d02f 2663 return true;
4d2f22d1
HH		 2664 }
2665
8628d02f
JP		 2666 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2667 initial_link_setting.lane_count = LANE_COUNT_ONE;
2668 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2669 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2670 initial_link_setting.use_link_rate_set = true;
2671 initial_link_setting.link_rate_set = 0;
2672 current_link_setting = initial_link_setting;
2673
5667ff5c
DA		 2674 /* search for the minimum link setting that:
2675 * 1. is supported according to the link training result
2676 * 2. could support the b/w requested by the timing
2677 */
8c4abe0b 2678 while (current_link_setting.link_rate <=
4654a2f7 2679 link->verified_link_cap.link_rate) {
332c1191
NC		 2680 link_bw = dc_link_bandwidth_kbps(
2681 link,
8c4abe0b
DW		 2682 &current_link_setting);
2683 if (req_bw <= link_bw) {
2684 *link_setting = current_link_setting;
8628d02f 2685 return true;
4562236b 2686 }
4562236b 2687
8c4abe0b 2688 if (current_link_setting.lane_count <
4654a2f7 2689 link->verified_link_cap.lane_count) {
8c4abe0b
DW		 2690 current_link_setting.lane_count =
2691 increase_lane_count(
2692 current_link_setting.lane_count);
2693 } else {
8628d02f
JP		 2694 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2695 current_link_setting.link_rate_set++;
2696 current_link_setting.link_rate =
2697 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2698 current_link_setting.lane_count =
2699 initial_link_setting.lane_count;
2700 } else
2701 break;
4562236b
HW		 2702 }
2703 }
8628d02f
JP		 2704 return false;
2705}
2706
c08321cb
WL		 2707static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2708{
2709 *link_setting = link->verified_link_cap;
2710 return true;
2711}
2712
8628d02f
JP		 2713void decide_link_settings(struct dc_stream_state *stream,
2714 struct dc_link_settings *link_setting)
2715{
2716 struct dc_link *link;
2717 uint32_t req_bw;
2718
e49f6936 2719 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
8628d02f
JP		 2720
2721 link = stream->link;
2722
2723 /* if preferred is specified through AMDDP, use it, if it's enough
2724 * to drive the mode
2725 */
2726 if (link->preferred_link_setting.lane_count !=
2727 LANE_COUNT_UNKNOWN &&
2728 link->preferred_link_setting.link_rate !=
2729 LINK_RATE_UNKNOWN) {
2730 *link_setting = link->preferred_link_setting;
2731 return;
2732 }
2733
2734 /* MST doesn't perform link training for now
2735 * TODO: add MST specific link training routine
2736 */
2737 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
c08321cb
WL		 2738 if (decide_mst_link_settings(link, link_setting))
2739 return;
2740 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
8628d02f
JP		 2741 if (decide_edp_link_settings(link, link_setting, req_bw))
2742 return;
2743 } else if (decide_dp_link_settings(link, link_setting, req_bw))
2744 return;
4562236b
HW		 2745
2746 BREAK_TO_DEBUGGER();
d0778ebf 2747 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
4562236b 2748
d0778ebf 2749 *link_setting = link->verified_link_cap;
4562236b
HW		 2750}
2751
2752/*************************Short Pulse IRQ***************************/
d0778ebf 2753static bool allow_hpd_rx_irq(const struct dc_link *link)
4562236b
HW		 2754{
2755 /*
2756 * Don't handle RX IRQ unless one of following is met:
2757 * 1) The link is established (cur_link_settings != unknown)
36c9137b 2758 * 2) We know we're dealing with a branch device, SST or MST
4562236b
HW		 2759 */
2760
d0778ebf 2761 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
36c9137b 2762 is_dp_branch_device(link))
4562236b
HW		 2763 return true;
2764
2765 return false;
2766}
2767
ab4a4072 2768static bool handle_hpd_irq_psr_sink(struct dc_link *link)
4562236b
HW		 2769{
2770 union dpcd_psr_configuration psr_configuration;
2771
d1ebfdd8 2772 if (!link->psr_settings.psr_feature_enabled)
4562236b
HW		 2773 return false;
2774
7c7f5b15
AG		 2775 dm_helpers_dp_read_dpcd(
2776 link->ctx,
d0778ebf 2777 link,
7c7f5b15
AG		 2778 368,/*DpcdAddress_PSR_Enable_Cfg*/
2779 &psr_configuration.raw,
2780 sizeof(psr_configuration.raw));
2781
4562236b
HW		 2782
2783 if (psr_configuration.bits.ENABLE) {
2784 unsigned char dpcdbuf[3] = {0};
2785 union psr_error_status psr_error_status;
2786 union psr_sink_psr_status psr_sink_psr_status;
2787
7c7f5b15
AG		 2788 dm_helpers_dp_read_dpcd(
2789 link->ctx,
d0778ebf 2790 link,
7c7f5b15
AG		 2791 0x2006, /*DpcdAddress_PSR_Error_Status*/
2792 (unsigned char *) dpcdbuf,
2793 sizeof(dpcdbuf));
4562236b
HW		 2794
2795 /*DPCD 2006h ERROR STATUS*/
2796 psr_error_status.raw = dpcdbuf[0];
2797 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
2798 psr_sink_psr_status.raw = dpcdbuf[2];
2799
2800 if (psr_error_status.bits.LINK_CRC_ERROR ||
63c954a1
WW		 2801 psr_error_status.bits.RFB_STORAGE_ERROR ||
2802 psr_error_status.bits.VSC_SDP_ERROR) {
4562236b 2803 /* Acknowledge and clear error bits */
7c7f5b15
AG		 2804 dm_helpers_dp_write_dpcd(
2805 link->ctx,
d0778ebf 2806 link,
7c7f5b15 2807 8198,/*DpcdAddress_PSR_Error_Status*/
4562236b
HW		 2808 &psr_error_status.raw,
2809 sizeof(psr_error_status.raw));
2810
2811 /* PSR error, disable and re-enable PSR */
1d496907
KK		 2812 dc_link_set_psr_allow_active(link, false, true, false);
2813 dc_link_set_psr_allow_active(link, true, true, false);
4562236b
HW		 2814
2815 return true;
2816 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2817 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2818 /* No error is detect, PSR is active.
2819 * We should return with IRQ_HPD handled without
2820 * checking for loss of sync since PSR would have
2821 * powered down main link.
2822 */
2823 return true;
2824 }
2825 }
2826 return false;
2827}
2828
d0778ebf 2829static void dp_test_send_link_training(struct dc_link *link)
4562236b 2830{
73c72602 2831 struct dc_link_settings link_settings = {0};
4562236b
HW		 2832
2833 core_link_read_dpcd(
2834 link,
3a340294 2835 DP_TEST_LANE_COUNT,
4562236b
HW		 2836 (unsigned char *)(&link_settings.lane_count),
2837 1);
2838 core_link_read_dpcd(
2839 link,
3a340294 2840 DP_TEST_LINK_RATE,
4562236b
HW		 2841 (unsigned char *)(&link_settings.link_rate),
2842 1);
2843
2844 /* Set preferred link settings */
d0778ebf
HW		 2845 link->verified_link_cap.lane_count = link_settings.lane_count;
2846 link->verified_link_cap.link_rate = link_settings.link_rate;
4562236b 2847
73c72602 2848 dp_retrain_link_dp_test(link, &link_settings, false);
4562236b
HW		 2849}
2850
9315e239 2851/* TODO Raven hbr2 compliance eye output is unstable
25bab0da
WL		 2852 * (toggling on and off) with debugger break
2853 * This caueses intermittent PHY automation failure
2854 * Need to look into the root cause */
d0778ebf 2855static void dp_test_send_phy_test_pattern(struct dc_link *link)
4562236b
HW		 2856{
2857 union phy_test_pattern dpcd_test_pattern;
2858 union lane_adjust dpcd_lane_adjustment[2];
2859 unsigned char dpcd_post_cursor_2_adjustment = 0;
5e9ff159 2860 unsigned char test_pattern_buffer[
3a340294
DA		 2861 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2862 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
5e9ff159 2863 unsigned int test_pattern_size = 0;
4562236b
HW		 2864 enum dp_test_pattern test_pattern;
2865 struct dc_link_training_settings link_settings;
2866 union lane_adjust dpcd_lane_adjust;
2867 unsigned int lane;
2868 struct link_training_settings link_training_settings;
2869 int i = 0;
2870
2871 dpcd_test_pattern.raw = 0;
2872 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2873 memset(&link_settings, 0, sizeof(link_settings));
2874
2875 /* get phy test pattern and pattern parameters from DP receiver */
2876 core_link_read_dpcd(
2877 link,
8811d9eb 2878 DP_PHY_TEST_PATTERN,
4562236b
HW		 2879 &dpcd_test_pattern.raw,
2880 sizeof(dpcd_test_pattern));
2881 core_link_read_dpcd(
2882 link,
3a340294 2883 DP_ADJUST_REQUEST_LANE0_1,
4562236b
HW		 2884 &dpcd_lane_adjustment[0].raw,
2885 sizeof(dpcd_lane_adjustment));
2886
2887 /*get post cursor 2 parameters
2888 * For DP 1.1a or eariler, this DPCD register's value is 0
2889 * For DP 1.2 or later:
2890 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2891 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2892 */
2893 core_link_read_dpcd(
2894 link,
3a340294 2895 DP_ADJUST_REQUEST_POST_CURSOR2,
4562236b
HW		 2896 &dpcd_post_cursor_2_adjustment,
2897 sizeof(dpcd_post_cursor_2_adjustment));
2898
2899 /* translate request */
2900 switch (dpcd_test_pattern.bits.PATTERN) {
2901 case PHY_TEST_PATTERN_D10_2:
2902 test_pattern = DP_TEST_PATTERN_D102;
0e19401f 2903 break;
4562236b
HW		 2904 case PHY_TEST_PATTERN_SYMBOL_ERROR:
2905 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 2906 break;
4562236b
HW		 2907 case PHY_TEST_PATTERN_PRBS7:
2908 test_pattern = DP_TEST_PATTERN_PRBS7;
0e19401f 2909 break;
4562236b
HW		 2910 case PHY_TEST_PATTERN_80BIT_CUSTOM:
2911 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 2912 break;
2913 case PHY_TEST_PATTERN_CP2520_1:
25bab0da 2914 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 2915 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 2916 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2917 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 2918 break;
2919 case PHY_TEST_PATTERN_CP2520_2:
25bab0da 2920 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 2921 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 2922 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2923 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 2924 break;
2925 case PHY_TEST_PATTERN_CP2520_3:
78e685f9 2926 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
0e19401f 2927 break;
4562236b
HW		 2928 default:
2929 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2930 break;
2931 }
2932
5e9ff159
GS		 2933 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2934 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2935 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
4562236b
HW		 2936 core_link_read_dpcd(
2937 link,
3a340294 2938 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
5e9ff159
GS		 2939 test_pattern_buffer,
2940 test_pattern_size);
2941 }
4562236b
HW		 2942
2943 /* prepare link training settings */
d0778ebf 2944 link_settings.link = link->cur_link_settings;
4562236b
HW		 2945
2946 for (lane = 0; lane <
d0778ebf 2947 (unsigned int)(link->cur_link_settings.lane_count);
4562236b
HW		 2948 lane++) {
2949 dpcd_lane_adjust.raw =
2950 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2951 link_settings.lane_settings[lane].VOLTAGE_SWING =
2952 (enum dc_voltage_swing)
2953 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2954 link_settings.lane_settings[lane].PRE_EMPHASIS =
2955 (enum dc_pre_emphasis)
2956 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2957 link_settings.lane_settings[lane].POST_CURSOR2 =
2958 (enum dc_post_cursor2)
2959 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2960 }
2961
2962 for (i = 0; i < 4; i++)
2963 link_training_settings.lane_settings[i] =
2964 link_settings.lane_settings[i];
2965 link_training_settings.link_settings = link_settings.link;
2966 link_training_settings.allow_invalid_msa_timing_param = false;
2967 /*Usage: Measure DP physical lane signal
2968 * by DP SI test equipment automatically.
2969 * PHY test pattern request is generated by equipment via HPD interrupt.
2970 * HPD needs to be active all the time. HPD should be active
2971 * all the time. Do not touch it.
2972 * forward request to DS
2973 */
2974 dc_link_dp_set_test_pattern(
d0778ebf 2975 link,
4562236b 2976 test_pattern,
2057b7e1 2977 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
4562236b 2978 &link_training_settings,
5e9ff159
GS		 2979 test_pattern_buffer,
2980 test_pattern_size);
4562236b
HW		 2981}
2982
d0778ebf 2983static void dp_test_send_link_test_pattern(struct dc_link *link)
4562236b
HW		 2984{
2985 union link_test_pattern dpcd_test_pattern;
2986 union test_misc dpcd_test_params;
2987 enum dp_test_pattern test_pattern;
2057b7e1
WL		 2988 enum dp_test_pattern_color_space test_pattern_color_space =
2989 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
ac3a4fa1
QZ		 2990 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2991 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2992 struct pipe_ctx *pipe_ctx = NULL;
2993 int i;
4562236b
HW		 2994
2995 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2996 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2997
ac3a4fa1
QZ		 2998 for (i = 0; i < MAX_PIPES; i++) {
2999 if (pipes[i].stream == NULL)
3000 continue;
3001
3002 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
3003 pipe_ctx = &pipes[i];
3004 break;
3005 }
3006 }
3007
3008 if (pipe_ctx == NULL)
3009 return;
3010
4562236b
HW		 3011 /* get link test pattern and pattern parameters */
3012 core_link_read_dpcd(
3013 link,
3a340294 3014 DP_TEST_PATTERN,
4562236b
HW		 3015 &dpcd_test_pattern.raw,
3016 sizeof(dpcd_test_pattern));
3017 core_link_read_dpcd(
3018 link,
3a340294 3019 DP_TEST_MISC0,
4562236b
HW		 3020 &dpcd_test_params.raw,
3021 sizeof(dpcd_test_params));
3022
3023 switch (dpcd_test_pattern.bits.PATTERN) {
3024 case LINK_TEST_PATTERN_COLOR_RAMP:
3025 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
3026 break;
3027 case LINK_TEST_PATTERN_VERTICAL_BARS:
3028 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
3029 break; /* black and white */
3030 case LINK_TEST_PATTERN_COLOR_SQUARES:
3031 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
3032 TEST_DYN_RANGE_VESA ?
3033 DP_TEST_PATTERN_COLOR_SQUARES :
3034 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
3035 break;
3036 default:
3037 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3038 break;
3039 }
3040
ef65c702
JFZ		 3041 if (dpcd_test_params.bits.CLR_FORMAT == 0)
3042 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
3043 else
3044 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
3045 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
3046 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2057b7e1 3047
ac3a4fa1
QZ		 3048 switch (dpcd_test_params.bits.BPC) {
3049 case 0: // 6 bits
3050 requestColorDepth = COLOR_DEPTH_666;
3051 break;
3052 case 1: // 8 bits
3053 requestColorDepth = COLOR_DEPTH_888;
3054 break;
3055 case 2: // 10 bits
3056 requestColorDepth = COLOR_DEPTH_101010;
3057 break;
3058 case 3: // 12 bits
3059 requestColorDepth = COLOR_DEPTH_121212;
3060 break;
3061 default:
3062 break;
3063 }
3064
98ad74c6
IB		 3065 switch (dpcd_test_params.bits.CLR_FORMAT) {
3066 case 0:
3067 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3068 break;
3069 case 1:
3070 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
3071 break;
3072 case 2:
3073 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
3074 break;
3075 default:
3076 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3077 break;
3078 }
3079
3080
ac3a4fa1
QZ		 3081 if (requestColorDepth != COLOR_DEPTH_UNDEFINED
3082 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
92589020
QZ		 3083 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
3084 __func__,
3085 pipe_ctx->stream->timing.display_color_depth,
3086 requestColorDepth);
ac3a4fa1 3087 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
ac3a4fa1
QZ		 3088 }
3089
98ad74c6
IB		 3090 dp_update_dsc_config(pipe_ctx);
3091
4562236b 3092 dc_link_dp_set_test_pattern(
d0778ebf 3093 link,
4562236b 3094 test_pattern,
2057b7e1 3095 test_pattern_color_space,
4562236b
HW		 3096 NULL,
3097 NULL,
3098 0);
3099}
3100
8c8048f2 3101static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3102{
3103 union audio_test_mode dpcd_test_mode = {0};
3104 struct audio_test_pattern_type dpcd_pattern_type = {0};
3105 union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3106 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3107
3108 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3109 struct pipe_ctx *pipe_ctx = &pipes[0];
3110 unsigned int channel_count;
3111 unsigned int channel = 0;
3112 unsigned int modes = 0;
3113 unsigned int sampling_rate_in_hz = 0;
3114
3115 // get audio test mode and test pattern parameters
3116 core_link_read_dpcd(
3117 link,
3118 DP_TEST_AUDIO_MODE,
3119 &dpcd_test_mode.raw,
3120 sizeof(dpcd_test_mode));
3121
3122 core_link_read_dpcd(
3123 link,
3124 DP_TEST_AUDIO_PATTERN_TYPE,
3125 &dpcd_pattern_type.value,
3126 sizeof(dpcd_pattern_type));
3127
3128 channel_count = dpcd_test_mode.bits.channel_count + 1;
3129
3130 // read pattern periods for requested channels when sawTooth pattern is requested
3131 if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3132 dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3133
3134 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3135 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3136 // read period for each channel
3137 for (channel = 0; channel < channel_count; channel++) {
3138 core_link_read_dpcd(
3139 link,
3140 DP_TEST_AUDIO_PERIOD_CH1 + channel,
3141 &dpcd_pattern_period[channel].raw,
3142 sizeof(dpcd_pattern_period[channel]));
3143 }
3144 }
3145
3146 // translate sampling rate
3147 switch (dpcd_test_mode.bits.sampling_rate) {
3148 case AUDIO_SAMPLING_RATE_32KHZ:
3149 sampling_rate_in_hz = 32000;
3150 break;
3151 case AUDIO_SAMPLING_RATE_44_1KHZ:
3152 sampling_rate_in_hz = 44100;
3153 break;
3154 case AUDIO_SAMPLING_RATE_48KHZ:
3155 sampling_rate_in_hz = 48000;
3156 break;
3157 case AUDIO_SAMPLING_RATE_88_2KHZ:
3158 sampling_rate_in_hz = 88200;
3159 break;
3160 case AUDIO_SAMPLING_RATE_96KHZ:
3161 sampling_rate_in_hz = 96000;
3162 break;
3163 case AUDIO_SAMPLING_RATE_176_4KHZ:
3164 sampling_rate_in_hz = 176400;
3165 break;
3166 case AUDIO_SAMPLING_RATE_192KHZ:
3167 sampling_rate_in_hz = 192000;
3168 break;
3169 default:
3170 sampling_rate_in_hz = 0;
3171 break;
3172 }
3173
3174 link->audio_test_data.flags.test_requested = 1;
3175 link->audio_test_data.flags.disable_video = disable_video;
3176 link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3177 link->audio_test_data.channel_count = channel_count;
3178 link->audio_test_data.pattern_type = test_pattern;
3179
3180 if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3181 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3182 link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3183 }
3184 }
3185}
3186
d0778ebf 3187static void handle_automated_test(struct dc_link *link)
4562236b
HW		 3188{
3189 union test_request test_request;
3190 union test_response test_response;
3191
3192 memset(&test_request, 0, sizeof(test_request));
3193 memset(&test_response, 0, sizeof(test_response));
3194
3195 core_link_read_dpcd(
3196 link,
3a340294 3197 DP_TEST_REQUEST,
4562236b
HW		 3198 &test_request.raw,
3199 sizeof(union test_request));
3200 if (test_request.bits.LINK_TRAINING) {
3201 /* ACK first to let DP RX test box monitor LT sequence */
3202 test_response.bits.ACK = 1;
3203 core_link_write_dpcd(
3204 link,
3a340294 3205 DP_TEST_RESPONSE,
4562236b
HW		 3206 &test_response.raw,
3207 sizeof(test_response));
3208 dp_test_send_link_training(link);
3209 /* no acknowledge request is needed again */
3210 test_response.bits.ACK = 0;
3211 }
3212 if (test_request.bits.LINK_TEST_PATTRN) {
3213 dp_test_send_link_test_pattern(link);
75a74755 3214 test_response.bits.ACK = 1;
4562236b 3215 }
8c8048f2 3216
3217 if (test_request.bits.AUDIO_TEST_PATTERN) {
3218 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3219 test_response.bits.ACK = 1;
3220 }
3221
4562236b
HW		 3222 if (test_request.bits.PHY_TEST_PATTERN) {
3223 dp_test_send_phy_test_pattern(link);
3224 test_response.bits.ACK = 1;
3225 }
a6729a5a 3226
4562236b
HW		 3227 /* send request acknowledgment */
3228 if (test_response.bits.ACK)
3229 core_link_write_dpcd(
3230 link,
3a340294 3231 DP_TEST_RESPONSE,
4562236b
HW		 3232 &test_response.raw,
3233 sizeof(test_response));
3234}
3235
4e18814e 3236bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
4562236b 3237{
9a6a8075 3238 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
c2e218dd 3239 union device_service_irq device_service_clear = { { 0 } };
d6258eaa 3240 enum dc_status result;
4562236b 3241 bool status = false;
48af9b91
AL		 3242 struct pipe_ctx *pipe_ctx;
3243 int i;
4e18814e
FD		 3244
3245 if (out_link_loss)
3246 *out_link_loss = false;
4562236b
HW		 3247 /* For use cases related to down stream connection status change,
3248 * PSR and device auto test, refer to function handle_sst_hpd_irq
3249 * in DAL2.1*/
3250
1296423b 3251 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
d0778ebf 3252 __func__, link->link_index);
4562236b 3253
8ee65d7c 3254
4562236b
HW		 3255 /* All the "handle_hpd_irq_xxx()" methods
3256 * should be called only after
3257 * dal_dpsst_ls_read_hpd_irq_data
3258 * Order of calls is important too
3259 */
3260 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
8ee65d7c
WL		 3261 if (out_hpd_irq_dpcd_data)
3262 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4562236b
HW		 3263
3264 if (result != DC_OK) {
1296423b 3265 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
4562236b
HW		 3266 __func__);
3267 return false;
3268 }
3269
3270 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3271 device_service_clear.bits.AUTOMATED_TEST = 1;
3272 core_link_write_dpcd(
3273 link,
3a340294 3274 DP_DEVICE_SERVICE_IRQ_VECTOR,
4562236b
HW		 3275 &device_service_clear.raw,
3276 sizeof(device_service_clear.raw));
3277 device_service_clear.raw = 0;
3278 handle_automated_test(link);
3279 return false;
3280 }
3281
3282 if (!allow_hpd_rx_irq(link)) {
1296423b 3283 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
d0778ebf 3284 __func__, link->link_index);
4562236b
HW		 3285 return false;
3286 }
3287
3288 if (handle_hpd_irq_psr_sink(link))
3289 /* PSR-related error was detected and handled */
3290 return true;
3291
3292 /* If PSR-related error handled, Main link may be off,
3293 * so do not handle as a normal sink status change interrupt.
3294 */
3295
aaa15026
WL		 3296 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3297 return true;
3298
4562236b 3299 /* check if we have MST msg and return since we poll for it */
aaa15026 3300 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
4562236b
HW		 3301 return false;
3302
3303 /* For now we only handle 'Downstream port status' case.
3304 * If we got sink count changed it means
3305 * Downstream port status changed,
e97ed496
AK		 3306 * then DM should call DC to do the detection.
3307 * NOTE: Do not handle link loss on eDP since it is internal link*/
3308 if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3309 hpd_rx_irq_check_link_loss_status(
3310 link,
3311 &hpd_irq_dpcd_data)) {
4562236b
HW		 3312 /* Connectivity log: link loss */
3313 CONN_DATA_LINK_LOSS(link,
3314 hpd_irq_dpcd_data.raw,
3315 sizeof(hpd_irq_dpcd_data),
3316 "Status: ");
3317
48af9b91
AL		 3318 for (i = 0; i < MAX_PIPES; i++) {
3319 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
832aa63b
PH		 3320 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3321 break;
3322 }
3323
3324 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3325 return false;
3326
832aa63b 3327
68423dab
AC		 3328 for (i = 0; i < MAX_PIPES; i++) {
3329 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3330 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
617ab854 3331 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
68423dab
AC		 3332 core_link_disable_stream(pipe_ctx);
3333 }
48af9b91 3334
422d9091
XY		 3335 for (i = 0; i < MAX_PIPES; i++) {
3336 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
68423dab 3337 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
617ab854 3338 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
68423dab 3339 core_link_enable_stream(link->dc->current_state, pipe_ctx);
422d9091
XY		 3340 }
3341
4562236b 3342 status = false;
4e18814e
FD		 3343 if (out_link_loss)
3344 *out_link_loss = true;
4562236b
HW		 3345 }
3346
36c9137b 3347 if (link->type == dc_connection_sst_branch &&
4562236b
HW		 3348 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3349 != link->dpcd_sink_count)
3350 status = true;
3351
3352 /* reasons for HPD RX:
3353 * 1. Link Loss - ie Re-train the Link
3354 * 2. MST sideband message
3355 * 3. Automated Test - ie. Internal Commit
3356 * 4. CP (copy protection) - (not interesting for DM???)
3357 * 5. DRR
3358 * 6. Downstream Port status changed
3359 * -ie. Detect - this the only one
3360 * which is interesting for DM because
3361 * it must call dc_link_detect.
3362 */
3363 return status;
3364}
3365
3366/*query dpcd for version and mst cap addresses*/
d0778ebf 3367bool is_mst_supported(struct dc_link *link)
4562236b
HW		 3368{
3369 bool mst = false;
3370 enum dc_status st = DC_OK;
3371 union dpcd_rev rev;
3372 union mstm_cap cap;
3373
0b226322
DG		 3374 if (link->preferred_training_settings.mst_enable &&
3375 *link->preferred_training_settings.mst_enable == false) {
3376 return false;
3377 }
3378
4562236b
HW		 3379 rev.raw = 0;
3380 cap.raw = 0;
3381
3a340294 3382 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4562236b
HW		 3383 sizeof(rev));
3384
3385 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3386
3a340294 3387 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4562236b
HW		 3388 &cap.raw, sizeof(cap));
3389 if (st == DC_OK && cap.bits.MST_CAP == 1)
3390 mst = true;
3391 }
3392 return mst;
3393
3394}
3395
d0778ebf 3396bool is_dp_active_dongle(const struct dc_link *link)
36c9137b
DZ		 3397{
3398 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3399 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3400}
3401
3402bool is_dp_branch_device(const struct dc_link *link)
4562236b 3403{
a504ad26 3404 return link->dpcd_caps.is_branch_dev;
4562236b
HW		 3405}
3406
6bffebc9
EY		 3407static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3408{
3409 switch (bpc) {
3410 case DOWN_STREAM_MAX_8BPC:
3411 return 8;
3412 case DOWN_STREAM_MAX_10BPC:
3413 return 10;
3414 case DOWN_STREAM_MAX_12BPC:
3415 return 12;
3416 case DOWN_STREAM_MAX_16BPC:
3417 return 16;
3418 default:
3419 break;
3420 }
3421
3422 return -1;
3423}
3424
ee13cea9
JB		 3425static void read_dp_device_vendor_id(struct dc_link *link)
3426{
3427 struct dp_device_vendor_id dp_id;
3428
3429 /* read IEEE branch device id */
3430 core_link_read_dpcd(
3431 link,
3432 DP_BRANCH_OUI,
3433 (uint8_t *)&dp_id,
3434 sizeof(dp_id));
3435
3436 link->dpcd_caps.branch_dev_id =
3437 (dp_id.ieee_oui[0] << 16) +
3438 (dp_id.ieee_oui[1] << 8) +
3439 dp_id.ieee_oui[2];
3440
3441 memmove(
3442 link->dpcd_caps.branch_dev_name,
3443 dp_id.ieee_device_id,
3444 sizeof(dp_id.ieee_device_id));
3445}
3446
3447
3448
4562236b 3449static void get_active_converter_info(
d0778ebf 3450 uint8_t data, struct dc_link *link)
4562236b
HW		 3451{
3452 union dp_downstream_port_present ds_port = { .byte = data };
dd998291 3453 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
4562236b
HW		 3454
3455 /* decode converter info*/
3456 if (!ds_port.fields.PORT_PRESENT) {
3457 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
d0778ebf 3458 ddc_service_set_dongle_type(link->ddc,
4562236b 3459 link->dpcd_caps.dongle_type);
ac3d76e0 3460 link->dpcd_caps.is_branch_dev = false;
4562236b
HW		 3461 return;
3462 }
3463
a504ad26 3464 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
9413b23f 3465 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
a504ad26 3466
4562236b
HW		 3467 switch (ds_port.fields.PORT_TYPE) {
3468 case DOWNSTREAM_VGA:
3469 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3470 break;
7a83645a
DZ		 3471 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3472 /* At this point we don't know is it DVI or HDMI or DP++,
4562236b
HW		 3473 * assume DVI.*/
3474 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3475 break;
3476 default:
3477 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3478 break;
3479 }
3480
ac0e562c 3481 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
242b0c8f 3482 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
4562236b
HW		 3483 union dwnstream_port_caps_byte0 *port_caps =
3484 (union dwnstream_port_caps_byte0 *)det_caps;
5aedc7bc 3485 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3486 det_caps, sizeof(det_caps)) == DC_OK) {
4562236b 3487
5aedc7bc 3488 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3489 /*Handle DP case as DONGLE_NONE*/
3490 case DOWN_STREAM_DETAILED_DP:
3491 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3492 break;
3493 case DOWN_STREAM_DETAILED_VGA:
3494 link->dpcd_caps.dongle_type =
3495 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3496 break;
3497 case DOWN_STREAM_DETAILED_DVI:
3498 link->dpcd_caps.dongle_type =
3499 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3500 break;
3501 case DOWN_STREAM_DETAILED_HDMI:
3502 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3503 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3504 link->dpcd_caps.dongle_type =
3505 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3506
3507 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3508 if (ds_port.fields.DETAILED_CAPS) {
3509
3510 union dwnstream_port_caps_byte3_hdmi
3511 hdmi_caps = {.raw = det_caps[3] };
3512 union dwnstream_port_caps_byte2
3513 hdmi_color_caps = {.raw = det_caps[2] };
3514 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3515 det_caps[1] * 2500;
3516
3517 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3518 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3519 /*YCBCR capability only for HDMI case*/
3520 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3521 == DOWN_STREAM_DETAILED_HDMI) {
3522 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3523 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3524 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3525 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3526 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3527 hdmi_caps.bits.YCrCr422_CONVERSION;
3528 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3529 hdmi_caps.bits.YCrCr420_CONVERSION;
3530 }
3531
3532 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3533 translate_dpcd_max_bpc(
3534 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3535
3536 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3537 link->dpcd_caps.dongle_caps.extendedCapValid = true;
7a83645a 3538 }
03f5c686 3539
5aedc7bc 3540 break;
4562236b 3541 }
4562236b
HW		 3542 }
3543 }
3544
d0778ebf 3545 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4562236b 3546
4562236b
HW		 3547 {
3548 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3549
3550 core_link_read_dpcd(
3551 link,
3a340294 3552 DP_BRANCH_REVISION_START,
4562236b
HW		 3553 (uint8_t *)&dp_hw_fw_revision,
3554 sizeof(dp_hw_fw_revision));
3555
3556 link->dpcd_caps.branch_hw_revision =
3557 dp_hw_fw_revision.ieee_hw_rev;
4b99affb
A		 3558
3559 memmove(
3560 link->dpcd_caps.branch_fw_revision,
3561 dp_hw_fw_revision.ieee_fw_rev,
3562 sizeof(dp_hw_fw_revision.ieee_fw_rev));
4562236b
HW		 3563 }
3564}
3565
d0778ebf 3566static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4562236b
HW		 3567 int length)
3568{
3569 int retry = 0;
4562236b
HW		 3570
3571 if (!link->dpcd_caps.dpcd_rev.raw) {
3572 do {
3573 dp_receiver_power_ctrl(link, true);
3a340294 3574 core_link_read_dpcd(link, DP_DPCD_REV,
4562236b
HW		 3575 dpcd_data, length);
3576 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3a340294
DA		 3577 DP_DPCD_REV -
3578 DP_DPCD_REV];
4562236b
HW		 3579 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3580 }
3581
4562236b
HW		 3582 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3583 switch (link->dpcd_caps.branch_dev_id) {
df3b7e32 3584 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
4562236b
HW		 3585 * all internal circuits including AUX communication preventing
3586 * reading DPCD table and EDID (spec violation).
3587 * Encoder will skip DP RX power down on disable_output to
3588 * keep receiver powered all the time.*/
df3b7e32
QZ		 3589 case DP_BRANCH_DEVICE_ID_0010FA:
3590 case DP_BRANCH_DEVICE_ID_0080E1:
566b4252 3591 case DP_BRANCH_DEVICE_ID_00E04C:
4562236b
HW		 3592 link->wa_flags.dp_keep_receiver_powered = true;
3593 break;
3594
3595 /* TODO: May need work around for other dongles. */
3596 default:
3597 link->wa_flags.dp_keep_receiver_powered = false;
3598 break;
3599 }
3600 } else
3601 link->wa_flags.dp_keep_receiver_powered = false;
3602}
3603
96577cf8
HW		 3604/* Read additional sink caps defined in source specific DPCD area
3605 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3606 */
3607static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3608{
3609 uint8_t dpcd_data;
3610
3611 if (!link)
3612 return false;
3613
3614 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3615 return false;
3616
3617 link->dpcd_sink_ext_caps.raw = dpcd_data;
3618 return true;
3619}
3620
ee9b1992 3621bool dp_retrieve_lttpr_cap(struct dc_link *link)
4562236b 3622{
61aa7a6f 3623 uint8_t lttpr_dpcd_data[6];
7809fc00
WC		 3624 bool vbios_lttpr_enable = false;
3625 bool vbios_lttpr_interop = false;
3626 struct dc_bios *bios = link->dc->ctx->dc_bios;
ee9b1992
WC		 3627 enum dc_status status = DC_ERROR_UNEXPECTED;
3628 bool is_lttpr_present = false;
8e5100a5 3629
61aa7a6f 3630 memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
7809fc00
WC		 3631 /* Query BIOS to determine if LTTPR functionality is forced on by system */
3632 if (bios->funcs->get_lttpr_caps) {
3633 enum bp_result bp_query_result;
3634 uint8_t is_vbios_lttpr_enable = 0;
3635
3636 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3637 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3638 }
3639
3640 if (bios->funcs->get_lttpr_interop) {
3641 enum bp_result bp_query_result;
3642 uint8_t is_vbios_interop_enabled = 0;
3643
3644 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3645 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3646 }
3647
3648 /*
3649 * Logic to determine LTTPR mode
3650 */
3651 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3652 if (vbios_lttpr_enable && vbios_lttpr_interop)
3653 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3654 else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3655 if (link->dc->config.allow_lttpr_non_transparent_mode)
3656 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3657 else
3658 link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3659 } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3660 if (!link->dc->config.allow_lttpr_non_transparent_mode
3661 || !link->dc->caps.extended_aux_timeout_support)
3662 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3663 else
3664 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3665 }
3666
3667 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
c797ede0 3668 /* By reading LTTPR capability, RX assumes that we will enable
7809fc00 3669 * LTTPR extended aux timeout if LTTPR is present.
c797ede0 3670 */
8e5100a5 3671 status = core_link_read_dpcd(
3672 link,
61aa7a6f 3673 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3674 lttpr_dpcd_data,
3675 sizeof(lttpr_dpcd_data));
3676
3677 link->dpcd_caps.lttpr_caps.revision.raw =
3678 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3679 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3680
3681 link->dpcd_caps.lttpr_caps.max_link_rate =
3682 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3683 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3684
3685 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3686 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3687 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3688
3689 link->dpcd_caps.lttpr_caps.max_lane_count =
3690 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3691 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3692
3693 link->dpcd_caps.lttpr_caps.mode =
3694 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3695 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3696
3697 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3698 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3699 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3700
ede4f6da 3701 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
788797c7 3702 is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
61aa7a6f 3703 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3704 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
c797ede0 3705 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
ac62875e 3706 if (is_lttpr_present) {
c797ede0 3707 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
ac62875e
WC		 3708 configure_lttpr_mode_transparent(link);
3709 } else
fab85801 3710 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
a1500a62 3711 }
ee9b1992
WC		 3712 return is_lttpr_present;
3713}
3714
3715static bool retrieve_link_cap(struct dc_link *link)
3716{
3717 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3718 * which means size 16 will be good for both of those DPCD register block reads
3719 */
3720 uint8_t dpcd_data[16];
3721 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3722 */
3723 uint8_t dpcd_dprx_data = '\0';
3724 uint8_t dpcd_power_state = '\0';
3725
3726 struct dp_device_vendor_id sink_id;
3727 union down_stream_port_count down_strm_port_count;
3728 union edp_configuration_cap edp_config_cap;
3729 union dp_downstream_port_present ds_port = { 0 };
3730 enum dc_status status = DC_ERROR_UNEXPECTED;
3731 uint32_t read_dpcd_retry_cnt = 3;
3732 int i;
3733 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3734 const uint32_t post_oui_delay = 30; // 30ms
3735 bool is_lttpr_present = false;
3736
3737 memset(dpcd_data, '\0', sizeof(dpcd_data));
3738 memset(&down_strm_port_count,
3739 '\0', sizeof(union down_stream_port_count));
3740 memset(&edp_config_cap, '\0',
3741 sizeof(union edp_configuration_cap));
3742
3743 /* if extended timeout is supported in hardware,
3744 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3745 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3746 */
3747 dc_link_aux_try_to_configure_timeout(link->ddc,
3748 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
fb8cf277 3749
ee9b1992 3750 is_lttpr_present = dp_retrieve_lttpr_cap(link);
c797ede0
WL		 3751 if (!is_lttpr_present)
3752 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3753
3754
0abda674
WC		 3755 status = core_link_read_dpcd(link, DP_SET_POWER,
3756 &dpcd_power_state, sizeof(dpcd_power_state));
3757
3758 /* Delay 1 ms if AUX CH is in power down state. Based on spec
3759 * section 2.3.1.2, if AUX CH may be powered down due to
3760 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3761 * signal and may need up to 1 ms before being able to reply.
3762 */
3763 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3764 udelay(1000);
3765
3766 dpcd_set_source_specific_data(link);
3767 /* Sink may need to configure internals based on vendor, so allow some
3768 * time before proceeding with possibly vendor specific transactions
3769 */
3770 msleep(post_oui_delay);
3771
3772 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3773 status = core_link_read_dpcd(
3774 link,
3775 DP_DPCD_REV,
3776 dpcd_data,
3777 sizeof(dpcd_data));
3778 if (status == DC_OK)
3779 break;
3780 }
3781
3782
3783 if (status != DC_OK) {
3784 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
3785 return false;
3786 }
3787
4562236b
HW		 3788 {
3789 union training_aux_rd_interval aux_rd_interval;
3790
3791 aux_rd_interval.raw =
3a340294 3792 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
4562236b 3793
3c7dd2cb 3794 link->dpcd_caps.ext_receiver_cap_field_present =
b239b59b 3795 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3c7dd2cb
HT		 3796
3797 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
818832bf
XY		 3798 uint8_t ext_cap_data[16];
3799
3800 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3801 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3802 status = core_link_read_dpcd(
4562236b 3803 link,
3a340294 3804 DP_DP13_DPCD_REV,
818832bf
XY		 3805 ext_cap_data,
3806 sizeof(ext_cap_data));
3807 if (status == DC_OK) {
3808 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3809 break;
3810 }
3811 }
3812 if (status != DC_OK)
3813 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
4562236b
HW		 3814 }
3815 }
3816
3c7dd2cb
HT		 3817 link->dpcd_caps.dpcd_rev.raw =
3818 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3819
7715fdf3 3820 if (link->dpcd_caps.ext_receiver_cap_field_present) {
3c7dd2cb
HT		 3821 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3822 status = core_link_read_dpcd(
3823 link,
3824 DP_DPRX_FEATURE_ENUMERATION_LIST,
3825 &dpcd_dprx_data,
3826 sizeof(dpcd_dprx_data));
3827 if (status == DC_OK)
3828 break;
3829 }
3830
3831 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3832
3833 if (status != DC_OK)
3834 dm_error("%s: Read DPRX caps data failed.\n", __func__);
3835 }
3836
3837 else {
3838 link->dpcd_caps.dprx_feature.raw = 0;
3839 }
3840
3841
07d6a199
AK		 3842 /* Error condition checking...
3843 * It is impossible for Sink to report Max Lane Count = 0.
3844 * It is possible for Sink to report Max Link Rate = 0, if it is
3845 * an eDP device that is reporting specialized link rates in the
3846 * SUPPORTED_LINK_RATE table.
3847 */
3848 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3849 return false;
3850
3a340294
DA		 3851 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3852 DP_DPCD_REV];
4562236b 3853
ee13cea9
JB		 3854 read_dp_device_vendor_id(link);
3855
4562236b
HW		 3856 get_active_converter_info(ds_port.byte, link);
3857
3858 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3859
98e6436d
AK		 3860 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3861 DP_DPCD_REV];
3862
4562236b
HW		 3863 link->dpcd_caps.allow_invalid_MSA_timing_param =
3864 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3865
3866 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3a340294 3867 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4562236b
HW		 3868
3869 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3a340294 3870 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4562236b 3871
d0778ebf 3872 link->reported_link_cap.lane_count =
4562236b 3873 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
d0778ebf 3874 link->reported_link_cap.link_rate = dpcd_data[
3a340294 3875 DP_MAX_LINK_RATE - DP_DPCD_REV];
d0778ebf 3876 link->reported_link_cap.link_spread =
4562236b
HW		 3877 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3878 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3879
3880 edp_config_cap.raw = dpcd_data[
3a340294 3881 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4562236b
HW		 3882 link->dpcd_caps.panel_mode_edp =
3883 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
9799624a
WL		 3884 link->dpcd_caps.dpcd_display_control_capable =
3885 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4562236b 3886
d0778ebf
HW		 3887 link->test_pattern_enabled = false;
3888 link->compliance_test_state.raw = 0;
4562236b 3889
4562236b
HW		 3890 /* read sink count */
3891 core_link_read_dpcd(link,
3a340294 3892 DP_SINK_COUNT,
4562236b
HW		 3893 &link->dpcd_caps.sink_count.raw,
3894 sizeof(link->dpcd_caps.sink_count.raw));
3895
8ca80900
AK		 3896 /* read sink ieee oui */
3897 core_link_read_dpcd(link,
3898 DP_SINK_OUI,
3899 (uint8_t *)(&sink_id),
3900 sizeof(sink_id));
3901
3902 link->dpcd_caps.sink_dev_id =
3903 (sink_id.ieee_oui[0] << 16) +
3904 (sink_id.ieee_oui[1] << 8) +
3905 (sink_id.ieee_oui[2]);
3906
4b99affb
A		 3907 memmove(
3908 link->dpcd_caps.sink_dev_id_str,
3909 sink_id.ieee_device_id,
3910 sizeof(sink_id.ieee_device_id));
3911
473e3f77
MK		 3912 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3913 {
3914 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3915
3916 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3917 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3918 sizeof(str_mbp_2017))) {
3919 link->reported_link_cap.link_rate = 0x0c;
3920 }
3921 }
3922
4b99affb
A		 3923 core_link_read_dpcd(
3924 link,
3925 DP_SINK_HW_REVISION_START,
3926 (uint8_t *)&dp_hw_fw_revision,
3927 sizeof(dp_hw_fw_revision));
3928
3929 link->dpcd_caps.sink_hw_revision =
3930 dp_hw_fw_revision.ieee_hw_rev;
3931
3932 memmove(
3933 link->dpcd_caps.sink_fw_revision,
3934 dp_hw_fw_revision.ieee_fw_rev,
3935 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3936
39a4eb85
WL		 3937 memset(&link->dpcd_caps.dsc_caps, '\0',
3938 sizeof(link->dpcd_caps.dsc_caps));
97bda032
HW		 3939 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3940 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3941 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
97bda032
HW		 3942 status = core_link_read_dpcd(
3943 link,
3944 DP_FEC_CAPABILITY,
3945 &link->dpcd_caps.fec_cap.raw,
3946 sizeof(link->dpcd_caps.fec_cap.raw));
39a4eb85
WL		 3947 status = core_link_read_dpcd(
3948 link,
3949 DP_DSC_SUPPORT,
3950 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3951 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3952 status = core_link_read_dpcd(
3953 link,
3954 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
6d824ed5
WL		 3955 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3956 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
97bda032 3957 }
6fbefb84 3958
96577cf8
HW		 3959 if (!dpcd_read_sink_ext_caps(link))
3960 link->dpcd_sink_ext_caps.raw = 0;
3961
4562236b
HW		 3962 /* Connectivity log: detection */
3963 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
cdb39798
YS		 3964
3965 return true;
4562236b
HW		 3966}
3967
8547058b
LH		 3968bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3969{
3970 uint8_t dpcd_data[16];
3971 uint32_t read_dpcd_retry_cnt = 3;
3972 enum dc_status status = DC_ERROR_UNEXPECTED;
3973 union dp_downstream_port_present ds_port = { 0 };
3974 union down_stream_port_count down_strm_port_count;
3975 union edp_configuration_cap edp_config_cap;
3976
3977 int i;
3978
3979 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3980 status = core_link_read_dpcd(
3981 link,
3982 DP_DPCD_REV,
3983 dpcd_data,
3984 sizeof(dpcd_data));
3985 if (status == DC_OK)
3986 break;
3987 }
3988
3989 link->dpcd_caps.dpcd_rev.raw =
3990 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3991
3992 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3993 return false;
3994
3995 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3996 DP_DPCD_REV];
3997
3998 get_active_converter_info(ds_port.byte, link);
3999
4000 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
4001 DP_DPCD_REV];
4002
4003 link->dpcd_caps.allow_invalid_MSA_timing_param =
4004 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
4005
4006 link->dpcd_caps.max_ln_count.raw = dpcd_data[
4007 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4008
4009 link->dpcd_caps.max_down_spread.raw = dpcd_data[
4010 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4011
4012 link->reported_link_cap.lane_count =
4013 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
4014 link->reported_link_cap.link_rate = dpcd_data[
4015 DP_MAX_LINK_RATE - DP_DPCD_REV];
4016 link->reported_link_cap.link_spread =
4017 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
4018 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
4019
4020 edp_config_cap.raw = dpcd_data[
4021 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4022 link->dpcd_caps.panel_mode_edp =
4023 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
4024 link->dpcd_caps.dpcd_display_control_capable =
4025 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4026
4027 return true;
4028}
4029
cdb39798 4030bool detect_dp_sink_caps(struct dc_link *link)
4562236b 4031{
cdb39798 4032 return retrieve_link_cap(link);
4562236b
HW		 4033
4034 /* dc init_hw has power encoder using default
4035 * signal for connector. For native DP, no
4036 * need to power up encoder again. If not native
4037 * DP, hw_init may need check signal or power up
4038 * encoder here.
4039 */
4562236b
HW		 4040 /* TODO save sink caps in link->sink */
4041}
4042
d308d0b4 4043static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
b03a599b
DL		 4044{
4045 enum dc_link_rate link_rate;
4046 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
4047 switch (link_rate_in_khz) {
4048 case 1620000:
4049 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
4050 break;
4051 case 2160000:
4052 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
4053 break;
4054 case 2430000:
4055 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
4056 break;
4057 case 2700000:
4058 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
4059 break;
4060 case 3240000:
4061 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
4062 break;
4063 case 4320000:
4064 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
4065 break;
4066 case 5400000:
4067 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
4068 break;
4069 case 8100000:
4070 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
4071 break;
4072 default:
4073 link_rate = LINK_RATE_UNKNOWN;
4074 break;
4075 }
4076 return link_rate;
4077}
4078
4654a2f7
RL		 4079void detect_edp_sink_caps(struct dc_link *link)
4080{
8628d02f 4081 uint8_t supported_link_rates[16];
b03a599b
DL		 4082 uint32_t entry;
4083 uint32_t link_rate_in_khz;
4084 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
65e870df 4085 uint8_t backlight_adj_cap;
48231fd5 4086
b03a599b 4087 retrieve_link_cap(link);
8628d02f
JP		 4088 link->dpcd_caps.edp_supported_link_rates_count = 0;
4089 memset(supported_link_rates, 0, sizeof(supported_link_rates));
48231fd5 4090
67c268a5
ZL		 4091 /*
4092 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
4093 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
4094 */
4095 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
66611a72 4096 (link->dc->debug.optimize_edp_link_rate ||
53c81fc7 4097 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
b03a599b
DL		 4098 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4099 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4100 supported_link_rates, sizeof(supported_link_rates));
4101
b03a599b
DL		 4102 for (entry = 0; entry < 16; entry += 2) {
4103 // DPCD register reports per-lane link rate = 16-bit link rate capability
8628d02f 4104 // value X 200 kHz. Need multiplier to find link rate in kHz.
b03a599b
DL		 4105 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4106 supported_link_rates[entry]) * 200;
4107
4108 if (link_rate_in_khz != 0) {
4109 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
8628d02f
JP		 4110 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4111 link->dpcd_caps.edp_supported_link_rates_count++;
53c81fc7
WC		 4112
4113 if (link->reported_link_cap.link_rate < link_rate)
4114 link->reported_link_cap.link_rate = link_rate;
b03a599b
DL		 4115 }
4116 }
4117 }
4654a2f7 4118 link->verified_link_cap = link->reported_link_cap;
96577cf8 4119
65e870df
RC		 4120 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4121 &backlight_adj_cap, sizeof(backlight_adj_cap));
4122
4123 link->dpcd_caps.dynamic_backlight_capable_edp =
4124 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4125
96577cf8 4126 dc_link_set_default_brightness_aux(link);
4654a2f7
RL		 4127}
4128
4562236b
HW		 4129void dc_link_dp_enable_hpd(const struct dc_link *link)
4130{
d0778ebf 4131 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 4132
4133 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4134 encoder->funcs->enable_hpd(encoder);
4135}
4136
4137void dc_link_dp_disable_hpd(const struct dc_link *link)
4138{
d0778ebf 4139 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 4140
4141 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4142 encoder->funcs->disable_hpd(encoder);
4143}
4144
4145static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4146{
0e19401f
TC		 4147 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4148 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4149 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4562236b
HW		 4150 return true;
4151 else
4152 return false;
4153}
4154
d0778ebf 4155static void set_crtc_test_pattern(struct dc_link *link,
4562236b 4156 struct pipe_ctx *pipe_ctx,
2057b7e1
WL		 4157 enum dp_test_pattern test_pattern,
4158 enum dp_test_pattern_color_space test_pattern_color_space)
4562236b
HW		 4159{
4160 enum controller_dp_test_pattern controller_test_pattern;
4161 enum dc_color_depth color_depth = pipe_ctx->
4fa086b9 4162 stream->timing.display_color_depth;
4562236b 4163 struct bit_depth_reduction_params params;
661a8cd9 4164 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
6fbefb84
HW		 4165 int width = pipe_ctx->stream->timing.h_addressable +
4166 pipe_ctx->stream->timing.h_border_left +
4167 pipe_ctx->stream->timing.h_border_right;
4168 int height = pipe_ctx->stream->timing.v_addressable +
4169 pipe_ctx->stream->timing.v_border_bottom +
4170 pipe_ctx->stream->timing.v_border_top;
4562236b
HW		 4171
4172 memset(&params, 0, sizeof(params));
4173
4174 switch (test_pattern) {
4175 case DP_TEST_PATTERN_COLOR_SQUARES:
4176 controller_test_pattern =
4177 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4178 break;
4179 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4180 controller_test_pattern =
4181 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4182 break;
4183 case DP_TEST_PATTERN_VERTICAL_BARS:
4184 controller_test_pattern =
4185 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4186 break;
4187 case DP_TEST_PATTERN_HORIZONTAL_BARS:
4188 controller_test_pattern =
4189 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4190 break;
4191 case DP_TEST_PATTERN_COLOR_RAMP:
4192 controller_test_pattern =
4193 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4194 break;
4195 default:
4196 controller_test_pattern =
4197 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4198 break;
4199 }
4200
4201 switch (test_pattern) {
4202 case DP_TEST_PATTERN_COLOR_SQUARES:
4203 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4204 case DP_TEST_PATTERN_VERTICAL_BARS:
4205 case DP_TEST_PATTERN_HORIZONTAL_BARS:
4206 case DP_TEST_PATTERN_COLOR_RAMP:
4207 {
4208 /* disable bit depth reduction */
4209 pipe_ctx->stream->bit_depth_params = params;
661a8cd9 4210 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
7f93c1de
CL		 4211 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4212 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b 4213 controller_test_pattern, color_depth);
dbf5256b 4214 else if (link->dc->hwss.set_disp_pattern_generator) {
b1f6d01c 4215 struct pipe_ctx *odm_pipe;
2057b7e1 4216 enum controller_dp_color_space controller_color_space;
b1f6d01c 4217 int opp_cnt = 1;
10b4e64e
WL		 4218 int offset = 0;
4219 int dpg_width = width;
6fbefb84 4220
2057b7e1
WL		 4221 switch (test_pattern_color_space) {
4222 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4223 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4224 break;
4225 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4226 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4227 break;
4228 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4229 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4230 break;
4231 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4232 default:
4233 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4234 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4235 ASSERT(0);
4236 break;
4237 }
4238
b1f6d01c
DL		 4239 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4240 opp_cnt++;
10b4e64e
WL		 4241 dpg_width = width / opp_cnt;
4242 offset = dpg_width;
6fbefb84 4243
dbf5256b
JA		 4244 link->dc->hwss.set_disp_pattern_generator(link->dc,
4245 pipe_ctx,
6fbefb84 4246 controller_test_pattern,
2057b7e1 4247 controller_color_space,
6fbefb84
HW		 4248 color_depth,
4249 NULL,
10b4e64e
WL		 4250 dpg_width,
4251 height,
dbf5256b
JA		 4252 0);
4253
4254 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4255 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4256
4257 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4258 link->dc->hwss.set_disp_pattern_generator(link->dc,
4259 odm_pipe,
4260 controller_test_pattern,
4261 controller_color_space,
4262 color_depth,
4263 NULL,
4264 dpg_width,
4265 height,
4266 offset);
10b4e64e 4267 offset += offset;
6fbefb84 4268 }
6fbefb84 4269 }
4562236b
HW		 4270 }
4271 break;
4272 case DP_TEST_PATTERN_VIDEO_MODE:
4273 {
4274 /* restore bitdepth reduction */
661a8cd9 4275 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4562236b 4276 pipe_ctx->stream->bit_depth_params = params;
661a8cd9 4277 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
7f93c1de
CL		 4278 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4279 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 4280 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4281 color_depth);
dbf5256b 4282 else if (link->dc->hwss.set_disp_pattern_generator) {
b1f6d01c
DL		 4283 struct pipe_ctx *odm_pipe;
4284 int opp_cnt = 1;
10b4e64e 4285 int dpg_width = width;
b1f6d01c
DL		 4286
4287 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4288 opp_cnt++;
6fbefb84 4289
10b4e64e 4290 dpg_width = width / opp_cnt;
b1f6d01c
DL		 4291 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4292 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
6fbefb84 4293
b1f6d01c 4294 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
dbf5256b
JA		 4295 link->dc->hwss.set_disp_pattern_generator(link->dc,
4296 odm_pipe,
4297 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4298 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4299 color_depth,
4300 NULL,
4301 dpg_width,
4302 height,
4303 0);
4304 }
4305 link->dc->hwss.set_disp_pattern_generator(link->dc,
4306 pipe_ctx,
6fbefb84 4307 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2057b7e1 4308 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
6fbefb84
HW		 4309 color_depth,
4310 NULL,
10b4e64e
WL		 4311 dpg_width,
4312 height,
4313 0);
6fbefb84 4314 }
4562236b
HW		 4315 }
4316 break;
4317
4318 default:
4319 break;
4320 }
4321}
4322
4323bool dc_link_dp_set_test_pattern(
d0778ebf 4324 struct dc_link *link,
4562236b 4325 enum dp_test_pattern test_pattern,
2057b7e1 4326 enum dp_test_pattern_color_space test_pattern_color_space,
4562236b
HW		 4327 const struct link_training_settings *p_link_settings,
4328 const unsigned char *p_custom_pattern,
4329 unsigned int cust_pattern_size)
4330{
608ac7bb 4331 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
33fd9cb8 4332 struct pipe_ctx *pipe_ctx = NULL;
4562236b
HW		 4333 unsigned int lane;
4334 unsigned int i;
4335 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4336 union dpcd_training_pattern training_pattern;
4562236b
HW		 4337 enum dpcd_phy_test_patterns pattern;
4338
4339 memset(&training_pattern, 0, sizeof(training_pattern));
4562236b
HW		 4340
4341 for (i = 0; i < MAX_PIPES; i++) {
33fd9cb8
QZ		 4342 if (pipes[i].stream == NULL)
4343 continue;
4344
24d01c9b 4345 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
0a8f43ff 4346 pipe_ctx = &pipes[i];
4562236b
HW		 4347 break;
4348 }
4349 }
4350
33fd9cb8
QZ		 4351 if (pipe_ctx == NULL)
4352 return false;
4353
dbf5256b 4354 /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
d0778ebf 4355 if (link->test_pattern_enabled && test_pattern ==
4562236b
HW		 4356 DP_TEST_PATTERN_VIDEO_MODE) {
4357 /* Set CRTC Test Pattern */
2057b7e1 4358 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
d0778ebf 4359 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 4360 (uint8_t *)p_custom_pattern,
4361 (uint32_t)cust_pattern_size);
4362
4363 /* Unblank Stream */
d0778ebf 4364 link->dc->hwss.unblank_stream(
0a8f43ff 4365 pipe_ctx,
d0778ebf 4366 &link->verified_link_cap);
4562236b
HW		 4367 /* TODO:m_pHwss->MuteAudioEndpoint
4368 * (pPathMode->pDisplayPath, false);
4369 */
4370
4371 /* Reset Test Pattern state */
d0778ebf 4372 link->test_pattern_enabled = false;
4562236b
HW		 4373
4374 return true;
4375 }
4376
4377 /* Check for PHY Test Patterns */
4378 if (is_dp_phy_pattern(test_pattern)) {
4379 /* Set DPCD Lane Settings before running test pattern */
4380 if (p_link_settings != NULL) {
64c12b73 4381 dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4382 dpcd_set_lane_settings(link, p_link_settings, DPRX);
4562236b
HW		 4383 }
4384
4385 /* Blank stream if running test pattern */
4386 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4387 /*TODO:
4388 * m_pHwss->
4389 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4390 */
4391 /* Blank stream */
8e9c4c8c 4392 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4562236b
HW		 4393 }
4394
d0778ebf 4395 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 4396 (uint8_t *)p_custom_pattern,
4397 (uint32_t)cust_pattern_size);
4398
4399 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4400 /* Set Test Pattern state */
d0778ebf 4401 link->test_pattern_enabled = true;
4562236b 4402 if (p_link_settings != NULL)
d0778ebf 4403 dpcd_set_link_settings(link,
4562236b
HW		 4404 p_link_settings);
4405 }
4406
4407 switch (test_pattern) {
4408 case DP_TEST_PATTERN_VIDEO_MODE:
4409 pattern = PHY_TEST_PATTERN_NONE;
0e19401f 4410 break;
4562236b
HW		 4411 case DP_TEST_PATTERN_D102:
4412 pattern = PHY_TEST_PATTERN_D10_2;
0e19401f 4413 break;
4562236b
HW		 4414 case DP_TEST_PATTERN_SYMBOL_ERROR:
4415 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 4416 break;
4562236b
HW		 4417 case DP_TEST_PATTERN_PRBS7:
4418 pattern = PHY_TEST_PATTERN_PRBS7;
0e19401f 4419 break;
4562236b
HW		 4420 case DP_TEST_PATTERN_80BIT_CUSTOM:
4421 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 4422 break;
4423 case DP_TEST_PATTERN_CP2520_1:
4424 pattern = PHY_TEST_PATTERN_CP2520_1;
4425 break;
4426 case DP_TEST_PATTERN_CP2520_2:
4427 pattern = PHY_TEST_PATTERN_CP2520_2;
4428 break;
4429 case DP_TEST_PATTERN_CP2520_3:
4430 pattern = PHY_TEST_PATTERN_CP2520_3;
4431 break;
4562236b
HW		 4432 default:
4433 return false;
4434 }
4435
4436 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4437 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4438 return false;
4439
d0778ebf 4440 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 4441 /* tell receiver that we are sending qualification
4442 * pattern DP 1.2 or later - DP receiver's link quality
4443 * pattern is set using DPCD LINK_QUAL_LANEx_SET
4444 * register (0x10B~0x10E)\
4445 */
4446 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4447 link_qual_pattern[lane] =
4448 (unsigned char)(pattern);
4449
d0778ebf 4450 core_link_write_dpcd(link,
3a340294 4451 DP_LINK_QUAL_LANE0_SET,
4562236b
HW		 4452 link_qual_pattern,
4453 sizeof(link_qual_pattern));
d0778ebf
HW		 4454 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4455 link->dpcd_caps.dpcd_rev.raw == 0) {
4562236b
HW		 4456 /* tell receiver that we are sending qualification
4457 * pattern DP 1.1a or earlier - DP receiver's link
4458 * quality pattern is set using
4459 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4460 * register (0x102). We will use v_1.3 when we are
4461 * setting test pattern for DP 1.1.
4462 */
d0778ebf
HW		 4463 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4464 &training_pattern.raw,
4465 sizeof(training_pattern));
4562236b 4466 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
d0778ebf
HW		 4467 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4468 &training_pattern.raw,
4469 sizeof(training_pattern));
4562236b
HW		 4470 }
4471 } else {
43563bc2 4472 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
43563bc2
WL		 4473
4474 switch (test_pattern_color_space) {
4475 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4476 color_space = COLOR_SPACE_SRGB;
4477 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4478 color_space = COLOR_SPACE_SRGB_LIMITED;
4479 break;
4480
4481 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4482 color_space = COLOR_SPACE_YCBCR601;
4483 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4484 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4485 break;
4486 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4487 color_space = COLOR_SPACE_YCBCR709;
4488 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4489 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4490 break;
4491 default:
4492 break;
4493 }
e8f9ecf2 4494
dc6e2448
WW		 4495 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4496 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4497 union dmub_hw_lock_flags hw_locks = { 0 };
4498 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4499
4500 hw_locks.bits.lock_dig = 1;
4501 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4502
4503 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4504 true,
4505 &hw_locks,
4506 &inst_flags);
4507 } else
4508 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4509 pipe_ctx->stream_res.tg);
4510 }
4511
e8f9ecf2 4512 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
43563bc2
WL		 4513 /* update MSA to requested color space */
4514 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4515 &pipe_ctx->stream->timing,
23bc5f34
WL		 4516 color_space,
4517 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4518 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
43563bc2 4519
e8f9ecf2
WL		 4520 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4521 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4522 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4523 else
4524 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4525 resource_build_info_frame(pipe_ctx);
4526 link->dc->hwss.update_info_frame(pipe_ctx);
4527 }
4528
43563bc2 4529 /* CRTC Patterns */
2057b7e1 4530 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
e8f9ecf2
WL		 4531 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4532 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4533 CRTC_STATE_VACTIVE);
4534 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4535 CRTC_STATE_VBLANK);
4536 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4537 CRTC_STATE_VACTIVE);
dc6e2448
WW		 4538
4539 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4540 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4541 union dmub_hw_lock_flags hw_locks = { 0 };
4542 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4543
4544 hw_locks.bits.lock_dig = 1;
4545 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4546
4547 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4548 false,
4549 &hw_locks,
4550 &inst_flags);
4551 } else
4552 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4553 pipe_ctx->stream_res.tg);
4554 }
4555
4562236b 4556 /* Set Test Pattern state */
d0778ebf 4557 link->test_pattern_enabled = true;
4562236b
HW		 4558 }
4559
4560 return true;
4561}
07c84c7a 4562
d0778ebf 4563void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
07c84c7a
DW		 4564{
4565 unsigned char mstmCntl;
4566
4567 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4568 if (enable)
4569 mstmCntl |= DP_MST_EN;
4570 else
4571 mstmCntl &= (~DP_MST_EN);
4572
4573 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4574}
6fbefb84 4575
0b226322
DG		 4576void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4577{
4578 union dpcd_edp_config edp_config_set;
4579 bool panel_mode_edp = false;
4580
4581 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4582
4583 if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4584
4585 switch (panel_mode) {
4586 case DP_PANEL_MODE_EDP:
4587 case DP_PANEL_MODE_SPECIAL:
4588 panel_mode_edp = true;
4589 break;
4590
4591 default:
4592 break;
4593 }
4594
4595 /*set edp panel mode in receiver*/
4596 core_link_read_dpcd(
4597 link,
4598 DP_EDP_CONFIGURATION_SET,
4599 &edp_config_set.raw,
4600 sizeof(edp_config_set.raw));
4601
4602 if (edp_config_set.bits.PANEL_MODE_EDP
4603 != panel_mode_edp) {
140b93eb 4604 enum dc_status result;
0b226322
DG		 4605
4606 edp_config_set.bits.PANEL_MODE_EDP =
4607 panel_mode_edp;
4608 result = core_link_write_dpcd(
4609 link,
4610 DP_EDP_CONFIGURATION_SET,
4611 &edp_config_set.raw,
4612 sizeof(edp_config_set.raw));
4613
a110f375 4614 ASSERT(result == DC_OK);
0b226322
DG		 4615 }
4616 }
4617 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4618 "eDP panel mode enabled: %d \n",
4619 link->link_index,
4620 link->dpcd_caps.panel_mode_edp,
4621 panel_mode_edp);
4622}
4623
4624enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4625{
4626 /* We need to explicitly check that connector
4627 * is not DP. Some Travis_VGA get reported
4628 * by video bios as DP.
4629 */
4630 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4631
4632 switch (link->dpcd_caps.branch_dev_id) {
df3b7e32
QZ		 4633 case DP_BRANCH_DEVICE_ID_0022B9:
4634 /* alternate scrambler reset is required for Travis
4635 * for the case when external chip does not
4636 * provide sink device id, alternate scrambler
4637 * scheme will be overriden later by querying
4638 * Encoder features
4639 */
0b226322
DG		 4640 if (strncmp(
4641 link->dpcd_caps.branch_dev_name,
4642 DP_VGA_LVDS_CONVERTER_ID_2,
4643 sizeof(
4644 link->dpcd_caps.
4645 branch_dev_name)) == 0) {
4646 return DP_PANEL_MODE_SPECIAL;
4647 }
4648 break;
df3b7e32
QZ		 4649 case DP_BRANCH_DEVICE_ID_00001A:
4650 /* alternate scrambler reset is required for Travis
4651 * for the case when external chip does not provide
4652 * sink device id, alternate scrambler scheme will
4653 * be overriden later by querying Encoder feature
4654 */
0b226322
DG		 4655 if (strncmp(link->dpcd_caps.branch_dev_name,
4656 DP_VGA_LVDS_CONVERTER_ID_3,
4657 sizeof(
4658 link->dpcd_caps.
4659 branch_dev_name)) == 0) {
4660 return DP_PANEL_MODE_SPECIAL;
4661 }
4662 break;
4663 default:
4664 break;
4665 }
4666 }
4667
4668 if (link->dpcd_caps.panel_mode_edp) {
4669 return DP_PANEL_MODE_EDP;
4670 }
4671
4672 return DP_PANEL_MODE_DEFAULT;
4673}
4674
7211b605 4675enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
97bda032
HW		 4676{
4677 /* FEC has to be "set ready" before the link training.
4678 * The policy is to always train with FEC
4679 * if the sink supports it and leave it enabled on link.
4680 * If FEC is not supported, disable it.
4681 */
7211b605
JK		 4682 struct link_encoder *link_enc = NULL;
4683 enum dc_status status = DC_OK;
97bda032
HW		 4684 uint8_t fec_config = 0;
4685
7211b605
JK		 4686 /* Access link encoder based on whether it is statically
4687 * or dynamically assigned to a link.
4688 */
4689 if (link->is_dig_mapping_flexible &&
4690 link->dc->res_pool->funcs->link_encs_assign)
4691 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
4692 else
4693 link_enc = link->link_enc;
4694 ASSERT(link_enc);
4695
89c7dfa9 4696 if (!dc_link_should_enable_fec(link))
7211b605 4697 return status;
97bda032
HW		 4698
4699 if (link_enc->funcs->fec_set_ready &&
4700 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
008a4016 4701 if (ready) {
97bda032 4702 fec_config = 1;
7211b605 4703 status = core_link_write_dpcd(link,
97bda032
HW		 4704 DP_FEC_CONFIGURATION,
4705 &fec_config,
7211b605
JK		 4706 sizeof(fec_config));
4707 if (status == DC_OK) {
97bda032
HW		 4708 link_enc->funcs->fec_set_ready(link_enc, true);
4709 link->fec_state = dc_link_fec_ready;
4710 } else {
7211b605 4711 link_enc->funcs->fec_set_ready(link->link_enc, false);
d68a7454 4712 link->fec_state = dc_link_fec_not_ready;
97bda032
HW		 4713 dm_error("dpcd write failed to set fec_ready");
4714 }
008a4016 4715 } else if (link->fec_state == dc_link_fec_ready) {
97bda032 4716 fec_config = 0;
7211b605 4717 status = core_link_write_dpcd(link,
97bda032
HW		 4718 DP_FEC_CONFIGURATION,
4719 &fec_config,
4720 sizeof(fec_config));
7211b605 4721 link_enc->funcs->fec_set_ready(link_enc, false);
97bda032
HW		 4722 link->fec_state = dc_link_fec_not_ready;
4723 }
4724 }
7211b605
JK		 4725
4726 return status;
97bda032
HW		 4727}
4728
4729void dp_set_fec_enable(struct dc_link *link, bool enable)
4730{
7211b605
JK		 4731 struct link_encoder *link_enc = NULL;
4732
4733 /* Access link encoder based on whether it is statically
4734 * or dynamically assigned to a link.
4735 */
4736 if (link->is_dig_mapping_flexible &&
4737 link->dc->res_pool->funcs->link_encs_assign)
4738 link_enc = link_enc_cfg_get_link_enc_used_by_link(
4739 link->dc->current_state, link);
4740 else
4741 link_enc = link->link_enc;
4742 ASSERT(link_enc);
97bda032 4743
89c7dfa9 4744 if (!dc_link_should_enable_fec(link))
97bda032
HW		 4745 return;
4746
4747 if (link_enc->funcs->fec_set_enable &&
4748 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4749 if (link->fec_state == dc_link_fec_ready && enable) {
fa11d3c9
LHM		 4750 /* Accord to DP spec, FEC enable sequence can first
4751 * be transmitted anytime after 1000 LL codes have
4752 * been transmitted on the link after link training
4753 * completion. Using 1 lane RBR should have the maximum
4754 * time for transmitting 1000 LL codes which is 6.173 us.
4755 * So use 7 microseconds delay instead.
4756 */
4757 udelay(7);
97bda032
HW		 4758 link_enc->funcs->fec_set_enable(link_enc, true);
4759 link->fec_state = dc_link_fec_enabled;
4760 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4761 link_enc->funcs->fec_set_enable(link_enc, false);
4762 link->fec_state = dc_link_fec_ready;
4763 }
4764 }
4765}
6fbefb84 4766
96577cf8
HW		 4767void dpcd_set_source_specific_data(struct dc_link *link)
4768{
0136684f 4769 if (!link->dc->vendor_signature.is_valid) {
61f02424 4770 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
29d5ac56
YS		 4771 struct dpcd_amd_signature amd_signature = {0};
4772 struct dpcd_amd_device_id amd_device_id = {0};
4773
4774 amd_device_id.device_id_byte1 =
0136684f 4775 (uint8_t)(link->ctx->asic_id.chip_id);
29d5ac56 4776 amd_device_id.device_id_byte2 =
0136684f 4777 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
29d5ac56 4778 amd_device_id.dce_version =
0136684f 4779 (uint8_t)(link->ctx->dce_version);
29d5ac56
YS		 4780 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4781 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4782
4783 core_link_read_dpcd(link, DP_SOURCE_OUI,
4784 (uint8_t *)(&amd_signature),
4785 sizeof(amd_signature));
0136684f 4786
29d5ac56
YS		 4787 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4788 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4789 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4790
4791 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4792 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4793 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4794
4795 core_link_write_dpcd(link, DP_SOURCE_OUI,
0136684f
CH		 4796 (uint8_t *)(&amd_signature),
4797 sizeof(amd_signature));
29d5ac56
YS		 4798 }
4799
4800 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4801 (uint8_t *)(&amd_device_id),
4802 sizeof(amd_device_id));
0136684f 4803
9248681f
AT		 4804 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4805 link->dc->caps.min_horizontal_blanking_period != 0) {
4806
4807 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4808
4809 result_write_min_hblank = core_link_write_dpcd(link,
4810 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4811 sizeof(hblank_size));
4812 }
4813 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4814 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4815 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4816 result_write_min_hblank,
4817 link->link_index,
4818 link->ctx->dce_version,
4819 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4820 link->dc->caps.min_horizontal_blanking_period,
4821 link->dpcd_caps.branch_dev_id,
4822 link->dpcd_caps.branch_dev_name[0],
4823 link->dpcd_caps.branch_dev_name[1],
4824 link->dpcd_caps.branch_dev_name[2],
4825 link->dpcd_caps.branch_dev_name[3],
4826 link->dpcd_caps.branch_dev_name[4],
4827 link->dpcd_caps.branch_dev_name[5]);
0136684f
CH		 4828 } else {
4829 core_link_write_dpcd(link, DP_SOURCE_OUI,
4830 link->dc->vendor_signature.data.raw,
4831 sizeof(link->dc->vendor_signature.data.raw));
4832 }
96577cf8
HW		 4833}
4834
4835bool dc_link_set_backlight_level_nits(struct dc_link *link,
4836 bool isHDR,
4837 uint32_t backlight_millinits,
4838 uint32_t transition_time_in_ms)
4839{
4840 struct dpcd_source_backlight_set dpcd_backlight_set;
4841 uint8_t backlight_control = isHDR ? 1 : 0;
4842
4843 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4844 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4845 return false;
4846
4847 // OLEDs have no PWM, they can only use AUX
4848 if (link->dpcd_sink_ext_caps.bits.oled == 1)
4849 backlight_control = 1;
4850
4851 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4852 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4853
4854
4855 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4856 (uint8_t *)(&dpcd_backlight_set),
4857 sizeof(dpcd_backlight_set)) != DC_OK)
4858 return false;
4859
4860 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4861 &backlight_control, 1) != DC_OK)
4862 return false;
4863
4864 return true;
4865}
4866
4867bool dc_link_get_backlight_level_nits(struct dc_link *link,
4868 uint32_t *backlight_millinits_avg,
4869 uint32_t *backlight_millinits_peak)
4870{
4871 union dpcd_source_backlight_get dpcd_backlight_get;
4872
4873 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4874
4875 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4876 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4877 return false;
4878
16697cf3 4879 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
96577cf8 4880 dpcd_backlight_get.raw,
16697cf3 4881 sizeof(union dpcd_source_backlight_get)) != DC_OK)
96577cf8
HW		 4882 return false;
4883
4884 *backlight_millinits_avg =
4885 dpcd_backlight_get.bytes.backlight_millinits_avg;
4886 *backlight_millinits_peak =
4887 dpcd_backlight_get.bytes.backlight_millinits_peak;
4888
4889 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4890 if (*backlight_millinits_avg == 0 ||
4891 *backlight_millinits_avg > *backlight_millinits_peak)
4892 return false;
4893
4894 return true;
4895}
4896
4897bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4898{
4899 uint8_t backlight_enable = enable ? 1 : 0;
4900
4901 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4902 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4903 return false;
4904
4905 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4906 &backlight_enable, 1) != DC_OK)
4907 return false;
4908
4909 return true;
4910}
4911
4912// we read default from 0x320 because we expect BIOS wrote it there
4913// regular get_backlight_nit reads from panel set at 0x326
4914bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4915{
4916 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4917 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4918 return false;
4919
16697cf3 4920 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
96577cf8 4921 (uint8_t *) backlight_millinits,
16697cf3 4922 sizeof(uint32_t)) != DC_OK)
96577cf8
HW		 4923 return false;
4924
4925 return true;
4926}
4927
4928bool dc_link_set_default_brightness_aux(struct dc_link *link)
4929{
4930 uint32_t default_backlight;
4931
4932 if (link &&
4933 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4934 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4935 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4936 default_backlight = 150000;
4937 // if < 5 nits or > 5000, it might be wrong readback
4938 if (default_backlight < 5000 || default_backlight > 5000000)
4939 default_backlight = 150000; //
4940
4941 return dc_link_set_backlight_level_nits(link, true,
4942 default_backlight, 0);
4943 }
4944 return false;
4945}
f9fc6f39
MS		 4946
4947bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4948{
4949 struct dc_link_settings link_setting;
4950 uint8_t link_bw_set;
4951 uint8_t link_rate_set;
4952 uint32_t req_bw;
4953 union lane_count_set lane_count_set = { {0} };
4954
4955 ASSERT(link || crtc_timing); // invalid input
4956
4957 if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4958 !link->dc->debug.optimize_edp_link_rate)
4959 return false;
4960
4961
4962 // Read DPCD 00100h to find if standard link rates are set
4963 core_link_read_dpcd(link, DP_LINK_BW_SET,
4964 &link_bw_set, sizeof(link_bw_set));
4965
0eda55ca
MS		 4966 if (link_bw_set) {
4967 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
f9fc6f39 4968 return true;
0eda55ca 4969 }
f9fc6f39
MS		 4970
4971 // Read DPCD 00115h to find the edp link rate set used
4972 core_link_read_dpcd(link, DP_LINK_RATE_SET,
4973 &link_rate_set, sizeof(link_rate_set));
4974
4975 // Read DPCD 00101h to find out the number of lanes currently set
4976 core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4977 &lane_count_set.raw, sizeof(lane_count_set));
4978
4979 req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4980
4981 decide_edp_link_settings(link, &link_setting, req_bw);
4982
4983 if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
0eda55ca
MS		 4984 lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4985 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
f9fc6f39 4986 return true;
0eda55ca 4987 }
f9fc6f39 4988
0eda55ca 4989 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
f9fc6f39
MS		 4990 return false;
4991}
4992
55bac4a7
WL		 4993enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4994{
4995 if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4996 (link_settings->link_rate <= LINK_RATE_HIGH3))
4997 return DP_8b_10b_ENCODING;
4998 return DP_UNKNOWN_ENCODING;
4999}
f9fc6f39 5000
Linux 6.x block layer and io_uring tree(s)