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drm/amd/display: separate scl functions out from dcn10_dpp
[linux-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
CommitLineData
4562236b
HW		 1/* Copyright 2015 Advanced Micro Devices, Inc. */
2#include "dm_services.h"
3#include "dc.h"
4#include "dc_link_dp.h"
5#include "dm_helpers.h"
6
7#include "inc/core_types.h"
8#include "link_hwss.h"
9#include "dc_link_ddc.h"
10#include "core_status.h"
11#include "dpcd_defs.h"
12
529cad0f 13#include "resource.h"
4562236b
HW		 14
15/* maximum pre emphasis level allowed for each voltage swing level*/
16static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
17 PRE_EMPHASIS_LEVEL3,
18 PRE_EMPHASIS_LEVEL2,
19 PRE_EMPHASIS_LEVEL1,
20 PRE_EMPHASIS_DISABLED };
21
22enum {
23 POST_LT_ADJ_REQ_LIMIT = 6,
24 POST_LT_ADJ_REQ_TIMEOUT = 200
25};
26
27enum {
28 LINK_TRAINING_MAX_RETRY_COUNT = 5,
29 /* to avoid infinite loop where-in the receiver
30 * switches between different VS
31 */
32 LINK_TRAINING_MAX_CR_RETRY = 100
33};
34
4562236b 35static void wait_for_training_aux_rd_interval(
d0778ebf 36 struct dc_link *link,
4562236b
HW		 37 uint32_t default_wait_in_micro_secs)
38{
39 union training_aux_rd_interval training_rd_interval;
40
41 /* overwrite the delay if rev > 1.1*/
42 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
43 /* DP 1.2 or later - retrieve delay through
44 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
45 core_link_read_dpcd(
46 link,
3a340294 47 DP_TRAINING_AUX_RD_INTERVAL,
4562236b
HW		 48 (uint8_t *)&training_rd_interval,
49 sizeof(training_rd_interval));
50
51 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
52 default_wait_in_micro_secs =
53 training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
54 }
55
56 udelay(default_wait_in_micro_secs);
57
58 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
59 "%s:\n wait = %d\n",
60 __func__,
61 default_wait_in_micro_secs);
62}
63
64static void dpcd_set_training_pattern(
d0778ebf 65 struct dc_link *link,
4562236b
HW		 66 union dpcd_training_pattern dpcd_pattern)
67{
68 core_link_write_dpcd(
69 link,
3a340294 70 DP_TRAINING_PATTERN_SET,
4562236b
HW		 71 &dpcd_pattern.raw,
72 1);
73
74 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
75 "%s\n %x pattern = %x\n",
76 __func__,
3a340294 77 DP_TRAINING_PATTERN_SET,
4562236b
HW		 78 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
79}
80
81static void dpcd_set_link_settings(
d0778ebf 82 struct dc_link *link,
4562236b
HW		 83 const struct link_training_settings *lt_settings)
84{
85 uint8_t rate = (uint8_t)
86 (lt_settings->link_settings.link_rate);
87
88 union down_spread_ctrl downspread = {{0}};
89 union lane_count_set lane_count_set = {{0}};
90 uint8_t link_set_buffer[2];
91
92 downspread.raw = (uint8_t)
93 (lt_settings->link_settings.link_spread);
94
95 lane_count_set.bits.LANE_COUNT_SET =
96 lt_settings->link_settings.lane_count;
97
98 lane_count_set.bits.ENHANCED_FRAMING = 1;
99
100 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
101 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
102
103 link_set_buffer[0] = rate;
104 link_set_buffer[1] = lane_count_set.raw;
105
3a340294 106 core_link_write_dpcd(link, DP_LINK_BW_SET,
4562236b 107 link_set_buffer, 2);
3a340294 108 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
4562236b
HW		 109 &downspread.raw, sizeof(downspread));
110
111 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
112 "%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
113 __func__,
3a340294 114 DP_LINK_BW_SET,
4562236b 115 lt_settings->link_settings.link_rate,
3a340294 116 DP_LANE_COUNT_SET,
4562236b 117 lt_settings->link_settings.lane_count,
3a340294 118 DP_DOWNSPREAD_CTRL,
4562236b
HW		 119 lt_settings->link_settings.link_spread);
120
121}
122
123static enum dpcd_training_patterns
124 hw_training_pattern_to_dpcd_training_pattern(
d0778ebf 125 struct dc_link *link,
4562236b
HW		 126 enum hw_dp_training_pattern pattern)
127{
128 enum dpcd_training_patterns dpcd_tr_pattern =
129 DPCD_TRAINING_PATTERN_VIDEOIDLE;
130
131 switch (pattern) {
132 case HW_DP_TRAINING_PATTERN_1:
133 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
134 break;
135 case HW_DP_TRAINING_PATTERN_2:
136 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
137 break;
138 case HW_DP_TRAINING_PATTERN_3:
139 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
140 break;
141 case HW_DP_TRAINING_PATTERN_4:
142 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
143 break;
144 default:
145 ASSERT(0);
146 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
147 "%s: Invalid HW Training pattern: %d\n",
148 __func__, pattern);
149 break;
150 }
151
152 return dpcd_tr_pattern;
153
154}
155
156static void dpcd_set_lt_pattern_and_lane_settings(
d0778ebf 157 struct dc_link *link,
4562236b
HW		 158 const struct link_training_settings *lt_settings,
159 enum hw_dp_training_pattern pattern)
160{
161 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
162 const uint32_t dpcd_base_lt_offset =
3a340294 163 DP_TRAINING_PATTERN_SET;
4562236b
HW		 164 uint8_t dpcd_lt_buffer[5] = {0};
165 union dpcd_training_pattern dpcd_pattern = {{0}};
166 uint32_t lane;
167 uint32_t size_in_bytes;
168 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
169
170 /*****************************************************************
171 * DpcdAddress_TrainingPatternSet
172 *****************************************************************/
173 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
174 hw_training_pattern_to_dpcd_training_pattern(link, pattern);
175
3a340294 176 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
4562236b
HW		 177 = dpcd_pattern.raw;
178
179 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
180 "%s\n %x pattern = %x\n",
181 __func__,
3a340294 182 DP_TRAINING_PATTERN_SET,
4562236b
HW		 183 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
184
185 /*****************************************************************
186 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
187 *****************************************************************/
188 for (lane = 0; lane <
189 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
190
191 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
192 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
193 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
194 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
195
196 dpcd_lane[lane].bits.MAX_SWING_REACHED =
197 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
198 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
199 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
200 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
201 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
202 }
203
204 /* concatinate everything into one buffer*/
205
206 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
207
208 // 0x00103 - 0x00102
209 memmove(
3a340294 210 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
4562236b
HW		 211 dpcd_lane,
212 size_in_bytes);
213
214 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
215 "%s:\n %x VS set = %x PE set = %x \
216 max VS Reached = %x max PE Reached = %x\n",
217 __func__,
3a340294 218 DP_TRAINING_LANE0_SET,
4562236b
HW		 219 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
220 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
221 dpcd_lane[0].bits.MAX_SWING_REACHED,
222 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
223
224 if (edp_workaround) {
225 /* for eDP write in 2 parts because the 5-byte burst is
226 * causing issues on some eDP panels (EPR#366724)
227 */
228 core_link_write_dpcd(
229 link,
3a340294 230 DP_TRAINING_PATTERN_SET,
4562236b
HW		 231 &dpcd_pattern.raw,
232 sizeof(dpcd_pattern.raw) );
233
234 core_link_write_dpcd(
235 link,
3a340294 236 DP_TRAINING_LANE0_SET,
4562236b
HW		 237 (uint8_t *)(dpcd_lane),
238 size_in_bytes);
239
240 } else
241 /* write it all in (1 + number-of-lanes)-byte burst*/
242 core_link_write_dpcd(
243 link,
244 dpcd_base_lt_offset,
245 dpcd_lt_buffer,
246 size_in_bytes + sizeof(dpcd_pattern.raw) );
247
d0778ebf 248 link->cur_lane_setting = lt_settings->lane_settings[0];
4562236b
HW		 249}
250
251static bool is_cr_done(enum dc_lane_count ln_count,
252 union lane_status *dpcd_lane_status)
253{
254 bool done = true;
255 uint32_t lane;
256 /*LANEx_CR_DONE bits All 1's?*/
257 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
258 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
259 done = false;
260 }
261 return done;
262
263}
264
265static bool is_ch_eq_done(enum dc_lane_count ln_count,
266 union lane_status *dpcd_lane_status,
267 union lane_align_status_updated *lane_status_updated)
268{
269 bool done = true;
270 uint32_t lane;
271 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
272 done = false;
273 else {
274 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
275 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
276 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
277 done = false;
278 }
279 }
280 return done;
281
282}
283
284static void update_drive_settings(
285 struct link_training_settings *dest,
286 struct link_training_settings src)
287{
288 uint32_t lane;
289 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
290 dest->lane_settings[lane].VOLTAGE_SWING =
291 src.lane_settings[lane].VOLTAGE_SWING;
292 dest->lane_settings[lane].PRE_EMPHASIS =
293 src.lane_settings[lane].PRE_EMPHASIS;
294 dest->lane_settings[lane].POST_CURSOR2 =
295 src.lane_settings[lane].POST_CURSOR2;
296 }
297}
298
299static uint8_t get_nibble_at_index(const uint8_t *buf,
300 uint32_t index)
301{
302 uint8_t nibble;
303 nibble = buf[index / 2];
304
305 if (index % 2)
306 nibble >>= 4;
307 else
308 nibble &= 0x0F;
309
310 return nibble;
311}
312
313static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
314 enum dc_voltage_swing voltage)
315{
316 enum dc_pre_emphasis pre_emphasis;
317 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
318
319 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
320 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
321
322 return pre_emphasis;
323
324}
325
326static void find_max_drive_settings(
327 const struct link_training_settings *link_training_setting,
328 struct link_training_settings *max_lt_setting)
329{
330 uint32_t lane;
331 struct dc_lane_settings max_requested;
332
333 max_requested.VOLTAGE_SWING =
334 link_training_setting->
335 lane_settings[0].VOLTAGE_SWING;
336 max_requested.PRE_EMPHASIS =
337 link_training_setting->
338 lane_settings[0].PRE_EMPHASIS;
339 /*max_requested.postCursor2 =
340 * link_training_setting->laneSettings[0].postCursor2;*/
341
342 /* Determine what the maximum of the requested settings are*/
343 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
344 lane++) {
345 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
346 max_requested.VOLTAGE_SWING)
347
348 max_requested.VOLTAGE_SWING =
349 link_training_setting->
350 lane_settings[lane].VOLTAGE_SWING;
351
352 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
353 max_requested.PRE_EMPHASIS)
354 max_requested.PRE_EMPHASIS =
355 link_training_setting->
356 lane_settings[lane].PRE_EMPHASIS;
357
358 /*
359 if (link_training_setting->laneSettings[lane].postCursor2 >
360 max_requested.postCursor2)
361 {
362 max_requested.postCursor2 =
363 link_training_setting->laneSettings[lane].postCursor2;
364 }
365 */
366 }
367
368 /* make sure the requested settings are
369 * not higher than maximum settings*/
370 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
371 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
372
373 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
374 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
375 /*
376 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
377 max_requested.postCursor2 = PostCursor2_MaxLevel;
378 */
379
380 /* make sure the pre-emphasis matches the voltage swing*/
381 if (max_requested.PRE_EMPHASIS >
382 get_max_pre_emphasis_for_voltage_swing(
383 max_requested.VOLTAGE_SWING))
384 max_requested.PRE_EMPHASIS =
385 get_max_pre_emphasis_for_voltage_swing(
386 max_requested.VOLTAGE_SWING);
387
388 /*
389 * Post Cursor2 levels are completely independent from
390 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
391 * can only be applied to each allowable combination of voltage
392 * swing and pre-emphasis levels */
393 /* if ( max_requested.postCursor2 >
394 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
395 * max_requested.postCursor2 =
396 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
397 */
398
399 max_lt_setting->link_settings.link_rate =
400 link_training_setting->link_settings.link_rate;
401 max_lt_setting->link_settings.lane_count =
402 link_training_setting->link_settings.lane_count;
403 max_lt_setting->link_settings.link_spread =
404 link_training_setting->link_settings.link_spread;
405
406 for (lane = 0; lane <
407 link_training_setting->link_settings.lane_count;
408 lane++) {
409 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
410 max_requested.VOLTAGE_SWING;
411 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
412 max_requested.PRE_EMPHASIS;
413 /*max_lt_setting->laneSettings[lane].postCursor2 =
414 * max_requested.postCursor2;
415 */
416 }
417
418}
419
420static void get_lane_status_and_drive_settings(
d0778ebf 421 struct dc_link *link,
4562236b
HW		 422 const struct link_training_settings *link_training_setting,
423 union lane_status *ln_status,
424 union lane_align_status_updated *ln_status_updated,
425 struct link_training_settings *req_settings)
426{
427 uint8_t dpcd_buf[6] = {0};
428 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {{{0}}};
429 struct link_training_settings request_settings = {{0}};
430 uint32_t lane;
431
432 memset(req_settings, '\0', sizeof(struct link_training_settings));
433
434 core_link_read_dpcd(
435 link,
3a340294 436 DP_LANE0_1_STATUS,
4562236b
HW		 437 (uint8_t *)(dpcd_buf),
438 sizeof(dpcd_buf));
439
440 for (lane = 0; lane <
441 (uint32_t)(link_training_setting->link_settings.lane_count);
442 lane++) {
443
444 ln_status[lane].raw =
445 get_nibble_at_index(&dpcd_buf[0], lane);
446 dpcd_lane_adjust[lane].raw =
447 get_nibble_at_index(&dpcd_buf[4], lane);
448 }
449
450 ln_status_updated->raw = dpcd_buf[2];
451
452 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
453 "%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
454 __func__,
3a340294
DA		 455 DP_LANE0_1_STATUS, dpcd_buf[0],
456 DP_LANE2_3_STATUS, dpcd_buf[1]);
4562236b
HW		 457
458 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
459 "%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
460 __func__,
3a340294 461 DP_ADJUST_REQUEST_LANE0_1,
4562236b 462 dpcd_buf[4],
3a340294 463 DP_ADJUST_REQUEST_LANE2_3,
4562236b
HW		 464 dpcd_buf[5]);
465
466 /*copy to req_settings*/
467 request_settings.link_settings.lane_count =
468 link_training_setting->link_settings.lane_count;
469 request_settings.link_settings.link_rate =
470 link_training_setting->link_settings.link_rate;
471 request_settings.link_settings.link_spread =
472 link_training_setting->link_settings.link_spread;
473
474 for (lane = 0; lane <
475 (uint32_t)(link_training_setting->link_settings.lane_count);
476 lane++) {
477
478 request_settings.lane_settings[lane].VOLTAGE_SWING =
479 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
480 VOLTAGE_SWING_LANE);
481 request_settings.lane_settings[lane].PRE_EMPHASIS =
482 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
483 PRE_EMPHASIS_LANE);
484 }
485
486 /*Note: for postcursor2, read adjusted
487 * postcursor2 settings from*/
488 /*DpcdAddress_AdjustRequestPostCursor2 =
489 *0x020C (not implemented yet)*/
490
491 /* we find the maximum of the requested settings across all lanes*/
492 /* and set this maximum for all lanes*/
493 find_max_drive_settings(&request_settings, req_settings);
494
495 /* if post cursor 2 is needed in the future,
496 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
497 */
498
499}
500
501static void dpcd_set_lane_settings(
d0778ebf 502 struct dc_link *link,
4562236b
HW		 503 const struct link_training_settings *link_training_setting)
504{
505 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
506 uint32_t lane;
507
508 for (lane = 0; lane <
509 (uint32_t)(link_training_setting->
510 link_settings.lane_count);
511 lane++) {
512 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
513 (uint8_t)(link_training_setting->
514 lane_settings[lane].VOLTAGE_SWING);
515 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
516 (uint8_t)(link_training_setting->
517 lane_settings[lane].PRE_EMPHASIS);
518 dpcd_lane[lane].bits.MAX_SWING_REACHED =
519 (link_training_setting->
520 lane_settings[lane].VOLTAGE_SWING ==
521 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
522 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
523 (link_training_setting->
524 lane_settings[lane].PRE_EMPHASIS ==
525 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
526 }
527
528 core_link_write_dpcd(link,
3a340294 529 DP_TRAINING_LANE0_SET,
4562236b
HW		 530 (uint8_t *)(dpcd_lane),
531 link_training_setting->link_settings.lane_count);
532
533 /*
534 if (LTSettings.link.rate == LinkRate_High2)
535 {
536 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
537 for ( uint32_t lane = 0;
538 lane < lane_count_DPMax; lane++)
539 {
540 dpcd_lane2[lane].bits.post_cursor2_set =
541 static_cast<unsigned char>(
542 LTSettings.laneSettings[lane].postCursor2);
543 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
544 }
545 m_pDpcdAccessSrv->WriteDpcdData(
546 DpcdAddress_Lane0Set2,
547 reinterpret_cast<unsigned char*>(dpcd_lane2),
548 LTSettings.link.lanes);
549 }
550 */
551
552 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
553 "%s\n %x VS set = %x PE set = %x \
554 max VS Reached = %x max PE Reached = %x\n",
555 __func__,
3a340294 556 DP_TRAINING_LANE0_SET,
4562236b
HW		 557 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
558 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
559 dpcd_lane[0].bits.MAX_SWING_REACHED,
560 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
561
d0778ebf 562 link->cur_lane_setting = link_training_setting->lane_settings[0];
4562236b
HW		 563
564}
565
566static bool is_max_vs_reached(
567 const struct link_training_settings *lt_settings)
568{
569 uint32_t lane;
570 for (lane = 0; lane <
571 (uint32_t)(lt_settings->link_settings.lane_count);
572 lane++) {
573 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
574 == VOLTAGE_SWING_MAX_LEVEL)
575 return true;
576 }
577 return false;
578
579}
580
581void dc_link_dp_set_drive_settings(
d0778ebf 582 struct dc_link *link,
4562236b
HW		 583 struct link_training_settings *lt_settings)
584{
4562236b 585 /* program ASIC PHY settings*/
d0778ebf 586 dp_set_hw_lane_settings(link, lt_settings);
4562236b
HW		 587
588 /* Notify DP sink the PHY settings from source */
d0778ebf 589 dpcd_set_lane_settings(link, lt_settings);
4562236b
HW		 590}
591
592static bool perform_post_lt_adj_req_sequence(
d0778ebf 593 struct dc_link *link,
4562236b
HW		 594 struct link_training_settings *lt_settings)
595{
596 enum dc_lane_count lane_count =
597 lt_settings->link_settings.lane_count;
598
599 uint32_t adj_req_count;
600 uint32_t adj_req_timer;
601 bool req_drv_setting_changed;
602 uint32_t lane;
603
604 req_drv_setting_changed = false;
605 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
606 adj_req_count++) {
607
608 req_drv_setting_changed = false;
609
610 for (adj_req_timer = 0;
611 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
612 adj_req_timer++) {
613
614 struct link_training_settings req_settings;
615 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
616 union lane_align_status_updated
617 dpcd_lane_status_updated;
618
619 get_lane_status_and_drive_settings(
620 link,
621 lt_settings,
622 dpcd_lane_status,
623 &dpcd_lane_status_updated,
624 &req_settings);
625
626 if (dpcd_lane_status_updated.bits.
627 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
628 return true;
629
630 if (!is_cr_done(lane_count, dpcd_lane_status))
631 return false;
632
633 if (!is_ch_eq_done(
634 lane_count,
635 dpcd_lane_status,
636 &dpcd_lane_status_updated))
637 return false;
638
639 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
640
641 if (lt_settings->
642 lane_settings[lane].VOLTAGE_SWING !=
643 req_settings.lane_settings[lane].
644 VOLTAGE_SWING ||
645 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
646 req_settings.lane_settings[lane].PRE_EMPHASIS) {
647
648 req_drv_setting_changed = true;
649 break;
650 }
651 }
652
653 if (req_drv_setting_changed) {
654 update_drive_settings(
655 lt_settings,req_settings);
656
d0778ebf 657 dc_link_dp_set_drive_settings(link,
4562236b
HW		 658 lt_settings);
659 break;
660 }
661
662 msleep(1);
663 }
664
665 if (!req_drv_setting_changed) {
666 dm_logger_write(link->ctx->logger, LOG_WARNING,
667 "%s: Post Link Training Adjust Request Timed out\n",
668 __func__);
669
670 ASSERT(0);
671 return true;
672 }
673 }
674 dm_logger_write(link->ctx->logger, LOG_WARNING,
675 "%s: Post Link Training Adjust Request limit reached\n",
676 __func__);
677
678 ASSERT(0);
679 return true;
680
681}
682
d0778ebf 683static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
4562236b
HW		 684{
685 enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
686 struct encoder_feature_support *features = &link->link_enc->features;
687 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
688
689 if (features->flags.bits.IS_TPS3_CAPABLE)
690 highest_tp = HW_DP_TRAINING_PATTERN_3;
691
692 if (features->flags.bits.IS_TPS4_CAPABLE)
693 highest_tp = HW_DP_TRAINING_PATTERN_4;
694
695 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
696 highest_tp >= HW_DP_TRAINING_PATTERN_4)
697 return HW_DP_TRAINING_PATTERN_4;
698
699 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
700 highest_tp >= HW_DP_TRAINING_PATTERN_3)
701 return HW_DP_TRAINING_PATTERN_3;
702
703 return HW_DP_TRAINING_PATTERN_2;
704}
705
820e3935 706static enum link_training_result perform_channel_equalization_sequence(
d0778ebf 707 struct dc_link *link,
4562236b
HW		 708 struct link_training_settings *lt_settings)
709{
710 struct link_training_settings req_settings;
711 enum hw_dp_training_pattern hw_tr_pattern;
712 uint32_t retries_ch_eq;
713 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
714 union lane_align_status_updated dpcd_lane_status_updated = {{0}};
715 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};;
716
717 hw_tr_pattern = get_supported_tp(link);
718
719 dp_set_hw_training_pattern(link, hw_tr_pattern);
720
721 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
722 retries_ch_eq++) {
723
724 dp_set_hw_lane_settings(link, lt_settings);
725
726 /* 2. update DPCD*/
727 if (!retries_ch_eq)
728 /* EPR #361076 - write as a 5-byte burst,
729 * but only for the 1-st iteration*/
730 dpcd_set_lt_pattern_and_lane_settings(
731 link,
732 lt_settings,
733 hw_tr_pattern);
734 else
735 dpcd_set_lane_settings(link, lt_settings);
736
737 /* 3. wait for receiver to lock-on*/
738 wait_for_training_aux_rd_interval(link, 400);
739
740 /* 4. Read lane status and requested
741 * drive settings as set by the sink*/
742
743 get_lane_status_and_drive_settings(
744 link,
745 lt_settings,
746 dpcd_lane_status,
747 &dpcd_lane_status_updated,
748 &req_settings);
749
750 /* 5. check CR done*/
751 if (!is_cr_done(lane_count, dpcd_lane_status))
820e3935 752 return LINK_TRAINING_EQ_FAIL_CR;
4562236b
HW		 753
754 /* 6. check CHEQ done*/
755 if (is_ch_eq_done(lane_count,
756 dpcd_lane_status,
757 &dpcd_lane_status_updated))
820e3935 758 return LINK_TRAINING_SUCCESS;
4562236b
HW		 759
760 /* 7. update VS/PE/PC2 in lt_settings*/
761 update_drive_settings(lt_settings, req_settings);
762 }
763
820e3935 764 return LINK_TRAINING_EQ_FAIL_EQ;
4562236b
HW		 765
766}
767
768static bool perform_clock_recovery_sequence(
d0778ebf 769 struct dc_link *link,
4562236b
HW		 770 struct link_training_settings *lt_settings)
771{
772 uint32_t retries_cr;
773 uint32_t retry_count;
774 uint32_t lane;
775 struct link_training_settings req_settings;
776 enum dc_lane_count lane_count =
777 lt_settings->link_settings.lane_count;
778 enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
779 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
780 union lane_align_status_updated dpcd_lane_status_updated;
781
782 retries_cr = 0;
783 retry_count = 0;
784 /* initial drive setting (VS/PE/PC2)*/
785 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
786 lt_settings->lane_settings[lane].VOLTAGE_SWING =
787 VOLTAGE_SWING_LEVEL0;
788 lt_settings->lane_settings[lane].PRE_EMPHASIS =
789 PRE_EMPHASIS_DISABLED;
790 lt_settings->lane_settings[lane].POST_CURSOR2 =
791 POST_CURSOR2_DISABLED;
792 }
793
794 dp_set_hw_training_pattern(link, hw_tr_pattern);
795
796 /* najeeb - The synaptics MST hub can put the LT in
797 * infinite loop by switching the VS
798 */
799 /* between level 0 and level 1 continuously, here
800 * we try for CR lock for LinkTrainingMaxCRRetry count*/
801 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
802 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
803
804 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
805 memset(&dpcd_lane_status_updated, '\0',
806 sizeof(dpcd_lane_status_updated));
807
808 /* 1. call HWSS to set lane settings*/
809 dp_set_hw_lane_settings(
810 link,
811 lt_settings);
812
813 /* 2. update DPCD of the receiver*/
814 if (!retries_cr)
815 /* EPR #361076 - write as a 5-byte burst,
816 * but only for the 1-st iteration.*/
817 dpcd_set_lt_pattern_and_lane_settings(
818 link,
819 lt_settings,
820 hw_tr_pattern);
821 else
822 dpcd_set_lane_settings(
823 link,
824 lt_settings);
825
826 /* 3. wait receiver to lock-on*/
827 wait_for_training_aux_rd_interval(
828 link,
829 100);
830
831 /* 4. Read lane status and requested drive
832 * settings as set by the sink
833 */
834 get_lane_status_and_drive_settings(
835 link,
836 lt_settings,
837 dpcd_lane_status,
838 &dpcd_lane_status_updated,
839 &req_settings);
840
841 /* 5. check CR done*/
842 if (is_cr_done(lane_count, dpcd_lane_status))
843 return true;
844
845 /* 6. max VS reached*/
846 if (is_max_vs_reached(lt_settings))
847 return false;
848
849 /* 7. same voltage*/
850 /* Note: VS same for all lanes,
851 * so comparing first lane is sufficient*/
852 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
853 req_settings.lane_settings[0].VOLTAGE_SWING)
854 retries_cr++;
855 else
856 retries_cr = 0;
857
858 /* 8. update VS/PE/PC2 in lt_settings*/
859 update_drive_settings(lt_settings, req_settings);
860
861 retry_count++;
862 }
863
864 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
865 ASSERT(0);
866 dm_logger_write(link->ctx->logger, LOG_ERROR,
867 "%s: Link Training Error, could not \
868 get CR after %d tries. \
869 Possibly voltage swing issue", __func__,
870 LINK_TRAINING_MAX_CR_RETRY);
871
872 }
873
874 return false;
875}
876
877static inline bool perform_link_training_int(
d0778ebf 878 struct dc_link *link,
4562236b
HW		 879 struct link_training_settings *lt_settings,
880 bool status)
881{
882 union lane_count_set lane_count_set = { {0} };
883 union dpcd_training_pattern dpcd_pattern = { {0} };
884
885 /* 3. set training not in progress*/
886 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
887 dpcd_set_training_pattern(link, dpcd_pattern);
888
889 /* 4. mainlink output idle pattern*/
890 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
891
892 /*
893 * 5. post training adjust if required
894 * If the upstream DPTX and downstream DPRX both support TPS4,
895 * TPS4 must be used instead of POST_LT_ADJ_REQ.
896 */
c30267f5
CL		 897 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
898 get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
4562236b
HW		 899 return status;
900
901 if (status &&
902 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
903 status = false;
904
905 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
906 lane_count_set.bits.ENHANCED_FRAMING = 1;
907 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
908
909 core_link_write_dpcd(
910 link,
3a340294 911 DP_LANE_COUNT_SET,
4562236b
HW		 912 &lane_count_set.raw,
913 sizeof(lane_count_set));
914
915 return status;
916}
917
820e3935 918enum link_training_result dc_link_dp_perform_link_training(
4562236b
HW		 919 struct dc_link *link,
920 const struct dc_link_settings *link_setting,
921 bool skip_video_pattern)
922{
820e3935 923 enum link_training_result status = LINK_TRAINING_SUCCESS;
4562236b
HW		 924
925 char *link_rate = "Unknown";
926 struct link_training_settings lt_settings;
927
4562236b
HW		 928 memset(&lt_settings, '\0', sizeof(lt_settings));
929
930 lt_settings.link_settings.link_rate = link_setting->link_rate;
931 lt_settings.link_settings.lane_count = link_setting->lane_count;
932
933 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
934
935 /* TODO hard coded to SS for now
936 * lt_settings.link_settings.link_spread =
937 * dal_display_path_is_ss_supported(
938 * path_mode->display_path) ?
939 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
940 * LINK_SPREAD_DISABLED;
941 */
942 lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
943
944 /* 1. set link rate, lane count and spread*/
d0778ebf 945 dpcd_set_link_settings(link, &lt_settings);
4562236b
HW		 946
947 /* 2. perform link training (set link training done
948 * to false is done as well)*/
d0778ebf 949 if (!perform_clock_recovery_sequence(link, &lt_settings)) {
820e3935
DW		 950 status = LINK_TRAINING_CR_FAIL;
951 } else {
d0778ebf 952 status = perform_channel_equalization_sequence(link,
820e3935 953 &lt_settings);
4562236b
HW		 954 }
955
820e3935 956 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
d0778ebf 957 if (!perform_link_training_int(link,
820e3935
DW		 958 &lt_settings,
959 status == LINK_TRAINING_SUCCESS)) {
960 /* the next link training setting in this case
961 * would be the same as CR failure case.
962 */
963 status = LINK_TRAINING_CR_FAIL;
964 }
965 }
4562236b
HW		 966
967 /* 6. print status message*/
968 switch (lt_settings.link_settings.link_rate) {
969
970 case LINK_RATE_LOW:
971 link_rate = "RBR";
972 break;
973 case LINK_RATE_HIGH:
974 link_rate = "HBR";
975 break;
976 case LINK_RATE_HIGH2:
977 link_rate = "HBR2";
978 break;
979 case LINK_RATE_RBR2:
980 link_rate = "RBR2";
981 break;
982 case LINK_RATE_HIGH3:
983 link_rate = "HBR3";
984 break;
985 default:
986 break;
987 }
988
989 /* Connectivity log: link training */
d0778ebf 990 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
4562236b
HW		 991 link_rate,
992 lt_settings.link_settings.lane_count,
820e3935
DW		 993 (status == LINK_TRAINING_SUCCESS) ? "pass" :
994 ((status == LINK_TRAINING_CR_FAIL) ? "CR failed" :
995 "EQ failed"),
4562236b
HW		 996 lt_settings.lane_settings[0].VOLTAGE_SWING,
997 lt_settings.lane_settings[0].PRE_EMPHASIS);
998
999 return status;
1000}
1001
1002
1003bool perform_link_training_with_retries(
d0778ebf 1004 struct dc_link *link,
4562236b
HW		 1005 const struct dc_link_settings *link_setting,
1006 bool skip_video_pattern,
1007 int attempts)
1008{
1009 uint8_t j;
1010 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1011
1012 for (j = 0; j < attempts; ++j) {
1013
1014 if (dc_link_dp_perform_link_training(
d0778ebf 1015 link,
4562236b 1016 link_setting,
820e3935 1017 skip_video_pattern) == LINK_TRAINING_SUCCESS)
4562236b
HW		 1018 return true;
1019
1020 msleep(delay_between_attempts);
1021 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1022 }
1023
1024 return false;
1025}
1026
d0778ebf 1027static struct dc_link_settings get_max_link_cap(struct dc_link *link)
4562236b
HW		 1028{
1029 /* Set Default link settings */
1030 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1031 LINK_SPREAD_05_DOWNSPREAD_30KHZ};
1032
1033 /* Higher link settings based on feature supported */
1034 if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1035 max_link_cap.link_rate = LINK_RATE_HIGH2;
1036
1037 if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1038 max_link_cap.link_rate = LINK_RATE_HIGH3;
1039
1040 /* Lower link settings based on sink's link cap */
d0778ebf 1041 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
4562236b 1042 max_link_cap.lane_count =
d0778ebf
HW		 1043 link->reported_link_cap.lane_count;
1044 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
4562236b 1045 max_link_cap.link_rate =
d0778ebf
HW		 1046 link->reported_link_cap.link_rate;
1047 if (link->reported_link_cap.link_spread <
4562236b
HW		 1048 max_link_cap.link_spread)
1049 max_link_cap.link_spread =
d0778ebf 1050 link->reported_link_cap.link_spread;
4562236b
HW		 1051 return max_link_cap;
1052}
1053
1054bool dp_hbr_verify_link_cap(
d0778ebf 1055 struct dc_link *link,
4562236b
HW		 1056 struct dc_link_settings *known_limit_link_setting)
1057{
1058 struct dc_link_settings max_link_cap = {0};
820e3935
DW		 1059 struct dc_link_settings cur_link_setting = {0};
1060 struct dc_link_settings *cur = &cur_link_setting;
1061 struct dc_link_settings initial_link_settings = {0};
4562236b
HW		 1062 bool success;
1063 bool skip_link_training;
4562236b 1064 bool skip_video_pattern;
4562236b
HW		 1065 struct clock_source *dp_cs;
1066 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
820e3935 1067 enum link_training_result status;
4562236b
HW		 1068
1069 success = false;
1070 skip_link_training = false;
1071
1072 max_link_cap = get_max_link_cap(link);
1073
1074 /* TODO implement override and monitor patch later */
1075
1076 /* try to train the link from high to low to
1077 * find the physical link capability
1078 */
1079 /* disable PHY done possible by BIOS, will be done by driver itself */
d0778ebf 1080 dp_disable_link_phy(link, link->connector_signal);
4562236b
HW		 1081
1082 dp_cs = link->dc->res_pool->dp_clock_source;
1083
1084 if (dp_cs)
1085 dp_cs_id = dp_cs->id;
1086 else {
1087 /*
1088 * dp clock source is not initialized for some reason.
1089 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1090 */
1091 ASSERT(dp_cs);
1092 }
1093
820e3935
DW		 1094 /* link training starts with the maximum common settings
1095 * supported by both sink and ASIC.
1096 */
1097 initial_link_settings = get_common_supported_link_settings(
1098 *known_limit_link_setting,
1099 max_link_cap);
1100 cur_link_setting = initial_link_settings;
1101 do {
4562236b 1102 skip_video_pattern = true;
820e3935 1103
4562236b
HW		 1104 if (cur->link_rate == LINK_RATE_LOW)
1105 skip_video_pattern = false;
1106
1107 dp_enable_link_phy(
1108 link,
d0778ebf 1109 link->connector_signal,
4562236b
HW		 1110 dp_cs_id,
1111 cur);
1112
1113 if (skip_link_training)
1114 success = true;
1115 else {
820e3935 1116 status = dc_link_dp_perform_link_training(
d0778ebf 1117 link,
4562236b
HW		 1118 cur,
1119 skip_video_pattern);
820e3935
DW		 1120 if (status == LINK_TRAINING_SUCCESS)
1121 success = true;
4562236b
HW		 1122 }
1123
1124 if (success)
d0778ebf 1125 link->verified_link_cap = *cur;
4562236b
HW		 1126
1127 /* always disable the link before trying another
1128 * setting or before returning we'll enable it later
1129 * based on the actual mode we're driving
1130 */
d0778ebf 1131 dp_disable_link_phy(link, link->connector_signal);
820e3935
DW		 1132 } while (!success && decide_fallback_link_setting(
1133 initial_link_settings, cur, status));
4562236b
HW		 1134
1135 /* Link Training failed for all Link Settings
1136 * (Lane Count is still unknown)
1137 */
1138 if (!success) {
1139 /* If all LT fails for all settings,
1140 * set verified = failed safe (1 lane low)
1141 */
d0778ebf
HW		 1142 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1143 link->verified_link_cap.link_rate = LINK_RATE_LOW;
4562236b 1144
d0778ebf 1145 link->verified_link_cap.link_spread =
4562236b
HW		 1146 LINK_SPREAD_DISABLED;
1147 }
1148
4562236b
HW		 1149
1150 return success;
1151}
1152
820e3935
DW		 1153struct dc_link_settings get_common_supported_link_settings (
1154 struct dc_link_settings link_setting_a,
1155 struct dc_link_settings link_setting_b)
1156{
1157 struct dc_link_settings link_settings = {0};
1158
1159 link_settings.lane_count =
1160 (link_setting_a.lane_count <=
1161 link_setting_b.lane_count) ?
1162 link_setting_a.lane_count :
1163 link_setting_b.lane_count;
1164 link_settings.link_rate =
1165 (link_setting_a.link_rate <=
1166 link_setting_b.link_rate) ?
1167 link_setting_a.link_rate :
1168 link_setting_b.link_rate;
1169 link_settings.link_spread = LINK_SPREAD_DISABLED;
1170
1171 /* in DP compliance test, DPR-120 may have
1172 * a random value in its MAX_LINK_BW dpcd field.
1173 * We map it to the maximum supported link rate that
1174 * is smaller than MAX_LINK_BW in this case.
1175 */
1176 if (link_settings.link_rate > LINK_RATE_HIGH3) {
1177 link_settings.link_rate = LINK_RATE_HIGH3;
1178 } else if (link_settings.link_rate < LINK_RATE_HIGH3
1179 && link_settings.link_rate > LINK_RATE_HIGH2) {
1180 link_settings.link_rate = LINK_RATE_HIGH2;
1181 } else if (link_settings.link_rate < LINK_RATE_HIGH2
1182 && link_settings.link_rate > LINK_RATE_HIGH) {
1183 link_settings.link_rate = LINK_RATE_HIGH;
1184 } else if (link_settings.link_rate < LINK_RATE_HIGH
1185 && link_settings.link_rate > LINK_RATE_LOW) {
1186 link_settings.link_rate = LINK_RATE_LOW;
1187 } else if (link_settings.link_rate < LINK_RATE_LOW) {
1188 link_settings.link_rate = LINK_RATE_UNKNOWN;
1189 }
1190
1191 return link_settings;
1192}
1193
1194bool reached_minimum_lane_count(enum dc_lane_count lane_count)
1195{
1196 return lane_count <= LANE_COUNT_ONE;
1197}
1198
1199bool reached_minimum_link_rate(enum dc_link_rate link_rate)
1200{
1201 return link_rate <= LINK_RATE_LOW;
1202}
1203
1204enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
1205{
1206 switch (lane_count) {
1207 case LANE_COUNT_FOUR:
1208 return LANE_COUNT_TWO;
1209 case LANE_COUNT_TWO:
1210 return LANE_COUNT_ONE;
1211 case LANE_COUNT_ONE:
1212 return LANE_COUNT_UNKNOWN;
1213 default:
1214 return LANE_COUNT_UNKNOWN;
1215 }
1216}
1217
1218enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
1219{
1220 switch (link_rate) {
1221 case LINK_RATE_HIGH3:
1222 return LINK_RATE_HIGH2;
1223 case LINK_RATE_HIGH2:
1224 return LINK_RATE_HIGH;
1225 case LINK_RATE_HIGH:
1226 return LINK_RATE_LOW;
1227 case LINK_RATE_LOW:
1228 return LINK_RATE_UNKNOWN;
1229 default:
1230 return LINK_RATE_UNKNOWN;
1231 }
1232}
1233
8c4abe0b
DW		 1234enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
1235{
1236 switch (lane_count) {
1237 case LANE_COUNT_ONE:
1238 return LANE_COUNT_TWO;
1239 case LANE_COUNT_TWO:
1240 return LANE_COUNT_FOUR;
1241 default:
1242 return LANE_COUNT_UNKNOWN;
1243 }
1244}
1245
1246enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
1247{
1248 switch (link_rate) {
1249 case LINK_RATE_LOW:
1250 return LINK_RATE_HIGH;
1251 case LINK_RATE_HIGH:
1252 return LINK_RATE_HIGH2;
1253 case LINK_RATE_HIGH2:
1254 return LINK_RATE_HIGH3;
1255 default:
1256 return LINK_RATE_UNKNOWN;
1257 }
1258}
1259
820e3935
DW		 1260/*
1261 * function: set link rate and lane count fallback based
1262 * on current link setting and last link training result
1263 * return value:
1264 * true - link setting could be set
1265 * false - has reached minimum setting
1266 * and no further fallback could be done
1267 */
1268bool decide_fallback_link_setting(
1269 struct dc_link_settings initial_link_settings,
1270 struct dc_link_settings *current_link_setting,
1271 enum link_training_result training_result)
1272{
1273 if (!current_link_setting)
1274 return false;
1275
1276 switch (training_result) {
1277 case LINK_TRAINING_CR_FAIL:
1278 {
1279 if (!reached_minimum_link_rate
1280 (current_link_setting->link_rate)) {
1281 current_link_setting->link_rate =
1282 reduce_link_rate(
1283 current_link_setting->link_rate);
1284 } else if (!reached_minimum_lane_count
1285 (current_link_setting->lane_count)) {
1286 current_link_setting->link_rate =
1287 initial_link_settings.link_rate;
1288 current_link_setting->lane_count =
1289 reduce_lane_count(
1290 current_link_setting->lane_count);
1291 } else {
1292 return false;
1293 }
1294 break;
1295 }
1296 case LINK_TRAINING_EQ_FAIL_EQ:
1297 {
1298 if (!reached_minimum_lane_count
1299 (current_link_setting->lane_count)) {
1300 current_link_setting->lane_count =
1301 reduce_lane_count(
1302 current_link_setting->lane_count);
1303 } else if (!reached_minimum_link_rate
1304 (current_link_setting->link_rate)) {
1305 current_link_setting->lane_count =
1306 initial_link_settings.lane_count;
1307 current_link_setting->link_rate =
1308 reduce_link_rate(
1309 current_link_setting->link_rate);
1310 } else {
1311 return false;
1312 }
1313 break;
1314 }
1315 case LINK_TRAINING_EQ_FAIL_CR:
1316 {
1317 if (!reached_minimum_link_rate
1318 (current_link_setting->link_rate)) {
1319 current_link_setting->link_rate =
1320 reduce_link_rate(
1321 current_link_setting->link_rate);
1322 } else {
1323 return false;
1324 }
1325 break;
1326 }
1327 default:
1328 return false;
1329 }
1330 return true;
1331}
1332
4562236b
HW		 1333static uint32_t bandwidth_in_kbps_from_timing(
1334 const struct dc_crtc_timing *timing)
1335{
1336 uint32_t bits_per_channel = 0;
1337 uint32_t kbps;
1338 switch (timing->display_color_depth) {
1339
1340 case COLOR_DEPTH_666:
1341 bits_per_channel = 6;
1342 break;
1343 case COLOR_DEPTH_888:
1344 bits_per_channel = 8;
1345 break;
1346 case COLOR_DEPTH_101010:
1347 bits_per_channel = 10;
1348 break;
1349 case COLOR_DEPTH_121212:
1350 bits_per_channel = 12;
1351 break;
1352 case COLOR_DEPTH_141414:
1353 bits_per_channel = 14;
1354 break;
1355 case COLOR_DEPTH_161616:
1356 bits_per_channel = 16;
1357 break;
1358 default:
1359 break;
1360 }
1361 ASSERT(bits_per_channel != 0);
1362
1363 kbps = timing->pix_clk_khz;
1364 kbps *= bits_per_channel;
1365
1366 if (timing->flags.Y_ONLY != 1)
1367 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
1368 kbps *= 3;
1369
1370 return kbps;
1371
1372}
1373
1374static uint32_t bandwidth_in_kbps_from_link_settings(
1375 const struct dc_link_settings *link_setting)
1376{
1377 uint32_t link_rate_in_kbps = link_setting->link_rate *
1378 LINK_RATE_REF_FREQ_IN_KHZ;
1379
1380 uint32_t lane_count = link_setting->lane_count;
1381 uint32_t kbps = link_rate_in_kbps;
1382 kbps *= lane_count;
1383 kbps *= 8; /* 8 bits per byte*/
1384
1385 return kbps;
1386
1387}
1388
1389bool dp_validate_mode_timing(
d0778ebf 1390 struct dc_link *link,
4562236b
HW		 1391 const struct dc_crtc_timing *timing)
1392{
1393 uint32_t req_bw;
1394 uint32_t max_bw;
1395
1396 const struct dc_link_settings *link_setting;
1397
1398 /*always DP fail safe mode*/
1399 if (timing->pix_clk_khz == (uint32_t)25175 &&
1400 timing->h_addressable == (uint32_t)640 &&
1401 timing->v_addressable == (uint32_t)480)
1402 return true;
1403
1404 /* We always use verified link settings */
d0778ebf 1405 link_setting = &link->verified_link_cap;
4562236b
HW		 1406
1407 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1408 /*if (flags.DYNAMIC_VALIDATION == 1 &&
d0778ebf
HW		 1409 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
1410 link_setting = &link->verified_link_cap;
4562236b
HW		 1411 */
1412
1413 req_bw = bandwidth_in_kbps_from_timing(timing);
1414 max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
1415
1416 if (req_bw <= max_bw) {
1417 /* remember the biggest mode here, during
1418 * initial link training (to get
1419 * verified_link_cap), LS sends event about
1420 * cannot train at reported cap to upper
1421 * layer and upper layer will re-enumerate modes.
1422 * this is not necessary if the lower
1423 * verified_link_cap is enough to drive
1424 * all the modes */
1425
1426 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1427 /* if (flags.DYNAMIC_VALIDATION == 1)
1428 dpsst->max_req_bw_for_verified_linkcap = dal_max(
1429 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
1430 return true;
1431 } else
1432 return false;
1433}
1434
0971c40e 1435void decide_link_settings(struct dc_stream_state *stream,
4562236b
HW		 1436 struct dc_link_settings *link_setting)
1437{
1438
8c4abe0b
DW		 1439 struct dc_link_settings initial_link_setting = {
1440 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED};
1441 struct dc_link_settings current_link_setting =
1442 initial_link_setting;
d0778ebf 1443 struct dc_link *link;
4562236b
HW		 1444 uint32_t req_bw;
1445 uint32_t link_bw;
4562236b 1446
4fa086b9 1447 req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
4562236b 1448
8c4abe0b
DW		 1449 link = stream->sink->link;
1450
4562236b
HW		 1451 /* if preferred is specified through AMDDP, use it, if it's enough
1452 * to drive the mode
1453 */
d0778ebf 1454 if (link->preferred_link_setting.lane_count !=
8c4abe0b 1455 LANE_COUNT_UNKNOWN &&
d0778ebf 1456 link->preferred_link_setting.link_rate !=
8c4abe0b 1457 LINK_RATE_UNKNOWN) {
d0778ebf 1458 *link_setting = link->preferred_link_setting;
8c4abe0b
DW		 1459 return;
1460 }
4562236b 1461
8c4abe0b
DW		 1462 /* search for the minimum link setting that:
1463 * 1. is supported according to the link training result
1464 * 2. could support the b/w requested by the timing
1465 */
1466 while (current_link_setting.link_rate <=
4654a2f7 1467 link->verified_link_cap.link_rate) {
4562236b 1468 link_bw = bandwidth_in_kbps_from_link_settings(
8c4abe0b
DW		 1469 &current_link_setting);
1470 if (req_bw <= link_bw) {
1471 *link_setting = current_link_setting;
4562236b
HW		 1472 return;
1473 }
4562236b 1474
8c4abe0b 1475 if (current_link_setting.lane_count <
4654a2f7 1476 link->verified_link_cap.lane_count) {
8c4abe0b
DW		 1477 current_link_setting.lane_count =
1478 increase_lane_count(
1479 current_link_setting.lane_count);
1480 } else {
1481 current_link_setting.link_rate =
1482 increase_link_rate(
1483 current_link_setting.link_rate);
1484 current_link_setting.lane_count =
1485 initial_link_setting.lane_count;
4562236b
HW		 1486 }
1487 }
1488
1489 BREAK_TO_DEBUGGER();
d0778ebf 1490 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
4562236b 1491
d0778ebf 1492 *link_setting = link->verified_link_cap;
4562236b
HW		 1493}
1494
1495/*************************Short Pulse IRQ***************************/
1496
1497static bool hpd_rx_irq_check_link_loss_status(
d0778ebf 1498 struct dc_link *link,
4562236b
HW		 1499 union hpd_irq_data *hpd_irq_dpcd_data)
1500{
1501 uint8_t irq_reg_rx_power_state;
1502 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1503 union lane_status lane_status;
1504 uint32_t lane;
1505 bool sink_status_changed;
1506 bool return_code;
1507
1508 sink_status_changed = false;
1509 return_code = false;
1510
d0778ebf 1511 if (link->cur_link_settings.lane_count == 0)
4562236b
HW		 1512 return return_code;
1513 /*1. Check that we can handle interrupt: Not in FS DOS,
1514 * Not in "Display Timeout" state, Link is trained.
1515 */
1516
1517 dpcd_result = core_link_read_dpcd(link,
3a340294 1518 DP_SET_POWER,
4562236b
HW		 1519 &irq_reg_rx_power_state,
1520 sizeof(irq_reg_rx_power_state));
1521
1522 if (dpcd_result != DC_OK) {
3a340294 1523 irq_reg_rx_power_state = DP_SET_POWER_D0;
4562236b
HW		 1524 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1525 "%s: DPCD read failed to obtain power state.\n",
1526 __func__);
1527 }
1528
3a340294 1529 if (irq_reg_rx_power_state == DP_SET_POWER_D0) {
4562236b
HW		 1530
1531 /*2. Check that Link Status changed, before re-training.*/
1532
1533 /*parse lane status*/
1534 for (lane = 0;
d0778ebf 1535 lane < link->cur_link_settings.lane_count;
4562236b
HW		 1536 lane++) {
1537
1538 /* check status of lanes 0,1
1539 * changed DpcdAddress_Lane01Status (0x202)*/
1540 lane_status.raw = get_nibble_at_index(
1541 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1542 lane);
1543
1544 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1545 !lane_status.bits.CR_DONE_0 ||
1546 !lane_status.bits.SYMBOL_LOCKED_0) {
1547 /* if one of the channel equalization, clock
1548 * recovery or symbol lock is dropped
1549 * consider it as (link has been
1550 * dropped) dp sink status has changed*/
1551 sink_status_changed = true;
1552 break;
1553 }
1554
1555 }
1556
1557 /* Check interlane align.*/
1558 if (sink_status_changed ||
1559 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.
1560 INTERLANE_ALIGN_DONE) {
1561
1562 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1563 "%s: Link Status changed.\n",
1564 __func__);
1565
1566 return_code = true;
1567 }
1568 }
1569
1570 return return_code;
1571}
1572
1573static enum dc_status read_hpd_rx_irq_data(
d0778ebf 1574 struct dc_link *link,
4562236b
HW		 1575 union hpd_irq_data *irq_data)
1576{
1577 /* The HW reads 16 bytes from 200h on HPD,
1578 * but if we get an AUX_DEFER, the HW cannot retry
1579 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1580 * fail, so we now explicitly read 6 bytes which is
1581 * the req from the above mentioned test cases.
1582 */
1583 return core_link_read_dpcd(
1584 link,
3a340294 1585 DP_SINK_COUNT,
4562236b
HW		 1586 irq_data->raw,
1587 sizeof(union hpd_irq_data));
1588}
1589
d0778ebf 1590static bool allow_hpd_rx_irq(const struct dc_link *link)
4562236b
HW		 1591{
1592 /*
1593 * Don't handle RX IRQ unless one of following is met:
1594 * 1) The link is established (cur_link_settings != unknown)
1595 * 2) We kicked off MST detection
1596 * 3) We know we're dealing with an active dongle
1597 */
1598
d0778ebf
HW		 1599 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1600 (link->type == dc_connection_mst_branch) ||
4562236b
HW		 1601 is_dp_active_dongle(link))
1602 return true;
1603
1604 return false;
1605}
1606
d0778ebf 1607static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
4562236b
HW		 1608{
1609 union dpcd_psr_configuration psr_configuration;
1610
94267b3d 1611 if (!link->psr_enabled)
4562236b
HW		 1612 return false;
1613
7c7f5b15
AG		 1614 dm_helpers_dp_read_dpcd(
1615 link->ctx,
d0778ebf 1616 link,
7c7f5b15
AG		 1617 368,/*DpcdAddress_PSR_Enable_Cfg*/
1618 &psr_configuration.raw,
1619 sizeof(psr_configuration.raw));
1620
4562236b
HW		 1621
1622 if (psr_configuration.bits.ENABLE) {
1623 unsigned char dpcdbuf[3] = {0};
1624 union psr_error_status psr_error_status;
1625 union psr_sink_psr_status psr_sink_psr_status;
1626
7c7f5b15
AG		 1627 dm_helpers_dp_read_dpcd(
1628 link->ctx,
d0778ebf 1629 link,
7c7f5b15
AG		 1630 0x2006, /*DpcdAddress_PSR_Error_Status*/
1631 (unsigned char *) dpcdbuf,
1632 sizeof(dpcdbuf));
4562236b
HW		 1633
1634 /*DPCD 2006h ERROR STATUS*/
1635 psr_error_status.raw = dpcdbuf[0];
1636 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
1637 psr_sink_psr_status.raw = dpcdbuf[2];
1638
1639 if (psr_error_status.bits.LINK_CRC_ERROR ||
1640 psr_error_status.bits.RFB_STORAGE_ERROR) {
1641 /* Acknowledge and clear error bits */
7c7f5b15
AG		 1642 dm_helpers_dp_write_dpcd(
1643 link->ctx,
d0778ebf 1644 link,
7c7f5b15 1645 8198,/*DpcdAddress_PSR_Error_Status*/
4562236b
HW		 1646 &psr_error_status.raw,
1647 sizeof(psr_error_status.raw));
1648
1649 /* PSR error, disable and re-enable PSR */
d0778ebf
HW		 1650 dc_link_set_psr_enable(link, false);
1651 dc_link_set_psr_enable(link, true);
4562236b
HW		 1652
1653 return true;
1654 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
1655 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
1656 /* No error is detect, PSR is active.
1657 * We should return with IRQ_HPD handled without
1658 * checking for loss of sync since PSR would have
1659 * powered down main link.
1660 */
1661 return true;
1662 }
1663 }
1664 return false;
1665}
1666
d0778ebf 1667static void dp_test_send_link_training(struct dc_link *link)
4562236b 1668{
73c72602 1669 struct dc_link_settings link_settings = {0};
4562236b
HW		 1670
1671 core_link_read_dpcd(
1672 link,
3a340294 1673 DP_TEST_LANE_COUNT,
4562236b
HW		 1674 (unsigned char *)(&link_settings.lane_count),
1675 1);
1676 core_link_read_dpcd(
1677 link,
3a340294 1678 DP_TEST_LINK_RATE,
4562236b
HW		 1679 (unsigned char *)(&link_settings.link_rate),
1680 1);
1681
1682 /* Set preferred link settings */
d0778ebf
HW		 1683 link->verified_link_cap.lane_count = link_settings.lane_count;
1684 link->verified_link_cap.link_rate = link_settings.link_rate;
4562236b 1685
73c72602 1686 dp_retrain_link_dp_test(link, &link_settings, false);
4562236b
HW		 1687}
1688
d0778ebf 1689static void dp_test_send_phy_test_pattern(struct dc_link *link)
4562236b
HW		 1690{
1691 union phy_test_pattern dpcd_test_pattern;
1692 union lane_adjust dpcd_lane_adjustment[2];
1693 unsigned char dpcd_post_cursor_2_adjustment = 0;
1694 unsigned char test_80_bit_pattern[
3a340294
DA		 1695 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1696 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
4562236b
HW		 1697 enum dp_test_pattern test_pattern;
1698 struct dc_link_training_settings link_settings;
1699 union lane_adjust dpcd_lane_adjust;
1700 unsigned int lane;
1701 struct link_training_settings link_training_settings;
1702 int i = 0;
1703
1704 dpcd_test_pattern.raw = 0;
1705 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
1706 memset(&link_settings, 0, sizeof(link_settings));
1707
1708 /* get phy test pattern and pattern parameters from DP receiver */
1709 core_link_read_dpcd(
1710 link,
3a340294 1711 DP_TEST_PHY_PATTERN,
4562236b
HW		 1712 &dpcd_test_pattern.raw,
1713 sizeof(dpcd_test_pattern));
1714 core_link_read_dpcd(
1715 link,
3a340294 1716 DP_ADJUST_REQUEST_LANE0_1,
4562236b
HW		 1717 &dpcd_lane_adjustment[0].raw,
1718 sizeof(dpcd_lane_adjustment));
1719
1720 /*get post cursor 2 parameters
1721 * For DP 1.1a or eariler, this DPCD register's value is 0
1722 * For DP 1.2 or later:
1723 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
1724 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
1725 */
1726 core_link_read_dpcd(
1727 link,
3a340294 1728 DP_ADJUST_REQUEST_POST_CURSOR2,
4562236b
HW		 1729 &dpcd_post_cursor_2_adjustment,
1730 sizeof(dpcd_post_cursor_2_adjustment));
1731
1732 /* translate request */
1733 switch (dpcd_test_pattern.bits.PATTERN) {
1734 case PHY_TEST_PATTERN_D10_2:
1735 test_pattern = DP_TEST_PATTERN_D102;
0e19401f 1736 break;
4562236b
HW		 1737 case PHY_TEST_PATTERN_SYMBOL_ERROR:
1738 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 1739 break;
4562236b
HW		 1740 case PHY_TEST_PATTERN_PRBS7:
1741 test_pattern = DP_TEST_PATTERN_PRBS7;
0e19401f 1742 break;
4562236b
HW		 1743 case PHY_TEST_PATTERN_80BIT_CUSTOM:
1744 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 1745 break;
1746 case PHY_TEST_PATTERN_CP2520_1:
1747 test_pattern = DP_TEST_PATTERN_CP2520_1;
1748 break;
1749 case PHY_TEST_PATTERN_CP2520_2:
1750 test_pattern = DP_TEST_PATTERN_CP2520_2;
1751 break;
1752 case PHY_TEST_PATTERN_CP2520_3:
1753 test_pattern = DP_TEST_PATTERN_CP2520_3;
1754 break;
4562236b
HW		 1755 default:
1756 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1757 break;
1758 }
1759
1760 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
1761 core_link_read_dpcd(
1762 link,
3a340294 1763 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
4562236b
HW		 1764 test_80_bit_pattern,
1765 sizeof(test_80_bit_pattern));
1766
1767 /* prepare link training settings */
d0778ebf 1768 link_settings.link = link->cur_link_settings;
4562236b
HW		 1769
1770 for (lane = 0; lane <
d0778ebf 1771 (unsigned int)(link->cur_link_settings.lane_count);
4562236b
HW		 1772 lane++) {
1773 dpcd_lane_adjust.raw =
1774 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
1775 link_settings.lane_settings[lane].VOLTAGE_SWING =
1776 (enum dc_voltage_swing)
1777 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
1778 link_settings.lane_settings[lane].PRE_EMPHASIS =
1779 (enum dc_pre_emphasis)
1780 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
1781 link_settings.lane_settings[lane].POST_CURSOR2 =
1782 (enum dc_post_cursor2)
1783 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
1784 }
1785
1786 for (i = 0; i < 4; i++)
1787 link_training_settings.lane_settings[i] =
1788 link_settings.lane_settings[i];
1789 link_training_settings.link_settings = link_settings.link;
1790 link_training_settings.allow_invalid_msa_timing_param = false;
1791 /*Usage: Measure DP physical lane signal
1792 * by DP SI test equipment automatically.
1793 * PHY test pattern request is generated by equipment via HPD interrupt.
1794 * HPD needs to be active all the time. HPD should be active
1795 * all the time. Do not touch it.
1796 * forward request to DS
1797 */
1798 dc_link_dp_set_test_pattern(
d0778ebf 1799 link,
4562236b
HW		 1800 test_pattern,
1801 &link_training_settings,
1802 test_80_bit_pattern,
3a340294
DA		 1803 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1804 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
4562236b
HW		 1805}
1806
d0778ebf 1807static void dp_test_send_link_test_pattern(struct dc_link *link)
4562236b
HW		 1808{
1809 union link_test_pattern dpcd_test_pattern;
1810 union test_misc dpcd_test_params;
1811 enum dp_test_pattern test_pattern;
1812
1813 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
1814 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
1815
1816 /* get link test pattern and pattern parameters */
1817 core_link_read_dpcd(
1818 link,
3a340294 1819 DP_TEST_PATTERN,
4562236b
HW		 1820 &dpcd_test_pattern.raw,
1821 sizeof(dpcd_test_pattern));
1822 core_link_read_dpcd(
1823 link,
3a340294 1824 DP_TEST_MISC0,
4562236b
HW		 1825 &dpcd_test_params.raw,
1826 sizeof(dpcd_test_params));
1827
1828 switch (dpcd_test_pattern.bits.PATTERN) {
1829 case LINK_TEST_PATTERN_COLOR_RAMP:
1830 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1831 break;
1832 case LINK_TEST_PATTERN_VERTICAL_BARS:
1833 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1834 break; /* black and white */
1835 case LINK_TEST_PATTERN_COLOR_SQUARES:
1836 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1837 TEST_DYN_RANGE_VESA ?
1838 DP_TEST_PATTERN_COLOR_SQUARES :
1839 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1840 break;
1841 default:
1842 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1843 break;
1844 }
1845
1846 dc_link_dp_set_test_pattern(
d0778ebf 1847 link,
4562236b
HW		 1848 test_pattern,
1849 NULL,
1850 NULL,
1851 0);
1852}
1853
d0778ebf 1854static void handle_automated_test(struct dc_link *link)
4562236b
HW		 1855{
1856 union test_request test_request;
1857 union test_response test_response;
1858
1859 memset(&test_request, 0, sizeof(test_request));
1860 memset(&test_response, 0, sizeof(test_response));
1861
1862 core_link_read_dpcd(
1863 link,
3a340294 1864 DP_TEST_REQUEST,
4562236b
HW		 1865 &test_request.raw,
1866 sizeof(union test_request));
1867 if (test_request.bits.LINK_TRAINING) {
1868 /* ACK first to let DP RX test box monitor LT sequence */
1869 test_response.bits.ACK = 1;
1870 core_link_write_dpcd(
1871 link,
3a340294 1872 DP_TEST_RESPONSE,
4562236b
HW		 1873 &test_response.raw,
1874 sizeof(test_response));
1875 dp_test_send_link_training(link);
1876 /* no acknowledge request is needed again */
1877 test_response.bits.ACK = 0;
1878 }
1879 if (test_request.bits.LINK_TEST_PATTRN) {
1880 dp_test_send_link_test_pattern(link);
75a74755 1881 test_response.bits.ACK = 1;
4562236b
HW		 1882 }
1883 if (test_request.bits.PHY_TEST_PATTERN) {
1884 dp_test_send_phy_test_pattern(link);
1885 test_response.bits.ACK = 1;
1886 }
1887 if (!test_request.raw)
1888 /* no requests, revert all test signals
1889 * TODO: revert all test signals
1890 */
1891 test_response.bits.ACK = 1;
1892 /* send request acknowledgment */
1893 if (test_response.bits.ACK)
1894 core_link_write_dpcd(
1895 link,
3a340294 1896 DP_TEST_RESPONSE,
4562236b
HW		 1897 &test_response.raw,
1898 sizeof(test_response));
1899}
1900
d0778ebf 1901bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data)
4562236b 1902{
4562236b 1903 union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}};
c2e218dd 1904 union device_service_irq device_service_clear = { { 0 } };
4562236b
HW		 1905 enum dc_status result = DDC_RESULT_UNKNOWN;
1906 bool status = false;
1907 /* For use cases related to down stream connection status change,
1908 * PSR and device auto test, refer to function handle_sst_hpd_irq
1909 * in DAL2.1*/
1910
1911 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1912 "%s: Got short pulse HPD on link %d\n",
d0778ebf 1913 __func__, link->link_index);
4562236b 1914
8ee65d7c 1915
4562236b
HW		 1916 /* All the "handle_hpd_irq_xxx()" methods
1917 * should be called only after
1918 * dal_dpsst_ls_read_hpd_irq_data
1919 * Order of calls is important too
1920 */
1921 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
8ee65d7c
WL		 1922 if (out_hpd_irq_dpcd_data)
1923 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4562236b
HW		 1924
1925 if (result != DC_OK) {
1926 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1927 "%s: DPCD read failed to obtain irq data\n",
1928 __func__);
1929 return false;
1930 }
1931
1932 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1933 device_service_clear.bits.AUTOMATED_TEST = 1;
1934 core_link_write_dpcd(
1935 link,
3a340294 1936 DP_DEVICE_SERVICE_IRQ_VECTOR,
4562236b
HW		 1937 &device_service_clear.raw,
1938 sizeof(device_service_clear.raw));
1939 device_service_clear.raw = 0;
1940 handle_automated_test(link);
1941 return false;
1942 }
1943
1944 if (!allow_hpd_rx_irq(link)) {
1945 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1946 "%s: skipping HPD handling on %d\n",
d0778ebf 1947 __func__, link->link_index);
4562236b
HW		 1948 return false;
1949 }
1950
1951 if (handle_hpd_irq_psr_sink(link))
1952 /* PSR-related error was detected and handled */
1953 return true;
1954
1955 /* If PSR-related error handled, Main link may be off,
1956 * so do not handle as a normal sink status change interrupt.
1957 */
1958
1959 /* check if we have MST msg and return since we poll for it */
1960 if (hpd_irq_dpcd_data.bytes.device_service_irq.
1961 bits.DOWN_REP_MSG_RDY ||
1962 hpd_irq_dpcd_data.bytes.device_service_irq.
1963 bits.UP_REQ_MSG_RDY)
1964 return false;
1965
1966 /* For now we only handle 'Downstream port status' case.
1967 * If we got sink count changed it means
1968 * Downstream port status changed,
1969 * then DM should call DC to do the detection. */
1970 if (hpd_rx_irq_check_link_loss_status(
1971 link,
1972 &hpd_irq_dpcd_data)) {
1973 /* Connectivity log: link loss */
1974 CONN_DATA_LINK_LOSS(link,
1975 hpd_irq_dpcd_data.raw,
1976 sizeof(hpd_irq_dpcd_data),
1977 "Status: ");
1978
1979 perform_link_training_with_retries(link,
d0778ebf 1980 &link->cur_link_settings,
4562236b
HW		 1981 true, LINK_TRAINING_ATTEMPTS);
1982
1983 status = false;
1984 }
1985
d0778ebf 1986 if (link->type == dc_connection_active_dongle &&
4562236b
HW		 1987 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
1988 != link->dpcd_sink_count)
1989 status = true;
1990
1991 /* reasons for HPD RX:
1992 * 1. Link Loss - ie Re-train the Link
1993 * 2. MST sideband message
1994 * 3. Automated Test - ie. Internal Commit
1995 * 4. CP (copy protection) - (not interesting for DM???)
1996 * 5. DRR
1997 * 6. Downstream Port status changed
1998 * -ie. Detect - this the only one
1999 * which is interesting for DM because
2000 * it must call dc_link_detect.
2001 */
2002 return status;
2003}
2004
2005/*query dpcd for version and mst cap addresses*/
d0778ebf 2006bool is_mst_supported(struct dc_link *link)
4562236b
HW		 2007{
2008 bool mst = false;
2009 enum dc_status st = DC_OK;
2010 union dpcd_rev rev;
2011 union mstm_cap cap;
2012
2013 rev.raw = 0;
2014 cap.raw = 0;
2015
3a340294 2016 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4562236b
HW		 2017 sizeof(rev));
2018
2019 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2020
3a340294 2021 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4562236b
HW		 2022 &cap.raw, sizeof(cap));
2023 if (st == DC_OK && cap.bits.MST_CAP == 1)
2024 mst = true;
2025 }
2026 return mst;
2027
2028}
2029
d0778ebf 2030bool is_dp_active_dongle(const struct dc_link *link)
4562236b
HW		 2031{
2032 enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
2033
2034 return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
2035 (dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
2036 (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
2037}
2038
2039static void get_active_converter_info(
d0778ebf 2040 uint8_t data, struct dc_link *link)
4562236b
HW		 2041{
2042 union dp_downstream_port_present ds_port = { .byte = data };
2043
2044 /* decode converter info*/
2045 if (!ds_port.fields.PORT_PRESENT) {
2046 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
d0778ebf 2047 ddc_service_set_dongle_type(link->ddc,
4562236b
HW		 2048 link->dpcd_caps.dongle_type);
2049 return;
2050 }
2051
2052 switch (ds_port.fields.PORT_TYPE) {
2053 case DOWNSTREAM_VGA:
2054 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
2055 break;
2056 case DOWNSTREAM_DVI_HDMI:
2057 /* At this point we don't know is it DVI or HDMI,
2058 * assume DVI.*/
2059 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
2060 break;
2061 default:
2062 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2063 break;
2064 }
2065
ac0e562c 2066 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
4562236b
HW		 2067 uint8_t det_caps[4];
2068 union dwnstream_port_caps_byte0 *port_caps =
2069 (union dwnstream_port_caps_byte0 *)det_caps;
3a340294 2070 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
4562236b
HW		 2071 det_caps, sizeof(det_caps));
2072
2073 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
2074 case DOWN_STREAM_DETAILED_VGA:
2075 link->dpcd_caps.dongle_type =
2076 DISPLAY_DONGLE_DP_VGA_CONVERTER;
2077 break;
2078 case DOWN_STREAM_DETAILED_DVI:
2079 link->dpcd_caps.dongle_type =
2080 DISPLAY_DONGLE_DP_DVI_CONVERTER;
2081 break;
2082 case DOWN_STREAM_DETAILED_HDMI:
2083 link->dpcd_caps.dongle_type =
2084 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
2085
03f5c686 2086 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
4562236b
HW		 2087 if (ds_port.fields.DETAILED_CAPS) {
2088
2089 union dwnstream_port_caps_byte3_hdmi
2090 hdmi_caps = {.raw = det_caps[3] };
03f5c686
CL		 2091 union dwnstream_port_caps_byte1
2092 hdmi_color_caps = {.raw = det_caps[2] };
2093 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
2094 det_caps[1] * 25000;
4562236b 2095
03f5c686 2096 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
4562236b 2097 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
03f5c686
CL		 2098 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
2099 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
2100 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
2101 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
2102 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
2103 hdmi_caps.bits.YCrCr422_CONVERSION;
2104 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
2105 hdmi_caps.bits.YCrCr420_CONVERSION;
2106
2107 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
2108 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT;
2109
2110 link->dpcd_caps.dongle_caps.extendedCapValid = true;
4562236b 2111 }
03f5c686 2112
4562236b
HW		 2113 break;
2114 }
2115 }
2116
d0778ebf 2117 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4562236b
HW		 2118
2119 {
2120 struct dp_device_vendor_id dp_id;
2121
2122 /* read IEEE branch device id */
2123 core_link_read_dpcd(
2124 link,
3a340294 2125 DP_BRANCH_OUI,
4562236b
HW		 2126 (uint8_t *)&dp_id,
2127 sizeof(dp_id));
2128
2129 link->dpcd_caps.branch_dev_id =
2130 (dp_id.ieee_oui[0] << 16) +
2131 (dp_id.ieee_oui[1] << 8) +
2132 dp_id.ieee_oui[2];
2133
2134 memmove(
2135 link->dpcd_caps.branch_dev_name,
2136 dp_id.ieee_device_id,
2137 sizeof(dp_id.ieee_device_id));
2138 }
2139
2140 {
2141 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2142
2143 core_link_read_dpcd(
2144 link,
3a340294 2145 DP_BRANCH_REVISION_START,
4562236b
HW		 2146 (uint8_t *)&dp_hw_fw_revision,
2147 sizeof(dp_hw_fw_revision));
2148
2149 link->dpcd_caps.branch_hw_revision =
2150 dp_hw_fw_revision.ieee_hw_rev;
2151 }
2152}
2153
d0778ebf 2154static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4562236b
HW		 2155 int length)
2156{
2157 int retry = 0;
2158 union dp_downstream_port_present ds_port = { 0 };
2159
2160 if (!link->dpcd_caps.dpcd_rev.raw) {
2161 do {
2162 dp_receiver_power_ctrl(link, true);
3a340294 2163 core_link_read_dpcd(link, DP_DPCD_REV,
4562236b
HW		 2164 dpcd_data, length);
2165 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3a340294
DA		 2166 DP_DPCD_REV -
2167 DP_DPCD_REV];
4562236b
HW		 2168 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
2169 }
2170
3a340294
DA		 2171 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2172 DP_DPCD_REV];
4562236b
HW		 2173
2174 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
2175 switch (link->dpcd_caps.branch_dev_id) {
2176 /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
2177 * all internal circuits including AUX communication preventing
2178 * reading DPCD table and EDID (spec violation).
2179 * Encoder will skip DP RX power down on disable_output to
2180 * keep receiver powered all the time.*/
2181 case DP_BRANCH_DEVICE_ID_1:
2182 case DP_BRANCH_DEVICE_ID_4:
2183 link->wa_flags.dp_keep_receiver_powered = true;
2184 break;
2185
2186 /* TODO: May need work around for other dongles. */
2187 default:
2188 link->wa_flags.dp_keep_receiver_powered = false;
2189 break;
2190 }
2191 } else
2192 link->wa_flags.dp_keep_receiver_powered = false;
2193}
2194
d0778ebf 2195static void retrieve_link_cap(struct dc_link *link)
4562236b 2196{
3a340294 2197 uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1];
4562236b
HW		 2198
2199 union down_stream_port_count down_strm_port_count;
2200 union edp_configuration_cap edp_config_cap;
2201 union dp_downstream_port_present ds_port = { 0 };
2202
2203 memset(dpcd_data, '\0', sizeof(dpcd_data));
2204 memset(&down_strm_port_count,
2205 '\0', sizeof(union down_stream_port_count));
2206 memset(&edp_config_cap, '\0',
2207 sizeof(union edp_configuration_cap));
2208
2209 core_link_read_dpcd(
2210 link,
3a340294 2211 DP_DPCD_REV,
4562236b
HW		 2212 dpcd_data,
2213 sizeof(dpcd_data));
2214
4562236b
HW		 2215 {
2216 union training_aux_rd_interval aux_rd_interval;
2217
2218 aux_rd_interval.raw =
3a340294 2219 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
4562236b
HW		 2220
2221 if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
2222 core_link_read_dpcd(
2223 link,
3a340294 2224 DP_DP13_DPCD_REV,
4562236b
HW		 2225 dpcd_data,
2226 sizeof(dpcd_data));
2227 }
2228 }
2229
cc04bf7e
TC		 2230 link->dpcd_caps.dpcd_rev.raw =
2231 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
2232
3a340294
DA		 2233 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2234 DP_DPCD_REV];
4562236b
HW		 2235
2236 get_active_converter_info(ds_port.byte, link);
2237
2238 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2239
2240 link->dpcd_caps.allow_invalid_MSA_timing_param =
2241 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2242
2243 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3a340294 2244 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4562236b
HW		 2245
2246 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3a340294 2247 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4562236b 2248
d0778ebf 2249 link->reported_link_cap.lane_count =
4562236b 2250 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
d0778ebf 2251 link->reported_link_cap.link_rate = dpcd_data[
3a340294 2252 DP_MAX_LINK_RATE - DP_DPCD_REV];
d0778ebf 2253 link->reported_link_cap.link_spread =
4562236b
HW		 2254 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
2255 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
2256
2257 edp_config_cap.raw = dpcd_data[
3a340294 2258 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4562236b
HW		 2259 link->dpcd_caps.panel_mode_edp =
2260 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
2261
d0778ebf
HW		 2262 link->test_pattern_enabled = false;
2263 link->compliance_test_state.raw = 0;
4562236b 2264
4562236b
HW		 2265 /* read sink count */
2266 core_link_read_dpcd(link,
3a340294 2267 DP_SINK_COUNT,
4562236b
HW		 2268 &link->dpcd_caps.sink_count.raw,
2269 sizeof(link->dpcd_caps.sink_count.raw));
2270
4562236b
HW		 2271 /* Connectivity log: detection */
2272 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
4562236b
HW		 2273}
2274
d0778ebf 2275void detect_dp_sink_caps(struct dc_link *link)
4562236b
HW		 2276{
2277 retrieve_link_cap(link);
2278
2279 /* dc init_hw has power encoder using default
2280 * signal for connector. For native DP, no
2281 * need to power up encoder again. If not native
2282 * DP, hw_init may need check signal or power up
2283 * encoder here.
2284 */
4562236b
HW		 2285 /* TODO save sink caps in link->sink */
2286}
2287
4654a2f7
RL		 2288void detect_edp_sink_caps(struct dc_link *link)
2289{
2290 retrieve_link_cap(link);
2291 link->verified_link_cap = link->reported_link_cap;
2292}
2293
4562236b
HW		 2294void dc_link_dp_enable_hpd(const struct dc_link *link)
2295{
d0778ebf 2296 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2297
2298 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2299 encoder->funcs->enable_hpd(encoder);
2300}
2301
2302void dc_link_dp_disable_hpd(const struct dc_link *link)
2303{
d0778ebf 2304 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2305
2306 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2307 encoder->funcs->disable_hpd(encoder);
2308}
2309
2310static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
2311{
0e19401f
TC		 2312 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
2313 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
2314 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4562236b
HW		 2315 return true;
2316 else
2317 return false;
2318}
2319
d0778ebf 2320static void set_crtc_test_pattern(struct dc_link *link,
4562236b
HW		 2321 struct pipe_ctx *pipe_ctx,
2322 enum dp_test_pattern test_pattern)
2323{
2324 enum controller_dp_test_pattern controller_test_pattern;
2325 enum dc_color_depth color_depth = pipe_ctx->
4fa086b9 2326 stream->timing.display_color_depth;
4562236b
HW		 2327 struct bit_depth_reduction_params params;
2328
2329 memset(&params, 0, sizeof(params));
2330
2331 switch (test_pattern) {
2332 case DP_TEST_PATTERN_COLOR_SQUARES:
2333 controller_test_pattern =
2334 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2335 break;
2336 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2337 controller_test_pattern =
2338 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
2339 break;
2340 case DP_TEST_PATTERN_VERTICAL_BARS:
2341 controller_test_pattern =
2342 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
2343 break;
2344 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2345 controller_test_pattern =
2346 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
2347 break;
2348 case DP_TEST_PATTERN_COLOR_RAMP:
2349 controller_test_pattern =
2350 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
2351 break;
2352 default:
2353 controller_test_pattern =
2354 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
2355 break;
2356 }
2357
2358 switch (test_pattern) {
2359 case DP_TEST_PATTERN_COLOR_SQUARES:
2360 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2361 case DP_TEST_PATTERN_VERTICAL_BARS:
2362 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2363 case DP_TEST_PATTERN_COLOR_RAMP:
2364 {
2365 /* disable bit depth reduction */
2366 pipe_ctx->stream->bit_depth_params = params;
a6a6cb34
HW		 2367 pipe_ctx->stream_res.opp->funcs->
2368 opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
4562236b 2369
6b670fa9 2370 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 2371 controller_test_pattern, color_depth);
2372 }
2373 break;
2374 case DP_TEST_PATTERN_VIDEO_MODE:
2375 {
2376 /* restore bitdepth reduction */
529cad0f 2377 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
4562236b
HW		 2378 &params);
2379 pipe_ctx->stream->bit_depth_params = params;
a6a6cb34
HW		 2380 pipe_ctx->stream_res.opp->funcs->
2381 opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
4562236b 2382
6b670fa9 2383 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 2384 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2385 color_depth);
2386 }
2387 break;
2388
2389 default:
2390 break;
2391 }
2392}
2393
2394bool dc_link_dp_set_test_pattern(
d0778ebf 2395 struct dc_link *link,
4562236b
HW		 2396 enum dp_test_pattern test_pattern,
2397 const struct link_training_settings *p_link_settings,
2398 const unsigned char *p_custom_pattern,
2399 unsigned int cust_pattern_size)
2400{
d0778ebf 2401 struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx;
0a8f43ff 2402 struct pipe_ctx *pipe_ctx = &pipes[0];
4562236b
HW		 2403 unsigned int lane;
2404 unsigned int i;
2405 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
2406 union dpcd_training_pattern training_pattern;
4562236b
HW		 2407 enum dpcd_phy_test_patterns pattern;
2408
2409 memset(&training_pattern, 0, sizeof(training_pattern));
4562236b
HW		 2410
2411 for (i = 0; i < MAX_PIPES; i++) {
d0778ebf 2412 if (pipes[i].stream->sink->link == link) {
0a8f43ff 2413 pipe_ctx = &pipes[i];
4562236b
HW		 2414 break;
2415 }
2416 }
2417
2418 /* Reset CRTC Test Pattern if it is currently running and request
2419 * is VideoMode Reset DP Phy Test Pattern if it is currently running
2420 * and request is VideoMode
2421 */
d0778ebf 2422 if (link->test_pattern_enabled && test_pattern ==
4562236b
HW		 2423 DP_TEST_PATTERN_VIDEO_MODE) {
2424 /* Set CRTC Test Pattern */
0a8f43ff 2425 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
d0778ebf 2426 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 2427 (uint8_t *)p_custom_pattern,
2428 (uint32_t)cust_pattern_size);
2429
2430 /* Unblank Stream */
d0778ebf 2431 link->dc->hwss.unblank_stream(
0a8f43ff 2432 pipe_ctx,
d0778ebf 2433 &link->verified_link_cap);
4562236b
HW		 2434 /* TODO:m_pHwss->MuteAudioEndpoint
2435 * (pPathMode->pDisplayPath, false);
2436 */
2437
2438 /* Reset Test Pattern state */
d0778ebf 2439 link->test_pattern_enabled = false;
4562236b
HW		 2440
2441 return true;
2442 }
2443
2444 /* Check for PHY Test Patterns */
2445 if (is_dp_phy_pattern(test_pattern)) {
2446 /* Set DPCD Lane Settings before running test pattern */
2447 if (p_link_settings != NULL) {
d0778ebf
HW		 2448 dp_set_hw_lane_settings(link, p_link_settings);
2449 dpcd_set_lane_settings(link, p_link_settings);
4562236b
HW		 2450 }
2451
2452 /* Blank stream if running test pattern */
2453 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2454 /*TODO:
2455 * m_pHwss->
2456 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
2457 */
2458 /* Blank stream */
8e9c4c8c 2459 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4562236b
HW		 2460 }
2461
d0778ebf 2462 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 2463 (uint8_t *)p_custom_pattern,
2464 (uint32_t)cust_pattern_size);
2465
2466 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2467 /* Set Test Pattern state */
d0778ebf 2468 link->test_pattern_enabled = true;
4562236b 2469 if (p_link_settings != NULL)
d0778ebf 2470 dpcd_set_link_settings(link,
4562236b
HW		 2471 p_link_settings);
2472 }
2473
2474 switch (test_pattern) {
2475 case DP_TEST_PATTERN_VIDEO_MODE:
2476 pattern = PHY_TEST_PATTERN_NONE;
0e19401f 2477 break;
4562236b
HW		 2478 case DP_TEST_PATTERN_D102:
2479 pattern = PHY_TEST_PATTERN_D10_2;
0e19401f 2480 break;
4562236b
HW		 2481 case DP_TEST_PATTERN_SYMBOL_ERROR:
2482 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 2483 break;
4562236b
HW		 2484 case DP_TEST_PATTERN_PRBS7:
2485 pattern = PHY_TEST_PATTERN_PRBS7;
0e19401f 2486 break;
4562236b
HW		 2487 case DP_TEST_PATTERN_80BIT_CUSTOM:
2488 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 2489 break;
2490 case DP_TEST_PATTERN_CP2520_1:
2491 pattern = PHY_TEST_PATTERN_CP2520_1;
2492 break;
2493 case DP_TEST_PATTERN_CP2520_2:
2494 pattern = PHY_TEST_PATTERN_CP2520_2;
2495 break;
2496 case DP_TEST_PATTERN_CP2520_3:
2497 pattern = PHY_TEST_PATTERN_CP2520_3;
2498 break;
4562236b
HW		 2499 default:
2500 return false;
2501 }
2502
2503 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
2504 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
2505 return false;
2506
d0778ebf 2507 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 2508 /* tell receiver that we are sending qualification
2509 * pattern DP 1.2 or later - DP receiver's link quality
2510 * pattern is set using DPCD LINK_QUAL_LANEx_SET
2511 * register (0x10B~0x10E)\
2512 */
2513 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
2514 link_qual_pattern[lane] =
2515 (unsigned char)(pattern);
2516
d0778ebf 2517 core_link_write_dpcd(link,
3a340294 2518 DP_LINK_QUAL_LANE0_SET,
4562236b
HW		 2519 link_qual_pattern,
2520 sizeof(link_qual_pattern));
d0778ebf
HW		 2521 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
2522 link->dpcd_caps.dpcd_rev.raw == 0) {
4562236b
HW		 2523 /* tell receiver that we are sending qualification
2524 * pattern DP 1.1a or earlier - DP receiver's link
2525 * quality pattern is set using
2526 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
2527 * register (0x102). We will use v_1.3 when we are
2528 * setting test pattern for DP 1.1.
2529 */
d0778ebf
HW		 2530 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
2531 &training_pattern.raw,
2532 sizeof(training_pattern));
4562236b 2533 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
d0778ebf
HW		 2534 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
2535 &training_pattern.raw,
2536 sizeof(training_pattern));
4562236b
HW		 2537 }
2538 } else {
2539 /* CRTC Patterns */
0a8f43ff 2540 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
4562236b 2541 /* Set Test Pattern state */
d0778ebf 2542 link->test_pattern_enabled = true;
4562236b
HW		 2543 }
2544
2545 return true;
2546}
07c84c7a 2547
d0778ebf 2548void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
07c84c7a
DW		 2549{
2550 unsigned char mstmCntl;
2551
2552 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2553 if (enable)
2554 mstmCntl |= DP_MST_EN;
2555 else
2556 mstmCntl &= (~DP_MST_EN);
2557
2558 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2559}
Linux 6.x block layer and io_uring tree(s)