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drm/amd/display: Check for null fclk voltage when parsing clock table
[linux-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
CommitLineData
4562236b
HW		 1/* Copyright 2015 Advanced Micro Devices, Inc. */
2#include "dm_services.h"
3#include "dc.h"
4#include "dc_link_dp.h"
5#include "dm_helpers.h"
7f93c1de 6#include "opp.h"
97bda032 7#include "dsc.h"
6fbefb84 8#include "resource.h"
4562236b
HW		 9
10#include "inc/core_types.h"
11#include "link_hwss.h"
12#include "dc_link_ddc.h"
13#include "core_status.h"
14#include "dpcd_defs.h"
15
529cad0f 16#include "resource.h"
1296423b
BL		 17#define DC_LOGGER \
18 link->ctx->logger
4562236b 19
8e5100a5 20
64c12b73 21#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
8e5100a5 22
4562236b
HW		 23/* maximum pre emphasis level allowed for each voltage swing level*/
24static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
25 PRE_EMPHASIS_LEVEL3,
26 PRE_EMPHASIS_LEVEL2,
27 PRE_EMPHASIS_LEVEL1,
28 PRE_EMPHASIS_DISABLED };
29
30enum {
31 POST_LT_ADJ_REQ_LIMIT = 6,
32 POST_LT_ADJ_REQ_TIMEOUT = 200
33};
34
35enum {
36 LINK_TRAINING_MAX_RETRY_COUNT = 5,
37 /* to avoid infinite loop where-in the receiver
38 * switches between different VS
39 */
40 LINK_TRAINING_MAX_CR_RETRY = 100
41};
42
04e21292
DA		 43static bool decide_fallback_link_setting(
44 struct dc_link_settings initial_link_settings,
45 struct dc_link_settings *current_link_setting,
46 enum link_training_result training_result);
9a6a8075 47static struct dc_link_settings get_common_supported_link_settings(
04e21292
DA		 48 struct dc_link_settings link_setting_a,
49 struct dc_link_settings link_setting_b);
50
e0a6440a 51static uint32_t get_training_aux_rd_interval(
d0778ebf 52 struct dc_link *link,
4562236b
HW		 53 uint32_t default_wait_in_micro_secs)
54{
d6d36b55
NC		 55 union training_aux_rd_interval training_rd_interval;
56
57 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
4562236b
HW		 58
59 /* overwrite the delay if rev > 1.1*/
60 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
61 /* DP 1.2 or later - retrieve delay through
62 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
63 core_link_read_dpcd(
64 link,
3a340294 65 DP_TRAINING_AUX_RD_INTERVAL,
4562236b
HW		 66 (uint8_t *)&training_rd_interval,
67 sizeof(training_rd_interval));
68
69 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
e0a6440a 70 default_wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
4562236b
HW		 71 }
72
e0a6440a
DG		 73 return default_wait_in_micro_secs;
74}
75
76static void wait_for_training_aux_rd_interval(
77 struct dc_link *link,
78 uint32_t wait_in_micro_secs)
79{
80 udelay(wait_in_micro_secs);
4562236b 81
1296423b 82 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
4562236b 83 __func__,
e0a6440a 84 wait_in_micro_secs);
4562236b
HW		 85}
86
87static void dpcd_set_training_pattern(
d0778ebf 88 struct dc_link *link,
4562236b
HW		 89 union dpcd_training_pattern dpcd_pattern)
90{
91 core_link_write_dpcd(
92 link,
3a340294 93 DP_TRAINING_PATTERN_SET,
4562236b
HW		 94 &dpcd_pattern.raw,
95 1);
96
1296423b 97 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
4562236b 98 __func__,
3a340294 99 DP_TRAINING_PATTERN_SET,
4562236b
HW		 100 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
101}
102
e0a6440a 103static enum dc_dp_training_pattern get_supported_tp(struct dc_link *link)
16b6253a 104{
e0a6440a 105 enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
16b6253a 106 struct encoder_feature_support *features = &link->link_enc->features;
107 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
108
109 if (features->flags.bits.IS_TPS3_CAPABLE)
e0a6440a 110 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
16b6253a 111
112 if (features->flags.bits.IS_TPS4_CAPABLE)
e0a6440a 113 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
16b6253a 114
115 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
e0a6440a
DG		 116 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
117 return DP_TRAINING_PATTERN_SEQUENCE_4;
16b6253a 118
119 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
e0a6440a
DG		 120 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
121 return DP_TRAINING_PATTERN_SEQUENCE_3;
16b6253a 122
e0a6440a 123 return DP_TRAINING_PATTERN_SEQUENCE_2;
16b6253a 124}
125
4562236b 126static void dpcd_set_link_settings(
d0778ebf 127 struct dc_link *link,
4562236b
HW		 128 const struct link_training_settings *lt_settings)
129{
8628d02f 130 uint8_t rate;
4562236b 131
9a6a8075
HW		 132 union down_spread_ctrl downspread = { {0} };
133 union lane_count_set lane_count_set = { {0} };
e0a6440a 134 enum dc_dp_training_pattern dp_tr_pattern;
4562236b
HW		 135
136 downspread.raw = (uint8_t)
137 (lt_settings->link_settings.link_spread);
138
139 lane_count_set.bits.LANE_COUNT_SET =
140 lt_settings->link_settings.lane_count;
141
e0a6440a 142 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
16b6253a 143 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
144
e0a6440a
DG		 145 dp_tr_pattern = get_supported_tp(link);
146
147 if (dp_tr_pattern != DP_TRAINING_PATTERN_SEQUENCE_4) {
16b6253a 148 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
149 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
150 }
4562236b 151
3a340294 152 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
e0a6440a 153 &downspread.raw, sizeof(downspread));
4562236b 154
8628d02f 155 core_link_write_dpcd(link, DP_LANE_COUNT_SET,
e0a6440a 156 &lane_count_set.raw, 1);
8628d02f 157
b03a599b 158 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
8628d02f
JP		 159 lt_settings->link_settings.use_link_rate_set == true) {
160 rate = 0;
161 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
b03a599b 162 core_link_write_dpcd(link, DP_LINK_RATE_SET,
8628d02f
JP		 163 &lt_settings->link_settings.link_rate_set, 1);
164 } else {
165 rate = (uint8_t) (lt_settings->link_settings.link_rate);
166 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
b03a599b
DL		 167 }
168
8628d02f 169 if (rate) {
e0a6440a 170 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
8628d02f
JP		 171 __func__,
172 DP_LINK_BW_SET,
173 lt_settings->link_settings.link_rate,
174 DP_LANE_COUNT_SET,
175 lt_settings->link_settings.lane_count,
e0a6440a 176 lt_settings->enhanced_framing,
8628d02f
JP		 177 DP_DOWNSPREAD_CTRL,
178 lt_settings->link_settings.link_spread);
179 } else {
e0a6440a 180 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
8628d02f
JP		 181 __func__,
182 DP_LINK_RATE_SET,
183 lt_settings->link_settings.link_rate_set,
184 DP_LANE_COUNT_SET,
185 lt_settings->link_settings.lane_count,
e0a6440a 186 lt_settings->enhanced_framing,
8628d02f
JP		 187 DP_DOWNSPREAD_CTRL,
188 lt_settings->link_settings.link_spread);
189 }
4562236b
HW		 190}
191
192static enum dpcd_training_patterns
e0a6440a 193 dc_dp_training_pattern_to_dpcd_training_pattern(
d0778ebf 194 struct dc_link *link,
e0a6440a 195 enum dc_dp_training_pattern pattern)
4562236b
HW		 196{
197 enum dpcd_training_patterns dpcd_tr_pattern =
198 DPCD_TRAINING_PATTERN_VIDEOIDLE;
199
200 switch (pattern) {
e0a6440a 201 case DP_TRAINING_PATTERN_SEQUENCE_1:
4562236b
HW		 202 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
203 break;
e0a6440a 204 case DP_TRAINING_PATTERN_SEQUENCE_2:
4562236b
HW		 205 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
206 break;
e0a6440a 207 case DP_TRAINING_PATTERN_SEQUENCE_3:
4562236b
HW		 208 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
209 break;
e0a6440a 210 case DP_TRAINING_PATTERN_SEQUENCE_4:
4562236b
HW		 211 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
212 break;
213 default:
214 ASSERT(0);
1296423b 215 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
4562236b
HW		 216 __func__, pattern);
217 break;
218 }
219
220 return dpcd_tr_pattern;
4562236b
HW		 221}
222
64c12b73 223static inline bool is_repeater(struct dc_link *link, uint32_t offset)
224{
225 return (!link->is_lttpr_mode_transparent && offset != 0);
226}
227
4562236b 228static void dpcd_set_lt_pattern_and_lane_settings(
d0778ebf 229 struct dc_link *link,
4562236b 230 const struct link_training_settings *lt_settings,
64c12b73 231 enum dc_dp_training_pattern pattern,
232 uint32_t offset)
4562236b 233{
9a6a8075 234 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
64c12b73 235
236 uint32_t dpcd_base_lt_offset;
237
4562236b 238 uint8_t dpcd_lt_buffer[5] = {0};
9a6a8075 239 union dpcd_training_pattern dpcd_pattern = { {0} };
4562236b
HW		 240 uint32_t lane;
241 uint32_t size_in_bytes;
242 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
64c12b73 243 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
244
245 if (is_repeater(link, offset))
246 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
247 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b
HW		 248
249 /*****************************************************************
250 * DpcdAddress_TrainingPatternSet
251 *****************************************************************/
252 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
e0a6440a 253 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
4562236b 254
64c12b73 255 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
4562236b
HW		 256 = dpcd_pattern.raw;
257
460adc6b 258 if (is_repeater(link, offset)) {
259 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
260 __func__,
261 offset,
262 dpcd_base_lt_offset,
263 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
264 } else {
265 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
266 __func__,
267 dpcd_base_lt_offset,
268 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
269 }
4562236b
HW		 270 /*****************************************************************
271 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
272 *****************************************************************/
273 for (lane = 0; lane <
274 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
275
276 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
277 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
278 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
279 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
280
281 dpcd_lane[lane].bits.MAX_SWING_REACHED =
282 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
283 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
284 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
285 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
286 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
287 }
288
64c12b73 289 /* concatenate everything into one buffer*/
4562236b
HW		 290
291 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
292
293 // 0x00103 - 0x00102
294 memmove(
64c12b73 295 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
4562236b
HW		 296 dpcd_lane,
297 size_in_bytes);
298
460adc6b 299 if (is_repeater(link, offset)) {
300 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
301 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
302 __func__,
303 offset,
304 dpcd_base_lt_offset,
305 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
306 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
307 dpcd_lane[0].bits.MAX_SWING_REACHED,
308 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
309 } else {
310 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
311 __func__,
312 dpcd_base_lt_offset,
313 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
314 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
315 dpcd_lane[0].bits.MAX_SWING_REACHED,
316 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
317 }
4562236b
HW		 318 if (edp_workaround) {
319 /* for eDP write in 2 parts because the 5-byte burst is
320 * causing issues on some eDP panels (EPR#366724)
321 */
322 core_link_write_dpcd(
323 link,
3a340294 324 DP_TRAINING_PATTERN_SET,
4562236b 325 &dpcd_pattern.raw,
9a6a8075 326 sizeof(dpcd_pattern.raw));
4562236b
HW		 327
328 core_link_write_dpcd(
329 link,
3a340294 330 DP_TRAINING_LANE0_SET,
4562236b
HW		 331 (uint8_t *)(dpcd_lane),
332 size_in_bytes);
333
334 } else
335 /* write it all in (1 + number-of-lanes)-byte burst*/
336 core_link_write_dpcd(
337 link,
338 dpcd_base_lt_offset,
339 dpcd_lt_buffer,
9a6a8075 340 size_in_bytes + sizeof(dpcd_pattern.raw));
4562236b 341
d0778ebf 342 link->cur_lane_setting = lt_settings->lane_settings[0];
4562236b
HW		 343}
344
345static bool is_cr_done(enum dc_lane_count ln_count,
346 union lane_status *dpcd_lane_status)
347{
348 bool done = true;
349 uint32_t lane;
350 /*LANEx_CR_DONE bits All 1's?*/
351 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
352 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
353 done = false;
354 }
355 return done;
356
357}
358
359static bool is_ch_eq_done(enum dc_lane_count ln_count,
360 union lane_status *dpcd_lane_status,
361 union lane_align_status_updated *lane_status_updated)
362{
363 bool done = true;
364 uint32_t lane;
365 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
366 done = false;
367 else {
368 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
369 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
370 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
371 done = false;
372 }
373 }
374 return done;
375
376}
377
378static void update_drive_settings(
379 struct link_training_settings *dest,
380 struct link_training_settings src)
381{
382 uint32_t lane;
383 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
e0a6440a
DG		 384 if (dest->voltage_swing == NULL)
385 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
386 else
387 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
388
389 if (dest->pre_emphasis == NULL)
390 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
391 else
392 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
393
394 if (dest->post_cursor2 == NULL)
395 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
396 else
397 dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
4562236b
HW		 398 }
399}
400
401static uint8_t get_nibble_at_index(const uint8_t *buf,
402 uint32_t index)
403{
404 uint8_t nibble;
405 nibble = buf[index / 2];
406
407 if (index % 2)
408 nibble >>= 4;
409 else
410 nibble &= 0x0F;
411
412 return nibble;
413}
414
415static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
416 enum dc_voltage_swing voltage)
417{
418 enum dc_pre_emphasis pre_emphasis;
419 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
420
421 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
422 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
423
424 return pre_emphasis;
425
426}
427
428static void find_max_drive_settings(
429 const struct link_training_settings *link_training_setting,
430 struct link_training_settings *max_lt_setting)
431{
432 uint32_t lane;
433 struct dc_lane_settings max_requested;
434
435 max_requested.VOLTAGE_SWING =
436 link_training_setting->
437 lane_settings[0].VOLTAGE_SWING;
438 max_requested.PRE_EMPHASIS =
439 link_training_setting->
440 lane_settings[0].PRE_EMPHASIS;
441 /*max_requested.postCursor2 =
442 * link_training_setting->laneSettings[0].postCursor2;*/
443
444 /* Determine what the maximum of the requested settings are*/
445 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
446 lane++) {
447 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
448 max_requested.VOLTAGE_SWING)
449
450 max_requested.VOLTAGE_SWING =
451 link_training_setting->
452 lane_settings[lane].VOLTAGE_SWING;
453
454 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
455 max_requested.PRE_EMPHASIS)
456 max_requested.PRE_EMPHASIS =
457 link_training_setting->
458 lane_settings[lane].PRE_EMPHASIS;
459
460 /*
461 if (link_training_setting->laneSettings[lane].postCursor2 >
462 max_requested.postCursor2)
463 {
464 max_requested.postCursor2 =
465 link_training_setting->laneSettings[lane].postCursor2;
466 }
467 */
468 }
469
470 /* make sure the requested settings are
471 * not higher than maximum settings*/
472 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
473 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
474
475 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
476 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
477 /*
478 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
479 max_requested.postCursor2 = PostCursor2_MaxLevel;
480 */
481
482 /* make sure the pre-emphasis matches the voltage swing*/
483 if (max_requested.PRE_EMPHASIS >
484 get_max_pre_emphasis_for_voltage_swing(
485 max_requested.VOLTAGE_SWING))
486 max_requested.PRE_EMPHASIS =
487 get_max_pre_emphasis_for_voltage_swing(
488 max_requested.VOLTAGE_SWING);
489
490 /*
491 * Post Cursor2 levels are completely independent from
492 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
493 * can only be applied to each allowable combination of voltage
494 * swing and pre-emphasis levels */
495 /* if ( max_requested.postCursor2 >
496 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
497 * max_requested.postCursor2 =
498 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
499 */
500
501 max_lt_setting->link_settings.link_rate =
502 link_training_setting->link_settings.link_rate;
503 max_lt_setting->link_settings.lane_count =
504 link_training_setting->link_settings.lane_count;
505 max_lt_setting->link_settings.link_spread =
506 link_training_setting->link_settings.link_spread;
507
508 for (lane = 0; lane <
509 link_training_setting->link_settings.lane_count;
510 lane++) {
511 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
512 max_requested.VOLTAGE_SWING;
513 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
514 max_requested.PRE_EMPHASIS;
515 /*max_lt_setting->laneSettings[lane].postCursor2 =
516 * max_requested.postCursor2;
517 */
518 }
519
520}
521
522static void get_lane_status_and_drive_settings(
d0778ebf 523 struct dc_link *link,
4562236b
HW		 524 const struct link_training_settings *link_training_setting,
525 union lane_status *ln_status,
526 union lane_align_status_updated *ln_status_updated,
64c12b73 527 struct link_training_settings *req_settings,
528 uint32_t offset)
4562236b 529{
64c12b73 530 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
531 uint8_t lane_adjust_offset = 4;
532 unsigned int lane01_adjust_address;
4562236b 533 uint8_t dpcd_buf[6] = {0};
9a6a8075
HW		 534 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
535 struct link_training_settings request_settings = { {0} };
4562236b
HW		 536 uint32_t lane;
537
538 memset(req_settings, '\0', sizeof(struct link_training_settings));
539
64c12b73 540 if (is_repeater(link, offset)) {
541 lane01_status_address =
542 DP_LANE0_1_STATUS_PHY_REPEATER1 +
543 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
544 lane_adjust_offset = 3;
545 }
546
4562236b
HW		 547 core_link_read_dpcd(
548 link,
64c12b73 549 lane01_status_address,
4562236b
HW		 550 (uint8_t *)(dpcd_buf),
551 sizeof(dpcd_buf));
552
553 for (lane = 0; lane <
554 (uint32_t)(link_training_setting->link_settings.lane_count);
555 lane++) {
556
557 ln_status[lane].raw =
558 get_nibble_at_index(&dpcd_buf[0], lane);
559 dpcd_lane_adjust[lane].raw =
64c12b73 560 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
4562236b
HW		 561 }
562
563 ln_status_updated->raw = dpcd_buf[2];
564
460adc6b 565 if (is_repeater(link, offset)) {
566 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
567 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
568 __func__,
569 offset,
570 lane01_status_address, dpcd_buf[0],
571 lane01_status_address + 1, dpcd_buf[1]);
572 } else {
573 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
574 __func__,
575 lane01_status_address, dpcd_buf[0],
576 lane01_status_address + 1, dpcd_buf[1]);
577 }
64c12b73 578 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
579
580 if (is_repeater(link, offset))
581 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
582 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b 583
460adc6b 584 if (is_repeater(link, offset)) {
585 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
586 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
587 __func__,
588 offset,
589 lane01_adjust_address,
590 dpcd_buf[lane_adjust_offset],
591 lane01_adjust_address + 1,
592 dpcd_buf[lane_adjust_offset + 1]);
593 } else {
594 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
595 __func__,
596 lane01_adjust_address,
597 dpcd_buf[lane_adjust_offset],
598 lane01_adjust_address + 1,
599 dpcd_buf[lane_adjust_offset + 1]);
600 }
4562236b
HW		 601
602 /*copy to req_settings*/
603 request_settings.link_settings.lane_count =
604 link_training_setting->link_settings.lane_count;
605 request_settings.link_settings.link_rate =
606 link_training_setting->link_settings.link_rate;
607 request_settings.link_settings.link_spread =
608 link_training_setting->link_settings.link_spread;
609
610 for (lane = 0; lane <
611 (uint32_t)(link_training_setting->link_settings.lane_count);
612 lane++) {
613
614 request_settings.lane_settings[lane].VOLTAGE_SWING =
615 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
616 VOLTAGE_SWING_LANE);
617 request_settings.lane_settings[lane].PRE_EMPHASIS =
618 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
619 PRE_EMPHASIS_LANE);
620 }
621
622 /*Note: for postcursor2, read adjusted
623 * postcursor2 settings from*/
624 /*DpcdAddress_AdjustRequestPostCursor2 =
625 *0x020C (not implemented yet)*/
626
627 /* we find the maximum of the requested settings across all lanes*/
628 /* and set this maximum for all lanes*/
629 find_max_drive_settings(&request_settings, req_settings);
630
631 /* if post cursor 2 is needed in the future,
632 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
633 */
634
635}
636
637static void dpcd_set_lane_settings(
d0778ebf 638 struct dc_link *link,
64c12b73 639 const struct link_training_settings *link_training_setting,
640 uint32_t offset)
4562236b
HW		 641{
642 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
643 uint32_t lane;
64c12b73 644 unsigned int lane0_set_address;
645
646 lane0_set_address = DP_TRAINING_LANE0_SET;
647
648 if (is_repeater(link, offset))
649 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
650 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
4562236b
HW		 651
652 for (lane = 0; lane <
653 (uint32_t)(link_training_setting->
654 link_settings.lane_count);
655 lane++) {
656 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
657 (uint8_t)(link_training_setting->
658 lane_settings[lane].VOLTAGE_SWING);
659 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
660 (uint8_t)(link_training_setting->
661 lane_settings[lane].PRE_EMPHASIS);
662 dpcd_lane[lane].bits.MAX_SWING_REACHED =
663 (link_training_setting->
664 lane_settings[lane].VOLTAGE_SWING ==
665 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
666 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
667 (link_training_setting->
668 lane_settings[lane].PRE_EMPHASIS ==
669 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
670 }
671
672 core_link_write_dpcd(link,
64c12b73 673 lane0_set_address,
4562236b
HW		 674 (uint8_t *)(dpcd_lane),
675 link_training_setting->link_settings.lane_count);
676
677 /*
678 if (LTSettings.link.rate == LinkRate_High2)
679 {
680 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
681 for ( uint32_t lane = 0;
682 lane < lane_count_DPMax; lane++)
683 {
684 dpcd_lane2[lane].bits.post_cursor2_set =
685 static_cast<unsigned char>(
686 LTSettings.laneSettings[lane].postCursor2);
687 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
688 }
689 m_pDpcdAccessSrv->WriteDpcdData(
690 DpcdAddress_Lane0Set2,
691 reinterpret_cast<unsigned char*>(dpcd_lane2),
692 LTSettings.link.lanes);
693 }
694 */
695
460adc6b 696 if (is_repeater(link, offset)) {
697 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
698 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
699 __func__,
700 offset,
701 lane0_set_address,
702 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
703 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
704 dpcd_lane[0].bits.MAX_SWING_REACHED,
705 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
4562236b 706
460adc6b 707 } else {
708 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
709 __func__,
710 lane0_set_address,
711 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
712 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
713 dpcd_lane[0].bits.MAX_SWING_REACHED,
714 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
715 }
d0778ebf 716 link->cur_lane_setting = link_training_setting->lane_settings[0];
4562236b
HW		 717
718}
719
720static bool is_max_vs_reached(
721 const struct link_training_settings *lt_settings)
722{
723 uint32_t lane;
724 for (lane = 0; lane <
725 (uint32_t)(lt_settings->link_settings.lane_count);
726 lane++) {
727 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
728 == VOLTAGE_SWING_MAX_LEVEL)
729 return true;
730 }
731 return false;
732
733}
734
4562236b 735static bool perform_post_lt_adj_req_sequence(
d0778ebf 736 struct dc_link *link,
4562236b
HW		 737 struct link_training_settings *lt_settings)
738{
739 enum dc_lane_count lane_count =
740 lt_settings->link_settings.lane_count;
741
742 uint32_t adj_req_count;
743 uint32_t adj_req_timer;
744 bool req_drv_setting_changed;
745 uint32_t lane;
746
747 req_drv_setting_changed = false;
748 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
749 adj_req_count++) {
750
751 req_drv_setting_changed = false;
752
753 for (adj_req_timer = 0;
754 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
755 adj_req_timer++) {
756
757 struct link_training_settings req_settings;
758 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
759 union lane_align_status_updated
760 dpcd_lane_status_updated;
761
762 get_lane_status_and_drive_settings(
763 link,
764 lt_settings,
765 dpcd_lane_status,
766 &dpcd_lane_status_updated,
64c12b73 767 &req_settings,
768 DPRX);
4562236b
HW		 769
770 if (dpcd_lane_status_updated.bits.
771 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
772 return true;
773
774 if (!is_cr_done(lane_count, dpcd_lane_status))
775 return false;
776
777 if (!is_ch_eq_done(
778 lane_count,
779 dpcd_lane_status,
780 &dpcd_lane_status_updated))
781 return false;
782
783 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
784
785 if (lt_settings->
786 lane_settings[lane].VOLTAGE_SWING !=
787 req_settings.lane_settings[lane].
788 VOLTAGE_SWING ||
789 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
790 req_settings.lane_settings[lane].PRE_EMPHASIS) {
791
792 req_drv_setting_changed = true;
793 break;
794 }
795 }
796
797 if (req_drv_setting_changed) {
798 update_drive_settings(
9a6a8075 799 lt_settings, req_settings);
4562236b 800
d0778ebf 801 dc_link_dp_set_drive_settings(link,
4562236b
HW		 802 lt_settings);
803 break;
804 }
805
806 msleep(1);
807 }
808
809 if (!req_drv_setting_changed) {
1296423b 810 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
4562236b
HW		 811 __func__);
812
813 ASSERT(0);
814 return true;
815 }
816 }
1296423b 817 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
4562236b
HW		 818 __func__);
819
820 ASSERT(0);
821 return true;
822
823}
824
64c12b73 825/* Only used for channel equalization */
826static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
827{
828 unsigned int aux_rd_interval_us = 400;
829
830 switch (dpcd_aux_read_interval) {
831 case 0x01:
832 aux_rd_interval_us = 400;
833 break;
834 case 0x02:
835 aux_rd_interval_us = 4000;
836 break;
837 case 0x03:
838 aux_rd_interval_us = 8000;
839 break;
840 case 0x04:
841 aux_rd_interval_us = 16000;
842 break;
843 default:
844 break;
845 }
846
847 return aux_rd_interval_us;
848}
849
94405cf6
WL		 850static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
851 union lane_status *dpcd_lane_status)
852{
853 enum link_training_result result = LINK_TRAINING_SUCCESS;
854
855 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
856 result = LINK_TRAINING_CR_FAIL_LANE0;
857 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
858 result = LINK_TRAINING_CR_FAIL_LANE1;
859 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
860 result = LINK_TRAINING_CR_FAIL_LANE23;
861 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
862 result = LINK_TRAINING_CR_FAIL_LANE23;
863 return result;
864}
865
820e3935 866static enum link_training_result perform_channel_equalization_sequence(
d0778ebf 867 struct dc_link *link,
64c12b73 868 struct link_training_settings *lt_settings,
869 uint32_t offset)
4562236b
HW		 870{
871 struct link_training_settings req_settings;
e0a6440a 872 enum dc_dp_training_pattern tr_pattern;
4562236b 873 uint32_t retries_ch_eq;
64c12b73 874 uint32_t wait_time_microsec;
4562236b 875 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
9a6a8075
HW		 876 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
877 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
4562236b 878
64c12b73 879 /* Note: also check that TPS4 is a supported feature*/
880
e0a6440a 881 tr_pattern = lt_settings->pattern_for_eq;
4562236b 882
64c12b73 883 if (is_repeater(link, offset))
884 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
885
886 dp_set_hw_training_pattern(link, tr_pattern, offset);
4562236b
HW		 887
888 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
889 retries_ch_eq++) {
890
64c12b73 891 dp_set_hw_lane_settings(link, lt_settings, offset);
4562236b
HW		 892
893 /* 2. update DPCD*/
894 if (!retries_ch_eq)
895 /* EPR #361076 - write as a 5-byte burst,
64c12b73 896 * but only for the 1-st iteration
897 */
898
4562236b
HW		 899 dpcd_set_lt_pattern_and_lane_settings(
900 link,
901 lt_settings,
64c12b73 902 tr_pattern, offset);
4562236b 903 else
64c12b73 904 dpcd_set_lane_settings(link, lt_settings, offset);
4562236b
HW		 905
906 /* 3. wait for receiver to lock-on*/
64c12b73 907 wait_time_microsec = lt_settings->eq_pattern_time;
908
5fd21b39 909 if (is_repeater(link, offset))
64c12b73 910 wait_time_microsec =
911 translate_training_aux_read_interval(
5fd21b39 912 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
64c12b73 913
914 wait_for_training_aux_rd_interval(
915 link,
916 wait_time_microsec);
4562236b
HW		 917
918 /* 4. Read lane status and requested
919 * drive settings as set by the sink*/
920
921 get_lane_status_and_drive_settings(
922 link,
923 lt_settings,
924 dpcd_lane_status,
925 &dpcd_lane_status_updated,
64c12b73 926 &req_settings,
927 offset);
4562236b
HW		 928
929 /* 5. check CR done*/
930 if (!is_cr_done(lane_count, dpcd_lane_status))
820e3935 931 return LINK_TRAINING_EQ_FAIL_CR;
4562236b
HW		 932
933 /* 6. check CHEQ done*/
934 if (is_ch_eq_done(lane_count,
935 dpcd_lane_status,
936 &dpcd_lane_status_updated))
820e3935 937 return LINK_TRAINING_SUCCESS;
4562236b
HW		 938
939 /* 7. update VS/PE/PC2 in lt_settings*/
940 update_drive_settings(lt_settings, req_settings);
941 }
942
820e3935 943 return LINK_TRAINING_EQ_FAIL_EQ;
4562236b
HW		 944
945}
64c12b73 946#define TRAINING_AUX_RD_INTERVAL 100 //us
4562236b 947
b01f22ec
DG		 948static void start_clock_recovery_pattern_early(struct dc_link *link,
949 struct link_training_settings *lt_settings,
950 uint32_t offset)
951{
952 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
953 __func__);
954 dp_set_hw_training_pattern(link, DP_TRAINING_PATTERN_SEQUENCE_1, offset);
955 dp_set_hw_lane_settings(link, lt_settings, offset);
956 udelay(400);
957}
958
94405cf6 959static enum link_training_result perform_clock_recovery_sequence(
d0778ebf 960 struct dc_link *link,
64c12b73 961 struct link_training_settings *lt_settings,
962 uint32_t offset)
4562236b
HW		 963{
964 uint32_t retries_cr;
965 uint32_t retry_count;
64c12b73 966 uint32_t wait_time_microsec;
4562236b 967 struct link_training_settings req_settings;
e0a6440a
DG		 968 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
969 enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
4562236b
HW		 970 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
971 union lane_align_status_updated dpcd_lane_status_updated;
972
973 retries_cr = 0;
974 retry_count = 0;
4562236b 975
82054678 976 if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
b01f22ec 977 dp_set_hw_training_pattern(link, tr_pattern, offset);
4562236b
HW		 978
979 /* najeeb - The synaptics MST hub can put the LT in
980 * infinite loop by switching the VS
981 */
982 /* between level 0 and level 1 continuously, here
983 * we try for CR lock for LinkTrainingMaxCRRetry count*/
984 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
e0a6440a 985 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
4562236b
HW		 986
987 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
988 memset(&dpcd_lane_status_updated, '\0',
989 sizeof(dpcd_lane_status_updated));
990
991 /* 1. call HWSS to set lane settings*/
992 dp_set_hw_lane_settings(
993 link,
64c12b73 994 lt_settings,
995 offset);
4562236b
HW		 996
997 /* 2. update DPCD of the receiver*/
50d2c602 998 if (!retry_count)
4562236b
HW		 999 /* EPR #361076 - write as a 5-byte burst,
1000 * but only for the 1-st iteration.*/
1001 dpcd_set_lt_pattern_and_lane_settings(
1002 link,
1003 lt_settings,
64c12b73 1004 tr_pattern,
1005 offset);
4562236b
HW		 1006 else
1007 dpcd_set_lane_settings(
1008 link,
64c12b73 1009 lt_settings,
1010 offset);
4562236b
HW		 1011
1012 /* 3. wait receiver to lock-on*/
64c12b73 1013 wait_time_microsec = lt_settings->cr_pattern_time;
1014
1015 if (!link->is_lttpr_mode_transparent)
1016 wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1017
4562236b
HW		 1018 wait_for_training_aux_rd_interval(
1019 link,
64c12b73 1020 wait_time_microsec);
4562236b
HW		 1021
1022 /* 4. Read lane status and requested drive
1023 * settings as set by the sink
1024 */
1025 get_lane_status_and_drive_settings(
1026 link,
1027 lt_settings,
1028 dpcd_lane_status,
1029 &dpcd_lane_status_updated,
64c12b73 1030 &req_settings,
1031 offset);
4562236b
HW		 1032
1033 /* 5. check CR done*/
1034 if (is_cr_done(lane_count, dpcd_lane_status))
94405cf6 1035 return LINK_TRAINING_SUCCESS;
4562236b
HW		 1036
1037 /* 6. max VS reached*/
1038 if (is_max_vs_reached(lt_settings))
94405cf6 1039 break;
4562236b
HW		 1040
1041 /* 7. same voltage*/
1042 /* Note: VS same for all lanes,
1043 * so comparing first lane is sufficient*/
1044 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
1045 req_settings.lane_settings[0].VOLTAGE_SWING)
1046 retries_cr++;
1047 else
1048 retries_cr = 0;
1049
1050 /* 8. update VS/PE/PC2 in lt_settings*/
1051 update_drive_settings(lt_settings, req_settings);
1052
1053 retry_count++;
1054 }
1055
1056 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1057 ASSERT(0);
1296423b 1058 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
4f42a2dd 1059 __func__,
4562236b
HW		 1060 LINK_TRAINING_MAX_CR_RETRY);
1061
1062 }
1063
94405cf6 1064 return get_cr_failure(lane_count, dpcd_lane_status);
4562236b
HW		 1065}
1066
94405cf6 1067static inline enum link_training_result perform_link_training_int(
d0778ebf 1068 struct dc_link *link,
4562236b 1069 struct link_training_settings *lt_settings,
94405cf6 1070 enum link_training_result status)
4562236b
HW		 1071{
1072 union lane_count_set lane_count_set = { {0} };
1073 union dpcd_training_pattern dpcd_pattern = { {0} };
1074
1075 /* 3. set training not in progress*/
1076 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1077 dpcd_set_training_pattern(link, dpcd_pattern);
1078
1079 /* 4. mainlink output idle pattern*/
1080 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1081
1082 /*
1083 * 5. post training adjust if required
1084 * If the upstream DPTX and downstream DPRX both support TPS4,
1085 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1086 */
c30267f5 1087 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
e0a6440a 1088 get_supported_tp(link) == DP_TRAINING_PATTERN_SEQUENCE_4)
4562236b
HW		 1089 return status;
1090
94405cf6 1091 if (status == LINK_TRAINING_SUCCESS &&
4562236b 1092 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
94405cf6 1093 status = LINK_TRAINING_LQA_FAIL;
4562236b
HW		 1094
1095 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
e0a6440a 1096 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
4562236b
HW		 1097 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1098
1099 core_link_write_dpcd(
1100 link,
3a340294 1101 DP_LANE_COUNT_SET,
4562236b
HW		 1102 &lane_count_set.raw,
1103 sizeof(lane_count_set));
1104
1105 return status;
1106}
1107
e0a6440a
DG		 1108static void initialize_training_settings(
1109 struct dc_link *link,
4562236b 1110 const struct dc_link_settings *link_setting,
0b226322 1111 const struct dc_link_training_overrides *overrides,
e0a6440a 1112 struct link_training_settings *lt_settings)
4562236b 1113{
e0a6440a 1114 uint32_t lane;
4562236b 1115
e0a6440a 1116 memset(lt_settings, '\0', sizeof(struct link_training_settings));
94405cf6 1117
e0a6440a
DG		 1118 /* Initialize link settings */
1119 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1120 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
4562236b 1121
e0a6440a
DG		 1122 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1123 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1124 else
1125 lt_settings->link_settings.link_rate = link_setting->link_rate;
4562236b 1126
e0a6440a
DG		 1127 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1128 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1129 else
1130 lt_settings->link_settings.lane_count = link_setting->lane_count;
4562236b
HW		 1131
1132 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1133
1134 /* TODO hard coded to SS for now
1135 * lt_settings.link_settings.link_spread =
1136 * dal_display_path_is_ss_supported(
1137 * path_mode->display_path) ?
1138 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1139 * LINK_SPREAD_DISABLED;
1140 */
e0a6440a 1141 /* Initialize link spread */
ad830e7a 1142 if (link->dp_ss_off)
e0a6440a 1143 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
0b226322 1144 else if (overrides->downspread != NULL)
e0a6440a 1145 lt_settings->link_settings.link_spread
0b226322 1146 = *overrides->downspread
e0a6440a
DG		 1147 ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1148 : LINK_SPREAD_DISABLED;
ad830e7a 1149 else
e0a6440a 1150 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
4562236b 1151
e0a6440a 1152 /* Initialize lane settings overrides */
0b226322
DG		 1153 if (overrides->voltage_swing != NULL)
1154 lt_settings->voltage_swing = overrides->voltage_swing;
4562236b 1155
0b226322
DG		 1156 if (overrides->pre_emphasis != NULL)
1157 lt_settings->pre_emphasis = overrides->pre_emphasis;
4562236b 1158
0b226322
DG		 1159 if (overrides->post_cursor2 != NULL)
1160 lt_settings->post_cursor2 = overrides->post_cursor2;
e0a6440a
DG		 1161
1162 /* Initialize lane settings (VS/PE/PC2) */
1163 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1164 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1165 lt_settings->voltage_swing != NULL ?
1166 *lt_settings->voltage_swing :
1167 VOLTAGE_SWING_LEVEL0;
1168 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1169 lt_settings->pre_emphasis != NULL ?
1170 *lt_settings->pre_emphasis
1171 : PRE_EMPHASIS_DISABLED;
1172 lt_settings->lane_settings[lane].POST_CURSOR2 =
1173 lt_settings->post_cursor2 != NULL ?
1174 *lt_settings->post_cursor2
1175 : POST_CURSOR2_DISABLED;
820e3935 1176 }
4562236b 1177
e0a6440a 1178 /* Initialize training timings */
0b226322
DG		 1179 if (overrides->cr_pattern_time != NULL)
1180 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
e0a6440a 1181 else
0b226322 1182 lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100);
e0a6440a 1183
0b226322
DG		 1184 if (overrides->eq_pattern_time != NULL)
1185 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
e0a6440a
DG		 1186 else
1187 lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400);
1188
0b226322
DG		 1189 if (overrides->pattern_for_eq != NULL)
1190 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
e0a6440a
DG		 1191 else
1192 lt_settings->pattern_for_eq = get_supported_tp(link);
1193
0b226322
DG		 1194 if (overrides->enhanced_framing != NULL)
1195 lt_settings->enhanced_framing = *overrides->enhanced_framing;
e0a6440a
DG		 1196 else
1197 lt_settings->enhanced_framing = 1;
1198}
1199
64c12b73 1200static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
1201{
1202 switch (lttpr_repeater_count) {
1203 case 0x80: // 1 lttpr repeater
1204 return 1;
1205 case 0x40: // 2 lttpr repeaters
1206 return 2;
1207 case 0x20: // 3 lttpr repeaters
1208 return 3;
1209 case 0x10: // 4 lttpr repeaters
1210 return 4;
1211 case 0x08: // 5 lttpr repeaters
1212 return 5;
1213 case 0x04: // 6 lttpr repeaters
1214 return 6;
1215 case 0x02: // 7 lttpr repeaters
1216 return 7;
1217 case 0x01: // 8 lttpr repeaters
1218 return 8;
1219 default:
1220 break;
1221 }
1222 return 0; // invalid value
1223}
1224
bad7ab0b 1225static void configure_lttpr_mode(struct dc_link *link)
1226{
1227 /* aux timeout is already set to extended */
1228 /* RESET/SET lttpr mode to enable non transparent mode */
64c12b73 1229 uint8_t repeater_cnt;
1230 uint32_t aux_interval_address;
1231 uint8_t repeater_id;
a166f86e 1232 enum dc_status result = DC_ERROR_UNEXPECTED;
61aa7a6f 1233 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
bad7ab0b 1234
c14f2507 1235 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
a166f86e 1236 result = core_link_write_dpcd(link,
bad7ab0b 1237 DP_PHY_REPEATER_MODE,
1238 (uint8_t *)&repeater_mode,
1239 sizeof(repeater_mode));
1240
a166f86e 1241 if (result == DC_OK) {
1242 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1243 }
1244
bad7ab0b 1245 if (!link->is_lttpr_mode_transparent) {
460adc6b 1246
c14f2507 1247 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
460adc6b 1248
61aa7a6f 1249 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
a166f86e 1250 result = core_link_write_dpcd(link,
bad7ab0b 1251 DP_PHY_REPEATER_MODE,
1252 (uint8_t *)&repeater_mode,
1253 sizeof(repeater_mode));
64c12b73 1254
a166f86e 1255 if (result == DC_OK) {
1256 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1257 }
1258
64c12b73 1259 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1260 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1261 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1262 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1263 core_link_read_dpcd(
1264 link,
1265 aux_interval_address,
1266 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1267 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1268 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1269 }
bad7ab0b 1270 }
1271}
1272
64c12b73 1273static void repeater_training_done(struct dc_link *link, uint32_t offset)
1274{
1275 union dpcd_training_pattern dpcd_pattern = { {0} };
1276
1277 const uint32_t dpcd_base_lt_offset =
1278 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1279 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1280 /* Set training not in progress*/
1281 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1282
1283 core_link_write_dpcd(
1284 link,
1285 dpcd_base_lt_offset,
1286 &dpcd_pattern.raw,
1287 1);
1288
460adc6b 1289 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
64c12b73 1290 __func__,
460adc6b 1291 offset,
64c12b73 1292 dpcd_base_lt_offset,
1293 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1294}
1295
e0a6440a
DG		 1296static void print_status_message(
1297 struct dc_link *link,
1298 const struct link_training_settings *lt_settings,
1299 enum link_training_result status)
1300{
1301 char *link_rate = "Unknown";
1302 char *lt_result = "Unknown";
1303 char *lt_spread = "Disabled";
4562236b 1304
e0a6440a 1305 switch (lt_settings->link_settings.link_rate) {
4562236b
HW		 1306 case LINK_RATE_LOW:
1307 link_rate = "RBR";
1308 break;
1309 case LINK_RATE_HIGH:
1310 link_rate = "HBR";
1311 break;
1312 case LINK_RATE_HIGH2:
1313 link_rate = "HBR2";
1314 break;
1315 case LINK_RATE_RBR2:
1316 link_rate = "RBR2";
1317 break;
1318 case LINK_RATE_HIGH3:
1319 link_rate = "HBR3";
1320 break;
1321 default:
1322 break;
1323 }
1324
94405cf6
WL		 1325 switch (status) {
1326 case LINK_TRAINING_SUCCESS:
1327 lt_result = "pass";
1328 break;
1329 case LINK_TRAINING_CR_FAIL_LANE0:
1330 lt_result = "CR failed lane0";
1331 break;
1332 case LINK_TRAINING_CR_FAIL_LANE1:
1333 lt_result = "CR failed lane1";
1334 break;
1335 case LINK_TRAINING_CR_FAIL_LANE23:
1336 lt_result = "CR failed lane23";
1337 break;
1338 case LINK_TRAINING_EQ_FAIL_CR:
1339 lt_result = "CR failed in EQ";
1340 break;
1341 case LINK_TRAINING_EQ_FAIL_EQ:
1342 lt_result = "EQ failed";
1343 break;
1344 case LINK_TRAINING_LQA_FAIL:
1345 lt_result = "LQA failed";
1346 break;
1347 default:
1348 break;
1349 }
1350
e0a6440a
DG		 1351 switch (lt_settings->link_settings.link_spread) {
1352 case LINK_SPREAD_DISABLED:
1353 lt_spread = "Disabled";
1354 break;
1355 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1356 lt_spread = "0.5% 30KHz";
1357 break;
1358 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1359 lt_spread = "0.5% 33KHz";
1360 break;
1361 default:
1362 break;
1363 }
1364
4562236b 1365 /* Connectivity log: link training */
e0a6440a
DG		 1366 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1367 link_rate,
1368 lt_settings->link_settings.lane_count,
1369 lt_result,
1370 lt_settings->lane_settings[0].VOLTAGE_SWING,
1371 lt_settings->lane_settings[0].PRE_EMPHASIS,
1372 lt_spread);
1373}
1374
64c12b73 1375void dc_link_dp_set_drive_settings(
1376 struct dc_link *link,
1377 struct link_training_settings *lt_settings)
1378{
1379 /* program ASIC PHY settings*/
1380 dp_set_hw_lane_settings(link, lt_settings, DPRX);
1381
1382 /* Notify DP sink the PHY settings from source */
1383 dpcd_set_lane_settings(link, lt_settings, DPRX);
1384}
1385
e0a6440a
DG		 1386bool dc_link_dp_perform_link_training_skip_aux(
1387 struct dc_link *link,
1388 const struct dc_link_settings *link_setting)
1389{
1390 struct link_training_settings lt_settings;
1391 enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1;
1392
0b226322
DG		 1393 initialize_training_settings(
1394 link,
1395 link_setting,
1396 &link->preferred_training_settings,
1397 &lt_settings);
e0a6440a
DG		 1398
1399 /* 1. Perform_clock_recovery_sequence. */
1400
1401 /* transmit training pattern for clock recovery */
64c12b73 1402 dp_set_hw_training_pattern(link, pattern_for_cr, DPRX);
e0a6440a
DG		 1403
1404 /* call HWSS to set lane settings*/
64c12b73 1405 dp_set_hw_lane_settings(link, &lt_settings, DPRX);
e0a6440a
DG		 1406
1407 /* wait receiver to lock-on*/
1408 wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1409
1410 /* 2. Perform_channel_equalization_sequence. */
1411
1412 /* transmit training pattern for channel equalization. */
64c12b73 1413 dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
e0a6440a
DG		 1414
1415 /* call HWSS to set lane settings*/
64c12b73 1416 dp_set_hw_lane_settings(link, &lt_settings, DPRX);
e0a6440a
DG		 1417
1418 /* wait receiver to lock-on. */
1419 wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1420
1421 /* 3. Perform_link_training_int. */
1422
1423 /* Mainlink output idle pattern. */
1424 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1425
1426 print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1427
1428 return true;
1429}
1430
1431enum link_training_result dc_link_dp_perform_link_training(
1432 struct dc_link *link,
1433 const struct dc_link_settings *link_setting,
1434 bool skip_video_pattern)
1435{
1436 enum link_training_result status = LINK_TRAINING_SUCCESS;
e0a6440a 1437 struct link_training_settings lt_settings;
64c12b73 1438
008a4016 1439 bool fec_enable;
64c12b73 1440 uint8_t repeater_cnt;
1441 uint8_t repeater_id;
e0a6440a 1442
0b226322
DG		 1443 initialize_training_settings(
1444 link,
1445 link_setting,
1446 &link->preferred_training_settings,
1447 &lt_settings);
e0a6440a 1448
bcc5042a 1449 /* Configure lttpr mode */
1450 if (!link->is_lttpr_mode_transparent)
1451 configure_lttpr_mode(link);
1452
82054678
ML		 1453 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1454 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
834a9a9f
ML		 1455
1456 /* 1. set link rate, lane count and spread. */
1457 dpcd_set_link_settings(link, &lt_settings);
e0a6440a 1458
008a4016
NC		 1459 if (link->preferred_training_settings.fec_enable != NULL)
1460 fec_enable = *link->preferred_training_settings.fec_enable;
1461 else
1462 fec_enable = true;
1463
1464 dp_set_fec_ready(link, fec_enable);
008a4016 1465
64c12b73 1466 if (!link->is_lttpr_mode_transparent) {
008a4016 1467
64c12b73 1468 /* 2. perform link training (set link training done
1469 * to false is done as well)
1470 */
1471 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1472
1473 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1474 repeater_id--) {
1475 status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
1476
1477 if (status != LINK_TRAINING_SUCCESS)
1478 break;
1479
1480 status = perform_channel_equalization_sequence(link,
1481 &lt_settings,
1482 repeater_id);
1483
1484 if (status != LINK_TRAINING_SUCCESS)
1485 break;
1486
1487 repeater_training_done(link, repeater_id);
1488 }
1489 }
1490
1491 if (status == LINK_TRAINING_SUCCESS) {
1492 status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
e0a6440a
DG		 1493 if (status == LINK_TRAINING_SUCCESS) {
1494 status = perform_channel_equalization_sequence(link,
64c12b73 1495 &lt_settings,
1496 DPRX);
1497 }
e0a6440a
DG		 1498 }
1499
1500 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1501 status = perform_link_training_int(link,
1502 &lt_settings,
1503 status);
1504 }
1505
1506 /* 6. print status message*/
1507 print_status_message(link, &lt_settings, status);
4562236b 1508
d6e75df4 1509 if (status != LINK_TRAINING_SUCCESS)
cfd84fd3 1510 link->ctx->dc->debug_data.ltFailCount++;
d6e75df4 1511
4562236b
HW		 1512 return status;
1513}
1514
4562236b 1515bool perform_link_training_with_retries(
4562236b
HW		 1516 const struct dc_link_settings *link_setting,
1517 bool skip_video_pattern,
832aa63b
PH		 1518 int attempts,
1519 struct pipe_ctx *pipe_ctx,
1520 enum signal_type signal)
4562236b
HW		 1521{
1522 uint8_t j;
1523 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
832aa63b
PH		 1524 struct dc_stream_state *stream = pipe_ctx->stream;
1525 struct dc_link *link = stream->link;
1526 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
4562236b
HW		 1527
1528 for (j = 0; j < attempts; ++j) {
1529
832aa63b
PH		 1530 dp_enable_link_phy(
1531 link,
1532 signal,
1533 pipe_ctx->clock_source->id,
1534 link_setting);
1535
1536 if (stream->sink_patches.dppowerup_delay > 0) {
1537 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1538
1539 msleep(delay_dp_power_up_in_ms);
1540 }
1541
1542 dp_set_panel_mode(link, panel_mode);
1543
1544 /* We need to do this before the link training to ensure the idle pattern in SST
1545 * mode will be sent right after the link training
1546 */
1547 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
1548 pipe_ctx->stream_res.stream_enc->id, true);
1549
1550 if (link->aux_access_disabled) {
1551 dc_link_dp_perform_link_training_skip_aux(link, link_setting);
1552 return true;
1553 } else if (dc_link_dp_perform_link_training(
d0778ebf 1554 link,
4562236b 1555 link_setting,
820e3935 1556 skip_video_pattern) == LINK_TRAINING_SUCCESS)
4562236b
HW		 1557 return true;
1558
832aa63b
PH		 1559 /* latest link training still fail, skip delay and keep PHY on
1560 */
1561 if (j == (attempts - 1))
1562 break;
1563
1564 dp_disable_link_phy(link, signal);
1565
4562236b 1566 msleep(delay_between_attempts);
832aa63b 1567
4562236b
HW		 1568 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1569 }
1570
1571 return false;
1572}
1573
0b226322
DG		 1574static enum clock_source_id get_clock_source_id(struct dc_link *link)
1575{
1576 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1577 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1578
1579 if (dp_cs != NULL) {
1580 dp_cs_id = dp_cs->id;
1581 } else {
1582 /*
1583 * dp clock source is not initialized for some reason.
1584 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1585 */
1586 ASSERT(dp_cs);
1587 }
1588
1589 return dp_cs_id;
1590}
1591
1592static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1593{
1594 if (mst_enable == false &&
1595 link->type == dc_connection_mst_branch) {
1596 /* Disable MST on link. Use only local sink. */
1597 dp_disable_link_phy_mst(link, link->connector_signal);
1598
1599 link->type = dc_connection_single;
1600 link->local_sink = link->remote_sinks[0];
1601 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1602 } else if (mst_enable == true &&
1603 link->type == dc_connection_single &&
1604 link->remote_sinks[0] != NULL) {
1605 /* Re-enable MST on link. */
1606 dp_disable_link_phy(link, link->connector_signal);
1607 dp_enable_mst_on_sink(link, true);
1608
1609 link->type = dc_connection_mst_branch;
1610 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1611 }
1612}
1613
1614bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1615{
1616 /* Begin Sync LT. During this time,
1617 * DPCD:600h must not be powered down.
1618 */
1619 link->sync_lt_in_progress = true;
1620
1621 /*Clear any existing preferred settings.*/
1622 memset(&link->preferred_training_settings, 0,
1623 sizeof(struct dc_link_training_overrides));
1624 memset(&link->preferred_link_setting, 0,
1625 sizeof(struct dc_link_settings));
1626
1627 return true;
1628}
1629
1630enum link_training_result dc_link_dp_sync_lt_attempt(
1631 struct dc_link *link,
1632 struct dc_link_settings *link_settings,
1633 struct dc_link_training_overrides *lt_overrides)
1634{
1635 struct link_training_settings lt_settings;
1636 enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1637 enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1638 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
0b226322 1639 bool fec_enable = false;
0b226322
DG		 1640
1641 initialize_training_settings(
1642 link,
1643 link_settings,
1644 lt_overrides,
1645 &lt_settings);
1646
1647 /* Setup MST Mode */
1648 if (lt_overrides->mst_enable)
1649 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1650
1651 /* Disable link */
1652 dp_disable_link_phy(link, link->connector_signal);
1653
1654 /* Enable link */
1655 dp_cs_id = get_clock_source_id(link);
1656 dp_enable_link_phy(link, link->connector_signal,
1657 dp_cs_id, link_settings);
1658
0b226322
DG		 1659 /* Set FEC enable */
1660 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1661 dp_set_fec_ready(link, fec_enable);
0b226322
DG		 1662
1663 if (lt_overrides->alternate_scrambler_reset) {
1664 if (*lt_overrides->alternate_scrambler_reset)
1665 panel_mode = DP_PANEL_MODE_EDP;
1666 else
1667 panel_mode = DP_PANEL_MODE_DEFAULT;
1668 } else
1669 panel_mode = dp_get_panel_mode(link);
1670
1671 dp_set_panel_mode(link, panel_mode);
1672
1673 /* Attempt to train with given link training settings */
82054678
ML		 1674 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1675 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
834a9a9f
ML		 1676
1677 /* Set link rate, lane count and spread. */
1678 dpcd_set_link_settings(link, &lt_settings);
0b226322
DG		 1679
1680 /* 2. perform link training (set link training done
1681 * to false is done as well)
1682 */
64c12b73 1683 lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
0b226322
DG		 1684 if (lt_status == LINK_TRAINING_SUCCESS) {
1685 lt_status = perform_channel_equalization_sequence(link,
64c12b73 1686 &lt_settings,
1687 DPRX);
0b226322
DG		 1688 }
1689
1690 /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1691 /* 4. print status message*/
1692 print_status_message(link, &lt_settings, lt_status);
1693
1694 return lt_status;
1695}
1696
1697bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1698{
1699 /* If input parameter is set, shut down phy.
1700 * Still shouldn't turn off dp_receiver (DPCD:600h)
1701 */
1702 if (link_down == true) {
1703 dp_disable_link_phy(link, link->connector_signal);
0b226322 1704 dp_set_fec_ready(link, false);
0b226322
DG		 1705 }
1706
1707 link->sync_lt_in_progress = false;
1708 return true;
1709}
1710
d0778ebf 1711static struct dc_link_settings get_max_link_cap(struct dc_link *link)
4562236b
HW		 1712{
1713 /* Set Default link settings */
1714 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
8628d02f 1715 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
4562236b
HW		 1716
1717 /* Higher link settings based on feature supported */
1718 if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1719 max_link_cap.link_rate = LINK_RATE_HIGH2;
1720
1721 if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1722 max_link_cap.link_rate = LINK_RATE_HIGH3;
1723
f537d474
LH		 1724 if (link->link_enc->funcs->get_max_link_cap)
1725 link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1726
4562236b 1727 /* Lower link settings based on sink's link cap */
d0778ebf 1728 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
4562236b 1729 max_link_cap.lane_count =
d0778ebf
HW		 1730 link->reported_link_cap.lane_count;
1731 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
4562236b 1732 max_link_cap.link_rate =
d0778ebf
HW		 1733 link->reported_link_cap.link_rate;
1734 if (link->reported_link_cap.link_spread <
4562236b
HW		 1735 max_link_cap.link_spread)
1736 max_link_cap.link_spread =
d0778ebf 1737 link->reported_link_cap.link_spread;
bad7ab0b 1738 /*
1739 * account for lttpr repeaters cap
1740 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1741 */
1742 if (!link->is_lttpr_mode_transparent) {
1743 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1744 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1745
1746 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1747 max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
460adc6b 1748
1749 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
1750 __func__,
1751 max_link_cap.lane_count,
1752 max_link_cap.link_rate);
bad7ab0b 1753 }
4562236b
HW		 1754 return max_link_cap;
1755}
1756
1ae62f31
WL		 1757static enum dc_status read_hpd_rx_irq_data(
1758 struct dc_link *link,
1759 union hpd_irq_data *irq_data)
1760{
1761 static enum dc_status retval;
1762
1763 /* The HW reads 16 bytes from 200h on HPD,
1764 * but if we get an AUX_DEFER, the HW cannot retry
1765 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1766 * fail, so we now explicitly read 6 bytes which is
1767 * the req from the above mentioned test cases.
1768 *
1769 * For DP 1.4 we need to read those from 2002h range.
1770 */
1771 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1772 retval = core_link_read_dpcd(
1773 link,
1774 DP_SINK_COUNT,
1775 irq_data->raw,
1776 sizeof(union hpd_irq_data));
1777 else {
1778 /* Read 14 bytes in a single read and then copy only the required fields.
1779 * This is more efficient than doing it in two separate AUX reads. */
1780
1781 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1782
1783 retval = core_link_read_dpcd(
1784 link,
1785 DP_SINK_COUNT_ESI,
1786 tmp,
1787 sizeof(tmp));
1788
1789 if (retval != DC_OK)
1790 return retval;
1791
1792 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1793 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1794 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1795 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1796 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1797 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1798 }
1799
1800 return retval;
1801}
1802
1803static bool hpd_rx_irq_check_link_loss_status(
1804 struct dc_link *link,
1805 union hpd_irq_data *hpd_irq_dpcd_data)
1806{
1807 uint8_t irq_reg_rx_power_state = 0;
1808 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1809 union lane_status lane_status;
1810 uint32_t lane;
1811 bool sink_status_changed;
1812 bool return_code;
1813
1814 sink_status_changed = false;
1815 return_code = false;
1816
1817 if (link->cur_link_settings.lane_count == 0)
1818 return return_code;
1819
1820 /*1. Check that Link Status changed, before re-training.*/
1821
1822 /*parse lane status*/
1823 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1824 /* check status of lanes 0,1
1825 * changed DpcdAddress_Lane01Status (0x202)
1826 */
1827 lane_status.raw = get_nibble_at_index(
1828 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1829 lane);
1830
1831 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1832 !lane_status.bits.CR_DONE_0 ||
1833 !lane_status.bits.SYMBOL_LOCKED_0) {
1834 /* if one of the channel equalization, clock
1835 * recovery or symbol lock is dropped
1836 * consider it as (link has been
1837 * dropped) dp sink status has changed
1838 */
1839 sink_status_changed = true;
1840 break;
1841 }
1842 }
1843
1844 /* Check interlane align.*/
1845 if (sink_status_changed ||
1846 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1847
1848 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1849
1850 return_code = true;
1851
1852 /*2. Check that we can handle interrupt: Not in FS DOS,
1853 * Not in "Display Timeout" state, Link is trained.
1854 */
1855 dpcd_result = core_link_read_dpcd(link,
1856 DP_SET_POWER,
1857 &irq_reg_rx_power_state,
1858 sizeof(irq_reg_rx_power_state));
1859
1860 if (dpcd_result != DC_OK) {
1861 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1862 __func__);
1863 } else {
1864 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1865 return_code = false;
1866 }
1867 }
1868
1869 return return_code;
1870}
1871
aafded88 1872bool dp_verify_link_cap(
d0778ebf 1873 struct dc_link *link,
824474ba
BL		 1874 struct dc_link_settings *known_limit_link_setting,
1875 int *fail_count)
4562236b
HW		 1876{
1877 struct dc_link_settings max_link_cap = {0};
820e3935
DW		 1878 struct dc_link_settings cur_link_setting = {0};
1879 struct dc_link_settings *cur = &cur_link_setting;
1880 struct dc_link_settings initial_link_settings = {0};
4562236b
HW		 1881 bool success;
1882 bool skip_link_training;
4562236b 1883 bool skip_video_pattern;
4562236b 1884 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
820e3935 1885 enum link_training_result status;
1ae62f31 1886 union hpd_irq_data irq_data;
4562236b 1887
aafded88
TC		 1888 if (link->dc->debug.skip_detection_link_training) {
1889 link->verified_link_cap = *known_limit_link_setting;
1890 return true;
1891 }
1892
1ae62f31 1893 memset(&irq_data, 0, sizeof(irq_data));
4562236b
HW		 1894 success = false;
1895 skip_link_training = false;
1896
1897 max_link_cap = get_max_link_cap(link);
1898
bad7ab0b 1899 /* Grant extended timeout request */
1900 if (!link->is_lttpr_mode_transparent && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
1901 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
1902
1903 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
1904 }
1905
4562236b
HW		 1906 /* TODO implement override and monitor patch later */
1907
1908 /* try to train the link from high to low to
1909 * find the physical link capability
1910 */
1911 /* disable PHY done possible by BIOS, will be done by driver itself */
d0778ebf 1912 dp_disable_link_phy(link, link->connector_signal);
4562236b 1913
b3282738
GS		 1914 dp_cs_id = get_clock_source_id(link);
1915
1916 /* link training starts with the maximum common settings
1917 * supported by both sink and ASIC.
1918 */
1919 initial_link_settings = get_common_supported_link_settings(
1920 *known_limit_link_setting,
1921 max_link_cap);
1922 cur_link_setting = initial_link_settings;
1923
ee765924
GS		 1924 /* Temporary Renoir-specific workaround for SWDEV-215184;
1925 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
1926 * so add extra cycle of enabling and disabling the PHY before first link training.
1927 */
1928 if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
1929 link->dc->debug.usbc_combo_phy_reset_wa) {
1930 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
1931 dp_disable_link_phy(link, link->connector_signal);
1932 }
1933
820e3935 1934 do {
4562236b 1935 skip_video_pattern = true;
820e3935 1936
4562236b
HW		 1937 if (cur->link_rate == LINK_RATE_LOW)
1938 skip_video_pattern = false;
1939
1940 dp_enable_link_phy(
1941 link,
d0778ebf 1942 link->connector_signal,
4562236b
HW		 1943 dp_cs_id,
1944 cur);
1945
94405cf6 1946
4562236b
HW		 1947 if (skip_link_training)
1948 success = true;
1949 else {
820e3935 1950 status = dc_link_dp_perform_link_training(
d0778ebf 1951 link,
4562236b
HW		 1952 cur,
1953 skip_video_pattern);
820e3935
DW		 1954 if (status == LINK_TRAINING_SUCCESS)
1955 success = true;
824474ba
BL		 1956 else
1957 (*fail_count)++;
4562236b
HW		 1958 }
1959
1ae62f31 1960 if (success) {
d0778ebf 1961 link->verified_link_cap = *cur;
1ae62f31
WL		 1962 udelay(1000);
1963 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
1964 if (hpd_rx_irq_check_link_loss_status(
1965 link,
1966 &irq_data))
1967 (*fail_count)++;
1968 }
4562236b
HW		 1969 /* always disable the link before trying another
1970 * setting or before returning we'll enable it later
1971 * based on the actual mode we're driving
1972 */
d0778ebf 1973 dp_disable_link_phy(link, link->connector_signal);
820e3935
DW		 1974 } while (!success && decide_fallback_link_setting(
1975 initial_link_settings, cur, status));
4562236b
HW		 1976
1977 /* Link Training failed for all Link Settings
1978 * (Lane Count is still unknown)
1979 */
1980 if (!success) {
1981 /* If all LT fails for all settings,
1982 * set verified = failed safe (1 lane low)
1983 */
d0778ebf
HW		 1984 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1985 link->verified_link_cap.link_rate = LINK_RATE_LOW;
4562236b 1986
d0778ebf 1987 link->verified_link_cap.link_spread =
4562236b
HW		 1988 LINK_SPREAD_DISABLED;
1989 }
1990
4562236b
HW		 1991
1992 return success;
1993}
1994
e7f2c80c
WL		 1995bool dp_verify_link_cap_with_retries(
1996 struct dc_link *link,
1997 struct dc_link_settings *known_limit_link_setting,
1998 int attempts)
1999{
2000 uint8_t i = 0;
2001 bool success = false;
2002
2003 for (i = 0; i < attempts; i++) {
2004 int fail_count = 0;
82db2e3c 2005 enum dc_connection_type type = dc_connection_none;
e7f2c80c
WL		 2006
2007 memset(&link->verified_link_cap, 0,
2008 sizeof(struct dc_link_settings));
82db2e3c
SK		 2009 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2010 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2011 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2012 link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
e7f2c80c
WL		 2013 break;
2014 } else if (dp_verify_link_cap(link,
2015 &link->reported_link_cap,
2016 &fail_count) && fail_count == 0) {
2017 success = true;
2018 break;
2019 }
2020 msleep(10);
2021 }
2022 return success;
2023}
2024
f537d474
LH		 2025bool dp_verify_mst_link_cap(
2026 struct dc_link *link)
2027{
2028 struct dc_link_settings max_link_cap = {0};
2029
2030 max_link_cap = get_max_link_cap(link);
2031 link->verified_link_cap = get_common_supported_link_settings(
2032 link->reported_link_cap,
2033 max_link_cap);
2034
2035 return true;
2036}
2037
9a6a8075 2038static struct dc_link_settings get_common_supported_link_settings(
820e3935
DW		 2039 struct dc_link_settings link_setting_a,
2040 struct dc_link_settings link_setting_b)
2041{
2042 struct dc_link_settings link_settings = {0};
2043
2044 link_settings.lane_count =
2045 (link_setting_a.lane_count <=
2046 link_setting_b.lane_count) ?
2047 link_setting_a.lane_count :
2048 link_setting_b.lane_count;
2049 link_settings.link_rate =
2050 (link_setting_a.link_rate <=
2051 link_setting_b.link_rate) ?
2052 link_setting_a.link_rate :
2053 link_setting_b.link_rate;
2054 link_settings.link_spread = LINK_SPREAD_DISABLED;
2055
2056 /* in DP compliance test, DPR-120 may have
2057 * a random value in its MAX_LINK_BW dpcd field.
2058 * We map it to the maximum supported link rate that
2059 * is smaller than MAX_LINK_BW in this case.
2060 */
2061 if (link_settings.link_rate > LINK_RATE_HIGH3) {
2062 link_settings.link_rate = LINK_RATE_HIGH3;
2063 } else if (link_settings.link_rate < LINK_RATE_HIGH3
2064 && link_settings.link_rate > LINK_RATE_HIGH2) {
2065 link_settings.link_rate = LINK_RATE_HIGH2;
2066 } else if (link_settings.link_rate < LINK_RATE_HIGH2
2067 && link_settings.link_rate > LINK_RATE_HIGH) {
2068 link_settings.link_rate = LINK_RATE_HIGH;
2069 } else if (link_settings.link_rate < LINK_RATE_HIGH
2070 && link_settings.link_rate > LINK_RATE_LOW) {
2071 link_settings.link_rate = LINK_RATE_LOW;
2072 } else if (link_settings.link_rate < LINK_RATE_LOW) {
2073 link_settings.link_rate = LINK_RATE_UNKNOWN;
2074 }
2075
2076 return link_settings;
2077}
2078
450619d3 2079static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 2080{
2081 return lane_count <= LANE_COUNT_ONE;
2082}
2083
450619d3 2084static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 2085{
2086 return link_rate <= LINK_RATE_LOW;
2087}
2088
44858055 2089static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 2090{
2091 switch (lane_count) {
2092 case LANE_COUNT_FOUR:
2093 return LANE_COUNT_TWO;
2094 case LANE_COUNT_TWO:
2095 return LANE_COUNT_ONE;
2096 case LANE_COUNT_ONE:
2097 return LANE_COUNT_UNKNOWN;
2098 default:
2099 return LANE_COUNT_UNKNOWN;
2100 }
2101}
2102
04e21292 2103static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 2104{
2105 switch (link_rate) {
2106 case LINK_RATE_HIGH3:
2107 return LINK_RATE_HIGH2;
2108 case LINK_RATE_HIGH2:
2109 return LINK_RATE_HIGH;
2110 case LINK_RATE_HIGH:
2111 return LINK_RATE_LOW;
2112 case LINK_RATE_LOW:
2113 return LINK_RATE_UNKNOWN;
2114 default:
2115 return LINK_RATE_UNKNOWN;
2116 }
2117}
2118
04e21292 2119static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
8c4abe0b
DW		 2120{
2121 switch (lane_count) {
2122 case LANE_COUNT_ONE:
2123 return LANE_COUNT_TWO;
2124 case LANE_COUNT_TWO:
2125 return LANE_COUNT_FOUR;
2126 default:
2127 return LANE_COUNT_UNKNOWN;
2128 }
2129}
2130
04e21292 2131static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
8c4abe0b
DW		 2132{
2133 switch (link_rate) {
2134 case LINK_RATE_LOW:
2135 return LINK_RATE_HIGH;
2136 case LINK_RATE_HIGH:
2137 return LINK_RATE_HIGH2;
2138 case LINK_RATE_HIGH2:
2139 return LINK_RATE_HIGH3;
2140 default:
2141 return LINK_RATE_UNKNOWN;
2142 }
2143}
2144
820e3935
DW		 2145/*
2146 * function: set link rate and lane count fallback based
2147 * on current link setting and last link training result
2148 * return value:
2149 * true - link setting could be set
2150 * false - has reached minimum setting
2151 * and no further fallback could be done
2152 */
04e21292 2153static bool decide_fallback_link_setting(
820e3935
DW		 2154 struct dc_link_settings initial_link_settings,
2155 struct dc_link_settings *current_link_setting,
2156 enum link_training_result training_result)
2157{
2158 if (!current_link_setting)
2159 return false;
2160
2161 switch (training_result) {
94405cf6
WL		 2162 case LINK_TRAINING_CR_FAIL_LANE0:
2163 case LINK_TRAINING_CR_FAIL_LANE1:
2164 case LINK_TRAINING_CR_FAIL_LANE23:
2165 case LINK_TRAINING_LQA_FAIL:
820e3935
DW		 2166 {
2167 if (!reached_minimum_link_rate
2168 (current_link_setting->link_rate)) {
2169 current_link_setting->link_rate =
2170 reduce_link_rate(
2171 current_link_setting->link_rate);
2172 } else if (!reached_minimum_lane_count
2173 (current_link_setting->lane_count)) {
2174 current_link_setting->link_rate =
2175 initial_link_settings.link_rate;
94405cf6
WL		 2176 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2177 return false;
2178 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2179 current_link_setting->lane_count =
2180 LANE_COUNT_ONE;
2181 else if (training_result ==
2182 LINK_TRAINING_CR_FAIL_LANE23)
2183 current_link_setting->lane_count =
2184 LANE_COUNT_TWO;
2185 else
2186 current_link_setting->lane_count =
2187 reduce_lane_count(
820e3935
DW		 2188 current_link_setting->lane_count);
2189 } else {
2190 return false;
2191 }
2192 break;
2193 }
2194 case LINK_TRAINING_EQ_FAIL_EQ:
2195 {
2196 if (!reached_minimum_lane_count
2197 (current_link_setting->lane_count)) {
2198 current_link_setting->lane_count =
2199 reduce_lane_count(
2200 current_link_setting->lane_count);
2201 } else if (!reached_minimum_link_rate
2202 (current_link_setting->link_rate)) {
820e3935
DW		 2203 current_link_setting->link_rate =
2204 reduce_link_rate(
2205 current_link_setting->link_rate);
2206 } else {
2207 return false;
2208 }
2209 break;
2210 }
2211 case LINK_TRAINING_EQ_FAIL_CR:
2212 {
2213 if (!reached_minimum_link_rate
2214 (current_link_setting->link_rate)) {
2215 current_link_setting->link_rate =
2216 reduce_link_rate(
2217 current_link_setting->link_rate);
2218 } else {
2219 return false;
2220 }
2221 break;
2222 }
2223 default:
2224 return false;
2225 }
2226 return true;
2227}
2228
4562236b 2229bool dp_validate_mode_timing(
d0778ebf 2230 struct dc_link *link,
4562236b
HW		 2231 const struct dc_crtc_timing *timing)
2232{
2233 uint32_t req_bw;
2234 uint32_t max_bw;
2235
2236 const struct dc_link_settings *link_setting;
2237
2238 /*always DP fail safe mode*/
380604e2 2239 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
9a6a8075
HW		 2240 timing->h_addressable == (uint32_t) 640 &&
2241 timing->v_addressable == (uint32_t) 480)
4562236b
HW		 2242 return true;
2243
5ac4619b 2244 link_setting = dc_link_get_link_cap(link);
4562236b
HW		 2245
2246 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2247 /*if (flags.DYNAMIC_VALIDATION == 1 &&
d0778ebf
HW		 2248 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2249 link_setting = &link->verified_link_cap;
4562236b
HW		 2250 */
2251
e49f6936 2252 req_bw = dc_bandwidth_in_kbps_from_timing(timing);
332c1191 2253 max_bw = dc_link_bandwidth_kbps(link, link_setting);
4562236b
HW		 2254
2255 if (req_bw <= max_bw) {
2256 /* remember the biggest mode here, during
2257 * initial link training (to get
2258 * verified_link_cap), LS sends event about
2259 * cannot train at reported cap to upper
2260 * layer and upper layer will re-enumerate modes.
2261 * this is not necessary if the lower
2262 * verified_link_cap is enough to drive
2263 * all the modes */
2264
2265 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2266 /* if (flags.DYNAMIC_VALIDATION == 1)
2267 dpsst->max_req_bw_for_verified_linkcap = dal_max(
2268 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2269 return true;
2270 } else
2271 return false;
2272}
2273
8628d02f 2274static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
4562236b 2275{
8c4abe0b 2276 struct dc_link_settings initial_link_setting = {
8628d02f 2277 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
8c4abe0b
DW		 2278 struct dc_link_settings current_link_setting =
2279 initial_link_setting;
4562236b 2280 uint32_t link_bw;
4562236b 2281
8628d02f
JP		 2282 /* search for the minimum link setting that:
2283 * 1. is supported according to the link training result
2284 * 2. could support the b/w requested by the timing
4562236b 2285 */
8628d02f
JP		 2286 while (current_link_setting.link_rate <=
2287 link->verified_link_cap.link_rate) {
332c1191
NC		 2288 link_bw = dc_link_bandwidth_kbps(
2289 link,
8628d02f
JP		 2290 &current_link_setting);
2291 if (req_bw <= link_bw) {
2292 *link_setting = current_link_setting;
2293 return true;
2294 }
4562236b 2295
8628d02f
JP		 2296 if (current_link_setting.lane_count <
2297 link->verified_link_cap.lane_count) {
2298 current_link_setting.lane_count =
2299 increase_lane_count(
2300 current_link_setting.lane_count);
2301 } else {
2302 current_link_setting.link_rate =
2303 increase_link_rate(
2304 current_link_setting.link_rate);
2305 current_link_setting.lane_count =
2306 initial_link_setting.lane_count;
2307 }
3f1f74f4
JZ		 2308 }
2309
8628d02f
JP		 2310 return false;
2311}
2312
2313static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2314{
2315 struct dc_link_settings initial_link_setting;
2316 struct dc_link_settings current_link_setting;
2317 uint32_t link_bw;
2318
2319 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
53c81fc7 2320 link->dpcd_caps.edp_supported_link_rates_count == 0) {
4d2f22d1 2321 *link_setting = link->verified_link_cap;
8628d02f 2322 return true;
4d2f22d1
HH		 2323 }
2324
8628d02f
JP		 2325 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2326 initial_link_setting.lane_count = LANE_COUNT_ONE;
2327 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2328 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2329 initial_link_setting.use_link_rate_set = true;
2330 initial_link_setting.link_rate_set = 0;
2331 current_link_setting = initial_link_setting;
2332
5667ff5c
DA		 2333 /* search for the minimum link setting that:
2334 * 1. is supported according to the link training result
2335 * 2. could support the b/w requested by the timing
2336 */
8c4abe0b 2337 while (current_link_setting.link_rate <=
4654a2f7 2338 link->verified_link_cap.link_rate) {
332c1191
NC		 2339 link_bw = dc_link_bandwidth_kbps(
2340 link,
8c4abe0b
DW		 2341 &current_link_setting);
2342 if (req_bw <= link_bw) {
2343 *link_setting = current_link_setting;
8628d02f 2344 return true;
4562236b 2345 }
4562236b 2346
8c4abe0b 2347 if (current_link_setting.lane_count <
4654a2f7 2348 link->verified_link_cap.lane_count) {
8c4abe0b
DW		 2349 current_link_setting.lane_count =
2350 increase_lane_count(
2351 current_link_setting.lane_count);
2352 } else {
8628d02f
JP		 2353 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2354 current_link_setting.link_rate_set++;
2355 current_link_setting.link_rate =
2356 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2357 current_link_setting.lane_count =
2358 initial_link_setting.lane_count;
2359 } else
2360 break;
4562236b
HW		 2361 }
2362 }
8628d02f
JP		 2363 return false;
2364}
2365
2366void decide_link_settings(struct dc_stream_state *stream,
2367 struct dc_link_settings *link_setting)
2368{
2369 struct dc_link *link;
2370 uint32_t req_bw;
2371
e49f6936 2372 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
8628d02f
JP		 2373
2374 link = stream->link;
2375
2376 /* if preferred is specified through AMDDP, use it, if it's enough
2377 * to drive the mode
2378 */
2379 if (link->preferred_link_setting.lane_count !=
2380 LANE_COUNT_UNKNOWN &&
2381 link->preferred_link_setting.link_rate !=
2382 LINK_RATE_UNKNOWN) {
2383 *link_setting = link->preferred_link_setting;
2384 return;
2385 }
2386
2387 /* MST doesn't perform link training for now
2388 * TODO: add MST specific link training routine
2389 */
2390 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2391 *link_setting = link->verified_link_cap;
2392 return;
2393 }
2394
2395 if (link->connector_signal == SIGNAL_TYPE_EDP) {
2396 if (decide_edp_link_settings(link, link_setting, req_bw))
2397 return;
2398 } else if (decide_dp_link_settings(link, link_setting, req_bw))
2399 return;
4562236b
HW		 2400
2401 BREAK_TO_DEBUGGER();
d0778ebf 2402 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
4562236b 2403
d0778ebf 2404 *link_setting = link->verified_link_cap;
4562236b
HW		 2405}
2406
2407/*************************Short Pulse IRQ***************************/
d0778ebf 2408static bool allow_hpd_rx_irq(const struct dc_link *link)
4562236b
HW		 2409{
2410 /*
2411 * Don't handle RX IRQ unless one of following is met:
2412 * 1) The link is established (cur_link_settings != unknown)
2413 * 2) We kicked off MST detection
2414 * 3) We know we're dealing with an active dongle
2415 */
2416
d0778ebf
HW		 2417 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2418 (link->type == dc_connection_mst_branch) ||
4562236b
HW		 2419 is_dp_active_dongle(link))
2420 return true;
2421
2422 return false;
2423}
2424
ab4a4072 2425static bool handle_hpd_irq_psr_sink(struct dc_link *link)
4562236b
HW		 2426{
2427 union dpcd_psr_configuration psr_configuration;
2428
ab4a4072 2429 if (!link->psr_feature_enabled)
4562236b
HW		 2430 return false;
2431
7c7f5b15
AG		 2432 dm_helpers_dp_read_dpcd(
2433 link->ctx,
d0778ebf 2434 link,
7c7f5b15
AG		 2435 368,/*DpcdAddress_PSR_Enable_Cfg*/
2436 &psr_configuration.raw,
2437 sizeof(psr_configuration.raw));
2438
4562236b
HW		 2439
2440 if (psr_configuration.bits.ENABLE) {
2441 unsigned char dpcdbuf[3] = {0};
2442 union psr_error_status psr_error_status;
2443 union psr_sink_psr_status psr_sink_psr_status;
2444
7c7f5b15
AG		 2445 dm_helpers_dp_read_dpcd(
2446 link->ctx,
d0778ebf 2447 link,
7c7f5b15
AG		 2448 0x2006, /*DpcdAddress_PSR_Error_Status*/
2449 (unsigned char *) dpcdbuf,
2450 sizeof(dpcdbuf));
4562236b
HW		 2451
2452 /*DPCD 2006h ERROR STATUS*/
2453 psr_error_status.raw = dpcdbuf[0];
2454 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
2455 psr_sink_psr_status.raw = dpcdbuf[2];
2456
2457 if (psr_error_status.bits.LINK_CRC_ERROR ||
2458 psr_error_status.bits.RFB_STORAGE_ERROR) {
2459 /* Acknowledge and clear error bits */
7c7f5b15
AG		 2460 dm_helpers_dp_write_dpcd(
2461 link->ctx,
d0778ebf 2462 link,
7c7f5b15 2463 8198,/*DpcdAddress_PSR_Error_Status*/
4562236b
HW		 2464 &psr_error_status.raw,
2465 sizeof(psr_error_status.raw));
2466
2467 /* PSR error, disable and re-enable PSR */
ab4a4072
EY		 2468 dc_link_set_psr_allow_active(link, false, true);
2469 dc_link_set_psr_allow_active(link, true, true);
4562236b
HW		 2470
2471 return true;
2472 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2473 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2474 /* No error is detect, PSR is active.
2475 * We should return with IRQ_HPD handled without
2476 * checking for loss of sync since PSR would have
2477 * powered down main link.
2478 */
2479 return true;
2480 }
2481 }
2482 return false;
2483}
2484
d0778ebf 2485static void dp_test_send_link_training(struct dc_link *link)
4562236b 2486{
73c72602 2487 struct dc_link_settings link_settings = {0};
4562236b
HW		 2488
2489 core_link_read_dpcd(
2490 link,
3a340294 2491 DP_TEST_LANE_COUNT,
4562236b
HW		 2492 (unsigned char *)(&link_settings.lane_count),
2493 1);
2494 core_link_read_dpcd(
2495 link,
3a340294 2496 DP_TEST_LINK_RATE,
4562236b
HW		 2497 (unsigned char *)(&link_settings.link_rate),
2498 1);
2499
2500 /* Set preferred link settings */
d0778ebf
HW		 2501 link->verified_link_cap.lane_count = link_settings.lane_count;
2502 link->verified_link_cap.link_rate = link_settings.link_rate;
4562236b 2503
73c72602 2504 dp_retrain_link_dp_test(link, &link_settings, false);
4562236b
HW		 2505}
2506
9315e239 2507/* TODO Raven hbr2 compliance eye output is unstable
25bab0da
WL		 2508 * (toggling on and off) with debugger break
2509 * This caueses intermittent PHY automation failure
2510 * Need to look into the root cause */
d0778ebf 2511static void dp_test_send_phy_test_pattern(struct dc_link *link)
4562236b
HW		 2512{
2513 union phy_test_pattern dpcd_test_pattern;
2514 union lane_adjust dpcd_lane_adjustment[2];
2515 unsigned char dpcd_post_cursor_2_adjustment = 0;
2516 unsigned char test_80_bit_pattern[
3a340294
DA		 2517 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2518 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
4562236b
HW		 2519 enum dp_test_pattern test_pattern;
2520 struct dc_link_training_settings link_settings;
2521 union lane_adjust dpcd_lane_adjust;
2522 unsigned int lane;
2523 struct link_training_settings link_training_settings;
2524 int i = 0;
2525
2526 dpcd_test_pattern.raw = 0;
2527 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2528 memset(&link_settings, 0, sizeof(link_settings));
2529
2530 /* get phy test pattern and pattern parameters from DP receiver */
2531 core_link_read_dpcd(
2532 link,
3a340294 2533 DP_TEST_PHY_PATTERN,
4562236b
HW		 2534 &dpcd_test_pattern.raw,
2535 sizeof(dpcd_test_pattern));
2536 core_link_read_dpcd(
2537 link,
3a340294 2538 DP_ADJUST_REQUEST_LANE0_1,
4562236b
HW		 2539 &dpcd_lane_adjustment[0].raw,
2540 sizeof(dpcd_lane_adjustment));
2541
2542 /*get post cursor 2 parameters
2543 * For DP 1.1a or eariler, this DPCD register's value is 0
2544 * For DP 1.2 or later:
2545 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2546 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2547 */
2548 core_link_read_dpcd(
2549 link,
3a340294 2550 DP_ADJUST_REQUEST_POST_CURSOR2,
4562236b
HW		 2551 &dpcd_post_cursor_2_adjustment,
2552 sizeof(dpcd_post_cursor_2_adjustment));
2553
2554 /* translate request */
2555 switch (dpcd_test_pattern.bits.PATTERN) {
2556 case PHY_TEST_PATTERN_D10_2:
2557 test_pattern = DP_TEST_PATTERN_D102;
0e19401f 2558 break;
4562236b
HW		 2559 case PHY_TEST_PATTERN_SYMBOL_ERROR:
2560 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 2561 break;
4562236b
HW		 2562 case PHY_TEST_PATTERN_PRBS7:
2563 test_pattern = DP_TEST_PATTERN_PRBS7;
0e19401f 2564 break;
4562236b
HW		 2565 case PHY_TEST_PATTERN_80BIT_CUSTOM:
2566 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 2567 break;
2568 case PHY_TEST_PATTERN_CP2520_1:
25bab0da 2569 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 2570 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 2571 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2572 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 2573 break;
2574 case PHY_TEST_PATTERN_CP2520_2:
25bab0da 2575 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 2576 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 2577 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2578 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 2579 break;
2580 case PHY_TEST_PATTERN_CP2520_3:
78e685f9 2581 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
0e19401f 2582 break;
4562236b
HW		 2583 default:
2584 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2585 break;
2586 }
2587
2588 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2589 core_link_read_dpcd(
2590 link,
3a340294 2591 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
4562236b
HW		 2592 test_80_bit_pattern,
2593 sizeof(test_80_bit_pattern));
2594
2595 /* prepare link training settings */
d0778ebf 2596 link_settings.link = link->cur_link_settings;
4562236b
HW		 2597
2598 for (lane = 0; lane <
d0778ebf 2599 (unsigned int)(link->cur_link_settings.lane_count);
4562236b
HW		 2600 lane++) {
2601 dpcd_lane_adjust.raw =
2602 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2603 link_settings.lane_settings[lane].VOLTAGE_SWING =
2604 (enum dc_voltage_swing)
2605 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2606 link_settings.lane_settings[lane].PRE_EMPHASIS =
2607 (enum dc_pre_emphasis)
2608 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2609 link_settings.lane_settings[lane].POST_CURSOR2 =
2610 (enum dc_post_cursor2)
2611 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2612 }
2613
2614 for (i = 0; i < 4; i++)
2615 link_training_settings.lane_settings[i] =
2616 link_settings.lane_settings[i];
2617 link_training_settings.link_settings = link_settings.link;
2618 link_training_settings.allow_invalid_msa_timing_param = false;
2619 /*Usage: Measure DP physical lane signal
2620 * by DP SI test equipment automatically.
2621 * PHY test pattern request is generated by equipment via HPD interrupt.
2622 * HPD needs to be active all the time. HPD should be active
2623 * all the time. Do not touch it.
2624 * forward request to DS
2625 */
2626 dc_link_dp_set_test_pattern(
d0778ebf 2627 link,
4562236b 2628 test_pattern,
2057b7e1 2629 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
4562236b
HW		 2630 &link_training_settings,
2631 test_80_bit_pattern,
3a340294
DA		 2632 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2633 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
4562236b
HW		 2634}
2635
d0778ebf 2636static void dp_test_send_link_test_pattern(struct dc_link *link)
4562236b
HW		 2637{
2638 union link_test_pattern dpcd_test_pattern;
2639 union test_misc dpcd_test_params;
2640 enum dp_test_pattern test_pattern;
2057b7e1
WL		 2641 enum dp_test_pattern_color_space test_pattern_color_space =
2642 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
4562236b
HW		 2643
2644 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2645 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2646
2647 /* get link test pattern and pattern parameters */
2648 core_link_read_dpcd(
2649 link,
3a340294 2650 DP_TEST_PATTERN,
4562236b
HW		 2651 &dpcd_test_pattern.raw,
2652 sizeof(dpcd_test_pattern));
2653 core_link_read_dpcd(
2654 link,
3a340294 2655 DP_TEST_MISC0,
4562236b
HW		 2656 &dpcd_test_params.raw,
2657 sizeof(dpcd_test_params));
2658
2659 switch (dpcd_test_pattern.bits.PATTERN) {
2660 case LINK_TEST_PATTERN_COLOR_RAMP:
2661 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2662 break;
2663 case LINK_TEST_PATTERN_VERTICAL_BARS:
2664 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2665 break; /* black and white */
2666 case LINK_TEST_PATTERN_COLOR_SQUARES:
2667 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2668 TEST_DYN_RANGE_VESA ?
2669 DP_TEST_PATTERN_COLOR_SQUARES :
2670 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2671 break;
2672 default:
2673 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2674 break;
2675 }
2676
ef65c702
JFZ		 2677 if (dpcd_test_params.bits.CLR_FORMAT == 0)
2678 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2679 else
2680 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2681 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2682 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2057b7e1 2683
4562236b 2684 dc_link_dp_set_test_pattern(
d0778ebf 2685 link,
4562236b 2686 test_pattern,
2057b7e1 2687 test_pattern_color_space,
4562236b
HW		 2688 NULL,
2689 NULL,
2690 0);
2691}
2692
8c8048f2 2693static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
2694{
2695 union audio_test_mode dpcd_test_mode = {0};
2696 struct audio_test_pattern_type dpcd_pattern_type = {0};
2697 union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
2698 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2699
2700 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2701 struct pipe_ctx *pipe_ctx = &pipes[0];
2702 unsigned int channel_count;
2703 unsigned int channel = 0;
2704 unsigned int modes = 0;
2705 unsigned int sampling_rate_in_hz = 0;
2706
2707 // get audio test mode and test pattern parameters
2708 core_link_read_dpcd(
2709 link,
2710 DP_TEST_AUDIO_MODE,
2711 &dpcd_test_mode.raw,
2712 sizeof(dpcd_test_mode));
2713
2714 core_link_read_dpcd(
2715 link,
2716 DP_TEST_AUDIO_PATTERN_TYPE,
2717 &dpcd_pattern_type.value,
2718 sizeof(dpcd_pattern_type));
2719
2720 channel_count = dpcd_test_mode.bits.channel_count + 1;
2721
2722 // read pattern periods for requested channels when sawTooth pattern is requested
2723 if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
2724 dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
2725
2726 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
2727 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2728 // read period for each channel
2729 for (channel = 0; channel < channel_count; channel++) {
2730 core_link_read_dpcd(
2731 link,
2732 DP_TEST_AUDIO_PERIOD_CH1 + channel,
2733 &dpcd_pattern_period[channel].raw,
2734 sizeof(dpcd_pattern_period[channel]));
2735 }
2736 }
2737
2738 // translate sampling rate
2739 switch (dpcd_test_mode.bits.sampling_rate) {
2740 case AUDIO_SAMPLING_RATE_32KHZ:
2741 sampling_rate_in_hz = 32000;
2742 break;
2743 case AUDIO_SAMPLING_RATE_44_1KHZ:
2744 sampling_rate_in_hz = 44100;
2745 break;
2746 case AUDIO_SAMPLING_RATE_48KHZ:
2747 sampling_rate_in_hz = 48000;
2748 break;
2749 case AUDIO_SAMPLING_RATE_88_2KHZ:
2750 sampling_rate_in_hz = 88200;
2751 break;
2752 case AUDIO_SAMPLING_RATE_96KHZ:
2753 sampling_rate_in_hz = 96000;
2754 break;
2755 case AUDIO_SAMPLING_RATE_176_4KHZ:
2756 sampling_rate_in_hz = 176400;
2757 break;
2758 case AUDIO_SAMPLING_RATE_192KHZ:
2759 sampling_rate_in_hz = 192000;
2760 break;
2761 default:
2762 sampling_rate_in_hz = 0;
2763 break;
2764 }
2765
2766 link->audio_test_data.flags.test_requested = 1;
2767 link->audio_test_data.flags.disable_video = disable_video;
2768 link->audio_test_data.sampling_rate = sampling_rate_in_hz;
2769 link->audio_test_data.channel_count = channel_count;
2770 link->audio_test_data.pattern_type = test_pattern;
2771
2772 if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
2773 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
2774 link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
2775 }
2776 }
2777}
2778
d0778ebf 2779static void handle_automated_test(struct dc_link *link)
4562236b
HW		 2780{
2781 union test_request test_request;
2782 union test_response test_response;
2783
2784 memset(&test_request, 0, sizeof(test_request));
2785 memset(&test_response, 0, sizeof(test_response));
2786
2787 core_link_read_dpcd(
2788 link,
3a340294 2789 DP_TEST_REQUEST,
4562236b
HW		 2790 &test_request.raw,
2791 sizeof(union test_request));
2792 if (test_request.bits.LINK_TRAINING) {
2793 /* ACK first to let DP RX test box monitor LT sequence */
2794 test_response.bits.ACK = 1;
2795 core_link_write_dpcd(
2796 link,
3a340294 2797 DP_TEST_RESPONSE,
4562236b
HW		 2798 &test_response.raw,
2799 sizeof(test_response));
2800 dp_test_send_link_training(link);
2801 /* no acknowledge request is needed again */
2802 test_response.bits.ACK = 0;
2803 }
2804 if (test_request.bits.LINK_TEST_PATTRN) {
2805 dp_test_send_link_test_pattern(link);
75a74755 2806 test_response.bits.ACK = 1;
4562236b 2807 }
8c8048f2 2808
2809 if (test_request.bits.AUDIO_TEST_PATTERN) {
2810 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
2811 test_response.bits.ACK = 1;
2812 }
2813
4562236b
HW		 2814 if (test_request.bits.PHY_TEST_PATTERN) {
2815 dp_test_send_phy_test_pattern(link);
2816 test_response.bits.ACK = 1;
2817 }
a6729a5a 2818
4562236b
HW		 2819 /* send request acknowledgment */
2820 if (test_response.bits.ACK)
2821 core_link_write_dpcd(
2822 link,
3a340294 2823 DP_TEST_RESPONSE,
4562236b
HW		 2824 &test_response.raw,
2825 sizeof(test_response));
2826}
2827
4e18814e 2828bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
4562236b 2829{
9a6a8075 2830 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
c2e218dd 2831 union device_service_irq device_service_clear = { { 0 } };
d6258eaa 2832 enum dc_status result;
4562236b 2833 bool status = false;
48af9b91 2834 struct pipe_ctx *pipe_ctx;
99218d12 2835 struct dc_link_settings previous_link_settings;
48af9b91 2836 int i;
4e18814e
FD		 2837
2838 if (out_link_loss)
2839 *out_link_loss = false;
4562236b
HW		 2840 /* For use cases related to down stream connection status change,
2841 * PSR and device auto test, refer to function handle_sst_hpd_irq
2842 * in DAL2.1*/
2843
1296423b 2844 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
d0778ebf 2845 __func__, link->link_index);
4562236b 2846
8ee65d7c 2847
4562236b
HW		 2848 /* All the "handle_hpd_irq_xxx()" methods
2849 * should be called only after
2850 * dal_dpsst_ls_read_hpd_irq_data
2851 * Order of calls is important too
2852 */
2853 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
8ee65d7c
WL		 2854 if (out_hpd_irq_dpcd_data)
2855 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4562236b
HW		 2856
2857 if (result != DC_OK) {
1296423b 2858 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
4562236b
HW		 2859 __func__);
2860 return false;
2861 }
2862
2863 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2864 device_service_clear.bits.AUTOMATED_TEST = 1;
2865 core_link_write_dpcd(
2866 link,
3a340294 2867 DP_DEVICE_SERVICE_IRQ_VECTOR,
4562236b
HW		 2868 &device_service_clear.raw,
2869 sizeof(device_service_clear.raw));
2870 device_service_clear.raw = 0;
2871 handle_automated_test(link);
2872 return false;
2873 }
2874
2875 if (!allow_hpd_rx_irq(link)) {
1296423b 2876 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
d0778ebf 2877 __func__, link->link_index);
4562236b
HW		 2878 return false;
2879 }
2880
2881 if (handle_hpd_irq_psr_sink(link))
2882 /* PSR-related error was detected and handled */
2883 return true;
2884
2885 /* If PSR-related error handled, Main link may be off,
2886 * so do not handle as a normal sink status change interrupt.
2887 */
2888
aaa15026
WL		 2889 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2890 return true;
2891
4562236b 2892 /* check if we have MST msg and return since we poll for it */
aaa15026 2893 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
4562236b
HW		 2894 return false;
2895
2896 /* For now we only handle 'Downstream port status' case.
2897 * If we got sink count changed it means
2898 * Downstream port status changed,
e97ed496
AK		 2899 * then DM should call DC to do the detection.
2900 * NOTE: Do not handle link loss on eDP since it is internal link*/
2901 if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
2902 hpd_rx_irq_check_link_loss_status(
2903 link,
2904 &hpd_irq_dpcd_data)) {
4562236b
HW		 2905 /* Connectivity log: link loss */
2906 CONN_DATA_LINK_LOSS(link,
2907 hpd_irq_dpcd_data.raw,
2908 sizeof(hpd_irq_dpcd_data),
2909 "Status: ");
2910
48af9b91
AL		 2911 for (i = 0; i < MAX_PIPES; i++) {
2912 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
832aa63b
PH		 2913 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2914 break;
2915 }
2916
2917 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
2918 return false;
2919
99218d12 2920 previous_link_settings = link->cur_link_settings;
832aa63b 2921
99218d12 2922 perform_link_training_with_retries(&previous_link_settings,
832aa63b
PH		 2923 true, LINK_TRAINING_ATTEMPTS,
2924 pipe_ctx,
2925 pipe_ctx->stream->signal);
2926
ffdaeb1f
PH		 2927 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2928 dc_link_reallocate_mst_payload(link);
48af9b91 2929
4562236b 2930 status = false;
4e18814e
FD		 2931 if (out_link_loss)
2932 *out_link_loss = true;
4562236b
HW		 2933 }
2934
d0778ebf 2935 if (link->type == dc_connection_active_dongle &&
4562236b
HW		 2936 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
2937 != link->dpcd_sink_count)
2938 status = true;
2939
2940 /* reasons for HPD RX:
2941 * 1. Link Loss - ie Re-train the Link
2942 * 2. MST sideband message
2943 * 3. Automated Test - ie. Internal Commit
2944 * 4. CP (copy protection) - (not interesting for DM???)
2945 * 5. DRR
2946 * 6. Downstream Port status changed
2947 * -ie. Detect - this the only one
2948 * which is interesting for DM because
2949 * it must call dc_link_detect.
2950 */
2951 return status;
2952}
2953
2954/*query dpcd for version and mst cap addresses*/
d0778ebf 2955bool is_mst_supported(struct dc_link *link)
4562236b
HW		 2956{
2957 bool mst = false;
2958 enum dc_status st = DC_OK;
2959 union dpcd_rev rev;
2960 union mstm_cap cap;
2961
0b226322
DG		 2962 if (link->preferred_training_settings.mst_enable &&
2963 *link->preferred_training_settings.mst_enable == false) {
2964 return false;
2965 }
2966
4562236b
HW		 2967 rev.raw = 0;
2968 cap.raw = 0;
2969
3a340294 2970 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4562236b
HW		 2971 sizeof(rev));
2972
2973 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2974
3a340294 2975 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4562236b
HW		 2976 &cap.raw, sizeof(cap));
2977 if (st == DC_OK && cap.bits.MST_CAP == 1)
2978 mst = true;
2979 }
2980 return mst;
2981
2982}
2983
d0778ebf 2984bool is_dp_active_dongle(const struct dc_link *link)
4562236b 2985{
a504ad26 2986 return link->dpcd_caps.is_branch_dev;
4562236b
HW		 2987}
2988
6bffebc9
EY		 2989static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
2990{
2991 switch (bpc) {
2992 case DOWN_STREAM_MAX_8BPC:
2993 return 8;
2994 case DOWN_STREAM_MAX_10BPC:
2995 return 10;
2996 case DOWN_STREAM_MAX_12BPC:
2997 return 12;
2998 case DOWN_STREAM_MAX_16BPC:
2999 return 16;
3000 default:
3001 break;
3002 }
3003
3004 return -1;
3005}
3006
ee13cea9
JB		 3007static void read_dp_device_vendor_id(struct dc_link *link)
3008{
3009 struct dp_device_vendor_id dp_id;
3010
3011 /* read IEEE branch device id */
3012 core_link_read_dpcd(
3013 link,
3014 DP_BRANCH_OUI,
3015 (uint8_t *)&dp_id,
3016 sizeof(dp_id));
3017
3018 link->dpcd_caps.branch_dev_id =
3019 (dp_id.ieee_oui[0] << 16) +
3020 (dp_id.ieee_oui[1] << 8) +
3021 dp_id.ieee_oui[2];
3022
3023 memmove(
3024 link->dpcd_caps.branch_dev_name,
3025 dp_id.ieee_device_id,
3026 sizeof(dp_id.ieee_device_id));
3027}
3028
3029
3030
4562236b 3031static void get_active_converter_info(
d0778ebf 3032 uint8_t data, struct dc_link *link)
4562236b
HW		 3033{
3034 union dp_downstream_port_present ds_port = { .byte = data };
dd998291 3035 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
4562236b
HW		 3036
3037 /* decode converter info*/
3038 if (!ds_port.fields.PORT_PRESENT) {
3039 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
d0778ebf 3040 ddc_service_set_dongle_type(link->ddc,
4562236b 3041 link->dpcd_caps.dongle_type);
ac3d76e0 3042 link->dpcd_caps.is_branch_dev = false;
4562236b
HW		 3043 return;
3044 }
3045
a504ad26 3046 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
ac3d76e0
HT		 3047 if (ds_port.fields.PORT_TYPE == DOWNSTREAM_DP) {
3048 link->dpcd_caps.is_branch_dev = false;
3049 }
3050
3051 else {
3052 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3053 }
a504ad26 3054
4562236b
HW		 3055 switch (ds_port.fields.PORT_TYPE) {
3056 case DOWNSTREAM_VGA:
3057 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3058 break;
7a83645a
DZ		 3059 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3060 /* At this point we don't know is it DVI or HDMI or DP++,
4562236b
HW		 3061 * assume DVI.*/
3062 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3063 break;
3064 default:
3065 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3066 break;
3067 }
3068
ac0e562c 3069 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
242b0c8f 3070 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
4562236b
HW		 3071 union dwnstream_port_caps_byte0 *port_caps =
3072 (union dwnstream_port_caps_byte0 *)det_caps;
3a340294 3073 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
4562236b
HW		 3074 det_caps, sizeof(det_caps));
3075
3076 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
7a83645a
DZ		 3077 /*Handle DP case as DONGLE_NONE*/
3078 case DOWN_STREAM_DETAILED_DP:
3079 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3080 break;
4562236b
HW		 3081 case DOWN_STREAM_DETAILED_VGA:
3082 link->dpcd_caps.dongle_type =
3083 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3084 break;
3085 case DOWN_STREAM_DETAILED_DVI:
3086 link->dpcd_caps.dongle_type =
3087 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3088 break;
3089 case DOWN_STREAM_DETAILED_HDMI:
7a83645a
DZ		 3090 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3091 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
4562236b
HW		 3092 link->dpcd_caps.dongle_type =
3093 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3094
03f5c686 3095 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
4562236b
HW		 3096 if (ds_port.fields.DETAILED_CAPS) {
3097
3098 union dwnstream_port_caps_byte3_hdmi
3099 hdmi_caps = {.raw = det_caps[3] };
7d8d90d8 3100 union dwnstream_port_caps_byte2
03f5c686 3101 hdmi_color_caps = {.raw = det_caps[2] };
e5490464
S		 3102 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3103 det_caps[1] * 2500;
4562236b 3104
03f5c686 3105 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
4562236b 3106 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
7a83645a
DZ		 3107 /*YCBCR capability only for HDMI case*/
3108 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3109 == DOWN_STREAM_DETAILED_HDMI) {
3110 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3111 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3112 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3113 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3114 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3115 hdmi_caps.bits.YCrCr422_CONVERSION;
3116 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3117 hdmi_caps.bits.YCrCr420_CONVERSION;
3118 }
03f5c686
CL		 3119
3120 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
6bffebc9
EY		 3121 translate_dpcd_max_bpc(
3122 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
03f5c686 3123
e5490464 3124 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
99b922f9 3125 link->dpcd_caps.dongle_caps.extendedCapValid = true;
4562236b 3126 }
03f5c686 3127
4562236b
HW		 3128 break;
3129 }
3130 }
3131
d0778ebf 3132 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4562236b 3133
4562236b
HW		 3134 {
3135 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3136
3137 core_link_read_dpcd(
3138 link,
3a340294 3139 DP_BRANCH_REVISION_START,
4562236b
HW		 3140 (uint8_t *)&dp_hw_fw_revision,
3141 sizeof(dp_hw_fw_revision));
3142
3143 link->dpcd_caps.branch_hw_revision =
3144 dp_hw_fw_revision.ieee_hw_rev;
4b99affb
A		 3145
3146 memmove(
3147 link->dpcd_caps.branch_fw_revision,
3148 dp_hw_fw_revision.ieee_fw_rev,
3149 sizeof(dp_hw_fw_revision.ieee_fw_rev));
4562236b
HW		 3150 }
3151}
3152
d0778ebf 3153static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4562236b
HW		 3154 int length)
3155{
3156 int retry = 0;
4562236b
HW		 3157
3158 if (!link->dpcd_caps.dpcd_rev.raw) {
3159 do {
3160 dp_receiver_power_ctrl(link, true);
3a340294 3161 core_link_read_dpcd(link, DP_DPCD_REV,
4562236b
HW		 3162 dpcd_data, length);
3163 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3a340294
DA		 3164 DP_DPCD_REV -
3165 DP_DPCD_REV];
4562236b
HW		 3166 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3167 }
3168
4562236b
HW		 3169 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3170 switch (link->dpcd_caps.branch_dev_id) {
df3b7e32 3171 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
4562236b
HW		 3172 * all internal circuits including AUX communication preventing
3173 * reading DPCD table and EDID (spec violation).
3174 * Encoder will skip DP RX power down on disable_output to
3175 * keep receiver powered all the time.*/
df3b7e32
QZ		 3176 case DP_BRANCH_DEVICE_ID_0010FA:
3177 case DP_BRANCH_DEVICE_ID_0080E1:
566b4252 3178 case DP_BRANCH_DEVICE_ID_00E04C:
4562236b
HW		 3179 link->wa_flags.dp_keep_receiver_powered = true;
3180 break;
3181
3182 /* TODO: May need work around for other dongles. */
3183 default:
3184 link->wa_flags.dp_keep_receiver_powered = false;
3185 break;
3186 }
3187 } else
3188 link->wa_flags.dp_keep_receiver_powered = false;
3189}
3190
96577cf8
HW		 3191/* Read additional sink caps defined in source specific DPCD area
3192 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3193 */
3194static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3195{
3196 uint8_t dpcd_data;
3197
3198 if (!link)
3199 return false;
3200
3201 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3202 return false;
3203
3204 link->dpcd_sink_ext_caps.raw = dpcd_data;
3205 return true;
3206}
3207
cdb39798 3208static bool retrieve_link_cap(struct dc_link *link)
4562236b 3209{
61aa7a6f 3210 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3211 * which means size 16 will be good for both of those DPCD register block reads
3212 */
3213 uint8_t dpcd_data[16];
3214 uint8_t lttpr_dpcd_data[6];
4562236b 3215
3c7dd2cb
HT		 3216 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3217 */
3218 uint8_t dpcd_dprx_data = '\0';
8633d96d 3219 uint8_t dpcd_power_state = '\0';
3c7dd2cb 3220
8ca80900 3221 struct dp_device_vendor_id sink_id;
4562236b
HW		 3222 union down_stream_port_count down_strm_port_count;
3223 union edp_configuration_cap edp_config_cap;
3224 union dp_downstream_port_present ds_port = { 0 };
cdb39798 3225 enum dc_status status = DC_ERROR_UNEXPECTED;
3c1a312a
YS		 3226 uint32_t read_dpcd_retry_cnt = 3;
3227 int i;
4b99affb 3228 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
4562236b 3229
8e5100a5 3230 /* Set default timeout to 3.2ms and read LTTPR capabilities */
3231 bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support &&
3232 !link->dc->config.disable_extended_timeout_support;
bad7ab0b 3233
903e859b 3234 link->is_lttpr_mode_transparent = true;
3235
8e5100a5 3236 if (ext_timeout_support) {
61aa7a6f 3237 dc_link_aux_configure_timeout(link->ddc,
3238 LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
8e5100a5 3239 }
3240
4562236b 3241 memset(dpcd_data, '\0', sizeof(dpcd_data));
61aa7a6f 3242 memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
4562236b
HW		 3243 memset(&down_strm_port_count,
3244 '\0', sizeof(union down_stream_port_count));
3245 memset(&edp_config_cap, '\0',
3246 sizeof(union edp_configuration_cap));
3247
8633d96d
AK		 3248 status = core_link_read_dpcd(link, DP_SET_POWER,
3249 &dpcd_power_state, sizeof(dpcd_power_state));
3250
3251 /* Delay 1 ms if AUX CH is in power down state. Based on spec
3252 * section 2.3.1.2, if AUX CH may be powered down due to
3253 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3254 * signal and may need up to 1 ms before being able to reply.
3255 */
3256 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3257 udelay(1000);
3258
3c1a312a
YS		 3259 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3260 status = core_link_read_dpcd(
3261 link,
3262 DP_DPCD_REV,
3263 dpcd_data,
3264 sizeof(dpcd_data));
3265 if (status == DC_OK)
3266 break;
3267 }
cdb39798
YS		 3268
3269 if (status != DC_OK) {
3270 dm_error("%s: Read dpcd data failed.\n", __func__);
3271 return false;
3272 }
4562236b 3273
9bffd080 3274 if (ext_timeout_support) {
61aa7a6f 3275
8e5100a5 3276 status = core_link_read_dpcd(
3277 link,
61aa7a6f 3278 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3279 lttpr_dpcd_data,
3280 sizeof(lttpr_dpcd_data));
3281
3282 link->dpcd_caps.lttpr_caps.revision.raw =
3283 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3284 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3285
3286 link->dpcd_caps.lttpr_caps.max_link_rate =
3287 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3288 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3289
3290 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3291 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3292 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3293
3294 link->dpcd_caps.lttpr_caps.max_lane_count =
3295 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3296 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3297
3298 link->dpcd_caps.lttpr_caps.mode =
3299 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3300 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3301
3302 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3303 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3304 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3305
3306 if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3307 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3308 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3309 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14) {
8e5100a5 3310 link->is_lttpr_mode_transparent = false;
8e5100a5 3311 } else {
61aa7a6f 3312 /*No lttpr reset timeout to its default value*/
3313 link->is_lttpr_mode_transparent = true;
3314 dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
8e5100a5 3315 }
460adc6b 3316
3317 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
8e5100a5 3318 }
3319
4562236b
HW		 3320 {
3321 union training_aux_rd_interval aux_rd_interval;
3322
3323 aux_rd_interval.raw =
3a340294 3324 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
4562236b 3325
3c7dd2cb 3326 link->dpcd_caps.ext_receiver_cap_field_present =
b239b59b 3327 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3c7dd2cb
HT		 3328
3329 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
818832bf
XY		 3330 uint8_t ext_cap_data[16];
3331
3332 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3333 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3334 status = core_link_read_dpcd(
4562236b 3335 link,
3a340294 3336 DP_DP13_DPCD_REV,
818832bf
XY		 3337 ext_cap_data,
3338 sizeof(ext_cap_data));
3339 if (status == DC_OK) {
3340 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3341 break;
3342 }
3343 }
3344 if (status != DC_OK)
3345 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
4562236b
HW		 3346 }
3347 }
3348
3c7dd2cb
HT		 3349 link->dpcd_caps.dpcd_rev.raw =
3350 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3351
3352 if (link->dpcd_caps.dpcd_rev.raw >= 0x14) {
3353 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3354 status = core_link_read_dpcd(
3355 link,
3356 DP_DPRX_FEATURE_ENUMERATION_LIST,
3357 &dpcd_dprx_data,
3358 sizeof(dpcd_dprx_data));
3359 if (status == DC_OK)
3360 break;
3361 }
3362
3363 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3364
3365 if (status != DC_OK)
3366 dm_error("%s: Read DPRX caps data failed.\n", __func__);
3367 }
3368
3369 else {
3370 link->dpcd_caps.dprx_feature.raw = 0;
3371 }
3372
3373
07d6a199
AK		 3374 /* Error condition checking...
3375 * It is impossible for Sink to report Max Lane Count = 0.
3376 * It is possible for Sink to report Max Link Rate = 0, if it is
3377 * an eDP device that is reporting specialized link rates in the
3378 * SUPPORTED_LINK_RATE table.
3379 */
3380 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3381 return false;
3382
3a340294
DA		 3383 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3384 DP_DPCD_REV];
4562236b 3385
ee13cea9
JB		 3386 read_dp_device_vendor_id(link);
3387
4562236b
HW		 3388 get_active_converter_info(ds_port.byte, link);
3389
3390 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3391
98e6436d
AK		 3392 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3393 DP_DPCD_REV];
3394
4562236b
HW		 3395 link->dpcd_caps.allow_invalid_MSA_timing_param =
3396 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3397
3398 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3a340294 3399 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4562236b
HW		 3400
3401 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3a340294 3402 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4562236b 3403
d0778ebf 3404 link->reported_link_cap.lane_count =
4562236b 3405 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
d0778ebf 3406 link->reported_link_cap.link_rate = dpcd_data[
3a340294 3407 DP_MAX_LINK_RATE - DP_DPCD_REV];
d0778ebf 3408 link->reported_link_cap.link_spread =
4562236b
HW		 3409 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3410 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3411
3412 edp_config_cap.raw = dpcd_data[
3a340294 3413 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4562236b
HW		 3414 link->dpcd_caps.panel_mode_edp =
3415 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
9799624a
WL		 3416 link->dpcd_caps.dpcd_display_control_capable =
3417 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4562236b 3418
d0778ebf
HW		 3419 link->test_pattern_enabled = false;
3420 link->compliance_test_state.raw = 0;
4562236b 3421
4562236b
HW		 3422 /* read sink count */
3423 core_link_read_dpcd(link,
3a340294 3424 DP_SINK_COUNT,
4562236b
HW		 3425 &link->dpcd_caps.sink_count.raw,
3426 sizeof(link->dpcd_caps.sink_count.raw));
3427
8ca80900
AK		 3428 /* read sink ieee oui */
3429 core_link_read_dpcd(link,
3430 DP_SINK_OUI,
3431 (uint8_t *)(&sink_id),
3432 sizeof(sink_id));
3433
3434 link->dpcd_caps.sink_dev_id =
3435 (sink_id.ieee_oui[0] << 16) +
3436 (sink_id.ieee_oui[1] << 8) +
3437 (sink_id.ieee_oui[2]);
3438
4b99affb
A		 3439 memmove(
3440 link->dpcd_caps.sink_dev_id_str,
3441 sink_id.ieee_device_id,
3442 sizeof(sink_id.ieee_device_id));
3443
473e3f77
MK		 3444 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3445 {
3446 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3447
3448 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3449 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3450 sizeof(str_mbp_2017))) {
3451 link->reported_link_cap.link_rate = 0x0c;
3452 }
3453 }
3454
4b99affb
A		 3455 core_link_read_dpcd(
3456 link,
3457 DP_SINK_HW_REVISION_START,
3458 (uint8_t *)&dp_hw_fw_revision,
3459 sizeof(dp_hw_fw_revision));
3460
3461 link->dpcd_caps.sink_hw_revision =
3462 dp_hw_fw_revision.ieee_hw_rev;
3463
3464 memmove(
3465 link->dpcd_caps.sink_fw_revision,
3466 dp_hw_fw_revision.ieee_fw_rev,
3467 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3468
39a4eb85
WL		 3469 memset(&link->dpcd_caps.dsc_caps, '\0',
3470 sizeof(link->dpcd_caps.dsc_caps));
97bda032
HW		 3471 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3472 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3473 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
97bda032
HW		 3474 status = core_link_read_dpcd(
3475 link,
3476 DP_FEC_CAPABILITY,
3477 &link->dpcd_caps.fec_cap.raw,
3478 sizeof(link->dpcd_caps.fec_cap.raw));
39a4eb85
WL		 3479 status = core_link_read_dpcd(
3480 link,
3481 DP_DSC_SUPPORT,
3482 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3483 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3484 status = core_link_read_dpcd(
3485 link,
3486 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3487 link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
3488 sizeof(link->dpcd_caps.dsc_caps.dsc_ext_caps.raw));
97bda032 3489 }
6fbefb84 3490
96577cf8
HW		 3491 if (!dpcd_read_sink_ext_caps(link))
3492 link->dpcd_sink_ext_caps.raw = 0;
3493
4562236b
HW		 3494 /* Connectivity log: detection */
3495 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
cdb39798
YS		 3496
3497 return true;
4562236b
HW		 3498}
3499
8547058b
LH		 3500bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3501{
3502 uint8_t dpcd_data[16];
3503 uint32_t read_dpcd_retry_cnt = 3;
3504 enum dc_status status = DC_ERROR_UNEXPECTED;
3505 union dp_downstream_port_present ds_port = { 0 };
3506 union down_stream_port_count down_strm_port_count;
3507 union edp_configuration_cap edp_config_cap;
3508
3509 int i;
3510
3511 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3512 status = core_link_read_dpcd(
3513 link,
3514 DP_DPCD_REV,
3515 dpcd_data,
3516 sizeof(dpcd_data));
3517 if (status == DC_OK)
3518 break;
3519 }
3520
3521 link->dpcd_caps.dpcd_rev.raw =
3522 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3523
3524 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3525 return false;
3526
3527 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3528 DP_DPCD_REV];
3529
3530 get_active_converter_info(ds_port.byte, link);
3531
3532 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3533 DP_DPCD_REV];
3534
3535 link->dpcd_caps.allow_invalid_MSA_timing_param =
3536 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3537
3538 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3539 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3540
3541 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3542 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3543
3544 link->reported_link_cap.lane_count =
3545 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3546 link->reported_link_cap.link_rate = dpcd_data[
3547 DP_MAX_LINK_RATE - DP_DPCD_REV];
3548 link->reported_link_cap.link_spread =
3549 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3550 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3551
3552 edp_config_cap.raw = dpcd_data[
3553 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3554 link->dpcd_caps.panel_mode_edp =
3555 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3556 link->dpcd_caps.dpcd_display_control_capable =
3557 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3558
3559 return true;
3560}
3561
cdb39798 3562bool detect_dp_sink_caps(struct dc_link *link)
4562236b 3563{
cdb39798 3564 return retrieve_link_cap(link);
4562236b
HW		 3565
3566 /* dc init_hw has power encoder using default
3567 * signal for connector. For native DP, no
3568 * need to power up encoder again. If not native
3569 * DP, hw_init may need check signal or power up
3570 * encoder here.
3571 */
4562236b
HW		 3572 /* TODO save sink caps in link->sink */
3573}
3574
b03a599b
DL		 3575enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3576{
3577 enum dc_link_rate link_rate;
3578 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3579 switch (link_rate_in_khz) {
3580 case 1620000:
3581 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
3582 break;
3583 case 2160000:
3584 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
3585 break;
3586 case 2430000:
3587 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
3588 break;
3589 case 2700000:
3590 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
3591 break;
3592 case 3240000:
3593 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
3594 break;
3595 case 4320000:
3596 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
3597 break;
3598 case 5400000:
3599 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
3600 break;
3601 case 8100000:
3602 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
3603 break;
3604 default:
3605 link_rate = LINK_RATE_UNKNOWN;
3606 break;
3607 }
3608 return link_rate;
3609}
3610
4654a2f7
RL		 3611void detect_edp_sink_caps(struct dc_link *link)
3612{
8628d02f 3613 uint8_t supported_link_rates[16];
b03a599b
DL		 3614 uint32_t entry;
3615 uint32_t link_rate_in_khz;
3616 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
48231fd5 3617
b03a599b 3618 retrieve_link_cap(link);
8628d02f
JP		 3619 link->dpcd_caps.edp_supported_link_rates_count = 0;
3620 memset(supported_link_rates, 0, sizeof(supported_link_rates));
48231fd5 3621
8628d02f 3622 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
53c81fc7
WC		 3623 (link->dc->config.optimize_edp_link_rate ||
3624 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
b03a599b
DL		 3625 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3626 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
3627 supported_link_rates, sizeof(supported_link_rates));
3628
b03a599b
DL		 3629 for (entry = 0; entry < 16; entry += 2) {
3630 // DPCD register reports per-lane link rate = 16-bit link rate capability
8628d02f 3631 // value X 200 kHz. Need multiplier to find link rate in kHz.
b03a599b
DL		 3632 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3633 supported_link_rates[entry]) * 200;
3634
3635 if (link_rate_in_khz != 0) {
3636 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
8628d02f
JP		 3637 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
3638 link->dpcd_caps.edp_supported_link_rates_count++;
53c81fc7
WC		 3639
3640 if (link->reported_link_cap.link_rate < link_rate)
3641 link->reported_link_cap.link_rate = link_rate;
b03a599b
DL		 3642 }
3643 }
3644 }
4654a2f7 3645 link->verified_link_cap = link->reported_link_cap;
96577cf8
HW		 3646
3647 dc_link_set_default_brightness_aux(link);
4654a2f7
RL		 3648}
3649
4562236b
HW		 3650void dc_link_dp_enable_hpd(const struct dc_link *link)
3651{
d0778ebf 3652 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 3653
3654 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3655 encoder->funcs->enable_hpd(encoder);
3656}
3657
3658void dc_link_dp_disable_hpd(const struct dc_link *link)
3659{
d0778ebf 3660 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 3661
3662 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3663 encoder->funcs->disable_hpd(encoder);
3664}
3665
3666static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
3667{
0e19401f
TC		 3668 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
3669 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
3670 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4562236b
HW		 3671 return true;
3672 else
3673 return false;
3674}
3675
d0778ebf 3676static void set_crtc_test_pattern(struct dc_link *link,
4562236b 3677 struct pipe_ctx *pipe_ctx,
2057b7e1
WL		 3678 enum dp_test_pattern test_pattern,
3679 enum dp_test_pattern_color_space test_pattern_color_space)
4562236b
HW		 3680{
3681 enum controller_dp_test_pattern controller_test_pattern;
3682 enum dc_color_depth color_depth = pipe_ctx->
4fa086b9 3683 stream->timing.display_color_depth;
4562236b 3684 struct bit_depth_reduction_params params;
661a8cd9 3685 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
6fbefb84
HW		 3686 int width = pipe_ctx->stream->timing.h_addressable +
3687 pipe_ctx->stream->timing.h_border_left +
3688 pipe_ctx->stream->timing.h_border_right;
3689 int height = pipe_ctx->stream->timing.v_addressable +
3690 pipe_ctx->stream->timing.v_border_bottom +
3691 pipe_ctx->stream->timing.v_border_top;
4562236b
HW		 3692
3693 memset(&params, 0, sizeof(params));
3694
3695 switch (test_pattern) {
3696 case DP_TEST_PATTERN_COLOR_SQUARES:
3697 controller_test_pattern =
3698 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
3699 break;
3700 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3701 controller_test_pattern =
3702 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
3703 break;
3704 case DP_TEST_PATTERN_VERTICAL_BARS:
3705 controller_test_pattern =
3706 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
3707 break;
3708 case DP_TEST_PATTERN_HORIZONTAL_BARS:
3709 controller_test_pattern =
3710 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
3711 break;
3712 case DP_TEST_PATTERN_COLOR_RAMP:
3713 controller_test_pattern =
3714 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
3715 break;
3716 default:
3717 controller_test_pattern =
3718 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
3719 break;
3720 }
3721
3722 switch (test_pattern) {
3723 case DP_TEST_PATTERN_COLOR_SQUARES:
3724 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3725 case DP_TEST_PATTERN_VERTICAL_BARS:
3726 case DP_TEST_PATTERN_HORIZONTAL_BARS:
3727 case DP_TEST_PATTERN_COLOR_RAMP:
3728 {
3729 /* disable bit depth reduction */
3730 pipe_ctx->stream->bit_depth_params = params;
661a8cd9 3731 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
7f93c1de
CL		 3732 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3733 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b 3734 controller_test_pattern, color_depth);
6fbefb84 3735 else if (opp->funcs->opp_set_disp_pattern_generator) {
b1f6d01c 3736 struct pipe_ctx *odm_pipe;
2057b7e1 3737 enum controller_dp_color_space controller_color_space;
b1f6d01c 3738 int opp_cnt = 1;
10b4e64e
WL		 3739 int offset = 0;
3740 int dpg_width = width;
6fbefb84 3741
2057b7e1
WL		 3742 switch (test_pattern_color_space) {
3743 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
3744 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
3745 break;
3746 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
3747 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
3748 break;
3749 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
3750 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
3751 break;
3752 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
3753 default:
3754 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
3755 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
3756 ASSERT(0);
3757 break;
3758 }
3759
b1f6d01c
DL		 3760 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3761 opp_cnt++;
10b4e64e
WL		 3762 dpg_width = width / opp_cnt;
3763 offset = dpg_width;
6fbefb84 3764
10b4e64e
WL		 3765 opp->funcs->opp_set_disp_pattern_generator(opp,
3766 controller_test_pattern,
3767 controller_color_space,
3768 color_depth,
3769 NULL,
3770 dpg_width,
3771 height,
3772 0);
b1f6d01c
DL		 3773
3774 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3775 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
b1f6d01c
DL		 3776 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
3777 odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
6fbefb84 3778 controller_test_pattern,
2057b7e1 3779 controller_color_space,
6fbefb84
HW		 3780 color_depth,
3781 NULL,
10b4e64e
WL		 3782 dpg_width,
3783 height,
3784 offset);
3785 offset += offset;
6fbefb84 3786 }
6fbefb84 3787 }
4562236b
HW		 3788 }
3789 break;
3790 case DP_TEST_PATTERN_VIDEO_MODE:
3791 {
3792 /* restore bitdepth reduction */
661a8cd9 3793 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4562236b 3794 pipe_ctx->stream->bit_depth_params = params;
661a8cd9 3795 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
7f93c1de
CL		 3796 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3797 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 3798 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3799 color_depth);
6fbefb84 3800 else if (opp->funcs->opp_set_disp_pattern_generator) {
b1f6d01c
DL		 3801 struct pipe_ctx *odm_pipe;
3802 int opp_cnt = 1;
10b4e64e 3803 int dpg_width = width;
b1f6d01c
DL		 3804
3805 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3806 opp_cnt++;
6fbefb84 3807
10b4e64e 3808 dpg_width = width / opp_cnt;
b1f6d01c
DL		 3809 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3810 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
6fbefb84 3811
b1f6d01c
DL		 3812 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
3813 odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
6fbefb84 3814 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2057b7e1 3815 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
6fbefb84
HW		 3816 color_depth,
3817 NULL,
10b4e64e
WL		 3818 dpg_width,
3819 height,
3820 0);
6fbefb84
HW		 3821 }
3822 opp->funcs->opp_set_disp_pattern_generator(opp,
3823 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2057b7e1 3824 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
6fbefb84
HW		 3825 color_depth,
3826 NULL,
10b4e64e
WL		 3827 dpg_width,
3828 height,
3829 0);
6fbefb84 3830 }
4562236b
HW		 3831 }
3832 break;
3833
3834 default:
3835 break;
3836 }
3837}
3838
3839bool dc_link_dp_set_test_pattern(
d0778ebf 3840 struct dc_link *link,
4562236b 3841 enum dp_test_pattern test_pattern,
2057b7e1 3842 enum dp_test_pattern_color_space test_pattern_color_space,
4562236b
HW		 3843 const struct link_training_settings *p_link_settings,
3844 const unsigned char *p_custom_pattern,
3845 unsigned int cust_pattern_size)
3846{
608ac7bb 3847 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
0a8f43ff 3848 struct pipe_ctx *pipe_ctx = &pipes[0];
4562236b
HW		 3849 unsigned int lane;
3850 unsigned int i;
3851 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
3852 union dpcd_training_pattern training_pattern;
4562236b
HW		 3853 enum dpcd_phy_test_patterns pattern;
3854
3855 memset(&training_pattern, 0, sizeof(training_pattern));
4562236b
HW		 3856
3857 for (i = 0; i < MAX_PIPES; i++) {
24d01c9b 3858 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
0a8f43ff 3859 pipe_ctx = &pipes[i];
4562236b
HW		 3860 break;
3861 }
3862 }
3863
3864 /* Reset CRTC Test Pattern if it is currently running and request
3865 * is VideoMode Reset DP Phy Test Pattern if it is currently running
3866 * and request is VideoMode
3867 */
d0778ebf 3868 if (link->test_pattern_enabled && test_pattern ==
4562236b
HW		 3869 DP_TEST_PATTERN_VIDEO_MODE) {
3870 /* Set CRTC Test Pattern */
2057b7e1 3871 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
d0778ebf 3872 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 3873 (uint8_t *)p_custom_pattern,
3874 (uint32_t)cust_pattern_size);
3875
3876 /* Unblank Stream */
d0778ebf 3877 link->dc->hwss.unblank_stream(
0a8f43ff 3878 pipe_ctx,
d0778ebf 3879 &link->verified_link_cap);
4562236b
HW		 3880 /* TODO:m_pHwss->MuteAudioEndpoint
3881 * (pPathMode->pDisplayPath, false);
3882 */
3883
3884 /* Reset Test Pattern state */
d0778ebf 3885 link->test_pattern_enabled = false;
4562236b
HW		 3886
3887 return true;
3888 }
3889
3890 /* Check for PHY Test Patterns */
3891 if (is_dp_phy_pattern(test_pattern)) {
3892 /* Set DPCD Lane Settings before running test pattern */
3893 if (p_link_settings != NULL) {
64c12b73 3894 dp_set_hw_lane_settings(link, p_link_settings, DPRX);
3895 dpcd_set_lane_settings(link, p_link_settings, DPRX);
4562236b
HW		 3896 }
3897
3898 /* Blank stream if running test pattern */
3899 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3900 /*TODO:
3901 * m_pHwss->
3902 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
3903 */
3904 /* Blank stream */
8e9c4c8c 3905 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4562236b
HW		 3906 }
3907
d0778ebf 3908 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 3909 (uint8_t *)p_custom_pattern,
3910 (uint32_t)cust_pattern_size);
3911
3912 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3913 /* Set Test Pattern state */
d0778ebf 3914 link->test_pattern_enabled = true;
4562236b 3915 if (p_link_settings != NULL)
d0778ebf 3916 dpcd_set_link_settings(link,
4562236b
HW		 3917 p_link_settings);
3918 }
3919
3920 switch (test_pattern) {
3921 case DP_TEST_PATTERN_VIDEO_MODE:
3922 pattern = PHY_TEST_PATTERN_NONE;
0e19401f 3923 break;
4562236b
HW		 3924 case DP_TEST_PATTERN_D102:
3925 pattern = PHY_TEST_PATTERN_D10_2;
0e19401f 3926 break;
4562236b
HW		 3927 case DP_TEST_PATTERN_SYMBOL_ERROR:
3928 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 3929 break;
4562236b
HW		 3930 case DP_TEST_PATTERN_PRBS7:
3931 pattern = PHY_TEST_PATTERN_PRBS7;
0e19401f 3932 break;
4562236b
HW		 3933 case DP_TEST_PATTERN_80BIT_CUSTOM:
3934 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 3935 break;
3936 case DP_TEST_PATTERN_CP2520_1:
3937 pattern = PHY_TEST_PATTERN_CP2520_1;
3938 break;
3939 case DP_TEST_PATTERN_CP2520_2:
3940 pattern = PHY_TEST_PATTERN_CP2520_2;
3941 break;
3942 case DP_TEST_PATTERN_CP2520_3:
3943 pattern = PHY_TEST_PATTERN_CP2520_3;
3944 break;
4562236b
HW		 3945 default:
3946 return false;
3947 }
3948
3949 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
3950 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
3951 return false;
3952
d0778ebf 3953 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 3954 /* tell receiver that we are sending qualification
3955 * pattern DP 1.2 or later - DP receiver's link quality
3956 * pattern is set using DPCD LINK_QUAL_LANEx_SET
3957 * register (0x10B~0x10E)\
3958 */
3959 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
3960 link_qual_pattern[lane] =
3961 (unsigned char)(pattern);
3962
d0778ebf 3963 core_link_write_dpcd(link,
3a340294 3964 DP_LINK_QUAL_LANE0_SET,
4562236b
HW		 3965 link_qual_pattern,
3966 sizeof(link_qual_pattern));
d0778ebf
HW		 3967 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
3968 link->dpcd_caps.dpcd_rev.raw == 0) {
4562236b
HW		 3969 /* tell receiver that we are sending qualification
3970 * pattern DP 1.1a or earlier - DP receiver's link
3971 * quality pattern is set using
3972 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
3973 * register (0x102). We will use v_1.3 when we are
3974 * setting test pattern for DP 1.1.
3975 */
d0778ebf
HW		 3976 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
3977 &training_pattern.raw,
3978 sizeof(training_pattern));
4562236b 3979 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
d0778ebf
HW		 3980 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
3981 &training_pattern.raw,
3982 sizeof(training_pattern));
4562236b
HW		 3983 }
3984 } else {
43563bc2 3985 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
43563bc2
WL		 3986
3987 switch (test_pattern_color_space) {
3988 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
3989 color_space = COLOR_SPACE_SRGB;
3990 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
3991 color_space = COLOR_SPACE_SRGB_LIMITED;
3992 break;
3993
3994 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
3995 color_space = COLOR_SPACE_YCBCR601;
3996 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
3997 color_space = COLOR_SPACE_YCBCR601_LIMITED;
3998 break;
3999 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4000 color_space = COLOR_SPACE_YCBCR709;
4001 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4002 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4003 break;
4004 default:
4005 break;
4006 }
e8f9ecf2
WL		 4007
4008 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable)
4009 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4010 pipe_ctx->stream_res.tg);
4011 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
43563bc2
WL		 4012 /* update MSA to requested color space */
4013 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4014 &pipe_ctx->stream->timing,
23bc5f34
WL		 4015 color_space,
4016 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4017 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
43563bc2 4018
e8f9ecf2
WL		 4019 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4020 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4021 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4022 else
4023 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4024 resource_build_info_frame(pipe_ctx);
4025 link->dc->hwss.update_info_frame(pipe_ctx);
4026 }
4027
43563bc2 4028 /* CRTC Patterns */
2057b7e1 4029 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
e8f9ecf2
WL		 4030 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4031 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4032 CRTC_STATE_VACTIVE);
4033 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4034 CRTC_STATE_VBLANK);
4035 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4036 CRTC_STATE_VACTIVE);
4037 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable)
4038 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4039 pipe_ctx->stream_res.tg);
4562236b 4040 /* Set Test Pattern state */
d0778ebf 4041 link->test_pattern_enabled = true;
4562236b
HW		 4042 }
4043
4044 return true;
4045}
07c84c7a 4046
d0778ebf 4047void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
07c84c7a
DW		 4048{
4049 unsigned char mstmCntl;
4050
4051 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4052 if (enable)
4053 mstmCntl |= DP_MST_EN;
4054 else
4055 mstmCntl &= (~DP_MST_EN);
4056
4057 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4058}
6fbefb84 4059
0b226322
DG		 4060void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4061{
4062 union dpcd_edp_config edp_config_set;
4063 bool panel_mode_edp = false;
4064
4065 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4066
4067 if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4068
4069 switch (panel_mode) {
4070 case DP_PANEL_MODE_EDP:
4071 case DP_PANEL_MODE_SPECIAL:
4072 panel_mode_edp = true;
4073 break;
4074
4075 default:
4076 break;
4077 }
4078
4079 /*set edp panel mode in receiver*/
4080 core_link_read_dpcd(
4081 link,
4082 DP_EDP_CONFIGURATION_SET,
4083 &edp_config_set.raw,
4084 sizeof(edp_config_set.raw));
4085
4086 if (edp_config_set.bits.PANEL_MODE_EDP
4087 != panel_mode_edp) {
4088 enum ddc_result result = DDC_RESULT_UNKNOWN;
4089
4090 edp_config_set.bits.PANEL_MODE_EDP =
4091 panel_mode_edp;
4092 result = core_link_write_dpcd(
4093 link,
4094 DP_EDP_CONFIGURATION_SET,
4095 &edp_config_set.raw,
4096 sizeof(edp_config_set.raw));
4097
4098 ASSERT(result == DDC_RESULT_SUCESSFULL);
4099 }
4100 }
4101 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4102 "eDP panel mode enabled: %d \n",
4103 link->link_index,
4104 link->dpcd_caps.panel_mode_edp,
4105 panel_mode_edp);
4106}
4107
4108enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4109{
4110 /* We need to explicitly check that connector
4111 * is not DP. Some Travis_VGA get reported
4112 * by video bios as DP.
4113 */
4114 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4115
4116 switch (link->dpcd_caps.branch_dev_id) {
df3b7e32
QZ		 4117 case DP_BRANCH_DEVICE_ID_0022B9:
4118 /* alternate scrambler reset is required for Travis
4119 * for the case when external chip does not
4120 * provide sink device id, alternate scrambler
4121 * scheme will be overriden later by querying
4122 * Encoder features
4123 */
0b226322
DG		 4124 if (strncmp(
4125 link->dpcd_caps.branch_dev_name,
4126 DP_VGA_LVDS_CONVERTER_ID_2,
4127 sizeof(
4128 link->dpcd_caps.
4129 branch_dev_name)) == 0) {
4130 return DP_PANEL_MODE_SPECIAL;
4131 }
4132 break;
df3b7e32
QZ		 4133 case DP_BRANCH_DEVICE_ID_00001A:
4134 /* alternate scrambler reset is required for Travis
4135 * for the case when external chip does not provide
4136 * sink device id, alternate scrambler scheme will
4137 * be overriden later by querying Encoder feature
4138 */
0b226322
DG		 4139 if (strncmp(link->dpcd_caps.branch_dev_name,
4140 DP_VGA_LVDS_CONVERTER_ID_3,
4141 sizeof(
4142 link->dpcd_caps.
4143 branch_dev_name)) == 0) {
4144 return DP_PANEL_MODE_SPECIAL;
4145 }
4146 break;
4147 default:
4148 break;
4149 }
4150 }
4151
4152 if (link->dpcd_caps.panel_mode_edp) {
4153 return DP_PANEL_MODE_EDP;
4154 }
4155
4156 return DP_PANEL_MODE_DEFAULT;
4157}
4158
97bda032
HW		 4159void dp_set_fec_ready(struct dc_link *link, bool ready)
4160{
4161 /* FEC has to be "set ready" before the link training.
4162 * The policy is to always train with FEC
4163 * if the sink supports it and leave it enabled on link.
4164 * If FEC is not supported, disable it.
4165 */
4166 struct link_encoder *link_enc = link->link_enc;
4167 uint8_t fec_config = 0;
4168
e6b11b43 4169 if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
97bda032
HW		 4170 return;
4171
4172 if (link_enc->funcs->fec_set_ready &&
4173 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
008a4016 4174 if (ready) {
97bda032
HW		 4175 fec_config = 1;
4176 if (core_link_write_dpcd(link,
4177 DP_FEC_CONFIGURATION,
4178 &fec_config,
4179 sizeof(fec_config)) == DC_OK) {
4180 link_enc->funcs->fec_set_ready(link_enc, true);
4181 link->fec_state = dc_link_fec_ready;
4182 } else {
d68a7454
NC		 4183 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4184 link->fec_state = dc_link_fec_not_ready;
97bda032
HW		 4185 dm_error("dpcd write failed to set fec_ready");
4186 }
008a4016 4187 } else if (link->fec_state == dc_link_fec_ready) {
97bda032
HW		 4188 fec_config = 0;
4189 core_link_write_dpcd(link,
4190 DP_FEC_CONFIGURATION,
4191 &fec_config,
4192 sizeof(fec_config));
4193 link->link_enc->funcs->fec_set_ready(
4194 link->link_enc, false);
4195 link->fec_state = dc_link_fec_not_ready;
4196 }
4197 }
4198}
4199
4200void dp_set_fec_enable(struct dc_link *link, bool enable)
4201{
4202 struct link_encoder *link_enc = link->link_enc;
4203
e6b11b43 4204 if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
97bda032
HW		 4205 return;
4206
4207 if (link_enc->funcs->fec_set_enable &&
4208 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4209 if (link->fec_state == dc_link_fec_ready && enable) {
fa11d3c9
LHM		 4210 /* Accord to DP spec, FEC enable sequence can first
4211 * be transmitted anytime after 1000 LL codes have
4212 * been transmitted on the link after link training
4213 * completion. Using 1 lane RBR should have the maximum
4214 * time for transmitting 1000 LL codes which is 6.173 us.
4215 * So use 7 microseconds delay instead.
4216 */
4217 udelay(7);
97bda032
HW		 4218 link_enc->funcs->fec_set_enable(link_enc, true);
4219 link->fec_state = dc_link_fec_enabled;
4220 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4221 link_enc->funcs->fec_set_enable(link_enc, false);
4222 link->fec_state = dc_link_fec_ready;
4223 }
4224 }
4225}
6fbefb84 4226
96577cf8
HW		 4227void dpcd_set_source_specific_data(struct dc_link *link)
4228{
96577cf8
HW		 4229 const uint32_t post_oui_delay = 30; // 30ms
4230
0136684f
CH		 4231 if (!link->dc->vendor_signature.is_valid) {
4232 struct dpcd_amd_signature amd_signature;
4233 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4234 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4235 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4236 amd_signature.device_id_byte1 =
4237 (uint8_t)(link->ctx->asic_id.chip_id);
4238 amd_signature.device_id_byte2 =
4239 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4240 memset(&amd_signature.zero, 0, 4);
4241 amd_signature.dce_version =
4242 (uint8_t)(link->ctx->dce_version);
4243 amd_signature.dal_version_byte1 = 0x0; // needed? where to get?
4244 amd_signature.dal_version_byte2 = 0x0; // needed? where to get?
4245
4246 core_link_write_dpcd(link, DP_SOURCE_OUI,
4247 (uint8_t *)(&amd_signature),
4248 sizeof(amd_signature));
4249
4250 } else {
4251 core_link_write_dpcd(link, DP_SOURCE_OUI,
4252 link->dc->vendor_signature.data.raw,
4253 sizeof(link->dc->vendor_signature.data.raw));
4254 }
96577cf8
HW		 4255
4256 // Sink may need to configure internals based on vendor, so allow some
4257 // time before proceeding with possibly vendor specific transactions
4258 msleep(post_oui_delay);
4259}
4260
4261bool dc_link_set_backlight_level_nits(struct dc_link *link,
4262 bool isHDR,
4263 uint32_t backlight_millinits,
4264 uint32_t transition_time_in_ms)
4265{
4266 struct dpcd_source_backlight_set dpcd_backlight_set;
4267 uint8_t backlight_control = isHDR ? 1 : 0;
4268
4269 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4270 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4271 return false;
4272
4273 // OLEDs have no PWM, they can only use AUX
4274 if (link->dpcd_sink_ext_caps.bits.oled == 1)
4275 backlight_control = 1;
4276
4277 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4278 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4279
4280
4281 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4282 (uint8_t *)(&dpcd_backlight_set),
4283 sizeof(dpcd_backlight_set)) != DC_OK)
4284 return false;
4285
4286 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4287 &backlight_control, 1) != DC_OK)
4288 return false;
4289
4290 return true;
4291}
4292
4293bool dc_link_get_backlight_level_nits(struct dc_link *link,
4294 uint32_t *backlight_millinits_avg,
4295 uint32_t *backlight_millinits_peak)
4296{
4297 union dpcd_source_backlight_get dpcd_backlight_get;
4298
4299 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4300
4301 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4302 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4303 return false;
4304
4305 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4306 dpcd_backlight_get.raw,
4307 sizeof(union dpcd_source_backlight_get)))
4308 return false;
4309
4310 *backlight_millinits_avg =
4311 dpcd_backlight_get.bytes.backlight_millinits_avg;
4312 *backlight_millinits_peak =
4313 dpcd_backlight_get.bytes.backlight_millinits_peak;
4314
4315 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4316 if (*backlight_millinits_avg == 0 ||
4317 *backlight_millinits_avg > *backlight_millinits_peak)
4318 return false;
4319
4320 return true;
4321}
4322
4323bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4324{
4325 uint8_t backlight_enable = enable ? 1 : 0;
4326
4327 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4328 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4329 return false;
4330
4331 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4332 &backlight_enable, 1) != DC_OK)
4333 return false;
4334
4335 return true;
4336}
4337
4338// we read default from 0x320 because we expect BIOS wrote it there
4339// regular get_backlight_nit reads from panel set at 0x326
4340bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4341{
4342 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4343 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4344 return false;
4345
4346 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4347 (uint8_t *) backlight_millinits,
4348 sizeof(uint32_t)))
4349 return false;
4350
4351 return true;
4352}
4353
4354bool dc_link_set_default_brightness_aux(struct dc_link *link)
4355{
4356 uint32_t default_backlight;
4357
4358 if (link &&
4359 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4360 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4361 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4362 default_backlight = 150000;
4363 // if < 5 nits or > 5000, it might be wrong readback
4364 if (default_backlight < 5000 || default_backlight > 5000000)
4365 default_backlight = 150000; //
4366
4367 return dc_link_set_backlight_level_nits(link, true,
4368 default_backlight, 0);
4369 }
4370 return false;
4371}
Linux 6.x block layer and io_uring tree(s)