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drm/amd/display: Don't share clk source between DP and HDMI
[linux-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
CommitLineData
4562236b
HW		 1/* Copyright 2015 Advanced Micro Devices, Inc. */
2#include "dm_services.h"
3#include "dc.h"
4#include "dc_link_dp.h"
5#include "dm_helpers.h"
7f93c1de 6#include "opp.h"
4562236b
HW		 7
8#include "inc/core_types.h"
9#include "link_hwss.h"
10#include "dc_link_ddc.h"
11#include "core_status.h"
12#include "dpcd_defs.h"
13
529cad0f 14#include "resource.h"
1296423b
BL		 15#define DC_LOGGER \
16 link->ctx->logger
4562236b
HW		 17
18/* maximum pre emphasis level allowed for each voltage swing level*/
19static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
20 PRE_EMPHASIS_LEVEL3,
21 PRE_EMPHASIS_LEVEL2,
22 PRE_EMPHASIS_LEVEL1,
23 PRE_EMPHASIS_DISABLED };
24
25enum {
26 POST_LT_ADJ_REQ_LIMIT = 6,
27 POST_LT_ADJ_REQ_TIMEOUT = 200
28};
29
30enum {
31 LINK_TRAINING_MAX_RETRY_COUNT = 5,
32 /* to avoid infinite loop where-in the receiver
33 * switches between different VS
34 */
35 LINK_TRAINING_MAX_CR_RETRY = 100
36};
37
04e21292
DA		 38static bool decide_fallback_link_setting(
39 struct dc_link_settings initial_link_settings,
40 struct dc_link_settings *current_link_setting,
41 enum link_training_result training_result);
9a6a8075 42static struct dc_link_settings get_common_supported_link_settings(
04e21292
DA		 43 struct dc_link_settings link_setting_a,
44 struct dc_link_settings link_setting_b);
45
4562236b 46static void wait_for_training_aux_rd_interval(
d0778ebf 47 struct dc_link *link,
4562236b
HW		 48 uint32_t default_wait_in_micro_secs)
49{
50 union training_aux_rd_interval training_rd_interval;
51
52 /* overwrite the delay if rev > 1.1*/
53 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
54 /* DP 1.2 or later - retrieve delay through
55 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
56 core_link_read_dpcd(
57 link,
3a340294 58 DP_TRAINING_AUX_RD_INTERVAL,
4562236b
HW		 59 (uint8_t *)&training_rd_interval,
60 sizeof(training_rd_interval));
61
62 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
63 default_wait_in_micro_secs =
64 training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
65 }
66
67 udelay(default_wait_in_micro_secs);
68
1296423b 69 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
4562236b
HW		 70 __func__,
71 default_wait_in_micro_secs);
72}
73
74static void dpcd_set_training_pattern(
d0778ebf 75 struct dc_link *link,
4562236b
HW		 76 union dpcd_training_pattern dpcd_pattern)
77{
78 core_link_write_dpcd(
79 link,
3a340294 80 DP_TRAINING_PATTERN_SET,
4562236b
HW		 81 &dpcd_pattern.raw,
82 1);
83
1296423b 84 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
4562236b 85 __func__,
3a340294 86 DP_TRAINING_PATTERN_SET,
4562236b
HW		 87 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
88}
89
90static void dpcd_set_link_settings(
d0778ebf 91 struct dc_link *link,
4562236b
HW		 92 const struct link_training_settings *lt_settings)
93{
94 uint8_t rate = (uint8_t)
95 (lt_settings->link_settings.link_rate);
96
9a6a8075
HW		 97 union down_spread_ctrl downspread = { {0} };
98 union lane_count_set lane_count_set = { {0} };
4562236b
HW		 99 uint8_t link_set_buffer[2];
100
101 downspread.raw = (uint8_t)
102 (lt_settings->link_settings.link_spread);
103
104 lane_count_set.bits.LANE_COUNT_SET =
105 lt_settings->link_settings.lane_count;
106
107 lane_count_set.bits.ENHANCED_FRAMING = 1;
108
109 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
110 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
111
112 link_set_buffer[0] = rate;
113 link_set_buffer[1] = lane_count_set.raw;
114
3a340294 115 core_link_write_dpcd(link, DP_LINK_BW_SET,
4562236b 116 link_set_buffer, 2);
3a340294 117 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
4562236b
HW		 118 &downspread.raw, sizeof(downspread));
119
1296423b 120 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
4562236b 121 __func__,
3a340294 122 DP_LINK_BW_SET,
4562236b 123 lt_settings->link_settings.link_rate,
3a340294 124 DP_LANE_COUNT_SET,
4562236b 125 lt_settings->link_settings.lane_count,
3a340294 126 DP_DOWNSPREAD_CTRL,
4562236b
HW		 127 lt_settings->link_settings.link_spread);
128
129}
130
131static enum dpcd_training_patterns
132 hw_training_pattern_to_dpcd_training_pattern(
d0778ebf 133 struct dc_link *link,
4562236b
HW		 134 enum hw_dp_training_pattern pattern)
135{
136 enum dpcd_training_patterns dpcd_tr_pattern =
137 DPCD_TRAINING_PATTERN_VIDEOIDLE;
138
139 switch (pattern) {
140 case HW_DP_TRAINING_PATTERN_1:
141 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
142 break;
143 case HW_DP_TRAINING_PATTERN_2:
144 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
145 break;
146 case HW_DP_TRAINING_PATTERN_3:
147 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
148 break;
149 case HW_DP_TRAINING_PATTERN_4:
150 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
151 break;
152 default:
153 ASSERT(0);
1296423b 154 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
4562236b
HW		 155 __func__, pattern);
156 break;
157 }
158
159 return dpcd_tr_pattern;
160
161}
162
163static void dpcd_set_lt_pattern_and_lane_settings(
d0778ebf 164 struct dc_link *link,
4562236b
HW		 165 const struct link_training_settings *lt_settings,
166 enum hw_dp_training_pattern pattern)
167{
9a6a8075 168 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
4562236b 169 const uint32_t dpcd_base_lt_offset =
3a340294 170 DP_TRAINING_PATTERN_SET;
4562236b 171 uint8_t dpcd_lt_buffer[5] = {0};
9a6a8075 172 union dpcd_training_pattern dpcd_pattern = { {0} };
4562236b
HW		 173 uint32_t lane;
174 uint32_t size_in_bytes;
175 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
176
177 /*****************************************************************
178 * DpcdAddress_TrainingPatternSet
179 *****************************************************************/
180 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
181 hw_training_pattern_to_dpcd_training_pattern(link, pattern);
182
3a340294 183 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
4562236b
HW		 184 = dpcd_pattern.raw;
185
1296423b 186 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
4562236b 187 __func__,
3a340294 188 DP_TRAINING_PATTERN_SET,
4562236b
HW		 189 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
190
191 /*****************************************************************
192 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
193 *****************************************************************/
194 for (lane = 0; lane <
195 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
196
197 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
198 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
199 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
200 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
201
202 dpcd_lane[lane].bits.MAX_SWING_REACHED =
203 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
204 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
205 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
206 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
207 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
208 }
209
210 /* concatinate everything into one buffer*/
211
212 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
213
214 // 0x00103 - 0x00102
215 memmove(
3a340294 216 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
4562236b
HW		 217 dpcd_lane,
218 size_in_bytes);
219
1296423b 220 DC_LOG_HW_LINK_TRAINING("%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
4562236b 221 __func__,
3a340294 222 DP_TRAINING_LANE0_SET,
4562236b
HW		 223 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
224 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
225 dpcd_lane[0].bits.MAX_SWING_REACHED,
226 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
227
228 if (edp_workaround) {
229 /* for eDP write in 2 parts because the 5-byte burst is
230 * causing issues on some eDP panels (EPR#366724)
231 */
232 core_link_write_dpcd(
233 link,
3a340294 234 DP_TRAINING_PATTERN_SET,
4562236b 235 &dpcd_pattern.raw,
9a6a8075 236 sizeof(dpcd_pattern.raw));
4562236b
HW		 237
238 core_link_write_dpcd(
239 link,
3a340294 240 DP_TRAINING_LANE0_SET,
4562236b
HW		 241 (uint8_t *)(dpcd_lane),
242 size_in_bytes);
243
244 } else
245 /* write it all in (1 + number-of-lanes)-byte burst*/
246 core_link_write_dpcd(
247 link,
248 dpcd_base_lt_offset,
249 dpcd_lt_buffer,
9a6a8075 250 size_in_bytes + sizeof(dpcd_pattern.raw));
4562236b 251
d0778ebf 252 link->cur_lane_setting = lt_settings->lane_settings[0];
4562236b
HW		 253}
254
255static bool is_cr_done(enum dc_lane_count ln_count,
256 union lane_status *dpcd_lane_status)
257{
258 bool done = true;
259 uint32_t lane;
260 /*LANEx_CR_DONE bits All 1's?*/
261 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
262 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
263 done = false;
264 }
265 return done;
266
267}
268
269static bool is_ch_eq_done(enum dc_lane_count ln_count,
270 union lane_status *dpcd_lane_status,
271 union lane_align_status_updated *lane_status_updated)
272{
273 bool done = true;
274 uint32_t lane;
275 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
276 done = false;
277 else {
278 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
279 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
280 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
281 done = false;
282 }
283 }
284 return done;
285
286}
287
288static void update_drive_settings(
289 struct link_training_settings *dest,
290 struct link_training_settings src)
291{
292 uint32_t lane;
293 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
294 dest->lane_settings[lane].VOLTAGE_SWING =
295 src.lane_settings[lane].VOLTAGE_SWING;
296 dest->lane_settings[lane].PRE_EMPHASIS =
297 src.lane_settings[lane].PRE_EMPHASIS;
298 dest->lane_settings[lane].POST_CURSOR2 =
299 src.lane_settings[lane].POST_CURSOR2;
300 }
301}
302
303static uint8_t get_nibble_at_index(const uint8_t *buf,
304 uint32_t index)
305{
306 uint8_t nibble;
307 nibble = buf[index / 2];
308
309 if (index % 2)
310 nibble >>= 4;
311 else
312 nibble &= 0x0F;
313
314 return nibble;
315}
316
317static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
318 enum dc_voltage_swing voltage)
319{
320 enum dc_pre_emphasis pre_emphasis;
321 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
322
323 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
324 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
325
326 return pre_emphasis;
327
328}
329
330static void find_max_drive_settings(
331 const struct link_training_settings *link_training_setting,
332 struct link_training_settings *max_lt_setting)
333{
334 uint32_t lane;
335 struct dc_lane_settings max_requested;
336
337 max_requested.VOLTAGE_SWING =
338 link_training_setting->
339 lane_settings[0].VOLTAGE_SWING;
340 max_requested.PRE_EMPHASIS =
341 link_training_setting->
342 lane_settings[0].PRE_EMPHASIS;
343 /*max_requested.postCursor2 =
344 * link_training_setting->laneSettings[0].postCursor2;*/
345
346 /* Determine what the maximum of the requested settings are*/
347 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
348 lane++) {
349 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
350 max_requested.VOLTAGE_SWING)
351
352 max_requested.VOLTAGE_SWING =
353 link_training_setting->
354 lane_settings[lane].VOLTAGE_SWING;
355
356 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
357 max_requested.PRE_EMPHASIS)
358 max_requested.PRE_EMPHASIS =
359 link_training_setting->
360 lane_settings[lane].PRE_EMPHASIS;
361
362 /*
363 if (link_training_setting->laneSettings[lane].postCursor2 >
364 max_requested.postCursor2)
365 {
366 max_requested.postCursor2 =
367 link_training_setting->laneSettings[lane].postCursor2;
368 }
369 */
370 }
371
372 /* make sure the requested settings are
373 * not higher than maximum settings*/
374 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
375 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
376
377 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
378 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
379 /*
380 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
381 max_requested.postCursor2 = PostCursor2_MaxLevel;
382 */
383
384 /* make sure the pre-emphasis matches the voltage swing*/
385 if (max_requested.PRE_EMPHASIS >
386 get_max_pre_emphasis_for_voltage_swing(
387 max_requested.VOLTAGE_SWING))
388 max_requested.PRE_EMPHASIS =
389 get_max_pre_emphasis_for_voltage_swing(
390 max_requested.VOLTAGE_SWING);
391
392 /*
393 * Post Cursor2 levels are completely independent from
394 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
395 * can only be applied to each allowable combination of voltage
396 * swing and pre-emphasis levels */
397 /* if ( max_requested.postCursor2 >
398 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
399 * max_requested.postCursor2 =
400 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
401 */
402
403 max_lt_setting->link_settings.link_rate =
404 link_training_setting->link_settings.link_rate;
405 max_lt_setting->link_settings.lane_count =
406 link_training_setting->link_settings.lane_count;
407 max_lt_setting->link_settings.link_spread =
408 link_training_setting->link_settings.link_spread;
409
410 for (lane = 0; lane <
411 link_training_setting->link_settings.lane_count;
412 lane++) {
413 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
414 max_requested.VOLTAGE_SWING;
415 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
416 max_requested.PRE_EMPHASIS;
417 /*max_lt_setting->laneSettings[lane].postCursor2 =
418 * max_requested.postCursor2;
419 */
420 }
421
422}
423
424static void get_lane_status_and_drive_settings(
d0778ebf 425 struct dc_link *link,
4562236b
HW		 426 const struct link_training_settings *link_training_setting,
427 union lane_status *ln_status,
428 union lane_align_status_updated *ln_status_updated,
429 struct link_training_settings *req_settings)
430{
431 uint8_t dpcd_buf[6] = {0};
9a6a8075
HW		 432 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
433 struct link_training_settings request_settings = { {0} };
4562236b
HW		 434 uint32_t lane;
435
436 memset(req_settings, '\0', sizeof(struct link_training_settings));
437
438 core_link_read_dpcd(
439 link,
3a340294 440 DP_LANE0_1_STATUS,
4562236b
HW		 441 (uint8_t *)(dpcd_buf),
442 sizeof(dpcd_buf));
443
444 for (lane = 0; lane <
445 (uint32_t)(link_training_setting->link_settings.lane_count);
446 lane++) {
447
448 ln_status[lane].raw =
449 get_nibble_at_index(&dpcd_buf[0], lane);
450 dpcd_lane_adjust[lane].raw =
451 get_nibble_at_index(&dpcd_buf[4], lane);
452 }
453
454 ln_status_updated->raw = dpcd_buf[2];
455
1296423b 456 DC_LOG_HW_LINK_TRAINING("%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
4562236b 457 __func__,
3a340294
DA		 458 DP_LANE0_1_STATUS, dpcd_buf[0],
459 DP_LANE2_3_STATUS, dpcd_buf[1]);
4562236b 460
1296423b 461 DC_LOG_HW_LINK_TRAINING("%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
4562236b 462 __func__,
3a340294 463 DP_ADJUST_REQUEST_LANE0_1,
4562236b 464 dpcd_buf[4],
3a340294 465 DP_ADJUST_REQUEST_LANE2_3,
4562236b
HW		 466 dpcd_buf[5]);
467
468 /*copy to req_settings*/
469 request_settings.link_settings.lane_count =
470 link_training_setting->link_settings.lane_count;
471 request_settings.link_settings.link_rate =
472 link_training_setting->link_settings.link_rate;
473 request_settings.link_settings.link_spread =
474 link_training_setting->link_settings.link_spread;
475
476 for (lane = 0; lane <
477 (uint32_t)(link_training_setting->link_settings.lane_count);
478 lane++) {
479
480 request_settings.lane_settings[lane].VOLTAGE_SWING =
481 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
482 VOLTAGE_SWING_LANE);
483 request_settings.lane_settings[lane].PRE_EMPHASIS =
484 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
485 PRE_EMPHASIS_LANE);
486 }
487
488 /*Note: for postcursor2, read adjusted
489 * postcursor2 settings from*/
490 /*DpcdAddress_AdjustRequestPostCursor2 =
491 *0x020C (not implemented yet)*/
492
493 /* we find the maximum of the requested settings across all lanes*/
494 /* and set this maximum for all lanes*/
495 find_max_drive_settings(&request_settings, req_settings);
496
497 /* if post cursor 2 is needed in the future,
498 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
499 */
500
501}
502
503static void dpcd_set_lane_settings(
d0778ebf 504 struct dc_link *link,
4562236b
HW		 505 const struct link_training_settings *link_training_setting)
506{
507 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
508 uint32_t lane;
509
510 for (lane = 0; lane <
511 (uint32_t)(link_training_setting->
512 link_settings.lane_count);
513 lane++) {
514 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
515 (uint8_t)(link_training_setting->
516 lane_settings[lane].VOLTAGE_SWING);
517 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
518 (uint8_t)(link_training_setting->
519 lane_settings[lane].PRE_EMPHASIS);
520 dpcd_lane[lane].bits.MAX_SWING_REACHED =
521 (link_training_setting->
522 lane_settings[lane].VOLTAGE_SWING ==
523 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
524 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
525 (link_training_setting->
526 lane_settings[lane].PRE_EMPHASIS ==
527 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
528 }
529
530 core_link_write_dpcd(link,
3a340294 531 DP_TRAINING_LANE0_SET,
4562236b
HW		 532 (uint8_t *)(dpcd_lane),
533 link_training_setting->link_settings.lane_count);
534
535 /*
536 if (LTSettings.link.rate == LinkRate_High2)
537 {
538 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
539 for ( uint32_t lane = 0;
540 lane < lane_count_DPMax; lane++)
541 {
542 dpcd_lane2[lane].bits.post_cursor2_set =
543 static_cast<unsigned char>(
544 LTSettings.laneSettings[lane].postCursor2);
545 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
546 }
547 m_pDpcdAccessSrv->WriteDpcdData(
548 DpcdAddress_Lane0Set2,
549 reinterpret_cast<unsigned char*>(dpcd_lane2),
550 LTSettings.link.lanes);
551 }
552 */
553
1296423b 554 DC_LOG_HW_LINK_TRAINING("%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
4562236b 555 __func__,
3a340294 556 DP_TRAINING_LANE0_SET,
4562236b
HW		 557 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
558 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
559 dpcd_lane[0].bits.MAX_SWING_REACHED,
560 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
561
d0778ebf 562 link->cur_lane_setting = link_training_setting->lane_settings[0];
4562236b
HW		 563
564}
565
566static bool is_max_vs_reached(
567 const struct link_training_settings *lt_settings)
568{
569 uint32_t lane;
570 for (lane = 0; lane <
571 (uint32_t)(lt_settings->link_settings.lane_count);
572 lane++) {
573 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
574 == VOLTAGE_SWING_MAX_LEVEL)
575 return true;
576 }
577 return false;
578
579}
580
581void dc_link_dp_set_drive_settings(
d0778ebf 582 struct dc_link *link,
4562236b
HW		 583 struct link_training_settings *lt_settings)
584{
4562236b 585 /* program ASIC PHY settings*/
d0778ebf 586 dp_set_hw_lane_settings(link, lt_settings);
4562236b
HW		 587
588 /* Notify DP sink the PHY settings from source */
d0778ebf 589 dpcd_set_lane_settings(link, lt_settings);
4562236b
HW		 590}
591
592static bool perform_post_lt_adj_req_sequence(
d0778ebf 593 struct dc_link *link,
4562236b
HW		 594 struct link_training_settings *lt_settings)
595{
596 enum dc_lane_count lane_count =
597 lt_settings->link_settings.lane_count;
598
599 uint32_t adj_req_count;
600 uint32_t adj_req_timer;
601 bool req_drv_setting_changed;
602 uint32_t lane;
603
604 req_drv_setting_changed = false;
605 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
606 adj_req_count++) {
607
608 req_drv_setting_changed = false;
609
610 for (adj_req_timer = 0;
611 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
612 adj_req_timer++) {
613
614 struct link_training_settings req_settings;
615 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
616 union lane_align_status_updated
617 dpcd_lane_status_updated;
618
619 get_lane_status_and_drive_settings(
620 link,
621 lt_settings,
622 dpcd_lane_status,
623 &dpcd_lane_status_updated,
624 &req_settings);
625
626 if (dpcd_lane_status_updated.bits.
627 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
628 return true;
629
630 if (!is_cr_done(lane_count, dpcd_lane_status))
631 return false;
632
633 if (!is_ch_eq_done(
634 lane_count,
635 dpcd_lane_status,
636 &dpcd_lane_status_updated))
637 return false;
638
639 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
640
641 if (lt_settings->
642 lane_settings[lane].VOLTAGE_SWING !=
643 req_settings.lane_settings[lane].
644 VOLTAGE_SWING ||
645 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
646 req_settings.lane_settings[lane].PRE_EMPHASIS) {
647
648 req_drv_setting_changed = true;
649 break;
650 }
651 }
652
653 if (req_drv_setting_changed) {
654 update_drive_settings(
9a6a8075 655 lt_settings, req_settings);
4562236b 656
d0778ebf 657 dc_link_dp_set_drive_settings(link,
4562236b
HW		 658 lt_settings);
659 break;
660 }
661
662 msleep(1);
663 }
664
665 if (!req_drv_setting_changed) {
1296423b 666 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
4562236b
HW		 667 __func__);
668
669 ASSERT(0);
670 return true;
671 }
672 }
1296423b 673 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
4562236b
HW		 674 __func__);
675
676 ASSERT(0);
677 return true;
678
679}
680
d0778ebf 681static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
4562236b
HW		 682{
683 enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
684 struct encoder_feature_support *features = &link->link_enc->features;
685 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
686
687 if (features->flags.bits.IS_TPS3_CAPABLE)
688 highest_tp = HW_DP_TRAINING_PATTERN_3;
689
690 if (features->flags.bits.IS_TPS4_CAPABLE)
691 highest_tp = HW_DP_TRAINING_PATTERN_4;
692
693 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
694 highest_tp >= HW_DP_TRAINING_PATTERN_4)
695 return HW_DP_TRAINING_PATTERN_4;
696
697 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
698 highest_tp >= HW_DP_TRAINING_PATTERN_3)
699 return HW_DP_TRAINING_PATTERN_3;
700
701 return HW_DP_TRAINING_PATTERN_2;
702}
703
94405cf6
WL		 704static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
705 union lane_status *dpcd_lane_status)
706{
707 enum link_training_result result = LINK_TRAINING_SUCCESS;
708
709 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
710 result = LINK_TRAINING_CR_FAIL_LANE0;
711 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
712 result = LINK_TRAINING_CR_FAIL_LANE1;
713 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
714 result = LINK_TRAINING_CR_FAIL_LANE23;
715 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
716 result = LINK_TRAINING_CR_FAIL_LANE23;
717 return result;
718}
719
820e3935 720static enum link_training_result perform_channel_equalization_sequence(
d0778ebf 721 struct dc_link *link,
4562236b
HW		 722 struct link_training_settings *lt_settings)
723{
724 struct link_training_settings req_settings;
725 enum hw_dp_training_pattern hw_tr_pattern;
726 uint32_t retries_ch_eq;
727 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
9a6a8075
HW		 728 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
729 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
4562236b
HW		 730
731 hw_tr_pattern = get_supported_tp(link);
732
733 dp_set_hw_training_pattern(link, hw_tr_pattern);
734
735 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
736 retries_ch_eq++) {
737
738 dp_set_hw_lane_settings(link, lt_settings);
739
740 /* 2. update DPCD*/
741 if (!retries_ch_eq)
742 /* EPR #361076 - write as a 5-byte burst,
743 * but only for the 1-st iteration*/
744 dpcd_set_lt_pattern_and_lane_settings(
745 link,
746 lt_settings,
747 hw_tr_pattern);
748 else
749 dpcd_set_lane_settings(link, lt_settings);
750
751 /* 3. wait for receiver to lock-on*/
752 wait_for_training_aux_rd_interval(link, 400);
753
754 /* 4. Read lane status and requested
755 * drive settings as set by the sink*/
756
757 get_lane_status_and_drive_settings(
758 link,
759 lt_settings,
760 dpcd_lane_status,
761 &dpcd_lane_status_updated,
762 &req_settings);
763
764 /* 5. check CR done*/
765 if (!is_cr_done(lane_count, dpcd_lane_status))
820e3935 766 return LINK_TRAINING_EQ_FAIL_CR;
4562236b
HW		 767
768 /* 6. check CHEQ done*/
769 if (is_ch_eq_done(lane_count,
770 dpcd_lane_status,
771 &dpcd_lane_status_updated))
820e3935 772 return LINK_TRAINING_SUCCESS;
4562236b
HW		 773
774 /* 7. update VS/PE/PC2 in lt_settings*/
775 update_drive_settings(lt_settings, req_settings);
776 }
777
820e3935 778 return LINK_TRAINING_EQ_FAIL_EQ;
4562236b
HW		 779
780}
781
94405cf6 782static enum link_training_result perform_clock_recovery_sequence(
d0778ebf 783 struct dc_link *link,
4562236b
HW		 784 struct link_training_settings *lt_settings)
785{
786 uint32_t retries_cr;
787 uint32_t retry_count;
788 uint32_t lane;
789 struct link_training_settings req_settings;
790 enum dc_lane_count lane_count =
791 lt_settings->link_settings.lane_count;
792 enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
793 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
794 union lane_align_status_updated dpcd_lane_status_updated;
795
796 retries_cr = 0;
797 retry_count = 0;
798 /* initial drive setting (VS/PE/PC2)*/
799 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
800 lt_settings->lane_settings[lane].VOLTAGE_SWING =
801 VOLTAGE_SWING_LEVEL0;
802 lt_settings->lane_settings[lane].PRE_EMPHASIS =
803 PRE_EMPHASIS_DISABLED;
804 lt_settings->lane_settings[lane].POST_CURSOR2 =
805 POST_CURSOR2_DISABLED;
806 }
807
808 dp_set_hw_training_pattern(link, hw_tr_pattern);
809
810 /* najeeb - The synaptics MST hub can put the LT in
811 * infinite loop by switching the VS
812 */
813 /* between level 0 and level 1 continuously, here
814 * we try for CR lock for LinkTrainingMaxCRRetry count*/
815 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
816 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
817
818 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
819 memset(&dpcd_lane_status_updated, '\0',
820 sizeof(dpcd_lane_status_updated));
821
822 /* 1. call HWSS to set lane settings*/
823 dp_set_hw_lane_settings(
824 link,
825 lt_settings);
826
827 /* 2. update DPCD of the receiver*/
828 if (!retries_cr)
829 /* EPR #361076 - write as a 5-byte burst,
830 * but only for the 1-st iteration.*/
831 dpcd_set_lt_pattern_and_lane_settings(
832 link,
833 lt_settings,
834 hw_tr_pattern);
835 else
836 dpcd_set_lane_settings(
837 link,
838 lt_settings);
839
840 /* 3. wait receiver to lock-on*/
841 wait_for_training_aux_rd_interval(
842 link,
843 100);
844
845 /* 4. Read lane status and requested drive
846 * settings as set by the sink
847 */
848 get_lane_status_and_drive_settings(
849 link,
850 lt_settings,
851 dpcd_lane_status,
852 &dpcd_lane_status_updated,
853 &req_settings);
854
855 /* 5. check CR done*/
856 if (is_cr_done(lane_count, dpcd_lane_status))
94405cf6 857 return LINK_TRAINING_SUCCESS;
4562236b
HW		 858
859 /* 6. max VS reached*/
860 if (is_max_vs_reached(lt_settings))
94405cf6 861 break;
4562236b
HW		 862
863 /* 7. same voltage*/
864 /* Note: VS same for all lanes,
865 * so comparing first lane is sufficient*/
866 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
867 req_settings.lane_settings[0].VOLTAGE_SWING)
868 retries_cr++;
869 else
870 retries_cr = 0;
871
872 /* 8. update VS/PE/PC2 in lt_settings*/
873 update_drive_settings(lt_settings, req_settings);
874
875 retry_count++;
876 }
877
878 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
879 ASSERT(0);
1296423b 880 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
4f42a2dd 881 __func__,
4562236b
HW		 882 LINK_TRAINING_MAX_CR_RETRY);
883
884 }
885
94405cf6 886 return get_cr_failure(lane_count, dpcd_lane_status);
4562236b
HW		 887}
888
94405cf6 889static inline enum link_training_result perform_link_training_int(
d0778ebf 890 struct dc_link *link,
4562236b 891 struct link_training_settings *lt_settings,
94405cf6 892 enum link_training_result status)
4562236b
HW		 893{
894 union lane_count_set lane_count_set = { {0} };
895 union dpcd_training_pattern dpcd_pattern = { {0} };
896
897 /* 3. set training not in progress*/
898 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
899 dpcd_set_training_pattern(link, dpcd_pattern);
900
901 /* 4. mainlink output idle pattern*/
902 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
903
904 /*
905 * 5. post training adjust if required
906 * If the upstream DPTX and downstream DPRX both support TPS4,
907 * TPS4 must be used instead of POST_LT_ADJ_REQ.
908 */
c30267f5
CL		 909 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
910 get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
4562236b
HW		 911 return status;
912
94405cf6 913 if (status == LINK_TRAINING_SUCCESS &&
4562236b 914 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
94405cf6 915 status = LINK_TRAINING_LQA_FAIL;
4562236b
HW		 916
917 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
918 lane_count_set.bits.ENHANCED_FRAMING = 1;
919 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
920
921 core_link_write_dpcd(
922 link,
3a340294 923 DP_LANE_COUNT_SET,
4562236b
HW		 924 &lane_count_set.raw,
925 sizeof(lane_count_set));
926
927 return status;
928}
929
820e3935 930enum link_training_result dc_link_dp_perform_link_training(
4562236b
HW		 931 struct dc_link *link,
932 const struct dc_link_settings *link_setting,
933 bool skip_video_pattern)
934{
820e3935 935 enum link_training_result status = LINK_TRAINING_SUCCESS;
4562236b
HW		 936
937 char *link_rate = "Unknown";
94405cf6
WL		 938 char *lt_result = "Unknown";
939
4562236b
HW		 940 struct link_training_settings lt_settings;
941
4562236b
HW		 942 memset(&lt_settings, '\0', sizeof(lt_settings));
943
944 lt_settings.link_settings.link_rate = link_setting->link_rate;
945 lt_settings.link_settings.lane_count = link_setting->lane_count;
946
947 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
948
949 /* TODO hard coded to SS for now
950 * lt_settings.link_settings.link_spread =
951 * dal_display_path_is_ss_supported(
952 * path_mode->display_path) ?
953 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
954 * LINK_SPREAD_DISABLED;
955 */
956 lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
957
958 /* 1. set link rate, lane count and spread*/
d0778ebf 959 dpcd_set_link_settings(link, &lt_settings);
4562236b
HW		 960
961 /* 2. perform link training (set link training done
962 * to false is done as well)*/
94405cf6
WL		 963 status = perform_clock_recovery_sequence(link, &lt_settings);
964 if (status == LINK_TRAINING_SUCCESS) {
d0778ebf 965 status = perform_channel_equalization_sequence(link,
820e3935 966 &lt_settings);
4562236b
HW		 967 }
968
820e3935 969 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
94405cf6 970 status = perform_link_training_int(link,
820e3935 971 &lt_settings,
94405cf6 972 status);
820e3935 973 }
4562236b
HW		 974
975 /* 6. print status message*/
976 switch (lt_settings.link_settings.link_rate) {
977
978 case LINK_RATE_LOW:
979 link_rate = "RBR";
980 break;
981 case LINK_RATE_HIGH:
982 link_rate = "HBR";
983 break;
984 case LINK_RATE_HIGH2:
985 link_rate = "HBR2";
986 break;
987 case LINK_RATE_RBR2:
988 link_rate = "RBR2";
989 break;
990 case LINK_RATE_HIGH3:
991 link_rate = "HBR3";
992 break;
993 default:
994 break;
995 }
996
94405cf6
WL		 997 switch (status) {
998 case LINK_TRAINING_SUCCESS:
999 lt_result = "pass";
1000 break;
1001 case LINK_TRAINING_CR_FAIL_LANE0:
1002 lt_result = "CR failed lane0";
1003 break;
1004 case LINK_TRAINING_CR_FAIL_LANE1:
1005 lt_result = "CR failed lane1";
1006 break;
1007 case LINK_TRAINING_CR_FAIL_LANE23:
1008 lt_result = "CR failed lane23";
1009 break;
1010 case LINK_TRAINING_EQ_FAIL_CR:
1011 lt_result = "CR failed in EQ";
1012 break;
1013 case LINK_TRAINING_EQ_FAIL_EQ:
1014 lt_result = "EQ failed";
1015 break;
1016 case LINK_TRAINING_LQA_FAIL:
1017 lt_result = "LQA failed";
1018 break;
1019 default:
1020 break;
1021 }
1022
4562236b 1023 /* Connectivity log: link training */
d0778ebf 1024 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
4562236b
HW		 1025 link_rate,
1026 lt_settings.link_settings.lane_count,
94405cf6 1027 lt_result,
4562236b
HW		 1028 lt_settings.lane_settings[0].VOLTAGE_SWING,
1029 lt_settings.lane_settings[0].PRE_EMPHASIS);
1030
d6e75df4 1031 if (status != LINK_TRAINING_SUCCESS)
cfd84fd3 1032 link->ctx->dc->debug_data.ltFailCount++;
d6e75df4 1033
4562236b
HW		 1034 return status;
1035}
1036
1037
1038bool perform_link_training_with_retries(
d0778ebf 1039 struct dc_link *link,
4562236b
HW		 1040 const struct dc_link_settings *link_setting,
1041 bool skip_video_pattern,
1042 int attempts)
1043{
1044 uint8_t j;
1045 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1046
1047 for (j = 0; j < attempts; ++j) {
1048
1049 if (dc_link_dp_perform_link_training(
d0778ebf 1050 link,
4562236b 1051 link_setting,
820e3935 1052 skip_video_pattern) == LINK_TRAINING_SUCCESS)
4562236b
HW		 1053 return true;
1054
1055 msleep(delay_between_attempts);
1056 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1057 }
1058
1059 return false;
1060}
1061
d0778ebf 1062static struct dc_link_settings get_max_link_cap(struct dc_link *link)
4562236b
HW		 1063{
1064 /* Set Default link settings */
1065 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1066 LINK_SPREAD_05_DOWNSPREAD_30KHZ};
1067
1068 /* Higher link settings based on feature supported */
1069 if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1070 max_link_cap.link_rate = LINK_RATE_HIGH2;
1071
1072 if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1073 max_link_cap.link_rate = LINK_RATE_HIGH3;
1074
1075 /* Lower link settings based on sink's link cap */
d0778ebf 1076 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
4562236b 1077 max_link_cap.lane_count =
d0778ebf
HW		 1078 link->reported_link_cap.lane_count;
1079 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
4562236b 1080 max_link_cap.link_rate =
d0778ebf
HW		 1081 link->reported_link_cap.link_rate;
1082 if (link->reported_link_cap.link_spread <
4562236b
HW		 1083 max_link_cap.link_spread)
1084 max_link_cap.link_spread =
d0778ebf 1085 link->reported_link_cap.link_spread;
4562236b
HW		 1086 return max_link_cap;
1087}
1088
aafded88 1089bool dp_verify_link_cap(
d0778ebf 1090 struct dc_link *link,
824474ba
BL		 1091 struct dc_link_settings *known_limit_link_setting,
1092 int *fail_count)
4562236b
HW		 1093{
1094 struct dc_link_settings max_link_cap = {0};
820e3935
DW		 1095 struct dc_link_settings cur_link_setting = {0};
1096 struct dc_link_settings *cur = &cur_link_setting;
1097 struct dc_link_settings initial_link_settings = {0};
4562236b
HW		 1098 bool success;
1099 bool skip_link_training;
4562236b 1100 bool skip_video_pattern;
4562236b
HW		 1101 struct clock_source *dp_cs;
1102 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
820e3935 1103 enum link_training_result status;
4562236b 1104
aafded88
TC		 1105 if (link->dc->debug.skip_detection_link_training) {
1106 link->verified_link_cap = *known_limit_link_setting;
1107 return true;
1108 }
1109
4562236b
HW		 1110 success = false;
1111 skip_link_training = false;
1112
1113 max_link_cap = get_max_link_cap(link);
1114
1115 /* TODO implement override and monitor patch later */
1116
1117 /* try to train the link from high to low to
1118 * find the physical link capability
1119 */
1120 /* disable PHY done possible by BIOS, will be done by driver itself */
d0778ebf 1121 dp_disable_link_phy(link, link->connector_signal);
4562236b
HW		 1122
1123 dp_cs = link->dc->res_pool->dp_clock_source;
1124
1125 if (dp_cs)
1126 dp_cs_id = dp_cs->id;
1127 else {
1128 /*
1129 * dp clock source is not initialized for some reason.
1130 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1131 */
1132 ASSERT(dp_cs);
1133 }
1134
820e3935
DW		 1135 /* link training starts with the maximum common settings
1136 * supported by both sink and ASIC.
1137 */
1138 initial_link_settings = get_common_supported_link_settings(
1139 *known_limit_link_setting,
1140 max_link_cap);
1141 cur_link_setting = initial_link_settings;
1142 do {
4562236b 1143 skip_video_pattern = true;
820e3935 1144
4562236b
HW		 1145 if (cur->link_rate == LINK_RATE_LOW)
1146 skip_video_pattern = false;
1147
1148 dp_enable_link_phy(
1149 link,
d0778ebf 1150 link->connector_signal,
4562236b
HW		 1151 dp_cs_id,
1152 cur);
1153
94405cf6 1154
4562236b
HW		 1155 if (skip_link_training)
1156 success = true;
1157 else {
820e3935 1158 status = dc_link_dp_perform_link_training(
d0778ebf 1159 link,
4562236b
HW		 1160 cur,
1161 skip_video_pattern);
820e3935
DW		 1162 if (status == LINK_TRAINING_SUCCESS)
1163 success = true;
824474ba
BL		 1164 else
1165 (*fail_count)++;
4562236b
HW		 1166 }
1167
1168 if (success)
d0778ebf 1169 link->verified_link_cap = *cur;
4562236b
HW		 1170
1171 /* always disable the link before trying another
1172 * setting or before returning we'll enable it later
1173 * based on the actual mode we're driving
1174 */
d0778ebf 1175 dp_disable_link_phy(link, link->connector_signal);
820e3935
DW		 1176 } while (!success && decide_fallback_link_setting(
1177 initial_link_settings, cur, status));
4562236b
HW		 1178
1179 /* Link Training failed for all Link Settings
1180 * (Lane Count is still unknown)
1181 */
1182 if (!success) {
1183 /* If all LT fails for all settings,
1184 * set verified = failed safe (1 lane low)
1185 */
d0778ebf
HW		 1186 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1187 link->verified_link_cap.link_rate = LINK_RATE_LOW;
4562236b 1188
d0778ebf 1189 link->verified_link_cap.link_spread =
4562236b
HW		 1190 LINK_SPREAD_DISABLED;
1191 }
1192
4562236b
HW		 1193
1194 return success;
1195}
1196
9a6a8075 1197static struct dc_link_settings get_common_supported_link_settings(
820e3935
DW		 1198 struct dc_link_settings link_setting_a,
1199 struct dc_link_settings link_setting_b)
1200{
1201 struct dc_link_settings link_settings = {0};
1202
1203 link_settings.lane_count =
1204 (link_setting_a.lane_count <=
1205 link_setting_b.lane_count) ?
1206 link_setting_a.lane_count :
1207 link_setting_b.lane_count;
1208 link_settings.link_rate =
1209 (link_setting_a.link_rate <=
1210 link_setting_b.link_rate) ?
1211 link_setting_a.link_rate :
1212 link_setting_b.link_rate;
1213 link_settings.link_spread = LINK_SPREAD_DISABLED;
1214
1215 /* in DP compliance test, DPR-120 may have
1216 * a random value in its MAX_LINK_BW dpcd field.
1217 * We map it to the maximum supported link rate that
1218 * is smaller than MAX_LINK_BW in this case.
1219 */
1220 if (link_settings.link_rate > LINK_RATE_HIGH3) {
1221 link_settings.link_rate = LINK_RATE_HIGH3;
1222 } else if (link_settings.link_rate < LINK_RATE_HIGH3
1223 && link_settings.link_rate > LINK_RATE_HIGH2) {
1224 link_settings.link_rate = LINK_RATE_HIGH2;
1225 } else if (link_settings.link_rate < LINK_RATE_HIGH2
1226 && link_settings.link_rate > LINK_RATE_HIGH) {
1227 link_settings.link_rate = LINK_RATE_HIGH;
1228 } else if (link_settings.link_rate < LINK_RATE_HIGH
1229 && link_settings.link_rate > LINK_RATE_LOW) {
1230 link_settings.link_rate = LINK_RATE_LOW;
1231 } else if (link_settings.link_rate < LINK_RATE_LOW) {
1232 link_settings.link_rate = LINK_RATE_UNKNOWN;
1233 }
1234
1235 return link_settings;
1236}
1237
450619d3 1238static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 1239{
1240 return lane_count <= LANE_COUNT_ONE;
1241}
1242
450619d3 1243static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 1244{
1245 return link_rate <= LINK_RATE_LOW;
1246}
1247
44858055 1248static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 1249{
1250 switch (lane_count) {
1251 case LANE_COUNT_FOUR:
1252 return LANE_COUNT_TWO;
1253 case LANE_COUNT_TWO:
1254 return LANE_COUNT_ONE;
1255 case LANE_COUNT_ONE:
1256 return LANE_COUNT_UNKNOWN;
1257 default:
1258 return LANE_COUNT_UNKNOWN;
1259 }
1260}
1261
04e21292 1262static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 1263{
1264 switch (link_rate) {
1265 case LINK_RATE_HIGH3:
1266 return LINK_RATE_HIGH2;
1267 case LINK_RATE_HIGH2:
1268 return LINK_RATE_HIGH;
1269 case LINK_RATE_HIGH:
1270 return LINK_RATE_LOW;
1271 case LINK_RATE_LOW:
1272 return LINK_RATE_UNKNOWN;
1273 default:
1274 return LINK_RATE_UNKNOWN;
1275 }
1276}
1277
04e21292 1278static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
8c4abe0b
DW		 1279{
1280 switch (lane_count) {
1281 case LANE_COUNT_ONE:
1282 return LANE_COUNT_TWO;
1283 case LANE_COUNT_TWO:
1284 return LANE_COUNT_FOUR;
1285 default:
1286 return LANE_COUNT_UNKNOWN;
1287 }
1288}
1289
04e21292 1290static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
8c4abe0b
DW		 1291{
1292 switch (link_rate) {
1293 case LINK_RATE_LOW:
1294 return LINK_RATE_HIGH;
1295 case LINK_RATE_HIGH:
1296 return LINK_RATE_HIGH2;
1297 case LINK_RATE_HIGH2:
1298 return LINK_RATE_HIGH3;
1299 default:
1300 return LINK_RATE_UNKNOWN;
1301 }
1302}
1303
820e3935
DW		 1304/*
1305 * function: set link rate and lane count fallback based
1306 * on current link setting and last link training result
1307 * return value:
1308 * true - link setting could be set
1309 * false - has reached minimum setting
1310 * and no further fallback could be done
1311 */
04e21292 1312static bool decide_fallback_link_setting(
820e3935
DW		 1313 struct dc_link_settings initial_link_settings,
1314 struct dc_link_settings *current_link_setting,
1315 enum link_training_result training_result)
1316{
1317 if (!current_link_setting)
1318 return false;
1319
1320 switch (training_result) {
94405cf6
WL		 1321 case LINK_TRAINING_CR_FAIL_LANE0:
1322 case LINK_TRAINING_CR_FAIL_LANE1:
1323 case LINK_TRAINING_CR_FAIL_LANE23:
1324 case LINK_TRAINING_LQA_FAIL:
820e3935
DW		 1325 {
1326 if (!reached_minimum_link_rate
1327 (current_link_setting->link_rate)) {
1328 current_link_setting->link_rate =
1329 reduce_link_rate(
1330 current_link_setting->link_rate);
1331 } else if (!reached_minimum_lane_count
1332 (current_link_setting->lane_count)) {
1333 current_link_setting->link_rate =
1334 initial_link_settings.link_rate;
94405cf6
WL		 1335 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
1336 return false;
1337 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
1338 current_link_setting->lane_count =
1339 LANE_COUNT_ONE;
1340 else if (training_result ==
1341 LINK_TRAINING_CR_FAIL_LANE23)
1342 current_link_setting->lane_count =
1343 LANE_COUNT_TWO;
1344 else
1345 current_link_setting->lane_count =
1346 reduce_lane_count(
820e3935
DW		 1347 current_link_setting->lane_count);
1348 } else {
1349 return false;
1350 }
1351 break;
1352 }
1353 case LINK_TRAINING_EQ_FAIL_EQ:
1354 {
1355 if (!reached_minimum_lane_count
1356 (current_link_setting->lane_count)) {
1357 current_link_setting->lane_count =
1358 reduce_lane_count(
1359 current_link_setting->lane_count);
1360 } else if (!reached_minimum_link_rate
1361 (current_link_setting->link_rate)) {
820e3935
DW		 1362 current_link_setting->link_rate =
1363 reduce_link_rate(
1364 current_link_setting->link_rate);
1365 } else {
1366 return false;
1367 }
1368 break;
1369 }
1370 case LINK_TRAINING_EQ_FAIL_CR:
1371 {
1372 if (!reached_minimum_link_rate
1373 (current_link_setting->link_rate)) {
1374 current_link_setting->link_rate =
1375 reduce_link_rate(
1376 current_link_setting->link_rate);
1377 } else {
1378 return false;
1379 }
1380 break;
1381 }
1382 default:
1383 return false;
1384 }
1385 return true;
1386}
1387
4562236b
HW		 1388static uint32_t bandwidth_in_kbps_from_timing(
1389 const struct dc_crtc_timing *timing)
1390{
1391 uint32_t bits_per_channel = 0;
1392 uint32_t kbps;
4562236b 1393
50834eb4
HW		 1394 switch (timing->display_color_depth) {
1395 case COLOR_DEPTH_666:
1396 bits_per_channel = 6;
1397 break;
1398 case COLOR_DEPTH_888:
1399 bits_per_channel = 8;
1400 break;
1401 case COLOR_DEPTH_101010:
1402 bits_per_channel = 10;
1403 break;
1404 case COLOR_DEPTH_121212:
4562236b 1405 bits_per_channel = 12;
50834eb4
HW		 1406 break;
1407 case COLOR_DEPTH_141414:
1408 bits_per_channel = 14;
1409 break;
1410 case COLOR_DEPTH_161616:
1411 bits_per_channel = 16;
1412 break;
1413 default:
1414 break;
4562236b 1415 }
50834eb4 1416
4562236b
HW		 1417 ASSERT(bits_per_channel != 0);
1418
1419 kbps = timing->pix_clk_khz;
1420 kbps *= bits_per_channel;
1421
cf65ebeb 1422 if (timing->flags.Y_ONLY != 1) {
4562236b
HW		 1423 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
1424 kbps *= 3;
cf65ebeb
EY		 1425 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1426 kbps /= 2;
1427 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1428 kbps = kbps * 2 / 3;
1429 }
4562236b
HW		 1430
1431 return kbps;
1432
1433}
1434
1435static uint32_t bandwidth_in_kbps_from_link_settings(
1436 const struct dc_link_settings *link_setting)
1437{
1438 uint32_t link_rate_in_kbps = link_setting->link_rate *
1439 LINK_RATE_REF_FREQ_IN_KHZ;
1440
1441 uint32_t lane_count = link_setting->lane_count;
1442 uint32_t kbps = link_rate_in_kbps;
9a6a8075 1443
4562236b
HW		 1444 kbps *= lane_count;
1445 kbps *= 8; /* 8 bits per byte*/
1446
1447 return kbps;
1448
1449}
1450
1451bool dp_validate_mode_timing(
d0778ebf 1452 struct dc_link *link,
4562236b
HW		 1453 const struct dc_crtc_timing *timing)
1454{
1455 uint32_t req_bw;
1456 uint32_t max_bw;
1457
1458 const struct dc_link_settings *link_setting;
1459
1460 /*always DP fail safe mode*/
9a6a8075
HW		 1461 if (timing->pix_clk_khz == (uint32_t) 25175 &&
1462 timing->h_addressable == (uint32_t) 640 &&
1463 timing->v_addressable == (uint32_t) 480)
4562236b
HW		 1464 return true;
1465
1466 /* We always use verified link settings */
d0778ebf 1467 link_setting = &link->verified_link_cap;
4562236b
HW		 1468
1469 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1470 /*if (flags.DYNAMIC_VALIDATION == 1 &&
d0778ebf
HW		 1471 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
1472 link_setting = &link->verified_link_cap;
4562236b
HW		 1473 */
1474
1475 req_bw = bandwidth_in_kbps_from_timing(timing);
1476 max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
1477
1478 if (req_bw <= max_bw) {
1479 /* remember the biggest mode here, during
1480 * initial link training (to get
1481 * verified_link_cap), LS sends event about
1482 * cannot train at reported cap to upper
1483 * layer and upper layer will re-enumerate modes.
1484 * this is not necessary if the lower
1485 * verified_link_cap is enough to drive
1486 * all the modes */
1487
1488 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1489 /* if (flags.DYNAMIC_VALIDATION == 1)
1490 dpsst->max_req_bw_for_verified_linkcap = dal_max(
1491 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
1492 return true;
1493 } else
1494 return false;
1495}
1496
0971c40e 1497void decide_link_settings(struct dc_stream_state *stream,
4562236b
HW		 1498 struct dc_link_settings *link_setting)
1499{
1500
8c4abe0b
DW		 1501 struct dc_link_settings initial_link_setting = {
1502 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED};
1503 struct dc_link_settings current_link_setting =
1504 initial_link_setting;
d0778ebf 1505 struct dc_link *link;
4562236b
HW		 1506 uint32_t req_bw;
1507 uint32_t link_bw;
4562236b 1508
4fa086b9 1509 req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
4562236b 1510
8c4abe0b
DW		 1511 link = stream->sink->link;
1512
4562236b
HW		 1513 /* if preferred is specified through AMDDP, use it, if it's enough
1514 * to drive the mode
1515 */
d0778ebf 1516 if (link->preferred_link_setting.lane_count !=
8c4abe0b 1517 LANE_COUNT_UNKNOWN &&
d0778ebf 1518 link->preferred_link_setting.link_rate !=
8c4abe0b 1519 LINK_RATE_UNKNOWN) {
d0778ebf 1520 *link_setting = link->preferred_link_setting;
8c4abe0b
DW		 1521 return;
1522 }
4562236b 1523
3f1f74f4
JZ		 1524 /* MST doesn't perform link training for now
1525 * TODO: add MST specific link training routine
1526 */
10dab193 1527 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3f1f74f4
JZ		 1528 *link_setting = link->verified_link_cap;
1529 return;
1530 }
1531
4d2f22d1
HH		 1532 /* EDP use the link cap setting */
1533 if (stream->sink->sink_signal == SIGNAL_TYPE_EDP) {
1534 *link_setting = link->verified_link_cap;
1535 return;
1536 }
1537
5667ff5c
DA		 1538 /* search for the minimum link setting that:
1539 * 1. is supported according to the link training result
1540 * 2. could support the b/w requested by the timing
1541 */
8c4abe0b 1542 while (current_link_setting.link_rate <=
4654a2f7 1543 link->verified_link_cap.link_rate) {
4562236b 1544 link_bw = bandwidth_in_kbps_from_link_settings(
8c4abe0b
DW		 1545 &current_link_setting);
1546 if (req_bw <= link_bw) {
1547 *link_setting = current_link_setting;
4562236b
HW		 1548 return;
1549 }
4562236b 1550
8c4abe0b 1551 if (current_link_setting.lane_count <
4654a2f7 1552 link->verified_link_cap.lane_count) {
8c4abe0b
DW		 1553 current_link_setting.lane_count =
1554 increase_lane_count(
1555 current_link_setting.lane_count);
1556 } else {
1557 current_link_setting.link_rate =
1558 increase_link_rate(
1559 current_link_setting.link_rate);
1560 current_link_setting.lane_count =
1561 initial_link_setting.lane_count;
4562236b
HW		 1562 }
1563 }
1564
1565 BREAK_TO_DEBUGGER();
d0778ebf 1566 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
4562236b 1567
d0778ebf 1568 *link_setting = link->verified_link_cap;
4562236b
HW		 1569}
1570
1571/*************************Short Pulse IRQ***************************/
1572
1573static bool hpd_rx_irq_check_link_loss_status(
d0778ebf 1574 struct dc_link *link,
4562236b
HW		 1575 union hpd_irq_data *hpd_irq_dpcd_data)
1576{
97011249 1577 uint8_t irq_reg_rx_power_state = 0;
4562236b
HW		 1578 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1579 union lane_status lane_status;
1580 uint32_t lane;
1581 bool sink_status_changed;
1582 bool return_code;
1583
1584 sink_status_changed = false;
1585 return_code = false;
1586
d0778ebf 1587 if (link->cur_link_settings.lane_count == 0)
4562236b 1588 return return_code;
4562236b 1589
97011249 1590 /*1. Check that Link Status changed, before re-training.*/
4562236b 1591
97011249
HW		 1592 /*parse lane status*/
1593 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1594 /* check status of lanes 0,1
1595 * changed DpcdAddress_Lane01Status (0x202)
1596 */
1597 lane_status.raw = get_nibble_at_index(
1598 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1599 lane);
1600
1601 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1602 !lane_status.bits.CR_DONE_0 ||
1603 !lane_status.bits.SYMBOL_LOCKED_0) {
1604 /* if one of the channel equalization, clock
1605 * recovery or symbol lock is dropped
1606 * consider it as (link has been
1607 * dropped) dp sink status has changed
1608 */
1609 sink_status_changed = true;
1610 break;
1611 }
4562236b
HW		 1612 }
1613
97011249
HW		 1614 /* Check interlane align.*/
1615 if (sink_status_changed ||
1616 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
4562236b 1617
1296423b 1618 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
4562236b 1619
97011249 1620 return_code = true;
4562236b 1621
97011249
HW		 1622 /*2. Check that we can handle interrupt: Not in FS DOS,
1623 * Not in "Display Timeout" state, Link is trained.
1624 */
1625 dpcd_result = core_link_read_dpcd(link,
1626 DP_SET_POWER,
1627 &irq_reg_rx_power_state,
1628 sizeof(irq_reg_rx_power_state));
4562236b 1629
97011249 1630 if (dpcd_result != DC_OK) {
1296423b 1631 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
4562236b 1632 __func__);
97011249
HW		 1633 } else {
1634 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1635 return_code = false;
4562236b
HW		 1636 }
1637 }
1638
1639 return return_code;
1640}
1641
1642static enum dc_status read_hpd_rx_irq_data(
d0778ebf 1643 struct dc_link *link,
4562236b
HW		 1644 union hpd_irq_data *irq_data)
1645{
c733e40c
NC		 1646 static enum dc_status retval;
1647
4562236b
HW		 1648 /* The HW reads 16 bytes from 200h on HPD,
1649 * but if we get an AUX_DEFER, the HW cannot retry
1650 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1651 * fail, so we now explicitly read 6 bytes which is
1652 * the req from the above mentioned test cases.
c733e40c
NC		 1653 *
1654 * For DP 1.4 we need to read those from 2002h range.
4562236b 1655 */
c733e40c
NC		 1656 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1657 retval = core_link_read_dpcd(
1658 link,
1659 DP_SINK_COUNT,
1660 irq_data->raw,
1661 sizeof(union hpd_irq_data));
1662 else {
3c8e4316
NC		 1663 /* Read 14 bytes in a single read and then copy only the required fields.
1664 * This is more efficient than doing it in two separate AUX reads. */
1665
1666 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1667
c733e40c
NC		 1668 retval = core_link_read_dpcd(
1669 link,
1670 DP_SINK_COUNT_ESI,
3c8e4316
NC		 1671 tmp,
1672 sizeof(tmp));
c733e40c
NC		 1673
1674 if (retval != DC_OK)
1675 return retval;
1676
3c8e4316
NC		 1677 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1678 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1679 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1680 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1681 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1682 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
c733e40c
NC		 1683 }
1684
1685 return retval;
4562236b
HW		 1686}
1687
d0778ebf 1688static bool allow_hpd_rx_irq(const struct dc_link *link)
4562236b
HW		 1689{
1690 /*
1691 * Don't handle RX IRQ unless one of following is met:
1692 * 1) The link is established (cur_link_settings != unknown)
1693 * 2) We kicked off MST detection
1694 * 3) We know we're dealing with an active dongle
1695 */
1696
d0778ebf
HW		 1697 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1698 (link->type == dc_connection_mst_branch) ||
4562236b
HW		 1699 is_dp_active_dongle(link))
1700 return true;
1701
1702 return false;
1703}
1704
d0778ebf 1705static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
4562236b
HW		 1706{
1707 union dpcd_psr_configuration psr_configuration;
1708
94267b3d 1709 if (!link->psr_enabled)
4562236b
HW		 1710 return false;
1711
7c7f5b15
AG		 1712 dm_helpers_dp_read_dpcd(
1713 link->ctx,
d0778ebf 1714 link,
7c7f5b15
AG		 1715 368,/*DpcdAddress_PSR_Enable_Cfg*/
1716 &psr_configuration.raw,
1717 sizeof(psr_configuration.raw));
1718
4562236b
HW		 1719
1720 if (psr_configuration.bits.ENABLE) {
1721 unsigned char dpcdbuf[3] = {0};
1722 union psr_error_status psr_error_status;
1723 union psr_sink_psr_status psr_sink_psr_status;
1724
7c7f5b15
AG		 1725 dm_helpers_dp_read_dpcd(
1726 link->ctx,
d0778ebf 1727 link,
7c7f5b15
AG		 1728 0x2006, /*DpcdAddress_PSR_Error_Status*/
1729 (unsigned char *) dpcdbuf,
1730 sizeof(dpcdbuf));
4562236b
HW		 1731
1732 /*DPCD 2006h ERROR STATUS*/
1733 psr_error_status.raw = dpcdbuf[0];
1734 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
1735 psr_sink_psr_status.raw = dpcdbuf[2];
1736
1737 if (psr_error_status.bits.LINK_CRC_ERROR ||
1738 psr_error_status.bits.RFB_STORAGE_ERROR) {
1739 /* Acknowledge and clear error bits */
7c7f5b15
AG		 1740 dm_helpers_dp_write_dpcd(
1741 link->ctx,
d0778ebf 1742 link,
7c7f5b15 1743 8198,/*DpcdAddress_PSR_Error_Status*/
4562236b
HW		 1744 &psr_error_status.raw,
1745 sizeof(psr_error_status.raw));
1746
1747 /* PSR error, disable and re-enable PSR */
c7299705
CL		 1748 dc_link_set_psr_enable(link, false, true);
1749 dc_link_set_psr_enable(link, true, true);
4562236b
HW		 1750
1751 return true;
1752 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
1753 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
1754 /* No error is detect, PSR is active.
1755 * We should return with IRQ_HPD handled without
1756 * checking for loss of sync since PSR would have
1757 * powered down main link.
1758 */
1759 return true;
1760 }
1761 }
1762 return false;
1763}
1764
d0778ebf 1765static void dp_test_send_link_training(struct dc_link *link)
4562236b 1766{
73c72602 1767 struct dc_link_settings link_settings = {0};
4562236b
HW		 1768
1769 core_link_read_dpcd(
1770 link,
3a340294 1771 DP_TEST_LANE_COUNT,
4562236b
HW		 1772 (unsigned char *)(&link_settings.lane_count),
1773 1);
1774 core_link_read_dpcd(
1775 link,
3a340294 1776 DP_TEST_LINK_RATE,
4562236b
HW		 1777 (unsigned char *)(&link_settings.link_rate),
1778 1);
1779
1780 /* Set preferred link settings */
d0778ebf
HW		 1781 link->verified_link_cap.lane_count = link_settings.lane_count;
1782 link->verified_link_cap.link_rate = link_settings.link_rate;
4562236b 1783
73c72602 1784 dp_retrain_link_dp_test(link, &link_settings, false);
4562236b
HW		 1785}
1786
9315e239 1787/* TODO Raven hbr2 compliance eye output is unstable
25bab0da
WL		 1788 * (toggling on and off) with debugger break
1789 * This caueses intermittent PHY automation failure
1790 * Need to look into the root cause */
d0778ebf 1791static void dp_test_send_phy_test_pattern(struct dc_link *link)
4562236b
HW		 1792{
1793 union phy_test_pattern dpcd_test_pattern;
1794 union lane_adjust dpcd_lane_adjustment[2];
1795 unsigned char dpcd_post_cursor_2_adjustment = 0;
1796 unsigned char test_80_bit_pattern[
3a340294
DA		 1797 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1798 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
4562236b
HW		 1799 enum dp_test_pattern test_pattern;
1800 struct dc_link_training_settings link_settings;
1801 union lane_adjust dpcd_lane_adjust;
1802 unsigned int lane;
1803 struct link_training_settings link_training_settings;
1804 int i = 0;
1805
1806 dpcd_test_pattern.raw = 0;
1807 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
1808 memset(&link_settings, 0, sizeof(link_settings));
1809
1810 /* get phy test pattern and pattern parameters from DP receiver */
1811 core_link_read_dpcd(
1812 link,
3a340294 1813 DP_TEST_PHY_PATTERN,
4562236b
HW		 1814 &dpcd_test_pattern.raw,
1815 sizeof(dpcd_test_pattern));
1816 core_link_read_dpcd(
1817 link,
3a340294 1818 DP_ADJUST_REQUEST_LANE0_1,
4562236b
HW		 1819 &dpcd_lane_adjustment[0].raw,
1820 sizeof(dpcd_lane_adjustment));
1821
1822 /*get post cursor 2 parameters
1823 * For DP 1.1a or eariler, this DPCD register's value is 0
1824 * For DP 1.2 or later:
1825 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
1826 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
1827 */
1828 core_link_read_dpcd(
1829 link,
3a340294 1830 DP_ADJUST_REQUEST_POST_CURSOR2,
4562236b
HW		 1831 &dpcd_post_cursor_2_adjustment,
1832 sizeof(dpcd_post_cursor_2_adjustment));
1833
1834 /* translate request */
1835 switch (dpcd_test_pattern.bits.PATTERN) {
1836 case PHY_TEST_PATTERN_D10_2:
1837 test_pattern = DP_TEST_PATTERN_D102;
0e19401f 1838 break;
4562236b
HW		 1839 case PHY_TEST_PATTERN_SYMBOL_ERROR:
1840 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 1841 break;
4562236b
HW		 1842 case PHY_TEST_PATTERN_PRBS7:
1843 test_pattern = DP_TEST_PATTERN_PRBS7;
0e19401f 1844 break;
4562236b
HW		 1845 case PHY_TEST_PATTERN_80BIT_CUSTOM:
1846 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 1847 break;
1848 case PHY_TEST_PATTERN_CP2520_1:
25bab0da 1849 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 1850 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 1851 DP_TEST_PATTERN_TRAINING_PATTERN4 :
1852 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 1853 break;
1854 case PHY_TEST_PATTERN_CP2520_2:
25bab0da 1855 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 1856 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 1857 DP_TEST_PATTERN_TRAINING_PATTERN4 :
1858 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 1859 break;
1860 case PHY_TEST_PATTERN_CP2520_3:
78e685f9 1861 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
0e19401f 1862 break;
4562236b
HW		 1863 default:
1864 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1865 break;
1866 }
1867
1868 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
1869 core_link_read_dpcd(
1870 link,
3a340294 1871 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
4562236b
HW		 1872 test_80_bit_pattern,
1873 sizeof(test_80_bit_pattern));
1874
1875 /* prepare link training settings */
d0778ebf 1876 link_settings.link = link->cur_link_settings;
4562236b
HW		 1877
1878 for (lane = 0; lane <
d0778ebf 1879 (unsigned int)(link->cur_link_settings.lane_count);
4562236b
HW		 1880 lane++) {
1881 dpcd_lane_adjust.raw =
1882 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
1883 link_settings.lane_settings[lane].VOLTAGE_SWING =
1884 (enum dc_voltage_swing)
1885 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
1886 link_settings.lane_settings[lane].PRE_EMPHASIS =
1887 (enum dc_pre_emphasis)
1888 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
1889 link_settings.lane_settings[lane].POST_CURSOR2 =
1890 (enum dc_post_cursor2)
1891 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
1892 }
1893
1894 for (i = 0; i < 4; i++)
1895 link_training_settings.lane_settings[i] =
1896 link_settings.lane_settings[i];
1897 link_training_settings.link_settings = link_settings.link;
1898 link_training_settings.allow_invalid_msa_timing_param = false;
1899 /*Usage: Measure DP physical lane signal
1900 * by DP SI test equipment automatically.
1901 * PHY test pattern request is generated by equipment via HPD interrupt.
1902 * HPD needs to be active all the time. HPD should be active
1903 * all the time. Do not touch it.
1904 * forward request to DS
1905 */
1906 dc_link_dp_set_test_pattern(
d0778ebf 1907 link,
4562236b
HW		 1908 test_pattern,
1909 &link_training_settings,
1910 test_80_bit_pattern,
3a340294
DA		 1911 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1912 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
4562236b
HW		 1913}
1914
d0778ebf 1915static void dp_test_send_link_test_pattern(struct dc_link *link)
4562236b
HW		 1916{
1917 union link_test_pattern dpcd_test_pattern;
1918 union test_misc dpcd_test_params;
1919 enum dp_test_pattern test_pattern;
1920
1921 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
1922 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
1923
1924 /* get link test pattern and pattern parameters */
1925 core_link_read_dpcd(
1926 link,
3a340294 1927 DP_TEST_PATTERN,
4562236b
HW		 1928 &dpcd_test_pattern.raw,
1929 sizeof(dpcd_test_pattern));
1930 core_link_read_dpcd(
1931 link,
3a340294 1932 DP_TEST_MISC0,
4562236b
HW		 1933 &dpcd_test_params.raw,
1934 sizeof(dpcd_test_params));
1935
1936 switch (dpcd_test_pattern.bits.PATTERN) {
1937 case LINK_TEST_PATTERN_COLOR_RAMP:
1938 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1939 break;
1940 case LINK_TEST_PATTERN_VERTICAL_BARS:
1941 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1942 break; /* black and white */
1943 case LINK_TEST_PATTERN_COLOR_SQUARES:
1944 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1945 TEST_DYN_RANGE_VESA ?
1946 DP_TEST_PATTERN_COLOR_SQUARES :
1947 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1948 break;
1949 default:
1950 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1951 break;
1952 }
1953
1954 dc_link_dp_set_test_pattern(
d0778ebf 1955 link,
4562236b
HW		 1956 test_pattern,
1957 NULL,
1958 NULL,
1959 0);
1960}
1961
d0778ebf 1962static void handle_automated_test(struct dc_link *link)
4562236b
HW		 1963{
1964 union test_request test_request;
1965 union test_response test_response;
1966
1967 memset(&test_request, 0, sizeof(test_request));
1968 memset(&test_response, 0, sizeof(test_response));
1969
1970 core_link_read_dpcd(
1971 link,
3a340294 1972 DP_TEST_REQUEST,
4562236b
HW		 1973 &test_request.raw,
1974 sizeof(union test_request));
1975 if (test_request.bits.LINK_TRAINING) {
1976 /* ACK first to let DP RX test box monitor LT sequence */
1977 test_response.bits.ACK = 1;
1978 core_link_write_dpcd(
1979 link,
3a340294 1980 DP_TEST_RESPONSE,
4562236b
HW		 1981 &test_response.raw,
1982 sizeof(test_response));
1983 dp_test_send_link_training(link);
1984 /* no acknowledge request is needed again */
1985 test_response.bits.ACK = 0;
1986 }
1987 if (test_request.bits.LINK_TEST_PATTRN) {
1988 dp_test_send_link_test_pattern(link);
75a74755 1989 test_response.bits.ACK = 1;
4562236b
HW		 1990 }
1991 if (test_request.bits.PHY_TEST_PATTERN) {
1992 dp_test_send_phy_test_pattern(link);
1993 test_response.bits.ACK = 1;
1994 }
1995 if (!test_request.raw)
1996 /* no requests, revert all test signals
1997 * TODO: revert all test signals
1998 */
1999 test_response.bits.ACK = 1;
2000 /* send request acknowledgment */
2001 if (test_response.bits.ACK)
2002 core_link_write_dpcd(
2003 link,
3a340294 2004 DP_TEST_RESPONSE,
4562236b
HW		 2005 &test_response.raw,
2006 sizeof(test_response));
2007}
2008
4e18814e 2009bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
4562236b 2010{
9a6a8075 2011 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
c2e218dd 2012 union device_service_irq device_service_clear = { { 0 } };
d6258eaa 2013 enum dc_status result;
4e18814e 2014
4562236b 2015 bool status = false;
4e18814e
FD		 2016
2017 if (out_link_loss)
2018 *out_link_loss = false;
4562236b
HW		 2019 /* For use cases related to down stream connection status change,
2020 * PSR and device auto test, refer to function handle_sst_hpd_irq
2021 * in DAL2.1*/
2022
1296423b 2023 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
d0778ebf 2024 __func__, link->link_index);
4562236b 2025
8ee65d7c 2026
4562236b
HW		 2027 /* All the "handle_hpd_irq_xxx()" methods
2028 * should be called only after
2029 * dal_dpsst_ls_read_hpd_irq_data
2030 * Order of calls is important too
2031 */
2032 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
8ee65d7c
WL		 2033 if (out_hpd_irq_dpcd_data)
2034 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4562236b
HW		 2035
2036 if (result != DC_OK) {
1296423b 2037 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
4562236b
HW		 2038 __func__);
2039 return false;
2040 }
2041
2042 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2043 device_service_clear.bits.AUTOMATED_TEST = 1;
2044 core_link_write_dpcd(
2045 link,
3a340294 2046 DP_DEVICE_SERVICE_IRQ_VECTOR,
4562236b
HW		 2047 &device_service_clear.raw,
2048 sizeof(device_service_clear.raw));
2049 device_service_clear.raw = 0;
2050 handle_automated_test(link);
2051 return false;
2052 }
2053
2054 if (!allow_hpd_rx_irq(link)) {
1296423b 2055 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
d0778ebf 2056 __func__, link->link_index);
4562236b
HW		 2057 return false;
2058 }
2059
2060 if (handle_hpd_irq_psr_sink(link))
2061 /* PSR-related error was detected and handled */
2062 return true;
2063
2064 /* If PSR-related error handled, Main link may be off,
2065 * so do not handle as a normal sink status change interrupt.
2066 */
2067
aaa15026
WL		 2068 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2069 return true;
2070
4562236b 2071 /* check if we have MST msg and return since we poll for it */
aaa15026 2072 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
4562236b
HW		 2073 return false;
2074
2075 /* For now we only handle 'Downstream port status' case.
2076 * If we got sink count changed it means
2077 * Downstream port status changed,
2078 * then DM should call DC to do the detection. */
2079 if (hpd_rx_irq_check_link_loss_status(
2080 link,
2081 &hpd_irq_dpcd_data)) {
2082 /* Connectivity log: link loss */
2083 CONN_DATA_LINK_LOSS(link,
2084 hpd_irq_dpcd_data.raw,
2085 sizeof(hpd_irq_dpcd_data),
2086 "Status: ");
2087
2088 perform_link_training_with_retries(link,
d0778ebf 2089 &link->cur_link_settings,
4562236b
HW		 2090 true, LINK_TRAINING_ATTEMPTS);
2091
2092 status = false;
4e18814e
FD		 2093 if (out_link_loss)
2094 *out_link_loss = true;
4562236b
HW		 2095 }
2096
d0778ebf 2097 if (link->type == dc_connection_active_dongle &&
4562236b
HW		 2098 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
2099 != link->dpcd_sink_count)
2100 status = true;
2101
2102 /* reasons for HPD RX:
2103 * 1. Link Loss - ie Re-train the Link
2104 * 2. MST sideband message
2105 * 3. Automated Test - ie. Internal Commit
2106 * 4. CP (copy protection) - (not interesting for DM???)
2107 * 5. DRR
2108 * 6. Downstream Port status changed
2109 * -ie. Detect - this the only one
2110 * which is interesting for DM because
2111 * it must call dc_link_detect.
2112 */
2113 return status;
2114}
2115
2116/*query dpcd for version and mst cap addresses*/
d0778ebf 2117bool is_mst_supported(struct dc_link *link)
4562236b
HW		 2118{
2119 bool mst = false;
2120 enum dc_status st = DC_OK;
2121 union dpcd_rev rev;
2122 union mstm_cap cap;
2123
2124 rev.raw = 0;
2125 cap.raw = 0;
2126
3a340294 2127 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4562236b
HW		 2128 sizeof(rev));
2129
2130 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2131
3a340294 2132 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4562236b
HW		 2133 &cap.raw, sizeof(cap));
2134 if (st == DC_OK && cap.bits.MST_CAP == 1)
2135 mst = true;
2136 }
2137 return mst;
2138
2139}
2140
d0778ebf 2141bool is_dp_active_dongle(const struct dc_link *link)
4562236b
HW		 2142{
2143 enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
2144
2145 return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
2146 (dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
2147 (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
2148}
2149
6bffebc9
EY		 2150static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
2151{
2152 switch (bpc) {
2153 case DOWN_STREAM_MAX_8BPC:
2154 return 8;
2155 case DOWN_STREAM_MAX_10BPC:
2156 return 10;
2157 case DOWN_STREAM_MAX_12BPC:
2158 return 12;
2159 case DOWN_STREAM_MAX_16BPC:
2160 return 16;
2161 default:
2162 break;
2163 }
2164
2165 return -1;
2166}
2167
4562236b 2168static void get_active_converter_info(
d0778ebf 2169 uint8_t data, struct dc_link *link)
4562236b
HW		 2170{
2171 union dp_downstream_port_present ds_port = { .byte = data };
2172
2173 /* decode converter info*/
2174 if (!ds_port.fields.PORT_PRESENT) {
2175 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
d0778ebf 2176 ddc_service_set_dongle_type(link->ddc,
4562236b
HW		 2177 link->dpcd_caps.dongle_type);
2178 return;
2179 }
2180
2181 switch (ds_port.fields.PORT_TYPE) {
2182 case DOWNSTREAM_VGA:
2183 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
2184 break;
2185 case DOWNSTREAM_DVI_HDMI:
2186 /* At this point we don't know is it DVI or HDMI,
2187 * assume DVI.*/
2188 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
2189 break;
2190 default:
2191 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2192 break;
2193 }
2194
ac0e562c 2195 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
4562236b
HW		 2196 uint8_t det_caps[4];
2197 union dwnstream_port_caps_byte0 *port_caps =
2198 (union dwnstream_port_caps_byte0 *)det_caps;
3a340294 2199 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
4562236b
HW		 2200 det_caps, sizeof(det_caps));
2201
2202 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
2203 case DOWN_STREAM_DETAILED_VGA:
2204 link->dpcd_caps.dongle_type =
2205 DISPLAY_DONGLE_DP_VGA_CONVERTER;
2206 break;
2207 case DOWN_STREAM_DETAILED_DVI:
2208 link->dpcd_caps.dongle_type =
2209 DISPLAY_DONGLE_DP_DVI_CONVERTER;
2210 break;
2211 case DOWN_STREAM_DETAILED_HDMI:
2212 link->dpcd_caps.dongle_type =
2213 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
2214
03f5c686 2215 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
4562236b
HW		 2216 if (ds_port.fields.DETAILED_CAPS) {
2217
2218 union dwnstream_port_caps_byte3_hdmi
2219 hdmi_caps = {.raw = det_caps[3] };
7d8d90d8 2220 union dwnstream_port_caps_byte2
03f5c686
CL		 2221 hdmi_color_caps = {.raw = det_caps[2] };
2222 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
2223 det_caps[1] * 25000;
4562236b 2224
03f5c686 2225 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
4562236b 2226 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
03f5c686
CL		 2227 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
2228 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
2229 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
2230 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
2231 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
2232 hdmi_caps.bits.YCrCr422_CONVERSION;
2233 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
2234 hdmi_caps.bits.YCrCr420_CONVERSION;
2235
2236 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
6bffebc9
EY		 2237 translate_dpcd_max_bpc(
2238 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
03f5c686
CL		 2239
2240 link->dpcd_caps.dongle_caps.extendedCapValid = true;
4562236b 2241 }
03f5c686 2242
4562236b
HW		 2243 break;
2244 }
2245 }
2246
d0778ebf 2247 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4562236b
HW		 2248
2249 {
2250 struct dp_device_vendor_id dp_id;
2251
2252 /* read IEEE branch device id */
2253 core_link_read_dpcd(
2254 link,
3a340294 2255 DP_BRANCH_OUI,
4562236b
HW		 2256 (uint8_t *)&dp_id,
2257 sizeof(dp_id));
2258
2259 link->dpcd_caps.branch_dev_id =
2260 (dp_id.ieee_oui[0] << 16) +
2261 (dp_id.ieee_oui[1] << 8) +
2262 dp_id.ieee_oui[2];
2263
2264 memmove(
2265 link->dpcd_caps.branch_dev_name,
2266 dp_id.ieee_device_id,
2267 sizeof(dp_id.ieee_device_id));
2268 }
2269
2270 {
2271 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2272
2273 core_link_read_dpcd(
2274 link,
3a340294 2275 DP_BRANCH_REVISION_START,
4562236b
HW		 2276 (uint8_t *)&dp_hw_fw_revision,
2277 sizeof(dp_hw_fw_revision));
2278
2279 link->dpcd_caps.branch_hw_revision =
2280 dp_hw_fw_revision.ieee_hw_rev;
4b99affb
A		 2281
2282 memmove(
2283 link->dpcd_caps.branch_fw_revision,
2284 dp_hw_fw_revision.ieee_fw_rev,
2285 sizeof(dp_hw_fw_revision.ieee_fw_rev));
4562236b
HW		 2286 }
2287}
2288
d0778ebf 2289static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4562236b
HW		 2290 int length)
2291{
2292 int retry = 0;
2293 union dp_downstream_port_present ds_port = { 0 };
2294
2295 if (!link->dpcd_caps.dpcd_rev.raw) {
2296 do {
2297 dp_receiver_power_ctrl(link, true);
3a340294 2298 core_link_read_dpcd(link, DP_DPCD_REV,
4562236b
HW		 2299 dpcd_data, length);
2300 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3a340294
DA		 2301 DP_DPCD_REV -
2302 DP_DPCD_REV];
4562236b
HW		 2303 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
2304 }
2305
3a340294
DA		 2306 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2307 DP_DPCD_REV];
4562236b
HW		 2308
2309 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
2310 switch (link->dpcd_caps.branch_dev_id) {
2311 /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
2312 * all internal circuits including AUX communication preventing
2313 * reading DPCD table and EDID (spec violation).
2314 * Encoder will skip DP RX power down on disable_output to
2315 * keep receiver powered all the time.*/
2316 case DP_BRANCH_DEVICE_ID_1:
2317 case DP_BRANCH_DEVICE_ID_4:
2318 link->wa_flags.dp_keep_receiver_powered = true;
2319 break;
2320
2321 /* TODO: May need work around for other dongles. */
2322 default:
2323 link->wa_flags.dp_keep_receiver_powered = false;
2324 break;
2325 }
2326 } else
2327 link->wa_flags.dp_keep_receiver_powered = false;
2328}
2329
cdb39798 2330static bool retrieve_link_cap(struct dc_link *link)
4562236b 2331{
794550c6 2332 uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
4562236b 2333
8ca80900 2334 struct dp_device_vendor_id sink_id;
4562236b
HW		 2335 union down_stream_port_count down_strm_port_count;
2336 union edp_configuration_cap edp_config_cap;
2337 union dp_downstream_port_present ds_port = { 0 };
cdb39798 2338 enum dc_status status = DC_ERROR_UNEXPECTED;
3c1a312a
YS		 2339 uint32_t read_dpcd_retry_cnt = 3;
2340 int i;
4b99affb 2341 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
4562236b
HW		 2342
2343 memset(dpcd_data, '\0', sizeof(dpcd_data));
2344 memset(&down_strm_port_count,
2345 '\0', sizeof(union down_stream_port_count));
2346 memset(&edp_config_cap, '\0',
2347 sizeof(union edp_configuration_cap));
2348
3c1a312a
YS		 2349 for (i = 0; i < read_dpcd_retry_cnt; i++) {
2350 status = core_link_read_dpcd(
2351 link,
2352 DP_DPCD_REV,
2353 dpcd_data,
2354 sizeof(dpcd_data));
2355 if (status == DC_OK)
2356 break;
2357 }
cdb39798
YS		 2358
2359 if (status != DC_OK) {
2360 dm_error("%s: Read dpcd data failed.\n", __func__);
2361 return false;
2362 }
4562236b 2363
4562236b
HW		 2364 {
2365 union training_aux_rd_interval aux_rd_interval;
2366
2367 aux_rd_interval.raw =
3a340294 2368 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
4562236b
HW		 2369
2370 if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
2371 core_link_read_dpcd(
2372 link,
3a340294 2373 DP_DP13_DPCD_REV,
4562236b
HW		 2374 dpcd_data,
2375 sizeof(dpcd_data));
2376 }
2377 }
2378
cc04bf7e
TC		 2379 link->dpcd_caps.dpcd_rev.raw =
2380 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
2381
3a340294
DA		 2382 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2383 DP_DPCD_REV];
4562236b
HW		 2384
2385 get_active_converter_info(ds_port.byte, link);
2386
2387 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2388
2389 link->dpcd_caps.allow_invalid_MSA_timing_param =
2390 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2391
2392 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3a340294 2393 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4562236b
HW		 2394
2395 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3a340294 2396 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4562236b 2397
d0778ebf 2398 link->reported_link_cap.lane_count =
4562236b 2399 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
d0778ebf 2400 link->reported_link_cap.link_rate = dpcd_data[
3a340294 2401 DP_MAX_LINK_RATE - DP_DPCD_REV];
d0778ebf 2402 link->reported_link_cap.link_spread =
4562236b
HW		 2403 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
2404 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
2405
2406 edp_config_cap.raw = dpcd_data[
3a340294 2407 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4562236b
HW		 2408 link->dpcd_caps.panel_mode_edp =
2409 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
9799624a
WL		 2410 link->dpcd_caps.dpcd_display_control_capable =
2411 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4562236b 2412
d0778ebf
HW		 2413 link->test_pattern_enabled = false;
2414 link->compliance_test_state.raw = 0;
4562236b 2415
4562236b
HW		 2416 /* read sink count */
2417 core_link_read_dpcd(link,
3a340294 2418 DP_SINK_COUNT,
4562236b
HW		 2419 &link->dpcd_caps.sink_count.raw,
2420 sizeof(link->dpcd_caps.sink_count.raw));
2421
8ca80900
AK		 2422 /* read sink ieee oui */
2423 core_link_read_dpcd(link,
2424 DP_SINK_OUI,
2425 (uint8_t *)(&sink_id),
2426 sizeof(sink_id));
2427
2428 link->dpcd_caps.sink_dev_id =
2429 (sink_id.ieee_oui[0] << 16) +
2430 (sink_id.ieee_oui[1] << 8) +
2431 (sink_id.ieee_oui[2]);
2432
4b99affb
A		 2433 memmove(
2434 link->dpcd_caps.sink_dev_id_str,
2435 sink_id.ieee_device_id,
2436 sizeof(sink_id.ieee_device_id));
2437
2438 core_link_read_dpcd(
2439 link,
2440 DP_SINK_HW_REVISION_START,
2441 (uint8_t *)&dp_hw_fw_revision,
2442 sizeof(dp_hw_fw_revision));
2443
2444 link->dpcd_caps.sink_hw_revision =
2445 dp_hw_fw_revision.ieee_hw_rev;
2446
2447 memmove(
2448 link->dpcd_caps.sink_fw_revision,
2449 dp_hw_fw_revision.ieee_fw_rev,
2450 sizeof(dp_hw_fw_revision.ieee_fw_rev));
2451
4562236b
HW		 2452 /* Connectivity log: detection */
2453 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
cdb39798
YS		 2454
2455 return true;
4562236b
HW		 2456}
2457
cdb39798 2458bool detect_dp_sink_caps(struct dc_link *link)
4562236b 2459{
cdb39798 2460 return retrieve_link_cap(link);
4562236b
HW		 2461
2462 /* dc init_hw has power encoder using default
2463 * signal for connector. For native DP, no
2464 * need to power up encoder again. If not native
2465 * DP, hw_init may need check signal or power up
2466 * encoder here.
2467 */
4562236b
HW		 2468 /* TODO save sink caps in link->sink */
2469}
2470
4654a2f7
RL		 2471void detect_edp_sink_caps(struct dc_link *link)
2472{
2473 retrieve_link_cap(link);
48231fd5
HW		 2474
2475 if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
2476 link->reported_link_cap.link_rate = LINK_RATE_HIGH2;
2477
4654a2f7
RL		 2478 link->verified_link_cap = link->reported_link_cap;
2479}
2480
4562236b
HW		 2481void dc_link_dp_enable_hpd(const struct dc_link *link)
2482{
d0778ebf 2483 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2484
2485 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2486 encoder->funcs->enable_hpd(encoder);
2487}
2488
2489void dc_link_dp_disable_hpd(const struct dc_link *link)
2490{
d0778ebf 2491 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2492
2493 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2494 encoder->funcs->disable_hpd(encoder);
2495}
2496
2497static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
2498{
0e19401f
TC		 2499 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
2500 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
2501 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4562236b
HW		 2502 return true;
2503 else
2504 return false;
2505}
2506
d0778ebf 2507static void set_crtc_test_pattern(struct dc_link *link,
4562236b
HW		 2508 struct pipe_ctx *pipe_ctx,
2509 enum dp_test_pattern test_pattern)
2510{
2511 enum controller_dp_test_pattern controller_test_pattern;
2512 enum dc_color_depth color_depth = pipe_ctx->
4fa086b9 2513 stream->timing.display_color_depth;
4562236b
HW		 2514 struct bit_depth_reduction_params params;
2515
2516 memset(&params, 0, sizeof(params));
2517
2518 switch (test_pattern) {
2519 case DP_TEST_PATTERN_COLOR_SQUARES:
2520 controller_test_pattern =
2521 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2522 break;
2523 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2524 controller_test_pattern =
2525 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
2526 break;
2527 case DP_TEST_PATTERN_VERTICAL_BARS:
2528 controller_test_pattern =
2529 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
2530 break;
2531 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2532 controller_test_pattern =
2533 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
2534 break;
2535 case DP_TEST_PATTERN_COLOR_RAMP:
2536 controller_test_pattern =
2537 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
2538 break;
2539 default:
2540 controller_test_pattern =
2541 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
2542 break;
2543 }
2544
2545 switch (test_pattern) {
2546 case DP_TEST_PATTERN_COLOR_SQUARES:
2547 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2548 case DP_TEST_PATTERN_VERTICAL_BARS:
2549 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2550 case DP_TEST_PATTERN_COLOR_RAMP:
2551 {
2552 /* disable bit depth reduction */
2553 pipe_ctx->stream->bit_depth_params = params;
a6a6cb34
HW		 2554 pipe_ctx->stream_res.opp->funcs->
2555 opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
7f93c1de
CL		 2556 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2557 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 2558 controller_test_pattern, color_depth);
2559 }
2560 break;
2561 case DP_TEST_PATTERN_VIDEO_MODE:
2562 {
2563 /* restore bitdepth reduction */
529cad0f 2564 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
4562236b
HW		 2565 &params);
2566 pipe_ctx->stream->bit_depth_params = params;
a6a6cb34
HW		 2567 pipe_ctx->stream_res.opp->funcs->
2568 opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
7f93c1de
CL		 2569 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2570 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 2571 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2572 color_depth);
2573 }
2574 break;
2575
2576 default:
2577 break;
2578 }
2579}
2580
2581bool dc_link_dp_set_test_pattern(
d0778ebf 2582 struct dc_link *link,
4562236b
HW		 2583 enum dp_test_pattern test_pattern,
2584 const struct link_training_settings *p_link_settings,
2585 const unsigned char *p_custom_pattern,
2586 unsigned int cust_pattern_size)
2587{
608ac7bb 2588 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
0a8f43ff 2589 struct pipe_ctx *pipe_ctx = &pipes[0];
4562236b
HW		 2590 unsigned int lane;
2591 unsigned int i;
2592 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
2593 union dpcd_training_pattern training_pattern;
4562236b
HW		 2594 enum dpcd_phy_test_patterns pattern;
2595
2596 memset(&training_pattern, 0, sizeof(training_pattern));
4562236b
HW		 2597
2598 for (i = 0; i < MAX_PIPES; i++) {
d0778ebf 2599 if (pipes[i].stream->sink->link == link) {
0a8f43ff 2600 pipe_ctx = &pipes[i];
4562236b
HW		 2601 break;
2602 }
2603 }
2604
2605 /* Reset CRTC Test Pattern if it is currently running and request
2606 * is VideoMode Reset DP Phy Test Pattern if it is currently running
2607 * and request is VideoMode
2608 */
d0778ebf 2609 if (link->test_pattern_enabled && test_pattern ==
4562236b
HW		 2610 DP_TEST_PATTERN_VIDEO_MODE) {
2611 /* Set CRTC Test Pattern */
0a8f43ff 2612 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
d0778ebf 2613 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 2614 (uint8_t *)p_custom_pattern,
2615 (uint32_t)cust_pattern_size);
2616
2617 /* Unblank Stream */
d0778ebf 2618 link->dc->hwss.unblank_stream(
0a8f43ff 2619 pipe_ctx,
d0778ebf 2620 &link->verified_link_cap);
4562236b
HW		 2621 /* TODO:m_pHwss->MuteAudioEndpoint
2622 * (pPathMode->pDisplayPath, false);
2623 */
2624
2625 /* Reset Test Pattern state */
d0778ebf 2626 link->test_pattern_enabled = false;
4562236b
HW		 2627
2628 return true;
2629 }
2630
2631 /* Check for PHY Test Patterns */
2632 if (is_dp_phy_pattern(test_pattern)) {
2633 /* Set DPCD Lane Settings before running test pattern */
2634 if (p_link_settings != NULL) {
d0778ebf
HW		 2635 dp_set_hw_lane_settings(link, p_link_settings);
2636 dpcd_set_lane_settings(link, p_link_settings);
4562236b
HW		 2637 }
2638
2639 /* Blank stream if running test pattern */
2640 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2641 /*TODO:
2642 * m_pHwss->
2643 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
2644 */
2645 /* Blank stream */
8e9c4c8c 2646 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4562236b
HW		 2647 }
2648
d0778ebf 2649 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 2650 (uint8_t *)p_custom_pattern,
2651 (uint32_t)cust_pattern_size);
2652
2653 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2654 /* Set Test Pattern state */
d0778ebf 2655 link->test_pattern_enabled = true;
4562236b 2656 if (p_link_settings != NULL)
d0778ebf 2657 dpcd_set_link_settings(link,
4562236b
HW		 2658 p_link_settings);
2659 }
2660
2661 switch (test_pattern) {
2662 case DP_TEST_PATTERN_VIDEO_MODE:
2663 pattern = PHY_TEST_PATTERN_NONE;
0e19401f 2664 break;
4562236b
HW		 2665 case DP_TEST_PATTERN_D102:
2666 pattern = PHY_TEST_PATTERN_D10_2;
0e19401f 2667 break;
4562236b
HW		 2668 case DP_TEST_PATTERN_SYMBOL_ERROR:
2669 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 2670 break;
4562236b
HW		 2671 case DP_TEST_PATTERN_PRBS7:
2672 pattern = PHY_TEST_PATTERN_PRBS7;
0e19401f 2673 break;
4562236b
HW		 2674 case DP_TEST_PATTERN_80BIT_CUSTOM:
2675 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 2676 break;
2677 case DP_TEST_PATTERN_CP2520_1:
2678 pattern = PHY_TEST_PATTERN_CP2520_1;
2679 break;
2680 case DP_TEST_PATTERN_CP2520_2:
2681 pattern = PHY_TEST_PATTERN_CP2520_2;
2682 break;
2683 case DP_TEST_PATTERN_CP2520_3:
2684 pattern = PHY_TEST_PATTERN_CP2520_3;
2685 break;
4562236b
HW		 2686 default:
2687 return false;
2688 }
2689
2690 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
2691 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
2692 return false;
2693
d0778ebf 2694 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 2695 /* tell receiver that we are sending qualification
2696 * pattern DP 1.2 or later - DP receiver's link quality
2697 * pattern is set using DPCD LINK_QUAL_LANEx_SET
2698 * register (0x10B~0x10E)\
2699 */
2700 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
2701 link_qual_pattern[lane] =
2702 (unsigned char)(pattern);
2703
d0778ebf 2704 core_link_write_dpcd(link,
3a340294 2705 DP_LINK_QUAL_LANE0_SET,
4562236b
HW		 2706 link_qual_pattern,
2707 sizeof(link_qual_pattern));
d0778ebf
HW		 2708 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
2709 link->dpcd_caps.dpcd_rev.raw == 0) {
4562236b
HW		 2710 /* tell receiver that we are sending qualification
2711 * pattern DP 1.1a or earlier - DP receiver's link
2712 * quality pattern is set using
2713 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
2714 * register (0x102). We will use v_1.3 when we are
2715 * setting test pattern for DP 1.1.
2716 */
d0778ebf
HW		 2717 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
2718 &training_pattern.raw,
2719 sizeof(training_pattern));
4562236b 2720 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
d0778ebf
HW		 2721 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
2722 &training_pattern.raw,
2723 sizeof(training_pattern));
4562236b
HW		 2724 }
2725 } else {
2726 /* CRTC Patterns */
0a8f43ff 2727 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
4562236b 2728 /* Set Test Pattern state */
d0778ebf 2729 link->test_pattern_enabled = true;
4562236b
HW		 2730 }
2731
2732 return true;
2733}
07c84c7a 2734
d0778ebf 2735void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
07c84c7a
DW		 2736{
2737 unsigned char mstmCntl;
2738
2739 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2740 if (enable)
2741 mstmCntl |= DP_MST_EN;
2742 else
2743 mstmCntl &= (~DP_MST_EN);
2744
2745 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2746}
Linux 6.x block layer and io_uring tree(s)