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drm/amd/display: Improve sharing of HUBBUB register lists
[linux-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
CommitLineData
4562236b
HW		 1/* Copyright 2015 Advanced Micro Devices, Inc. */
2#include "dm_services.h"
3#include "dc.h"
4#include "dc_link_dp.h"
5#include "dm_helpers.h"
7f93c1de 6#include "opp.h"
97bda032
HW		 7#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
8#include "dsc.h"
9#endif
6fbefb84
HW		 10#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
11#include "resource.h"
12#endif
4562236b
HW		 13
14#include "inc/core_types.h"
15#include "link_hwss.h"
16#include "dc_link_ddc.h"
17#include "core_status.h"
18#include "dpcd_defs.h"
19
529cad0f 20#include "resource.h"
1296423b
BL		 21#define DC_LOGGER \
22 link->ctx->logger
4562236b
HW		 23
24/* maximum pre emphasis level allowed for each voltage swing level*/
25static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
26 PRE_EMPHASIS_LEVEL3,
27 PRE_EMPHASIS_LEVEL2,
28 PRE_EMPHASIS_LEVEL1,
29 PRE_EMPHASIS_DISABLED };
30
31enum {
32 POST_LT_ADJ_REQ_LIMIT = 6,
33 POST_LT_ADJ_REQ_TIMEOUT = 200
34};
35
36enum {
37 LINK_TRAINING_MAX_RETRY_COUNT = 5,
38 /* to avoid infinite loop where-in the receiver
39 * switches between different VS
40 */
41 LINK_TRAINING_MAX_CR_RETRY = 100
42};
43
04e21292
DA		 44static bool decide_fallback_link_setting(
45 struct dc_link_settings initial_link_settings,
46 struct dc_link_settings *current_link_setting,
47 enum link_training_result training_result);
9a6a8075 48static struct dc_link_settings get_common_supported_link_settings(
04e21292
DA		 49 struct dc_link_settings link_setting_a,
50 struct dc_link_settings link_setting_b);
51
e0a6440a 52static uint32_t get_training_aux_rd_interval(
d0778ebf 53 struct dc_link *link,
4562236b
HW		 54 uint32_t default_wait_in_micro_secs)
55{
d6d36b55
NC		 56 union training_aux_rd_interval training_rd_interval;
57
58 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
4562236b
HW		 59
60 /* overwrite the delay if rev > 1.1*/
61 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
62 /* DP 1.2 or later - retrieve delay through
63 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
64 core_link_read_dpcd(
65 link,
3a340294 66 DP_TRAINING_AUX_RD_INTERVAL,
4562236b
HW		 67 (uint8_t *)&training_rd_interval,
68 sizeof(training_rd_interval));
69
70 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
e0a6440a 71 default_wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
4562236b
HW		 72 }
73
e0a6440a
DG		 74 return default_wait_in_micro_secs;
75}
76
77static void wait_for_training_aux_rd_interval(
78 struct dc_link *link,
79 uint32_t wait_in_micro_secs)
80{
81 udelay(wait_in_micro_secs);
4562236b 82
1296423b 83 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
4562236b 84 __func__,
e0a6440a 85 wait_in_micro_secs);
4562236b
HW		 86}
87
88static void dpcd_set_training_pattern(
d0778ebf 89 struct dc_link *link,
4562236b
HW		 90 union dpcd_training_pattern dpcd_pattern)
91{
92 core_link_write_dpcd(
93 link,
3a340294 94 DP_TRAINING_PATTERN_SET,
4562236b
HW		 95 &dpcd_pattern.raw,
96 1);
97
1296423b 98 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
4562236b 99 __func__,
3a340294 100 DP_TRAINING_PATTERN_SET,
4562236b
HW		 101 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
102}
103
e0a6440a 104static enum dc_dp_training_pattern get_supported_tp(struct dc_link *link)
16b6253a 105{
e0a6440a 106 enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
16b6253a 107 struct encoder_feature_support *features = &link->link_enc->features;
108 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
109
110 if (features->flags.bits.IS_TPS3_CAPABLE)
e0a6440a 111 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
16b6253a 112
113 if (features->flags.bits.IS_TPS4_CAPABLE)
e0a6440a 114 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
16b6253a 115
116 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
e0a6440a
DG		 117 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
118 return DP_TRAINING_PATTERN_SEQUENCE_4;
16b6253a 119
120 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
e0a6440a
DG		 121 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
122 return DP_TRAINING_PATTERN_SEQUENCE_3;
16b6253a 123
e0a6440a 124 return DP_TRAINING_PATTERN_SEQUENCE_2;
16b6253a 125}
126
4562236b 127static void dpcd_set_link_settings(
d0778ebf 128 struct dc_link *link,
4562236b
HW		 129 const struct link_training_settings *lt_settings)
130{
8628d02f 131 uint8_t rate;
4562236b 132
9a6a8075
HW		 133 union down_spread_ctrl downspread = { {0} };
134 union lane_count_set lane_count_set = { {0} };
e0a6440a 135 enum dc_dp_training_pattern dp_tr_pattern;
4562236b
HW		 136
137 downspread.raw = (uint8_t)
138 (lt_settings->link_settings.link_spread);
139
140 lane_count_set.bits.LANE_COUNT_SET =
141 lt_settings->link_settings.lane_count;
142
e0a6440a 143 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
16b6253a 144 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
145
e0a6440a
DG		 146 dp_tr_pattern = get_supported_tp(link);
147
148 if (dp_tr_pattern != DP_TRAINING_PATTERN_SEQUENCE_4) {
16b6253a 149 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
150 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
151 }
4562236b 152
3a340294 153 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
e0a6440a 154 &downspread.raw, sizeof(downspread));
4562236b 155
8628d02f 156 core_link_write_dpcd(link, DP_LANE_COUNT_SET,
e0a6440a 157 &lane_count_set.raw, 1);
8628d02f 158
b03a599b 159 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
8628d02f
JP		 160 lt_settings->link_settings.use_link_rate_set == true) {
161 rate = 0;
162 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
b03a599b 163 core_link_write_dpcd(link, DP_LINK_RATE_SET,
8628d02f
JP		 164 &lt_settings->link_settings.link_rate_set, 1);
165 } else {
166 rate = (uint8_t) (lt_settings->link_settings.link_rate);
167 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
b03a599b
DL		 168 }
169
8628d02f 170 if (rate) {
e0a6440a 171 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
8628d02f
JP		 172 __func__,
173 DP_LINK_BW_SET,
174 lt_settings->link_settings.link_rate,
175 DP_LANE_COUNT_SET,
176 lt_settings->link_settings.lane_count,
e0a6440a 177 lt_settings->enhanced_framing,
8628d02f
JP		 178 DP_DOWNSPREAD_CTRL,
179 lt_settings->link_settings.link_spread);
180 } else {
e0a6440a 181 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
8628d02f
JP		 182 __func__,
183 DP_LINK_RATE_SET,
184 lt_settings->link_settings.link_rate_set,
185 DP_LANE_COUNT_SET,
186 lt_settings->link_settings.lane_count,
e0a6440a 187 lt_settings->enhanced_framing,
8628d02f
JP		 188 DP_DOWNSPREAD_CTRL,
189 lt_settings->link_settings.link_spread);
190 }
4562236b
HW		 191}
192
193static enum dpcd_training_patterns
e0a6440a 194 dc_dp_training_pattern_to_dpcd_training_pattern(
d0778ebf 195 struct dc_link *link,
e0a6440a 196 enum dc_dp_training_pattern pattern)
4562236b
HW		 197{
198 enum dpcd_training_patterns dpcd_tr_pattern =
199 DPCD_TRAINING_PATTERN_VIDEOIDLE;
200
201 switch (pattern) {
e0a6440a 202 case DP_TRAINING_PATTERN_SEQUENCE_1:
4562236b
HW		 203 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
204 break;
e0a6440a 205 case DP_TRAINING_PATTERN_SEQUENCE_2:
4562236b
HW		 206 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
207 break;
e0a6440a 208 case DP_TRAINING_PATTERN_SEQUENCE_3:
4562236b
HW		 209 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
210 break;
e0a6440a 211 case DP_TRAINING_PATTERN_SEQUENCE_4:
4562236b
HW		 212 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
213 break;
214 default:
215 ASSERT(0);
1296423b 216 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
4562236b
HW		 217 __func__, pattern);
218 break;
219 }
220
221 return dpcd_tr_pattern;
4562236b
HW		 222}
223
224static void dpcd_set_lt_pattern_and_lane_settings(
d0778ebf 225 struct dc_link *link,
4562236b 226 const struct link_training_settings *lt_settings,
e0a6440a 227 enum dc_dp_training_pattern pattern)
4562236b 228{
9a6a8075 229 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
4562236b 230 const uint32_t dpcd_base_lt_offset =
3a340294 231 DP_TRAINING_PATTERN_SET;
4562236b 232 uint8_t dpcd_lt_buffer[5] = {0};
9a6a8075 233 union dpcd_training_pattern dpcd_pattern = { {0} };
4562236b
HW		 234 uint32_t lane;
235 uint32_t size_in_bytes;
236 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
237
238 /*****************************************************************
239 * DpcdAddress_TrainingPatternSet
240 *****************************************************************/
241 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
e0a6440a 242 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
4562236b 243
3a340294 244 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
4562236b
HW		 245 = dpcd_pattern.raw;
246
1296423b 247 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
4562236b 248 __func__,
3a340294 249 DP_TRAINING_PATTERN_SET,
4562236b
HW		 250 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
251
252 /*****************************************************************
253 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
254 *****************************************************************/
255 for (lane = 0; lane <
256 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
257
258 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
259 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
260 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
261 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
262
263 dpcd_lane[lane].bits.MAX_SWING_REACHED =
264 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
265 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
266 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
267 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
268 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
269 }
270
271 /* concatinate everything into one buffer*/
272
273 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
274
275 // 0x00103 - 0x00102
276 memmove(
3a340294 277 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
4562236b
HW		 278 dpcd_lane,
279 size_in_bytes);
280
1296423b 281 DC_LOG_HW_LINK_TRAINING("%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
4562236b 282 __func__,
3a340294 283 DP_TRAINING_LANE0_SET,
4562236b
HW		 284 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
285 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
286 dpcd_lane[0].bits.MAX_SWING_REACHED,
287 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
288
289 if (edp_workaround) {
290 /* for eDP write in 2 parts because the 5-byte burst is
291 * causing issues on some eDP panels (EPR#366724)
292 */
293 core_link_write_dpcd(
294 link,
3a340294 295 DP_TRAINING_PATTERN_SET,
4562236b 296 &dpcd_pattern.raw,
9a6a8075 297 sizeof(dpcd_pattern.raw));
4562236b
HW		 298
299 core_link_write_dpcd(
300 link,
3a340294 301 DP_TRAINING_LANE0_SET,
4562236b
HW		 302 (uint8_t *)(dpcd_lane),
303 size_in_bytes);
304
305 } else
306 /* write it all in (1 + number-of-lanes)-byte burst*/
307 core_link_write_dpcd(
308 link,
309 dpcd_base_lt_offset,
310 dpcd_lt_buffer,
9a6a8075 311 size_in_bytes + sizeof(dpcd_pattern.raw));
4562236b 312
d0778ebf 313 link->cur_lane_setting = lt_settings->lane_settings[0];
4562236b
HW		 314}
315
316static bool is_cr_done(enum dc_lane_count ln_count,
317 union lane_status *dpcd_lane_status)
318{
319 bool done = true;
320 uint32_t lane;
321 /*LANEx_CR_DONE bits All 1's?*/
322 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
323 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
324 done = false;
325 }
326 return done;
327
328}
329
330static bool is_ch_eq_done(enum dc_lane_count ln_count,
331 union lane_status *dpcd_lane_status,
332 union lane_align_status_updated *lane_status_updated)
333{
334 bool done = true;
335 uint32_t lane;
336 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
337 done = false;
338 else {
339 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
340 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
341 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
342 done = false;
343 }
344 }
345 return done;
346
347}
348
349static void update_drive_settings(
350 struct link_training_settings *dest,
351 struct link_training_settings src)
352{
353 uint32_t lane;
354 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
e0a6440a
DG		 355 if (dest->voltage_swing == NULL)
356 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
357 else
358 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
359
360 if (dest->pre_emphasis == NULL)
361 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
362 else
363 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
364
365 if (dest->post_cursor2 == NULL)
366 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
367 else
368 dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
4562236b
HW		 369 }
370}
371
372static uint8_t get_nibble_at_index(const uint8_t *buf,
373 uint32_t index)
374{
375 uint8_t nibble;
376 nibble = buf[index / 2];
377
378 if (index % 2)
379 nibble >>= 4;
380 else
381 nibble &= 0x0F;
382
383 return nibble;
384}
385
386static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
387 enum dc_voltage_swing voltage)
388{
389 enum dc_pre_emphasis pre_emphasis;
390 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
391
392 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
393 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
394
395 return pre_emphasis;
396
397}
398
399static void find_max_drive_settings(
400 const struct link_training_settings *link_training_setting,
401 struct link_training_settings *max_lt_setting)
402{
403 uint32_t lane;
404 struct dc_lane_settings max_requested;
405
406 max_requested.VOLTAGE_SWING =
407 link_training_setting->
408 lane_settings[0].VOLTAGE_SWING;
409 max_requested.PRE_EMPHASIS =
410 link_training_setting->
411 lane_settings[0].PRE_EMPHASIS;
412 /*max_requested.postCursor2 =
413 * link_training_setting->laneSettings[0].postCursor2;*/
414
415 /* Determine what the maximum of the requested settings are*/
416 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
417 lane++) {
418 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
419 max_requested.VOLTAGE_SWING)
420
421 max_requested.VOLTAGE_SWING =
422 link_training_setting->
423 lane_settings[lane].VOLTAGE_SWING;
424
425 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
426 max_requested.PRE_EMPHASIS)
427 max_requested.PRE_EMPHASIS =
428 link_training_setting->
429 lane_settings[lane].PRE_EMPHASIS;
430
431 /*
432 if (link_training_setting->laneSettings[lane].postCursor2 >
433 max_requested.postCursor2)
434 {
435 max_requested.postCursor2 =
436 link_training_setting->laneSettings[lane].postCursor2;
437 }
438 */
439 }
440
441 /* make sure the requested settings are
442 * not higher than maximum settings*/
443 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
444 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
445
446 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
447 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
448 /*
449 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
450 max_requested.postCursor2 = PostCursor2_MaxLevel;
451 */
452
453 /* make sure the pre-emphasis matches the voltage swing*/
454 if (max_requested.PRE_EMPHASIS >
455 get_max_pre_emphasis_for_voltage_swing(
456 max_requested.VOLTAGE_SWING))
457 max_requested.PRE_EMPHASIS =
458 get_max_pre_emphasis_for_voltage_swing(
459 max_requested.VOLTAGE_SWING);
460
461 /*
462 * Post Cursor2 levels are completely independent from
463 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
464 * can only be applied to each allowable combination of voltage
465 * swing and pre-emphasis levels */
466 /* if ( max_requested.postCursor2 >
467 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
468 * max_requested.postCursor2 =
469 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
470 */
471
472 max_lt_setting->link_settings.link_rate =
473 link_training_setting->link_settings.link_rate;
474 max_lt_setting->link_settings.lane_count =
475 link_training_setting->link_settings.lane_count;
476 max_lt_setting->link_settings.link_spread =
477 link_training_setting->link_settings.link_spread;
478
479 for (lane = 0; lane <
480 link_training_setting->link_settings.lane_count;
481 lane++) {
482 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
483 max_requested.VOLTAGE_SWING;
484 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
485 max_requested.PRE_EMPHASIS;
486 /*max_lt_setting->laneSettings[lane].postCursor2 =
487 * max_requested.postCursor2;
488 */
489 }
490
491}
492
493static void get_lane_status_and_drive_settings(
d0778ebf 494 struct dc_link *link,
4562236b
HW		 495 const struct link_training_settings *link_training_setting,
496 union lane_status *ln_status,
497 union lane_align_status_updated *ln_status_updated,
498 struct link_training_settings *req_settings)
499{
500 uint8_t dpcd_buf[6] = {0};
9a6a8075
HW		 501 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
502 struct link_training_settings request_settings = { {0} };
4562236b
HW		 503 uint32_t lane;
504
505 memset(req_settings, '\0', sizeof(struct link_training_settings));
506
507 core_link_read_dpcd(
508 link,
3a340294 509 DP_LANE0_1_STATUS,
4562236b
HW		 510 (uint8_t *)(dpcd_buf),
511 sizeof(dpcd_buf));
512
513 for (lane = 0; lane <
514 (uint32_t)(link_training_setting->link_settings.lane_count);
515 lane++) {
516
517 ln_status[lane].raw =
518 get_nibble_at_index(&dpcd_buf[0], lane);
519 dpcd_lane_adjust[lane].raw =
520 get_nibble_at_index(&dpcd_buf[4], lane);
521 }
522
523 ln_status_updated->raw = dpcd_buf[2];
524
1296423b 525 DC_LOG_HW_LINK_TRAINING("%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
4562236b 526 __func__,
3a340294
DA		 527 DP_LANE0_1_STATUS, dpcd_buf[0],
528 DP_LANE2_3_STATUS, dpcd_buf[1]);
4562236b 529
1296423b 530 DC_LOG_HW_LINK_TRAINING("%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
4562236b 531 __func__,
3a340294 532 DP_ADJUST_REQUEST_LANE0_1,
4562236b 533 dpcd_buf[4],
3a340294 534 DP_ADJUST_REQUEST_LANE2_3,
4562236b
HW		 535 dpcd_buf[5]);
536
537 /*copy to req_settings*/
538 request_settings.link_settings.lane_count =
539 link_training_setting->link_settings.lane_count;
540 request_settings.link_settings.link_rate =
541 link_training_setting->link_settings.link_rate;
542 request_settings.link_settings.link_spread =
543 link_training_setting->link_settings.link_spread;
544
545 for (lane = 0; lane <
546 (uint32_t)(link_training_setting->link_settings.lane_count);
547 lane++) {
548
549 request_settings.lane_settings[lane].VOLTAGE_SWING =
550 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
551 VOLTAGE_SWING_LANE);
552 request_settings.lane_settings[lane].PRE_EMPHASIS =
553 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
554 PRE_EMPHASIS_LANE);
555 }
556
557 /*Note: for postcursor2, read adjusted
558 * postcursor2 settings from*/
559 /*DpcdAddress_AdjustRequestPostCursor2 =
560 *0x020C (not implemented yet)*/
561
562 /* we find the maximum of the requested settings across all lanes*/
563 /* and set this maximum for all lanes*/
564 find_max_drive_settings(&request_settings, req_settings);
565
566 /* if post cursor 2 is needed in the future,
567 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
568 */
569
570}
571
572static void dpcd_set_lane_settings(
d0778ebf 573 struct dc_link *link,
4562236b
HW		 574 const struct link_training_settings *link_training_setting)
575{
576 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
577 uint32_t lane;
578
579 for (lane = 0; lane <
580 (uint32_t)(link_training_setting->
581 link_settings.lane_count);
582 lane++) {
583 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
584 (uint8_t)(link_training_setting->
585 lane_settings[lane].VOLTAGE_SWING);
586 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
587 (uint8_t)(link_training_setting->
588 lane_settings[lane].PRE_EMPHASIS);
589 dpcd_lane[lane].bits.MAX_SWING_REACHED =
590 (link_training_setting->
591 lane_settings[lane].VOLTAGE_SWING ==
592 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
593 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
594 (link_training_setting->
595 lane_settings[lane].PRE_EMPHASIS ==
596 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
597 }
598
599 core_link_write_dpcd(link,
3a340294 600 DP_TRAINING_LANE0_SET,
4562236b
HW		 601 (uint8_t *)(dpcd_lane),
602 link_training_setting->link_settings.lane_count);
603
604 /*
605 if (LTSettings.link.rate == LinkRate_High2)
606 {
607 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
608 for ( uint32_t lane = 0;
609 lane < lane_count_DPMax; lane++)
610 {
611 dpcd_lane2[lane].bits.post_cursor2_set =
612 static_cast<unsigned char>(
613 LTSettings.laneSettings[lane].postCursor2);
614 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
615 }
616 m_pDpcdAccessSrv->WriteDpcdData(
617 DpcdAddress_Lane0Set2,
618 reinterpret_cast<unsigned char*>(dpcd_lane2),
619 LTSettings.link.lanes);
620 }
621 */
622
1296423b 623 DC_LOG_HW_LINK_TRAINING("%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
4562236b 624 __func__,
3a340294 625 DP_TRAINING_LANE0_SET,
4562236b
HW		 626 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
627 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
628 dpcd_lane[0].bits.MAX_SWING_REACHED,
629 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
630
d0778ebf 631 link->cur_lane_setting = link_training_setting->lane_settings[0];
4562236b
HW		 632
633}
634
635static bool is_max_vs_reached(
636 const struct link_training_settings *lt_settings)
637{
638 uint32_t lane;
639 for (lane = 0; lane <
640 (uint32_t)(lt_settings->link_settings.lane_count);
641 lane++) {
642 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
643 == VOLTAGE_SWING_MAX_LEVEL)
644 return true;
645 }
646 return false;
647
648}
649
650void dc_link_dp_set_drive_settings(
d0778ebf 651 struct dc_link *link,
4562236b
HW		 652 struct link_training_settings *lt_settings)
653{
4562236b 654 /* program ASIC PHY settings*/
d0778ebf 655 dp_set_hw_lane_settings(link, lt_settings);
4562236b
HW		 656
657 /* Notify DP sink the PHY settings from source */
d0778ebf 658 dpcd_set_lane_settings(link, lt_settings);
4562236b
HW		 659}
660
661static bool perform_post_lt_adj_req_sequence(
d0778ebf 662 struct dc_link *link,
4562236b
HW		 663 struct link_training_settings *lt_settings)
664{
665 enum dc_lane_count lane_count =
666 lt_settings->link_settings.lane_count;
667
668 uint32_t adj_req_count;
669 uint32_t adj_req_timer;
670 bool req_drv_setting_changed;
671 uint32_t lane;
672
673 req_drv_setting_changed = false;
674 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
675 adj_req_count++) {
676
677 req_drv_setting_changed = false;
678
679 for (adj_req_timer = 0;
680 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
681 adj_req_timer++) {
682
683 struct link_training_settings req_settings;
684 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
685 union lane_align_status_updated
686 dpcd_lane_status_updated;
687
688 get_lane_status_and_drive_settings(
689 link,
690 lt_settings,
691 dpcd_lane_status,
692 &dpcd_lane_status_updated,
693 &req_settings);
694
695 if (dpcd_lane_status_updated.bits.
696 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
697 return true;
698
699 if (!is_cr_done(lane_count, dpcd_lane_status))
700 return false;
701
702 if (!is_ch_eq_done(
703 lane_count,
704 dpcd_lane_status,
705 &dpcd_lane_status_updated))
706 return false;
707
708 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
709
710 if (lt_settings->
711 lane_settings[lane].VOLTAGE_SWING !=
712 req_settings.lane_settings[lane].
713 VOLTAGE_SWING ||
714 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
715 req_settings.lane_settings[lane].PRE_EMPHASIS) {
716
717 req_drv_setting_changed = true;
718 break;
719 }
720 }
721
722 if (req_drv_setting_changed) {
723 update_drive_settings(
9a6a8075 724 lt_settings, req_settings);
4562236b 725
d0778ebf 726 dc_link_dp_set_drive_settings(link,
4562236b
HW		 727 lt_settings);
728 break;
729 }
730
731 msleep(1);
732 }
733
734 if (!req_drv_setting_changed) {
1296423b 735 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
4562236b
HW		 736 __func__);
737
738 ASSERT(0);
739 return true;
740 }
741 }
1296423b 742 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
4562236b
HW		 743 __func__);
744
745 ASSERT(0);
746 return true;
747
748}
749
94405cf6
WL		 750static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
751 union lane_status *dpcd_lane_status)
752{
753 enum link_training_result result = LINK_TRAINING_SUCCESS;
754
755 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
756 result = LINK_TRAINING_CR_FAIL_LANE0;
757 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
758 result = LINK_TRAINING_CR_FAIL_LANE1;
759 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
760 result = LINK_TRAINING_CR_FAIL_LANE23;
761 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
762 result = LINK_TRAINING_CR_FAIL_LANE23;
763 return result;
764}
765
820e3935 766static enum link_training_result perform_channel_equalization_sequence(
d0778ebf 767 struct dc_link *link,
4562236b
HW		 768 struct link_training_settings *lt_settings)
769{
770 struct link_training_settings req_settings;
e0a6440a 771 enum dc_dp_training_pattern tr_pattern;
4562236b
HW		 772 uint32_t retries_ch_eq;
773 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
9a6a8075
HW		 774 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
775 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
4562236b 776
e0a6440a 777 tr_pattern = lt_settings->pattern_for_eq;
4562236b 778
e0a6440a 779 dp_set_hw_training_pattern(link, tr_pattern);
4562236b
HW		 780
781 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
782 retries_ch_eq++) {
783
784 dp_set_hw_lane_settings(link, lt_settings);
785
786 /* 2. update DPCD*/
787 if (!retries_ch_eq)
788 /* EPR #361076 - write as a 5-byte burst,
789 * but only for the 1-st iteration*/
790 dpcd_set_lt_pattern_and_lane_settings(
791 link,
792 lt_settings,
e0a6440a 793 tr_pattern);
4562236b
HW		 794 else
795 dpcd_set_lane_settings(link, lt_settings);
796
797 /* 3. wait for receiver to lock-on*/
e0a6440a 798 wait_for_training_aux_rd_interval(link, lt_settings->eq_pattern_time);
4562236b
HW		 799
800 /* 4. Read lane status and requested
801 * drive settings as set by the sink*/
802
803 get_lane_status_and_drive_settings(
804 link,
805 lt_settings,
806 dpcd_lane_status,
807 &dpcd_lane_status_updated,
808 &req_settings);
809
810 /* 5. check CR done*/
811 if (!is_cr_done(lane_count, dpcd_lane_status))
820e3935 812 return LINK_TRAINING_EQ_FAIL_CR;
4562236b
HW		 813
814 /* 6. check CHEQ done*/
815 if (is_ch_eq_done(lane_count,
816 dpcd_lane_status,
817 &dpcd_lane_status_updated))
820e3935 818 return LINK_TRAINING_SUCCESS;
4562236b
HW		 819
820 /* 7. update VS/PE/PC2 in lt_settings*/
821 update_drive_settings(lt_settings, req_settings);
822 }
823
820e3935 824 return LINK_TRAINING_EQ_FAIL_EQ;
4562236b
HW		 825
826}
827
94405cf6 828static enum link_training_result perform_clock_recovery_sequence(
d0778ebf 829 struct dc_link *link,
4562236b
HW		 830 struct link_training_settings *lt_settings)
831{
832 uint32_t retries_cr;
833 uint32_t retry_count;
4562236b 834 struct link_training_settings req_settings;
e0a6440a
DG		 835 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
836 enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
4562236b
HW		 837 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
838 union lane_align_status_updated dpcd_lane_status_updated;
839
840 retries_cr = 0;
841 retry_count = 0;
4562236b 842
e0a6440a 843 dp_set_hw_training_pattern(link, tr_pattern);
4562236b
HW		 844
845 /* najeeb - The synaptics MST hub can put the LT in
846 * infinite loop by switching the VS
847 */
848 /* between level 0 and level 1 continuously, here
849 * we try for CR lock for LinkTrainingMaxCRRetry count*/
850 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
e0a6440a 851 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
4562236b
HW		 852
853 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
854 memset(&dpcd_lane_status_updated, '\0',
855 sizeof(dpcd_lane_status_updated));
856
857 /* 1. call HWSS to set lane settings*/
858 dp_set_hw_lane_settings(
859 link,
860 lt_settings);
861
862 /* 2. update DPCD of the receiver*/
863 if (!retries_cr)
864 /* EPR #361076 - write as a 5-byte burst,
865 * but only for the 1-st iteration.*/
866 dpcd_set_lt_pattern_and_lane_settings(
867 link,
868 lt_settings,
e0a6440a 869 tr_pattern);
4562236b
HW		 870 else
871 dpcd_set_lane_settings(
872 link,
873 lt_settings);
874
875 /* 3. wait receiver to lock-on*/
876 wait_for_training_aux_rd_interval(
877 link,
e0a6440a 878 lt_settings->cr_pattern_time);
4562236b
HW		 879
880 /* 4. Read lane status and requested drive
881 * settings as set by the sink
882 */
883 get_lane_status_and_drive_settings(
884 link,
885 lt_settings,
886 dpcd_lane_status,
887 &dpcd_lane_status_updated,
888 &req_settings);
889
890 /* 5. check CR done*/
891 if (is_cr_done(lane_count, dpcd_lane_status))
94405cf6 892 return LINK_TRAINING_SUCCESS;
4562236b
HW		 893
894 /* 6. max VS reached*/
895 if (is_max_vs_reached(lt_settings))
94405cf6 896 break;
4562236b
HW		 897
898 /* 7. same voltage*/
899 /* Note: VS same for all lanes,
900 * so comparing first lane is sufficient*/
901 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
902 req_settings.lane_settings[0].VOLTAGE_SWING)
903 retries_cr++;
904 else
905 retries_cr = 0;
906
907 /* 8. update VS/PE/PC2 in lt_settings*/
908 update_drive_settings(lt_settings, req_settings);
909
910 retry_count++;
911 }
912
913 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
914 ASSERT(0);
1296423b 915 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
4f42a2dd 916 __func__,
4562236b
HW		 917 LINK_TRAINING_MAX_CR_RETRY);
918
919 }
920
94405cf6 921 return get_cr_failure(lane_count, dpcd_lane_status);
4562236b
HW		 922}
923
94405cf6 924static inline enum link_training_result perform_link_training_int(
d0778ebf 925 struct dc_link *link,
4562236b 926 struct link_training_settings *lt_settings,
94405cf6 927 enum link_training_result status)
4562236b
HW		 928{
929 union lane_count_set lane_count_set = { {0} };
930 union dpcd_training_pattern dpcd_pattern = { {0} };
931
932 /* 3. set training not in progress*/
933 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
934 dpcd_set_training_pattern(link, dpcd_pattern);
935
936 /* 4. mainlink output idle pattern*/
937 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
938
939 /*
940 * 5. post training adjust if required
941 * If the upstream DPTX and downstream DPRX both support TPS4,
942 * TPS4 must be used instead of POST_LT_ADJ_REQ.
943 */
c30267f5 944 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
e0a6440a 945 get_supported_tp(link) == DP_TRAINING_PATTERN_SEQUENCE_4)
4562236b
HW		 946 return status;
947
94405cf6 948 if (status == LINK_TRAINING_SUCCESS &&
4562236b 949 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
94405cf6 950 status = LINK_TRAINING_LQA_FAIL;
4562236b
HW		 951
952 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
e0a6440a 953 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
4562236b
HW		 954 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
955
956 core_link_write_dpcd(
957 link,
3a340294 958 DP_LANE_COUNT_SET,
4562236b
HW		 959 &lane_count_set.raw,
960 sizeof(lane_count_set));
961
962 return status;
963}
964
e0a6440a
DG		 965static void initialize_training_settings(
966 struct dc_link *link,
4562236b 967 const struct dc_link_settings *link_setting,
e0a6440a 968 struct link_training_settings *lt_settings)
4562236b 969{
e0a6440a 970 uint32_t lane;
4562236b 971
e0a6440a 972 memset(lt_settings, '\0', sizeof(struct link_training_settings));
94405cf6 973
e0a6440a
DG		 974 /* Initialize link settings */
975 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
976 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
4562236b 977
e0a6440a
DG		 978 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
979 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
980 else
981 lt_settings->link_settings.link_rate = link_setting->link_rate;
4562236b 982
e0a6440a
DG		 983 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
984 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
985 else
986 lt_settings->link_settings.lane_count = link_setting->lane_count;
4562236b
HW		 987
988 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
989
990 /* TODO hard coded to SS for now
991 * lt_settings.link_settings.link_spread =
992 * dal_display_path_is_ss_supported(
993 * path_mode->display_path) ?
994 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
995 * LINK_SPREAD_DISABLED;
996 */
e0a6440a 997 /* Initialize link spread */
ad830e7a 998 if (link->dp_ss_off)
e0a6440a
DG		 999 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1000 else if (link->preferred_training_settings.downspread != NULL)
1001 lt_settings->link_settings.link_spread
1002 = *link->preferred_training_settings.downspread
1003 ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1004 : LINK_SPREAD_DISABLED;
ad830e7a 1005 else
e0a6440a 1006 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
4562236b 1007
e0a6440a
DG		 1008 /* Initialize lane settings overrides */
1009 if (link->preferred_training_settings.voltage_swing != NULL)
1010 lt_settings->voltage_swing = link->preferred_training_settings.voltage_swing;
4562236b 1011
e0a6440a
DG		 1012 if (link->preferred_training_settings.pre_emphasis != NULL)
1013 lt_settings->pre_emphasis = link->preferred_training_settings.pre_emphasis;
4562236b 1014
e0a6440a
DG		 1015 if (link->preferred_training_settings.post_cursor2 != NULL)
1016 lt_settings->post_cursor2 = link->preferred_training_settings.post_cursor2;
1017
1018 /* Initialize lane settings (VS/PE/PC2) */
1019 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1020 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1021 lt_settings->voltage_swing != NULL ?
1022 *lt_settings->voltage_swing :
1023 VOLTAGE_SWING_LEVEL0;
1024 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1025 lt_settings->pre_emphasis != NULL ?
1026 *lt_settings->pre_emphasis
1027 : PRE_EMPHASIS_DISABLED;
1028 lt_settings->lane_settings[lane].POST_CURSOR2 =
1029 lt_settings->post_cursor2 != NULL ?
1030 *lt_settings->post_cursor2
1031 : POST_CURSOR2_DISABLED;
820e3935 1032 }
4562236b 1033
e0a6440a
DG		 1034 /* Initialize training timings */
1035 if (link->preferred_training_settings.cr_pattern_time != NULL)
1036 lt_settings->cr_pattern_time = *link->preferred_training_settings.cr_pattern_time;
1037 else
04300171 1038 lt_settings->cr_pattern_time = 100;
e0a6440a
DG		 1039
1040 if (link->preferred_training_settings.eq_pattern_time != NULL)
1041 lt_settings->eq_pattern_time = *link->preferred_training_settings.eq_pattern_time;
1042 else
1043 lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400);
1044
1045 if (link->preferred_training_settings.pattern_for_eq != NULL)
1046 lt_settings->pattern_for_eq = *link->preferred_training_settings.pattern_for_eq;
1047 else
1048 lt_settings->pattern_for_eq = get_supported_tp(link);
1049
1050 if (link->preferred_training_settings.enhanced_framing != NULL)
1051 lt_settings->enhanced_framing = *link->preferred_training_settings.enhanced_framing;
1052 else
1053 lt_settings->enhanced_framing = 1;
1054}
1055
1056static void print_status_message(
1057 struct dc_link *link,
1058 const struct link_training_settings *lt_settings,
1059 enum link_training_result status)
1060{
1061 char *link_rate = "Unknown";
1062 char *lt_result = "Unknown";
1063 char *lt_spread = "Disabled";
4562236b 1064
e0a6440a 1065 switch (lt_settings->link_settings.link_rate) {
4562236b
HW		 1066 case LINK_RATE_LOW:
1067 link_rate = "RBR";
1068 break;
1069 case LINK_RATE_HIGH:
1070 link_rate = "HBR";
1071 break;
1072 case LINK_RATE_HIGH2:
1073 link_rate = "HBR2";
1074 break;
1075 case LINK_RATE_RBR2:
1076 link_rate = "RBR2";
1077 break;
1078 case LINK_RATE_HIGH3:
1079 link_rate = "HBR3";
1080 break;
1081 default:
1082 break;
1083 }
1084
94405cf6
WL		 1085 switch (status) {
1086 case LINK_TRAINING_SUCCESS:
1087 lt_result = "pass";
1088 break;
1089 case LINK_TRAINING_CR_FAIL_LANE0:
1090 lt_result = "CR failed lane0";
1091 break;
1092 case LINK_TRAINING_CR_FAIL_LANE1:
1093 lt_result = "CR failed lane1";
1094 break;
1095 case LINK_TRAINING_CR_FAIL_LANE23:
1096 lt_result = "CR failed lane23";
1097 break;
1098 case LINK_TRAINING_EQ_FAIL_CR:
1099 lt_result = "CR failed in EQ";
1100 break;
1101 case LINK_TRAINING_EQ_FAIL_EQ:
1102 lt_result = "EQ failed";
1103 break;
1104 case LINK_TRAINING_LQA_FAIL:
1105 lt_result = "LQA failed";
1106 break;
1107 default:
1108 break;
1109 }
1110
e0a6440a
DG		 1111 switch (lt_settings->link_settings.link_spread) {
1112 case LINK_SPREAD_DISABLED:
1113 lt_spread = "Disabled";
1114 break;
1115 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1116 lt_spread = "0.5% 30KHz";
1117 break;
1118 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1119 lt_spread = "0.5% 33KHz";
1120 break;
1121 default:
1122 break;
1123 }
1124
4562236b 1125 /* Connectivity log: link training */
e0a6440a
DG		 1126 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1127 link_rate,
1128 lt_settings->link_settings.lane_count,
1129 lt_result,
1130 lt_settings->lane_settings[0].VOLTAGE_SWING,
1131 lt_settings->lane_settings[0].PRE_EMPHASIS,
1132 lt_spread);
1133}
1134
1135bool dc_link_dp_perform_link_training_skip_aux(
1136 struct dc_link *link,
1137 const struct dc_link_settings *link_setting)
1138{
1139 struct link_training_settings lt_settings;
1140 enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1;
1141
1142 initialize_training_settings(link, link_setting, &lt_settings);
1143
1144 /* 1. Perform_clock_recovery_sequence. */
1145
1146 /* transmit training pattern for clock recovery */
1147 dp_set_hw_training_pattern(link, pattern_for_cr);
1148
1149 /* call HWSS to set lane settings*/
1150 dp_set_hw_lane_settings(link, &lt_settings);
1151
1152 /* wait receiver to lock-on*/
1153 wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1154
1155 /* 2. Perform_channel_equalization_sequence. */
1156
1157 /* transmit training pattern for channel equalization. */
1158 dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq);
1159
1160 /* call HWSS to set lane settings*/
1161 dp_set_hw_lane_settings(link, &lt_settings);
1162
1163 /* wait receiver to lock-on. */
1164 wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1165
1166 /* 3. Perform_link_training_int. */
1167
1168 /* Mainlink output idle pattern. */
1169 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1170
1171 print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1172
1173 return true;
1174}
1175
1176enum link_training_result dc_link_dp_perform_link_training(
1177 struct dc_link *link,
1178 const struct dc_link_settings *link_setting,
1179 bool skip_video_pattern)
1180{
1181 enum link_training_result status = LINK_TRAINING_SUCCESS;
e0a6440a 1182 struct link_training_settings lt_settings;
008a4016
NC		 1183#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1184 bool fec_enable;
1185#endif
e0a6440a
DG		 1186
1187 initialize_training_settings(link, link_setting, &lt_settings);
1188
1189 /* 1. set link rate, lane count and spread. */
1190 dpcd_set_link_settings(link, &lt_settings);
1191
008a4016
NC		 1192#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1193 if (link->preferred_training_settings.fec_enable != NULL)
1194 fec_enable = *link->preferred_training_settings.fec_enable;
1195 else
1196 fec_enable = true;
1197
1198 dp_set_fec_ready(link, fec_enable);
1199#endif
1200
1201
e0a6440a
DG		 1202 /* 2. perform link training (set link training done
1203 * to false is done as well)
1204 */
1205 status = perform_clock_recovery_sequence(link, &lt_settings);
1206 if (status == LINK_TRAINING_SUCCESS) {
1207 status = perform_channel_equalization_sequence(link,
1208 &lt_settings);
1209 }
1210
1211 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1212 status = perform_link_training_int(link,
1213 &lt_settings,
1214 status);
1215 }
1216
1217 /* 6. print status message*/
1218 print_status_message(link, &lt_settings, status);
4562236b 1219
d6e75df4 1220 if (status != LINK_TRAINING_SUCCESS)
cfd84fd3 1221 link->ctx->dc->debug_data.ltFailCount++;
d6e75df4 1222
4562236b
HW		 1223 return status;
1224}
1225
4562236b 1226bool perform_link_training_with_retries(
d0778ebf 1227 struct dc_link *link,
4562236b
HW		 1228 const struct dc_link_settings *link_setting,
1229 bool skip_video_pattern,
1230 int attempts)
1231{
1232 uint8_t j;
1233 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1234
1235 for (j = 0; j < attempts; ++j) {
1236
1237 if (dc_link_dp_perform_link_training(
d0778ebf 1238 link,
4562236b 1239 link_setting,
820e3935 1240 skip_video_pattern) == LINK_TRAINING_SUCCESS)
4562236b
HW		 1241 return true;
1242
1243 msleep(delay_between_attempts);
1244 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1245 }
1246
1247 return false;
1248}
1249
d0778ebf 1250static struct dc_link_settings get_max_link_cap(struct dc_link *link)
4562236b
HW		 1251{
1252 /* Set Default link settings */
1253 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
8628d02f 1254 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
4562236b
HW		 1255
1256 /* Higher link settings based on feature supported */
1257 if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1258 max_link_cap.link_rate = LINK_RATE_HIGH2;
1259
1260 if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1261 max_link_cap.link_rate = LINK_RATE_HIGH3;
1262
1263 /* Lower link settings based on sink's link cap */
d0778ebf 1264 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
4562236b 1265 max_link_cap.lane_count =
d0778ebf
HW		 1266 link->reported_link_cap.lane_count;
1267 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
4562236b 1268 max_link_cap.link_rate =
d0778ebf
HW		 1269 link->reported_link_cap.link_rate;
1270 if (link->reported_link_cap.link_spread <
4562236b
HW		 1271 max_link_cap.link_spread)
1272 max_link_cap.link_spread =
d0778ebf 1273 link->reported_link_cap.link_spread;
4562236b
HW		 1274 return max_link_cap;
1275}
1276
1ae62f31
WL		 1277static enum dc_status read_hpd_rx_irq_data(
1278 struct dc_link *link,
1279 union hpd_irq_data *irq_data)
1280{
1281 static enum dc_status retval;
1282
1283 /* The HW reads 16 bytes from 200h on HPD,
1284 * but if we get an AUX_DEFER, the HW cannot retry
1285 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1286 * fail, so we now explicitly read 6 bytes which is
1287 * the req from the above mentioned test cases.
1288 *
1289 * For DP 1.4 we need to read those from 2002h range.
1290 */
1291 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1292 retval = core_link_read_dpcd(
1293 link,
1294 DP_SINK_COUNT,
1295 irq_data->raw,
1296 sizeof(union hpd_irq_data));
1297 else {
1298 /* Read 14 bytes in a single read and then copy only the required fields.
1299 * This is more efficient than doing it in two separate AUX reads. */
1300
1301 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1302
1303 retval = core_link_read_dpcd(
1304 link,
1305 DP_SINK_COUNT_ESI,
1306 tmp,
1307 sizeof(tmp));
1308
1309 if (retval != DC_OK)
1310 return retval;
1311
1312 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1313 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1314 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1315 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1316 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1317 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1318 }
1319
1320 return retval;
1321}
1322
1323static bool hpd_rx_irq_check_link_loss_status(
1324 struct dc_link *link,
1325 union hpd_irq_data *hpd_irq_dpcd_data)
1326{
1327 uint8_t irq_reg_rx_power_state = 0;
1328 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1329 union lane_status lane_status;
1330 uint32_t lane;
1331 bool sink_status_changed;
1332 bool return_code;
1333
1334 sink_status_changed = false;
1335 return_code = false;
1336
1337 if (link->cur_link_settings.lane_count == 0)
1338 return return_code;
1339
1340 /*1. Check that Link Status changed, before re-training.*/
1341
1342 /*parse lane status*/
1343 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1344 /* check status of lanes 0,1
1345 * changed DpcdAddress_Lane01Status (0x202)
1346 */
1347 lane_status.raw = get_nibble_at_index(
1348 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1349 lane);
1350
1351 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1352 !lane_status.bits.CR_DONE_0 ||
1353 !lane_status.bits.SYMBOL_LOCKED_0) {
1354 /* if one of the channel equalization, clock
1355 * recovery or symbol lock is dropped
1356 * consider it as (link has been
1357 * dropped) dp sink status has changed
1358 */
1359 sink_status_changed = true;
1360 break;
1361 }
1362 }
1363
1364 /* Check interlane align.*/
1365 if (sink_status_changed ||
1366 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1367
1368 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1369
1370 return_code = true;
1371
1372 /*2. Check that we can handle interrupt: Not in FS DOS,
1373 * Not in "Display Timeout" state, Link is trained.
1374 */
1375 dpcd_result = core_link_read_dpcd(link,
1376 DP_SET_POWER,
1377 &irq_reg_rx_power_state,
1378 sizeof(irq_reg_rx_power_state));
1379
1380 if (dpcd_result != DC_OK) {
1381 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1382 __func__);
1383 } else {
1384 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1385 return_code = false;
1386 }
1387 }
1388
1389 return return_code;
1390}
1391
aafded88 1392bool dp_verify_link_cap(
d0778ebf 1393 struct dc_link *link,
824474ba
BL		 1394 struct dc_link_settings *known_limit_link_setting,
1395 int *fail_count)
4562236b
HW		 1396{
1397 struct dc_link_settings max_link_cap = {0};
820e3935
DW		 1398 struct dc_link_settings cur_link_setting = {0};
1399 struct dc_link_settings *cur = &cur_link_setting;
1400 struct dc_link_settings initial_link_settings = {0};
4562236b
HW		 1401 bool success;
1402 bool skip_link_training;
4562236b 1403 bool skip_video_pattern;
4562236b
HW		 1404 struct clock_source *dp_cs;
1405 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
820e3935 1406 enum link_training_result status;
1ae62f31 1407 union hpd_irq_data irq_data;
4562236b 1408
aafded88
TC		 1409 if (link->dc->debug.skip_detection_link_training) {
1410 link->verified_link_cap = *known_limit_link_setting;
1411 return true;
1412 }
1413
1ae62f31 1414 memset(&irq_data, 0, sizeof(irq_data));
4562236b
HW		 1415 success = false;
1416 skip_link_training = false;
1417
1418 max_link_cap = get_max_link_cap(link);
1419
1420 /* TODO implement override and monitor patch later */
1421
1422 /* try to train the link from high to low to
1423 * find the physical link capability
1424 */
1425 /* disable PHY done possible by BIOS, will be done by driver itself */
d0778ebf 1426 dp_disable_link_phy(link, link->connector_signal);
4562236b
HW		 1427
1428 dp_cs = link->dc->res_pool->dp_clock_source;
1429
1430 if (dp_cs)
1431 dp_cs_id = dp_cs->id;
1432 else {
1433 /*
1434 * dp clock source is not initialized for some reason.
1435 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1436 */
1437 ASSERT(dp_cs);
1438 }
1439
820e3935
DW		 1440 /* link training starts with the maximum common settings
1441 * supported by both sink and ASIC.
1442 */
1443 initial_link_settings = get_common_supported_link_settings(
1444 *known_limit_link_setting,
1445 max_link_cap);
1446 cur_link_setting = initial_link_settings;
1447 do {
4562236b 1448 skip_video_pattern = true;
820e3935 1449
4562236b
HW		 1450 if (cur->link_rate == LINK_RATE_LOW)
1451 skip_video_pattern = false;
1452
1453 dp_enable_link_phy(
1454 link,
d0778ebf 1455 link->connector_signal,
4562236b
HW		 1456 dp_cs_id,
1457 cur);
1458
94405cf6 1459
4562236b
HW		 1460 if (skip_link_training)
1461 success = true;
1462 else {
820e3935 1463 status = dc_link_dp_perform_link_training(
d0778ebf 1464 link,
4562236b
HW		 1465 cur,
1466 skip_video_pattern);
820e3935
DW		 1467 if (status == LINK_TRAINING_SUCCESS)
1468 success = true;
824474ba
BL		 1469 else
1470 (*fail_count)++;
4562236b
HW		 1471 }
1472
1ae62f31 1473 if (success) {
d0778ebf 1474 link->verified_link_cap = *cur;
1ae62f31
WL		 1475 udelay(1000);
1476 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
1477 if (hpd_rx_irq_check_link_loss_status(
1478 link,
1479 &irq_data))
1480 (*fail_count)++;
1481 }
4562236b
HW		 1482 /* always disable the link before trying another
1483 * setting or before returning we'll enable it later
1484 * based on the actual mode we're driving
1485 */
d0778ebf 1486 dp_disable_link_phy(link, link->connector_signal);
820e3935
DW		 1487 } while (!success && decide_fallback_link_setting(
1488 initial_link_settings, cur, status));
4562236b
HW		 1489
1490 /* Link Training failed for all Link Settings
1491 * (Lane Count is still unknown)
1492 */
1493 if (!success) {
1494 /* If all LT fails for all settings,
1495 * set verified = failed safe (1 lane low)
1496 */
d0778ebf
HW		 1497 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1498 link->verified_link_cap.link_rate = LINK_RATE_LOW;
4562236b 1499
d0778ebf 1500 link->verified_link_cap.link_spread =
4562236b
HW		 1501 LINK_SPREAD_DISABLED;
1502 }
1503
4562236b
HW		 1504
1505 return success;
1506}
1507
9a6a8075 1508static struct dc_link_settings get_common_supported_link_settings(
820e3935
DW		 1509 struct dc_link_settings link_setting_a,
1510 struct dc_link_settings link_setting_b)
1511{
1512 struct dc_link_settings link_settings = {0};
1513
1514 link_settings.lane_count =
1515 (link_setting_a.lane_count <=
1516 link_setting_b.lane_count) ?
1517 link_setting_a.lane_count :
1518 link_setting_b.lane_count;
1519 link_settings.link_rate =
1520 (link_setting_a.link_rate <=
1521 link_setting_b.link_rate) ?
1522 link_setting_a.link_rate :
1523 link_setting_b.link_rate;
1524 link_settings.link_spread = LINK_SPREAD_DISABLED;
1525
1526 /* in DP compliance test, DPR-120 may have
1527 * a random value in its MAX_LINK_BW dpcd field.
1528 * We map it to the maximum supported link rate that
1529 * is smaller than MAX_LINK_BW in this case.
1530 */
1531 if (link_settings.link_rate > LINK_RATE_HIGH3) {
1532 link_settings.link_rate = LINK_RATE_HIGH3;
1533 } else if (link_settings.link_rate < LINK_RATE_HIGH3
1534 && link_settings.link_rate > LINK_RATE_HIGH2) {
1535 link_settings.link_rate = LINK_RATE_HIGH2;
1536 } else if (link_settings.link_rate < LINK_RATE_HIGH2
1537 && link_settings.link_rate > LINK_RATE_HIGH) {
1538 link_settings.link_rate = LINK_RATE_HIGH;
1539 } else if (link_settings.link_rate < LINK_RATE_HIGH
1540 && link_settings.link_rate > LINK_RATE_LOW) {
1541 link_settings.link_rate = LINK_RATE_LOW;
1542 } else if (link_settings.link_rate < LINK_RATE_LOW) {
1543 link_settings.link_rate = LINK_RATE_UNKNOWN;
1544 }
1545
1546 return link_settings;
1547}
1548
450619d3 1549static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 1550{
1551 return lane_count <= LANE_COUNT_ONE;
1552}
1553
450619d3 1554static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 1555{
1556 return link_rate <= LINK_RATE_LOW;
1557}
1558
44858055 1559static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
820e3935
DW		 1560{
1561 switch (lane_count) {
1562 case LANE_COUNT_FOUR:
1563 return LANE_COUNT_TWO;
1564 case LANE_COUNT_TWO:
1565 return LANE_COUNT_ONE;
1566 case LANE_COUNT_ONE:
1567 return LANE_COUNT_UNKNOWN;
1568 default:
1569 return LANE_COUNT_UNKNOWN;
1570 }
1571}
1572
04e21292 1573static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
820e3935
DW		 1574{
1575 switch (link_rate) {
1576 case LINK_RATE_HIGH3:
1577 return LINK_RATE_HIGH2;
1578 case LINK_RATE_HIGH2:
1579 return LINK_RATE_HIGH;
1580 case LINK_RATE_HIGH:
1581 return LINK_RATE_LOW;
1582 case LINK_RATE_LOW:
1583 return LINK_RATE_UNKNOWN;
1584 default:
1585 return LINK_RATE_UNKNOWN;
1586 }
1587}
1588
04e21292 1589static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
8c4abe0b
DW		 1590{
1591 switch (lane_count) {
1592 case LANE_COUNT_ONE:
1593 return LANE_COUNT_TWO;
1594 case LANE_COUNT_TWO:
1595 return LANE_COUNT_FOUR;
1596 default:
1597 return LANE_COUNT_UNKNOWN;
1598 }
1599}
1600
04e21292 1601static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
8c4abe0b
DW		 1602{
1603 switch (link_rate) {
1604 case LINK_RATE_LOW:
1605 return LINK_RATE_HIGH;
1606 case LINK_RATE_HIGH:
1607 return LINK_RATE_HIGH2;
1608 case LINK_RATE_HIGH2:
1609 return LINK_RATE_HIGH3;
1610 default:
1611 return LINK_RATE_UNKNOWN;
1612 }
1613}
1614
820e3935
DW		 1615/*
1616 * function: set link rate and lane count fallback based
1617 * on current link setting and last link training result
1618 * return value:
1619 * true - link setting could be set
1620 * false - has reached minimum setting
1621 * and no further fallback could be done
1622 */
04e21292 1623static bool decide_fallback_link_setting(
820e3935
DW		 1624 struct dc_link_settings initial_link_settings,
1625 struct dc_link_settings *current_link_setting,
1626 enum link_training_result training_result)
1627{
1628 if (!current_link_setting)
1629 return false;
1630
1631 switch (training_result) {
94405cf6
WL		 1632 case LINK_TRAINING_CR_FAIL_LANE0:
1633 case LINK_TRAINING_CR_FAIL_LANE1:
1634 case LINK_TRAINING_CR_FAIL_LANE23:
1635 case LINK_TRAINING_LQA_FAIL:
820e3935
DW		 1636 {
1637 if (!reached_minimum_link_rate
1638 (current_link_setting->link_rate)) {
1639 current_link_setting->link_rate =
1640 reduce_link_rate(
1641 current_link_setting->link_rate);
1642 } else if (!reached_minimum_lane_count
1643 (current_link_setting->lane_count)) {
1644 current_link_setting->link_rate =
1645 initial_link_settings.link_rate;
94405cf6
WL		 1646 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
1647 return false;
1648 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
1649 current_link_setting->lane_count =
1650 LANE_COUNT_ONE;
1651 else if (training_result ==
1652 LINK_TRAINING_CR_FAIL_LANE23)
1653 current_link_setting->lane_count =
1654 LANE_COUNT_TWO;
1655 else
1656 current_link_setting->lane_count =
1657 reduce_lane_count(
820e3935
DW		 1658 current_link_setting->lane_count);
1659 } else {
1660 return false;
1661 }
1662 break;
1663 }
1664 case LINK_TRAINING_EQ_FAIL_EQ:
1665 {
1666 if (!reached_minimum_lane_count
1667 (current_link_setting->lane_count)) {
1668 current_link_setting->lane_count =
1669 reduce_lane_count(
1670 current_link_setting->lane_count);
1671 } else if (!reached_minimum_link_rate
1672 (current_link_setting->link_rate)) {
820e3935
DW		 1673 current_link_setting->link_rate =
1674 reduce_link_rate(
1675 current_link_setting->link_rate);
1676 } else {
1677 return false;
1678 }
1679 break;
1680 }
1681 case LINK_TRAINING_EQ_FAIL_CR:
1682 {
1683 if (!reached_minimum_link_rate
1684 (current_link_setting->link_rate)) {
1685 current_link_setting->link_rate =
1686 reduce_link_rate(
1687 current_link_setting->link_rate);
1688 } else {
1689 return false;
1690 }
1691 break;
1692 }
1693 default:
1694 return false;
1695 }
1696 return true;
1697}
1698
4562236b 1699bool dp_validate_mode_timing(
d0778ebf 1700 struct dc_link *link,
4562236b
HW		 1701 const struct dc_crtc_timing *timing)
1702{
1703 uint32_t req_bw;
1704 uint32_t max_bw;
1705
1706 const struct dc_link_settings *link_setting;
1707
1708 /*always DP fail safe mode*/
380604e2 1709 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
9a6a8075
HW		 1710 timing->h_addressable == (uint32_t) 640 &&
1711 timing->v_addressable == (uint32_t) 480)
4562236b
HW		 1712 return true;
1713
5ac4619b 1714 link_setting = dc_link_get_link_cap(link);
4562236b
HW		 1715
1716 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1717 /*if (flags.DYNAMIC_VALIDATION == 1 &&
d0778ebf
HW		 1718 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
1719 link_setting = &link->verified_link_cap;
4562236b
HW		 1720 */
1721
e49f6936 1722 req_bw = dc_bandwidth_in_kbps_from_timing(timing);
332c1191 1723 max_bw = dc_link_bandwidth_kbps(link, link_setting);
4562236b
HW		 1724
1725 if (req_bw <= max_bw) {
1726 /* remember the biggest mode here, during
1727 * initial link training (to get
1728 * verified_link_cap), LS sends event about
1729 * cannot train at reported cap to upper
1730 * layer and upper layer will re-enumerate modes.
1731 * this is not necessary if the lower
1732 * verified_link_cap is enough to drive
1733 * all the modes */
1734
1735 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1736 /* if (flags.DYNAMIC_VALIDATION == 1)
1737 dpsst->max_req_bw_for_verified_linkcap = dal_max(
1738 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
1739 return true;
1740 } else
1741 return false;
1742}
1743
8628d02f 1744static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
4562236b 1745{
8c4abe0b 1746 struct dc_link_settings initial_link_setting = {
8628d02f 1747 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
8c4abe0b
DW		 1748 struct dc_link_settings current_link_setting =
1749 initial_link_setting;
4562236b 1750 uint32_t link_bw;
4562236b 1751
8628d02f
JP		 1752 /* search for the minimum link setting that:
1753 * 1. is supported according to the link training result
1754 * 2. could support the b/w requested by the timing
4562236b 1755 */
8628d02f
JP		 1756 while (current_link_setting.link_rate <=
1757 link->verified_link_cap.link_rate) {
332c1191
NC		 1758 link_bw = dc_link_bandwidth_kbps(
1759 link,
8628d02f
JP		 1760 &current_link_setting);
1761 if (req_bw <= link_bw) {
1762 *link_setting = current_link_setting;
1763 return true;
1764 }
4562236b 1765
8628d02f
JP		 1766 if (current_link_setting.lane_count <
1767 link->verified_link_cap.lane_count) {
1768 current_link_setting.lane_count =
1769 increase_lane_count(
1770 current_link_setting.lane_count);
1771 } else {
1772 current_link_setting.link_rate =
1773 increase_link_rate(
1774 current_link_setting.link_rate);
1775 current_link_setting.lane_count =
1776 initial_link_setting.lane_count;
1777 }
3f1f74f4
JZ		 1778 }
1779
8628d02f
JP		 1780 return false;
1781}
1782
1783static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
1784{
1785 struct dc_link_settings initial_link_setting;
1786 struct dc_link_settings current_link_setting;
1787 uint32_t link_bw;
1788
1789 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
53c81fc7 1790 link->dpcd_caps.edp_supported_link_rates_count == 0) {
4d2f22d1 1791 *link_setting = link->verified_link_cap;
8628d02f 1792 return true;
4d2f22d1
HH		 1793 }
1794
8628d02f
JP		 1795 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
1796 initial_link_setting.lane_count = LANE_COUNT_ONE;
1797 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
1798 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
1799 initial_link_setting.use_link_rate_set = true;
1800 initial_link_setting.link_rate_set = 0;
1801 current_link_setting = initial_link_setting;
1802
5667ff5c
DA		 1803 /* search for the minimum link setting that:
1804 * 1. is supported according to the link training result
1805 * 2. could support the b/w requested by the timing
1806 */
8c4abe0b 1807 while (current_link_setting.link_rate <=
4654a2f7 1808 link->verified_link_cap.link_rate) {
332c1191
NC		 1809 link_bw = dc_link_bandwidth_kbps(
1810 link,
8c4abe0b
DW		 1811 &current_link_setting);
1812 if (req_bw <= link_bw) {
1813 *link_setting = current_link_setting;
8628d02f 1814 return true;
4562236b 1815 }
4562236b 1816
8c4abe0b 1817 if (current_link_setting.lane_count <
4654a2f7 1818 link->verified_link_cap.lane_count) {
8c4abe0b
DW		 1819 current_link_setting.lane_count =
1820 increase_lane_count(
1821 current_link_setting.lane_count);
1822 } else {
8628d02f
JP		 1823 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
1824 current_link_setting.link_rate_set++;
1825 current_link_setting.link_rate =
1826 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
1827 current_link_setting.lane_count =
1828 initial_link_setting.lane_count;
1829 } else
1830 break;
4562236b
HW		 1831 }
1832 }
8628d02f
JP		 1833 return false;
1834}
1835
1836void decide_link_settings(struct dc_stream_state *stream,
1837 struct dc_link_settings *link_setting)
1838{
1839 struct dc_link *link;
1840 uint32_t req_bw;
1841
e49f6936 1842 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
8628d02f
JP		 1843
1844 link = stream->link;
1845
1846 /* if preferred is specified through AMDDP, use it, if it's enough
1847 * to drive the mode
1848 */
1849 if (link->preferred_link_setting.lane_count !=
1850 LANE_COUNT_UNKNOWN &&
1851 link->preferred_link_setting.link_rate !=
1852 LINK_RATE_UNKNOWN) {
1853 *link_setting = link->preferred_link_setting;
1854 return;
1855 }
1856
1857 /* MST doesn't perform link training for now
1858 * TODO: add MST specific link training routine
1859 */
1860 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1861 *link_setting = link->verified_link_cap;
1862 return;
1863 }
1864
1865 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1866 if (decide_edp_link_settings(link, link_setting, req_bw))
1867 return;
1868 } else if (decide_dp_link_settings(link, link_setting, req_bw))
1869 return;
4562236b
HW		 1870
1871 BREAK_TO_DEBUGGER();
d0778ebf 1872 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
4562236b 1873
d0778ebf 1874 *link_setting = link->verified_link_cap;
4562236b
HW		 1875}
1876
1877/*************************Short Pulse IRQ***************************/
d0778ebf 1878static bool allow_hpd_rx_irq(const struct dc_link *link)
4562236b
HW		 1879{
1880 /*
1881 * Don't handle RX IRQ unless one of following is met:
1882 * 1) The link is established (cur_link_settings != unknown)
1883 * 2) We kicked off MST detection
1884 * 3) We know we're dealing with an active dongle
1885 */
1886
d0778ebf
HW		 1887 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1888 (link->type == dc_connection_mst_branch) ||
4562236b
HW		 1889 is_dp_active_dongle(link))
1890 return true;
1891
1892 return false;
1893}
1894
d0778ebf 1895static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
4562236b
HW		 1896{
1897 union dpcd_psr_configuration psr_configuration;
1898
94267b3d 1899 if (!link->psr_enabled)
4562236b
HW		 1900 return false;
1901
7c7f5b15
AG		 1902 dm_helpers_dp_read_dpcd(
1903 link->ctx,
d0778ebf 1904 link,
7c7f5b15
AG		 1905 368,/*DpcdAddress_PSR_Enable_Cfg*/
1906 &psr_configuration.raw,
1907 sizeof(psr_configuration.raw));
1908
4562236b
HW		 1909
1910 if (psr_configuration.bits.ENABLE) {
1911 unsigned char dpcdbuf[3] = {0};
1912 union psr_error_status psr_error_status;
1913 union psr_sink_psr_status psr_sink_psr_status;
1914
7c7f5b15
AG		 1915 dm_helpers_dp_read_dpcd(
1916 link->ctx,
d0778ebf 1917 link,
7c7f5b15
AG		 1918 0x2006, /*DpcdAddress_PSR_Error_Status*/
1919 (unsigned char *) dpcdbuf,
1920 sizeof(dpcdbuf));
4562236b
HW		 1921
1922 /*DPCD 2006h ERROR STATUS*/
1923 psr_error_status.raw = dpcdbuf[0];
1924 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
1925 psr_sink_psr_status.raw = dpcdbuf[2];
1926
1927 if (psr_error_status.bits.LINK_CRC_ERROR ||
1928 psr_error_status.bits.RFB_STORAGE_ERROR) {
1929 /* Acknowledge and clear error bits */
7c7f5b15
AG		 1930 dm_helpers_dp_write_dpcd(
1931 link->ctx,
d0778ebf 1932 link,
7c7f5b15 1933 8198,/*DpcdAddress_PSR_Error_Status*/
4562236b
HW		 1934 &psr_error_status.raw,
1935 sizeof(psr_error_status.raw));
1936
1937 /* PSR error, disable and re-enable PSR */
c7299705
CL		 1938 dc_link_set_psr_enable(link, false, true);
1939 dc_link_set_psr_enable(link, true, true);
4562236b
HW		 1940
1941 return true;
1942 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
1943 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
1944 /* No error is detect, PSR is active.
1945 * We should return with IRQ_HPD handled without
1946 * checking for loss of sync since PSR would have
1947 * powered down main link.
1948 */
1949 return true;
1950 }
1951 }
1952 return false;
1953}
1954
d0778ebf 1955static void dp_test_send_link_training(struct dc_link *link)
4562236b 1956{
73c72602 1957 struct dc_link_settings link_settings = {0};
4562236b
HW		 1958
1959 core_link_read_dpcd(
1960 link,
3a340294 1961 DP_TEST_LANE_COUNT,
4562236b
HW		 1962 (unsigned char *)(&link_settings.lane_count),
1963 1);
1964 core_link_read_dpcd(
1965 link,
3a340294 1966 DP_TEST_LINK_RATE,
4562236b
HW		 1967 (unsigned char *)(&link_settings.link_rate),
1968 1);
1969
1970 /* Set preferred link settings */
d0778ebf
HW		 1971 link->verified_link_cap.lane_count = link_settings.lane_count;
1972 link->verified_link_cap.link_rate = link_settings.link_rate;
4562236b 1973
73c72602 1974 dp_retrain_link_dp_test(link, &link_settings, false);
4562236b
HW		 1975}
1976
9315e239 1977/* TODO Raven hbr2 compliance eye output is unstable
25bab0da
WL		 1978 * (toggling on and off) with debugger break
1979 * This caueses intermittent PHY automation failure
1980 * Need to look into the root cause */
d0778ebf 1981static void dp_test_send_phy_test_pattern(struct dc_link *link)
4562236b
HW		 1982{
1983 union phy_test_pattern dpcd_test_pattern;
1984 union lane_adjust dpcd_lane_adjustment[2];
1985 unsigned char dpcd_post_cursor_2_adjustment = 0;
1986 unsigned char test_80_bit_pattern[
3a340294
DA		 1987 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1988 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
4562236b
HW		 1989 enum dp_test_pattern test_pattern;
1990 struct dc_link_training_settings link_settings;
1991 union lane_adjust dpcd_lane_adjust;
1992 unsigned int lane;
1993 struct link_training_settings link_training_settings;
1994 int i = 0;
1995
1996 dpcd_test_pattern.raw = 0;
1997 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
1998 memset(&link_settings, 0, sizeof(link_settings));
1999
2000 /* get phy test pattern and pattern parameters from DP receiver */
2001 core_link_read_dpcd(
2002 link,
3a340294 2003 DP_TEST_PHY_PATTERN,
4562236b
HW		 2004 &dpcd_test_pattern.raw,
2005 sizeof(dpcd_test_pattern));
2006 core_link_read_dpcd(
2007 link,
3a340294 2008 DP_ADJUST_REQUEST_LANE0_1,
4562236b
HW		 2009 &dpcd_lane_adjustment[0].raw,
2010 sizeof(dpcd_lane_adjustment));
2011
2012 /*get post cursor 2 parameters
2013 * For DP 1.1a or eariler, this DPCD register's value is 0
2014 * For DP 1.2 or later:
2015 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2016 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2017 */
2018 core_link_read_dpcd(
2019 link,
3a340294 2020 DP_ADJUST_REQUEST_POST_CURSOR2,
4562236b
HW		 2021 &dpcd_post_cursor_2_adjustment,
2022 sizeof(dpcd_post_cursor_2_adjustment));
2023
2024 /* translate request */
2025 switch (dpcd_test_pattern.bits.PATTERN) {
2026 case PHY_TEST_PATTERN_D10_2:
2027 test_pattern = DP_TEST_PATTERN_D102;
0e19401f 2028 break;
4562236b
HW		 2029 case PHY_TEST_PATTERN_SYMBOL_ERROR:
2030 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 2031 break;
4562236b
HW		 2032 case PHY_TEST_PATTERN_PRBS7:
2033 test_pattern = DP_TEST_PATTERN_PRBS7;
0e19401f 2034 break;
4562236b
HW		 2035 case PHY_TEST_PATTERN_80BIT_CUSTOM:
2036 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 2037 break;
2038 case PHY_TEST_PATTERN_CP2520_1:
25bab0da 2039 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 2040 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 2041 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2042 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 2043 break;
2044 case PHY_TEST_PATTERN_CP2520_2:
25bab0da 2045 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
9315e239 2046 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
25bab0da
WL		 2047 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2048 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
0e19401f
TC		 2049 break;
2050 case PHY_TEST_PATTERN_CP2520_3:
78e685f9 2051 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
0e19401f 2052 break;
4562236b
HW		 2053 default:
2054 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2055 break;
2056 }
2057
2058 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2059 core_link_read_dpcd(
2060 link,
3a340294 2061 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
4562236b
HW		 2062 test_80_bit_pattern,
2063 sizeof(test_80_bit_pattern));
2064
2065 /* prepare link training settings */
d0778ebf 2066 link_settings.link = link->cur_link_settings;
4562236b
HW		 2067
2068 for (lane = 0; lane <
d0778ebf 2069 (unsigned int)(link->cur_link_settings.lane_count);
4562236b
HW		 2070 lane++) {
2071 dpcd_lane_adjust.raw =
2072 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2073 link_settings.lane_settings[lane].VOLTAGE_SWING =
2074 (enum dc_voltage_swing)
2075 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2076 link_settings.lane_settings[lane].PRE_EMPHASIS =
2077 (enum dc_pre_emphasis)
2078 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2079 link_settings.lane_settings[lane].POST_CURSOR2 =
2080 (enum dc_post_cursor2)
2081 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2082 }
2083
2084 for (i = 0; i < 4; i++)
2085 link_training_settings.lane_settings[i] =
2086 link_settings.lane_settings[i];
2087 link_training_settings.link_settings = link_settings.link;
2088 link_training_settings.allow_invalid_msa_timing_param = false;
2089 /*Usage: Measure DP physical lane signal
2090 * by DP SI test equipment automatically.
2091 * PHY test pattern request is generated by equipment via HPD interrupt.
2092 * HPD needs to be active all the time. HPD should be active
2093 * all the time. Do not touch it.
2094 * forward request to DS
2095 */
2096 dc_link_dp_set_test_pattern(
d0778ebf 2097 link,
4562236b
HW		 2098 test_pattern,
2099 &link_training_settings,
2100 test_80_bit_pattern,
3a340294
DA		 2101 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2102 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
4562236b
HW		 2103}
2104
d0778ebf 2105static void dp_test_send_link_test_pattern(struct dc_link *link)
4562236b
HW		 2106{
2107 union link_test_pattern dpcd_test_pattern;
2108 union test_misc dpcd_test_params;
2109 enum dp_test_pattern test_pattern;
2110
2111 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2112 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2113
2114 /* get link test pattern and pattern parameters */
2115 core_link_read_dpcd(
2116 link,
3a340294 2117 DP_TEST_PATTERN,
4562236b
HW		 2118 &dpcd_test_pattern.raw,
2119 sizeof(dpcd_test_pattern));
2120 core_link_read_dpcd(
2121 link,
3a340294 2122 DP_TEST_MISC0,
4562236b
HW		 2123 &dpcd_test_params.raw,
2124 sizeof(dpcd_test_params));
2125
2126 switch (dpcd_test_pattern.bits.PATTERN) {
2127 case LINK_TEST_PATTERN_COLOR_RAMP:
2128 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2129 break;
2130 case LINK_TEST_PATTERN_VERTICAL_BARS:
2131 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2132 break; /* black and white */
2133 case LINK_TEST_PATTERN_COLOR_SQUARES:
2134 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2135 TEST_DYN_RANGE_VESA ?
2136 DP_TEST_PATTERN_COLOR_SQUARES :
2137 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2138 break;
2139 default:
2140 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2141 break;
2142 }
2143
2144 dc_link_dp_set_test_pattern(
d0778ebf 2145 link,
4562236b
HW		 2146 test_pattern,
2147 NULL,
2148 NULL,
2149 0);
2150}
2151
d0778ebf 2152static void handle_automated_test(struct dc_link *link)
4562236b
HW		 2153{
2154 union test_request test_request;
2155 union test_response test_response;
2156
2157 memset(&test_request, 0, sizeof(test_request));
2158 memset(&test_response, 0, sizeof(test_response));
2159
2160 core_link_read_dpcd(
2161 link,
3a340294 2162 DP_TEST_REQUEST,
4562236b
HW		 2163 &test_request.raw,
2164 sizeof(union test_request));
2165 if (test_request.bits.LINK_TRAINING) {
2166 /* ACK first to let DP RX test box monitor LT sequence */
2167 test_response.bits.ACK = 1;
2168 core_link_write_dpcd(
2169 link,
3a340294 2170 DP_TEST_RESPONSE,
4562236b
HW		 2171 &test_response.raw,
2172 sizeof(test_response));
2173 dp_test_send_link_training(link);
2174 /* no acknowledge request is needed again */
2175 test_response.bits.ACK = 0;
2176 }
2177 if (test_request.bits.LINK_TEST_PATTRN) {
2178 dp_test_send_link_test_pattern(link);
75a74755 2179 test_response.bits.ACK = 1;
4562236b
HW		 2180 }
2181 if (test_request.bits.PHY_TEST_PATTERN) {
2182 dp_test_send_phy_test_pattern(link);
2183 test_response.bits.ACK = 1;
2184 }
a6729a5a 2185
4562236b
HW		 2186 /* send request acknowledgment */
2187 if (test_response.bits.ACK)
2188 core_link_write_dpcd(
2189 link,
3a340294 2190 DP_TEST_RESPONSE,
4562236b
HW		 2191 &test_response.raw,
2192 sizeof(test_response));
2193}
2194
4e18814e 2195bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
4562236b 2196{
9a6a8075 2197 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
c2e218dd 2198 union device_service_irq device_service_clear = { { 0 } };
d6258eaa 2199 enum dc_status result;
4e18814e 2200
4562236b 2201 bool status = false;
4e18814e
FD		 2202
2203 if (out_link_loss)
2204 *out_link_loss = false;
4562236b
HW		 2205 /* For use cases related to down stream connection status change,
2206 * PSR and device auto test, refer to function handle_sst_hpd_irq
2207 * in DAL2.1*/
2208
1296423b 2209 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
d0778ebf 2210 __func__, link->link_index);
4562236b 2211
8ee65d7c 2212
4562236b
HW		 2213 /* All the "handle_hpd_irq_xxx()" methods
2214 * should be called only after
2215 * dal_dpsst_ls_read_hpd_irq_data
2216 * Order of calls is important too
2217 */
2218 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
8ee65d7c
WL		 2219 if (out_hpd_irq_dpcd_data)
2220 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4562236b
HW		 2221
2222 if (result != DC_OK) {
1296423b 2223 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
4562236b
HW		 2224 __func__);
2225 return false;
2226 }
2227
2228 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2229 device_service_clear.bits.AUTOMATED_TEST = 1;
2230 core_link_write_dpcd(
2231 link,
3a340294 2232 DP_DEVICE_SERVICE_IRQ_VECTOR,
4562236b
HW		 2233 &device_service_clear.raw,
2234 sizeof(device_service_clear.raw));
2235 device_service_clear.raw = 0;
2236 handle_automated_test(link);
2237 return false;
2238 }
2239
2240 if (!allow_hpd_rx_irq(link)) {
1296423b 2241 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
d0778ebf 2242 __func__, link->link_index);
4562236b
HW		 2243 return false;
2244 }
2245
2246 if (handle_hpd_irq_psr_sink(link))
2247 /* PSR-related error was detected and handled */
2248 return true;
2249
2250 /* If PSR-related error handled, Main link may be off,
2251 * so do not handle as a normal sink status change interrupt.
2252 */
2253
aaa15026
WL		 2254 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2255 return true;
2256
4562236b 2257 /* check if we have MST msg and return since we poll for it */
aaa15026 2258 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
4562236b
HW		 2259 return false;
2260
2261 /* For now we only handle 'Downstream port status' case.
2262 * If we got sink count changed it means
2263 * Downstream port status changed,
2264 * then DM should call DC to do the detection. */
2265 if (hpd_rx_irq_check_link_loss_status(
2266 link,
2267 &hpd_irq_dpcd_data)) {
2268 /* Connectivity log: link loss */
2269 CONN_DATA_LINK_LOSS(link,
2270 hpd_irq_dpcd_data.raw,
2271 sizeof(hpd_irq_dpcd_data),
2272 "Status: ");
2273
2274 perform_link_training_with_retries(link,
d0778ebf 2275 &link->cur_link_settings,
4562236b
HW		 2276 true, LINK_TRAINING_ATTEMPTS);
2277
2278 status = false;
4e18814e
FD		 2279 if (out_link_loss)
2280 *out_link_loss = true;
4562236b
HW		 2281 }
2282
d0778ebf 2283 if (link->type == dc_connection_active_dongle &&
4562236b
HW		 2284 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
2285 != link->dpcd_sink_count)
2286 status = true;
2287
2288 /* reasons for HPD RX:
2289 * 1. Link Loss - ie Re-train the Link
2290 * 2. MST sideband message
2291 * 3. Automated Test - ie. Internal Commit
2292 * 4. CP (copy protection) - (not interesting for DM???)
2293 * 5. DRR
2294 * 6. Downstream Port status changed
2295 * -ie. Detect - this the only one
2296 * which is interesting for DM because
2297 * it must call dc_link_detect.
2298 */
2299 return status;
2300}
2301
2302/*query dpcd for version and mst cap addresses*/
d0778ebf 2303bool is_mst_supported(struct dc_link *link)
4562236b
HW		 2304{
2305 bool mst = false;
2306 enum dc_status st = DC_OK;
2307 union dpcd_rev rev;
2308 union mstm_cap cap;
2309
2310 rev.raw = 0;
2311 cap.raw = 0;
2312
3a340294 2313 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4562236b
HW		 2314 sizeof(rev));
2315
2316 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2317
3a340294 2318 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4562236b
HW		 2319 &cap.raw, sizeof(cap));
2320 if (st == DC_OK && cap.bits.MST_CAP == 1)
2321 mst = true;
2322 }
2323 return mst;
2324
2325}
2326
d0778ebf 2327bool is_dp_active_dongle(const struct dc_link *link)
4562236b 2328{
a504ad26 2329 return link->dpcd_caps.is_branch_dev;
4562236b
HW		 2330}
2331
6bffebc9
EY		 2332static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
2333{
2334 switch (bpc) {
2335 case DOWN_STREAM_MAX_8BPC:
2336 return 8;
2337 case DOWN_STREAM_MAX_10BPC:
2338 return 10;
2339 case DOWN_STREAM_MAX_12BPC:
2340 return 12;
2341 case DOWN_STREAM_MAX_16BPC:
2342 return 16;
2343 default:
2344 break;
2345 }
2346
2347 return -1;
2348}
2349
ee13cea9
JB		 2350static void read_dp_device_vendor_id(struct dc_link *link)
2351{
2352 struct dp_device_vendor_id dp_id;
2353
2354 /* read IEEE branch device id */
2355 core_link_read_dpcd(
2356 link,
2357 DP_BRANCH_OUI,
2358 (uint8_t *)&dp_id,
2359 sizeof(dp_id));
2360
2361 link->dpcd_caps.branch_dev_id =
2362 (dp_id.ieee_oui[0] << 16) +
2363 (dp_id.ieee_oui[1] << 8) +
2364 dp_id.ieee_oui[2];
2365
2366 memmove(
2367 link->dpcd_caps.branch_dev_name,
2368 dp_id.ieee_device_id,
2369 sizeof(dp_id.ieee_device_id));
2370}
2371
2372
2373
4562236b 2374static void get_active_converter_info(
d0778ebf 2375 uint8_t data, struct dc_link *link)
4562236b
HW		 2376{
2377 union dp_downstream_port_present ds_port = { .byte = data };
2378
2379 /* decode converter info*/
2380 if (!ds_port.fields.PORT_PRESENT) {
2381 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
d0778ebf 2382 ddc_service_set_dongle_type(link->ddc,
4562236b 2383 link->dpcd_caps.dongle_type);
ac3d76e0 2384 link->dpcd_caps.is_branch_dev = false;
4562236b
HW		 2385 return;
2386 }
2387
a504ad26 2388 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
ac3d76e0
HT		 2389 if (ds_port.fields.PORT_TYPE == DOWNSTREAM_DP) {
2390 link->dpcd_caps.is_branch_dev = false;
2391 }
2392
2393 else {
2394 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
2395 }
a504ad26 2396
4562236b
HW		 2397 switch (ds_port.fields.PORT_TYPE) {
2398 case DOWNSTREAM_VGA:
2399 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
2400 break;
7a83645a
DZ		 2401 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
2402 /* At this point we don't know is it DVI or HDMI or DP++,
4562236b
HW		 2403 * assume DVI.*/
2404 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
2405 break;
2406 default:
2407 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2408 break;
2409 }
2410
ac0e562c 2411 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
242b0c8f 2412 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
4562236b
HW		 2413 union dwnstream_port_caps_byte0 *port_caps =
2414 (union dwnstream_port_caps_byte0 *)det_caps;
3a340294 2415 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
4562236b
HW		 2416 det_caps, sizeof(det_caps));
2417
2418 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
7a83645a
DZ		 2419 /*Handle DP case as DONGLE_NONE*/
2420 case DOWN_STREAM_DETAILED_DP:
2421 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2422 break;
4562236b
HW		 2423 case DOWN_STREAM_DETAILED_VGA:
2424 link->dpcd_caps.dongle_type =
2425 DISPLAY_DONGLE_DP_VGA_CONVERTER;
2426 break;
2427 case DOWN_STREAM_DETAILED_DVI:
2428 link->dpcd_caps.dongle_type =
2429 DISPLAY_DONGLE_DP_DVI_CONVERTER;
2430 break;
2431 case DOWN_STREAM_DETAILED_HDMI:
7a83645a
DZ		 2432 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
2433 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
4562236b
HW		 2434 link->dpcd_caps.dongle_type =
2435 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
2436
03f5c686 2437 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
4562236b
HW		 2438 if (ds_port.fields.DETAILED_CAPS) {
2439
2440 union dwnstream_port_caps_byte3_hdmi
2441 hdmi_caps = {.raw = det_caps[3] };
7d8d90d8 2442 union dwnstream_port_caps_byte2
03f5c686 2443 hdmi_color_caps = {.raw = det_caps[2] };
e5490464
S		 2444 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
2445 det_caps[1] * 2500;
4562236b 2446
03f5c686 2447 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
4562236b 2448 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
7a83645a
DZ		 2449 /*YCBCR capability only for HDMI case*/
2450 if (port_caps->bits.DWN_STRM_PORTX_TYPE
2451 == DOWN_STREAM_DETAILED_HDMI) {
2452 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
2453 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
2454 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
2455 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
2456 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
2457 hdmi_caps.bits.YCrCr422_CONVERSION;
2458 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
2459 hdmi_caps.bits.YCrCr420_CONVERSION;
2460 }
03f5c686
CL		 2461
2462 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
6bffebc9
EY		 2463 translate_dpcd_max_bpc(
2464 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
03f5c686 2465
e5490464 2466 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
99b922f9 2467 link->dpcd_caps.dongle_caps.extendedCapValid = true;
4562236b 2468 }
03f5c686 2469
4562236b
HW		 2470 break;
2471 }
2472 }
2473
d0778ebf 2474 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4562236b 2475
4562236b
HW		 2476 {
2477 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2478
2479 core_link_read_dpcd(
2480 link,
3a340294 2481 DP_BRANCH_REVISION_START,
4562236b
HW		 2482 (uint8_t *)&dp_hw_fw_revision,
2483 sizeof(dp_hw_fw_revision));
2484
2485 link->dpcd_caps.branch_hw_revision =
2486 dp_hw_fw_revision.ieee_hw_rev;
4b99affb
A		 2487
2488 memmove(
2489 link->dpcd_caps.branch_fw_revision,
2490 dp_hw_fw_revision.ieee_fw_rev,
2491 sizeof(dp_hw_fw_revision.ieee_fw_rev));
4562236b
HW		 2492 }
2493}
2494
d0778ebf 2495static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4562236b
HW		 2496 int length)
2497{
2498 int retry = 0;
2499 union dp_downstream_port_present ds_port = { 0 };
2500
2501 if (!link->dpcd_caps.dpcd_rev.raw) {
2502 do {
2503 dp_receiver_power_ctrl(link, true);
3a340294 2504 core_link_read_dpcd(link, DP_DPCD_REV,
4562236b
HW		 2505 dpcd_data, length);
2506 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3a340294
DA		 2507 DP_DPCD_REV -
2508 DP_DPCD_REV];
4562236b
HW		 2509 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
2510 }
2511
3a340294
DA		 2512 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2513 DP_DPCD_REV];
4562236b
HW		 2514
2515 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
2516 switch (link->dpcd_caps.branch_dev_id) {
2517 /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
2518 * all internal circuits including AUX communication preventing
2519 * reading DPCD table and EDID (spec violation).
2520 * Encoder will skip DP RX power down on disable_output to
2521 * keep receiver powered all the time.*/
2522 case DP_BRANCH_DEVICE_ID_1:
2523 case DP_BRANCH_DEVICE_ID_4:
2524 link->wa_flags.dp_keep_receiver_powered = true;
2525 break;
2526
2527 /* TODO: May need work around for other dongles. */
2528 default:
2529 link->wa_flags.dp_keep_receiver_powered = false;
2530 break;
2531 }
2532 } else
2533 link->wa_flags.dp_keep_receiver_powered = false;
2534}
2535
cdb39798 2536static bool retrieve_link_cap(struct dc_link *link)
4562236b 2537{
794550c6 2538 uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
4562236b 2539
3c7dd2cb
HT		 2540 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
2541 */
2542 uint8_t dpcd_dprx_data = '\0';
8633d96d 2543 uint8_t dpcd_power_state = '\0';
3c7dd2cb 2544
8ca80900 2545 struct dp_device_vendor_id sink_id;
4562236b
HW		 2546 union down_stream_port_count down_strm_port_count;
2547 union edp_configuration_cap edp_config_cap;
2548 union dp_downstream_port_present ds_port = { 0 };
cdb39798 2549 enum dc_status status = DC_ERROR_UNEXPECTED;
3c1a312a
YS		 2550 uint32_t read_dpcd_retry_cnt = 3;
2551 int i;
4b99affb 2552 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
4562236b
HW		 2553
2554 memset(dpcd_data, '\0', sizeof(dpcd_data));
2555 memset(&down_strm_port_count,
2556 '\0', sizeof(union down_stream_port_count));
2557 memset(&edp_config_cap, '\0',
2558 sizeof(union edp_configuration_cap));
2559
8633d96d
AK		 2560 status = core_link_read_dpcd(link, DP_SET_POWER,
2561 &dpcd_power_state, sizeof(dpcd_power_state));
2562
2563 /* Delay 1 ms if AUX CH is in power down state. Based on spec
2564 * section 2.3.1.2, if AUX CH may be powered down due to
2565 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
2566 * signal and may need up to 1 ms before being able to reply.
2567 */
2568 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
2569 udelay(1000);
2570
3c1a312a
YS		 2571 for (i = 0; i < read_dpcd_retry_cnt; i++) {
2572 status = core_link_read_dpcd(
2573 link,
2574 DP_DPCD_REV,
2575 dpcd_data,
2576 sizeof(dpcd_data));
2577 if (status == DC_OK)
2578 break;
2579 }
cdb39798
YS		 2580
2581 if (status != DC_OK) {
2582 dm_error("%s: Read dpcd data failed.\n", __func__);
2583 return false;
2584 }
4562236b 2585
4562236b
HW		 2586 {
2587 union training_aux_rd_interval aux_rd_interval;
2588
2589 aux_rd_interval.raw =
3a340294 2590 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
4562236b 2591
3c7dd2cb
HT		 2592 link->dpcd_caps.ext_receiver_cap_field_present =
2593 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1 ? true:false;
2594
2595 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
818832bf
XY		 2596 uint8_t ext_cap_data[16];
2597
2598 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
2599 for (i = 0; i < read_dpcd_retry_cnt; i++) {
2600 status = core_link_read_dpcd(
4562236b 2601 link,
3a340294 2602 DP_DP13_DPCD_REV,
818832bf
XY		 2603 ext_cap_data,
2604 sizeof(ext_cap_data));
2605 if (status == DC_OK) {
2606 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
2607 break;
2608 }
2609 }
2610 if (status != DC_OK)
2611 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
4562236b
HW		 2612 }
2613 }
2614
3c7dd2cb
HT		 2615 link->dpcd_caps.dpcd_rev.raw =
2616 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
2617
2618 if (link->dpcd_caps.dpcd_rev.raw >= 0x14) {
2619 for (i = 0; i < read_dpcd_retry_cnt; i++) {
2620 status = core_link_read_dpcd(
2621 link,
2622 DP_DPRX_FEATURE_ENUMERATION_LIST,
2623 &dpcd_dprx_data,
2624 sizeof(dpcd_dprx_data));
2625 if (status == DC_OK)
2626 break;
2627 }
2628
2629 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
2630
2631 if (status != DC_OK)
2632 dm_error("%s: Read DPRX caps data failed.\n", __func__);
2633 }
2634
2635 else {
2636 link->dpcd_caps.dprx_feature.raw = 0;
2637 }
2638
2639
07d6a199
AK		 2640 /* Error condition checking...
2641 * It is impossible for Sink to report Max Lane Count = 0.
2642 * It is possible for Sink to report Max Link Rate = 0, if it is
2643 * an eDP device that is reporting specialized link rates in the
2644 * SUPPORTED_LINK_RATE table.
2645 */
2646 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
2647 return false;
2648
3a340294
DA		 2649 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2650 DP_DPCD_REV];
4562236b 2651
ee13cea9
JB		 2652 read_dp_device_vendor_id(link);
2653
4562236b
HW		 2654 get_active_converter_info(ds_port.byte, link);
2655
2656 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2657
98e6436d
AK		 2658 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
2659 DP_DPCD_REV];
2660
4562236b
HW		 2661 link->dpcd_caps.allow_invalid_MSA_timing_param =
2662 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2663
2664 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3a340294 2665 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4562236b
HW		 2666
2667 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3a340294 2668 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4562236b 2669
d0778ebf 2670 link->reported_link_cap.lane_count =
4562236b 2671 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
d0778ebf 2672 link->reported_link_cap.link_rate = dpcd_data[
3a340294 2673 DP_MAX_LINK_RATE - DP_DPCD_REV];
d0778ebf 2674 link->reported_link_cap.link_spread =
4562236b
HW		 2675 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
2676 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
2677
2678 edp_config_cap.raw = dpcd_data[
3a340294 2679 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4562236b
HW		 2680 link->dpcd_caps.panel_mode_edp =
2681 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
9799624a
WL		 2682 link->dpcd_caps.dpcd_display_control_capable =
2683 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4562236b 2684
d0778ebf
HW		 2685 link->test_pattern_enabled = false;
2686 link->compliance_test_state.raw = 0;
4562236b 2687
4562236b
HW		 2688 /* read sink count */
2689 core_link_read_dpcd(link,
3a340294 2690 DP_SINK_COUNT,
4562236b
HW		 2691 &link->dpcd_caps.sink_count.raw,
2692 sizeof(link->dpcd_caps.sink_count.raw));
2693
8ca80900
AK		 2694 /* read sink ieee oui */
2695 core_link_read_dpcd(link,
2696 DP_SINK_OUI,
2697 (uint8_t *)(&sink_id),
2698 sizeof(sink_id));
2699
2700 link->dpcd_caps.sink_dev_id =
2701 (sink_id.ieee_oui[0] << 16) +
2702 (sink_id.ieee_oui[1] << 8) +
2703 (sink_id.ieee_oui[2]);
2704
4b99affb
A		 2705 memmove(
2706 link->dpcd_caps.sink_dev_id_str,
2707 sink_id.ieee_device_id,
2708 sizeof(sink_id.ieee_device_id));
2709
2710 core_link_read_dpcd(
2711 link,
2712 DP_SINK_HW_REVISION_START,
2713 (uint8_t *)&dp_hw_fw_revision,
2714 sizeof(dp_hw_fw_revision));
2715
2716 link->dpcd_caps.sink_hw_revision =
2717 dp_hw_fw_revision.ieee_hw_rev;
2718
2719 memmove(
2720 link->dpcd_caps.sink_fw_revision,
2721 dp_hw_fw_revision.ieee_fw_rev,
2722 sizeof(dp_hw_fw_revision.ieee_fw_rev));
2723
97bda032 2724#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
39a4eb85
WL		 2725 memset(&link->dpcd_caps.dsc_caps, '\0',
2726 sizeof(link->dpcd_caps.dsc_caps));
97bda032
HW		 2727 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
2728 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
2729 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
97bda032
HW		 2730 status = core_link_read_dpcd(
2731 link,
2732 DP_FEC_CAPABILITY,
2733 &link->dpcd_caps.fec_cap.raw,
2734 sizeof(link->dpcd_caps.fec_cap.raw));
39a4eb85
WL		 2735 status = core_link_read_dpcd(
2736 link,
2737 DP_DSC_SUPPORT,
2738 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
2739 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
2740 status = core_link_read_dpcd(
2741 link,
2742 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
2743 link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
2744 sizeof(link->dpcd_caps.dsc_caps.dsc_ext_caps.raw));
97bda032
HW		 2745 }
2746#endif
6fbefb84 2747
4562236b
HW		 2748 /* Connectivity log: detection */
2749 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
cdb39798
YS		 2750
2751 return true;
4562236b
HW		 2752}
2753
cdb39798 2754bool detect_dp_sink_caps(struct dc_link *link)
4562236b 2755{
cdb39798 2756 return retrieve_link_cap(link);
4562236b
HW		 2757
2758 /* dc init_hw has power encoder using default
2759 * signal for connector. For native DP, no
2760 * need to power up encoder again. If not native
2761 * DP, hw_init may need check signal or power up
2762 * encoder here.
2763 */
4562236b
HW		 2764 /* TODO save sink caps in link->sink */
2765}
2766
b03a599b
DL		 2767enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
2768{
2769 enum dc_link_rate link_rate;
2770 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
2771 switch (link_rate_in_khz) {
2772 case 1620000:
2773 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
2774 break;
2775 case 2160000:
2776 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
2777 break;
2778 case 2430000:
2779 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
2780 break;
2781 case 2700000:
2782 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
2783 break;
2784 case 3240000:
2785 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
2786 break;
2787 case 4320000:
2788 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
2789 break;
2790 case 5400000:
2791 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
2792 break;
2793 case 8100000:
2794 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
2795 break;
2796 default:
2797 link_rate = LINK_RATE_UNKNOWN;
2798 break;
2799 }
2800 return link_rate;
2801}
2802
4654a2f7
RL		 2803void detect_edp_sink_caps(struct dc_link *link)
2804{
8628d02f 2805 uint8_t supported_link_rates[16];
b03a599b
DL		 2806 uint32_t entry;
2807 uint32_t link_rate_in_khz;
2808 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
48231fd5 2809
b03a599b 2810 retrieve_link_cap(link);
8628d02f
JP		 2811 link->dpcd_caps.edp_supported_link_rates_count = 0;
2812 memset(supported_link_rates, 0, sizeof(supported_link_rates));
48231fd5 2813
8628d02f 2814 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
53c81fc7
WC		 2815 (link->dc->config.optimize_edp_link_rate ||
2816 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
b03a599b
DL		 2817 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
2818 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
2819 supported_link_rates, sizeof(supported_link_rates));
2820
b03a599b
DL		 2821 for (entry = 0; entry < 16; entry += 2) {
2822 // DPCD register reports per-lane link rate = 16-bit link rate capability
8628d02f 2823 // value X 200 kHz. Need multiplier to find link rate in kHz.
b03a599b
DL		 2824 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2825 supported_link_rates[entry]) * 200;
2826
2827 if (link_rate_in_khz != 0) {
2828 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
8628d02f
JP		 2829 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
2830 link->dpcd_caps.edp_supported_link_rates_count++;
53c81fc7
WC		 2831
2832 if (link->reported_link_cap.link_rate < link_rate)
2833 link->reported_link_cap.link_rate = link_rate;
b03a599b
DL		 2834 }
2835 }
2836 }
4654a2f7
RL		 2837 link->verified_link_cap = link->reported_link_cap;
2838}
2839
4562236b
HW		 2840void dc_link_dp_enable_hpd(const struct dc_link *link)
2841{
d0778ebf 2842 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2843
2844 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2845 encoder->funcs->enable_hpd(encoder);
2846}
2847
2848void dc_link_dp_disable_hpd(const struct dc_link *link)
2849{
d0778ebf 2850 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2851
2852 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2853 encoder->funcs->disable_hpd(encoder);
2854}
2855
2856static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
2857{
0e19401f
TC		 2858 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
2859 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
2860 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4562236b
HW		 2861 return true;
2862 else
2863 return false;
2864}
2865
d0778ebf 2866static void set_crtc_test_pattern(struct dc_link *link,
4562236b
HW		 2867 struct pipe_ctx *pipe_ctx,
2868 enum dp_test_pattern test_pattern)
2869{
2870 enum controller_dp_test_pattern controller_test_pattern;
2871 enum dc_color_depth color_depth = pipe_ctx->
4fa086b9 2872 stream->timing.display_color_depth;
4562236b 2873 struct bit_depth_reduction_params params;
661a8cd9 2874 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
6fbefb84
HW		 2875#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2876 int width = pipe_ctx->stream->timing.h_addressable +
2877 pipe_ctx->stream->timing.h_border_left +
2878 pipe_ctx->stream->timing.h_border_right;
2879 int height = pipe_ctx->stream->timing.v_addressable +
2880 pipe_ctx->stream->timing.v_border_bottom +
2881 pipe_ctx->stream->timing.v_border_top;
2882#endif
4562236b
HW		 2883
2884 memset(&params, 0, sizeof(params));
2885
2886 switch (test_pattern) {
2887 case DP_TEST_PATTERN_COLOR_SQUARES:
2888 controller_test_pattern =
2889 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2890 break;
2891 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2892 controller_test_pattern =
2893 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
2894 break;
2895 case DP_TEST_PATTERN_VERTICAL_BARS:
2896 controller_test_pattern =
2897 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
2898 break;
2899 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2900 controller_test_pattern =
2901 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
2902 break;
2903 case DP_TEST_PATTERN_COLOR_RAMP:
2904 controller_test_pattern =
2905 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
2906 break;
2907 default:
2908 controller_test_pattern =
2909 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
2910 break;
2911 }
2912
2913 switch (test_pattern) {
2914 case DP_TEST_PATTERN_COLOR_SQUARES:
2915 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2916 case DP_TEST_PATTERN_VERTICAL_BARS:
2917 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2918 case DP_TEST_PATTERN_COLOR_RAMP:
2919 {
2920 /* disable bit depth reduction */
2921 pipe_ctx->stream->bit_depth_params = params;
661a8cd9 2922 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
7f93c1de
CL		 2923 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2924 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b 2925 controller_test_pattern, color_depth);
6fbefb84
HW		 2926#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2927 else if (opp->funcs->opp_set_disp_pattern_generator) {
2928 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
2929
2930 if (bot_odm_pipe) {
2931 struct output_pixel_processor *bot_opp = bot_odm_pipe->stream_res.opp;
2932
2933 bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, &params);
2934 width /= 2;
2935 bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp,
2936 controller_test_pattern,
2937 color_depth,
2938 NULL,
2939 width,
2940 height);
2941 }
2942 opp->funcs->opp_set_disp_pattern_generator(opp,
2943 controller_test_pattern,
2944 color_depth,
2945 NULL,
2946 width,
2947 height);
2948 }
2949#endif
4562236b
HW		 2950 }
2951 break;
2952 case DP_TEST_PATTERN_VIDEO_MODE:
2953 {
2954 /* restore bitdepth reduction */
661a8cd9 2955 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4562236b 2956 pipe_ctx->stream->bit_depth_params = params;
661a8cd9 2957 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
7f93c1de
CL		 2958 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2959 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4562236b
HW		 2960 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2961 color_depth);
6fbefb84
HW		 2962#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2963 else if (opp->funcs->opp_set_disp_pattern_generator) {
2964 struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
2965
2966 if (bot_odm_pipe) {
2967 struct output_pixel_processor *bot_opp = bot_odm_pipe->stream_res.opp;
2968
2969 bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, &params);
2970 width /= 2;
2971 bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp,
2972 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2973 color_depth,
2974 NULL,
2975 width,
2976 height);
2977 }
2978 opp->funcs->opp_set_disp_pattern_generator(opp,
2979 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2980 color_depth,
2981 NULL,
2982 width,
2983 height);
2984 }
2985#endif
4562236b
HW		 2986 }
2987 break;
2988
2989 default:
2990 break;
2991 }
2992}
2993
2994bool dc_link_dp_set_test_pattern(
d0778ebf 2995 struct dc_link *link,
4562236b
HW		 2996 enum dp_test_pattern test_pattern,
2997 const struct link_training_settings *p_link_settings,
2998 const unsigned char *p_custom_pattern,
2999 unsigned int cust_pattern_size)
3000{
608ac7bb 3001 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
0a8f43ff 3002 struct pipe_ctx *pipe_ctx = &pipes[0];
4562236b
HW		 3003 unsigned int lane;
3004 unsigned int i;
3005 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
3006 union dpcd_training_pattern training_pattern;
4562236b
HW		 3007 enum dpcd_phy_test_patterns pattern;
3008
3009 memset(&training_pattern, 0, sizeof(training_pattern));
4562236b
HW		 3010
3011 for (i = 0; i < MAX_PIPES; i++) {
ceb3dbb4 3012 if (pipes[i].stream->link == link) {
0a8f43ff 3013 pipe_ctx = &pipes[i];
4562236b
HW		 3014 break;
3015 }
3016 }
3017
3018 /* Reset CRTC Test Pattern if it is currently running and request
3019 * is VideoMode Reset DP Phy Test Pattern if it is currently running
3020 * and request is VideoMode
3021 */
d0778ebf 3022 if (link->test_pattern_enabled && test_pattern ==
4562236b
HW		 3023 DP_TEST_PATTERN_VIDEO_MODE) {
3024 /* Set CRTC Test Pattern */
0a8f43ff 3025 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
d0778ebf 3026 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 3027 (uint8_t *)p_custom_pattern,
3028 (uint32_t)cust_pattern_size);
3029
3030 /* Unblank Stream */
d0778ebf 3031 link->dc->hwss.unblank_stream(
0a8f43ff 3032 pipe_ctx,
d0778ebf 3033 &link->verified_link_cap);
4562236b
HW		 3034 /* TODO:m_pHwss->MuteAudioEndpoint
3035 * (pPathMode->pDisplayPath, false);
3036 */
3037
3038 /* Reset Test Pattern state */
d0778ebf 3039 link->test_pattern_enabled = false;
4562236b
HW		 3040
3041 return true;
3042 }
3043
3044 /* Check for PHY Test Patterns */
3045 if (is_dp_phy_pattern(test_pattern)) {
3046 /* Set DPCD Lane Settings before running test pattern */
3047 if (p_link_settings != NULL) {
d0778ebf
HW		 3048 dp_set_hw_lane_settings(link, p_link_settings);
3049 dpcd_set_lane_settings(link, p_link_settings);
4562236b
HW		 3050 }
3051
3052 /* Blank stream if running test pattern */
3053 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3054 /*TODO:
3055 * m_pHwss->
3056 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
3057 */
3058 /* Blank stream */
8e9c4c8c 3059 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4562236b
HW		 3060 }
3061
d0778ebf 3062 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 3063 (uint8_t *)p_custom_pattern,
3064 (uint32_t)cust_pattern_size);
3065
3066 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3067 /* Set Test Pattern state */
d0778ebf 3068 link->test_pattern_enabled = true;
4562236b 3069 if (p_link_settings != NULL)
d0778ebf 3070 dpcd_set_link_settings(link,
4562236b
HW		 3071 p_link_settings);
3072 }
3073
3074 switch (test_pattern) {
3075 case DP_TEST_PATTERN_VIDEO_MODE:
3076 pattern = PHY_TEST_PATTERN_NONE;
0e19401f 3077 break;
4562236b
HW		 3078 case DP_TEST_PATTERN_D102:
3079 pattern = PHY_TEST_PATTERN_D10_2;
0e19401f 3080 break;
4562236b
HW		 3081 case DP_TEST_PATTERN_SYMBOL_ERROR:
3082 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 3083 break;
4562236b
HW		 3084 case DP_TEST_PATTERN_PRBS7:
3085 pattern = PHY_TEST_PATTERN_PRBS7;
0e19401f 3086 break;
4562236b
HW		 3087 case DP_TEST_PATTERN_80BIT_CUSTOM:
3088 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 3089 break;
3090 case DP_TEST_PATTERN_CP2520_1:
3091 pattern = PHY_TEST_PATTERN_CP2520_1;
3092 break;
3093 case DP_TEST_PATTERN_CP2520_2:
3094 pattern = PHY_TEST_PATTERN_CP2520_2;
3095 break;
3096 case DP_TEST_PATTERN_CP2520_3:
3097 pattern = PHY_TEST_PATTERN_CP2520_3;
3098 break;
4562236b
HW		 3099 default:
3100 return false;
3101 }
3102
3103 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
3104 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
3105 return false;
3106
d0778ebf 3107 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 3108 /* tell receiver that we are sending qualification
3109 * pattern DP 1.2 or later - DP receiver's link quality
3110 * pattern is set using DPCD LINK_QUAL_LANEx_SET
3111 * register (0x10B~0x10E)\
3112 */
3113 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
3114 link_qual_pattern[lane] =
3115 (unsigned char)(pattern);
3116
d0778ebf 3117 core_link_write_dpcd(link,
3a340294 3118 DP_LINK_QUAL_LANE0_SET,
4562236b
HW		 3119 link_qual_pattern,
3120 sizeof(link_qual_pattern));
d0778ebf
HW		 3121 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
3122 link->dpcd_caps.dpcd_rev.raw == 0) {
4562236b
HW		 3123 /* tell receiver that we are sending qualification
3124 * pattern DP 1.1a or earlier - DP receiver's link
3125 * quality pattern is set using
3126 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
3127 * register (0x102). We will use v_1.3 when we are
3128 * setting test pattern for DP 1.1.
3129 */
d0778ebf
HW		 3130 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
3131 &training_pattern.raw,
3132 sizeof(training_pattern));
4562236b 3133 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
d0778ebf
HW		 3134 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
3135 &training_pattern.raw,
3136 sizeof(training_pattern));
4562236b
HW		 3137 }
3138 } else {
3139 /* CRTC Patterns */
0a8f43ff 3140 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
4562236b 3141 /* Set Test Pattern state */
d0778ebf 3142 link->test_pattern_enabled = true;
4562236b
HW		 3143 }
3144
3145 return true;
3146}
07c84c7a 3147
d0778ebf 3148void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
07c84c7a
DW		 3149{
3150 unsigned char mstmCntl;
3151
3152 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
3153 if (enable)
3154 mstmCntl |= DP_MST_EN;
3155 else
3156 mstmCntl &= (~DP_MST_EN);
3157
3158 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
3159}
6fbefb84 3160
97bda032
HW		 3161#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3162void dp_set_fec_ready(struct dc_link *link, bool ready)
3163{
3164 /* FEC has to be "set ready" before the link training.
3165 * The policy is to always train with FEC
3166 * if the sink supports it and leave it enabled on link.
3167 * If FEC is not supported, disable it.
3168 */
3169 struct link_encoder *link_enc = link->link_enc;
3170 uint8_t fec_config = 0;
3171
3172 if (link->dc->debug.disable_fec ||
3173 IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
3174 return;
3175
3176 if (link_enc->funcs->fec_set_ready &&
3177 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
008a4016 3178 if (ready) {
97bda032
HW		 3179 fec_config = 1;
3180 if (core_link_write_dpcd(link,
3181 DP_FEC_CONFIGURATION,
3182 &fec_config,
3183 sizeof(fec_config)) == DC_OK) {
3184 link_enc->funcs->fec_set_ready(link_enc, true);
3185 link->fec_state = dc_link_fec_ready;
3186 } else {
d68a7454
NC		 3187 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
3188 link->fec_state = dc_link_fec_not_ready;
97bda032
HW		 3189 dm_error("dpcd write failed to set fec_ready");
3190 }
008a4016 3191 } else if (link->fec_state == dc_link_fec_ready) {
97bda032
HW		 3192 fec_config = 0;
3193 core_link_write_dpcd(link,
3194 DP_FEC_CONFIGURATION,
3195 &fec_config,
3196 sizeof(fec_config));
3197 link->link_enc->funcs->fec_set_ready(
3198 link->link_enc, false);
3199 link->fec_state = dc_link_fec_not_ready;
3200 }
3201 }
3202}
3203
3204void dp_set_fec_enable(struct dc_link *link, bool enable)
3205{
3206 struct link_encoder *link_enc = link->link_enc;
3207
3208 if (link->dc->debug.disable_fec ||
3209 IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
3210 return;
3211
3212 if (link_enc->funcs->fec_set_enable &&
3213 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
3214 if (link->fec_state == dc_link_fec_ready && enable) {
3215 msleep(1);
3216 link_enc->funcs->fec_set_enable(link_enc, true);
3217 link->fec_state = dc_link_fec_enabled;
3218 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
3219 link_enc->funcs->fec_set_enable(link_enc, false);
3220 link->fec_state = dc_link_fec_ready;
3221 }
3222 }
3223}
3224#endif
6fbefb84 3225
Linux 6.x block layer and io_uring tree(s)