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drm/amd/display: log HUBP using DTN logging
[linux-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c
CommitLineData
4562236b
HW		 1/* Copyright 2015 Advanced Micro Devices, Inc. */
2#include "dm_services.h"
3#include "dc.h"
4#include "dc_link_dp.h"
5#include "dm_helpers.h"
6
7#include "inc/core_types.h"
8#include "link_hwss.h"
9#include "dc_link_ddc.h"
10#include "core_status.h"
11#include "dpcd_defs.h"
12
13#include "core_dc.h"
529cad0f 14#include "resource.h"
4562236b
HW		 15
16/* maximum pre emphasis level allowed for each voltage swing level*/
17static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
18 PRE_EMPHASIS_LEVEL3,
19 PRE_EMPHASIS_LEVEL2,
20 PRE_EMPHASIS_LEVEL1,
21 PRE_EMPHASIS_DISABLED };
22
23enum {
24 POST_LT_ADJ_REQ_LIMIT = 6,
25 POST_LT_ADJ_REQ_TIMEOUT = 200
26};
27
28enum {
29 LINK_TRAINING_MAX_RETRY_COUNT = 5,
30 /* to avoid infinite loop where-in the receiver
31 * switches between different VS
32 */
33 LINK_TRAINING_MAX_CR_RETRY = 100
34};
35
4562236b 36static void wait_for_training_aux_rd_interval(
d0778ebf 37 struct dc_link *link,
4562236b
HW		 38 uint32_t default_wait_in_micro_secs)
39{
40 union training_aux_rd_interval training_rd_interval;
41
42 /* overwrite the delay if rev > 1.1*/
43 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
44 /* DP 1.2 or later - retrieve delay through
45 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
46 core_link_read_dpcd(
47 link,
3a340294 48 DP_TRAINING_AUX_RD_INTERVAL,
4562236b
HW		 49 (uint8_t *)&training_rd_interval,
50 sizeof(training_rd_interval));
51
52 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
53 default_wait_in_micro_secs =
54 training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
55 }
56
57 udelay(default_wait_in_micro_secs);
58
59 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
60 "%s:\n wait = %d\n",
61 __func__,
62 default_wait_in_micro_secs);
63}
64
65static void dpcd_set_training_pattern(
d0778ebf 66 struct dc_link *link,
4562236b
HW		 67 union dpcd_training_pattern dpcd_pattern)
68{
69 core_link_write_dpcd(
70 link,
3a340294 71 DP_TRAINING_PATTERN_SET,
4562236b
HW		 72 &dpcd_pattern.raw,
73 1);
74
75 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
76 "%s\n %x pattern = %x\n",
77 __func__,
3a340294 78 DP_TRAINING_PATTERN_SET,
4562236b
HW		 79 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
80}
81
82static void dpcd_set_link_settings(
d0778ebf 83 struct dc_link *link,
4562236b
HW		 84 const struct link_training_settings *lt_settings)
85{
86 uint8_t rate = (uint8_t)
87 (lt_settings->link_settings.link_rate);
88
89 union down_spread_ctrl downspread = {{0}};
90 union lane_count_set lane_count_set = {{0}};
91 uint8_t link_set_buffer[2];
92
93 downspread.raw = (uint8_t)
94 (lt_settings->link_settings.link_spread);
95
96 lane_count_set.bits.LANE_COUNT_SET =
97 lt_settings->link_settings.lane_count;
98
99 lane_count_set.bits.ENHANCED_FRAMING = 1;
100
101 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
102 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
103
104 link_set_buffer[0] = rate;
105 link_set_buffer[1] = lane_count_set.raw;
106
3a340294 107 core_link_write_dpcd(link, DP_LINK_BW_SET,
4562236b 108 link_set_buffer, 2);
3a340294 109 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
4562236b
HW		 110 &downspread.raw, sizeof(downspread));
111
112 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
113 "%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
114 __func__,
3a340294 115 DP_LINK_BW_SET,
4562236b 116 lt_settings->link_settings.link_rate,
3a340294 117 DP_LANE_COUNT_SET,
4562236b 118 lt_settings->link_settings.lane_count,
3a340294 119 DP_DOWNSPREAD_CTRL,
4562236b
HW		 120 lt_settings->link_settings.link_spread);
121
122}
123
124static enum dpcd_training_patterns
125 hw_training_pattern_to_dpcd_training_pattern(
d0778ebf 126 struct dc_link *link,
4562236b
HW		 127 enum hw_dp_training_pattern pattern)
128{
129 enum dpcd_training_patterns dpcd_tr_pattern =
130 DPCD_TRAINING_PATTERN_VIDEOIDLE;
131
132 switch (pattern) {
133 case HW_DP_TRAINING_PATTERN_1:
134 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
135 break;
136 case HW_DP_TRAINING_PATTERN_2:
137 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
138 break;
139 case HW_DP_TRAINING_PATTERN_3:
140 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
141 break;
142 case HW_DP_TRAINING_PATTERN_4:
143 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
144 break;
145 default:
146 ASSERT(0);
147 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
148 "%s: Invalid HW Training pattern: %d\n",
149 __func__, pattern);
150 break;
151 }
152
153 return dpcd_tr_pattern;
154
155}
156
157static void dpcd_set_lt_pattern_and_lane_settings(
d0778ebf 158 struct dc_link *link,
4562236b
HW		 159 const struct link_training_settings *lt_settings,
160 enum hw_dp_training_pattern pattern)
161{
162 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
163 const uint32_t dpcd_base_lt_offset =
3a340294 164 DP_TRAINING_PATTERN_SET;
4562236b
HW		 165 uint8_t dpcd_lt_buffer[5] = {0};
166 union dpcd_training_pattern dpcd_pattern = {{0}};
167 uint32_t lane;
168 uint32_t size_in_bytes;
169 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
170
171 /*****************************************************************
172 * DpcdAddress_TrainingPatternSet
173 *****************************************************************/
174 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
175 hw_training_pattern_to_dpcd_training_pattern(link, pattern);
176
3a340294 177 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
4562236b
HW		 178 = dpcd_pattern.raw;
179
180 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
181 "%s\n %x pattern = %x\n",
182 __func__,
3a340294 183 DP_TRAINING_PATTERN_SET,
4562236b
HW		 184 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
185
186 /*****************************************************************
187 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
188 *****************************************************************/
189 for (lane = 0; lane <
190 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
191
192 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
193 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
194 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
195 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
196
197 dpcd_lane[lane].bits.MAX_SWING_REACHED =
198 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
199 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
200 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
201 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
202 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
203 }
204
205 /* concatinate everything into one buffer*/
206
207 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
208
209 // 0x00103 - 0x00102
210 memmove(
3a340294 211 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
4562236b
HW		 212 dpcd_lane,
213 size_in_bytes);
214
215 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
216 "%s:\n %x VS set = %x PE set = %x \
217 max VS Reached = %x max PE Reached = %x\n",
218 __func__,
3a340294 219 DP_TRAINING_LANE0_SET,
4562236b
HW		 220 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
221 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
222 dpcd_lane[0].bits.MAX_SWING_REACHED,
223 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
224
225 if (edp_workaround) {
226 /* for eDP write in 2 parts because the 5-byte burst is
227 * causing issues on some eDP panels (EPR#366724)
228 */
229 core_link_write_dpcd(
230 link,
3a340294 231 DP_TRAINING_PATTERN_SET,
4562236b
HW		 232 &dpcd_pattern.raw,
233 sizeof(dpcd_pattern.raw) );
234
235 core_link_write_dpcd(
236 link,
3a340294 237 DP_TRAINING_LANE0_SET,
4562236b
HW		 238 (uint8_t *)(dpcd_lane),
239 size_in_bytes);
240
241 } else
242 /* write it all in (1 + number-of-lanes)-byte burst*/
243 core_link_write_dpcd(
244 link,
245 dpcd_base_lt_offset,
246 dpcd_lt_buffer,
247 size_in_bytes + sizeof(dpcd_pattern.raw) );
248
d0778ebf 249 link->cur_lane_setting = lt_settings->lane_settings[0];
4562236b
HW		 250}
251
252static bool is_cr_done(enum dc_lane_count ln_count,
253 union lane_status *dpcd_lane_status)
254{
255 bool done = true;
256 uint32_t lane;
257 /*LANEx_CR_DONE bits All 1's?*/
258 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
259 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
260 done = false;
261 }
262 return done;
263
264}
265
266static bool is_ch_eq_done(enum dc_lane_count ln_count,
267 union lane_status *dpcd_lane_status,
268 union lane_align_status_updated *lane_status_updated)
269{
270 bool done = true;
271 uint32_t lane;
272 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
273 done = false;
274 else {
275 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
276 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
277 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
278 done = false;
279 }
280 }
281 return done;
282
283}
284
285static void update_drive_settings(
286 struct link_training_settings *dest,
287 struct link_training_settings src)
288{
289 uint32_t lane;
290 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
291 dest->lane_settings[lane].VOLTAGE_SWING =
292 src.lane_settings[lane].VOLTAGE_SWING;
293 dest->lane_settings[lane].PRE_EMPHASIS =
294 src.lane_settings[lane].PRE_EMPHASIS;
295 dest->lane_settings[lane].POST_CURSOR2 =
296 src.lane_settings[lane].POST_CURSOR2;
297 }
298}
299
300static uint8_t get_nibble_at_index(const uint8_t *buf,
301 uint32_t index)
302{
303 uint8_t nibble;
304 nibble = buf[index / 2];
305
306 if (index % 2)
307 nibble >>= 4;
308 else
309 nibble &= 0x0F;
310
311 return nibble;
312}
313
314static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
315 enum dc_voltage_swing voltage)
316{
317 enum dc_pre_emphasis pre_emphasis;
318 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
319
320 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
321 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
322
323 return pre_emphasis;
324
325}
326
327static void find_max_drive_settings(
328 const struct link_training_settings *link_training_setting,
329 struct link_training_settings *max_lt_setting)
330{
331 uint32_t lane;
332 struct dc_lane_settings max_requested;
333
334 max_requested.VOLTAGE_SWING =
335 link_training_setting->
336 lane_settings[0].VOLTAGE_SWING;
337 max_requested.PRE_EMPHASIS =
338 link_training_setting->
339 lane_settings[0].PRE_EMPHASIS;
340 /*max_requested.postCursor2 =
341 * link_training_setting->laneSettings[0].postCursor2;*/
342
343 /* Determine what the maximum of the requested settings are*/
344 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
345 lane++) {
346 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
347 max_requested.VOLTAGE_SWING)
348
349 max_requested.VOLTAGE_SWING =
350 link_training_setting->
351 lane_settings[lane].VOLTAGE_SWING;
352
353 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
354 max_requested.PRE_EMPHASIS)
355 max_requested.PRE_EMPHASIS =
356 link_training_setting->
357 lane_settings[lane].PRE_EMPHASIS;
358
359 /*
360 if (link_training_setting->laneSettings[lane].postCursor2 >
361 max_requested.postCursor2)
362 {
363 max_requested.postCursor2 =
364 link_training_setting->laneSettings[lane].postCursor2;
365 }
366 */
367 }
368
369 /* make sure the requested settings are
370 * not higher than maximum settings*/
371 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
372 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
373
374 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
375 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
376 /*
377 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
378 max_requested.postCursor2 = PostCursor2_MaxLevel;
379 */
380
381 /* make sure the pre-emphasis matches the voltage swing*/
382 if (max_requested.PRE_EMPHASIS >
383 get_max_pre_emphasis_for_voltage_swing(
384 max_requested.VOLTAGE_SWING))
385 max_requested.PRE_EMPHASIS =
386 get_max_pre_emphasis_for_voltage_swing(
387 max_requested.VOLTAGE_SWING);
388
389 /*
390 * Post Cursor2 levels are completely independent from
391 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
392 * can only be applied to each allowable combination of voltage
393 * swing and pre-emphasis levels */
394 /* if ( max_requested.postCursor2 >
395 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
396 * max_requested.postCursor2 =
397 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
398 */
399
400 max_lt_setting->link_settings.link_rate =
401 link_training_setting->link_settings.link_rate;
402 max_lt_setting->link_settings.lane_count =
403 link_training_setting->link_settings.lane_count;
404 max_lt_setting->link_settings.link_spread =
405 link_training_setting->link_settings.link_spread;
406
407 for (lane = 0; lane <
408 link_training_setting->link_settings.lane_count;
409 lane++) {
410 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
411 max_requested.VOLTAGE_SWING;
412 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
413 max_requested.PRE_EMPHASIS;
414 /*max_lt_setting->laneSettings[lane].postCursor2 =
415 * max_requested.postCursor2;
416 */
417 }
418
419}
420
421static void get_lane_status_and_drive_settings(
d0778ebf 422 struct dc_link *link,
4562236b
HW		 423 const struct link_training_settings *link_training_setting,
424 union lane_status *ln_status,
425 union lane_align_status_updated *ln_status_updated,
426 struct link_training_settings *req_settings)
427{
428 uint8_t dpcd_buf[6] = {0};
429 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {{{0}}};
430 struct link_training_settings request_settings = {{0}};
431 uint32_t lane;
432
433 memset(req_settings, '\0', sizeof(struct link_training_settings));
434
435 core_link_read_dpcd(
436 link,
3a340294 437 DP_LANE0_1_STATUS,
4562236b
HW		 438 (uint8_t *)(dpcd_buf),
439 sizeof(dpcd_buf));
440
441 for (lane = 0; lane <
442 (uint32_t)(link_training_setting->link_settings.lane_count);
443 lane++) {
444
445 ln_status[lane].raw =
446 get_nibble_at_index(&dpcd_buf[0], lane);
447 dpcd_lane_adjust[lane].raw =
448 get_nibble_at_index(&dpcd_buf[4], lane);
449 }
450
451 ln_status_updated->raw = dpcd_buf[2];
452
453 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
454 "%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
455 __func__,
3a340294
DA		 456 DP_LANE0_1_STATUS, dpcd_buf[0],
457 DP_LANE2_3_STATUS, dpcd_buf[1]);
4562236b
HW		 458
459 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
460 "%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
461 __func__,
3a340294 462 DP_ADJUST_REQUEST_LANE0_1,
4562236b 463 dpcd_buf[4],
3a340294 464 DP_ADJUST_REQUEST_LANE2_3,
4562236b
HW		 465 dpcd_buf[5]);
466
467 /*copy to req_settings*/
468 request_settings.link_settings.lane_count =
469 link_training_setting->link_settings.lane_count;
470 request_settings.link_settings.link_rate =
471 link_training_setting->link_settings.link_rate;
472 request_settings.link_settings.link_spread =
473 link_training_setting->link_settings.link_spread;
474
475 for (lane = 0; lane <
476 (uint32_t)(link_training_setting->link_settings.lane_count);
477 lane++) {
478
479 request_settings.lane_settings[lane].VOLTAGE_SWING =
480 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
481 VOLTAGE_SWING_LANE);
482 request_settings.lane_settings[lane].PRE_EMPHASIS =
483 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
484 PRE_EMPHASIS_LANE);
485 }
486
487 /*Note: for postcursor2, read adjusted
488 * postcursor2 settings from*/
489 /*DpcdAddress_AdjustRequestPostCursor2 =
490 *0x020C (not implemented yet)*/
491
492 /* we find the maximum of the requested settings across all lanes*/
493 /* and set this maximum for all lanes*/
494 find_max_drive_settings(&request_settings, req_settings);
495
496 /* if post cursor 2 is needed in the future,
497 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
498 */
499
500}
501
502static void dpcd_set_lane_settings(
d0778ebf 503 struct dc_link *link,
4562236b
HW		 504 const struct link_training_settings *link_training_setting)
505{
506 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
507 uint32_t lane;
508
509 for (lane = 0; lane <
510 (uint32_t)(link_training_setting->
511 link_settings.lane_count);
512 lane++) {
513 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
514 (uint8_t)(link_training_setting->
515 lane_settings[lane].VOLTAGE_SWING);
516 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
517 (uint8_t)(link_training_setting->
518 lane_settings[lane].PRE_EMPHASIS);
519 dpcd_lane[lane].bits.MAX_SWING_REACHED =
520 (link_training_setting->
521 lane_settings[lane].VOLTAGE_SWING ==
522 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
523 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
524 (link_training_setting->
525 lane_settings[lane].PRE_EMPHASIS ==
526 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
527 }
528
529 core_link_write_dpcd(link,
3a340294 530 DP_TRAINING_LANE0_SET,
4562236b
HW		 531 (uint8_t *)(dpcd_lane),
532 link_training_setting->link_settings.lane_count);
533
534 /*
535 if (LTSettings.link.rate == LinkRate_High2)
536 {
537 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
538 for ( uint32_t lane = 0;
539 lane < lane_count_DPMax; lane++)
540 {
541 dpcd_lane2[lane].bits.post_cursor2_set =
542 static_cast<unsigned char>(
543 LTSettings.laneSettings[lane].postCursor2);
544 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
545 }
546 m_pDpcdAccessSrv->WriteDpcdData(
547 DpcdAddress_Lane0Set2,
548 reinterpret_cast<unsigned char*>(dpcd_lane2),
549 LTSettings.link.lanes);
550 }
551 */
552
553 dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
554 "%s\n %x VS set = %x PE set = %x \
555 max VS Reached = %x max PE Reached = %x\n",
556 __func__,
3a340294 557 DP_TRAINING_LANE0_SET,
4562236b
HW		 558 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
559 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
560 dpcd_lane[0].bits.MAX_SWING_REACHED,
561 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
562
d0778ebf 563 link->cur_lane_setting = link_training_setting->lane_settings[0];
4562236b
HW		 564
565}
566
567static bool is_max_vs_reached(
568 const struct link_training_settings *lt_settings)
569{
570 uint32_t lane;
571 for (lane = 0; lane <
572 (uint32_t)(lt_settings->link_settings.lane_count);
573 lane++) {
574 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
575 == VOLTAGE_SWING_MAX_LEVEL)
576 return true;
577 }
578 return false;
579
580}
581
582void dc_link_dp_set_drive_settings(
d0778ebf 583 struct dc_link *link,
4562236b
HW		 584 struct link_training_settings *lt_settings)
585{
4562236b 586 /* program ASIC PHY settings*/
d0778ebf 587 dp_set_hw_lane_settings(link, lt_settings);
4562236b
HW		 588
589 /* Notify DP sink the PHY settings from source */
d0778ebf 590 dpcd_set_lane_settings(link, lt_settings);
4562236b
HW		 591}
592
593static bool perform_post_lt_adj_req_sequence(
d0778ebf 594 struct dc_link *link,
4562236b
HW		 595 struct link_training_settings *lt_settings)
596{
597 enum dc_lane_count lane_count =
598 lt_settings->link_settings.lane_count;
599
600 uint32_t adj_req_count;
601 uint32_t adj_req_timer;
602 bool req_drv_setting_changed;
603 uint32_t lane;
604
605 req_drv_setting_changed = false;
606 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
607 adj_req_count++) {
608
609 req_drv_setting_changed = false;
610
611 for (adj_req_timer = 0;
612 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
613 adj_req_timer++) {
614
615 struct link_training_settings req_settings;
616 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
617 union lane_align_status_updated
618 dpcd_lane_status_updated;
619
620 get_lane_status_and_drive_settings(
621 link,
622 lt_settings,
623 dpcd_lane_status,
624 &dpcd_lane_status_updated,
625 &req_settings);
626
627 if (dpcd_lane_status_updated.bits.
628 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
629 return true;
630
631 if (!is_cr_done(lane_count, dpcd_lane_status))
632 return false;
633
634 if (!is_ch_eq_done(
635 lane_count,
636 dpcd_lane_status,
637 &dpcd_lane_status_updated))
638 return false;
639
640 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
641
642 if (lt_settings->
643 lane_settings[lane].VOLTAGE_SWING !=
644 req_settings.lane_settings[lane].
645 VOLTAGE_SWING ||
646 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
647 req_settings.lane_settings[lane].PRE_EMPHASIS) {
648
649 req_drv_setting_changed = true;
650 break;
651 }
652 }
653
654 if (req_drv_setting_changed) {
655 update_drive_settings(
656 lt_settings,req_settings);
657
d0778ebf 658 dc_link_dp_set_drive_settings(link,
4562236b
HW		 659 lt_settings);
660 break;
661 }
662
663 msleep(1);
664 }
665
666 if (!req_drv_setting_changed) {
667 dm_logger_write(link->ctx->logger, LOG_WARNING,
668 "%s: Post Link Training Adjust Request Timed out\n",
669 __func__);
670
671 ASSERT(0);
672 return true;
673 }
674 }
675 dm_logger_write(link->ctx->logger, LOG_WARNING,
676 "%s: Post Link Training Adjust Request limit reached\n",
677 __func__);
678
679 ASSERT(0);
680 return true;
681
682}
683
d0778ebf 684static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
4562236b
HW		 685{
686 enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
687 struct encoder_feature_support *features = &link->link_enc->features;
688 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
689
690 if (features->flags.bits.IS_TPS3_CAPABLE)
691 highest_tp = HW_DP_TRAINING_PATTERN_3;
692
693 if (features->flags.bits.IS_TPS4_CAPABLE)
694 highest_tp = HW_DP_TRAINING_PATTERN_4;
695
696 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
697 highest_tp >= HW_DP_TRAINING_PATTERN_4)
698 return HW_DP_TRAINING_PATTERN_4;
699
700 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
701 highest_tp >= HW_DP_TRAINING_PATTERN_3)
702 return HW_DP_TRAINING_PATTERN_3;
703
704 return HW_DP_TRAINING_PATTERN_2;
705}
706
820e3935 707static enum link_training_result perform_channel_equalization_sequence(
d0778ebf 708 struct dc_link *link,
4562236b
HW		 709 struct link_training_settings *lt_settings)
710{
711 struct link_training_settings req_settings;
712 enum hw_dp_training_pattern hw_tr_pattern;
713 uint32_t retries_ch_eq;
714 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
715 union lane_align_status_updated dpcd_lane_status_updated = {{0}};
716 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};;
717
718 hw_tr_pattern = get_supported_tp(link);
719
720 dp_set_hw_training_pattern(link, hw_tr_pattern);
721
722 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
723 retries_ch_eq++) {
724
725 dp_set_hw_lane_settings(link, lt_settings);
726
727 /* 2. update DPCD*/
728 if (!retries_ch_eq)
729 /* EPR #361076 - write as a 5-byte burst,
730 * but only for the 1-st iteration*/
731 dpcd_set_lt_pattern_and_lane_settings(
732 link,
733 lt_settings,
734 hw_tr_pattern);
735 else
736 dpcd_set_lane_settings(link, lt_settings);
737
738 /* 3. wait for receiver to lock-on*/
739 wait_for_training_aux_rd_interval(link, 400);
740
741 /* 4. Read lane status and requested
742 * drive settings as set by the sink*/
743
744 get_lane_status_and_drive_settings(
745 link,
746 lt_settings,
747 dpcd_lane_status,
748 &dpcd_lane_status_updated,
749 &req_settings);
750
751 /* 5. check CR done*/
752 if (!is_cr_done(lane_count, dpcd_lane_status))
820e3935 753 return LINK_TRAINING_EQ_FAIL_CR;
4562236b
HW		 754
755 /* 6. check CHEQ done*/
756 if (is_ch_eq_done(lane_count,
757 dpcd_lane_status,
758 &dpcd_lane_status_updated))
820e3935 759 return LINK_TRAINING_SUCCESS;
4562236b
HW		 760
761 /* 7. update VS/PE/PC2 in lt_settings*/
762 update_drive_settings(lt_settings, req_settings);
763 }
764
820e3935 765 return LINK_TRAINING_EQ_FAIL_EQ;
4562236b
HW		 766
767}
768
769static bool perform_clock_recovery_sequence(
d0778ebf 770 struct dc_link *link,
4562236b
HW		 771 struct link_training_settings *lt_settings)
772{
773 uint32_t retries_cr;
774 uint32_t retry_count;
775 uint32_t lane;
776 struct link_training_settings req_settings;
777 enum dc_lane_count lane_count =
778 lt_settings->link_settings.lane_count;
779 enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
780 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
781 union lane_align_status_updated dpcd_lane_status_updated;
782
783 retries_cr = 0;
784 retry_count = 0;
785 /* initial drive setting (VS/PE/PC2)*/
786 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
787 lt_settings->lane_settings[lane].VOLTAGE_SWING =
788 VOLTAGE_SWING_LEVEL0;
789 lt_settings->lane_settings[lane].PRE_EMPHASIS =
790 PRE_EMPHASIS_DISABLED;
791 lt_settings->lane_settings[lane].POST_CURSOR2 =
792 POST_CURSOR2_DISABLED;
793 }
794
795 dp_set_hw_training_pattern(link, hw_tr_pattern);
796
797 /* najeeb - The synaptics MST hub can put the LT in
798 * infinite loop by switching the VS
799 */
800 /* between level 0 and level 1 continuously, here
801 * we try for CR lock for LinkTrainingMaxCRRetry count*/
802 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
803 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
804
805 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
806 memset(&dpcd_lane_status_updated, '\0',
807 sizeof(dpcd_lane_status_updated));
808
809 /* 1. call HWSS to set lane settings*/
810 dp_set_hw_lane_settings(
811 link,
812 lt_settings);
813
814 /* 2. update DPCD of the receiver*/
815 if (!retries_cr)
816 /* EPR #361076 - write as a 5-byte burst,
817 * but only for the 1-st iteration.*/
818 dpcd_set_lt_pattern_and_lane_settings(
819 link,
820 lt_settings,
821 hw_tr_pattern);
822 else
823 dpcd_set_lane_settings(
824 link,
825 lt_settings);
826
827 /* 3. wait receiver to lock-on*/
828 wait_for_training_aux_rd_interval(
829 link,
830 100);
831
832 /* 4. Read lane status and requested drive
833 * settings as set by the sink
834 */
835 get_lane_status_and_drive_settings(
836 link,
837 lt_settings,
838 dpcd_lane_status,
839 &dpcd_lane_status_updated,
840 &req_settings);
841
842 /* 5. check CR done*/
843 if (is_cr_done(lane_count, dpcd_lane_status))
844 return true;
845
846 /* 6. max VS reached*/
847 if (is_max_vs_reached(lt_settings))
848 return false;
849
850 /* 7. same voltage*/
851 /* Note: VS same for all lanes,
852 * so comparing first lane is sufficient*/
853 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
854 req_settings.lane_settings[0].VOLTAGE_SWING)
855 retries_cr++;
856 else
857 retries_cr = 0;
858
859 /* 8. update VS/PE/PC2 in lt_settings*/
860 update_drive_settings(lt_settings, req_settings);
861
862 retry_count++;
863 }
864
865 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
866 ASSERT(0);
867 dm_logger_write(link->ctx->logger, LOG_ERROR,
868 "%s: Link Training Error, could not \
869 get CR after %d tries. \
870 Possibly voltage swing issue", __func__,
871 LINK_TRAINING_MAX_CR_RETRY);
872
873 }
874
875 return false;
876}
877
878static inline bool perform_link_training_int(
d0778ebf 879 struct dc_link *link,
4562236b
HW		 880 struct link_training_settings *lt_settings,
881 bool status)
882{
883 union lane_count_set lane_count_set = { {0} };
884 union dpcd_training_pattern dpcd_pattern = { {0} };
885
886 /* 3. set training not in progress*/
887 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
888 dpcd_set_training_pattern(link, dpcd_pattern);
889
890 /* 4. mainlink output idle pattern*/
891 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
892
893 /*
894 * 5. post training adjust if required
895 * If the upstream DPTX and downstream DPRX both support TPS4,
896 * TPS4 must be used instead of POST_LT_ADJ_REQ.
897 */
c30267f5
CL		 898 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
899 get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
4562236b
HW		 900 return status;
901
902 if (status &&
903 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
904 status = false;
905
906 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
907 lane_count_set.bits.ENHANCED_FRAMING = 1;
908 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
909
910 core_link_write_dpcd(
911 link,
3a340294 912 DP_LANE_COUNT_SET,
4562236b
HW		 913 &lane_count_set.raw,
914 sizeof(lane_count_set));
915
916 return status;
917}
918
820e3935 919enum link_training_result dc_link_dp_perform_link_training(
4562236b
HW		 920 struct dc_link *link,
921 const struct dc_link_settings *link_setting,
922 bool skip_video_pattern)
923{
820e3935 924 enum link_training_result status = LINK_TRAINING_SUCCESS;
4562236b
HW		 925
926 char *link_rate = "Unknown";
927 struct link_training_settings lt_settings;
928
4562236b
HW		 929 memset(&lt_settings, '\0', sizeof(lt_settings));
930
931 lt_settings.link_settings.link_rate = link_setting->link_rate;
932 lt_settings.link_settings.lane_count = link_setting->lane_count;
933
934 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
935
936 /* TODO hard coded to SS for now
937 * lt_settings.link_settings.link_spread =
938 * dal_display_path_is_ss_supported(
939 * path_mode->display_path) ?
940 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
941 * LINK_SPREAD_DISABLED;
942 */
943 lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
944
945 /* 1. set link rate, lane count and spread*/
d0778ebf 946 dpcd_set_link_settings(link, &lt_settings);
4562236b
HW		 947
948 /* 2. perform link training (set link training done
949 * to false is done as well)*/
d0778ebf 950 if (!perform_clock_recovery_sequence(link, &lt_settings)) {
820e3935
DW		 951 status = LINK_TRAINING_CR_FAIL;
952 } else {
d0778ebf 953 status = perform_channel_equalization_sequence(link,
820e3935 954 &lt_settings);
4562236b
HW		 955 }
956
820e3935 957 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
d0778ebf 958 if (!perform_link_training_int(link,
820e3935
DW		 959 &lt_settings,
960 status == LINK_TRAINING_SUCCESS)) {
961 /* the next link training setting in this case
962 * would be the same as CR failure case.
963 */
964 status = LINK_TRAINING_CR_FAIL;
965 }
966 }
4562236b
HW		 967
968 /* 6. print status message*/
969 switch (lt_settings.link_settings.link_rate) {
970
971 case LINK_RATE_LOW:
972 link_rate = "RBR";
973 break;
974 case LINK_RATE_HIGH:
975 link_rate = "HBR";
976 break;
977 case LINK_RATE_HIGH2:
978 link_rate = "HBR2";
979 break;
980 case LINK_RATE_RBR2:
981 link_rate = "RBR2";
982 break;
983 case LINK_RATE_HIGH3:
984 link_rate = "HBR3";
985 break;
986 default:
987 break;
988 }
989
990 /* Connectivity log: link training */
d0778ebf 991 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
4562236b
HW		 992 link_rate,
993 lt_settings.link_settings.lane_count,
820e3935
DW		 994 (status == LINK_TRAINING_SUCCESS) ? "pass" :
995 ((status == LINK_TRAINING_CR_FAIL) ? "CR failed" :
996 "EQ failed"),
4562236b
HW		 997 lt_settings.lane_settings[0].VOLTAGE_SWING,
998 lt_settings.lane_settings[0].PRE_EMPHASIS);
999
1000 return status;
1001}
1002
1003
1004bool perform_link_training_with_retries(
d0778ebf 1005 struct dc_link *link,
4562236b
HW		 1006 const struct dc_link_settings *link_setting,
1007 bool skip_video_pattern,
1008 int attempts)
1009{
1010 uint8_t j;
1011 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1012
1013 for (j = 0; j < attempts; ++j) {
1014
1015 if (dc_link_dp_perform_link_training(
d0778ebf 1016 link,
4562236b 1017 link_setting,
820e3935 1018 skip_video_pattern) == LINK_TRAINING_SUCCESS)
4562236b
HW		 1019 return true;
1020
1021 msleep(delay_between_attempts);
1022 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1023 }
1024
1025 return false;
1026}
1027
d0778ebf 1028static struct dc_link_settings get_max_link_cap(struct dc_link *link)
4562236b
HW		 1029{
1030 /* Set Default link settings */
1031 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1032 LINK_SPREAD_05_DOWNSPREAD_30KHZ};
1033
1034 /* Higher link settings based on feature supported */
1035 if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1036 max_link_cap.link_rate = LINK_RATE_HIGH2;
1037
1038 if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1039 max_link_cap.link_rate = LINK_RATE_HIGH3;
1040
1041 /* Lower link settings based on sink's link cap */
d0778ebf 1042 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
4562236b 1043 max_link_cap.lane_count =
d0778ebf
HW		 1044 link->reported_link_cap.lane_count;
1045 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
4562236b 1046 max_link_cap.link_rate =
d0778ebf
HW		 1047 link->reported_link_cap.link_rate;
1048 if (link->reported_link_cap.link_spread <
4562236b
HW		 1049 max_link_cap.link_spread)
1050 max_link_cap.link_spread =
d0778ebf 1051 link->reported_link_cap.link_spread;
4562236b
HW		 1052 return max_link_cap;
1053}
1054
1055bool dp_hbr_verify_link_cap(
d0778ebf 1056 struct dc_link *link,
4562236b
HW		 1057 struct dc_link_settings *known_limit_link_setting)
1058{
1059 struct dc_link_settings max_link_cap = {0};
820e3935
DW		 1060 struct dc_link_settings cur_link_setting = {0};
1061 struct dc_link_settings *cur = &cur_link_setting;
1062 struct dc_link_settings initial_link_settings = {0};
4562236b
HW		 1063 bool success;
1064 bool skip_link_training;
4562236b 1065 bool skip_video_pattern;
4562236b
HW		 1066 struct clock_source *dp_cs;
1067 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
820e3935 1068 enum link_training_result status;
4562236b
HW		 1069
1070 success = false;
1071 skip_link_training = false;
1072
1073 max_link_cap = get_max_link_cap(link);
1074
1075 /* TODO implement override and monitor patch later */
1076
1077 /* try to train the link from high to low to
1078 * find the physical link capability
1079 */
1080 /* disable PHY done possible by BIOS, will be done by driver itself */
d0778ebf 1081 dp_disable_link_phy(link, link->connector_signal);
4562236b
HW		 1082
1083 dp_cs = link->dc->res_pool->dp_clock_source;
1084
1085 if (dp_cs)
1086 dp_cs_id = dp_cs->id;
1087 else {
1088 /*
1089 * dp clock source is not initialized for some reason.
1090 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1091 */
1092 ASSERT(dp_cs);
1093 }
1094
820e3935
DW		 1095 /* link training starts with the maximum common settings
1096 * supported by both sink and ASIC.
1097 */
1098 initial_link_settings = get_common_supported_link_settings(
1099 *known_limit_link_setting,
1100 max_link_cap);
1101 cur_link_setting = initial_link_settings;
1102 do {
4562236b 1103 skip_video_pattern = true;
820e3935 1104
4562236b
HW		 1105 if (cur->link_rate == LINK_RATE_LOW)
1106 skip_video_pattern = false;
1107
1108 dp_enable_link_phy(
1109 link,
d0778ebf 1110 link->connector_signal,
4562236b
HW		 1111 dp_cs_id,
1112 cur);
1113
1114 if (skip_link_training)
1115 success = true;
1116 else {
820e3935 1117 status = dc_link_dp_perform_link_training(
d0778ebf 1118 link,
4562236b
HW		 1119 cur,
1120 skip_video_pattern);
820e3935
DW		 1121 if (status == LINK_TRAINING_SUCCESS)
1122 success = true;
4562236b
HW		 1123 }
1124
1125 if (success)
d0778ebf 1126 link->verified_link_cap = *cur;
4562236b
HW		 1127
1128 /* always disable the link before trying another
1129 * setting or before returning we'll enable it later
1130 * based on the actual mode we're driving
1131 */
d0778ebf 1132 dp_disable_link_phy(link, link->connector_signal);
820e3935
DW		 1133 } while (!success && decide_fallback_link_setting(
1134 initial_link_settings, cur, status));
4562236b
HW		 1135
1136 /* Link Training failed for all Link Settings
1137 * (Lane Count is still unknown)
1138 */
1139 if (!success) {
1140 /* If all LT fails for all settings,
1141 * set verified = failed safe (1 lane low)
1142 */
d0778ebf
HW		 1143 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1144 link->verified_link_cap.link_rate = LINK_RATE_LOW;
4562236b 1145
d0778ebf 1146 link->verified_link_cap.link_spread =
4562236b
HW		 1147 LINK_SPREAD_DISABLED;
1148 }
1149
d0778ebf 1150 link->max_link_setting = link->verified_link_cap;
4562236b
HW		 1151
1152 return success;
1153}
1154
820e3935
DW		 1155struct dc_link_settings get_common_supported_link_settings (
1156 struct dc_link_settings link_setting_a,
1157 struct dc_link_settings link_setting_b)
1158{
1159 struct dc_link_settings link_settings = {0};
1160
1161 link_settings.lane_count =
1162 (link_setting_a.lane_count <=
1163 link_setting_b.lane_count) ?
1164 link_setting_a.lane_count :
1165 link_setting_b.lane_count;
1166 link_settings.link_rate =
1167 (link_setting_a.link_rate <=
1168 link_setting_b.link_rate) ?
1169 link_setting_a.link_rate :
1170 link_setting_b.link_rate;
1171 link_settings.link_spread = LINK_SPREAD_DISABLED;
1172
1173 /* in DP compliance test, DPR-120 may have
1174 * a random value in its MAX_LINK_BW dpcd field.
1175 * We map it to the maximum supported link rate that
1176 * is smaller than MAX_LINK_BW in this case.
1177 */
1178 if (link_settings.link_rate > LINK_RATE_HIGH3) {
1179 link_settings.link_rate = LINK_RATE_HIGH3;
1180 } else if (link_settings.link_rate < LINK_RATE_HIGH3
1181 && link_settings.link_rate > LINK_RATE_HIGH2) {
1182 link_settings.link_rate = LINK_RATE_HIGH2;
1183 } else if (link_settings.link_rate < LINK_RATE_HIGH2
1184 && link_settings.link_rate > LINK_RATE_HIGH) {
1185 link_settings.link_rate = LINK_RATE_HIGH;
1186 } else if (link_settings.link_rate < LINK_RATE_HIGH
1187 && link_settings.link_rate > LINK_RATE_LOW) {
1188 link_settings.link_rate = LINK_RATE_LOW;
1189 } else if (link_settings.link_rate < LINK_RATE_LOW) {
1190 link_settings.link_rate = LINK_RATE_UNKNOWN;
1191 }
1192
1193 return link_settings;
1194}
1195
1196bool reached_minimum_lane_count(enum dc_lane_count lane_count)
1197{
1198 return lane_count <= LANE_COUNT_ONE;
1199}
1200
1201bool reached_minimum_link_rate(enum dc_link_rate link_rate)
1202{
1203 return link_rate <= LINK_RATE_LOW;
1204}
1205
1206enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
1207{
1208 switch (lane_count) {
1209 case LANE_COUNT_FOUR:
1210 return LANE_COUNT_TWO;
1211 case LANE_COUNT_TWO:
1212 return LANE_COUNT_ONE;
1213 case LANE_COUNT_ONE:
1214 return LANE_COUNT_UNKNOWN;
1215 default:
1216 return LANE_COUNT_UNKNOWN;
1217 }
1218}
1219
1220enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
1221{
1222 switch (link_rate) {
1223 case LINK_RATE_HIGH3:
1224 return LINK_RATE_HIGH2;
1225 case LINK_RATE_HIGH2:
1226 return LINK_RATE_HIGH;
1227 case LINK_RATE_HIGH:
1228 return LINK_RATE_LOW;
1229 case LINK_RATE_LOW:
1230 return LINK_RATE_UNKNOWN;
1231 default:
1232 return LINK_RATE_UNKNOWN;
1233 }
1234}
1235
8c4abe0b
DW		 1236enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
1237{
1238 switch (lane_count) {
1239 case LANE_COUNT_ONE:
1240 return LANE_COUNT_TWO;
1241 case LANE_COUNT_TWO:
1242 return LANE_COUNT_FOUR;
1243 default:
1244 return LANE_COUNT_UNKNOWN;
1245 }
1246}
1247
1248enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
1249{
1250 switch (link_rate) {
1251 case LINK_RATE_LOW:
1252 return LINK_RATE_HIGH;
1253 case LINK_RATE_HIGH:
1254 return LINK_RATE_HIGH2;
1255 case LINK_RATE_HIGH2:
1256 return LINK_RATE_HIGH3;
1257 default:
1258 return LINK_RATE_UNKNOWN;
1259 }
1260}
1261
820e3935
DW		 1262/*
1263 * function: set link rate and lane count fallback based
1264 * on current link setting and last link training result
1265 * return value:
1266 * true - link setting could be set
1267 * false - has reached minimum setting
1268 * and no further fallback could be done
1269 */
1270bool decide_fallback_link_setting(
1271 struct dc_link_settings initial_link_settings,
1272 struct dc_link_settings *current_link_setting,
1273 enum link_training_result training_result)
1274{
1275 if (!current_link_setting)
1276 return false;
1277
1278 switch (training_result) {
1279 case LINK_TRAINING_CR_FAIL:
1280 {
1281 if (!reached_minimum_link_rate
1282 (current_link_setting->link_rate)) {
1283 current_link_setting->link_rate =
1284 reduce_link_rate(
1285 current_link_setting->link_rate);
1286 } else if (!reached_minimum_lane_count
1287 (current_link_setting->lane_count)) {
1288 current_link_setting->link_rate =
1289 initial_link_settings.link_rate;
1290 current_link_setting->lane_count =
1291 reduce_lane_count(
1292 current_link_setting->lane_count);
1293 } else {
1294 return false;
1295 }
1296 break;
1297 }
1298 case LINK_TRAINING_EQ_FAIL_EQ:
1299 {
1300 if (!reached_minimum_lane_count
1301 (current_link_setting->lane_count)) {
1302 current_link_setting->lane_count =
1303 reduce_lane_count(
1304 current_link_setting->lane_count);
1305 } else if (!reached_minimum_link_rate
1306 (current_link_setting->link_rate)) {
1307 current_link_setting->lane_count =
1308 initial_link_settings.lane_count;
1309 current_link_setting->link_rate =
1310 reduce_link_rate(
1311 current_link_setting->link_rate);
1312 } else {
1313 return false;
1314 }
1315 break;
1316 }
1317 case LINK_TRAINING_EQ_FAIL_CR:
1318 {
1319 if (!reached_minimum_link_rate
1320 (current_link_setting->link_rate)) {
1321 current_link_setting->link_rate =
1322 reduce_link_rate(
1323 current_link_setting->link_rate);
1324 } else {
1325 return false;
1326 }
1327 break;
1328 }
1329 default:
1330 return false;
1331 }
1332 return true;
1333}
1334
4562236b
HW		 1335static uint32_t bandwidth_in_kbps_from_timing(
1336 const struct dc_crtc_timing *timing)
1337{
1338 uint32_t bits_per_channel = 0;
1339 uint32_t kbps;
1340 switch (timing->display_color_depth) {
1341
1342 case COLOR_DEPTH_666:
1343 bits_per_channel = 6;
1344 break;
1345 case COLOR_DEPTH_888:
1346 bits_per_channel = 8;
1347 break;
1348 case COLOR_DEPTH_101010:
1349 bits_per_channel = 10;
1350 break;
1351 case COLOR_DEPTH_121212:
1352 bits_per_channel = 12;
1353 break;
1354 case COLOR_DEPTH_141414:
1355 bits_per_channel = 14;
1356 break;
1357 case COLOR_DEPTH_161616:
1358 bits_per_channel = 16;
1359 break;
1360 default:
1361 break;
1362 }
1363 ASSERT(bits_per_channel != 0);
1364
1365 kbps = timing->pix_clk_khz;
1366 kbps *= bits_per_channel;
1367
1368 if (timing->flags.Y_ONLY != 1)
1369 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
1370 kbps *= 3;
1371
1372 return kbps;
1373
1374}
1375
1376static uint32_t bandwidth_in_kbps_from_link_settings(
1377 const struct dc_link_settings *link_setting)
1378{
1379 uint32_t link_rate_in_kbps = link_setting->link_rate *
1380 LINK_RATE_REF_FREQ_IN_KHZ;
1381
1382 uint32_t lane_count = link_setting->lane_count;
1383 uint32_t kbps = link_rate_in_kbps;
1384 kbps *= lane_count;
1385 kbps *= 8; /* 8 bits per byte*/
1386
1387 return kbps;
1388
1389}
1390
1391bool dp_validate_mode_timing(
d0778ebf 1392 struct dc_link *link,
4562236b
HW		 1393 const struct dc_crtc_timing *timing)
1394{
1395 uint32_t req_bw;
1396 uint32_t max_bw;
1397
1398 const struct dc_link_settings *link_setting;
1399
1400 /*always DP fail safe mode*/
1401 if (timing->pix_clk_khz == (uint32_t)25175 &&
1402 timing->h_addressable == (uint32_t)640 &&
1403 timing->v_addressable == (uint32_t)480)
1404 return true;
1405
1406 /* We always use verified link settings */
d0778ebf 1407 link_setting = &link->verified_link_cap;
4562236b
HW		 1408
1409 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1410 /*if (flags.DYNAMIC_VALIDATION == 1 &&
d0778ebf
HW		 1411 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
1412 link_setting = &link->verified_link_cap;
4562236b
HW		 1413 */
1414
1415 req_bw = bandwidth_in_kbps_from_timing(timing);
1416 max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
1417
1418 if (req_bw <= max_bw) {
1419 /* remember the biggest mode here, during
1420 * initial link training (to get
1421 * verified_link_cap), LS sends event about
1422 * cannot train at reported cap to upper
1423 * layer and upper layer will re-enumerate modes.
1424 * this is not necessary if the lower
1425 * verified_link_cap is enough to drive
1426 * all the modes */
1427
1428 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1429 /* if (flags.DYNAMIC_VALIDATION == 1)
1430 dpsst->max_req_bw_for_verified_linkcap = dal_max(
1431 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
1432 return true;
1433 } else
1434 return false;
1435}
1436
1437void decide_link_settings(struct core_stream *stream,
1438 struct dc_link_settings *link_setting)
1439{
1440
8c4abe0b
DW		 1441 struct dc_link_settings initial_link_setting = {
1442 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED};
1443 struct dc_link_settings current_link_setting =
1444 initial_link_setting;
d0778ebf 1445 struct dc_link *link;
4562236b
HW		 1446 uint32_t req_bw;
1447 uint32_t link_bw;
4562236b
HW		 1448
1449 req_bw = bandwidth_in_kbps_from_timing(
1450 &stream->public.timing);
1451
8c4abe0b
DW		 1452 link = stream->sink->link;
1453
4562236b
HW		 1454 /* if preferred is specified through AMDDP, use it, if it's enough
1455 * to drive the mode
1456 */
d0778ebf 1457 if (link->preferred_link_setting.lane_count !=
8c4abe0b 1458 LANE_COUNT_UNKNOWN &&
d0778ebf 1459 link->preferred_link_setting.link_rate !=
8c4abe0b 1460 LINK_RATE_UNKNOWN) {
d0778ebf 1461 *link_setting = link->preferred_link_setting;
8c4abe0b
DW		 1462 return;
1463 }
4562236b 1464
8c4abe0b
DW		 1465 /* search for the minimum link setting that:
1466 * 1. is supported according to the link training result
1467 * 2. could support the b/w requested by the timing
1468 */
1469 while (current_link_setting.link_rate <=
d0778ebf 1470 link->max_link_setting.link_rate) {
4562236b 1471 link_bw = bandwidth_in_kbps_from_link_settings(
8c4abe0b
DW		 1472 &current_link_setting);
1473 if (req_bw <= link_bw) {
1474 *link_setting = current_link_setting;
4562236b
HW		 1475 return;
1476 }
4562236b 1477
8c4abe0b 1478 if (current_link_setting.lane_count <
d0778ebf 1479 link->max_link_setting.lane_count) {
8c4abe0b
DW		 1480 current_link_setting.lane_count =
1481 increase_lane_count(
1482 current_link_setting.lane_count);
1483 } else {
1484 current_link_setting.link_rate =
1485 increase_link_rate(
1486 current_link_setting.link_rate);
1487 current_link_setting.lane_count =
1488 initial_link_setting.lane_count;
4562236b
HW		 1489 }
1490 }
1491
1492 BREAK_TO_DEBUGGER();
d0778ebf 1493 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
4562236b 1494
d0778ebf 1495 *link_setting = link->verified_link_cap;
4562236b
HW		 1496}
1497
1498/*************************Short Pulse IRQ***************************/
1499
1500static bool hpd_rx_irq_check_link_loss_status(
d0778ebf 1501 struct dc_link *link,
4562236b
HW		 1502 union hpd_irq_data *hpd_irq_dpcd_data)
1503{
1504 uint8_t irq_reg_rx_power_state;
1505 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1506 union lane_status lane_status;
1507 uint32_t lane;
1508 bool sink_status_changed;
1509 bool return_code;
1510
1511 sink_status_changed = false;
1512 return_code = false;
1513
d0778ebf 1514 if (link->cur_link_settings.lane_count == 0)
4562236b
HW		 1515 return return_code;
1516 /*1. Check that we can handle interrupt: Not in FS DOS,
1517 * Not in "Display Timeout" state, Link is trained.
1518 */
1519
1520 dpcd_result = core_link_read_dpcd(link,
3a340294 1521 DP_SET_POWER,
4562236b
HW		 1522 &irq_reg_rx_power_state,
1523 sizeof(irq_reg_rx_power_state));
1524
1525 if (dpcd_result != DC_OK) {
3a340294 1526 irq_reg_rx_power_state = DP_SET_POWER_D0;
4562236b
HW		 1527 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1528 "%s: DPCD read failed to obtain power state.\n",
1529 __func__);
1530 }
1531
3a340294 1532 if (irq_reg_rx_power_state == DP_SET_POWER_D0) {
4562236b
HW		 1533
1534 /*2. Check that Link Status changed, before re-training.*/
1535
1536 /*parse lane status*/
1537 for (lane = 0;
d0778ebf 1538 lane < link->cur_link_settings.lane_count;
4562236b
HW		 1539 lane++) {
1540
1541 /* check status of lanes 0,1
1542 * changed DpcdAddress_Lane01Status (0x202)*/
1543 lane_status.raw = get_nibble_at_index(
1544 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1545 lane);
1546
1547 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1548 !lane_status.bits.CR_DONE_0 ||
1549 !lane_status.bits.SYMBOL_LOCKED_0) {
1550 /* if one of the channel equalization, clock
1551 * recovery or symbol lock is dropped
1552 * consider it as (link has been
1553 * dropped) dp sink status has changed*/
1554 sink_status_changed = true;
1555 break;
1556 }
1557
1558 }
1559
1560 /* Check interlane align.*/
1561 if (sink_status_changed ||
1562 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.
1563 INTERLANE_ALIGN_DONE) {
1564
1565 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1566 "%s: Link Status changed.\n",
1567 __func__);
1568
1569 return_code = true;
1570 }
1571 }
1572
1573 return return_code;
1574}
1575
1576static enum dc_status read_hpd_rx_irq_data(
d0778ebf 1577 struct dc_link *link,
4562236b
HW		 1578 union hpd_irq_data *irq_data)
1579{
1580 /* The HW reads 16 bytes from 200h on HPD,
1581 * but if we get an AUX_DEFER, the HW cannot retry
1582 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1583 * fail, so we now explicitly read 6 bytes which is
1584 * the req from the above mentioned test cases.
1585 */
1586 return core_link_read_dpcd(
1587 link,
3a340294 1588 DP_SINK_COUNT,
4562236b
HW		 1589 irq_data->raw,
1590 sizeof(union hpd_irq_data));
1591}
1592
d0778ebf 1593static bool allow_hpd_rx_irq(const struct dc_link *link)
4562236b
HW		 1594{
1595 /*
1596 * Don't handle RX IRQ unless one of following is met:
1597 * 1) The link is established (cur_link_settings != unknown)
1598 * 2) We kicked off MST detection
1599 * 3) We know we're dealing with an active dongle
1600 */
1601
d0778ebf
HW		 1602 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1603 (link->type == dc_connection_mst_branch) ||
4562236b
HW		 1604 is_dp_active_dongle(link))
1605 return true;
1606
1607 return false;
1608}
1609
d0778ebf 1610static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
4562236b
HW		 1611{
1612 union dpcd_psr_configuration psr_configuration;
1613
94267b3d 1614 if (!link->psr_enabled)
4562236b
HW		 1615 return false;
1616
7c7f5b15
AG		 1617 dm_helpers_dp_read_dpcd(
1618 link->ctx,
d0778ebf 1619 link,
7c7f5b15
AG		 1620 368,/*DpcdAddress_PSR_Enable_Cfg*/
1621 &psr_configuration.raw,
1622 sizeof(psr_configuration.raw));
1623
4562236b
HW		 1624
1625 if (psr_configuration.bits.ENABLE) {
1626 unsigned char dpcdbuf[3] = {0};
1627 union psr_error_status psr_error_status;
1628 union psr_sink_psr_status psr_sink_psr_status;
1629
7c7f5b15
AG		 1630 dm_helpers_dp_read_dpcd(
1631 link->ctx,
d0778ebf 1632 link,
7c7f5b15
AG		 1633 0x2006, /*DpcdAddress_PSR_Error_Status*/
1634 (unsigned char *) dpcdbuf,
1635 sizeof(dpcdbuf));
4562236b
HW		 1636
1637 /*DPCD 2006h ERROR STATUS*/
1638 psr_error_status.raw = dpcdbuf[0];
1639 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
1640 psr_sink_psr_status.raw = dpcdbuf[2];
1641
1642 if (psr_error_status.bits.LINK_CRC_ERROR ||
1643 psr_error_status.bits.RFB_STORAGE_ERROR) {
1644 /* Acknowledge and clear error bits */
7c7f5b15
AG		 1645 dm_helpers_dp_write_dpcd(
1646 link->ctx,
d0778ebf 1647 link,
7c7f5b15 1648 8198,/*DpcdAddress_PSR_Error_Status*/
4562236b
HW		 1649 &psr_error_status.raw,
1650 sizeof(psr_error_status.raw));
1651
1652 /* PSR error, disable and re-enable PSR */
d0778ebf
HW		 1653 dc_link_set_psr_enable(link, false);
1654 dc_link_set_psr_enable(link, true);
4562236b
HW		 1655
1656 return true;
1657 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
1658 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
1659 /* No error is detect, PSR is active.
1660 * We should return with IRQ_HPD handled without
1661 * checking for loss of sync since PSR would have
1662 * powered down main link.
1663 */
1664 return true;
1665 }
1666 }
1667 return false;
1668}
1669
d0778ebf 1670static void dp_test_send_link_training(struct dc_link *link)
4562236b 1671{
73c72602 1672 struct dc_link_settings link_settings = {0};
4562236b
HW		 1673
1674 core_link_read_dpcd(
1675 link,
3a340294 1676 DP_TEST_LANE_COUNT,
4562236b
HW		 1677 (unsigned char *)(&link_settings.lane_count),
1678 1);
1679 core_link_read_dpcd(
1680 link,
3a340294 1681 DP_TEST_LINK_RATE,
4562236b
HW		 1682 (unsigned char *)(&link_settings.link_rate),
1683 1);
1684
1685 /* Set preferred link settings */
d0778ebf
HW		 1686 link->verified_link_cap.lane_count = link_settings.lane_count;
1687 link->verified_link_cap.link_rate = link_settings.link_rate;
4562236b 1688
73c72602 1689 dp_retrain_link_dp_test(link, &link_settings, false);
4562236b
HW		 1690}
1691
d0778ebf 1692static void dp_test_send_phy_test_pattern(struct dc_link *link)
4562236b
HW		 1693{
1694 union phy_test_pattern dpcd_test_pattern;
1695 union lane_adjust dpcd_lane_adjustment[2];
1696 unsigned char dpcd_post_cursor_2_adjustment = 0;
1697 unsigned char test_80_bit_pattern[
3a340294
DA		 1698 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1699 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
4562236b
HW		 1700 enum dp_test_pattern test_pattern;
1701 struct dc_link_training_settings link_settings;
1702 union lane_adjust dpcd_lane_adjust;
1703 unsigned int lane;
1704 struct link_training_settings link_training_settings;
1705 int i = 0;
1706
1707 dpcd_test_pattern.raw = 0;
1708 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
1709 memset(&link_settings, 0, sizeof(link_settings));
1710
1711 /* get phy test pattern and pattern parameters from DP receiver */
1712 core_link_read_dpcd(
1713 link,
3a340294 1714 DP_TEST_PHY_PATTERN,
4562236b
HW		 1715 &dpcd_test_pattern.raw,
1716 sizeof(dpcd_test_pattern));
1717 core_link_read_dpcd(
1718 link,
3a340294 1719 DP_ADJUST_REQUEST_LANE0_1,
4562236b
HW		 1720 &dpcd_lane_adjustment[0].raw,
1721 sizeof(dpcd_lane_adjustment));
1722
1723 /*get post cursor 2 parameters
1724 * For DP 1.1a or eariler, this DPCD register's value is 0
1725 * For DP 1.2 or later:
1726 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
1727 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
1728 */
1729 core_link_read_dpcd(
1730 link,
3a340294 1731 DP_ADJUST_REQUEST_POST_CURSOR2,
4562236b
HW		 1732 &dpcd_post_cursor_2_adjustment,
1733 sizeof(dpcd_post_cursor_2_adjustment));
1734
1735 /* translate request */
1736 switch (dpcd_test_pattern.bits.PATTERN) {
1737 case PHY_TEST_PATTERN_D10_2:
1738 test_pattern = DP_TEST_PATTERN_D102;
0e19401f 1739 break;
4562236b
HW		 1740 case PHY_TEST_PATTERN_SYMBOL_ERROR:
1741 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 1742 break;
4562236b
HW		 1743 case PHY_TEST_PATTERN_PRBS7:
1744 test_pattern = DP_TEST_PATTERN_PRBS7;
0e19401f 1745 break;
4562236b
HW		 1746 case PHY_TEST_PATTERN_80BIT_CUSTOM:
1747 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 1748 break;
1749 case PHY_TEST_PATTERN_CP2520_1:
1750 test_pattern = DP_TEST_PATTERN_CP2520_1;
1751 break;
1752 case PHY_TEST_PATTERN_CP2520_2:
1753 test_pattern = DP_TEST_PATTERN_CP2520_2;
1754 break;
1755 case PHY_TEST_PATTERN_CP2520_3:
1756 test_pattern = DP_TEST_PATTERN_CP2520_3;
1757 break;
4562236b
HW		 1758 default:
1759 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1760 break;
1761 }
1762
1763 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
1764 core_link_read_dpcd(
1765 link,
3a340294 1766 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
4562236b
HW		 1767 test_80_bit_pattern,
1768 sizeof(test_80_bit_pattern));
1769
1770 /* prepare link training settings */
d0778ebf 1771 link_settings.link = link->cur_link_settings;
4562236b
HW		 1772
1773 for (lane = 0; lane <
d0778ebf 1774 (unsigned int)(link->cur_link_settings.lane_count);
4562236b
HW		 1775 lane++) {
1776 dpcd_lane_adjust.raw =
1777 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
1778 link_settings.lane_settings[lane].VOLTAGE_SWING =
1779 (enum dc_voltage_swing)
1780 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
1781 link_settings.lane_settings[lane].PRE_EMPHASIS =
1782 (enum dc_pre_emphasis)
1783 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
1784 link_settings.lane_settings[lane].POST_CURSOR2 =
1785 (enum dc_post_cursor2)
1786 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
1787 }
1788
1789 for (i = 0; i < 4; i++)
1790 link_training_settings.lane_settings[i] =
1791 link_settings.lane_settings[i];
1792 link_training_settings.link_settings = link_settings.link;
1793 link_training_settings.allow_invalid_msa_timing_param = false;
1794 /*Usage: Measure DP physical lane signal
1795 * by DP SI test equipment automatically.
1796 * PHY test pattern request is generated by equipment via HPD interrupt.
1797 * HPD needs to be active all the time. HPD should be active
1798 * all the time. Do not touch it.
1799 * forward request to DS
1800 */
1801 dc_link_dp_set_test_pattern(
d0778ebf 1802 link,
4562236b
HW		 1803 test_pattern,
1804 &link_training_settings,
1805 test_80_bit_pattern,
3a340294
DA		 1806 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1807 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
4562236b
HW		 1808}
1809
d0778ebf 1810static void dp_test_send_link_test_pattern(struct dc_link *link)
4562236b
HW		 1811{
1812 union link_test_pattern dpcd_test_pattern;
1813 union test_misc dpcd_test_params;
1814 enum dp_test_pattern test_pattern;
1815
1816 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
1817 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
1818
1819 /* get link test pattern and pattern parameters */
1820 core_link_read_dpcd(
1821 link,
3a340294 1822 DP_TEST_PATTERN,
4562236b
HW		 1823 &dpcd_test_pattern.raw,
1824 sizeof(dpcd_test_pattern));
1825 core_link_read_dpcd(
1826 link,
3a340294 1827 DP_TEST_MISC0,
4562236b
HW		 1828 &dpcd_test_params.raw,
1829 sizeof(dpcd_test_params));
1830
1831 switch (dpcd_test_pattern.bits.PATTERN) {
1832 case LINK_TEST_PATTERN_COLOR_RAMP:
1833 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1834 break;
1835 case LINK_TEST_PATTERN_VERTICAL_BARS:
1836 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1837 break; /* black and white */
1838 case LINK_TEST_PATTERN_COLOR_SQUARES:
1839 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1840 TEST_DYN_RANGE_VESA ?
1841 DP_TEST_PATTERN_COLOR_SQUARES :
1842 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1843 break;
1844 default:
1845 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1846 break;
1847 }
1848
1849 dc_link_dp_set_test_pattern(
d0778ebf 1850 link,
4562236b
HW		 1851 test_pattern,
1852 NULL,
1853 NULL,
1854 0);
1855}
1856
d0778ebf 1857static void handle_automated_test(struct dc_link *link)
4562236b
HW		 1858{
1859 union test_request test_request;
1860 union test_response test_response;
1861
1862 memset(&test_request, 0, sizeof(test_request));
1863 memset(&test_response, 0, sizeof(test_response));
1864
1865 core_link_read_dpcd(
1866 link,
3a340294 1867 DP_TEST_REQUEST,
4562236b
HW		 1868 &test_request.raw,
1869 sizeof(union test_request));
1870 if (test_request.bits.LINK_TRAINING) {
1871 /* ACK first to let DP RX test box monitor LT sequence */
1872 test_response.bits.ACK = 1;
1873 core_link_write_dpcd(
1874 link,
3a340294 1875 DP_TEST_RESPONSE,
4562236b
HW		 1876 &test_response.raw,
1877 sizeof(test_response));
1878 dp_test_send_link_training(link);
1879 /* no acknowledge request is needed again */
1880 test_response.bits.ACK = 0;
1881 }
1882 if (test_request.bits.LINK_TEST_PATTRN) {
1883 dp_test_send_link_test_pattern(link);
75a74755 1884 test_response.bits.ACK = 1;
4562236b
HW		 1885 }
1886 if (test_request.bits.PHY_TEST_PATTERN) {
1887 dp_test_send_phy_test_pattern(link);
1888 test_response.bits.ACK = 1;
1889 }
1890 if (!test_request.raw)
1891 /* no requests, revert all test signals
1892 * TODO: revert all test signals
1893 */
1894 test_response.bits.ACK = 1;
1895 /* send request acknowledgment */
1896 if (test_response.bits.ACK)
1897 core_link_write_dpcd(
1898 link,
3a340294 1899 DP_TEST_RESPONSE,
4562236b
HW		 1900 &test_response.raw,
1901 sizeof(test_response));
1902}
1903
d0778ebf 1904bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data)
4562236b 1905{
4562236b 1906 union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}};
c2e218dd 1907 union device_service_irq device_service_clear = { { 0 } };
4562236b
HW		 1908 enum dc_status result = DDC_RESULT_UNKNOWN;
1909 bool status = false;
1910 /* For use cases related to down stream connection status change,
1911 * PSR and device auto test, refer to function handle_sst_hpd_irq
1912 * in DAL2.1*/
1913
1914 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1915 "%s: Got short pulse HPD on link %d\n",
d0778ebf 1916 __func__, link->link_index);
4562236b 1917
8ee65d7c 1918
4562236b
HW		 1919 /* All the "handle_hpd_irq_xxx()" methods
1920 * should be called only after
1921 * dal_dpsst_ls_read_hpd_irq_data
1922 * Order of calls is important too
1923 */
1924 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
8ee65d7c
WL		 1925 if (out_hpd_irq_dpcd_data)
1926 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4562236b
HW		 1927
1928 if (result != DC_OK) {
1929 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1930 "%s: DPCD read failed to obtain irq data\n",
1931 __func__);
1932 return false;
1933 }
1934
1935 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1936 device_service_clear.bits.AUTOMATED_TEST = 1;
1937 core_link_write_dpcd(
1938 link,
3a340294 1939 DP_DEVICE_SERVICE_IRQ_VECTOR,
4562236b
HW		 1940 &device_service_clear.raw,
1941 sizeof(device_service_clear.raw));
1942 device_service_clear.raw = 0;
1943 handle_automated_test(link);
1944 return false;
1945 }
1946
1947 if (!allow_hpd_rx_irq(link)) {
1948 dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
1949 "%s: skipping HPD handling on %d\n",
d0778ebf 1950 __func__, link->link_index);
4562236b
HW		 1951 return false;
1952 }
1953
1954 if (handle_hpd_irq_psr_sink(link))
1955 /* PSR-related error was detected and handled */
1956 return true;
1957
1958 /* If PSR-related error handled, Main link may be off,
1959 * so do not handle as a normal sink status change interrupt.
1960 */
1961
1962 /* check if we have MST msg and return since we poll for it */
1963 if (hpd_irq_dpcd_data.bytes.device_service_irq.
1964 bits.DOWN_REP_MSG_RDY ||
1965 hpd_irq_dpcd_data.bytes.device_service_irq.
1966 bits.UP_REQ_MSG_RDY)
1967 return false;
1968
1969 /* For now we only handle 'Downstream port status' case.
1970 * If we got sink count changed it means
1971 * Downstream port status changed,
1972 * then DM should call DC to do the detection. */
1973 if (hpd_rx_irq_check_link_loss_status(
1974 link,
1975 &hpd_irq_dpcd_data)) {
1976 /* Connectivity log: link loss */
1977 CONN_DATA_LINK_LOSS(link,
1978 hpd_irq_dpcd_data.raw,
1979 sizeof(hpd_irq_dpcd_data),
1980 "Status: ");
1981
1982 perform_link_training_with_retries(link,
d0778ebf 1983 &link->cur_link_settings,
4562236b
HW		 1984 true, LINK_TRAINING_ATTEMPTS);
1985
1986 status = false;
1987 }
1988
d0778ebf 1989 if (link->type == dc_connection_active_dongle &&
4562236b
HW		 1990 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
1991 != link->dpcd_sink_count)
1992 status = true;
1993
1994 /* reasons for HPD RX:
1995 * 1. Link Loss - ie Re-train the Link
1996 * 2. MST sideband message
1997 * 3. Automated Test - ie. Internal Commit
1998 * 4. CP (copy protection) - (not interesting for DM???)
1999 * 5. DRR
2000 * 6. Downstream Port status changed
2001 * -ie. Detect - this the only one
2002 * which is interesting for DM because
2003 * it must call dc_link_detect.
2004 */
2005 return status;
2006}
2007
2008/*query dpcd for version and mst cap addresses*/
d0778ebf 2009bool is_mst_supported(struct dc_link *link)
4562236b
HW		 2010{
2011 bool mst = false;
2012 enum dc_status st = DC_OK;
2013 union dpcd_rev rev;
2014 union mstm_cap cap;
2015
2016 rev.raw = 0;
2017 cap.raw = 0;
2018
3a340294 2019 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4562236b
HW		 2020 sizeof(rev));
2021
2022 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2023
3a340294 2024 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4562236b
HW		 2025 &cap.raw, sizeof(cap));
2026 if (st == DC_OK && cap.bits.MST_CAP == 1)
2027 mst = true;
2028 }
2029 return mst;
2030
2031}
2032
d0778ebf 2033bool is_dp_active_dongle(const struct dc_link *link)
4562236b
HW		 2034{
2035 enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
2036
2037 return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
2038 (dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
2039 (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
2040}
2041
2042static void get_active_converter_info(
d0778ebf 2043 uint8_t data, struct dc_link *link)
4562236b
HW		 2044{
2045 union dp_downstream_port_present ds_port = { .byte = data };
2046
2047 /* decode converter info*/
2048 if (!ds_port.fields.PORT_PRESENT) {
2049 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
d0778ebf 2050 ddc_service_set_dongle_type(link->ddc,
4562236b
HW		 2051 link->dpcd_caps.dongle_type);
2052 return;
2053 }
2054
2055 switch (ds_port.fields.PORT_TYPE) {
2056 case DOWNSTREAM_VGA:
2057 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
2058 break;
2059 case DOWNSTREAM_DVI_HDMI:
2060 /* At this point we don't know is it DVI or HDMI,
2061 * assume DVI.*/
2062 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
2063 break;
2064 default:
2065 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2066 break;
2067 }
2068
ac0e562c 2069 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
4562236b
HW		 2070 uint8_t det_caps[4];
2071 union dwnstream_port_caps_byte0 *port_caps =
2072 (union dwnstream_port_caps_byte0 *)det_caps;
3a340294 2073 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
4562236b
HW		 2074 det_caps, sizeof(det_caps));
2075
2076 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
2077 case DOWN_STREAM_DETAILED_VGA:
2078 link->dpcd_caps.dongle_type =
2079 DISPLAY_DONGLE_DP_VGA_CONVERTER;
2080 break;
2081 case DOWN_STREAM_DETAILED_DVI:
2082 link->dpcd_caps.dongle_type =
2083 DISPLAY_DONGLE_DP_DVI_CONVERTER;
2084 break;
2085 case DOWN_STREAM_DETAILED_HDMI:
2086 link->dpcd_caps.dongle_type =
2087 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
2088
03f5c686 2089 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
4562236b
HW		 2090 if (ds_port.fields.DETAILED_CAPS) {
2091
2092 union dwnstream_port_caps_byte3_hdmi
2093 hdmi_caps = {.raw = det_caps[3] };
03f5c686
CL		 2094 union dwnstream_port_caps_byte1
2095 hdmi_color_caps = {.raw = det_caps[2] };
2096 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
2097 det_caps[1] * 25000;
4562236b 2098
03f5c686 2099 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
4562236b 2100 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
03f5c686
CL		 2101 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
2102 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
2103 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
2104 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
2105 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
2106 hdmi_caps.bits.YCrCr422_CONVERSION;
2107 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
2108 hdmi_caps.bits.YCrCr420_CONVERSION;
2109
2110 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
2111 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT;
2112
2113 link->dpcd_caps.dongle_caps.extendedCapValid = true;
4562236b 2114 }
03f5c686 2115
4562236b
HW		 2116 break;
2117 }
2118 }
2119
d0778ebf 2120 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4562236b
HW		 2121
2122 {
2123 struct dp_device_vendor_id dp_id;
2124
2125 /* read IEEE branch device id */
2126 core_link_read_dpcd(
2127 link,
3a340294 2128 DP_BRANCH_OUI,
4562236b
HW		 2129 (uint8_t *)&dp_id,
2130 sizeof(dp_id));
2131
2132 link->dpcd_caps.branch_dev_id =
2133 (dp_id.ieee_oui[0] << 16) +
2134 (dp_id.ieee_oui[1] << 8) +
2135 dp_id.ieee_oui[2];
2136
2137 memmove(
2138 link->dpcd_caps.branch_dev_name,
2139 dp_id.ieee_device_id,
2140 sizeof(dp_id.ieee_device_id));
2141 }
2142
2143 {
2144 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2145
2146 core_link_read_dpcd(
2147 link,
3a340294 2148 DP_BRANCH_REVISION_START,
4562236b
HW		 2149 (uint8_t *)&dp_hw_fw_revision,
2150 sizeof(dp_hw_fw_revision));
2151
2152 link->dpcd_caps.branch_hw_revision =
2153 dp_hw_fw_revision.ieee_hw_rev;
2154 }
2155}
2156
d0778ebf 2157static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4562236b
HW		 2158 int length)
2159{
2160 int retry = 0;
2161 union dp_downstream_port_present ds_port = { 0 };
2162
2163 if (!link->dpcd_caps.dpcd_rev.raw) {
2164 do {
2165 dp_receiver_power_ctrl(link, true);
3a340294 2166 core_link_read_dpcd(link, DP_DPCD_REV,
4562236b
HW		 2167 dpcd_data, length);
2168 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3a340294
DA		 2169 DP_DPCD_REV -
2170 DP_DPCD_REV];
4562236b
HW		 2171 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
2172 }
2173
3a340294
DA		 2174 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2175 DP_DPCD_REV];
4562236b
HW		 2176
2177 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
2178 switch (link->dpcd_caps.branch_dev_id) {
2179 /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
2180 * all internal circuits including AUX communication preventing
2181 * reading DPCD table and EDID (spec violation).
2182 * Encoder will skip DP RX power down on disable_output to
2183 * keep receiver powered all the time.*/
2184 case DP_BRANCH_DEVICE_ID_1:
2185 case DP_BRANCH_DEVICE_ID_4:
2186 link->wa_flags.dp_keep_receiver_powered = true;
2187 break;
2188
2189 /* TODO: May need work around for other dongles. */
2190 default:
2191 link->wa_flags.dp_keep_receiver_powered = false;
2192 break;
2193 }
2194 } else
2195 link->wa_flags.dp_keep_receiver_powered = false;
2196}
2197
d0778ebf 2198static void retrieve_link_cap(struct dc_link *link)
4562236b 2199{
3a340294 2200 uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1];
4562236b
HW		 2201
2202 union down_stream_port_count down_strm_port_count;
2203 union edp_configuration_cap edp_config_cap;
2204 union dp_downstream_port_present ds_port = { 0 };
2205
2206 memset(dpcd_data, '\0', sizeof(dpcd_data));
2207 memset(&down_strm_port_count,
2208 '\0', sizeof(union down_stream_port_count));
2209 memset(&edp_config_cap, '\0',
2210 sizeof(union edp_configuration_cap));
2211
2212 core_link_read_dpcd(
2213 link,
3a340294 2214 DP_DPCD_REV,
4562236b
HW		 2215 dpcd_data,
2216 sizeof(dpcd_data));
2217
4562236b
HW		 2218 {
2219 union training_aux_rd_interval aux_rd_interval;
2220
2221 aux_rd_interval.raw =
3a340294 2222 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
4562236b
HW		 2223
2224 if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
2225 core_link_read_dpcd(
2226 link,
3a340294 2227 DP_DP13_DPCD_REV,
4562236b
HW		 2228 dpcd_data,
2229 sizeof(dpcd_data));
2230 }
2231 }
2232
cc04bf7e
TC		 2233 link->dpcd_caps.dpcd_rev.raw =
2234 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
2235
3a340294
DA		 2236 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2237 DP_DPCD_REV];
4562236b
HW		 2238
2239 get_active_converter_info(ds_port.byte, link);
2240
2241 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2242
2243 link->dpcd_caps.allow_invalid_MSA_timing_param =
2244 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2245
2246 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3a340294 2247 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4562236b
HW		 2248
2249 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3a340294 2250 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4562236b 2251
d0778ebf 2252 link->reported_link_cap.lane_count =
4562236b 2253 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
d0778ebf 2254 link->reported_link_cap.link_rate = dpcd_data[
3a340294 2255 DP_MAX_LINK_RATE - DP_DPCD_REV];
d0778ebf 2256 link->reported_link_cap.link_spread =
4562236b
HW		 2257 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
2258 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
2259
2260 edp_config_cap.raw = dpcd_data[
3a340294 2261 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4562236b
HW		 2262 link->dpcd_caps.panel_mode_edp =
2263 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
2264
d0778ebf
HW		 2265 link->test_pattern_enabled = false;
2266 link->compliance_test_state.raw = 0;
4562236b 2267
4562236b
HW		 2268 /* read sink count */
2269 core_link_read_dpcd(link,
3a340294 2270 DP_SINK_COUNT,
4562236b
HW		 2271 &link->dpcd_caps.sink_count.raw,
2272 sizeof(link->dpcd_caps.sink_count.raw));
2273
4562236b
HW		 2274 /* Connectivity log: detection */
2275 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
4562236b
HW		 2276}
2277
d0778ebf 2278void detect_dp_sink_caps(struct dc_link *link)
4562236b
HW		 2279{
2280 retrieve_link_cap(link);
2281
2282 /* dc init_hw has power encoder using default
2283 * signal for connector. For native DP, no
2284 * need to power up encoder again. If not native
2285 * DP, hw_init may need check signal or power up
2286 * encoder here.
2287 */
2288
2289 if (is_mst_supported(link)) {
d0778ebf 2290 link->verified_link_cap = link->reported_link_cap;
4562236b
HW		 2291 } else {
2292 dp_hbr_verify_link_cap(link,
d0778ebf 2293 &link->reported_link_cap);
4562236b
HW		 2294 }
2295 /* TODO save sink caps in link->sink */
2296}
2297
2298void dc_link_dp_enable_hpd(const struct dc_link *link)
2299{
d0778ebf 2300 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2301
2302 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2303 encoder->funcs->enable_hpd(encoder);
2304}
2305
2306void dc_link_dp_disable_hpd(const struct dc_link *link)
2307{
d0778ebf 2308 struct link_encoder *encoder = link->link_enc;
4562236b
HW		 2309
2310 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2311 encoder->funcs->disable_hpd(encoder);
2312}
2313
2314static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
2315{
0e19401f
TC		 2316 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
2317 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
2318 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4562236b
HW		 2319 return true;
2320 else
2321 return false;
2322}
2323
d0778ebf 2324static void set_crtc_test_pattern(struct dc_link *link,
4562236b
HW		 2325 struct pipe_ctx *pipe_ctx,
2326 enum dp_test_pattern test_pattern)
2327{
2328 enum controller_dp_test_pattern controller_test_pattern;
2329 enum dc_color_depth color_depth = pipe_ctx->
2330 stream->public.timing.display_color_depth;
2331 struct bit_depth_reduction_params params;
2332
2333 memset(&params, 0, sizeof(params));
2334
2335 switch (test_pattern) {
2336 case DP_TEST_PATTERN_COLOR_SQUARES:
2337 controller_test_pattern =
2338 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2339 break;
2340 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2341 controller_test_pattern =
2342 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
2343 break;
2344 case DP_TEST_PATTERN_VERTICAL_BARS:
2345 controller_test_pattern =
2346 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
2347 break;
2348 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2349 controller_test_pattern =
2350 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
2351 break;
2352 case DP_TEST_PATTERN_COLOR_RAMP:
2353 controller_test_pattern =
2354 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
2355 break;
2356 default:
2357 controller_test_pattern =
2358 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
2359 break;
2360 }
2361
2362 switch (test_pattern) {
2363 case DP_TEST_PATTERN_COLOR_SQUARES:
2364 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2365 case DP_TEST_PATTERN_VERTICAL_BARS:
2366 case DP_TEST_PATTERN_HORIZONTAL_BARS:
2367 case DP_TEST_PATTERN_COLOR_RAMP:
2368 {
2369 /* disable bit depth reduction */
2370 pipe_ctx->stream->bit_depth_params = params;
2371 pipe_ctx->opp->funcs->
2372 opp_program_bit_depth_reduction(pipe_ctx->opp, &params);
2373
2374 pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
2375 controller_test_pattern, color_depth);
2376 }
2377 break;
2378 case DP_TEST_PATTERN_VIDEO_MODE:
2379 {
2380 /* restore bitdepth reduction */
529cad0f 2381 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
4562236b
HW		 2382 &params);
2383 pipe_ctx->stream->bit_depth_params = params;
2384 pipe_ctx->opp->funcs->
2385 opp_program_bit_depth_reduction(pipe_ctx->opp, &params);
2386
2387 pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
2388 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2389 color_depth);
2390 }
2391 break;
2392
2393 default:
2394 break;
2395 }
2396}
2397
2398bool dc_link_dp_set_test_pattern(
d0778ebf 2399 struct dc_link *link,
4562236b
HW		 2400 enum dp_test_pattern test_pattern,
2401 const struct link_training_settings *p_link_settings,
2402 const unsigned char *p_custom_pattern,
2403 unsigned int cust_pattern_size)
2404{
d0778ebf 2405 struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx;
4562236b
HW		 2406 struct pipe_ctx pipe_ctx = pipes[0];
2407 unsigned int lane;
2408 unsigned int i;
2409 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
2410 union dpcd_training_pattern training_pattern;
4562236b
HW		 2411 enum dpcd_phy_test_patterns pattern;
2412
2413 memset(&training_pattern, 0, sizeof(training_pattern));
4562236b
HW		 2414
2415 for (i = 0; i < MAX_PIPES; i++) {
d0778ebf 2416 if (pipes[i].stream->sink->link == link) {
4562236b
HW		 2417 pipe_ctx = pipes[i];
2418 break;
2419 }
2420 }
2421
2422 /* Reset CRTC Test Pattern if it is currently running and request
2423 * is VideoMode Reset DP Phy Test Pattern if it is currently running
2424 * and request is VideoMode
2425 */
d0778ebf 2426 if (link->test_pattern_enabled && test_pattern ==
4562236b
HW		 2427 DP_TEST_PATTERN_VIDEO_MODE) {
2428 /* Set CRTC Test Pattern */
d0778ebf
HW		 2429 set_crtc_test_pattern(link, &pipe_ctx, test_pattern);
2430 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 2431 (uint8_t *)p_custom_pattern,
2432 (uint32_t)cust_pattern_size);
2433
2434 /* Unblank Stream */
d0778ebf 2435 link->dc->hwss.unblank_stream(
4562236b 2436 &pipe_ctx,
d0778ebf 2437 &link->verified_link_cap);
4562236b
HW		 2438 /* TODO:m_pHwss->MuteAudioEndpoint
2439 * (pPathMode->pDisplayPath, false);
2440 */
2441
2442 /* Reset Test Pattern state */
d0778ebf 2443 link->test_pattern_enabled = false;
4562236b
HW		 2444
2445 return true;
2446 }
2447
2448 /* Check for PHY Test Patterns */
2449 if (is_dp_phy_pattern(test_pattern)) {
2450 /* Set DPCD Lane Settings before running test pattern */
2451 if (p_link_settings != NULL) {
d0778ebf
HW		 2452 dp_set_hw_lane_settings(link, p_link_settings);
2453 dpcd_set_lane_settings(link, p_link_settings);
4562236b
HW		 2454 }
2455
2456 /* Blank stream if running test pattern */
2457 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2458 /*TODO:
2459 * m_pHwss->
2460 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
2461 */
2462 /* Blank stream */
2463 pipes->stream_enc->funcs->dp_blank(pipe_ctx.stream_enc);
2464 }
2465
d0778ebf 2466 dp_set_hw_test_pattern(link, test_pattern,
4562236b
HW		 2467 (uint8_t *)p_custom_pattern,
2468 (uint32_t)cust_pattern_size);
2469
2470 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2471 /* Set Test Pattern state */
d0778ebf 2472 link->test_pattern_enabled = true;
4562236b 2473 if (p_link_settings != NULL)
d0778ebf 2474 dpcd_set_link_settings(link,
4562236b
HW		 2475 p_link_settings);
2476 }
2477
2478 switch (test_pattern) {
2479 case DP_TEST_PATTERN_VIDEO_MODE:
2480 pattern = PHY_TEST_PATTERN_NONE;
0e19401f 2481 break;
4562236b
HW		 2482 case DP_TEST_PATTERN_D102:
2483 pattern = PHY_TEST_PATTERN_D10_2;
0e19401f 2484 break;
4562236b
HW		 2485 case DP_TEST_PATTERN_SYMBOL_ERROR:
2486 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
0e19401f 2487 break;
4562236b
HW		 2488 case DP_TEST_PATTERN_PRBS7:
2489 pattern = PHY_TEST_PATTERN_PRBS7;
0e19401f 2490 break;
4562236b
HW		 2491 case DP_TEST_PATTERN_80BIT_CUSTOM:
2492 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
0e19401f
TC		 2493 break;
2494 case DP_TEST_PATTERN_CP2520_1:
2495 pattern = PHY_TEST_PATTERN_CP2520_1;
2496 break;
2497 case DP_TEST_PATTERN_CP2520_2:
2498 pattern = PHY_TEST_PATTERN_CP2520_2;
2499 break;
2500 case DP_TEST_PATTERN_CP2520_3:
2501 pattern = PHY_TEST_PATTERN_CP2520_3;
2502 break;
4562236b
HW		 2503 default:
2504 return false;
2505 }
2506
2507 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
2508 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
2509 return false;
2510
d0778ebf 2511 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4562236b
HW		 2512 /* tell receiver that we are sending qualification
2513 * pattern DP 1.2 or later - DP receiver's link quality
2514 * pattern is set using DPCD LINK_QUAL_LANEx_SET
2515 * register (0x10B~0x10E)\
2516 */
2517 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
2518 link_qual_pattern[lane] =
2519 (unsigned char)(pattern);
2520
d0778ebf 2521 core_link_write_dpcd(link,
3a340294 2522 DP_LINK_QUAL_LANE0_SET,
4562236b
HW		 2523 link_qual_pattern,
2524 sizeof(link_qual_pattern));
d0778ebf
HW		 2525 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
2526 link->dpcd_caps.dpcd_rev.raw == 0) {
4562236b
HW		 2527 /* tell receiver that we are sending qualification
2528 * pattern DP 1.1a or earlier - DP receiver's link
2529 * quality pattern is set using
2530 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
2531 * register (0x102). We will use v_1.3 when we are
2532 * setting test pattern for DP 1.1.
2533 */
d0778ebf
HW		 2534 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
2535 &training_pattern.raw,
2536 sizeof(training_pattern));
4562236b 2537 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
d0778ebf
HW		 2538 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
2539 &training_pattern.raw,
2540 sizeof(training_pattern));
4562236b
HW		 2541 }
2542 } else {
2543 /* CRTC Patterns */
d0778ebf 2544 set_crtc_test_pattern(link, &pipe_ctx, test_pattern);
4562236b 2545 /* Set Test Pattern state */
d0778ebf 2546 link->test_pattern_enabled = true;
4562236b
HW		 2547 }
2548
2549 return true;
2550}
07c84c7a 2551
d0778ebf 2552void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
07c84c7a
DW		 2553{
2554 unsigned char mstmCntl;
2555
2556 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2557 if (enable)
2558 mstmCntl |= DP_MST_EN;
2559 else
2560 mstmCntl &= (~DP_MST_EN);
2561
2562 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2563}
Linux 6.x block layer and io_uring tree(s)