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Merge remote-tracking branches 'asoc/topic/wm8753', 'asoc/topic/wm8770', 'asoc/topic...
[linux-block.git] / drivers / gpu / drm / amd / display / dc / core / dc_link.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
cc57306f 27#include "atom.h"
4562236b
HW		 28#include "dm_helpers.h"
29#include "dc.h"
4562236b
HW		 30#include "grph_object_id.h"
31#include "gpio_service_interface.h"
32#include "core_status.h"
33#include "dc_link_dp.h"
34#include "dc_link_ddc.h"
35#include "link_hwss.h"
fb3466a4 36
4562236b
HW		 37#include "link_encoder.h"
38#include "hw_sequencer.h"
39#include "resource.h"
6728b30c 40#include "abm.h"
4562236b 41#include "fixed31_32.h"
eaca91ee 42#include "dpcd_defs.h"
3548f073 43#include "dmcu.h"
4562236b
HW		 44
45#include "dce/dce_11_0_d.h"
46#include "dce/dce_11_0_enum.h"
47#include "dce/dce_11_0_sh_mask.h"
48
4562236b
HW		 49#define LINK_INFO(...) \
50 dm_logger_write(dc_ctx->logger, LOG_HW_HOTPLUG, \
51 __VA_ARGS__)
52
53/*******************************************************************************
54 * Private structures
55 ******************************************************************************/
56
57enum {
58 LINK_RATE_REF_FREQ_IN_MHZ = 27,
59 PEAK_FACTOR_X1000 = 1006
60};
61
62/*******************************************************************************
63 * Private functions
64 ******************************************************************************/
d0778ebf 65static void destruct(struct dc_link *link)
4562236b
HW		 66{
67 int i;
68
d0778ebf
HW		 69 if (link->ddc)
70 dal_ddc_service_destroy(&link->ddc);
4562236b
HW		 71
72 if(link->link_enc)
73 link->link_enc->funcs->destroy(&link->link_enc);
74
d0778ebf
HW		 75 if (link->local_sink)
76 dc_sink_release(link->local_sink);
4562236b 77
d0778ebf
HW		 78 for (i = 0; i < link->sink_count; ++i)
79 dc_sink_release(link->remote_sinks[i]);
4562236b
HW		 80}
81
87401969
AJ		 82struct gpio *get_hpd_gpio(struct dc_bios *dcb,
83 struct graphics_object_id link_id,
84 struct gpio_service *gpio_service)
4562236b
HW		 85{
86 enum bp_result bp_result;
4562236b
HW		 87 struct graphics_object_hpd_info hpd_info;
88 struct gpio_pin_info pin_info;
89
87401969 90 if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
4562236b
HW		 91 return NULL;
92
93 bp_result = dcb->funcs->get_gpio_pin_info(dcb,
94 hpd_info.hpd_int_gpio_uid, &pin_info);
95
96 if (bp_result != BP_RESULT_OK) {
97 ASSERT(bp_result == BP_RESULT_NORECORD);
98 return NULL;
99 }
100
101 return dal_gpio_service_create_irq(
87401969 102 gpio_service,
4562236b
HW		 103 pin_info.offset,
104 pin_info.mask);
105}
106
107/*
108 * Function: program_hpd_filter
109 *
110 * @brief
111 * Programs HPD filter on associated HPD line
112 *
113 * @param [in] delay_on_connect_in_ms: Connect filter timeout
114 * @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
115 *
116 * @return
117 * true on success, false otherwise
118 */
119static bool program_hpd_filter(
d0778ebf 120 const struct dc_link *link)
4562236b
HW		 121{
122 bool result = false;
123
124 struct gpio *hpd;
125
126 int delay_on_connect_in_ms = 0;
127 int delay_on_disconnect_in_ms = 0;
128
129 /* Verify feature is supported */
d0778ebf 130 switch (link->connector_signal) {
4562236b
HW		 131 case SIGNAL_TYPE_DVI_SINGLE_LINK:
132 case SIGNAL_TYPE_DVI_DUAL_LINK:
133 case SIGNAL_TYPE_HDMI_TYPE_A:
134 /* Program hpd filter */
135 delay_on_connect_in_ms = 500;
136 delay_on_disconnect_in_ms = 100;
137 break;
138 case SIGNAL_TYPE_DISPLAY_PORT:
139 case SIGNAL_TYPE_DISPLAY_PORT_MST:
140 /* Program hpd filter to allow DP signal to settle */
141 /* 500: not able to detect MST <-> SST switch as HPD is low for
142 * only 100ms on DELL U2413
143 * 0: some passive dongle still show aux mode instead of i2c
144 * 20-50:not enough to hide bouncing HPD with passive dongle.
145 * also see intermittent i2c read issues.
146 */
147 delay_on_connect_in_ms = 80;
148 delay_on_disconnect_in_ms = 0;
149 break;
150 case SIGNAL_TYPE_LVDS:
151 case SIGNAL_TYPE_EDP:
152 default:
153 /* Don't program hpd filter */
154 return false;
155 }
156
157 /* Obtain HPD handle */
87401969 158 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4562236b
HW		 159
160 if (!hpd)
161 return result;
162
163 /* Setup HPD filtering */
164 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
165 struct gpio_hpd_config config;
166
167 config.delay_on_connect = delay_on_connect_in_ms;
168 config.delay_on_disconnect = delay_on_disconnect_in_ms;
169
170 dal_irq_setup_hpd_filter(hpd, &config);
171
172 dal_gpio_close(hpd);
173
174 result = true;
175 } else {
176 ASSERT_CRITICAL(false);
177 }
178
179 /* Release HPD handle */
180 dal_gpio_destroy_irq(&hpd);
181
182 return result;
183}
184
d0778ebf 185static bool detect_sink(struct dc_link *link, enum dc_connection_type *type)
4562236b
HW		 186{
187 uint32_t is_hpd_high = 0;
188 struct gpio *hpd_pin;
189
190 /* todo: may need to lock gpio access */
87401969 191 hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4562236b
HW		 192 if (hpd_pin == NULL)
193 goto hpd_gpio_failure;
194
195 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
196 dal_gpio_get_value(hpd_pin, &is_hpd_high);
197 dal_gpio_close(hpd_pin);
198 dal_gpio_destroy_irq(&hpd_pin);
199
200 if (is_hpd_high) {
201 *type = dc_connection_single;
202 /* TODO: need to do the actual detection */
203 } else {
204 *type = dc_connection_none;
205 }
206
207 return true;
208
209hpd_gpio_failure:
210 return false;
211}
212
44858055 213static enum ddc_transaction_type get_ddc_transaction_type(
4562236b
HW		 214 enum signal_type sink_signal)
215{
216 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
217
218 switch (sink_signal) {
219 case SIGNAL_TYPE_DVI_SINGLE_LINK:
220 case SIGNAL_TYPE_DVI_DUAL_LINK:
221 case SIGNAL_TYPE_HDMI_TYPE_A:
222 case SIGNAL_TYPE_LVDS:
223 case SIGNAL_TYPE_RGB:
224 transaction_type = DDC_TRANSACTION_TYPE_I2C;
225 break;
226
227 case SIGNAL_TYPE_DISPLAY_PORT:
228 case SIGNAL_TYPE_EDP:
229 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
230 break;
231
232 case SIGNAL_TYPE_DISPLAY_PORT_MST:
233 /* MST does not use I2COverAux, but there is the
234 * SPECIAL use case for "immediate dwnstrm device
235 * access" (EPR#370830). */
236 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
237 break;
238
239 default:
240 break;
241 }
242
243 return transaction_type;
244}
245
246static enum signal_type get_basic_signal_type(
247 struct graphics_object_id encoder,
248 struct graphics_object_id downstream)
249{
250 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
251 switch (downstream.id) {
252 case CONNECTOR_ID_SINGLE_LINK_DVII:
253 switch (encoder.id) {
254 case ENCODER_ID_INTERNAL_DAC1:
255 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
256 case ENCODER_ID_INTERNAL_DAC2:
257 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
258 return SIGNAL_TYPE_RGB;
259 default:
260 return SIGNAL_TYPE_DVI_SINGLE_LINK;
261 }
262 break;
263 case CONNECTOR_ID_DUAL_LINK_DVII:
264 {
265 switch (encoder.id) {
266 case ENCODER_ID_INTERNAL_DAC1:
267 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
268 case ENCODER_ID_INTERNAL_DAC2:
269 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
270 return SIGNAL_TYPE_RGB;
271 default:
272 return SIGNAL_TYPE_DVI_DUAL_LINK;
273 }
274 }
275 break;
276 case CONNECTOR_ID_SINGLE_LINK_DVID:
277 return SIGNAL_TYPE_DVI_SINGLE_LINK;
278 case CONNECTOR_ID_DUAL_LINK_DVID:
279 return SIGNAL_TYPE_DVI_DUAL_LINK;
280 case CONNECTOR_ID_VGA:
281 return SIGNAL_TYPE_RGB;
282 case CONNECTOR_ID_HDMI_TYPE_A:
283 return SIGNAL_TYPE_HDMI_TYPE_A;
284 case CONNECTOR_ID_LVDS:
285 return SIGNAL_TYPE_LVDS;
286 case CONNECTOR_ID_DISPLAY_PORT:
287 return SIGNAL_TYPE_DISPLAY_PORT;
288 case CONNECTOR_ID_EDP:
289 return SIGNAL_TYPE_EDP;
290 default:
291 return SIGNAL_TYPE_NONE;
292 }
293 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
294 switch (downstream.id) {
295 case ENCODER_ID_EXTERNAL_NUTMEG:
296 case ENCODER_ID_EXTERNAL_TRAVIS:
297 return SIGNAL_TYPE_DISPLAY_PORT;
298 default:
299 return SIGNAL_TYPE_NONE;
300 }
301 }
302
303 return SIGNAL_TYPE_NONE;
304}
305
306/*
307 * @brief
308 * Check whether there is a dongle on DP connector
309 */
d0778ebf 310static bool is_dp_sink_present(struct dc_link *link)
4562236b
HW		 311{
312 enum gpio_result gpio_result;
313 uint32_t clock_pin = 0;
4562236b
HW		 314
315 struct ddc *ddc;
316
317 enum connector_id connector_id =
318 dal_graphics_object_id_get_connector_id(link->link_id);
319
320 bool present =
321 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
322 (connector_id == CONNECTOR_ID_EDP));
323
d0778ebf 324 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
4562236b
HW		 325
326 if (!ddc) {
327 BREAK_TO_DEBUGGER();
328 return present;
329 }
330
331 /* Open GPIO and set it to I2C mode */
332 /* Note: this GpioMode_Input will be converted
333 * to GpioConfigType_I2cAuxDualMode in GPIO component,
334 * which indicates we need additional delay */
335
336 if (GPIO_RESULT_OK != dal_ddc_open(
337 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
338 dal_gpio_destroy_ddc(&ddc);
339
340 return present;
341 }
342
343 /* Read GPIO: DP sink is present if both clock and data pins are zero */
344 /* [anaumov] in DAL2, there was no check for GPIO failure */
345
346 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
347 ASSERT(gpio_result == GPIO_RESULT_OK);
348
4dfb0bad 349 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
4562236b
HW		 350
351 dal_ddc_close(ddc);
352
353 return present;
354}
355
356/*
357 * @brief
358 * Detect output sink type
359 */
8f38b66c
HW		 360static enum signal_type link_detect_sink(
361 struct dc_link *link,
362 enum dc_detect_reason reason)
4562236b
HW		 363{
364 enum signal_type result = get_basic_signal_type(
365 link->link_enc->id, link->link_id);
366
367 /* Internal digital encoder will detect only dongles
368 * that require digital signal */
369
370 /* Detection mechanism is different
371 * for different native connectors.
372 * LVDS connector supports only LVDS signal;
373 * PCIE is a bus slot, the actual connector needs to be detected first;
374 * eDP connector supports only eDP signal;
375 * HDMI should check straps for audio */
376
377 /* PCIE detects the actual connector on add-on board */
378
379 if (link->link_id.id == CONNECTOR_ID_PCIE) {
380 /* ZAZTODO implement PCIE add-on card detection */
381 }
382
383 switch (link->link_id.id) {
384 case CONNECTOR_ID_HDMI_TYPE_A: {
385 /* check audio support:
386 * if native HDMI is not supported, switch to DVI */
387 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
388
389 if (!aud_support->hdmi_audio_native)
390 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
391 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
392 }
393 break;
394 case CONNECTOR_ID_DISPLAY_PORT: {
8f38b66c
HW		 395 /* DP HPD short pulse. Passive DP dongle will not
396 * have short pulse
397 */
398 if (reason != DETECT_REASON_HPDRX) {
399 /* Check whether DP signal detected: if not -
400 * we assume signal is DVI; it could be corrected
401 * to HDMI after dongle detection
402 */
403 if (!is_dp_sink_present(link))
404 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
405 }
4562236b
HW		 406 }
407 break;
408 default:
409 break;
410 }
411
412 return result;
413}
414
415static enum signal_type decide_signal_from_strap_and_dongle_type(
416 enum display_dongle_type dongle_type,
417 struct audio_support *audio_support)
418{
419 enum signal_type signal = SIGNAL_TYPE_NONE;
420
421 switch (dongle_type) {
422 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
423 if (audio_support->hdmi_audio_on_dongle)
424 signal = SIGNAL_TYPE_HDMI_TYPE_A;
425 else
426 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
427 break;
428 case DISPLAY_DONGLE_DP_DVI_DONGLE:
429 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
430 break;
431 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
432 if (audio_support->hdmi_audio_native)
433 signal = SIGNAL_TYPE_HDMI_TYPE_A;
434 else
435 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
436 break;
437 default:
438 signal = SIGNAL_TYPE_NONE;
439 break;
440 }
441
442 return signal;
443}
444
445static enum signal_type dp_passive_dongle_detection(
446 struct ddc_service *ddc,
447 struct display_sink_capability *sink_cap,
448 struct audio_support *audio_support)
449{
450 dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
451 ddc, sink_cap);
452 return decide_signal_from_strap_and_dongle_type(
453 sink_cap->dongle_type,
454 audio_support);
455}
456
d0778ebf 457static void link_disconnect_sink(struct dc_link *link)
4562236b 458{
d0778ebf
HW		 459 if (link->local_sink) {
460 dc_sink_release(link->local_sink);
461 link->local_sink = NULL;
4562236b
HW		 462 }
463
464 link->dpcd_sink_count = 0;
465}
466
4562236b 467static void detect_dp(
d0778ebf 468 struct dc_link *link,
4562236b
HW		 469 struct display_sink_capability *sink_caps,
470 bool *converter_disable_audio,
471 struct audio_support *audio_support,
8f38b66c 472 enum dc_detect_reason reason)
4562236b 473{
8f38b66c
HW		 474 bool boot = false;
475 sink_caps->signal = link_detect_sink(link, reason);
4562236b
HW		 476 sink_caps->transaction_type =
477 get_ddc_transaction_type(sink_caps->signal);
478
479 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
480 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
481 detect_dp_sink_caps(link);
482
4562236b
HW		 483 if (is_mst_supported(link)) {
484 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
e4ba6335 485 link->type = dc_connection_mst_branch;
4562236b
HW		 486
487 /*
488 * This call will initiate MST topology discovery. Which
489 * will detect MST ports and add new DRM connector DRM
490 * framework. Then read EDID via remote i2c over aux. In
491 * the end, will notify DRM detect result and save EDID
492 * into DRM framework.
493 *
494 * .detect is called by .fill_modes.
495 * .fill_modes is called by user mode ioctl
496 * DRM_IOCTL_MODE_GETCONNECTOR.
497 *
498 * .get_modes is called by .fill_modes.
499 *
500 * call .get_modes, AMDGPU DM implementation will create
501 * new dc_sink and add to dc_link. For long HPD plug
502 * in/out, MST has its own handle.
503 *
504 * Therefore, just after dc_create, link->sink is not
505 * created for MST until user mode app calls
506 * DRM_IOCTL_MODE_GETCONNECTOR.
507 *
508 * Need check ->sink usages in case ->sink = NULL
509 * TODO: s3 resume check
510 */
8f38b66c
HW		 511 if (reason == DETECT_REASON_BOOT)
512 boot = true;
4562236b 513
e4ba6335 514 if (!dm_helpers_dp_mst_start_top_mgr(
4562236b 515 link->ctx,
d0778ebf 516 link, boot)) {
4562236b 517 /* MST not supported */
e4ba6335 518 link->type = dc_connection_single;
4562236b
HW		 519 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
520 }
521 }
58fe8990
HW		 522
523 if (link->type != dc_connection_mst_branch &&
524 is_dp_active_dongle(link)) {
525 /* DP active dongles */
526 link->type = dc_connection_active_dongle;
527 if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
528 /*
529 * active dongle unplug processing for short irq
530 */
531 link_disconnect_sink(link);
532 return;
533 }
534
535 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
536 *converter_disable_audio = true;
537 }
4562236b
HW		 538 } else {
539 /* DP passive dongles */
d0778ebf 540 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
4562236b
HW		 541 sink_caps,
542 audio_support);
543 }
544}
545
8f38b66c 546bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
4562236b 547{
4562236b
HW		 548 struct dc_sink_init_data sink_init_data = { 0 };
549 struct display_sink_capability sink_caps = { 0 };
550 uint8_t i;
551 bool converter_disable_audio = false;
552 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
553 enum dc_edid_status edid_status;
554 struct dc_context *dc_ctx = link->ctx;
533ed6c7 555 struct dc_sink *sink = NULL;
4562236b
HW		 556 enum dc_connection_type new_connection_type = dc_connection_none;
557
d0778ebf 558 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
4562236b
HW		 559 return false;
560
561 if (false == detect_sink(link, &new_connection_type)) {
562 BREAK_TO_DEBUGGER();
563 return false;
564 }
565
d0778ebf
HW		 566 if (link->connector_signal == SIGNAL_TYPE_EDP &&
567 link->local_sink)
4562236b
HW		 568 return true;
569
dcf298c3
WL		 570 link_disconnect_sink(link);
571
4562236b 572 if (new_connection_type != dc_connection_none) {
d0778ebf 573 link->type = new_connection_type;
4562236b
HW		 574
575 /* From Disconnected-to-Connected. */
d0778ebf 576 switch (link->connector_signal) {
4562236b
HW		 577 case SIGNAL_TYPE_HDMI_TYPE_A: {
578 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
579 if (aud_support->hdmi_audio_native)
580 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
581 else
582 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
583 break;
584 }
585
586 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
587 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
588 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
589 break;
590 }
591
592 case SIGNAL_TYPE_DVI_DUAL_LINK: {
593 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
594 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
595 break;
596 }
597
598 case SIGNAL_TYPE_EDP: {
4654a2f7 599 detect_edp_sink_caps(link);
4562236b
HW		 600 sink_caps.transaction_type =
601 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
602 sink_caps.signal = SIGNAL_TYPE_EDP;
603 break;
604 }
605
606 case SIGNAL_TYPE_DISPLAY_PORT: {
607 detect_dp(
608 link,
609 &sink_caps,
610 &converter_disable_audio,
8f38b66c 611 aud_support, reason);
4562236b
HW		 612
613 /* Active dongle downstream unplug */
d0778ebf 614 if (link->type == dc_connection_active_dongle
4562236b
HW		 615 && link->dpcd_caps.sink_count.
616 bits.SINK_COUNT == 0)
617 return true;
618
d0778ebf 619 if (link->type == dc_connection_mst_branch) {
4562236b 620 LINK_INFO("link=%d, mst branch is now Connected\n",
d0778ebf 621 link->link_index);
3f1f74f4
JZ		 622 /* Need to setup mst link_cap struct here
623 * otherwise dc_link_detect() will leave mst link_cap
624 * empty which leads to allocate_mst_payload() has "0"
625 * pbn_per_slot value leading to exception on dal_fixed31_32_div()
626 */
627 link->verified_link_cap = link->reported_link_cap;
4562236b
HW		 628 return false;
629 }
630
631 break;
632 }
633
634 default:
635 DC_ERROR("Invalid connector type! signal:%d\n",
d0778ebf 636 link->connector_signal);
4562236b
HW		 637 return false;
638 } /* switch() */
639
640 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
641 link->dpcd_sink_count = link->dpcd_caps.sink_count.
642 bits.SINK_COUNT;
2a0b4d85
MT		 643 else
644 link->dpcd_sink_count = 1;
4562236b
HW		 645
646 dal_ddc_service_set_transaction_type(
d0778ebf 647 link->ddc,
4562236b
HW		 648 sink_caps.transaction_type);
649
d0778ebf
HW		 650 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
651 link->ddc);
7c7f5b15 652
d0778ebf 653 sink_init_data.link = link;
4562236b 654 sink_init_data.sink_signal = sink_caps.signal;
4562236b 655
7d58e721
MT		 656 sink = dc_sink_create(&sink_init_data);
657 if (!sink) {
658 DC_ERROR("Failed to create sink!\n");
659 return false;
660 }
4562236b 661
dcf298c3
WL		 662 sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
663 sink->converter_disable_audio = converter_disable_audio;
7d58e721 664
dcf298c3 665 link->local_sink = sink;
4562236b 666
dcf298c3 667 edid_status = dm_helpers_read_local_edid(
7c7f5b15 668 link->ctx,
d0778ebf 669 link,
b73a22d3 670 sink);
4562236b
HW		 671
672 switch (edid_status) {
673 case EDID_BAD_CHECKSUM:
674 dm_logger_write(link->ctx->logger, LOG_ERROR,
675 "EDID checksum invalid.\n");
676 break;
677 case EDID_NO_RESPONSE:
678 dm_logger_write(link->ctx->logger, LOG_ERROR,
679 "No EDID read.\n");
680 return false;
681
682 default:
683 break;
684 }
685
f334073a
WL		 686 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
687 sink_caps.transaction_type ==
688 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
689 /*
690 * TODO debug why Dell 2413 doesn't like
691 * two link trainings
692 */
3f1f74f4
JZ		 693
694 /* deal with non-mst cases */
695 dp_hbr_verify_link_cap(link, &link->reported_link_cap);
f334073a
WL		 696 }
697
4562236b 698 /* HDMI-DVI Dongle */
b73a22d3
HW		 699 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
700 !sink->edid_caps.edid_hdmi)
701 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
4562236b
HW		 702
703 /* Connectivity log: detection */
b73a22d3 704 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
4562236b 705 CONN_DATA_DETECT(link,
b73a22d3 706 &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
4562236b 707 EDID_BLOCK_SIZE,
b73a22d3 708 "%s: [Block %d] ", sink->edid_caps.display_name, i);
4562236b
HW		 709 }
710
711 dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,
712 "%s: "
713 "manufacturer_id = %X, "
714 "product_id = %X, "
715 "serial_number = %X, "
716 "manufacture_week = %d, "
717 "manufacture_year = %d, "
718 "display_name = %s, "
719 "speaker_flag = %d, "
720 "audio_mode_count = %d\n",
721 __func__,
b73a22d3
HW		 722 sink->edid_caps.manufacturer_id,
723 sink->edid_caps.product_id,
724 sink->edid_caps.serial_number,
725 sink->edid_caps.manufacture_week,
726 sink->edid_caps.manufacture_year,
727 sink->edid_caps.display_name,
728 sink->edid_caps.speaker_flags,
729 sink->edid_caps.audio_mode_count);
730
731 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
4562236b
HW		 732 dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,
733 "%s: mode number = %d, "
734 "format_code = %d, "
735 "channel_count = %d, "
736 "sample_rate = %d, "
737 "sample_size = %d\n",
738 __func__,
739 i,
b73a22d3
HW		 740 sink->edid_caps.audio_modes[i].format_code,
741 sink->edid_caps.audio_modes[i].channel_count,
742 sink->edid_caps.audio_modes[i].sample_rate,
743 sink->edid_caps.audio_modes[i].sample_size);
4562236b
HW		 744 }
745
746 } else {
747 /* From Connected-to-Disconnected. */
d0778ebf 748 if (link->type == dc_connection_mst_branch) {
4562236b 749 LINK_INFO("link=%d, mst branch is now Disconnected\n",
d0778ebf 750 link->link_index);
dcf298c3 751
d0778ebf 752 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
4562236b
HW		 753
754 link->mst_stream_alloc_table.stream_count = 0;
755 memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
756 }
757
dcf298c3
WL		 758 link->type = dc_connection_none;
759 sink_caps.signal = SIGNAL_TYPE_NONE;
4562236b
HW		 760 }
761
762 LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
b73a22d3 763 link->link_index, sink,
4562236b
HW		 764 (sink_caps.signal == SIGNAL_TYPE_NONE ?
765 "Disconnected":"Connected"));
766
767 return true;
768}
769
770static enum hpd_source_id get_hpd_line(
d0778ebf 771 struct dc_link *link)
4562236b
HW		 772{
773 struct gpio *hpd;
774 enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
775
87401969 776 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4562236b
HW		 777
778 if (hpd) {
779 switch (dal_irq_get_source(hpd)) {
780 case DC_IRQ_SOURCE_HPD1:
781 hpd_id = HPD_SOURCEID1;
782 break;
783 case DC_IRQ_SOURCE_HPD2:
784 hpd_id = HPD_SOURCEID2;
785 break;
786 case DC_IRQ_SOURCE_HPD3:
787 hpd_id = HPD_SOURCEID3;
788 break;
789 case DC_IRQ_SOURCE_HPD4:
790 hpd_id = HPD_SOURCEID4;
791 break;
792 case DC_IRQ_SOURCE_HPD5:
793 hpd_id = HPD_SOURCEID5;
794 break;
795 case DC_IRQ_SOURCE_HPD6:
796 hpd_id = HPD_SOURCEID6;
797 break;
798 default:
799 BREAK_TO_DEBUGGER();
800 break;
801 }
802
803 dal_gpio_destroy_irq(&hpd);
804 }
805
806 return hpd_id;
807}
808
d0778ebf 809static enum channel_id get_ddc_line(struct dc_link *link)
4562236b
HW		 810{
811 struct ddc *ddc;
812 enum channel_id channel = CHANNEL_ID_UNKNOWN;
813
d0778ebf 814 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
4562236b
HW		 815
816 if (ddc) {
817 switch (dal_ddc_get_line(ddc)) {
818 case GPIO_DDC_LINE_DDC1:
819 channel = CHANNEL_ID_DDC1;
820 break;
821 case GPIO_DDC_LINE_DDC2:
822 channel = CHANNEL_ID_DDC2;
823 break;
824 case GPIO_DDC_LINE_DDC3:
825 channel = CHANNEL_ID_DDC3;
826 break;
827 case GPIO_DDC_LINE_DDC4:
828 channel = CHANNEL_ID_DDC4;
829 break;
830 case GPIO_DDC_LINE_DDC5:
831 channel = CHANNEL_ID_DDC5;
832 break;
833 case GPIO_DDC_LINE_DDC6:
834 channel = CHANNEL_ID_DDC6;
835 break;
836 case GPIO_DDC_LINE_DDC_VGA:
837 channel = CHANNEL_ID_DDC_VGA;
838 break;
839 case GPIO_DDC_LINE_I2C_PAD:
840 channel = CHANNEL_ID_I2C_PAD;
841 break;
842 default:
843 BREAK_TO_DEBUGGER();
844 break;
845 }
846 }
847
848 return channel;
849}
850
851static enum transmitter translate_encoder_to_transmitter(
852 struct graphics_object_id encoder)
853{
854 switch (encoder.id) {
855 case ENCODER_ID_INTERNAL_UNIPHY:
856 switch (encoder.enum_id) {
857 case ENUM_ID_1:
858 return TRANSMITTER_UNIPHY_A;
859 case ENUM_ID_2:
860 return TRANSMITTER_UNIPHY_B;
861 default:
862 return TRANSMITTER_UNKNOWN;
863 }
864 break;
865 case ENCODER_ID_INTERNAL_UNIPHY1:
866 switch (encoder.enum_id) {
867 case ENUM_ID_1:
868 return TRANSMITTER_UNIPHY_C;
869 case ENUM_ID_2:
870 return TRANSMITTER_UNIPHY_D;
871 default:
872 return TRANSMITTER_UNKNOWN;
873 }
874 break;
875 case ENCODER_ID_INTERNAL_UNIPHY2:
876 switch (encoder.enum_id) {
877 case ENUM_ID_1:
878 return TRANSMITTER_UNIPHY_E;
879 case ENUM_ID_2:
880 return TRANSMITTER_UNIPHY_F;
881 default:
882 return TRANSMITTER_UNKNOWN;
883 }
884 break;
885 case ENCODER_ID_INTERNAL_UNIPHY3:
886 switch (encoder.enum_id) {
887 case ENUM_ID_1:
888 return TRANSMITTER_UNIPHY_G;
889 default:
890 return TRANSMITTER_UNKNOWN;
891 }
892 break;
893 case ENCODER_ID_EXTERNAL_NUTMEG:
894 switch (encoder.enum_id) {
895 case ENUM_ID_1:
896 return TRANSMITTER_NUTMEG_CRT;
897 default:
898 return TRANSMITTER_UNKNOWN;
899 }
900 break;
901 case ENCODER_ID_EXTERNAL_TRAVIS:
902 switch (encoder.enum_id) {
903 case ENUM_ID_1:
904 return TRANSMITTER_TRAVIS_CRT;
905 case ENUM_ID_2:
906 return TRANSMITTER_TRAVIS_LCD;
907 default:
908 return TRANSMITTER_UNKNOWN;
909 }
910 break;
911 default:
912 return TRANSMITTER_UNKNOWN;
913 }
914}
915
916static bool construct(
d0778ebf 917 struct dc_link *link,
4562236b
HW		 918 const struct link_init_data *init_params)
919{
920 uint8_t i;
921 struct gpio *hpd_gpio = NULL;
c2e218dd 922 struct ddc_service_init_data ddc_service_init_data = { { 0 } };
4562236b
HW		 923 struct dc_context *dc_ctx = init_params->ctx;
924 struct encoder_init_data enc_init_data = { 0 };
925 struct integrated_info info = {{{ 0 }}};
926 struct dc_bios *bios = init_params->dc->ctx->dc_bios;
927 const struct dc_vbios_funcs *bp_funcs = bios->funcs;
928
d0778ebf
HW		 929 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
930 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
4562236b
HW		 931
932 link->link_status.dpcd_caps = &link->dpcd_caps;
933
934 link->dc = init_params->dc;
935 link->ctx = dc_ctx;
d0778ebf 936 link->link_index = init_params->link_index;
4562236b
HW		 937
938 link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
939
940 if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
63b371ec
HW		 941 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
942 __func__, init_params->connector_index,
943 link->link_id.type, OBJECT_TYPE_CONNECTOR);
4562236b
HW		 944 goto create_fail;
945 }
946
87401969 947 hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4562236b
HW		 948
949 if (hpd_gpio != NULL)
d0778ebf 950 link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
4562236b
HW		 951
952 switch (link->link_id.id) {
953 case CONNECTOR_ID_HDMI_TYPE_A:
d0778ebf 954 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
4562236b
HW		 955
956 break;
957 case CONNECTOR_ID_SINGLE_LINK_DVID:
958 case CONNECTOR_ID_SINGLE_LINK_DVII:
d0778ebf 959 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
4562236b
HW		 960 break;
961 case CONNECTOR_ID_DUAL_LINK_DVID:
962 case CONNECTOR_ID_DUAL_LINK_DVII:
d0778ebf 963 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
4562236b
HW		 964 break;
965 case CONNECTOR_ID_DISPLAY_PORT:
d0778ebf 966 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
4562236b
HW		 967
968 if (hpd_gpio != NULL)
d0778ebf 969 link->irq_source_hpd_rx =
4562236b
HW		 970 dal_irq_get_rx_source(hpd_gpio);
971
972 break;
973 case CONNECTOR_ID_EDP:
d0778ebf 974 link->connector_signal = SIGNAL_TYPE_EDP;
4562236b
HW		 975
976 if (hpd_gpio != NULL) {
d0778ebf
HW		 977 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
978 link->irq_source_hpd_rx =
4562236b
HW		 979 dal_irq_get_rx_source(hpd_gpio);
980 }
981 break;
982 default:
983 dm_logger_write(dc_ctx->logger, LOG_WARNING,
984 "Unsupported Connector type:%d!\n", link->link_id.id);
985 goto create_fail;
986 }
987
988 if (hpd_gpio != NULL) {
989 dal_gpio_destroy_irq(&hpd_gpio);
990 hpd_gpio = NULL;
991 }
992
993 /* TODO: #DAL3 Implement id to str function.*/
994 LINK_INFO("Connector[%d] description:"
995 "signal %d\n",
996 init_params->connector_index,
d0778ebf 997 link->connector_signal);
4562236b
HW		 998
999 ddc_service_init_data.ctx = link->ctx;
1000 ddc_service_init_data.id = link->link_id;
1001 ddc_service_init_data.link = link;
d0778ebf 1002 link->ddc = dal_ddc_service_create(&ddc_service_init_data);
4562236b 1003
d0778ebf 1004 if (link->ddc == NULL) {
4562236b
HW		 1005 DC_ERROR("Failed to create ddc_service!\n");
1006 goto ddc_create_fail;
1007 }
1008
d0778ebf 1009 link->ddc_hw_inst =
4562236b 1010 dal_ddc_get_line(
d0778ebf 1011 dal_ddc_service_get_ddc_pin(link->ddc));
4562236b
HW		 1012
1013 enc_init_data.ctx = dc_ctx;
1014 bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1015 enc_init_data.connector = link->link_id;
1016 enc_init_data.channel = get_ddc_line(link);
1017 enc_init_data.hpd_source = get_hpd_line(link);
7a096334 1018
d0778ebf 1019 link->hpd_src = enc_init_data.hpd_source;
7a096334 1020
4562236b
HW		 1021 enc_init_data.transmitter =
1022 translate_encoder_to_transmitter(enc_init_data.encoder);
1023 link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1024 &enc_init_data);
1025
1026 if( link->link_enc == NULL) {
1027 DC_ERROR("Failed to create link encoder!\n");
1028 goto link_enc_create_fail;
1029 }
1030
d0778ebf 1031 link->link_enc_hw_inst = link->link_enc->transmitter;
4562236b
HW		 1032
1033 for (i = 0; i < 4; i++) {
1034 if (BP_RESULT_OK !=
1035 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1036 DC_ERROR("Failed to find device tag!\n");
1037 goto device_tag_fail;
1038 }
1039
1040 /* Look for device tag that matches connector signal,
1041 * CRT for rgb, LCD for other supported signal tyes
1042 */
1043 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1044 continue;
1045 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
d0778ebf 1046 && link->connector_signal != SIGNAL_TYPE_RGB)
4562236b
HW		 1047 continue;
1048 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
d0778ebf 1049 && link->connector_signal == SIGNAL_TYPE_RGB)
4562236b 1050 continue;
4562236b
HW		 1051 break;
1052 }
1053
1054 if (bios->integrated_info)
1055 info = *bios->integrated_info;
1056
1057 /* Look for channel mapping corresponding to connector and device tag */
1058 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1059 struct external_display_path *path =
1060 &info.ext_disp_conn_info.path[i];
1061 if (path->device_connector_id.enum_id == link->link_id.enum_id
1062 && path->device_connector_id.id == link->link_id.id
1e8635ea
ZF		 1063 && path->device_connector_id.type == link->link_id.type) {
1064
1065 if (link->device_tag.acpi_device != 0
1066 && path->device_acpi_enum == link->device_tag.acpi_device) {
1067 link->ddi_channel_mapping = path->channel_mapping;
1068 link->chip_caps = path->caps;
1069 } else if (path->device_tag ==
1070 link->device_tag.dev_id.raw_device_tag) {
1071 link->ddi_channel_mapping = path->channel_mapping;
1072 link->chip_caps = path->caps;
1073 }
4562236b
HW		 1074 break;
1075 }
1076 }
1077
1078 /*
1079 * TODO check if GPIO programmed correctly
1080 *
1081 * If GPIO isn't programmed correctly HPD might not rise or drain
1082 * fast enough, leading to bounces.
1083 */
1084 program_hpd_filter(link);
1085
1086 return true;
1087device_tag_fail:
1088 link->link_enc->funcs->destroy(&link->link_enc);
1089link_enc_create_fail:
d0778ebf 1090 dal_ddc_service_destroy(&link->ddc);
4562236b
HW		 1091ddc_create_fail:
1092create_fail:
1093
1094 if (hpd_gpio != NULL) {
1095 dal_gpio_destroy_irq(&hpd_gpio);
1096 }
1097
1098 return false;
1099}
1100
1101/*******************************************************************************
1102 * Public functions
1103 ******************************************************************************/
d0778ebf 1104struct dc_link *link_create(const struct link_init_data *init_params)
4562236b 1105{
d0778ebf 1106 struct dc_link *link =
2004f45e 1107 kzalloc(sizeof(*link), GFP_KERNEL);
4562236b
HW		 1108
1109 if (NULL == link)
1110 goto alloc_fail;
1111
1112 if (false == construct(link, init_params))
1113 goto construct_fail;
1114
1115 return link;
1116
1117construct_fail:
2004f45e 1118 kfree(link);
4562236b
HW		 1119
1120alloc_fail:
1121 return NULL;
1122}
1123
d0778ebf 1124void link_destroy(struct dc_link **link)
4562236b
HW		 1125{
1126 destruct(*link);
2004f45e 1127 kfree(*link);
4562236b
HW		 1128 *link = NULL;
1129}
1130
1131static void dpcd_configure_panel_mode(
d0778ebf 1132 struct dc_link *link,
4562236b
HW		 1133 enum dp_panel_mode panel_mode)
1134{
1135 union dpcd_edp_config edp_config_set;
1136 bool panel_mode_edp = false;
1137
1138 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1139
1140 if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1141
1142 switch (panel_mode) {
1143 case DP_PANEL_MODE_EDP:
1144 case DP_PANEL_MODE_SPECIAL:
1145 panel_mode_edp = true;
1146 break;
1147
1148 default:
1149 break;
1150 }
1151
1152 /*set edp panel mode in receiver*/
1153 core_link_read_dpcd(
1154 link,
3a340294 1155 DP_EDP_CONFIGURATION_SET,
4562236b
HW		 1156 &edp_config_set.raw,
1157 sizeof(edp_config_set.raw));
1158
1159 if (edp_config_set.bits.PANEL_MODE_EDP
1160 != panel_mode_edp) {
1161 enum ddc_result result = DDC_RESULT_UNKNOWN;
1162
1163 edp_config_set.bits.PANEL_MODE_EDP =
1164 panel_mode_edp;
1165 result = core_link_write_dpcd(
1166 link,
3a340294 1167 DP_EDP_CONFIGURATION_SET,
4562236b
HW		 1168 &edp_config_set.raw,
1169 sizeof(edp_config_set.raw));
1170
1171 ASSERT(result == DDC_RESULT_SUCESSFULL);
1172 }
1173 }
1174 dm_logger_write(link->ctx->logger, LOG_DETECTION_DP_CAPS,
1175 "Link: %d eDP panel mode supported: %d "
1176 "eDP panel mode enabled: %d \n",
d0778ebf 1177 link->link_index,
4562236b
HW		 1178 link->dpcd_caps.panel_mode_edp,
1179 panel_mode_edp);
1180}
1181
1182static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1183{
0971c40e 1184 struct dc_stream_state *stream = pipe_ctx->stream;
d0778ebf 1185 struct dc_link *link = stream->sink->link;
4562236b
HW		 1186 union down_spread_ctrl downspread;
1187
3a340294 1188 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
4562236b
HW		 1189 &downspread.raw, sizeof(downspread));
1190
1191 downspread.bits.IGNORE_MSA_TIMING_PARAM =
4fa086b9 1192 (stream->ignore_msa_timing_param) ? 1 : 0;
4562236b 1193
3a340294 1194 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
4562236b
HW		 1195 &downspread.raw, sizeof(downspread));
1196}
1197
ab8db3e1
AG		 1198static enum dc_status enable_link_dp(
1199 struct dc_state *state,
1200 struct pipe_ctx *pipe_ctx)
4562236b 1201{
0971c40e 1202 struct dc_stream_state *stream = pipe_ctx->stream;
4562236b
HW		 1203 enum dc_status status;
1204 bool skip_video_pattern;
d0778ebf 1205 struct dc_link *link = stream->sink->link;
4562236b
HW		 1206 struct dc_link_settings link_settings = {0};
1207 enum dp_panel_mode panel_mode;
4562236b
HW		 1208 enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
1209
1210 /* get link settings for video mode timing */
1211 decide_link_settings(stream, &link_settings);
1212
1213 /* raise clock state for HBR3 if required. Confirmed with HW DCE/DPCS
1214 * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
1215 */
1216 if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1217 max_link_rate = LINK_RATE_HIGH3;
1218
1219 if (link_settings.link_rate == max_link_rate) {
ab8db3e1
AG		 1220 if (state->dis_clk->funcs->set_min_clocks_state) {
1221 if (state->dis_clk->cur_min_clks_state < DM_PP_CLOCKS_STATE_NOMINAL)
1222 state->dis_clk->funcs->set_min_clocks_state(
1223 state->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL);
4562236b 1224 } else {
2c8ad2d5
AD		 1225 uint32_t dp_phyclk_in_khz;
1226 const struct clocks_value clocks_value =
ab8db3e1 1227 state->dis_clk->cur_clocks_value;
2c8ad2d5
AD		 1228
1229 /* 27mhz = 27000000hz= 27000khz */
1230 dp_phyclk_in_khz = link_settings.link_rate * 27000;
1231
1232 if (((clocks_value.max_non_dp_phyclk_in_khz != 0) &&
1233 (dp_phyclk_in_khz > clocks_value.max_non_dp_phyclk_in_khz)) ||
1234 (dp_phyclk_in_khz > clocks_value.max_dp_phyclk_in_khz)) {
ab8db3e1
AG		 1235 state->dis_clk->funcs->apply_clock_voltage_request(
1236 state->dis_clk,
2c8ad2d5
AD		 1237 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1238 dp_phyclk_in_khz,
1239 false,
1240 true);
1241 }
4562236b
HW		 1242 }
1243 }
1244
1245 dp_enable_link_phy(
1246 link,
1247 pipe_ctx->stream->signal,
1248 pipe_ctx->clock_source->id,
1249 &link_settings);
1250
1251 panel_mode = dp_get_panel_mode(link);
1252 dpcd_configure_panel_mode(link, panel_mode);
1253
1254 skip_video_pattern = true;
1255
1256 if (link_settings.link_rate == LINK_RATE_LOW)
1257 skip_video_pattern = false;
1258
1259 if (perform_link_training_with_retries(
1260 link,
1261 &link_settings,
1262 skip_video_pattern,
1263 LINK_TRAINING_ATTEMPTS)) {
d0778ebf 1264 link->cur_link_settings = link_settings;
4562236b
HW		 1265 status = DC_OK;
1266 }
1267 else
c0ba5ec7 1268 status = DC_FAIL_DP_LINK_TRAINING;
4562236b
HW		 1269
1270 enable_stream_features(pipe_ctx);
1271
1272 return status;
1273}
1274
904623ee
YS		 1275static enum dc_status enable_link_edp(
1276 struct dc_state *state,
1277 struct pipe_ctx *pipe_ctx)
1278{
1279 enum dc_status status;
1280 struct dc_stream_state *stream = pipe_ctx->stream;
1281 struct dc_link *link = stream->sink->link;
1282
1283 link->dc->hwss.edp_power_control(link, true);
1284 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1285
1286 status = enable_link_dp(state, pipe_ctx);
1287
1288 link->dc->hwss.edp_backlight_control(link, true);
1289
1290 return status;
1291}
1292
ab8db3e1
AG		 1293static enum dc_status enable_link_dp_mst(
1294 struct dc_state *state,
1295 struct pipe_ctx *pipe_ctx)
4562236b 1296{
d0778ebf 1297 struct dc_link *link = pipe_ctx->stream->sink->link;
4562236b
HW		 1298
1299 /* sink signal type after MST branch is MST. Multiple MST sinks
1300 * share one link. Link DP PHY is enable or training only once.
1301 */
d0778ebf 1302 if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
4562236b
HW		 1303 return DC_OK;
1304
07c84c7a
DW		 1305 /* set the sink to MST mode before enabling the link */
1306 dp_enable_mst_on_sink(link, true);
1307
ab8db3e1 1308 return enable_link_dp(state, pipe_ctx);
4562236b
HW		 1309}
1310
1e8635ea
ZF		 1311static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1312 enum engine_id eng_id,
1313 struct ext_hdmi_settings *settings)
1314{
1315 bool result = false;
1316 int i = 0;
1317 struct integrated_info *integrated_info =
1318 pipe_ctx->stream->ctx->dc_bios->integrated_info;
1319
1320 if (integrated_info == NULL)
1321 return false;
1322
1323 /*
1324 * Get retimer settings from sbios for passing SI eye test for DCE11
1325 * The setting values are varied based on board revision and port id
1326 * Therefore the setting values of each ports is passed by sbios.
1327 */
1328
1329 // Check if current bios contains ext Hdmi settings
1330 if (integrated_info->gpu_cap_info & 0x20) {
1331 switch (eng_id) {
1332 case ENGINE_ID_DIGA:
1333 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1334 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1335 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1336 memmove(settings->reg_settings,
1337 integrated_info->dp0_ext_hdmi_reg_settings,
1338 sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1339 memmove(settings->reg_settings_6g,
1340 integrated_info->dp0_ext_hdmi_6g_reg_settings,
1341 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1342 result = true;
1343 break;
1344 case ENGINE_ID_DIGB:
1345 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1346 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1347 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1348 memmove(settings->reg_settings,
1349 integrated_info->dp1_ext_hdmi_reg_settings,
1350 sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1351 memmove(settings->reg_settings_6g,
1352 integrated_info->dp1_ext_hdmi_6g_reg_settings,
1353 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1354 result = true;
1355 break;
1356 case ENGINE_ID_DIGC:
1357 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1358 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1359 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1360 memmove(settings->reg_settings,
1361 integrated_info->dp2_ext_hdmi_reg_settings,
1362 sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1363 memmove(settings->reg_settings_6g,
1364 integrated_info->dp2_ext_hdmi_6g_reg_settings,
1365 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1366 result = true;
1367 break;
4e527c01
AJ		 1368 case ENGINE_ID_DIGD:
1369 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1370 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1371 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1372 memmove(settings->reg_settings,
1373 integrated_info->dp3_ext_hdmi_reg_settings,
1374 sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1375 memmove(settings->reg_settings_6g,
1376 integrated_info->dp3_ext_hdmi_6g_reg_settings,
1377 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1378 result = true;
1379 break;
1e8635ea
ZF		 1380 default:
1381 break;
1382 }
1383
1384 if (result == true) {
1385 // Validate settings from bios integrated info table
1386 if (settings->slv_addr == 0)
1387 return false;
1388 if (settings->reg_num > 9)
1389 return false;
1390 if (settings->reg_num_6g > 3)
1391 return false;
1392
1393 for (i = 0; i < settings->reg_num; i++) {
1394 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1395 return false;
1396 }
1397
1398 for (i = 0; i < settings->reg_num_6g; i++) {
1399 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1400 return false;
1401 }
1402 }
1403 }
1404
1405 return result;
1406}
1407
1408static bool i2c_write(struct pipe_ctx *pipe_ctx,
1409 uint8_t address, uint8_t *buffer, uint32_t length)
1410{
1411 struct i2c_command cmd = {0};
1412 struct i2c_payload payload = {0};
1413
1414 memset(&payload, 0, sizeof(payload));
1415 memset(&cmd, 0, sizeof(cmd));
1416
1417 cmd.number_of_payloads = 1;
1418 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1419 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1420
1421 payload.address = address;
1422 payload.data = buffer;
1423 payload.length = length;
1424 payload.write = true;
1425 cmd.payloads = &payload;
1426
1427 if (dc_submit_i2c(pipe_ctx->stream->ctx->dc,
1428 pipe_ctx->stream->sink->link->link_index, &cmd))
1429 return true;
1430
1431 return false;
1432}
1433
1434static void write_i2c_retimer_setting(
1435 struct pipe_ctx *pipe_ctx,
1436 bool is_vga_mode,
1437 bool is_over_340mhz,
1438 struct ext_hdmi_settings *settings)
1439{
1440 uint8_t slave_address = (settings->slv_addr >> 1);
1441 uint8_t buffer[2];
1442 const uint8_t apply_rx_tx_change = 0x4;
1443 uint8_t offset = 0xA;
1444 uint8_t value = 0;
1445 int i = 0;
1446 bool i2c_success = false;
1447
1448 memset(&buffer, 0, sizeof(buffer));
1449
1450 /* Start Ext-Hdmi programming*/
1451
1452 for (i = 0; i < settings->reg_num; i++) {
1453 /* Apply 3G settings */
1454 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1455
1456 buffer[0] = settings->reg_settings[i].i2c_reg_index;
1457 buffer[1] = settings->reg_settings[i].i2c_reg_val;
1458 i2c_success = i2c_write(pipe_ctx, slave_address,
1459 buffer, sizeof(buffer));
1460
1461 if (!i2c_success)
1462 /* Write failure */
1463 ASSERT(i2c_success);
1464
1465 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1466 * needs to be set to 1 on every 0xA-0xC write.
1467 */
1468 if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1469 settings->reg_settings[i].i2c_reg_index == 0xB ||
1470 settings->reg_settings[i].i2c_reg_index == 0xC) {
1471
1472 /* Query current value from offset 0xA */
1473 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1474 value = settings->reg_settings[i].i2c_reg_val;
1475 else {
1476 i2c_success =
1477 dal_ddc_service_query_ddc_data(
1478 pipe_ctx->stream->sink->link->ddc,
1479 slave_address, &offset, 1, &value, 1);
1480 if (!i2c_success)
1481 /* Write failure */
1482 ASSERT(i2c_success);
1483 }
1484
1485 buffer[0] = offset;
1486 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1487 buffer[1] = value | apply_rx_tx_change;
1488 i2c_success = i2c_write(pipe_ctx, slave_address,
1489 buffer, sizeof(buffer));
1490 if (!i2c_success)
1491 /* Write failure */
1492 ASSERT(i2c_success);
1493 }
1494 }
1495 }
1496
1497 /* Apply 3G settings */
1498 if (is_over_340mhz) {
1499 for (i = 0; i < settings->reg_num_6g; i++) {
1500 /* Apply 3G settings */
1501 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1502
1503 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1504 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1505 i2c_success = i2c_write(pipe_ctx, slave_address,
1506 buffer, sizeof(buffer));
1507
1508 if (!i2c_success)
1509 /* Write failure */
1510 ASSERT(i2c_success);
1511
1512 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1513 * needs to be set to 1 on every 0xA-0xC write.
1514 */
1515 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1516 settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1517 settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1518
1519 /* Query current value from offset 0xA */
1520 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1521 value = settings->reg_settings_6g[i].i2c_reg_val;
1522 else {
1523 i2c_success =
1524 dal_ddc_service_query_ddc_data(
1525 pipe_ctx->stream->sink->link->ddc,
1526 slave_address, &offset, 1, &value, 1);
1527 if (!i2c_success)
1528 /* Write failure */
1529 ASSERT(i2c_success);
1530 }
1531
1532 buffer[0] = offset;
1533 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1534 buffer[1] = value | apply_rx_tx_change;
1535 i2c_success = i2c_write(pipe_ctx, slave_address,
1536 buffer, sizeof(buffer));
1537 if (!i2c_success)
1538 /* Write failure */
1539 ASSERT(i2c_success);
1540 }
1541 }
1542 }
1543 }
1544
1545 if (is_vga_mode) {
1546 /* Program additional settings if using 640x480 resolution */
1547
1548 /* Write offset 0xFF to 0x01 */
1549 buffer[0] = 0xff;
1550 buffer[1] = 0x01;
1551 i2c_success = i2c_write(pipe_ctx, slave_address,
1552 buffer, sizeof(buffer));
1553 if (!i2c_success)
1554 /* Write failure */
1555 ASSERT(i2c_success);
1556
1557 /* Write offset 0x00 to 0x23 */
1558 buffer[0] = 0x00;
1559 buffer[1] = 0x23;
1560 i2c_success = i2c_write(pipe_ctx, slave_address,
1561 buffer, sizeof(buffer));
1562 if (!i2c_success)
1563 /* Write failure */
1564 ASSERT(i2c_success);
1565
1566 /* Write offset 0xff to 0x00 */
1567 buffer[0] = 0xff;
1568 buffer[1] = 0x00;
1569 i2c_success = i2c_write(pipe_ctx, slave_address,
1570 buffer, sizeof(buffer));
1571 if (!i2c_success)
1572 /* Write failure */
1573 ASSERT(i2c_success);
1574
1575 }
1576}
1577
1578static void write_i2c_default_retimer_setting(
1579 struct pipe_ctx *pipe_ctx,
1580 bool is_vga_mode,
1581 bool is_over_340mhz)
1582{
1583 uint8_t slave_address = (0xBA >> 1);
1584 uint8_t buffer[2];
1585 bool i2c_success = false;
1586
1587 memset(&buffer, 0, sizeof(buffer));
1588
1589 /* Program Slave Address for tuning single integrity */
1590 /* Write offset 0x0A to 0x13 */
1591 buffer[0] = 0x0A;
1592 buffer[1] = 0x13;
1593 i2c_success = i2c_write(pipe_ctx, slave_address,
1594 buffer, sizeof(buffer));
1595 if (!i2c_success)
1596 /* Write failure */
1597 ASSERT(i2c_success);
1598
1599 /* Write offset 0x0A to 0x17 */
1600 buffer[0] = 0x0A;
1601 buffer[1] = 0x17;
1602 i2c_success = i2c_write(pipe_ctx, slave_address,
1603 buffer, sizeof(buffer));
1604 if (!i2c_success)
1605 /* Write failure */
1606 ASSERT(i2c_success);
1607
1608 /* Write offset 0x0B to 0xDA or 0xD8 */
1609 buffer[0] = 0x0B;
1610 buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1611 i2c_success = i2c_write(pipe_ctx, slave_address,
1612 buffer, sizeof(buffer));
1613 if (!i2c_success)
1614 /* Write failure */
1615 ASSERT(i2c_success);
1616
1617 /* Write offset 0x0A to 0x17 */
1618 buffer[0] = 0x0A;
1619 buffer[1] = 0x17;
1620 i2c_success = i2c_write(pipe_ctx, slave_address,
1621 buffer, sizeof(buffer));
1622 if (!i2c_success)
1623 /* Write failure */
1624 ASSERT(i2c_success);
1625
1626 /* Write offset 0x0C to 0x1D or 0x91 */
1627 buffer[0] = 0x0C;
1628 buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1629 i2c_success = i2c_write(pipe_ctx, slave_address,
1630 buffer, sizeof(buffer));
1631 if (!i2c_success)
1632 /* Write failure */
1633 ASSERT(i2c_success);
1634
1635 /* Write offset 0x0A to 0x17 */
1636 buffer[0] = 0x0A;
1637 buffer[1] = 0x17;
1638 i2c_success = i2c_write(pipe_ctx, slave_address,
1639 buffer, sizeof(buffer));
1640 if (!i2c_success)
1641 /* Write failure */
1642 ASSERT(i2c_success);
1643
1644
1645 if (is_vga_mode) {
1646 /* Program additional settings if using 640x480 resolution */
1647
1648 /* Write offset 0xFF to 0x01 */
1649 buffer[0] = 0xff;
1650 buffer[1] = 0x01;
1651 i2c_success = i2c_write(pipe_ctx, slave_address,
1652 buffer, sizeof(buffer));
1653 if (!i2c_success)
1654 /* Write failure */
1655 ASSERT(i2c_success);
1656
1657 /* Write offset 0x00 to 0x23 */
1658 buffer[0] = 0x00;
1659 buffer[1] = 0x23;
1660 i2c_success = i2c_write(pipe_ctx, slave_address,
1661 buffer, sizeof(buffer));
1662 if (!i2c_success)
1663 /* Write failure */
1664 ASSERT(i2c_success);
1665
1666 /* Write offset 0xff to 0x00 */
1667 buffer[0] = 0xff;
1668 buffer[1] = 0x00;
1669 i2c_success = i2c_write(pipe_ctx, slave_address,
1670 buffer, sizeof(buffer));
1671 if (!i2c_success)
1672 /* Write failure */
1673 ASSERT(i2c_success);
1674 }
1675}
1676
1677static void write_i2c_redriver_setting(
1678 struct pipe_ctx *pipe_ctx,
1679 bool is_over_340mhz)
1680{
1681 uint8_t slave_address = (0xF0 >> 1);
1682 uint8_t buffer[16];
1683 bool i2c_success = false;
1684
1685 memset(&buffer, 0, sizeof(buffer));
1686
1687 // Program Slave Address for tuning single integrity
1688 buffer[3] = 0x4E;
1689 buffer[4] = 0x4E;
1690 buffer[5] = 0x4E;
1691 buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1692
1693 i2c_success = i2c_write(pipe_ctx, slave_address,
1694 buffer, sizeof(buffer));
1695
1696 if (!i2c_success)
1697 /* Write failure */
1698 ASSERT(i2c_success);
1699}
1700
4562236b
HW		 1701static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1702{
0971c40e 1703 struct dc_stream_state *stream = pipe_ctx->stream;
d0778ebf 1704 struct dc_link *link = stream->sink->link;
cc4d99b8 1705 enum dc_color_depth display_color_depth;
1e8635ea
ZF		 1706 enum engine_id eng_id;
1707 struct ext_hdmi_settings settings = {0};
1708 bool is_over_340mhz = false;
1709 bool is_vga_mode = (stream->timing.h_addressable == 640)
1710 && (stream->timing.v_addressable == 480);
1711
1712 if (stream->phy_pix_clk > 340000)
1713 is_over_340mhz = true;
1714
1715 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3e5e2215
AJ		 1716 unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
1717 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
cc57306f 1718 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1e8635ea
ZF		 1719 /* DP159, Retimer settings */
1720 eng_id = pipe_ctx->stream_res.stream_enc->id;
1721
1722 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1723 write_i2c_retimer_setting(pipe_ctx,
1724 is_vga_mode, is_over_340mhz, &settings);
1725 } else {
1726 write_i2c_default_retimer_setting(pipe_ctx,
1727 is_vga_mode, is_over_340mhz);
1728 }
cc57306f 1729 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1e8635ea
ZF		 1730 /* PI3EQX1204, Redriver settings */
1731 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1732 }
1733 }
4562236b
HW		 1734
1735 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1736 dal_ddc_service_write_scdc_data(
d0778ebf 1737 stream->sink->link->ddc,
4562236b 1738 stream->phy_pix_clk,
4fa086b9 1739 stream->timing.flags.LTE_340MCSC_SCRAMBLE);
4562236b 1740
d0778ebf 1741 memset(&stream->sink->link->cur_link_settings, 0,
4562236b
HW		 1742 sizeof(struct dc_link_settings));
1743
4fa086b9
LSL		 1744 display_color_depth = stream->timing.display_color_depth;
1745 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
cc4d99b8
CL		 1746 display_color_depth = COLOR_DEPTH_888;
1747
4562236b
HW		 1748 link->link_enc->funcs->enable_tmds_output(
1749 link->link_enc,
1750 pipe_ctx->clock_source->id,
cc4d99b8 1751 display_color_depth,
35c4c88c 1752 pipe_ctx->stream->signal,
4562236b
HW		 1753 stream->phy_pix_clk);
1754
1755 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
d0778ebf 1756 dal_ddc_service_read_scdc_data(link->ddc);
4562236b
HW		 1757}
1758
1759/****************************enable_link***********************************/
ab8db3e1
AG		 1760static enum dc_status enable_link(
1761 struct dc_state *state,
1762 struct pipe_ctx *pipe_ctx)
4562236b
HW		 1763{
1764 enum dc_status status = DC_ERROR_UNEXPECTED;
1765 switch (pipe_ctx->stream->signal) {
1766 case SIGNAL_TYPE_DISPLAY_PORT:
ab8db3e1 1767 status = enable_link_dp(state, pipe_ctx);
4562236b 1768 break;
904623ee
YS		 1769 case SIGNAL_TYPE_EDP:
1770 status = enable_link_edp(state, pipe_ctx);
1771 break;
4562236b 1772 case SIGNAL_TYPE_DISPLAY_PORT_MST:
ab8db3e1 1773 status = enable_link_dp_mst(state, pipe_ctx);
4562236b
HW		 1774 msleep(200);
1775 break;
1776 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1777 case SIGNAL_TYPE_DVI_DUAL_LINK:
1778 case SIGNAL_TYPE_HDMI_TYPE_A:
1779 enable_link_hdmi(pipe_ctx);
1780 status = DC_OK;
1781 break;
1782 case SIGNAL_TYPE_VIRTUAL:
1783 status = DC_OK;
1784 break;
1785 default:
1786 break;
1787 }
1788
afaacef4 1789 if (pipe_ctx->stream_res.audio && status == DC_OK) {
4562236b 1790 /* notify audio driver for audio modes of monitor */
afaacef4 1791 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
4562236b
HW		 1792
1793 /* un-mute audio */
1794 /* TODO: audio should be per stream rather than per link */
8e9c4c8c
HW		 1795 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1796 pipe_ctx->stream_res.stream_enc, false);
4562236b
HW		 1797 }
1798
1799 return status;
1800}
1801
d0778ebf 1802static void disable_link(struct dc_link *link, enum signal_type signal)
4562236b
HW		 1803{
1804 /*
1805 * TODO: implement call for dp_set_hw_test_pattern
1806 * it is needed for compliance testing
1807 */
1808
1809 /* here we need to specify that encoder output settings
1810 * need to be calculated as for the set mode,
1811 * it will lead to querying dynamic link capabilities
1812 * which should be done before enable output */
1813
1814 if (dc_is_dp_signal(signal)) {
1815 /* SST DP, eDP */
1816 if (dc_is_dp_sst_signal(signal))
1817 dp_disable_link_phy(link, signal);
1818 else
1819 dp_disable_link_phy_mst(link, signal);
1820 } else
069d418f 1821 link->link_enc->funcs->disable_output(link->link_enc, signal);
4562236b
HW		 1822}
1823
73da927b 1824static bool dp_active_dongle_validate_timing(
6bffebc9
EY		 1825 const struct dc_crtc_timing *timing,
1826 const struct dc_dongle_caps *dongle_caps)
1827{
1828 unsigned int required_pix_clk = timing->pix_clk_khz;
1829
1830 if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
1831 dongle_caps->extendedCapValid == false)
1832 return true;
1833
1834 /* Check Pixel Encoding */
1835 switch (timing->pixel_encoding) {
1836 case PIXEL_ENCODING_RGB:
1837 case PIXEL_ENCODING_YCBCR444:
1838 break;
1839 case PIXEL_ENCODING_YCBCR422:
1840 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
1841 return false;
1842 break;
1843 case PIXEL_ENCODING_YCBCR420:
1844 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
1845 return false;
1846 break;
1847 default:
1848 /* Invalid Pixel Encoding*/
1849 return false;
1850 }
1851
1852
1853 /* Check Color Depth and Pixel Clock */
1854 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1855 required_pix_clk /= 2;
73da927b
EY		 1856 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1857 required_pix_clk = required_pix_clk * 2 / 3;
6bffebc9
EY		 1858
1859 switch (timing->display_color_depth) {
1860 case COLOR_DEPTH_666:
1861 case COLOR_DEPTH_888:
1862 /*888 and 666 should always be supported*/
1863 break;
1864 case COLOR_DEPTH_101010:
1865 if (dongle_caps->dp_hdmi_max_bpc < 10)
1866 return false;
1867 required_pix_clk = required_pix_clk * 10 / 8;
1868 break;
1869 case COLOR_DEPTH_121212:
1870 if (dongle_caps->dp_hdmi_max_bpc < 12)
1871 return false;
1872 required_pix_clk = required_pix_clk * 12 / 8;
1873 break;
1874
1875 case COLOR_DEPTH_141414:
1876 case COLOR_DEPTH_161616:
1877 default:
1878 /* These color depths are currently not supported */
1879 return false;
1880 }
1881
1882 if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
1883 return false;
1884
1885 return true;
1886}
1887
4562236b 1888enum dc_status dc_link_validate_mode_timing(
0971c40e 1889 const struct dc_stream_state *stream,
d0778ebf 1890 struct dc_link *link,
4562236b
HW		 1891 const struct dc_crtc_timing *timing)
1892{
b73a22d3 1893 uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
7d8d90d8 1894 struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps;
4562236b
HW		 1895
1896 /* A hack to avoid failing any modes for EDID override feature on
1897 * topology change such as lower quality cable for DP or different dongle
1898 */
d0778ebf 1899 if (link->remote_sinks[0])
4562236b
HW		 1900 return DC_OK;
1901
6bffebc9 1902 /* Passive Dongle */
4562236b 1903 if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
6bffebc9
EY		 1904 return DC_EXCEED_DONGLE_CAP;
1905
1906 /* Active Dongle*/
1907 if (!dp_active_dongle_validate_timing(timing, dongle_caps))
1908 return DC_EXCEED_DONGLE_CAP;
4562236b
HW		 1909
1910 switch (stream->signal) {
1911 case SIGNAL_TYPE_EDP:
1912 case SIGNAL_TYPE_DISPLAY_PORT:
1913 if (!dp_validate_mode_timing(
1914 link,
1915 timing))
1916 return DC_NO_DP_LINK_BANDWIDTH;
1917 break;
1918
1919 default:
1920 break;
1921 }
1922
1923 return DC_OK;
1924}
1925
1926
d0778ebf 1927bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
0971c40e 1928 uint32_t frame_ramp, const struct dc_stream_state *stream)
4562236b 1929{
fb3466a4 1930 struct dc *core_dc = link->ctx->dc;
6728b30c 1931 struct abm *abm = core_dc->res_pool->abm;
23bfb331 1932 struct dmcu *dmcu = core_dc->res_pool->dmcu;
4562236b 1933 unsigned int controller_id = 0;
23bfb331 1934 bool use_smooth_brightness = true;
4562236b 1935 int i;
4562236b 1936
23bfb331
AK		 1937 if ((dmcu == NULL) ||
1938 (abm == NULL) ||
1939 (abm->funcs->set_backlight_level == NULL))
6728b30c 1940 return false;
4562236b 1941
23bfb331
AK		 1942 use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
1943
6728b30c
AK		 1944 dm_logger_write(link->ctx->logger, LOG_BACKLIGHT,
1945 "New Backlight level: %d (0x%X)\n", level, level);
4562236b 1946
d0778ebf 1947 if (dc_is_embedded_signal(link->connector_signal)) {
6728b30c 1948 if (stream != NULL) {
6728b30c 1949 for (i = 0; i < MAX_PIPES; i++) {
608ac7bb 1950 if (core_dc->current_state->res_ctx.
6728b30c 1951 pipe_ctx[i].stream
4fa086b9 1952 == stream)
6728b30c
AK		 1953 /* DMCU -1 for all controller id values,
1954 * therefore +1 here
1955 */
1956 controller_id =
608ac7bb 1957 core_dc->current_state->
6b670fa9 1958 res_ctx.pipe_ctx[i].stream_res.tg->inst +
6728b30c
AK		 1959 1;
1960 }
4562236b 1961 }
6728b30c
AK		 1962 abm->funcs->set_backlight_level(
1963 abm,
1964 level,
1965 frame_ramp,
23bfb331
AK		 1966 controller_id,
1967 use_smooth_brightness);
4562236b 1968 }
4562236b
HW		 1969
1970 return true;
1971}
1972
c7299705 1973bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
4562236b 1974{
fb3466a4 1975 struct dc *core_dc = link->ctx->dc;
3548f073
AZ		 1976 struct dmcu *dmcu = core_dc->res_pool->dmcu;
1977
94267b3d 1978 if (dmcu != NULL && link->psr_enabled)
c7299705 1979 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
4562236b 1980
4562236b
HW		 1981 return true;
1982}
1983
d0778ebf 1984const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
4562236b 1985{
4562236b
HW		 1986 return &link->link_status;
1987}
1988
d0778ebf 1989void core_link_resume(struct dc_link *link)
4562236b 1990{
d0778ebf 1991 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
4562236b
HW		 1992 program_hpd_filter(link);
1993}
1994
0971c40e 1995static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
4562236b
HW		 1996{
1997 struct dc_link_settings *link_settings =
d0778ebf 1998 &stream->sink->link->cur_link_settings;
4562236b
HW		 1999 uint32_t link_rate_in_mbps =
2000 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2001 struct fixed31_32 mbps = dal_fixed31_32_from_int(
2002 link_rate_in_mbps * link_settings->lane_count);
2003
2004 return dal_fixed31_32_div_int(mbps, 54);
2005}
2006
2007static int get_color_depth(enum dc_color_depth color_depth)
2008{
2009 switch (color_depth) {
2010 case COLOR_DEPTH_666: return 6;
2011 case COLOR_DEPTH_888: return 8;
2012 case COLOR_DEPTH_101010: return 10;
2013 case COLOR_DEPTH_121212: return 12;
2014 case COLOR_DEPTH_141414: return 14;
2015 case COLOR_DEPTH_161616: return 16;
2016 default: return 0;
2017 }
2018}
2019
2020static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2021{
2022 uint32_t bpc;
2023 uint64_t kbps;
2024 struct fixed31_32 peak_kbps;
2025 uint32_t numerator;
2026 uint32_t denominator;
2027
10688217
HW		 2028 bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2029 kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
4562236b
HW		 2030
2031 /*
2032 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2033 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2034 * common multiplier to render an integer PBN for all link rate/lane
2035 * counts combinations
2036 * calculate
2037 * peak_kbps *= (1006/1000)
2038 * peak_kbps *= (64/54)
2039 * peak_kbps *= 8 convert to bytes
2040 */
2041
2042 numerator = 64 * PEAK_FACTOR_X1000;
2043 denominator = 54 * 8 * 1000 * 1000;
2044 kbps *= numerator;
2045 peak_kbps = dal_fixed31_32_from_fraction(kbps, denominator);
2046
2047 return peak_kbps;
2048}
2049
2050static void update_mst_stream_alloc_table(
d0778ebf 2051 struct dc_link *link,
4562236b
HW		 2052 struct stream_encoder *stream_enc,
2053 const struct dp_mst_stream_allocation_table *proposed_table)
2054{
2055 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2056 { 0 } };
2057 struct link_mst_stream_allocation *dc_alloc;
2058
2059 int i;
2060 int j;
2061
2062 /* if DRM proposed_table has more than one new payload */
2063 ASSERT(proposed_table->stream_count -
2064 link->mst_stream_alloc_table.stream_count < 2);
2065
d0778ebf 2066 /* copy proposed_table to link, add stream encoder */
4562236b
HW		 2067 for (i = 0; i < proposed_table->stream_count; i++) {
2068
2069 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2070 dc_alloc =
2071 &link->mst_stream_alloc_table.stream_allocations[j];
2072
2073 if (dc_alloc->vcp_id ==
2074 proposed_table->stream_allocations[i].vcp_id) {
2075
2076 work_table[i] = *dc_alloc;
2077 break; /* exit j loop */
2078 }
2079 }
2080
2081 /* new vcp_id */
2082 if (j == link->mst_stream_alloc_table.stream_count) {
2083 work_table[i].vcp_id =
2084 proposed_table->stream_allocations[i].vcp_id;
2085 work_table[i].slot_count =
2086 proposed_table->stream_allocations[i].slot_count;
2087 work_table[i].stream_enc = stream_enc;
2088 }
2089 }
2090
2091 /* update link->mst_stream_alloc_table with work_table */
2092 link->mst_stream_alloc_table.stream_count =
2093 proposed_table->stream_count;
2094 for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2095 link->mst_stream_alloc_table.stream_allocations[i] =
2096 work_table[i];
2097}
2098
2099/* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2100 * because stream_encoder is not exposed to dm
2101 */
2102static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2103{
0971c40e 2104 struct dc_stream_state *stream = pipe_ctx->stream;
d0778ebf 2105 struct dc_link *link = stream->sink->link;
4562236b 2106 struct link_encoder *link_encoder = link->link_enc;
8e9c4c8c 2107 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
4562236b
HW		 2108 struct dp_mst_stream_allocation_table proposed_table = {0};
2109 struct fixed31_32 avg_time_slots_per_mtp;
2110 struct fixed31_32 pbn;
2111 struct fixed31_32 pbn_per_slot;
2112 uint8_t i;
2113
2114 /* enable_link_dp_mst already check link->enabled_stream_count
2115 * and stream is in link->stream[]. This is called during set mode,
2116 * stream_enc is available.
2117 */
2118
2119 /* get calculate VC payload for stream: stream_alloc */
2120 if (dm_helpers_dp_mst_write_payload_allocation_table(
2121 stream->ctx,
4fa086b9 2122 stream,
4562236b
HW		 2123 &proposed_table,
2124 true)) {
2125 update_mst_stream_alloc_table(
8e9c4c8c 2126 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
4562236b
HW		 2127 }
2128 else
2129 dm_logger_write(link->ctx->logger, LOG_WARNING,
2130 "Failed to update"
2131 "MST allocation table for"
2132 "pipe idx:%d\n",
2133 pipe_ctx->pipe_idx);
2134
2135 dm_logger_write(link->ctx->logger, LOG_MST,
2136 "%s "
2137 "stream_count: %d: \n ",
2138 __func__,
2139 link->mst_stream_alloc_table.stream_count);
2140
2141 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2142 dm_logger_write(link->ctx->logger, LOG_MST,
2143 "stream_enc[%d]: 0x%x "
2144 "stream[%d].vcp_id: %d "
2145 "stream[%d].slot_count: %d\n",
2146 i,
2147 link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2148 i,
2149 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2150 i,
2151 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2152 }
2153
2154 ASSERT(proposed_table.stream_count > 0);
2155
2156 /* program DP source TX for payload */
2157 link_encoder->funcs->update_mst_stream_allocation_table(
2158 link_encoder,
2159 &link->mst_stream_alloc_table);
2160
2161 /* send down message */
2162 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2163 stream->ctx,
4fa086b9 2164 stream);
4562236b
HW		 2165
2166 dm_helpers_dp_mst_send_payload_allocation(
2167 stream->ctx,
4fa086b9 2168 stream,
4562236b
HW		 2169 true);
2170
2171 /* slot X.Y for only current stream */
2172 pbn_per_slot = get_pbn_per_slot(stream);
2173 pbn = get_pbn_from_timing(pipe_ctx);
2174 avg_time_slots_per_mtp = dal_fixed31_32_div(pbn, pbn_per_slot);
2175
2176 stream_encoder->funcs->set_mst_bandwidth(
2177 stream_encoder,
2178 avg_time_slots_per_mtp);
2179
2180 return DC_OK;
2181
2182}
2183
2184static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2185{
0971c40e 2186 struct dc_stream_state *stream = pipe_ctx->stream;
d0778ebf 2187 struct dc_link *link = stream->sink->link;
4562236b 2188 struct link_encoder *link_encoder = link->link_enc;
8e9c4c8c 2189 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
4562236b
HW		 2190 struct dp_mst_stream_allocation_table proposed_table = {0};
2191 struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
2192 uint8_t i;
d0778ebf 2193 bool mst_mode = (link->type == dc_connection_mst_branch);
4562236b
HW		 2194
2195 /* deallocate_mst_payload is called before disable link. When mode or
2196 * disable/enable monitor, new stream is created which is not in link
2197 * stream[] yet. For this, payload is not allocated yet, so de-alloc
2198 * should not done. For new mode set, map_resources will get engine
2199 * for new stream, so stream_enc->id should be validated until here.
2200 */
2201
2202 /* slot X.Y */
2203 stream_encoder->funcs->set_mst_bandwidth(
2204 stream_encoder,
2205 avg_time_slots_per_mtp);
2206
2207 /* TODO: which component is responsible for remove payload table? */
2208 if (mst_mode) {
2209 if (dm_helpers_dp_mst_write_payload_allocation_table(
2210 stream->ctx,
4fa086b9 2211 stream,
4562236b
HW		 2212 &proposed_table,
2213 false)) {
2214
2215 update_mst_stream_alloc_table(
8e9c4c8c 2216 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
4562236b
HW		 2217 }
2218 else {
2219 dm_logger_write(link->ctx->logger, LOG_WARNING,
2220 "Failed to update"
2221 "MST allocation table for"
2222 "pipe idx:%d\n",
2223 pipe_ctx->pipe_idx);
2224 }
2225 }
2226
2227 dm_logger_write(link->ctx->logger, LOG_MST,
2228 "%s"
2229 "stream_count: %d: ",
2230 __func__,
2231 link->mst_stream_alloc_table.stream_count);
2232
2233 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2234 dm_logger_write(link->ctx->logger, LOG_MST,
2235 "stream_enc[%d]: 0x%x "
2236 "stream[%d].vcp_id: %d "
2237 "stream[%d].slot_count: %d\n",
2238 i,
2239 link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2240 i,
2241 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2242 i,
2243 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2244 }
2245
2246 link_encoder->funcs->update_mst_stream_allocation_table(
2247 link_encoder,
2248 &link->mst_stream_alloc_table);
2249
2250 if (mst_mode) {
2251 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2252 stream->ctx,
4fa086b9 2253 stream);
4562236b
HW		 2254
2255 dm_helpers_dp_mst_send_payload_allocation(
2256 stream->ctx,
4fa086b9 2257 stream,
4562236b
HW		 2258 false);
2259 }
2260
2261 return DC_OK;
2262}
2263
ab8db3e1
AG		 2264void core_link_enable_stream(
2265 struct dc_state *state,
2266 struct pipe_ctx *pipe_ctx)
4562236b 2267{
fb3466a4 2268 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
4562236b 2269
ab8db3e1 2270 enum dc_status status = enable_link(state, pipe_ctx);
c0ba5ec7
KC		 2271
2272 if (status != DC_OK) {
2273 dm_logger_write(pipe_ctx->stream->ctx->logger,
2274 LOG_WARNING, "enabling link %u failed: %d\n",
d0778ebf 2275 pipe_ctx->stream->sink->link->link_index,
c0ba5ec7
KC		 2276 status);
2277
2278 /* Abort stream enable *unless* the failure was due to
2279 * DP link training - some DP monitors will recover and
00f713c6
EY		 2280 * show the stream anyway. But MST displays can't proceed
2281 * without link training.
c0ba5ec7 2282 */
00f713c6
EY		 2283 if (status != DC_FAIL_DP_LINK_TRAINING ||
2284 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
c0ba5ec7
KC		 2285 BREAK_TO_DEBUGGER();
2286 return;
2287 }
4562236b
HW		 2288 }
2289
71021265 2290 /* turn off otg test pattern if enable */
6b670fa9 2291 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
71021265
HW		 2292 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2293 COLOR_DEPTH_UNDEFINED);
2294
4562236b
HW		 2295 core_dc->hwss.enable_stream(pipe_ctx);
2296
2297 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2298 allocate_mst_payload(pipe_ctx);
d050f8ed
HW		 2299
2300 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2301 core_dc->hwss.unblank_stream(pipe_ctx,
2302 &pipe_ctx->stream->sink->link->cur_link_settings);
4562236b
HW		 2303}
2304
4176664b 2305void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
4562236b 2306{
fb3466a4 2307 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
4562236b
HW		 2308
2309 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2310 deallocate_mst_payload(pipe_ctx);
2311
904623ee
YS		 2312 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
2313 core_dc->hwss.edp_backlight_control(pipe_ctx->stream->sink->link, false);
2314
4176664b 2315 core_dc->hwss.disable_stream(pipe_ctx, option);
4562236b
HW		 2316
2317 disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
2318}
2319
15e17335
CL		 2320void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2321{
fb3466a4 2322 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
15e17335
CL		 2323
2324 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2325 return;
2326
2327 core_dc->hwss.set_avmute(pipe_ctx, enable);
2328}
2329
Linux 6.x block layer and io_uring tree(s)