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drm/amd/display: Fix 128b132b link loss handling
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / clk_mgr / dcn32 / dcn32_clk_mgr.c
CommitLineData
265280b9
AP		 1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dccg.h"
27#include "clk_mgr_internal.h"
28
29#include "dcn32/dcn32_clk_mgr_smu_msg.h"
30#include "dcn20/dcn20_clk_mgr.h"
31#include "dce100/dce_clk_mgr.h"
405bb9ee 32#include "dcn31/dcn31_clk_mgr.h"
265280b9
AP		 33#include "reg_helper.h"
34#include "core_types.h"
35#include "dm_helpers.h"
d5a43956 36#include "link.h"
265280b9
AP		 37
38#include "atomfirmware.h"
39#include "smu13_driver_if.h"
40
41#include "dcn/dcn_3_2_0_offset.h"
42#include "dcn/dcn_3_2_0_sh_mask.h"
43
44#include "dcn32/dcn32_clk_mgr.h"
041a1109 45#include "dml/dcn32/dcn32_fpu.h"
265280b9
AP		 46
47#define DCN_BASE__INST0_SEG1 0x000000C0
48
49#define mmCLK1_CLK_PLL_REQ 0x16E37
50#define mmCLK1_CLK0_DFS_CNTL 0x16E69
51#define mmCLK1_CLK1_DFS_CNTL 0x16E6C
52#define mmCLK1_CLK2_DFS_CNTL 0x16E6F
53#define mmCLK1_CLK3_DFS_CNTL 0x16E72
54#define mmCLK1_CLK4_DFS_CNTL 0x16E75
55
56#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
57#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
58#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
59#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
60#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
61#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
62
63#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
64#define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E64
65#define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E67
66#define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6A
67#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E6D
68#define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E70
69
70#define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffL
71#define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000L
72#define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000L
73#define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
74#define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
75#define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
76
77#undef FN
78#define FN(reg_name, field_name) \
79 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
80
81#define REG(reg) \
82 (clk_mgr->regs->reg)
83
84#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
85
86#define BASE(seg) BASE_INNER(seg)
87
88#define SR(reg_name)\
89 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
90 reg ## reg_name
91
92#define CLK_SR_DCN32(reg_name)\
93 .reg_name = mm ## reg_name
94
95static const struct clk_mgr_registers clk_mgr_regs_dcn32 = {
96 CLK_REG_LIST_DCN32()
97};
98
99static const struct clk_mgr_shift clk_mgr_shift_dcn32 = {
100 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
101};
102
103static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {
104 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
105};
106
107
108#define CLK_SR_DCN321(reg_name, block, inst)\
109 .reg_name = mm ## block ## _ ## reg_name
110
111static const struct clk_mgr_registers clk_mgr_regs_dcn321 = {
112 CLK_REG_LIST_DCN321()
113};
114
115static const struct clk_mgr_shift clk_mgr_shift_dcn321 = {
116 CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT)
117};
118
119static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
120 CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)
121};
122
123
124/* Query SMU for all clock states for a particular clock */
125static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
126 unsigned int *num_levels)
127{
128 unsigned int i;
129 char *entry_i = (char *)entry_0;
130
131 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
132
133 if (ret & (1 << 31))
134 /* fine-grained, only min and max */
135 *num_levels = 2;
136 else
137 /* discrete, a number of fixed states */
138 /* will set num_levels to 0 on failure */
139 *num_levels = ret & 0xFF;
140
141 /* if the initial message failed, num_levels will be 0 */
142 for (i = 0; i < *num_levels; i++) {
143 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
144 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
145 }
146}
147
148static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
149{
041a1109
RS		 150 DC_FP_START();
151 dcn32_build_wm_range_table_fpu(clk_mgr);
152 DC_FP_END();
265280b9
AP		 153}
154
155void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
156{
157 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
158 unsigned int num_levels;
d6170e41 159 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
f7f69740 160 unsigned int i;
265280b9
AP		 161
162 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
163 clk_mgr_base->clks.p_state_change_support = true;
164 clk_mgr_base->clks.prev_p_state_change_support = true;
165 clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
166 clk_mgr->smu_present = false;
3141d6cb 167 clk_mgr->dpm_present = false;
265280b9
AP		 168
169 if (!clk_mgr_base->bw_params)
170 return;
171
172 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
173 clk_mgr->smu_present = true;
174
175 if (!clk_mgr->smu_present)
176 return;
177
178 dcn30_smu_check_driver_if_version(clk_mgr);
179 dcn30_smu_check_msg_header_version(clk_mgr);
180
181 /* DCFCLK */
182 dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
d6170e41 184 &num_entries_per_clk->num_dcfclk_levels);
3b718dca 185 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
265280b9
AP		 186
187 /* SOCCLK */
188 dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
189 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
d6170e41 190 &num_entries_per_clk->num_socclk_levels);
3b718dca 191 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
d6170e41 192
265280b9 193 /* DTBCLK */
3b718dca 194 if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
405bb9ee
AL		 195 dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
196 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
d6170e41 197 &num_entries_per_clk->num_dtbclk_levels);
3b718dca
AZ		 198 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz =
199 dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
200 }
265280b9
AP		 201
202 /* DISPCLK */
203 dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
204 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
d6170e41
DV		 205 &num_entries_per_clk->num_dispclk_levels);
206 num_levels = num_entries_per_clk->num_dispclk_levels;
3b718dca
AZ		 207 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
208 //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x
209 if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950)
210 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950;
3141d6cb 211
d6170e41
DV		 212 if (num_entries_per_clk->num_dcfclk_levels &&
213 num_entries_per_clk->num_dtbclk_levels &&
214 num_entries_per_clk->num_dispclk_levels)
3141d6cb 215 clk_mgr->dpm_present = true;
265280b9 216
074efb5c 217 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
074efb5c
RS		 218 for (i = 0; i < num_levels; i++)
219 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
220 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
221 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
222 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
223 }
f7f69740
JL		 224 for (i = 0; i < num_levels; i++)
225 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
226 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
074efb5c
RS		 227
228 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
074efb5c
RS		 229 for (i = 0; i < num_levels; i++)
230 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
231 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
232 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
233 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
234 }
265280b9
AP		 235
236 /* Get UCLK, update bounding box */
237 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
238
c5da61cf 239 DC_FP_START();
265280b9
AP		 240 /* WM range table */
241 dcn32_build_wm_range_table(clk_mgr);
c5da61cf 242 DC_FP_END();
265280b9
AP		 243}
244
128c1ca0
AL		 245static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
246 struct dc_state *context,
247 int ref_dtbclk_khz)
248{
249 struct dccg *dccg = clk_mgr->dccg;
250 uint32_t tg_mask = 0;
251 int i;
252
253 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
254 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
255 struct dtbclk_dto_params dto_params = {0};
256
257 /* use mask to program DTO once per tg */
258 if (pipe_ctx->stream_res.tg &&
259 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
260 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
261
262 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
263 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
264
265 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
266 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
267 }
268 }
269}
270
04e6931a
AL		 271/* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
272 * update DPPCLK to be the exact frequency that will be set after the DPPCLK
273 * divider is updated. This will prevent rounding issues that could cause DPP
274 * refclk and DPP DTO to not match up.
275 */
276static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
277{
278 int dpp_divider = 0;
279 int disp_divider = 0;
280
a3a88587
GS		 281 if (new_clocks->dppclk_khz) {
282 dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
283 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
284 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
285 }
286 if (new_clocks->dispclk_khz > 0) {
287 disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
288 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
289 new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
290 }
04e6931a
AL		 291}
292
cd487b6d
AL		 293void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
294 struct dc_state *context, bool safe_to_lower)
295{
296 int i;
297
298 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
299 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
300 int dpp_inst, dppclk_khz, prev_dppclk_khz;
301
302 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
303
304 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
305 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
306 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
307 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
308 * In this case just continue in loop
309 */
310 continue;
311 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
312 /* The software state is not valid if dpp resource is NULL and
313 * dppclk_khz > 0.
314 */
315 ASSERT(false);
316 continue;
317 }
318
319 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
320
321 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
322 clk_mgr->dccg->funcs->update_dpp_dto(
323 clk_mgr->dccg, dpp_inst, dppclk_khz);
324 }
325}
326
fc41c734
DV		 327static void dcn32_update_clocks_update_dentist(
328 struct clk_mgr_internal *clk_mgr,
7bd571b2 329 struct dc_state *context)
fc41c734
DV		 330{
331 uint32_t new_disp_divider = 0;
fc41c734
DV		 332 uint32_t new_dispclk_wdivider = 0;
333 uint32_t old_dispclk_wdivider = 0;
334 uint32_t i;
7bd571b2
AL		 335 uint32_t dentist_dispclk_wdivider_readback = 0;
336 struct dc *dc = clk_mgr->base.ctx->dc;
fc41c734 337
7bd571b2 338 if (clk_mgr->base.clks.dispclk_khz == 0)
fc41c734
DV		 339 return;
340
341 new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
342 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
fc41c734
DV		 343
344 new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);
7bd571b2
AL		 345 REG_GET(DENTIST_DISPCLK_CNTL,
346 DENTIST_DISPCLK_WDIVIDER, &old_dispclk_wdivider);
fc41c734
DV		 347
348 /* When changing divider to or from 127, some extra programming is required to prevent corruption */
349 if (old_dispclk_wdivider == 127 && new_dispclk_wdivider != 127) {
350 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
351 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
352 uint32_t fifo_level;
353 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
354 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
355 int32_t N;
356 int32_t j;
357
358 if (!pipe_ctx->stream)
359 continue;
360 /* Virtual encoders don't have this function */
361 if (!stream_enc->funcs->get_fifo_cal_average_level)
362 continue;
363 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
364 stream_enc);
365 N = fifo_level / 4;
366 dccg->funcs->set_fifo_errdet_ovr_en(
367 dccg,
368 true);
369 for (j = 0; j < N - 4; j++)
370 dccg->funcs->otg_drop_pixel(
371 dccg,
372 pipe_ctx->stream_res.tg->inst);
373 dccg->funcs->set_fifo_errdet_ovr_en(
374 dccg,
375 false);
376 }
377 } else if (new_dispclk_wdivider == 127 && old_dispclk_wdivider != 127) {
378 /* request clock with 126 divider first */
379 uint32_t temp_disp_divider = dentist_get_divider_from_did(126);
380 uint32_t temp_dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / temp_disp_divider;
381
382 if (clk_mgr->smu_present)
383 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(temp_dispclk_khz));
384
7bd571b2
AL		 385 if (dc->debug.override_dispclk_programming) {
386 REG_GET(DENTIST_DISPCLK_CNTL,
387 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
388
389 if (dentist_dispclk_wdivider_readback != 126) {
390 REG_UPDATE(DENTIST_DISPCLK_CNTL,
391 DENTIST_DISPCLK_WDIVIDER, 126);
392 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
393 }
394 }
395
fc41c734
DV		 396 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
397 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
398 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
399 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
400 uint32_t fifo_level;
401 int32_t N;
402 int32_t j;
403
404 if (!pipe_ctx->stream)
405 continue;
406 /* Virtual encoders don't have this function */
407 if (!stream_enc->funcs->get_fifo_cal_average_level)
408 continue;
409 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
410 stream_enc);
411 N = fifo_level / 4;
412 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
413 for (j = 0; j < 12 - N; j++)
414 dccg->funcs->otg_add_pixel(dccg,
415 pipe_ctx->stream_res.tg->inst);
416 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
417 }
418 }
419
420 /* do requested DISPCLK updates*/
421 if (clk_mgr->smu_present)
422 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr->base.clks.dispclk_khz));
7bd571b2
AL		 423
424 if (dc->debug.override_dispclk_programming) {
425 REG_GET(DENTIST_DISPCLK_CNTL,
426 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
427
428 if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) {
429 REG_UPDATE(DENTIST_DISPCLK_CNTL,
430 DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider);
431 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
432 }
433 }
434
fc41c734
DV		 435}
436
d170e938
AL		 437static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
438{
439 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
440 uint32_t dispclk_wdivider;
441 int disp_divider;
442
443 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
444 disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
445
446 /* Return DISPCLK freq in Khz */
447 if (disp_divider)
448 return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
449
450 return 0;
451}
452
453
265280b9
AP		 454static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
455 struct dc_state *context,
456 bool safe_to_lower)
457{
458 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
459 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
460 struct dc *dc = clk_mgr_base->ctx->dc;
461 int display_count;
462 bool update_dppclk = false;
463 bool update_dispclk = false;
464 bool enter_display_off = false;
465 bool dpp_clock_lowered = false;
466 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
467 bool force_reset = false;
0c9ed604 468 bool update_uclk = false, update_fclk = false;
265280b9
AP		 469 bool p_state_change_support;
470 bool fclk_p_state_change_support;
265280b9
AP		 471
472 if (clk_mgr_base->clks.dispclk_khz == 0 ||
473 (dc->debug.force_clock_mode & 0x1)) {
474 /* This is from resume or boot up, if forced_clock cfg option used,
475 * we bypass program dispclk and DPPCLK, but need set them for S3.
476 */
477 force_reset = true;
478
479 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
480
481 /* Force_clock_mode 0x1: force reset the clock even it is the same clock
482 * as long as it is in Passive level.
483 */
484 }
485 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
486
487 if (display_count == 0)
488 enter_display_off = true;
489
e127306d
JL		 490 if (clk_mgr->smu_present) {
491 if (enter_display_off == safe_to_lower)
492 dcn30_smu_set_num_of_displays(clk_mgr, display_count);
265280b9 493
c1969fba
DV		 494 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
495
c8cefb99 496 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support;
c1969fba 497
1d8355ad
AL		 498 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
499 !dc->work_arounds.clock_update_disable_mask.fclk) {
c1969fba
DV		 500 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
501
3867bbd4
DV		 502 /* To enable FCLK P-state switching, send FCLK_PSTATE_SUPPORTED message to PMFW */
503 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) {
c1969fba
DV		 504 /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
505 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
506 }
507 }
508
e127306d
JL		 509 if (dc->debug.force_min_dcfclk_mhz > 0)
510 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
511 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
265280b9 512
1d8355ad
AL		 513 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) &&
514 !dc->work_arounds.clock_update_disable_mask.dcfclk) {
e127306d 515 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
405bb9ee 516 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
e127306d 517 }
265280b9 518
1d8355ad
AL		 519 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) &&
520 !dc->work_arounds.clock_update_disable_mask.dcfclk_ds) {
e127306d
JL		 521 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
522 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
523 }
524
525 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
526 /* We don't actually care about socclk, don't notify SMU of hard min */
527 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
265280b9 528
e127306d 529 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
e127306d 530 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
265280b9 531
e127306d
JL		 532 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
533 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
534 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
535 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
536 }
265280b9 537
c8cefb99 538 p_state_change_support = new_clocks->p_state_change_support;
1d8355ad
AL		 539 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support) &&
540 !dc->work_arounds.clock_update_disable_mask.uclk) {
e127306d 541 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
265280b9 542
e127306d
JL		 543 /* to disable P-State switching, set UCLK min = max */
544 if (!clk_mgr_base->clks.p_state_change_support)
405bb9ee 545 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
d6170e41 546 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
e127306d 547 }
265280b9 548
c1969fba
DV		 549 /* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
550 if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
551 update_fclk = true;
552 }
265280b9 553
1d8355ad
AL		 554 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && update_fclk &&
555 !dc->work_arounds.clock_update_disable_mask.fclk) {
c1969fba
DV		 556 /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
557 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
265280b9 558 }
265280b9 559
e127306d 560 /* Always update saved value, even if new value not set due to P-State switching unsupported */
1d8355ad
AL		 561 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz) &&
562 !dc->work_arounds.clock_update_disable_mask.uclk) {
e127306d
JL		 563 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
564 update_uclk = true;
565 }
566
567 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
568 if (clk_mgr_base->clks.p_state_change_support &&
1d8355ad
AL		 569 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&
570 !dc->work_arounds.clock_update_disable_mask.uclk)
405bb9ee 571 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
265280b9 572
e127306d
JL		 573 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
574 clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
575 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
576 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
577 }
265280b9
AP		 578 }
579
04e6931a 580 dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks);
265280b9
AP		 581 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
582 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
583 dpp_clock_lowered = true;
584
585 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
e127306d 586
04e6931a 587 if (clk_mgr->smu_present && !dpp_clock_lowered)
405bb9ee 588 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
e127306d 589
265280b9
AP		 590 update_dppclk = true;
591 }
592
593 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
594 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
e127306d 595
265280b9
AP		 596 update_dispclk = true;
597 }
598
405bb9ee 599 if (!new_clocks->dtbclk_en) {
f6015da7 600 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
405bb9ee
AL		 601 }
602
603 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
604 if (!dc->debug.disable_dtb_ref_clk_switch &&
605 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
606 /* DCCG requires KHz precision for DTBCLK */
607 clk_mgr_base->clks.ref_dtbclk_khz =
608 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
128c1ca0 609 dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
405bb9ee
AL		 610 }
611
265280b9
AP		 612 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
613 if (dpp_clock_lowered) {
614 /* if clock is being lowered, increase DTO before lowering refclk */
cd487b6d 615 dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
7bd571b2 616 dcn32_update_clocks_update_dentist(clk_mgr, context);
04e6931a
AL		 617 if (clk_mgr->smu_present)
618 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
265280b9
AP		 619 } else {
620 /* if clock is being raised, increase refclk before lowering DTO */
621 if (update_dppclk || update_dispclk)
7bd571b2 622 dcn32_update_clocks_update_dentist(clk_mgr, context);
265280b9
AP		 623 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
624 * that we do not lower dto when it is not safe to lower. We do not need to
625 * compare the current and new dppclk before calling this function.
626 */
cd487b6d 627 dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
265280b9
AP		 628 }
629 }
630
631 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
632 /*update dmcu for wait_loop count*/
633 dmcu->funcs->set_psr_wait_loop(dmcu,
634 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
635}
636
3e838f7c
RS		 637static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
638{
639 struct fixed31_32 pll_req;
640 uint32_t pll_req_reg = 0;
641
642 /* get FbMult value */
643 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev))
644 pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
645 else
646 pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);
647
648 /* set up a fixed-point number
649 * this works because the int part is on the right edge of the register
650 * and the frac part is on the left edge
651 */
10a9035c 652 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
3e838f7c
RS		 653 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
654
655 /* multiply by REFCLK period */
656 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
657
658 return dc_fixpt_floor(pll_req);
659}
660
661static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
662 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
663{
664 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
665 uint32_t dprefclk_did = 0;
666 uint32_t dcfclk_did = 0;
667 uint32_t dtbclk_did = 0;
668 uint32_t dispclk_did = 0;
669 uint32_t dppclk_did = 0;
670 uint32_t target_div = 0;
671
672 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
673 /* DFS Slice 0 is used for DISPCLK */
674 dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
675 /* DFS Slice 1 is used for DPPCLK */
676 dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
677 /* DFS Slice 2 is used for DPREFCLK */
678 dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
679 /* DFS Slice 3 is used for DCFCLK */
680 dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
681 /* DFS Slice 4 is used for DTBCLK */
682 dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
683 } else {
684 /* DFS Slice 0 is used for DISPCLK */
685 dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);
686 /* DFS Slice 1 is used for DPPCLK */
687 dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);
688 /* DFS Slice 2 is used for DPREFCLK */
689 dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);
690 /* DFS Slice 3 is used for DCFCLK */
691 dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);
692 /* DFS Slice 4 is used for DTBCLK */
693 dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);
694 }
695
696 /* Convert DISPCLK DFS Slice DID to divider*/
697 target_div = dentist_get_divider_from_did(dispclk_did);
698 //Get dispclk in khz
699 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
700 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
701
702 /* Convert DISPCLK DFS Slice DID to divider*/
703 target_div = dentist_get_divider_from_did(dppclk_did);
704 //Get dppclk in khz
705 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
706 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
707
708 /* Convert DPREFCLK DFS Slice DID to divider*/
709 target_div = dentist_get_divider_from_did(dprefclk_did);
710 //Get dprefclk in khz
711 regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
712 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
713
714 /* Convert DCFCLK DFS Slice DID to divider*/
715 target_div = dentist_get_divider_from_did(dcfclk_did);
716 //Get dcfclk in khz
717 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
718 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
719
720 /* Convert DTBCLK DFS Slice DID to divider*/
721 target_div = dentist_get_divider_from_did(dtbclk_did);
722 //Get dtbclk in khz
723 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
724 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
725}
726
b94b02d7 727static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
265280b9
AP		 728{
729 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
730 int ss_info_num = bp->funcs->get_ss_entry_number(
731 bp, AS_SIGNAL_TYPE_GPU_PLL);
732
733 if (ss_info_num) {
734 struct spread_spectrum_info info = { { 0 } };
735 enum bp_result result = bp->funcs->get_spread_spectrum_info(
736 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
737
738 /* SSInfo.spreadSpectrumPercentage !=0 would be sign
739 * that SS is enabled
740 */
741 if (result == BP_RESULT_OK &&
742 info.spread_spectrum_percentage != 0) {
743 clk_mgr->ss_on_dprefclk = true;
744 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
745
746 if (info.type.CENTER_MODE == 0) {
747 /* Currently for DP Reference clock we
748 * need only SS percentage for
749 * downspread
750 */
751 clk_mgr->dprefclk_ss_percentage =
752 info.spread_spectrum_percentage;
753 }
754 }
755 }
756}
757static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
758{
e06c5f59 759 unsigned int i;
265280b9
AP		 760 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
761 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
762
763 if (!clk_mgr->smu_present)
764 return;
765
766 if (!table)
767 return;
768
769 memset(table, 0, sizeof(*table));
770
e06c5f59
AL		 771 /* collect valid ranges, place in pmfw table */
772 for (i = 0; i < WM_SET_COUNT; i++)
773 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
774 table->Watermarks.WatermarkRow[i].WmSetting = i;
775 table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
776 }
265280b9
AP		 777 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
778 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
779 dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
780}
781
782/* Set min memclk to minimum, either constrained by the current mode or DPM0 */
783static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
784{
785 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
786
787 if (!clk_mgr->smu_present)
788 return;
789
790 if (current_mode) {
791 if (clk_mgr_base->clks.p_state_change_support)
405bb9ee 792 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
265280b9
AP		 793 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
794 else
405bb9ee 795 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
d6170e41 796 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
265280b9 797 } else {
405bb9ee 798 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
265280b9
AP		 799 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
800 }
801}
802
803/* Set max memclk to highest DPM value */
804static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
805{
806 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
807
808 if (!clk_mgr->smu_present)
809 return;
810
811 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
d6170e41 812 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
265280b9
AP		 813}
814
815/* Get current memclk states, update bounding box */
816static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
817{
818 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
d6170e41 819 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
265280b9
AP		 820 unsigned int num_levels;
821
822 if (!clk_mgr->smu_present)
823 return;
824
d6170e41 825 /* Refresh memclk and fclk states */
265280b9
AP		 826 dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
827 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
d6170e41 828 &num_entries_per_clk->num_memclk_levels);
3b718dca 829 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
d6170e41 830
33151fb7
DV		 831 /* memclk must have at least one level */
832 num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
833
d6170e41
DV		 834 dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
835 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
836 &num_entries_per_clk->num_fclk_levels);
3b718dca 837 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
d6170e41
DV		 838
839 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
840 num_levels = num_entries_per_clk->num_memclk_levels;
841 } else {
842 num_levels = num_entries_per_clk->num_fclk_levels;
843 }
844
265280b9
AP		 845 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
846
3141d6cb
ST		 847 if (clk_mgr->dpm_present && !num_levels)
848 clk_mgr->dpm_present = false;
849
850 if (!clk_mgr->dpm_present)
851 dcn32_patch_dpm_table(clk_mgr_base->bw_params);
852
c5da61cf 853 DC_FP_START();
265280b9
AP		 854 /* Refresh bounding box */
855 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
856 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
c5da61cf 857 DC_FP_END();
265280b9
AP		 858}
859
860static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
861 struct dc_clocks *b)
862{
863 if (a->dispclk_khz != b->dispclk_khz)
864 return false;
865 else if (a->dppclk_khz != b->dppclk_khz)
866 return false;
867 else if (a->dcfclk_khz != b->dcfclk_khz)
868 return false;
869 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
870 return false;
871 else if (a->dramclk_khz != b->dramclk_khz)
872 return false;
873 else if (a->p_state_change_support != b->p_state_change_support)
874 return false;
875 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
876 return false;
877
878 return true;
879}
880
881static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
882{
883 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
884
885 if (!clk_mgr->smu_present)
886 return;
887
aeb73c60 888 dcn32_smu_set_pme_workaround(clk_mgr);
265280b9
AP		 889}
890
891static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
892{
893 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
894 return clk_mgr->smu_present;
895}
896
897
898static struct clk_mgr_funcs dcn32_funcs = {
2d7a1ef8
RS		 899 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
900 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
265280b9 901 .update_clocks = dcn32_update_clocks,
3e838f7c 902 .dump_clk_registers = dcn32_dump_clk_registers,
265280b9
AP		 903 .init_clocks = dcn32_init_clocks,
904 .notify_wm_ranges = dcn32_notify_wm_ranges,
905 .set_hard_min_memclk = dcn32_set_hard_min_memclk,
906 .set_hard_max_memclk = dcn32_set_hard_max_memclk,
907 .get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu,
908 .are_clock_states_equal = dcn32_are_clock_states_equal,
909 .enable_pme_wa = dcn32_enable_pme_wa,
910 .is_smu_present = dcn32_is_smu_present,
d170e938 911 .get_dispclk_from_dentist = dcn32_get_dispclk_from_dentist,
265280b9
AP		 912};
913
914void dcn32_clk_mgr_construct(
915 struct dc_context *ctx,
916 struct clk_mgr_internal *clk_mgr,
917 struct pp_smu_funcs *pp_smu,
918 struct dccg *dccg)
919{
d1c5c3e2
AP		 920 struct clk_log_info log_info = {0};
921
265280b9
AP		 922 clk_mgr->base.ctx = ctx;
923 clk_mgr->base.funcs = &dcn32_funcs;
924 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
925 clk_mgr->regs = &clk_mgr_regs_dcn321;
926 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;
927 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;
928 } else {
929 clk_mgr->regs = &clk_mgr_regs_dcn32;
930 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;
931 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;
932 }
933
934 clk_mgr->dccg = dccg;
935 clk_mgr->dfs_bypass_disp_clk = 0;
936
937 clk_mgr->dprefclk_ss_percentage = 0;
938 clk_mgr->dprefclk_ss_divider = 1000;
939 clk_mgr->ss_on_dprefclk = false;
940 clk_mgr->dfs_ref_freq_khz = 100000;
941
b6a93844
ST		 942 /* Changed from DCN3.2_clock_frequency doc to match
943 * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
944 * dprefclk DID divider
945 */
946 clk_mgr->base.dprefclk_khz = 716666;
405bb9ee
AL		 947 if (ctx->dc->debug.disable_dtb_ref_clk_switch) {
948 //initialize DTB ref clock value if DPM disabled
949 if (ctx->dce_version == DCN_VERSION_3_21)
950 clk_mgr->base.clks.ref_dtbclk_khz = 477800;
951 else
952 clk_mgr->base.clks.ref_dtbclk_khz = 268750;
953 }
265280b9 954
d1c5c3e2 955
265280b9 956 /* integer part is now VCO frequency in kHz */
3e838f7c
RS		 957 clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);
958
265280b9
AP		 959 /* in case we don't get a value from the register, use default */
960 if (clk_mgr->base.dentist_vco_freq_khz == 0)
961 clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
962
d1c5c3e2
AP		 963 dcn32_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
964
405bb9ee
AL		 965 if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
966 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
967 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
2267a195
DV		 968 }
969
265280b9 970 if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
b6a93844 971 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
265280b9
AP		 972 }
973 dcn32_clock_read_ss_info(clk_mgr);
974
975 clk_mgr->dfs_bypass_enabled = false;
976
977 clk_mgr->smu_present = false;
978
979 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
980
981 /* need physical address of table to give to PMFW */
982 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
983 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
984 &clk_mgr->wm_range_table_addr);
985}
986
987void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
988{
447395e1 989 kfree(clk_mgr->base.bw_params);
265280b9
AP		 990
991 if (clk_mgr->wm_range_table)
992 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
993 clk_mgr->wm_range_table);
994}
995
Linux 6.x block layer and io_uring tree(s)