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drm/amd/display: Fix naming of DSC Debugfs entry
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / clk_mgr / dcn30 / dcn30_clk_mgr.c
CommitLineData
4d55b0dd
BL		 1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dccg.h"
27#include "clk_mgr_internal.h"
28
29#include "dcn30_clk_mgr_smu_msg.h"
30#include "dcn20/dcn20_clk_mgr.h"
31#include "dce100/dce_clk_mgr.h"
32#include "reg_helper.h"
33#include "core_types.h"
34#include "dm_helpers.h"
35
36#include "atomfirmware.h"
37
38
39#include "sienna_cichlid_ip_offset.h"
40#include "dcn/dcn_3_0_0_offset.h"
41#include "dcn/dcn_3_0_0_sh_mask.h"
42
43#include "nbio/nbio_7_4_offset.h"
44
45#include "dcn/dpcs_3_0_0_offset.h"
46#include "dcn/dpcs_3_0_0_sh_mask.h"
47
48#include "mmhub/mmhub_2_0_0_offset.h"
49#include "mmhub/mmhub_2_0_0_sh_mask.h"
50/*we don't have clk folder yet*/
51#include "dcn30/dcn30_clk_mgr.h"
52
53#undef FN
54#define FN(reg_name, field_name) \
55 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
56
57#define REG(reg) \
58 (clk_mgr->regs->reg)
59
60#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
61
62#define BASE(seg) BASE_INNER(seg)
63
64#define SR(reg_name)\
65 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
66 mm ## reg_name
67
68#undef CLK_SRI
69#define CLK_SRI(reg_name, block, inst)\
70 .reg_name = mm ## block ## _ ## reg_name
71
72static const struct clk_mgr_registers clk_mgr_regs = {
73 CLK_REG_LIST_DCN3()
74};
75
76static const struct clk_mgr_shift clk_mgr_shift = {
77 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(__SHIFT)
78};
79
80static const struct clk_mgr_mask clk_mgr_mask = {
81 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(_MASK)
82};
83
84
85/* Query SMU for all clock states for a particular clock */
86static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels)
87{
88 unsigned int i;
89 char *entry_i = (char *)entry_0;
90 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
91
92 if (ret & (1 << 31))
93 /* fine-grained, only min and max */
94 *num_levels = 2;
95 else
96 /* discrete, a number of fixed states */
97 /* will set num_levels to 0 on failure */
98 *num_levels = ret & 0xFF;
99
100 /* if the initial message failed, num_levels will be 0 */
101 for (i = 0; i < *num_levels; i++) {
102 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
103 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
104 }
105}
106
107static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
108{
109 /* defaults */
110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
111 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
113 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
114
115 /* Set A - Normal - default values*/
116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
119 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;
122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
123 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
125
126 /* Set B - Performance - higher minimum clocks */
127// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
128// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
129// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
130// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
131// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
132// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = TUNED VALUE;
133// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
134// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = TUNED VALUE;
135// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
136
137 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
138 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
139 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us;
140 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
141 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
142 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
143 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0;
144 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
145 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
146 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
147
148}
149
150void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
151{
152 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
153 unsigned int num_levels;
154
155 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
156 clk_mgr_base->clks.p_state_change_support = true;
157 clk_mgr_base->clks.prev_p_state_change_support = true;
158 clk_mgr->smu_present = false;
159
160 if (!clk_mgr_base->bw_params)
161 return;
162
163 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
164 clk_mgr->smu_present = true;
165
166 if (!clk_mgr->smu_present)
167 return;
168
169 // do we fail if these fail? if so, how? do we not care to check?
170 dcn30_smu_check_driver_if_version(clk_mgr);
171 dcn30_smu_check_msg_header_version(clk_mgr);
172
173 /* DCFCLK */
174 dcn3_init_single_clock(clk_mgr, PPCLK_DCEFCLK,
175 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
176 &num_levels);
177
178 /* DTBCLK */
179 dcn3_init_single_clock(clk_mgr, PPCLK_DTBCLK,
180 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
181 &num_levels);
182
183 // DPREFCLK ???
184
185 /* DISPCLK */
186 dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK,
187 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
188 &num_levels);
189
190 /* DPPCLK */
191 dcn3_init_single_clock(clk_mgr, PPCLK_PIXCLK,
192 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
193 &num_levels);
194
195 /* PHYCLK */
196 dcn3_init_single_clock(clk_mgr, PPCLK_PHYCLK,
197 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz,
198 &num_levels);
199
200 /* Get UCLK, update bounding box */
201 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
202
203 /* WM range table */
204 dcn3_build_wm_range_table(clk_mgr);
205}
206
207static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
208{
209 /* get FbMult value */
210 struct fixed31_32 pll_req;
211 /* get FbMult value */
212 uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
213
214 /* set up a fixed-point number
215 * this works because the int part is on the right edge of the register
216 * and the frac part is on the left edge
217 */
218 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
219 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
220
221 /* multiply by REFCLK period */
222 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
223
224 return dc_fixpt_floor(pll_req);
225}
226
227static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
228 struct dc_state *context,
229 bool safe_to_lower)
230{
231 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
232 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
233 struct dc *dc = clk_mgr_base->ctx->dc;
234 int display_count;
235 bool update_dppclk = false;
236 bool update_dispclk = false;
237 bool enter_display_off = false;
238 bool dpp_clock_lowered = false;
239 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
240 bool force_reset = false;
241 bool update_uclk = false;
242
243 if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)
244 return;
245
246 if (clk_mgr_base->clks.dispclk_khz == 0 ||
247 (dc->debug.force_clock_mode & 0x1)) {
248 /* this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. */
249 force_reset = true;
250
251 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
252
253 /* force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. */
254 }
255 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
256
257 if (display_count == 0)
258 enter_display_off = true;
259
260 if (enter_display_off == safe_to_lower)
261 dcn30_smu_set_num_of_displays(clk_mgr, display_count);
262
4d55b0dd
BL		 263 if (dc->debug.force_min_dcfclk_mhz > 0)
264 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
265 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
266
267 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
268 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
269 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, clk_mgr_base->clks.dcfclk_khz / 1000);
270 }
271
272 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
273 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
274 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
275 }
276
277 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
278 /* We don't actually care about socclk, don't notify SMU of hard min */
279 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
280
281 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
282 if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
283 clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
284
285 /* to disable P-State switching, set UCLK min = max */
286 if (!clk_mgr_base->clks.p_state_change_support)
287 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
288 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
289 }
290
291 /* Always update saved value, even if new value not set due to P-State switching unsupported */
292 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
293 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
294 update_uclk = true;
295 }
296
297 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
298 if (clk_mgr_base->clks.p_state_change_support &&
299 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
300 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->clks.dramclk_khz / 1000);
301
302 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
303 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
304 dpp_clock_lowered = true;
305
306 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
307 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, clk_mgr_base->clks.dppclk_khz / 1000);
308 update_dppclk = true;
309 }
310
311 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
312 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
313 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
314 update_dispclk = true;
315 }
316
317 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
318 if (dpp_clock_lowered) {
319 /* if clock is being lowered, increase DTO before lowering refclk */
320 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
321 dcn20_update_clocks_update_dentist(clk_mgr);
322 } else {
323 /* if clock is being raised, increase refclk before lowering DTO */
324 if (update_dppclk || update_dispclk)
325 dcn20_update_clocks_update_dentist(clk_mgr);
326 /* always update dtos unless clock is lowered and not safe to lower */
327 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
328 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
329 }
330 }
331
332 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
333 /*update dmcu for wait_loop count*/
334 dmcu->funcs->set_psr_wait_loop(dmcu,
335 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
336}
337
338
339static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
340{
341 unsigned int i;
4d55b0dd 342 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
dd827a48 343 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
4d55b0dd
BL		 344
345 if (!clk_mgr->smu_present)
346 return;
347
4d55b0dd
BL		 348 if (!table)
349 // should log failure
350 return;
351
352 memset(table, 0, sizeof(*table));
353
354 /* collect valid ranges, place in pmfw table */
355 for (i = 0; i < WM_SET_COUNT; i++)
356 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
357 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk;
358 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk;
359 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk;
360 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk;
361 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i;
362 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
363 }
364
dd827a48
JA		 365 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
366 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
4d55b0dd 367 dcn30_smu_transfer_wm_table_dram_2_smu(clk_mgr);
4d55b0dd
BL		 368}
369
370/* Set min memclk to minimum, either constrained by the current mode or DPM0 */
371static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
372{
373 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
374
375 if (!clk_mgr->smu_present)
376 return;
377
378 if (current_mode)
379 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
380 clk_mgr_base->clks.dramclk_khz / 1000);
381 else
382 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
383 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
384}
385
386/* Set max memclk to highest DPM value */
387static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
388{
389 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
390
391 if (!clk_mgr->smu_present)
392 return;
393
394 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
395 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
396}
397
398/* Get current memclk states, update bounding box */
399static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
400{
401 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
402 unsigned int num_levels;
403
404 if (!clk_mgr->smu_present)
405 return;
406
407 /* Refresh memclk states */
408 dcn3_init_single_clock(clk_mgr, PPCLK_UCLK,
409 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
410 &num_levels);
411 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
412
413 /* Refresh bounding box */
414 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
415 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
416}
417
418static bool dcn3_are_clock_states_equal(struct dc_clocks *a,
419 struct dc_clocks *b)
420{
421 if (a->dispclk_khz != b->dispclk_khz)
422 return false;
423 else if (a->dppclk_khz != b->dppclk_khz)
424 return false;
425 else if (a->dcfclk_khz != b->dcfclk_khz)
426 return false;
427 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
428 return false;
4d55b0dd
BL		 429 else if (a->dramclk_khz != b->dramclk_khz)
430 return false;
431 else if (a->p_state_change_support != b->p_state_change_support)
432 return false;
433
434 return true;
435}
436
437static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base)
438{
439 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
440
441 if (!clk_mgr->smu_present)
442 return;
443
444 dcn30_smu_set_pme_workaround(clk_mgr);
445}
446
efc7d165
JA		 447/* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
448static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
449{
450 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
451 unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000;
452
453 if (!clk_mgr->smu_present)
454 return;
455
456 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
457
458 for (i = 0; i < MAX_PIPES * 2; i++) {
459 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
460 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
461 }
462
463 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
464 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
465 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
466 }
467}
468
4d55b0dd
BL		 469static struct clk_mgr_funcs dcn3_funcs = {
470 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
471 .update_clocks = dcn3_update_clocks,
472 .init_clocks = dcn3_init_clocks,
473 .notify_wm_ranges = dcn3_notify_wm_ranges,
474 .set_hard_min_memclk = dcn3_set_hard_min_memclk,
475 .set_hard_max_memclk = dcn3_set_hard_max_memclk,
476 .get_memclk_states_from_smu = dcn3_get_memclk_states_from_smu,
477 .are_clock_states_equal = dcn3_are_clock_states_equal,
efc7d165
JA		 478 .enable_pme_wa = dcn3_enable_pme_wa,
479 .notify_link_rate_change = dcn30_notify_link_rate_change,
4d55b0dd
BL		 480};
481
482static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr)
483{
484 dcn2_init_clocks(clk_mgr);
485
486/* TODO: Implement the functions and remove the ifndef guard */
487}
488
489static struct clk_mgr_funcs dcn3_fpga_funcs = {
490 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
491 .update_clocks = dcn2_update_clocks_fpga,
492 .init_clocks = dcn3_init_clocks_fpga,
493};
494
495/*todo for dcn30 for clk register offset*/
496void dcn3_clk_mgr_construct(
497 struct dc_context *ctx,
498 struct clk_mgr_internal *clk_mgr,
499 struct pp_smu_funcs *pp_smu,
500 struct dccg *dccg)
501{
502 clk_mgr->base.ctx = ctx;
503 clk_mgr->base.funcs = &dcn3_funcs;
504 clk_mgr->regs = &clk_mgr_regs;
505 clk_mgr->clk_mgr_shift = &clk_mgr_shift;
506 clk_mgr->clk_mgr_mask = &clk_mgr_mask;
507
508 clk_mgr->dccg = dccg;
509 clk_mgr->dfs_bypass_disp_clk = 0;
510
511 clk_mgr->dprefclk_ss_percentage = 0;
512 clk_mgr->dprefclk_ss_divider = 1000;
513 clk_mgr->ss_on_dprefclk = false;
514 clk_mgr->dfs_ref_freq_khz = 100000;
515
516 clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
517
518 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
519 clk_mgr->base.funcs = &dcn3_fpga_funcs;
520 clk_mgr->base.dentist_vco_freq_khz = 3650000;
521
522 } else {
523 struct clk_state_registers_and_bypass s = { 0 };
524
525 /* integer part is now VCO frequency in kHz */
526 clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr);
527
528 /* in case we don't get a value from the register, use default */
529 if (clk_mgr->base.dentist_vco_freq_khz == 0)
530 clk_mgr->base.dentist_vco_freq_khz = 3650000;
531 /* Convert dprefclk units from MHz to KHz */
532 /* Value already divided by 10, some resolution lost */
533
534 /*TODO: uncomment assert once dcn3_dump_clk_registers is implemented */
535 //ASSERT(s.dprefclk != 0);
536 if (s.dprefclk != 0)
537 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
538 }
539
540 clk_mgr->dfs_bypass_enabled = false;
541
542 clk_mgr->smu_present = false;
543
544 dce_clock_read_ss_info(clk_mgr);
545
546 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
dd827a48
JA		 547
548 /* need physical address of table to give to PMFW */
549 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
550 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
551 &clk_mgr->wm_range_table_addr);
4d55b0dd
BL		 552}
553
554void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
555{
cc0e7ff8 556 kfree(clk_mgr->base.bw_params);
dd827a48
JA		 557
558 if (clk_mgr->wm_range_table)
559 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
560 clk_mgr->wm_range_table);
4d55b0dd 561}
Linux 6.x block layer and io_uring tree(s)