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Merge tag 'for-linus-2021-01-24' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / clk_mgr / dcn30 / dcn30_clk_mgr.c
CommitLineData
4d55b0dd
BL		 1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dccg.h"
27#include "clk_mgr_internal.h"
28
29#include "dcn30_clk_mgr_smu_msg.h"
30#include "dcn20/dcn20_clk_mgr.h"
31#include "dce100/dce_clk_mgr.h"
32#include "reg_helper.h"
33#include "core_types.h"
34#include "dm_helpers.h"
35
36#include "atomfirmware.h"
37
38
39#include "sienna_cichlid_ip_offset.h"
40#include "dcn/dcn_3_0_0_offset.h"
41#include "dcn/dcn_3_0_0_sh_mask.h"
42
43#include "nbio/nbio_7_4_offset.h"
44
45#include "dcn/dpcs_3_0_0_offset.h"
46#include "dcn/dpcs_3_0_0_sh_mask.h"
47
48#include "mmhub/mmhub_2_0_0_offset.h"
49#include "mmhub/mmhub_2_0_0_sh_mask.h"
50/*we don't have clk folder yet*/
51#include "dcn30/dcn30_clk_mgr.h"
52
53#undef FN
54#define FN(reg_name, field_name) \
55 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
56
57#define REG(reg) \
58 (clk_mgr->regs->reg)
59
60#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
61
62#define BASE(seg) BASE_INNER(seg)
63
64#define SR(reg_name)\
65 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
66 mm ## reg_name
67
68#undef CLK_SRI
69#define CLK_SRI(reg_name, block, inst)\
70 .reg_name = mm ## block ## _ ## reg_name
71
72static const struct clk_mgr_registers clk_mgr_regs = {
73 CLK_REG_LIST_DCN3()
74};
75
76static const struct clk_mgr_shift clk_mgr_shift = {
77 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(__SHIFT)
78};
79
80static const struct clk_mgr_mask clk_mgr_mask = {
81 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(_MASK)
82};
83
84
85/* Query SMU for all clock states for a particular clock */
86static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels)
87{
88 unsigned int i;
89 char *entry_i = (char *)entry_0;
90 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
91
92 if (ret & (1 << 31))
93 /* fine-grained, only min and max */
94 *num_levels = 2;
95 else
96 /* discrete, a number of fixed states */
97 /* will set num_levels to 0 on failure */
98 *num_levels = ret & 0xFF;
99
100 /* if the initial message failed, num_levels will be 0 */
101 for (i = 0; i < *num_levels; i++) {
102 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
103 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
104 }
105}
106
582e2ce5 107static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
4d55b0dd
BL		 108{
109 /* defaults */
110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
111 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
113 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
114
115 /* Set A - Normal - default values*/
116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
119 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;
122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
123 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
125
126 /* Set B - Performance - higher minimum clocks */
127// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
128// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
129// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
130// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
131// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
132// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = TUNED VALUE;
133// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
134// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = TUNED VALUE;
135// clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
136
137 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
138 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
139 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us;
140 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
141 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
142 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
143 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0;
144 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
145 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
146 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
147
52f2e83e
BL		 148 /* Set D - MALL - SR enter and exit times adjusted for MALL */
149// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
150// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us;
151// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2;
152// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4;
153// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
154// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0;
155// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
156// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
157// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
4d55b0dd
BL		 158}
159
160void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
161{
162 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
163 unsigned int num_levels;
164
165 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
166 clk_mgr_base->clks.p_state_change_support = true;
167 clk_mgr_base->clks.prev_p_state_change_support = true;
168 clk_mgr->smu_present = false;
169
170 if (!clk_mgr_base->bw_params)
171 return;
172
173 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
174 clk_mgr->smu_present = true;
175
176 if (!clk_mgr->smu_present)
177 return;
178
179 // do we fail if these fail? if so, how? do we not care to check?
180 dcn30_smu_check_driver_if_version(clk_mgr);
181 dcn30_smu_check_msg_header_version(clk_mgr);
182
183 /* DCFCLK */
184 dcn3_init_single_clock(clk_mgr, PPCLK_DCEFCLK,
185 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
186 &num_levels);
187
188 /* DTBCLK */
189 dcn3_init_single_clock(clk_mgr, PPCLK_DTBCLK,
190 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
191 &num_levels);
192
193 // DPREFCLK ???
194
195 /* DISPCLK */
196 dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK,
197 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
198 &num_levels);
199
200 /* DPPCLK */
201 dcn3_init_single_clock(clk_mgr, PPCLK_PIXCLK,
202 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
203 &num_levels);
204
205 /* PHYCLK */
206 dcn3_init_single_clock(clk_mgr, PPCLK_PHYCLK,
207 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz,
208 &num_levels);
209
210 /* Get UCLK, update bounding box */
211 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
212
213 /* WM range table */
582e2ce5 214 DC_FP_START();
4d55b0dd 215 dcn3_build_wm_range_table(clk_mgr);
582e2ce5 216 DC_FP_END();
4d55b0dd
BL		 217}
218
219static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
220{
221 /* get FbMult value */
222 struct fixed31_32 pll_req;
223 /* get FbMult value */
224 uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
225
226 /* set up a fixed-point number
227 * this works because the int part is on the right edge of the register
228 * and the frac part is on the left edge
229 */
230 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
231 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
232
233 /* multiply by REFCLK period */
234 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
235
236 return dc_fixpt_floor(pll_req);
237}
238
239static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
240 struct dc_state *context,
241 bool safe_to_lower)
242{
243 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
244 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
245 struct dc *dc = clk_mgr_base->ctx->dc;
246 int display_count;
247 bool update_dppclk = false;
248 bool update_dispclk = false;
249 bool enter_display_off = false;
250 bool dpp_clock_lowered = false;
251 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
252 bool force_reset = false;
253 bool update_uclk = false;
8bc3d461 254 bool p_state_change_support;
4d55b0dd
BL		 255
256 if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)
257 return;
258
259 if (clk_mgr_base->clks.dispclk_khz == 0 ||
260 (dc->debug.force_clock_mode & 0x1)) {
261 /* this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. */
262 force_reset = true;
263
264 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
265
266 /* force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. */
267 }
268 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
269
270 if (display_count == 0)
271 enter_display_off = true;
272
273 if (enter_display_off == safe_to_lower)
274 dcn30_smu_set_num_of_displays(clk_mgr, display_count);
275
4d55b0dd
BL		 276 if (dc->debug.force_min_dcfclk_mhz > 0)
277 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
278 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
279
280 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
281 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
282 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, clk_mgr_base->clks.dcfclk_khz / 1000);
283 }
284
285 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
286 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
287 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
288 }
289
290 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
291 /* We don't actually care about socclk, don't notify SMU of hard min */
292 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
293
294 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
8bc3d461
AC		 295 p_state_change_support = new_clocks->p_state_change_support || (display_count == 0);
296 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
297 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
4d55b0dd
BL		 298
299 /* to disable P-State switching, set UCLK min = max */
300 if (!clk_mgr_base->clks.p_state_change_support)
301 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
302 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
303 }
304
305 /* Always update saved value, even if new value not set due to P-State switching unsupported */
306 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
307 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
308 update_uclk = true;
309 }
310
311 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
312 if (clk_mgr_base->clks.p_state_change_support &&
313 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
314 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->clks.dramclk_khz / 1000);
315
316 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
317 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
318 dpp_clock_lowered = true;
319
320 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
321 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, clk_mgr_base->clks.dppclk_khz / 1000);
322 update_dppclk = true;
323 }
324
325 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
326 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
327 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
328 update_dispclk = true;
329 }
330
331 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
332 if (dpp_clock_lowered) {
333 /* if clock is being lowered, increase DTO before lowering refclk */
334 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
335 dcn20_update_clocks_update_dentist(clk_mgr);
336 } else {
337 /* if clock is being raised, increase refclk before lowering DTO */
338 if (update_dppclk || update_dispclk)
339 dcn20_update_clocks_update_dentist(clk_mgr);
be6ccdf8
AL		 340 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
341 * that we do not lower dto when it is not safe to lower. We do not need to
342 * compare the current and new dppclk before calling this function.*/
343 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
4d55b0dd
BL		 344 }
345 }
346
347 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
348 /*update dmcu for wait_loop count*/
349 dmcu->funcs->set_psr_wait_loop(dmcu,
350 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
351}
352
353
354static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
355{
356 unsigned int i;
4d55b0dd 357 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
dd827a48 358 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
4d55b0dd
BL		 359
360 if (!clk_mgr->smu_present)
361 return;
362
4d55b0dd
BL		 363 if (!table)
364 // should log failure
365 return;
366
367 memset(table, 0, sizeof(*table));
368
369 /* collect valid ranges, place in pmfw table */
370 for (i = 0; i < WM_SET_COUNT; i++)
371 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
372 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk;
373 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk;
374 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk;
375 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk;
376 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i;
377 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
378 }
379
dd827a48
JA		 380 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
381 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
4d55b0dd 382 dcn30_smu_transfer_wm_table_dram_2_smu(clk_mgr);
4d55b0dd
BL		 383}
384
385/* Set min memclk to minimum, either constrained by the current mode or DPM0 */
386static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
387{
388 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
389
390 if (!clk_mgr->smu_present)
391 return;
392
393 if (current_mode)
394 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
395 clk_mgr_base->clks.dramclk_khz / 1000);
396 else
397 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
398 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
399}
400
401/* Set max memclk to highest DPM value */
402static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
403{
404 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
405
406 if (!clk_mgr->smu_present)
407 return;
408
409 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
410 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
411}
412
413/* Get current memclk states, update bounding box */
414static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
415{
416 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
417 unsigned int num_levels;
418
419 if (!clk_mgr->smu_present)
420 return;
421
422 /* Refresh memclk states */
423 dcn3_init_single_clock(clk_mgr, PPCLK_UCLK,
424 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
425 &num_levels);
426 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
427
428 /* Refresh bounding box */
429 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
430 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
431}
432
433static bool dcn3_are_clock_states_equal(struct dc_clocks *a,
434 struct dc_clocks *b)
435{
436 if (a->dispclk_khz != b->dispclk_khz)
437 return false;
438 else if (a->dppclk_khz != b->dppclk_khz)
439 return false;
440 else if (a->dcfclk_khz != b->dcfclk_khz)
441 return false;
442 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
443 return false;
4d55b0dd
BL		 444 else if (a->dramclk_khz != b->dramclk_khz)
445 return false;
446 else if (a->p_state_change_support != b->p_state_change_support)
447 return false;
448
449 return true;
450}
451
452static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base)
453{
454 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
455
456 if (!clk_mgr->smu_present)
457 return;
458
459 dcn30_smu_set_pme_workaround(clk_mgr);
460}
461
efc7d165
JA		 462/* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
463static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
464{
465 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
466 unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000;
467
468 if (!clk_mgr->smu_present)
469 return;
470
471 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
472
473 for (i = 0; i < MAX_PIPES * 2; i++) {
474 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
475 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
476 }
477
478 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
479 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
480 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
481 }
482}
483
4d55b0dd
BL		 484static struct clk_mgr_funcs dcn3_funcs = {
485 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
486 .update_clocks = dcn3_update_clocks,
487 .init_clocks = dcn3_init_clocks,
488 .notify_wm_ranges = dcn3_notify_wm_ranges,
489 .set_hard_min_memclk = dcn3_set_hard_min_memclk,
490 .set_hard_max_memclk = dcn3_set_hard_max_memclk,
491 .get_memclk_states_from_smu = dcn3_get_memclk_states_from_smu,
492 .are_clock_states_equal = dcn3_are_clock_states_equal,
efc7d165
JA		 493 .enable_pme_wa = dcn3_enable_pme_wa,
494 .notify_link_rate_change = dcn30_notify_link_rate_change,
4d55b0dd
BL		 495};
496
497static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr)
498{
499 dcn2_init_clocks(clk_mgr);
500
501/* TODO: Implement the functions and remove the ifndef guard */
502}
503
42ddf36e 504struct clk_mgr_funcs dcn3_fpga_funcs = {
4d55b0dd
BL		 505 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
506 .update_clocks = dcn2_update_clocks_fpga,
507 .init_clocks = dcn3_init_clocks_fpga,
508};
509
510/*todo for dcn30 for clk register offset*/
511void dcn3_clk_mgr_construct(
512 struct dc_context *ctx,
513 struct clk_mgr_internal *clk_mgr,
514 struct pp_smu_funcs *pp_smu,
515 struct dccg *dccg)
516{
517 clk_mgr->base.ctx = ctx;
518 clk_mgr->base.funcs = &dcn3_funcs;
519 clk_mgr->regs = &clk_mgr_regs;
520 clk_mgr->clk_mgr_shift = &clk_mgr_shift;
521 clk_mgr->clk_mgr_mask = &clk_mgr_mask;
522
523 clk_mgr->dccg = dccg;
524 clk_mgr->dfs_bypass_disp_clk = 0;
525
526 clk_mgr->dprefclk_ss_percentage = 0;
527 clk_mgr->dprefclk_ss_divider = 1000;
528 clk_mgr->ss_on_dprefclk = false;
529 clk_mgr->dfs_ref_freq_khz = 100000;
530
531 clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
532
533 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
534 clk_mgr->base.funcs = &dcn3_fpga_funcs;
535 clk_mgr->base.dentist_vco_freq_khz = 3650000;
536
537 } else {
538 struct clk_state_registers_and_bypass s = { 0 };
539
540 /* integer part is now VCO frequency in kHz */
541 clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr);
542
543 /* in case we don't get a value from the register, use default */
544 if (clk_mgr->base.dentist_vco_freq_khz == 0)
545 clk_mgr->base.dentist_vco_freq_khz = 3650000;
546 /* Convert dprefclk units from MHz to KHz */
547 /* Value already divided by 10, some resolution lost */
548
549 /*TODO: uncomment assert once dcn3_dump_clk_registers is implemented */
550 //ASSERT(s.dprefclk != 0);
551 if (s.dprefclk != 0)
552 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
553 }
554
555 clk_mgr->dfs_bypass_enabled = false;
556
557 clk_mgr->smu_present = false;
558
559 dce_clock_read_ss_info(clk_mgr);
560
561 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
dd827a48
JA		 562
563 /* need physical address of table to give to PMFW */
564 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
565 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
566 &clk_mgr->wm_range_table_addr);
4d55b0dd
BL		 567}
568
569void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
570{
cc0e7ff8 571 kfree(clk_mgr->base.bw_params);
dd827a48
JA		 572
573 if (clk_mgr->wm_range_table)
574 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
575 clk_mgr->wm_range_table);
4d55b0dd 576}
Linux 6.x block layer and io_uring tree(s)