[linux-block.git] / drivers / gpu / drm / amd / display / dc / clk_mgr / dcn20 / dcn20_clk_mgr.c

/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dccg.h"
#include "clk_mgr_internal.h"

#include "dce100/dce_clk_mgr.h"
#include "dcn20_clk_mgr.h"
#include "reg_helper.h"
#include "core_types.h"
#include "dm_helpers.h"

#include "navi10_ip_offset.h"
#include "dcn/dcn_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_sh_mask.h"
#include "clk/clk_11_0_0_offset.h"
#include "clk/clk_11_0_0_sh_mask.h"

#undef FN
#define FN(reg_name, field_name) \
	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

#define REG(reg) \
	(clk_mgr->regs->reg)

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

#define BASE(seg) BASE_INNER(seg)

#define SR(reg_name)\
		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
					mm ## reg_name

#define CLK_BASE_INNER(seg) \
	CLK_BASE__INST0_SEG ## seg


static const struct clk_mgr_registers clk_mgr_regs = {
	CLK_REG_LIST_NV10()
};

static const struct clk_mgr_shift clk_mgr_shift = {
	CLK_MASK_SH_LIST_NV10(__SHIFT)
};

static const struct clk_mgr_mask clk_mgr_mask = {
	CLK_MASK_SH_LIST_NV10(_MASK)
};

uint32_t dentist_get_did_from_divider(int divider)
{
	uint32_t divider_id;

	/* we want to floor here to get higher clock than required rather than lower */
	if (divider < DENTIST_DIVIDER_RANGE_2_START) {
		if (divider < DENTIST_DIVIDER_RANGE_1_START)
			divider_id = DENTIST_BASE_DID_1;
		else
			divider_id = DENTIST_BASE_DID_1
				+ (divider - DENTIST_DIVIDER_RANGE_1_START)
					/ DENTIST_DIVIDER_RANGE_1_STEP;
	} else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
		divider_id = DENTIST_BASE_DID_2
				+ (divider - DENTIST_DIVIDER_RANGE_2_START)
					/ DENTIST_DIVIDER_RANGE_2_STEP;
	} else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
		divider_id = DENTIST_BASE_DID_3
				+ (divider - DENTIST_DIVIDER_RANGE_3_START)
					/ DENTIST_DIVIDER_RANGE_3_STEP;
	} else {
		divider_id = DENTIST_BASE_DID_4
				+ (divider - DENTIST_DIVIDER_RANGE_4_START)
					/ DENTIST_DIVIDER_RANGE_4_STEP;
		if (divider_id > DENTIST_MAX_DID)
			divider_id = DENTIST_MAX_DID;
	}

	return divider_id;
}

void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
		struct dc_state *context, bool safe_to_lower)
{
	int i;

	clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
		int dpp_inst, dppclk_khz, prev_dppclk_khz;

		/* Loop index will match dpp->inst if resource exists,
		 * and we want to avoid dependency on dpp object
		 */
		dpp_inst = i;
		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

		prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

		if ((prev_dppclk_khz > dppclk_khz && safe_to_lower) || prev_dppclk_khz < dppclk_khz) {
			clk_mgr->dccg->funcs->update_dpp_dto(
							clk_mgr->dccg, dpp_inst, dppclk_khz);
		}
	}
}

void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
{
	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;

	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);

	REG_UPDATE(DENTIST_DISPCLK_CNTL,
			DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
//	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
	REG_UPDATE(DENTIST_DISPCLK_CNTL,
			DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
}


void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
			struct dc_state *context,
			bool safe_to_lower)
{
	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
	struct dc *dc = clk_mgr_base->ctx->dc;
	struct pp_smu_funcs_nv *pp_smu = NULL;
	int display_count;
	bool update_dppclk = false;
	bool update_dispclk = false;
	bool enter_display_off = false;
	bool dpp_clock_lowered = false;
	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
	bool force_reset = false;

	if (dc->work_arounds.skip_clock_update)
		return;

	if (clk_mgr_base->clks.dispclk_khz == 0 ||
		dc->debug.force_clock_mode & 0x1) {
		//this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.
		force_reset = true;

		dcn2_read_clocks_from_hw_dentist(clk_mgr_base);

		//force_clock_mode 0x1:  force reset the clock even it is the same clock as long as it is in Passive level.
	}
	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
	if (dc->res_pool->pp_smu)
		pp_smu = &dc->res_pool->pp_smu->nv_funcs;

	if (display_count == 0)
		enter_display_off = true;

	if (enter_display_off == safe_to_lower) {
		if (pp_smu && pp_smu->set_display_count)
			pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
	}

	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
		if (pp_smu && pp_smu->set_voltage_by_freq)
			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
	}


	if (dc->debug.force_min_dcfclk_mhz > 0)
		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);

	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
		if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)
			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000);
	}

	if (should_set_clock(safe_to_lower,
			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
		if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)
			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
	}

	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
		clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
		if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)
			pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
	}

	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
		clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
		if (pp_smu && pp_smu->set_pstate_handshake_support)
			pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
	}

	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
		if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)
			pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
	}

	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
			dpp_clock_lowered = true;
		clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;

		if (pp_smu && pp_smu->set_voltage_by_freq)
			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);

		update_dppclk = true;
	}

	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
		if (pp_smu && pp_smu->set_voltage_by_freq)
			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);

		update_dispclk = true;
	}

	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
		if (dpp_clock_lowered) {
			// if clock is being lowered, increase DTO before lowering refclk
			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
			dcn20_update_clocks_update_dentist(clk_mgr);
		} else {
			// if clock is being raised, increase refclk before lowering DTO
			if (update_dppclk || update_dispclk)
				dcn20_update_clocks_update_dentist(clk_mgr);
			// always update dtos unless clock is lowered and not safe to lower
			if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
				dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
		}
	}

	if (update_dispclk &&
			dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
		/*update dmcu for wait_loop count*/
		dmcu->funcs->set_psr_wait_loop(dmcu,
			clk_mgr_base->clks.dispclk_khz / 1000 / 7);
	}
}

void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
		struct dc_state *context,
		bool safe_to_lower)
{
	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
	/* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
	int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;

	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
		clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
	}

	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
		clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
	}

	if (should_set_clock(safe_to_lower,
			new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
		clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
	}

	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
		clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
	}

	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
		clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
	}

	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
		clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
	}

	if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
		clk_mgr->clks.fclk_khz = fclk_adj;
	}

	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
		clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
	}

	/* Both fclk and ref_dppclk run on the same scemi clock.
	 * So take the higher value since the DPP DTO is typically programmed
	 * such that max dppclk is 1:1 with ref_dppclk.
	 */
	if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
		clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
	if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
		clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;

	// Both fclk and ref_dppclk run on the same scemi clock.
	clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

	dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
}

void dcn2_init_clocks(struct clk_mgr *clk_mgr)
{
	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
	// Assumption is that boot state always supports pstate
	clk_mgr->clks.p_state_change_support = true;
	clk_mgr->clks.prev_p_state_change_support = true;
}

void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
{
	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	struct pp_smu_funcs_nv *pp_smu = NULL;

	if (clk_mgr->pp_smu) {
		pp_smu = &clk_mgr->pp_smu->nv_funcs;

		if (pp_smu->set_pme_wa_enable)
			pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
	}
}


void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)
{
	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	uint32_t dispclk_wdivider;
	uint32_t dppclk_wdivider;
	int disp_divider;
	int dpp_divider;

	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider);

	disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
	dpp_divider = dentist_get_divider_from_did(dispclk_wdivider);

	if (disp_divider && dpp_divider) {
		/* Calculate the current DFS clock, in kHz.*/
		clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
			* clk_mgr->base.dentist_vco_freq_khz) / disp_divider;

		clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
				* clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
	}

}

void dcn2_get_clock(struct clk_mgr *clk_mgr,
		struct dc_state *context,
			enum dc_clock_type clock_type,
			struct dc_clock_config *clock_cfg)
{

	if (clock_type == DC_CLOCK_TYPE_DISPCLK) {
		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
		clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
		clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
	}
	if (clock_type == DC_CLOCK_TYPE_DPPCLK) {
		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
		clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
		clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
	}
}

static bool dcn2_are_clock_states_equal(struct dc_clocks *a,
		struct dc_clocks *b)
{
	if (a->dispclk_khz != b->dispclk_khz)
		return false;
	else if (a->dppclk_khz != b->dppclk_khz)
		return false;
	else if (a->dcfclk_khz != b->dcfclk_khz)
		return false;
	else if (a->socclk_khz != b->socclk_khz)
		return false;
	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
		return false;
	else if (a->phyclk_khz != b->phyclk_khz)
		return false;
	else if (a->dramclk_khz != b->dramclk_khz)
		return false;
	else if (a->p_state_change_support != b->p_state_change_support)
		return false;

	return true;
}

static struct clk_mgr_funcs dcn2_funcs = {
	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
	.update_clocks = dcn2_update_clocks,
	.init_clocks = dcn2_init_clocks,
	.enable_pme_wa = dcn2_enable_pme_wa,
	.get_clock = dcn2_get_clock,
	.are_clock_states_equal = dcn2_are_clock_states_equal,
};


void dcn20_clk_mgr_construct(
		struct dc_context *ctx,
		struct clk_mgr_internal *clk_mgr,
		struct pp_smu_funcs *pp_smu,
		struct dccg *dccg)
{
	clk_mgr->base.ctx = ctx;
	clk_mgr->pp_smu = pp_smu;
	clk_mgr->base.funcs = &dcn2_funcs;
	clk_mgr->regs = &clk_mgr_regs;
	clk_mgr->clk_mgr_shift = &clk_mgr_shift;
	clk_mgr->clk_mgr_mask = &clk_mgr_mask;

	clk_mgr->dccg = dccg;
	clk_mgr->dfs_bypass_disp_clk = 0;

	clk_mgr->dprefclk_ss_percentage = 0;
	clk_mgr->dprefclk_ss_divider = 1000;
	clk_mgr->ss_on_dprefclk = false;

	clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved

	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
		dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
		clk_mgr->base.dentist_vco_freq_khz = 3850000;

	} else {
		/* DFS Slice 2 should be used for DPREFCLK */
		int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
		/* Convert DPREFCLK DFS Slice DID to actual divider*/
		int target_div = dentist_get_divider_from_did(dprefclk_did);

		/* get FbMult value */
		uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
		struct fixed31_32 pll_req;

		/* set up a fixed-point number
		 * this works because the int part is on the right edge of the register
		 * and the frac part is on the left edge
		 */

		pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
		pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;

		/* multiply by REFCLK period */
		pll_req = dc_fixpt_mul_int(pll_req, 100000);

		/* integer part is now VCO frequency in kHz */
		clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);

		/* in case we don't get a value from the register, use default */
		if (clk_mgr->base.dentist_vco_freq_khz == 0)
			clk_mgr->base.dentist_vco_freq_khz = 3850000;

		/* Calculate the DPREFCLK in kHz.*/
		clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
	}
	//Integrated_info table does not exist on dGPU projects so should not be referenced
	//anywhere in code for dGPUs.
	//Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
	clk_mgr->dfs_bypass_enabled = false;

	dce_clock_read_ss_info(clk_mgr);
}
Commit	Line	Data
fcee01b9 HW	1	/*
	2	* Copyright 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include "dccg.h"
	27	#include "clk_mgr_internal.h"
	28
fcee01b9	29	#include "dce100/dce_clk_mgr.h"
ccce745c	30	#include "dcn20_clk_mgr.h"
fcee01b9 HW	31	#include "reg_helper.h"
	32	#include "core_types.h"
	33	#include "dm_helpers.h"
	34
	35	#include "navi10_ip_offset.h"
	36	#include "dcn/dcn_2_0_0_offset.h"
	37	#include "dcn/dcn_2_0_0_sh_mask.h"
	38	#include "clk/clk_11_0_0_offset.h"
	39	#include "clk/clk_11_0_0_sh_mask.h"
	40
	41	#undef FN
	42	#define FN(reg_name, field_name) \
	43	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
	44
	45	#define REG(reg) \
	46	(clk_mgr->regs->reg)
	47
	48	#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
	49
	50	#define BASE(seg) BASE_INNER(seg)
	51
	52	#define SR(reg_name)\
	53	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
	54	mm ## reg_name
	55
	56	#define CLK_BASE_INNER(seg) \
	57	CLK_BASE__INST0_SEG ## seg
	58
	59
	60	static const struct clk_mgr_registers clk_mgr_regs = {
	61	CLK_REG_LIST_NV10()
	62	};
	63
	64	static const struct clk_mgr_shift clk_mgr_shift = {
	65	CLK_MASK_SH_LIST_NV10(__SHIFT)
	66	};
	67
	68	static const struct clk_mgr_mask clk_mgr_mask = {
	69	CLK_MASK_SH_LIST_NV10(_MASK)
	70	};
	71
7a5ab155	72	uint32_t dentist_get_did_from_divider(int divider)
fcee01b9 HW	73	{
	74	uint32_t divider_id;
	75
	76	/* we want to floor here to get higher clock than required rather than lower */
	77	if (divider < DENTIST_DIVIDER_RANGE_2_START) {
	78	if (divider < DENTIST_DIVIDER_RANGE_1_START)
	79	divider_id = DENTIST_BASE_DID_1;
	80	else
	81	divider_id = DENTIST_BASE_DID_1
	82	+ (divider - DENTIST_DIVIDER_RANGE_1_START)
	83	/ DENTIST_DIVIDER_RANGE_1_STEP;
	84	} else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
	85	divider_id = DENTIST_BASE_DID_2
	86	+ (divider - DENTIST_DIVIDER_RANGE_2_START)
	87	/ DENTIST_DIVIDER_RANGE_2_STEP;
	88	} else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
	89	divider_id = DENTIST_BASE_DID_3
	90	+ (divider - DENTIST_DIVIDER_RANGE_3_START)
	91	/ DENTIST_DIVIDER_RANGE_3_STEP;
	92	} else {
	93	divider_id = DENTIST_BASE_DID_4
	94	+ (divider - DENTIST_DIVIDER_RANGE_4_START)
	95	/ DENTIST_DIVIDER_RANGE_4_STEP;
	96	if (divider_id > DENTIST_MAX_DID)
	97	divider_id = DENTIST_MAX_DID;
	98	}
	99
	100	return divider_id;
	101	}
	102
c69dd2d0	103	void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
54790345	104	struct dc_state *context, bool safe_to_lower)
fcee01b9 HW	105	{
	106	int i;
	107
799c5b9c	108	clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
fcee01b9	109	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
54790345	110	int dpp_inst, dppclk_khz, prev_dppclk_khz;
fcee01b9	111
1ea8751b NA	112	/* Loop index will match dpp->inst if resource exists,
	113	* and we want to avoid dependency on dpp object
	114	*/
	115	dpp_inst = i;
fcee01b9	116	dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
1ea8751b	117
54790345 SL	118	prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
54790345 SL	119
8fab6a2f	120	if ((prev_dppclk_khz > dppclk_khz && safe_to_lower) \|\| prev_dppclk_khz < dppclk_khz) {
54790345 SL	121	clk_mgr->dccg->funcs->update_dpp_dto(
	122	clk_mgr->dccg, dpp_inst, dppclk_khz);
	123	}
fcee01b9 HW	124	}
	125	}
	126
799c5b9c	127	void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
fcee01b9 HW	128	{
fcee01b9 HW	129	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
44ce0cd3	130	* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
f7f38ffe	131	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
44ce0cd3	132	* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
f7f38ffe	133
799c5b9c	134	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
f7f38ffe JL	135	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
	136
	137	REG_UPDATE(DENTIST_DISPCLK_CNTL,
	138	DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
799c5b9c WC	139	// REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
	140	REG_UPDATE(DENTIST_DISPCLK_CNTL,
	141	DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
	142	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
f7f38ffe JL	143	}
f7f38ffe JL	144
fcee01b9 HW	145
	146	void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
	147	struct dc_state *context,
	148	bool safe_to_lower)
	149	{
	150	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	151	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
	152	struct dc *dc = clk_mgr_base->ctx->dc;
	153	struct pp_smu_funcs_nv *pp_smu = NULL;
	154	int display_count;
799c5b9c	155	bool update_dppclk = false;
fcee01b9 HW	156	bool update_dispclk = false;
fcee01b9 HW	157	bool enter_display_off = false;
799c5b9c	158	bool dpp_clock_lowered = false;
8712bda4	159	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
39bca359	160	bool force_reset = false;
fcee01b9	161
37495fbd JC	162	if (dc->work_arounds.skip_clock_update)
	163	return;
	164
39bca359 CL	165	if (clk_mgr_base->clks.dispclk_khz == 0 \|\|
	166	dc->debug.force_clock_mode & 0x1) {
	167	//this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.
	168	force_reset = true;
ccce745c ML	169
	170	dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
	171
39bca359 CL	172	//force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level.
39bca359 CL	173	}
c69dd2d0	174	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
fcee01b9 HW	175	if (dc->res_pool->pp_smu)
	176	pp_smu = &dc->res_pool->pp_smu->nv_funcs;
	177
	178	if (display_count == 0)
	179	enter_display_off = true;
	180
	181	if (enter_display_off == safe_to_lower) {
	182	if (pp_smu && pp_smu->set_display_count)
	183	pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
	184	}
	185
	186	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
	187	clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
	188	if (pp_smu && pp_smu->set_voltage_by_freq)
	189	pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
	190	}
	191
f7f38ffe	192
2131f655 JL	193	if (dc->debug.force_min_dcfclk_mhz > 0)
	194	new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
	195	new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
	196
fcee01b9 HW	197	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
	198	clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
	199	if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)
	200	pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000);
	201	}
	202
	203	if (should_set_clock(safe_to_lower,
	204	new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
	205	clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
	206	if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)
	207	pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
	208	}
	209
	210	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
	211	clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
	212	if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)
	213	pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
	214	}
	215
6e17b5b8	216	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
057fc695	217	clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
6ba11740	218	clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
6e17b5b8 JL	219	if (pp_smu && pp_smu->set_pstate_handshake_support)
6e17b5b8 JL	220	pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
6ba11740	221	}
fcee01b9 HW	222
	223	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
	224	clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
	225	if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)
	226	pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
	227	}
	228
799c5b9c WC	229	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
	230	if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
	231	dpp_clock_lowered = true;
	232	clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
fcee01b9	233
799c5b9c WC	234	if (pp_smu && pp_smu->set_voltage_by_freq)
799c5b9c WC	235	pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
fcee01b9	236
799c5b9c WC	237	update_dppclk = true;
799c5b9c WC	238	}
fcee01b9	239
799c5b9c WC	240	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
	241	clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
	242	if (pp_smu && pp_smu->set_voltage_by_freq)
	243	pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
f7f38ffe	244
799c5b9c WC	245	update_dispclk = true;
799c5b9c WC	246	}
1ea8751b	247
799c5b9c WC	248	if (dc->config.forced_clocks == false \|\| (force_reset && safe_to_lower)) {
	249	if (dpp_clock_lowered) {
	250	// if clock is being lowered, increase DTO before lowering refclk
54790345	251	dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
799c5b9c WC	252	dcn20_update_clocks_update_dentist(clk_mgr);
	253	} else {
	254	// if clock is being raised, increase refclk before lowering DTO
	255	if (update_dppclk \|\| update_dispclk)
	256	dcn20_update_clocks_update_dentist(clk_mgr);
1ea8751b NA	257	// always update dtos unless clock is lowered and not safe to lower
1ea8751b NA	258	if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
54790345	259	dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
a6465d1f	260	}
c69dd2d0	261	}
1ea8751b	262
c69dd2d0 EY	263	if (update_dispclk &&
	264	dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
	265	/update dmcu for wait_loop count/
	266	dmcu->funcs->set_psr_wait_loop(dmcu,
	267	clk_mgr_base->clks.dispclk_khz / 1000 / 7);
fcee01b9 HW	268	}
	269	}
	270
	271	void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
	272	struct dc_state *context,
	273	bool safe_to_lower)
	274	{
952f6c4b AK	275	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
952f6c4b AK	276
fcee01b9	277	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
5940ff39 TD	278	/* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
5940ff39 TD	279	int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
fcee01b9 HW	280
	281	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
	282	clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
	283	}
	284
	285	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
	286	clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
	287	}
	288
	289	if (should_set_clock(safe_to_lower,
	290	new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
	291	clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
	292	}
	293
	294	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
	295	clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
	296	}
	297
	298	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
	299	clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
	300	}
	301
	302	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
	303	clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
	304	}
	305
0ff8dfe8 DL	306	if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
0ff8dfe8 DL	307	clk_mgr->clks.fclk_khz = fclk_adj;
fcee01b9 HW	308	}
	309
	310	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
	311	clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
	312	}
	313
952f6c4b AK	314	/* Both fclk and ref_dppclk run on the same scemi clock.
	315	* So take the higher value since the DPP DTO is typically programmed
	316	* such that max dppclk is 1:1 with ref_dppclk.
fcee01b9 HW	317	*/
	318	if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
	319	clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
0ff8dfe8 DL	320	if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
0ff8dfe8 DL	321	clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
fcee01b9	322
952f6c4b AK	323	// Both fclk and ref_dppclk run on the same scemi clock.
	324	clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
	325
fcee01b9 HW	326	dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
	327	}
	328
	329	void dcn2_init_clocks(struct clk_mgr *clk_mgr)
	330	{
	331	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
93c25fbd JL	332	// Assumption is that boot state always supports pstate
93c25fbd JL	333	clk_mgr->clks.p_state_change_support = true;
057fc695	334	clk_mgr->clks.prev_p_state_change_support = true;
fcee01b9 HW	335	}
fcee01b9 HW	336
170a2398 SSC	337	void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
	338	{
	339	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	340	struct pp_smu_funcs_nv *pp_smu = NULL;
	341
	342	if (clk_mgr->pp_smu) {
	343	pp_smu = &clk_mgr->pp_smu->nv_funcs;
	344
	345	if (pp_smu->set_pme_wa_enable)
	346	pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
	347	}
	348	}
	349
ccce745c ML	350
	351	void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)
	352	{
	353	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	354	uint32_t dispclk_wdivider;
	355	uint32_t dppclk_wdivider;
	356	int disp_divider;
	357	int dpp_divider;
	358
	359	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
	360	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider);
	361
	362	disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
	363	dpp_divider = dentist_get_divider_from_did(dispclk_wdivider);
	364
	365	if (disp_divider && dpp_divider) {
	366	/* Calculate the current DFS clock, in kHz.*/
	367	clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
	368	* clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
	369
	370	clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
	371	* clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
	372	}
	373
	374	}
	375
925f566c CL	376	void dcn2_get_clock(struct clk_mgr *clk_mgr,
	377	struct dc_state *context,
	378	enum dc_clock_type clock_type,
	379	struct dc_clock_config *clock_cfg)
	380	{
	381
	382	if (clock_type == DC_CLOCK_TYPE_DISPCLK) {
	383	clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
	384	clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
	385	clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
	386	clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
	387	}
	388	if (clock_type == DC_CLOCK_TYPE_DPPCLK) {
	389	clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
	390	clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
	391	clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
	392	clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
	393	}
	394	}
	395
deb79818 JL	396	static bool dcn2_are_clock_states_equal(struct dc_clocks *a,
	397	struct dc_clocks *b)
	398	{
	399	if (a->dispclk_khz != b->dispclk_khz)
	400	return false;
	401	else if (a->dppclk_khz != b->dppclk_khz)
	402	return false;
	403	else if (a->dcfclk_khz != b->dcfclk_khz)
	404	return false;
	405	else if (a->socclk_khz != b->socclk_khz)
	406	return false;
	407	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
	408	return false;
	409	else if (a->phyclk_khz != b->phyclk_khz)
	410	return false;
	411	else if (a->dramclk_khz != b->dramclk_khz)
	412	return false;
	413	else if (a->p_state_change_support != b->p_state_change_support)
	414	return false;
	415
	416	return true;
	417	}
	418
fcee01b9 HW	419	static struct clk_mgr_funcs dcn2_funcs = {
	420	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
	421	.update_clocks = dcn2_update_clocks,
170a2398	422	.init_clocks = dcn2_init_clocks,
925f566c CL	423	.enable_pme_wa = dcn2_enable_pme_wa,
925f566c CL	424	.get_clock = dcn2_get_clock,
deb79818	425	.are_clock_states_equal = dcn2_are_clock_states_equal,
fcee01b9 HW	426	};
	427
	428
	429	void dcn20_clk_mgr_construct(
	430	struct dc_context *ctx,
	431	struct clk_mgr_internal *clk_mgr,
	432	struct pp_smu_funcs *pp_smu,
	433	struct dccg *dccg)
	434	{
	435	clk_mgr->base.ctx = ctx;
1d0610bc	436	clk_mgr->pp_smu = pp_smu;
fcee01b9 HW	437	clk_mgr->base.funcs = &dcn2_funcs;
	438	clk_mgr->regs = &clk_mgr_regs;
	439	clk_mgr->clk_mgr_shift = &clk_mgr_shift;
	440	clk_mgr->clk_mgr_mask = &clk_mgr_mask;
	441
	442	clk_mgr->dccg = dccg;
	443	clk_mgr->dfs_bypass_disp_clk = 0;
	444
	445	clk_mgr->dprefclk_ss_percentage = 0;
	446	clk_mgr->dprefclk_ss_divider = 1000;
	447	clk_mgr->ss_on_dprefclk = false;
	448
	449	clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
	450
	451	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
	452	dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
44ce0cd3	453	clk_mgr->base.dentist_vco_freq_khz = 3850000;
fcee01b9 HW	454
	455	} else {
	456	/* DFS Slice 2 should be used for DPREFCLK */
	457	int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
	458	/* Convert DPREFCLK DFS Slice DID to actual divider*/
	459	int target_div = dentist_get_divider_from_did(dprefclk_did);
	460
	461	/* get FbMult value */
	462	uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
	463	struct fixed31_32 pll_req;
	464
	465	/* set up a fixed-point number
	466	* this works because the int part is on the right edge of the register
	467	* and the frac part is on the left edge
	468	*/
8712bda4	469
fcee01b9 HW	470	pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
	471	pll_req.value \|= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
	472
	473	/* multiply by REFCLK period */
	474	pll_req = dc_fixpt_mul_int(pll_req, 100000);
	475
	476	/* integer part is now VCO frequency in kHz */
44ce0cd3	477	clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
fcee01b9 HW	478
fcee01b9 HW	479	/* in case we don't get a value from the register, use default */
44ce0cd3 DL	480	if (clk_mgr->base.dentist_vco_freq_khz == 0)
44ce0cd3 DL	481	clk_mgr->base.dentist_vco_freq_khz = 3850000;
fcee01b9 HW	482
	483	/* Calculate the DPREFCLK in kHz.*/
	484	clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
44ce0cd3	485	* clk_mgr->base.dentist_vco_freq_khz) / target_div;
fcee01b9 HW	486	}
	487	//Integrated_info table does not exist on dGPU projects so should not be referenced
	488	//anywhere in code for dGPUs.
	489	//Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
	490	clk_mgr->dfs_bypass_enabled = false;
	491
	492	dce_clock_read_ss_info(clk_mgr);
	493	}
	494