[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / clk_mgr / dcn20 / dcn20_clk_mgr.c

/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dccg.h"
#include "clk_mgr_internal.h"


#include "dcn20/dcn20_clk_mgr.h"
#include "dce100/dce_clk_mgr.h"
#include "reg_helper.h"
#include "core_types.h"
#include "dm_helpers.h"

#include "navi10_ip_offset.h"
#include "dcn/dcn_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_sh_mask.h"
#include "clk/clk_11_0_0_offset.h"
#include "clk/clk_11_0_0_sh_mask.h"

#undef FN
#define FN(reg_name, field_name) \
	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

#define REG(reg) \
	(clk_mgr->regs->reg)

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

#define BASE(seg) BASE_INNER(seg)

#define SR(reg_name)\
		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
					mm ## reg_name

#define CLK_BASE_INNER(seg) \
	CLK_BASE__INST0_SEG ## seg


static const struct clk_mgr_registers clk_mgr_regs = {
	CLK_REG_LIST_NV10()
};

static const struct clk_mgr_shift clk_mgr_shift = {
	CLK_MASK_SH_LIST_NV10(__SHIFT)
};

static const struct clk_mgr_mask clk_mgr_mask = {
	CLK_MASK_SH_LIST_NV10(_MASK)
};

uint32_t dentist_get_did_from_divider(int divider)
{
	uint32_t divider_id;

	/* we want to floor here to get higher clock than required rather than lower */
	if (divider < DENTIST_DIVIDER_RANGE_2_START) {
		if (divider < DENTIST_DIVIDER_RANGE_1_START)
			divider_id = DENTIST_BASE_DID_1;
		else
			divider_id = DENTIST_BASE_DID_1
				+ (divider - DENTIST_DIVIDER_RANGE_1_START)
					/ DENTIST_DIVIDER_RANGE_1_STEP;
	} else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
		divider_id = DENTIST_BASE_DID_2
				+ (divider - DENTIST_DIVIDER_RANGE_2_START)
					/ DENTIST_DIVIDER_RANGE_2_STEP;
	} else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
		divider_id = DENTIST_BASE_DID_3
				+ (divider - DENTIST_DIVIDER_RANGE_3_START)
					/ DENTIST_DIVIDER_RANGE_3_STEP;
	} else {
		divider_id = DENTIST_BASE_DID_4
				+ (divider - DENTIST_DIVIDER_RANGE_4_START)
					/ DENTIST_DIVIDER_RANGE_4_STEP;
		if (divider_id > DENTIST_MAX_DID)
			divider_id = DENTIST_MAX_DID;
	}

	return divider_id;
}

void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
		struct dc_state *context)
{
	int i;

	clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
		int dpp_inst, dppclk_khz;

		if (!context->res_ctx.pipe_ctx[i].plane_state)
			continue;

		dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
		clk_mgr->dccg->funcs->update_dpp_dto(
				clk_mgr->dccg, dpp_inst, dppclk_khz);
	}
}

void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
{
	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;

	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);

	REG_UPDATE(DENTIST_DISPCLK_CNTL,
			DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
//	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
	REG_UPDATE(DENTIST_DISPCLK_CNTL,
			DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
}


void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
			struct dc_state *context,
			bool safe_to_lower)
{
	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
	struct dc *dc = clk_mgr_base->ctx->dc;
	struct pp_smu_funcs_nv *pp_smu = NULL;
	int display_count;
	bool update_dppclk = false;
	bool update_dispclk = false;
	bool enter_display_off = false;
	bool dpp_clock_lowered = false;
	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
	if (dc->res_pool->pp_smu)
		pp_smu = &dc->res_pool->pp_smu->nv_funcs;

	if (display_count == 0)
		enter_display_off = true;

	if (enter_display_off == safe_to_lower) {
		if (pp_smu && pp_smu->set_display_count)
			pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
	}

	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
		if (pp_smu && pp_smu->set_voltage_by_freq)
			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
	}

	if (dc->debug.force_min_dcfclk_mhz > 0)
		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);

	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
		if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)
			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000);
	}

	if (should_set_clock(safe_to_lower,
			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
		if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)
			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
	}

	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
		clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
		if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)
			pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
	}

	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
		clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
		if (pp_smu && pp_smu->set_pstate_handshake_support)
			pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
	}

	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
		if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)
			pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
	}

	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
			dpp_clock_lowered = true;
		clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;

		if (pp_smu && pp_smu->set_voltage_by_freq)
			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);

		update_dppclk = true;
	}

	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
		if (pp_smu && pp_smu->set_voltage_by_freq)
			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);

		update_dispclk = true;
	}
	if (dc->config.forced_clocks == false) {
		if (dpp_clock_lowered) {
			// if clock is being lowered, increase DTO before lowering refclk
			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
			dcn20_update_clocks_update_dentist(clk_mgr);
		} else {
			// if clock is being raised, increase refclk before lowering DTO
			if (update_dppclk || update_dispclk)
				dcn20_update_clocks_update_dentist(clk_mgr);
			if (update_dppclk)
				dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
		}
	}
	if (update_dispclk &&
			dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
		/*update dmcu for wait_loop count*/
		dmcu->funcs->set_psr_wait_loop(dmcu,
			clk_mgr_base->clks.dispclk_khz / 1000 / 7);
	}
}

void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
		struct dc_state *context,
		bool safe_to_lower)
{
	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
	/* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
	int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;

	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
		clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
	}

	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
		clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
	}

	if (should_set_clock(safe_to_lower,
			new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
		clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
	}

	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
		clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
	}

	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
		clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
	}

	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
		clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
	}

	if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
		clk_mgr->clks.fclk_khz = fclk_adj;
	}

	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
		clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
	}

	/* Both fclk and dppclk ref are run on the same scemi clock so we
	 * need to keep the same value for both
	 */
	if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
		clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
	if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
		clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;

	dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
}

void dcn2_init_clocks(struct clk_mgr *clk_mgr)
{
	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
	// Assumption is that boot state always supports pstate
	clk_mgr->clks.p_state_change_support = true;
}

void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
{
	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	struct pp_smu_funcs_nv *pp_smu = NULL;

	if (clk_mgr->pp_smu) {
		pp_smu = &clk_mgr->pp_smu->nv_funcs;

		if (pp_smu->set_pme_wa_enable)
			pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
	}
}

static struct clk_mgr_funcs dcn2_funcs = {
	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
	.update_clocks = dcn2_update_clocks,
	.init_clocks = dcn2_init_clocks,
	.enable_pme_wa = dcn2_enable_pme_wa
};


void dcn20_clk_mgr_construct(
		struct dc_context *ctx,
		struct clk_mgr_internal *clk_mgr,
		struct pp_smu_funcs *pp_smu,
		struct dccg *dccg)
{
	clk_mgr->base.ctx = ctx;
	clk_mgr->pp_smu = pp_smu;
	clk_mgr->base.funcs = &dcn2_funcs;
	clk_mgr->regs = &clk_mgr_regs;
	clk_mgr->clk_mgr_shift = &clk_mgr_shift;
	clk_mgr->clk_mgr_mask = &clk_mgr_mask;

	clk_mgr->dccg = dccg;
	clk_mgr->dfs_bypass_disp_clk = 0;

	clk_mgr->dprefclk_ss_percentage = 0;
	clk_mgr->dprefclk_ss_divider = 1000;
	clk_mgr->ss_on_dprefclk = false;

	clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved

	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
		dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
		clk_mgr->dentist_vco_freq_khz = 3850000;

	} else {
		/* DFS Slice 2 should be used for DPREFCLK */
		int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
		/* Convert DPREFCLK DFS Slice DID to actual divider*/
		int target_div = dentist_get_divider_from_did(dprefclk_did);

		/* get FbMult value */
		uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
		struct fixed31_32 pll_req;

		/* set up a fixed-point number
		 * this works because the int part is on the right edge of the register
		 * and the frac part is on the left edge
		 */

		pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
		pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;

		/* multiply by REFCLK period */
		pll_req = dc_fixpt_mul_int(pll_req, 100000);

		/* integer part is now VCO frequency in kHz */
		clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req);

		/* in case we don't get a value from the register, use default */
		if (clk_mgr->dentist_vco_freq_khz == 0)
			clk_mgr->dentist_vco_freq_khz = 3850000;

		/* Calculate the DPREFCLK in kHz.*/
		clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
			* clk_mgr->dentist_vco_freq_khz) / target_div;
	}
	//Integrated_info table does not exist on dGPU projects so should not be referenced
	//anywhere in code for dGPUs.
	//Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
	clk_mgr->dfs_bypass_enabled = false;

	dce_clock_read_ss_info(clk_mgr);
}
Commit	Line	Data
fcee01b9 HW	1	/*
	2	* Copyright 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include "dccg.h"
	27	#include "clk_mgr_internal.h"
	28
	29
	30	#include "dcn20/dcn20_clk_mgr.h"
	31	#include "dce100/dce_clk_mgr.h"
	32	#include "reg_helper.h"
	33	#include "core_types.h"
	34	#include "dm_helpers.h"
	35
	36	#include "navi10_ip_offset.h"
	37	#include "dcn/dcn_2_0_0_offset.h"
	38	#include "dcn/dcn_2_0_0_sh_mask.h"
	39	#include "clk/clk_11_0_0_offset.h"
	40	#include "clk/clk_11_0_0_sh_mask.h"
	41
	42	#undef FN
	43	#define FN(reg_name, field_name) \
	44	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
	45
	46	#define REG(reg) \
	47	(clk_mgr->regs->reg)
	48
	49	#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
	50
	51	#define BASE(seg) BASE_INNER(seg)
	52
	53	#define SR(reg_name)\
	54	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
	55	mm ## reg_name
	56
	57	#define CLK_BASE_INNER(seg) \
	58	CLK_BASE__INST0_SEG ## seg
	59
	60
	61	static const struct clk_mgr_registers clk_mgr_regs = {
	62	CLK_REG_LIST_NV10()
	63	};
	64
65	static const struct clk_mgr_shift clk_mgr_shift = {
66	CLK_MASK_SH_LIST_NV10(__SHIFT)
67	};
68
69	static const struct clk_mgr_mask clk_mgr_mask = {
70	CLK_MASK_SH_LIST_NV10(_MASK)
71	};
72
7a5ab155	73	uint32_t dentist_get_did_from_divider(int divider)
fcee01b9 HW	74	{
	75	uint32_t divider_id;
	76
	77	/* we want to floor here to get higher clock than required rather than lower */
	78	if (divider < DENTIST_DIVIDER_RANGE_2_START) {
	79	if (divider < DENTIST_DIVIDER_RANGE_1_START)
	80	divider_id = DENTIST_BASE_DID_1;
	81	else
	82	divider_id = DENTIST_BASE_DID_1
	83	+ (divider - DENTIST_DIVIDER_RANGE_1_START)
	84	/ DENTIST_DIVIDER_RANGE_1_STEP;
	85	} else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
	86	divider_id = DENTIST_BASE_DID_2
	87	+ (divider - DENTIST_DIVIDER_RANGE_2_START)
	88	/ DENTIST_DIVIDER_RANGE_2_STEP;
	89	} else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
	90	divider_id = DENTIST_BASE_DID_3
	91	+ (divider - DENTIST_DIVIDER_RANGE_3_START)
	92	/ DENTIST_DIVIDER_RANGE_3_STEP;
	93	} else {
	94	divider_id = DENTIST_BASE_DID_4
	95	+ (divider - DENTIST_DIVIDER_RANGE_4_START)
	96	/ DENTIST_DIVIDER_RANGE_4_STEP;
	97	if (divider_id > DENTIST_MAX_DID)
	98	divider_id = DENTIST_MAX_DID;
	99	}
	100
	101	return divider_id;
	102	}
	103
c69dd2d0	104	void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
fcee01b9 HW	105	struct dc_state *context)
	106	{
	107	int i;
	108
	109	clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
	110	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
	111	int dpp_inst, dppclk_khz;
	112
	113	if (!context->res_ctx.pipe_ctx[i].plane_state)
	114	continue;
	115
	116	dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
	117	dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
	118	clk_mgr->dccg->funcs->update_dpp_dto(
	119	clk_mgr->dccg, dpp_inst, dppclk_khz);
	120	}
	121	}
	122
c69dd2d0	123	void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
fcee01b9 HW	124	{
	125	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
	126	* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
	127	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
	128	* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
	129
	130	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
	131	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
	132
	133	REG_UPDATE(DENTIST_DISPCLK_CNTL,
	134	DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
	135	// REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
	136	REG_UPDATE(DENTIST_DISPCLK_CNTL,
	137	DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
	138	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
	139	}
	140
	141
	142	void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
	143	struct dc_state *context,
	144	bool safe_to_lower)
	145	{
	146	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	147	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
	148	struct dc *dc = clk_mgr_base->ctx->dc;
	149	struct pp_smu_funcs_nv *pp_smu = NULL;
	150	int display_count;
	151	bool update_dppclk = false;
	152	bool update_dispclk = false;
	153	bool enter_display_off = false;
	154	bool dpp_clock_lowered = false;
8712bda4	155	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
fcee01b9	156
c69dd2d0	157	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
fcee01b9 HW	158	if (dc->res_pool->pp_smu)
	159	pp_smu = &dc->res_pool->pp_smu->nv_funcs;
	160
	161	if (display_count == 0)
	162	enter_display_off = true;
	163
	164	if (enter_display_off == safe_to_lower) {
	165	if (pp_smu && pp_smu->set_display_count)
	166	pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
	167	}
	168
	169	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
	170	clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
	171	if (pp_smu && pp_smu->set_voltage_by_freq)
	172	pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
	173	}
	174
2131f655 JL	175	if (dc->debug.force_min_dcfclk_mhz > 0)
	176	new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
	177	new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
	178
fcee01b9 HW	179	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
	180	clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
	181	if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)
	182	pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000);
	183	}
	184
	185	if (should_set_clock(safe_to_lower,
	186	new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
	187	clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
	188	if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)
	189	pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
	190	}
	191
	192	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
	193	clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
	194	if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)
	195	pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
	196	}
	197
6e17b5b8	198	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
6ba11740	199	clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
6e17b5b8 JL	200	if (pp_smu && pp_smu->set_pstate_handshake_support)
6e17b5b8 JL	201	pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
6ba11740	202	}
fcee01b9 HW	203
	204	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
	205	clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
	206	if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)
	207	pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
	208	}
	209
	210	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
	211	if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
	212	dpp_clock_lowered = true;
	213	clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
	214
	215	if (pp_smu && pp_smu->set_voltage_by_freq)
	216	pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
	217
	218	update_dppclk = true;
	219	}
	220
	221	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
	222	clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
	223	if (pp_smu && pp_smu->set_voltage_by_freq)
	224	pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
	225
	226	update_dispclk = true;
	227	}
a6465d1f CL	228	if (dc->config.forced_clocks == false) {
	229	if (dpp_clock_lowered) {
	230	// if clock is being lowered, increase DTO before lowering refclk
c69dd2d0	231	dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
a6465d1f CL	232	dcn20_update_clocks_update_dentist(clk_mgr);
	233	} else {
	234	// if clock is being raised, increase refclk before lowering DTO
	235	if (update_dppclk \|\| update_dispclk)
	236	dcn20_update_clocks_update_dentist(clk_mgr);
	237	if (update_dppclk)
	238	dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
	239	}
c69dd2d0	240	}
c69dd2d0 EY	241	if (update_dispclk &&
	242	dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
	243	/update dmcu for wait_loop count/
	244	dmcu->funcs->set_psr_wait_loop(dmcu,
	245	clk_mgr_base->clks.dispclk_khz / 1000 / 7);
fcee01b9 HW	246	}
	247	}
	248
	249	void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
	250	struct dc_state *context,
	251	bool safe_to_lower)
	252	{
	253	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
5940ff39 TD	254	/* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
5940ff39 TD	255	int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
fcee01b9 HW	256
	257	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
	258	clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
	259	}
	260
	261	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
	262	clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
	263	}
	264
	265	if (should_set_clock(safe_to_lower,
	266	new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
	267	clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
	268	}
	269
	270	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
	271	clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
	272	}
	273
	274	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
	275	clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
	276	}
	277
	278	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
	279	clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
	280	}
	281
0ff8dfe8 DL	282	if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
0ff8dfe8 DL	283	clk_mgr->clks.fclk_khz = fclk_adj;
fcee01b9 HW	284	}
	285
	286	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
	287	clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
	288	}
	289
	290	/* Both fclk and dppclk ref are run on the same scemi clock so we
	291	* need to keep the same value for both
	292	*/
	293	if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
	294	clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
0ff8dfe8 DL	295	if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
0ff8dfe8 DL	296	clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
fcee01b9 HW	297
	298	dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
	299	}
	300
	301	void dcn2_init_clocks(struct clk_mgr *clk_mgr)
	302	{
	303	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
61f33f6a JL	304	// Assumption is that boot state always supports pstate
61f33f6a JL	305	clk_mgr->clks.p_state_change_support = true;
fcee01b9 HW	306	}
fcee01b9 HW	307
170a2398 SSC	308	void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
	309	{
	310	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	311	struct pp_smu_funcs_nv *pp_smu = NULL;
	312
	313	if (clk_mgr->pp_smu) {
	314	pp_smu = &clk_mgr->pp_smu->nv_funcs;
	315
	316	if (pp_smu->set_pme_wa_enable)
	317	pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
	318	}
	319	}
	320
fcee01b9 HW	321	static struct clk_mgr_funcs dcn2_funcs = {
	322	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
	323	.update_clocks = dcn2_update_clocks,
170a2398 SSC	324	.init_clocks = dcn2_init_clocks,
170a2398 SSC	325	.enable_pme_wa = dcn2_enable_pme_wa
fcee01b9 HW	326	};
	327
	328
	329	void dcn20_clk_mgr_construct(
	330	struct dc_context *ctx,
	331	struct clk_mgr_internal *clk_mgr,
	332	struct pp_smu_funcs *pp_smu,
	333	struct dccg *dccg)
	334	{
	335	clk_mgr->base.ctx = ctx;
19f87696	336	clk_mgr->pp_smu = pp_smu;
fcee01b9 HW	337	clk_mgr->base.funcs = &dcn2_funcs;
	338	clk_mgr->regs = &clk_mgr_regs;
	339	clk_mgr->clk_mgr_shift = &clk_mgr_shift;
	340	clk_mgr->clk_mgr_mask = &clk_mgr_mask;
	341
	342	clk_mgr->dccg = dccg;
	343	clk_mgr->dfs_bypass_disp_clk = 0;
	344
	345	clk_mgr->dprefclk_ss_percentage = 0;
	346	clk_mgr->dprefclk_ss_divider = 1000;
	347	clk_mgr->ss_on_dprefclk = false;
	348
	349	clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
	350
	351	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
	352	dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
	353	clk_mgr->dentist_vco_freq_khz = 3850000;
	354
	355	} else {
	356	/* DFS Slice 2 should be used for DPREFCLK */
	357	int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
	358	/* Convert DPREFCLK DFS Slice DID to actual divider*/
	359	int target_div = dentist_get_divider_from_did(dprefclk_did);
	360
	361	/* get FbMult value */
	362	uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
	363	struct fixed31_32 pll_req;
	364
	365	/* set up a fixed-point number
	366	* this works because the int part is on the right edge of the register
	367	* and the frac part is on the left edge
	368	*/
8712bda4	369
fcee01b9 HW	370	pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
	371	pll_req.value \|= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
	372
	373	/* multiply by REFCLK period */
	374	pll_req = dc_fixpt_mul_int(pll_req, 100000);
	375
	376	/* integer part is now VCO frequency in kHz */
	377	clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
	378
	379	/* in case we don't get a value from the register, use default */
	380	if (clk_mgr->dentist_vco_freq_khz == 0)
	381	clk_mgr->dentist_vco_freq_khz = 3850000;
	382
	383	/* Calculate the DPREFCLK in kHz.*/
	384	clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
	385	* clk_mgr->dentist_vco_freq_khz) / target_div;
	386	}
	387	//Integrated_info table does not exist on dGPU projects so should not be referenced
	388	//anywhere in code for dGPUs.
	389	//Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
	390	clk_mgr->dfs_bypass_enabled = false;
	391
	392	dce_clock_read_ss_info(clk_mgr);
	393	}
	394