[linux-block.git] / drivers / gpu / drm / amd / display / dc / clk_mgr / dce100 / dce_clk_mgr.c

/*
 * Copyright 2012-16 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */


#include "dccg.h"
#include "clk_mgr_internal.h"
#include "dce_clk_mgr.h"
#include "dce110/dce110_clk_mgr.h"
#include "dce112/dce112_clk_mgr.h"
#include "reg_helper.h"
#include "dmcu.h"
#include "core_types.h"
#include "dal_asic_id.h"

/*
 * Currently the register shifts and masks in this file are used for dce100 and dce80
 * which has identical definitions.
 * TODO: remove this when DPREFCLK_CNTL and dpref DENTIST_DISPCLK_CNTL
 * is moved to dccg, where it belongs
 */
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"

#define REG(reg) \
	(clk_mgr->regs->reg)

#undef FN
#define FN(reg_name, field_name) \
	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

static const struct clk_mgr_registers disp_clk_regs = {
		CLK_COMMON_REG_LIST_DCE_BASE()
};

static const struct clk_mgr_shift disp_clk_shift = {
		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
};

static const struct clk_mgr_mask disp_clk_mask = {
		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};


/* Max clock values for each state indexed by "enum clocks_state": */
static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
/* ClocksStateInvalid - should not be used */
{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
/* ClocksStateLow */
{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
/* ClocksStateNominal */
{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
/* ClocksStatePerformance */
{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };

int dentist_get_divider_from_did(int did)
{
	if (did < DENTIST_BASE_DID_1)
		did = DENTIST_BASE_DID_1;
	if (did > DENTIST_MAX_DID)
		did = DENTIST_MAX_DID;

	if (did < DENTIST_BASE_DID_2) {
		return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP
							* (did - DENTIST_BASE_DID_1);
	} else if (did < DENTIST_BASE_DID_3) {
		return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
							* (did - DENTIST_BASE_DID_2);
	} else if (did < DENTIST_BASE_DID_4) {
		return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
							* (did - DENTIST_BASE_DID_3);
	} else {
		return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP
							* (did - DENTIST_BASE_DID_4);
	}
}

/* SW will adjust DP REF Clock average value for all purposes
 * (DP DTO / DP Audio DTO and DP GTC)
 if clock is spread for all cases:
 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
 calculations for DS_INCR/DS_MODULO (this is planned to be default case)
 -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
 calculations (not planned to be used, but average clock should still
 be valid)
 -if SS enabled on DP Ref clock and HW de-spreading disabled
 (should not be case with CIK) then SW should program all rates
 generated according to average value (case as with previous ASICs)
  */

int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz)
{
	if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) {
		struct fixed31_32 ss_percentage = dc_fixpt_div_int(
				dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage,
							clk_mgr_dce->dprefclk_ss_divider), 200);
		struct fixed31_32 adj_dp_ref_clk_khz;

		ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
		adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
		dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
	}
	return dp_ref_clk_khz;
}

int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
{
	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	int dprefclk_wdivider;
	int dprefclk_src_sel;
	int dp_ref_clk_khz;
	int target_div;

	/* ASSERT DP Reference Clock source is from DFS*/
	REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
	ASSERT(dprefclk_src_sel == 0);

	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);

	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
	target_div = dentist_get_divider_from_did(dprefclk_wdivider);

	/* Calculate the current DFS clock, in kHz.*/
	dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
		* clk_mgr->base.dentist_vco_freq_khz) / target_div;

	return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
}

int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
{
	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz);
}

/* unit: in_khz before mode set, get pixel clock from context. ASIC register
 * may not be programmed yet
 */
uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context)
{
	uint32_t max_pix_clk = 0;
	int i;

	for (i = 0; i < MAX_PIPES; i++) {
		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

		if (pipe_ctx->stream == NULL)
			continue;

		/* do not check under lay */
		if (pipe_ctx->top_pipe)
			continue;

		if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
			max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

		/* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS
		 * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
		 */
		if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
				pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
			max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
	}

	return max_pix_clk;
}

enum dm_pp_clocks_state dce_get_required_clocks_state(
	struct clk_mgr *clk_mgr_base,
	struct dc_state *context)
{
	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	int i;
	enum dm_pp_clocks_state low_req_clk;
	int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context);

	/* Iterate from highest supported to lowest valid state, and update
	 * lowest RequiredState with the lowest state that satisfies
	 * all required clocks
	 */
	for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
		if (context->bw_ctx.bw.dce.dispclk_khz >
				clk_mgr_dce->max_clks_by_state[i].display_clk_khz
			|| max_pix_clk >
				clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz)
			break;

	low_req_clk = i + 1;
	if (low_req_clk > clk_mgr_dce->max_clks_state) {
		/* set max clock state for high phyclock, invalid on exceeding display clock */
		if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
				< context->bw_ctx.bw.dce.dispclk_khz)
			low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
		else
			low_req_clk = clk_mgr_dce->max_clks_state;
	}

	return low_req_clk;
}


/* TODO: remove use the two broken down functions */
int dce_set_clock(
	struct clk_mgr *clk_mgr_base,
	int requested_clk_khz)
{
	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
	struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
	int actual_clock = requested_clk_khz;
	struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;

	/* Make sure requested clock isn't lower than minimum threshold*/
	if (requested_clk_khz > 0)
		requested_clk_khz = max(requested_clk_khz,
				clk_mgr_dce->base.dentist_vco_freq_khz / 64);

	/* Prepare to program display clock*/
	pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
	pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;

	if (clk_mgr_dce->dfs_bypass_active)
		pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;

	bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);

	if (clk_mgr_dce->dfs_bypass_active) {
		/* Cache the fixed display clock*/
		clk_mgr_dce->dfs_bypass_disp_clk =
			pxl_clk_params.dfs_bypass_display_clock;
		actual_clock = pxl_clk_params.dfs_bypass_display_clock;
	}

	/* from power down, we need mark the clock state as ClocksStateNominal
	 * from HWReset, so when resume we will call pplib voltage regulator.*/
	if (requested_clk_khz == 0)
		clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;

	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
		dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);

	return actual_clock;
}


static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
{
	struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
	int i;

	if (bp->integrated_info)
		clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
	if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) {
		clk_mgr_dce->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
		if (clk_mgr_dce->base.dentist_vco_freq_khz == 0)
			clk_mgr_dce->base.dentist_vco_freq_khz = 3600000;
	}

	/*update the maximum display clock for each power state*/
	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
		enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;

		switch (i) {
		case 0:
			clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
			break;

		case 1:
			clk_state = DM_PP_CLOCKS_STATE_LOW;
			break;

		case 2:
			clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
			break;

		case 3:
			clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
			break;

		default:
			clk_state = DM_PP_CLOCKS_STATE_INVALID;
			break;
		}

		/*Do not allow bad VBIOS/SBIOS to override with invalid values,
		 * check for > 100MHz*/
		if (bp->integrated_info)
			if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
				clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
					bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
	}

	if (!debug->disable_dfs_bypass && bp->integrated_info)
		if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
			clk_mgr_dce->dfs_bypass_enabled = true;
}

void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce)
{
	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
	int ss_info_num = bp->funcs->get_ss_entry_number(
			bp, AS_SIGNAL_TYPE_GPU_PLL);

	if (ss_info_num) {
		struct spread_spectrum_info info = { { 0 } };
		enum bp_result result = bp->funcs->get_spread_spectrum_info(
				bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);

		/* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
		 * even if SS not enabled and in that case
		 * SSInfo.spreadSpectrumPercentage !=0 would be sign
		 * that SS is enabled
		 */
		if (result == BP_RESULT_OK &&
				info.spread_spectrum_percentage != 0) {
			clk_mgr_dce->ss_on_dprefclk = true;
			clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;

			if (info.type.CENTER_MODE == 0) {
				/* TODO: Currently for DP Reference clock we
				 * need only SS percentage for
				 * downspread */
				clk_mgr_dce->dprefclk_ss_percentage =
						info.spread_spectrum_percentage;
			}

			return;
		}

		result = bp->funcs->get_spread_spectrum_info(
				bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);

		/* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
		 * even if SS not enabled and in that case
		 * SSInfo.spreadSpectrumPercentage !=0 would be sign
		 * that SS is enabled
		 */
		if (result == BP_RESULT_OK &&
				info.spread_spectrum_percentage != 0) {
			clk_mgr_dce->ss_on_dprefclk = true;
			clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;

			if (info.type.CENTER_MODE == 0) {
				/* Currently for DP Reference clock we
				 * need only SS percentage for
				 * downspread */
				clk_mgr_dce->dprefclk_ss_percentage =
						info.spread_spectrum_percentage;
			}
			if (clk_mgr_dce->base.ctx->dc->config.ignore_dpref_ss)
				clk_mgr_dce->dprefclk_ss_percentage = 0;
		}
	}
}

static void dce_pplib_apply_display_requirements(
	struct dc *dc,
	struct dc_state *context)
{
	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;

	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);

	dce110_fill_display_configs(context, pp_display_cfg);

	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
}

static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
			struct dc_state *context,
			bool safe_to_lower)
{
	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
	struct dm_pp_power_level_change_request level_change_req;
	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;

	/*TODO: W/A for dal3 linux, investigate why this works */
	if (!clk_mgr_dce->dfs_bypass_active)
		patched_disp_clk = patched_disp_clk * 115 / 100;

	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
	/* get max clock state from PPLIB */
	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
	}

	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
		patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
		clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
	}
	dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
}


static struct clk_mgr_funcs dce_funcs = {
	.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
	.update_clocks = dce_update_clocks
};

void dce_clk_mgr_construct(
		struct dc_context *ctx,
		struct clk_mgr_internal *clk_mgr)
{
	struct clk_mgr *base = &clk_mgr->base;
	struct dm_pp_static_clock_info static_clk_info = {0};

	memcpy(clk_mgr->max_clks_by_state,
		dce80_max_clks_by_state,
		sizeof(dce80_max_clks_by_state));

	base->ctx = ctx;
	base->funcs = &dce_funcs;

	clk_mgr->regs = &disp_clk_regs;
	clk_mgr->clk_mgr_shift = &disp_clk_shift;
	clk_mgr->clk_mgr_mask = &disp_clk_mask;
	clk_mgr->dfs_bypass_disp_clk = 0;

	clk_mgr->dprefclk_ss_percentage = 0;
	clk_mgr->dprefclk_ss_divider = 1000;
	clk_mgr->ss_on_dprefclk = false;

	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
		clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
	else
		clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
	clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;

	dce_clock_read_integrated_info(clk_mgr);
	dce_clock_read_ss_info(clk_mgr);
}
Commit	Line	Data
9a70eba7 DL	1	/*
	2	* Copyright 2012-16 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
9b93eb47 EY	25
9b93eb47 EY	26
dc88b4a6 EY	27	#include "dccg.h"
dc88b4a6 EY	28	#include "clk_mgr_internal.h"
84e7fc05	29	#include "dce_clk_mgr.h"
9b93eb47 EY	30	#include "dce110/dce110_clk_mgr.h"
9b93eb47 EY	31	#include "dce112/dce112_clk_mgr.h"
9a70eba7	32	#include "reg_helper.h"
9f72f51d	33	#include "dmcu.h"
fb3466a4	34	#include "core_types.h"
14a13a0e	35	#include "dal_asic_id.h"
15a27de2	36
dc88b4a6 EY	37	/*
	38	* Currently the register shifts and masks in this file are used for dce100 and dce80
	39	* which has identical definitions.
	40	* TODO: remove this when DPREFCLK_CNTL and dpref DENTIST_DISPCLK_CNTL
	41	* is moved to dccg, where it belongs
	42	*/
	43	#include "dce/dce_8_0_d.h"
	44	#include "dce/dce_8_0_sh_mask.h"
9a70eba7 DL	45
9a70eba7 DL	46	#define REG(reg) \
dc88b4a6	47	(clk_mgr->regs->reg)
9a70eba7 DL	48
	49	#undef FN
	50	#define FN(reg_name, field_name) \
dc88b4a6 EY	51	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
	52
	53	static const struct clk_mgr_registers disp_clk_regs = {
	54	CLK_COMMON_REG_LIST_DCE_BASE()
	55	};
	56
	57	static const struct clk_mgr_shift disp_clk_shift = {
	58	CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
	59	};
	60
	61	static const struct clk_mgr_mask disp_clk_mask = {
	62	CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
	63	};
9a70eba7	64
9a70eba7	65
e11b86ad	66	/* Max clock values for each state indexed by "enum clocks_state": */
395f669e	67	static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
e11b86ad DL	68	/* ClocksStateInvalid - should not be used */
	69	{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
	70	/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
	71	{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
	72	/* ClocksStateLow */
	73	{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
	74	/* ClocksStateNominal */
	75	{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
	76	/* ClocksStatePerformance */
	77	{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
	78
261f3924	79	int dentist_get_divider_from_did(int did)
e11b86ad	80	{
294c7e73 DL	81	if (did < DENTIST_BASE_DID_1)
	82	did = DENTIST_BASE_DID_1;
	83	if (did > DENTIST_MAX_DID)
	84	did = DENTIST_MAX_DID;
	85
	86	if (did < DENTIST_BASE_DID_2) {
	87	return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP
	88	* (did - DENTIST_BASE_DID_1);
	89	} else if (did < DENTIST_BASE_DID_3) {
	90	return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
	91	* (did - DENTIST_BASE_DID_2);
39a3cd67	92	} else if (did < DENTIST_BASE_DID_4) {
294c7e73 DL	93	return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
294c7e73 DL	94	* (did - DENTIST_BASE_DID_3);
39a3cd67 DL	95	} else {
	96	return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP
	97	* (did - DENTIST_BASE_DID_4);
e11b86ad	98	}
e11b86ad DL	99	}
e11b86ad DL	100
3cdecd45 DL	101	/* SW will adjust DP REF Clock average value for all purposes
	102	* (DP DTO / DP Audio DTO and DP GTC)
	103	if clock is spread for all cases:
	104	-if SS enabled on DP Ref clock and HW de-spreading enabled with SW
	105	calculations for DS_INCR/DS_MODULO (this is planned to be default case)
	106	-if SS enabled on DP Ref clock and HW de-spreading enabled with HW
	107	calculations (not planned to be used, but average clock should still
	108	be valid)
	109	-if SS enabled on DP Ref clock and HW de-spreading disabled
	110	(should not be case with CIK) then SW should program all rates
	111	generated according to average value (case as with previous ASICs)
	112	*/
dc88b4a6 EY	113
dc88b4a6 EY	114	int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz)
3cdecd45	115	{
84e7fc05	116	if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) {
3cdecd45	117	struct fixed31_32 ss_percentage = dc_fixpt_div_int(
84e7fc05 DL	118	dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage,
84e7fc05 DL	119	clk_mgr_dce->dprefclk_ss_divider), 200);
3cdecd45 DL	120	struct fixed31_32 adj_dp_ref_clk_khz;
	121
	122	ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
	123	adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
	124	dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
	125	}
	126	return dp_ref_clk_khz;
	127	}
	128
dc88b4a6	129	int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
9a70eba7	130	{
dc88b4a6	131	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
9a70eba7 DL	132	int dprefclk_wdivider;
9a70eba7 DL	133	int dprefclk_src_sel;
5edb7691	134	int dp_ref_clk_khz;
472800a0	135	int target_div;
9a70eba7 DL	136
	137	/* ASSERT DP Reference Clock source is from DFS*/
	138	REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
	139	ASSERT(dprefclk_src_sel == 0);
	140
	141	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
	142	* programmed DID DENTIST_DPREFCLK_WDIVIDER*/
	143	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
	144
	145	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
472800a0 DL	146	target_div = dentist_get_divider_from_did(dprefclk_wdivider);
	147
	148	/* Calculate the current DFS clock, in kHz.*/
294c7e73	149	dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
44ce0cd3	150	* clk_mgr->base.dentist_vco_freq_khz) / target_div;
9a70eba7	151
dc88b4a6	152	return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
9a70eba7 DL	153	}
9a70eba7 DL	154
dc88b4a6	155	int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
3f6d7435	156	{
dc88b4a6	157	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
3f6d7435	158
dc88b4a6	159	return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz);
24f7dd7e DL	160	}
	161
	162	/* unit: in_khz before mode set, get pixel clock from context. ASIC register
	163	* may not be programmed yet
	164	*/
dc88b4a6	165	uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context)
24f7dd7e DL	166	{
	167	uint32_t max_pix_clk = 0;
	168	int i;
	169
	170	for (i = 0; i < MAX_PIPES; i++) {
	171	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
	172
	173	if (pipe_ctx->stream == NULL)
	174	continue;
	175
	176	/* do not check under lay */
	177	if (pipe_ctx->top_pipe)
	178	continue;
	179
380604e2 KC	180	if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
380604e2 KC	181	max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
24f7dd7e DL	182
	183	/* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS
	184	* logic for HBR3 still needs Nominal (0.8V) on VDDC rail
	185	*/
	186	if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
	187	pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
	188	max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
	189	}
	190
	191	return max_pix_clk;
3f6d7435	192	}
3cdecd45	193
dc88b4a6 EY	194	enum dm_pp_clocks_state dce_get_required_clocks_state(
dc88b4a6 EY	195	struct clk_mgr *clk_mgr_base,
24f7dd7e	196	struct dc_state *context)
9a70eba7	197	{
dc88b4a6	198	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
9a70eba7 DL	199	int i;
9a70eba7 DL	200	enum dm_pp_clocks_state low_req_clk;
dc88b4a6	201	int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context);
9a70eba7 DL	202
	203	/* Iterate from highest supported to lowest valid state, and update
	204	* lowest RequiredState with the lowest state that satisfies
	205	* all required clocks
	206	*/
84e7fc05	207	for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
813d20dc	208	if (context->bw_ctx.bw.dce.dispclk_khz >
84e7fc05	209	clk_mgr_dce->max_clks_by_state[i].display_clk_khz
24f7dd7e	210	\|\| max_pix_clk >
84e7fc05	211	clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz)
9a70eba7 DL	212	break;
	213
	214	low_req_clk = i + 1;
84e7fc05	215	if (low_req_clk > clk_mgr_dce->max_clks_state) {
fab55d61	216	/* set max clock state for high phyclock, invalid on exceeding display clock */
84e7fc05	217	if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
813d20dc	218	< context->bw_ctx.bw.dce.dispclk_khz)
fab55d61 DL	219	low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
fab55d61 DL	220	else
84e7fc05	221	low_req_clk = clk_mgr_dce->max_clks_state;
9a70eba7 DL	222	}
	223
	224	return low_req_clk;
	225	}
	226
dc88b4a6	227
b2293ac2	228	/* TODO: remove use the two broken down functions */
dc88b4a6 EY	229	int dce_set_clock(
dc88b4a6 EY	230	struct clk_mgr *clk_mgr_base,
e11b86ad	231	int requested_clk_khz)
9a70eba7	232	{
dc88b4a6	233	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
9a70eba7	234	struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
dc88b4a6	235	struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
b8e9eb72	236	int actual_clock = requested_clk_khz;
84e7fc05	237	struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
9a70eba7 DL	238
	239	/* Make sure requested clock isn't lower than minimum threshold*/
	240	if (requested_clk_khz > 0)
7d7024ca	241	requested_clk_khz = max(requested_clk_khz,
44ce0cd3	242	clk_mgr_dce->base.dentist_vco_freq_khz / 64);
9a70eba7 DL	243
9a70eba7 DL	244	/* Prepare to program display clock*/
380604e2	245	pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
9a70eba7 DL	246	pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
9a70eba7 DL	247
84e7fc05	248	if (clk_mgr_dce->dfs_bypass_active)
4e60536d NK	249	pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;
4e60536d NK	250
9a70eba7 DL	251	bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
9a70eba7 DL	252
84e7fc05	253	if (clk_mgr_dce->dfs_bypass_active) {
9a70eba7	254	/* Cache the fixed display clock*/
84e7fc05	255	clk_mgr_dce->dfs_bypass_disp_clk =
9a70eba7	256	pxl_clk_params.dfs_bypass_display_clock;
b8e9eb72	257	actual_clock = pxl_clk_params.dfs_bypass_display_clock;
9a70eba7 DL	258	}
	259
	260	/* from power down, we need mark the clock state as ClocksStateNominal
	261	* from HWReset, so when resume we will call pplib voltage regulator.*/
	262	if (requested_clk_khz == 0)
84e7fc05	263	clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
9a70eba7	264
4b594b8d DF	265	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
4b594b8d DF	266	dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
9f72f51d	267
24f7dd7e	268	return actual_clock;
9a70eba7 DL	269	}
9a70eba7 DL	270
b2293ac2	271
dc88b4a6	272	static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
9a70eba7	273	{
84e7fc05 DL	274	struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
84e7fc05 DL	275	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
9a70eba7 DL	276	int i;
	277
	278	if (bp->integrated_info)
44ce0cd3 DL	279	clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
	280	if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) {
	281	clk_mgr_dce->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
	282	if (clk_mgr_dce->base.dentist_vco_freq_khz == 0)
	283	clk_mgr_dce->base.dentist_vco_freq_khz = 3600000;
9a70eba7 DL	284	}
	285
	286	/update the maximum display clock for each power state/
	287	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
	288	enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
	289
	290	switch (i) {
	291	case 0:
	292	clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
	293	break;
	294
	295	case 1:
	296	clk_state = DM_PP_CLOCKS_STATE_LOW;
	297	break;
	298
	299	case 2:
	300	clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
	301	break;
	302
	303	case 3:
	304	clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
	305	break;
	306
	307	default:
	308	clk_state = DM_PP_CLOCKS_STATE_INVALID;
	309	break;
	310	}
	311
	312	/*Do not allow bad VBIOS/SBIOS to override with invalid values,
	313	* check for > 100MHz*/
9adc8050 DL	314	if (bp->integrated_info)
	315	if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
	316	clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
	317	bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
9a70eba7 DL	318	}
9a70eba7 DL	319
85944914	320	if (!debug->disable_dfs_bypass && bp->integrated_info)
9a70eba7	321	if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
84e7fc05	322	clk_mgr_dce->dfs_bypass_enabled = true;
9a70eba7 DL	323	}
9a70eba7 DL	324
dc88b4a6	325	void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce)
9a70eba7	326	{
84e7fc05	327	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
9a70eba7 DL	328	int ss_info_num = bp->funcs->get_ss_entry_number(
	329	bp, AS_SIGNAL_TYPE_GPU_PLL);
	330
	331	if (ss_info_num) {
c2e218dd	332	struct spread_spectrum_info info = { { 0 } };
9a70eba7 DL	333	enum bp_result result = bp->funcs->get_spread_spectrum_info(
	334	bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
	335
	336	/* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
	337	* even if SS not enabled and in that case
	338	* SSInfo.spreadSpectrumPercentage !=0 would be sign
	339	* that SS is enabled
	340	*/
	341	if (result == BP_RESULT_OK &&
	342	info.spread_spectrum_percentage != 0) {
84e7fc05 DL	343	clk_mgr_dce->ss_on_dprefclk = true;
84e7fc05 DL	344	clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
9a70eba7 DL	345
9a70eba7 DL	346	if (info.type.CENTER_MODE == 0) {
7d091f7a	347	/* TODO: Currently for DP Reference clock we
9a70eba7 DL	348	* need only SS percentage for
9a70eba7 DL	349	* downspread */
84e7fc05	350	clk_mgr_dce->dprefclk_ss_percentage =
9a70eba7 DL	351	info.spread_spectrum_percentage;
9a70eba7 DL	352	}
7d091f7a HW	353
7d091f7a HW	354	return;
9a70eba7 DL	355	}
9a70eba7 DL	356
7d091f7a HW	357	result = bp->funcs->get_spread_spectrum_info(
	358	bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);
	359
	360	/* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
	361	* even if SS not enabled and in that case
	362	* SSInfo.spreadSpectrumPercentage !=0 would be sign
	363	* that SS is enabled
	364	*/
	365	if (result == BP_RESULT_OK &&
	366	info.spread_spectrum_percentage != 0) {
84e7fc05 DL	367	clk_mgr_dce->ss_on_dprefclk = true;
84e7fc05 DL	368	clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
7d091f7a HW	369
	370	if (info.type.CENTER_MODE == 0) {
	371	/* Currently for DP Reference clock we
	372	* need only SS percentage for
	373	* downspread */
84e7fc05	374	clk_mgr_dce->dprefclk_ss_percentage =
7d091f7a HW	375	info.spread_spectrum_percentage;
7d091f7a HW	376	}
382aceb3	377	if (clk_mgr_dce->base.ctx->dc->config.ignore_dpref_ss)
301306a9	378	clk_mgr_dce->dprefclk_ss_percentage = 0;
7d091f7a	379	}
9a70eba7 DL	380	}
	381	}
	382
24f7dd7e DL	383	static void dce_pplib_apply_display_requirements(
	384	struct dc *dc,
	385	struct dc_state *context)
	386	{
	387	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
	388
	389	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
	390
	391	dce110_fill_display_configs(context, pp_display_cfg);
	392
	393	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
	394	dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
	395	}
	396
dc88b4a6	397	static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
24f7dd7e	398	struct dc_state *context,
fab55d61 DL	399	bool safe_to_lower)
fab55d61 DL	400	{
dc88b4a6	401	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
fab55d61	402	struct dm_pp_power_level_change_request level_change_req;
813d20dc	403	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
6c0984d5	404
24f7dd7e	405	/TODO: W/A for dal3 linux, investigate why this works /
84e7fc05	406	if (!clk_mgr_dce->dfs_bypass_active)
8d25a560	407	patched_disp_clk = patched_disp_clk * 115 / 100;
fab55d61	408
dc88b4a6	409	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
fab55d61	410	/* get max clock state from PPLIB */
84e7fc05 DL	411	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
84e7fc05 DL	412	\|\| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
dc88b4a6	413	if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
84e7fc05	414	clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
fab55d61 DL	415	}
fab55d61 DL	416
dc88b4a6 EY	417	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
	418	patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
	419	clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
24f7dd7e	420	}
dc88b4a6	421	dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
24f7dd7e DL	422	}
24f7dd7e DL	423
9a70eba7	424
9b93eb47 EY	425
	426
	427
	428
	429
	430
21e471f0	431	static struct clk_mgr_funcs dce_funcs = {
3cdecd45	432	.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
fab55d61	433	.update_clocks = dce_update_clocks
9a70eba7 DL	434	};
9a70eba7 DL	435
dc88b4a6 EY	436	void dce_clk_mgr_construct(
	437	struct dc_context *ctx,
	438	struct clk_mgr_internal *clk_mgr)
9a70eba7	439	{
dc88b4a6	440	struct clk_mgr *base = &clk_mgr->base;
4244381c	441	struct dm_pp_static_clock_info static_clk_info = {0};
9a70eba7	442
dc88b4a6 EY	443	memcpy(clk_mgr->max_clks_by_state,
	444	dce80_max_clks_by_state,
	445	sizeof(dce80_max_clks_by_state));
	446
9a70eba7 DL	447	base->ctx = ctx;
	448	base->funcs = &dce_funcs;
	449
dc88b4a6 EY	450	clk_mgr->regs = &disp_clk_regs;
	451	clk_mgr->clk_mgr_shift = &disp_clk_shift;
	452	clk_mgr->clk_mgr_mask = &disp_clk_mask;
	453	clk_mgr->dfs_bypass_disp_clk = 0;
7d091f7a	454
dc88b4a6 EY	455	clk_mgr->dprefclk_ss_percentage = 0;
	456	clk_mgr->dprefclk_ss_divider = 1000;
	457	clk_mgr->ss_on_dprefclk = false;
4244381c DL	458
4244381c DL	459	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
dc88b4a6	460	clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
4244381c	461	else
dc88b4a6 EY	462	clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
dc88b4a6 EY	463	clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
9a70eba7	464
dc88b4a6 EY	465	dce_clock_read_integrated_info(clk_mgr);
dc88b4a6 EY	466	dce_clock_read_ss_info(clk_mgr);
9a70eba7	467	}
9b93eb47	468