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Merge branch 'ras/urgent' into ras/core
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / dc / bios / bios_parser2.c
CommitLineData
ae79c310
HW		 1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27
ae79c310
HW		 28#include "ObjectID.h"
29#include "atomfirmware.h"
ae79c310
HW		 30
31#include "dc_bios_types.h"
32#include "include/grph_object_ctrl_defs.h"
33#include "include/bios_parser_interface.h"
34#include "include/i2caux_interface.h"
35#include "include/logger_interface.h"
36
37#include "command_table2.h"
38
39#include "bios_parser_helper.h"
40#include "command_table_helper2.h"
41#include "bios_parser2.h"
42#include "bios_parser_types_internal2.h"
43#include "bios_parser_interface.h"
44
e25cb588 45#include "bios_parser_common.h"
ae79c310 46#define LAST_RECORD_TYPE 0xff
316178f0 47#define SMU9_SYSPLL0_ID 0
ae79c310
HW		 48
49struct i2c_id_config_access {
50 uint8_t bfI2C_LineMux:4;
51 uint8_t bfHW_EngineID:3;
52 uint8_t bfHW_Capable:1;
53 uint8_t ucAccess;
54};
55
ae79c310
HW		 56static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
57 struct atom_i2c_record *record,
58 struct graphics_object_i2c_info *info);
59
60static enum bp_result bios_parser_get_firmware_info(
61 struct dc_bios *dcb,
1515a47b 62 struct dc_firmware_info *info);
ae79c310
HW		 63
64static enum bp_result bios_parser_get_encoder_cap_info(
65 struct dc_bios *dcb,
66 struct graphics_object_id object_id,
67 struct bp_encoder_cap_info *info);
68
69static enum bp_result get_firmware_info_v3_1(
70 struct bios_parser *bp,
1515a47b 71 struct dc_firmware_info *info);
ae79c310 72
6e65fb86
HW		 73static enum bp_result get_firmware_info_v3_2(
74 struct bios_parser *bp,
75 struct dc_firmware_info *info);
76
ae79c310
HW		 77static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
78 struct atom_display_object_path_v2 *object);
79
80static struct atom_encoder_caps_record *get_encoder_cap_record(
81 struct bios_parser *bp,
82 struct atom_display_object_path_v2 *object);
83
84#define BIOS_IMAGE_SIZE_OFFSET 2
85#define BIOS_IMAGE_SIZE_UNIT 512
86
87#define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
88
89
90static void destruct(struct bios_parser *bp)
91{
d029810c
DA		 92 kfree(bp->base.bios_local_image);
93 kfree(bp->base.integrated_info);
ae79c310
HW		 94}
95
96static void firmware_parser_destroy(struct dc_bios **dcb)
97{
98 struct bios_parser *bp = BP_FROM_DCB(*dcb);
99
100 if (!bp) {
101 BREAK_TO_DEBUGGER();
102 return;
103 }
104
105 destruct(bp);
106
2004f45e 107 kfree(bp);
ae79c310
HW		 108 *dcb = NULL;
109}
110
111static void get_atom_data_table_revision(
112 struct atom_common_table_header *atom_data_tbl,
113 struct atom_data_revision *tbl_revision)
114{
115 if (!tbl_revision)
116 return;
117
118 /* initialize the revision to 0 which is invalid revision */
119 tbl_revision->major = 0;
120 tbl_revision->minor = 0;
121
122 if (!atom_data_tbl)
123 return;
124
125 tbl_revision->major =
126 (uint32_t) atom_data_tbl->format_revision & 0x3f;
127 tbl_revision->minor =
128 (uint32_t) atom_data_tbl->content_revision & 0x3f;
129}
130
e4bf0a0e
HW		 131/* BIOS oject table displaypath is per connector.
132 * There is extra path not for connector. BIOS fill its encoderid as 0
133 */
ae79c310
HW		 134static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
135{
136 struct bios_parser *bp = BP_FROM_DCB(dcb);
137 unsigned int count = 0;
138 unsigned int i;
139
140 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
e4bf0a0e 141 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
ae79c310
HW		 142 count++;
143 }
144 return count;
145}
146
147static struct graphics_object_id bios_parser_get_encoder_id(
148 struct dc_bios *dcb,
149 uint32_t i)
150{
151 struct bios_parser *bp = BP_FROM_DCB(dcb);
152 struct graphics_object_id object_id = dal_graphics_object_id_init(
153 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
154
155 if (bp->object_info_tbl.v1_4->number_of_path > i)
156 object_id = object_id_from_bios_object_id(
157 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
158
159 return object_id;
160}
161
162static struct graphics_object_id bios_parser_get_connector_id(
163 struct dc_bios *dcb,
164 uint8_t i)
165{
166 struct bios_parser *bp = BP_FROM_DCB(dcb);
167 struct graphics_object_id object_id = dal_graphics_object_id_init(
168 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
169 struct object_info_table *tbl = &bp->object_info_tbl;
170 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
171
172 if (v1_4->number_of_path > i) {
173 /* If display_objid is generic object id, the encoderObj
174 * /extencoderobjId should be 0
175 */
176 if (v1_4->display_path[i].encoderobjid != 0 &&
177 v1_4->display_path[i].display_objid != 0)
178 object_id = object_id_from_bios_object_id(
179 v1_4->display_path[i].display_objid);
180 }
181
182 return object_id;
183}
184
185
186/* TODO: GetNumberOfSrc*/
187
188static uint32_t bios_parser_get_dst_number(struct dc_bios *dcb,
189 struct graphics_object_id id)
190{
191 /* connector has 1 Dest, encoder has 0 Dest */
192 switch (id.type) {
193 case OBJECT_TYPE_ENCODER:
194 return 0;
195 case OBJECT_TYPE_CONNECTOR:
196 return 1;
197 default:
198 return 0;
199 }
200}
201
202/* removed getSrcObjList, getDestObjList*/
203
204
205static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
206 struct graphics_object_id object_id, uint32_t index,
207 struct graphics_object_id *src_object_id)
208{
209 struct bios_parser *bp = BP_FROM_DCB(dcb);
210 unsigned int i;
211 enum bp_result bp_result = BP_RESULT_BADINPUT;
212 struct graphics_object_id obj_id = {0};
213 struct object_info_table *tbl = &bp->object_info_tbl;
214
215 if (!src_object_id)
216 return bp_result;
217
218 switch (object_id.type) {
219 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
220 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
221 */
222 case OBJECT_TYPE_ENCODER:
223 /* TODO: since num of src must be less than 2.
224 * If found in for loop, should break.
225 * DAL2 implementation may be changed too
226 */
227 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
228 obj_id = object_id_from_bios_object_id(
229 tbl->v1_4->display_path[i].encoderobjid);
230 if (object_id.type == obj_id.type &&
231 object_id.id == obj_id.id &&
232 object_id.enum_id ==
233 obj_id.enum_id) {
234 *src_object_id =
235 object_id_from_bios_object_id(0x1100);
236 /* break; */
237 }
238 }
239 bp_result = BP_RESULT_OK;
240 break;
241 case OBJECT_TYPE_CONNECTOR:
242 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
243 obj_id = object_id_from_bios_object_id(
244 tbl->v1_4->display_path[i].display_objid);
245
246 if (object_id.type == obj_id.type &&
247 object_id.id == obj_id.id &&
248 object_id.enum_id == obj_id.enum_id) {
249 *src_object_id =
250 object_id_from_bios_object_id(
251 tbl->v1_4->display_path[i].encoderobjid);
252 /* break; */
253 }
254 }
255 bp_result = BP_RESULT_OK;
256 break;
257 default:
258 break;
259 }
260
261 return bp_result;
262}
263
264static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb,
265 struct graphics_object_id object_id, uint32_t index,
266 struct graphics_object_id *dest_object_id)
267{
268 struct bios_parser *bp = BP_FROM_DCB(dcb);
269 unsigned int i;
270 enum bp_result bp_result = BP_RESULT_BADINPUT;
271 struct graphics_object_id obj_id = {0};
272 struct object_info_table *tbl = &bp->object_info_tbl;
273
274 if (!dest_object_id)
275 return BP_RESULT_BADINPUT;
276
277 switch (object_id.type) {
278 case OBJECT_TYPE_ENCODER:
279 /* TODO: since num of src must be less than 2.
280 * If found in for loop, should break.
281 * DAL2 implementation may be changed too
282 */
283 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
284 obj_id = object_id_from_bios_object_id(
285 tbl->v1_4->display_path[i].encoderobjid);
286 if (object_id.type == obj_id.type &&
287 object_id.id == obj_id.id &&
288 object_id.enum_id ==
289 obj_id.enum_id) {
290 *dest_object_id =
291 object_id_from_bios_object_id(
292 tbl->v1_4->display_path[i].display_objid);
293 /* break; */
294 }
295 }
296 bp_result = BP_RESULT_OK;
297 break;
298 default:
299 break;
300 }
301
302 return bp_result;
303}
304
305
306/* from graphics_object_id, find display path which includes the object_id */
307static struct atom_display_object_path_v2 *get_bios_object(
308 struct bios_parser *bp,
309 struct graphics_object_id id)
310{
311 unsigned int i;
312 struct graphics_object_id obj_id = {0};
313
314 switch (id.type) {
315 case OBJECT_TYPE_ENCODER:
316 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
317 obj_id = object_id_from_bios_object_id(
318 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
319 if (id.type == obj_id.type &&
320 id.id == obj_id.id &&
321 id.enum_id == obj_id.enum_id)
322 return
323 &bp->object_info_tbl.v1_4->display_path[i];
324 }
325 case OBJECT_TYPE_CONNECTOR:
326 case OBJECT_TYPE_GENERIC:
327 /* Both Generic and Connector Object ID
328 * will be stored on display_objid
329 */
330 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
331 obj_id = object_id_from_bios_object_id(
332 bp->object_info_tbl.v1_4->display_path[i].display_objid
333 );
334 if (id.type == obj_id.type &&
335 id.id == obj_id.id &&
336 id.enum_id == obj_id.enum_id)
337 return
338 &bp->object_info_tbl.v1_4->display_path[i];
339 }
340 default:
341 return NULL;
342 }
343}
344
345static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
346 struct graphics_object_id id,
347 struct graphics_object_i2c_info *info)
348{
349 uint32_t offset;
350 struct atom_display_object_path_v2 *object;
351 struct atom_common_record_header *header;
352 struct atom_i2c_record *record;
353 struct bios_parser *bp = BP_FROM_DCB(dcb);
354
355 if (!info)
356 return BP_RESULT_BADINPUT;
357
358 object = get_bios_object(bp, id);
359
360 if (!object)
361 return BP_RESULT_BADINPUT;
362
363 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
364
365 for (;;) {
366 header = GET_IMAGE(struct atom_common_record_header, offset);
367
368 if (!header)
369 return BP_RESULT_BADBIOSTABLE;
370
371 if (header->record_type == LAST_RECORD_TYPE ||
372 !header->record_size)
373 break;
374
375 if (header->record_type == ATOM_I2C_RECORD_TYPE
376 && sizeof(struct atom_i2c_record) <=
377 header->record_size) {
378 /* get the I2C info */
379 record = (struct atom_i2c_record *) header;
380
381 if (get_gpio_i2c_info(bp, record, info) ==
382 BP_RESULT_OK)
383 return BP_RESULT_OK;
384 }
385
386 offset += header->record_size;
387 }
388
389 return BP_RESULT_NORECORD;
390}
391
392static enum bp_result get_gpio_i2c_info(
393 struct bios_parser *bp,
394 struct atom_i2c_record *record,
395 struct graphics_object_i2c_info *info)
396{
397 struct atom_gpio_pin_lut_v2_1 *header;
398 uint32_t count = 0;
399 unsigned int table_index = 0;
400
401 if (!info)
402 return BP_RESULT_BADINPUT;
403
404 /* get the GPIO_I2C info */
405 if (!DATA_TABLES(gpio_pin_lut))
406 return BP_RESULT_BADBIOSTABLE;
407
408 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
409 DATA_TABLES(gpio_pin_lut));
410 if (!header)
411 return BP_RESULT_BADBIOSTABLE;
412
413 if (sizeof(struct atom_common_table_header) +
414 sizeof(struct atom_gpio_pin_assignment) >
415 le16_to_cpu(header->table_header.structuresize))
416 return BP_RESULT_BADBIOSTABLE;
417
418 /* TODO: is version change? */
419 if (header->table_header.content_revision != 1)
420 return BP_RESULT_UNSUPPORTED;
421
422 /* get data count */
423 count = (le16_to_cpu(header->table_header.structuresize)
424 - sizeof(struct atom_common_table_header))
425 / sizeof(struct atom_gpio_pin_assignment);
426
427 table_index = record->i2c_id & I2C_HW_LANE_MUX;
428
429 if (count < table_index) {
430 bool find_valid = false;
431
432 for (table_index = 0; table_index < count; table_index++) {
433 if (((record->i2c_id & I2C_HW_CAP) == (
434 header->gpio_pin[table_index].gpio_id &
435 I2C_HW_CAP)) &&
436 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) ==
437 (header->gpio_pin[table_index].gpio_id &
438 I2C_HW_ENGINE_ID_MASK)) &&
439 ((record->i2c_id & I2C_HW_LANE_MUX) ==
440 (header->gpio_pin[table_index].gpio_id &
441 I2C_HW_LANE_MUX))) {
442 /* still valid */
443 find_valid = true;
444 break;
445 }
446 }
447 /* If we don't find the entry that we are looking for then
448 * we will return BP_Result_BadBiosTable.
449 */
450 if (find_valid == false)
451 return BP_RESULT_BADBIOSTABLE;
452 }
453
454 /* get the GPIO_I2C_INFO */
455 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
456 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
457 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
458 info->i2c_slave_address = record->i2c_slave_addr;
459
460 /* TODO: check how to get register offset for en, Y, etc. */
461 info->gpio_info.clk_a_register_index =
462 le16_to_cpu(
463 header->gpio_pin[table_index].data_a_reg_index);
464 info->gpio_info.clk_a_shift =
465 header->gpio_pin[table_index].gpio_bitshift;
466
467 return BP_RESULT_OK;
468}
469
470static enum bp_result get_voltage_ddc_info_v4(
471 uint8_t *i2c_line,
472 uint32_t index,
473 struct atom_common_table_header *header,
474 uint8_t *address)
475{
476 enum bp_result result = BP_RESULT_NORECORD;
477 struct atom_voltage_objects_info_v4_1 *info =
478 (struct atom_voltage_objects_info_v4_1 *) address;
479
480 uint8_t *voltage_current_object =
481 (uint8_t *) (&(info->voltage_object[0]));
482
483 while ((address + le16_to_cpu(header->structuresize)) >
484 voltage_current_object) {
485 struct atom_i2c_voltage_object_v4 *object =
486 (struct atom_i2c_voltage_object_v4 *)
487 voltage_current_object;
488
489 if (object->header.voltage_mode ==
490 ATOM_INIT_VOLTAGE_REGULATOR) {
491 if (object->header.voltage_type == index) {
492 *i2c_line = object->i2c_id ^ 0x90;
493 result = BP_RESULT_OK;
494 break;
495 }
496 }
497
498 voltage_current_object +=
499 le16_to_cpu(object->header.object_size);
500 }
501 return result;
502}
503
504static enum bp_result bios_parser_get_thermal_ddc_info(
505 struct dc_bios *dcb,
506 uint32_t i2c_channel_id,
507 struct graphics_object_i2c_info *info)
508{
509 struct bios_parser *bp = BP_FROM_DCB(dcb);
510 struct i2c_id_config_access *config;
511 struct atom_i2c_record record;
512
513 if (!info)
514 return BP_RESULT_BADINPUT;
515
516 config = (struct i2c_id_config_access *) &i2c_channel_id;
517
518 record.i2c_id = config->bfHW_Capable;
519 record.i2c_id |= config->bfI2C_LineMux;
520 record.i2c_id |= config->bfHW_EngineID;
521
522 return get_gpio_i2c_info(bp, &record, info);
523}
524
525static enum bp_result bios_parser_get_voltage_ddc_info(struct dc_bios *dcb,
526 uint32_t index,
527 struct graphics_object_i2c_info *info)
528{
529 uint8_t i2c_line = 0;
530 enum bp_result result = BP_RESULT_NORECORD;
531 uint8_t *voltage_info_address;
532 struct atom_common_table_header *header;
533 struct atom_data_revision revision = {0};
534 struct bios_parser *bp = BP_FROM_DCB(dcb);
535
536 if (!DATA_TABLES(voltageobject_info))
537 return result;
538
2a206cc2 539 voltage_info_address = bios_get_image(&bp->base,
ae79c310
HW		 540 DATA_TABLES(voltageobject_info),
541 sizeof(struct atom_common_table_header));
542
543 header = (struct atom_common_table_header *) voltage_info_address;
544
545 get_atom_data_table_revision(header, &revision);
546
547 switch (revision.major) {
548 case 4:
549 if (revision.minor != 1)
550 break;
551 result = get_voltage_ddc_info_v4(&i2c_line, index, header,
552 voltage_info_address);
553 break;
554 }
555
556 if (result == BP_RESULT_OK)
557 result = bios_parser_get_thermal_ddc_info(dcb,
558 i2c_line, info);
559
560 return result;
561}
562
563static enum bp_result bios_parser_get_hpd_info(
564 struct dc_bios *dcb,
565 struct graphics_object_id id,
566 struct graphics_object_hpd_info *info)
567{
568 struct bios_parser *bp = BP_FROM_DCB(dcb);
569 struct atom_display_object_path_v2 *object;
570 struct atom_hpd_int_record *record = NULL;
571
572 if (!info)
573 return BP_RESULT_BADINPUT;
574
575 object = get_bios_object(bp, id);
576
577 if (!object)
578 return BP_RESULT_BADINPUT;
579
580 record = get_hpd_record(bp, object);
581
582 if (record != NULL) {
583 info->hpd_int_gpio_uid = record->pin_id;
584 info->hpd_active = record->plugin_pin_state;
585 return BP_RESULT_OK;
586 }
587
588 return BP_RESULT_NORECORD;
589}
590
591static struct atom_hpd_int_record *get_hpd_record(
592 struct bios_parser *bp,
593 struct atom_display_object_path_v2 *object)
594{
595 struct atom_common_record_header *header;
596 uint32_t offset;
597
598 if (!object) {
599 BREAK_TO_DEBUGGER(); /* Invalid object */
600 return NULL;
601 }
602
603 offset = le16_to_cpu(object->disp_recordoffset)
604 + bp->object_info_tbl_offset;
605
606 for (;;) {
607 header = GET_IMAGE(struct atom_common_record_header, offset);
608
609 if (!header)
610 return NULL;
611
612 if (header->record_type == LAST_RECORD_TYPE ||
613 !header->record_size)
614 break;
615
616 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
617 && sizeof(struct atom_hpd_int_record) <=
618 header->record_size)
619 return (struct atom_hpd_int_record *) header;
620
621 offset += header->record_size;
622 }
623
624 return NULL;
625}
626
627/**
628 * bios_parser_get_gpio_pin_info
629 * Get GpioPin information of input gpio id
630 *
631 * @param gpio_id, GPIO ID
632 * @param info, GpioPin information structure
633 * @return Bios parser result code
634 * @note
635 * to get the GPIO PIN INFO, we need:
636 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
637 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
638 * to get the registerA offset/mask
639 */
640static enum bp_result bios_parser_get_gpio_pin_info(
641 struct dc_bios *dcb,
642 uint32_t gpio_id,
643 struct gpio_pin_info *info)
644{
645 struct bios_parser *bp = BP_FROM_DCB(dcb);
646 struct atom_gpio_pin_lut_v2_1 *header;
647 uint32_t count = 0;
648 uint32_t i = 0;
649
650 if (!DATA_TABLES(gpio_pin_lut))
651 return BP_RESULT_BADBIOSTABLE;
652
653 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
654 DATA_TABLES(gpio_pin_lut));
655 if (!header)
656 return BP_RESULT_BADBIOSTABLE;
657
658 if (sizeof(struct atom_common_table_header) +
659 sizeof(struct atom_gpio_pin_lut_v2_1)
660 > le16_to_cpu(header->table_header.structuresize))
661 return BP_RESULT_BADBIOSTABLE;
662
663 if (header->table_header.content_revision != 1)
664 return BP_RESULT_UNSUPPORTED;
665
666 /* Temporary hard code gpio pin info */
667#if defined(FOR_SIMNOW_BOOT)
668 {
669 struct atom_gpio_pin_assignment gpio_pin[8] = {
670 {0x5db5, 0, 0, 1, 0},
671 {0x5db5, 8, 8, 2, 0},
672 {0x5db5, 0x10, 0x10, 3, 0},
673 {0x5db5, 0x18, 0x14, 4, 0},
674 {0x5db5, 0x1A, 0x18, 5, 0},
675 {0x5db5, 0x1C, 0x1C, 6, 0},
676 };
677
678 count = 6;
679 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
680 }
681#else
682 count = (le16_to_cpu(header->table_header.structuresize)
683 - sizeof(struct atom_common_table_header))
684 / sizeof(struct atom_gpio_pin_assignment);
685#endif
686 for (i = 0; i < count; ++i) {
687 if (header->gpio_pin[i].gpio_id != gpio_id)
688 continue;
689
690 info->offset =
691 (uint32_t) le16_to_cpu(
692 header->gpio_pin[i].data_a_reg_index);
693 info->offset_y = info->offset + 2;
694 info->offset_en = info->offset + 1;
695 info->offset_mask = info->offset - 1;
696
697 info->mask = (uint32_t) (1 <<
698 header->gpio_pin[i].gpio_bitshift);
699 info->mask_y = info->mask + 2;
700 info->mask_en = info->mask + 1;
701 info->mask_mask = info->mask - 1;
702
703 return BP_RESULT_OK;
704 }
705
706 return BP_RESULT_NORECORD;
707}
708
709static struct device_id device_type_from_device_id(uint16_t device_id)
710{
711
712 struct device_id result_device_id;
713
1e8635ea
ZF		 714 result_device_id.raw_device_tag = device_id;
715
ae79c310
HW		 716 switch (device_id) {
717 case ATOM_DISPLAY_LCD1_SUPPORT:
718 result_device_id.device_type = DEVICE_TYPE_LCD;
719 result_device_id.enum_id = 1;
720 break;
721
722 case ATOM_DISPLAY_DFP1_SUPPORT:
723 result_device_id.device_type = DEVICE_TYPE_DFP;
724 result_device_id.enum_id = 1;
725 break;
726
727 case ATOM_DISPLAY_DFP2_SUPPORT:
728 result_device_id.device_type = DEVICE_TYPE_DFP;
729 result_device_id.enum_id = 2;
730 break;
731
732 case ATOM_DISPLAY_DFP3_SUPPORT:
733 result_device_id.device_type = DEVICE_TYPE_DFP;
734 result_device_id.enum_id = 3;
735 break;
736
737 case ATOM_DISPLAY_DFP4_SUPPORT:
738 result_device_id.device_type = DEVICE_TYPE_DFP;
739 result_device_id.enum_id = 4;
740 break;
741
742 case ATOM_DISPLAY_DFP5_SUPPORT:
743 result_device_id.device_type = DEVICE_TYPE_DFP;
744 result_device_id.enum_id = 5;
745 break;
746
747 case ATOM_DISPLAY_DFP6_SUPPORT:
748 result_device_id.device_type = DEVICE_TYPE_DFP;
749 result_device_id.enum_id = 6;
750 break;
751
752 default:
753 BREAK_TO_DEBUGGER(); /* Invalid device Id */
754 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
755 result_device_id.enum_id = 0;
756 }
757 return result_device_id;
758}
759
760static enum bp_result bios_parser_get_device_tag(
761 struct dc_bios *dcb,
762 struct graphics_object_id connector_object_id,
763 uint32_t device_tag_index,
764 struct connector_device_tag_info *info)
765{
766 struct bios_parser *bp = BP_FROM_DCB(dcb);
767 struct atom_display_object_path_v2 *object;
768
769 if (!info)
770 return BP_RESULT_BADINPUT;
771
772 /* getBiosObject will return MXM object */
773 object = get_bios_object(bp, connector_object_id);
774
775 if (!object) {
776 BREAK_TO_DEBUGGER(); /* Invalid object id */
777 return BP_RESULT_BADINPUT;
778 }
779
780 info->acpi_device = 0; /* BIOS no longer provides this */
781 info->dev_id = device_type_from_device_id(object->device_tag);
782
783 return BP_RESULT_OK;
784}
785
786static enum bp_result get_ss_info_v4_1(
787 struct bios_parser *bp,
788 uint32_t id,
789 uint32_t index,
790 struct spread_spectrum_info *ss_info)
791{
792 enum bp_result result = BP_RESULT_OK;
793 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
ae79c310
HW		 794
795 if (!ss_info)
796 return BP_RESULT_BADINPUT;
797
798 if (!DATA_TABLES(dce_info))
799 return BP_RESULT_BADBIOSTABLE;
800
ae79c310
HW		 801 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
802 DATA_TABLES(dce_info));
803 if (!disp_cntl_tbl)
804 return BP_RESULT_BADBIOSTABLE;
805
ae79c310
HW		 806 ss_info->type.STEP_AND_DELAY_INFO = false;
807 ss_info->spread_percentage_divider = 1000;
808 /* BIOS no longer uses target clock. Always enable for now */
809 ss_info->target_clock_range = 0xffffffff;
810
811 switch (id) {
812 case AS_SIGNAL_TYPE_DVI:
813 ss_info->spread_spectrum_percentage =
814 disp_cntl_tbl->dvi_ss_percentage;
815 ss_info->spread_spectrum_range =
816 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
817 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
818 ss_info->type.CENTER_MODE = true;
819 break;
820 case AS_SIGNAL_TYPE_HDMI:
821 ss_info->spread_spectrum_percentage =
822 disp_cntl_tbl->hdmi_ss_percentage;
823 ss_info->spread_spectrum_range =
824 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
825 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
826 ss_info->type.CENTER_MODE = true;
827 break;
828 /* TODO LVDS not support anymore? */
829 case AS_SIGNAL_TYPE_DISPLAY_PORT:
830 ss_info->spread_spectrum_percentage =
831 disp_cntl_tbl->dp_ss_percentage;
832 ss_info->spread_spectrum_range =
833 disp_cntl_tbl->dp_ss_rate_10hz * 10;
834 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
835 ss_info->type.CENTER_MODE = true;
836 break;
837 case AS_SIGNAL_TYPE_GPU_PLL:
7d091f7a
HW		 838 /* atom_firmware: DAL only get data from dce_info table.
839 * if data within smu_info is needed for DAL, VBIOS should
840 * copy it into dce_info
841 */
842 result = BP_RESULT_UNSUPPORTED;
ae79c310
HW		 843 break;
844 default:
845 result = BP_RESULT_UNSUPPORTED;
846 }
847
848 return result;
849}
850
85a51eee
CL		 851static enum bp_result get_ss_info_v4_2(
852 struct bios_parser *bp,
853 uint32_t id,
854 uint32_t index,
855 struct spread_spectrum_info *ss_info)
856{
857 enum bp_result result = BP_RESULT_OK;
858 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
3f6d7435 859 struct atom_smu_info_v3_1 *smu_info = NULL;
85a51eee
CL		 860
861 if (!ss_info)
862 return BP_RESULT_BADINPUT;
863
864 if (!DATA_TABLES(dce_info))
865 return BP_RESULT_BADBIOSTABLE;
866
3f6d7435
HW		 867 if (!DATA_TABLES(smu_info))
868 return BP_RESULT_BADBIOSTABLE;
869
85a51eee
CL		 870 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
871 DATA_TABLES(dce_info));
872 if (!disp_cntl_tbl)
873 return BP_RESULT_BADBIOSTABLE;
874
3f6d7435
HW		 875 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
876 if (!smu_info)
877 return BP_RESULT_BADBIOSTABLE;
878
85a51eee
CL		 879 ss_info->type.STEP_AND_DELAY_INFO = false;
880 ss_info->spread_percentage_divider = 1000;
881 /* BIOS no longer uses target clock. Always enable for now */
882 ss_info->target_clock_range = 0xffffffff;
883
884 switch (id) {
885 case AS_SIGNAL_TYPE_DVI:
886 ss_info->spread_spectrum_percentage =
887 disp_cntl_tbl->dvi_ss_percentage;
888 ss_info->spread_spectrum_range =
889 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
890 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
891 ss_info->type.CENTER_MODE = true;
892 break;
893 case AS_SIGNAL_TYPE_HDMI:
894 ss_info->spread_spectrum_percentage =
895 disp_cntl_tbl->hdmi_ss_percentage;
896 ss_info->spread_spectrum_range =
897 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
898 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
899 ss_info->type.CENTER_MODE = true;
900 break;
901 /* TODO LVDS not support anymore? */
902 case AS_SIGNAL_TYPE_DISPLAY_PORT:
903 ss_info->spread_spectrum_percentage =
3f6d7435 904 smu_info->gpuclk_ss_percentage;
85a51eee 905 ss_info->spread_spectrum_range =
3f6d7435
HW		 906 smu_info->gpuclk_ss_rate_10hz * 10;
907 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
85a51eee
CL		 908 ss_info->type.CENTER_MODE = true;
909 break;
910 case AS_SIGNAL_TYPE_GPU_PLL:
7d091f7a
HW		 911 /* atom_firmware: DAL only get data from dce_info table.
912 * if data within smu_info is needed for DAL, VBIOS should
913 * copy it into dce_info
914 */
915 result = BP_RESULT_UNSUPPORTED;
85a51eee
CL		 916 break;
917 default:
918 result = BP_RESULT_UNSUPPORTED;
919 }
920
921 return result;
922}
923
ae79c310
HW		 924/**
925 * bios_parser_get_spread_spectrum_info
926 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
927 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
928 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
929 * ver 3.1,
930 * there is only one entry for each signal /ss id. However, there is
931 * no planning of supporting multiple spread Sprectum entry for EverGreen
932 * @param [in] this
933 * @param [in] signal, ASSignalType to be converted to info index
934 * @param [in] index, number of entries that match the converted info index
935 * @param [out] ss_info, sprectrum information structure,
936 * @return Bios parser result code
937 */
938static enum bp_result bios_parser_get_spread_spectrum_info(
939 struct dc_bios *dcb,
940 enum as_signal_type signal,
941 uint32_t index,
942 struct spread_spectrum_info *ss_info)
943{
944 struct bios_parser *bp = BP_FROM_DCB(dcb);
945 enum bp_result result = BP_RESULT_UNSUPPORTED;
946 struct atom_common_table_header *header;
947 struct atom_data_revision tbl_revision;
948
949 if (!ss_info) /* check for bad input */
950 return BP_RESULT_BADINPUT;
951
952 if (!DATA_TABLES(dce_info))
953 return BP_RESULT_UNSUPPORTED;
954
955 header = GET_IMAGE(struct atom_common_table_header,
956 DATA_TABLES(dce_info));
957 get_atom_data_table_revision(header, &tbl_revision);
958
959 switch (tbl_revision.major) {
960 case 4:
961 switch (tbl_revision.minor) {
962 case 1:
963 return get_ss_info_v4_1(bp, signal, index, ss_info);
85a51eee
CL		 964 case 2:
965 return get_ss_info_v4_2(bp, signal, index, ss_info);
ae79c310
HW		 966 default:
967 break;
968 }
969 break;
970 default:
971 break;
972 }
973 /* there can not be more then one entry for SS Info table */
974 return result;
975}
976
977static enum bp_result get_embedded_panel_info_v2_1(
978 struct bios_parser *bp,
979 struct embedded_panel_info *info)
980{
981 struct lcd_info_v2_1 *lvds;
982
983 if (!info)
984 return BP_RESULT_BADINPUT;
985
986 if (!DATA_TABLES(lcd_info))
987 return BP_RESULT_UNSUPPORTED;
988
989 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
990
991 if (!lvds)
992 return BP_RESULT_BADBIOSTABLE;
993
994 /* TODO: previous vv1_3, should v2_1 */
995 if (!((lvds->table_header.format_revision == 2)
996 && (lvds->table_header.content_revision >= 1)))
997 return BP_RESULT_UNSUPPORTED;
998
999 memset(info, 0, sizeof(struct embedded_panel_info));
1000
1001 /* We need to convert from 10KHz units into KHz units */
1002 info->lcd_timing.pixel_clk =
1003 le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
1004 /* usHActive does not include borders, according to VBIOS team */
1005 info->lcd_timing.horizontal_addressable =
1006 le16_to_cpu(lvds->lcd_timing.h_active);
1007 /* usHBlanking_Time includes borders, so we should really be
1008 * subtractingborders duing this translation, but LVDS generally
1009 * doesn't have borders, so we should be okay leaving this as is for
1010 * now. May need to revisit if we ever have LVDS with borders
1011 */
1012 info->lcd_timing.horizontal_blanking_time =
1013 le16_to_cpu(lvds->lcd_timing.h_blanking_time);
1014 /* usVActive does not include borders, according to VBIOS team*/
1015 info->lcd_timing.vertical_addressable =
1016 le16_to_cpu(lvds->lcd_timing.v_active);
1017 /* usVBlanking_Time includes borders, so we should really be
1018 * subtracting borders duing this translation, but LVDS generally
1019 * doesn't have borders, so we should be okay leaving this as is for
1020 * now. May need to revisit if we ever have LVDS with borders
1021 */
1022 info->lcd_timing.vertical_blanking_time =
1023 le16_to_cpu(lvds->lcd_timing.v_blanking_time);
1024 info->lcd_timing.horizontal_sync_offset =
1025 le16_to_cpu(lvds->lcd_timing.h_sync_offset);
1026 info->lcd_timing.horizontal_sync_width =
1027 le16_to_cpu(lvds->lcd_timing.h_sync_width);
1028 info->lcd_timing.vertical_sync_offset =
1029 le16_to_cpu(lvds->lcd_timing.v_sync_offset);
1030 info->lcd_timing.vertical_sync_width =
1031 le16_to_cpu(lvds->lcd_timing.v_syncwidth);
1032 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
1033 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
1034
1035 /* not provided by VBIOS */
1036 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
1037
1038 info->lcd_timing.misc_info.H_SYNC_POLARITY =
1039 ~(uint32_t)
1040 (lvds->lcd_timing.miscinfo & ATOM_HSYNC_POLARITY);
1041 info->lcd_timing.misc_info.V_SYNC_POLARITY =
1042 ~(uint32_t)
1043 (lvds->lcd_timing.miscinfo & ATOM_VSYNC_POLARITY);
1044
1045 /* not provided by VBIOS */
1046 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
1047
1048 info->lcd_timing.misc_info.H_REPLICATION_BY2 =
085b017b 1049 !!(lvds->lcd_timing.miscinfo & ATOM_H_REPLICATIONBY2);
ae79c310 1050 info->lcd_timing.misc_info.V_REPLICATION_BY2 =
085b017b 1051 !!(lvds->lcd_timing.miscinfo & ATOM_V_REPLICATIONBY2);
ae79c310 1052 info->lcd_timing.misc_info.COMPOSITE_SYNC =
085b017b 1053 !!(lvds->lcd_timing.miscinfo & ATOM_COMPOSITESYNC);
ae79c310 1054 info->lcd_timing.misc_info.INTERLACE =
085b017b 1055 !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
ae79c310
HW		 1056
1057 /* not provided by VBIOS*/
1058 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
1059 /* not provided by VBIOS*/
1060 info->ss_id = 0;
1061
1062 info->realtek_eDPToLVDS =
085b017b 1063 !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
ae79c310
HW		 1064
1065 return BP_RESULT_OK;
1066}
1067
1068static enum bp_result bios_parser_get_embedded_panel_info(
1069 struct dc_bios *dcb,
1070 struct embedded_panel_info *info)
1071{
1072 struct bios_parser *bp = BP_FROM_DCB(dcb);
1073 struct atom_common_table_header *header;
1074 struct atom_data_revision tbl_revision;
1075
1076 if (!DATA_TABLES(lcd_info))
1077 return BP_RESULT_FAILURE;
1078
1079 header = GET_IMAGE(struct atom_common_table_header,
1080 DATA_TABLES(lcd_info));
1081
1082 if (!header)
1083 return BP_RESULT_BADBIOSTABLE;
1084
1085 get_atom_data_table_revision(header, &tbl_revision);
1086
1087
1088 switch (tbl_revision.major) {
1089 case 2:
1090 switch (tbl_revision.minor) {
1091 case 1:
1092 return get_embedded_panel_info_v2_1(bp, info);
1093 default:
1094 break;
1095 }
1096 default:
1097 break;
1098 }
1099
1100 return BP_RESULT_FAILURE;
1101}
1102
1103static uint32_t get_support_mask_for_device_id(struct device_id device_id)
1104{
1105 enum dal_device_type device_type = device_id.device_type;
1106 uint32_t enum_id = device_id.enum_id;
1107
1108 switch (device_type) {
1109 case DEVICE_TYPE_LCD:
1110 switch (enum_id) {
1111 case 1:
1112 return ATOM_DISPLAY_LCD1_SUPPORT;
1113 default:
1114 break;
1115 }
1116 break;
1117 case DEVICE_TYPE_DFP:
1118 switch (enum_id) {
1119 case 1:
1120 return ATOM_DISPLAY_DFP1_SUPPORT;
1121 case 2:
1122 return ATOM_DISPLAY_DFP2_SUPPORT;
1123 case 3:
1124 return ATOM_DISPLAY_DFP3_SUPPORT;
1125 case 4:
1126 return ATOM_DISPLAY_DFP4_SUPPORT;
1127 case 5:
1128 return ATOM_DISPLAY_DFP5_SUPPORT;
1129 case 6:
1130 return ATOM_DISPLAY_DFP6_SUPPORT;
1131 default:
1132 break;
1133 }
1134 break;
1135 default:
1136 break;
1137 };
1138
1139 /* Unidentified device ID, return empty support mask. */
1140 return 0;
1141}
1142
1143static bool bios_parser_is_device_id_supported(
1144 struct dc_bios *dcb,
1145 struct device_id id)
1146{
1147 struct bios_parser *bp = BP_FROM_DCB(dcb);
1148
1149 uint32_t mask = get_support_mask_for_device_id(id);
1150
1151 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
1152 mask) != 0;
1153}
1154
1155static void bios_parser_post_init(
1156 struct dc_bios *dcb)
1157{
1158 /* TODO for OPM module. Need implement later */
1159}
1160
1161static uint32_t bios_parser_get_ss_entry_number(
1162 struct dc_bios *dcb,
1163 enum as_signal_type signal)
1164{
1165 /* TODO: DAL2 atomfirmware implementation does not need this.
1166 * why DAL3 need this?
1167 */
1168 return 1;
1169}
1170
1171static enum bp_result bios_parser_transmitter_control(
1172 struct dc_bios *dcb,
1173 struct bp_transmitter_control *cntl)
1174{
1175 struct bios_parser *bp = BP_FROM_DCB(dcb);
1176
1177 if (!bp->cmd_tbl.transmitter_control)
1178 return BP_RESULT_FAILURE;
1179
1180 return bp->cmd_tbl.transmitter_control(bp, cntl);
1181}
1182
1183static enum bp_result bios_parser_encoder_control(
1184 struct dc_bios *dcb,
1185 struct bp_encoder_control *cntl)
1186{
1187 struct bios_parser *bp = BP_FROM_DCB(dcb);
1188
1189 if (!bp->cmd_tbl.dig_encoder_control)
1190 return BP_RESULT_FAILURE;
1191
1192 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1193}
1194
1195static enum bp_result bios_parser_set_pixel_clock(
1196 struct dc_bios *dcb,
1197 struct bp_pixel_clock_parameters *bp_params)
1198{
1199 struct bios_parser *bp = BP_FROM_DCB(dcb);
1200
1201 if (!bp->cmd_tbl.set_pixel_clock)
1202 return BP_RESULT_FAILURE;
1203
1204 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1205}
1206
1207static enum bp_result bios_parser_set_dce_clock(
1208 struct dc_bios *dcb,
1209 struct bp_set_dce_clock_parameters *bp_params)
1210{
1211 struct bios_parser *bp = BP_FROM_DCB(dcb);
1212
1213 if (!bp->cmd_tbl.set_dce_clock)
1214 return BP_RESULT_FAILURE;
1215
1216 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1217}
1218
1219static unsigned int bios_parser_get_smu_clock_info(
1220 struct dc_bios *dcb)
1221{
1222 struct bios_parser *bp = BP_FROM_DCB(dcb);
1223
1224 if (!bp->cmd_tbl.get_smu_clock_info)
1225 return BP_RESULT_FAILURE;
1226
316178f0 1227 return bp->cmd_tbl.get_smu_clock_info(bp, 0);
ae79c310
HW		 1228}
1229
1230static enum bp_result bios_parser_program_crtc_timing(
1231 struct dc_bios *dcb,
1232 struct bp_hw_crtc_timing_parameters *bp_params)
1233{
1234 struct bios_parser *bp = BP_FROM_DCB(dcb);
1235
1236 if (!bp->cmd_tbl.set_crtc_timing)
1237 return BP_RESULT_FAILURE;
1238
1239 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1240}
1241
1242static enum bp_result bios_parser_enable_crtc(
1243 struct dc_bios *dcb,
1244 enum controller_id id,
1245 bool enable)
1246{
1247 struct bios_parser *bp = BP_FROM_DCB(dcb);
1248
1249 if (!bp->cmd_tbl.enable_crtc)
1250 return BP_RESULT_FAILURE;
1251
1252 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1253}
1254
1255static enum bp_result bios_parser_crtc_source_select(
1256 struct dc_bios *dcb,
1257 struct bp_crtc_source_select *bp_params)
1258{
1259 struct bios_parser *bp = BP_FROM_DCB(dcb);
1260
1261 if (!bp->cmd_tbl.select_crtc_source)
1262 return BP_RESULT_FAILURE;
1263
1264 return bp->cmd_tbl.select_crtc_source(bp, bp_params);
1265}
1266
1267static enum bp_result bios_parser_enable_disp_power_gating(
1268 struct dc_bios *dcb,
1269 enum controller_id controller_id,
1270 enum bp_pipe_control_action action)
1271{
1272 struct bios_parser *bp = BP_FROM_DCB(dcb);
1273
1274 if (!bp->cmd_tbl.enable_disp_power_gating)
1275 return BP_RESULT_FAILURE;
1276
1277 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1278 action);
1279}
1280
1281static bool bios_parser_is_accelerated_mode(
1282 struct dc_bios *dcb)
1283{
1284 return bios_is_accelerated_mode(dcb);
1285}
1286
c5fc7f59
CL		 1287static uint32_t bios_parser_get_vga_enabled_displays(
1288 struct dc_bios *bios)
1289{
1290 return bios_get_vga_enabled_displays(bios);
1291}
1292
ae79c310
HW		 1293
1294/**
1295 * bios_parser_set_scratch_critical_state
1296 *
1297 * @brief
1298 * update critical state bit in VBIOS scratch register
1299 *
1300 * @param
1301 * bool - to set or reset state
1302 */
1303static void bios_parser_set_scratch_critical_state(
1304 struct dc_bios *dcb,
1305 bool state)
1306{
1307 bios_set_scratch_critical_state(dcb, state);
1308}
1309
1310static enum bp_result bios_parser_get_firmware_info(
1311 struct dc_bios *dcb,
1515a47b 1312 struct dc_firmware_info *info)
ae79c310
HW		 1313{
1314 struct bios_parser *bp = BP_FROM_DCB(dcb);
1315 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1316 struct atom_common_table_header *header;
1317
1318 struct atom_data_revision revision;
1319
1320 if (info && DATA_TABLES(firmwareinfo)) {
1321 header = GET_IMAGE(struct atom_common_table_header,
1322 DATA_TABLES(firmwareinfo));
1323 get_atom_data_table_revision(header, &revision);
1324 switch (revision.major) {
1325 case 3:
1326 switch (revision.minor) {
1327 case 1:
1328 result = get_firmware_info_v3_1(bp, info);
1329 break;
6e65fb86
HW		 1330 case 2:
1331 result = get_firmware_info_v3_2(bp, info);
1332 break;
ae79c310
HW		 1333 default:
1334 break;
1335 }
1336 break;
1337 default:
1338 break;
1339 }
1340 }
1341
1342 return result;
1343}
1344
1345static enum bp_result get_firmware_info_v3_1(
1346 struct bios_parser *bp,
1515a47b 1347 struct dc_firmware_info *info)
ae79c310
HW		 1348{
1349 struct atom_firmware_info_v3_1 *firmware_info;
1350 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1351
1352 if (!info)
1353 return BP_RESULT_BADINPUT;
1354
1355 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1356 DATA_TABLES(firmwareinfo));
1357
1358 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1359 DATA_TABLES(dce_info));
1360
1361 if (!firmware_info || !dce_info)
1362 return BP_RESULT_BADBIOSTABLE;
1363
1364 memset(info, 0, sizeof(*info));
1365
1366 /* Pixel clock pll information. */
1367 /* We need to convert from 10KHz units into KHz units */
1368 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1369 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1370
1371 /* 27MHz for Vega10: */
1372 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1373
1374 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1375 if (info->pll_info.crystal_frequency == 0)
1376 info->pll_info.crystal_frequency = 27000;
85a51eee 1377 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
ae79c310
HW		 1378 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1379 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1380
1381 /* Get GPU PLL VCO Clock */
1382
1383 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1384 /* VBIOS gives in 10KHz */
1385 info->smu_gpu_pll_output_freq =
316178f0 1386 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
ae79c310
HW		 1387 }
1388
bf5563ed 1389 return BP_RESULT_OK;
ae79c310
HW		 1390}
1391
6e65fb86
HW		 1392static enum bp_result get_firmware_info_v3_2(
1393 struct bios_parser *bp,
1394 struct dc_firmware_info *info)
1395{
1396 struct atom_firmware_info_v3_2 *firmware_info;
1397 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1398 struct atom_common_table_header *header;
1399 struct atom_data_revision revision;
1400 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1401 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1402
1403 if (!info)
1404 return BP_RESULT_BADINPUT;
1405
1406 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1407 DATA_TABLES(firmwareinfo));
1408
1409 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1410 DATA_TABLES(dce_info));
1411
1412 if (!firmware_info || !dce_info)
1413 return BP_RESULT_BADBIOSTABLE;
1414
1415 memset(info, 0, sizeof(*info));
1416
1417 header = GET_IMAGE(struct atom_common_table_header,
1418 DATA_TABLES(smu_info));
1419 get_atom_data_table_revision(header, &revision);
1420
1421 if (revision.minor == 2) {
1422 /* Vega12 */
1423 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1424 DATA_TABLES(smu_info));
1425
1426 if (!smu_info_v3_2)
1427 return BP_RESULT_BADBIOSTABLE;
1428
1429 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1430 } else if (revision.minor == 3) {
1431 /* Vega20 */
1432 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1433 DATA_TABLES(smu_info));
1434
1435 if (!smu_info_v3_3)
1436 return BP_RESULT_BADBIOSTABLE;
1437
1438 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1439 }
1440
1441 // We need to convert from 10KHz units into KHz units.
1442 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1443
1444 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1445 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1446 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1447 if (info->pll_info.crystal_frequency == 0) {
1448 if (revision.minor == 2)
1449 info->pll_info.crystal_frequency = 27000;
1450 else if (revision.minor == 3)
1451 info->pll_info.crystal_frequency = 100000;
1452 }
1453 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1454 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1455 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1456
1457 /* Get GPU PLL VCO Clock */
1458 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1459 if (revision.minor == 2)
1460 info->smu_gpu_pll_output_freq =
1461 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1462 else if (revision.minor == 3)
1463 info->smu_gpu_pll_output_freq =
1464 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1465 }
1466
1467 return BP_RESULT_OK;
1468}
1469
ae79c310
HW		 1470static enum bp_result bios_parser_get_encoder_cap_info(
1471 struct dc_bios *dcb,
1472 struct graphics_object_id object_id,
1473 struct bp_encoder_cap_info *info)
1474{
1475 struct bios_parser *bp = BP_FROM_DCB(dcb);
1476 struct atom_display_object_path_v2 *object;
1477 struct atom_encoder_caps_record *record = NULL;
1478
1479 if (!info)
1480 return BP_RESULT_BADINPUT;
1481
1482 object = get_bios_object(bp, object_id);
1483
1484 if (!object)
1485 return BP_RESULT_BADINPUT;
1486
1487 record = get_encoder_cap_record(bp, object);
1488 if (!record)
1489 return BP_RESULT_NORECORD;
1490
1491 info->DP_HBR2_CAP = (record->encodercaps &
1492 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
1493 info->DP_HBR2_EN = (record->encodercaps &
1494 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
1495 info->DP_HBR3_EN = (record->encodercaps &
1496 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
1497 info->HDMI_6GB_EN = (record->encodercaps &
1498 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
1499
1500 return BP_RESULT_OK;
1501}
1502
1503
1504static struct atom_encoder_caps_record *get_encoder_cap_record(
1505 struct bios_parser *bp,
1506 struct atom_display_object_path_v2 *object)
1507{
1508 struct atom_common_record_header *header;
1509 uint32_t offset;
1510
1511 if (!object) {
1512 BREAK_TO_DEBUGGER(); /* Invalid object */
1513 return NULL;
1514 }
1515
1516 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
1517
1518 for (;;) {
1519 header = GET_IMAGE(struct atom_common_record_header, offset);
1520
1521 if (!header)
1522 return NULL;
1523
1524 offset += header->record_size;
1525
1526 if (header->record_type == LAST_RECORD_TYPE ||
1527 !header->record_size)
1528 break;
1529
1530 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
1531 continue;
1532
1533 if (sizeof(struct atom_encoder_caps_record) <=
1534 header->record_size)
1535 return (struct atom_encoder_caps_record *)header;
1536 }
1537
1538 return NULL;
1539}
1540
1541/*
1542 * get_integrated_info_v11
1543 *
1544 * @brief
1545 * Get V8 integrated BIOS information
1546 *
1547 * @param
1548 * bios_parser *bp - [in]BIOS parser handler to get master data table
1549 * integrated_info *info - [out] store and output integrated info
1550 *
1551 * @return
1552 * enum bp_result - BP_RESULT_OK if information is available,
1553 * BP_RESULT_BADBIOSTABLE otherwise.
1554 */
1555static enum bp_result get_integrated_info_v11(
1556 struct bios_parser *bp,
1557 struct integrated_info *info)
1558{
1559 struct atom_integrated_system_info_v1_11 *info_v11;
1560 uint32_t i;
1561
1562 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
1563 DATA_TABLES(integratedsysteminfo));
1564
1565 if (info_v11 == NULL)
c1199962 1566 return BP_RESULT_BADBIOSTABLE;
ae79c310
HW		 1567
1568 info->gpu_cap_info =
1569 le32_to_cpu(info_v11->gpucapinfo);
1570 /*
1571 * system_config: Bit[0] = 0 : PCIE power gating disabled
1572 * = 1 : PCIE power gating enabled
1573 * Bit[1] = 0 : DDR-PLL shut down disabled
1574 * = 1 : DDR-PLL shut down enabled
1575 * Bit[2] = 0 : DDR-PLL power down disabled
1576 * = 1 : DDR-PLL power down enabled
1577 */
1578 info->system_config = le32_to_cpu(info_v11->system_config);
1579 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
1580 info->memory_type = info_v11->memorytype;
1581 info->ma_channel_number = info_v11->umachannelnumber;
1582 info->lvds_ss_percentage =
1583 le16_to_cpu(info_v11->lvds_ss_percentage);
1584 info->lvds_sspread_rate_in_10hz =
1585 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
1586 info->hdmi_ss_percentage =
1587 le16_to_cpu(info_v11->hdmi_ss_percentage);
1588 info->hdmi_sspread_rate_in_10hz =
1589 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
1590 info->dvi_ss_percentage =
1591 le16_to_cpu(info_v11->dvi_ss_percentage);
1592 info->dvi_sspread_rate_in_10_hz =
1593 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
1594 info->lvds_misc = info_v11->lvds_misc;
1595 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
1596 info->ext_disp_conn_info.gu_id[i] =
1597 info_v11->extdispconninfo.guid[i];
1598 }
1599
1600 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
1601 info->ext_disp_conn_info.path[i].device_connector_id =
1602 object_id_from_bios_object_id(
1603 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
1604
1605 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
1606 object_id_from_bios_object_id(
1607 le16_to_cpu(
1608 info_v11->extdispconninfo.path[i].ext_encoder_objid));
1609
1610 info->ext_disp_conn_info.path[i].device_tag =
1611 le16_to_cpu(
1612 info_v11->extdispconninfo.path[i].device_tag);
1613 info->ext_disp_conn_info.path[i].device_acpi_enum =
1614 le16_to_cpu(
1615 info_v11->extdispconninfo.path[i].device_acpi_enum);
1616 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
1617 info_v11->extdispconninfo.path[i].auxddclut_index;
1618 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
1619 info_v11->extdispconninfo.path[i].hpdlut_index;
1620 info->ext_disp_conn_info.path[i].channel_mapping.raw =
1621 info_v11->extdispconninfo.path[i].channelmapping;
1e8635ea
ZF		 1622 info->ext_disp_conn_info.path[i].caps =
1623 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
ae79c310
HW		 1624 }
1625 info->ext_disp_conn_info.checksum =
1626 info_v11->extdispconninfo.checksum;
1627
1e8635ea
ZF		 1628 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
1629 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
1630 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
1631 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
1632 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1633 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
1634 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1635 }
1636 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
1637 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
1638 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1639 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1640 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1641 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1642 }
1643
1644 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
1645 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
1646 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
1647 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
1648 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1649 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
1650 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1651 }
1652 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
1653 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
1654 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1655 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1656 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1657 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1658 }
1659
1660 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
1661 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
1662 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
1663 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
1664 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1665 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
1666 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1667 }
1668 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
1669 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
1670 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1671 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1672 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1673 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1674 }
1675
1676 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
1677 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
1678 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
1679 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
1680 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1681 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
1682 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1683 }
1684 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
1685 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
1686 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1687 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1688 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1689 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1690 }
1691
1692
ae79c310
HW		 1693 /** TODO - review **/
1694 #if 0
1695 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
1696 * 10;
1697 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
1698 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
1699
1700 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1701 /* Convert [10KHz] into [KHz] */
1702 info->disp_clk_voltage[i].max_supported_clk =
1703 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
1704 ulMaximumSupportedCLK) * 10;
1705 info->disp_clk_voltage[i].voltage_index =
1706 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
1707 }
1708
1709 info->boot_up_req_display_vector =
1710 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
1711 info->boot_up_nb_voltage =
1712 le16_to_cpu(info_v11->usBootUpNBVoltage);
1713 info->ext_disp_conn_info_offset =
1714 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
1715 info->gmc_restore_reset_time =
1716 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
1717 info->minimum_n_clk =
1718 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
1719 for (i = 1; i < 4; ++i)
1720 info->minimum_n_clk =
1721 info->minimum_n_clk <
1722 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
1723 info->minimum_n_clk : le32_to_cpu(
1724 info_v11->ulNbpStateNClkFreq[i]);
1725
1726 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
1727 info->ddr_dll_power_up_time =
1728 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
1729 info->ddr_pll_power_up_time =
1730 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
1731 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
1732 info->max_lvds_pclk_freq_in_single_link =
1733 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1734 info->max_lvds_pclk_freq_in_single_link =
1735 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1736 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
1737 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
1738 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
1739 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
1740 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
1741 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
1742 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
1743 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
1744 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
1745 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
1746 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
1747 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
1748 info->lvds_off_to_on_delay_in_4ms =
1749 info_v11->ucLVDSOffToOnDelay_in4Ms;
1750 info->lvds_bit_depth_control_val =
1751 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
1752
1753 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
1754 /* Convert [10KHz] into [KHz] */
1755 info->avail_s_clk[i].supported_s_clk =
1756 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
1757 * 10;
1758 info->avail_s_clk[i].voltage_index =
1759 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
1760 info->avail_s_clk[i].voltage_id =
1761 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
1762 }
1763 #endif /* TODO*/
1764
1765 return BP_RESULT_OK;
1766}
1767
1768
1769/*
1770 * construct_integrated_info
1771 *
1772 * @brief
1773 * Get integrated BIOS information based on table revision
1774 *
1775 * @param
1776 * bios_parser *bp - [in]BIOS parser handler to get master data table
1777 * integrated_info *info - [out] store and output integrated info
1778 *
1779 * @return
1780 * enum bp_result - BP_RESULT_OK if information is available,
1781 * BP_RESULT_BADBIOSTABLE otherwise.
1782 */
1783static enum bp_result construct_integrated_info(
1784 struct bios_parser *bp,
1785 struct integrated_info *info)
1786{
1787 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1788
1789 struct atom_common_table_header *header;
1790 struct atom_data_revision revision;
1791
1792 struct clock_voltage_caps temp = {0, 0};
1793 uint32_t i;
1794 uint32_t j;
1795
1796 if (info && DATA_TABLES(integratedsysteminfo)) {
1797 header = GET_IMAGE(struct atom_common_table_header,
1798 DATA_TABLES(integratedsysteminfo));
1799
1800 get_atom_data_table_revision(header, &revision);
1801
1802 /* Don't need to check major revision as they are all 1 */
1803 switch (revision.minor) {
1804 case 11:
1805 result = get_integrated_info_v11(bp, info);
1806 break;
1807 default:
1808 return result;
1809 }
1810 }
1811
1812 if (result != BP_RESULT_OK)
1813 return result;
1814
1815 /* Sort voltage table from low to high*/
1816 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1817 for (j = i; j > 0; --j) {
1818 if (info->disp_clk_voltage[j].max_supported_clk <
1819 info->disp_clk_voltage[j-1].max_supported_clk
1820 ) {
1821 /* swap j and j - 1*/
1822 temp = info->disp_clk_voltage[j-1];
1823 info->disp_clk_voltage[j-1] =
1824 info->disp_clk_voltage[j];
1825 info->disp_clk_voltage[j] = temp;
1826 }
1827 }
1828 }
1829
1830 return result;
1831}
1832
1833static struct integrated_info *bios_parser_create_integrated_info(
1834 struct dc_bios *dcb)
1835{
1836 struct bios_parser *bp = BP_FROM_DCB(dcb);
1837 struct integrated_info *info = NULL;
1838
2004f45e 1839 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
ae79c310
HW		 1840
1841 if (info == NULL) {
1842 ASSERT_CRITICAL(0);
1843 return NULL;
1844 }
1845
1846 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
c1199962 1847 return info;
ae79c310 1848
2004f45e 1849 kfree(info);
ae79c310
HW		 1850
1851 return NULL;
1852}
1853
1854static const struct dc_vbios_funcs vbios_funcs = {
1855 .get_connectors_number = bios_parser_get_connectors_number,
1856
1857 .get_encoder_id = bios_parser_get_encoder_id,
1858
1859 .get_connector_id = bios_parser_get_connector_id,
1860
1861 .get_dst_number = bios_parser_get_dst_number,
1862
1863 .get_src_obj = bios_parser_get_src_obj,
1864
1865 .get_dst_obj = bios_parser_get_dst_obj,
1866
1867 .get_i2c_info = bios_parser_get_i2c_info,
1868
1869 .get_voltage_ddc_info = bios_parser_get_voltage_ddc_info,
1870
1871 .get_thermal_ddc_info = bios_parser_get_thermal_ddc_info,
1872
1873 .get_hpd_info = bios_parser_get_hpd_info,
1874
1875 .get_device_tag = bios_parser_get_device_tag,
1876
1877 .get_firmware_info = bios_parser_get_firmware_info,
1878
1879 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
1880
1881 .get_ss_entry_number = bios_parser_get_ss_entry_number,
1882
1883 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
1884
1885 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
1886
1887 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
1888
1889 .is_device_id_supported = bios_parser_is_device_id_supported,
1890
1891
1892
1893 .is_accelerated_mode = bios_parser_is_accelerated_mode,
c5fc7f59 1894 .get_vga_enabled_displays = bios_parser_get_vga_enabled_displays,
ae79c310
HW		 1895
1896 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
1897
1898
1899/* COMMANDS */
1900 .encoder_control = bios_parser_encoder_control,
1901
1902 .transmitter_control = bios_parser_transmitter_control,
1903
1904 .enable_crtc = bios_parser_enable_crtc,
1905
1906 .set_pixel_clock = bios_parser_set_pixel_clock,
1907
1908 .set_dce_clock = bios_parser_set_dce_clock,
1909
1910 .program_crtc_timing = bios_parser_program_crtc_timing,
1911
1912 /* .blank_crtc = bios_parser_blank_crtc, */
1913
1914 .crtc_source_select = bios_parser_crtc_source_select,
1915
1916 /* .external_encoder_control = bios_parser_external_encoder_control, */
1917
1918 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
1919
1920 .post_init = bios_parser_post_init,
1921
1922 .bios_parser_destroy = firmware_parser_destroy,
1923
1924 .get_smu_clock_info = bios_parser_get_smu_clock_info,
1925};
1926
1927static bool bios_parser_construct(
1928 struct bios_parser *bp,
1929 struct bp_init_data *init,
1930 enum dce_version dce_version)
1931{
1932 uint16_t *rom_header_offset = NULL;
1933 struct atom_rom_header_v2_2 *rom_header = NULL;
1934 struct display_object_info_table_v1_4 *object_info_tbl;
1935 struct atom_data_revision tbl_rev = {0};
1936
1937 if (!init)
1938 return false;
1939
1940 if (!init->bios)
1941 return false;
1942
1943 bp->base.funcs = &vbios_funcs;
1944 bp->base.bios = init->bios;
1945 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
1946
1947 bp->base.ctx = init->ctx;
1948
1949 bp->base.bios_local_image = NULL;
1950
1951 rom_header_offset =
1952 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
1953
1954 if (!rom_header_offset)
1955 return false;
1956
1957 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
1958
1959 if (!rom_header)
1960 return false;
1961
1962 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
1963 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
1964 return false;
1965
1966 bp->master_data_tbl =
1967 GET_IMAGE(struct atom_master_data_table_v2_1,
1968 rom_header->masterdatatable_offset);
1969
1970 if (!bp->master_data_tbl)
1971 return false;
1972
1973 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
1974
1975 if (!bp->object_info_tbl_offset)
1976 return false;
1977
1978 object_info_tbl =
1979 GET_IMAGE(struct display_object_info_table_v1_4,
1980 bp->object_info_tbl_offset);
1981
1982 if (!object_info_tbl)
1983 return false;
1984
1985 get_atom_data_table_revision(&object_info_tbl->table_header,
1986 &bp->object_info_tbl.revision);
1987
1988 if (bp->object_info_tbl.revision.major == 1
1989 && bp->object_info_tbl.revision.minor >= 4) {
1990 struct display_object_info_table_v1_4 *tbl_v1_4;
1991
1992 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
1993 bp->object_info_tbl_offset);
1994 if (!tbl_v1_4)
1995 return false;
1996
1997 bp->object_info_tbl.v1_4 = tbl_v1_4;
1998 } else
1999 return false;
2000
2001 dal_firmware_parser_init_cmd_tbl(bp);
2002 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
2003
2004 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
2005
2006 return true;
2007}
2008
2009struct dc_bios *firmware_parser_create(
2010 struct bp_init_data *init,
2011 enum dce_version dce_version)
2012{
2013 struct bios_parser *bp = NULL;
2014
2004f45e 2015 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
ae79c310
HW		 2016 if (!bp)
2017 return NULL;
2018
2019 if (bios_parser_construct(bp, init, dce_version))
2020 return &bp->base;
2021
2004f45e 2022 kfree(bp);
ae79c310
HW		 2023 return NULL;
2024}
2025
2026
Linux 6.x block layer and io_uring tree(s)