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Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_helpers.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
c6a83708
ML		 26#include <acpi/video.h>
27
4562236b
HW		 28#include <linux/string.h>
29#include <linux/acpi.h>
4562236b
HW		 30#include <linux/i2c.h>
31
4d07b0bc 32#include <drm/drm_atomic.h>
fcd70cd3 33#include <drm/drm_probe_helper.h>
4562236b
HW		 34#include <drm/amdgpu_drm.h>
35#include <drm/drm_edid.h>
191dc439 36#include <drm/drm_fixed.h>
4562236b
HW		 37
38#include "dm_services.h"
39#include "amdgpu.h"
40#include "dc.h"
41#include "amdgpu_dm.h"
42#include "amdgpu_dm_irq.h"
f9c8742c 43#include "amdgpu_dm_mst_types.h"
028c4ccf
QZ		 44#include "dpcd_defs.h"
45#include "dc/inc/core_types.h"
4562236b
HW		 46
47#include "dm_helpers.h"
9cc37043 48#include "ddc_service_types.h"
8a79f7cd 49#include "clk_mgr.h"
4562236b 50
613a7956
AP		 51static u32 edid_extract_panel_id(struct edid *edid)
52{
53 return (u32)edid->mfg_id[0] << 24 |
54 (u32)edid->mfg_id[1] << 16 |
55 (u32)EDID_PRODUCT_ID(edid);
56}
57
41b83047 58static void apply_edid_quirks(struct drm_device *dev, struct edid *edid, struct dc_edid_caps *edid_caps)
613a7956
AP		 59{
60 uint32_t panel_id = edid_extract_panel_id(edid);
61
62 switch (panel_id) {
41b83047
AP		 63 /* Workaround for monitors that need a delay after detecting the link */
64 case drm_edid_encode_panel_id('G', 'B', 'T', 0x3215):
65 drm_dbg_driver(dev, "Add 10s delay for link detection for panel id %X\n", panel_id);
66 edid_caps->panel_patch.wait_after_dpcd_poweroff_ms = 10000;
67 break;
613a7956
AP		 68 /* Workaround for some monitors which does not work well with FAMS */
69 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
70 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
71 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
a89b5303 72 drm_dbg_driver(dev, "Disabling FAMS on monitor with panel id %X\n", panel_id);
613a7956
AP		 73 edid_caps->panel_patch.disable_fams = true;
74 break;
3d71a872
IL		 75 /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */
76 case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
77 case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
b7cdccc6
RL		 78 case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A):
79 case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1):
7c0ac603 80 case drm_edid_encode_panel_id('M', 'S', 'F', 0x1003):
a89b5303 81 drm_dbg_driver(dev, "Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);
3d71a872
IL		 82 edid_caps->panel_patch.remove_sink_ext_caps = true;
83 break;
4d425728 84 case drm_edid_encode_panel_id('S', 'D', 'C', 0x4154):
a89b5303 85 drm_dbg_driver(dev, "Disabling VSC on monitor with panel id %X\n", panel_id);
4d425728
AH		 86 edid_caps->panel_patch.disable_colorimetry = true;
87 break;
613a7956
AP		 88 default:
89 return;
90 }
91}
92
f0b60e6e
SS		 93/**
94 * dm_helpers_parse_edid_caps() - Parse edid caps
4562236b 95 *
f0b60e6e 96 * @link: current detected link
4562236b 97 * @edid: [in] pointer to edid
f0b60e6e
SS		 98 * @edid_caps: [in] pointer to edid caps
99 *
100 * Return: void
101 */
4562236b 102enum dc_edid_status dm_helpers_parse_edid_caps(
3c021931 103 struct dc_link *link,
4562236b
HW		 104 const struct dc_edid *edid,
105 struct dc_edid_caps *edid_caps)
106{
3c021931
CS		 107 struct amdgpu_dm_connector *aconnector = link->priv;
108 struct drm_connector *connector = &aconnector->base;
41b83047 109 struct drm_device *dev = connector->dev;
3222a811 110 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
4562236b
HW		 111 struct cea_sad *sads;
112 int sad_count = -1;
113 int sadb_count = -1;
114 int i = 0;
4562236b
HW		 115 uint8_t *sadb = NULL;
116
117 enum dc_edid_status result = EDID_OK;
118
119 if (!edid_caps || !edid)
120 return EDID_BAD_INPUT;
121
122 if (!drm_edid_is_valid(edid_buf))
123 result = EDID_BAD_CHECKSUM;
124
125 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
126 ((uint16_t) edid_buf->mfg_id[1])<<8;
127 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
128 ((uint16_t) edid_buf->prod_code[1])<<8;
129 edid_caps->serial_number = edid_buf->serial;
130 edid_caps->manufacture_week = edid_buf->mfg_week;
131 edid_caps->manufacture_year = edid_buf->mfg_year;
132
0b7778f4
CS		 133 drm_edid_get_monitor_name(edid_buf,
134 edid_caps->display_name,
135 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
4562236b 136
3c021931 137 edid_caps->edid_hdmi = connector->display_info.is_hdmi;
4562236b 138
41b83047 139 apply_edid_quirks(dev, edid_buf, edid_caps);
b7cdccc6 140
4562236b 141 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
ae2a3495 142 if (sad_count <= 0)
4562236b 143 return result;
4562236b 144
1347b15d 145 edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);
4562236b
HW		 146 for (i = 0; i < edid_caps->audio_mode_count; ++i) {
147 struct cea_sad *sad = &sads[i];
148
149 edid_caps->audio_modes[i].format_code = sad->format;
731a3736 150 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
4562236b
HW		 151 edid_caps->audio_modes[i].sample_rate = sad->freq;
152 edid_caps->audio_modes[i].sample_size = sad->byte2;
153 }
154
155 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
156
157 if (sadb_count < 0) {
158 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
159 sadb_count = 0;
160 }
161
162 if (sadb_count)
163 edid_caps->speaker_flags = sadb[0];
164 else
165 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
166
167 kfree(sads);
168 kfree(sadb);
169
170 return result;
171}
172
dbaadb3c 173static void
ea38dd57
WL		 174fill_dc_mst_payload_table_from_drm(struct dc_link *link,
175 bool enable,
176 struct drm_dp_mst_atomic_payload *target_payload,
4d07b0bc 177 struct dc_dp_mst_stream_allocation_table *table)
4562236b 178{
4d07b0bc
LP		 179 struct dc_dp_mst_stream_allocation_table new_table = { 0 };
180 struct dc_dp_mst_stream_allocation *sa;
ea38dd57
WL		 181 struct link_mst_stream_allocation_table copy_of_link_table =
182 link->mst_stream_alloc_table;
183
184 int i;
185 int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
186 struct link_mst_stream_allocation *dc_alloc;
187
188 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
189 if (enable) {
190 dc_alloc =
191 &copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
192 dc_alloc->vcp_id = target_payload->vcpi;
193 dc_alloc->slot_count = target_payload->time_slots;
194 } else {
195 for (i = 0; i < copy_of_link_table.stream_count; i++) {
196 dc_alloc =
197 &copy_of_link_table.stream_allocations[i];
198
199 if (dc_alloc->vcp_id == target_payload->vcpi) {
200 dc_alloc->vcp_id = 0;
201 dc_alloc->slot_count = 0;
202 break;
203 }
204 }
205 ASSERT(i != copy_of_link_table.stream_count);
206 }
4d07b0bc
LP		 207
208 /* Fill payload info*/
ea38dd57
WL		 209 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
210 dc_alloc =
211 &copy_of_link_table.stream_allocations[i];
212 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
213 sa = &new_table.stream_allocations[new_table.stream_count];
214 sa->slot_count = dc_alloc->slot_count;
215 sa->vcp_id = dc_alloc->vcp_id;
216 new_table.stream_count++;
217 }
4562236b
HW		 218 }
219
4d07b0bc
LP		 220 /* Overwrite the old table */
221 *table = new_table;
4562236b
HW		 222}
223
2068afe6
NC		 224void dm_helpers_dp_update_branch_info(
225 struct dc_context *ctx,
226 const struct dc_link *link)
227{}
228
b5ac7036 229static void dm_helpers_construct_old_payload(
9031e001
WL		 230 struct drm_dp_mst_topology_mgr *mgr,
231 struct drm_dp_mst_topology_state *mst_state,
b5ac7036
WL		 232 struct drm_dp_mst_atomic_payload *new_payload,
233 struct drm_dp_mst_atomic_payload *old_payload)
234{
9031e001 235 struct drm_dp_mst_atomic_payload *pos;
221d6546 236 int pbn_per_slot = dfixed_trunc(mst_state->pbn_div);
9031e001
WL		 237 u8 next_payload_vc_start = mgr->next_start_slot;
238 u8 payload_vc_start = new_payload->vc_start_slot;
239 u8 allocated_time_slots;
b5ac7036
WL		 240
241 *old_payload = *new_payload;
242
243 /* Set correct time_slots/PBN of old payload.
244 * other fields (delete & dsc_enabled) in
245 * struct drm_dp_mst_atomic_payload are don't care fields
5aa1dfcd 246 * while calling drm_dp_remove_payload_part2()
b5ac7036 247 */
9031e001
WL		 248 list_for_each_entry(pos, &mst_state->payloads, next) {
249 if (pos != new_payload &&
250 pos->vc_start_slot > payload_vc_start &&
251 pos->vc_start_slot < next_payload_vc_start)
252 next_payload_vc_start = pos->vc_start_slot;
b5ac7036
WL		 253 }
254
9031e001 255 allocated_time_slots = next_payload_vc_start - payload_vc_start;
b5ac7036 256
9031e001
WL		 257 old_payload->time_slots = allocated_time_slots;
258 old_payload->pbn = allocated_time_slots * pbn_per_slot;
b5ac7036
WL		 259}
260
4562236b
HW		 261/*
262 * Writes payload allocation table in immediate downstream device.
263 */
264bool dm_helpers_dp_mst_write_payload_allocation_table(
265 struct dc_context *ctx,
0971c40e 266 const struct dc_stream_state *stream,
8c5e9bbb 267 struct dc_dp_mst_stream_allocation_table *proposed_table,
4562236b
HW		 268 bool enable)
269{
c84dec2f 270 struct amdgpu_dm_connector *aconnector;
4d07b0bc 271 struct drm_dp_mst_topology_state *mst_state;
b5ac7036 272 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
4562236b 273 struct drm_dp_mst_topology_mgr *mst_mgr;
4562236b 274
ceb3dbb4 275 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
3261e013
ML		 276 /* Accessing the connector state is required for vcpi_slots allocation
277 * and directly relies on behaviour in commit check
278 * that blocks before commit guaranteeing that the state
f0b60e6e
SS		 279 * is not gonna be swapped while still in use in commit tail
280 */
3261e013 281
f0127cb1 282 if (!aconnector || !aconnector->mst_root)
4562236b
HW		 283 return false;
284
f0127cb1 285 mst_mgr = &aconnector->mst_root->mst_mgr;
4d07b0bc 286 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
b5ac7036
WL		 287 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
288
289 if (enable) {
290 target_payload = new_payload;
291
5aa1dfcd 292 /* It's OK for this to fail */
b5ac7036
WL		 293 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
294 } else {
295 /* construct old payload by VCPI*/
9031e001
WL		 296 dm_helpers_construct_old_payload(mst_mgr, mst_state,
297 new_payload, &old_payload);
b5ac7036
WL		 298 target_payload = &old_payload;
299
5aa1dfcd 300 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload);
b5ac7036 301 }
4562236b
HW		 302
303 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
304 * AUX message. The sequence is slot 1-63 allocated sequence for each
305 * stream. AMD ASIC stream slot allocation should follow the same
f0b60e6e
SS		 306 * sequence. copy DRM MST allocation to dc
307 */
b5ac7036 308 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
4562236b 309
4562236b
HW		 310 return true;
311}
312
22051b63 313/*
9cc032b2 314 * poll pending down reply
22051b63
MT		 315 */
316void dm_helpers_dp_mst_poll_pending_down_reply(
317 struct dc_context *ctx,
318 const struct dc_link *link)
319{}
fd92ac1b
HW		 320
321/*
322 * Clear payload allocation table before enable MST DP link.
323 */
324void dm_helpers_dp_mst_clear_payload_allocation_table(
325 struct dc_context *ctx,
326 const struct dc_link *link)
327{}
328
4562236b
HW		 329/*
330 * Polls for ACT (allocation change trigger) handled and sends
331 * ALLOCATE_PAYLOAD message.
332 */
48af9b91 333enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
4562236b 334 struct dc_context *ctx,
0971c40e 335 const struct dc_stream_state *stream)
4562236b 336{
c84dec2f 337 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 338 struct drm_dp_mst_topology_mgr *mst_mgr;
339 int ret;
340
ceb3dbb4 341 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
4562236b 342
f0127cb1 343 if (!aconnector || !aconnector->mst_root)
48af9b91 344 return ACT_FAILED;
4562236b 345
f0127cb1 346 mst_mgr = &aconnector->mst_root->mst_mgr;
4562236b
HW		 347
348 if (!mst_mgr->mst_state)
48af9b91 349 return ACT_FAILED;
4562236b
HW		 350
351 ret = drm_dp_check_act_status(mst_mgr);
352
353 if (ret)
48af9b91 354 return ACT_FAILED;
4562236b 355
48af9b91 356 return ACT_SUCCESS;
4562236b
HW		 357}
358
83a79dd6 359void dm_helpers_dp_mst_send_payload_allocation(
4562236b 360 struct dc_context *ctx,
83a79dd6 361 const struct dc_stream_state *stream)
4562236b 362{
c84dec2f 363 struct amdgpu_dm_connector *aconnector;
4d07b0bc 364 struct drm_dp_mst_topology_state *mst_state;
4562236b 365 struct drm_dp_mst_topology_mgr *mst_mgr;
83a79dd6 366 struct drm_dp_mst_atomic_payload *new_payload;
25f7cde8
WL		 367 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
368 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
ba512eaa 369 int ret = 0;
4562236b 370
ceb3dbb4 371 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
4562236b 372
f0127cb1 373 if (!aconnector || !aconnector->mst_root)
83a79dd6 374 return;
4562236b 375
f0127cb1 376 mst_mgr = &aconnector->mst_root->mst_mgr;
4d07b0bc 377 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
5aa1dfcd 378 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
f0127cb1 379
5a507b7d 380 ret = drm_dp_add_payload_part2(mst_mgr, new_payload);
ba512eaa
WL		 381
382 if (ret) {
25f7cde8
WL		 383 amdgpu_dm_set_mst_status(&aconnector->mst_status,
384 set_flag, false);
385 } else {
386 amdgpu_dm_set_mst_status(&aconnector->mst_status,
387 set_flag, true);
388 amdgpu_dm_set_mst_status(&aconnector->mst_status,
389 clr_flag, false);
390 }
4562236b
HW		 391}
392
83a79dd6
WL		 393void dm_helpers_dp_mst_update_mst_mgr_for_deallocation(
394 struct dc_context *ctx,
395 const struct dc_stream_state *stream)
396{
397 struct amdgpu_dm_connector *aconnector;
398 struct drm_dp_mst_topology_state *mst_state;
399 struct drm_dp_mst_topology_mgr *mst_mgr;
400 struct drm_dp_mst_atomic_payload *new_payload, old_payload;
401 enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
402 enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
403
404 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
405
406 if (!aconnector || !aconnector->mst_root)
407 return;
408
409 mst_mgr = &aconnector->mst_root->mst_mgr;
410 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
411 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
412 dm_helpers_construct_old_payload(mst_mgr, mst_state,
413 new_payload, &old_payload);
414
415 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload);
416
417 amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true);
418 amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false);
419 }
420
46659a83
NK		 421void dm_dtn_log_begin(struct dc_context *ctx,
422 struct dc_log_buffer_ctx *log_ctx)
e498eb71 423{
46659a83
NK		 424 static const char msg[] = "[dtn begin]\n";
425
426 if (!log_ctx) {
427 pr_info("%s", msg);
428 return;
429 }
430
431 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
e498eb71 432}
2248eb6b 433
fb8284a5 434__printf(3, 4)
2248eb6b 435void dm_dtn_log_append_v(struct dc_context *ctx,
46659a83
NK		 436 struct dc_log_buffer_ctx *log_ctx,
437 const char *msg, ...)
e498eb71 438{
e498eb71 439 va_list args;
46659a83
NK		 440 size_t total;
441 int n;
442
443 if (!log_ctx) {
444 /* No context, redirect to dmesg. */
445 struct va_format vaf;
446
447 vaf.fmt = msg;
448 vaf.va = &args;
449
450 va_start(args, msg);
451 pr_info("%pV", &vaf);
452 va_end(args);
e498eb71 453
46659a83
NK		 454 return;
455 }
456
457 /* Measure the output. */
e498eb71 458 va_start(args, msg);
46659a83
NK		 459 n = vsnprintf(NULL, 0, msg, args);
460 va_end(args);
461
462 if (n <= 0)
463 return;
464
465 /* Reallocate the string buffer as needed. */
466 total = log_ctx->pos + n + 1;
e498eb71 467
46659a83 468 if (total > log_ctx->size) {
d228419f 469 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL);
46659a83
NK		 470
471 if (buf) {
472 memcpy(buf, log_ctx->buf, log_ctx->pos);
473 kfree(log_ctx->buf);
474
475 log_ctx->buf = buf;
476 log_ctx->size = total;
477 }
478 }
479
480 if (!log_ctx->buf)
481 return;
482
483 /* Write the formatted string to the log buffer. */
484 va_start(args, msg);
485 n = vscnprintf(
486 log_ctx->buf + log_ctx->pos,
487 log_ctx->size - log_ctx->pos,
488 msg,
489 args);
e498eb71 490 va_end(args);
46659a83
NK		 491
492 if (n > 0)
493 log_ctx->pos += n;
e498eb71 494}
2248eb6b 495
46659a83
NK		 496void dm_dtn_log_end(struct dc_context *ctx,
497 struct dc_log_buffer_ctx *log_ctx)
e498eb71 498{
46659a83
NK		 499 static const char msg[] = "[dtn end]\n";
500
501 if (!log_ctx) {
502 pr_info("%s", msg);
503 return;
504 }
505
506 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
e498eb71 507}
a235bd9f 508
4562236b
HW		 509bool dm_helpers_dp_mst_start_top_mgr(
510 struct dc_context *ctx,
511 const struct dc_link *link,
512 bool boot)
513{
c84dec2f 514 struct amdgpu_dm_connector *aconnector = link->priv;
e3834491 515 int ret;
4562236b
HW		 516
517 if (!aconnector) {
3c1fcc55
RL		 518 DRM_ERROR("Failed to find connector for link!");
519 return false;
4562236b
HW		 520 }
521
522 if (boot) {
523 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
524 aconnector, aconnector->base.base.id);
525 return true;
526 }
527
528 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
529 aconnector, aconnector->base.base.id);
530
e3834491
FZ		 531 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
532 if (ret < 0) {
533 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
534 return false;
535 }
536
537 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],
538 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);
539
540 return true;
4562236b
HW		 541}
542
87e298d6 543bool dm_helpers_dp_mst_stop_top_mgr(
4562236b 544 struct dc_context *ctx,
3f16ae82 545 struct dc_link *link)
4562236b 546{
c84dec2f 547 struct amdgpu_dm_connector *aconnector = link->priv;
4562236b
HW		 548
549 if (!aconnector) {
3c1fcc55 550 DRM_ERROR("Failed to find connector for link!");
87e298d6 551 return false;
4562236b
HW		 552 }
553
554 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
555 aconnector, aconnector->base.base.id);
556
dfd9be42 557 if (aconnector->mst_mgr.mst_state == true) {
4562236b 558 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
84a8b390 559 link->cur_link_settings.lane_count = 0;
dfd9be42
WL		 560 }
561
87e298d6 562 return false;
4562236b
HW		 563}
564
565bool dm_helpers_dp_read_dpcd(
566 struct dc_context *ctx,
567 const struct dc_link *link,
568 uint32_t address,
569 uint8_t *data,
570 uint32_t size)
571{
572
c84dec2f 573 struct amdgpu_dm_connector *aconnector = link->priv;
4562236b 574
270b301b 575 if (!aconnector)
4562236b 576 return false;
4562236b 577
4648cf5f
HM		 578 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data,
579 size) == size;
4562236b
HW		 580}
581
582bool dm_helpers_dp_write_dpcd(
583 struct dc_context *ctx,
584 const struct dc_link *link,
585 uint32_t address,
586 const uint8_t *data,
587 uint32_t size)
588{
c84dec2f 589 struct amdgpu_dm_connector *aconnector = link->priv;
4562236b 590
032831f2 591 if (!aconnector)
4562236b 592 return false;
4562236b
HW		 593
594 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
595 address, (uint8_t *)data, size) > 0;
596}
597
598bool dm_helpers_submit_i2c(
599 struct dc_context *ctx,
600 const struct dc_link *link,
601 struct i2c_command *cmd)
602{
c84dec2f 603 struct amdgpu_dm_connector *aconnector = link->priv;
4562236b
HW		 604 struct i2c_msg *msgs;
605 int i = 0;
606 int num = cmd->number_of_payloads;
607 bool result;
608
609 if (!aconnector) {
3c1fcc55 610 DRM_ERROR("Failed to find connector for link!");
4562236b
HW		 611 return false;
612 }
613
6396bb22 614 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
4562236b
HW		 615
616 if (!msgs)
617 return false;
618
619 for (i = 0; i < num; i++) {
bb01672c 620 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
4562236b
HW		 621 msgs[i].addr = cmd->payloads[i].address;
622 msgs[i].len = cmd->payloads[i].length;
623 msgs[i].buf = cmd->payloads[i].data;
624 }
625
626 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
627
628 kfree(msgs);
629
630 return result;
631}
2ca97adc 632
ce801e5d
DK		 633bool dm_helpers_execute_fused_io(
634 struct dc_context *ctx,
635 struct dc_link *link,
636 union dmub_rb_cmd *commands,
637 uint8_t count,
638 uint32_t timeout_us
639)
640{
641 struct amdgpu_device *dev = ctx->driver_context;
642
643 return amdgpu_dm_execute_fused_io(dev, link, commands, count, timeout_us);
644}
645
1ca489fc 646static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
2ca97adc
FZ		 647 bool is_write_cmd,
648 unsigned char cmd,
649 unsigned int length,
650 unsigned int offset,
651 unsigned char *data)
652{
653 bool success = false;
654 unsigned char rc_data[16] = {0};
655 unsigned char rc_offset[4] = {0};
656 unsigned char rc_length[2] = {0};
657 unsigned char rc_cmd = 0;
658 unsigned char rc_result = 0xFF;
659 unsigned char i = 0;
06ac561f 660 int ret;
2ca97adc
FZ		 661
662 if (is_write_cmd) {
663 // write rc data
664 memmove(rc_data, data, length);
665 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
204f5573
AH		 666 if (ret < 0)
667 goto err;
2ca97adc
FZ		 668 }
669
670 // write rc offset
671 rc_offset[0] = (unsigned char) offset & 0xFF;
672 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
673 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
674 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
675 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
204f5573
AH		 676 if (ret < 0)
677 goto err;
2ca97adc
FZ		 678
679 // write rc length
680 rc_length[0] = (unsigned char) length & 0xFF;
681 rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
682 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
204f5573
AH		 683 if (ret < 0)
684 goto err;
2ca97adc
FZ		 685
686 // write rc cmd
687 rc_cmd = cmd | 0x80;
688 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
204f5573
AH		 689 if (ret < 0)
690 goto err;
2ca97adc
FZ		 691
692 // poll until active is 0
693 for (i = 0; i < 10; i++) {
694 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
695 if (rc_cmd == cmd)
696 // active is 0
697 break;
698 msleep(10);
699 }
700
701 // read rc result
702 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
703 success = (rc_result == 0);
704
705 if (success && !is_write_cmd) {
706 // read rc data
707 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
708 }
709
5d72e247 710 drm_dbg_dp(aux->drm_dev, "success = %d\n", success);
2ca97adc
FZ		 711
712 return success;
204f5573
AH		 713
714err:
715 DRM_ERROR("%s: write cmd ..., err = %d\n", __func__, ret);
716 return false;
2ca97adc
FZ		 717}
718
719static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
720{
721 unsigned char data[16] = {0};
722
5d72e247 723 drm_dbg_dp(aux->drm_dev, "Start\n");
2ca97adc
FZ		 724
725 // Step 2
726 data[0] = 'P';
727 data[1] = 'R';
728 data[2] = 'I';
729 data[3] = 'U';
730 data[4] = 'S';
731
1ca489fc 732 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
2ca97adc
FZ		 733 return;
734
735 // Step 3 and 4
1ca489fc 736 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
2ca97adc
FZ		 737 return;
738
739 data[0] &= (~(1 << 1)); // set bit 1 to 0
1ca489fc 740 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
2ca97adc
FZ		 741 return;
742
1ca489fc 743 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
2ca97adc
FZ		 744 return;
745
746 data[0] &= (~(1 << 1)); // set bit 1 to 0
1ca489fc 747 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
2ca97adc
FZ		 748 return;
749
1ca489fc 750 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
2ca97adc
FZ		 751 return;
752
753 data[0] &= (~(1 << 1)); // set bit 1 to 0
1ca489fc 754 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
2ca97adc
FZ		 755 return;
756
757 // Step 3 and 5
1ca489fc 758 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
2ca97adc
FZ		 759 return;
760
761 data[0] |= (1 << 1); // set bit 1 to 1
1ca489fc 762 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
2ca97adc
FZ		 763 return;
764
1ca489fc 765 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
2ca97adc
FZ		 766 return;
767
768 data[0] |= (1 << 1); // set bit 1 to 1
2ca97adc 769
1ca489fc 770 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
2ca97adc
FZ		 771 return;
772
773 data[0] |= (1 << 1); // set bit 1 to 1
1ca489fc 774 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
2ca97adc
FZ		 775 return;
776
777 // Step 6
1ca489fc 778 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
2ca97adc
FZ		 779 return;
780
5d72e247 781 drm_dbg_dp(aux->drm_dev, "Done\n");
2ca97adc
FZ		 782}
783
c168feed
LJ		 784/* MST Dock */
785static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
786
9cc37043
FZ		 787static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
788 struct drm_dp_aux *aux,
789 const struct dc_stream_state *stream,
790 bool enable)
791{
792 uint8_t ret = 0;
793
5d72e247 794 drm_dbg_dp(aux->drm_dev,
3715112c 795 "MST_DSC Configure DSC to non-virtual dpcd synaptics\n");
9cc37043
FZ		 796
797 if (enable) {
798 /* When DSC is enabled on previous boot and reboot with the hub,
799 * there is a chance that Synaptics hub gets stuck during reboot sequence.
800 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
801 */
802 if (!stream->link->link_status.link_active &&
803 memcmp(stream->link->dpcd_caps.branch_dev_name,
804 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
805 apply_synaptics_fifo_reset_wa(aux);
806
807 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
3715112c 808 DRM_INFO("MST_DSC Send DSC enable to synaptics\n");
9cc37043
FZ		 809
810 } else {
811 /* Synaptics hub not support virtual dpcd,
812 * external monitor occur garbage while disable DSC,
813 * Disable DSC only when entire link status turn to false,
814 */
815 if (!stream->link->link_status.link_active) {
816 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
3715112c 817 DRM_INFO("MST_DSC Send DSC disable to synaptics\n");
9cc37043
FZ		 818 }
819 }
820
821 return ret;
822}
9cc37043 823
97bda032
HW		 824bool dm_helpers_dp_write_dsc_enable(
825 struct dc_context *ctx,
826 const struct dc_stream_state *stream,
bd0c064c 827 bool enable)
97bda032 828{
a4d32303
HM		 829 static const uint8_t DSC_DISABLE;
830 static const uint8_t DSC_DECODING = 0x01;
831 static const uint8_t DSC_PASSTHROUGH = 0x02;
832
5d72e247
HM		 833 struct amdgpu_dm_connector *aconnector =
834 (struct amdgpu_dm_connector *)stream->dm_stream_context;
835 struct drm_device *dev = aconnector->base.dev;
a4d32303
HM		 836 struct drm_dp_mst_port *port;
837 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
838 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
6302aead 839 uint8_t ret = 0;
f9c8742c 840
f9c8742c 841 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
f9c8742c
DF		 842 if (!aconnector->dsc_aux)
843 return false;
844
9cc37043
FZ		 845 // apply w/a to synaptics
846 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
847 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
848 return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
849 aconnector->dsc_aux, stream, enable_dsc);
9cc37043 850
f0127cb1 851 port = aconnector->mst_output_port;
a4d32303
HM		 852
853 if (enable) {
854 if (port->passthrough_aux) {
855 ret = drm_dp_dpcd_write(port->passthrough_aux,
856 DP_DSC_ENABLE,
857 &enable_passthrough, 1);
5d72e247 858 drm_dbg_dp(dev,
3715112c 859 "MST_DSC Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
5d72e247 860 ret);
a4d32303
HM		 861 }
862
863 ret = drm_dp_dpcd_write(aconnector->dsc_aux,
864 DP_DSC_ENABLE, &enable_dsc, 1);
5d72e247 865 drm_dbg_dp(dev,
3715112c 866 "MST_DSC Sent DSC decoding enable to %s port, ret = %u\n",
5d72e247
HM		 867 (port->passthrough_aux) ? "remote RX" :
868 "virtual dpcd",
869 ret);
a4d32303
HM		 870 } else {
871 ret = drm_dp_dpcd_write(aconnector->dsc_aux,
872 DP_DSC_ENABLE, &enable_dsc, 1);
5d72e247 873 drm_dbg_dp(dev,
3715112c 874 "MST_DSC Sent DSC decoding disable to %s port, ret = %u\n",
5d72e247
HM		 875 (port->passthrough_aux) ? "remote RX" :
876 "virtual dpcd",
877 ret);
a4d32303
HM		 878
879 if (port->passthrough_aux) {
880 ret = drm_dp_dpcd_write(port->passthrough_aux,
881 DP_DSC_ENABLE,
882 &enable_passthrough, 1);
5d72e247 883 drm_dbg_dp(dev,
3715112c 884 "MST_DSC Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
5d72e247 885 ret);
a4d32303
HM		 886 }
887 }
f9c8742c
DF		 888 }
889
16f0c500 890 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
50b1f44e 891 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
50b1f44e 892 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
5d72e247 893 drm_dbg_dp(dev,
3715112c 894 "SST_DSC Send DSC %s to SST RX\n",
5d72e247 895 enable_dsc ? "enable" : "disable");
50b1f44e
FZ		 896 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
897 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
5d72e247 898 drm_dbg_dp(dev,
3715112c 899 "SST_DSC Send DSC %s to DP-HDMI PCON\n",
5d72e247 900 enable_dsc ? "enable" : "disable");
50b1f44e 901 }
eda8f799 902 }
df2f1015 903
a4d32303 904 return ret;
97bda032 905}
7c7f5b15 906
1619d416
GS		 907bool dm_helpers_dp_write_hblank_reduction(struct dc_context *ctx, const struct dc_stream_state *stream)
908{
909 // TODO
910 return false;
911}
912
aac5db82
HW		 913bool dm_helpers_is_dp_sink_present(struct dc_link *link)
914{
915 bool dp_sink_present;
916 struct amdgpu_dm_connector *aconnector = link->priv;
917
918 if (!aconnector) {
3c1fcc55 919 BUG_ON("Failed to find connector for link!");
aac5db82
HW		 920 return true;
921 }
922
923 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
924 dp_sink_present = dc_link_is_dp_sink_present(link);
925 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
926 return dp_sink_present;
927}
928
c6a83708
ML		 929static int
930dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len)
931{
932 struct drm_connector *connector = data;
933 struct acpi_device *acpidev = ACPI_COMPANION(connector->dev->dev);
a918bb4a 934 unsigned short start = block * EDID_LENGTH;
0f15cbc2 935 struct edid *edid;
c6a83708
ML		 936 int r;
937
938 if (!acpidev)
939 return -ENODEV;
940
941 /* fetch the entire edid from BIOS */
0f15cbc2 942 r = acpi_video_get_edid(acpidev, ACPI_VIDEO_DISPLAY_LCD, -1, (void *)&edid);
c6a83708
ML		 943 if (r < 0) {
944 drm_dbg(connector->dev, "Failed to get EDID from ACPI: %d\n", r);
945 return r;
946 }
947 if (len > r || start > r || start + len > r) {
948 r = -EINVAL;
949 goto cleanup;
950 }
951
0f15cbc2
ML		 952 /* sanity check */
953 if (edid->revision < 4 || !(edid->input & DRM_EDID_INPUT_DIGITAL) ||
954 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_UNDEF) {
955 r = -EINVAL;
956 goto cleanup;
957 }
958
959 memcpy(buf, (void *)edid + start, len);
c6a83708
ML		 960 r = 0;
961
962cleanup:
963 kfree(edid);
964
965 return r;
966}
967
968static const struct drm_edid *
969dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector)
970{
971 struct drm_connector *connector = &aconnector->base;
972
973 if (amdgpu_dc_debug_mask & DC_DISABLE_ACPI_EDID)
974 return NULL;
975
976 switch (connector->connector_type) {
977 case DRM_MODE_CONNECTOR_LVDS:
978 case DRM_MODE_CONNECTOR_eDP:
979 break;
980 default:
981 return NULL;
982 }
983
984 if (connector->force == DRM_FORCE_OFF)
985 return NULL;
986
987 return drm_edid_read_custom(connector, dm_helpers_probe_acpi_edid, connector);
988}
989
7c7f5b15
AG		 990enum dc_edid_status dm_helpers_read_local_edid(
991 struct dc_context *ctx,
992 struct dc_link *link,
993 struct dc_sink *sink)
994{
c84dec2f 995 struct amdgpu_dm_connector *aconnector = link->priv;
85d4d684 996 struct drm_connector *connector = &aconnector->base;
7c7f5b15
AG		 997 struct i2c_adapter *ddc;
998 int retry = 3;
999 enum dc_edid_status edid_status;
48edb2a4
MW		 1000 const struct drm_edid *drm_edid;
1001 const struct edid *edid;
7c7f5b15
AG		 1002
1003 if (link->aux_mode)
1004 ddc = &aconnector->dm_dp_aux.aux.ddc;
1005 else
1006 ddc = &aconnector->i2c->base;
1007
1008 /* some dongles read edid incorrectly the first time,
1009 * do check sum and retry to make sure read correct edid.
1010 */
1011 do {
c6a83708
ML		 1012 drm_edid = dm_helpers_read_acpi_edid(aconnector);
1013 if (drm_edid)
1014 drm_info(connector->dev, "Using ACPI provided EDID for %s\n", connector->name);
1015 else
1016 drm_edid = drm_edid_read_ddc(connector, ddc);
48edb2a4 1017 drm_edid_connector_update(connector, drm_edid);
7c7f5b15 1018
85d4d684
JFZ		 1019 /* DP Compliance Test 4.2.2.6 */
1020 if (link->aux_mode && connector->edid_corrupt)
1021 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
1022
48edb2a4 1023 if (!drm_edid && connector->edid_corrupt) {
85d4d684
JFZ		 1024 connector->edid_corrupt = false;
1025 return EDID_BAD_CHECKSUM;
1026 }
1027
48edb2a4 1028 if (!drm_edid)
7c7f5b15
AG		 1029 return EDID_NO_RESPONSE;
1030
48edb2a4 1031 edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
6847b3b6
TI		 1032 if (!edid ||
1033 edid->extensions >= sizeof(sink->dc_edid.raw_edid) / EDID_LENGTH)
1034 return EDID_BAD_INPUT;
1035
7c7f5b15
AG		 1036 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
1037 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
1038
1039 /* We don't need the original edid anymore */
48edb2a4 1040 drm_edid_free(drm_edid);
7c7f5b15
AG		 1041
1042 edid_status = dm_helpers_parse_edid_caps(
3c021931 1043 link,
7c7f5b15
AG		 1044 &sink->dc_edid,
1045 &sink->edid_caps);
1046
1047 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
1048
1049 if (edid_status != EDID_OK)
1050 DRM_ERROR("EDID err: %d, on connector: %s",
1051 edid_status,
1052 aconnector->base.name);
2a66c0c9
ML		 1053 if (link->aux_mode) {
1054 union test_request test_request = {0};
1055 union test_response test_response = {0};
6e0ef9d8 1056
2a66c0c9
ML		 1057 dm_helpers_dp_read_dpcd(ctx,
1058 link,
1059 DP_TEST_REQUEST,
1060 &test_request.raw,
1061 sizeof(union test_request));
1062
1063 if (!test_request.bits.EDID_READ)
1064 return edid_status;
1065
1066 test_response.bits.EDID_CHECKSUM_WRITE = 1;
1067
1068 dm_helpers_dp_write_dpcd(ctx,
1069 link,
1070 DP_TEST_EDID_CHECKSUM,
1071 &sink->dc_edid.raw_edid[sink->dc_edid.length-1],
1072 1);
1073
1074 dm_helpers_dp_write_dpcd(ctx,
1075 link,
1076 DP_TEST_RESPONSE,
1077 &test_response.raw,
1078 sizeof(test_response));
1079
1080 }
7c7f5b15
AG		 1081
1082 return edid_status;
1083}
81927e28
JS		 1084int dm_helper_dmub_aux_transfer_sync(
1085 struct dc_context *ctx,
1086 const struct dc_link *link,
1087 struct aux_payload *payload,
1088 enum aux_return_code_type *operation_result)
1089{
bfe79f5f
WL		 1090 if (!link->hpd_status) {
1091 *operation_result = AUX_RET_ERROR_HPD_DISCON;
1092 return -1;
1093 }
1094
ead08b95
SW		 1095 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,
1096 operation_result);
81927e28 1097}
88f52b1f
JS		 1098
1099int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
1100 const struct dc_link *link,
1101 struct set_config_cmd_payload *payload,
1102 enum set_config_status *operation_result)
1103{
ead08b95
SW		 1104 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,
1105 operation_result);
88f52b1f
JS		 1106}
1107
15cf3974
DL		 1108void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
1109{
1110 /* TODO: something */
1111}
79037324 1112
118a3315
NK		 1113void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
1114{
1115 // TODO:
1116 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
1117}
1118
c17a34e0
IC		 1119void dm_helpers_init_panel_settings(
1120 struct dc_context *ctx,
eccff6cd
IC		 1121 struct dc_panel_config *panel_config,
1122 struct dc_sink *sink)
c17a34e0 1123{
eccff6cd
IC		 1124 // Extra Panel Power Sequence
1125 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
1126 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
1127 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
1128 panel_config->pps.extra_post_t7_ms = 0;
1129 panel_config->pps.extra_pre_t11_ms = 0;
1130 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
1131 panel_config->pps.extra_post_OUI_ms = 0;
c17a34e0
IC		 1132 // Feature DSC
1133 panel_config->dsc.disable_dsc_edp = false;
1134 panel_config->dsc.force_dsc_edp_policy = 0;
1135}
1136
1137void dm_helpers_override_panel_settings(
1138 struct dc_context *ctx,
1139 struct dc_panel_config *panel_config)
1140{
1141 // Feature DSC
f0b60e6e 1142 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
c17a34e0 1143 panel_config->dsc.disable_dsc_edp = true;
c17a34e0
IC		 1144}
1145
79037324
BL		 1146void *dm_helpers_allocate_gpu_mem(
1147 struct dc_context *ctx,
1148 enum dc_gpu_mem_alloc_type type,
1149 size_t size,
1150 long long *addr)
1151{
0dd79532 1152 struct amdgpu_device *adev = ctx->driver_context;
0dd79532 1153
234e9455 1154 return dm_allocate_gpu_mem(adev, type, size, addr);
79037324
BL		 1155}
1156
1157void dm_helpers_free_gpu_mem(
1158 struct dc_context *ctx,
1159 enum dc_gpu_mem_alloc_type type,
1160 void *pvMem)
1161{
0dd79532 1162 struct amdgpu_device *adev = ctx->driver_context;
d4f36e5f
AP		 1163
1164 dm_free_gpu_mem(adev, type, pvMem);
79037324 1165}
70732504 1166
81927e28 1167bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
70732504 1168{
a08f16cf
LHM		 1169 enum dc_irq_source irq_source;
1170 bool ret;
1171
81927e28 1172 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
a08f16cf
LHM		 1173
1174 ret = dc_interrupt_set(ctx->dc, irq_source, enable);
1175
1176 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
1177 enable ? "en" : "dis", ret);
1178 return ret;
70732504 1179}
6016cd9d
BG		 1180
1181void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
1182{
1183 /* TODO: virtual DPCD */
1184 struct dc_link *link = stream->link;
1185 union down_spread_ctrl old_downspread;
1186 union down_spread_ctrl new_downspread;
1187
1188 if (link->aux_access_disabled)
1189 return;
1190
1191 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1192 &old_downspread.raw,
1193 sizeof(old_downspread)))
1194 return;
1195
1196 new_downspread.raw = old_downspread.raw;
1197 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1198 (stream->ignore_msa_timing_param) ? 1 : 0;
1199
1200 if (new_downspread.raw != old_downspread.raw)
1201 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1202 &new_downspread.raw,
1203 sizeof(new_downspread));
1204}
f01ee019 1205
028c4ccf
QZ		 1206bool dm_helpers_dp_handle_test_pattern_request(
1207 struct dc_context *ctx,
1208 const struct dc_link *link,
1209 union link_test_pattern dpcd_test_pattern,
1210 union test_misc dpcd_test_params)
1211{
1212 enum dp_test_pattern test_pattern;
1213 enum dp_test_pattern_color_space test_pattern_color_space =
1214 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
1215 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
1216 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
1217 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
1218 struct pipe_ctx *pipe_ctx = NULL;
1219 struct amdgpu_dm_connector *aconnector = link->priv;
5d72e247 1220 struct drm_device *dev = aconnector->base.dev;
8a79f7cd
AP		 1221 struct dc_state *dc_state = ctx->dc->current_state;
1222 struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;
028c4ccf
QZ		 1223 int i;
1224
1225 for (i = 0; i < MAX_PIPES; i++) {
1226 if (pipes[i].stream == NULL)
1227 continue;
1228
1229 if (pipes[i].stream->link == link && !pipes[i].top_pipe &&
1230 !pipes[i].prev_odm_pipe) {
1231 pipe_ctx = &pipes[i];
1232 break;
1233 }
1234 }
1235
1236 if (pipe_ctx == NULL)
1237 return false;
1238
1239 switch (dpcd_test_pattern.bits.PATTERN) {
1240 case LINK_TEST_PATTERN_COLOR_RAMP:
1241 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1242 break;
1243 case LINK_TEST_PATTERN_VERTICAL_BARS:
1244 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1245 break; /* black and white */
1246 case LINK_TEST_PATTERN_COLOR_SQUARES:
1247 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1248 TEST_DYN_RANGE_VESA ?
1249 DP_TEST_PATTERN_COLOR_SQUARES :
1250 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1251 break;
1252 default:
1253 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1254 break;
1255 }
1256
1257 if (dpcd_test_params.bits.CLR_FORMAT == 0)
1258 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
1259 else
1260 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
1261 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
1262 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
1263
1264 switch (dpcd_test_params.bits.BPC) {
1265 case 0: // 6 bits
1266 requestColorDepth = COLOR_DEPTH_666;
1267 break;
1268 case 1: // 8 bits
1269 requestColorDepth = COLOR_DEPTH_888;
1270 break;
1271 case 2: // 10 bits
1272 requestColorDepth = COLOR_DEPTH_101010;
1273 break;
1274 case 3: // 12 bits
1275 requestColorDepth = COLOR_DEPTH_121212;
1276 break;
1277 default:
1278 break;
1279 }
1280
1281 switch (dpcd_test_params.bits.CLR_FORMAT) {
1282 case 0:
1283 requestPixelEncoding = PIXEL_ENCODING_RGB;
1284 break;
1285 case 1:
1286 requestPixelEncoding = PIXEL_ENCODING_YCBCR422;
1287 break;
1288 case 2:
1289 requestPixelEncoding = PIXEL_ENCODING_YCBCR444;
1290 break;
1291 default:
1292 requestPixelEncoding = PIXEL_ENCODING_RGB;
1293 break;
1294 }
1295
1296 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED
1297 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
1298 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED
1299 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
5d72e247
HM		 1300 drm_dbg(dev,
1301 "original bpc %d pix encoding %d, changing to %d %d\n",
1302 pipe_ctx->stream->timing.display_color_depth,
1303 pipe_ctx->stream->timing.pixel_encoding,
1304 requestColorDepth,
1305 requestPixelEncoding);
028c4ccf
QZ		 1306 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
1307 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
1308
54618888 1309 dc_link_update_dsc_config(pipe_ctx);
028c4ccf
QZ		 1310
1311 aconnector->timing_changed = true;
1312 /* store current timing */
1313 if (aconnector->timing_requested)
1314 *aconnector->timing_requested = pipe_ctx->stream->timing;
1315 else
5d72e247 1316 drm_err(dev, "timing storage failed\n");
028c4ccf
QZ		 1317
1318 }
1319
d736c2e0
GS		 1320 pipe_ctx->stream->test_pattern.type = test_pattern;
1321 pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;
1322
8a79f7cd
AP		 1323 /* Temp W/A for compliance test failure */
1324 dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1325 dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?
1326 clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;
1327 dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;
1328 ctx->dc->clk_mgr->funcs->update_clocks(
1329 ctx->dc->clk_mgr,
1330 dc_state,
1331 false);
1332
028c4ccf
QZ		 1333 dc_link_dp_set_test_pattern(
1334 (struct dc_link *) link,
1335 test_pattern,
1336 test_pattern_color_space,
1337 NULL,
1338 NULL,
1339 0);
1340
1341 return false;
1342}
1343
f01ee019
FZ		 1344void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
1345{
d9eb8fea 1346 // TODO
f01ee019 1347}
ac02dc34 1348
ac02dc34
EY		 1349void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
1350{
afca033f
RL		 1351 struct amdgpu_device *adev = ctx->driver_context;
1352
9862ef7b 1353 if (adev->dm.idle_workqueue) {
afca033f 1354 adev->dm.idle_workqueue->enable = enable;
9862ef7b
RL		 1355 if (enable && !adev->dm.idle_workqueue->running && amdgpu_dm_is_headless(adev))
1356 schedule_work(&adev->dm.idle_workqueue->work);
1357 }
ac02dc34 1358}
ea192af5
MS		 1359
1360void dm_helpers_dp_mst_update_branch_bandwidth(
1361 struct dc_context *ctx,
1362 struct dc_link *link)
1363{
1364 // TODO
1365}
1366
5b49da02
SJK		 1367static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
1368{
1369 bool ret_val = false;
1370
1371 switch (branch_dev_id) {
1372 case DP_BRANCH_DEVICE_ID_0060AD:
6ed373b0
SJK		 1373 case DP_BRANCH_DEVICE_ID_00E04C:
1374 case DP_BRANCH_DEVICE_ID_90CC24:
5b49da02
SJK		 1375 ret_val = true;
1376 break;
1377 default:
1378 break;
1379 }
1380
1381 return ret_val;
1382}
1383
1384enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
1385{
1386 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1387 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
1388
1389 switch (dpcd_caps->dongle_type) {
1390 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
1391 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&
1392 dpcd_caps->allow_invalid_MSA_timing_param == true &&
1393 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))
1394 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;
1395 break;
1396 default:
1397 break;
1398 }
1399
1400 return as_type;
1401}
5f30ee49
ST		 1402
1403bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream)
1404{
1405 // TODO
1406 return false;
1407}
1408
1409bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream)
1410{
1411 // TODO
1412 return false;
c6a83708 1413}
Linux 6.x block layer and io_uring tree(s)