[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_helpers.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include <linux/string.h>
#include <linux/acpi.h>
#include <linux/version.h>
#include <linux/i2c.h>

#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/amdgpu_drm.h>
#include <drm/drm_edid.h>

#include "dm_services.h"
#include "amdgpu.h"
#include "dc.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_irq.h"

#include "dm_helpers.h"

/* dm_helpers_parse_edid_caps
 *
 * Parse edid caps
 *
 * @edid:	[in] pointer to edid
 *  edid_caps:	[in] pointer to edid caps
 * @return
 *	void
 * */
enum dc_edid_status dm_helpers_parse_edid_caps(
		struct dc_context *ctx,
		const struct dc_edid *edid,
		struct dc_edid_caps *edid_caps)
{
	struct edid *edid_buf = (struct edid *) edid->raw_edid;
	struct cea_sad *sads;
	int sad_count = -1;
	int sadb_count = -1;
	int i = 0;
	int j = 0;
	uint8_t *sadb = NULL;

	enum dc_edid_status result = EDID_OK;

	if (!edid_caps || !edid)
		return EDID_BAD_INPUT;

	if (!drm_edid_is_valid(edid_buf))
		result = EDID_BAD_CHECKSUM;

	edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
					((uint16_t) edid_buf->mfg_id[1])<<8;
	edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
					((uint16_t) edid_buf->prod_code[1])<<8;
	edid_caps->serial_number = edid_buf->serial;
	edid_caps->manufacture_week = edid_buf->mfg_week;
	edid_caps->manufacture_year = edid_buf->mfg_year;

	/* One of the four detailed_timings stores the monitor name. It's
	 * stored in an array of length 13. */
	for (i = 0; i < 4; i++) {
		if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) {
			while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) {
				if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n')
					break;

				edid_caps->display_name[j] =
					edid_buf->detailed_timings[i].data.other_data.data.str.str[j];
				j++;
			}
		}
	}

	edid_caps->edid_hdmi = drm_detect_hdmi_monitor(
			(struct edid *) edid->raw_edid);

	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
	if (sad_count <= 0) {
		DRM_INFO("SADs count is: %d, don't need to read it\n",
				sad_count);
		return result;
	}

	edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
	for (i = 0; i < edid_caps->audio_mode_count; ++i) {
		struct cea_sad *sad = &sads[i];

		edid_caps->audio_modes[i].format_code = sad->format;
		edid_caps->audio_modes[i].channel_count = sad->channels + 1;
		edid_caps->audio_modes[i].sample_rate = sad->freq;
		edid_caps->audio_modes[i].sample_size = sad->byte2;
	}

	sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);

	if (sadb_count < 0) {
		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
		sadb_count = 0;
	}

	if (sadb_count)
		edid_caps->speaker_flags = sadb[0];
	else
		edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;

	kfree(sads);
	kfree(sadb);

	return result;
}

static void get_payload_table(
		struct amdgpu_dm_connector *aconnector,
		struct dp_mst_stream_allocation_table *proposed_table)
{
	int i;
	struct drm_dp_mst_topology_mgr *mst_mgr =
			&aconnector->mst_port->mst_mgr;

	mutex_lock(&mst_mgr->payload_lock);

	proposed_table->stream_count = 0;

	/* number of active streams */
	for (i = 0; i < mst_mgr->max_payloads; i++) {
		if (mst_mgr->payloads[i].num_slots == 0)
			break; /* end of vcp_id table */

		ASSERT(mst_mgr->payloads[i].payload_state !=
				DP_PAYLOAD_DELETE_LOCAL);

		if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL ||
			mst_mgr->payloads[i].payload_state ==
					DP_PAYLOAD_REMOTE) {

			struct dp_mst_stream_allocation *sa =
					&proposed_table->stream_allocations[
						proposed_table->stream_count];

			sa->slot_count = mst_mgr->payloads[i].num_slots;
			sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
			proposed_table->stream_count++;
		}
	}

	mutex_unlock(&mst_mgr->payload_lock);
}

void dm_helpers_dp_update_branch_info(
	struct dc_context *ctx,
	const struct dc_link *link)
{}

/*
 * Writes payload allocation table in immediate downstream device.
 */
bool dm_helpers_dp_mst_write_payload_allocation_table(
		struct dc_context *ctx,
		const struct dc_stream_state *stream,
		struct dp_mst_stream_allocation_table *proposed_table,
		bool enable)
{
	struct amdgpu_dm_connector *aconnector;
	struct drm_dp_mst_topology_mgr *mst_mgr;
	struct drm_dp_mst_port *mst_port;
	int slots = 0;
	bool ret;
	int clock;
	int bpp = 0;
	int pbn = 0;

	aconnector = stream->sink->priv;

	if (!aconnector || !aconnector->mst_port)
		return false;

	mst_mgr = &aconnector->mst_port->mst_mgr;

	if (!mst_mgr->mst_state)
		return false;

	mst_port = aconnector->port;

	if (enable) {
		clock = stream->timing.pix_clk_khz;

		switch (stream->timing.display_color_depth) {

		case COLOR_DEPTH_666:
			bpp = 6;
			break;
		case COLOR_DEPTH_888:
			bpp = 8;
			break;
		case COLOR_DEPTH_101010:
			bpp = 10;
			break;
		case COLOR_DEPTH_121212:
			bpp = 12;
			break;
		case COLOR_DEPTH_141414:
			bpp = 14;
			break;
		case COLOR_DEPTH_161616:
			bpp = 16;
			break;
		default:
			ASSERT(bpp != 0);
			break;
		}

		bpp = bpp * 3;

		/* TODO need to know link rate */

		pbn = drm_dp_calc_pbn_mode(clock, bpp);

		slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
		ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);

		if (!ret)
			return false;

	} else {
		drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
	}

	ret = drm_dp_update_payload_part1(mst_mgr);

	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
	 * AUX message. The sequence is slot 1-63 allocated sequence for each
	 * stream. AMD ASIC stream slot allocation should follow the same
	 * sequence. copy DRM MST allocation to dc */

	get_payload_table(aconnector, proposed_table);

	if (ret)
		return false;

	return true;
}


/*
 * Clear payload allocation table before enable MST DP link.
 */
void dm_helpers_dp_mst_clear_payload_allocation_table(
	struct dc_context *ctx,
	const struct dc_link *link)
{}

/*
 * Polls for ACT (allocation change trigger) handled and sends
 * ALLOCATE_PAYLOAD message.
 */
bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
		struct dc_context *ctx,
		const struct dc_stream_state *stream)
{
	struct amdgpu_dm_connector *aconnector;
	struct drm_dp_mst_topology_mgr *mst_mgr;
	int ret;

	aconnector = stream->sink->priv;

	if (!aconnector || !aconnector->mst_port)
		return false;

	mst_mgr = &aconnector->mst_port->mst_mgr;

	if (!mst_mgr->mst_state)
		return false;

	ret = drm_dp_check_act_status(mst_mgr);

	if (ret)
		return false;

	return true;
}

bool dm_helpers_dp_mst_send_payload_allocation(
		struct dc_context *ctx,
		const struct dc_stream_state *stream,
		bool enable)
{
	struct amdgpu_dm_connector *aconnector;
	struct drm_dp_mst_topology_mgr *mst_mgr;
	struct drm_dp_mst_port *mst_port;
	int ret;

	aconnector = stream->sink->priv;

	if (!aconnector || !aconnector->mst_port)
		return false;

	mst_port = aconnector->port;

	mst_mgr = &aconnector->mst_port->mst_mgr;

	if (!mst_mgr->mst_state)
		return false;

	ret = drm_dp_update_payload_part2(mst_mgr);

	if (ret)
		return false;

	if (!enable)
		drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);

	return true;
}

void dm_dtn_log_begin(struct dc_context *ctx)
{
	pr_info("[dtn begin]\n");
}

void dm_dtn_log_append_v(struct dc_context *ctx,
		const char *msg, ...)
{
	struct va_format vaf;
	va_list args;

	va_start(args, msg);
	vaf.fmt = msg;
	vaf.va = &args;

	pr_info("%pV", &vaf);
	va_end(args);
}

void dm_dtn_log_end(struct dc_context *ctx)
{
	pr_info("[dtn end]\n");
}

bool dm_helpers_dp_mst_start_top_mgr(
		struct dc_context *ctx,
		const struct dc_link *link,
		bool boot)
{
	struct amdgpu_dm_connector *aconnector = link->priv;

	if (!aconnector) {
			DRM_ERROR("Failed to found connector for link!");
			return false;
	}

	if (boot) {
		DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
					aconnector, aconnector->base.base.id);
		return true;
	}

	DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
			aconnector, aconnector->base.base.id);

	return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
}

void dm_helpers_dp_mst_stop_top_mgr(
		struct dc_context *ctx,
		const struct dc_link *link)
{
	struct amdgpu_dm_connector *aconnector = link->priv;

	if (!aconnector) {
			DRM_ERROR("Failed to found connector for link!");
			return;
	}

	DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
			aconnector, aconnector->base.base.id);

	if (aconnector->mst_mgr.mst_state == true)
		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
}

bool dm_helpers_dp_read_dpcd(
		struct dc_context *ctx,
		const struct dc_link *link,
		uint32_t address,
		uint8_t *data,
		uint32_t size)
{

	struct amdgpu_dm_connector *aconnector = link->priv;

	if (!aconnector) {
		DRM_ERROR("Failed to found connector for link!");
		return false;
	}

	return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
			data, size) > 0;
}

bool dm_helpers_dp_write_dpcd(
		struct dc_context *ctx,
		const struct dc_link *link,
		uint32_t address,
		const uint8_t *data,
		uint32_t size)
{
	struct amdgpu_dm_connector *aconnector = link->priv;

	if (!aconnector) {
		DRM_ERROR("Failed to found connector for link!");
		return false;
	}

	return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
			address, (uint8_t *)data, size) > 0;
}

bool dm_helpers_submit_i2c(
		struct dc_context *ctx,
		const struct dc_link *link,
		struct i2c_command *cmd)
{
	struct amdgpu_dm_connector *aconnector = link->priv;
	struct i2c_msg *msgs;
	int i = 0;
	int num = cmd->number_of_payloads;
	bool result;

	if (!aconnector) {
		DRM_ERROR("Failed to found connector for link!");
		return false;
	}

	msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);

	if (!msgs)
		return false;

	for (i = 0; i < num; i++) {
		msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
		msgs[i].addr = cmd->payloads[i].address;
		msgs[i].len = cmd->payloads[i].length;
		msgs[i].buf = cmd->payloads[i].data;
	}

	result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;

	kfree(msgs);

	return result;
}

bool dm_helpers_is_dp_sink_present(struct dc_link *link)
{
	bool dp_sink_present;
	struct amdgpu_dm_connector *aconnector = link->priv;

	if (!aconnector) {
		BUG_ON("Failed to found connector for link!");
		return true;
	}

	mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
	dp_sink_present = dc_link_is_dp_sink_present(link);
	mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
	return dp_sink_present;
}

enum dc_edid_status dm_helpers_read_local_edid(
		struct dc_context *ctx,
		struct dc_link *link,
		struct dc_sink *sink)
{
	struct amdgpu_dm_connector *aconnector = link->priv;
	struct i2c_adapter *ddc;
	int retry = 3;
	enum dc_edid_status edid_status;
	struct edid *edid;

	if (link->aux_mode)
		ddc = &aconnector->dm_dp_aux.aux.ddc;
	else
		ddc = &aconnector->i2c->base;

	/* some dongles read edid incorrectly the first time,
	 * do check sum and retry to make sure read correct edid.
	 */
	do {

		edid = drm_get_edid(&aconnector->base, ddc);

		if (!edid)
			return EDID_NO_RESPONSE;

		sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
		memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);

		/* We don't need the original edid anymore */
		kfree(edid);

		edid_status = dm_helpers_parse_edid_caps(
						ctx,
						&sink->dc_edid,
						&sink->edid_caps);

	} while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);

	if (edid_status != EDID_OK)
		DRM_ERROR("EDID err: %d, on connector: %s",
				edid_status,
				aconnector->base.name);
	if (link->aux_mode) {
		union test_request test_request = { {0} };
		union test_response test_response = { {0} };

		dm_helpers_dp_read_dpcd(ctx,
					link,
					DP_TEST_REQUEST,
					&test_request.raw,
					sizeof(union test_request));

		if (!test_request.bits.EDID_READ)
			return edid_status;

		test_response.bits.EDID_CHECKSUM_WRITE = 1;

		dm_helpers_dp_write_dpcd(ctx,
					link,
					DP_TEST_EDID_CHECKSUM,
					&sink->dc_edid.raw_edid[sink->dc_edid.length-1],
					1);

		dm_helpers_dp_write_dpcd(ctx,
					link,
					DP_TEST_RESPONSE,
					&test_response.raw,
					sizeof(test_response));

	}

	return edid_status;
}

void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
{
	/* TODO: something */
}
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include <linux/string.h>
	27	#include <linux/acpi.h>
	28	#include <linux/version.h>
	29	#include <linux/i2c.h>
	30
	31	#include <drm/drmP.h>
	32	#include <drm/drm_crtc_helper.h>
	33	#include <drm/amdgpu_drm.h>
	34	#include <drm/drm_edid.h>
	35
	36	#include "dm_services.h"
	37	#include "amdgpu.h"
	38	#include "dc.h"
	39	#include "amdgpu_dm.h"
	40	#include "amdgpu_dm_irq.h"
4562236b HW	41
	42	#include "dm_helpers.h"
	43
	44	/* dm_helpers_parse_edid_caps
	45	*
	46	* Parse edid caps
	47	*
	48	* @edid: [in] pointer to edid
	49	* edid_caps: [in] pointer to edid caps
	50	* @return
	51	* void
	52	* */
	53	enum dc_edid_status dm_helpers_parse_edid_caps(
	54	struct dc_context *ctx,
	55	const struct dc_edid *edid,
	56	struct dc_edid_caps *edid_caps)
	57	{
	58	struct edid edid_buf = (struct edid ) edid->raw_edid;
	59	struct cea_sad *sads;
	60	int sad_count = -1;
	61	int sadb_count = -1;
	62	int i = 0;
	63	int j = 0;
	64	uint8_t *sadb = NULL;
	65
	66	enum dc_edid_status result = EDID_OK;
	67
	68	if (!edid_caps \|\| !edid)
	69	return EDID_BAD_INPUT;
	70
	71	if (!drm_edid_is_valid(edid_buf))
	72	result = EDID_BAD_CHECKSUM;
	73
	74	edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] \|
	75	((uint16_t) edid_buf->mfg_id[1])<<8;
	76	edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] \|
	77	((uint16_t) edid_buf->prod_code[1])<<8;
	78	edid_caps->serial_number = edid_buf->serial;
	79	edid_caps->manufacture_week = edid_buf->mfg_week;
	80	edid_caps->manufacture_year = edid_buf->mfg_year;
	81
	82	/* One of the four detailed_timings stores the monitor name. It's
	83	* stored in an array of length 13. */
	84	for (i = 0; i < 4; i++) {
	85	if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) {
	86	while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) {
	87	if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n')
	88	break;
	89
	90	edid_caps->display_name[j] =
	91	edid_buf->detailed_timings[i].data.other_data.data.str.str[j];
	92	j++;
	93	}
	94	}
	95	}
	96
	97	edid_caps->edid_hdmi = drm_detect_hdmi_monitor(
	98	(struct edid *) edid->raw_edid);
	99
	100	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
	101	if (sad_count <= 0) {
	102	DRM_INFO("SADs count is: %d, don't need to read it\n",
	103	sad_count);
	104	return result;
105	}
106
107	edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
108	for (i = 0; i < edid_caps->audio_mode_count; ++i) {
109	struct cea_sad *sad = &sads[i];
110
111	edid_caps->audio_modes[i].format_code = sad->format;
731a3736	112	edid_caps->audio_modes[i].channel_count = sad->channels + 1;
4562236b HW	113	edid_caps->audio_modes[i].sample_rate = sad->freq;
	114	edid_caps->audio_modes[i].sample_size = sad->byte2;
	115	}
	116
	117	sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
	118
	119	if (sadb_count < 0) {
	120	DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
	121	sadb_count = 0;
	122	}
	123
	124	if (sadb_count)
	125	edid_caps->speaker_flags = sadb[0];
	126	else
	127	edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
	128
	129	kfree(sads);
	130	kfree(sadb);
	131
	132	return result;
	133	}
	134
4562236b	135	static void get_payload_table(
c84dec2f	136	struct amdgpu_dm_connector *aconnector,
4562236b HW	137	struct dp_mst_stream_allocation_table *proposed_table)
	138	{
	139	int i;
	140	struct drm_dp_mst_topology_mgr *mst_mgr =
	141	&aconnector->mst_port->mst_mgr;
	142
	143	mutex_lock(&mst_mgr->payload_lock);
	144
	145	proposed_table->stream_count = 0;
	146
	147	/* number of active streams */
	148	for (i = 0; i < mst_mgr->max_payloads; i++) {
	149	if (mst_mgr->payloads[i].num_slots == 0)
	150	break; /* end of vcp_id table */
	151
	152	ASSERT(mst_mgr->payloads[i].payload_state !=
	153	DP_PAYLOAD_DELETE_LOCAL);
	154
	155	if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL \|\|
	156	mst_mgr->payloads[i].payload_state ==
	157	DP_PAYLOAD_REMOTE) {
	158
	159	struct dp_mst_stream_allocation *sa =
	160	&proposed_table->stream_allocations[
	161	proposed_table->stream_count];
	162
	163	sa->slot_count = mst_mgr->payloads[i].num_slots;
	164	sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
	165	proposed_table->stream_count++;
	166	}
	167	}
	168
	169	mutex_unlock(&mst_mgr->payload_lock);
	170	}
	171
2068afe6 NC	172	void dm_helpers_dp_update_branch_info(
	173	struct dc_context *ctx,
	174	const struct dc_link *link)
	175	{}
	176
4562236b HW	177	/*
	178	* Writes payload allocation table in immediate downstream device.
	179	*/
	180	bool dm_helpers_dp_mst_write_payload_allocation_table(
	181	struct dc_context *ctx,
0971c40e	182	const struct dc_stream_state *stream,
4562236b HW	183	struct dp_mst_stream_allocation_table *proposed_table,
	184	bool enable)
	185	{
c84dec2f	186	struct amdgpu_dm_connector *aconnector;
4562236b HW	187	struct drm_dp_mst_topology_mgr *mst_mgr;
	188	struct drm_dp_mst_port *mst_port;
	189	int slots = 0;
	190	bool ret;
	191	int clock;
	192	int bpp = 0;
	193	int pbn = 0;
	194
5c4e9806	195	aconnector = stream->sink->priv;
4562236b HW	196
	197	if (!aconnector \|\| !aconnector->mst_port)
	198	return false;
	199
	200	mst_mgr = &aconnector->mst_port->mst_mgr;
	201
	202	if (!mst_mgr->mst_state)
	203	return false;
	204
	205	mst_port = aconnector->port;
	206
	207	if (enable) {
	208	clock = stream->timing.pix_clk_khz;
	209
	210	switch (stream->timing.display_color_depth) {
	211
	212	case COLOR_DEPTH_666:
	213	bpp = 6;
	214	break;
	215	case COLOR_DEPTH_888:
	216	bpp = 8;
	217	break;
	218	case COLOR_DEPTH_101010:
	219	bpp = 10;
	220	break;
	221	case COLOR_DEPTH_121212:
	222	bpp = 12;
	223	break;
	224	case COLOR_DEPTH_141414:
	225	bpp = 14;
	226	break;
	227	case COLOR_DEPTH_161616:
	228	bpp = 16;
	229	break;
	230	default:
	231	ASSERT(bpp != 0);
	232	break;
	233	}
	234
	235	bpp = bpp * 3;
	236
	237	/* TODO need to know link rate */
	238
	239	pbn = drm_dp_calc_pbn_mode(clock, bpp);
	240
	241	slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
	242	ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
	243
	244	if (!ret)
	245	return false;
	246
	247	} else {
	248	drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
	249	}
	250
	251	ret = drm_dp_update_payload_part1(mst_mgr);
	252
	253	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
	254	* AUX message. The sequence is slot 1-63 allocated sequence for each
	255	* stream. AMD ASIC stream slot allocation should follow the same
	256	* sequence. copy DRM MST allocation to dc */
	257
	258	get_payload_table(aconnector, proposed_table);
	259
260	if (ret)
261	return false;
262
263	return true;
264	}
265
fd92ac1b HW	266
	267	/*
	268	* Clear payload allocation table before enable MST DP link.
	269	*/
	270	void dm_helpers_dp_mst_clear_payload_allocation_table(
	271	struct dc_context *ctx,
	272	const struct dc_link *link)
	273	{}
	274
4562236b HW	275	/*
	276	* Polls for ACT (allocation change trigger) handled and sends
	277	* ALLOCATE_PAYLOAD message.
	278	*/
	279	bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
	280	struct dc_context *ctx,
0971c40e	281	const struct dc_stream_state *stream)
4562236b	282	{
c84dec2f	283	struct amdgpu_dm_connector *aconnector;
4562236b HW	284	struct drm_dp_mst_topology_mgr *mst_mgr;
	285	int ret;
	286
5c4e9806	287	aconnector = stream->sink->priv;
4562236b HW	288
	289	if (!aconnector \|\| !aconnector->mst_port)
	290	return false;
	291
	292	mst_mgr = &aconnector->mst_port->mst_mgr;
	293
	294	if (!mst_mgr->mst_state)
	295	return false;
	296
	297	ret = drm_dp_check_act_status(mst_mgr);
	298
	299	if (ret)
	300	return false;
	301
	302	return true;
	303	}
	304
	305	bool dm_helpers_dp_mst_send_payload_allocation(
	306	struct dc_context *ctx,
0971c40e	307	const struct dc_stream_state *stream,
4562236b HW	308	bool enable)
4562236b HW	309	{
c84dec2f	310	struct amdgpu_dm_connector *aconnector;
4562236b HW	311	struct drm_dp_mst_topology_mgr *mst_mgr;
	312	struct drm_dp_mst_port *mst_port;
	313	int ret;
	314
5c4e9806	315	aconnector = stream->sink->priv;
4562236b HW	316
	317	if (!aconnector \|\| !aconnector->mst_port)
	318	return false;
	319
	320	mst_port = aconnector->port;
	321
	322	mst_mgr = &aconnector->mst_port->mst_mgr;
	323
	324	if (!mst_mgr->mst_state)
	325	return false;
	326
	327	ret = drm_dp_update_payload_part2(mst_mgr);
	328
	329	if (ret)
	330	return false;
	331
	332	if (!enable)
	333	drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
	334
	335	return true;
	336	}
	337
2248eb6b	338	void dm_dtn_log_begin(struct dc_context *ctx)
e498eb71 NK	339	{
	340	pr_info("[dtn begin]\n");
	341	}
2248eb6b TC	342
2248eb6b TC	343	void dm_dtn_log_append_v(struct dc_context *ctx,
e498eb71 NK	344	const char *msg, ...)
	345	{
	346	struct va_format vaf;
	347	va_list args;
	348
	349	va_start(args, msg);
	350	vaf.fmt = msg;
	351	vaf.va = &args;
	352
	353	pr_info("%pV", &vaf);
	354	va_end(args);
	355	}
2248eb6b TC	356
2248eb6b TC	357	void dm_dtn_log_end(struct dc_context *ctx)
e498eb71 NK	358	{
	359	pr_info("[dtn end]\n");
	360	}
a235bd9f	361
4562236b HW	362	bool dm_helpers_dp_mst_start_top_mgr(
	363	struct dc_context *ctx,
	364	const struct dc_link *link,
	365	bool boot)
	366	{
c84dec2f	367	struct amdgpu_dm_connector *aconnector = link->priv;
4562236b HW	368
	369	if (!aconnector) {
	370	DRM_ERROR("Failed to found connector for link!");
	371	return false;
	372	}
	373
	374	if (boot) {
	375	DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
	376	aconnector, aconnector->base.base.id);
	377	return true;
	378	}
	379
	380	DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
	381	aconnector, aconnector->base.base.id);
	382
	383	return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
	384	}
	385
	386	void dm_helpers_dp_mst_stop_top_mgr(
	387	struct dc_context *ctx,
	388	const struct dc_link *link)
	389	{
c84dec2f	390	struct amdgpu_dm_connector *aconnector = link->priv;
4562236b HW	391
	392	if (!aconnector) {
	393	DRM_ERROR("Failed to found connector for link!");
	394	return;
	395	}
	396
	397	DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
	398	aconnector, aconnector->base.base.id);
	399
	400	if (aconnector->mst_mgr.mst_state == true)
	401	drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
	402	}
	403
	404	bool dm_helpers_dp_read_dpcd(
	405	struct dc_context *ctx,
	406	const struct dc_link *link,
	407	uint32_t address,
	408	uint8_t *data,
	409	uint32_t size)
	410	{
	411
c84dec2f	412	struct amdgpu_dm_connector *aconnector = link->priv;
4562236b HW	413
	414	if (!aconnector) {
	415	DRM_ERROR("Failed to found connector for link!");
	416	return false;
	417	}
	418
	419	return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
	420	data, size) > 0;
	421	}
	422
	423	bool dm_helpers_dp_write_dpcd(
	424	struct dc_context *ctx,
	425	const struct dc_link *link,
	426	uint32_t address,
	427	const uint8_t *data,
	428	uint32_t size)
	429	{
c84dec2f	430	struct amdgpu_dm_connector *aconnector = link->priv;
4562236b HW	431
	432	if (!aconnector) {
	433	DRM_ERROR("Failed to found connector for link!");
	434	return false;
	435	}
	436
	437	return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
	438	address, (uint8_t *)data, size) > 0;
	439	}
	440
	441	bool dm_helpers_submit_i2c(
	442	struct dc_context *ctx,
	443	const struct dc_link *link,
	444	struct i2c_command *cmd)
	445	{
c84dec2f	446	struct amdgpu_dm_connector *aconnector = link->priv;
4562236b HW	447	struct i2c_msg *msgs;
	448	int i = 0;
	449	int num = cmd->number_of_payloads;
	450	bool result;
	451
	452	if (!aconnector) {
	453	DRM_ERROR("Failed to found connector for link!");
	454	return false;
	455	}
	456
6396bb22	457	msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
4562236b HW	458
	459	if (!msgs)
	460	return false;
	461
	462	for (i = 0; i < num; i++) {
bb01672c	463	msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
4562236b HW	464	msgs[i].addr = cmd->payloads[i].address;
	465	msgs[i].len = cmd->payloads[i].length;
	466	msgs[i].buf = cmd->payloads[i].data;
	467	}
	468
	469	result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
	470
	471	kfree(msgs);
	472
	473	return result;
	474	}
7c7f5b15	475
aac5db82 HW	476	bool dm_helpers_is_dp_sink_present(struct dc_link *link)
	477	{
	478	bool dp_sink_present;
	479	struct amdgpu_dm_connector *aconnector = link->priv;
	480
	481	if (!aconnector) {
	482	BUG_ON("Failed to found connector for link!");
	483	return true;
	484	}
	485
	486	mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
	487	dp_sink_present = dc_link_is_dp_sink_present(link);
	488	mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
	489	return dp_sink_present;
	490	}
	491
7c7f5b15 AG	492	enum dc_edid_status dm_helpers_read_local_edid(
	493	struct dc_context *ctx,
	494	struct dc_link *link,
	495	struct dc_sink *sink)
	496	{
c84dec2f	497	struct amdgpu_dm_connector *aconnector = link->priv;
7c7f5b15 AG	498	struct i2c_adapter *ddc;
	499	int retry = 3;
	500	enum dc_edid_status edid_status;
	501	struct edid *edid;
	502
	503	if (link->aux_mode)
	504	ddc = &aconnector->dm_dp_aux.aux.ddc;
	505	else
	506	ddc = &aconnector->i2c->base;
	507
	508	/* some dongles read edid incorrectly the first time,
	509	* do check sum and retry to make sure read correct edid.
	510	*/
	511	do {
	512
	513	edid = drm_get_edid(&aconnector->base, ddc);
	514
	515	if (!edid)
	516	return EDID_NO_RESPONSE;
	517
	518	sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
	519	memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
	520
	521	/* We don't need the original edid anymore */
	522	kfree(edid);
	523
	524	edid_status = dm_helpers_parse_edid_caps(
	525	ctx,
	526	&sink->dc_edid,
	527	&sink->edid_caps);
	528
	529	} while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
	530
	531	if (edid_status != EDID_OK)
	532	DRM_ERROR("EDID err: %d, on connector: %s",
	533	edid_status,
	534	aconnector->base.name);
6e0ef9d8	535	if (link->aux_mode) {
1a2eaed8 LSL	536	union test_request test_request = { {0} };
1a2eaed8 LSL	537	union test_response test_response = { {0} };
6e0ef9d8 ML	538
	539	dm_helpers_dp_read_dpcd(ctx,
	540	link,
	541	DP_TEST_REQUEST,
	542	&test_request.raw,
	543	sizeof(union test_request));
	544
	545	if (!test_request.bits.EDID_READ)
	546	return edid_status;
	547
	548	test_response.bits.EDID_CHECKSUM_WRITE = 1;
	549
	550	dm_helpers_dp_write_dpcd(ctx,
	551	link,
	552	DP_TEST_EDID_CHECKSUM,
	553	&sink->dc_edid.raw_edid[sink->dc_edid.length-1],
	554	1);
	555
	556	dm_helpers_dp_write_dpcd(ctx,
	557	link,
	558	DP_TEST_RESPONSE,
	559	&test_response.raw,
	560	sizeof(test_response));
	561
	562	}
7c7f5b15 AG	563
	564	return edid_status;
	565	}
15cf3974 DL	566
	567	void dm_set_dcn_clocks(struct dc_context ctx, struct dc_clocks clks)
	568	{
	569	/* TODO: something */
	570	}