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4562236b HW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #include <linux/string.h> | |
27 | #include <linux/acpi.h> | |
28 | #include <linux/version.h> | |
29 | #include <linux/i2c.h> | |
30 | ||
fcd70cd3 | 31 | #include <drm/drm_probe_helper.h> |
4562236b HW |
32 | #include <drm/amdgpu_drm.h> |
33 | #include <drm/drm_edid.h> | |
34 | ||
35 | #include "dm_services.h" | |
36 | #include "amdgpu.h" | |
37 | #include "dc.h" | |
38 | #include "amdgpu_dm.h" | |
39 | #include "amdgpu_dm_irq.h" | |
f9c8742c | 40 | #include "amdgpu_dm_mst_types.h" |
4562236b HW |
41 | |
42 | #include "dm_helpers.h" | |
43 | ||
44 | /* dm_helpers_parse_edid_caps | |
45 | * | |
46 | * Parse edid caps | |
47 | * | |
48 | * @edid: [in] pointer to edid | |
49 | * edid_caps: [in] pointer to edid caps | |
50 | * @return | |
51 | * void | |
52 | * */ | |
53 | enum dc_edid_status dm_helpers_parse_edid_caps( | |
54 | struct dc_context *ctx, | |
55 | const struct dc_edid *edid, | |
56 | struct dc_edid_caps *edid_caps) | |
57 | { | |
58 | struct edid *edid_buf = (struct edid *) edid->raw_edid; | |
59 | struct cea_sad *sads; | |
60 | int sad_count = -1; | |
61 | int sadb_count = -1; | |
62 | int i = 0; | |
63 | int j = 0; | |
64 | uint8_t *sadb = NULL; | |
65 | ||
66 | enum dc_edid_status result = EDID_OK; | |
67 | ||
68 | if (!edid_caps || !edid) | |
69 | return EDID_BAD_INPUT; | |
70 | ||
71 | if (!drm_edid_is_valid(edid_buf)) | |
72 | result = EDID_BAD_CHECKSUM; | |
73 | ||
74 | edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | | |
75 | ((uint16_t) edid_buf->mfg_id[1])<<8; | |
76 | edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | | |
77 | ((uint16_t) edid_buf->prod_code[1])<<8; | |
78 | edid_caps->serial_number = edid_buf->serial; | |
79 | edid_caps->manufacture_week = edid_buf->mfg_week; | |
80 | edid_caps->manufacture_year = edid_buf->mfg_year; | |
81 | ||
82 | /* One of the four detailed_timings stores the monitor name. It's | |
83 | * stored in an array of length 13. */ | |
84 | for (i = 0; i < 4; i++) { | |
85 | if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) { | |
86 | while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) { | |
87 | if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n') | |
88 | break; | |
89 | ||
90 | edid_caps->display_name[j] = | |
91 | edid_buf->detailed_timings[i].data.other_data.data.str.str[j]; | |
92 | j++; | |
93 | } | |
94 | } | |
95 | } | |
96 | ||
97 | edid_caps->edid_hdmi = drm_detect_hdmi_monitor( | |
98 | (struct edid *) edid->raw_edid); | |
99 | ||
100 | sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); | |
ae2a3495 | 101 | if (sad_count <= 0) |
4562236b | 102 | return result; |
4562236b HW |
103 | |
104 | edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT; | |
105 | for (i = 0; i < edid_caps->audio_mode_count; ++i) { | |
106 | struct cea_sad *sad = &sads[i]; | |
107 | ||
108 | edid_caps->audio_modes[i].format_code = sad->format; | |
731a3736 | 109 | edid_caps->audio_modes[i].channel_count = sad->channels + 1; |
4562236b HW |
110 | edid_caps->audio_modes[i].sample_rate = sad->freq; |
111 | edid_caps->audio_modes[i].sample_size = sad->byte2; | |
112 | } | |
113 | ||
114 | sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); | |
115 | ||
116 | if (sadb_count < 0) { | |
117 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); | |
118 | sadb_count = 0; | |
119 | } | |
120 | ||
121 | if (sadb_count) | |
122 | edid_caps->speaker_flags = sadb[0]; | |
123 | else | |
124 | edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; | |
125 | ||
126 | kfree(sads); | |
127 | kfree(sadb); | |
128 | ||
129 | return result; | |
130 | } | |
131 | ||
4562236b | 132 | static void get_payload_table( |
c84dec2f | 133 | struct amdgpu_dm_connector *aconnector, |
4562236b HW |
134 | struct dp_mst_stream_allocation_table *proposed_table) |
135 | { | |
136 | int i; | |
137 | struct drm_dp_mst_topology_mgr *mst_mgr = | |
138 | &aconnector->mst_port->mst_mgr; | |
139 | ||
140 | mutex_lock(&mst_mgr->payload_lock); | |
141 | ||
142 | proposed_table->stream_count = 0; | |
143 | ||
144 | /* number of active streams */ | |
145 | for (i = 0; i < mst_mgr->max_payloads; i++) { | |
146 | if (mst_mgr->payloads[i].num_slots == 0) | |
147 | break; /* end of vcp_id table */ | |
148 | ||
149 | ASSERT(mst_mgr->payloads[i].payload_state != | |
150 | DP_PAYLOAD_DELETE_LOCAL); | |
151 | ||
152 | if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL || | |
153 | mst_mgr->payloads[i].payload_state == | |
154 | DP_PAYLOAD_REMOTE) { | |
155 | ||
156 | struct dp_mst_stream_allocation *sa = | |
157 | &proposed_table->stream_allocations[ | |
158 | proposed_table->stream_count]; | |
159 | ||
160 | sa->slot_count = mst_mgr->payloads[i].num_slots; | |
161 | sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi; | |
162 | proposed_table->stream_count++; | |
163 | } | |
164 | } | |
165 | ||
166 | mutex_unlock(&mst_mgr->payload_lock); | |
167 | } | |
168 | ||
2068afe6 NC |
169 | void dm_helpers_dp_update_branch_info( |
170 | struct dc_context *ctx, | |
171 | const struct dc_link *link) | |
172 | {} | |
173 | ||
4562236b HW |
174 | /* |
175 | * Writes payload allocation table in immediate downstream device. | |
176 | */ | |
177 | bool dm_helpers_dp_mst_write_payload_allocation_table( | |
178 | struct dc_context *ctx, | |
0971c40e | 179 | const struct dc_stream_state *stream, |
4562236b HW |
180 | struct dp_mst_stream_allocation_table *proposed_table, |
181 | bool enable) | |
182 | { | |
c84dec2f | 183 | struct amdgpu_dm_connector *aconnector; |
3261e013 | 184 | struct dm_connector_state *dm_conn_state; |
4562236b HW |
185 | struct drm_dp_mst_topology_mgr *mst_mgr; |
186 | struct drm_dp_mst_port *mst_port; | |
4562236b | 187 | bool ret; |
4562236b | 188 | |
ceb3dbb4 | 189 | aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; |
3261e013 ML |
190 | /* Accessing the connector state is required for vcpi_slots allocation |
191 | * and directly relies on behaviour in commit check | |
192 | * that blocks before commit guaranteeing that the state | |
193 | * is not gonna be swapped while still in use in commit tail */ | |
194 | ||
4562236b HW |
195 | if (!aconnector || !aconnector->mst_port) |
196 | return false; | |
197 | ||
320f6d81 CIK |
198 | dm_conn_state = to_dm_connector_state(aconnector->base.state); |
199 | ||
4562236b HW |
200 | mst_mgr = &aconnector->mst_port->mst_mgr; |
201 | ||
202 | if (!mst_mgr->mst_state) | |
203 | return false; | |
204 | ||
205 | mst_port = aconnector->port; | |
206 | ||
207 | if (enable) { | |
4562236b | 208 | |
3261e013 ML |
209 | ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, |
210 | dm_conn_state->pbn, | |
211 | dm_conn_state->vcpi_slots); | |
4562236b HW |
212 | if (!ret) |
213 | return false; | |
214 | ||
215 | } else { | |
216 | drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port); | |
217 | } | |
218 | ||
58fe03d6 LP |
219 | /* It's OK for this to fail */ |
220 | drm_dp_update_payload_part1(mst_mgr); | |
4562236b HW |
221 | |
222 | /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or | |
223 | * AUX message. The sequence is slot 1-63 allocated sequence for each | |
224 | * stream. AMD ASIC stream slot allocation should follow the same | |
225 | * sequence. copy DRM MST allocation to dc */ | |
226 | ||
227 | get_payload_table(aconnector, proposed_table); | |
228 | ||
4562236b HW |
229 | return true; |
230 | } | |
231 | ||
22051b63 | 232 | /* |
9cc032b2 | 233 | * poll pending down reply |
22051b63 MT |
234 | */ |
235 | void dm_helpers_dp_mst_poll_pending_down_reply( | |
236 | struct dc_context *ctx, | |
237 | const struct dc_link *link) | |
238 | {} | |
fd92ac1b HW |
239 | |
240 | /* | |
241 | * Clear payload allocation table before enable MST DP link. | |
242 | */ | |
243 | void dm_helpers_dp_mst_clear_payload_allocation_table( | |
244 | struct dc_context *ctx, | |
245 | const struct dc_link *link) | |
246 | {} | |
247 | ||
4562236b HW |
248 | /* |
249 | * Polls for ACT (allocation change trigger) handled and sends | |
250 | * ALLOCATE_PAYLOAD message. | |
251 | */ | |
48af9b91 | 252 | enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( |
4562236b | 253 | struct dc_context *ctx, |
0971c40e | 254 | const struct dc_stream_state *stream) |
4562236b | 255 | { |
c84dec2f | 256 | struct amdgpu_dm_connector *aconnector; |
4562236b HW |
257 | struct drm_dp_mst_topology_mgr *mst_mgr; |
258 | int ret; | |
259 | ||
ceb3dbb4 | 260 | aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; |
4562236b HW |
261 | |
262 | if (!aconnector || !aconnector->mst_port) | |
48af9b91 | 263 | return ACT_FAILED; |
4562236b HW |
264 | |
265 | mst_mgr = &aconnector->mst_port->mst_mgr; | |
266 | ||
267 | if (!mst_mgr->mst_state) | |
48af9b91 | 268 | return ACT_FAILED; |
4562236b HW |
269 | |
270 | ret = drm_dp_check_act_status(mst_mgr); | |
271 | ||
272 | if (ret) | |
48af9b91 | 273 | return ACT_FAILED; |
4562236b | 274 | |
48af9b91 | 275 | return ACT_SUCCESS; |
4562236b HW |
276 | } |
277 | ||
278 | bool dm_helpers_dp_mst_send_payload_allocation( | |
279 | struct dc_context *ctx, | |
0971c40e | 280 | const struct dc_stream_state *stream, |
4562236b HW |
281 | bool enable) |
282 | { | |
c84dec2f | 283 | struct amdgpu_dm_connector *aconnector; |
4562236b HW |
284 | struct drm_dp_mst_topology_mgr *mst_mgr; |
285 | struct drm_dp_mst_port *mst_port; | |
4562236b | 286 | |
ceb3dbb4 | 287 | aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; |
4562236b HW |
288 | |
289 | if (!aconnector || !aconnector->mst_port) | |
290 | return false; | |
291 | ||
292 | mst_port = aconnector->port; | |
293 | ||
294 | mst_mgr = &aconnector->mst_port->mst_mgr; | |
295 | ||
296 | if (!mst_mgr->mst_state) | |
297 | return false; | |
298 | ||
58fe03d6 LP |
299 | /* It's OK for this to fail */ |
300 | drm_dp_update_payload_part2(mst_mgr); | |
4562236b HW |
301 | |
302 | if (!enable) | |
303 | drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port); | |
304 | ||
305 | return true; | |
306 | } | |
307 | ||
46659a83 NK |
308 | void dm_dtn_log_begin(struct dc_context *ctx, |
309 | struct dc_log_buffer_ctx *log_ctx) | |
e498eb71 | 310 | { |
46659a83 NK |
311 | static const char msg[] = "[dtn begin]\n"; |
312 | ||
313 | if (!log_ctx) { | |
314 | pr_info("%s", msg); | |
315 | return; | |
316 | } | |
317 | ||
318 | dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); | |
e498eb71 | 319 | } |
2248eb6b TC |
320 | |
321 | void dm_dtn_log_append_v(struct dc_context *ctx, | |
46659a83 NK |
322 | struct dc_log_buffer_ctx *log_ctx, |
323 | const char *msg, ...) | |
e498eb71 | 324 | { |
e498eb71 | 325 | va_list args; |
46659a83 NK |
326 | size_t total; |
327 | int n; | |
328 | ||
329 | if (!log_ctx) { | |
330 | /* No context, redirect to dmesg. */ | |
331 | struct va_format vaf; | |
332 | ||
333 | vaf.fmt = msg; | |
334 | vaf.va = &args; | |
335 | ||
336 | va_start(args, msg); | |
337 | pr_info("%pV", &vaf); | |
338 | va_end(args); | |
e498eb71 | 339 | |
46659a83 NK |
340 | return; |
341 | } | |
342 | ||
343 | /* Measure the output. */ | |
e498eb71 | 344 | va_start(args, msg); |
46659a83 NK |
345 | n = vsnprintf(NULL, 0, msg, args); |
346 | va_end(args); | |
347 | ||
348 | if (n <= 0) | |
349 | return; | |
350 | ||
351 | /* Reallocate the string buffer as needed. */ | |
352 | total = log_ctx->pos + n + 1; | |
e498eb71 | 353 | |
46659a83 NK |
354 | if (total > log_ctx->size) { |
355 | char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL); | |
356 | ||
357 | if (buf) { | |
358 | memcpy(buf, log_ctx->buf, log_ctx->pos); | |
359 | kfree(log_ctx->buf); | |
360 | ||
361 | log_ctx->buf = buf; | |
362 | log_ctx->size = total; | |
363 | } | |
364 | } | |
365 | ||
366 | if (!log_ctx->buf) | |
367 | return; | |
368 | ||
369 | /* Write the formatted string to the log buffer. */ | |
370 | va_start(args, msg); | |
371 | n = vscnprintf( | |
372 | log_ctx->buf + log_ctx->pos, | |
373 | log_ctx->size - log_ctx->pos, | |
374 | msg, | |
375 | args); | |
e498eb71 | 376 | va_end(args); |
46659a83 NK |
377 | |
378 | if (n > 0) | |
379 | log_ctx->pos += n; | |
e498eb71 | 380 | } |
2248eb6b | 381 | |
46659a83 NK |
382 | void dm_dtn_log_end(struct dc_context *ctx, |
383 | struct dc_log_buffer_ctx *log_ctx) | |
e498eb71 | 384 | { |
46659a83 NK |
385 | static const char msg[] = "[dtn end]\n"; |
386 | ||
387 | if (!log_ctx) { | |
388 | pr_info("%s", msg); | |
389 | return; | |
390 | } | |
391 | ||
392 | dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); | |
e498eb71 | 393 | } |
a235bd9f | 394 | |
4562236b HW |
395 | bool dm_helpers_dp_mst_start_top_mgr( |
396 | struct dc_context *ctx, | |
397 | const struct dc_link *link, | |
398 | bool boot) | |
399 | { | |
c84dec2f | 400 | struct amdgpu_dm_connector *aconnector = link->priv; |
4562236b HW |
401 | |
402 | if (!aconnector) { | |
3c1fcc55 RL |
403 | DRM_ERROR("Failed to find connector for link!"); |
404 | return false; | |
4562236b HW |
405 | } |
406 | ||
407 | if (boot) { | |
408 | DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", | |
409 | aconnector, aconnector->base.base.id); | |
410 | return true; | |
411 | } | |
412 | ||
413 | DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", | |
414 | aconnector, aconnector->base.base.id); | |
415 | ||
416 | return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0); | |
417 | } | |
418 | ||
419 | void dm_helpers_dp_mst_stop_top_mgr( | |
420 | struct dc_context *ctx, | |
3f16ae82 | 421 | struct dc_link *link) |
4562236b | 422 | { |
c84dec2f | 423 | struct amdgpu_dm_connector *aconnector = link->priv; |
3f16ae82 | 424 | uint8_t i; |
4562236b HW |
425 | |
426 | if (!aconnector) { | |
3c1fcc55 RL |
427 | DRM_ERROR("Failed to find connector for link!"); |
428 | return; | |
4562236b HW |
429 | } |
430 | ||
431 | DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", | |
432 | aconnector, aconnector->base.base.id); | |
433 | ||
3f16ae82 | 434 | if (aconnector->mst_mgr.mst_state == true) { |
4562236b | 435 | drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); |
3f16ae82 AP |
436 | |
437 | for (i = 0; i < MAX_SINKS_PER_LINK; i++) { | |
438 | if (link->remote_sinks[i] == NULL) | |
439 | continue; | |
440 | ||
441 | if (link->remote_sinks[i]->sink_signal == | |
442 | SIGNAL_TYPE_DISPLAY_PORT_MST) { | |
443 | dc_link_remove_remote_sink(link, link->remote_sinks[i]); | |
444 | ||
445 | if (aconnector->dc_sink) { | |
446 | dc_sink_release(aconnector->dc_sink); | |
447 | aconnector->dc_sink = NULL; | |
448 | aconnector->dc_link->cur_link_settings.lane_count = 0; | |
449 | } | |
450 | } | |
451 | } | |
452 | } | |
4562236b HW |
453 | } |
454 | ||
455 | bool dm_helpers_dp_read_dpcd( | |
456 | struct dc_context *ctx, | |
457 | const struct dc_link *link, | |
458 | uint32_t address, | |
459 | uint8_t *data, | |
460 | uint32_t size) | |
461 | { | |
462 | ||
c84dec2f | 463 | struct amdgpu_dm_connector *aconnector = link->priv; |
4562236b HW |
464 | |
465 | if (!aconnector) { | |
f9135b08 | 466 | DC_LOG_DC("Failed to find connector for link!\n"); |
4562236b HW |
467 | return false; |
468 | } | |
469 | ||
470 | return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, | |
471 | data, size) > 0; | |
472 | } | |
473 | ||
474 | bool dm_helpers_dp_write_dpcd( | |
475 | struct dc_context *ctx, | |
476 | const struct dc_link *link, | |
477 | uint32_t address, | |
478 | const uint8_t *data, | |
479 | uint32_t size) | |
480 | { | |
c84dec2f | 481 | struct amdgpu_dm_connector *aconnector = link->priv; |
4562236b HW |
482 | |
483 | if (!aconnector) { | |
3c1fcc55 | 484 | DRM_ERROR("Failed to find connector for link!"); |
4562236b HW |
485 | return false; |
486 | } | |
487 | ||
488 | return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, | |
489 | address, (uint8_t *)data, size) > 0; | |
490 | } | |
491 | ||
492 | bool dm_helpers_submit_i2c( | |
493 | struct dc_context *ctx, | |
494 | const struct dc_link *link, | |
495 | struct i2c_command *cmd) | |
496 | { | |
c84dec2f | 497 | struct amdgpu_dm_connector *aconnector = link->priv; |
4562236b HW |
498 | struct i2c_msg *msgs; |
499 | int i = 0; | |
500 | int num = cmd->number_of_payloads; | |
501 | bool result; | |
502 | ||
503 | if (!aconnector) { | |
3c1fcc55 | 504 | DRM_ERROR("Failed to find connector for link!"); |
4562236b HW |
505 | return false; |
506 | } | |
507 | ||
6396bb22 | 508 | msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); |
4562236b HW |
509 | |
510 | if (!msgs) | |
511 | return false; | |
512 | ||
513 | for (i = 0; i < num; i++) { | |
bb01672c | 514 | msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; |
4562236b HW |
515 | msgs[i].addr = cmd->payloads[i].address; |
516 | msgs[i].len = cmd->payloads[i].length; | |
517 | msgs[i].buf = cmd->payloads[i].data; | |
518 | } | |
519 | ||
520 | result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; | |
521 | ||
522 | kfree(msgs); | |
523 | ||
524 | return result; | |
525 | } | |
97bda032 HW |
526 | bool dm_helpers_dp_write_dsc_enable( |
527 | struct dc_context *ctx, | |
528 | const struct dc_stream_state *stream, | |
529 | bool enable | |
530 | ) | |
531 | { | |
df2f1015 | 532 | uint8_t enable_dsc = enable ? 1 : 0; |
f9c8742c DF |
533 | struct amdgpu_dm_connector *aconnector; |
534 | ||
535 | if (!stream) | |
536 | return false; | |
537 | ||
538 | if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { | |
539 | aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; | |
540 | ||
541 | if (!aconnector->dsc_aux) | |
542 | return false; | |
543 | ||
544 | return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1) >= 0); | |
545 | } | |
546 | ||
547 | if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) | |
548 | return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); | |
df2f1015 | 549 | |
f9c8742c | 550 | return false; |
97bda032 | 551 | } |
7c7f5b15 | 552 | |
aac5db82 HW |
553 | bool dm_helpers_is_dp_sink_present(struct dc_link *link) |
554 | { | |
555 | bool dp_sink_present; | |
556 | struct amdgpu_dm_connector *aconnector = link->priv; | |
557 | ||
558 | if (!aconnector) { | |
3c1fcc55 | 559 | BUG_ON("Failed to find connector for link!"); |
aac5db82 HW |
560 | return true; |
561 | } | |
562 | ||
563 | mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); | |
564 | dp_sink_present = dc_link_is_dp_sink_present(link); | |
565 | mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); | |
566 | return dp_sink_present; | |
567 | } | |
568 | ||
7c7f5b15 AG |
569 | enum dc_edid_status dm_helpers_read_local_edid( |
570 | struct dc_context *ctx, | |
571 | struct dc_link *link, | |
572 | struct dc_sink *sink) | |
573 | { | |
c84dec2f | 574 | struct amdgpu_dm_connector *aconnector = link->priv; |
85d4d684 | 575 | struct drm_connector *connector = &aconnector->base; |
7c7f5b15 AG |
576 | struct i2c_adapter *ddc; |
577 | int retry = 3; | |
578 | enum dc_edid_status edid_status; | |
579 | struct edid *edid; | |
580 | ||
581 | if (link->aux_mode) | |
582 | ddc = &aconnector->dm_dp_aux.aux.ddc; | |
583 | else | |
584 | ddc = &aconnector->i2c->base; | |
585 | ||
586 | /* some dongles read edid incorrectly the first time, | |
587 | * do check sum and retry to make sure read correct edid. | |
588 | */ | |
589 | do { | |
590 | ||
591 | edid = drm_get_edid(&aconnector->base, ddc); | |
592 | ||
85d4d684 JFZ |
593 | /* DP Compliance Test 4.2.2.6 */ |
594 | if (link->aux_mode && connector->edid_corrupt) | |
595 | drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); | |
596 | ||
597 | if (!edid && connector->edid_corrupt) { | |
598 | connector->edid_corrupt = false; | |
599 | return EDID_BAD_CHECKSUM; | |
600 | } | |
601 | ||
7c7f5b15 AG |
602 | if (!edid) |
603 | return EDID_NO_RESPONSE; | |
604 | ||
605 | sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); | |
606 | memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); | |
607 | ||
608 | /* We don't need the original edid anymore */ | |
609 | kfree(edid); | |
610 | ||
97e51c16 HW |
611 | /* connector->display_info will be parsed from EDID and saved |
612 | * into drm_connector->display_info from edid by call stack | |
613 | * below: | |
614 | * drm_parse_ycbcr420_deep_color_info | |
615 | * drm_parse_hdmi_forum_vsdb | |
616 | * drm_parse_cea_ext | |
617 | * drm_add_display_info | |
618 | * drm_connector_update_edid_property | |
619 | * | |
620 | * drm_connector->display_info will be used by amdgpu_dm funcs, | |
621 | * like fill_stream_properties_from_drm_display_mode | |
622 | */ | |
623 | amdgpu_dm_update_connector_after_detect(aconnector); | |
624 | ||
7c7f5b15 AG |
625 | edid_status = dm_helpers_parse_edid_caps( |
626 | ctx, | |
627 | &sink->dc_edid, | |
628 | &sink->edid_caps); | |
629 | ||
630 | } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); | |
631 | ||
632 | if (edid_status != EDID_OK) | |
633 | DRM_ERROR("EDID err: %d, on connector: %s", | |
634 | edid_status, | |
635 | aconnector->base.name); | |
6e0ef9d8 | 636 | |
85d4d684 JFZ |
637 | /* DP Compliance Test 4.2.2.3 */ |
638 | if (link->aux_mode) | |
639 | drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, sink->dc_edid.raw_edid[sink->dc_edid.length-1]); | |
7c7f5b15 AG |
640 | |
641 | return edid_status; | |
642 | } | |
15cf3974 DL |
643 | |
644 | void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) | |
645 | { | |
646 | /* TODO: something */ | |
647 | } | |
79037324 BL |
648 | |
649 | void *dm_helpers_allocate_gpu_mem( | |
650 | struct dc_context *ctx, | |
651 | enum dc_gpu_mem_alloc_type type, | |
652 | size_t size, | |
653 | long long *addr) | |
654 | { | |
655 | // TODO | |
656 | return NULL; | |
657 | } | |
658 | ||
659 | void dm_helpers_free_gpu_mem( | |
660 | struct dc_context *ctx, | |
661 | enum dc_gpu_mem_alloc_type type, | |
662 | void *pvMem) | |
663 | { | |
664 | // TODO | |
665 | } |