Commit | Line | Data |
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a193ed20 BL |
1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #include "amdgpu_dm_hdcp.h" | |
27 | #include "amdgpu.h" | |
28 | #include "amdgpu_dm.h" | |
55b50e68 | 29 | #include "dm_helpers.h" |
6a99099f | 30 | #include <drm/display/drm_hdcp_helper.h> |
9037246b BL |
31 | #include "hdcp_psp.h" |
32 | ||
1746d5a1 BL |
33 | /* |
34 | * If the SRM version being loaded is less than or equal to the | |
35 | * currently loaded SRM, psp will return 0xFFFF as the version | |
36 | */ | |
37 | #define PSP_SRM_VERSION_MAX 0xFFFF | |
55b50e68 | 38 | |
dab8f7e9 | 39 | static bool |
40 | lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size) | |
55b50e68 BL |
41 | { |
42 | ||
43 | struct dc_link *link = handle; | |
44 | struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} }; | |
45 | struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz}; | |
46 | ||
47 | return dm_helpers_submit_i2c(link->ctx, link, &cmd); | |
48 | } | |
49 | ||
dab8f7e9 | 50 | static bool |
51 | lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size) | |
55b50e68 BL |
52 | { |
53 | struct dc_link *link = handle; | |
54 | ||
55 | struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset}, {false, address, size, data} }; | |
56 | struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz}; | |
57 | ||
58 | return dm_helpers_submit_i2c(link->ctx, link, &cmd); | |
59 | } | |
60 | ||
dab8f7e9 | 61 | static bool |
62 | lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size) | |
55b50e68 BL |
63 | { |
64 | struct dc_link *link = handle; | |
65 | ||
66 | return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size); | |
67 | } | |
68 | ||
dab8f7e9 | 69 | static bool |
70 | lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size) | |
55b50e68 BL |
71 | { |
72 | struct dc_link *link = handle; | |
73 | ||
74 | return dm_helpers_dp_read_dpcd(link->ctx, link, address, data, size); | |
75 | } | |
a193ed20 | 76 | |
9037246b BL |
77 | static uint8_t *psp_get_srm(struct psp_context *psp, uint32_t *srm_version, uint32_t *srm_size) |
78 | { | |
1746d5a1 BL |
79 | |
80 | struct ta_hdcp_shared_memory *hdcp_cmd; | |
81 | ||
ce97f37b | 82 | if (!psp->hdcp_context.context.initialized) { |
1746d5a1 BL |
83 | DRM_WARN("Failed to get hdcp srm. HDCP TA is not initialized."); |
84 | return NULL; | |
85 | } | |
86 | ||
ce97f37b | 87 | hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf; |
1746d5a1 BL |
88 | memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory)); |
89 | ||
90 | hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_GET_SRM; | |
91 | psp_hdcp_invoke(psp, hdcp_cmd->cmd_id); | |
92 | ||
93 | if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS) | |
94 | return NULL; | |
95 | ||
96 | *srm_version = hdcp_cmd->out_msg.hdcp_get_srm.srm_version; | |
97 | *srm_size = hdcp_cmd->out_msg.hdcp_get_srm.srm_buf_size; | |
98 | ||
99 | ||
100 | return hdcp_cmd->out_msg.hdcp_get_srm.srm_buf; | |
9037246b BL |
101 | } |
102 | ||
103 | static int psp_set_srm(struct psp_context *psp, uint8_t *srm, uint32_t srm_size, uint32_t *srm_version) | |
104 | { | |
1746d5a1 BL |
105 | |
106 | struct ta_hdcp_shared_memory *hdcp_cmd; | |
107 | ||
ce97f37b | 108 | if (!psp->hdcp_context.context.initialized) { |
1746d5a1 BL |
109 | DRM_WARN("Failed to get hdcp srm. HDCP TA is not initialized."); |
110 | return -EINVAL; | |
111 | } | |
112 | ||
ce97f37b | 113 | hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf; |
1746d5a1 BL |
114 | memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory)); |
115 | ||
116 | memcpy(hdcp_cmd->in_msg.hdcp_set_srm.srm_buf, srm, srm_size); | |
117 | hdcp_cmd->in_msg.hdcp_set_srm.srm_buf_size = srm_size; | |
118 | hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_SET_SRM; | |
119 | ||
120 | psp_hdcp_invoke(psp, hdcp_cmd->cmd_id); | |
121 | ||
122 | if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS || hdcp_cmd->out_msg.hdcp_set_srm.valid_signature != 1 || | |
123 | hdcp_cmd->out_msg.hdcp_set_srm.srm_version == PSP_SRM_VERSION_MAX) | |
124 | return -EINVAL; | |
125 | ||
126 | *srm_version = hdcp_cmd->out_msg.hdcp_set_srm.srm_version; | |
9037246b BL |
127 | return 0; |
128 | } | |
129 | ||
a193ed20 BL |
130 | static void process_output(struct hdcp_workqueue *hdcp_work) |
131 | { | |
132 | struct mod_hdcp_output output = hdcp_work->output; | |
133 | ||
134 | if (output.callback_stop) | |
135 | cancel_delayed_work(&hdcp_work->callback_dwork); | |
136 | ||
137 | if (output.callback_needed) | |
138 | schedule_delayed_work(&hdcp_work->callback_dwork, | |
139 | msecs_to_jiffies(output.callback_delay)); | |
140 | ||
141 | if (output.watchdog_timer_stop) | |
142 | cancel_delayed_work(&hdcp_work->watchdog_timer_dwork); | |
143 | ||
144 | if (output.watchdog_timer_needed) | |
145 | schedule_delayed_work(&hdcp_work->watchdog_timer_dwork, | |
146 | msecs_to_jiffies(output.watchdog_timer_delay)); | |
147 | ||
45375a50 | 148 | schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(0)); |
a193ed20 BL |
149 | } |
150 | ||
9037246b BL |
151 | static void link_lock(struct hdcp_workqueue *work, bool lock) |
152 | { | |
153 | ||
154 | int i = 0; | |
155 | ||
156 | for (i = 0; i < work->max_link; i++) { | |
157 | if (lock) | |
158 | mutex_lock(&work[i].mutex); | |
159 | else | |
160 | mutex_unlock(&work[i].mutex); | |
161 | } | |
162 | } | |
b1abe558 BL |
163 | void hdcp_update_display(struct hdcp_workqueue *hdcp_work, |
164 | unsigned int link_index, | |
165 | struct amdgpu_dm_connector *aconnector, | |
23eb4191 | 166 | uint8_t content_type, |
b1abe558 | 167 | bool enable_encryption) |
a193ed20 BL |
168 | { |
169 | struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; | |
170 | struct mod_hdcp_display *display = &hdcp_work[link_index].display; | |
171 | struct mod_hdcp_link *link = &hdcp_work[link_index].link; | |
b1abe558 | 172 | struct mod_hdcp_display_query query; |
aa9fdd5d | 173 | unsigned int conn_index = aconnector->base.index; |
a193ed20 BL |
174 | |
175 | mutex_lock(&hdcp_w->mutex); | |
aa9fdd5d | 176 | hdcp_w->aconnector[conn_index] = aconnector; |
a193ed20 | 177 | |
b1abe558 BL |
178 | query.display = NULL; |
179 | mod_hdcp_query_display(&hdcp_w->hdcp, aconnector->base.index, &query); | |
180 | ||
181 | if (query.display != NULL) { | |
182 | memcpy(display, query.display, sizeof(struct mod_hdcp_display)); | |
183 | mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); | |
184 | ||
23eb4191 BL |
185 | hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0; |
186 | ||
b1abe558 | 187 | if (enable_encryption) { |
f4406d6f BL |
188 | /* Explicitly set the saved SRM as sysfs call will be after we already enabled hdcp |
189 | * (s3 resume case) | |
190 | */ | |
191 | if (hdcp_work->srm_size > 0) | |
192 | psp_set_srm(hdcp_work->hdcp.config.psp.handle, hdcp_work->srm, hdcp_work->srm_size, | |
193 | &hdcp_work->srm_version); | |
194 | ||
4fe1fdcc | 195 | display->adjust.disable = MOD_HDCP_DISPLAY_NOT_DISABLE; |
c2850c12 BL |
196 | if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) { |
197 | hdcp_w->link.adjust.hdcp1.disable = 0; | |
23eb4191 | 198 | hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0; |
c2850c12 BL |
199 | } else if (content_type == DRM_MODE_HDCP_CONTENT_TYPE1) { |
200 | hdcp_w->link.adjust.hdcp1.disable = 1; | |
23eb4191 | 201 | hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1; |
c2850c12 | 202 | } |
23eb4191 | 203 | |
b1abe558 BL |
204 | schedule_delayed_work(&hdcp_w->property_validate_dwork, |
205 | msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS)); | |
206 | } else { | |
4fe1fdcc | 207 | display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION; |
aa9fdd5d | 208 | hdcp_w->encryption_status[conn_index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; |
b1abe558 BL |
209 | cancel_delayed_work(&hdcp_w->property_validate_dwork); |
210 | } | |
a193ed20 | 211 | |
b1abe558 BL |
212 | display->state = MOD_HDCP_DISPLAY_ACTIVE; |
213 | } | |
a193ed20 | 214 | |
b1abe558 | 215 | mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output); |
da3fd7ac | 216 | |
a193ed20 | 217 | process_output(hdcp_w); |
a193ed20 | 218 | mutex_unlock(&hdcp_w->mutex); |
a193ed20 BL |
219 | } |
220 | ||
a30a8c2f BL |
221 | static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, |
222 | unsigned int link_index, | |
223 | struct amdgpu_dm_connector *aconnector) | |
224 | { | |
225 | struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; | |
caa18dd6 | 226 | struct drm_connector_state *conn_state = aconnector->base.state; |
aa9fdd5d | 227 | unsigned int conn_index = aconnector->base.index; |
a30a8c2f BL |
228 | |
229 | mutex_lock(&hdcp_w->mutex); | |
aa9fdd5d | 230 | hdcp_w->aconnector[conn_index] = aconnector; |
a30a8c2f | 231 | |
caa18dd6 DDZ |
232 | /* the removal of display will invoke auth reset -> hdcp destroy and |
233 | * we'd expect the Content Protection (CP) property changed back to | |
234 | * DESIRED if at the time ENABLED. CP property change should occur | |
235 | * before the element removed from linked list. | |
236 | */ | |
237 | if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { | |
238 | conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
239 | ||
240 | DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n", | |
241 | aconnector->base.index, conn_state->hdcp_content_type, aconnector->base.dpms); | |
242 | } | |
243 | ||
a30a8c2f BL |
244 | mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); |
245 | ||
246 | process_output(hdcp_w); | |
247 | mutex_unlock(&hdcp_w->mutex); | |
248 | } | |
a193ed20 BL |
249 | void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index) |
250 | { | |
251 | struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; | |
aa9fdd5d | 252 | unsigned int conn_index; |
a193ed20 BL |
253 | |
254 | mutex_lock(&hdcp_w->mutex); | |
255 | ||
256 | mod_hdcp_reset_connection(&hdcp_w->hdcp, &hdcp_w->output); | |
257 | ||
da3fd7ac | 258 | cancel_delayed_work(&hdcp_w->property_validate_dwork); |
aa9fdd5d | 259 | |
260 | for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; conn_index++) { | |
261 | hdcp_w->encryption_status[conn_index] = | |
262 | MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; | |
263 | } | |
da3fd7ac | 264 | |
a193ed20 BL |
265 | process_output(hdcp_w); |
266 | ||
267 | mutex_unlock(&hdcp_w->mutex); | |
268 | } | |
269 | ||
270 | void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index) | |
271 | { | |
272 | struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; | |
273 | ||
274 | schedule_work(&hdcp_w->cpirq_work); | |
275 | } | |
276 | ||
277 | ||
278 | ||
279 | ||
280 | static void event_callback(struct work_struct *work) | |
281 | { | |
282 | struct hdcp_workqueue *hdcp_work; | |
283 | ||
284 | hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue, | |
285 | callback_dwork); | |
286 | ||
287 | mutex_lock(&hdcp_work->mutex); | |
288 | ||
2ebbe7c9 | 289 | cancel_delayed_work(&hdcp_work->callback_dwork); |
a193ed20 BL |
290 | |
291 | mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CALLBACK, | |
292 | &hdcp_work->output); | |
293 | ||
294 | process_output(hdcp_work); | |
295 | ||
296 | mutex_unlock(&hdcp_work->mutex); | |
297 | ||
298 | ||
299 | } | |
aa9fdd5d | 300 | |
da3fd7ac BL |
301 | static void event_property_update(struct work_struct *work) |
302 | { | |
da3fd7ac | 303 | struct hdcp_workqueue *hdcp_work = container_of(work, struct hdcp_workqueue, property_update_work); |
aa9fdd5d | 304 | struct amdgpu_dm_connector *aconnector = NULL; |
305 | struct drm_device *dev; | |
da3fd7ac | 306 | long ret; |
aa9fdd5d | 307 | unsigned int conn_index; |
308 | struct drm_connector *connector; | |
309 | struct drm_connector_state *conn_state; | |
da3fd7ac | 310 | |
aa9fdd5d | 311 | for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; conn_index++) { |
312 | aconnector = hdcp_work->aconnector[conn_index]; | |
da3fd7ac | 313 | |
aa9fdd5d | 314 | if (!aconnector) |
315 | continue; | |
da3fd7ac | 316 | |
aa9fdd5d | 317 | connector = &aconnector->base; |
318 | ||
319 | /* check if display connected */ | |
320 | if (connector->status != connector_status_connected) | |
321 | continue; | |
da3fd7ac | 322 | |
aa9fdd5d | 323 | conn_state = aconnector->base.state; |
324 | ||
325 | if (!conn_state) | |
326 | continue; | |
327 | ||
328 | dev = connector->dev; | |
329 | ||
330 | if (!dev) | |
331 | continue; | |
332 | ||
333 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
334 | mutex_lock(&hdcp_work->mutex); | |
335 | ||
336 | if (conn_state->commit) { | |
337 | ret = wait_for_completion_interruptible_timeout( | |
338 | &conn_state->commit->hw_done, 10 * HZ); | |
339 | if (ret == 0) { | |
340 | DRM_ERROR( | |
341 | "HDCP state unknown! Setting it to DESIRED"); | |
342 | hdcp_work->encryption_status[conn_index] = | |
343 | MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; | |
344 | } | |
345 | } | |
346 | if (hdcp_work->encryption_status[conn_index] != | |
347 | MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) { | |
348 | if (conn_state->hdcp_content_type == | |
72bb5030 | 349 | DRM_MODE_HDCP_CONTENT_TYPE0 && |
aa9fdd5d | 350 | hdcp_work->encryption_status[conn_index] <= |
351 | MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON) { | |
352 | ||
353 | DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_ENABLED\n"); | |
354 | drm_hdcp_update_content_protection( | |
355 | connector, | |
72bb5030 | 356 | DRM_MODE_CONTENT_PROTECTION_ENABLED); |
aa9fdd5d | 357 | } else if (conn_state->hdcp_content_type == |
72bb5030 | 358 | DRM_MODE_HDCP_CONTENT_TYPE1 && |
aa9fdd5d | 359 | hdcp_work->encryption_status[conn_index] == |
360 | MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON) { | |
361 | drm_hdcp_update_content_protection( | |
362 | connector, | |
72bb5030 | 363 | DRM_MODE_CONTENT_PROTECTION_ENABLED); |
aa9fdd5d | 364 | } |
72bb5030 | 365 | } else { |
aa9fdd5d | 366 | DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_DESIRED\n"); |
367 | drm_hdcp_update_content_protection( | |
368 | connector, DRM_MODE_CONTENT_PROTECTION_DESIRED); | |
369 | ||
72bb5030 | 370 | } |
aa9fdd5d | 371 | mutex_unlock(&hdcp_work->mutex); |
372 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
53e108aa | 373 | } |
da3fd7ac BL |
374 | } |
375 | ||
376 | static void event_property_validate(struct work_struct *work) | |
377 | { | |
378 | struct hdcp_workqueue *hdcp_work = | |
379 | container_of(to_delayed_work(work), struct hdcp_workqueue, property_validate_dwork); | |
380 | struct mod_hdcp_display_query query; | |
aa9fdd5d | 381 | struct amdgpu_dm_connector *aconnector; |
382 | unsigned int conn_index; | |
79c4ac0d | 383 | |
da3fd7ac | 384 | mutex_lock(&hdcp_work->mutex); |
a193ed20 | 385 | |
aa9fdd5d | 386 | for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; |
387 | conn_index++) { | |
388 | aconnector = hdcp_work->aconnector[conn_index]; | |
389 | ||
aa9fdd5d | 390 | if (!aconnector) |
391 | continue; | |
392 | ||
aa9fdd5d | 393 | /* check if display connected */ |
394 | if (aconnector->base.status != connector_status_connected) | |
395 | continue; | |
da3fd7ac | 396 | |
aa9fdd5d | 397 | if (!aconnector->base.state) |
398 | continue; | |
399 | ||
400 | query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; | |
401 | mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.index, | |
402 | &query); | |
403 | ||
404 | DRM_DEBUG_DRIVER("[HDCP_DM] disp %d, connector->CP %u, (query, work): (%d, %d)\n", | |
405 | aconnector->base.index, | |
406 | aconnector->base.state->content_protection, | |
407 | query.encryption_status, | |
408 | hdcp_work->encryption_status[conn_index]); | |
409 | ||
410 | if (query.encryption_status != | |
411 | hdcp_work->encryption_status[conn_index]) { | |
412 | DRM_DEBUG_DRIVER("[HDCP_DM] encryption_status change from %x to %x\n", | |
413 | hdcp_work->encryption_status[conn_index], query.encryption_status); | |
414 | ||
415 | hdcp_work->encryption_status[conn_index] = | |
416 | query.encryption_status; | |
417 | ||
418 | DRM_DEBUG_DRIVER("[HDCP_DM] trigger property_update_work\n"); | |
419 | ||
420 | schedule_work(&hdcp_work->property_update_work); | |
421 | } | |
da3fd7ac BL |
422 | } |
423 | ||
da3fd7ac BL |
424 | mutex_unlock(&hdcp_work->mutex); |
425 | } | |
a193ed20 BL |
426 | |
427 | static void event_watchdog_timer(struct work_struct *work) | |
428 | { | |
429 | struct hdcp_workqueue *hdcp_work; | |
430 | ||
431 | hdcp_work = container_of(to_delayed_work(work), | |
432 | struct hdcp_workqueue, | |
433 | watchdog_timer_dwork); | |
434 | ||
435 | mutex_lock(&hdcp_work->mutex); | |
436 | ||
2ebbe7c9 BL |
437 | cancel_delayed_work(&hdcp_work->watchdog_timer_dwork); |
438 | ||
a193ed20 BL |
439 | mod_hdcp_process_event(&hdcp_work->hdcp, |
440 | MOD_HDCP_EVENT_WATCHDOG_TIMEOUT, | |
441 | &hdcp_work->output); | |
442 | ||
443 | process_output(hdcp_work); | |
444 | ||
445 | mutex_unlock(&hdcp_work->mutex); | |
446 | ||
447 | } | |
448 | ||
449 | static void event_cpirq(struct work_struct *work) | |
450 | { | |
451 | struct hdcp_workqueue *hdcp_work; | |
452 | ||
453 | hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work); | |
454 | ||
455 | mutex_lock(&hdcp_work->mutex); | |
456 | ||
457 | mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CPIRQ, &hdcp_work->output); | |
458 | ||
459 | process_output(hdcp_work); | |
460 | ||
461 | mutex_unlock(&hdcp_work->mutex); | |
462 | ||
463 | } | |
464 | ||
465 | ||
e96b1b29 | 466 | void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *hdcp_work) |
a193ed20 BL |
467 | { |
468 | int i = 0; | |
469 | ||
470 | for (i = 0; i < hdcp_work->max_link; i++) { | |
471 | cancel_delayed_work_sync(&hdcp_work[i].callback_dwork); | |
472 | cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork); | |
473 | } | |
474 | ||
e96b1b29 | 475 | sysfs_remove_bin_file(kobj, &hdcp_work[0].attr); |
9037246b BL |
476 | kfree(hdcp_work->srm); |
477 | kfree(hdcp_work->srm_temp); | |
a193ed20 | 478 | kfree(hdcp_work); |
a193ed20 BL |
479 | } |
480 | ||
ef9de187 BL |
481 | |
482 | static bool enable_assr(void *handle, struct dc_link *link) | |
483 | { | |
484 | ||
485 | struct hdcp_workqueue *hdcp_work = handle; | |
486 | struct mod_hdcp hdcp = hdcp_work->hdcp; | |
487 | struct psp_context *psp = hdcp.config.psp.handle; | |
488 | struct ta_dtm_shared_memory *dtm_cmd; | |
489 | bool res = true; | |
490 | ||
ce97f37b | 491 | if (!psp->dtm_context.context.initialized) { |
ef9de187 BL |
492 | DRM_INFO("Failed to enable ASSR, DTM TA is not initialized."); |
493 | return false; | |
494 | } | |
495 | ||
ce97f37b | 496 | dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf; |
ef9de187 BL |
497 | |
498 | mutex_lock(&psp->dtm_context.mutex); | |
499 | memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory)); | |
500 | ||
501 | dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE; | |
502 | dtm_cmd->dtm_in_message.topology_assr_enable.display_topology_dig_be_index = link->link_enc_hw_inst; | |
503 | dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE; | |
504 | ||
505 | psp_dtm_invoke(psp, dtm_cmd->cmd_id); | |
506 | ||
507 | if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) { | |
508 | DRM_INFO("Failed to enable ASSR"); | |
509 | res = false; | |
510 | } | |
511 | ||
512 | mutex_unlock(&psp->dtm_context.mutex); | |
513 | ||
514 | return res; | |
515 | } | |
516 | ||
a193ed20 BL |
517 | static void update_config(void *handle, struct cp_psp_stream_config *config) |
518 | { | |
519 | struct hdcp_workqueue *hdcp_work = handle; | |
520 | struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx; | |
521 | int link_index = aconnector->dc_link->link_index; | |
522 | struct mod_hdcp_display *display = &hdcp_work[link_index].display; | |
523 | struct mod_hdcp_link *link = &hdcp_work[link_index].link; | |
26739690 | 524 | struct drm_connector_state *conn_state; |
4d31819a | 525 | struct dc_sink *sink = NULL; |
035f5496 | 526 | bool link_is_hdcp14 = false; |
a193ed20 | 527 | |
a30a8c2f BL |
528 | if (config->dpms_off) { |
529 | hdcp_remove_display(hdcp_work, link_index, aconnector); | |
530 | return; | |
531 | } | |
3528cae9 LHM |
532 | |
533 | memset(display, 0, sizeof(*display)); | |
534 | memset(link, 0, sizeof(*link)); | |
535 | ||
536 | display->index = aconnector->base.index; | |
a193ed20 BL |
537 | display->state = MOD_HDCP_DISPLAY_ACTIVE; |
538 | ||
4d31819a WL |
539 | if (aconnector->dc_sink) |
540 | sink = aconnector->dc_sink; | |
541 | else if (aconnector->dc_em_sink) | |
542 | sink = aconnector->dc_em_sink; | |
543 | ||
544 | if (sink != NULL) | |
545 | link->mode = mod_hdcp_signal_type_to_operation_mode(sink->sink_signal); | |
a193ed20 BL |
546 | |
547 | display->controller = CONTROLLER_ID_D0 + config->otg_inst; | |
aac6d439 WL |
548 | display->dig_fe = config->dig_fe; |
549 | link->dig_be = config->dig_be; | |
a193ed20 | 550 | link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1; |
bf62221e NK |
551 | display->stream_enc_idx = config->stream_enc_idx; |
552 | link->link_enc_idx = config->link_enc_idx; | |
f51d22b0 | 553 | link->dio_output_id = config->dio_output_idx; |
bf62221e | 554 | link->phy_idx = config->phy_idx; |
10a36226 | 555 | |
4d31819a WL |
556 | if (sink) |
557 | link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal); | |
035f5496 | 558 | link->hdcp_supported_informational = link_is_hdcp14; |
a193ed20 | 559 | link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; |
aac6d439 WL |
560 | link->dp.assr_enabled = config->assr_enabled; |
561 | link->dp.mst_enabled = config->mst_enabled; | |
c32699ca | 562 | link->dp.dp2_enabled = config->dp2_enabled; |
f51d22b0 | 563 | link->dp.usb4_enabled = config->usb4_enabled; |
4fe1fdcc | 564 | display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION; |
28f7e897 | 565 | link->adjust.auth_delay = 2; |
c2850c12 | 566 | link->adjust.hdcp1.disable = 0; |
26739690 | 567 | conn_state = aconnector->base.state; |
a193ed20 | 568 | |
caa18dd6 | 569 | DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index, |
26739690 DDZ |
570 | (!!aconnector->base.state) ? aconnector->base.state->content_protection : -1, |
571 | (!!aconnector->base.state) ? aconnector->base.state->hdcp_content_type : -1); | |
572 | ||
72bb5030 | 573 | if (conn_state) |
574 | hdcp_update_display(hdcp_work, link_index, aconnector, | |
575 | conn_state->hdcp_content_type, false); | |
a193ed20 BL |
576 | } |
577 | ||
9037246b BL |
578 | |
579 | /* NOTE: From the usermodes prospective you only need to call write *ONCE*, the kernel | |
580 | * will automatically call once or twice depending on the size | |
581 | * | |
582 | * call: "cat file > /sys/class/drm/card0/device/hdcp_srm" from usermode no matter what the size is | |
583 | * | |
584 | * The kernel can only send PAGE_SIZE at once and since MAX_SRM_FILE(5120) > PAGE_SIZE(4096), | |
585 | * srm_data_write can be called multiple times. | |
586 | * | |
587 | * sysfs interface doesn't tell us the size we will get so we are sending partial SRMs to psp and on | |
588 | * the last call we will send the full SRM. PSP will fail on every call before the last. | |
589 | * | |
590 | * This means we don't know if the SRM is good until the last call. And because of this limitation we | |
591 | * cannot throw errors early as it will stop the kernel from writing to sysfs | |
592 | * | |
593 | * Example 1: | |
594 | * Good SRM size = 5096 | |
595 | * first call to write 4096 -> PSP fails | |
596 | * Second call to write 1000 -> PSP Pass -> SRM is set | |
597 | * | |
598 | * Example 2: | |
599 | * Bad SRM size = 4096 | |
600 | * first call to write 4096 -> PSP fails (This is the same as above, but we don't know if this | |
601 | * is the last call) | |
602 | * | |
603 | * Solution?: | |
604 | * 1: Parse the SRM? -> It is signed so we don't know the EOF | |
605 | * 2: We can have another sysfs that passes the size before calling set. -> simpler solution | |
606 | * below | |
607 | * | |
608 | * Easy Solution: | |
609 | * Always call get after Set to verify if set was successful. | |
610 | * +----------------------+ | |
611 | * | Why it works: | | |
612 | * +----------------------+ | |
613 | * PSP will only update its srm if its older than the one we are trying to load. | |
614 | * Always do set first than get. | |
615 | * -if we try to "1. SET" a older version PSP will reject it and we can "2. GET" the newer | |
616 | * version and save it | |
617 | * | |
618 | * -if we try to "1. SET" a newer version PSP will accept it and we can "2. GET" the | |
619 | * same(newer) version back and save it | |
620 | * | |
621 | * -if we try to "1. SET" a newer version and PSP rejects it. That means the format is | |
622 | * incorrect/corrupted and we should correct our SRM by getting it from PSP | |
623 | */ | |
624 | static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, struct bin_attribute *bin_attr, char *buffer, | |
625 | loff_t pos, size_t count) | |
626 | { | |
627 | struct hdcp_workqueue *work; | |
628 | uint32_t srm_version = 0; | |
629 | ||
630 | work = container_of(bin_attr, struct hdcp_workqueue, attr); | |
631 | link_lock(work, true); | |
632 | ||
633 | memcpy(work->srm_temp + pos, buffer, count); | |
634 | ||
635 | if (!psp_set_srm(work->hdcp.config.psp.handle, work->srm_temp, pos + count, &srm_version)) { | |
636 | DRM_DEBUG_DRIVER("HDCP SRM SET version 0x%X", srm_version); | |
637 | memcpy(work->srm, work->srm_temp, pos + count); | |
638 | work->srm_size = pos + count; | |
639 | work->srm_version = srm_version; | |
640 | } | |
641 | ||
642 | ||
643 | link_lock(work, false); | |
644 | ||
645 | return count; | |
646 | } | |
647 | ||
648 | static ssize_t srm_data_read(struct file *filp, struct kobject *kobj, struct bin_attribute *bin_attr, char *buffer, | |
649 | loff_t pos, size_t count) | |
650 | { | |
651 | struct hdcp_workqueue *work; | |
652 | uint8_t *srm = NULL; | |
653 | uint32_t srm_version; | |
654 | uint32_t srm_size; | |
655 | size_t ret = count; | |
656 | ||
657 | work = container_of(bin_attr, struct hdcp_workqueue, attr); | |
658 | ||
659 | link_lock(work, true); | |
660 | ||
661 | srm = psp_get_srm(work->hdcp.config.psp.handle, &srm_version, &srm_size); | |
662 | ||
8ef51b42 JK |
663 | if (!srm) { |
664 | ret = -EINVAL; | |
665 | goto ret; | |
666 | } | |
9037246b BL |
667 | |
668 | if (pos >= srm_size) | |
669 | ret = 0; | |
670 | ||
671 | if (srm_size - pos < count) { | |
672 | memcpy(buffer, srm + pos, srm_size - pos); | |
673 | ret = srm_size - pos; | |
674 | goto ret; | |
675 | } | |
676 | ||
677 | memcpy(buffer, srm + pos, count); | |
678 | ||
679 | ret: | |
680 | link_lock(work, false); | |
681 | return ret; | |
682 | } | |
683 | ||
684 | /* From the hdcp spec (5.Renewability) SRM needs to be stored in a non-volatile memory. | |
685 | * | |
686 | * For example, | |
687 | * if Application "A" sets the SRM (ver 2) and we reboot/suspend and later when Application "B" | |
688 | * needs to use HDCP, the version in PSP should be SRM(ver 2). So SRM should be persistent | |
689 | * across boot/reboots/suspend/resume/shutdown | |
690 | * | |
691 | * Currently when the system goes down (suspend/shutdown) the SRM is cleared from PSP. For HDCP we need | |
692 | * to make the SRM persistent. | |
693 | * | |
694 | * -PSP owns the checking of SRM but doesn't have the ability to store it in a non-volatile memory. | |
695 | * -The kernel cannot write to the file systems. | |
696 | * -So we need usermode to do this for us, which is why an interface for usermode is needed | |
697 | * | |
698 | * | |
699 | * | |
700 | * Usermode can read/write to/from PSP using the sysfs interface | |
701 | * For example: | |
702 | * to save SRM from PSP to storage : cat /sys/class/drm/card0/device/hdcp_srm > srmfile | |
703 | * to load from storage to PSP: cat srmfile > /sys/class/drm/card0/device/hdcp_srm | |
704 | */ | |
705 | static const struct bin_attribute data_attr = { | |
706 | .attr = {.name = "hdcp_srm", .mode = 0664}, | |
707 | .size = PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, /* Limit SRM size */ | |
708 | .write = srm_data_write, | |
709 | .read = srm_data_read, | |
710 | }; | |
711 | ||
712 | ||
e50dc171 | 713 | struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct cp_psp *cp_psp, struct dc *dc) |
a193ed20 BL |
714 | { |
715 | ||
716 | int max_caps = dc->caps.max_links; | |
9037246b | 717 | struct hdcp_workqueue *hdcp_work; |
a193ed20 BL |
718 | int i = 0; |
719 | ||
9037246b | 720 | hdcp_work = kcalloc(max_caps, sizeof(*hdcp_work), GFP_KERNEL); |
898c7302 | 721 | if (ZERO_OR_NULL_PTR(hdcp_work)) |
9037246b BL |
722 | return NULL; |
723 | ||
724 | hdcp_work->srm = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, sizeof(*hdcp_work->srm), GFP_KERNEL); | |
725 | ||
726 | if (hdcp_work->srm == NULL) | |
727 | goto fail_alloc_context; | |
728 | ||
729 | hdcp_work->srm_temp = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, sizeof(*hdcp_work->srm_temp), GFP_KERNEL); | |
730 | ||
731 | if (hdcp_work->srm_temp == NULL) | |
a193ed20 BL |
732 | goto fail_alloc_context; |
733 | ||
734 | hdcp_work->max_link = max_caps; | |
735 | ||
736 | for (i = 0; i < max_caps; i++) { | |
a193ed20 BL |
737 | mutex_init(&hdcp_work[i].mutex); |
738 | ||
739 | INIT_WORK(&hdcp_work[i].cpirq_work, event_cpirq); | |
da3fd7ac | 740 | INIT_WORK(&hdcp_work[i].property_update_work, event_property_update); |
a193ed20 BL |
741 | INIT_DELAYED_WORK(&hdcp_work[i].callback_dwork, event_callback); |
742 | INIT_DELAYED_WORK(&hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer); | |
da3fd7ac | 743 | INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate); |
a193ed20 | 744 | |
e50dc171 | 745 | hdcp_work[i].hdcp.config.psp.handle = &adev->psp; |
de7cc1b4 | 746 | if (dc->ctx->dce_version == DCN_VERSION_3_1 || |
e850f6b1 | 747 | dc->ctx->dce_version == DCN_VERSION_3_14 || |
b5b8ed44 | 748 | dc->ctx->dce_version == DCN_VERSION_3_15 || |
de7cc1b4 | 749 | dc->ctx->dce_version == DCN_VERSION_3_16) |
bf62221e | 750 | hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1; |
a193ed20 | 751 | hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i); |
55b50e68 BL |
752 | hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c; |
753 | hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c; | |
754 | hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd = lp_write_dpcd; | |
755 | hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd = lp_read_dpcd; | |
aa9fdd5d | 756 | |
757 | memset(hdcp_work[i].aconnector, 0, | |
758 | sizeof(struct amdgpu_dm_connector *) * | |
759 | AMDGPU_DM_MAX_DISPLAY_INDEX); | |
760 | memset(hdcp_work[i].encryption_status, 0, | |
761 | sizeof(enum mod_hdcp_encryption_status) * | |
762 | AMDGPU_DM_MAX_DISPLAY_INDEX); | |
a193ed20 BL |
763 | } |
764 | ||
765 | cp_psp->funcs.update_stream_config = update_config; | |
ef9de187 | 766 | cp_psp->funcs.enable_assr = enable_assr; |
a193ed20 BL |
767 | cp_psp->handle = hdcp_work; |
768 | ||
9037246b BL |
769 | /* File created at /sys/class/drm/card0/device/hdcp_srm*/ |
770 | hdcp_work[0].attr = data_attr; | |
fe1c97d0 | 771 | sysfs_bin_attr_init(&hdcp_work[0].attr); |
9037246b BL |
772 | |
773 | if (sysfs_create_bin_file(&adev->dev->kobj, &hdcp_work[0].attr)) | |
774 | DRM_WARN("Failed to create device file hdcp_srm"); | |
775 | ||
a193ed20 BL |
776 | return hdcp_work; |
777 | ||
778 | fail_alloc_context: | |
9037246b BL |
779 | kfree(hdcp_work->srm); |
780 | kfree(hdcp_work->srm_temp); | |
a193ed20 BL |
781 | kfree(hdcp_work); |
782 | ||
783 | return NULL; | |
784 | ||
785 | ||
786 | ||
787 | } | |
788 | ||
789 | ||
790 |