Commit | Line | Data |
---|---|---|
4562236b | 1 | /* |
b972b4f9 | 2 | * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. |
4562236b HW |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #ifndef __AMDGPU_DM_H__ | |
27 | #define __AMDGPU_DM_H__ | |
28 | ||
da68386d | 29 | #include <drm/display/drm_dp_mst_helper.h> |
e7b07cee | 30 | #include <drm/drm_atomic.h> |
831583c3 SR |
31 | #include <drm/drm_connector.h> |
32 | #include <drm/drm_crtc.h> | |
831583c3 | 33 | #include <drm/drm_plane.h> |
028c4ccf | 34 | #include "link_service_types.h" |
4562236b HW |
35 | |
36 | /* | |
37 | * This file contains the definition for amdgpu_display_manager | |
38 | * and its API for amdgpu driver's use. | |
39 | * This component provides all the display related functionality | |
40 | * and this is the only component that calls DAL API. | |
41 | * The API contained here intended for amdgpu driver use. | |
42 | * The API that is called directly from KMS framework is located | |
43 | * in amdgpu_dm_kms.h file | |
44 | */ | |
45 | ||
46 | #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 | |
f74367e4 AD |
47 | |
48 | #define AMDGPU_DM_MAX_CRTC 6 | |
49 | ||
118b4627 | 50 | #define AMDGPU_DM_MAX_NUM_EDP 2 |
e27c41d5 JS |
51 | |
52 | #define AMDGPU_DMUB_NOTIFICATION_MAX 5 | |
88f52b1f | 53 | |
ec8e59cb BL |
54 | #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A |
55 | #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 | |
56 | #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 | |
4562236b HW |
57 | /* |
58 | #include "include/amdgpu_dal_power_if.h" | |
59 | #include "amdgpu_dm_irq.h" | |
60 | */ | |
61 | ||
62 | #include "irq_types.h" | |
63 | #include "signal_types.h" | |
14b25846 | 64 | #include "amdgpu_dm_crc.h" |
5b49da02 | 65 | #include "mod_info_packet.h" |
81927e28 | 66 | struct aux_payload; |
ead08b95 | 67 | struct set_config_cmd_payload; |
81927e28 | 68 | enum aux_return_code_type; |
ead08b95 | 69 | enum set_config_status; |
4562236b HW |
70 | |
71 | /* Forward declarations */ | |
72 | struct amdgpu_device; | |
09a5df6c | 73 | struct amdgpu_crtc; |
4562236b | 74 | struct drm_device; |
c99c7d6e | 75 | struct dc; |
743b9786 NK |
76 | struct amdgpu_bo; |
77 | struct dmub_srv; | |
f4fb5595 | 78 | struct dc_plane_state; |
81927e28 | 79 | struct dmub_notification; |
4562236b | 80 | |
ec8e59cb BL |
81 | struct amd_vsdb_block { |
82 | unsigned char ieee_id[3]; | |
83 | unsigned char version; | |
84 | unsigned char feature_caps; | |
85 | }; | |
86 | ||
4562236b HW |
87 | struct common_irq_params { |
88 | struct amdgpu_device *adev; | |
89 | enum dc_irq_source irq_src; | |
47588233 | 90 | atomic64_t previous_timestamp; |
4562236b HW |
91 | }; |
92 | ||
b8592b48 LL |
93 | /** |
94 | * struct dm_compressor_info - Buffer info used by frame buffer compression | |
95 | * @cpu_addr: MMIO cpu addr | |
96 | * @bo_ptr: Pointer to the buffer object | |
97 | * @gpu_addr: MMIO gpu addr | |
98 | */ | |
4d154b85 | 99 | struct dm_compressor_info { |
a32e24b4 RL |
100 | void *cpu_addr; |
101 | struct amdgpu_bo *bo_ptr; | |
102 | uint64_t gpu_addr; | |
103 | }; | |
a32e24b4 | 104 | |
e27c41d5 JS |
105 | typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); |
106 | ||
107 | /** | |
108 | * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ | |
109 | * | |
110 | * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq | |
111 | * @dmub_notify: notification for callback function | |
112 | * @adev: amdgpu_device pointer | |
113 | */ | |
114 | struct dmub_hpd_work { | |
115 | struct work_struct handle_hpd_work; | |
116 | struct dmub_notification *dmub_notify; | |
117 | struct amdgpu_device *adev; | |
118 | }; | |
119 | ||
d7faf6f5 | 120 | /** |
09a5df6c NK |
121 | * struct vblank_control_work - Work data for vblank control |
122 | * @work: Kernel work data for the work event | |
d7faf6f5 | 123 | * @dm: amdgpu display manager device |
09a5df6c | 124 | * @acrtc: amdgpu CRTC instance for which the event has occurred |
58aa1c50 | 125 | * @stream: DC stream for which the event has occurred |
09a5df6c | 126 | * @enable: true if enabling vblank |
d7faf6f5 | 127 | */ |
09a5df6c NK |
128 | struct vblank_control_work { |
129 | struct work_struct work; | |
d7faf6f5 | 130 | struct amdgpu_display_manager *dm; |
09a5df6c | 131 | struct amdgpu_crtc *acrtc; |
58aa1c50 | 132 | struct dc_stream_state *stream; |
d7faf6f5 QZ |
133 | bool enable; |
134 | }; | |
135 | ||
206bbafe | 136 | /** |
94562810 RS |
137 | * struct amdgpu_dm_backlight_caps - Information about backlight |
138 | * | |
139 | * Describe the backlight support for ACPI or eDP AUX. | |
206bbafe DF |
140 | */ |
141 | struct amdgpu_dm_backlight_caps { | |
94562810 RS |
142 | /** |
143 | * @ext_caps: Keep the data struct with all the information about the | |
144 | * display support for HDR. | |
145 | */ | |
146 | union dpcd_sink_ext_caps *ext_caps; | |
147 | /** | |
148 | * @aux_min_input_signal: Min brightness value supported by the display | |
149 | */ | |
150 | u32 aux_min_input_signal; | |
151 | /** | |
152 | * @aux_max_input_signal: Max brightness value supported by the display | |
153 | * in nits. | |
154 | */ | |
155 | u32 aux_max_input_signal; | |
156 | /** | |
157 | * @min_input_signal: minimum possible input in range 0-255. | |
158 | */ | |
206bbafe | 159 | int min_input_signal; |
94562810 RS |
160 | /** |
161 | * @max_input_signal: maximum possible input in range 0-255. | |
162 | */ | |
206bbafe | 163 | int max_input_signal; |
94562810 RS |
164 | /** |
165 | * @caps_valid: true if these values are from the ACPI interface. | |
166 | */ | |
206bbafe | 167 | bool caps_valid; |
94562810 RS |
168 | /** |
169 | * @aux_support: Describes if the display supports AUX backlight. | |
170 | */ | |
171 | bool aux_support; | |
206bbafe DF |
172 | }; |
173 | ||
0dd79532 ZL |
174 | /** |
175 | * struct dal_allocation - Tracks mapped FB memory for SMU communication | |
cbd4945c AD |
176 | * @list: list of dal allocations |
177 | * @bo: GPU buffer object | |
178 | * @cpu_ptr: CPU virtual address of the GPU buffer object | |
179 | * @gpu_addr: GPU virtual address of the GPU buffer object | |
0dd79532 ZL |
180 | */ |
181 | struct dal_allocation { | |
182 | struct list_head list; | |
183 | struct amdgpu_bo *bo; | |
184 | void *cpu_ptr; | |
185 | u64 gpu_addr; | |
186 | }; | |
187 | ||
8e794421 WL |
188 | /** |
189 | * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq | |
190 | * offload work | |
191 | */ | |
192 | struct hpd_rx_irq_offload_work_queue { | |
193 | /** | |
194 | * @wq: workqueue structure to queue offload work. | |
195 | */ | |
196 | struct workqueue_struct *wq; | |
197 | /** | |
198 | * @offload_lock: To protect fields of offload work queue. | |
199 | */ | |
200 | spinlock_t offload_lock; | |
201 | /** | |
202 | * @is_handling_link_loss: Used to prevent inserting link loss event when | |
203 | * we're handling link loss | |
204 | */ | |
205 | bool is_handling_link_loss; | |
bb4fa525 WL |
206 | /** |
207 | * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message | |
208 | * ready event when we're already handling mst message ready event | |
209 | */ | |
210 | bool is_handling_mst_msg_rdy_event; | |
8e794421 WL |
211 | /** |
212 | * @aconnector: The aconnector that this work queue is attached to | |
213 | */ | |
214 | struct amdgpu_dm_connector *aconnector; | |
215 | }; | |
216 | ||
217 | /** | |
218 | * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure | |
219 | */ | |
220 | struct hpd_rx_irq_offload_work { | |
221 | /** | |
222 | * @work: offload work | |
223 | */ | |
224 | struct work_struct work; | |
225 | /** | |
226 | * @data: reference irq data which is used while handling offload work | |
227 | */ | |
228 | union hpd_irq_data data; | |
229 | /** | |
230 | * @offload_wq: offload work queue that this work is queued to | |
231 | */ | |
232 | struct hpd_rx_irq_offload_work_queue *offload_wq; | |
233 | }; | |
234 | ||
b8592b48 LL |
235 | /** |
236 | * struct amdgpu_display_manager - Central amdgpu display manager device | |
237 | * | |
238 | * @dc: Display Core control structure | |
239 | * @adev: AMDGPU base driver structure | |
240 | * @ddev: DRM base driver structure | |
241 | * @display_indexes_num: Max number of display streams supported | |
242 | * @irq_handler_list_table_lock: Synchronizes access to IRQ tables | |
243 | * @backlight_dev: Backlight control device | |
b8e8c934 HW |
244 | * @backlight_link: Link on which to control backlight |
245 | * @backlight_caps: Capabilities of the backlight device | |
246 | * @freesync_module: Module handling freesync calculations | |
282fd22b | 247 | * @hdcp_workqueue: AMDGPU content protection queue |
b8e8c934 HW |
248 | * @fw_dmcu: Reference to DMCU firmware |
249 | * @dmcu_fw_version: Version of the DMCU firmware | |
250 | * @soc_bounding_box: SOC bounding box values provided by gpu_info FW | |
b8592b48 | 251 | * @cached_state: Caches device atomic state for suspend/resume |
282fd22b | 252 | * @cached_dc_state: Cached state of content streams |
4d154b85 | 253 | * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info |
8d8ac1a1 MCC |
254 | * @force_timing_sync: set via debugfs. When set, indicates that all connected |
255 | * displays will be forced to synchronize. | |
a273f315 | 256 | * @dmcub_trace_event_en: enable dmcub trace events |
2639d3e4 MCC |
257 | * @dmub_outbox_params: DMUB Outbox parameters |
258 | * @num_of_edps: number of backlight eDPs | |
259 | * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the | |
260 | * driver when true | |
261 | * @dmub_aux_transfer_done: struct completion used to indicate when DMUB | |
262 | * transfers are done | |
263 | * @delayed_hpd_wq: work queue used to delay DMUB HPD work | |
b8592b48 | 264 | */ |
4562236b | 265 | struct amdgpu_display_manager { |
b8592b48 | 266 | |
4562236b | 267 | struct dc *dc; |
b8592b48 | 268 | |
743b9786 NK |
269 | /** |
270 | * @dmub_srv: | |
271 | * | |
272 | * DMUB service, used for controlling the DMUB on hardware | |
273 | * that supports it. The pointer to the dmub_srv will be | |
274 | * NULL on hardware that does not support it. | |
275 | */ | |
276 | struct dmub_srv *dmub_srv; | |
277 | ||
e27c41d5 JS |
278 | /** |
279 | * @dmub_notify: | |
280 | * | |
281 | * Notification from DMUB. | |
282 | */ | |
283 | ||
81927e28 JS |
284 | struct dmub_notification *dmub_notify; |
285 | ||
e27c41d5 JS |
286 | /** |
287 | * @dmub_callback: | |
288 | * | |
289 | * Callback functions to handle notification from DMUB. | |
290 | */ | |
291 | ||
292 | dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; | |
293 | ||
294 | /** | |
295 | * @dmub_thread_offload: | |
296 | * | |
297 | * Flag to indicate if callback is offload. | |
298 | */ | |
299 | ||
300 | bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; | |
301 | ||
8c7aea40 NK |
302 | /** |
303 | * @dmub_fb_info: | |
304 | * | |
305 | * Framebuffer regions for the DMUB. | |
306 | */ | |
307 | struct dmub_srv_fb_info *dmub_fb_info; | |
308 | ||
743b9786 NK |
309 | /** |
310 | * @dmub_fw: | |
311 | * | |
312 | * DMUB firmware, required on hardware that has DMUB support. | |
313 | */ | |
314 | const struct firmware *dmub_fw; | |
315 | ||
316 | /** | |
317 | * @dmub_bo: | |
318 | * | |
319 | * Buffer object for the DMUB. | |
320 | */ | |
321 | struct amdgpu_bo *dmub_bo; | |
322 | ||
323 | /** | |
324 | * @dmub_bo_gpu_addr: | |
325 | * | |
326 | * GPU virtual address for the DMUB buffer object. | |
327 | */ | |
328 | u64 dmub_bo_gpu_addr; | |
329 | ||
330 | /** | |
331 | * @dmub_bo_cpu_addr: | |
332 | * | |
333 | * CPU address for the DMUB buffer object. | |
334 | */ | |
335 | void *dmub_bo_cpu_addr; | |
336 | ||
337 | /** | |
338 | * @dmcub_fw_version: | |
339 | * | |
340 | * DMCUB firmware version. | |
341 | */ | |
342 | uint32_t dmcub_fw_version; | |
343 | ||
b8592b48 LL |
344 | /** |
345 | * @cgs_device: | |
346 | * | |
347 | * The Common Graphics Services device. It provides an interface for | |
348 | * accessing registers. | |
349 | */ | |
4562236b | 350 | struct cgs_device *cgs_device; |
4562236b | 351 | |
b8592b48 LL |
352 | struct amdgpu_device *adev; |
353 | struct drm_device *ddev; | |
4562236b HW |
354 | u16 display_indexes_num; |
355 | ||
eb3dc897 | 356 | /** |
b8e8c934 | 357 | * @atomic_obj: |
eb3dc897 NK |
358 | * |
359 | * In combination with &dm_atomic_state it helps manage | |
360 | * global atomic state that doesn't map cleanly into existing | |
361 | * drm resources, like &dc_context. | |
362 | */ | |
363 | struct drm_private_obj atomic_obj; | |
364 | ||
674e78ac NK |
365 | /** |
366 | * @dc_lock: | |
367 | * | |
368 | * Guards access to DC functions that can issue register write | |
369 | * sequences. | |
370 | */ | |
371 | struct mutex dc_lock; | |
372 | ||
6ce8f316 NK |
373 | /** |
374 | * @audio_lock: | |
375 | * | |
376 | * Guards access to audio instance changes. | |
377 | */ | |
378 | struct mutex audio_lock; | |
379 | ||
380 | /** | |
381 | * @audio_component: | |
382 | * | |
383 | * Used to notify ELD changes to sound driver. | |
384 | */ | |
385 | struct drm_audio_component *audio_component; | |
386 | ||
387 | /** | |
388 | * @audio_registered: | |
389 | * | |
390 | * True if the audio component has been registered | |
391 | * successfully, false otherwise. | |
392 | */ | |
393 | bool audio_registered; | |
394 | ||
b8592b48 LL |
395 | /** |
396 | * @irq_handler_list_low_tab: | |
397 | * | |
398 | * Low priority IRQ handler table. | |
4562236b | 399 | * |
b8592b48 LL |
400 | * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ |
401 | * source. Low priority IRQ handlers are deferred to a workqueue to be | |
402 | * processed. Hence, they can sleep. | |
4562236b HW |
403 | * |
404 | * Note that handlers are called in the same order as they were | |
405 | * registered (FIFO). | |
406 | */ | |
b6f91fc1 | 407 | struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; |
b8592b48 LL |
408 | |
409 | /** | |
410 | * @irq_handler_list_high_tab: | |
411 | * | |
412 | * High priority IRQ handler table. | |
413 | * | |
414 | * It is a n*m table, same as &irq_handler_list_low_tab. However, | |
415 | * handlers in this table are not deferred and are called immediately. | |
416 | */ | |
4562236b HW |
417 | struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; |
418 | ||
b8592b48 LL |
419 | /** |
420 | * @pflip_params: | |
421 | * | |
422 | * Page flip IRQ parameters, passed to registered handlers when | |
423 | * triggered. | |
424 | */ | |
4562236b HW |
425 | struct common_irq_params |
426 | pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; | |
427 | ||
b8592b48 LL |
428 | /** |
429 | * @vblank_params: | |
430 | * | |
431 | * Vertical blanking IRQ parameters, passed to registered handlers when | |
432 | * triggered. | |
433 | */ | |
4562236b | 434 | struct common_irq_params |
b57de80a | 435 | vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; |
4562236b | 436 | |
86bc2219 WL |
437 | /** |
438 | * @vline0_params: | |
439 | * | |
440 | * OTG vertical interrupt0 IRQ parameters, passed to registered | |
441 | * handlers when triggered. | |
442 | */ | |
443 | struct common_irq_params | |
444 | vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; | |
445 | ||
d2574c33 MK |
446 | /** |
447 | * @vupdate_params: | |
448 | * | |
449 | * Vertical update IRQ parameters, passed to registered handlers when | |
450 | * triggered. | |
451 | */ | |
452 | struct common_irq_params | |
453 | vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; | |
454 | ||
a08f16cf LHM |
455 | /** |
456 | * @dmub_trace_params: | |
457 | * | |
458 | * DMUB trace event IRQ parameters, passed to registered handlers when | |
459 | * triggered. | |
460 | */ | |
461 | struct common_irq_params | |
462 | dmub_trace_params[1]; | |
463 | ||
81927e28 JS |
464 | struct common_irq_params |
465 | dmub_outbox_params[1]; | |
466 | ||
4562236b HW |
467 | spinlock_t irq_handler_list_table_lock; |
468 | ||
7fd13bae | 469 | struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; |
4562236b | 470 | |
118b4627 ML |
471 | const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; |
472 | ||
473 | uint8_t num_of_edps; | |
474 | ||
7fd13bae | 475 | struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; |
4562236b | 476 | |
4562236b | 477 | struct mod_freesync *freesync_module; |
52704fca | 478 | struct hdcp_workqueue *hdcp_workqueue; |
a3621485 | 479 | |
61a74712 | 480 | /** |
09a5df6c | 481 | * @vblank_control_workqueue: |
61a74712 | 482 | * |
09a5df6c | 483 | * Deferred work for vblank control events. |
61a74712 | 484 | */ |
09a5df6c | 485 | struct workqueue_struct *vblank_control_workqueue; |
d7faf6f5 | 486 | |
a3621485 | 487 | struct drm_atomic_state *cached_state; |
cdaae837 | 488 | struct dc_state *cached_dc_state; |
5099114b | 489 | |
4d154b85 | 490 | struct dm_compressor_info compressor; |
a94d5569 DF |
491 | |
492 | const struct firmware *fw_dmcu; | |
ee6e89c0 | 493 | uint32_t dmcu_fw_version; |
48321c3d | 494 | /** |
b8e8c934 HW |
495 | * @soc_bounding_box: |
496 | * | |
48321c3d HW |
497 | * gpu_info FW provided soc bounding box struct or 0 if not |
498 | * available in FW | |
499 | */ | |
500 | const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; | |
f74367e4 | 501 | |
71338cb4 | 502 | /** |
1dbb6c8f | 503 | * @active_vblank_irq_count: |
71338cb4 BL |
504 | * |
505 | * number of currently active vblank irqs | |
506 | */ | |
507 | uint32_t active_vblank_irq_count; | |
61a74712 | 508 | |
9a65df19 | 509 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
1c85f3db | 510 | /** |
1b11ff76 | 511 | * @secure_display_ctxs: |
1c85f3db | 512 | * |
1b11ff76 AL |
513 | * Store the ROI information and the work_struct to command dmub and psp for |
514 | * all crtcs. | |
1c85f3db | 515 | */ |
1b11ff76 | 516 | struct secure_display_context *secure_display_ctxs; |
9a65df19 | 517 | #endif |
8e794421 WL |
518 | /** |
519 | * @hpd_rx_offload_wq: | |
520 | * | |
521 | * Work queue to offload works of hpd_rx_irq | |
522 | */ | |
523 | struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; | |
f74367e4 AD |
524 | /** |
525 | * @mst_encoders: | |
526 | * | |
527 | * fake encoders used for DP MST. | |
528 | */ | |
529 | struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; | |
0749ddeb | 530 | bool force_timing_sync; |
b972b4f9 | 531 | bool disable_hpd_irq; |
46a83eba | 532 | bool dmcub_trace_event_en; |
0dd79532 ZL |
533 | /** |
534 | * @da_list: | |
535 | * | |
536 | * DAL fb memory allocation list, for communication with SMU. | |
537 | */ | |
538 | struct list_head da_list; | |
81927e28 | 539 | struct completion dmub_aux_transfer_done; |
e27c41d5 | 540 | struct workqueue_struct *delayed_hpd_wq; |
3d6c9164 AD |
541 | |
542 | /** | |
543 | * @brightness: | |
544 | * | |
545 | * cached backlight values. | |
546 | */ | |
547 | u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; | |
4052287a S |
548 | /** |
549 | * @actual_brightness: | |
550 | * | |
551 | * last successfully applied backlight values. | |
552 | */ | |
553 | u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; | |
57b9f338 FZ |
554 | |
555 | /** | |
556 | * @aux_hpd_discon_quirk: | |
557 | * | |
558 | * quirk for hpd discon while aux is on-going. | |
559 | * occurred on certain intel platform | |
560 | */ | |
561 | bool aux_hpd_discon_quirk; | |
ead08b95 SW |
562 | |
563 | /** | |
564 | * @dpia_aux_lock: | |
565 | * | |
566 | * Guards access to DPIA AUX | |
567 | */ | |
568 | struct mutex dpia_aux_lock; | |
0749ddeb EB |
569 | }; |
570 | ||
571 | enum dsc_clock_force_state { | |
572 | DSC_CLK_FORCE_DEFAULT = 0, | |
573 | DSC_CLK_FORCE_ENABLE, | |
574 | DSC_CLK_FORCE_DISABLE, | |
4562236b HW |
575 | }; |
576 | ||
097e6d98 | 577 | struct dsc_preferred_settings { |
0749ddeb | 578 | enum dsc_clock_force_state dsc_force_enable; |
28b2f656 EB |
579 | uint32_t dsc_num_slices_v; |
580 | uint32_t dsc_num_slices_h; | |
5268bf13 | 581 | uint32_t dsc_bits_per_pixel; |
fcd1e484 | 582 | bool dsc_force_disable_passthrough; |
097e6d98 EB |
583 | }; |
584 | ||
25f7cde8 WL |
585 | enum mst_progress_status { |
586 | MST_STATUS_DEFAULT = 0, | |
587 | MST_PROBE = BIT(0), | |
588 | MST_REMOTE_EDID = BIT(1), | |
589 | MST_ALLOCATE_NEW_PAYLOAD = BIT(2), | |
590 | MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), | |
591 | }; | |
592 | ||
5b49da02 SJK |
593 | /** |
594 | * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info | |
595 | * | |
596 | * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this | |
597 | * struct is useful to keep track of the display-specific information about | |
598 | * FreeSync. | |
599 | */ | |
600 | struct amdgpu_hdmi_vsdb_info { | |
601 | /** | |
602 | * @amd_vsdb_version: Vendor Specific Data Block Version, should be | |
603 | * used to determine which Vendor Specific InfoFrame (VSIF) to send. | |
604 | */ | |
605 | unsigned int amd_vsdb_version; | |
606 | ||
607 | /** | |
608 | * @freesync_supported: FreeSync Supported. | |
609 | */ | |
610 | bool freesync_supported; | |
611 | ||
612 | /** | |
613 | * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. | |
614 | */ | |
615 | unsigned int min_refresh_rate_hz; | |
616 | ||
617 | /** | |
618 | * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz | |
619 | */ | |
620 | unsigned int max_refresh_rate_hz; | |
ec8e59cb BL |
621 | |
622 | /** | |
a10ea0ff | 623 | * @replay_mode: Replay supported |
ec8e59cb BL |
624 | */ |
625 | bool replay_mode; | |
5b49da02 SJK |
626 | }; |
627 | ||
c84dec2f HW |
628 | struct amdgpu_dm_connector { |
629 | ||
630 | struct drm_connector base; | |
631 | uint32_t connector_id; | |
f196198c | 632 | int bl_idx; |
c84dec2f HW |
633 | |
634 | /* we need to mind the EDID between detect | |
635 | and get modes due to analog/digital/tvencoder */ | |
636 | struct edid *edid; | |
637 | ||
638 | /* shared with amdgpu */ | |
639 | struct amdgpu_hpd hpd; | |
640 | ||
641 | /* number of modes generated from EDID at 'dc_sink' */ | |
642 | int num_modes; | |
643 | ||
644 | /* The 'old' sink - before an HPD. | |
645 | * The 'current' sink is in dc_link->sink. */ | |
646 | struct dc_sink *dc_sink; | |
647 | struct dc_link *dc_link; | |
c620e79b RS |
648 | |
649 | /** | |
650 | * @dc_em_sink: Reference to the emulated (virtual) sink. | |
651 | */ | |
c84dec2f HW |
652 | struct dc_sink *dc_em_sink; |
653 | ||
654 | /* DM only */ | |
655 | struct drm_dp_mst_topology_mgr mst_mgr; | |
656 | struct amdgpu_dm_dp_aux dm_dp_aux; | |
f0127cb1 WL |
657 | struct drm_dp_mst_port *mst_output_port; |
658 | struct amdgpu_dm_connector *mst_root; | |
ec0ca697 | 659 | struct drm_dp_aux *dsc_aux; |
bb4fa525 WL |
660 | struct mutex handle_mst_msg_ready; |
661 | ||
c84dec2f HW |
662 | /* TODO see if we can merge with ddc_bus or make a dm_connector */ |
663 | struct amdgpu_i2c_adapter *i2c; | |
664 | ||
665 | /* Monitor range limits */ | |
c620e79b RS |
666 | /** |
667 | * @min_vfreq: Minimal frequency supported by the display in Hz. This | |
668 | * value is set to zero when there is no FreeSync support. | |
669 | */ | |
670 | int min_vfreq; | |
671 | ||
672 | /** | |
673 | * @max_vfreq: Maximum frequency supported by the display in Hz. This | |
674 | * value is set to zero when there is no FreeSync support. | |
675 | */ | |
c84dec2f HW |
676 | int max_vfreq ; |
677 | int pixel_clock_mhz; | |
678 | ||
6ce8f316 NK |
679 | /* Audio instance - protected by audio_lock. */ |
680 | int audio_inst; | |
681 | ||
c84dec2f | 682 | struct mutex hpd_lock; |
2e0ac3d6 HW |
683 | |
684 | bool fake_enable; | |
d4252eee | 685 | bool force_yuv420_output; |
097e6d98 | 686 | struct dsc_preferred_settings dsc_settings; |
09db246c | 687 | union dp_downstream_port_present mst_downstream_port_present; |
a85ba005 NC |
688 | /* Cached display modes */ |
689 | struct drm_display_mode freesync_vid_base; | |
1a365683 RL |
690 | |
691 | int psr_skip_count; | |
25f7cde8 WL |
692 | |
693 | /* Record progress status of mst*/ | |
694 | uint8_t mst_status; | |
028c4ccf QZ |
695 | |
696 | /* Automated testing */ | |
697 | bool timing_changed; | |
698 | struct dc_crtc_timing *timing_requested; | |
5b49da02 SJK |
699 | |
700 | /* Adaptive Sync */ | |
701 | bool pack_sdp_v1_3; | |
702 | enum adaptive_sync_type as_type; | |
703 | struct amdgpu_hdmi_vsdb_info vsdb_info; | |
c84dec2f HW |
704 | }; |
705 | ||
25f7cde8 WL |
706 | static inline void amdgpu_dm_set_mst_status(uint8_t *status, |
707 | uint8_t flags, bool set) | |
708 | { | |
709 | if (set) | |
710 | *status |= flags; | |
711 | else | |
712 | *status &= ~flags; | |
713 | } | |
714 | ||
c84dec2f HW |
715 | #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) |
716 | ||
4562236b HW |
717 | extern const struct amdgpu_ip_block_version dm_ip_block; |
718 | ||
e7b07cee HW |
719 | struct dm_plane_state { |
720 | struct drm_plane_state base; | |
3be5262e | 721 | struct dc_plane_state *dc_state; |
e7b07cee HW |
722 | }; |
723 | ||
724 | struct dm_crtc_state { | |
725 | struct drm_crtc_state base; | |
0971c40e | 726 | struct dc_stream_state *stream; |
31aec354 | 727 | |
cf020d49 NK |
728 | bool cm_has_degamma; |
729 | bool cm_is_degamma_srgb; | |
730 | ||
214993e1 ML |
731 | bool mpo_requested; |
732 | ||
caff0e66 | 733 | int update_type; |
d6ef9b41 | 734 | int active_planes; |
d6ef9b41 | 735 | |
a0a31ec4 | 736 | int crc_skip_count; |
98e6436d | 737 | |
bb47de73 NK |
738 | bool freesync_vrr_info_changed; |
739 | ||
886876ec | 740 | bool dsc_force_changed; |
bb47de73 NK |
741 | bool vrr_supported; |
742 | struct mod_freesync_config freesync_config; | |
98e6436d | 743 | struct dc_info_packet vrr_infopacket; |
c1ee92f9 DF |
744 | |
745 | int abm_level; | |
e7b07cee HW |
746 | }; |
747 | ||
98e6436d | 748 | #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) |
e7b07cee HW |
749 | |
750 | struct dm_atomic_state { | |
eb3dc897 | 751 | struct drm_private_state base; |
e7b07cee | 752 | |
608ac7bb | 753 | struct dc_state *context; |
e7b07cee HW |
754 | }; |
755 | ||
756 | #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) | |
757 | ||
b3734397 HW |
758 | struct dm_connector_state { |
759 | struct drm_connector_state base; | |
760 | ||
761 | enum amdgpu_rmx_type scaling; | |
762 | uint8_t underscan_vborder; | |
763 | uint8_t underscan_hborder; | |
764 | bool underscan_enable; | |
8218d7f1 | 765 | bool freesync_capable; |
97f6c917 | 766 | bool update_hdcp; |
c1ee92f9 | 767 | uint8_t abm_level; |
3261e013 ML |
768 | int vcpi_slots; |
769 | uint64_t pbn; | |
b3734397 HW |
770 | }; |
771 | ||
772 | #define to_dm_connector_state(x)\ | |
773 | container_of((x), struct dm_connector_state, base) | |
e7b07cee | 774 | |
e7b07cee | 775 | void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); |
3ee6b26b AD |
776 | struct drm_connector_state * |
777 | amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); | |
778 | int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, | |
779 | struct drm_connector_state *state, | |
780 | struct drm_property *property, | |
781 | uint64_t val); | |
782 | ||
783 | int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, | |
784 | const struct drm_connector_state *state, | |
785 | struct drm_property *property, | |
786 | uint64_t *val); | |
e7b07cee HW |
787 | |
788 | int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); | |
789 | ||
3ee6b26b AD |
790 | void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, |
791 | struct amdgpu_dm_connector *aconnector, | |
792 | int connector_type, | |
793 | struct dc_link *link, | |
794 | int link_index); | |
e7b07cee | 795 | |
ba9ca088 | 796 | enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, |
3ee6b26b | 797 | struct drm_display_mode *mode); |
e7b07cee | 798 | |
3ee6b26b AD |
799 | void dm_restore_drm_connector_state(struct drm_device *dev, |
800 | struct drm_connector *connector); | |
e7b07cee | 801 | |
98e6436d AK |
802 | void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
803 | struct edid *edid); | |
e7b07cee | 804 | |
3d4e52d0 VL |
805 | void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); |
806 | ||
086247a4 LSL |
807 | #define MAX_COLOR_LUT_ENTRIES 4096 |
808 | /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ | |
809 | #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 | |
236d0e4f | 810 | |
e277adc5 | 811 | void amdgpu_dm_init_color_mod(void); |
03fc4cf4 | 812 | int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); |
cf020d49 NK |
813 | int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); |
814 | int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, | |
815 | struct dc_plane_state *dc_plane_state); | |
303afd2d | 816 | |
97e51c16 HW |
817 | void amdgpu_dm_update_connector_after_detect( |
818 | struct amdgpu_dm_connector *aconnector); | |
819 | ||
e7b07cee HW |
820 | extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; |
821 | ||
ead08b95 SW |
822 | int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, |
823 | struct aux_payload *payload, enum aux_return_code_type *operation_result); | |
824 | ||
825 | int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, | |
826 | struct set_config_cmd_payload *payload, enum set_config_status *operation_result); | |
1edf5ae1 | 827 | |
17ce8a69 RL |
828 | struct dc_stream_state * |
829 | create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, | |
830 | const struct drm_display_mode *drm_mode, | |
831 | const struct dm_connector_state *dm_state, | |
832 | const struct dc_stream_state *old_stream); | |
833 | ||
834 | int dm_atomic_get_state(struct drm_atomic_state *state, | |
835 | struct dm_atomic_state **dm_state); | |
836 | ||
837 | struct amdgpu_dm_connector * | |
838 | amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, | |
839 | struct drm_crtc *crtc); | |
f04d275d | 840 | |
841 | int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); | |
4562236b | 842 | #endif /* __AMDGPU_DM_H__ */ |