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drm/amd/display: use num_timing_generator instead of pipe_count
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
62#include "raven1/DCN/dcn_1_0_offset.h"
63#include "raven1/DCN/dcn_1_0_sh_mask.h"
64#include "vega10/soc15ip.h"
65
66#include "soc15_common.h"
67#endif
68
e7b07cee
HW		 69#include "modules/inc/mod_freesync.h"
70
71#include "i2caux_interface.h"
72
7578ecda
AD		 73/* basic init/fini API */
74static int amdgpu_dm_init(struct amdgpu_device *adev);
75static void amdgpu_dm_fini(struct amdgpu_device *adev);
76
77/* initializes drm_device display related structures, based on the information
78 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
79 * drm_encoder, drm_mode_config
80 *
81 * Returns 0 on success
82 */
83static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
84/* removes and deallocates the drm structures, created by the above function */
85static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
86
87static void
88amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
89
90static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
91 struct amdgpu_plane *aplane,
92 unsigned long possible_crtcs);
93static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
94 struct drm_plane *plane,
95 uint32_t link_index);
96static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
97 struct amdgpu_dm_connector *amdgpu_dm_connector,
98 uint32_t link_index,
99 struct amdgpu_encoder *amdgpu_encoder);
100static int amdgpu_dm_encoder_init(struct drm_device *dev,
101 struct amdgpu_encoder *aencoder,
102 uint32_t link_index);
103
104static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
105
106static int amdgpu_dm_atomic_commit(struct drm_device *dev,
107 struct drm_atomic_state *state,
108 bool nonblock);
109
110static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
111
112static int amdgpu_dm_atomic_check(struct drm_device *dev,
113 struct drm_atomic_state *state);
114
115
116
e7b07cee 117
e04a6123 118static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 119 DRM_PLANE_TYPE_PRIMARY,
120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125};
126
e04a6123 127static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 128 DRM_PLANE_TYPE_PRIMARY,
129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
132};
133
e04a6123 134static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 135 DRM_PLANE_TYPE_PRIMARY,
136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
138};
139
4562236b
HW		 140/*
141 * dm_vblank_get_counter
142 *
143 * @brief
144 * Get counter for number of vertical blanks
145 *
146 * @param
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
149 *
150 * @return
151 * Counter for vertical blanks
152 */
153static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
154{
155 if (crtc >= adev->mode_info.num_crtc)
156 return 0;
157 else {
158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
160 acrtc->base.state);
4562236b 161
da5c47f6
AG		 162
163 if (acrtc_state->stream == NULL) {
0971c40e
HW		 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
165 crtc);
4562236b
HW		 166 return 0;
167 }
168
da5c47f6 169 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 170 }
171}
172
173static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 174 u32 *vbl, u32 *position)
4562236b 175{
81c50963
ST		 176 uint32_t v_blank_start, v_blank_end, h_position, v_position;
177
4562236b
HW		 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
179 return -EINVAL;
180 else {
181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
183 acrtc->base.state);
4562236b 184
da5c47f6 185 if (acrtc_state->stream == NULL) {
0971c40e
HW		 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
187 crtc);
4562236b
HW		 188 return 0;
189 }
190
81c50963
ST		 191 /*
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
194 */
da5c47f6 195 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 196 &v_blank_start,
197 &v_blank_end,
198 &h_position,
199 &v_position);
200
e806208d
AG		 201 *position = v_position | (h_position << 16);
202 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 203 }
204
205 return 0;
206}
207
208static bool dm_is_idle(void *handle)
209{
210 /* XXX todo */
211 return true;
212}
213
214static int dm_wait_for_idle(void *handle)
215{
216 /* XXX todo */
217 return 0;
218}
219
220static bool dm_check_soft_reset(void *handle)
221{
222 return false;
223}
224
225static int dm_soft_reset(void *handle)
226{
227 /* XXX todo */
228 return 0;
229}
230
3ee6b26b
AD		 231static struct amdgpu_crtc *
232get_crtc_by_otg_inst(struct amdgpu_device *adev,
233 int otg_inst)
4562236b
HW		 234{
235 struct drm_device *dev = adev->ddev;
236 struct drm_crtc *crtc;
237 struct amdgpu_crtc *amdgpu_crtc;
238
239 /*
240 * following if is check inherited from both functions where this one is
241 * used now. Need to be checked why it could happen.
242 */
243 if (otg_inst == -1) {
244 WARN_ON(1);
245 return adev->mode_info.crtcs[0];
246 }
247
248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
249 amdgpu_crtc = to_amdgpu_crtc(crtc);
250
251 if (amdgpu_crtc->otg_inst == otg_inst)
252 return amdgpu_crtc;
253 }
254
255 return NULL;
256}
257
258static void dm_pflip_high_irq(void *interrupt_params)
259{
4562236b
HW		 260 struct amdgpu_crtc *amdgpu_crtc;
261 struct common_irq_params *irq_params = interrupt_params;
262 struct amdgpu_device *adev = irq_params->adev;
263 unsigned long flags;
264
265 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
266
267 /* IRQ could occur when in initial stage */
268 /*TODO work and BO cleanup */
269 if (amdgpu_crtc == NULL) {
270 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
271 return;
272 }
273
274 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 275
276 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
277 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
278 amdgpu_crtc->pflip_status,
279 AMDGPU_FLIP_SUBMITTED,
280 amdgpu_crtc->crtc_id,
281 amdgpu_crtc);
282 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
283 return;
284 }
285
4562236b
HW		 286
287 /* wakeup usersapce */
1159898a 288 if (amdgpu_crtc->event) {
753c66c9
MK		 289 /* Update to correct count/ts if racing with vblank irq */
290 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
291
54f5499a 292 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 293
54f5499a
AG		 294 /* page flip completed. clean up */
295 amdgpu_crtc->event = NULL;
1159898a 296
54f5499a
AG		 297 } else
298 WARN_ON(1);
4562236b 299
54f5499a 300 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 301 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
302
54f5499a
AG		 303 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
304 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 305
306 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 307}
308
309static void dm_crtc_high_irq(void *interrupt_params)
310{
311 struct common_irq_params *irq_params = interrupt_params;
312 struct amdgpu_device *adev = irq_params->adev;
313 uint8_t crtc_index = 0;
314 struct amdgpu_crtc *acrtc;
315
b57de80a 316 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 317
318 if (acrtc)
319 crtc_index = acrtc->crtc_id;
320
321 drm_handle_vblank(adev->ddev, crtc_index);
322}
323
324static int dm_set_clockgating_state(void *handle,
325 enum amd_clockgating_state state)
326{
327 return 0;
328}
329
330static int dm_set_powergating_state(void *handle,
331 enum amd_powergating_state state)
332{
333 return 0;
334}
335
336/* Prototypes of private functions */
337static int dm_early_init(void* handle);
338
339static void hotplug_notify_work_func(struct work_struct *work)
340{
341 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
342 struct drm_device *dev = dm->ddev;
343
344 drm_kms_helper_hotplug_event(dev);
345}
346
6ef39a62 347#if defined(CONFIG_DRM_AMD_DC_FBC)
a32e24b4
RL		 348#include "dal_asic_id.h"
349/* Allocate memory for FBC compressed data */
350/* TODO: Dynamic allocation */
351#define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
352
7578ecda 353static void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
a32e24b4
RL		 354{
355 int r;
356 struct dm_comressor_info *compressor = &adev->dm.compressor;
357
358 if (!compressor->bo_ptr) {
359 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
360 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
361 &compressor->gpu_addr, &compressor->cpu_addr);
362
363 if (r)
364 DRM_ERROR("DM: Failed to initialize fbc\n");
365 }
366
367}
368#endif
369
370
4562236b
HW		 371/* Init display KMS
372 *
373 * Returns 0 on success
374 */
7578ecda 375static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 376{
377 struct dc_init_data init_data;
378 adev->dm.ddev = adev->ddev;
379 adev->dm.adev = adev;
380
4562236b
HW		 381 /* Zero all the fields */
382 memset(&init_data, 0, sizeof(init_data));
383
384 /* initialize DAL's lock (for SYNC context use) */
385 spin_lock_init(&adev->dm.dal_lock);
386
387 /* initialize DAL's mutex */
388 mutex_init(&adev->dm.dal_mutex);
389
390 if(amdgpu_dm_irq_init(adev)) {
391 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
392 goto error;
393 }
394
395 init_data.asic_id.chip_family = adev->family;
396
397 init_data.asic_id.pci_revision_id = adev->rev_id;
398 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
399
400 init_data.asic_id.vram_width = adev->mc.vram_width;
401 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
402 init_data.asic_id.atombios_base_address =
403 adev->mode_info.atom_context->bios;
404
405 init_data.driver = adev;
406
407 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
408
409 if (!adev->dm.cgs_device) {
410 DRM_ERROR("amdgpu: failed to create cgs device.\n");
411 goto error;
412 }
413
414 init_data.cgs_device = adev->dm.cgs_device;
415
416 adev->dm.dal = NULL;
417
418 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
419
f1ad2f5e
HW		 420 if (amdgpu_dc_log)
421 init_data.log_mask = DC_DEFAULT_LOG_MASK;
422 else
423 init_data.log_mask = DC_MIN_LOG_MASK;
01a526f3 424
6ef39a62 425#if defined(CONFIG_DRM_AMD_DC_FBC)
a32e24b4
RL		 426 if (adev->family == FAMILY_CZ)
427 amdgpu_dm_initialize_fbc(adev);
428 init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
429#endif
4562236b
HW		 430 /* Display Core create. */
431 adev->dm.dc = dc_create(&init_data);
432
423788c7 433 if (adev->dm.dc) {
f1ad2f5e 434 DRM_INFO("Display Core initialized!\n");
423788c7 435 } else {
4562236b 436 DRM_INFO("Display Core failed to initialize!\n");
423788c7
ES		 437 goto error;
438 }
4562236b
HW		 439
440 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
441
442 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
443 if (!adev->dm.freesync_module) {
444 DRM_ERROR(
445 "amdgpu: failed to initialize freesync_module.\n");
446 } else
f1ad2f5e 447 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 448 adev->dm.freesync_module);
449
450 if (amdgpu_dm_initialize_drm_device(adev)) {
451 DRM_ERROR(
452 "amdgpu: failed to initialize sw for display support.\n");
453 goto error;
454 }
455
456 /* Update the actual used number of crtc */
457 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
458
459 /* TODO: Add_display_info? */
460
461 /* TODO use dynamic cursor width */
ce75805e
AG		 462 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
463 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 464
465 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
466 DRM_ERROR(
467 "amdgpu: failed to initialize sw for display support.\n");
468 goto error;
469 }
470
f1ad2f5e 471 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 472
473 return 0;
474error:
475 amdgpu_dm_fini(adev);
476
477 return -1;
478}
479
7578ecda 480static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 481{
482 amdgpu_dm_destroy_drm_device(&adev->dm);
483 /*
484 * TODO: pageflip, vlank interrupt
485 *
486 * amdgpu_dm_irq_fini(adev);
487 */
488
489 if (adev->dm.cgs_device) {
490 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
491 adev->dm.cgs_device = NULL;
492 }
493 if (adev->dm.freesync_module) {
494 mod_freesync_destroy(adev->dm.freesync_module);
495 adev->dm.freesync_module = NULL;
496 }
497 /* DC Destroy TODO: Replace destroy DAL */
21de3396 498 if (adev->dm.dc)
4562236b 499 dc_destroy(&adev->dm.dc);
4562236b
HW		 500 return;
501}
502
4562236b
HW		 503static int dm_sw_init(void *handle)
504{
505 return 0;
506}
507
508static int dm_sw_fini(void *handle)
509{
510 return 0;
511}
512
7abcf6b5 513static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 514{
c84dec2f 515 struct amdgpu_dm_connector *aconnector;
4562236b 516 struct drm_connector *connector;
7abcf6b5 517 int ret = 0;
4562236b
HW		 518
519 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
520
521 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 522 aconnector = to_amdgpu_dm_connector(connector);
7abcf6b5 523 if (aconnector->dc_link->type == dc_connection_mst_branch) {
f1ad2f5e 524 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 525 aconnector, aconnector->base.base.id);
526
527 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
528 if (ret < 0) {
529 DRM_ERROR("DM_MST: Failed to start MST\n");
530 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
531 return ret;
4562236b 532 }
7abcf6b5 533 }
4562236b
HW		 534 }
535
536 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 537 return ret;
538}
539
540static int dm_late_init(void *handle)
541{
542 struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
7abcf6b5 543
33be2785 544 return detect_mst_link_for_all_connectors(dev);
4562236b
HW		 545}
546
547static void s3_handle_mst(struct drm_device *dev, bool suspend)
548{
c84dec2f 549 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 550 struct drm_connector *connector;
551
552 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
553
554 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 555 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 556 if (aconnector->dc_link->type == dc_connection_mst_branch &&
557 !aconnector->mst_port) {
558
559 if (suspend)
560 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
561 else
562 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
563 }
564 }
565
566 drm_modeset_unlock(&dev->mode_config.connection_mutex);
567}
568
569static int dm_hw_init(void *handle)
570{
571 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
572 /* Create DAL display manager */
573 amdgpu_dm_init(adev);
4562236b
HW		 574 amdgpu_dm_hpd_init(adev);
575
4562236b
HW		 576 return 0;
577}
578
579static int dm_hw_fini(void *handle)
580{
581 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
582
583 amdgpu_dm_hpd_fini(adev);
584
585 amdgpu_dm_irq_fini(adev);
21de3396 586 amdgpu_dm_fini(adev);
4562236b
HW		 587 return 0;
588}
589
590static int dm_suspend(void *handle)
591{
592 struct amdgpu_device *adev = handle;
593 struct amdgpu_display_manager *dm = &adev->dm;
594 int ret = 0;
4562236b
HW		 595
596 s3_handle_mst(adev->ddev, true);
597
4562236b
HW		 598 amdgpu_dm_irq_suspend(adev);
599
0a214e2f 600 WARN_ON(adev->dm.cached_state);
a3621485
AG		 601 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
602
32f5062d 603 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 604
605 return ret;
606}
607
1daf8c63
AD		 608static struct amdgpu_dm_connector *
609amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
610 struct drm_crtc *crtc)
4562236b
HW		 611{
612 uint32_t i;
c2cea706 613 struct drm_connector_state *new_con_state;
4562236b
HW		 614 struct drm_connector *connector;
615 struct drm_crtc *crtc_from_state;
616
c2cea706
LSL		 617 for_each_new_connector_in_state(state, connector, new_con_state, i) {
618 crtc_from_state = new_con_state->crtc;
4562236b
HW		 619
620 if (crtc_from_state == crtc)
c84dec2f 621 return to_amdgpu_dm_connector(connector);
4562236b
HW		 622 }
623
624 return NULL;
625}
626
4562236b
HW		 627static int dm_resume(void *handle)
628{
629 struct amdgpu_device *adev = handle;
630 struct amdgpu_display_manager *dm = &adev->dm;
631
632 /* power on hardware */
1fb0c9cc 633 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
4562236b
HW		 634
635 return 0;
636}
637
1ecfc3da 638int amdgpu_dm_display_resume(struct amdgpu_device *adev)
4562236b
HW		 639{
640 struct drm_device *ddev = adev->ddev;
641 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 642 struct amdgpu_dm_connector *aconnector;
4562236b 643 struct drm_connector *connector;
4562236b 644 struct drm_crtc *crtc;
c2cea706 645 struct drm_crtc_state *new_crtc_state;
a3621485
AG		 646 int ret = 0;
647 int i;
4562236b
HW		 648
649 /* program HPD filter */
650 dc_resume(dm->dc);
651
652 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
653 s3_handle_mst(ddev, false);
654
655 /*
656 * early enable HPD Rx IRQ, should be done before set mode as short
657 * pulse interrupts are used for MST
658 */
659 amdgpu_dm_irq_resume_early(adev);
660
4562236b
HW		 661 /* Do detection*/
662 list_for_each_entry(connector,
663 &ddev->mode_config.connector_list, head) {
c84dec2f 664 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 665
666 /*
667 * this is the case when traversing through already created
668 * MST connectors, should be skipped
669 */
670 if (aconnector->mst_port)
671 continue;
672
03ea364c 673 mutex_lock(&aconnector->hpd_lock);
8f38b66c 674 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
4562236b
HW		 675 aconnector->dc_sink = NULL;
676 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 677 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 678 }
679
a3621485 680 /* Force mode set in atomic comit */
c2cea706
LSL		 681 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
682 new_crtc_state->active_changed = true;
4f346e65 683
a3621485 684 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 685
0a214e2f
AG		 686 drm_atomic_state_put(adev->dm.cached_state);
687 adev->dm.cached_state = NULL;
688
9faa4237 689 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 690
691 return ret;
692}
693
694static const struct amd_ip_funcs amdgpu_dm_funcs = {
695 .name = "dm",
696 .early_init = dm_early_init,
7abcf6b5 697 .late_init = dm_late_init,
4562236b
HW		 698 .sw_init = dm_sw_init,
699 .sw_fini = dm_sw_fini,
700 .hw_init = dm_hw_init,
701 .hw_fini = dm_hw_fini,
702 .suspend = dm_suspend,
703 .resume = dm_resume,
704 .is_idle = dm_is_idle,
705 .wait_for_idle = dm_wait_for_idle,
706 .check_soft_reset = dm_check_soft_reset,
707 .soft_reset = dm_soft_reset,
708 .set_clockgating_state = dm_set_clockgating_state,
709 .set_powergating_state = dm_set_powergating_state,
710};
711
712const struct amdgpu_ip_block_version dm_ip_block =
713{
714 .type = AMD_IP_BLOCK_TYPE_DCE,
715 .major = 1,
716 .minor = 0,
717 .rev = 0,
718 .funcs = &amdgpu_dm_funcs,
719};
720
ca3268c4 721
7578ecda 722static struct drm_atomic_state *
ca3268c4
HW		 723dm_atomic_state_alloc(struct drm_device *dev)
724{
725 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
726
1dc90497 727 if (!state)
ca3268c4 728 return NULL;
1dc90497
AG		 729
730 if (drm_atomic_state_init(dev, &state->base) < 0)
731 goto fail;
732
ca3268c4 733 return &state->base;
1dc90497
AG		 734
735fail:
736 kfree(state);
737 return NULL;
ca3268c4
HW		 738}
739
0a323b84
AG		 740static void
741dm_atomic_state_clear(struct drm_atomic_state *state)
742{
743 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
744
745 if (dm_state->context) {
608ac7bb 746 dc_release_state(dm_state->context);
0a323b84
AG		 747 dm_state->context = NULL;
748 }
749
750 drm_atomic_state_default_clear(state);
751}
752
753static void
754dm_atomic_state_alloc_free(struct drm_atomic_state *state)
755{
756 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
757 drm_atomic_state_default_release(state);
758 kfree(dm_state);
759}
760
b3663f70 761static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
a49dcb88
HW		 762 .fb_create = amdgpu_user_framebuffer_create,
763 .output_poll_changed = amdgpu_output_poll_changed,
4562236b 764 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 765 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 766 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 767 .atomic_state_clear = dm_atomic_state_clear,
768 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 769};
770
771static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
772 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 773};
774
7578ecda 775static void
3ee6b26b 776amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 777{
778 struct drm_connector *connector = &aconnector->base;
779 struct drm_device *dev = connector->dev;
b73a22d3 780 struct dc_sink *sink;
4562236b
HW		 781
782 /* MST handled by drm_mst framework */
783 if (aconnector->mst_mgr.mst_state == true)
784 return;
785
786
787 sink = aconnector->dc_link->local_sink;
788
789 /* Edid mgmt connector gets first update only in mode_valid hook and then
790 * the connector sink is set to either fake or physical sink depends on link status.
791 * don't do it here if u are during boot
792 */
793 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
794 && aconnector->dc_em_sink) {
795
ab2541b6 796 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 797 * because on resume connecotr->sink is set ti NULL
798 */
799 mutex_lock(&dev->mode_config.mutex);
800
801 if (sink) {
922aa1e1 802 if (aconnector->dc_sink) {
4562236b
HW		 803 amdgpu_dm_remove_sink_from_freesync_module(
804 connector);
922aa1e1
AG		 805 /* retain and release bellow are used for
806 * bump up refcount for sink because the link don't point
807 * to it anymore after disconnect so on next crtc to connector
808 * reshuffle by UMD we will get into unwanted dc_sink release
809 */
810 if (aconnector->dc_sink != aconnector->dc_em_sink)
811 dc_sink_release(aconnector->dc_sink);
812 }
4562236b
HW		 813 aconnector->dc_sink = sink;
814 amdgpu_dm_add_sink_to_freesync_module(
815 connector, aconnector->edid);
816 } else {
817 amdgpu_dm_remove_sink_from_freesync_module(connector);
818 if (!aconnector->dc_sink)
819 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 820 else if (aconnector->dc_sink != aconnector->dc_em_sink)
821 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 822 }
823
824 mutex_unlock(&dev->mode_config.mutex);
825 return;
826 }
827
828 /*
829 * TODO: temporary guard to look for proper fix
830 * if this sink is MST sink, we should not do anything
831 */
832 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
833 return;
834
835 if (aconnector->dc_sink == sink) {
836 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
837 * Do nothing!! */
f1ad2f5e 838 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 839 aconnector->connector_id);
840 return;
841 }
842
f1ad2f5e 843 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 844 aconnector->connector_id, aconnector->dc_sink, sink);
845
846 mutex_lock(&dev->mode_config.mutex);
847
848 /* 1. Update status of the drm connector
849 * 2. Send an event and let userspace tell us what to do */
850 if (sink) {
851 /* TODO: check if we still need the S3 mode update workaround.
852 * If yes, put it here. */
853 if (aconnector->dc_sink)
854 amdgpu_dm_remove_sink_from_freesync_module(
855 connector);
856
857 aconnector->dc_sink = sink;
900b3cb1 858 if (sink->dc_edid.length == 0) {
4562236b 859 aconnector->edid = NULL;
900b3cb1 860 } else {
4562236b
HW		 861 aconnector->edid =
862 (struct edid *) sink->dc_edid.raw_edid;
863
864
865 drm_mode_connector_update_edid_property(connector,
866 aconnector->edid);
867 }
868 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
869
870 } else {
871 amdgpu_dm_remove_sink_from_freesync_module(connector);
872 drm_mode_connector_update_edid_property(connector, NULL);
873 aconnector->num_modes = 0;
874 aconnector->dc_sink = NULL;
875 }
876
877 mutex_unlock(&dev->mode_config.mutex);
878}
879
880static void handle_hpd_irq(void *param)
881{
c84dec2f 882 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 883 struct drm_connector *connector = &aconnector->base;
884 struct drm_device *dev = connector->dev;
885
886 /* In case of failure or MST no need to update connector status or notify the OS
887 * since (for MST case) MST does this in it's own context.
888 */
889 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 890
891 if (aconnector->fake_enable)
892 aconnector->fake_enable = false;
893
8f38b66c 894 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 895 amdgpu_dm_update_connector_after_detect(aconnector);
896
897
898 drm_modeset_lock_all(dev);
899 dm_restore_drm_connector_state(dev, connector);
900 drm_modeset_unlock_all(dev);
901
902 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
903 drm_kms_helper_hotplug_event(dev);
904 }
905 mutex_unlock(&aconnector->hpd_lock);
906
907}
908
c84dec2f 909static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 910{
911 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
912 uint8_t dret;
913 bool new_irq_handled = false;
914 int dpcd_addr;
915 int dpcd_bytes_to_read;
916
917 const int max_process_count = 30;
918 int process_count = 0;
919
920 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
921
922 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
923 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
924 /* DPCD 0x200 - 0x201 for downstream IRQ */
925 dpcd_addr = DP_SINK_COUNT;
926 } else {
927 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
928 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
929 dpcd_addr = DP_SINK_COUNT_ESI;
930 }
931
932 dret = drm_dp_dpcd_read(
933 &aconnector->dm_dp_aux.aux,
934 dpcd_addr,
935 esi,
936 dpcd_bytes_to_read);
937
938 while (dret == dpcd_bytes_to_read &&
939 process_count < max_process_count) {
940 uint8_t retry;
941 dret = 0;
942
943 process_count++;
944
f1ad2f5e 945 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 946 /* handle HPD short pulse irq */
947 if (aconnector->mst_mgr.mst_state)
948 drm_dp_mst_hpd_irq(
949 &aconnector->mst_mgr,
950 esi,
951 &new_irq_handled);
4562236b
HW		 952
953 if (new_irq_handled) {
954 /* ACK at DPCD to notify down stream */
955 const int ack_dpcd_bytes_to_write =
956 dpcd_bytes_to_read - 1;
957
958 for (retry = 0; retry < 3; retry++) {
959 uint8_t wret;
960
961 wret = drm_dp_dpcd_write(
962 &aconnector->dm_dp_aux.aux,
963 dpcd_addr + 1,
964 &esi[1],
965 ack_dpcd_bytes_to_write);
966 if (wret == ack_dpcd_bytes_to_write)
967 break;
968 }
969
970 /* check if there is new irq to be handle */
971 dret = drm_dp_dpcd_read(
972 &aconnector->dm_dp_aux.aux,
973 dpcd_addr,
974 esi,
975 dpcd_bytes_to_read);
976
977 new_irq_handled = false;
d4a6e8a9 978 } else {
4562236b 979 break;
d4a6e8a9 980 }
4562236b
HW		 981 }
982
983 if (process_count == max_process_count)
f1ad2f5e 984 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 985}
986
987static void handle_hpd_rx_irq(void *param)
988{
c84dec2f 989 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 990 struct drm_connector *connector = &aconnector->base;
991 struct drm_device *dev = connector->dev;
53cbf65c 992 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 993 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
994
995 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
996 * conflict, after implement i2c helper, this mutex should be
997 * retired.
998 */
53cbf65c 999 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1000 mutex_lock(&aconnector->hpd_lock);
1001
53cbf65c 1002 if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
4562236b
HW		 1003 !is_mst_root_connector) {
1004 /* Downstream Port status changed. */
53cbf65c 1005 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
4562236b
HW		 1006 amdgpu_dm_update_connector_after_detect(aconnector);
1007
1008
1009 drm_modeset_lock_all(dev);
1010 dm_restore_drm_connector_state(dev, connector);
1011 drm_modeset_unlock_all(dev);
1012
1013 drm_kms_helper_hotplug_event(dev);
1014 }
1015 }
1016 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1017 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1018 dm_handle_hpd_rx_irq(aconnector);
1019
53cbf65c 1020 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1021 mutex_unlock(&aconnector->hpd_lock);
1022}
1023
1024static void register_hpd_handlers(struct amdgpu_device *adev)
1025{
1026 struct drm_device *dev = adev->ddev;
1027 struct drm_connector *connector;
c84dec2f 1028 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1029 const struct dc_link *dc_link;
1030 struct dc_interrupt_params int_params = {0};
1031
1032 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1033 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1034
1035 list_for_each_entry(connector,
1036 &dev->mode_config.connector_list, head) {
1037
c84dec2f 1038 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1039 dc_link = aconnector->dc_link;
1040
1041 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1042 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1043 int_params.irq_source = dc_link->irq_source_hpd;
1044
1045 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1046 handle_hpd_irq,
1047 (void *) aconnector);
1048 }
1049
1050 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1051
1052 /* Also register for DP short pulse (hpd_rx). */
1053 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1054 int_params.irq_source = dc_link->irq_source_hpd_rx;
1055
1056 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1057 handle_hpd_rx_irq,
1058 (void *) aconnector);
1059 }
1060 }
1061}
1062
1063/* Register IRQ sources and initialize IRQ callbacks */
1064static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1065{
1066 struct dc *dc = adev->dm.dc;
1067 struct common_irq_params *c_irq_params;
1068 struct dc_interrupt_params int_params = {0};
1069 int r;
1070 int i;
2c8ad2d5
AD		 1071 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1072
ff5ef992
AD		 1073 if (adev->asic_type == CHIP_VEGA10 ||
1074 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1075 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1076
1077 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1078 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1079
1080 /* Actions of amdgpu_irq_add_id():
1081 * 1. Register a set() function with base driver.
1082 * Base driver will call set() function to enable/disable an
1083 * interrupt in DC hardware.
1084 * 2. Register amdgpu_dm_irq_handler().
1085 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1086 * coming from DC hardware.
1087 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1088 * for acknowledging and handling. */
1089
b57de80a 1090 /* Use VBLANK interrupt */
e9029155 1091 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1092 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1093 if (r) {
1094 DRM_ERROR("Failed to add crtc irq id!\n");
1095 return r;
1096 }
1097
1098 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1099 int_params.irq_source =
3d761e79 1100 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1101
b57de80a 1102 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1103
1104 c_irq_params->adev = adev;
1105 c_irq_params->irq_src = int_params.irq_source;
1106
1107 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1108 dm_crtc_high_irq, c_irq_params);
1109 }
1110
3d761e79 1111 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1112 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1113 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1114 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1115 if (r) {
1116 DRM_ERROR("Failed to add page flip irq id!\n");
1117 return r;
1118 }
1119
1120 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1121 int_params.irq_source =
1122 dc_interrupt_to_irq_source(dc, i, 0);
1123
1124 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1125
1126 c_irq_params->adev = adev;
1127 c_irq_params->irq_src = int_params.irq_source;
1128
1129 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1130 dm_pflip_high_irq, c_irq_params);
1131
1132 }
1133
1134 /* HPD */
2c8ad2d5
AD		 1135 r = amdgpu_irq_add_id(adev, client_id,
1136 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1137 if (r) {
1138 DRM_ERROR("Failed to add hpd irq id!\n");
1139 return r;
1140 }
1141
1142 register_hpd_handlers(adev);
1143
1144 return 0;
1145}
1146
ff5ef992
AD		 1147#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1148/* Register IRQ sources and initialize IRQ callbacks */
1149static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1150{
1151 struct dc *dc = adev->dm.dc;
1152 struct common_irq_params *c_irq_params;
1153 struct dc_interrupt_params int_params = {0};
1154 int r;
1155 int i;
1156
1157 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1158 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1159
1160 /* Actions of amdgpu_irq_add_id():
1161 * 1. Register a set() function with base driver.
1162 * Base driver will call set() function to enable/disable an
1163 * interrupt in DC hardware.
1164 * 2. Register amdgpu_dm_irq_handler().
1165 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1166 * coming from DC hardware.
1167 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1168 * for acknowledging and handling.
1169 * */
1170
1171 /* Use VSTARTUP interrupt */
1172 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1173 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1174 i++) {
1175 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1176
1177 if (r) {
1178 DRM_ERROR("Failed to add crtc irq id!\n");
1179 return r;
1180 }
1181
1182 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1183 int_params.irq_source =
1184 dc_interrupt_to_irq_source(dc, i, 0);
1185
1186 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1187
1188 c_irq_params->adev = adev;
1189 c_irq_params->irq_src = int_params.irq_source;
1190
1191 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1192 dm_crtc_high_irq, c_irq_params);
1193 }
1194
1195 /* Use GRPH_PFLIP interrupt */
1196 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1197 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1198 i++) {
1199 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1200 if (r) {
1201 DRM_ERROR("Failed to add page flip irq id!\n");
1202 return r;
1203 }
1204
1205 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1206 int_params.irq_source =
1207 dc_interrupt_to_irq_source(dc, i, 0);
1208
1209 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1210
1211 c_irq_params->adev = adev;
1212 c_irq_params->irq_src = int_params.irq_source;
1213
1214 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1215 dm_pflip_high_irq, c_irq_params);
1216
1217 }
1218
1219 /* HPD */
1220 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1221 &adev->hpd_irq);
1222 if (r) {
1223 DRM_ERROR("Failed to add hpd irq id!\n");
1224 return r;
1225 }
1226
1227 register_hpd_handlers(adev);
1228
1229 return 0;
1230}
1231#endif
1232
4562236b
HW		 1233static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1234{
1235 int r;
1236
1237 adev->mode_info.mode_config_initialized = true;
1238
4562236b 1239 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1240 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1241
1242 adev->ddev->mode_config.max_width = 16384;
1243 adev->ddev->mode_config.max_height = 16384;
1244
1245 adev->ddev->mode_config.preferred_depth = 24;
1246 adev->ddev->mode_config.prefer_shadow = 1;
1247 /* indicate support of immediate flip */
1248 adev->ddev->mode_config.async_page_flip = true;
1249
1250 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1251
1252 r = amdgpu_modeset_create_props(adev);
1253 if (r)
1254 return r;
1255
1256 return 0;
1257}
1258
1259#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1260 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1261
1262static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1263{
1264 struct amdgpu_display_manager *dm = bl_get_data(bd);
1265
1266 if (dc_link_set_backlight_level(dm->backlight_link,
1267 bd->props.brightness, 0, 0))
1268 return 0;
1269 else
1270 return 1;
1271}
1272
1273static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1274{
1275 return bd->props.brightness;
1276}
1277
1278static const struct backlight_ops amdgpu_dm_backlight_ops = {
1279 .get_brightness = amdgpu_dm_backlight_get_brightness,
1280 .update_status = amdgpu_dm_backlight_update_status,
1281};
1282
7578ecda
AD		 1283static void
1284amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1285{
1286 char bl_name[16];
1287 struct backlight_properties props = { 0 };
1288
1289 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1290 props.type = BACKLIGHT_RAW;
1291
1292 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1293 dm->adev->ddev->primary->index);
1294
1295 dm->backlight_dev = backlight_device_register(bl_name,
1296 dm->adev->ddev->dev,
1297 dm,
1298 &amdgpu_dm_backlight_ops,
1299 &props);
1300
74baea42 1301 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1302 DRM_ERROR("DM: Backlight registration failed!\n");
1303 else
f1ad2f5e 1304 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1305}
1306
1307#endif
1308
1309/* In this architecture, the association
1310 * connector -> encoder -> crtc
1311 * id not really requried. The crtc and connector will hold the
1312 * display_index as an abstraction to use with DAL component
1313 *
1314 * Returns 0 on success
1315 */
7578ecda 1316static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1317{
1318 struct amdgpu_display_manager *dm = &adev->dm;
1319 uint32_t i;
c84dec2f 1320 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1321 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1322 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1323 uint32_t link_cnt;
92f3ac40 1324 unsigned long possible_crtcs;
4562236b
HW		 1325
1326 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1327 if (amdgpu_dm_mode_config_init(dm->adev)) {
1328 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1329 return -1;
4562236b
HW		 1330 }
1331
3be5262e 1332 for (i = 0; i < dm->dc->caps.max_planes; i++) {
efa6a8b7
HW		 1333 struct amdgpu_plane *plane;
1334
1335 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1336 mode_info->planes[i] = plane;
1337
1338 if (!plane) {
3be5262e 1339 DRM_ERROR("KMS: Failed to allocate plane\n");
cd8a2ae8 1340 goto fail;
d4e13b0d 1341 }
efa6a8b7 1342 plane->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1343
1344 /*
1345 * HACK: IGT tests expect that each plane can only have one
1346 * one possible CRTC. For now, set one CRTC for each
1347 * plane that is not an underlay, but still allow multiple
1348 * CRTCs for underlay planes.
1349 */
1350 possible_crtcs = 1 << i;
1351 if (i >= dm->dc->caps.max_streams)
1352 possible_crtcs = 0xff;
1353
1354 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d 1355 DRM_ERROR("KMS: Failed to initialize plane\n");
cd8a2ae8 1356 goto fail;
d4e13b0d
AD		 1357 }
1358 }
4562236b 1359
d4e13b0d
AD		 1360 for (i = 0; i < dm->dc->caps.max_streams; i++)
1361 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1362 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1363 goto fail;
4562236b 1364 }
4562236b 1365
ab2541b6 1366 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1367
1368 /* loops over all connectors on the board */
1369 for (i = 0; i < link_cnt; i++) {
1370
1371 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1372 DRM_ERROR(
1373 "KMS: Cannot support more than %d display indexes\n",
1374 AMDGPU_DM_MAX_DISPLAY_INDEX);
1375 continue;
1376 }
1377
1378 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1379 if (!aconnector)
cd8a2ae8 1380 goto fail;
4562236b
HW		 1381
1382 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1383 if (!aencoder)
cd8a2ae8 1384 goto fail;
4562236b
HW		 1385
1386 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1387 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1388 goto fail;
4562236b
HW		 1389 }
1390
1391 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1392 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1393 goto fail;
4562236b
HW		 1394 }
1395
8f38b66c
HW		 1396 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1397 DETECT_REASON_BOOT))
4562236b
HW		 1398 amdgpu_dm_update_connector_after_detect(aconnector);
1399 }
1400
1401 /* Software is initialized. Now we can register interrupt handlers. */
1402 switch (adev->asic_type) {
1403 case CHIP_BONAIRE:
1404 case CHIP_HAWAII:
cd4b356f
AD		 1405 case CHIP_KAVERI:
1406 case CHIP_KABINI:
1407 case CHIP_MULLINS:
4562236b
HW		 1408 case CHIP_TONGA:
1409 case CHIP_FIJI:
1410 case CHIP_CARRIZO:
1411 case CHIP_STONEY:
1412 case CHIP_POLARIS11:
1413 case CHIP_POLARIS10:
b264d345 1414 case CHIP_POLARIS12:
2c8ad2d5 1415 case CHIP_VEGA10:
4562236b
HW		 1416 if (dce110_register_irq_handlers(dm->adev)) {
1417 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1418 goto fail;
4562236b
HW		 1419 }
1420 break;
ff5ef992
AD		 1421#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1422 case CHIP_RAVEN:
1423 if (dcn10_register_irq_handlers(dm->adev)) {
1424 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1425 goto fail;
ff5ef992 1426 }
79c24086
BL		 1427 /*
1428 * Temporary disable until pplib/smu interaction is implemented
1429 */
1430 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1431 break;
1432#endif
4562236b
HW		 1433 default:
1434 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 1435 goto fail;
4562236b
HW		 1436 }
1437
4562236b 1438 return 0;
cd8a2ae8 1439fail:
4562236b 1440 kfree(aencoder);
4562236b 1441 kfree(aconnector);
3be5262e 1442 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1443 kfree(mode_info->planes[i]);
4562236b
HW		 1444 return -1;
1445}
1446
7578ecda 1447static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1448{
1449 drm_mode_config_cleanup(dm->ddev);
1450 return;
1451}
1452
1453/******************************************************************************
1454 * amdgpu_display_funcs functions
1455 *****************************************************************************/
1456
1457/**
1458 * dm_bandwidth_update - program display watermarks
1459 *
1460 * @adev: amdgpu_device pointer
1461 *
1462 * Calculate and program the display watermarks and line buffer allocation.
1463 */
1464static void dm_bandwidth_update(struct amdgpu_device *adev)
1465{
49c07a99 1466 /* TODO: implement later */
4562236b
HW		 1467}
1468
1469static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1470 u8 level)
1471{
1472 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1473}
1474
1475static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1476{
1477 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1478 return 0;
1479}
1480
4562236b
HW		 1481static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1482 struct drm_file *filp)
1483{
1484 struct mod_freesync_params freesync_params;
ab2541b6 1485 uint8_t num_streams;
4562236b 1486 uint8_t i;
4562236b
HW		 1487
1488 struct amdgpu_device *adev = dev->dev_private;
1489 int r = 0;
1490
1491 /* Get freesync enable flag from DRM */
1492
ab2541b6 1493 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1494
ab2541b6 1495 for (i = 0; i < num_streams; i++) {
0971c40e 1496 struct dc_stream_state *stream;
ab2541b6 1497 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1498
1499 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1500 &stream, 1, &freesync_params);
4562236b
HW		 1501 }
1502
1503 return r;
1504}
1505
39cc5be2 1506static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1507 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1508 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1509 .vblank_wait = NULL,
1510 .backlight_set_level =
1511 dm_set_backlight_level,/* called unconditionally */
1512 .backlight_get_level =
1513 dm_get_backlight_level,/* called unconditionally */
1514 .hpd_sense = NULL,/* called unconditionally */
1515 .hpd_set_polarity = NULL, /* called unconditionally */
1516 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1517 .page_flip_get_scanoutpos =
1518 dm_crtc_get_scanoutpos,/* called unconditionally */
1519 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1520 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1521 .notify_freesync = amdgpu_notify_freesync,
1522
1523};
1524
1525#if defined(CONFIG_DEBUG_KERNEL_DC)
1526
3ee6b26b
AD		 1527static ssize_t s3_debug_store(struct device *device,
1528 struct device_attribute *attr,
1529 const char *buf,
1530 size_t count)
4562236b
HW		 1531{
1532 int ret;
1533 int s3_state;
1534 struct pci_dev *pdev = to_pci_dev(device);
1535 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1536 struct amdgpu_device *adev = drm_dev->dev_private;
1537
1538 ret = kstrtoint(buf, 0, &s3_state);
1539
1540 if (ret == 0) {
1541 if (s3_state) {
1542 dm_resume(adev);
1543 amdgpu_dm_display_resume(adev);
1544 drm_kms_helper_hotplug_event(adev->ddev);
1545 } else
1546 dm_suspend(adev);
1547 }
1548
1549 return ret == 0 ? count : 0;
1550}
1551
1552DEVICE_ATTR_WO(s3_debug);
1553
1554#endif
1555
1556static int dm_early_init(void *handle)
1557{
1558 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1559
d7ec53d9 1560 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
4562236b
HW		 1561 amdgpu_dm_set_irq_funcs(adev);
1562
1563 switch (adev->asic_type) {
1564 case CHIP_BONAIRE:
1565 case CHIP_HAWAII:
1566 adev->mode_info.num_crtc = 6;
1567 adev->mode_info.num_hpd = 6;
1568 adev->mode_info.num_dig = 6;
3be5262e 1569 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1570 break;
cd4b356f
AD		 1571 case CHIP_KAVERI:
1572 adev->mode_info.num_crtc = 4;
1573 adev->mode_info.num_hpd = 6;
1574 adev->mode_info.num_dig = 7;
1575 adev->mode_info.plane_type = dm_plane_type_default;
1576 break;
1577 case CHIP_KABINI:
1578 case CHIP_MULLINS:
1579 adev->mode_info.num_crtc = 2;
1580 adev->mode_info.num_hpd = 6;
1581 adev->mode_info.num_dig = 6;
1582 adev->mode_info.plane_type = dm_plane_type_default;
1583 break;
4562236b
HW		 1584 case CHIP_FIJI:
1585 case CHIP_TONGA:
1586 adev->mode_info.num_crtc = 6;
1587 adev->mode_info.num_hpd = 6;
1588 adev->mode_info.num_dig = 7;
3be5262e 1589 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1590 break;
1591 case CHIP_CARRIZO:
1592 adev->mode_info.num_crtc = 3;
1593 adev->mode_info.num_hpd = 6;
1594 adev->mode_info.num_dig = 9;
3be5262e 1595 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1596 break;
1597 case CHIP_STONEY:
1598 adev->mode_info.num_crtc = 2;
1599 adev->mode_info.num_hpd = 6;
1600 adev->mode_info.num_dig = 9;
3be5262e 1601 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1602 break;
1603 case CHIP_POLARIS11:
b264d345 1604 case CHIP_POLARIS12:
4562236b
HW		 1605 adev->mode_info.num_crtc = 5;
1606 adev->mode_info.num_hpd = 5;
1607 adev->mode_info.num_dig = 5;
3be5262e 1608 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1609 break;
1610 case CHIP_POLARIS10:
1611 adev->mode_info.num_crtc = 6;
1612 adev->mode_info.num_hpd = 6;
1613 adev->mode_info.num_dig = 6;
3be5262e 1614 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1615 break;
2c8ad2d5
AD		 1616 case CHIP_VEGA10:
1617 adev->mode_info.num_crtc = 6;
1618 adev->mode_info.num_hpd = 6;
1619 adev->mode_info.num_dig = 6;
3be5262e 1620 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1621 break;
ff5ef992
AD		 1622#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1623 case CHIP_RAVEN:
1624 adev->mode_info.num_crtc = 4;
1625 adev->mode_info.num_hpd = 4;
1626 adev->mode_info.num_dig = 4;
3be5262e 1627 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1628 break;
1629#endif
4562236b
HW		 1630 default:
1631 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1632 return -EINVAL;
1633 }
1634
39cc5be2
AD		 1635 if (adev->mode_info.funcs == NULL)
1636 adev->mode_info.funcs = &dm_display_funcs;
1637
4562236b
HW		 1638 /* Note: Do NOT change adev->audio_endpt_rreg and
1639 * adev->audio_endpt_wreg because they are initialised in
1640 * amdgpu_device_init() */
1641#if defined(CONFIG_DEBUG_KERNEL_DC)
1642 device_create_file(
1643 adev->ddev->dev,
1644 &dev_attr_s3_debug);
1645#endif
1646
1647 return 0;
1648}
1649
e7b07cee
HW		 1650struct dm_connector_state {
1651 struct drm_connector_state base;
1652
1653 enum amdgpu_rmx_type scaling;
1654 uint8_t underscan_vborder;
1655 uint8_t underscan_hborder;
1656 bool underscan_enable;
1657};
1658
1659#define to_dm_connector_state(x)\
1660 container_of((x), struct dm_connector_state, base)
1661
9b690ef3 1662static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1663 struct dc_stream_state *new_stream,
1664 struct dc_stream_state *old_stream)
9b690ef3 1665{
e7b07cee
HW		 1666 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1667 return false;
1668
1669 if (!crtc_state->enable)
1670 return false;
1671
1672 return crtc_state->active;
1673}
1674
1675static bool modereset_required(struct drm_crtc_state *crtc_state)
1676{
1677 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1678 return false;
1679
1680 return !crtc_state->enable || !crtc_state->active;
1681}
1682
7578ecda 1683static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1684{
1685 drm_encoder_cleanup(encoder);
1686 kfree(encoder);
1687}
1688
1689static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1690 .destroy = amdgpu_dm_encoder_destroy,
1691};
1692
3ee6b26b
AD		 1693static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1694 struct dc_plane_state *plane_state)
e7b07cee 1695{
3be5262e
HW		 1696 plane_state->src_rect.x = state->src_x >> 16;
1697 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1698 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1699 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1700
3be5262e 1701 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1702 return false;
1703
3be5262e
HW		 1704 plane_state->src_rect.height = state->src_h >> 16;
1705 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1706 return false;
1707
3be5262e
HW		 1708 plane_state->dst_rect.x = state->crtc_x;
1709 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1710
1711 if (state->crtc_w == 0)
1712 return false;
1713
3be5262e 1714 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1715
1716 if (state->crtc_h == 0)
1717 return false;
1718
3be5262e 1719 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1720
3be5262e 1721 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1722
1723 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1724 case DRM_MODE_ROTATE_0:
3be5262e 1725 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1726 break;
1727 case DRM_MODE_ROTATE_90:
3be5262e 1728 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1729 break;
1730 case DRM_MODE_ROTATE_180:
3be5262e 1731 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1732 break;
1733 case DRM_MODE_ROTATE_270:
3be5262e 1734 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1735 break;
1736 default:
3be5262e 1737 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1738 break;
1739 }
1740
4562236b
HW		 1741 return true;
1742}
3ee6b26b
AD		 1743static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1744 uint64_t *tiling_flags,
1745 uint64_t *fb_location)
e7b07cee
HW		 1746{
1747 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1748 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1749
e7b07cee 1750 if (unlikely(r)) {
9bbc3031
JZ		 1751 // Don't show error msg. when return -ERESTARTSYS
1752 if (r != -ERESTARTSYS)
1753 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1754 return r;
1755 }
1756
1757 if (fb_location)
1758 *fb_location = amdgpu_bo_gpu_offset(rbo);
1759
1760 if (tiling_flags)
1761 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1762
1763 amdgpu_bo_unreserve(rbo);
1764
1765 return r;
1766}
1767
3ee6b26b
AD		 1768static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1769 struct dc_plane_state *plane_state,
1770 const struct amdgpu_framebuffer *amdgpu_fb,
1771 bool addReq)
e7b07cee
HW		 1772{
1773 uint64_t tiling_flags;
1774 uint64_t fb_location = 0;
4d3e00da 1775 uint64_t chroma_addr = 0;
e7b07cee
HW		 1776 unsigned int awidth;
1777 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1778 int ret = 0;
1779 struct drm_format_name_buf format_name;
1780
1781 ret = get_fb_info(
1782 amdgpu_fb,
1783 &tiling_flags,
1784 addReq == true ? &fb_location:NULL);
1785
1786 if (ret)
1787 return ret;
1788
1789 switch (fb->format->format) {
1790 case DRM_FORMAT_C8:
3be5262e 1791 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1792 break;
1793 case DRM_FORMAT_RGB565:
3be5262e 1794 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1795 break;
1796 case DRM_FORMAT_XRGB8888:
1797 case DRM_FORMAT_ARGB8888:
3be5262e 1798 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1799 break;
1800 case DRM_FORMAT_XRGB2101010:
1801 case DRM_FORMAT_ARGB2101010:
3be5262e 1802 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1803 break;
1804 case DRM_FORMAT_XBGR2101010:
1805 case DRM_FORMAT_ABGR2101010:
3be5262e 1806 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1807 break;
1808 case DRM_FORMAT_NV21:
3be5262e 1809 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1810 break;
1811 case DRM_FORMAT_NV12:
3be5262e 1812 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1813 break;
1814 default:
1815 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1816 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1817 return -EINVAL;
1818 }
1819
3be5262e
HW		 1820 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1821 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1822 plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
1823 plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
1824 plane_state->plane_size.grph.surface_size.x = 0;
1825 plane_state->plane_size.grph.surface_size.y = 0;
1826 plane_state->plane_size.grph.surface_size.width = fb->width;
1827 plane_state->plane_size.grph.surface_size.height = fb->height;
1828 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1829 fb->pitches[0] / fb->format->cpp[0];
1830 /* TODO: unhardcode */
3be5262e 1831 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1832
1833 } else {
1834 awidth = ALIGN(fb->width, 64);
3be5262e
HW		 1835 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1836 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 1837 = lower_32_bits(fb_location);
4d3e00da
S		 1838 plane_state->address.video_progressive.luma_addr.high_part
1839 = upper_32_bits(fb_location);
1840 chroma_addr = fb_location + (u64)(awidth * fb->height);
3be5262e 1841 plane_state->address.video_progressive.chroma_addr.low_part
4d3e00da
S		 1842 = lower_32_bits(chroma_addr);
1843 plane_state->address.video_progressive.chroma_addr.high_part
1844 = upper_32_bits(chroma_addr);
3be5262e
HW		 1845 plane_state->plane_size.video.luma_size.x = 0;
1846 plane_state->plane_size.video.luma_size.y = 0;
1847 plane_state->plane_size.video.luma_size.width = awidth;
1848 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1849 /* TODO: unhardcode */
3be5262e 1850 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1851
3be5262e
HW		 1852 plane_state->plane_size.video.chroma_size.x = 0;
1853 plane_state->plane_size.video.chroma_size.y = 0;
1854 plane_state->plane_size.video.chroma_size.width = awidth;
1855 plane_state->plane_size.video.chroma_size.height = fb->height;
1856 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1857
1858 /* TODO: unhardcode */
3be5262e 1859 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1860 }
1861
3be5262e 1862 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1863
b830ebc9
HW		 1864 /* Fill GFX8 params */
1865 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1866 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1867
1868 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1869 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1870 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1871 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1872 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1873
1874 /* XXX fix me for VI */
3be5262e
HW		 1875 plane_state->tiling_info.gfx8.num_banks = num_banks;
1876 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1877 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1878 plane_state->tiling_info.gfx8.tile_split = tile_split;
1879 plane_state->tiling_info.gfx8.bank_width = bankw;
1880 plane_state->tiling_info.gfx8.bank_height = bankh;
1881 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1882 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1883 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1884 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1885 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1886 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1887 }
1888
3be5262e 1889 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1890 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1891
1892 if (adev->asic_type == CHIP_VEGA10 ||
1893 adev->asic_type == CHIP_RAVEN) {
1894 /* Fill GFX9 params */
3be5262e 1895 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1896 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1897 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1898 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1899 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1900 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1901 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1902 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1903 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1904 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1905 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1906 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1907 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1908 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1909 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1910 }
1911
3be5262e
HW		 1912 plane_state->visible = true;
1913 plane_state->scaling_quality.h_taps_c = 0;
1914 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1915
3be5262e
HW		 1916 /* is this needed? is plane_state zeroed at allocation? */
1917 plane_state->scaling_quality.h_taps = 0;
1918 plane_state->scaling_quality.v_taps = 0;
1919 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1920
1921 return ret;
1922
1923}
1924
3ee6b26b
AD		 1925static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state,
1926 struct dc_plane_state *plane_state)
e7b07cee
HW		 1927{
1928 int i;
1929 struct dc_gamma *gamma;
d66cf5f5
AK		 1930 struct drm_color_lut *lut =
1931 (struct drm_color_lut *) crtc_state->gamma_lut->data;
e7b07cee
HW		 1932
1933 gamma = dc_create_gamma();
1934
1935 if (gamma == NULL) {
1936 WARN_ON(1);
1937 return;
1938 }
1939
7483bed4
HW		 1940 gamma->type = GAMMA_RGB_256;
1941 gamma->num_entries = GAMMA_RGB_256_ENTRIES;
d66cf5f5
AK		 1942 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1943 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1944 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1945 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
e7b07cee
HW		 1946 }
1947
3be5262e 1948 plane_state->gamma_correction = gamma;
e7b07cee
HW		 1949}
1950
3ee6b26b
AD		 1951static int fill_plane_attributes(struct amdgpu_device *adev,
1952 struct dc_plane_state *dc_plane_state,
1953 struct drm_plane_state *plane_state,
1954 struct drm_crtc_state *crtc_state,
1955 bool addrReq)
e7b07cee
HW		 1956{
1957 const struct amdgpu_framebuffer *amdgpu_fb =
1958 to_amdgpu_framebuffer(plane_state->fb);
1959 const struct drm_crtc *crtc = plane_state->crtc;
1960 struct dc_transfer_func *input_tf;
1961 int ret = 0;
1962
3be5262e 1963 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1964 return -EINVAL;
1965
1966 ret = fill_plane_attributes_from_fb(
1967 crtc->dev->dev_private,
3be5262e 1968 dc_plane_state,
e7b07cee
HW		 1969 amdgpu_fb,
1970 addrReq);
1971
1972 if (ret)
1973 return ret;
1974
1975 input_tf = dc_create_transfer_func();
1976
1977 if (input_tf == NULL)
1978 return -ENOMEM;
1979
1980 input_tf->type = TF_TYPE_PREDEFINED;
1981 input_tf->tf = TRANSFER_FUNCTION_SRGB;
1982
3be5262e 1983 dc_plane_state->in_transfer_func = input_tf;
e7b07cee
HW		 1984
1985 /* In case of gamma set, update gamma value */
1986 if (crtc_state->gamma_lut)
3be5262e 1987 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
e7b07cee
HW		 1988
1989 return ret;
1990}
1991
1992/*****************************************************************************/
1993
3ee6b26b
AD		 1994static void update_stream_scaling_settings(const struct drm_display_mode *mode,
1995 const struct dm_connector_state *dm_state,
1996 struct dc_stream_state *stream)
e7b07cee
HW		 1997{
1998 enum amdgpu_rmx_type rmx_type;
1999
2000 struct rect src = { 0 }; /* viewport in composition space*/
2001 struct rect dst = { 0 }; /* stream addressable area */
2002
2003 /* no mode. nothing to be done */
2004 if (!mode)
2005 return;
2006
2007 /* Full screen scaling by default */
2008 src.width = mode->hdisplay;
2009 src.height = mode->vdisplay;
2010 dst.width = stream->timing.h_addressable;
2011 dst.height = stream->timing.v_addressable;
2012
2013 rmx_type = dm_state->scaling;
2014 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2015 if (src.width * dst.height <
2016 src.height * dst.width) {
2017 /* height needs less upscaling/more downscaling */
2018 dst.width = src.width *
2019 dst.height / src.height;
2020 } else {
2021 /* width needs less upscaling/more downscaling */
2022 dst.height = src.height *
2023 dst.width / src.width;
2024 }
2025 } else if (rmx_type == RMX_CENTER) {
2026 dst = src;
2027 }
2028
2029 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2030 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2031
2032 if (dm_state->underscan_enable) {
2033 dst.x += dm_state->underscan_hborder / 2;
2034 dst.y += dm_state->underscan_vborder / 2;
2035 dst.width -= dm_state->underscan_hborder;
2036 dst.height -= dm_state->underscan_vborder;
2037 }
2038
2039 stream->src = src;
2040 stream->dst = dst;
2041
f1ad2f5e 2042 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2043 dst.x, dst.y, dst.width, dst.height);
2044
2045}
2046
3ee6b26b
AD		 2047static enum dc_color_depth
2048convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2049{
2050 uint32_t bpc = connector->display_info.bpc;
2051
2052 /* Limited color depth to 8bit
b830ebc9
HW		 2053 * TODO: Still need to handle deep color
2054 */
e7b07cee
HW		 2055 if (bpc > 8)
2056 bpc = 8;
2057
2058 switch (bpc) {
2059 case 0:
2060 /* Temporary Work around, DRM don't parse color depth for
2061 * EDID revision before 1.4
2062 * TODO: Fix edid parsing
2063 */
2064 return COLOR_DEPTH_888;
2065 case 6:
2066 return COLOR_DEPTH_666;
2067 case 8:
2068 return COLOR_DEPTH_888;
2069 case 10:
2070 return COLOR_DEPTH_101010;
2071 case 12:
2072 return COLOR_DEPTH_121212;
2073 case 14:
2074 return COLOR_DEPTH_141414;
2075 case 16:
2076 return COLOR_DEPTH_161616;
2077 default:
2078 return COLOR_DEPTH_UNDEFINED;
2079 }
2080}
2081
3ee6b26b
AD		 2082static enum dc_aspect_ratio
2083get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2084{
2085 int32_t width = mode_in->crtc_hdisplay * 9;
2086 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2087
e7b07cee
HW		 2088 if ((width - height) < 10 && (width - height) > -10)
2089 return ASPECT_RATIO_16_9;
2090 else
2091 return ASPECT_RATIO_4_3;
2092}
2093
3ee6b26b
AD		 2094static enum dc_color_space
2095get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2096{
2097 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2098
2099 switch (dc_crtc_timing->pixel_encoding) {
2100 case PIXEL_ENCODING_YCBCR422:
2101 case PIXEL_ENCODING_YCBCR444:
2102 case PIXEL_ENCODING_YCBCR420:
2103 {
2104 /*
2105 * 27030khz is the separation point between HDTV and SDTV
2106 * according to HDMI spec, we use YCbCr709 and YCbCr601
2107 * respectively
2108 */
2109 if (dc_crtc_timing->pix_clk_khz > 27030) {
2110 if (dc_crtc_timing->flags.Y_ONLY)
2111 color_space =
2112 COLOR_SPACE_YCBCR709_LIMITED;
2113 else
2114 color_space = COLOR_SPACE_YCBCR709;
2115 } else {
2116 if (dc_crtc_timing->flags.Y_ONLY)
2117 color_space =
2118 COLOR_SPACE_YCBCR601_LIMITED;
2119 else
2120 color_space = COLOR_SPACE_YCBCR601;
2121 }
2122
2123 }
2124 break;
2125 case PIXEL_ENCODING_RGB:
2126 color_space = COLOR_SPACE_SRGB;
2127 break;
2128
2129 default:
2130 WARN_ON(1);
2131 break;
2132 }
2133
2134 return color_space;
2135}
2136
2137/*****************************************************************************/
2138
3ee6b26b
AD		 2139static void
2140fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2141 const struct drm_display_mode *mode_in,
2142 const struct drm_connector *connector)
e7b07cee
HW		 2143{
2144 struct dc_crtc_timing *timing_out = &stream->timing;
b830ebc9 2145
e7b07cee
HW		 2146 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2147
2148 timing_out->h_border_left = 0;
2149 timing_out->h_border_right = 0;
2150 timing_out->v_border_top = 0;
2151 timing_out->v_border_bottom = 0;
2152 /* TODO: un-hardcode */
2153
2154 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2155 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2156 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2157 else
2158 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2159
2160 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2161 timing_out->display_color_depth = convert_color_depth_from_display_info(
2162 connector);
2163 timing_out->scan_type = SCANNING_TYPE_NODATA;
2164 timing_out->hdmi_vic = 0;
2165 timing_out->vic = drm_match_cea_mode(mode_in);
2166
2167 timing_out->h_addressable = mode_in->crtc_hdisplay;
2168 timing_out->h_total = mode_in->crtc_htotal;
2169 timing_out->h_sync_width =
2170 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2171 timing_out->h_front_porch =
2172 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2173 timing_out->v_total = mode_in->crtc_vtotal;
2174 timing_out->v_addressable = mode_in->crtc_vdisplay;
2175 timing_out->v_front_porch =
2176 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2177 timing_out->v_sync_width =
2178 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2179 timing_out->pix_clk_khz = mode_in->crtc_clock;
2180 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2181 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2182 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2183 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2184 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2185
2186 stream->output_color_space = get_output_color_space(timing_out);
2187
2188 {
2189 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2190
e7b07cee
HW		 2191 tf->type = TF_TYPE_PREDEFINED;
2192 tf->tf = TRANSFER_FUNCTION_SRGB;
2193 stream->out_transfer_func = tf;
2194 }
2195}
2196
3ee6b26b
AD		 2197static void fill_audio_info(struct audio_info *audio_info,
2198 const struct drm_connector *drm_connector,
2199 const struct dc_sink *dc_sink)
e7b07cee
HW		 2200{
2201 int i = 0;
2202 int cea_revision = 0;
2203 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2204
2205 audio_info->manufacture_id = edid_caps->manufacturer_id;
2206 audio_info->product_id = edid_caps->product_id;
2207
2208 cea_revision = drm_connector->display_info.cea_rev;
2209
d2b2562c
TSD		 2210 strncpy(audio_info->display_name,
2211 edid_caps->display_name,
2212 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2213
b830ebc9 2214 if (cea_revision >= 3) {
e7b07cee
HW		 2215 audio_info->mode_count = edid_caps->audio_mode_count;
2216
2217 for (i = 0; i < audio_info->mode_count; ++i) {
2218 audio_info->modes[i].format_code =
2219 (enum audio_format_code)
2220 (edid_caps->audio_modes[i].format_code);
2221 audio_info->modes[i].channel_count =
2222 edid_caps->audio_modes[i].channel_count;
2223 audio_info->modes[i].sample_rates.all =
2224 edid_caps->audio_modes[i].sample_rate;
2225 audio_info->modes[i].sample_size =
2226 edid_caps->audio_modes[i].sample_size;
2227 }
2228 }
2229
2230 audio_info->flags.all = edid_caps->speaker_flags;
2231
2232 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2233 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2234 audio_info->video_latency = drm_connector->video_latency[0];
2235 audio_info->audio_latency = drm_connector->audio_latency[0];
2236 }
2237
2238 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2239
2240}
2241
3ee6b26b
AD		 2242static void
2243copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2244 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2245{
2246 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2247 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2248 dst_mode->crtc_clock = src_mode->crtc_clock;
2249 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2250 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2251 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2252 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2253 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2254 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2255 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2256 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2257 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2258 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2259 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2260}
2261
3ee6b26b
AD		 2262static void
2263decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2264 const struct drm_display_mode *native_mode,
2265 bool scale_enabled)
e7b07cee
HW		 2266{
2267 if (scale_enabled) {
2268 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2269 } else if (native_mode->clock == drm_mode->clock &&
2270 native_mode->htotal == drm_mode->htotal &&
2271 native_mode->vtotal == drm_mode->vtotal) {
2272 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2273 } else {
2274 /* no scaling nor amdgpu inserted, no need to patch */
2275 }
2276}
2277
423788c7 2278static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6
HW		 2279{
2280 struct dc_sink *sink = NULL;
2281 struct dc_sink_init_data sink_init_data = { 0 };
2282
2283 sink_init_data.link = aconnector->dc_link;
2284 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2285
2286 sink = dc_sink_create(&sink_init_data);
423788c7 2287 if (!sink) {
2e0ac3d6 2288 DRM_ERROR("Failed to create sink!\n");
423788c7
ES		 2289 return -ENOMEM;
2290 }
2e0ac3d6
HW		 2291
2292 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2293 aconnector->fake_enable = true;
2294
2295 aconnector->dc_sink = sink;
2296 aconnector->dc_link->local_sink = sink;
423788c7
ES		 2297
2298 return 0;
2e0ac3d6
HW		 2299}
2300
3ee6b26b
AD		 2301static struct dc_stream_state *
2302create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2303 const struct drm_display_mode *drm_mode,
2304 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2305{
2306 struct drm_display_mode *preferred_mode = NULL;
2307 const struct drm_connector *drm_connector;
0971c40e 2308 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2309 struct drm_display_mode mode = *drm_mode;
2310 bool native_mode_found = false;
2311
b830ebc9 2312 if (aconnector == NULL) {
e7b07cee
HW		 2313 DRM_ERROR("aconnector is NULL!\n");
2314 goto drm_connector_null;
2315 }
2316
b830ebc9 2317 if (dm_state == NULL) {
e7b07cee
HW		 2318 DRM_ERROR("dm_state is NULL!\n");
2319 goto dm_state_null;
2320 }
4562236b 2321
e7b07cee 2322 drm_connector = &aconnector->base;
2e0ac3d6 2323
f4ac176e
JZ		 2324 if (!aconnector->dc_sink) {
2325 /*
2326 * Exclude MST from creating fake_sink
2327 * TODO: need to enable MST into fake_sink feature
2328 */
2329 if (aconnector->mst_port)
2330 goto stream_create_fail;
2331
423788c7
ES		 2332 if (create_fake_sink(aconnector))
2333 goto stream_create_fail;
f4ac176e 2334 }
2e0ac3d6 2335
e7b07cee 2336 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2337
b830ebc9 2338 if (stream == NULL) {
e7b07cee
HW		 2339 DRM_ERROR("Failed to create stream for sink!\n");
2340 goto stream_create_fail;
2341 }
2342
2343 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2344 /* Search for preferred mode */
2345 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2346 native_mode_found = true;
2347 break;
2348 }
2349 }
2350 if (!native_mode_found)
2351 preferred_mode = list_first_entry_or_null(
2352 &aconnector->base.modes,
2353 struct drm_display_mode,
2354 head);
2355
b830ebc9 2356 if (preferred_mode == NULL) {
e7b07cee
HW		 2357 /* This may not be an error, the use case is when we we have no
2358 * usermode calls to reset and set mode upon hotplug. In this
2359 * case, we call set mode ourselves to restore the previous mode
2360 * and the modelist may not be filled in in time.
2361 */
f1ad2f5e 2362 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2363 } else {
2364 decide_crtc_timing_for_drm_display_mode(
2365 &mode, preferred_mode,
2366 dm_state->scaling != RMX_OFF);
2367 }
2368
2369 fill_stream_properties_from_drm_display_mode(stream,
2370 &mode, &aconnector->base);
2371 update_stream_scaling_settings(&mode, dm_state, stream);
2372
2373 fill_audio_info(
2374 &stream->audio_info,
2375 drm_connector,
2376 aconnector->dc_sink);
2377
2378stream_create_fail:
2379dm_state_null:
2380drm_connector_null:
2381 return stream;
2382}
2383
7578ecda 2384static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2385{
2386 drm_crtc_cleanup(crtc);
2387 kfree(crtc);
2388}
2389
2390static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2391 struct drm_crtc_state *state)
e7b07cee
HW		 2392{
2393 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2394
2395 /* TODO Destroy dc_stream objects are stream object is flattened */
2396 if (cur->stream)
2397 dc_stream_release(cur->stream);
2398
2399
2400 __drm_atomic_helper_crtc_destroy_state(state);
2401
2402
2403 kfree(state);
2404}
2405
2406static void dm_crtc_reset_state(struct drm_crtc *crtc)
2407{
2408 struct dm_crtc_state *state;
2409
2410 if (crtc->state)
2411 dm_crtc_destroy_state(crtc, crtc->state);
2412
2413 state = kzalloc(sizeof(*state), GFP_KERNEL);
2414 if (WARN_ON(!state))
2415 return;
2416
2417 crtc->state = &state->base;
2418 crtc->state->crtc = crtc;
2419
2420}
2421
2422static struct drm_crtc_state *
2423dm_crtc_duplicate_state(struct drm_crtc *crtc)
2424{
2425 struct dm_crtc_state *state, *cur;
2426
2427 cur = to_dm_crtc_state(crtc->state);
2428
2429 if (WARN_ON(!crtc->state))
2430 return NULL;
2431
2004f45e 2432 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 2433 if (!state)
2434 return NULL;
e7b07cee
HW		 2435
2436 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2437
2438 if (cur->stream) {
2439 state->stream = cur->stream;
2440 dc_stream_retain(state->stream);
2441 }
2442
2443 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2444
2445 return &state->base;
2446}
2447
2448/* Implemented only the options currently availible for the driver */
2449static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2450 .reset = dm_crtc_reset_state,
2451 .destroy = amdgpu_dm_crtc_destroy,
2452 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2453 .set_config = drm_atomic_helper_set_config,
2454 .page_flip = drm_atomic_helper_page_flip,
2455 .atomic_duplicate_state = dm_crtc_duplicate_state,
2456 .atomic_destroy_state = dm_crtc_destroy_state,
2457};
2458
2459static enum drm_connector_status
2460amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2461{
2462 bool connected;
c84dec2f 2463 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2464
2465 /* Notes:
2466 * 1. This interface is NOT called in context of HPD irq.
2467 * 2. This interface *is called* in context of user-mode ioctl. Which
2468 * makes it a bad place for *any* MST-related activit. */
2469
8580d60b
HW		 2470 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2471 !aconnector->fake_enable)
e7b07cee
HW		 2472 connected = (aconnector->dc_sink != NULL);
2473 else
2474 connected = (aconnector->base.force == DRM_FORCE_ON);
2475
2476 return (connected ? connector_status_connected :
2477 connector_status_disconnected);
2478}
2479
3ee6b26b
AD		 2480int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2481 struct drm_connector_state *connector_state,
2482 struct drm_property *property,
2483 uint64_t val)
e7b07cee
HW		 2484{
2485 struct drm_device *dev = connector->dev;
2486 struct amdgpu_device *adev = dev->dev_private;
2487 struct dm_connector_state *dm_old_state =
2488 to_dm_connector_state(connector->state);
2489 struct dm_connector_state *dm_new_state =
2490 to_dm_connector_state(connector_state);
2491
2492 int ret = -EINVAL;
2493
2494 if (property == dev->mode_config.scaling_mode_property) {
2495 enum amdgpu_rmx_type rmx_type;
2496
2497 switch (val) {
2498 case DRM_MODE_SCALE_CENTER:
2499 rmx_type = RMX_CENTER;
2500 break;
2501 case DRM_MODE_SCALE_ASPECT:
2502 rmx_type = RMX_ASPECT;
2503 break;
2504 case DRM_MODE_SCALE_FULLSCREEN:
2505 rmx_type = RMX_FULL;
2506 break;
2507 case DRM_MODE_SCALE_NONE:
2508 default:
2509 rmx_type = RMX_OFF;
2510 break;
2511 }
2512
2513 if (dm_old_state->scaling == rmx_type)
2514 return 0;
2515
2516 dm_new_state->scaling = rmx_type;
2517 ret = 0;
2518 } else if (property == adev->mode_info.underscan_hborder_property) {
2519 dm_new_state->underscan_hborder = val;
2520 ret = 0;
2521 } else if (property == adev->mode_info.underscan_vborder_property) {
2522 dm_new_state->underscan_vborder = val;
2523 ret = 0;
2524 } else if (property == adev->mode_info.underscan_property) {
2525 dm_new_state->underscan_enable = val;
2526 ret = 0;
2527 }
2528
2529 return ret;
2530}
2531
3ee6b26b
AD		 2532int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2533 const struct drm_connector_state *state,
2534 struct drm_property *property,
2535 uint64_t *val)
e7b07cee
HW		 2536{
2537 struct drm_device *dev = connector->dev;
2538 struct amdgpu_device *adev = dev->dev_private;
2539 struct dm_connector_state *dm_state =
2540 to_dm_connector_state(state);
2541 int ret = -EINVAL;
2542
2543 if (property == dev->mode_config.scaling_mode_property) {
2544 switch (dm_state->scaling) {
2545 case RMX_CENTER:
2546 *val = DRM_MODE_SCALE_CENTER;
2547 break;
2548 case RMX_ASPECT:
2549 *val = DRM_MODE_SCALE_ASPECT;
2550 break;
2551 case RMX_FULL:
2552 *val = DRM_MODE_SCALE_FULLSCREEN;
2553 break;
2554 case RMX_OFF:
2555 default:
2556 *val = DRM_MODE_SCALE_NONE;
2557 break;
2558 }
2559 ret = 0;
2560 } else if (property == adev->mode_info.underscan_hborder_property) {
2561 *val = dm_state->underscan_hborder;
2562 ret = 0;
2563 } else if (property == adev->mode_info.underscan_vborder_property) {
2564 *val = dm_state->underscan_vborder;
2565 ret = 0;
2566 } else if (property == adev->mode_info.underscan_property) {
2567 *val = dm_state->underscan_enable;
2568 ret = 0;
2569 }
2570 return ret;
2571}
2572
7578ecda 2573static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2574{
c84dec2f 2575 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2576 const struct dc_link *link = aconnector->dc_link;
2577 struct amdgpu_device *adev = connector->dev->dev_private;
2578 struct amdgpu_display_manager *dm = &adev->dm;
2579#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2580 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2581
2582 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2583 amdgpu_dm_register_backlight_device(dm);
2584
2585 if (dm->backlight_dev) {
2586 backlight_device_unregister(dm->backlight_dev);
2587 dm->backlight_dev = NULL;
2588 }
2589
2590 }
2591#endif
2592 drm_connector_unregister(connector);
2593 drm_connector_cleanup(connector);
2594 kfree(connector);
2595}
2596
2597void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2598{
2599 struct dm_connector_state *state =
2600 to_dm_connector_state(connector->state);
2601
2602 kfree(state);
2603
2604 state = kzalloc(sizeof(*state), GFP_KERNEL);
2605
2606 if (state) {
2607 state->scaling = RMX_OFF;
2608 state->underscan_enable = false;
2609 state->underscan_hborder = 0;
2610 state->underscan_vborder = 0;
2611
2612 connector->state = &state->base;
2613 connector->state->connector = connector;
2614 }
2615}
2616
3ee6b26b
AD		 2617struct drm_connector_state *
2618amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2619{
2620 struct dm_connector_state *state =
2621 to_dm_connector_state(connector->state);
2622
2623 struct dm_connector_state *new_state =
2624 kmemdup(state, sizeof(*state), GFP_KERNEL);
2625
2626 if (new_state) {
2627 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2628 &new_state->base);
e7b07cee
HW		 2629 return &new_state->base;
2630 }
2631
2632 return NULL;
2633}
2634
2635static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2636 .reset = amdgpu_dm_connector_funcs_reset,
2637 .detect = amdgpu_dm_connector_detect,
2638 .fill_modes = drm_helper_probe_single_connector_modes,
2639 .destroy = amdgpu_dm_connector_destroy,
2640 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2641 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2642 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2643 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2644};
2645
2646static struct drm_encoder *best_encoder(struct drm_connector *connector)
2647{
2648 int enc_id = connector->encoder_ids[0];
2649 struct drm_mode_object *obj;
2650 struct drm_encoder *encoder;
2651
f1ad2f5e 2652 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2653
2654 /* pick the encoder ids */
2655 if (enc_id) {
bd21a37d 2656 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2657 if (!obj) {
2658 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2659 return NULL;
2660 }
2661 encoder = obj_to_encoder(obj);
2662 return encoder;
2663 }
2664 DRM_ERROR("No encoder id\n");
2665 return NULL;
2666}
2667
2668static int get_modes(struct drm_connector *connector)
2669{
2670 return amdgpu_dm_connector_get_modes(connector);
2671}
2672
c84dec2f 2673static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2674{
2675 struct dc_sink_init_data init_params = {
2676 .link = aconnector->dc_link,
2677 .sink_signal = SIGNAL_TYPE_VIRTUAL
2678 };
2679 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2680
2681 if (!aconnector->base.edid_blob_ptr ||
2682 !aconnector->base.edid_blob_ptr->data) {
2683 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2684 aconnector->base.name);
2685
2686 aconnector->base.force = DRM_FORCE_OFF;
2687 aconnector->base.override_edid = false;
2688 return;
2689 }
2690
2691 aconnector->edid = edid;
2692
2693 aconnector->dc_em_sink = dc_link_add_remote_sink(
2694 aconnector->dc_link,
2695 (uint8_t *)edid,
2696 (edid->extensions + 1) * EDID_LENGTH,
2697 &init_params);
2698
a68d90e7 2699 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 2700 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2701 aconnector->dc_link->local_sink :
2702 aconnector->dc_em_sink;
2703}
2704
c84dec2f 2705static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2706{
2707 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2708
2709 /* In case of headless boot with force on for DP managed connector
2710 * Those settings have to be != 0 to get initial modeset
2711 */
2712 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2713 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2714 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2715 }
2716
2717
2718 aconnector->base.override_edid = true;
2719 create_eml_sink(aconnector);
2720}
2721
3ee6b26b
AD		 2722int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2723 struct drm_display_mode *mode)
e7b07cee
HW		 2724{
2725 int result = MODE_ERROR;
2726 struct dc_sink *dc_sink;
2727 struct amdgpu_device *adev = connector->dev->dev_private;
2728 /* TODO: Unhardcode stream count */
0971c40e 2729 struct dc_stream_state *stream;
c84dec2f 2730 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2731
2732 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2733 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2734 return result;
2735
2736 /* Only run this the first time mode_valid is called to initilialize
2737 * EDID mgmt
2738 */
2739 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2740 !aconnector->dc_em_sink)
2741 handle_edid_mgmt(aconnector);
2742
c84dec2f 2743 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2744
b830ebc9 2745 if (dc_sink == NULL) {
e7b07cee
HW		 2746 DRM_ERROR("dc_sink is NULL!\n");
2747 goto fail;
2748 }
2749
2750 stream = dc_create_stream_for_sink(dc_sink);
b830ebc9 2751 if (stream == NULL) {
e7b07cee
HW		 2752 DRM_ERROR("Failed to create stream for sink!\n");
2753 goto fail;
2754 }
2755
2756 drm_mode_set_crtcinfo(mode, 0);
2757 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2758
2759 stream->src.width = mode->hdisplay;
2760 stream->src.height = mode->vdisplay;
2761 stream->dst = stream->src;
2762
62c933f9 2763 if (dc_validate_stream(adev->dm.dc, stream) == DC_OK)
e7b07cee
HW		 2764 result = MODE_OK;
2765
2766 dc_stream_release(stream);
2767
2768fail:
2769 /* TODO: error handling*/
2770 return result;
2771}
2772
2773static const struct drm_connector_helper_funcs
2774amdgpu_dm_connector_helper_funcs = {
2775 /*
b830ebc9
HW		 2776 * If hotplug a second bigger display in FB Con mode, bigger resolution
2777 * modes will be filtered by drm_mode_validate_size(), and those modes
2778 * is missing after user start lightdm. So we need to renew modes list.
2779 * in get_modes call back, not just return the modes count
2780 */
e7b07cee
HW		 2781 .get_modes = get_modes,
2782 .mode_valid = amdgpu_dm_connector_mode_valid,
2783 .best_encoder = best_encoder
2784};
2785
2786static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2787{
2788}
2789
3ee6b26b
AD		 2790static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2791 struct drm_crtc_state *state)
e7b07cee
HW		 2792{
2793 struct amdgpu_device *adev = crtc->dev->dev_private;
2794 struct dc *dc = adev->dm.dc;
2795 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2796 int ret = -EINVAL;
2797
9b690ef3
BL		 2798 if (unlikely(!dm_crtc_state->stream &&
2799 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2800 WARN_ON(1);
2801 return ret;
2802 }
2803
2804 /* In some use cases, like reset, no stream is attached */
2805 if (!dm_crtc_state->stream)
2806 return 0;
2807
62c933f9 2808 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 2809 return 0;
2810
2811 return ret;
2812}
2813
3ee6b26b
AD		 2814static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2815 const struct drm_display_mode *mode,
2816 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2817{
2818 return true;
2819}
2820
2821static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2822 .disable = dm_crtc_helper_disable,
2823 .atomic_check = dm_crtc_helper_atomic_check,
2824 .mode_fixup = dm_crtc_helper_mode_fixup
2825};
2826
2827static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2828{
2829
2830}
2831
3ee6b26b
AD		 2832static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2833 struct drm_crtc_state *crtc_state,
2834 struct drm_connector_state *conn_state)
e7b07cee
HW		 2835{
2836 return 0;
2837}
2838
2839const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2840 .disable = dm_encoder_helper_disable,
2841 .atomic_check = dm_encoder_helper_atomic_check
2842};
2843
2844static void dm_drm_plane_reset(struct drm_plane *plane)
2845{
2846 struct dm_plane_state *amdgpu_state = NULL;
2847
2848 if (plane->state)
2849 plane->funcs->atomic_destroy_state(plane, plane->state);
2850
2851 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d
TSD		 2852 WARN_ON(amdgpu_state == NULL);
2853
e7b07cee
HW		 2854 if (amdgpu_state) {
2855 plane->state = &amdgpu_state->base;
2856 plane->state->plane = plane;
2857 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 2858 }
e7b07cee
HW		 2859}
2860
2861static struct drm_plane_state *
2862dm_drm_plane_duplicate_state(struct drm_plane *plane)
2863{
2864 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2865
2866 old_dm_plane_state = to_dm_plane_state(plane->state);
2867 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2868 if (!dm_plane_state)
2869 return NULL;
2870
2871 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2872
3be5262e
HW		 2873 if (old_dm_plane_state->dc_state) {
2874 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2875 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2876 }
2877
2878 return &dm_plane_state->base;
2879}
2880
2881void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2882 struct drm_plane_state *state)
e7b07cee
HW		 2883{
2884 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2885
3be5262e
HW		 2886 if (dm_plane_state->dc_state)
2887 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2888
0627bbd3 2889 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2890}
2891
2892static const struct drm_plane_funcs dm_plane_funcs = {
2893 .update_plane = drm_atomic_helper_update_plane,
2894 .disable_plane = drm_atomic_helper_disable_plane,
2895 .destroy = drm_plane_cleanup,
2896 .reset = dm_drm_plane_reset,
2897 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2898 .atomic_destroy_state = dm_drm_plane_destroy_state,
2899};
2900
3ee6b26b
AD		 2901static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2902 struct drm_plane_state *new_state)
e7b07cee
HW		 2903{
2904 struct amdgpu_framebuffer *afb;
2905 struct drm_gem_object *obj;
2906 struct amdgpu_bo *rbo;
56087b31 2907 uint64_t chroma_addr = 0;
e7b07cee
HW		 2908 int r;
2909 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2910 unsigned int awidth;
2911
2912 dm_plane_state_old = to_dm_plane_state(plane->state);
2913 dm_plane_state_new = to_dm_plane_state(new_state);
2914
2915 if (!new_state->fb) {
f1ad2f5e 2916 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 2917 return 0;
2918 }
2919
2920 afb = to_amdgpu_framebuffer(new_state->fb);
2921
2922 obj = afb->obj;
2923 rbo = gem_to_amdgpu_bo(obj);
2924 r = amdgpu_bo_reserve(rbo, false);
2925 if (unlikely(r != 0))
2926 return r;
2927
2928 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
2929
2930
2931 amdgpu_bo_unreserve(rbo);
2932
2933 if (unlikely(r != 0)) {
30b7c614
HW		 2934 if (r != -ERESTARTSYS)
2935 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
e7b07cee
HW		 2936 return r;
2937 }
2938
2939 amdgpu_bo_ref(rbo);
2940
3be5262e
HW		 2941 if (dm_plane_state_new->dc_state &&
2942 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2943 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 2944
3be5262e
HW		 2945 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2946 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
2947 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 2948 } else {
2949 awidth = ALIGN(new_state->fb->width, 64);
56087b31 2950 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 2951 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 2952 = lower_32_bits(afb->address);
56087b31
S		 2953 plane_state->address.video_progressive.luma_addr.high_part
2954 = upper_32_bits(afb->address);
2955 chroma_addr = afb->address + (u64)(awidth * new_state->fb->height);
3be5262e 2956 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 2957 = lower_32_bits(chroma_addr);
2958 plane_state->address.video_progressive.chroma_addr.high_part
2959 = upper_32_bits(chroma_addr);
e7b07cee
HW		 2960 }
2961 }
2962
2963 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
2964 * prepare and cleanup in drm_atomic_helper_prepare_planes
2965 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
2966 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
2967 * code touching fram buffers should be avoided for DC.
2968 */
2969 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2970 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
2971
2972 acrtc->cursor_bo = obj;
2973 }
2974 return 0;
2975}
2976
3ee6b26b
AD		 2977static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
2978 struct drm_plane_state *old_state)
e7b07cee
HW		 2979{
2980 struct amdgpu_bo *rbo;
2981 struct amdgpu_framebuffer *afb;
2982 int r;
2983
2984 if (!old_state->fb)
2985 return;
2986
2987 afb = to_amdgpu_framebuffer(old_state->fb);
2988 rbo = gem_to_amdgpu_bo(afb->obj);
2989 r = amdgpu_bo_reserve(rbo, false);
2990 if (unlikely(r)) {
2991 DRM_ERROR("failed to reserve rbo before unpin\n");
2992 return;
b830ebc9
HW		 2993 }
2994
2995 amdgpu_bo_unpin(rbo);
2996 amdgpu_bo_unreserve(rbo);
2997 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 2998}
2999
7578ecda
AD		 3000static int dm_plane_atomic_check(struct drm_plane *plane,
3001 struct drm_plane_state *state)
cbd19488
AG		 3002{
3003 struct amdgpu_device *adev = plane->dev->dev_private;
3004 struct dc *dc = adev->dm.dc;
3005 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3006
3be5262e 3007 if (!dm_plane_state->dc_state)
9a3329b1 3008 return 0;
cbd19488 3009
62c933f9 3010 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3011 return 0;
3012
3013 return -EINVAL;
3014}
3015
e7b07cee
HW		 3016static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3017 .prepare_fb = dm_plane_helper_prepare_fb,
3018 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3019 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3020};
3021
3022/*
3023 * TODO: these are currently initialized to rgb formats only.
3024 * For future use cases we should either initialize them dynamically based on
3025 * plane capabilities, or initialize this array to all formats, so internal drm
3026 * check will succeed, and let DC to implement proper check
3027 */
d90371b0 3028static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3029 DRM_FORMAT_RGB888,
3030 DRM_FORMAT_XRGB8888,
3031 DRM_FORMAT_ARGB8888,
3032 DRM_FORMAT_RGBA8888,
3033 DRM_FORMAT_XRGB2101010,
3034 DRM_FORMAT_XBGR2101010,
3035 DRM_FORMAT_ARGB2101010,
3036 DRM_FORMAT_ABGR2101010,
3037};
3038
99d1abf8 3039static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3040 DRM_FORMAT_NV12,
3041 DRM_FORMAT_NV21,
3042};
3043
3044static const u32 cursor_formats[] = {
3045 DRM_FORMAT_ARGB8888
3046};
3047
7578ecda
AD		 3048static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3049 struct amdgpu_plane *aplane,
3050 unsigned long possible_crtcs)
e7b07cee
HW		 3051{
3052 int res = -EPERM;
3053
3054 switch (aplane->base.type) {
3055 case DRM_PLANE_TYPE_PRIMARY:
3056 aplane->base.format_default = true;
3057
3058 res = drm_universal_plane_init(
3059 dm->adev->ddev,
3060 &aplane->base,
3061 possible_crtcs,
3062 &dm_plane_funcs,
3063 rgb_formats,
3064 ARRAY_SIZE(rgb_formats),
3065 NULL, aplane->base.type, NULL);
3066 break;
3067 case DRM_PLANE_TYPE_OVERLAY:
3068 res = drm_universal_plane_init(
3069 dm->adev->ddev,
3070 &aplane->base,
3071 possible_crtcs,
3072 &dm_plane_funcs,
3073 yuv_formats,
3074 ARRAY_SIZE(yuv_formats),
3075 NULL, aplane->base.type, NULL);
3076 break;
3077 case DRM_PLANE_TYPE_CURSOR:
3078 res = drm_universal_plane_init(
3079 dm->adev->ddev,
3080 &aplane->base,
3081 possible_crtcs,
3082 &dm_plane_funcs,
3083 cursor_formats,
3084 ARRAY_SIZE(cursor_formats),
3085 NULL, aplane->base.type, NULL);
3086 break;
3087 }
3088
3089 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3090
96719c54
HW		 3091 /* Create (reset) the plane state */
3092 if (aplane->base.funcs->reset)
3093 aplane->base.funcs->reset(&aplane->base);
3094
3095
e7b07cee
HW		 3096 return res;
3097}
3098
7578ecda
AD		 3099static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3100 struct drm_plane *plane,
3101 uint32_t crtc_index)
e7b07cee
HW		 3102{
3103 struct amdgpu_crtc *acrtc = NULL;
3104 struct amdgpu_plane *cursor_plane;
3105
3106 int res = -ENOMEM;
3107
3108 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3109 if (!cursor_plane)
3110 goto fail;
3111
3112 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3113 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3114
3115 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3116 if (!acrtc)
3117 goto fail;
3118
3119 res = drm_crtc_init_with_planes(
3120 dm->ddev,
3121 &acrtc->base,
3122 plane,
3123 &cursor_plane->base,
3124 &amdgpu_dm_crtc_funcs, NULL);
3125
3126 if (res)
3127 goto fail;
3128
3129 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3130
96719c54
HW		 3131 /* Create (reset) the plane state */
3132 if (acrtc->base.funcs->reset)
3133 acrtc->base.funcs->reset(&acrtc->base);
3134
e7b07cee
HW		 3135 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3136 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3137
3138 acrtc->crtc_id = crtc_index;
3139 acrtc->base.enabled = false;
3140
3141 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3142 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3143
3144 return 0;
3145
3146fail:
b830ebc9
HW		 3147 kfree(acrtc);
3148 kfree(cursor_plane);
e7b07cee
HW		 3149 return res;
3150}
3151
3152
3153static int to_drm_connector_type(enum signal_type st)
3154{
3155 switch (st) {
3156 case SIGNAL_TYPE_HDMI_TYPE_A:
3157 return DRM_MODE_CONNECTOR_HDMIA;
3158 case SIGNAL_TYPE_EDP:
3159 return DRM_MODE_CONNECTOR_eDP;
3160 case SIGNAL_TYPE_RGB:
3161 return DRM_MODE_CONNECTOR_VGA;
3162 case SIGNAL_TYPE_DISPLAY_PORT:
3163 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3164 return DRM_MODE_CONNECTOR_DisplayPort;
3165 case SIGNAL_TYPE_DVI_DUAL_LINK:
3166 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3167 return DRM_MODE_CONNECTOR_DVID;
3168 case SIGNAL_TYPE_VIRTUAL:
3169 return DRM_MODE_CONNECTOR_VIRTUAL;
3170
3171 default:
3172 return DRM_MODE_CONNECTOR_Unknown;
3173 }
3174}
3175
3176static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3177{
3178 const struct drm_connector_helper_funcs *helper =
3179 connector->helper_private;
3180 struct drm_encoder *encoder;
3181 struct amdgpu_encoder *amdgpu_encoder;
3182
3183 encoder = helper->best_encoder(connector);
3184
3185 if (encoder == NULL)
3186 return;
3187
3188 amdgpu_encoder = to_amdgpu_encoder(encoder);
3189
3190 amdgpu_encoder->native_mode.clock = 0;
3191
3192 if (!list_empty(&connector->probed_modes)) {
3193 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3194
e7b07cee 3195 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3196 &connector->probed_modes,
3197 head) {
3198 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3199 amdgpu_encoder->native_mode = *preferred_mode;
3200
e7b07cee
HW		 3201 break;
3202 }
3203
3204 }
3205}
3206
3ee6b26b
AD		 3207static struct drm_display_mode *
3208amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3209 char *name,
3210 int hdisplay, int vdisplay)
e7b07cee
HW		 3211{
3212 struct drm_device *dev = encoder->dev;
3213 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3214 struct drm_display_mode *mode = NULL;
3215 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3216
3217 mode = drm_mode_duplicate(dev, native_mode);
3218
b830ebc9 3219 if (mode == NULL)
e7b07cee
HW		 3220 return NULL;
3221
3222 mode->hdisplay = hdisplay;
3223 mode->vdisplay = vdisplay;
3224 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3225 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3226
3227 return mode;
3228
3229}
3230
3231static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3232 struct drm_connector *connector)
e7b07cee
HW		 3233{
3234 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3235 struct drm_display_mode *mode = NULL;
3236 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3237 struct amdgpu_dm_connector *amdgpu_dm_connector =
3238 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3239 int i;
3240 int n;
3241 struct mode_size {
3242 char name[DRM_DISPLAY_MODE_LEN];
3243 int w;
3244 int h;
b830ebc9 3245 } common_modes[] = {
e7b07cee
HW		 3246 { "640x480", 640, 480},
3247 { "800x600", 800, 600},
3248 { "1024x768", 1024, 768},
3249 { "1280x720", 1280, 720},
3250 { "1280x800", 1280, 800},
3251 {"1280x1024", 1280, 1024},
3252 { "1440x900", 1440, 900},
3253 {"1680x1050", 1680, 1050},
3254 {"1600x1200", 1600, 1200},
3255 {"1920x1080", 1920, 1080},
3256 {"1920x1200", 1920, 1200}
3257 };
3258
b830ebc9 3259 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3260
3261 for (i = 0; i < n; i++) {
3262 struct drm_display_mode *curmode = NULL;
3263 bool mode_existed = false;
3264
3265 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3266 common_modes[i].h > native_mode->vdisplay ||
3267 (common_modes[i].w == native_mode->hdisplay &&
3268 common_modes[i].h == native_mode->vdisplay))
3269 continue;
e7b07cee
HW		 3270
3271 list_for_each_entry(curmode, &connector->probed_modes, head) {
3272 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3273 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3274 mode_existed = true;
3275 break;
3276 }
3277 }
3278
3279 if (mode_existed)
3280 continue;
3281
3282 mode = amdgpu_dm_create_common_mode(encoder,
3283 common_modes[i].name, common_modes[i].w,
3284 common_modes[i].h);
3285 drm_mode_probed_add(connector, mode);
c84dec2f 3286 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3287 }
3288}
3289
3ee6b26b
AD		 3290static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3291 struct edid *edid)
e7b07cee 3292{
c84dec2f
HW		 3293 struct amdgpu_dm_connector *amdgpu_dm_connector =
3294 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3295
3296 if (edid) {
3297 /* empty probed_modes */
3298 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3299 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3300 drm_add_edid_modes(connector, edid);
3301
3302 drm_edid_to_eld(connector, edid);
3303
3304 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3305 } else {
c84dec2f 3306 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3307 }
e7b07cee
HW		 3308}
3309
7578ecda 3310static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3311{
3312 const struct drm_connector_helper_funcs *helper =
3313 connector->helper_private;
c84dec2f
HW		 3314 struct amdgpu_dm_connector *amdgpu_dm_connector =
3315 to_amdgpu_dm_connector(connector);
e7b07cee 3316 struct drm_encoder *encoder;
c84dec2f 3317 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3318
3319 encoder = helper->best_encoder(connector);
3320
3321 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3322 amdgpu_dm_connector_add_common_modes(encoder, connector);
c84dec2f 3323 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3324}
3325
3ee6b26b
AD		 3326void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3327 struct amdgpu_dm_connector *aconnector,
3328 int connector_type,
3329 struct dc_link *link,
3330 int link_index)
e7b07cee
HW		 3331{
3332 struct amdgpu_device *adev = dm->ddev->dev_private;
3333
3334 aconnector->connector_id = link_index;
3335 aconnector->dc_link = link;
3336 aconnector->base.interlace_allowed = false;
3337 aconnector->base.doublescan_allowed = false;
3338 aconnector->base.stereo_allowed = false;
3339 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3340 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3341
3342 mutex_init(&aconnector->hpd_lock);
3343
b830ebc9
HW		 3344 /* configure support HPD hot plug connector_>polled default value is 0
3345 * which means HPD hot plug not supported
3346 */
e7b07cee
HW		 3347 switch (connector_type) {
3348 case DRM_MODE_CONNECTOR_HDMIA:
3349 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3350 break;
3351 case DRM_MODE_CONNECTOR_DisplayPort:
3352 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3353 break;
3354 case DRM_MODE_CONNECTOR_DVID:
3355 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3356 break;
3357 default:
3358 break;
3359 }
3360
3361 drm_object_attach_property(&aconnector->base.base,
3362 dm->ddev->mode_config.scaling_mode_property,
3363 DRM_MODE_SCALE_NONE);
3364
3365 drm_object_attach_property(&aconnector->base.base,
3366 adev->mode_info.underscan_property,
3367 UNDERSCAN_OFF);
3368 drm_object_attach_property(&aconnector->base.base,
3369 adev->mode_info.underscan_hborder_property,
3370 0);
3371 drm_object_attach_property(&aconnector->base.base,
3372 adev->mode_info.underscan_vborder_property,
3373 0);
3374
3375}
3376
7578ecda
AD		 3377static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3378 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3379{
3380 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3381 struct ddc_service *ddc_service = i2c->ddc_service;
3382 struct i2c_command cmd;
3383 int i;
3384 int result = -EIO;
3385
b830ebc9 3386 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3387
3388 if (!cmd.payloads)
3389 return result;
3390
3391 cmd.number_of_payloads = num;
3392 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3393 cmd.speed = 100;
3394
3395 for (i = 0; i < num; i++) {
3396 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3397 cmd.payloads[i].address = msgs[i].addr;
3398 cmd.payloads[i].length = msgs[i].len;
3399 cmd.payloads[i].data = msgs[i].buf;
3400 }
3401
3402 if (dal_i2caux_submit_i2c_command(
3403 ddc_service->ctx->i2caux,
3404 ddc_service->ddc_pin,
3405 &cmd))
3406 result = num;
3407
3408 kfree(cmd.payloads);
3409 return result;
3410}
3411
7578ecda 3412static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3413{
3414 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3415}
3416
3417static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3418 .master_xfer = amdgpu_dm_i2c_xfer,
3419 .functionality = amdgpu_dm_i2c_func,
3420};
3421
3ee6b26b
AD		 3422static struct amdgpu_i2c_adapter *
3423create_i2c(struct ddc_service *ddc_service,
3424 int link_index,
3425 int *res)
e7b07cee
HW		 3426{
3427 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3428 struct amdgpu_i2c_adapter *i2c;
3429
b830ebc9 3430 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 3431 if (!i2c)
3432 return NULL;
e7b07cee
HW		 3433 i2c->base.owner = THIS_MODULE;
3434 i2c->base.class = I2C_CLASS_DDC;
3435 i2c->base.dev.parent = &adev->pdev->dev;
3436 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3437 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3438 i2c_set_adapdata(&i2c->base, i2c);
3439 i2c->ddc_service = ddc_service;
3440
3441 return i2c;
3442}
3443
3444/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3445 * dc_link which will be represented by this aconnector.
3446 */
7578ecda
AD		 3447static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3448 struct amdgpu_dm_connector *aconnector,
3449 uint32_t link_index,
3450 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3451{
3452 int res = 0;
3453 int connector_type;
3454 struct dc *dc = dm->dc;
3455 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3456 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 3457
3458 link->priv = aconnector;
e7b07cee 3459
f1ad2f5e 3460 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3461
3462 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 3463 if (!i2c) {
3464 DRM_ERROR("Failed to create i2c adapter data\n");
3465 return -ENOMEM;
3466 }
3467
e7b07cee
HW		 3468 aconnector->i2c = i2c;
3469 res = i2c_add_adapter(&i2c->base);
3470
3471 if (res) {
3472 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3473 goto out_free;
3474 }
3475
3476 connector_type = to_drm_connector_type(link->connector_signal);
3477
3478 res = drm_connector_init(
3479 dm->ddev,
3480 &aconnector->base,
3481 &amdgpu_dm_connector_funcs,
3482 connector_type);
3483
3484 if (res) {
3485 DRM_ERROR("connector_init failed\n");
3486 aconnector->connector_id = -1;
3487 goto out_free;
3488 }
3489
3490 drm_connector_helper_add(
3491 &aconnector->base,
3492 &amdgpu_dm_connector_helper_funcs);
3493
96719c54
HW		 3494 if (aconnector->base.funcs->reset)
3495 aconnector->base.funcs->reset(&aconnector->base);
3496
e7b07cee
HW		 3497 amdgpu_dm_connector_init_helper(
3498 dm,
3499 aconnector,
3500 connector_type,
3501 link,
3502 link_index);
3503
3504 drm_mode_connector_attach_encoder(
3505 &aconnector->base, &aencoder->base);
3506
3507 drm_connector_register(&aconnector->base);
3508
3509 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3510 || connector_type == DRM_MODE_CONNECTOR_eDP)
3511 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3512
3513#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3514 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3515
3516 /* NOTE: this currently will create backlight device even if a panel
3517 * is not connected to the eDP/LVDS connector.
3518 *
3519 * This is less than ideal but we don't have sink information at this
3520 * stage since detection happens after. We can't do detection earlier
3521 * since MST detection needs connectors to be created first.
3522 */
3523 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3524 /* Event if registration failed, we should continue with
3525 * DM initialization because not having a backlight control
b830ebc9
HW		 3526 * is better then a black screen.
3527 */
e7b07cee
HW		 3528 amdgpu_dm_register_backlight_device(dm);
3529
3530 if (dm->backlight_dev)
3531 dm->backlight_link = link;
3532 }
3533#endif
3534
3535out_free:
3536 if (res) {
3537 kfree(i2c);
3538 aconnector->i2c = NULL;
3539 }
3540 return res;
3541}
3542
3543int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3544{
3545 switch (adev->mode_info.num_crtc) {
3546 case 1:
3547 return 0x1;
3548 case 2:
3549 return 0x3;
3550 case 3:
3551 return 0x7;
3552 case 4:
3553 return 0xf;
3554 case 5:
3555 return 0x1f;
3556 case 6:
3557 default:
3558 return 0x3f;
3559 }
3560}
3561
7578ecda
AD		 3562static int amdgpu_dm_encoder_init(struct drm_device *dev,
3563 struct amdgpu_encoder *aencoder,
3564 uint32_t link_index)
e7b07cee
HW		 3565{
3566 struct amdgpu_device *adev = dev->dev_private;
3567
3568 int res = drm_encoder_init(dev,
3569 &aencoder->base,
3570 &amdgpu_dm_encoder_funcs,
3571 DRM_MODE_ENCODER_TMDS,
3572 NULL);
3573
3574 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3575
3576 if (!res)
3577 aencoder->encoder_id = link_index;
3578 else
3579 aencoder->encoder_id = -1;
3580
3581 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3582
3583 return res;
3584}
3585
3ee6b26b
AD		 3586static void manage_dm_interrupts(struct amdgpu_device *adev,
3587 struct amdgpu_crtc *acrtc,
3588 bool enable)
e7b07cee
HW		 3589{
3590 /*
3591 * this is not correct translation but will work as soon as VBLANK
3592 * constant is the same as PFLIP
3593 */
3594 int irq_type =
3595 amdgpu_crtc_idx_to_irq_type(
3596 adev,
3597 acrtc->crtc_id);
3598
3599 if (enable) {
3600 drm_crtc_vblank_on(&acrtc->base);
3601 amdgpu_irq_get(
3602 adev,
3603 &adev->pageflip_irq,
3604 irq_type);
3605 } else {
3606
3607 amdgpu_irq_put(
3608 adev,
3609 &adev->pageflip_irq,
3610 irq_type);
3611 drm_crtc_vblank_off(&acrtc->base);
3612 }
3613}
3614
3ee6b26b
AD		 3615static bool
3616is_scaling_state_different(const struct dm_connector_state *dm_state,
3617 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3618{
3619 if (dm_state->scaling != old_dm_state->scaling)
3620 return true;
3621 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3622 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3623 return true;
3624 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3625 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3626 return true;
b830ebc9
HW		 3627 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3628 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3629 return true;
e7b07cee
HW		 3630 return false;
3631}
3632
3ee6b26b
AD		 3633static void remove_stream(struct amdgpu_device *adev,
3634 struct amdgpu_crtc *acrtc,
3635 struct dc_stream_state *stream)
e7b07cee
HW		 3636{
3637 /* this is the update mode case */
3638 if (adev->dm.freesync_module)
3639 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3640
3641 acrtc->otg_inst = -1;
3642 acrtc->enabled = false;
3643}
3644
7578ecda
AD		 3645static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3646 struct dc_cursor_position *position)
2a8f6ccb
HW		 3647{
3648 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3649 int x, y;
3650 int xorigin = 0, yorigin = 0;
3651
3652 if (!crtc || !plane->state->fb) {
3653 position->enable = false;
3654 position->x = 0;
3655 position->y = 0;
3656 return 0;
3657 }
3658
3659 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3660 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3661 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3662 __func__,
3663 plane->state->crtc_w,
3664 plane->state->crtc_h);
3665 return -EINVAL;
3666 }
3667
3668 x = plane->state->crtc_x;
3669 y = plane->state->crtc_y;
3670 /* avivo cursor are offset into the total surface */
3671 x += crtc->primary->state->src_x >> 16;
3672 y += crtc->primary->state->src_y >> 16;
3673 if (x < 0) {
3674 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3675 x = 0;
3676 }
3677 if (y < 0) {
3678 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3679 y = 0;
3680 }
3681 position->enable = true;
3682 position->x = x;
3683 position->y = y;
3684 position->x_hotspot = xorigin;
3685 position->y_hotspot = yorigin;
3686
3687 return 0;
3688}
3689
3ee6b26b
AD		 3690static void handle_cursor_update(struct drm_plane *plane,
3691 struct drm_plane_state *old_plane_state)
e7b07cee 3692{
2a8f6ccb
HW		 3693 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3694 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3695 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3696 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3697 uint64_t address = afb ? afb->address : 0;
3698 struct dc_cursor_position position;
3699 struct dc_cursor_attributes attributes;
3700 int ret;
3701
e7b07cee
HW		 3702 if (!plane->state->fb && !old_plane_state->fb)
3703 return;
3704
f1ad2f5e 3705 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3706 __func__,
3707 amdgpu_crtc->crtc_id,
3708 plane->state->crtc_w,
3709 plane->state->crtc_h);
2a8f6ccb
HW		 3710
3711 ret = get_cursor_position(plane, crtc, &position);
3712 if (ret)
3713 return;
3714
3715 if (!position.enable) {
3716 /* turn off cursor */
3717 if (crtc_state && crtc_state->stream)
3718 dc_stream_set_cursor_position(crtc_state->stream,
3719 &position);
3720 return;
e7b07cee 3721 }
e7b07cee 3722
2a8f6ccb
HW		 3723 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3724 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3725
3726 attributes.address.high_part = upper_32_bits(address);
3727 attributes.address.low_part = lower_32_bits(address);
3728 attributes.width = plane->state->crtc_w;
3729 attributes.height = plane->state->crtc_h;
3730 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3731 attributes.rotation_angle = 0;
3732 attributes.attribute_flags.value = 0;
3733
3734 attributes.pitch = attributes.width;
3735
886daac9
JZ		 3736 if (crtc_state->stream) {
3737 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3738 &attributes))
3739 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3740
2a8f6ccb
HW		 3741 if (!dc_stream_set_cursor_position(crtc_state->stream,
3742 &position))
3743 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3744 }
2a8f6ccb 3745}
e7b07cee
HW		 3746
3747static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3748{
3749
3750 assert_spin_locked(&acrtc->base.dev->event_lock);
3751 WARN_ON(acrtc->event);
3752
3753 acrtc->event = acrtc->base.state->event;
3754
3755 /* Set the flip status */
3756 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3757
3758 /* Mark this event as consumed */
3759 acrtc->base.state->event = NULL;
3760
3761 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3762 acrtc->crtc_id);
3763}
3764
3765/*
3766 * Executes flip
3767 *
3768 * Waits on all BO's fences and for proper vblank count
3769 */
3ee6b26b
AD		 3770static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3771 struct drm_framebuffer *fb,
bc6828e0
BL		 3772 uint32_t target,
3773 struct dc_state *state)
e7b07cee
HW		 3774{
3775 unsigned long flags;
3776 uint32_t target_vblank;
3777 int r, vpos, hpos;
3778 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3779 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3780 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3781 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3782 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3783 struct dc_flip_addrs addr = { {0} };
3be5262e 3784 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3785 struct dc_surface_update surface_updates[1] = { {0} };
3786 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3787
3788
3789 /* Prepare wait for target vblank early - before the fence-waits */
3790 target_vblank = target - drm_crtc_vblank_count(crtc) +
3791 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3792
b830ebc9 3793 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3794 * explicitly on fences instead
3795 * and in general should be called for
3796 * blocking commit to as per framework helpers
b830ebc9 3797 */
e7b07cee
HW		 3798 r = amdgpu_bo_reserve(abo, true);
3799 if (unlikely(r != 0)) {
3800 DRM_ERROR("failed to reserve buffer before flip\n");
3801 WARN_ON(1);
3802 }
3803
3804 /* Wait for all fences on this FB */
3805 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3806 MAX_SCHEDULE_TIMEOUT) < 0);
3807
3808 amdgpu_bo_unreserve(abo);
3809
3810 /* Wait until we're out of the vertical blank period before the one
3811 * targeted by the flip
3812 */
3813 while ((acrtc->enabled &&
3814 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3815 &vpos, &hpos, NULL, NULL,
3816 &crtc->hwmode)
3817 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3818 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3819 (int)(target_vblank -
3820 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3821 usleep_range(1000, 1100);
3822 }
3823
3824 /* Flip */
3825 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3826 /* update crtc fb */
3827 crtc->primary->fb = fb;
3828
3829 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3830 WARN_ON(!acrtc_state->stream);
3831
3832 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3833 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3834 addr.flip_immediate = async_flip;
3835
3836
3837 if (acrtc->base.state->event)
3838 prepare_flip_isr(acrtc);
3839
3be5262e 3840 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3841 surface_updates->flip_addr = &addr;
3842
3843
bc6828e0
BL		 3844 dc_commit_updates_for_stream(adev->dm.dc,
3845 surface_updates,
3846 1,
3847 acrtc_state->stream,
3848 NULL,
3849 &surface_updates->surface,
3850 state);
e7b07cee
HW		 3851
3852 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3853 __func__,
3854 addr.address.grph.addr.high_part,
3855 addr.address.grph.addr.low_part);
3856
3857
3858 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3859}
3860
3be5262e 3861static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 3862 struct drm_device *dev,
3863 struct amdgpu_display_manager *dm,
3864 struct drm_crtc *pcrtc,
3865 bool *wait_for_vblank)
e7b07cee
HW		 3866{
3867 uint32_t i;
3868 struct drm_plane *plane;
0bc9706d 3869 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 3870 struct dc_stream_state *dc_stream_attach;
3be5262e 3871 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 3872 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 3873 struct drm_crtc_state *new_pcrtc_state =
3874 drm_atomic_get_new_crtc_state(state, pcrtc);
3875 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
bc6828e0 3876 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 3877 int planes_count = 0;
3878 unsigned long flags;
3879
3880 /* update planes when needed */
0bc9706d
LSL		 3881 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3882 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 3883 struct drm_crtc_state *new_crtc_state;
0bc9706d 3884 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 3885 bool pflip_needed;
54d76575 3886 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 3887
3888 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3889 handle_cursor_update(plane, old_plane_state);
3890 continue;
3891 }
3892
f5ba60fe
DD		 3893 if (!fb || !crtc || pcrtc != crtc)
3894 continue;
3895
3896 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
3897 if (!new_crtc_state->active)
e7b07cee
HW		 3898 continue;
3899
3900 pflip_needed = !state->allow_modeset;
3901
3902 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3903 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3904 DRM_ERROR("%s: acrtc %d, already busy\n",
3905 __func__,
3906 acrtc_attach->crtc_id);
b830ebc9 3907 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3908 WARN_ON(1);
3909 }
3910 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3911
3912 if (!pflip_needed) {
54d76575 3913 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 3914
54d76575 3915 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 3916
3917 dc_stream_attach = acrtc_state->stream;
3918 planes_count++;
3919
0bc9706d 3920 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 3921 /* Assume even ONE crtc with immediate flip means
3922 * entire can't wait for VBLANK
3923 * TODO Check if it's correct
3924 */
3925 *wait_for_vblank =
0bc9706d 3926 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 3927 false : true;
3928
3929 /* TODO: Needs rework for multiplane flip */
3930 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3931 drm_crtc_vblank_get(crtc);
3932
3933 amdgpu_dm_do_flip(
3934 crtc,
3935 fb,
bc6828e0
BL		 3936 drm_crtc_vblank_count(crtc) + *wait_for_vblank,
3937 dm_state->context);
e7b07cee
HW		 3938 }
3939
3940 }
3941
3942 if (planes_count) {
3943 unsigned long flags;
3944
0bc9706d 3945 if (new_pcrtc_state->event) {
e7b07cee
HW		 3946
3947 drm_crtc_vblank_get(pcrtc);
3948
3949 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
3950 prepare_flip_isr(acrtc_attach);
3951 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
3952 }
3953
3be5262e
HW		 3954 if (false == dc_commit_planes_to_stream(dm->dc,
3955 plane_states_constructed,
3956 planes_count,
bc6828e0
BL		 3957 dc_stream_attach,
3958 dm_state->context))
3be5262e 3959 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 3960 } else {
3961 /*TODO BUG Here should go disable planes on CRTC. */
3962 }
3963}
3964
3965
7578ecda
AD		 3966static int amdgpu_dm_atomic_commit(struct drm_device *dev,
3967 struct drm_atomic_state *state,
3968 bool nonblock)
e7b07cee
HW		 3969{
3970 struct drm_crtc *crtc;
c2cea706 3971 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 3972 struct amdgpu_device *adev = dev->dev_private;
3973 int i;
3974
3975 /*
3976 * We evade vblanks and pflips on crtc that
3977 * should be changed. We do it here to flush & disable
3978 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
3979 * it will update crtc->dm_crtc_state->stream pointer which is used in
3980 * the ISRs.
3981 */
c2cea706 3982 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 3983 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 3984 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3985
54d76575 3986 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 3987 manage_dm_interrupts(adev, acrtc, false);
3988 }
fc9e9920
S		 3989 /* Add check here for SoC's that support hardware cursor plane, to
3990 * unset legacy_cursor_update */
e7b07cee
HW		 3991
3992 return drm_atomic_helper_commit(dev, state, nonblock);
3993
3994 /*TODO Handle EINTR, reenable IRQ*/
3995}
3996
7578ecda 3997static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 3998{
3999 struct drm_device *dev = state->dev;
4000 struct amdgpu_device *adev = dev->dev_private;
4001 struct amdgpu_display_manager *dm = &adev->dm;
4002 struct dm_atomic_state *dm_state;
4003 uint32_t i, j;
4004 uint32_t new_crtcs_count = 0;
5cc6dcbd 4005 struct drm_crtc *crtc;
0bc9706d 4006 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee 4007 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
0971c40e 4008 struct dc_stream_state *new_stream = NULL;
e7b07cee
HW		 4009 unsigned long flags;
4010 bool wait_for_vblank = true;
4011 struct drm_connector *connector;
c2cea706 4012 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4013 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
e7b07cee
HW		 4014
4015 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4016
4017 dm_state = to_dm_atomic_state(state);
4018
4019 /* update changed items */
0bc9706d 4020 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4021 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4022
54d76575
LSL		 4023 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4024 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4025
f1ad2f5e 4026 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4027 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4028 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4029 "connectors_changed:%d\n",
4030 acrtc->crtc_id,
0bc9706d
LSL		 4031 new_crtc_state->enable,
4032 new_crtc_state->active,
4033 new_crtc_state->planes_changed,
4034 new_crtc_state->mode_changed,
4035 new_crtc_state->active_changed,
4036 new_crtc_state->connectors_changed);
e7b07cee
HW		 4037
4038 /* handles headless hotplug case, updating new_state and
4039 * aconnector as needed
4040 */
4041
54d76575 4042 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4043
f1ad2f5e 4044 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4045
54d76575 4046 if (!dm_new_crtc_state->stream) {
e7b07cee 4047 /*
b830ebc9
HW		 4048 * this could happen because of issues with
4049 * userspace notifications delivery.
4050 * In this case userspace tries to set mode on
4051 * display which is disconnect in fact.
4052 * dc_sink in NULL in this case on aconnector.
4053 * We expect reset mode will come soon.
4054 *
4055 * This can also happen when unplug is done
4056 * during resume sequence ended
4057 *
4058 * In this case, we want to pretend we still
4059 * have a sink to keep the pipe running so that
4060 * hw state is consistent with the sw state
4061 */
f1ad2f5e 4062 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4063 __func__, acrtc->base.base.id);
4064 continue;
4065 }
4066
4067
54d76575
LSL		 4068 if (dm_old_crtc_state->stream)
4069 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4070
4071
4072 /*
4073 * this loop saves set mode crtcs
4074 * we needed to enable vblanks once all
4075 * resources acquired in dc after dc_commit_streams
4076 */
4077
4078 /*TODO move all this into dm_crtc_state, get rid of
4079 * new_crtcs array and use old and new atomic states
4080 * instead
4081 */
4082 new_crtcs[new_crtcs_count] = acrtc;
4083 new_crtcs_count++;
4084
0bc9706d 4085 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
e7b07cee 4086 acrtc->enabled = true;
0bc9706d
LSL		 4087 acrtc->hw_mode = new_crtc_state->mode;
4088 crtc->hwmode = new_crtc_state->mode;
4089 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4090 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4091
4092 /* i.e. reset mode */
54d76575
LSL		 4093 if (dm_old_crtc_state->stream)
4094 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4095 }
4096 } /* for_each_crtc_in_state() */
4097
4098 /*
4099 * Add streams after required streams from new and replaced streams
4100 * are removed from freesync module
4101 */
4102 if (adev->dm.freesync_module) {
4103 for (i = 0; i < new_crtcs_count; i++) {
c84dec2f 4104 struct amdgpu_dm_connector *aconnector = NULL;
b830ebc9 4105
0bc9706d
LSL		 4106 new_crtc_state = drm_atomic_get_new_crtc_state(state,
4107 &new_crtcs[i]->base);
54d76575 4108 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4109
54d76575 4110 new_stream = dm_new_crtc_state->stream;
1daf8c63 4111 aconnector = amdgpu_dm_find_first_crtc_matching_connector(
e7b07cee 4112 state,
9ba29fcb 4113 &new_crtcs[i]->base);
e7b07cee 4114 if (!aconnector) {
f1ad2f5e 4115 DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d "
b830ebc9
HW		 4116 "skipping freesync init\n",
4117 new_crtcs[i]->crtc_id);
e7b07cee
HW		 4118 continue;
4119 }
4120
4121 mod_freesync_add_stream(adev->dm.freesync_module,
4122 new_stream, &aconnector->caps);
4123 }
4124 }
4125
4126 if (dm_state->context)
608ac7bb 4127 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
e7b07cee 4128
0bc9706d 4129 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4130 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4131
54d76575 4132 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4133
54d76575 4134 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4135 const struct dc_stream_status *status =
54d76575 4136 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4137
4138 if (!status)
54d76575 4139 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4140 else
4141 acrtc->otg_inst = status->primary_otg_inst;
4142 }
4143 }
4144
ebdd27e1 4145 /* Handle scaling and underscan changes*/
c2cea706 4146 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4147 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4148 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4149 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4150 struct dc_stream_status *status = NULL;
4151
0bc9706d
LSL		 4152 if (acrtc)
4153 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4154
e7b07cee 4155 /* Skip any modesets/resets */
0bc9706d 4156 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4157 continue;
4158
4159 /* Skip any thing not scale or underscan changes */
54d76575 4160 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4161 continue;
4162
54d76575 4163 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4164
54d76575
LSL		 4165 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4166 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4167
54d76575 4168 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4169 WARN_ON(!status);
3be5262e 4170 WARN_ON(!status->plane_count);
e7b07cee 4171
54d76575 4172 if (!dm_new_crtc_state->stream)
e7b07cee
HW		 4173 continue;
4174
4175 /*TODO How it works with MPO ?*/
3be5262e 4176 if (!dc_commit_planes_to_stream(
e7b07cee 4177 dm->dc,
3be5262e
HW		 4178 status->plane_states,
4179 status->plane_count,
bc6828e0
BL		 4180 dm_new_crtc_state->stream,
4181 dm_state->context))
e7b07cee
HW		 4182 dm_error("%s: Failed to update stream scaling!\n", __func__);
4183 }
4184
4185 for (i = 0; i < new_crtcs_count; i++) {
4186 /*
4187 * loop to enable interrupts on newly arrived crtc
4188 */
4189 struct amdgpu_crtc *acrtc = new_crtcs[i];
b830ebc9 4190
0bc9706d 4191 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
54d76575 4192 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 4193
4194 if (adev->dm.freesync_module)
4195 mod_freesync_notify_mode_change(
54d76575 4196 adev->dm.freesync_module, &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4197
4198 manage_dm_interrupts(adev, acrtc, true);
4199 }
4200
4201 /* update planes when needed per crtc*/
5cc6dcbd 4202 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4203 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4204
54d76575 4205 if (dm_new_crtc_state->stream)
5cc6dcbd 4206 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4207 }
4208
4209
4210 /*
4211 * send vblank event on all events not handled in flip and
4212 * mark consumed event for drm_atomic_helper_commit_hw_done
4213 */
4214 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4215 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4216
0bc9706d
LSL		 4217 if (new_crtc_state->event)
4218 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4219
0bc9706d 4220 new_crtc_state->event = NULL;
e7b07cee
HW		 4221 }
4222 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4223
4224 /* Signal HW programming completion */
4225 drm_atomic_helper_commit_hw_done(state);
4226
4227 if (wait_for_vblank)
4228 drm_atomic_helper_wait_for_vblanks(dev, state);
4229
4230 drm_atomic_helper_cleanup_planes(dev, state);
4231}
4232
4233
4234static int dm_force_atomic_commit(struct drm_connector *connector)
4235{
4236 int ret = 0;
4237 struct drm_device *ddev = connector->dev;
4238 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4239 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4240 struct drm_plane *plane = disconnected_acrtc->base.primary;
4241 struct drm_connector_state *conn_state;
4242 struct drm_crtc_state *crtc_state;
4243 struct drm_plane_state *plane_state;
4244
4245 if (!state)
4246 return -ENOMEM;
4247
4248 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4249
4250 /* Construct an atomic state to restore previous display setting */
4251
4252 /*
4253 * Attach connectors to drm_atomic_state
4254 */
4255 conn_state = drm_atomic_get_connector_state(state, connector);
4256
4257 ret = PTR_ERR_OR_ZERO(conn_state);
4258 if (ret)
4259 goto err;
4260
4261 /* Attach crtc to drm_atomic_state*/
4262 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4263
4264 ret = PTR_ERR_OR_ZERO(crtc_state);
4265 if (ret)
4266 goto err;
4267
4268 /* force a restore */
4269 crtc_state->mode_changed = true;
4270
4271 /* Attach plane to drm_atomic_state */
4272 plane_state = drm_atomic_get_plane_state(state, plane);
4273
4274 ret = PTR_ERR_OR_ZERO(plane_state);
4275 if (ret)
4276 goto err;
4277
4278
4279 /* Call commit internally with the state we just constructed */
4280 ret = drm_atomic_commit(state);
4281 if (!ret)
4282 return 0;
4283
4284err:
4285 DRM_ERROR("Restoring old state failed with %i\n", ret);
4286 drm_atomic_state_put(state);
4287
4288 return ret;
4289}
4290
4291/*
4292 * This functions handle all cases when set mode does not come upon hotplug.
4293 * This include when the same display is unplugged then plugged back into the
4294 * same port and when we are running without usermode desktop manager supprot
4295 */
3ee6b26b
AD		 4296void dm_restore_drm_connector_state(struct drm_device *dev,
4297 struct drm_connector *connector)
e7b07cee 4298{
c84dec2f 4299 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4300 struct amdgpu_crtc *disconnected_acrtc;
4301 struct dm_crtc_state *acrtc_state;
4302
4303 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4304 return;
4305
4306 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4307 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4308
4309 if (!disconnected_acrtc || !acrtc_state->stream)
4310 return;
4311
4312 /*
4313 * If the previous sink is not released and different from the current,
4314 * we deduce we are in a state where we can not rely on usermode call
4315 * to turn on the display, so we do it here
4316 */
4317 if (acrtc_state->stream->sink != aconnector->dc_sink)
4318 dm_force_atomic_commit(&aconnector->base);
4319}
4320
e7b07cee
HW		 4321/*`
4322 * Grabs all modesetting locks to serialize against any blocking commits,
4323 * Waits for completion of all non blocking commits.
4324 */
3ee6b26b
AD		 4325static int do_aquire_global_lock(struct drm_device *dev,
4326 struct drm_atomic_state *state)
e7b07cee
HW		 4327{
4328 struct drm_crtc *crtc;
4329 struct drm_crtc_commit *commit;
4330 long ret;
4331
4332 /* Adding all modeset locks to aquire_ctx will
4333 * ensure that when the framework release it the
4334 * extra locks we are locking here will get released to
4335 */
4336 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4337 if (ret)
4338 return ret;
4339
4340 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4341 spin_lock(&crtc->commit_lock);
4342 commit = list_first_entry_or_null(&crtc->commit_list,
4343 struct drm_crtc_commit, commit_entry);
4344 if (commit)
4345 drm_crtc_commit_get(commit);
4346 spin_unlock(&crtc->commit_lock);
4347
4348 if (!commit)
4349 continue;
4350
4351 /* Make sure all pending HW programming completed and
4352 * page flips done
4353 */
4354 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4355
4356 if (ret > 0)
4357 ret = wait_for_completion_interruptible_timeout(
4358 &commit->flip_done, 10*HZ);
4359
4360 if (ret == 0)
4361 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4362 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4363
4364 drm_crtc_commit_put(commit);
4365 }
4366
4367 return ret < 0 ? ret : 0;
4368}
4369
3ee6b26b
AD		 4370static int dm_update_crtcs_state(struct dc *dc,
4371 struct drm_atomic_state *state,
4372 bool enable,
4373 bool *lock_and_validation_needed)
e7b07cee 4374{
e7b07cee 4375 struct drm_crtc *crtc;
c2cea706 4376 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4377 int i;
54d76575 4378 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4379 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4380 struct dc_stream_state *new_stream;
62f55537 4381 int ret = 0;
d4d4a645 4382
62f55537
AG		 4383 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4384 /* update changed items */
c2cea706 4385 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4386 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4387 struct amdgpu_dm_connector *aconnector = NULL;
c2cea706 4388 struct drm_connector_state *new_con_state = NULL;
62f55537 4389 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4390
9635b754
DS		 4391 new_stream = NULL;
4392
54d76575
LSL		 4393 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4394 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4395 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4396
1daf8c63 4397 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4398
62f55537 4399 /* TODO This hack should go away */
f4ac176e
JZ		 4400 if (aconnector && enable) {
4401 // Make sure fake sink is created in plug-in scenario
c2cea706
LSL		 4402 new_con_state = drm_atomic_get_connector_state(state,
4403 &aconnector->base);
19f89e23 4404
c2cea706
LSL		 4405 if (IS_ERR(new_con_state)) {
4406 ret = PTR_ERR_OR_ZERO(new_con_state);
62f55537
AG		 4407 break;
4408 }
19f89e23 4409
c2cea706 4410 dm_conn_state = to_dm_connector_state(new_con_state);
19f89e23 4411
62f55537 4412 new_stream = create_stream_for_sink(aconnector,
c2cea706 4413 &new_crtc_state->mode,
62f55537 4414 dm_conn_state);
19f89e23 4415
62f55537
AG		 4416 /*
4417 * we can have no stream on ACTION_SET if a display
4418 * was disconnected during S3, in this case it not and
4419 * error, the OS will be updated after detection, and
4420 * do the right thing on next atomic commit
4421 */
19f89e23 4422
62f55537 4423 if (!new_stream) {
f1ad2f5e 4424 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4425 __func__, acrtc->base.base.id);
4426 break;
19f89e23 4427 }
62f55537 4428 }
19f89e23 4429
9a5d9c48
LSL		 4430 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4431 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
19f89e23 4432
c2cea706 4433 new_crtc_state->mode_changed = false;
e7b07cee 4434
c2cea706 4435 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9a5d9c48 4436 new_crtc_state->mode_changed);
62f55537 4437 }
b830ebc9 4438
e7b07cee 4439
c2cea706 4440 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4441 goto next_crtc;
e7b07cee 4442
f1ad2f5e 4443 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4444 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4445 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4446 "connectors_changed:%d\n",
4447 acrtc->crtc_id,
c2cea706
LSL		 4448 new_crtc_state->enable,
4449 new_crtc_state->active,
4450 new_crtc_state->planes_changed,
4451 new_crtc_state->mode_changed,
4452 new_crtc_state->active_changed,
4453 new_crtc_state->connectors_changed);
e7b07cee 4454
62f55537
AG		 4455 /* Remove stream for any changed/disabled CRTC */
4456 if (!enable) {
4457
54d76575 4458 if (!dm_old_crtc_state->stream)
9635b754 4459 goto next_crtc;
62f55537 4460
f1ad2f5e 4461 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4462 crtc->base.id);
e7b07cee 4463
1dc90497 4464 /* i.e. reset mode */
62c933f9 4465 if (dc_remove_stream_from_ctx(
62f55537
AG		 4466 dc,
4467 dm_state->context,
62c933f9 4468 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4469 ret = -EINVAL;
9635b754 4470 goto fail;
62f55537
AG		 4471 }
4472
54d76575
LSL		 4473 dc_stream_release(dm_old_crtc_state->stream);
4474 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4475
4476 *lock_and_validation_needed = true;
4477
4478 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4479 /*
4480 * Quick fix to prevent NULL pointer on new_stream when
4481 * added MST connectors not found in existing crtc_state in the chained mode
4482 * TODO: need to dig out the root cause of that
4483 */
4484 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4485 goto next_crtc;
62f55537 4486
c2cea706 4487 if (modereset_required(new_crtc_state))
9635b754 4488 goto next_crtc;
62f55537 4489
c2cea706 4490 if (modeset_required(new_crtc_state, new_stream,
54d76575 4491 dm_old_crtc_state->stream)) {
62f55537 4492
54d76575 4493 WARN_ON(dm_new_crtc_state->stream);
62f55537 4494
54d76575 4495 dm_new_crtc_state->stream = new_stream;
62f55537
AG		 4496 dc_stream_retain(new_stream);
4497
f1ad2f5e 4498 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4499 crtc->base.id);
1dc90497 4500
13ab1b44 4501 if (dc_add_stream_to_ctx(
1dc90497
AG		 4502 dc,
4503 dm_state->context,
13ab1b44 4504 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4505 ret = -EINVAL;
9635b754 4506 goto fail;
1dc90497
AG		 4507 }
4508
62f55537 4509 *lock_and_validation_needed = true;
9b690ef3 4510 }
62f55537 4511 }
9b690ef3 4512
9635b754 4513next_crtc:
62f55537
AG		 4514 /* Release extra reference */
4515 if (new_stream)
4516 dc_stream_release(new_stream);
4517 }
e7b07cee 4518
62f55537 4519 return ret;
9635b754
DS		 4520
4521fail:
4522 if (new_stream)
4523 dc_stream_release(new_stream);
4524 return ret;
62f55537 4525}
9b690ef3 4526
3ee6b26b
AD		 4527static int dm_update_planes_state(struct dc *dc,
4528 struct drm_atomic_state *state,
4529 bool enable,
4530 bool *lock_and_validation_needed)
62f55537
AG		 4531{
4532 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4533 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4534 struct drm_plane *plane;
4535 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4536 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4537 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4538 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4539 int i ;
4540 /* TODO return page_flip_needed() function */
4541 bool pflip_needed = !state->allow_modeset;
4542 int ret = 0;
e7b07cee 4543
62f55537
AG		 4544 if (pflip_needed)
4545 return ret;
9b690ef3 4546
62f55537
AG		 4547 /* Add new planes */
4548 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4549 new_plane_crtc = new_plane_state->crtc;
4550 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4551 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4552 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4553
4554 /*TODO Implement atomic check for cursor plane */
4555 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4556 continue;
9b690ef3 4557
62f55537
AG		 4558 /* Remove any changed/removed planes */
4559 if (!enable) {
a7b06724 4560
62f55537
AG		 4561 if (!old_plane_crtc)
4562 continue;
4563
0bc9706d
LSL		 4564 old_crtc_state = drm_atomic_get_old_crtc_state(
4565 state, old_plane_crtc);
54d76575 4566 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4567
54d76575 4568 if (!dm_old_crtc_state->stream)
62f55537
AG		 4569 continue;
4570
f1ad2f5e 4571 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4572 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4573
62f55537
AG		 4574 if (!dc_remove_plane_from_context(
4575 dc,
54d76575
LSL		 4576 dm_old_crtc_state->stream,
4577 dm_old_plane_state->dc_state,
62f55537
AG		 4578 dm_state->context)) {
4579
4580 ret = EINVAL;
4581 return ret;
e7b07cee
HW		 4582 }
4583
9b690ef3 4584
54d76575
LSL		 4585 dc_plane_state_release(dm_old_plane_state->dc_state);
4586 dm_new_plane_state->dc_state = NULL;
1dc90497 4587
62f55537 4588 *lock_and_validation_needed = true;
1dc90497 4589
62f55537 4590 } else { /* Add new planes */
1dc90497 4591
62f55537
AG		 4592 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4593 continue;
e7b07cee 4594
62f55537
AG		 4595 if (!new_plane_crtc)
4596 continue;
e7b07cee 4597
62f55537 4598 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4599 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4600
54d76575 4601 if (!dm_new_crtc_state->stream)
62f55537
AG		 4602 continue;
4603
4604
54d76575 4605 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4606
54d76575 4607 dm_new_plane_state->dc_state = dc_create_plane_state(dc);
62f55537 4608
f1ad2f5e 4609 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
62f55537
AG		 4610 plane->base.id, new_plane_crtc->base.id);
4611
54d76575 4612 if (!dm_new_plane_state->dc_state) {
62f55537
AG		 4613 ret = -EINVAL;
4614 return ret;
4615 }
4616
4617 ret = fill_plane_attributes(
4618 new_plane_crtc->dev->dev_private,
54d76575 4619 dm_new_plane_state->dc_state,
62f55537
AG		 4620 new_plane_state,
4621 new_crtc_state,
4622 false);
4623 if (ret)
4624 return ret;
4625
4626
4627 if (!dc_add_plane_to_context(
4628 dc,
54d76575
LSL		 4629 dm_new_crtc_state->stream,
4630 dm_new_plane_state->dc_state,
62f55537
AG		 4631 dm_state->context)) {
4632
4633 ret = -EINVAL;
4634 return ret;
e7b07cee 4635 }
62f55537
AG		 4636
4637 *lock_and_validation_needed = true;
e7b07cee 4638 }
62f55537 4639 }
e7b07cee
HW		 4640
4641
62f55537
AG		 4642 return ret;
4643}
4644
7578ecda
AD		 4645static int amdgpu_dm_atomic_check(struct drm_device *dev,
4646 struct drm_atomic_state *state)
62f55537
AG		 4647{
4648 int i;
4649 int ret;
4650 struct amdgpu_device *adev = dev->dev_private;
4651 struct dc *dc = adev->dm.dc;
4652 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4653 struct drm_connector *connector;
c2cea706 4654 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4655 struct drm_crtc *crtc;
fc9e9920 4656 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee 4657
62f55537
AG		 4658 /*
4659 * This bool will be set for true for any modeset/reset
4660 * or plane update which implies non fast surface update.
4661 */
4662 bool lock_and_validation_needed = false;
4663
4664 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 4665 if (ret)
4666 goto fail;
62f55537
AG		 4667
4668 /*
fc9e9920
S		 4669 * legacy_cursor_update should be made false for SoC's having
4670 * a dedicated hardware plane for cursor in amdgpu_dm_atomic_commit(),
4671 * otherwise for software cursor plane,
4672 * we should not add it to list of affected planes.
62f55537 4673 */
fc9e9920
S		 4674 if (state->legacy_cursor_update) {
4675 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4676 if (new_crtc_state->color_mgmt_changed) {
4677 ret = drm_atomic_add_affected_planes(state, crtc);
4678 if (ret)
4679 goto fail;
4680 }
4681 }
4682 } else {
4683 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7bef1af3
S		 4684 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
4685 continue;
4686
fc9e9920
S		 4687 if (!new_crtc_state->enable)
4688 continue;
4689
4690 ret = drm_atomic_add_affected_connectors(state, crtc);
4691 if (ret)
4692 return ret;
4693
e7b07cee
HW		 4694 ret = drm_atomic_add_affected_planes(state, crtc);
4695 if (ret)
4696 goto fail;
4697 }
4698 }
4699
62f55537
AG		 4700 dm_state->context = dc_create_state();
4701 ASSERT(dm_state->context);
f36cc577 4702 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4703
4704 /* Remove exiting planes if they are modified */
4705 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4706 if (ret) {
4707 goto fail;
4708 }
4709
4710 /* Disable all crtcs which require disable */
4711 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4712 if (ret) {
4713 goto fail;
4714 }
4715
4716 /* Enable all crtcs which require enable */
4717 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4718 if (ret) {
4719 goto fail;
4720 }
4721
4722 /* Add new/modified planes */
4723 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4724 if (ret) {
4725 goto fail;
4726 }
4727
b349f76e
ES		 4728 /* Run this here since we want to validate the streams we created */
4729 ret = drm_atomic_helper_check_planes(dev, state);
4730 if (ret)
4731 goto fail;
62f55537 4732
ebdd27e1 4733 /* Check scaling and underscan changes*/
e7b07cee
HW		 4734 /*TODO Removed scaling changes validation due to inability to commit
4735 * new stream into context w\o causing full reset. Need to
4736 * decide how to handle.
4737 */
c2cea706 4738 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4739 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4740 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4741 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4742
4743 /* Skip any modesets/resets */
0bc9706d
LSL		 4744 if (!acrtc || drm_atomic_crtc_needs_modeset(
4745 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 4746 continue;
4747
b830ebc9 4748 /* Skip any thing not scale or underscan changes */
54d76575 4749 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4750 continue;
4751
4752 lock_and_validation_needed = true;
4753 }
4754
e7b07cee
HW		 4755 /*
4756 * For full updates case when
4757 * removing/adding/updating streams on once CRTC while flipping
4758 * on another CRTC,
4759 * acquiring global lock will guarantee that any such full
4760 * update commit
4761 * will wait for completion of any outstanding flip using DRMs
4762 * synchronization events.
4763 */
4764
4765 if (lock_and_validation_needed) {
4766
4767 ret = do_aquire_global_lock(dev, state);
4768 if (ret)
4769 goto fail;
1dc90497 4770
e750d56d 4771 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 4772 ret = -EINVAL;
4773 goto fail;
4774 }
4775 }
4776
4777 /* Must be success */
4778 WARN_ON(ret);
4779 return ret;
4780
4781fail:
4782 if (ret == -EDEADLK)
01e28f9c 4783 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 4784 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 4785 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 4786 else
01e28f9c 4787 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 4788
4789 return ret;
4790}
4791
3ee6b26b
AD		 4792static bool is_dp_capable_without_timing_msa(struct dc *dc,
4793 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 4794{
4795 uint8_t dpcd_data;
4796 bool capable = false;
4797
c84dec2f 4798 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 4799 dm_helpers_dp_read_dpcd(
4800 NULL,
c84dec2f 4801 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 4802 DP_DOWN_STREAM_PORT_COUNT,
4803 &dpcd_data,
4804 sizeof(dpcd_data))) {
4805 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4806 }
4807
4808 return capable;
4809}
3ee6b26b
AD		 4810void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4811 struct edid *edid)
e7b07cee
HW		 4812{
4813 int i;
4814 uint64_t val_capable;
4815 bool edid_check_required;
4816 struct detailed_timing *timing;
4817 struct detailed_non_pixel *data;
4818 struct detailed_data_monitor_range *range;
c84dec2f
HW		 4819 struct amdgpu_dm_connector *amdgpu_dm_connector =
4820 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4821
4822 struct drm_device *dev = connector->dev;
4823 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4824
e7b07cee 4825 edid_check_required = false;
c84dec2f 4826 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 4827 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4828 return;
4829 }
4830 if (!adev->dm.freesync_module)
4831 return;
4832 /*
4833 * if edid non zero restrict freesync only for dp and edp
4834 */
4835 if (edid) {
c84dec2f
HW		 4836 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4837 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 4838 edid_check_required = is_dp_capable_without_timing_msa(
4839 adev->dm.dc,
c84dec2f 4840 amdgpu_dm_connector);
e7b07cee
HW		 4841 }
4842 }
4843 val_capable = 0;
4844 if (edid_check_required == true && (edid->version > 1 ||
4845 (edid->version == 1 && edid->revision > 1))) {
4846 for (i = 0; i < 4; i++) {
4847
4848 timing = &edid->detailed_timings[i];
4849 data = &timing->data.other_data;
4850 range = &data->data.range;
4851 /*
4852 * Check if monitor has continuous frequency mode
4853 */
4854 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4855 continue;
4856 /*
4857 * Check for flag range limits only. If flag == 1 then
4858 * no additional timing information provided.
4859 * Default GTF, GTF Secondary curve and CVT are not
4860 * supported
4861 */
4862 if (range->flags != 1)
4863 continue;
4864
c84dec2f
HW		 4865 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
4866 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
4867 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 4868 range->pixel_clock_mhz * 10;
4869 break;
4870 }
4871
c84dec2f
HW		 4872 if (amdgpu_dm_connector->max_vfreq -
4873 amdgpu_dm_connector->min_vfreq > 10) {
4874 amdgpu_dm_connector->caps.supported = true;
4875 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
4876 amdgpu_dm_connector->min_vfreq * 1000000;
4877 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
4878 amdgpu_dm_connector->max_vfreq * 1000000;
e7b07cee
HW		 4879 val_capable = 1;
4880 }
4881 }
4882
4883 /*
4884 * TODO figure out how to notify user-mode or DRM of freesync caps
4885 * once we figure out how to deal with freesync in an upstreamable
4886 * fashion
4887 */
4888
4889}
4890
3ee6b26b 4891void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 4892{
4893 /*
4894 * TODO fill in once we figure out how to deal with freesync in
4895 * an upstreamable fashion
4896 */
4897}
Linux 6.x block layer and io_uring tree(s)