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drm/amd/display: Add plane capabilities to dc_caps
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
1dc90497 31#include "dc/inc/core_types.h"
4562236b
HW		 32
33#include "vid.h"
34#include "amdgpu.h"
a49dcb88 35#include "amdgpu_display.h"
a94d5569 36#include "amdgpu_ucode.h"
4562236b
HW		 37#include "atom.h"
38#include "amdgpu_dm.h"
e7b07cee 39#include "amdgpu_pm.h"
4562236b
HW		 40
41#include "amd_shared.h"
42#include "amdgpu_dm_irq.h"
43#include "dm_helpers.h"
e7b07cee 44#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 45#if defined(CONFIG_DEBUG_FS)
46#include "amdgpu_dm_debugfs.h"
47#endif
4562236b
HW		 48
49#include "ivsrcid/ivsrcid_vislands30.h"
50
51#include <linux/module.h>
52#include <linux/moduleparam.h>
53#include <linux/version.h>
e7b07cee 54#include <linux/types.h>
97028037 55#include <linux/pm_runtime.h>
a94d5569 56#include <linux/firmware.h>
4562236b 57
e7b07cee 58#include <drm/drmP.h>
4562236b 59#include <drm/drm_atomic.h>
674e78ac 60#include <drm/drm_atomic_uapi.h>
4562236b
HW		 61#include <drm/drm_atomic_helper.h>
62#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 63#include <drm/drm_fb_helper.h>
64#include <drm/drm_edid.h>
4562236b 65
ff5ef992
AD		 66#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
67#include "ivsrcid/irqsrcs_dcn_1_0.h"
68
ad941f7a
FX		 69#include "dcn/dcn_1_0_offset.h"
70#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 71#include "soc15_hw_ip.h"
72#include "vega10_ip_offset.h"
ff5ef992
AD		 73
74#include "soc15_common.h"
75#endif
76
e7b07cee 77#include "modules/inc/mod_freesync.h"
bbf854dc 78#include "modules/power/power_helpers.h"
ecd0136b 79#include "modules/inc/mod_info_packet.h"
e7b07cee 80
a94d5569
DF		 81#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
82MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 83
b8592b48
LL		 84/**
85 * DOC: overview
86 *
87 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
88 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
89 * requests into DC requests, and DC responses into DRM responses.
90 *
91 * The root control structure is &struct amdgpu_display_manager.
92 */
93
7578ecda
AD		 94/* basic init/fini API */
95static int amdgpu_dm_init(struct amdgpu_device *adev);
96static void amdgpu_dm_fini(struct amdgpu_device *adev);
97
1f6010a9
DF		 98/*
99 * initializes drm_device display related structures, based on the information
7578ecda
AD		 100 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
101 * drm_encoder, drm_mode_config
102 *
103 * Returns 0 on success
104 */
105static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
106/* removes and deallocates the drm structures, created by the above function */
107static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
108
109static void
110amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
111
112static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 113 struct drm_plane *plane,
7578ecda
AD		 114 unsigned long possible_crtcs);
115static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
116 struct drm_plane *plane,
117 uint32_t link_index);
118static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
119 struct amdgpu_dm_connector *amdgpu_dm_connector,
120 uint32_t link_index,
121 struct amdgpu_encoder *amdgpu_encoder);
122static int amdgpu_dm_encoder_init(struct drm_device *dev,
123 struct amdgpu_encoder *aencoder,
124 uint32_t link_index);
125
126static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
127
128static int amdgpu_dm_atomic_commit(struct drm_device *dev,
129 struct drm_atomic_state *state,
130 bool nonblock);
131
132static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
133
134static int amdgpu_dm_atomic_check(struct drm_device *dev,
135 struct drm_atomic_state *state);
136
674e78ac
NK		 137static void handle_cursor_update(struct drm_plane *plane,
138 struct drm_plane_state *old_plane_state);
7578ecda
AD		 139
140
e7b07cee 141
e04a6123 142static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 143 DRM_PLANE_TYPE_PRIMARY,
144 DRM_PLANE_TYPE_PRIMARY,
145 DRM_PLANE_TYPE_PRIMARY,
146 DRM_PLANE_TYPE_PRIMARY,
147 DRM_PLANE_TYPE_PRIMARY,
148 DRM_PLANE_TYPE_PRIMARY,
149};
150
e04a6123 151static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 152 DRM_PLANE_TYPE_PRIMARY,
153 DRM_PLANE_TYPE_PRIMARY,
154 DRM_PLANE_TYPE_PRIMARY,
155 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
156};
157
e04a6123 158static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 159 DRM_PLANE_TYPE_PRIMARY,
160 DRM_PLANE_TYPE_PRIMARY,
161 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
162};
163
4562236b
HW		 164/*
165 * dm_vblank_get_counter
166 *
167 * @brief
168 * Get counter for number of vertical blanks
169 *
170 * @param
171 * struct amdgpu_device *adev - [in] desired amdgpu device
172 * int disp_idx - [in] which CRTC to get the counter from
173 *
174 * @return
175 * Counter for vertical blanks
176 */
177static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
178{
179 if (crtc >= adev->mode_info.num_crtc)
180 return 0;
181 else {
182 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 183 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
184 acrtc->base.state);
4562236b 185
da5c47f6
AG		 186
187 if (acrtc_state->stream == NULL) {
0971c40e
HW		 188 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
189 crtc);
4562236b
HW		 190 return 0;
191 }
192
da5c47f6 193 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 194 }
195}
196
197static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 198 u32 *vbl, u32 *position)
4562236b 199{
81c50963
ST		 200 uint32_t v_blank_start, v_blank_end, h_position, v_position;
201
4562236b
HW		 202 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
203 return -EINVAL;
204 else {
205 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 206 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
207 acrtc->base.state);
4562236b 208
da5c47f6 209 if (acrtc_state->stream == NULL) {
0971c40e
HW		 210 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
211 crtc);
4562236b
HW		 212 return 0;
213 }
214
81c50963
ST		 215 /*
216 * TODO rework base driver to use values directly.
217 * for now parse it back into reg-format
218 */
da5c47f6 219 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 220 &v_blank_start,
221 &v_blank_end,
222 &h_position,
223 &v_position);
224
e806208d
AG		 225 *position = v_position | (h_position << 16);
226 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 227 }
228
229 return 0;
230}
231
232static bool dm_is_idle(void *handle)
233{
234 /* XXX todo */
235 return true;
236}
237
238static int dm_wait_for_idle(void *handle)
239{
240 /* XXX todo */
241 return 0;
242}
243
244static bool dm_check_soft_reset(void *handle)
245{
246 return false;
247}
248
249static int dm_soft_reset(void *handle)
250{
251 /* XXX todo */
252 return 0;
253}
254
3ee6b26b
AD		 255static struct amdgpu_crtc *
256get_crtc_by_otg_inst(struct amdgpu_device *adev,
257 int otg_inst)
4562236b
HW		 258{
259 struct drm_device *dev = adev->ddev;
260 struct drm_crtc *crtc;
261 struct amdgpu_crtc *amdgpu_crtc;
262
4562236b
HW		 263 if (otg_inst == -1) {
264 WARN_ON(1);
265 return adev->mode_info.crtcs[0];
266 }
267
268 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
269 amdgpu_crtc = to_amdgpu_crtc(crtc);
270
271 if (amdgpu_crtc->otg_inst == otg_inst)
272 return amdgpu_crtc;
273 }
274
275 return NULL;
276}
277
278static void dm_pflip_high_irq(void *interrupt_params)
279{
4562236b
HW		 280 struct amdgpu_crtc *amdgpu_crtc;
281 struct common_irq_params *irq_params = interrupt_params;
282 struct amdgpu_device *adev = irq_params->adev;
283 unsigned long flags;
284
285 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
286
287 /* IRQ could occur when in initial stage */
1f6010a9 288 /* TODO work and BO cleanup */
4562236b
HW		 289 if (amdgpu_crtc == NULL) {
290 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
291 return;
292 }
293
294 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 295
296 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
297 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
298 amdgpu_crtc->pflip_status,
299 AMDGPU_FLIP_SUBMITTED,
300 amdgpu_crtc->crtc_id,
301 amdgpu_crtc);
302 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
303 return;
304 }
305
7b19bba5
MK		 306 /* Update to correct count(s) if racing with vblank irq */
307 amdgpu_crtc->last_flip_vblank = drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
4562236b 308
1f6010a9 309 /* wake up userspace */
1159898a 310 if (amdgpu_crtc->event) {
54f5499a 311 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 312
54f5499a
AG		 313 /* page flip completed. clean up */
314 amdgpu_crtc->event = NULL;
1159898a 315
54f5499a
AG		 316 } else
317 WARN_ON(1);
4562236b 318
54f5499a 319 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 320 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
321
54f5499a
AG		 322 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
323 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 324
325 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 326}
327
328static void dm_crtc_high_irq(void *interrupt_params)
329{
330 struct common_irq_params *irq_params = interrupt_params;
331 struct amdgpu_device *adev = irq_params->adev;
4562236b 332 struct amdgpu_crtc *acrtc;
180db303 333 struct dm_crtc_state *acrtc_state;
4562236b 334
b57de80a 335 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 336
e5d0170e
LSL		 337 if (acrtc) {
338 drm_crtc_handle_vblank(&acrtc->base);
339 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
180db303
NK		 340
341 acrtc_state = to_dm_crtc_state(acrtc->base.state);
342
343 if (acrtc_state->stream &&
344 acrtc_state->vrr_params.supported &&
345 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
346 mod_freesync_handle_v_update(
347 adev->dm.freesync_module,
348 acrtc_state->stream,
349 &acrtc_state->vrr_params);
350
351 dc_stream_adjust_vmin_vmax(
352 adev->dm.dc,
353 acrtc_state->stream,
354 &acrtc_state->vrr_params.adjust);
355 }
e5d0170e 356 }
4562236b
HW		 357}
358
359static int dm_set_clockgating_state(void *handle,
360 enum amd_clockgating_state state)
361{
362 return 0;
363}
364
365static int dm_set_powergating_state(void *handle,
366 enum amd_powergating_state state)
367{
368 return 0;
369}
370
371/* Prototypes of private functions */
372static int dm_early_init(void* handle);
373
a32e24b4 374/* Allocate memory for FBC compressed data */
3e332d3a 375static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 376{
3e332d3a
RL		 377 struct drm_device *dev = connector->dev;
378 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 379 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 380 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
381 struct drm_display_mode *mode;
42e67c3b
RL		 382 unsigned long max_size = 0;
383
384 if (adev->dm.dc->fbc_compressor == NULL)
385 return;
a32e24b4 386
3e332d3a 387 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 388 return;
389
3e332d3a
RL		 390 if (compressor->bo_ptr)
391 return;
42e67c3b 392
42e67c3b 393
3e332d3a
RL		 394 list_for_each_entry(mode, &connector->modes, head) {
395 if (max_size < mode->htotal * mode->vtotal)
396 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 397 }
398
399 if (max_size) {
400 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 401 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 402 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 403
404 if (r)
42e67c3b
RL		 405 DRM_ERROR("DM: Failed to initialize FBC\n");
406 else {
407 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
408 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
409 }
410
a32e24b4
RL		 411 }
412
413}
a32e24b4 414
7578ecda 415static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 416{
417 struct dc_init_data init_data;
418 adev->dm.ddev = adev->ddev;
419 adev->dm.adev = adev;
420
4562236b
HW		 421 /* Zero all the fields */
422 memset(&init_data, 0, sizeof(init_data));
423
674e78ac
NK		 424 mutex_init(&adev->dm.dc_lock);
425
4562236b
HW		 426 if(amdgpu_dm_irq_init(adev)) {
427 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
428 goto error;
429 }
430
431 init_data.asic_id.chip_family = adev->family;
432
433 init_data.asic_id.pci_revision_id = adev->rev_id;
434 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
435
770d13b1 436 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 437 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
438 init_data.asic_id.atombios_base_address =
439 adev->mode_info.atom_context->bios;
440
441 init_data.driver = adev;
442
443 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
444
445 if (!adev->dm.cgs_device) {
446 DRM_ERROR("amdgpu: failed to create cgs device.\n");
447 goto error;
448 }
449
450 init_data.cgs_device = adev->dm.cgs_device;
451
4562236b
HW		 452 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
453
6e227308
HW		 454 /*
455 * TODO debug why this doesn't work on Raven
456 */
457 if (adev->flags & AMD_IS_APU &&
458 adev->asic_type >= CHIP_CARRIZO &&
459 adev->asic_type < CHIP_RAVEN)
460 init_data.flags.gpu_vm_support = true;
461
04b94af4
AD		 462 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
463 init_data.flags.fbc_support = true;
464
4562236b
HW		 465 /* Display Core create. */
466 adev->dm.dc = dc_create(&init_data);
467
423788c7 468 if (adev->dm.dc) {
76121231 469 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 470 } else {
76121231 471 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 472 goto error;
473 }
4562236b 474
4562236b
HW		 475 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
476 if (!adev->dm.freesync_module) {
477 DRM_ERROR(
478 "amdgpu: failed to initialize freesync_module.\n");
479 } else
f1ad2f5e 480 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 481 adev->dm.freesync_module);
482
e277adc5
LSL		 483 amdgpu_dm_init_color_mod();
484
4562236b
HW		 485 if (amdgpu_dm_initialize_drm_device(adev)) {
486 DRM_ERROR(
487 "amdgpu: failed to initialize sw for display support.\n");
488 goto error;
489 }
490
491 /* Update the actual used number of crtc */
492 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
493
494 /* TODO: Add_display_info? */
495
496 /* TODO use dynamic cursor width */
ce75805e
AG		 497 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
498 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 499
500 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
501 DRM_ERROR(
502 "amdgpu: failed to initialize sw for display support.\n");
503 goto error;
504 }
505
e498eb71
NK		 506#if defined(CONFIG_DEBUG_FS)
507 if (dtn_debugfs_init(adev))
508 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
509#endif
510
f1ad2f5e 511 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 512
513 return 0;
514error:
515 amdgpu_dm_fini(adev);
516
59d0f396 517 return -EINVAL;
4562236b
HW		 518}
519
7578ecda 520static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 521{
522 amdgpu_dm_destroy_drm_device(&adev->dm);
523 /*
524 * TODO: pageflip, vlank interrupt
525 *
526 * amdgpu_dm_irq_fini(adev);
527 */
528
529 if (adev->dm.cgs_device) {
530 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
531 adev->dm.cgs_device = NULL;
532 }
533 if (adev->dm.freesync_module) {
534 mod_freesync_destroy(adev->dm.freesync_module);
535 adev->dm.freesync_module = NULL;
536 }
537 /* DC Destroy TODO: Replace destroy DAL */
21de3396 538 if (adev->dm.dc)
4562236b 539 dc_destroy(&adev->dm.dc);
674e78ac
NK		 540
541 mutex_destroy(&adev->dm.dc_lock);
542
4562236b
HW		 543 return;
544}
545
a94d5569 546static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 547{
a94d5569
DF		 548 const char *fw_name_dmcu;
549 int r;
550 const struct dmcu_firmware_header_v1_0 *hdr;
551
552 switch(adev->asic_type) {
553 case CHIP_BONAIRE:
554 case CHIP_HAWAII:
555 case CHIP_KAVERI:
556 case CHIP_KABINI:
557 case CHIP_MULLINS:
558 case CHIP_TONGA:
559 case CHIP_FIJI:
560 case CHIP_CARRIZO:
561 case CHIP_STONEY:
562 case CHIP_POLARIS11:
563 case CHIP_POLARIS10:
564 case CHIP_POLARIS12:
565 case CHIP_VEGAM:
566 case CHIP_VEGA10:
567 case CHIP_VEGA12:
568 case CHIP_VEGA20:
569 return 0;
570 case CHIP_RAVEN:
571 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
572 break;
573 default:
574 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 575 return -EINVAL;
a94d5569
DF		 576 }
577
578 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
579 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
580 return 0;
581 }
582
583 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
584 if (r == -ENOENT) {
585 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
586 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
587 adev->dm.fw_dmcu = NULL;
588 return 0;
589 }
590 if (r) {
591 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
592 fw_name_dmcu);
593 return r;
594 }
595
596 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
597 if (r) {
598 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
599 fw_name_dmcu);
600 release_firmware(adev->dm.fw_dmcu);
601 adev->dm.fw_dmcu = NULL;
602 return r;
603 }
604
605 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
606 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
607 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
608 adev->firmware.fw_size +=
609 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
610
611 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
612 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
613 adev->firmware.fw_size +=
614 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
615
ee6e89c0
DF		 616 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
617
a94d5569
DF		 618 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
619
4562236b
HW		 620 return 0;
621}
622
a94d5569
DF		 623static int dm_sw_init(void *handle)
624{
625 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
626
627 return load_dmcu_fw(adev);
628}
629
4562236b
HW		 630static int dm_sw_fini(void *handle)
631{
a94d5569
DF		 632 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
633
634 if(adev->dm.fw_dmcu) {
635 release_firmware(adev->dm.fw_dmcu);
636 adev->dm.fw_dmcu = NULL;
637 }
638
4562236b
HW		 639 return 0;
640}
641
7abcf6b5 642static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 643{
c84dec2f 644 struct amdgpu_dm_connector *aconnector;
4562236b 645 struct drm_connector *connector;
7abcf6b5 646 int ret = 0;
4562236b
HW		 647
648 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
649
650 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 651 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 652 if (aconnector->dc_link->type == dc_connection_mst_branch &&
653 aconnector->mst_mgr.aux) {
f1ad2f5e 654 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 655 aconnector, aconnector->base.base.id);
656
657 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
658 if (ret < 0) {
659 DRM_ERROR("DM_MST: Failed to start MST\n");
660 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
661 return ret;
4562236b 662 }
7abcf6b5 663 }
4562236b
HW		 664 }
665
666 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 667 return ret;
668}
669
670static int dm_late_init(void *handle)
671{
42e67c3b 672 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 673
bbf854dc
DF		 674 struct dmcu_iram_parameters params;
675 unsigned int linear_lut[16];
676 int i;
677 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
678 bool ret;
679
680 for (i = 0; i < 16; i++)
681 linear_lut[i] = 0xFFFF * i / 15;
682
683 params.set = 0;
684 params.backlight_ramping_start = 0xCCCC;
685 params.backlight_ramping_reduction = 0xCCCCCCCC;
686 params.backlight_lut_array_size = 16;
687 params.backlight_lut_array = linear_lut;
688
689 ret = dmcu_load_iram(dmcu, params);
690
691 if (!ret)
692 return -EINVAL;
693
42e67c3b 694 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 695}
696
697static void s3_handle_mst(struct drm_device *dev, bool suspend)
698{
c84dec2f 699 struct amdgpu_dm_connector *aconnector;
4562236b 700 struct drm_connector *connector;
fe7553be
LP		 701 struct drm_dp_mst_topology_mgr *mgr;
702 int ret;
703 bool need_hotplug = false;
4562236b
HW		 704
705 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
706
fe7553be
LP		 707 list_for_each_entry(connector, &dev->mode_config.connector_list,
708 head) {
709 aconnector = to_amdgpu_dm_connector(connector);
710 if (aconnector->dc_link->type != dc_connection_mst_branch ||
711 aconnector->mst_port)
712 continue;
713
714 mgr = &aconnector->mst_mgr;
715
716 if (suspend) {
717 drm_dp_mst_topology_mgr_suspend(mgr);
718 } else {
719 ret = drm_dp_mst_topology_mgr_resume(mgr);
720 if (ret < 0) {
721 drm_dp_mst_topology_mgr_set_mst(mgr, false);
722 need_hotplug = true;
723 }
724 }
4562236b
HW		 725 }
726
727 drm_modeset_unlock(&dev->mode_config.connection_mutex);
fe7553be
LP		 728
729 if (need_hotplug)
730 drm_kms_helper_hotplug_event(dev);
4562236b
HW		 731}
732
b8592b48
LL		 733/**
734 * dm_hw_init() - Initialize DC device
735 * @handle: The base driver device containing the amdpgu_dm device.
736 *
737 * Initialize the &struct amdgpu_display_manager device. This involves calling
738 * the initializers of each DM component, then populating the struct with them.
739 *
740 * Although the function implies hardware initialization, both hardware and
741 * software are initialized here. Splitting them out to their relevant init
742 * hooks is a future TODO item.
743 *
744 * Some notable things that are initialized here:
745 *
746 * - Display Core, both software and hardware
747 * - DC modules that we need (freesync and color management)
748 * - DRM software states
749 * - Interrupt sources and handlers
750 * - Vblank support
751 * - Debug FS entries, if enabled
752 */
4562236b
HW		 753static int dm_hw_init(void *handle)
754{
755 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
756 /* Create DAL display manager */
757 amdgpu_dm_init(adev);
4562236b
HW		 758 amdgpu_dm_hpd_init(adev);
759
4562236b
HW		 760 return 0;
761}
762
b8592b48
LL		 763/**
764 * dm_hw_fini() - Teardown DC device
765 * @handle: The base driver device containing the amdpgu_dm device.
766 *
767 * Teardown components within &struct amdgpu_display_manager that require
768 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
769 * were loaded. Also flush IRQ workqueues and disable them.
770 */
4562236b
HW		 771static int dm_hw_fini(void *handle)
772{
773 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
774
775 amdgpu_dm_hpd_fini(adev);
776
777 amdgpu_dm_irq_fini(adev);
21de3396 778 amdgpu_dm_fini(adev);
4562236b
HW		 779 return 0;
780}
781
782static int dm_suspend(void *handle)
783{
784 struct amdgpu_device *adev = handle;
785 struct amdgpu_display_manager *dm = &adev->dm;
786 int ret = 0;
4562236b
HW		 787
788 s3_handle_mst(adev->ddev, true);
789
4562236b
HW		 790 amdgpu_dm_irq_suspend(adev);
791
0a214e2f 792 WARN_ON(adev->dm.cached_state);
a3621485
AG		 793 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
794
32f5062d 795 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 796
797 return ret;
798}
799
1daf8c63
AD		 800static struct amdgpu_dm_connector *
801amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
802 struct drm_crtc *crtc)
4562236b
HW		 803{
804 uint32_t i;
c2cea706 805 struct drm_connector_state *new_con_state;
4562236b
HW		 806 struct drm_connector *connector;
807 struct drm_crtc *crtc_from_state;
808
c2cea706
LSL		 809 for_each_new_connector_in_state(state, connector, new_con_state, i) {
810 crtc_from_state = new_con_state->crtc;
4562236b
HW		 811
812 if (crtc_from_state == crtc)
c84dec2f 813 return to_amdgpu_dm_connector(connector);
4562236b
HW		 814 }
815
816 return NULL;
817}
818
fbbdadf2
BL		 819static void emulated_link_detect(struct dc_link *link)
820{
821 struct dc_sink_init_data sink_init_data = { 0 };
822 struct display_sink_capability sink_caps = { 0 };
823 enum dc_edid_status edid_status;
824 struct dc_context *dc_ctx = link->ctx;
825 struct dc_sink *sink = NULL;
826 struct dc_sink *prev_sink = NULL;
827
828 link->type = dc_connection_none;
829 prev_sink = link->local_sink;
830
831 if (prev_sink != NULL)
832 dc_sink_retain(prev_sink);
833
834 switch (link->connector_signal) {
835 case SIGNAL_TYPE_HDMI_TYPE_A: {
836 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
837 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
838 break;
839 }
840
841 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
842 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
843 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
844 break;
845 }
846
847 case SIGNAL_TYPE_DVI_DUAL_LINK: {
848 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
849 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
850 break;
851 }
852
853 case SIGNAL_TYPE_LVDS: {
854 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
855 sink_caps.signal = SIGNAL_TYPE_LVDS;
856 break;
857 }
858
859 case SIGNAL_TYPE_EDP: {
860 sink_caps.transaction_type =
861 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
862 sink_caps.signal = SIGNAL_TYPE_EDP;
863 break;
864 }
865
866 case SIGNAL_TYPE_DISPLAY_PORT: {
867 sink_caps.transaction_type =
868 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
869 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
870 break;
871 }
872
873 default:
874 DC_ERROR("Invalid connector type! signal:%d\n",
875 link->connector_signal);
876 return;
877 }
878
879 sink_init_data.link = link;
880 sink_init_data.sink_signal = sink_caps.signal;
881
882 sink = dc_sink_create(&sink_init_data);
883 if (!sink) {
884 DC_ERROR("Failed to create sink!\n");
885 return;
886 }
887
dcd5fb82 888 /* dc_sink_create returns a new reference */
fbbdadf2
BL		 889 link->local_sink = sink;
890
891 edid_status = dm_helpers_read_local_edid(
892 link->ctx,
893 link,
894 sink);
895
896 if (edid_status != EDID_OK)
897 DC_ERROR("Failed to read EDID");
898
899}
900
4562236b
HW		 901static int dm_resume(void *handle)
902{
903 struct amdgpu_device *adev = handle;
4562236b
HW		 904 struct drm_device *ddev = adev->ddev;
905 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 906 struct amdgpu_dm_connector *aconnector;
4562236b 907 struct drm_connector *connector;
4562236b 908 struct drm_crtc *crtc;
c2cea706 909 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 910 struct dm_crtc_state *dm_new_crtc_state;
911 struct drm_plane *plane;
912 struct drm_plane_state *new_plane_state;
913 struct dm_plane_state *dm_new_plane_state;
fbbdadf2 914 enum dc_connection_type new_connection_type = dc_connection_none;
a3621485 915 int i;
4562236b 916
a80aa93d
ML		 917 /* power on hardware */
918 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
919
4562236b
HW		 920 /* program HPD filter */
921 dc_resume(dm->dc);
922
923 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
924 s3_handle_mst(ddev, false);
925
926 /*
927 * early enable HPD Rx IRQ, should be done before set mode as short
928 * pulse interrupts are used for MST
929 */
930 amdgpu_dm_irq_resume_early(adev);
931
4562236b 932 /* Do detection*/
a80aa93d 933 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 934 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 935
936 /*
937 * this is the case when traversing through already created
938 * MST connectors, should be skipped
939 */
940 if (aconnector->mst_port)
941 continue;
942
03ea364c 943 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 944 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
945 DRM_ERROR("KMS: Failed to detect connector\n");
946
947 if (aconnector->base.force && new_connection_type == dc_connection_none)
948 emulated_link_detect(aconnector->dc_link);
949 else
950 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 951
952 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
953 aconnector->fake_enable = false;
954
dcd5fb82
MF		 955 if (aconnector->dc_sink)
956 dc_sink_release(aconnector->dc_sink);
4562236b
HW		 957 aconnector->dc_sink = NULL;
958 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 959 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 960 }
961
1f6010a9 962 /* Force mode set in atomic commit */
a80aa93d 963 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 964 new_crtc_state->active_changed = true;
4f346e65 965
fcb4019e
LSL		 966 /*
967 * atomic_check is expected to create the dc states. We need to release
968 * them here, since they were duplicated as part of the suspend
969 * procedure.
970 */
a80aa93d 971 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 972 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
973 if (dm_new_crtc_state->stream) {
974 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
975 dc_stream_release(dm_new_crtc_state->stream);
976 dm_new_crtc_state->stream = NULL;
977 }
978 }
979
a80aa93d 980 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 981 dm_new_plane_state = to_dm_plane_state(new_plane_state);
982 if (dm_new_plane_state->dc_state) {
983 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
984 dc_plane_state_release(dm_new_plane_state->dc_state);
985 dm_new_plane_state->dc_state = NULL;
986 }
987 }
988
2d1af6a1 989 drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 990
a80aa93d 991 dm->cached_state = NULL;
0a214e2f 992
9faa4237 993 amdgpu_dm_irq_resume_late(adev);
4562236b 994
2d1af6a1 995 return 0;
4562236b
HW		 996}
997
b8592b48
LL		 998/**
999 * DOC: DM Lifecycle
1000 *
1001 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1002 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1003 * the base driver's device list to be initialized and torn down accordingly.
1004 *
1005 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1006 */
1007
4562236b
HW		 1008static const struct amd_ip_funcs amdgpu_dm_funcs = {
1009 .name = "dm",
1010 .early_init = dm_early_init,
7abcf6b5 1011 .late_init = dm_late_init,
4562236b
HW		 1012 .sw_init = dm_sw_init,
1013 .sw_fini = dm_sw_fini,
1014 .hw_init = dm_hw_init,
1015 .hw_fini = dm_hw_fini,
1016 .suspend = dm_suspend,
1017 .resume = dm_resume,
1018 .is_idle = dm_is_idle,
1019 .wait_for_idle = dm_wait_for_idle,
1020 .check_soft_reset = dm_check_soft_reset,
1021 .soft_reset = dm_soft_reset,
1022 .set_clockgating_state = dm_set_clockgating_state,
1023 .set_powergating_state = dm_set_powergating_state,
1024};
1025
1026const struct amdgpu_ip_block_version dm_ip_block =
1027{
1028 .type = AMD_IP_BLOCK_TYPE_DCE,
1029 .major = 1,
1030 .minor = 0,
1031 .rev = 0,
1032 .funcs = &amdgpu_dm_funcs,
1033};
1034
ca3268c4 1035
b8592b48
LL		 1036/**
1037 * DOC: atomic
1038 *
1039 * *WIP*
1040 */
0a323b84 1041
b3663f70 1042static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 1043 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 1044 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 1045 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 1046 .atomic_commit = amdgpu_dm_atomic_commit,
54f5499a
AG		 1047};
1048
1049static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1050 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 1051};
1052
7578ecda 1053static void
3ee6b26b 1054amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1055{
1056 struct drm_connector *connector = &aconnector->base;
1057 struct drm_device *dev = connector->dev;
b73a22d3 1058 struct dc_sink *sink;
4562236b
HW		 1059
1060 /* MST handled by drm_mst framework */
1061 if (aconnector->mst_mgr.mst_state == true)
1062 return;
1063
1064
1065 sink = aconnector->dc_link->local_sink;
dcd5fb82
MF		 1066 if (sink)
1067 dc_sink_retain(sink);
4562236b 1068
1f6010a9
DF		 1069 /*
1070 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 1071 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 1072 * Skip if already done during boot.
4562236b
HW		 1073 */
1074 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1075 && aconnector->dc_em_sink) {
1076
1f6010a9
DF		 1077 /*
1078 * For S3 resume with headless use eml_sink to fake stream
1079 * because on resume connector->sink is set to NULL
4562236b
HW		 1080 */
1081 mutex_lock(&dev->mode_config.mutex);
1082
1083 if (sink) {
922aa1e1 1084 if (aconnector->dc_sink) {
98e6436d 1085 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 1086 /*
1087 * retain and release below are used to
1088 * bump up refcount for sink because the link doesn't point
1089 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 1090 * reshuffle by UMD we will get into unwanted dc_sink release
1091 */
dcd5fb82 1092 dc_sink_release(aconnector->dc_sink);
922aa1e1 1093 }
4562236b 1094 aconnector->dc_sink = sink;
dcd5fb82 1095 dc_sink_retain(aconnector->dc_sink);
98e6436d
AK		 1096 amdgpu_dm_update_freesync_caps(connector,
1097 aconnector->edid);
4562236b 1098 } else {
98e6436d 1099 amdgpu_dm_update_freesync_caps(connector, NULL);
dcd5fb82 1100 if (!aconnector->dc_sink) {
4562236b 1101 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1 1102 dc_sink_retain(aconnector->dc_sink);
dcd5fb82 1103 }
4562236b
HW		 1104 }
1105
1106 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1107
1108 if (sink)
1109 dc_sink_release(sink);
4562236b
HW		 1110 return;
1111 }
1112
1113 /*
1114 * TODO: temporary guard to look for proper fix
1115 * if this sink is MST sink, we should not do anything
1116 */
dcd5fb82
MF		 1117 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1118 dc_sink_release(sink);
4562236b 1119 return;
dcd5fb82 1120 }
4562236b
HW		 1121
1122 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 1123 /*
1124 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1125 * Do nothing!!
1126 */
f1ad2f5e 1127 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b 1128 aconnector->connector_id);
dcd5fb82
MF		 1129 if (sink)
1130 dc_sink_release(sink);
4562236b
HW		 1131 return;
1132 }
1133
f1ad2f5e 1134 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 1135 aconnector->connector_id, aconnector->dc_sink, sink);
1136
1137 mutex_lock(&dev->mode_config.mutex);
1138
1f6010a9
DF		 1139 /*
1140 * 1. Update status of the drm connector
1141 * 2. Send an event and let userspace tell us what to do
1142 */
4562236b 1143 if (sink) {
1f6010a9
DF		 1144 /*
1145 * TODO: check if we still need the S3 mode update workaround.
1146 * If yes, put it here.
1147 */
4562236b 1148 if (aconnector->dc_sink)
98e6436d 1149 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1150
1151 aconnector->dc_sink = sink;
dcd5fb82 1152 dc_sink_retain(aconnector->dc_sink);
900b3cb1 1153 if (sink->dc_edid.length == 0) {
4562236b 1154 aconnector->edid = NULL;
e86e8947 1155 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 1156 } else {
4562236b
HW		 1157 aconnector->edid =
1158 (struct edid *) sink->dc_edid.raw_edid;
1159
1160
c555f023 1161 drm_connector_update_edid_property(connector,
4562236b 1162 aconnector->edid);
e86e8947
HV		 1163 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1164 aconnector->edid);
4562236b 1165 }
98e6436d 1166 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 1167
1168 } else {
e86e8947 1169 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 1170 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 1171 drm_connector_update_edid_property(connector, NULL);
4562236b 1172 aconnector->num_modes = 0;
dcd5fb82 1173 dc_sink_release(aconnector->dc_sink);
4562236b 1174 aconnector->dc_sink = NULL;
5326c452 1175 aconnector->edid = NULL;
4562236b
HW		 1176 }
1177
1178 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1179
1180 if (sink)
1181 dc_sink_release(sink);
4562236b
HW		 1182}
1183
1184static void handle_hpd_irq(void *param)
1185{
c84dec2f 1186 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1187 struct drm_connector *connector = &aconnector->base;
1188 struct drm_device *dev = connector->dev;
fbbdadf2 1189 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1190
1f6010a9
DF		 1191 /*
1192 * In case of failure or MST no need to update connector status or notify the OS
1193 * since (for MST case) MST does this in its own context.
4562236b
HW		 1194 */
1195 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 1196
1197 if (aconnector->fake_enable)
1198 aconnector->fake_enable = false;
1199
fbbdadf2
BL		 1200 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1201 DRM_ERROR("KMS: Failed to detect connector\n");
1202
1203 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1204 emulated_link_detect(aconnector->dc_link);
1205
1206
1207 drm_modeset_lock_all(dev);
1208 dm_restore_drm_connector_state(dev, connector);
1209 drm_modeset_unlock_all(dev);
1210
1211 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1212 drm_kms_helper_hotplug_event(dev);
1213
1214 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1215 amdgpu_dm_update_connector_after_detect(aconnector);
1216
1217
1218 drm_modeset_lock_all(dev);
1219 dm_restore_drm_connector_state(dev, connector);
1220 drm_modeset_unlock_all(dev);
1221
1222 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1223 drm_kms_helper_hotplug_event(dev);
1224 }
1225 mutex_unlock(&aconnector->hpd_lock);
1226
1227}
1228
c84dec2f 1229static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1230{
1231 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1232 uint8_t dret;
1233 bool new_irq_handled = false;
1234 int dpcd_addr;
1235 int dpcd_bytes_to_read;
1236
1237 const int max_process_count = 30;
1238 int process_count = 0;
1239
1240 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1241
1242 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1243 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1244 /* DPCD 0x200 - 0x201 for downstream IRQ */
1245 dpcd_addr = DP_SINK_COUNT;
1246 } else {
1247 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1248 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1249 dpcd_addr = DP_SINK_COUNT_ESI;
1250 }
1251
1252 dret = drm_dp_dpcd_read(
1253 &aconnector->dm_dp_aux.aux,
1254 dpcd_addr,
1255 esi,
1256 dpcd_bytes_to_read);
1257
1258 while (dret == dpcd_bytes_to_read &&
1259 process_count < max_process_count) {
1260 uint8_t retry;
1261 dret = 0;
1262
1263 process_count++;
1264
f1ad2f5e 1265 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1266 /* handle HPD short pulse irq */
1267 if (aconnector->mst_mgr.mst_state)
1268 drm_dp_mst_hpd_irq(
1269 &aconnector->mst_mgr,
1270 esi,
1271 &new_irq_handled);
4562236b
HW		 1272
1273 if (new_irq_handled) {
1274 /* ACK at DPCD to notify down stream */
1275 const int ack_dpcd_bytes_to_write =
1276 dpcd_bytes_to_read - 1;
1277
1278 for (retry = 0; retry < 3; retry++) {
1279 uint8_t wret;
1280
1281 wret = drm_dp_dpcd_write(
1282 &aconnector->dm_dp_aux.aux,
1283 dpcd_addr + 1,
1284 &esi[1],
1285 ack_dpcd_bytes_to_write);
1286 if (wret == ack_dpcd_bytes_to_write)
1287 break;
1288 }
1289
1f6010a9 1290 /* check if there is new irq to be handled */
4562236b
HW		 1291 dret = drm_dp_dpcd_read(
1292 &aconnector->dm_dp_aux.aux,
1293 dpcd_addr,
1294 esi,
1295 dpcd_bytes_to_read);
1296
1297 new_irq_handled = false;
d4a6e8a9 1298 } else {
4562236b 1299 break;
d4a6e8a9 1300 }
4562236b
HW		 1301 }
1302
1303 if (process_count == max_process_count)
f1ad2f5e 1304 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1305}
1306
1307static void handle_hpd_rx_irq(void *param)
1308{
c84dec2f 1309 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1310 struct drm_connector *connector = &aconnector->base;
1311 struct drm_device *dev = connector->dev;
53cbf65c 1312 struct dc_link *dc_link = aconnector->dc_link;
4562236b 1313 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
fbbdadf2 1314 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1315
1f6010a9
DF		 1316 /*
1317 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 1318 * conflict, after implement i2c helper, this mutex should be
1319 * retired.
1320 */
53cbf65c 1321 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1322 mutex_lock(&aconnector->hpd_lock);
1323
4e18814e 1324 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1325 !is_mst_root_connector) {
1326 /* Downstream Port status changed. */
fbbdadf2
BL		 1327 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1328 DRM_ERROR("KMS: Failed to detect connector\n");
1329
1330 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1331 emulated_link_detect(dc_link);
1332
1333 if (aconnector->fake_enable)
1334 aconnector->fake_enable = false;
1335
1336 amdgpu_dm_update_connector_after_detect(aconnector);
1337
1338
1339 drm_modeset_lock_all(dev);
1340 dm_restore_drm_connector_state(dev, connector);
1341 drm_modeset_unlock_all(dev);
1342
1343 drm_kms_helper_hotplug_event(dev);
1344 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1345
1346 if (aconnector->fake_enable)
1347 aconnector->fake_enable = false;
1348
4562236b
HW		 1349 amdgpu_dm_update_connector_after_detect(aconnector);
1350
1351
1352 drm_modeset_lock_all(dev);
1353 dm_restore_drm_connector_state(dev, connector);
1354 drm_modeset_unlock_all(dev);
1355
1356 drm_kms_helper_hotplug_event(dev);
1357 }
1358 }
1359 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1360 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1361 dm_handle_hpd_rx_irq(aconnector);
1362
e86e8947
HV		 1363 if (dc_link->type != dc_connection_mst_branch) {
1364 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 1365 mutex_unlock(&aconnector->hpd_lock);
e86e8947 1366 }
4562236b
HW		 1367}
1368
1369static void register_hpd_handlers(struct amdgpu_device *adev)
1370{
1371 struct drm_device *dev = adev->ddev;
1372 struct drm_connector *connector;
c84dec2f 1373 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1374 const struct dc_link *dc_link;
1375 struct dc_interrupt_params int_params = {0};
1376
1377 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1378 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1379
1380 list_for_each_entry(connector,
1381 &dev->mode_config.connector_list, head) {
1382
c84dec2f 1383 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1384 dc_link = aconnector->dc_link;
1385
1386 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1387 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1388 int_params.irq_source = dc_link->irq_source_hpd;
1389
1390 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1391 handle_hpd_irq,
1392 (void *) aconnector);
1393 }
1394
1395 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1396
1397 /* Also register for DP short pulse (hpd_rx). */
1398 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1399 int_params.irq_source = dc_link->irq_source_hpd_rx;
1400
1401 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1402 handle_hpd_rx_irq,
1403 (void *) aconnector);
1404 }
1405 }
1406}
1407
1408/* Register IRQ sources and initialize IRQ callbacks */
1409static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1410{
1411 struct dc *dc = adev->dm.dc;
1412 struct common_irq_params *c_irq_params;
1413 struct dc_interrupt_params int_params = {0};
1414 int r;
1415 int i;
1ffdeca6 1416 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 1417
ff5ef992 1418 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1419 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1420 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1421 adev->asic_type == CHIP_RAVEN)
3760f76c 1422 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1423
1424 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1425 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1426
1f6010a9
DF		 1427 /*
1428 * Actions of amdgpu_irq_add_id():
4562236b
HW		 1429 * 1. Register a set() function with base driver.
1430 * Base driver will call set() function to enable/disable an
1431 * interrupt in DC hardware.
1432 * 2. Register amdgpu_dm_irq_handler().
1433 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1434 * coming from DC hardware.
1435 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1436 * for acknowledging and handling. */
1437
b57de80a 1438 /* Use VBLANK interrupt */
e9029155 1439 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1440 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1441 if (r) {
1442 DRM_ERROR("Failed to add crtc irq id!\n");
1443 return r;
1444 }
1445
1446 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1447 int_params.irq_source =
3d761e79 1448 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1449
b57de80a 1450 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1451
1452 c_irq_params->adev = adev;
1453 c_irq_params->irq_src = int_params.irq_source;
1454
1455 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1456 dm_crtc_high_irq, c_irq_params);
1457 }
1458
3d761e79 1459 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1460 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1461 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1462 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1463 if (r) {
1464 DRM_ERROR("Failed to add page flip irq id!\n");
1465 return r;
1466 }
1467
1468 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1469 int_params.irq_source =
1470 dc_interrupt_to_irq_source(dc, i, 0);
1471
1472 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1473
1474 c_irq_params->adev = adev;
1475 c_irq_params->irq_src = int_params.irq_source;
1476
1477 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1478 dm_pflip_high_irq, c_irq_params);
1479
1480 }
1481
1482 /* HPD */
2c8ad2d5
AD		 1483 r = amdgpu_irq_add_id(adev, client_id,
1484 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1485 if (r) {
1486 DRM_ERROR("Failed to add hpd irq id!\n");
1487 return r;
1488 }
1489
1490 register_hpd_handlers(adev);
1491
1492 return 0;
1493}
1494
ff5ef992
AD		 1495#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1496/* Register IRQ sources and initialize IRQ callbacks */
1497static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1498{
1499 struct dc *dc = adev->dm.dc;
1500 struct common_irq_params *c_irq_params;
1501 struct dc_interrupt_params int_params = {0};
1502 int r;
1503 int i;
1504
1505 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1506 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1507
1f6010a9
DF		 1508 /*
1509 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 1510 * 1. Register a set() function with base driver.
1511 * Base driver will call set() function to enable/disable an
1512 * interrupt in DC hardware.
1513 * 2. Register amdgpu_dm_irq_handler().
1514 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1515 * coming from DC hardware.
1516 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1517 * for acknowledging and handling.
1f6010a9 1518 */
ff5ef992
AD		 1519
1520 /* Use VSTARTUP interrupt */
1521 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1522 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1523 i++) {
3760f76c 1524 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1525
1526 if (r) {
1527 DRM_ERROR("Failed to add crtc irq id!\n");
1528 return r;
1529 }
1530
1531 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1532 int_params.irq_source =
1533 dc_interrupt_to_irq_source(dc, i, 0);
1534
1535 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1536
1537 c_irq_params->adev = adev;
1538 c_irq_params->irq_src = int_params.irq_source;
1539
1540 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1541 dm_crtc_high_irq, c_irq_params);
1542 }
1543
1544 /* Use GRPH_PFLIP interrupt */
1545 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1546 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1547 i++) {
3760f76c 1548 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1549 if (r) {
1550 DRM_ERROR("Failed to add page flip irq id!\n");
1551 return r;
1552 }
1553
1554 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1555 int_params.irq_source =
1556 dc_interrupt_to_irq_source(dc, i, 0);
1557
1558 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1559
1560 c_irq_params->adev = adev;
1561 c_irq_params->irq_src = int_params.irq_source;
1562
1563 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1564 dm_pflip_high_irq, c_irq_params);
1565
1566 }
1567
1568 /* HPD */
3760f76c 1569 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1570 &adev->hpd_irq);
1571 if (r) {
1572 DRM_ERROR("Failed to add hpd irq id!\n");
1573 return r;
1574 }
1575
1576 register_hpd_handlers(adev);
1577
1578 return 0;
1579}
1580#endif
1581
eb3dc897
NK		 1582/*
1583 * Acquires the lock for the atomic state object and returns
1584 * the new atomic state.
1585 *
1586 * This should only be called during atomic check.
1587 */
1588static int dm_atomic_get_state(struct drm_atomic_state *state,
1589 struct dm_atomic_state **dm_state)
1590{
1591 struct drm_device *dev = state->dev;
1592 struct amdgpu_device *adev = dev->dev_private;
1593 struct amdgpu_display_manager *dm = &adev->dm;
1594 struct drm_private_state *priv_state;
1595 int ret;
1596
1597 if (*dm_state)
1598 return 0;
1599
1600 ret = drm_modeset_lock(&dm->atomic_obj_lock, state->acquire_ctx);
1601 if (ret)
1602 return ret;
1603
1604 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1605 if (IS_ERR(priv_state))
1606 return PTR_ERR(priv_state);
1607
1608 *dm_state = to_dm_atomic_state(priv_state);
1609
1610 return 0;
1611}
1612
1613struct dm_atomic_state *
1614dm_atomic_get_new_state(struct drm_atomic_state *state)
1615{
1616 struct drm_device *dev = state->dev;
1617 struct amdgpu_device *adev = dev->dev_private;
1618 struct amdgpu_display_manager *dm = &adev->dm;
1619 struct drm_private_obj *obj;
1620 struct drm_private_state *new_obj_state;
1621 int i;
1622
1623 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1624 if (obj->funcs == dm->atomic_obj.funcs)
1625 return to_dm_atomic_state(new_obj_state);
1626 }
1627
1628 return NULL;
1629}
1630
1631struct dm_atomic_state *
1632dm_atomic_get_old_state(struct drm_atomic_state *state)
1633{
1634 struct drm_device *dev = state->dev;
1635 struct amdgpu_device *adev = dev->dev_private;
1636 struct amdgpu_display_manager *dm = &adev->dm;
1637 struct drm_private_obj *obj;
1638 struct drm_private_state *old_obj_state;
1639 int i;
1640
1641 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1642 if (obj->funcs == dm->atomic_obj.funcs)
1643 return to_dm_atomic_state(old_obj_state);
1644 }
1645
1646 return NULL;
1647}
1648
1649static struct drm_private_state *
1650dm_atomic_duplicate_state(struct drm_private_obj *obj)
1651{
1652 struct dm_atomic_state *old_state, *new_state;
1653
1654 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1655 if (!new_state)
1656 return NULL;
1657
1658 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1659
1660 new_state->context = dc_create_state();
1661 if (!new_state->context) {
1662 kfree(new_state);
1663 return NULL;
1664 }
1665
1666 old_state = to_dm_atomic_state(obj->state);
1667 if (old_state && old_state->context)
1668 dc_resource_state_copy_construct(old_state->context,
1669 new_state->context);
1670
1671 return &new_state->base;
1672}
1673
1674static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1675 struct drm_private_state *state)
1676{
1677 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1678
1679 if (dm_state && dm_state->context)
1680 dc_release_state(dm_state->context);
1681
1682 kfree(dm_state);
1683}
1684
1685static struct drm_private_state_funcs dm_atomic_state_funcs = {
1686 .atomic_duplicate_state = dm_atomic_duplicate_state,
1687 .atomic_destroy_state = dm_atomic_destroy_state,
1688};
1689
4562236b
HW		 1690static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1691{
eb3dc897 1692 struct dm_atomic_state *state;
4562236b
HW		 1693 int r;
1694
1695 adev->mode_info.mode_config_initialized = true;
1696
4562236b 1697 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1698 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1699
1700 adev->ddev->mode_config.max_width = 16384;
1701 adev->ddev->mode_config.max_height = 16384;
1702
1703 adev->ddev->mode_config.preferred_depth = 24;
1704 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 1705 /* indicates support for immediate flip */
4562236b
HW		 1706 adev->ddev->mode_config.async_page_flip = true;
1707
770d13b1 1708 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1709
eb3dc897
NK		 1710 drm_modeset_lock_init(&adev->dm.atomic_obj_lock);
1711
1712 state = kzalloc(sizeof(*state), GFP_KERNEL);
1713 if (!state)
1714 return -ENOMEM;
1715
1716 state->context = dc_create_state();
1717 if (!state->context) {
1718 kfree(state);
1719 return -ENOMEM;
1720 }
1721
1722 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1723
8c1a765b
DA		 1724 drm_atomic_private_obj_init(adev->ddev,
1725 &adev->dm.atomic_obj,
eb3dc897
NK		 1726 &state->base,
1727 &dm_atomic_state_funcs);
1728
3dc9b1ce 1729 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1730 if (r)
1731 return r;
1732
1733 return 0;
1734}
1735
206bbafe
DF		 1736#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1737#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1738
4562236b
HW		 1739#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1740 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1741
206bbafe
DF		 1742static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1743{
1744#if defined(CONFIG_ACPI)
1745 struct amdgpu_dm_backlight_caps caps;
1746
1747 if (dm->backlight_caps.caps_valid)
1748 return;
1749
1750 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1751 if (caps.caps_valid) {
1752 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1753 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1754 dm->backlight_caps.caps_valid = true;
1755 } else {
1756 dm->backlight_caps.min_input_signal =
1757 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1758 dm->backlight_caps.max_input_signal =
1759 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1760 }
1761#else
8bcbc9ef
DF		 1762 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1763 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 1764#endif
1765}
1766
4562236b
HW		 1767static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1768{
1769 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe
DF		 1770 struct amdgpu_dm_backlight_caps caps;
1771 uint32_t brightness = bd->props.brightness;
4562236b 1772
206bbafe
DF		 1773 amdgpu_dm_update_backlight_caps(dm);
1774 caps = dm->backlight_caps;
0cafc82f 1775 /*
206bbafe
DF		 1776 * The brightness input is in the range 0-255
1777 * It needs to be rescaled to be between the
1778 * requested min and max input signal
1779 *
1780 * It also needs to be scaled up by 0x101 to
1781 * match the DC interface which has a range of
1782 * 0 to 0xffff
0cafc82f 1783 */
206bbafe
DF		 1784 brightness =
1785 brightness
1786 * 0x101
1787 * (caps.max_input_signal - caps.min_input_signal)
1788 / AMDGPU_MAX_BL_LEVEL
1789 + caps.min_input_signal * 0x101;
4562236b
HW		 1790
1791 if (dc_link_set_backlight_level(dm->backlight_link,
923fe495 1792 brightness, 0))
4562236b
HW		 1793 return 0;
1794 else
1795 return 1;
1796}
1797
1798static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1799{
620a0d27
DF		 1800 struct amdgpu_display_manager *dm = bl_get_data(bd);
1801 int ret = dc_link_get_backlight_level(dm->backlight_link);
1802
1803 if (ret == DC_ERROR_UNEXPECTED)
1804 return bd->props.brightness;
1805 return ret;
4562236b
HW		 1806}
1807
1808static const struct backlight_ops amdgpu_dm_backlight_ops = {
1809 .get_brightness = amdgpu_dm_backlight_get_brightness,
1810 .update_status = amdgpu_dm_backlight_update_status,
1811};
1812
7578ecda
AD		 1813static void
1814amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1815{
1816 char bl_name[16];
1817 struct backlight_properties props = { 0 };
1818
206bbafe
DF		 1819 amdgpu_dm_update_backlight_caps(dm);
1820
4562236b 1821 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 1822 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 1823 props.type = BACKLIGHT_RAW;
1824
1825 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1826 dm->adev->ddev->primary->index);
1827
1828 dm->backlight_dev = backlight_device_register(bl_name,
1829 dm->adev->ddev->dev,
1830 dm,
1831 &amdgpu_dm_backlight_ops,
1832 &props);
1833
74baea42 1834 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1835 DRM_ERROR("DM: Backlight registration failed!\n");
1836 else
f1ad2f5e 1837 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1838}
1839
1840#endif
1841
df534fff
S		 1842static int initialize_plane(struct amdgpu_display_manager *dm,
1843 struct amdgpu_mode_info *mode_info,
1844 int plane_id)
1845{
f180b4bc 1846 struct drm_plane *plane;
df534fff
S		 1847 unsigned long possible_crtcs;
1848 int ret = 0;
1849
f180b4bc 1850 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 1851 mode_info->planes[plane_id] = plane;
1852
1853 if (!plane) {
1854 DRM_ERROR("KMS: Failed to allocate plane\n");
1855 return -ENOMEM;
1856 }
f180b4bc 1857 plane->type = mode_info->plane_type[plane_id];
df534fff
S		 1858
1859 /*
1f6010a9 1860 * HACK: IGT tests expect that each plane can only have
df534fff
S		 1861 * one possible CRTC. For now, set one CRTC for each
1862 * plane that is not an underlay, but still allow multiple
1863 * CRTCs for underlay planes.
1864 */
1865 possible_crtcs = 1 << plane_id;
1866 if (plane_id >= dm->dc->caps.max_streams)
1867 possible_crtcs = 0xff;
1868
1869 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1870
1871 if (ret) {
1872 DRM_ERROR("KMS: Failed to initialize plane\n");
1873 return ret;
1874 }
1875
1876 return ret;
1877}
1878
89fc8d4e
HW		 1879
1880static void register_backlight_device(struct amdgpu_display_manager *dm,
1881 struct dc_link *link)
1882{
1883#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1884 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1885
1886 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1887 link->type != dc_connection_none) {
1f6010a9
DF		 1888 /*
1889 * Event if registration failed, we should continue with
89fc8d4e
HW		 1890 * DM initialization because not having a backlight control
1891 * is better then a black screen.
1892 */
1893 amdgpu_dm_register_backlight_device(dm);
1894
1895 if (dm->backlight_dev)
1896 dm->backlight_link = link;
1897 }
1898#endif
1899}
1900
1901
1f6010a9
DF		 1902/*
1903 * In this architecture, the association
4562236b
HW		 1904 * connector -> encoder -> crtc
1905 * id not really requried. The crtc and connector will hold the
1906 * display_index as an abstraction to use with DAL component
1907 *
1908 * Returns 0 on success
1909 */
7578ecda 1910static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1911{
1912 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 1913 int32_t i;
c84dec2f 1914 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1915 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1916 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1917 uint32_t link_cnt;
df534fff 1918 int32_t total_overlay_planes, total_primary_planes;
fbbdadf2 1919 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b
HW		 1920
1921 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1922 if (amdgpu_dm_mode_config_init(dm->adev)) {
1923 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 1924 return -EINVAL;
4562236b
HW		 1925 }
1926
df534fff
S		 1927 /* Identify the number of planes to be initialized */
1928 total_overlay_planes = dm->dc->caps.max_slave_planes;
1929 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
efa6a8b7 1930
df534fff
S		 1931 /* First initialize overlay planes, index starting after primary planes */
1932 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1933 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1934 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 1935 goto fail;
d4e13b0d 1936 }
df534fff 1937 }
92f3ac40 1938
df534fff
S		 1939 /* Initialize primary planes */
1940 for (i = (total_primary_planes - 1); i >= 0; i--) {
1941 if (initialize_plane(dm, mode_info, i)) {
1942 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 1943 goto fail;
d4e13b0d
AD		 1944 }
1945 }
4562236b 1946
d4e13b0d 1947 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 1948 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 1949 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1950 goto fail;
4562236b 1951 }
4562236b 1952
ab2541b6 1953 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1954
1955 /* loops over all connectors on the board */
1956 for (i = 0; i < link_cnt; i++) {
89fc8d4e 1957 struct dc_link *link = NULL;
4562236b
HW		 1958
1959 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1960 DRM_ERROR(
1961 "KMS: Cannot support more than %d display indexes\n",
1962 AMDGPU_DM_MAX_DISPLAY_INDEX);
1963 continue;
1964 }
1965
1966 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1967 if (!aconnector)
cd8a2ae8 1968 goto fail;
4562236b
HW		 1969
1970 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1971 if (!aencoder)
cd8a2ae8 1972 goto fail;
4562236b
HW		 1973
1974 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1975 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1976 goto fail;
4562236b
HW		 1977 }
1978
1979 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1980 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1981 goto fail;
4562236b
HW		 1982 }
1983
89fc8d4e
HW		 1984 link = dc_get_link_at_index(dm->dc, i);
1985
fbbdadf2
BL		 1986 if (!dc_link_detect_sink(link, &new_connection_type))
1987 DRM_ERROR("KMS: Failed to detect connector\n");
1988
1989 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1990 emulated_link_detect(link);
1991 amdgpu_dm_update_connector_after_detect(aconnector);
1992
1993 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 1994 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 1995 register_backlight_device(dm, link);
1996 }
1997
1998
4562236b
HW		 1999 }
2000
2001 /* Software is initialized. Now we can register interrupt handlers. */
2002 switch (adev->asic_type) {
2003 case CHIP_BONAIRE:
2004 case CHIP_HAWAII:
cd4b356f
AD		 2005 case CHIP_KAVERI:
2006 case CHIP_KABINI:
2007 case CHIP_MULLINS:
4562236b
HW		 2008 case CHIP_TONGA:
2009 case CHIP_FIJI:
2010 case CHIP_CARRIZO:
2011 case CHIP_STONEY:
2012 case CHIP_POLARIS11:
2013 case CHIP_POLARIS10:
b264d345 2014 case CHIP_POLARIS12:
7737de91 2015 case CHIP_VEGAM:
2c8ad2d5 2016 case CHIP_VEGA10:
2325ff30 2017 case CHIP_VEGA12:
1fe6bf2f 2018 case CHIP_VEGA20:
4562236b
HW		 2019 if (dce110_register_irq_handlers(dm->adev)) {
2020 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2021 goto fail;
4562236b
HW		 2022 }
2023 break;
ff5ef992
AD		 2024#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2025 case CHIP_RAVEN:
2026 if (dcn10_register_irq_handlers(dm->adev)) {
2027 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2028 goto fail;
ff5ef992
AD		 2029 }
2030 break;
2031#endif
4562236b 2032 default:
e63f8673 2033 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 2034 goto fail;
4562236b
HW		 2035 }
2036
1bc460a4
HW		 2037 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2038 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2039
4562236b 2040 return 0;
cd8a2ae8 2041fail:
4562236b 2042 kfree(aencoder);
4562236b 2043 kfree(aconnector);
3be5262e 2044 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 2045 kfree(mode_info->planes[i]);
59d0f396 2046 return -EINVAL;
4562236b
HW		 2047}
2048
7578ecda 2049static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2050{
2051 drm_mode_config_cleanup(dm->ddev);
eb3dc897 2052 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 2053 return;
2054}
2055
2056/******************************************************************************
2057 * amdgpu_display_funcs functions
2058 *****************************************************************************/
2059
1f6010a9 2060/*
4562236b
HW		 2061 * dm_bandwidth_update - program display watermarks
2062 *
2063 * @adev: amdgpu_device pointer
2064 *
2065 * Calculate and program the display watermarks and line buffer allocation.
2066 */
2067static void dm_bandwidth_update(struct amdgpu_device *adev)
2068{
49c07a99 2069 /* TODO: implement later */
4562236b
HW		 2070}
2071
39cc5be2 2072static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 2073 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2074 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 2075 .backlight_set_level = NULL, /* never called for DC */
2076 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 2077 .hpd_sense = NULL,/* called unconditionally */
2078 .hpd_set_polarity = NULL, /* called unconditionally */
2079 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2080 .page_flip_get_scanoutpos =
2081 dm_crtc_get_scanoutpos,/* called unconditionally */
2082 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2083 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2084};
2085
2086#if defined(CONFIG_DEBUG_KERNEL_DC)
2087
3ee6b26b
AD		 2088static ssize_t s3_debug_store(struct device *device,
2089 struct device_attribute *attr,
2090 const char *buf,
2091 size_t count)
4562236b
HW		 2092{
2093 int ret;
2094 int s3_state;
2095 struct pci_dev *pdev = to_pci_dev(device);
2096 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2097 struct amdgpu_device *adev = drm_dev->dev_private;
2098
2099 ret = kstrtoint(buf, 0, &s3_state);
2100
2101 if (ret == 0) {
2102 if (s3_state) {
2103 dm_resume(adev);
4562236b
HW		 2104 drm_kms_helper_hotplug_event(adev->ddev);
2105 } else
2106 dm_suspend(adev);
2107 }
2108
2109 return ret == 0 ? count : 0;
2110}
2111
2112DEVICE_ATTR_WO(s3_debug);
2113
2114#endif
2115
2116static int dm_early_init(void *handle)
2117{
2118 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2119
4562236b
HW		 2120 switch (adev->asic_type) {
2121 case CHIP_BONAIRE:
2122 case CHIP_HAWAII:
2123 adev->mode_info.num_crtc = 6;
2124 adev->mode_info.num_hpd = 6;
2125 adev->mode_info.num_dig = 6;
3be5262e 2126 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 2127 break;
cd4b356f
AD		 2128 case CHIP_KAVERI:
2129 adev->mode_info.num_crtc = 4;
2130 adev->mode_info.num_hpd = 6;
2131 adev->mode_info.num_dig = 7;
2132 adev->mode_info.plane_type = dm_plane_type_default;
2133 break;
2134 case CHIP_KABINI:
2135 case CHIP_MULLINS:
2136 adev->mode_info.num_crtc = 2;
2137 adev->mode_info.num_hpd = 6;
2138 adev->mode_info.num_dig = 6;
2139 adev->mode_info.plane_type = dm_plane_type_default;
2140 break;
4562236b
HW		 2141 case CHIP_FIJI:
2142 case CHIP_TONGA:
2143 adev->mode_info.num_crtc = 6;
2144 adev->mode_info.num_hpd = 6;
2145 adev->mode_info.num_dig = 7;
3be5262e 2146 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 2147 break;
2148 case CHIP_CARRIZO:
2149 adev->mode_info.num_crtc = 3;
2150 adev->mode_info.num_hpd = 6;
2151 adev->mode_info.num_dig = 9;
3be5262e 2152 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 2153 break;
2154 case CHIP_STONEY:
2155 adev->mode_info.num_crtc = 2;
2156 adev->mode_info.num_hpd = 6;
2157 adev->mode_info.num_dig = 9;
3be5262e 2158 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 2159 break;
2160 case CHIP_POLARIS11:
b264d345 2161 case CHIP_POLARIS12:
4562236b
HW		 2162 adev->mode_info.num_crtc = 5;
2163 adev->mode_info.num_hpd = 5;
2164 adev->mode_info.num_dig = 5;
3be5262e 2165 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 2166 break;
2167 case CHIP_POLARIS10:
7737de91 2168 case CHIP_VEGAM:
4562236b
HW		 2169 adev->mode_info.num_crtc = 6;
2170 adev->mode_info.num_hpd = 6;
2171 adev->mode_info.num_dig = 6;
3be5262e 2172 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 2173 break;
2c8ad2d5 2174 case CHIP_VEGA10:
2325ff30 2175 case CHIP_VEGA12:
1fe6bf2f 2176 case CHIP_VEGA20:
2c8ad2d5
AD		 2177 adev->mode_info.num_crtc = 6;
2178 adev->mode_info.num_hpd = 6;
2179 adev->mode_info.num_dig = 6;
3be5262e 2180 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 2181 break;
ff5ef992
AD		 2182#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2183 case CHIP_RAVEN:
2184 adev->mode_info.num_crtc = 4;
2185 adev->mode_info.num_hpd = 4;
2186 adev->mode_info.num_dig = 4;
3be5262e 2187 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 2188 break;
2189#endif
4562236b 2190 default:
e63f8673 2191 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 2192 return -EINVAL;
2193 }
2194
c8dd5715
MD		 2195 amdgpu_dm_set_irq_funcs(adev);
2196
39cc5be2
AD		 2197 if (adev->mode_info.funcs == NULL)
2198 adev->mode_info.funcs = &dm_display_funcs;
2199
1f6010a9
DF		 2200 /*
2201 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 2202 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 2203 * amdgpu_device_init()
2204 */
4562236b
HW		 2205#if defined(CONFIG_DEBUG_KERNEL_DC)
2206 device_create_file(
2207 adev->ddev->dev,
2208 &dev_attr_s3_debug);
2209#endif
2210
2211 return 0;
2212}
2213
9b690ef3 2214static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 2215 struct dc_stream_state *new_stream,
2216 struct dc_stream_state *old_stream)
9b690ef3 2217{
e7b07cee
HW		 2218 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2219 return false;
2220
2221 if (!crtc_state->enable)
2222 return false;
2223
2224 return crtc_state->active;
2225}
2226
2227static bool modereset_required(struct drm_crtc_state *crtc_state)
2228{
2229 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2230 return false;
2231
2232 return !crtc_state->enable || !crtc_state->active;
2233}
2234
7578ecda 2235static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 2236{
2237 drm_encoder_cleanup(encoder);
2238 kfree(encoder);
2239}
2240
2241static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2242 .destroy = amdgpu_dm_encoder_destroy,
2243};
2244
3ee6b26b
AD		 2245static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
2246 struct dc_plane_state *plane_state)
e7b07cee 2247{
3be5262e
HW		 2248 plane_state->src_rect.x = state->src_x >> 16;
2249 plane_state->src_rect.y = state->src_y >> 16;
1f6010a9 2250 /* we ignore the mantissa for now and do not deal with floating pixels :( */
3be5262e 2251 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 2252
3be5262e 2253 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 2254 return false;
2255
3be5262e
HW		 2256 plane_state->src_rect.height = state->src_h >> 16;
2257 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 2258 return false;
2259
3be5262e
HW		 2260 plane_state->dst_rect.x = state->crtc_x;
2261 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 2262
2263 if (state->crtc_w == 0)
2264 return false;
2265
3be5262e 2266 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 2267
2268 if (state->crtc_h == 0)
2269 return false;
2270
3be5262e 2271 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 2272
3be5262e 2273 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 2274
2275 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
2276 case DRM_MODE_ROTATE_0:
3be5262e 2277 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2278 break;
2279 case DRM_MODE_ROTATE_90:
3be5262e 2280 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 2281 break;
2282 case DRM_MODE_ROTATE_180:
3be5262e 2283 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 2284 break;
2285 case DRM_MODE_ROTATE_270:
3be5262e 2286 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 2287 break;
2288 default:
3be5262e 2289 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2290 break;
2291 }
2292
4562236b
HW		 2293 return true;
2294}
3ee6b26b 2295static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 2296 uint64_t *tiling_flags)
e7b07cee 2297{
e68d14dd 2298 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 2299 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 2300
e7b07cee 2301 if (unlikely(r)) {
1f6010a9 2302 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 2303 if (r != -ERESTARTSYS)
2304 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 2305 return r;
2306 }
2307
e7b07cee
HW		 2308 if (tiling_flags)
2309 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2310
2311 amdgpu_bo_unreserve(rbo);
2312
2313 return r;
2314}
2315
7df7e505
NK		 2316static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2317{
2318 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2319
2320 return offset ? (address + offset * 256) : 0;
2321}
2322
2323static bool fill_plane_dcc_attributes(struct amdgpu_device *adev,
2324 const struct amdgpu_framebuffer *afb,
2325 struct dc_plane_state *plane_state,
2326 uint64_t info)
2327{
2328 struct dc *dc = adev->dm.dc;
8daa1218
NC		 2329 struct dc_dcc_surface_param input;
2330 struct dc_surface_dcc_cap output;
7df7e505
NK		 2331 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2332 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2333 uint64_t dcc_address;
2334
8daa1218
NC		 2335 memset(&input, 0, sizeof(input));
2336 memset(&output, 0, sizeof(output));
2337
7df7e505
NK		 2338 if (!offset)
2339 return false;
2340
2341 if (!dc->cap_funcs.get_dcc_compression_cap)
2342 return false;
2343
2344 input.format = plane_state->format;
2345 input.surface_size.width =
2346 plane_state->plane_size.grph.surface_size.width;
2347 input.surface_size.height =
2348 plane_state->plane_size.grph.surface_size.height;
2349 input.swizzle_mode = plane_state->tiling_info.gfx9.swizzle;
2350
2351 if (plane_state->rotation == ROTATION_ANGLE_0 ||
2352 plane_state->rotation == ROTATION_ANGLE_180)
2353 input.scan = SCAN_DIRECTION_HORIZONTAL;
2354 else if (plane_state->rotation == ROTATION_ANGLE_90 ||
2355 plane_state->rotation == ROTATION_ANGLE_270)
2356 input.scan = SCAN_DIRECTION_VERTICAL;
2357
2358 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2359 return false;
2360
2361 if (!output.capable)
2362 return false;
2363
2364 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2365 return false;
2366
2367 plane_state->dcc.enable = 1;
2368 plane_state->dcc.grph.meta_pitch =
2369 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2370 plane_state->dcc.grph.independent_64b_blks = i64b;
2371
2372 dcc_address = get_dcc_address(afb->address, info);
2373 plane_state->address.grph.meta_addr.low_part =
2374 lower_32_bits(dcc_address);
2375 plane_state->address.grph.meta_addr.high_part =
2376 upper_32_bits(dcc_address);
2377
2378 return true;
2379}
2380
3ee6b26b
AD		 2381static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
2382 struct dc_plane_state *plane_state,
9817d5f5 2383 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 2384{
2385 uint64_t tiling_flags;
e7b07cee
HW		 2386 unsigned int awidth;
2387 const struct drm_framebuffer *fb = &amdgpu_fb->base;
2388 int ret = 0;
2389 struct drm_format_name_buf format_name;
2390
2391 ret = get_fb_info(
2392 amdgpu_fb,
9817d5f5 2393 &tiling_flags);
e7b07cee
HW		 2394
2395 if (ret)
2396 return ret;
2397
2398 switch (fb->format->format) {
2399 case DRM_FORMAT_C8:
3be5262e 2400 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 2401 break;
2402 case DRM_FORMAT_RGB565:
3be5262e 2403 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 2404 break;
2405 case DRM_FORMAT_XRGB8888:
2406 case DRM_FORMAT_ARGB8888:
3be5262e 2407 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 2408 break;
2409 case DRM_FORMAT_XRGB2101010:
2410 case DRM_FORMAT_ARGB2101010:
3be5262e 2411 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 2412 break;
2413 case DRM_FORMAT_XBGR2101010:
2414 case DRM_FORMAT_ABGR2101010:
3be5262e 2415 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee 2416 break;
bcd47f60
MR		 2417 case DRM_FORMAT_XBGR8888:
2418 case DRM_FORMAT_ABGR8888:
2419 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2420 break;
e7b07cee 2421 case DRM_FORMAT_NV21:
3be5262e 2422 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 2423 break;
2424 case DRM_FORMAT_NV12:
3be5262e 2425 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 2426 break;
2427 default:
2428 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 2429 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 2430 return -EINVAL;
2431 }
2432
7df7e505
NK		 2433 memset(&plane_state->address, 0, sizeof(plane_state->address));
2434 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
2435 memset(&plane_state->dcc, 0, sizeof(plane_state->dcc));
2436
3be5262e
HW		 2437 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2438 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 2439 plane_state->plane_size.grph.surface_size.x = 0;
2440 plane_state->plane_size.grph.surface_size.y = 0;
2441 plane_state->plane_size.grph.surface_size.width = fb->width;
2442 plane_state->plane_size.grph.surface_size.height = fb->height;
2443 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 2444 fb->pitches[0] / fb->format->cpp[0];
2445 /* TODO: unhardcode */
3be5262e 2446 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 2447
2448 } else {
2449 awidth = ALIGN(fb->width, 64);
3be5262e 2450 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 2451 plane_state->plane_size.video.luma_size.x = 0;
2452 plane_state->plane_size.video.luma_size.y = 0;
2453 plane_state->plane_size.video.luma_size.width = awidth;
2454 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 2455 /* TODO: unhardcode */
3be5262e 2456 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 2457
3be5262e
HW		 2458 plane_state->plane_size.video.chroma_size.x = 0;
2459 plane_state->plane_size.video.chroma_size.y = 0;
2460 plane_state->plane_size.video.chroma_size.width = awidth;
2461 plane_state->plane_size.video.chroma_size.height = fb->height;
2462 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 2463
2464 /* TODO: unhardcode */
3be5262e 2465 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 2466 }
2467
b830ebc9
HW		 2468 /* Fill GFX8 params */
2469 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2470 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 2471
2472 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2473 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2474 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2475 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2476 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2477
2478 /* XXX fix me for VI */
3be5262e
HW		 2479 plane_state->tiling_info.gfx8.num_banks = num_banks;
2480 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 2481 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 2482 plane_state->tiling_info.gfx8.tile_split = tile_split;
2483 plane_state->tiling_info.gfx8.bank_width = bankw;
2484 plane_state->tiling_info.gfx8.bank_height = bankh;
2485 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2486 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 2487 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2488 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2489 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 2490 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 2491 }
2492
3be5262e 2493 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 2494 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2495
2496 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 2497 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 2498 adev->asic_type == CHIP_VEGA20 ||
e7b07cee
HW		 2499 adev->asic_type == CHIP_RAVEN) {
2500 /* Fill GFX9 params */
3be5262e 2501 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 2502 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 2503 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 2504 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 2505 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 2506 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 2507 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 2508 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 2509 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 2510 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 2511 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 2512 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 2513 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 2514 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 2515 plane_state->tiling_info.gfx9.shaderEnable = 1;
7df7e505
NK		 2516
2517 fill_plane_dcc_attributes(adev, amdgpu_fb, plane_state,
2518 tiling_flags);
e7b07cee
HW		 2519 }
2520
3be5262e
HW		 2521 plane_state->visible = true;
2522 plane_state->scaling_quality.h_taps_c = 0;
2523 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 2524
3be5262e
HW		 2525 /* is this needed? is plane_state zeroed at allocation? */
2526 plane_state->scaling_quality.h_taps = 0;
2527 plane_state->scaling_quality.v_taps = 0;
2528 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 2529
2530 return ret;
2531
2532}
2533
3ee6b26b
AD		 2534static int fill_plane_attributes(struct amdgpu_device *adev,
2535 struct dc_plane_state *dc_plane_state,
2536 struct drm_plane_state *plane_state,
9817d5f5 2537 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2538{
2539 const struct amdgpu_framebuffer *amdgpu_fb =
2540 to_amdgpu_framebuffer(plane_state->fb);
2541 const struct drm_crtc *crtc = plane_state->crtc;
e7b07cee
HW		 2542 int ret = 0;
2543
3be5262e 2544 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 2545 return -EINVAL;
2546
2547 ret = fill_plane_attributes_from_fb(
2548 crtc->dev->dev_private,
3be5262e 2549 dc_plane_state,
9817d5f5 2550 amdgpu_fb);
e7b07cee
HW		 2551
2552 if (ret)
2553 return ret;
2554
e277adc5
LSL		 2555 /*
2556 * Always set input transfer function, since plane state is refreshed
2557 * every time.
2558 */
2559 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2560 if (ret) {
2561 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2562 dc_plane_state->in_transfer_func = NULL;
2563 }
e7b07cee
HW		 2564
2565 return ret;
2566}
2567
3ee6b26b
AD		 2568static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2569 const struct dm_connector_state *dm_state,
2570 struct dc_stream_state *stream)
e7b07cee
HW		 2571{
2572 enum amdgpu_rmx_type rmx_type;
2573
2574 struct rect src = { 0 }; /* viewport in composition space*/
2575 struct rect dst = { 0 }; /* stream addressable area */
2576
2577 /* no mode. nothing to be done */
2578 if (!mode)
2579 return;
2580
2581 /* Full screen scaling by default */
2582 src.width = mode->hdisplay;
2583 src.height = mode->vdisplay;
2584 dst.width = stream->timing.h_addressable;
2585 dst.height = stream->timing.v_addressable;
2586
f4791779
HW		 2587 if (dm_state) {
2588 rmx_type = dm_state->scaling;
2589 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2590 if (src.width * dst.height <
2591 src.height * dst.width) {
2592 /* height needs less upscaling/more downscaling */
2593 dst.width = src.width *
2594 dst.height / src.height;
2595 } else {
2596 /* width needs less upscaling/more downscaling */
2597 dst.height = src.height *
2598 dst.width / src.width;
2599 }
2600 } else if (rmx_type == RMX_CENTER) {
2601 dst = src;
e7b07cee 2602 }
e7b07cee 2603
f4791779
HW		 2604 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2605 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2606
f4791779
HW		 2607 if (dm_state->underscan_enable) {
2608 dst.x += dm_state->underscan_hborder / 2;
2609 dst.y += dm_state->underscan_vborder / 2;
2610 dst.width -= dm_state->underscan_hborder;
2611 dst.height -= dm_state->underscan_vborder;
2612 }
e7b07cee
HW		 2613 }
2614
2615 stream->src = src;
2616 stream->dst = dst;
2617
f1ad2f5e 2618 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2619 dst.x, dst.y, dst.width, dst.height);
2620
2621}
2622
3ee6b26b
AD		 2623static enum dc_color_depth
2624convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee 2625{
07e3a1cf
NK		 2626 struct dm_connector_state *dm_conn_state =
2627 to_dm_connector_state(connector->state);
e7b07cee
HW		 2628 uint32_t bpc = connector->display_info.bpc;
2629
07e3a1cf
NK		 2630 /* TODO: Remove this when there's support for max_bpc in drm */
2631 if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2632 /* Round down to nearest even number. */
2633 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2634
e7b07cee
HW		 2635 switch (bpc) {
2636 case 0:
1f6010a9
DF		 2637 /*
2638 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 2639 * EDID revision before 1.4
2640 * TODO: Fix edid parsing
2641 */
2642 return COLOR_DEPTH_888;
2643 case 6:
2644 return COLOR_DEPTH_666;
2645 case 8:
2646 return COLOR_DEPTH_888;
2647 case 10:
2648 return COLOR_DEPTH_101010;
2649 case 12:
2650 return COLOR_DEPTH_121212;
2651 case 14:
2652 return COLOR_DEPTH_141414;
2653 case 16:
2654 return COLOR_DEPTH_161616;
2655 default:
2656 return COLOR_DEPTH_UNDEFINED;
2657 }
2658}
2659
3ee6b26b
AD		 2660static enum dc_aspect_ratio
2661get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 2662{
e11d4147
LSL		 2663 /* 1-1 mapping, since both enums follow the HDMI spec. */
2664 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 2665}
2666
3ee6b26b
AD		 2667static enum dc_color_space
2668get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2669{
2670 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2671
2672 switch (dc_crtc_timing->pixel_encoding) {
2673 case PIXEL_ENCODING_YCBCR422:
2674 case PIXEL_ENCODING_YCBCR444:
2675 case PIXEL_ENCODING_YCBCR420:
2676 {
2677 /*
2678 * 27030khz is the separation point between HDTV and SDTV
2679 * according to HDMI spec, we use YCbCr709 and YCbCr601
2680 * respectively
2681 */
380604e2 2682 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 2683 if (dc_crtc_timing->flags.Y_ONLY)
2684 color_space =
2685 COLOR_SPACE_YCBCR709_LIMITED;
2686 else
2687 color_space = COLOR_SPACE_YCBCR709;
2688 } else {
2689 if (dc_crtc_timing->flags.Y_ONLY)
2690 color_space =
2691 COLOR_SPACE_YCBCR601_LIMITED;
2692 else
2693 color_space = COLOR_SPACE_YCBCR601;
2694 }
2695
2696 }
2697 break;
2698 case PIXEL_ENCODING_RGB:
2699 color_space = COLOR_SPACE_SRGB;
2700 break;
2701
2702 default:
2703 WARN_ON(1);
2704 break;
2705 }
2706
2707 return color_space;
2708}
2709
400443e8
ML		 2710static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2711{
2712 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2713 return;
2714
2715 timing_out->display_color_depth--;
2716}
2717
2718static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2719 const struct drm_display_info *info)
2720{
2721 int normalized_clk;
2722 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2723 return;
2724 do {
380604e2 2725 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 2726 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2727 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2728 normalized_clk /= 2;
2729 /* Adjusting pix clock following on HDMI spec based on colour depth */
2730 switch (timing_out->display_color_depth) {
2731 case COLOR_DEPTH_101010:
2732 normalized_clk = (normalized_clk * 30) / 24;
2733 break;
2734 case COLOR_DEPTH_121212:
2735 normalized_clk = (normalized_clk * 36) / 24;
2736 break;
2737 case COLOR_DEPTH_161616:
2738 normalized_clk = (normalized_clk * 48) / 24;
2739 break;
2740 default:
2741 return;
2742 }
2743 if (normalized_clk <= info->max_tmds_clock)
2744 return;
2745 reduce_mode_colour_depth(timing_out);
2746
2747 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2748
2749}
e7b07cee 2750
3ee6b26b
AD		 2751static void
2752fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2753 const struct drm_display_mode *mode_in,
b333730d
BL		 2754 const struct drm_connector *connector,
2755 const struct dc_stream_state *old_stream)
e7b07cee
HW		 2756{
2757 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 2758 const struct drm_display_info *info = &connector->display_info;
b830ebc9 2759
e7b07cee
HW		 2760 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2761
2762 timing_out->h_border_left = 0;
2763 timing_out->h_border_right = 0;
2764 timing_out->v_border_top = 0;
2765 timing_out->v_border_bottom = 0;
2766 /* TODO: un-hardcode */
fe61a2f1 2767 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 2768 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1
ML		 2769 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2770 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
ceb3dbb4 2771 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 2772 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2773 else
2774 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2775
2776 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2777 timing_out->display_color_depth = convert_color_depth_from_display_info(
2778 connector);
2779 timing_out->scan_type = SCANNING_TYPE_NODATA;
2780 timing_out->hdmi_vic = 0;
b333730d
BL		 2781
2782 if(old_stream) {
2783 timing_out->vic = old_stream->timing.vic;
2784 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
2785 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
2786 } else {
2787 timing_out->vic = drm_match_cea_mode(mode_in);
2788 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2789 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2790 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2791 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2792 }
e7b07cee
HW		 2793
2794 timing_out->h_addressable = mode_in->crtc_hdisplay;
2795 timing_out->h_total = mode_in->crtc_htotal;
2796 timing_out->h_sync_width =
2797 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2798 timing_out->h_front_porch =
2799 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2800 timing_out->v_total = mode_in->crtc_vtotal;
2801 timing_out->v_addressable = mode_in->crtc_vdisplay;
2802 timing_out->v_front_porch =
2803 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2804 timing_out->v_sync_width =
2805 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
380604e2 2806 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
e7b07cee 2807 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 2808
2809 stream->output_color_space = get_output_color_space(timing_out);
2810
e43a432c
AK		 2811 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2812 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ceb3dbb4 2813 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
400443e8 2814 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 2815}
2816
3ee6b26b
AD		 2817static void fill_audio_info(struct audio_info *audio_info,
2818 const struct drm_connector *drm_connector,
2819 const struct dc_sink *dc_sink)
e7b07cee
HW		 2820{
2821 int i = 0;
2822 int cea_revision = 0;
2823 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2824
2825 audio_info->manufacture_id = edid_caps->manufacturer_id;
2826 audio_info->product_id = edid_caps->product_id;
2827
2828 cea_revision = drm_connector->display_info.cea_rev;
2829
090afc1e 2830 strscpy(audio_info->display_name,
d2b2562c 2831 edid_caps->display_name,
090afc1e 2832 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 2833
b830ebc9 2834 if (cea_revision >= 3) {
e7b07cee
HW		 2835 audio_info->mode_count = edid_caps->audio_mode_count;
2836
2837 for (i = 0; i < audio_info->mode_count; ++i) {
2838 audio_info->modes[i].format_code =
2839 (enum audio_format_code)
2840 (edid_caps->audio_modes[i].format_code);
2841 audio_info->modes[i].channel_count =
2842 edid_caps->audio_modes[i].channel_count;
2843 audio_info->modes[i].sample_rates.all =
2844 edid_caps->audio_modes[i].sample_rate;
2845 audio_info->modes[i].sample_size =
2846 edid_caps->audio_modes[i].sample_size;
2847 }
2848 }
2849
2850 audio_info->flags.all = edid_caps->speaker_flags;
2851
2852 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2853 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2854 audio_info->video_latency = drm_connector->video_latency[0];
2855 audio_info->audio_latency = drm_connector->audio_latency[0];
2856 }
2857
2858 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2859
2860}
2861
3ee6b26b
AD		 2862static void
2863copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2864 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2865{
2866 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2867 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2868 dst_mode->crtc_clock = src_mode->crtc_clock;
2869 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2870 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2871 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2872 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2873 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2874 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2875 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2876 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2877 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2878 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2879 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2880}
2881
3ee6b26b
AD		 2882static void
2883decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2884 const struct drm_display_mode *native_mode,
2885 bool scale_enabled)
e7b07cee
HW		 2886{
2887 if (scale_enabled) {
2888 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2889 } else if (native_mode->clock == drm_mode->clock &&
2890 native_mode->htotal == drm_mode->htotal &&
2891 native_mode->vtotal == drm_mode->vtotal) {
2892 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2893 } else {
2894 /* no scaling nor amdgpu inserted, no need to patch */
2895 }
2896}
2897
aed15309
ML		 2898static struct dc_sink *
2899create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 2900{
2e0ac3d6 2901 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 2902 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 2903 sink_init_data.link = aconnector->dc_link;
2904 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2905
2906 sink = dc_sink_create(&sink_init_data);
423788c7 2907 if (!sink) {
2e0ac3d6 2908 DRM_ERROR("Failed to create sink!\n");
aed15309 2909 return NULL;
423788c7 2910 }
2e0ac3d6 2911 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 2912
aed15309 2913 return sink;
2e0ac3d6
HW		 2914}
2915
fa2123db
ML		 2916static void set_multisync_trigger_params(
2917 struct dc_stream_state *stream)
2918{
2919 if (stream->triggered_crtc_reset.enabled) {
2920 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2921 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2922 }
2923}
2924
2925static void set_master_stream(struct dc_stream_state *stream_set[],
2926 int stream_count)
2927{
2928 int j, highest_rfr = 0, master_stream = 0;
2929
2930 for (j = 0; j < stream_count; j++) {
2931 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2932 int refresh_rate = 0;
2933
380604e2 2934 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 2935 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2936 if (refresh_rate > highest_rfr) {
2937 highest_rfr = refresh_rate;
2938 master_stream = j;
2939 }
2940 }
2941 }
2942 for (j = 0; j < stream_count; j++) {
03736f4c 2943 if (stream_set[j])
fa2123db
ML		 2944 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2945 }
2946}
2947
2948static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2949{
2950 int i = 0;
2951
2952 if (context->stream_count < 2)
2953 return;
2954 for (i = 0; i < context->stream_count ; i++) {
2955 if (!context->streams[i])
2956 continue;
1f6010a9
DF		 2957 /*
2958 * TODO: add a function to read AMD VSDB bits and set
fa2123db 2959 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 2960 * For now it's set to false
fa2123db
ML		 2961 */
2962 set_multisync_trigger_params(context->streams[i]);
2963 }
2964 set_master_stream(context->streams, context->stream_count);
2965}
2966
3ee6b26b
AD		 2967static struct dc_stream_state *
2968create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2969 const struct drm_display_mode *drm_mode,
b333730d
BL		 2970 const struct dm_connector_state *dm_state,
2971 const struct dc_stream_state *old_stream)
e7b07cee
HW		 2972{
2973 struct drm_display_mode *preferred_mode = NULL;
391ef035 2974 struct drm_connector *drm_connector;
0971c40e 2975 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2976 struct drm_display_mode mode = *drm_mode;
2977 bool native_mode_found = false;
b333730d
BL		 2978 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
2979 int mode_refresh;
58124bf8 2980 int preferred_refresh = 0;
b333730d 2981
aed15309 2982 struct dc_sink *sink = NULL;
b830ebc9 2983 if (aconnector == NULL) {
e7b07cee 2984 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2985 return stream;
e7b07cee
HW		 2986 }
2987
e7b07cee 2988 drm_connector = &aconnector->base;
2e0ac3d6 2989
f4ac176e 2990 if (!aconnector->dc_sink) {
e3fa5c4c
JFZ		 2991 sink = create_fake_sink(aconnector);
2992 if (!sink)
2993 return stream;
aed15309
ML		 2994 } else {
2995 sink = aconnector->dc_sink;
dcd5fb82 2996 dc_sink_retain(sink);
f4ac176e 2997 }
2e0ac3d6 2998
aed15309 2999 stream = dc_create_stream_for_sink(sink);
4562236b 3000
b830ebc9 3001 if (stream == NULL) {
e7b07cee 3002 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 3003 goto finish;
e7b07cee
HW		 3004 }
3005
ceb3dbb4
JL		 3006 stream->dm_stream_context = aconnector;
3007
e7b07cee
HW		 3008 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3009 /* Search for preferred mode */
3010 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3011 native_mode_found = true;
3012 break;
3013 }
3014 }
3015 if (!native_mode_found)
3016 preferred_mode = list_first_entry_or_null(
3017 &aconnector->base.modes,
3018 struct drm_display_mode,
3019 head);
3020
b333730d
BL		 3021 mode_refresh = drm_mode_vrefresh(&mode);
3022
b830ebc9 3023 if (preferred_mode == NULL) {
1f6010a9
DF		 3024 /*
3025 * This may not be an error, the use case is when we have no
e7b07cee
HW		 3026 * usermode calls to reset and set mode upon hotplug. In this
3027 * case, we call set mode ourselves to restore the previous mode
3028 * and the modelist may not be filled in in time.
3029 */
f1ad2f5e 3030 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 3031 } else {
3032 decide_crtc_timing_for_drm_display_mode(
3033 &mode, preferred_mode,
f4791779 3034 dm_state ? (dm_state->scaling != RMX_OFF) : false);
58124bf8 3035 preferred_refresh = drm_mode_vrefresh(preferred_mode);
e7b07cee
HW		 3036 }
3037
f783577c
JFZ		 3038 if (!dm_state)
3039 drm_mode_set_crtcinfo(&mode, 0);
3040
b333730d
BL		 3041 /*
3042 * If scaling is enabled and refresh rate didn't change
3043 * we copy the vic and polarities of the old timings
3044 */
3045 if (!scale || mode_refresh != preferred_refresh)
3046 fill_stream_properties_from_drm_display_mode(stream,
3047 &mode, &aconnector->base, NULL);
3048 else
3049 fill_stream_properties_from_drm_display_mode(stream,
3050 &mode, &aconnector->base, old_stream);
3051
e7b07cee
HW		 3052 update_stream_scaling_settings(&mode, dm_state, stream);
3053
3054 fill_audio_info(
3055 &stream->audio_info,
3056 drm_connector,
aed15309 3057 sink);
e7b07cee 3058
ceb3dbb4 3059 update_stream_signal(stream, sink);
9182b4cb 3060
aed15309 3061finish:
dcd5fb82 3062 dc_sink_release(sink);
9e3efe3e 3063
e7b07cee
HW		 3064 return stream;
3065}
3066
7578ecda 3067static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 3068{
3069 drm_crtc_cleanup(crtc);
3070 kfree(crtc);
3071}
3072
3073static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 3074 struct drm_crtc_state *state)
e7b07cee
HW		 3075{
3076 struct dm_crtc_state *cur = to_dm_crtc_state(state);
3077
3078 /* TODO Destroy dc_stream objects are stream object is flattened */
3079 if (cur->stream)
3080 dc_stream_release(cur->stream);
3081
3082
3083 __drm_atomic_helper_crtc_destroy_state(state);
3084
3085
3086 kfree(state);
3087}
3088
3089static void dm_crtc_reset_state(struct drm_crtc *crtc)
3090{
3091 struct dm_crtc_state *state;
3092
3093 if (crtc->state)
3094 dm_crtc_destroy_state(crtc, crtc->state);
3095
3096 state = kzalloc(sizeof(*state), GFP_KERNEL);
3097 if (WARN_ON(!state))
3098 return;
3099
3100 crtc->state = &state->base;
3101 crtc->state->crtc = crtc;
3102
3103}
3104
3105static struct drm_crtc_state *
3106dm_crtc_duplicate_state(struct drm_crtc *crtc)
3107{
3108 struct dm_crtc_state *state, *cur;
3109
3110 cur = to_dm_crtc_state(crtc->state);
3111
3112 if (WARN_ON(!crtc->state))
3113 return NULL;
3114
2004f45e 3115 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 3116 if (!state)
3117 return NULL;
e7b07cee
HW		 3118
3119 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3120
3121 if (cur->stream) {
3122 state->stream = cur->stream;
3123 dc_stream_retain(state->stream);
3124 }
3125
180db303 3126 state->vrr_params = cur->vrr_params;
98e6436d 3127 state->vrr_infopacket = cur->vrr_infopacket;
c1ee92f9 3128 state->abm_level = cur->abm_level;
bb47de73
NK		 3129 state->vrr_supported = cur->vrr_supported;
3130 state->freesync_config = cur->freesync_config;
ed20dc0d 3131 state->crc_enabled = cur->crc_enabled;
98e6436d 3132
e7b07cee
HW		 3133 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3134
3135 return &state->base;
3136}
3137
589d2739
HW		 3138
3139static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3140{
3141 enum dc_irq_source irq_source;
3142 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3143 struct amdgpu_device *adev = crtc->dev->dev_private;
3144
3145 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 3146 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 3147}
3148
3149static int dm_enable_vblank(struct drm_crtc *crtc)
3150{
3151 return dm_set_vblank(crtc, true);
3152}
3153
3154static void dm_disable_vblank(struct drm_crtc *crtc)
3155{
3156 dm_set_vblank(crtc, false);
3157}
3158
e7b07cee
HW		 3159/* Implemented only the options currently availible for the driver */
3160static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3161 .reset = dm_crtc_reset_state,
3162 .destroy = amdgpu_dm_crtc_destroy,
3163 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3164 .set_config = drm_atomic_helper_set_config,
3165 .page_flip = drm_atomic_helper_page_flip,
3166 .atomic_duplicate_state = dm_crtc_duplicate_state,
3167 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 3168 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 3169 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
589d2739
HW		 3170 .enable_vblank = dm_enable_vblank,
3171 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 3172};
3173
3174static enum drm_connector_status
3175amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3176{
3177 bool connected;
c84dec2f 3178 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 3179
1f6010a9
DF		 3180 /*
3181 * Notes:
e7b07cee
HW		 3182 * 1. This interface is NOT called in context of HPD irq.
3183 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 3184 * makes it a bad place for *any* MST-related activity.
3185 */
e7b07cee 3186
8580d60b
HW		 3187 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3188 !aconnector->fake_enable)
e7b07cee
HW		 3189 connected = (aconnector->dc_sink != NULL);
3190 else
3191 connected = (aconnector->base.force == DRM_FORCE_ON);
3192
3193 return (connected ? connector_status_connected :
3194 connector_status_disconnected);
3195}
3196
3ee6b26b
AD		 3197int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3198 struct drm_connector_state *connector_state,
3199 struct drm_property *property,
3200 uint64_t val)
e7b07cee
HW		 3201{
3202 struct drm_device *dev = connector->dev;
3203 struct amdgpu_device *adev = dev->dev_private;
3204 struct dm_connector_state *dm_old_state =
3205 to_dm_connector_state(connector->state);
3206 struct dm_connector_state *dm_new_state =
3207 to_dm_connector_state(connector_state);
3208
3209 int ret = -EINVAL;
3210
3211 if (property == dev->mode_config.scaling_mode_property) {
3212 enum amdgpu_rmx_type rmx_type;
3213
3214 switch (val) {
3215 case DRM_MODE_SCALE_CENTER:
3216 rmx_type = RMX_CENTER;
3217 break;
3218 case DRM_MODE_SCALE_ASPECT:
3219 rmx_type = RMX_ASPECT;
3220 break;
3221 case DRM_MODE_SCALE_FULLSCREEN:
3222 rmx_type = RMX_FULL;
3223 break;
3224 case DRM_MODE_SCALE_NONE:
3225 default:
3226 rmx_type = RMX_OFF;
3227 break;
3228 }
3229
3230 if (dm_old_state->scaling == rmx_type)
3231 return 0;
3232
3233 dm_new_state->scaling = rmx_type;
3234 ret = 0;
3235 } else if (property == adev->mode_info.underscan_hborder_property) {
3236 dm_new_state->underscan_hborder = val;
3237 ret = 0;
3238 } else if (property == adev->mode_info.underscan_vborder_property) {
3239 dm_new_state->underscan_vborder = val;
3240 ret = 0;
3241 } else if (property == adev->mode_info.underscan_property) {
3242 dm_new_state->underscan_enable = val;
3243 ret = 0;
07e3a1cf
NK		 3244 } else if (property == adev->mode_info.max_bpc_property) {
3245 dm_new_state->max_bpc = val;
3246 ret = 0;
c1ee92f9
DF		 3247 } else if (property == adev->mode_info.abm_level_property) {
3248 dm_new_state->abm_level = val;
3249 ret = 0;
e7b07cee
HW		 3250 }
3251
3252 return ret;
3253}
3254
3ee6b26b
AD		 3255int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3256 const struct drm_connector_state *state,
3257 struct drm_property *property,
3258 uint64_t *val)
e7b07cee
HW		 3259{
3260 struct drm_device *dev = connector->dev;
3261 struct amdgpu_device *adev = dev->dev_private;
3262 struct dm_connector_state *dm_state =
3263 to_dm_connector_state(state);
3264 int ret = -EINVAL;
3265
3266 if (property == dev->mode_config.scaling_mode_property) {
3267 switch (dm_state->scaling) {
3268 case RMX_CENTER:
3269 *val = DRM_MODE_SCALE_CENTER;
3270 break;
3271 case RMX_ASPECT:
3272 *val = DRM_MODE_SCALE_ASPECT;
3273 break;
3274 case RMX_FULL:
3275 *val = DRM_MODE_SCALE_FULLSCREEN;
3276 break;
3277 case RMX_OFF:
3278 default:
3279 *val = DRM_MODE_SCALE_NONE;
3280 break;
3281 }
3282 ret = 0;
3283 } else if (property == adev->mode_info.underscan_hborder_property) {
3284 *val = dm_state->underscan_hborder;
3285 ret = 0;
3286 } else if (property == adev->mode_info.underscan_vborder_property) {
3287 *val = dm_state->underscan_vborder;
3288 ret = 0;
3289 } else if (property == adev->mode_info.underscan_property) {
3290 *val = dm_state->underscan_enable;
3291 ret = 0;
07e3a1cf
NK		 3292 } else if (property == adev->mode_info.max_bpc_property) {
3293 *val = dm_state->max_bpc;
3294 ret = 0;
c1ee92f9
DF		 3295 } else if (property == adev->mode_info.abm_level_property) {
3296 *val = dm_state->abm_level;
3297 ret = 0;
e7b07cee 3298 }
c1ee92f9 3299
e7b07cee
HW		 3300 return ret;
3301}
3302
7578ecda 3303static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 3304{
c84dec2f 3305 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3306 const struct dc_link *link = aconnector->dc_link;
3307 struct amdgpu_device *adev = connector->dev->dev_private;
3308 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 3309
e7b07cee
HW		 3310#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3311 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3312
89fc8d4e 3313 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 3314 link->type != dc_connection_none &&
3315 dm->backlight_dev) {
3316 backlight_device_unregister(dm->backlight_dev);
3317 dm->backlight_dev = NULL;
e7b07cee
HW		 3318 }
3319#endif
dcd5fb82
MF		 3320
3321 if (aconnector->dc_em_sink)
3322 dc_sink_release(aconnector->dc_em_sink);
3323 aconnector->dc_em_sink = NULL;
3324 if (aconnector->dc_sink)
3325 dc_sink_release(aconnector->dc_sink);
3326 aconnector->dc_sink = NULL;
3327
e86e8947 3328 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 3329 drm_connector_unregister(connector);
3330 drm_connector_cleanup(connector);
3331 kfree(connector);
3332}
3333
3334void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3335{
3336 struct dm_connector_state *state =
3337 to_dm_connector_state(connector->state);
3338
df099b9b
LSL		 3339 if (connector->state)
3340 __drm_atomic_helper_connector_destroy_state(connector->state);
3341
e7b07cee
HW		 3342 kfree(state);
3343
3344 state = kzalloc(sizeof(*state), GFP_KERNEL);
3345
3346 if (state) {
3347 state->scaling = RMX_OFF;
3348 state->underscan_enable = false;
3349 state->underscan_hborder = 0;
3350 state->underscan_vborder = 0;
49f1c44b 3351 state->max_bpc = 8;
e7b07cee 3352
df099b9b 3353 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 3354 }
3355}
3356
3ee6b26b
AD		 3357struct drm_connector_state *
3358amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 3359{
3360 struct dm_connector_state *state =
3361 to_dm_connector_state(connector->state);
3362
3363 struct dm_connector_state *new_state =
3364 kmemdup(state, sizeof(*state), GFP_KERNEL);
3365
98e6436d
AK		 3366 if (!new_state)
3367 return NULL;
e7b07cee 3368
98e6436d
AK		 3369 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3370
3371 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 3372 new_state->abm_level = state->abm_level;
922454c2
NK		 3373 new_state->scaling = state->scaling;
3374 new_state->underscan_enable = state->underscan_enable;
3375 new_state->underscan_hborder = state->underscan_hborder;
3376 new_state->underscan_vborder = state->underscan_vborder;
49f1c44b 3377 new_state->max_bpc = state->max_bpc;
98e6436d
AK		 3378
3379 return &new_state->base;
e7b07cee
HW		 3380}
3381
3382static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3383 .reset = amdgpu_dm_connector_funcs_reset,
3384 .detect = amdgpu_dm_connector_detect,
3385 .fill_modes = drm_helper_probe_single_connector_modes,
3386 .destroy = amdgpu_dm_connector_destroy,
3387 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3388 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3389 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3390 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3391};
3392
e7b07cee
HW		 3393static int get_modes(struct drm_connector *connector)
3394{
3395 return amdgpu_dm_connector_get_modes(connector);
3396}
3397
c84dec2f 3398static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3399{
3400 struct dc_sink_init_data init_params = {
3401 .link = aconnector->dc_link,
3402 .sink_signal = SIGNAL_TYPE_VIRTUAL
3403 };
70e8ffc5 3404 struct edid *edid;
e7b07cee 3405
a89ff457 3406 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 3407 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3408 aconnector->base.name);
3409
3410 aconnector->base.force = DRM_FORCE_OFF;
3411 aconnector->base.override_edid = false;
3412 return;
3413 }
3414
70e8ffc5
HW		 3415 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3416
e7b07cee
HW		 3417 aconnector->edid = edid;
3418
3419 aconnector->dc_em_sink = dc_link_add_remote_sink(
3420 aconnector->dc_link,
3421 (uint8_t *)edid,
3422 (edid->extensions + 1) * EDID_LENGTH,
3423 &init_params);
3424
dcd5fb82 3425 if (aconnector->base.force == DRM_FORCE_ON) {
e7b07cee
HW		 3426 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3427 aconnector->dc_link->local_sink :
3428 aconnector->dc_em_sink;
dcd5fb82
MF		 3429 dc_sink_retain(aconnector->dc_sink);
3430 }
e7b07cee
HW		 3431}
3432
c84dec2f 3433static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3434{
3435 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3436
1f6010a9
DF		 3437 /*
3438 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 3439 * Those settings have to be != 0 to get initial modeset
3440 */
3441 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3442 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3443 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3444 }
3445
3446
3447 aconnector->base.override_edid = true;
3448 create_eml_sink(aconnector);
3449}
3450
ba9ca088 3451enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 3452 struct drm_display_mode *mode)
e7b07cee
HW		 3453{
3454 int result = MODE_ERROR;
3455 struct dc_sink *dc_sink;
3456 struct amdgpu_device *adev = connector->dev->dev_private;
3457 /* TODO: Unhardcode stream count */
0971c40e 3458 struct dc_stream_state *stream;
c84dec2f 3459 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 3460 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 3461
3462 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3463 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3464 return result;
3465
1f6010a9
DF		 3466 /*
3467 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 3468 * EDID mgmt
3469 */
3470 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3471 !aconnector->dc_em_sink)
3472 handle_edid_mgmt(aconnector);
3473
c84dec2f 3474 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 3475
b830ebc9 3476 if (dc_sink == NULL) {
e7b07cee
HW		 3477 DRM_ERROR("dc_sink is NULL!\n");
3478 goto fail;
3479 }
3480
b333730d 3481 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
b830ebc9 3482 if (stream == NULL) {
e7b07cee
HW		 3483 DRM_ERROR("Failed to create stream for sink!\n");
3484 goto fail;
3485 }
3486
a39438f0
HW		 3487 dc_result = dc_validate_stream(adev->dm.dc, stream);
3488
3489 if (dc_result == DC_OK)
e7b07cee 3490 result = MODE_OK;
a39438f0 3491 else
9f921b14 3492 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 3493 mode->vdisplay,
3494 mode->hdisplay,
9f921b14
HW		 3495 mode->clock,
3496 dc_result);
e7b07cee
HW		 3497
3498 dc_stream_release(stream);
3499
3500fail:
3501 /* TODO: error handling*/
3502 return result;
3503}
3504
3505static const struct drm_connector_helper_funcs
3506amdgpu_dm_connector_helper_funcs = {
3507 /*
1f6010a9 3508 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 3509 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 3510 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 3511 * in get_modes call back, not just return the modes count
3512 */
e7b07cee
HW		 3513 .get_modes = get_modes,
3514 .mode_valid = amdgpu_dm_connector_mode_valid,
e7b07cee
HW		 3515};
3516
3517static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3518{
3519}
3520
3ee6b26b
AD		 3521static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3522 struct drm_crtc_state *state)
e7b07cee
HW		 3523{
3524 struct amdgpu_device *adev = crtc->dev->dev_private;
3525 struct dc *dc = adev->dm.dc;
3526 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3527 int ret = -EINVAL;
3528
9b690ef3
BL		 3529 if (unlikely(!dm_crtc_state->stream &&
3530 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 3531 WARN_ON(1);
3532 return ret;
3533 }
3534
1f6010a9 3535 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 3536 if (!dm_crtc_state->stream)
3537 return 0;
3538
62c933f9 3539 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 3540 return 0;
3541
3542 return ret;
3543}
3544
3ee6b26b
AD		 3545static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3546 const struct drm_display_mode *mode,
3547 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 3548{
3549 return true;
3550}
3551
3552static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3553 .disable = dm_crtc_helper_disable,
3554 .atomic_check = dm_crtc_helper_atomic_check,
3555 .mode_fixup = dm_crtc_helper_mode_fixup
3556};
3557
3558static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3559{
3560
3561}
3562
3ee6b26b
AD		 3563static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3564 struct drm_crtc_state *crtc_state,
3565 struct drm_connector_state *conn_state)
e7b07cee
HW		 3566{
3567 return 0;
3568}
3569
3570const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3571 .disable = dm_encoder_helper_disable,
3572 .atomic_check = dm_encoder_helper_atomic_check
3573};
3574
3575static void dm_drm_plane_reset(struct drm_plane *plane)
3576{
3577 struct dm_plane_state *amdgpu_state = NULL;
3578
3579 if (plane->state)
3580 plane->funcs->atomic_destroy_state(plane, plane->state);
3581
3582 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 3583 WARN_ON(amdgpu_state == NULL);
1f6010a9 3584
e7b07cee
HW		 3585 if (amdgpu_state) {
3586 plane->state = &amdgpu_state->base;
3587 plane->state->plane = plane;
3588 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 3589 }
e7b07cee
HW		 3590}
3591
3592static struct drm_plane_state *
3593dm_drm_plane_duplicate_state(struct drm_plane *plane)
3594{
3595 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3596
3597 old_dm_plane_state = to_dm_plane_state(plane->state);
3598 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3599 if (!dm_plane_state)
3600 return NULL;
3601
3602 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3603
3be5262e
HW		 3604 if (old_dm_plane_state->dc_state) {
3605 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3606 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 3607 }
3608
3609 return &dm_plane_state->base;
3610}
3611
3612void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 3613 struct drm_plane_state *state)
e7b07cee
HW		 3614{
3615 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3616
3be5262e
HW		 3617 if (dm_plane_state->dc_state)
3618 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 3619
0627bbd3 3620 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 3621}
3622
3623static const struct drm_plane_funcs dm_plane_funcs = {
3624 .update_plane = drm_atomic_helper_update_plane,
3625 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 3626 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 3627 .reset = dm_drm_plane_reset,
3628 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3629 .atomic_destroy_state = dm_drm_plane_destroy_state,
3630};
3631
3ee6b26b
AD		 3632static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3633 struct drm_plane_state *new_state)
e7b07cee
HW		 3634{
3635 struct amdgpu_framebuffer *afb;
3636 struct drm_gem_object *obj;
5d43be0c 3637 struct amdgpu_device *adev;
e7b07cee 3638 struct amdgpu_bo *rbo;
56087b31 3639 uint64_t chroma_addr = 0;
e7b07cee 3640 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
7df7e505 3641 uint64_t tiling_flags, dcc_address;
e7b07cee 3642 unsigned int awidth;
5d43be0c
CK		 3643 uint32_t domain;
3644 int r;
e7b07cee
HW		 3645
3646 dm_plane_state_old = to_dm_plane_state(plane->state);
3647 dm_plane_state_new = to_dm_plane_state(new_state);
3648
3649 if (!new_state->fb) {
f1ad2f5e 3650 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3651 return 0;
3652 }
3653
3654 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 3655 obj = new_state->fb->obj[0];
e7b07cee 3656 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3657 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3658 r = amdgpu_bo_reserve(rbo, false);
3659 if (unlikely(r != 0))
3660 return r;
3661
5d43be0c 3662 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 3663 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 3664 else
3665 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3666
7b7c6c81 3667 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 3668 if (unlikely(r != 0)) {
30b7c614
HW		 3669 if (r != -ERESTARTSYS)
3670 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
bb812f1e 3671 amdgpu_bo_unreserve(rbo);
e7b07cee
HW		 3672 return r;
3673 }
3674
bb812f1e
JZ		 3675 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3676 if (unlikely(r != 0)) {
3677 amdgpu_bo_unpin(rbo);
3678 amdgpu_bo_unreserve(rbo);
3679 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 3680 return r;
3681 }
7df7e505
NK		 3682
3683 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
3684
bb812f1e
JZ		 3685 amdgpu_bo_unreserve(rbo);
3686
7b7c6c81 3687 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 3688
3689 amdgpu_bo_ref(rbo);
3690
3be5262e
HW		 3691 if (dm_plane_state_new->dc_state &&
3692 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3693 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3694
3be5262e
HW		 3695 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3696 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3697 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
7df7e505
NK		 3698
3699 dcc_address =
3700 get_dcc_address(afb->address, tiling_flags);
3701 plane_state->address.grph.meta_addr.low_part =
3702 lower_32_bits(dcc_address);
3703 plane_state->address.grph.meta_addr.high_part =
3704 upper_32_bits(dcc_address);
e7b07cee
HW		 3705 } else {
3706 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3707 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3708 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3709 = lower_32_bits(afb->address);
56087b31
S		 3710 plane_state->address.video_progressive.luma_addr.high_part
3711 = upper_32_bits(afb->address);
35888630 3712 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3713 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3714 = lower_32_bits(chroma_addr);
3715 plane_state->address.video_progressive.chroma_addr.high_part
3716 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3717 }
3718 }
3719
e7b07cee
HW		 3720 return 0;
3721}
3722
3ee6b26b
AD		 3723static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3724 struct drm_plane_state *old_state)
e7b07cee
HW		 3725{
3726 struct amdgpu_bo *rbo;
e7b07cee
HW		 3727 int r;
3728
3729 if (!old_state->fb)
3730 return;
3731
e68d14dd 3732 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 3733 r = amdgpu_bo_reserve(rbo, false);
3734 if (unlikely(r)) {
3735 DRM_ERROR("failed to reserve rbo before unpin\n");
3736 return;
b830ebc9
HW		 3737 }
3738
3739 amdgpu_bo_unpin(rbo);
3740 amdgpu_bo_unreserve(rbo);
3741 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3742}
3743
7578ecda
AD		 3744static int dm_plane_atomic_check(struct drm_plane *plane,
3745 struct drm_plane_state *state)
cbd19488
AG		 3746{
3747 struct amdgpu_device *adev = plane->dev->dev_private;
3748 struct dc *dc = adev->dm.dc;
3749 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3750
3be5262e 3751 if (!dm_plane_state->dc_state)
9a3329b1 3752 return 0;
cbd19488 3753
a05bcff1
S		 3754 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3755 return -EINVAL;
3756
62c933f9 3757 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3758 return 0;
3759
3760 return -EINVAL;
3761}
3762
674e78ac
NK		 3763static int dm_plane_atomic_async_check(struct drm_plane *plane,
3764 struct drm_plane_state *new_plane_state)
3765{
77acd1cd
NK		 3766 struct drm_plane_state *old_plane_state =
3767 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
3768
674e78ac
NK		 3769 /* Only support async updates on cursor planes. */
3770 if (plane->type != DRM_PLANE_TYPE_CURSOR)
3771 return -EINVAL;
3772
77acd1cd
NK		 3773 /*
3774 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
3775 * async commits so don't allow fb changes.
3776 */
3777 if (old_plane_state->fb != new_plane_state->fb)
3778 return -EINVAL;
3779
674e78ac
NK		 3780 return 0;
3781}
3782
3783static void dm_plane_atomic_async_update(struct drm_plane *plane,
3784 struct drm_plane_state *new_state)
3785{
3786 struct drm_plane_state *old_state =
3787 drm_atomic_get_old_plane_state(new_state->state, plane);
3788
3789 if (plane->state->fb != new_state->fb)
3790 drm_atomic_set_fb_for_plane(plane->state, new_state->fb);
3791
3792 plane->state->src_x = new_state->src_x;
3793 plane->state->src_y = new_state->src_y;
3794 plane->state->src_w = new_state->src_w;
3795 plane->state->src_h = new_state->src_h;
3796 plane->state->crtc_x = new_state->crtc_x;
3797 plane->state->crtc_y = new_state->crtc_y;
3798 plane->state->crtc_w = new_state->crtc_w;
3799 plane->state->crtc_h = new_state->crtc_h;
3800
3801 handle_cursor_update(plane, old_state);
3802}
3803
e7b07cee
HW		 3804static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3805 .prepare_fb = dm_plane_helper_prepare_fb,
3806 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3807 .atomic_check = dm_plane_atomic_check,
674e78ac
NK		 3808 .atomic_async_check = dm_plane_atomic_async_check,
3809 .atomic_async_update = dm_plane_atomic_async_update
e7b07cee
HW		 3810};
3811
3812/*
3813 * TODO: these are currently initialized to rgb formats only.
3814 * For future use cases we should either initialize them dynamically based on
3815 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 3816 * check will succeed, and let DC implement proper check
e7b07cee 3817 */
d90371b0 3818static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3819 DRM_FORMAT_XRGB8888,
3820 DRM_FORMAT_ARGB8888,
3821 DRM_FORMAT_RGBA8888,
3822 DRM_FORMAT_XRGB2101010,
3823 DRM_FORMAT_XBGR2101010,
3824 DRM_FORMAT_ARGB2101010,
3825 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 3826 DRM_FORMAT_XBGR8888,
3827 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 3828};
3829
99d1abf8 3830static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3831 DRM_FORMAT_NV12,
3832 DRM_FORMAT_NV21,
3833};
3834
3835static const u32 cursor_formats[] = {
3836 DRM_FORMAT_ARGB8888
3837};
3838
7578ecda 3839static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 3840 struct drm_plane *plane,
7578ecda 3841 unsigned long possible_crtcs)
e7b07cee
HW		 3842{
3843 int res = -EPERM;
3844
f180b4bc 3845 switch (plane->type) {
e7b07cee 3846 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3847 res = drm_universal_plane_init(
3848 dm->adev->ddev,
f180b4bc 3849 plane,
e7b07cee
HW		 3850 possible_crtcs,
3851 &dm_plane_funcs,
3852 rgb_formats,
3853 ARRAY_SIZE(rgb_formats),
f180b4bc 3854 NULL, plane->type, NULL);
e7b07cee
HW		 3855 break;
3856 case DRM_PLANE_TYPE_OVERLAY:
3857 res = drm_universal_plane_init(
3858 dm->adev->ddev,
f180b4bc 3859 plane,
e7b07cee
HW		 3860 possible_crtcs,
3861 &dm_plane_funcs,
3862 yuv_formats,
3863 ARRAY_SIZE(yuv_formats),
f180b4bc 3864 NULL, plane->type, NULL);
e7b07cee
HW		 3865 break;
3866 case DRM_PLANE_TYPE_CURSOR:
3867 res = drm_universal_plane_init(
3868 dm->adev->ddev,
f180b4bc 3869 plane,
e7b07cee
HW		 3870 possible_crtcs,
3871 &dm_plane_funcs,
3872 cursor_formats,
3873 ARRAY_SIZE(cursor_formats),
f180b4bc 3874 NULL, plane->type, NULL);
e7b07cee
HW		 3875 break;
3876 }
3877
f180b4bc 3878 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 3879
96719c54 3880 /* Create (reset) the plane state */
f180b4bc
HW		 3881 if (plane->funcs->reset)
3882 plane->funcs->reset(plane);
96719c54
HW		 3883
3884
e7b07cee
HW		 3885 return res;
3886}
3887
7578ecda
AD		 3888static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3889 struct drm_plane *plane,
3890 uint32_t crtc_index)
e7b07cee
HW		 3891{
3892 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 3893 struct drm_plane *cursor_plane;
e7b07cee
HW		 3894
3895 int res = -ENOMEM;
3896
3897 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3898 if (!cursor_plane)
3899 goto fail;
3900
f180b4bc 3901 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
e7b07cee
HW		 3902 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3903
3904 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3905 if (!acrtc)
3906 goto fail;
3907
3908 res = drm_crtc_init_with_planes(
3909 dm->ddev,
3910 &acrtc->base,
3911 plane,
f180b4bc 3912 cursor_plane,
e7b07cee
HW		 3913 &amdgpu_dm_crtc_funcs, NULL);
3914
3915 if (res)
3916 goto fail;
3917
3918 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3919
96719c54
HW		 3920 /* Create (reset) the plane state */
3921 if (acrtc->base.funcs->reset)
3922 acrtc->base.funcs->reset(&acrtc->base);
3923
e7b07cee
HW		 3924 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3925 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3926
3927 acrtc->crtc_id = crtc_index;
3928 acrtc->base.enabled = false;
c37e2d29 3929 acrtc->otg_inst = -1;
e7b07cee
HW		 3930
3931 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3932 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3933 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3934 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3935
3936 return 0;
3937
3938fail:
b830ebc9
HW		 3939 kfree(acrtc);
3940 kfree(cursor_plane);
e7b07cee
HW		 3941 return res;
3942}
3943
3944
3945static int to_drm_connector_type(enum signal_type st)
3946{
3947 switch (st) {
3948 case SIGNAL_TYPE_HDMI_TYPE_A:
3949 return DRM_MODE_CONNECTOR_HDMIA;
3950 case SIGNAL_TYPE_EDP:
3951 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 3952 case SIGNAL_TYPE_LVDS:
3953 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 3954 case SIGNAL_TYPE_RGB:
3955 return DRM_MODE_CONNECTOR_VGA;
3956 case SIGNAL_TYPE_DISPLAY_PORT:
3957 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3958 return DRM_MODE_CONNECTOR_DisplayPort;
3959 case SIGNAL_TYPE_DVI_DUAL_LINK:
3960 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3961 return DRM_MODE_CONNECTOR_DVID;
3962 case SIGNAL_TYPE_VIRTUAL:
3963 return DRM_MODE_CONNECTOR_VIRTUAL;
3964
3965 default:
3966 return DRM_MODE_CONNECTOR_Unknown;
3967 }
3968}
3969
2b4c1c05
DV		 3970static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
3971{
3972 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
3973}
3974
e7b07cee
HW		 3975static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3976{
e7b07cee
HW		 3977 struct drm_encoder *encoder;
3978 struct amdgpu_encoder *amdgpu_encoder;
3979
2b4c1c05 3980 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 3981
3982 if (encoder == NULL)
3983 return;
3984
3985 amdgpu_encoder = to_amdgpu_encoder(encoder);
3986
3987 amdgpu_encoder->native_mode.clock = 0;
3988
3989 if (!list_empty(&connector->probed_modes)) {
3990 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3991
e7b07cee 3992 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3993 &connector->probed_modes,
3994 head) {
3995 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3996 amdgpu_encoder->native_mode = *preferred_mode;
3997
e7b07cee
HW		 3998 break;
3999 }
4000
4001 }
4002}
4003
3ee6b26b
AD		 4004static struct drm_display_mode *
4005amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4006 char *name,
4007 int hdisplay, int vdisplay)
e7b07cee
HW		 4008{
4009 struct drm_device *dev = encoder->dev;
4010 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4011 struct drm_display_mode *mode = NULL;
4012 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4013
4014 mode = drm_mode_duplicate(dev, native_mode);
4015
b830ebc9 4016 if (mode == NULL)
e7b07cee
HW		 4017 return NULL;
4018
4019 mode->hdisplay = hdisplay;
4020 mode->vdisplay = vdisplay;
4021 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 4022 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 4023
4024 return mode;
4025
4026}
4027
4028static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 4029 struct drm_connector *connector)
e7b07cee
HW		 4030{
4031 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4032 struct drm_display_mode *mode = NULL;
4033 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 4034 struct amdgpu_dm_connector *amdgpu_dm_connector =
4035 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4036 int i;
4037 int n;
4038 struct mode_size {
4039 char name[DRM_DISPLAY_MODE_LEN];
4040 int w;
4041 int h;
b830ebc9 4042 } common_modes[] = {
e7b07cee
HW		 4043 { "640x480", 640, 480},
4044 { "800x600", 800, 600},
4045 { "1024x768", 1024, 768},
4046 { "1280x720", 1280, 720},
4047 { "1280x800", 1280, 800},
4048 {"1280x1024", 1280, 1024},
4049 { "1440x900", 1440, 900},
4050 {"1680x1050", 1680, 1050},
4051 {"1600x1200", 1600, 1200},
4052 {"1920x1080", 1920, 1080},
4053 {"1920x1200", 1920, 1200}
4054 };
4055
b830ebc9 4056 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 4057
4058 for (i = 0; i < n; i++) {
4059 struct drm_display_mode *curmode = NULL;
4060 bool mode_existed = false;
4061
4062 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 4063 common_modes[i].h > native_mode->vdisplay ||
4064 (common_modes[i].w == native_mode->hdisplay &&
4065 common_modes[i].h == native_mode->vdisplay))
4066 continue;
e7b07cee
HW		 4067
4068 list_for_each_entry(curmode, &connector->probed_modes, head) {
4069 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 4070 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 4071 mode_existed = true;
4072 break;
4073 }
4074 }
4075
4076 if (mode_existed)
4077 continue;
4078
4079 mode = amdgpu_dm_create_common_mode(encoder,
4080 common_modes[i].name, common_modes[i].w,
4081 common_modes[i].h);
4082 drm_mode_probed_add(connector, mode);
c84dec2f 4083 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 4084 }
4085}
4086
3ee6b26b
AD		 4087static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4088 struct edid *edid)
e7b07cee 4089{
c84dec2f
HW		 4090 struct amdgpu_dm_connector *amdgpu_dm_connector =
4091 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4092
4093 if (edid) {
4094 /* empty probed_modes */
4095 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 4096 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 4097 drm_add_edid_modes(connector, edid);
4098
e7b07cee 4099 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 4100 } else {
c84dec2f 4101 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 4102 }
e7b07cee
HW		 4103}
4104
7578ecda 4105static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 4106{
c84dec2f
HW		 4107 struct amdgpu_dm_connector *amdgpu_dm_connector =
4108 to_amdgpu_dm_connector(connector);
e7b07cee 4109 struct drm_encoder *encoder;
c84dec2f 4110 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 4111
2b4c1c05 4112 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 4113
85ee15d6 4114 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 4115 amdgpu_dm_connector->num_modes =
4116 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 4117 } else {
4118 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4119 amdgpu_dm_connector_add_common_modes(encoder, connector);
4120 }
3e332d3a 4121 amdgpu_dm_fbc_init(connector);
5099114b 4122
c84dec2f 4123 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 4124}
4125
3ee6b26b
AD		 4126void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4127 struct amdgpu_dm_connector *aconnector,
4128 int connector_type,
4129 struct dc_link *link,
4130 int link_index)
e7b07cee
HW		 4131{
4132 struct amdgpu_device *adev = dm->ddev->dev_private;
4133
4134 aconnector->connector_id = link_index;
4135 aconnector->dc_link = link;
4136 aconnector->base.interlace_allowed = false;
4137 aconnector->base.doublescan_allowed = false;
4138 aconnector->base.stereo_allowed = false;
4139 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4140 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
e7b07cee
HW		 4141 mutex_init(&aconnector->hpd_lock);
4142
1f6010a9
DF		 4143 /*
4144 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 4145 * which means HPD hot plug not supported
4146 */
e7b07cee
HW		 4147 switch (connector_type) {
4148 case DRM_MODE_CONNECTOR_HDMIA:
4149 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4150 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4151 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 4152 break;
4153 case DRM_MODE_CONNECTOR_DisplayPort:
4154 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4155 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4156 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 4157 break;
4158 case DRM_MODE_CONNECTOR_DVID:
4159 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4160 break;
4161 default:
4162 break;
4163 }
4164
4165 drm_object_attach_property(&aconnector->base.base,
4166 dm->ddev->mode_config.scaling_mode_property,
4167 DRM_MODE_SCALE_NONE);
4168
4169 drm_object_attach_property(&aconnector->base.base,
4170 adev->mode_info.underscan_property,
4171 UNDERSCAN_OFF);
4172 drm_object_attach_property(&aconnector->base.base,
4173 adev->mode_info.underscan_hborder_property,
4174 0);
4175 drm_object_attach_property(&aconnector->base.base,
4176 adev->mode_info.underscan_vborder_property,
4177 0);
07e3a1cf
NK		 4178 drm_object_attach_property(&aconnector->base.base,
4179 adev->mode_info.max_bpc_property,
4180 0);
e7b07cee 4181
c1ee92f9
DF		 4182 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4183 dc_is_dmcu_initialized(adev->dm.dc)) {
4184 drm_object_attach_property(&aconnector->base.base,
4185 adev->mode_info.abm_level_property, 0);
4186 }
bb47de73
NK		 4187
4188 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7fad8da1
NK		 4189 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4190 connector_type == DRM_MODE_CONNECTOR_eDP) {
bb47de73
NK		 4191 drm_connector_attach_vrr_capable_property(
4192 &aconnector->base);
4193 }
e7b07cee
HW		 4194}
4195
7578ecda
AD		 4196static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4197 struct i2c_msg *msgs, int num)
e7b07cee
HW		 4198{
4199 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4200 struct ddc_service *ddc_service = i2c->ddc_service;
4201 struct i2c_command cmd;
4202 int i;
4203 int result = -EIO;
4204
b830ebc9 4205 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 4206
4207 if (!cmd.payloads)
4208 return result;
4209
4210 cmd.number_of_payloads = num;
4211 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4212 cmd.speed = 100;
4213
4214 for (i = 0; i < num; i++) {
4215 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4216 cmd.payloads[i].address = msgs[i].addr;
4217 cmd.payloads[i].length = msgs[i].len;
4218 cmd.payloads[i].data = msgs[i].buf;
4219 }
4220
c85e6e54
DF		 4221 if (dc_submit_i2c(
4222 ddc_service->ctx->dc,
4223 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 4224 &cmd))
4225 result = num;
4226
4227 kfree(cmd.payloads);
4228 return result;
4229}
4230
7578ecda 4231static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 4232{
4233 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4234}
4235
4236static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4237 .master_xfer = amdgpu_dm_i2c_xfer,
4238 .functionality = amdgpu_dm_i2c_func,
4239};
4240
3ee6b26b
AD		 4241static struct amdgpu_i2c_adapter *
4242create_i2c(struct ddc_service *ddc_service,
4243 int link_index,
4244 int *res)
e7b07cee
HW		 4245{
4246 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4247 struct amdgpu_i2c_adapter *i2c;
4248
b830ebc9 4249 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 4250 if (!i2c)
4251 return NULL;
e7b07cee
HW		 4252 i2c->base.owner = THIS_MODULE;
4253 i2c->base.class = I2C_CLASS_DDC;
4254 i2c->base.dev.parent = &adev->pdev->dev;
4255 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 4256 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 4257 i2c_set_adapdata(&i2c->base, i2c);
4258 i2c->ddc_service = ddc_service;
c85e6e54 4259 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 4260
4261 return i2c;
4262}
4263
89fc8d4e 4264
1f6010a9
DF		 4265/*
4266 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 4267 * dc_link which will be represented by this aconnector.
4268 */
7578ecda
AD		 4269static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4270 struct amdgpu_dm_connector *aconnector,
4271 uint32_t link_index,
4272 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 4273{
4274 int res = 0;
4275 int connector_type;
4276 struct dc *dc = dm->dc;
4277 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4278 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 4279
4280 link->priv = aconnector;
e7b07cee 4281
f1ad2f5e 4282 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 4283
4284 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 4285 if (!i2c) {
4286 DRM_ERROR("Failed to create i2c adapter data\n");
4287 return -ENOMEM;
4288 }
4289
e7b07cee
HW		 4290 aconnector->i2c = i2c;
4291 res = i2c_add_adapter(&i2c->base);
4292
4293 if (res) {
4294 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4295 goto out_free;
4296 }
4297
4298 connector_type = to_drm_connector_type(link->connector_signal);
4299
4300 res = drm_connector_init(
4301 dm->ddev,
4302 &aconnector->base,
4303 &amdgpu_dm_connector_funcs,
4304 connector_type);
4305
4306 if (res) {
4307 DRM_ERROR("connector_init failed\n");
4308 aconnector->connector_id = -1;
4309 goto out_free;
4310 }
4311
4312 drm_connector_helper_add(
4313 &aconnector->base,
4314 &amdgpu_dm_connector_helper_funcs);
4315
96719c54
HW		 4316 if (aconnector->base.funcs->reset)
4317 aconnector->base.funcs->reset(&aconnector->base);
4318
e7b07cee
HW		 4319 amdgpu_dm_connector_init_helper(
4320 dm,
4321 aconnector,
4322 connector_type,
4323 link,
4324 link_index);
4325
cde4c44d 4326 drm_connector_attach_encoder(
e7b07cee
HW		 4327 &aconnector->base, &aencoder->base);
4328
4329 drm_connector_register(&aconnector->base);
dc38fd9d
DF		 4330#if defined(CONFIG_DEBUG_FS)
4331 res = connector_debugfs_init(aconnector);
4332 if (res) {
4333 DRM_ERROR("Failed to create debugfs for connector");
4334 goto out_free;
4335 }
4336#endif
e7b07cee
HW		 4337
4338 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4339 || connector_type == DRM_MODE_CONNECTOR_eDP)
4340 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4341
e7b07cee
HW		 4342out_free:
4343 if (res) {
4344 kfree(i2c);
4345 aconnector->i2c = NULL;
4346 }
4347 return res;
4348}
4349
4350int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4351{
4352 switch (adev->mode_info.num_crtc) {
4353 case 1:
4354 return 0x1;
4355 case 2:
4356 return 0x3;
4357 case 3:
4358 return 0x7;
4359 case 4:
4360 return 0xf;
4361 case 5:
4362 return 0x1f;
4363 case 6:
4364 default:
4365 return 0x3f;
4366 }
4367}
4368
7578ecda
AD		 4369static int amdgpu_dm_encoder_init(struct drm_device *dev,
4370 struct amdgpu_encoder *aencoder,
4371 uint32_t link_index)
e7b07cee
HW		 4372{
4373 struct amdgpu_device *adev = dev->dev_private;
4374
4375 int res = drm_encoder_init(dev,
4376 &aencoder->base,
4377 &amdgpu_dm_encoder_funcs,
4378 DRM_MODE_ENCODER_TMDS,
4379 NULL);
4380
4381 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4382
4383 if (!res)
4384 aencoder->encoder_id = link_index;
4385 else
4386 aencoder->encoder_id = -1;
4387
4388 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4389
4390 return res;
4391}
4392
3ee6b26b
AD		 4393static void manage_dm_interrupts(struct amdgpu_device *adev,
4394 struct amdgpu_crtc *acrtc,
4395 bool enable)
e7b07cee
HW		 4396{
4397 /*
4398 * this is not correct translation but will work as soon as VBLANK
4399 * constant is the same as PFLIP
4400 */
4401 int irq_type =
734dd01d 4402 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 4403 adev,
4404 acrtc->crtc_id);
4405
4406 if (enable) {
4407 drm_crtc_vblank_on(&acrtc->base);
4408 amdgpu_irq_get(
4409 adev,
4410 &adev->pageflip_irq,
4411 irq_type);
4412 } else {
4413
4414 amdgpu_irq_put(
4415 adev,
4416 &adev->pageflip_irq,
4417 irq_type);
4418 drm_crtc_vblank_off(&acrtc->base);
4419 }
4420}
4421
3ee6b26b
AD		 4422static bool
4423is_scaling_state_different(const struct dm_connector_state *dm_state,
4424 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 4425{
4426 if (dm_state->scaling != old_dm_state->scaling)
4427 return true;
4428 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4429 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4430 return true;
4431 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4432 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4433 return true;
b830ebc9
HW		 4434 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4435 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4436 return true;
e7b07cee
HW		 4437 return false;
4438}
4439
3ee6b26b
AD		 4440static void remove_stream(struct amdgpu_device *adev,
4441 struct amdgpu_crtc *acrtc,
4442 struct dc_stream_state *stream)
e7b07cee
HW		 4443{
4444 /* this is the update mode case */
e7b07cee
HW		 4445
4446 acrtc->otg_inst = -1;
4447 acrtc->enabled = false;
4448}
4449
7578ecda
AD		 4450static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4451 struct dc_cursor_position *position)
2a8f6ccb 4452{
f4c2cc43 4453 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 4454 int x, y;
4455 int xorigin = 0, yorigin = 0;
4456
4457 if (!crtc || !plane->state->fb) {
4458 position->enable = false;
4459 position->x = 0;
4460 position->y = 0;
4461 return 0;
4462 }
4463
4464 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4465 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4466 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4467 __func__,
4468 plane->state->crtc_w,
4469 plane->state->crtc_h);
4470 return -EINVAL;
4471 }
4472
4473 x = plane->state->crtc_x;
4474 y = plane->state->crtc_y;
4475 /* avivo cursor are offset into the total surface */
4476 x += crtc->primary->state->src_x >> 16;
4477 y += crtc->primary->state->src_y >> 16;
4478 if (x < 0) {
4479 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4480 x = 0;
4481 }
4482 if (y < 0) {
4483 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4484 y = 0;
4485 }
4486 position->enable = true;
4487 position->x = x;
4488 position->y = y;
4489 position->x_hotspot = xorigin;
4490 position->y_hotspot = yorigin;
4491
4492 return 0;
4493}
4494
3ee6b26b
AD		 4495static void handle_cursor_update(struct drm_plane *plane,
4496 struct drm_plane_state *old_plane_state)
e7b07cee 4497{
674e78ac 4498 struct amdgpu_device *adev = plane->dev->dev_private;
2a8f6ccb
HW		 4499 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4500 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4501 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4502 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4503 uint64_t address = afb ? afb->address : 0;
4504 struct dc_cursor_position position;
4505 struct dc_cursor_attributes attributes;
4506 int ret;
4507
e7b07cee
HW		 4508 if (!plane->state->fb && !old_plane_state->fb)
4509 return;
4510
f1ad2f5e 4511 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 4512 __func__,
4513 amdgpu_crtc->crtc_id,
4514 plane->state->crtc_w,
4515 plane->state->crtc_h);
2a8f6ccb
HW		 4516
4517 ret = get_cursor_position(plane, crtc, &position);
4518 if (ret)
4519 return;
4520
4521 if (!position.enable) {
4522 /* turn off cursor */
674e78ac
NK		 4523 if (crtc_state && crtc_state->stream) {
4524 mutex_lock(&adev->dm.dc_lock);
2a8f6ccb
HW		 4525 dc_stream_set_cursor_position(crtc_state->stream,
4526 &position);
674e78ac
NK		 4527 mutex_unlock(&adev->dm.dc_lock);
4528 }
2a8f6ccb 4529 return;
e7b07cee 4530 }
e7b07cee 4531
2a8f6ccb
HW		 4532 amdgpu_crtc->cursor_width = plane->state->crtc_w;
4533 amdgpu_crtc->cursor_height = plane->state->crtc_h;
4534
4535 attributes.address.high_part = upper_32_bits(address);
4536 attributes.address.low_part = lower_32_bits(address);
4537 attributes.width = plane->state->crtc_w;
4538 attributes.height = plane->state->crtc_h;
4539 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4540 attributes.rotation_angle = 0;
4541 attributes.attribute_flags.value = 0;
4542
4543 attributes.pitch = attributes.width;
4544
886daac9 4545 if (crtc_state->stream) {
674e78ac 4546 mutex_lock(&adev->dm.dc_lock);
886daac9
JZ		 4547 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4548 &attributes))
4549 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 4550
2a8f6ccb
HW		 4551 if (!dc_stream_set_cursor_position(crtc_state->stream,
4552 &position))
4553 DRM_ERROR("DC failed to set cursor position\n");
674e78ac 4554 mutex_unlock(&adev->dm.dc_lock);
886daac9 4555 }
2a8f6ccb 4556}
e7b07cee
HW		 4557
4558static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4559{
4560
4561 assert_spin_locked(&acrtc->base.dev->event_lock);
4562 WARN_ON(acrtc->event);
4563
4564 acrtc->event = acrtc->base.state->event;
4565
4566 /* Set the flip status */
4567 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4568
4569 /* Mark this event as consumed */
4570 acrtc->base.state->event = NULL;
4571
4572 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4573 acrtc->crtc_id);
4574}
4575
bb47de73
NK		 4576static void update_freesync_state_on_stream(
4577 struct amdgpu_display_manager *dm,
4578 struct dm_crtc_state *new_crtc_state,
180db303
NK		 4579 struct dc_stream_state *new_stream,
4580 struct dc_plane_state *surface,
4581 u32 flip_timestamp_in_us)
bb47de73 4582{
180db303 4583 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params;
bb47de73
NK		 4584 struct dc_info_packet vrr_infopacket = {0};
4585 struct mod_freesync_config config = new_crtc_state->freesync_config;
4586
4587 if (!new_stream)
4588 return;
4589
4590 /*
4591 * TODO: Determine why min/max totals and vrefresh can be 0 here.
4592 * For now it's sufficient to just guard against these conditions.
4593 */
4594
4595 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
4596 return;
4597
4598 if (new_crtc_state->vrr_supported &&
4599 config.min_refresh_in_uhz &&
4600 config.max_refresh_in_uhz) {
4601 config.state = new_crtc_state->base.vrr_enabled ?
4602 VRR_STATE_ACTIVE_VARIABLE :
4603 VRR_STATE_INACTIVE;
4604 } else {
4605 config.state = VRR_STATE_UNSUPPORTED;
4606 }
4607
4608 mod_freesync_build_vrr_params(dm->freesync_module,
4609 new_stream,
180db303
NK		 4610 &config, &vrr_params);
4611
4612 if (surface) {
4613 mod_freesync_handle_preflip(
4614 dm->freesync_module,
4615 surface,
4616 new_stream,
4617 flip_timestamp_in_us,
4618 &vrr_params);
4619 }
bb47de73
NK		 4620
4621 mod_freesync_build_vrr_infopacket(
4622 dm->freesync_module,
4623 new_stream,
180db303 4624 &vrr_params,
ecd0136b
HT		 4625 PACKET_TYPE_VRR,
4626 TRANSFER_FUNC_UNKNOWN,
bb47de73
NK		 4627 &vrr_infopacket);
4628
8a48b44c 4629 new_crtc_state->freesync_timing_changed |=
180db303
NK		 4630 (memcmp(&new_crtc_state->vrr_params.adjust,
4631 &vrr_params.adjust,
4632 sizeof(vrr_params.adjust)) != 0);
bb47de73 4633
8a48b44c 4634 new_crtc_state->freesync_vrr_info_changed |=
bb47de73
NK		 4635 (memcmp(&new_crtc_state->vrr_infopacket,
4636 &vrr_infopacket,
4637 sizeof(vrr_infopacket)) != 0);
4638
180db303 4639 new_crtc_state->vrr_params = vrr_params;
bb47de73
NK		 4640 new_crtc_state->vrr_infopacket = vrr_infopacket;
4641
180db303 4642 new_stream->adjust = new_crtc_state->vrr_params.adjust;
bb47de73
NK		 4643 new_stream->vrr_infopacket = vrr_infopacket;
4644
4645 if (new_crtc_state->freesync_vrr_info_changed)
4646 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
4647 new_crtc_state->base.crtc->base.id,
4648 (int)new_crtc_state->base.vrr_enabled,
180db303 4649 (int)vrr_params.state);
bb47de73
NK		 4650}
4651
3be5262e 4652static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 4653 struct dc_state *dc_state,
3ee6b26b
AD		 4654 struct drm_device *dev,
4655 struct amdgpu_display_manager *dm,
4656 struct drm_crtc *pcrtc,
420cd472 4657 bool wait_for_vblank)
e7b07cee 4658{
8a48b44c
DF		 4659 uint32_t i, r;
4660 uint64_t timestamp_ns;
e7b07cee 4661 struct drm_plane *plane;
0bc9706d 4662 struct drm_plane_state *old_plane_state, *new_plane_state;
e7b07cee 4663 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 4664 struct drm_crtc_state *new_pcrtc_state =
4665 drm_atomic_get_new_crtc_state(state, pcrtc);
4666 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 4667 struct dm_crtc_state *dm_old_crtc_state =
4668 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
74aa7bd4 4669 int planes_count = 0, vpos, hpos;
e7b07cee 4670 unsigned long flags;
8a48b44c
DF		 4671 struct amdgpu_bo *abo;
4672 uint64_t tiling_flags, dcc_address;
8a48b44c 4673 uint32_t target, target_vblank;
7b19bba5
MK		 4674 uint64_t last_flip_vblank;
4675 bool vrr_active = acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE;
74aa7bd4 4676 bool pflip_present = false;
8a48b44c 4677
bc7f670e
DF		 4678 struct {
4679 struct dc_surface_update surface_updates[MAX_SURFACES];
4680 struct dc_plane_info plane_infos[MAX_SURFACES];
4681 struct dc_scaling_info scaling_infos[MAX_SURFACES];
74aa7bd4 4682 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
bc7f670e 4683 struct dc_stream_update stream_update;
74aa7bd4 4684 } *bundle;
bc7f670e 4685
74aa7bd4 4686 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8a48b44c 4687
74aa7bd4
DF		 4688 if (!bundle) {
4689 dm_error("Failed to allocate update bundle\n");
4b510503
NK		 4690 goto cleanup;
4691 }
e7b07cee
HW		 4692
4693 /* update planes when needed */
0bc9706d
LSL		 4694 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4695 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 4696 struct drm_crtc_state *new_crtc_state;
0bc9706d 4697 struct drm_framebuffer *fb = new_plane_state->fb;
8a48b44c 4698 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
74aa7bd4 4699 bool framebuffer_changed;
c7af5f77 4700 struct dc_plane_state *dc_plane;
54d76575 4701 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee 4702
80c218d5
NK		 4703 /* Cursor plane is handled after stream updates */
4704 if (plane->type == DRM_PLANE_TYPE_CURSOR)
e7b07cee 4705 continue;
e7b07cee 4706
f5ba60fe
DD		 4707 if (!fb || !crtc || pcrtc != crtc)
4708 continue;
4709
4710 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4711 if (!new_crtc_state->active)
e7b07cee
HW		 4712 continue;
4713
74aa7bd4
DF		 4714 dc_plane = dm_new_plane_state->dc_state;
4715
4716 framebuffer_changed = old_plane_state->fb &&
b2e85302 4717 old_plane_state->fb != new_plane_state->fb;
e7b07cee 4718
74aa7bd4 4719 pflip_present = pflip_present || framebuffer_changed;
e7b07cee 4720
74aa7bd4 4721 if (framebuffer_changed) {
8a48b44c
DF		 4722 /*
4723 * TODO This might fail and hence better not used, wait
4724 * explicitly on fences instead
4725 * and in general should be called for
4726 * blocking commit to as per framework helpers
4727 */
4728 abo = gem_to_amdgpu_bo(fb->obj[0]);
4729 r = amdgpu_bo_reserve(abo, true);
f7c8930d 4730 if (unlikely(r != 0))
8a48b44c 4731 DRM_ERROR("failed to reserve buffer before flip\n");
8a48b44c 4732
f7c8930d
AG		 4733 /*
4734 * Wait for all fences on this FB. Do limited wait to avoid
4735 * deadlock during GPU reset when this fence will not signal
4736 * but we hold reservation lock for the BO.
4737 */
4738 r = reservation_object_wait_timeout_rcu(abo->tbo.resv,
4739 true, false,
4740 msecs_to_jiffies(5000));
4741 if (unlikely(r == 0))
4742 DRM_ERROR("Waiting for fences timed out.");
4743
4744
8a48b44c
DF		 4745
4746 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
4747
4748 amdgpu_bo_unreserve(abo);
4749
74aa7bd4
DF		 4750 bundle->flip_addrs[planes_count].address.grph.addr.low_part = lower_32_bits(afb->address);
4751 bundle->flip_addrs[planes_count].address.grph.addr.high_part = upper_32_bits(afb->address);
8a48b44c
DF		 4752
4753 dcc_address = get_dcc_address(afb->address, tiling_flags);
74aa7bd4
DF		 4754 bundle->flip_addrs[planes_count].address.grph.meta_addr.low_part = lower_32_bits(dcc_address);
4755 bundle->flip_addrs[planes_count].address.grph.meta_addr.high_part = upper_32_bits(dcc_address);
8a48b44c 4756
74aa7bd4 4757 bundle->flip_addrs[planes_count].flip_immediate =
8a48b44c
DF		 4758 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
4759
4760 timestamp_ns = ktime_get_ns();
74aa7bd4
DF		 4761 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
4762 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
4763 bundle->surface_updates[planes_count].surface = dc_plane;
8a48b44c 4764
74aa7bd4 4765 if (!bundle->surface_updates[planes_count].surface) {
8a48b44c
DF		 4766 DRM_ERROR("No surface for CRTC: id=%d\n",
4767 acrtc_attach->crtc_id);
4768 continue;
4769 }
4770
c7af5f77 4771 if (plane == pcrtc->primary)
8a48b44c
DF		 4772 update_freesync_state_on_stream(
4773 dm,
4774 acrtc_state,
4775 acrtc_state->stream,
c7af5f77 4776 dc_plane,
74aa7bd4 4777 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8a48b44c 4778
8a48b44c
DF		 4779 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
4780 __func__,
74aa7bd4
DF		 4781 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
4782 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8a48b44c
DF		 4783 }
4784
74aa7bd4 4785 bundle->surface_updates[planes_count].surface = dc_plane;
bc7f670e 4786 if (new_pcrtc_state->color_mgmt_changed) {
74aa7bd4
DF		 4787 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
4788 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
bc7f670e
DF		 4789 }
4790
4791
74aa7bd4
DF		 4792 bundle->scaling_infos[planes_count].scaling_quality = dc_plane->scaling_quality;
4793 bundle->scaling_infos[planes_count].src_rect = dc_plane->src_rect;
4794 bundle->scaling_infos[planes_count].dst_rect = dc_plane->dst_rect;
4795 bundle->scaling_infos[planes_count].clip_rect = dc_plane->clip_rect;
4796 bundle->surface_updates[planes_count].scaling_info = &bundle->scaling_infos[planes_count];
bc7f670e
DF		 4797
4798
74aa7bd4
DF		 4799 bundle->plane_infos[planes_count].color_space = dc_plane->color_space;
4800 bundle->plane_infos[planes_count].format = dc_plane->format;
4801 bundle->plane_infos[planes_count].plane_size = dc_plane->plane_size;
4802 bundle->plane_infos[planes_count].rotation = dc_plane->rotation;
4803 bundle->plane_infos[planes_count].horizontal_mirror = dc_plane->horizontal_mirror;
4804 bundle->plane_infos[planes_count].stereo_format = dc_plane->stereo_format;
4805 bundle->plane_infos[planes_count].tiling_info = dc_plane->tiling_info;
4806 bundle->plane_infos[planes_count].visible = dc_plane->visible;
4807 bundle->plane_infos[planes_count].per_pixel_alpha = dc_plane->per_pixel_alpha;
4808 bundle->plane_infos[planes_count].dcc = dc_plane->dcc;
4809 bundle->surface_updates[planes_count].plane_info = &bundle->plane_infos[planes_count];
bc7f670e
DF		 4810
4811 planes_count += 1;
4812
8a48b44c
DF		 4813 }
4814
74aa7bd4 4815 if (pflip_present) {
7b19bba5
MK		 4816 if (!vrr_active) {
4817 /* Use old throttling in non-vrr fixed refresh rate mode
4818 * to keep flip scheduling based on target vblank counts
4819 * working in a backwards compatible way, e.g., for
4820 * clients using the GLX_OML_sync_control extension or
4821 * DRI3/Present extension with defined target_msc.
4822 */
4823 last_flip_vblank = drm_crtc_vblank_count(pcrtc);
4824 }
4825 else {
4826 /* For variable refresh rate mode only:
4827 * Get vblank of last completed flip to avoid > 1 vrr
4828 * flips per video frame by use of throttling, but allow
4829 * flip programming anywhere in the possibly large
4830 * variable vrr vblank interval for fine-grained flip
4831 * timing control and more opportunity to avoid stutter
4832 * on late submission of flips.
4833 */
4834 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4835 last_flip_vblank = acrtc_attach->last_flip_vblank;
4836 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4837 }
4838
420cd472 4839 target = (uint32_t)last_flip_vblank + wait_for_vblank;
7b19bba5 4840
8a48b44c
DF		 4841 /* Prepare wait for target vblank early - before the fence-waits */
4842 target_vblank = target - (uint32_t)drm_crtc_vblank_count(pcrtc) +
4843 amdgpu_get_vblank_counter_kms(pcrtc->dev, acrtc_attach->crtc_id);
4844
4845 /*
4846 * Wait until we're out of the vertical blank period before the one
4847 * targeted by the flip
4848 */
4849 while ((acrtc_attach->enabled &&
4850 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
4851 0, &vpos, &hpos, NULL,
4852 NULL, &pcrtc->hwmode)
4853 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4854 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4855 (int)(target_vblank -
4856 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
4857 usleep_range(1000, 1100);
4858 }
4859
4860 if (acrtc_attach->base.state->event) {
4861 drm_crtc_vblank_get(pcrtc);
4862
4863 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4864
4865 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
4866 prepare_flip_isr(acrtc_attach);
4867
4868 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4869 }
4870
4871 if (acrtc_state->stream) {
4872
4873 if (acrtc_state->freesync_timing_changed)
74aa7bd4 4874 bundle->stream_update.adjust =
8a48b44c
DF		 4875 &acrtc_state->stream->adjust;
4876
4877 if (acrtc_state->freesync_vrr_info_changed)
74aa7bd4 4878 bundle->stream_update.vrr_infopacket =
8a48b44c 4879 &acrtc_state->stream->vrr_infopacket;
e7b07cee 4880 }
e7b07cee
HW		 4881 }
4882
4883 if (planes_count) {
bc7f670e 4884 if (new_pcrtc_state->mode_changed) {
74aa7bd4
DF		 4885 bundle->stream_update.src = acrtc_state->stream->src;
4886 bundle->stream_update.dst = acrtc_state->stream->dst;
e7b07cee
HW		 4887 }
4888
bc7f670e 4889 if (new_pcrtc_state->color_mgmt_changed)
74aa7bd4 4890 bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func;
bc7f670e 4891
8a48b44c 4892 acrtc_state->stream->abm_level = acrtc_state->abm_level;
bc7f670e 4893 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
74aa7bd4 4894 bundle->stream_update.abm_level = &acrtc_state->abm_level;
44d09c6a 4895
bc7f670e
DF		 4896 mutex_lock(&dm->dc_lock);
4897 dc_commit_updates_for_stream(dm->dc,
74aa7bd4 4898 bundle->surface_updates,
bc7f670e
DF		 4899 planes_count,
4900 acrtc_state->stream,
74aa7bd4 4901 &bundle->stream_update,
bc7f670e
DF		 4902 dc_state);
4903 mutex_unlock(&dm->dc_lock);
e7b07cee 4904 }
4b510503 4905
80c218d5
NK		 4906 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
4907 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4908 handle_cursor_update(plane, old_plane_state);
4909
4b510503 4910cleanup:
74aa7bd4 4911 kfree(bundle);
e7b07cee
HW		 4912}
4913
1f6010a9 4914/*
27b3f4fc
LSL		 4915 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4916 * @crtc_state: the DRM CRTC state
4917 * @stream_state: the DC stream state.
4918 *
4919 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4920 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4921 */
4922static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4923 struct dc_stream_state *stream_state)
4924{
b9952f93 4925 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
27b3f4fc 4926}
e7b07cee 4927
7578ecda
AD		 4928static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4929 struct drm_atomic_state *state,
4930 bool nonblock)
e7b07cee
HW		 4931{
4932 struct drm_crtc *crtc;
c2cea706 4933 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4934 struct amdgpu_device *adev = dev->dev_private;
4935 int i;
4936
4937 /*
4938 * We evade vblanks and pflips on crtc that
4939 * should be changed. We do it here to flush & disable
4940 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4941 * it will update crtc->dm_crtc_state->stream pointer which is used in
4942 * the ISRs.
4943 */
c2cea706 4944 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4945 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
428da2bd 4946 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 4947 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4948
428da2bd
NK		 4949 if (drm_atomic_crtc_needs_modeset(new_crtc_state)
4950 && dm_old_crtc_state->stream) {
4951 /*
43a6a02e
NK		 4952 * If the stream is removed and CRC capture was
4953 * enabled on the CRTC the extra vblank reference
4954 * needs to be dropped since CRC capture will be
4955 * disabled.
428da2bd 4956 */
43a6a02e
NK		 4957 if (!dm_new_crtc_state->stream
4958 && dm_new_crtc_state->crc_enabled) {
428da2bd
NK		 4959 drm_crtc_vblank_put(crtc);
4960 dm_new_crtc_state->crc_enabled = false;
4961 }
4962
e7b07cee 4963 manage_dm_interrupts(adev, acrtc, false);
428da2bd 4964 }
e7b07cee 4965 }
1f6010a9
DF		 4966 /*
4967 * Add check here for SoC's that support hardware cursor plane, to
4968 * unset legacy_cursor_update
4969 */
e7b07cee
HW		 4970
4971 return drm_atomic_helper_commit(dev, state, nonblock);
4972
4973 /*TODO Handle EINTR, reenable IRQ*/
4974}
4975
b8592b48
LL		 4976/**
4977 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
4978 * @state: The atomic state to commit
4979 *
4980 * This will tell DC to commit the constructed DC state from atomic_check,
4981 * programming the hardware. Any failures here implies a hardware failure, since
4982 * atomic check should have filtered anything non-kosher.
4983 */
7578ecda 4984static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4985{
4986 struct drm_device *dev = state->dev;
4987 struct amdgpu_device *adev = dev->dev_private;
4988 struct amdgpu_display_manager *dm = &adev->dm;
4989 struct dm_atomic_state *dm_state;
eb3dc897 4990 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 4991 uint32_t i, j;
5cc6dcbd 4992 struct drm_crtc *crtc;
0bc9706d 4993 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4994 unsigned long flags;
4995 bool wait_for_vblank = true;
4996 struct drm_connector *connector;
c2cea706 4997 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4998 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 4999 int crtc_disable_count = 0;
e7b07cee
HW		 5000
5001 drm_atomic_helper_update_legacy_modeset_state(dev, state);
5002
eb3dc897
NK		 5003 dm_state = dm_atomic_get_new_state(state);
5004 if (dm_state && dm_state->context) {
5005 dc_state = dm_state->context;
5006 } else {
5007 /* No state changes, retain current state. */
5008 dc_state_temp = dc_create_state();
5009 ASSERT(dc_state_temp);
5010 dc_state = dc_state_temp;
5011 dc_resource_state_copy_construct_current(dm->dc, dc_state);
5012 }
e7b07cee
HW		 5013
5014 /* update changed items */
0bc9706d 5015 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 5016 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5017
54d76575
LSL		 5018 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5019 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 5020
f1ad2f5e 5021 DRM_DEBUG_DRIVER(
e7b07cee
HW		 5022 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5023 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5024 "connectors_changed:%d\n",
5025 acrtc->crtc_id,
0bc9706d
LSL		 5026 new_crtc_state->enable,
5027 new_crtc_state->active,
5028 new_crtc_state->planes_changed,
5029 new_crtc_state->mode_changed,
5030 new_crtc_state->active_changed,
5031 new_crtc_state->connectors_changed);
e7b07cee 5032
27b3f4fc
LSL		 5033 /* Copy all transient state flags into dc state */
5034 if (dm_new_crtc_state->stream) {
5035 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5036 dm_new_crtc_state->stream);
5037 }
5038
e7b07cee
HW		 5039 /* handles headless hotplug case, updating new_state and
5040 * aconnector as needed
5041 */
5042
54d76575 5043 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 5044
f1ad2f5e 5045 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 5046
54d76575 5047 if (!dm_new_crtc_state->stream) {
e7b07cee 5048 /*
b830ebc9
HW		 5049 * this could happen because of issues with
5050 * userspace notifications delivery.
5051 * In this case userspace tries to set mode on
1f6010a9
DF		 5052 * display which is disconnected in fact.
5053 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 5054 * We expect reset mode will come soon.
5055 *
5056 * This can also happen when unplug is done
5057 * during resume sequence ended
5058 *
5059 * In this case, we want to pretend we still
5060 * have a sink to keep the pipe running so that
5061 * hw state is consistent with the sw state
5062 */
f1ad2f5e 5063 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 5064 __func__, acrtc->base.base.id);
5065 continue;
5066 }
5067
54d76575
LSL		 5068 if (dm_old_crtc_state->stream)
5069 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 5070
97028037
LP		 5071 pm_runtime_get_noresume(dev->dev);
5072
e7b07cee 5073 acrtc->enabled = true;
0bc9706d
LSL		 5074 acrtc->hw_mode = new_crtc_state->mode;
5075 crtc->hwmode = new_crtc_state->mode;
5076 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 5077 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 5078
5079 /* i.e. reset mode */
54d76575
LSL		 5080 if (dm_old_crtc_state->stream)
5081 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 5082 }
5083 } /* for_each_crtc_in_state() */
5084
eb3dc897
NK		 5085 if (dc_state) {
5086 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 5087 mutex_lock(&dm->dc_lock);
eb3dc897 5088 WARN_ON(!dc_commit_state(dm->dc, dc_state));
674e78ac 5089 mutex_unlock(&dm->dc_lock);
fa2123db 5090 }
e7b07cee 5091
0bc9706d 5092 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5093 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5094
54d76575 5095 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5096
54d76575 5097 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 5098 const struct dc_stream_status *status =
54d76575 5099 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5100
eb3dc897 5101 if (!status)
09f609c3
LL		 5102 status = dc_stream_get_status_from_state(dc_state,
5103 dm_new_crtc_state->stream);
eb3dc897 5104
e7b07cee 5105 if (!status)
54d76575 5106 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 5107 else
5108 acrtc->otg_inst = status->primary_otg_inst;
5109 }
5110 }
5111
02d6a6fc 5112 /* Handle connector state changes */
c2cea706 5113 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5114 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5115 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5116 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
19afd799
NC		 5117 struct dc_surface_update dummy_updates[MAX_SURFACES];
5118 struct dc_stream_update stream_update;
e7b07cee
HW		 5119 struct dc_stream_status *status = NULL;
5120
19afd799
NC		 5121 memset(&dummy_updates, 0, sizeof(dummy_updates));
5122 memset(&stream_update, 0, sizeof(stream_update));
5123
44d09c6a 5124 if (acrtc) {
0bc9706d 5125 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 5126 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5127 }
0bc9706d 5128
e7b07cee 5129 /* Skip any modesets/resets */
0bc9706d 5130 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 5131 continue;
5132
54d76575 5133 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 5134 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5135
c1ee92f9
DF		 5136 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5137 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5138 continue;
e7b07cee 5139
02d6a6fc
DF		 5140 if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) {
5141 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5142 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 5143
02d6a6fc
DF		 5144 stream_update.src = dm_new_crtc_state->stream->src;
5145 stream_update.dst = dm_new_crtc_state->stream->dst;
5146 }
5147
5148 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
5149 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
5150
5151 stream_update.abm_level = &dm_new_crtc_state->abm_level;
5152 }
70e8ffc5 5153
54d76575 5154 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5155 WARN_ON(!status);
3be5262e 5156 WARN_ON(!status->plane_count);
e7b07cee 5157
02d6a6fc
DF		 5158 /*
5159 * TODO: DC refuses to perform stream updates without a dc_surface_update.
5160 * Here we create an empty update on each plane.
5161 * To fix this, DC should permit updating only stream properties.
5162 */
5163 for (j = 0; j < status->plane_count; j++)
5164 dummy_updates[j].surface = status->plane_states[0];
5165
5166
5167 mutex_lock(&dm->dc_lock);
5168 dc_commit_updates_for_stream(dm->dc,
5169 dummy_updates,
5170 status->plane_count,
5171 dm_new_crtc_state->stream,
5172 &stream_update,
5173 dc_state);
5174 mutex_unlock(&dm->dc_lock);
e7b07cee
HW		 5175 }
5176
e1fc2dca
LSL		 5177 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5178 new_crtc_state, i) {
e7b07cee
HW		 5179 /*
5180 * loop to enable interrupts on newly arrived crtc
5181 */
e1fc2dca
LSL		 5182 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5183 bool modeset_needed;
b830ebc9 5184
fe2a1965
LP		 5185 if (old_crtc_state->active && !new_crtc_state->active)
5186 crtc_disable_count++;
5187
54d76575 5188 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 5189 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5190 modeset_needed = modeset_required(
5191 new_crtc_state,
5192 dm_new_crtc_state->stream,
5193 dm_old_crtc_state->stream);
5194
5195 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
5196 continue;
e7b07cee 5197
e7b07cee 5198 manage_dm_interrupts(adev, acrtc, true);
43a6a02e 5199
cc7e422d 5200#ifdef CONFIG_DEBUG_FS
43a6a02e
NK		 5201 /* The stream has changed so CRC capture needs to re-enabled. */
5202 if (dm_new_crtc_state->crc_enabled)
5203 amdgpu_dm_crtc_set_crc_source(crtc, "auto");
cc7e422d 5204#endif
e7b07cee
HW		 5205 }
5206
420cd472
DF		 5207 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
5208 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
5209 wait_for_vblank = false;
5210
e7b07cee 5211 /* update planes when needed per crtc*/
5cc6dcbd 5212 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 5213 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5214
54d76575 5215 if (dm_new_crtc_state->stream)
eb3dc897 5216 amdgpu_dm_commit_planes(state, dc_state, dev,
420cd472 5217 dm, crtc, wait_for_vblank);
e7b07cee
HW		 5218 }
5219
5220
5221 /*
5222 * send vblank event on all events not handled in flip and
5223 * mark consumed event for drm_atomic_helper_commit_hw_done
5224 */
5225 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 5226 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5227
0bc9706d
LSL		 5228 if (new_crtc_state->event)
5229 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 5230
0bc9706d 5231 new_crtc_state->event = NULL;
e7b07cee
HW		 5232 }
5233 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5234
29c8f234
LL		 5235 /* Signal HW programming completion */
5236 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 5237
5238 if (wait_for_vblank)
320a1274 5239 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 5240
5241 drm_atomic_helper_cleanup_planes(dev, state);
97028037 5242
1f6010a9
DF		 5243 /*
5244 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 5245 * so we can put the GPU into runtime suspend if we're not driving any
5246 * displays anymore
5247 */
fe2a1965
LP		 5248 for (i = 0; i < crtc_disable_count; i++)
5249 pm_runtime_put_autosuspend(dev->dev);
97028037 5250 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 5251
5252 if (dc_state_temp)
5253 dc_release_state(dc_state_temp);
e7b07cee
HW		 5254}
5255
5256
5257static int dm_force_atomic_commit(struct drm_connector *connector)
5258{
5259 int ret = 0;
5260 struct drm_device *ddev = connector->dev;
5261 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5262 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5263 struct drm_plane *plane = disconnected_acrtc->base.primary;
5264 struct drm_connector_state *conn_state;
5265 struct drm_crtc_state *crtc_state;
5266 struct drm_plane_state *plane_state;
5267
5268 if (!state)
5269 return -ENOMEM;
5270
5271 state->acquire_ctx = ddev->mode_config.acquire_ctx;
5272
5273 /* Construct an atomic state to restore previous display setting */
5274
5275 /*
5276 * Attach connectors to drm_atomic_state
5277 */
5278 conn_state = drm_atomic_get_connector_state(state, connector);
5279
5280 ret = PTR_ERR_OR_ZERO(conn_state);
5281 if (ret)
5282 goto err;
5283
5284 /* Attach crtc to drm_atomic_state*/
5285 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5286
5287 ret = PTR_ERR_OR_ZERO(crtc_state);
5288 if (ret)
5289 goto err;
5290
5291 /* force a restore */
5292 crtc_state->mode_changed = true;
5293
5294 /* Attach plane to drm_atomic_state */
5295 plane_state = drm_atomic_get_plane_state(state, plane);
5296
5297 ret = PTR_ERR_OR_ZERO(plane_state);
5298 if (ret)
5299 goto err;
5300
5301
5302 /* Call commit internally with the state we just constructed */
5303 ret = drm_atomic_commit(state);
5304 if (!ret)
5305 return 0;
5306
5307err:
5308 DRM_ERROR("Restoring old state failed with %i\n", ret);
5309 drm_atomic_state_put(state);
5310
5311 return ret;
5312}
5313
5314/*
1f6010a9
DF		 5315 * This function handles all cases when set mode does not come upon hotplug.
5316 * This includes when a display is unplugged then plugged back into the
5317 * same port and when running without usermode desktop manager supprot
e7b07cee 5318 */
3ee6b26b
AD		 5319void dm_restore_drm_connector_state(struct drm_device *dev,
5320 struct drm_connector *connector)
e7b07cee 5321{
c84dec2f 5322 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5323 struct amdgpu_crtc *disconnected_acrtc;
5324 struct dm_crtc_state *acrtc_state;
5325
5326 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5327 return;
5328
5329 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 5330 if (!disconnected_acrtc)
5331 return;
e7b07cee 5332
70e8ffc5
HW		 5333 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5334 if (!acrtc_state->stream)
e7b07cee
HW		 5335 return;
5336
5337 /*
5338 * If the previous sink is not released and different from the current,
5339 * we deduce we are in a state where we can not rely on usermode call
5340 * to turn on the display, so we do it here
5341 */
5342 if (acrtc_state->stream->sink != aconnector->dc_sink)
5343 dm_force_atomic_commit(&aconnector->base);
5344}
5345
1f6010a9 5346/*
e7b07cee
HW		 5347 * Grabs all modesetting locks to serialize against any blocking commits,
5348 * Waits for completion of all non blocking commits.
5349 */
3ee6b26b
AD		 5350static int do_aquire_global_lock(struct drm_device *dev,
5351 struct drm_atomic_state *state)
e7b07cee
HW		 5352{
5353 struct drm_crtc *crtc;
5354 struct drm_crtc_commit *commit;
5355 long ret;
5356
1f6010a9
DF		 5357 /*
5358 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 5359 * ensure that when the framework release it the
5360 * extra locks we are locking here will get released to
5361 */
5362 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
5363 if (ret)
5364 return ret;
5365
5366 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5367 spin_lock(&crtc->commit_lock);
5368 commit = list_first_entry_or_null(&crtc->commit_list,
5369 struct drm_crtc_commit, commit_entry);
5370 if (commit)
5371 drm_crtc_commit_get(commit);
5372 spin_unlock(&crtc->commit_lock);
5373
5374 if (!commit)
5375 continue;
5376
1f6010a9
DF		 5377 /*
5378 * Make sure all pending HW programming completed and
e7b07cee
HW		 5379 * page flips done
5380 */
5381 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
5382
5383 if (ret > 0)
5384 ret = wait_for_completion_interruptible_timeout(
5385 &commit->flip_done, 10*HZ);
5386
5387 if (ret == 0)
5388 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 5389 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 5390
5391 drm_crtc_commit_put(commit);
5392 }
5393
5394 return ret < 0 ? ret : 0;
5395}
5396
bb47de73
NK		 5397static void get_freesync_config_for_crtc(
5398 struct dm_crtc_state *new_crtc_state,
5399 struct dm_connector_state *new_con_state)
98e6436d
AK		 5400{
5401 struct mod_freesync_config config = {0};
98e6436d
AK		 5402 struct amdgpu_dm_connector *aconnector =
5403 to_amdgpu_dm_connector(new_con_state->base.connector);
a057ec46 5404 struct drm_display_mode *mode = &new_crtc_state->base.mode;
98e6436d 5405
a057ec46
IB		 5406 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
5407 aconnector->min_vfreq <= drm_mode_vrefresh(mode);
bb47de73 5408
a057ec46
IB		 5409 if (new_crtc_state->vrr_supported) {
5410 new_crtc_state->stream->ignore_msa_timing_param = true;
bb47de73 5411 config.state = new_crtc_state->base.vrr_enabled ?
98e6436d
AK		 5412 VRR_STATE_ACTIVE_VARIABLE :
5413 VRR_STATE_INACTIVE;
5414 config.min_refresh_in_uhz =
5415 aconnector->min_vfreq * 1000000;
5416 config.max_refresh_in_uhz =
5417 aconnector->max_vfreq * 1000000;
69ff8845 5418 config.vsif_supported = true;
180db303 5419 config.btr = true;
98e6436d
AK		 5420 }
5421
bb47de73
NK		 5422 new_crtc_state->freesync_config = config;
5423}
98e6436d 5424
bb47de73
NK		 5425static void reset_freesync_config_for_crtc(
5426 struct dm_crtc_state *new_crtc_state)
5427{
5428 new_crtc_state->vrr_supported = false;
98e6436d 5429
180db303
NK		 5430 memset(&new_crtc_state->vrr_params, 0,
5431 sizeof(new_crtc_state->vrr_params));
bb47de73
NK		 5432 memset(&new_crtc_state->vrr_infopacket, 0,
5433 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 5434}
5435
4b9674e5
LL		 5436static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
5437 struct drm_atomic_state *state,
5438 struct drm_crtc *crtc,
5439 struct drm_crtc_state *old_crtc_state,
5440 struct drm_crtc_state *new_crtc_state,
5441 bool enable,
5442 bool *lock_and_validation_needed)
e7b07cee 5443{
eb3dc897 5444 struct dm_atomic_state *dm_state = NULL;
54d76575 5445 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 5446 struct dc_stream_state *new_stream;
62f55537 5447 int ret = 0;
d4d4a645 5448
1f6010a9
DF		 5449 /*
5450 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
5451 * update changed items
5452 */
4b9674e5
LL		 5453 struct amdgpu_crtc *acrtc = NULL;
5454 struct amdgpu_dm_connector *aconnector = NULL;
5455 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
5456 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
5457 struct drm_plane_state *new_plane_state = NULL;
e7b07cee 5458
4b9674e5 5459 new_stream = NULL;
9635b754 5460
4b9674e5
LL		 5461 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5462 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5463 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 5464
4b9674e5 5465 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
f2877656 5466
4b9674e5
LL		 5467 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
5468 ret = -EINVAL;
5469 goto fail;
5470 }
f2877656 5471
4b9674e5 5472 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 5473
4b9674e5
LL		 5474 /* TODO This hack should go away */
5475 if (aconnector && enable) {
5476 /* Make sure fake sink is created in plug-in scenario */
5477 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
5478 &aconnector->base);
5479 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
5480 &aconnector->base);
19f89e23 5481
4b9674e5
LL		 5482 if (IS_ERR(drm_new_conn_state)) {
5483 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
5484 goto fail;
5485 }
19f89e23 5486
4b9674e5
LL		 5487 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
5488 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 5489
02d35a67
JFZ		 5490 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5491 goto skip_modeset;
5492
4b9674e5
LL		 5493 new_stream = create_stream_for_sink(aconnector,
5494 &new_crtc_state->mode,
5495 dm_new_conn_state,
5496 dm_old_crtc_state->stream);
19f89e23 5497
4b9674e5
LL		 5498 /*
5499 * we can have no stream on ACTION_SET if a display
5500 * was disconnected during S3, in this case it is not an
5501 * error, the OS will be updated after detection, and
5502 * will do the right thing on next atomic commit
5503 */
19f89e23 5504
4b9674e5
LL		 5505 if (!new_stream) {
5506 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5507 __func__, acrtc->base.base.id);
5508 ret = -ENOMEM;
5509 goto fail;
5510 }
e7b07cee 5511
4b9674e5 5512 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 5513
4b9674e5
LL		 5514 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
5515 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
5516 new_crtc_state->mode_changed = false;
5517 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
5518 new_crtc_state->mode_changed);
62f55537 5519 }
4b9674e5 5520 }
b830ebc9 5521
02d35a67 5522 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 5523 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5524 goto skip_modeset;
e7b07cee 5525
4b9674e5
LL		 5526 DRM_DEBUG_DRIVER(
5527 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5528 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5529 "connectors_changed:%d\n",
5530 acrtc->crtc_id,
5531 new_crtc_state->enable,
5532 new_crtc_state->active,
5533 new_crtc_state->planes_changed,
5534 new_crtc_state->mode_changed,
5535 new_crtc_state->active_changed,
5536 new_crtc_state->connectors_changed);
62f55537 5537
4b9674e5
LL		 5538 /* Remove stream for any changed/disabled CRTC */
5539 if (!enable) {
62f55537 5540
4b9674e5
LL		 5541 if (!dm_old_crtc_state->stream)
5542 goto skip_modeset;
eb3dc897 5543
4b9674e5
LL		 5544 ret = dm_atomic_get_state(state, &dm_state);
5545 if (ret)
5546 goto fail;
e7b07cee 5547
4b9674e5
LL		 5548 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
5549 crtc->base.id);
62f55537 5550
4b9674e5
LL		 5551 /* i.e. reset mode */
5552 if (dc_remove_stream_from_ctx(
5553 dm->dc,
5554 dm_state->context,
5555 dm_old_crtc_state->stream) != DC_OK) {
5556 ret = -EINVAL;
5557 goto fail;
5558 }
62f55537 5559
4b9674e5
LL		 5560 dc_stream_release(dm_old_crtc_state->stream);
5561 dm_new_crtc_state->stream = NULL;
bb47de73 5562
4b9674e5 5563 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 5564
4b9674e5 5565 *lock_and_validation_needed = true;
62f55537 5566
4b9674e5
LL		 5567 } else {/* Add stream for any updated/enabled CRTC */
5568 /*
5569 * Quick fix to prevent NULL pointer on new_stream when
5570 * added MST connectors not found in existing crtc_state in the chained mode
5571 * TODO: need to dig out the root cause of that
5572 */
5573 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
5574 goto skip_modeset;
62f55537 5575
4b9674e5
LL		 5576 if (modereset_required(new_crtc_state))
5577 goto skip_modeset;
62f55537 5578
4b9674e5
LL		 5579 if (modeset_required(new_crtc_state, new_stream,
5580 dm_old_crtc_state->stream)) {
62f55537 5581
4b9674e5 5582 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 5583
4b9674e5
LL		 5584 ret = dm_atomic_get_state(state, &dm_state);
5585 if (ret)
5586 goto fail;
27b3f4fc 5587
4b9674e5 5588 dm_new_crtc_state->stream = new_stream;
62f55537 5589
4b9674e5 5590 dc_stream_retain(new_stream);
1dc90497 5591
4b9674e5
LL		 5592 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
5593 crtc->base.id);
1dc90497 5594
4b9674e5
LL		 5595 if (dc_add_stream_to_ctx(
5596 dm->dc,
5597 dm_state->context,
5598 dm_new_crtc_state->stream) != DC_OK) {
5599 ret = -EINVAL;
5600 goto fail;
9b690ef3
BL		 5601 }
5602
4b9674e5
LL		 5603 *lock_and_validation_needed = true;
5604 }
5605 }
e277adc5 5606
4b9674e5
LL		 5607skip_modeset:
5608 /* Release extra reference */
5609 if (new_stream)
5610 dc_stream_release(new_stream);
e277adc5 5611
4b9674e5
LL		 5612 /*
5613 * We want to do dc stream updates that do not require a
5614 * full modeset below.
5615 */
5616 if (!(enable && aconnector && new_crtc_state->enable &&
5617 new_crtc_state->active))
5618 return 0;
5619 /*
5620 * Given above conditions, the dc state cannot be NULL because:
5621 * 1. We're in the process of enabling CRTCs (just been added
5622 * to the dc context, or already is on the context)
5623 * 2. Has a valid connector attached, and
5624 * 3. Is currently active and enabled.
5625 * => The dc stream state currently exists.
5626 */
5627 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 5628
4b9674e5
LL		 5629 /* Scaling or underscan settings */
5630 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
5631 update_stream_scaling_settings(
5632 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 5633
4b9674e5
LL		 5634 /*
5635 * Color management settings. We also update color properties
5636 * when a modeset is needed, to ensure it gets reprogrammed.
5637 */
5638 if (dm_new_crtc_state->base.color_mgmt_changed ||
5639 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
5640 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
5641 if (ret)
5642 goto fail;
5643 amdgpu_dm_set_ctm(dm_new_crtc_state);
62f55537 5644 }
e7b07cee 5645
4b9674e5
LL		 5646 /* Update Freesync settings. */
5647 get_freesync_config_for_crtc(dm_new_crtc_state,
5648 dm_new_conn_state);
5649
62f55537 5650 return ret;
9635b754
DS		 5651
5652fail:
5653 if (new_stream)
5654 dc_stream_release(new_stream);
5655 return ret;
62f55537 5656}
9b690ef3 5657
9e869063
LL		 5658static int dm_update_plane_state(struct dc *dc,
5659 struct drm_atomic_state *state,
5660 struct drm_plane *plane,
5661 struct drm_plane_state *old_plane_state,
5662 struct drm_plane_state *new_plane_state,
5663 bool enable,
5664 bool *lock_and_validation_needed)
62f55537 5665{
eb3dc897
NK		 5666
5667 struct dm_atomic_state *dm_state = NULL;
62f55537 5668 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 5669 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 5670 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 5671 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 5672 /* TODO return page_flip_needed() function */
5673 bool pflip_needed = !state->allow_modeset;
5674 int ret = 0;
e7b07cee 5675
9b690ef3 5676
9e869063
LL		 5677 new_plane_crtc = new_plane_state->crtc;
5678 old_plane_crtc = old_plane_state->crtc;
5679 dm_new_plane_state = to_dm_plane_state(new_plane_state);
5680 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 5681
9e869063
LL		 5682 /*TODO Implement atomic check for cursor plane */
5683 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5684 return 0;
9b690ef3 5685
9e869063
LL		 5686 /* Remove any changed/removed planes */
5687 if (!enable) {
5688 if (pflip_needed &&
5689 plane->type != DRM_PLANE_TYPE_OVERLAY)
5690 return 0;
a7b06724 5691
9e869063
LL		 5692 if (!old_plane_crtc)
5693 return 0;
62f55537 5694
9e869063
LL		 5695 old_crtc_state = drm_atomic_get_old_crtc_state(
5696 state, old_plane_crtc);
5697 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 5698
9e869063
LL		 5699 if (!dm_old_crtc_state->stream)
5700 return 0;
62f55537 5701
9e869063
LL		 5702 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
5703 plane->base.id, old_plane_crtc->base.id);
9b690ef3 5704
9e869063
LL		 5705 ret = dm_atomic_get_state(state, &dm_state);
5706 if (ret)
5707 return ret;
eb3dc897 5708
9e869063
LL		 5709 if (!dc_remove_plane_from_context(
5710 dc,
5711 dm_old_crtc_state->stream,
5712 dm_old_plane_state->dc_state,
5713 dm_state->context)) {
62f55537 5714
9e869063
LL		 5715 ret = EINVAL;
5716 return ret;
5717 }
e7b07cee 5718
9b690ef3 5719
9e869063
LL		 5720 dc_plane_state_release(dm_old_plane_state->dc_state);
5721 dm_new_plane_state->dc_state = NULL;
1dc90497 5722
9e869063 5723 *lock_and_validation_needed = true;
1dc90497 5724
9e869063
LL		 5725 } else { /* Add new planes */
5726 struct dc_plane_state *dc_new_plane_state;
1dc90497 5727
9e869063
LL		 5728 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
5729 return 0;
e7b07cee 5730
9e869063
LL		 5731 if (!new_plane_crtc)
5732 return 0;
e7b07cee 5733
9e869063
LL		 5734 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
5735 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 5736
9e869063
LL		 5737 if (!dm_new_crtc_state->stream)
5738 return 0;
62f55537 5739
9e869063
LL		 5740 if (pflip_needed && plane->type != DRM_PLANE_TYPE_OVERLAY)
5741 return 0;
62f55537 5742
9e869063 5743 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 5744
9e869063
LL		 5745 dc_new_plane_state = dc_create_plane_state(dc);
5746 if (!dc_new_plane_state)
5747 return -ENOMEM;
62f55537 5748
9e869063
LL		 5749 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5750 plane->base.id, new_plane_crtc->base.id);
8c45c5db 5751
9e869063
LL		 5752 ret = fill_plane_attributes(
5753 new_plane_crtc->dev->dev_private,
5754 dc_new_plane_state,
5755 new_plane_state,
5756 new_crtc_state);
5757 if (ret) {
5758 dc_plane_state_release(dc_new_plane_state);
5759 return ret;
5760 }
62f55537 5761
9e869063
LL		 5762 ret = dm_atomic_get_state(state, &dm_state);
5763 if (ret) {
5764 dc_plane_state_release(dc_new_plane_state);
5765 return ret;
5766 }
eb3dc897 5767
9e869063
LL		 5768 /*
5769 * Any atomic check errors that occur after this will
5770 * not need a release. The plane state will be attached
5771 * to the stream, and therefore part of the atomic
5772 * state. It'll be released when the atomic state is
5773 * cleaned.
5774 */
5775 if (!dc_add_plane_to_context(
5776 dc,
5777 dm_new_crtc_state->stream,
5778 dc_new_plane_state,
5779 dm_state->context)) {
62f55537 5780
9e869063
LL		 5781 dc_plane_state_release(dc_new_plane_state);
5782 return -EINVAL;
5783 }
8c45c5db 5784
9e869063 5785 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 5786
9e869063
LL		 5787 /* Tell DC to do a full surface update every time there
5788 * is a plane change. Inefficient, but works for now.
5789 */
5790 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5791
5792 *lock_and_validation_needed = true;
62f55537 5793 }
e7b07cee
HW		 5794
5795
62f55537
AG		 5796 return ret;
5797}
a87fa993 5798
eb3dc897
NK		 5799static int
5800dm_determine_update_type_for_commit(struct dc *dc,
5801 struct drm_atomic_state *state,
5802 enum surface_update_type *out_type)
5803{
5804 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
5805 int i, j, num_plane, ret = 0;
a87fa993
BL		 5806 struct drm_plane_state *old_plane_state, *new_plane_state;
5807 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
5808 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5809 struct drm_plane *plane;
5810
5811 struct drm_crtc *crtc;
5812 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
5813 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
5814 struct dc_stream_status *status = NULL;
5815
fe96b99d
GS		 5816 struct dc_surface_update *updates;
5817 struct dc_plane_state *surface;
a87fa993
BL		 5818 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5819
fe96b99d
GS		 5820 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
5821 surface = kcalloc(MAX_SURFACES, sizeof(*surface), GFP_KERNEL);
5822
4f712911
BL		 5823 if (!updates || !surface) {
5824 DRM_ERROR("Plane or surface update failed to allocate");
5825 /* Set type to FULL to avoid crashing in DC*/
5826 update_type = UPDATE_TYPE_FULL;
eb3dc897 5827 goto cleanup;
4f712911 5828 }
a87fa993
BL		 5829
5830 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
c448a53a
NK		 5831 struct dc_stream_update stream_update = { 0 };
5832
a87fa993
BL		 5833 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5834 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
5835 num_plane = 0;
5836
6836d239
NK		 5837 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
5838 update_type = UPDATE_TYPE_FULL;
5839 goto cleanup;
5840 }
a87fa993 5841
6836d239 5842 if (!new_dm_crtc_state->stream)
c744e974 5843 continue;
eb3dc897 5844
c744e974
NK		 5845 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5846 new_plane_crtc = new_plane_state->crtc;
5847 old_plane_crtc = old_plane_state->crtc;
5848 new_dm_plane_state = to_dm_plane_state(new_plane_state);
5849 old_dm_plane_state = to_dm_plane_state(old_plane_state);
eb3dc897 5850
c744e974
NK		 5851 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5852 continue;
eb3dc897 5853
6836d239
NK		 5854 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
5855 update_type = UPDATE_TYPE_FULL;
5856 goto cleanup;
5857 }
5858
c744e974
NK		 5859 if (!state->allow_modeset)
5860 continue;
a87fa993 5861
c744e974
NK		 5862 if (crtc != new_plane_crtc)
5863 continue;
5864
5865 updates[num_plane].surface = &surface[num_plane];
5866
5867 if (new_crtc_state->mode_changed) {
5868 updates[num_plane].surface->src_rect =
5869 new_dm_plane_state->dc_state->src_rect;
5870 updates[num_plane].surface->dst_rect =
5871 new_dm_plane_state->dc_state->dst_rect;
5872 updates[num_plane].surface->rotation =
5873 new_dm_plane_state->dc_state->rotation;
5874 updates[num_plane].surface->in_transfer_func =
5875 new_dm_plane_state->dc_state->in_transfer_func;
5876 stream_update.dst = new_dm_crtc_state->stream->dst;
5877 stream_update.src = new_dm_crtc_state->stream->src;
5878 }
5879
5880 if (new_crtc_state->color_mgmt_changed) {
5881 updates[num_plane].gamma =
5882 new_dm_plane_state->dc_state->gamma_correction;
5883 updates[num_plane].in_transfer_func =
5884 new_dm_plane_state->dc_state->in_transfer_func;
5885 stream_update.gamut_remap =
5886 &new_dm_crtc_state->stream->gamut_remap_matrix;
5887 stream_update.out_transfer_func =
5888 new_dm_crtc_state->stream->out_transfer_func;
a87fa993
BL		 5889 }
5890
c744e974
NK		 5891 num_plane++;
5892 }
5893
5894 if (num_plane == 0)
5895 continue;
5896
5897 ret = dm_atomic_get_state(state, &dm_state);
5898 if (ret)
5899 goto cleanup;
5900
5901 old_dm_state = dm_atomic_get_old_state(state);
5902 if (!old_dm_state) {
5903 ret = -EINVAL;
5904 goto cleanup;
5905 }
5906
5907 status = dc_stream_get_status_from_state(old_dm_state->context,
5908 new_dm_crtc_state->stream);
5909
5910 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5911 &stream_update, status);
5912
5913 if (update_type > UPDATE_TYPE_MED) {
a87fa993 5914 update_type = UPDATE_TYPE_FULL;
eb3dc897 5915 goto cleanup;
a87fa993
BL		 5916 }
5917 }
5918
eb3dc897 5919cleanup:
a87fa993
BL		 5920 kfree(updates);
5921 kfree(surface);
5922
eb3dc897
NK		 5923 *out_type = update_type;
5924 return ret;
a87fa993 5925}
62f55537 5926
b8592b48
LL		 5927/**
5928 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
5929 * @dev: The DRM device
5930 * @state: The atomic state to commit
5931 *
5932 * Validate that the given atomic state is programmable by DC into hardware.
5933 * This involves constructing a &struct dc_state reflecting the new hardware
5934 * state we wish to commit, then querying DC to see if it is programmable. It's
5935 * important not to modify the existing DC state. Otherwise, atomic_check
5936 * may unexpectedly commit hardware changes.
5937 *
5938 * When validating the DC state, it's important that the right locks are
5939 * acquired. For full updates case which removes/adds/updates streams on one
5940 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
5941 * that any such full update commit will wait for completion of any outstanding
5942 * flip using DRMs synchronization events. See
5943 * dm_determine_update_type_for_commit()
5944 *
5945 * Note that DM adds the affected connectors for all CRTCs in state, when that
5946 * might not seem necessary. This is because DC stream creation requires the
5947 * DC sink, which is tied to the DRM connector state. Cleaning this up should
5948 * be possible but non-trivial - a possible TODO item.
5949 *
5950 * Return: -Error code if validation failed.
5951 */
7578ecda
AD		 5952static int amdgpu_dm_atomic_check(struct drm_device *dev,
5953 struct drm_atomic_state *state)
62f55537 5954{
62f55537 5955 struct amdgpu_device *adev = dev->dev_private;
eb3dc897 5956 struct dm_atomic_state *dm_state = NULL;
62f55537 5957 struct dc *dc = adev->dm.dc;
62f55537 5958 struct drm_connector *connector;
c2cea706 5959 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 5960 struct drm_crtc *crtc;
fc9e9920 5961 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 5962 struct drm_plane *plane;
5963 struct drm_plane_state *old_plane_state, *new_plane_state;
a87fa993
BL		 5964 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5965 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
5966
1e88ad0a 5967 int ret, i;
e7b07cee 5968
62f55537
AG		 5969 /*
5970 * This bool will be set for true for any modeset/reset
5971 * or plane update which implies non fast surface update.
5972 */
5973 bool lock_and_validation_needed = false;
5974
5975 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 5976 if (ret)
5977 goto fail;
62f55537 5978
1e88ad0a
S		 5979 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5980 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 5981 !new_crtc_state->color_mgmt_changed &&
a93587b3 5982 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
1e88ad0a 5983 continue;
7bef1af3 5984
1e88ad0a
S		 5985 if (!new_crtc_state->enable)
5986 continue;
fc9e9920 5987
1e88ad0a
S		 5988 ret = drm_atomic_add_affected_connectors(state, crtc);
5989 if (ret)
5990 return ret;
fc9e9920 5991
1e88ad0a
S		 5992 ret = drm_atomic_add_affected_planes(state, crtc);
5993 if (ret)
5994 goto fail;
e7b07cee
HW		 5995 }
5996
2d9e6431
NK		 5997 /*
5998 * Add all primary and overlay planes on the CRTC to the state
5999 * whenever a plane is enabled to maintain correct z-ordering
6000 * and to enable fast surface updates.
6001 */
6002 drm_for_each_crtc(crtc, dev) {
6003 bool modified = false;
6004
6005 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
6006 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6007 continue;
6008
6009 if (new_plane_state->crtc == crtc ||
6010 old_plane_state->crtc == crtc) {
6011 modified = true;
6012 break;
6013 }
6014 }
6015
6016 if (!modified)
6017 continue;
6018
6019 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
6020 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6021 continue;
6022
6023 new_plane_state =
6024 drm_atomic_get_plane_state(state, plane);
6025
6026 if (IS_ERR(new_plane_state)) {
6027 ret = PTR_ERR(new_plane_state);
6028 goto fail;
6029 }
6030 }
6031 }
6032
62f55537 6033 /* Remove exiting planes if they are modified */
9e869063
LL		 6034 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6035 ret = dm_update_plane_state(dc, state, plane,
6036 old_plane_state,
6037 new_plane_state,
6038 false,
6039 &lock_and_validation_needed);
6040 if (ret)
6041 goto fail;
62f55537
AG		 6042 }
6043
6044 /* Disable all crtcs which require disable */
4b9674e5
LL		 6045 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6046 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6047 old_crtc_state,
6048 new_crtc_state,
6049 false,
6050 &lock_and_validation_needed);
6051 if (ret)
6052 goto fail;
62f55537
AG		 6053 }
6054
6055 /* Enable all crtcs which require enable */
4b9674e5
LL		 6056 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6057 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6058 old_crtc_state,
6059 new_crtc_state,
6060 true,
6061 &lock_and_validation_needed);
6062 if (ret)
6063 goto fail;
62f55537
AG		 6064 }
6065
6066 /* Add new/modified planes */
9e869063
LL		 6067 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6068 ret = dm_update_plane_state(dc, state, plane,
6069 old_plane_state,
6070 new_plane_state,
6071 true,
6072 &lock_and_validation_needed);
6073 if (ret)
6074 goto fail;
62f55537
AG		 6075 }
6076
b349f76e
ES		 6077 /* Run this here since we want to validate the streams we created */
6078 ret = drm_atomic_helper_check_planes(dev, state);
6079 if (ret)
6080 goto fail;
62f55537 6081
ebdd27e1 6082 /* Check scaling and underscan changes*/
1f6010a9 6083 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 6084 * new stream into context w\o causing full reset. Need to
6085 * decide how to handle.
6086 */
c2cea706 6087 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 6088 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6089 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6090 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 6091
6092 /* Skip any modesets/resets */
0bc9706d
LSL		 6093 if (!acrtc || drm_atomic_crtc_needs_modeset(
6094 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 6095 continue;
6096
b830ebc9 6097 /* Skip any thing not scale or underscan changes */
54d76575 6098 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 6099 continue;
6100
a87fa993 6101 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 6102 lock_and_validation_needed = true;
6103 }
6104
eb3dc897
NK		 6105 ret = dm_determine_update_type_for_commit(dc, state, &update_type);
6106 if (ret)
6107 goto fail;
a87fa993
BL		 6108
6109 if (overall_update_type < update_type)
6110 overall_update_type = update_type;
6111
6112 /*
6113 * lock_and_validation_needed was an old way to determine if we need to set
6114 * the global lock. Leaving it in to check if we broke any corner cases
6115 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
6116 * lock_and_validation_needed false = UPDATE_TYPE_FAST
6117 */
6118 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
6119 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
6120 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
6121 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
e7b07cee 6122
e7b07cee 6123
a87fa993 6124 if (overall_update_type > UPDATE_TYPE_FAST) {
eb3dc897
NK		 6125 ret = dm_atomic_get_state(state, &dm_state);
6126 if (ret)
6127 goto fail;
e7b07cee
HW		 6128
6129 ret = do_aquire_global_lock(dev, state);
6130 if (ret)
6131 goto fail;
1dc90497 6132
e750d56d 6133 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 6134 ret = -EINVAL;
6135 goto fail;
6136 }
674e78ac
NK		 6137 } else if (state->legacy_cursor_update) {
6138 /*
6139 * This is a fast cursor update coming from the plane update
6140 * helper, check if it can be done asynchronously for better
6141 * performance.
6142 */
6143 state->async_update = !drm_atomic_helper_async_check(dev, state);
e7b07cee
HW		 6144 }
6145
6146 /* Must be success */
6147 WARN_ON(ret);
6148 return ret;
6149
6150fail:
6151 if (ret == -EDEADLK)
01e28f9c 6152 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 6153 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 6154 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 6155 else
01e28f9c 6156 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 6157
6158 return ret;
6159}
6160
3ee6b26b
AD		 6161static bool is_dp_capable_without_timing_msa(struct dc *dc,
6162 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 6163{
6164 uint8_t dpcd_data;
6165 bool capable = false;
6166
c84dec2f 6167 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 6168 dm_helpers_dp_read_dpcd(
6169 NULL,
c84dec2f 6170 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 6171 DP_DOWN_STREAM_PORT_COUNT,
6172 &dpcd_data,
6173 sizeof(dpcd_data))) {
6174 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
6175 }
6176
6177 return capable;
6178}
98e6436d
AK		 6179void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
6180 struct edid *edid)
e7b07cee
HW		 6181{
6182 int i;
e7b07cee
HW		 6183 bool edid_check_required;
6184 struct detailed_timing *timing;
6185 struct detailed_non_pixel *data;
6186 struct detailed_data_monitor_range *range;
c84dec2f
HW		 6187 struct amdgpu_dm_connector *amdgpu_dm_connector =
6188 to_amdgpu_dm_connector(connector);
bb47de73 6189 struct dm_connector_state *dm_con_state = NULL;
e7b07cee
HW		 6190
6191 struct drm_device *dev = connector->dev;
6192 struct amdgpu_device *adev = dev->dev_private;
bb47de73 6193 bool freesync_capable = false;
b830ebc9 6194
8218d7f1
HW		 6195 if (!connector->state) {
6196 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 6197 goto update;
8218d7f1
HW		 6198 }
6199
98e6436d
AK		 6200 if (!edid) {
6201 dm_con_state = to_dm_connector_state(connector->state);
6202
6203 amdgpu_dm_connector->min_vfreq = 0;
6204 amdgpu_dm_connector->max_vfreq = 0;
6205 amdgpu_dm_connector->pixel_clock_mhz = 0;
6206
bb47de73 6207 goto update;
98e6436d
AK		 6208 }
6209
8218d7f1
HW		 6210 dm_con_state = to_dm_connector_state(connector->state);
6211
e7b07cee 6212 edid_check_required = false;
c84dec2f 6213 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee 6214 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
bb47de73 6215 goto update;
e7b07cee
HW		 6216 }
6217 if (!adev->dm.freesync_module)
bb47de73 6218 goto update;
e7b07cee
HW		 6219 /*
6220 * if edid non zero restrict freesync only for dp and edp
6221 */
6222 if (edid) {
c84dec2f
HW		 6223 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
6224 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 6225 edid_check_required = is_dp_capable_without_timing_msa(
6226 adev->dm.dc,
c84dec2f 6227 amdgpu_dm_connector);
e7b07cee
HW		 6228 }
6229 }
e7b07cee
HW		 6230 if (edid_check_required == true && (edid->version > 1 ||
6231 (edid->version == 1 && edid->revision > 1))) {
6232 for (i = 0; i < 4; i++) {
6233
6234 timing = &edid->detailed_timings[i];
6235 data = &timing->data.other_data;
6236 range = &data->data.range;
6237 /*
6238 * Check if monitor has continuous frequency mode
6239 */
6240 if (data->type != EDID_DETAIL_MONITOR_RANGE)
6241 continue;
6242 /*
6243 * Check for flag range limits only. If flag == 1 then
6244 * no additional timing information provided.
6245 * Default GTF, GTF Secondary curve and CVT are not
6246 * supported
6247 */
6248 if (range->flags != 1)
6249 continue;
6250
c84dec2f
HW		 6251 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6252 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6253 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 6254 range->pixel_clock_mhz * 10;
6255 break;
6256 }
6257
c84dec2f 6258 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 6259 amdgpu_dm_connector->min_vfreq > 10) {
6260
bb47de73 6261 freesync_capable = true;
e7b07cee
HW		 6262 }
6263 }
bb47de73
NK		 6264
6265update:
6266 if (dm_con_state)
6267 dm_con_state->freesync_capable = freesync_capable;
6268
6269 if (connector->vrr_capable_property)
6270 drm_connector_set_vrr_capable_property(connector,
6271 freesync_capable);
e7b07cee
HW		 6272}
6273
Linux 6.x block layer and io_uring tree(s)