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drm/amd/display: Add support for hw_state logging via debugfs
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 42#if defined(CONFIG_DEBUG_FS)
43#include "amdgpu_dm_debugfs.h"
44#endif
4562236b
HW		 45
46#include "ivsrcid/ivsrcid_vislands30.h"
47
48#include <linux/module.h>
49#include <linux/moduleparam.h>
50#include <linux/version.h>
e7b07cee 51#include <linux/types.h>
97028037 52#include <linux/pm_runtime.h>
4562236b 53
e7b07cee 54#include <drm/drmP.h>
4562236b
HW		 55#include <drm/drm_atomic.h>
56#include <drm/drm_atomic_helper.h>
57#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 58#include <drm/drm_fb_helper.h>
59#include <drm/drm_edid.h>
4562236b 60
dc37a9a0 61#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 62#include "ivsrcid/irqsrcs_dcn_1_0.h"
63
ad941f7a
FX		 64#include "dcn/dcn_1_0_offset.h"
65#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 66#include "soc15_hw_ip.h"
67#include "vega10_ip_offset.h"
ff5ef992
AD		 68
69#include "soc15_common.h"
70#endif
71
e7b07cee
HW		 72#include "modules/inc/mod_freesync.h"
73
7578ecda
AD		 74/* basic init/fini API */
75static int amdgpu_dm_init(struct amdgpu_device *adev);
76static void amdgpu_dm_fini(struct amdgpu_device *adev);
77
78/* initializes drm_device display related structures, based on the information
79 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
80 * drm_encoder, drm_mode_config
81 *
82 * Returns 0 on success
83 */
84static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
85/* removes and deallocates the drm structures, created by the above function */
86static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
87
88static void
89amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
90
91static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
92 struct amdgpu_plane *aplane,
93 unsigned long possible_crtcs);
94static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
95 struct drm_plane *plane,
96 uint32_t link_index);
97static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
98 struct amdgpu_dm_connector *amdgpu_dm_connector,
99 uint32_t link_index,
100 struct amdgpu_encoder *amdgpu_encoder);
101static int amdgpu_dm_encoder_init(struct drm_device *dev,
102 struct amdgpu_encoder *aencoder,
103 uint32_t link_index);
104
105static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
106
107static int amdgpu_dm_atomic_commit(struct drm_device *dev,
108 struct drm_atomic_state *state,
109 bool nonblock);
110
111static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
112
113static int amdgpu_dm_atomic_check(struct drm_device *dev,
114 struct drm_atomic_state *state);
115
116
117
e7b07cee 118
e04a6123 119static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125 DRM_PLANE_TYPE_PRIMARY,
126};
127
e04a6123 128static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_PRIMARY,
132 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
133};
134
e04a6123 135static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_PRIMARY,
138 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
139};
140
4562236b
HW		 141/*
142 * dm_vblank_get_counter
143 *
144 * @brief
145 * Get counter for number of vertical blanks
146 *
147 * @param
148 * struct amdgpu_device *adev - [in] desired amdgpu device
149 * int disp_idx - [in] which CRTC to get the counter from
150 *
151 * @return
152 * Counter for vertical blanks
153 */
154static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
155{
156 if (crtc >= adev->mode_info.num_crtc)
157 return 0;
158 else {
159 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 160 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
161 acrtc->base.state);
4562236b 162
da5c47f6
AG		 163
164 if (acrtc_state->stream == NULL) {
0971c40e
HW		 165 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
166 crtc);
4562236b
HW		 167 return 0;
168 }
169
da5c47f6 170 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 171 }
172}
173
174static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 175 u32 *vbl, u32 *position)
4562236b 176{
81c50963
ST		 177 uint32_t v_blank_start, v_blank_end, h_position, v_position;
178
4562236b
HW		 179 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
180 return -EINVAL;
181 else {
182 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 183 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
184 acrtc->base.state);
4562236b 185
da5c47f6 186 if (acrtc_state->stream == NULL) {
0971c40e
HW		 187 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
188 crtc);
4562236b
HW		 189 return 0;
190 }
191
81c50963
ST		 192 /*
193 * TODO rework base driver to use values directly.
194 * for now parse it back into reg-format
195 */
da5c47f6 196 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 197 &v_blank_start,
198 &v_blank_end,
199 &h_position,
200 &v_position);
201
e806208d
AG		 202 *position = v_position | (h_position << 16);
203 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 204 }
205
206 return 0;
207}
208
209static bool dm_is_idle(void *handle)
210{
211 /* XXX todo */
212 return true;
213}
214
215static int dm_wait_for_idle(void *handle)
216{
217 /* XXX todo */
218 return 0;
219}
220
221static bool dm_check_soft_reset(void *handle)
222{
223 return false;
224}
225
226static int dm_soft_reset(void *handle)
227{
228 /* XXX todo */
229 return 0;
230}
231
3ee6b26b
AD		 232static struct amdgpu_crtc *
233get_crtc_by_otg_inst(struct amdgpu_device *adev,
234 int otg_inst)
4562236b
HW		 235{
236 struct drm_device *dev = adev->ddev;
237 struct drm_crtc *crtc;
238 struct amdgpu_crtc *amdgpu_crtc;
239
240 /*
241 * following if is check inherited from both functions where this one is
242 * used now. Need to be checked why it could happen.
243 */
244 if (otg_inst == -1) {
245 WARN_ON(1);
246 return adev->mode_info.crtcs[0];
247 }
248
249 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
250 amdgpu_crtc = to_amdgpu_crtc(crtc);
251
252 if (amdgpu_crtc->otg_inst == otg_inst)
253 return amdgpu_crtc;
254 }
255
256 return NULL;
257}
258
259static void dm_pflip_high_irq(void *interrupt_params)
260{
4562236b
HW		 261 struct amdgpu_crtc *amdgpu_crtc;
262 struct common_irq_params *irq_params = interrupt_params;
263 struct amdgpu_device *adev = irq_params->adev;
264 unsigned long flags;
265
266 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
267
268 /* IRQ could occur when in initial stage */
269 /*TODO work and BO cleanup */
270 if (amdgpu_crtc == NULL) {
271 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
272 return;
273 }
274
275 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 276
277 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
278 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
279 amdgpu_crtc->pflip_status,
280 AMDGPU_FLIP_SUBMITTED,
281 amdgpu_crtc->crtc_id,
282 amdgpu_crtc);
283 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
284 return;
285 }
286
4562236b
HW		 287
288 /* wakeup usersapce */
1159898a 289 if (amdgpu_crtc->event) {
753c66c9
MK		 290 /* Update to correct count/ts if racing with vblank irq */
291 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
292
54f5499a 293 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 294
54f5499a
AG		 295 /* page flip completed. clean up */
296 amdgpu_crtc->event = NULL;
1159898a 297
54f5499a
AG		 298 } else
299 WARN_ON(1);
4562236b 300
54f5499a 301 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 302 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
303
54f5499a
AG		 304 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
305 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 306
307 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 308}
309
310static void dm_crtc_high_irq(void *interrupt_params)
311{
312 struct common_irq_params *irq_params = interrupt_params;
313 struct amdgpu_device *adev = irq_params->adev;
4562236b
HW		 314 struct amdgpu_crtc *acrtc;
315
b57de80a 316 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 317
e5d0170e
LSL		 318 if (acrtc) {
319 drm_crtc_handle_vblank(&acrtc->base);
320 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
321 }
4562236b
HW		 322}
323
324static int dm_set_clockgating_state(void *handle,
325 enum amd_clockgating_state state)
326{
327 return 0;
328}
329
330static int dm_set_powergating_state(void *handle,
331 enum amd_powergating_state state)
332{
333 return 0;
334}
335
336/* Prototypes of private functions */
337static int dm_early_init(void* handle);
338
339static void hotplug_notify_work_func(struct work_struct *work)
340{
341 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
342 struct drm_device *dev = dm->ddev;
343
344 drm_kms_helper_hotplug_event(dev);
345}
346
a32e24b4 347/* Allocate memory for FBC compressed data */
3e332d3a 348static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 349{
3e332d3a
RL		 350 struct drm_device *dev = connector->dev;
351 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 352 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 353 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
354 struct drm_display_mode *mode;
42e67c3b
RL		 355 unsigned long max_size = 0;
356
357 if (adev->dm.dc->fbc_compressor == NULL)
358 return;
a32e24b4 359
3e332d3a 360 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 361 return;
362
3e332d3a
RL		 363 if (compressor->bo_ptr)
364 return;
42e67c3b 365
42e67c3b 366
3e332d3a
RL		 367 list_for_each_entry(mode, &connector->modes, head) {
368 if (max_size < mode->htotal * mode->vtotal)
369 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 370 }
371
372 if (max_size) {
373 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 374 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 375 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 376
377 if (r)
42e67c3b
RL		 378 DRM_ERROR("DM: Failed to initialize FBC\n");
379 else {
380 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
381 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
382 }
383
a32e24b4
RL		 384 }
385
386}
a32e24b4
RL		 387
388
4562236b
HW		 389/* Init display KMS
390 *
391 * Returns 0 on success
392 */
7578ecda 393static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 394{
395 struct dc_init_data init_data;
396 adev->dm.ddev = adev->ddev;
397 adev->dm.adev = adev;
398
4562236b
HW		 399 /* Zero all the fields */
400 memset(&init_data, 0, sizeof(init_data));
401
4562236b
HW		 402 if(amdgpu_dm_irq_init(adev)) {
403 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
404 goto error;
405 }
406
407 init_data.asic_id.chip_family = adev->family;
408
409 init_data.asic_id.pci_revision_id = adev->rev_id;
410 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
411
770d13b1 412 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 413 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
414 init_data.asic_id.atombios_base_address =
415 adev->mode_info.atom_context->bios;
416
417 init_data.driver = adev;
418
419 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
420
421 if (!adev->dm.cgs_device) {
422 DRM_ERROR("amdgpu: failed to create cgs device.\n");
423 goto error;
424 }
425
426 init_data.cgs_device = adev->dm.cgs_device;
427
428 adev->dm.dal = NULL;
429
430 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
431
6e227308
HW		 432 /*
433 * TODO debug why this doesn't work on Raven
434 */
435 if (adev->flags & AMD_IS_APU &&
436 adev->asic_type >= CHIP_CARRIZO &&
437 adev->asic_type < CHIP_RAVEN)
438 init_data.flags.gpu_vm_support = true;
439
4562236b
HW		 440 /* Display Core create. */
441 adev->dm.dc = dc_create(&init_data);
442
423788c7 443 if (adev->dm.dc) {
76121231 444 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 445 } else {
76121231 446 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 447 goto error;
448 }
4562236b
HW		 449
450 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
451
452 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
453 if (!adev->dm.freesync_module) {
454 DRM_ERROR(
455 "amdgpu: failed to initialize freesync_module.\n");
456 } else
f1ad2f5e 457 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 458 adev->dm.freesync_module);
459
e277adc5
LSL		 460 amdgpu_dm_init_color_mod();
461
4562236b
HW		 462 if (amdgpu_dm_initialize_drm_device(adev)) {
463 DRM_ERROR(
464 "amdgpu: failed to initialize sw for display support.\n");
465 goto error;
466 }
467
468 /* Update the actual used number of crtc */
469 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
470
471 /* TODO: Add_display_info? */
472
473 /* TODO use dynamic cursor width */
ce75805e
AG		 474 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
475 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 476
477 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
478 DRM_ERROR(
479 "amdgpu: failed to initialize sw for display support.\n");
480 goto error;
481 }
482
e498eb71
NK		 483#if defined(CONFIG_DEBUG_FS)
484 if (dtn_debugfs_init(adev))
485 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
486#endif
487
f1ad2f5e 488 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 489
490 return 0;
491error:
492 amdgpu_dm_fini(adev);
493
494 return -1;
495}
496
7578ecda 497static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 498{
499 amdgpu_dm_destroy_drm_device(&adev->dm);
500 /*
501 * TODO: pageflip, vlank interrupt
502 *
503 * amdgpu_dm_irq_fini(adev);
504 */
505
506 if (adev->dm.cgs_device) {
507 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
508 adev->dm.cgs_device = NULL;
509 }
510 if (adev->dm.freesync_module) {
511 mod_freesync_destroy(adev->dm.freesync_module);
512 adev->dm.freesync_module = NULL;
513 }
514 /* DC Destroy TODO: Replace destroy DAL */
21de3396 515 if (adev->dm.dc)
4562236b 516 dc_destroy(&adev->dm.dc);
4562236b
HW		 517 return;
518}
519
4562236b
HW		 520static int dm_sw_init(void *handle)
521{
522 return 0;
523}
524
525static int dm_sw_fini(void *handle)
526{
527 return 0;
528}
529
7abcf6b5 530static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 531{
c84dec2f 532 struct amdgpu_dm_connector *aconnector;
4562236b 533 struct drm_connector *connector;
7abcf6b5 534 int ret = 0;
4562236b
HW		 535
536 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
537
538 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 539 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 540 if (aconnector->dc_link->type == dc_connection_mst_branch &&
541 aconnector->mst_mgr.aux) {
f1ad2f5e 542 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 543 aconnector, aconnector->base.base.id);
544
545 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
546 if (ret < 0) {
547 DRM_ERROR("DM_MST: Failed to start MST\n");
548 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
549 return ret;
4562236b 550 }
7abcf6b5 551 }
4562236b
HW		 552 }
553
554 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 555 return ret;
556}
557
558static int dm_late_init(void *handle)
559{
42e67c3b 560 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 561
42e67c3b 562 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 563}
564
565static void s3_handle_mst(struct drm_device *dev, bool suspend)
566{
c84dec2f 567 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 568 struct drm_connector *connector;
569
570 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
571
572 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 573 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 574 if (aconnector->dc_link->type == dc_connection_mst_branch &&
575 !aconnector->mst_port) {
576
577 if (suspend)
578 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
579 else
580 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
581 }
582 }
583
584 drm_modeset_unlock(&dev->mode_config.connection_mutex);
585}
586
587static int dm_hw_init(void *handle)
588{
589 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
590 /* Create DAL display manager */
591 amdgpu_dm_init(adev);
4562236b
HW		 592 amdgpu_dm_hpd_init(adev);
593
4562236b
HW		 594 return 0;
595}
596
597static int dm_hw_fini(void *handle)
598{
599 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
600
601 amdgpu_dm_hpd_fini(adev);
602
603 amdgpu_dm_irq_fini(adev);
21de3396 604 amdgpu_dm_fini(adev);
4562236b
HW		 605 return 0;
606}
607
608static int dm_suspend(void *handle)
609{
610 struct amdgpu_device *adev = handle;
611 struct amdgpu_display_manager *dm = &adev->dm;
612 int ret = 0;
4562236b
HW		 613
614 s3_handle_mst(adev->ddev, true);
615
4562236b
HW		 616 amdgpu_dm_irq_suspend(adev);
617
0a214e2f 618 WARN_ON(adev->dm.cached_state);
a3621485
AG		 619 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
620
32f5062d 621 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 622
623 return ret;
624}
625
1daf8c63
AD		 626static struct amdgpu_dm_connector *
627amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
628 struct drm_crtc *crtc)
4562236b
HW		 629{
630 uint32_t i;
c2cea706 631 struct drm_connector_state *new_con_state;
4562236b
HW		 632 struct drm_connector *connector;
633 struct drm_crtc *crtc_from_state;
634
c2cea706
LSL		 635 for_each_new_connector_in_state(state, connector, new_con_state, i) {
636 crtc_from_state = new_con_state->crtc;
4562236b
HW		 637
638 if (crtc_from_state == crtc)
c84dec2f 639 return to_amdgpu_dm_connector(connector);
4562236b
HW		 640 }
641
642 return NULL;
643}
644
4562236b
HW		 645static int dm_resume(void *handle)
646{
647 struct amdgpu_device *adev = handle;
4562236b
HW		 648 struct drm_device *ddev = adev->ddev;
649 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 650 struct amdgpu_dm_connector *aconnector;
4562236b 651 struct drm_connector *connector;
4562236b 652 struct drm_crtc *crtc;
c2cea706 653 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 654 struct dm_crtc_state *dm_new_crtc_state;
655 struct drm_plane *plane;
656 struct drm_plane_state *new_plane_state;
657 struct dm_plane_state *dm_new_plane_state;
a80aa93d 658 int ret;
a3621485 659 int i;
4562236b 660
a80aa93d
ML		 661 /* power on hardware */
662 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
663
4562236b
HW		 664 /* program HPD filter */
665 dc_resume(dm->dc);
666
667 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
668 s3_handle_mst(ddev, false);
669
670 /*
671 * early enable HPD Rx IRQ, should be done before set mode as short
672 * pulse interrupts are used for MST
673 */
674 amdgpu_dm_irq_resume_early(adev);
675
4562236b 676 /* Do detection*/
a80aa93d 677 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 678 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 679
680 /*
681 * this is the case when traversing through already created
682 * MST connectors, should be skipped
683 */
684 if (aconnector->mst_port)
685 continue;
686
03ea364c 687 mutex_lock(&aconnector->hpd_lock);
8f38b66c 688 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 689
690 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
691 aconnector->fake_enable = false;
692
4562236b
HW		 693 aconnector->dc_sink = NULL;
694 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 695 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 696 }
697
a3621485 698 /* Force mode set in atomic comit */
a80aa93d 699 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 700 new_crtc_state->active_changed = true;
4f346e65 701
fcb4019e
LSL		 702 /*
703 * atomic_check is expected to create the dc states. We need to release
704 * them here, since they were duplicated as part of the suspend
705 * procedure.
706 */
a80aa93d 707 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 708 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
709 if (dm_new_crtc_state->stream) {
710 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
711 dc_stream_release(dm_new_crtc_state->stream);
712 dm_new_crtc_state->stream = NULL;
713 }
714 }
715
a80aa93d 716 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 717 dm_new_plane_state = to_dm_plane_state(new_plane_state);
718 if (dm_new_plane_state->dc_state) {
719 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
720 dc_plane_state_release(dm_new_plane_state->dc_state);
721 dm_new_plane_state->dc_state = NULL;
722 }
723 }
724
a80aa93d 725 ret = drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 726
a80aa93d 727 dm->cached_state = NULL;
0a214e2f 728
9faa4237 729 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 730
731 return ret;
732}
733
734static const struct amd_ip_funcs amdgpu_dm_funcs = {
735 .name = "dm",
736 .early_init = dm_early_init,
7abcf6b5 737 .late_init = dm_late_init,
4562236b
HW		 738 .sw_init = dm_sw_init,
739 .sw_fini = dm_sw_fini,
740 .hw_init = dm_hw_init,
741 .hw_fini = dm_hw_fini,
742 .suspend = dm_suspend,
743 .resume = dm_resume,
744 .is_idle = dm_is_idle,
745 .wait_for_idle = dm_wait_for_idle,
746 .check_soft_reset = dm_check_soft_reset,
747 .soft_reset = dm_soft_reset,
748 .set_clockgating_state = dm_set_clockgating_state,
749 .set_powergating_state = dm_set_powergating_state,
750};
751
752const struct amdgpu_ip_block_version dm_ip_block =
753{
754 .type = AMD_IP_BLOCK_TYPE_DCE,
755 .major = 1,
756 .minor = 0,
757 .rev = 0,
758 .funcs = &amdgpu_dm_funcs,
759};
760
ca3268c4 761
7578ecda 762static struct drm_atomic_state *
ca3268c4
HW		 763dm_atomic_state_alloc(struct drm_device *dev)
764{
765 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
766
1dc90497 767 if (!state)
ca3268c4 768 return NULL;
1dc90497
AG		 769
770 if (drm_atomic_state_init(dev, &state->base) < 0)
771 goto fail;
772
ca3268c4 773 return &state->base;
1dc90497
AG		 774
775fail:
776 kfree(state);
777 return NULL;
ca3268c4
HW		 778}
779
0a323b84
AG		 780static void
781dm_atomic_state_clear(struct drm_atomic_state *state)
782{
783 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
784
785 if (dm_state->context) {
608ac7bb 786 dc_release_state(dm_state->context);
0a323b84
AG		 787 dm_state->context = NULL;
788 }
789
790 drm_atomic_state_default_clear(state);
791}
792
793static void
794dm_atomic_state_alloc_free(struct drm_atomic_state *state)
795{
796 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
797 drm_atomic_state_default_release(state);
798 kfree(dm_state);
799}
800
b3663f70 801static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 802 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 803 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 804 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 805 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 806 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 807 .atomic_state_clear = dm_atomic_state_clear,
808 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 809};
810
811static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
812 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 813};
814
7578ecda 815static void
3ee6b26b 816amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 817{
818 struct drm_connector *connector = &aconnector->base;
819 struct drm_device *dev = connector->dev;
b73a22d3 820 struct dc_sink *sink;
4562236b
HW		 821
822 /* MST handled by drm_mst framework */
823 if (aconnector->mst_mgr.mst_state == true)
824 return;
825
826
827 sink = aconnector->dc_link->local_sink;
828
829 /* Edid mgmt connector gets first update only in mode_valid hook and then
830 * the connector sink is set to either fake or physical sink depends on link status.
831 * don't do it here if u are during boot
832 */
833 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
834 && aconnector->dc_em_sink) {
835
ab2541b6 836 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 837 * because on resume connecotr->sink is set ti NULL
838 */
839 mutex_lock(&dev->mode_config.mutex);
840
841 if (sink) {
922aa1e1 842 if (aconnector->dc_sink) {
98e6436d 843 amdgpu_dm_update_freesync_caps(connector, NULL);
922aa1e1
AG		 844 /* retain and release bellow are used for
845 * bump up refcount for sink because the link don't point
846 * to it anymore after disconnect so on next crtc to connector
847 * reshuffle by UMD we will get into unwanted dc_sink release
848 */
849 if (aconnector->dc_sink != aconnector->dc_em_sink)
850 dc_sink_release(aconnector->dc_sink);
851 }
4562236b 852 aconnector->dc_sink = sink;
98e6436d
AK		 853 amdgpu_dm_update_freesync_caps(connector,
854 aconnector->edid);
4562236b 855 } else {
98e6436d 856 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 857 if (!aconnector->dc_sink)
858 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 859 else if (aconnector->dc_sink != aconnector->dc_em_sink)
860 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 861 }
862
863 mutex_unlock(&dev->mode_config.mutex);
864 return;
865 }
866
867 /*
868 * TODO: temporary guard to look for proper fix
869 * if this sink is MST sink, we should not do anything
870 */
871 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
872 return;
873
874 if (aconnector->dc_sink == sink) {
875 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
876 * Do nothing!! */
f1ad2f5e 877 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 878 aconnector->connector_id);
879 return;
880 }
881
f1ad2f5e 882 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 883 aconnector->connector_id, aconnector->dc_sink, sink);
884
885 mutex_lock(&dev->mode_config.mutex);
886
887 /* 1. Update status of the drm connector
888 * 2. Send an event and let userspace tell us what to do */
889 if (sink) {
890 /* TODO: check if we still need the S3 mode update workaround.
891 * If yes, put it here. */
892 if (aconnector->dc_sink)
98e6436d 893 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 894
895 aconnector->dc_sink = sink;
900b3cb1 896 if (sink->dc_edid.length == 0) {
4562236b 897 aconnector->edid = NULL;
900b3cb1 898 } else {
4562236b
HW		 899 aconnector->edid =
900 (struct edid *) sink->dc_edid.raw_edid;
901
902
c555f023 903 drm_connector_update_edid_property(connector,
4562236b
HW		 904 aconnector->edid);
905 }
98e6436d 906 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 907
908 } else {
98e6436d 909 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 910 drm_connector_update_edid_property(connector, NULL);
4562236b
HW		 911 aconnector->num_modes = 0;
912 aconnector->dc_sink = NULL;
5326c452 913 aconnector->edid = NULL;
4562236b
HW		 914 }
915
916 mutex_unlock(&dev->mode_config.mutex);
917}
918
919static void handle_hpd_irq(void *param)
920{
c84dec2f 921 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 922 struct drm_connector *connector = &aconnector->base;
923 struct drm_device *dev = connector->dev;
924
925 /* In case of failure or MST no need to update connector status or notify the OS
926 * since (for MST case) MST does this in it's own context.
927 */
928 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 929
930 if (aconnector->fake_enable)
931 aconnector->fake_enable = false;
932
8f38b66c 933 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 934 amdgpu_dm_update_connector_after_detect(aconnector);
935
936
937 drm_modeset_lock_all(dev);
938 dm_restore_drm_connector_state(dev, connector);
939 drm_modeset_unlock_all(dev);
940
941 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
942 drm_kms_helper_hotplug_event(dev);
943 }
944 mutex_unlock(&aconnector->hpd_lock);
945
946}
947
c84dec2f 948static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 949{
950 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
951 uint8_t dret;
952 bool new_irq_handled = false;
953 int dpcd_addr;
954 int dpcd_bytes_to_read;
955
956 const int max_process_count = 30;
957 int process_count = 0;
958
959 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
960
961 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
962 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
963 /* DPCD 0x200 - 0x201 for downstream IRQ */
964 dpcd_addr = DP_SINK_COUNT;
965 } else {
966 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
967 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
968 dpcd_addr = DP_SINK_COUNT_ESI;
969 }
970
971 dret = drm_dp_dpcd_read(
972 &aconnector->dm_dp_aux.aux,
973 dpcd_addr,
974 esi,
975 dpcd_bytes_to_read);
976
977 while (dret == dpcd_bytes_to_read &&
978 process_count < max_process_count) {
979 uint8_t retry;
980 dret = 0;
981
982 process_count++;
983
f1ad2f5e 984 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 985 /* handle HPD short pulse irq */
986 if (aconnector->mst_mgr.mst_state)
987 drm_dp_mst_hpd_irq(
988 &aconnector->mst_mgr,
989 esi,
990 &new_irq_handled);
4562236b
HW		 991
992 if (new_irq_handled) {
993 /* ACK at DPCD to notify down stream */
994 const int ack_dpcd_bytes_to_write =
995 dpcd_bytes_to_read - 1;
996
997 for (retry = 0; retry < 3; retry++) {
998 uint8_t wret;
999
1000 wret = drm_dp_dpcd_write(
1001 &aconnector->dm_dp_aux.aux,
1002 dpcd_addr + 1,
1003 &esi[1],
1004 ack_dpcd_bytes_to_write);
1005 if (wret == ack_dpcd_bytes_to_write)
1006 break;
1007 }
1008
1009 /* check if there is new irq to be handle */
1010 dret = drm_dp_dpcd_read(
1011 &aconnector->dm_dp_aux.aux,
1012 dpcd_addr,
1013 esi,
1014 dpcd_bytes_to_read);
1015
1016 new_irq_handled = false;
d4a6e8a9 1017 } else {
4562236b 1018 break;
d4a6e8a9 1019 }
4562236b
HW		 1020 }
1021
1022 if (process_count == max_process_count)
f1ad2f5e 1023 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1024}
1025
1026static void handle_hpd_rx_irq(void *param)
1027{
c84dec2f 1028 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1029 struct drm_connector *connector = &aconnector->base;
1030 struct drm_device *dev = connector->dev;
53cbf65c 1031 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 1032 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1033
1034 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1035 * conflict, after implement i2c helper, this mutex should be
1036 * retired.
1037 */
53cbf65c 1038 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1039 mutex_lock(&aconnector->hpd_lock);
1040
4e18814e 1041 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1042 !is_mst_root_connector) {
1043 /* Downstream Port status changed. */
53cbf65c 1044 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1045
1046 if (aconnector->fake_enable)
1047 aconnector->fake_enable = false;
1048
4562236b
HW		 1049 amdgpu_dm_update_connector_after_detect(aconnector);
1050
1051
1052 drm_modeset_lock_all(dev);
1053 dm_restore_drm_connector_state(dev, connector);
1054 drm_modeset_unlock_all(dev);
1055
1056 drm_kms_helper_hotplug_event(dev);
1057 }
1058 }
1059 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1060 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1061 dm_handle_hpd_rx_irq(aconnector);
1062
53cbf65c 1063 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1064 mutex_unlock(&aconnector->hpd_lock);
1065}
1066
1067static void register_hpd_handlers(struct amdgpu_device *adev)
1068{
1069 struct drm_device *dev = adev->ddev;
1070 struct drm_connector *connector;
c84dec2f 1071 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1072 const struct dc_link *dc_link;
1073 struct dc_interrupt_params int_params = {0};
1074
1075 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1076 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1077
1078 list_for_each_entry(connector,
1079 &dev->mode_config.connector_list, head) {
1080
c84dec2f 1081 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1082 dc_link = aconnector->dc_link;
1083
1084 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1085 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1086 int_params.irq_source = dc_link->irq_source_hpd;
1087
1088 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1089 handle_hpd_irq,
1090 (void *) aconnector);
1091 }
1092
1093 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1094
1095 /* Also register for DP short pulse (hpd_rx). */
1096 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1097 int_params.irq_source = dc_link->irq_source_hpd_rx;
1098
1099 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1100 handle_hpd_rx_irq,
1101 (void *) aconnector);
1102 }
1103 }
1104}
1105
1106/* Register IRQ sources and initialize IRQ callbacks */
1107static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1108{
1109 struct dc *dc = adev->dm.dc;
1110 struct common_irq_params *c_irq_params;
1111 struct dc_interrupt_params int_params = {0};
1112 int r;
1113 int i;
2c8ad2d5
AD		 1114 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1115
ff5ef992 1116 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1117 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1118 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1119 adev->asic_type == CHIP_RAVEN)
3760f76c 1120 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1121
1122 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1123 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1124
1125 /* Actions of amdgpu_irq_add_id():
1126 * 1. Register a set() function with base driver.
1127 * Base driver will call set() function to enable/disable an
1128 * interrupt in DC hardware.
1129 * 2. Register amdgpu_dm_irq_handler().
1130 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1131 * coming from DC hardware.
1132 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1133 * for acknowledging and handling. */
1134
b57de80a 1135 /* Use VBLANK interrupt */
e9029155 1136 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1137 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1138 if (r) {
1139 DRM_ERROR("Failed to add crtc irq id!\n");
1140 return r;
1141 }
1142
1143 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1144 int_params.irq_source =
3d761e79 1145 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1146
b57de80a 1147 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1148
1149 c_irq_params->adev = adev;
1150 c_irq_params->irq_src = int_params.irq_source;
1151
1152 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1153 dm_crtc_high_irq, c_irq_params);
1154 }
1155
3d761e79 1156 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1157 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1158 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1159 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1160 if (r) {
1161 DRM_ERROR("Failed to add page flip irq id!\n");
1162 return r;
1163 }
1164
1165 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1166 int_params.irq_source =
1167 dc_interrupt_to_irq_source(dc, i, 0);
1168
1169 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1170
1171 c_irq_params->adev = adev;
1172 c_irq_params->irq_src = int_params.irq_source;
1173
1174 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1175 dm_pflip_high_irq, c_irq_params);
1176
1177 }
1178
1179 /* HPD */
2c8ad2d5
AD		 1180 r = amdgpu_irq_add_id(adev, client_id,
1181 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1182 if (r) {
1183 DRM_ERROR("Failed to add hpd irq id!\n");
1184 return r;
1185 }
1186
1187 register_hpd_handlers(adev);
1188
1189 return 0;
1190}
1191
dc37a9a0 1192#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 1193/* Register IRQ sources and initialize IRQ callbacks */
1194static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1195{
1196 struct dc *dc = adev->dm.dc;
1197 struct common_irq_params *c_irq_params;
1198 struct dc_interrupt_params int_params = {0};
1199 int r;
1200 int i;
1201
1202 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1203 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1204
1205 /* Actions of amdgpu_irq_add_id():
1206 * 1. Register a set() function with base driver.
1207 * Base driver will call set() function to enable/disable an
1208 * interrupt in DC hardware.
1209 * 2. Register amdgpu_dm_irq_handler().
1210 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1211 * coming from DC hardware.
1212 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1213 * for acknowledging and handling.
1214 * */
1215
1216 /* Use VSTARTUP interrupt */
1217 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1218 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1219 i++) {
3760f76c 1220 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1221
1222 if (r) {
1223 DRM_ERROR("Failed to add crtc irq id!\n");
1224 return r;
1225 }
1226
1227 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1228 int_params.irq_source =
1229 dc_interrupt_to_irq_source(dc, i, 0);
1230
1231 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1232
1233 c_irq_params->adev = adev;
1234 c_irq_params->irq_src = int_params.irq_source;
1235
1236 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1237 dm_crtc_high_irq, c_irq_params);
1238 }
1239
1240 /* Use GRPH_PFLIP interrupt */
1241 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1242 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1243 i++) {
3760f76c 1244 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1245 if (r) {
1246 DRM_ERROR("Failed to add page flip irq id!\n");
1247 return r;
1248 }
1249
1250 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1251 int_params.irq_source =
1252 dc_interrupt_to_irq_source(dc, i, 0);
1253
1254 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1255
1256 c_irq_params->adev = adev;
1257 c_irq_params->irq_src = int_params.irq_source;
1258
1259 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1260 dm_pflip_high_irq, c_irq_params);
1261
1262 }
1263
1264 /* HPD */
3760f76c 1265 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1266 &adev->hpd_irq);
1267 if (r) {
1268 DRM_ERROR("Failed to add hpd irq id!\n");
1269 return r;
1270 }
1271
1272 register_hpd_handlers(adev);
1273
1274 return 0;
1275}
1276#endif
1277
4562236b
HW		 1278static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1279{
1280 int r;
1281
1282 adev->mode_info.mode_config_initialized = true;
1283
4562236b 1284 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1285 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1286
1287 adev->ddev->mode_config.max_width = 16384;
1288 adev->ddev->mode_config.max_height = 16384;
1289
1290 adev->ddev->mode_config.preferred_depth = 24;
1291 adev->ddev->mode_config.prefer_shadow = 1;
1292 /* indicate support of immediate flip */
1293 adev->ddev->mode_config.async_page_flip = true;
1294
770d13b1 1295 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1296
3dc9b1ce 1297 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1298 if (r)
1299 return r;
1300
1301 return 0;
1302}
1303
1304#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1305 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1306
1307static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1308{
1309 struct amdgpu_display_manager *dm = bl_get_data(bd);
1310
1311 if (dc_link_set_backlight_level(dm->backlight_link,
1312 bd->props.brightness, 0, 0))
1313 return 0;
1314 else
1315 return 1;
1316}
1317
1318static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1319{
620a0d27
DF		 1320 struct amdgpu_display_manager *dm = bl_get_data(bd);
1321 int ret = dc_link_get_backlight_level(dm->backlight_link);
1322
1323 if (ret == DC_ERROR_UNEXPECTED)
1324 return bd->props.brightness;
1325 return ret;
4562236b
HW		 1326}
1327
1328static const struct backlight_ops amdgpu_dm_backlight_ops = {
1329 .get_brightness = amdgpu_dm_backlight_get_brightness,
1330 .update_status = amdgpu_dm_backlight_update_status,
1331};
1332
7578ecda
AD		 1333static void
1334amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1335{
1336 char bl_name[16];
1337 struct backlight_properties props = { 0 };
1338
1339 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 1340 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 1341 props.type = BACKLIGHT_RAW;
1342
1343 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1344 dm->adev->ddev->primary->index);
1345
1346 dm->backlight_dev = backlight_device_register(bl_name,
1347 dm->adev->ddev->dev,
1348 dm,
1349 &amdgpu_dm_backlight_ops,
1350 &props);
1351
74baea42 1352 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1353 DRM_ERROR("DM: Backlight registration failed!\n");
1354 else
f1ad2f5e 1355 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1356}
1357
1358#endif
1359
df534fff
S		 1360static int initialize_plane(struct amdgpu_display_manager *dm,
1361 struct amdgpu_mode_info *mode_info,
1362 int plane_id)
1363{
1364 struct amdgpu_plane *plane;
1365 unsigned long possible_crtcs;
1366 int ret = 0;
1367
1368 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1369 mode_info->planes[plane_id] = plane;
1370
1371 if (!plane) {
1372 DRM_ERROR("KMS: Failed to allocate plane\n");
1373 return -ENOMEM;
1374 }
1375 plane->base.type = mode_info->plane_type[plane_id];
1376
1377 /*
1378 * HACK: IGT tests expect that each plane can only have one
1379 * one possible CRTC. For now, set one CRTC for each
1380 * plane that is not an underlay, but still allow multiple
1381 * CRTCs for underlay planes.
1382 */
1383 possible_crtcs = 1 << plane_id;
1384 if (plane_id >= dm->dc->caps.max_streams)
1385 possible_crtcs = 0xff;
1386
1387 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1388
1389 if (ret) {
1390 DRM_ERROR("KMS: Failed to initialize plane\n");
1391 return ret;
1392 }
1393
1394 return ret;
1395}
1396
89fc8d4e
HW		 1397
1398static void register_backlight_device(struct amdgpu_display_manager *dm,
1399 struct dc_link *link)
1400{
1401#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1402 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1403
1404 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1405 link->type != dc_connection_none) {
1406 /* Event if registration failed, we should continue with
1407 * DM initialization because not having a backlight control
1408 * is better then a black screen.
1409 */
1410 amdgpu_dm_register_backlight_device(dm);
1411
1412 if (dm->backlight_dev)
1413 dm->backlight_link = link;
1414 }
1415#endif
1416}
1417
1418
4562236b
HW		 1419/* In this architecture, the association
1420 * connector -> encoder -> crtc
1421 * id not really requried. The crtc and connector will hold the
1422 * display_index as an abstraction to use with DAL component
1423 *
1424 * Returns 0 on success
1425 */
7578ecda 1426static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1427{
1428 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 1429 int32_t i;
c84dec2f 1430 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1431 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1432 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1433 uint32_t link_cnt;
df534fff 1434 int32_t total_overlay_planes, total_primary_planes;
4562236b
HW		 1435
1436 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1437 if (amdgpu_dm_mode_config_init(dm->adev)) {
1438 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1439 return -1;
4562236b
HW		 1440 }
1441
df534fff
S		 1442 /* Identify the number of planes to be initialized */
1443 total_overlay_planes = dm->dc->caps.max_slave_planes;
1444 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
efa6a8b7 1445
df534fff
S		 1446 /* First initialize overlay planes, index starting after primary planes */
1447 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1448 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1449 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 1450 goto fail;
d4e13b0d 1451 }
df534fff 1452 }
92f3ac40 1453
df534fff
S		 1454 /* Initialize primary planes */
1455 for (i = (total_primary_planes - 1); i >= 0; i--) {
1456 if (initialize_plane(dm, mode_info, i)) {
1457 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 1458 goto fail;
d4e13b0d
AD		 1459 }
1460 }
4562236b 1461
d4e13b0d
AD		 1462 for (i = 0; i < dm->dc->caps.max_streams; i++)
1463 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1464 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1465 goto fail;
4562236b 1466 }
4562236b 1467
ab2541b6 1468 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1469
1470 /* loops over all connectors on the board */
1471 for (i = 0; i < link_cnt; i++) {
89fc8d4e 1472 struct dc_link *link = NULL;
4562236b
HW		 1473
1474 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1475 DRM_ERROR(
1476 "KMS: Cannot support more than %d display indexes\n",
1477 AMDGPU_DM_MAX_DISPLAY_INDEX);
1478 continue;
1479 }
1480
1481 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1482 if (!aconnector)
cd8a2ae8 1483 goto fail;
4562236b
HW		 1484
1485 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1486 if (!aencoder)
cd8a2ae8 1487 goto fail;
4562236b
HW		 1488
1489 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1490 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1491 goto fail;
4562236b
HW		 1492 }
1493
1494 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1495 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1496 goto fail;
4562236b
HW		 1497 }
1498
89fc8d4e
HW		 1499 link = dc_get_link_at_index(dm->dc, i);
1500
1501 if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 1502 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 1503 register_backlight_device(dm, link);
1504 }
1505
1506
4562236b
HW		 1507 }
1508
1509 /* Software is initialized. Now we can register interrupt handlers. */
1510 switch (adev->asic_type) {
1511 case CHIP_BONAIRE:
1512 case CHIP_HAWAII:
cd4b356f
AD		 1513 case CHIP_KAVERI:
1514 case CHIP_KABINI:
1515 case CHIP_MULLINS:
4562236b
HW		 1516 case CHIP_TONGA:
1517 case CHIP_FIJI:
1518 case CHIP_CARRIZO:
1519 case CHIP_STONEY:
1520 case CHIP_POLARIS11:
1521 case CHIP_POLARIS10:
b264d345 1522 case CHIP_POLARIS12:
7737de91 1523 case CHIP_VEGAM:
2c8ad2d5 1524 case CHIP_VEGA10:
2325ff30 1525 case CHIP_VEGA12:
1fe6bf2f 1526 case CHIP_VEGA20:
4562236b
HW		 1527 if (dce110_register_irq_handlers(dm->adev)) {
1528 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1529 goto fail;
4562236b
HW		 1530 }
1531 break;
dc37a9a0 1532#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 1533 case CHIP_RAVEN:
1534 if (dcn10_register_irq_handlers(dm->adev)) {
1535 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1536 goto fail;
ff5ef992
AD		 1537 }
1538 break;
1539#endif
4562236b 1540 default:
e63f8673 1541 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 1542 goto fail;
4562236b
HW		 1543 }
1544
1bc460a4
HW		 1545 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1546 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1547
4562236b 1548 return 0;
cd8a2ae8 1549fail:
4562236b 1550 kfree(aencoder);
4562236b 1551 kfree(aconnector);
3be5262e 1552 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1553 kfree(mode_info->planes[i]);
4562236b
HW		 1554 return -1;
1555}
1556
7578ecda 1557static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1558{
1559 drm_mode_config_cleanup(dm->ddev);
1560 return;
1561}
1562
1563/******************************************************************************
1564 * amdgpu_display_funcs functions
1565 *****************************************************************************/
1566
1567/**
1568 * dm_bandwidth_update - program display watermarks
1569 *
1570 * @adev: amdgpu_device pointer
1571 *
1572 * Calculate and program the display watermarks and line buffer allocation.
1573 */
1574static void dm_bandwidth_update(struct amdgpu_device *adev)
1575{
49c07a99 1576 /* TODO: implement later */
4562236b
HW		 1577}
1578
4562236b
HW		 1579static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1580 struct drm_file *filp)
1581{
98e6436d
AK		 1582 struct drm_atomic_state *state;
1583 struct drm_modeset_acquire_ctx ctx;
1584 struct drm_crtc *crtc;
1585 struct drm_connector *connector;
1586 struct drm_connector_state *old_con_state, *new_con_state;
1587 int ret = 0;
4562236b 1588 uint8_t i;
98e6436d 1589 bool enable = false;
4562236b 1590
98e6436d
AK		 1591 drm_modeset_acquire_init(&ctx, 0);
1592
1593 state = drm_atomic_state_alloc(dev);
1594 if (!state) {
1595 ret = -ENOMEM;
1596 goto out;
1597 }
1598 state->acquire_ctx = &ctx;
1599
1600retry:
1601 drm_for_each_crtc(crtc, dev) {
1602 ret = drm_atomic_add_affected_connectors(state, crtc);
1603 if (ret)
1604 goto fail;
1605
1606 /* TODO rework amdgpu_dm_commit_planes so we don't need this */
1607 ret = drm_atomic_add_affected_planes(state, crtc);
1608 if (ret)
1609 goto fail;
1610 }
4562236b 1611
98e6436d
AK		 1612 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
1613 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
1614 struct drm_crtc_state *new_crtc_state;
1615 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
1616 struct dm_crtc_state *dm_new_crtc_state;
4562236b 1617
98e6436d
AK		 1618 if (!acrtc) {
1619 ASSERT(0);
1620 continue;
1621 }
4562236b 1622
98e6436d
AK		 1623 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
1624 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4562236b 1625
98e6436d 1626 dm_new_crtc_state->freesync_enabled = enable;
4562236b
HW		 1627 }
1628
98e6436d
AK		 1629 ret = drm_atomic_commit(state);
1630
1631fail:
1632 if (ret == -EDEADLK) {
1633 drm_atomic_state_clear(state);
1634 drm_modeset_backoff(&ctx);
1635 goto retry;
1636 }
1637
1638 drm_atomic_state_put(state);
1639
1640out:
1641 drm_modeset_drop_locks(&ctx);
1642 drm_modeset_acquire_fini(&ctx);
1643 return ret;
4562236b
HW		 1644}
1645
39cc5be2 1646static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1647 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1648 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 1649 .backlight_set_level = NULL, /* never called for DC */
1650 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 1651 .hpd_sense = NULL,/* called unconditionally */
1652 .hpd_set_polarity = NULL, /* called unconditionally */
1653 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1654 .page_flip_get_scanoutpos =
1655 dm_crtc_get_scanoutpos,/* called unconditionally */
1656 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1657 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1658 .notify_freesync = amdgpu_notify_freesync,
1659
1660};
1661
1662#if defined(CONFIG_DEBUG_KERNEL_DC)
1663
3ee6b26b
AD		 1664static ssize_t s3_debug_store(struct device *device,
1665 struct device_attribute *attr,
1666 const char *buf,
1667 size_t count)
4562236b
HW		 1668{
1669 int ret;
1670 int s3_state;
1671 struct pci_dev *pdev = to_pci_dev(device);
1672 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1673 struct amdgpu_device *adev = drm_dev->dev_private;
1674
1675 ret = kstrtoint(buf, 0, &s3_state);
1676
1677 if (ret == 0) {
1678 if (s3_state) {
1679 dm_resume(adev);
4562236b
HW		 1680 drm_kms_helper_hotplug_event(adev->ddev);
1681 } else
1682 dm_suspend(adev);
1683 }
1684
1685 return ret == 0 ? count : 0;
1686}
1687
1688DEVICE_ATTR_WO(s3_debug);
1689
1690#endif
1691
1692static int dm_early_init(void *handle)
1693{
1694 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1695
4562236b
HW		 1696 switch (adev->asic_type) {
1697 case CHIP_BONAIRE:
1698 case CHIP_HAWAII:
1699 adev->mode_info.num_crtc = 6;
1700 adev->mode_info.num_hpd = 6;
1701 adev->mode_info.num_dig = 6;
3be5262e 1702 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1703 break;
cd4b356f
AD		 1704 case CHIP_KAVERI:
1705 adev->mode_info.num_crtc = 4;
1706 adev->mode_info.num_hpd = 6;
1707 adev->mode_info.num_dig = 7;
1708 adev->mode_info.plane_type = dm_plane_type_default;
1709 break;
1710 case CHIP_KABINI:
1711 case CHIP_MULLINS:
1712 adev->mode_info.num_crtc = 2;
1713 adev->mode_info.num_hpd = 6;
1714 adev->mode_info.num_dig = 6;
1715 adev->mode_info.plane_type = dm_plane_type_default;
1716 break;
4562236b
HW		 1717 case CHIP_FIJI:
1718 case CHIP_TONGA:
1719 adev->mode_info.num_crtc = 6;
1720 adev->mode_info.num_hpd = 6;
1721 adev->mode_info.num_dig = 7;
3be5262e 1722 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1723 break;
1724 case CHIP_CARRIZO:
1725 adev->mode_info.num_crtc = 3;
1726 adev->mode_info.num_hpd = 6;
1727 adev->mode_info.num_dig = 9;
3be5262e 1728 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1729 break;
1730 case CHIP_STONEY:
1731 adev->mode_info.num_crtc = 2;
1732 adev->mode_info.num_hpd = 6;
1733 adev->mode_info.num_dig = 9;
3be5262e 1734 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1735 break;
1736 case CHIP_POLARIS11:
b264d345 1737 case CHIP_POLARIS12:
4562236b
HW		 1738 adev->mode_info.num_crtc = 5;
1739 adev->mode_info.num_hpd = 5;
1740 adev->mode_info.num_dig = 5;
3be5262e 1741 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1742 break;
1743 case CHIP_POLARIS10:
7737de91 1744 case CHIP_VEGAM:
4562236b
HW		 1745 adev->mode_info.num_crtc = 6;
1746 adev->mode_info.num_hpd = 6;
1747 adev->mode_info.num_dig = 6;
3be5262e 1748 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1749 break;
2c8ad2d5 1750 case CHIP_VEGA10:
2325ff30 1751 case CHIP_VEGA12:
1fe6bf2f 1752 case CHIP_VEGA20:
2c8ad2d5
AD		 1753 adev->mode_info.num_crtc = 6;
1754 adev->mode_info.num_hpd = 6;
1755 adev->mode_info.num_dig = 6;
3be5262e 1756 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1757 break;
dc37a9a0 1758#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 1759 case CHIP_RAVEN:
1760 adev->mode_info.num_crtc = 4;
1761 adev->mode_info.num_hpd = 4;
1762 adev->mode_info.num_dig = 4;
3be5262e 1763 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1764 break;
1765#endif
4562236b 1766 default:
e63f8673 1767 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 1768 return -EINVAL;
1769 }
1770
c8dd5715
MD		 1771 amdgpu_dm_set_irq_funcs(adev);
1772
39cc5be2
AD		 1773 if (adev->mode_info.funcs == NULL)
1774 adev->mode_info.funcs = &dm_display_funcs;
1775
4562236b
HW		 1776 /* Note: Do NOT change adev->audio_endpt_rreg and
1777 * adev->audio_endpt_wreg because they are initialised in
1778 * amdgpu_device_init() */
1779#if defined(CONFIG_DEBUG_KERNEL_DC)
1780 device_create_file(
1781 adev->ddev->dev,
1782 &dev_attr_s3_debug);
1783#endif
1784
1785 return 0;
1786}
1787
9b690ef3 1788static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1789 struct dc_stream_state *new_stream,
1790 struct dc_stream_state *old_stream)
9b690ef3 1791{
e7b07cee
HW		 1792 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1793 return false;
1794
1795 if (!crtc_state->enable)
1796 return false;
1797
1798 return crtc_state->active;
1799}
1800
1801static bool modereset_required(struct drm_crtc_state *crtc_state)
1802{
1803 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1804 return false;
1805
1806 return !crtc_state->enable || !crtc_state->active;
1807}
1808
7578ecda 1809static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1810{
1811 drm_encoder_cleanup(encoder);
1812 kfree(encoder);
1813}
1814
1815static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1816 .destroy = amdgpu_dm_encoder_destroy,
1817};
1818
3ee6b26b
AD		 1819static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1820 struct dc_plane_state *plane_state)
e7b07cee 1821{
3be5262e
HW		 1822 plane_state->src_rect.x = state->src_x >> 16;
1823 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1824 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1825 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1826
3be5262e 1827 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1828 return false;
1829
3be5262e
HW		 1830 plane_state->src_rect.height = state->src_h >> 16;
1831 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1832 return false;
1833
3be5262e
HW		 1834 plane_state->dst_rect.x = state->crtc_x;
1835 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1836
1837 if (state->crtc_w == 0)
1838 return false;
1839
3be5262e 1840 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1841
1842 if (state->crtc_h == 0)
1843 return false;
1844
3be5262e 1845 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1846
3be5262e 1847 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1848
1849 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1850 case DRM_MODE_ROTATE_0:
3be5262e 1851 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1852 break;
1853 case DRM_MODE_ROTATE_90:
3be5262e 1854 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1855 break;
1856 case DRM_MODE_ROTATE_180:
3be5262e 1857 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1858 break;
1859 case DRM_MODE_ROTATE_270:
3be5262e 1860 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1861 break;
1862 default:
3be5262e 1863 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1864 break;
1865 }
1866
4562236b
HW		 1867 return true;
1868}
3ee6b26b 1869static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 1870 uint64_t *tiling_flags)
e7b07cee 1871{
e68d14dd 1872 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 1873 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1874
e7b07cee 1875 if (unlikely(r)) {
9bbc3031
JZ		 1876 // Don't show error msg. when return -ERESTARTSYS
1877 if (r != -ERESTARTSYS)
1878 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1879 return r;
1880 }
1881
e7b07cee
HW		 1882 if (tiling_flags)
1883 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1884
1885 amdgpu_bo_unreserve(rbo);
1886
1887 return r;
1888}
1889
3ee6b26b
AD		 1890static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1891 struct dc_plane_state *plane_state,
9817d5f5 1892 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 1893{
1894 uint64_t tiling_flags;
e7b07cee
HW		 1895 unsigned int awidth;
1896 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1897 int ret = 0;
1898 struct drm_format_name_buf format_name;
1899
1900 ret = get_fb_info(
1901 amdgpu_fb,
9817d5f5 1902 &tiling_flags);
e7b07cee
HW		 1903
1904 if (ret)
1905 return ret;
1906
1907 switch (fb->format->format) {
1908 case DRM_FORMAT_C8:
3be5262e 1909 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1910 break;
1911 case DRM_FORMAT_RGB565:
3be5262e 1912 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1913 break;
1914 case DRM_FORMAT_XRGB8888:
1915 case DRM_FORMAT_ARGB8888:
3be5262e 1916 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1917 break;
1918 case DRM_FORMAT_XRGB2101010:
1919 case DRM_FORMAT_ARGB2101010:
3be5262e 1920 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1921 break;
1922 case DRM_FORMAT_XBGR2101010:
1923 case DRM_FORMAT_ABGR2101010:
3be5262e 1924 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee 1925 break;
bcd47f60
MR		 1926 case DRM_FORMAT_XBGR8888:
1927 case DRM_FORMAT_ABGR8888:
1928 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
1929 break;
e7b07cee 1930 case DRM_FORMAT_NV21:
3be5262e 1931 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1932 break;
1933 case DRM_FORMAT_NV12:
3be5262e 1934 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1935 break;
1936 default:
1937 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1938 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1939 return -EINVAL;
1940 }
1941
3be5262e
HW		 1942 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1943 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 1944 plane_state->plane_size.grph.surface_size.x = 0;
1945 plane_state->plane_size.grph.surface_size.y = 0;
1946 plane_state->plane_size.grph.surface_size.width = fb->width;
1947 plane_state->plane_size.grph.surface_size.height = fb->height;
1948 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1949 fb->pitches[0] / fb->format->cpp[0];
1950 /* TODO: unhardcode */
3be5262e 1951 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1952
1953 } else {
1954 awidth = ALIGN(fb->width, 64);
3be5262e 1955 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 1956 plane_state->plane_size.video.luma_size.x = 0;
1957 plane_state->plane_size.video.luma_size.y = 0;
1958 plane_state->plane_size.video.luma_size.width = awidth;
1959 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1960 /* TODO: unhardcode */
3be5262e 1961 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1962
3be5262e
HW		 1963 plane_state->plane_size.video.chroma_size.x = 0;
1964 plane_state->plane_size.video.chroma_size.y = 0;
1965 plane_state->plane_size.video.chroma_size.width = awidth;
1966 plane_state->plane_size.video.chroma_size.height = fb->height;
1967 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1968
1969 /* TODO: unhardcode */
3be5262e 1970 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1971 }
1972
3be5262e 1973 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1974
b830ebc9
HW		 1975 /* Fill GFX8 params */
1976 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1977 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1978
1979 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1980 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1981 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1982 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1983 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1984
1985 /* XXX fix me for VI */
3be5262e
HW		 1986 plane_state->tiling_info.gfx8.num_banks = num_banks;
1987 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1988 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1989 plane_state->tiling_info.gfx8.tile_split = tile_split;
1990 plane_state->tiling_info.gfx8.bank_width = bankw;
1991 plane_state->tiling_info.gfx8.bank_height = bankh;
1992 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1993 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1994 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1995 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1996 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1997 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1998 }
1999
3be5262e 2000 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 2001 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2002
2003 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 2004 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 2005 adev->asic_type == CHIP_VEGA20 ||
e7b07cee
HW		 2006 adev->asic_type == CHIP_RAVEN) {
2007 /* Fill GFX9 params */
3be5262e 2008 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 2009 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 2010 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 2011 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 2012 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 2013 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 2014 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 2015 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 2016 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 2017 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 2018 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 2019 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 2020 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 2021 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 2022 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 2023 }
2024
3be5262e
HW		 2025 plane_state->visible = true;
2026 plane_state->scaling_quality.h_taps_c = 0;
2027 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 2028
3be5262e
HW		 2029 /* is this needed? is plane_state zeroed at allocation? */
2030 plane_state->scaling_quality.h_taps = 0;
2031 plane_state->scaling_quality.v_taps = 0;
2032 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 2033
2034 return ret;
2035
2036}
2037
3ee6b26b
AD		 2038static int fill_plane_attributes(struct amdgpu_device *adev,
2039 struct dc_plane_state *dc_plane_state,
2040 struct drm_plane_state *plane_state,
9817d5f5 2041 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2042{
2043 const struct amdgpu_framebuffer *amdgpu_fb =
2044 to_amdgpu_framebuffer(plane_state->fb);
2045 const struct drm_crtc *crtc = plane_state->crtc;
e7b07cee
HW		 2046 int ret = 0;
2047
3be5262e 2048 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 2049 return -EINVAL;
2050
2051 ret = fill_plane_attributes_from_fb(
2052 crtc->dev->dev_private,
3be5262e 2053 dc_plane_state,
9817d5f5 2054 amdgpu_fb);
e7b07cee
HW		 2055
2056 if (ret)
2057 return ret;
2058
e277adc5
LSL		 2059 /*
2060 * Always set input transfer function, since plane state is refreshed
2061 * every time.
2062 */
2063 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2064 if (ret) {
2065 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2066 dc_plane_state->in_transfer_func = NULL;
2067 }
e7b07cee
HW		 2068
2069 return ret;
2070}
2071
2072/*****************************************************************************/
2073
3ee6b26b
AD		 2074static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2075 const struct dm_connector_state *dm_state,
2076 struct dc_stream_state *stream)
e7b07cee
HW		 2077{
2078 enum amdgpu_rmx_type rmx_type;
2079
2080 struct rect src = { 0 }; /* viewport in composition space*/
2081 struct rect dst = { 0 }; /* stream addressable area */
2082
2083 /* no mode. nothing to be done */
2084 if (!mode)
2085 return;
2086
2087 /* Full screen scaling by default */
2088 src.width = mode->hdisplay;
2089 src.height = mode->vdisplay;
2090 dst.width = stream->timing.h_addressable;
2091 dst.height = stream->timing.v_addressable;
2092
f4791779
HW		 2093 if (dm_state) {
2094 rmx_type = dm_state->scaling;
2095 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2096 if (src.width * dst.height <
2097 src.height * dst.width) {
2098 /* height needs less upscaling/more downscaling */
2099 dst.width = src.width *
2100 dst.height / src.height;
2101 } else {
2102 /* width needs less upscaling/more downscaling */
2103 dst.height = src.height *
2104 dst.width / src.width;
2105 }
2106 } else if (rmx_type == RMX_CENTER) {
2107 dst = src;
e7b07cee 2108 }
e7b07cee 2109
f4791779
HW		 2110 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2111 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2112
f4791779
HW		 2113 if (dm_state->underscan_enable) {
2114 dst.x += dm_state->underscan_hborder / 2;
2115 dst.y += dm_state->underscan_vborder / 2;
2116 dst.width -= dm_state->underscan_hborder;
2117 dst.height -= dm_state->underscan_vborder;
2118 }
e7b07cee
HW		 2119 }
2120
2121 stream->src = src;
2122 stream->dst = dst;
2123
f1ad2f5e 2124 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2125 dst.x, dst.y, dst.width, dst.height);
2126
2127}
2128
3ee6b26b
AD		 2129static enum dc_color_depth
2130convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2131{
2132 uint32_t bpc = connector->display_info.bpc;
2133
e7b07cee
HW		 2134 switch (bpc) {
2135 case 0:
2136 /* Temporary Work around, DRM don't parse color depth for
2137 * EDID revision before 1.4
2138 * TODO: Fix edid parsing
2139 */
2140 return COLOR_DEPTH_888;
2141 case 6:
2142 return COLOR_DEPTH_666;
2143 case 8:
2144 return COLOR_DEPTH_888;
2145 case 10:
2146 return COLOR_DEPTH_101010;
2147 case 12:
2148 return COLOR_DEPTH_121212;
2149 case 14:
2150 return COLOR_DEPTH_141414;
2151 case 16:
2152 return COLOR_DEPTH_161616;
2153 default:
2154 return COLOR_DEPTH_UNDEFINED;
2155 }
2156}
2157
3ee6b26b
AD		 2158static enum dc_aspect_ratio
2159get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 2160{
e11d4147
LSL		 2161 /* 1-1 mapping, since both enums follow the HDMI spec. */
2162 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 2163}
2164
3ee6b26b
AD		 2165static enum dc_color_space
2166get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2167{
2168 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2169
2170 switch (dc_crtc_timing->pixel_encoding) {
2171 case PIXEL_ENCODING_YCBCR422:
2172 case PIXEL_ENCODING_YCBCR444:
2173 case PIXEL_ENCODING_YCBCR420:
2174 {
2175 /*
2176 * 27030khz is the separation point between HDTV and SDTV
2177 * according to HDMI spec, we use YCbCr709 and YCbCr601
2178 * respectively
2179 */
2180 if (dc_crtc_timing->pix_clk_khz > 27030) {
2181 if (dc_crtc_timing->flags.Y_ONLY)
2182 color_space =
2183 COLOR_SPACE_YCBCR709_LIMITED;
2184 else
2185 color_space = COLOR_SPACE_YCBCR709;
2186 } else {
2187 if (dc_crtc_timing->flags.Y_ONLY)
2188 color_space =
2189 COLOR_SPACE_YCBCR601_LIMITED;
2190 else
2191 color_space = COLOR_SPACE_YCBCR601;
2192 }
2193
2194 }
2195 break;
2196 case PIXEL_ENCODING_RGB:
2197 color_space = COLOR_SPACE_SRGB;
2198 break;
2199
2200 default:
2201 WARN_ON(1);
2202 break;
2203 }
2204
2205 return color_space;
2206}
2207
400443e8
ML		 2208static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2209{
2210 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2211 return;
2212
2213 timing_out->display_color_depth--;
2214}
2215
2216static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2217 const struct drm_display_info *info)
2218{
2219 int normalized_clk;
2220 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2221 return;
2222 do {
2223 normalized_clk = timing_out->pix_clk_khz;
2224 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2225 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2226 normalized_clk /= 2;
2227 /* Adjusting pix clock following on HDMI spec based on colour depth */
2228 switch (timing_out->display_color_depth) {
2229 case COLOR_DEPTH_101010:
2230 normalized_clk = (normalized_clk * 30) / 24;
2231 break;
2232 case COLOR_DEPTH_121212:
2233 normalized_clk = (normalized_clk * 36) / 24;
2234 break;
2235 case COLOR_DEPTH_161616:
2236 normalized_clk = (normalized_clk * 48) / 24;
2237 break;
2238 default:
2239 return;
2240 }
2241 if (normalized_clk <= info->max_tmds_clock)
2242 return;
2243 reduce_mode_colour_depth(timing_out);
2244
2245 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2246
2247}
e7b07cee
HW		 2248/*****************************************************************************/
2249
3ee6b26b
AD		 2250static void
2251fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2252 const struct drm_display_mode *mode_in,
2253 const struct drm_connector *connector)
e7b07cee
HW		 2254{
2255 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 2256 const struct drm_display_info *info = &connector->display_info;
b830ebc9 2257
e7b07cee
HW		 2258 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2259
2260 timing_out->h_border_left = 0;
2261 timing_out->h_border_right = 0;
2262 timing_out->v_border_top = 0;
2263 timing_out->v_border_bottom = 0;
2264 /* TODO: un-hardcode */
fe61a2f1
ML		 2265 if (drm_mode_is_420_only(info, mode_in)
2266 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2267 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2268 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
e7b07cee
HW		 2269 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2270 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2271 else
2272 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2273
2274 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2275 timing_out->display_color_depth = convert_color_depth_from_display_info(
2276 connector);
2277 timing_out->scan_type = SCANNING_TYPE_NODATA;
2278 timing_out->hdmi_vic = 0;
2279 timing_out->vic = drm_match_cea_mode(mode_in);
2280
2281 timing_out->h_addressable = mode_in->crtc_hdisplay;
2282 timing_out->h_total = mode_in->crtc_htotal;
2283 timing_out->h_sync_width =
2284 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2285 timing_out->h_front_porch =
2286 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2287 timing_out->v_total = mode_in->crtc_vtotal;
2288 timing_out->v_addressable = mode_in->crtc_vdisplay;
2289 timing_out->v_front_porch =
2290 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2291 timing_out->v_sync_width =
2292 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2293 timing_out->pix_clk_khz = mode_in->crtc_clock;
2294 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2295 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2296 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2297 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2298 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2299
2300 stream->output_color_space = get_output_color_space(timing_out);
2301
e43a432c
AK		 2302 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2303 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
400443e8
ML		 2304 if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2305 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 2306}
2307
3ee6b26b
AD		 2308static void fill_audio_info(struct audio_info *audio_info,
2309 const struct drm_connector *drm_connector,
2310 const struct dc_sink *dc_sink)
e7b07cee
HW		 2311{
2312 int i = 0;
2313 int cea_revision = 0;
2314 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2315
2316 audio_info->manufacture_id = edid_caps->manufacturer_id;
2317 audio_info->product_id = edid_caps->product_id;
2318
2319 cea_revision = drm_connector->display_info.cea_rev;
2320
d2b2562c
TSD		 2321 strncpy(audio_info->display_name,
2322 edid_caps->display_name,
2323 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2324
b830ebc9 2325 if (cea_revision >= 3) {
e7b07cee
HW		 2326 audio_info->mode_count = edid_caps->audio_mode_count;
2327
2328 for (i = 0; i < audio_info->mode_count; ++i) {
2329 audio_info->modes[i].format_code =
2330 (enum audio_format_code)
2331 (edid_caps->audio_modes[i].format_code);
2332 audio_info->modes[i].channel_count =
2333 edid_caps->audio_modes[i].channel_count;
2334 audio_info->modes[i].sample_rates.all =
2335 edid_caps->audio_modes[i].sample_rate;
2336 audio_info->modes[i].sample_size =
2337 edid_caps->audio_modes[i].sample_size;
2338 }
2339 }
2340
2341 audio_info->flags.all = edid_caps->speaker_flags;
2342
2343 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2344 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2345 audio_info->video_latency = drm_connector->video_latency[0];
2346 audio_info->audio_latency = drm_connector->audio_latency[0];
2347 }
2348
2349 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2350
2351}
2352
3ee6b26b
AD		 2353static void
2354copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2355 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2356{
2357 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2358 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2359 dst_mode->crtc_clock = src_mode->crtc_clock;
2360 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2361 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2362 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2363 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2364 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2365 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2366 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2367 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2368 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2369 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2370 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2371}
2372
3ee6b26b
AD		 2373static void
2374decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2375 const struct drm_display_mode *native_mode,
2376 bool scale_enabled)
e7b07cee
HW		 2377{
2378 if (scale_enabled) {
2379 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2380 } else if (native_mode->clock == drm_mode->clock &&
2381 native_mode->htotal == drm_mode->htotal &&
2382 native_mode->vtotal == drm_mode->vtotal) {
2383 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2384 } else {
2385 /* no scaling nor amdgpu inserted, no need to patch */
2386 }
2387}
2388
aed15309
ML		 2389static struct dc_sink *
2390create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 2391{
2e0ac3d6 2392 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 2393 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 2394 sink_init_data.link = aconnector->dc_link;
2395 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2396
2397 sink = dc_sink_create(&sink_init_data);
423788c7 2398 if (!sink) {
2e0ac3d6 2399 DRM_ERROR("Failed to create sink!\n");
aed15309 2400 return NULL;
423788c7 2401 }
2e0ac3d6 2402 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 2403
aed15309 2404 return sink;
2e0ac3d6
HW		 2405}
2406
fa2123db
ML		 2407static void set_multisync_trigger_params(
2408 struct dc_stream_state *stream)
2409{
2410 if (stream->triggered_crtc_reset.enabled) {
2411 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2412 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2413 }
2414}
2415
2416static void set_master_stream(struct dc_stream_state *stream_set[],
2417 int stream_count)
2418{
2419 int j, highest_rfr = 0, master_stream = 0;
2420
2421 for (j = 0; j < stream_count; j++) {
2422 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2423 int refresh_rate = 0;
2424
2425 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2426 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2427 if (refresh_rate > highest_rfr) {
2428 highest_rfr = refresh_rate;
2429 master_stream = j;
2430 }
2431 }
2432 }
2433 for (j = 0; j < stream_count; j++) {
03736f4c 2434 if (stream_set[j])
fa2123db
ML		 2435 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2436 }
2437}
2438
2439static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2440{
2441 int i = 0;
2442
2443 if (context->stream_count < 2)
2444 return;
2445 for (i = 0; i < context->stream_count ; i++) {
2446 if (!context->streams[i])
2447 continue;
2448 /* TODO: add a function to read AMD VSDB bits and will set
2449 * crtc_sync_master.multi_sync_enabled flag
2450 * For now its set to false
2451 */
2452 set_multisync_trigger_params(context->streams[i]);
2453 }
2454 set_master_stream(context->streams, context->stream_count);
2455}
2456
3ee6b26b
AD		 2457static struct dc_stream_state *
2458create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2459 const struct drm_display_mode *drm_mode,
2460 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2461{
2462 struct drm_display_mode *preferred_mode = NULL;
391ef035 2463 struct drm_connector *drm_connector;
0971c40e 2464 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2465 struct drm_display_mode mode = *drm_mode;
2466 bool native_mode_found = false;
aed15309 2467 struct dc_sink *sink = NULL;
b830ebc9 2468 if (aconnector == NULL) {
e7b07cee 2469 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2470 return stream;
e7b07cee
HW		 2471 }
2472
e7b07cee 2473 drm_connector = &aconnector->base;
2e0ac3d6 2474
f4ac176e
JZ		 2475 if (!aconnector->dc_sink) {
2476 /*
391ef035
JFZ		 2477 * Create dc_sink when necessary to MST
2478 * Don't apply fake_sink to MST
f4ac176e 2479 */
391ef035
JFZ		 2480 if (aconnector->mst_port) {
2481 dm_dp_mst_dc_sink_create(drm_connector);
64245fa7 2482 return stream;
391ef035 2483 }
f4ac176e 2484
aed15309
ML		 2485 sink = create_fake_sink(aconnector);
2486 if (!sink)
64245fa7 2487 return stream;
aed15309
ML		 2488 } else {
2489 sink = aconnector->dc_sink;
f4ac176e 2490 }
2e0ac3d6 2491
aed15309 2492 stream = dc_create_stream_for_sink(sink);
4562236b 2493
b830ebc9 2494 if (stream == NULL) {
e7b07cee 2495 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 2496 goto finish;
e7b07cee
HW		 2497 }
2498
2499 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2500 /* Search for preferred mode */
2501 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2502 native_mode_found = true;
2503 break;
2504 }
2505 }
2506 if (!native_mode_found)
2507 preferred_mode = list_first_entry_or_null(
2508 &aconnector->base.modes,
2509 struct drm_display_mode,
2510 head);
2511
b830ebc9 2512 if (preferred_mode == NULL) {
e7b07cee
HW		 2513 /* This may not be an error, the use case is when we we have no
2514 * usermode calls to reset and set mode upon hotplug. In this
2515 * case, we call set mode ourselves to restore the previous mode
2516 * and the modelist may not be filled in in time.
2517 */
f1ad2f5e 2518 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2519 } else {
2520 decide_crtc_timing_for_drm_display_mode(
2521 &mode, preferred_mode,
f4791779 2522 dm_state ? (dm_state->scaling != RMX_OFF) : false);
e7b07cee
HW		 2523 }
2524
f783577c
JFZ		 2525 if (!dm_state)
2526 drm_mode_set_crtcinfo(&mode, 0);
2527
e7b07cee
HW		 2528 fill_stream_properties_from_drm_display_mode(stream,
2529 &mode, &aconnector->base);
2530 update_stream_scaling_settings(&mode, dm_state, stream);
2531
2532 fill_audio_info(
2533 &stream->audio_info,
2534 drm_connector,
aed15309 2535 sink);
e7b07cee 2536
9182b4cb
HW		 2537 update_stream_signal(stream);
2538
9e3efe3e
HW		 2539 if (dm_state && dm_state->freesync_capable)
2540 stream->ignore_msa_timing_param = true;
aed15309
ML		 2541finish:
2542 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
2543 dc_sink_release(sink);
9e3efe3e 2544
e7b07cee
HW		 2545 return stream;
2546}
2547
7578ecda 2548static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2549{
2550 drm_crtc_cleanup(crtc);
2551 kfree(crtc);
2552}
2553
2554static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2555 struct drm_crtc_state *state)
e7b07cee
HW		 2556{
2557 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2558
2559 /* TODO Destroy dc_stream objects are stream object is flattened */
2560 if (cur->stream)
2561 dc_stream_release(cur->stream);
2562
2563
2564 __drm_atomic_helper_crtc_destroy_state(state);
2565
2566
2567 kfree(state);
2568}
2569
2570static void dm_crtc_reset_state(struct drm_crtc *crtc)
2571{
2572 struct dm_crtc_state *state;
2573
2574 if (crtc->state)
2575 dm_crtc_destroy_state(crtc, crtc->state);
2576
2577 state = kzalloc(sizeof(*state), GFP_KERNEL);
2578 if (WARN_ON(!state))
2579 return;
2580
2581 crtc->state = &state->base;
2582 crtc->state->crtc = crtc;
2583
2584}
2585
2586static struct drm_crtc_state *
2587dm_crtc_duplicate_state(struct drm_crtc *crtc)
2588{
2589 struct dm_crtc_state *state, *cur;
2590
2591 cur = to_dm_crtc_state(crtc->state);
2592
2593 if (WARN_ON(!crtc->state))
2594 return NULL;
2595
2004f45e 2596 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 2597 if (!state)
2598 return NULL;
e7b07cee
HW		 2599
2600 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2601
2602 if (cur->stream) {
2603 state->stream = cur->stream;
2604 dc_stream_retain(state->stream);
2605 }
2606
98e6436d
AK		 2607 state->adjust = cur->adjust;
2608 state->vrr_infopacket = cur->vrr_infopacket;
2609 state->freesync_enabled = cur->freesync_enabled;
2610
e7b07cee
HW		 2611 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2612
2613 return &state->base;
2614}
2615
589d2739
HW		 2616
2617static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2618{
2619 enum dc_irq_source irq_source;
2620 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2621 struct amdgpu_device *adev = crtc->dev->dev_private;
2622
2623 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 2624 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 2625}
2626
2627static int dm_enable_vblank(struct drm_crtc *crtc)
2628{
2629 return dm_set_vblank(crtc, true);
2630}
2631
2632static void dm_disable_vblank(struct drm_crtc *crtc)
2633{
2634 dm_set_vblank(crtc, false);
2635}
2636
e7b07cee
HW		 2637/* Implemented only the options currently availible for the driver */
2638static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2639 .reset = dm_crtc_reset_state,
2640 .destroy = amdgpu_dm_crtc_destroy,
2641 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2642 .set_config = drm_atomic_helper_set_config,
2643 .page_flip = drm_atomic_helper_page_flip,
2644 .atomic_duplicate_state = dm_crtc_duplicate_state,
2645 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 2646 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
589d2739
HW		 2647 .enable_vblank = dm_enable_vblank,
2648 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 2649};
2650
2651static enum drm_connector_status
2652amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2653{
2654 bool connected;
c84dec2f 2655 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2656
2657 /* Notes:
2658 * 1. This interface is NOT called in context of HPD irq.
2659 * 2. This interface *is called* in context of user-mode ioctl. Which
2660 * makes it a bad place for *any* MST-related activit. */
2661
8580d60b
HW		 2662 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2663 !aconnector->fake_enable)
e7b07cee
HW		 2664 connected = (aconnector->dc_sink != NULL);
2665 else
2666 connected = (aconnector->base.force == DRM_FORCE_ON);
2667
2668 return (connected ? connector_status_connected :
2669 connector_status_disconnected);
2670}
2671
3ee6b26b
AD		 2672int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2673 struct drm_connector_state *connector_state,
2674 struct drm_property *property,
2675 uint64_t val)
e7b07cee
HW		 2676{
2677 struct drm_device *dev = connector->dev;
2678 struct amdgpu_device *adev = dev->dev_private;
2679 struct dm_connector_state *dm_old_state =
2680 to_dm_connector_state(connector->state);
2681 struct dm_connector_state *dm_new_state =
2682 to_dm_connector_state(connector_state);
2683
2684 int ret = -EINVAL;
2685
2686 if (property == dev->mode_config.scaling_mode_property) {
2687 enum amdgpu_rmx_type rmx_type;
2688
2689 switch (val) {
2690 case DRM_MODE_SCALE_CENTER:
2691 rmx_type = RMX_CENTER;
2692 break;
2693 case DRM_MODE_SCALE_ASPECT:
2694 rmx_type = RMX_ASPECT;
2695 break;
2696 case DRM_MODE_SCALE_FULLSCREEN:
2697 rmx_type = RMX_FULL;
2698 break;
2699 case DRM_MODE_SCALE_NONE:
2700 default:
2701 rmx_type = RMX_OFF;
2702 break;
2703 }
2704
2705 if (dm_old_state->scaling == rmx_type)
2706 return 0;
2707
2708 dm_new_state->scaling = rmx_type;
2709 ret = 0;
2710 } else if (property == adev->mode_info.underscan_hborder_property) {
2711 dm_new_state->underscan_hborder = val;
2712 ret = 0;
2713 } else if (property == adev->mode_info.underscan_vborder_property) {
2714 dm_new_state->underscan_vborder = val;
2715 ret = 0;
2716 } else if (property == adev->mode_info.underscan_property) {
2717 dm_new_state->underscan_enable = val;
2718 ret = 0;
2719 }
2720
2721 return ret;
2722}
2723
3ee6b26b
AD		 2724int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2725 const struct drm_connector_state *state,
2726 struct drm_property *property,
2727 uint64_t *val)
e7b07cee
HW		 2728{
2729 struct drm_device *dev = connector->dev;
2730 struct amdgpu_device *adev = dev->dev_private;
2731 struct dm_connector_state *dm_state =
2732 to_dm_connector_state(state);
2733 int ret = -EINVAL;
2734
2735 if (property == dev->mode_config.scaling_mode_property) {
2736 switch (dm_state->scaling) {
2737 case RMX_CENTER:
2738 *val = DRM_MODE_SCALE_CENTER;
2739 break;
2740 case RMX_ASPECT:
2741 *val = DRM_MODE_SCALE_ASPECT;
2742 break;
2743 case RMX_FULL:
2744 *val = DRM_MODE_SCALE_FULLSCREEN;
2745 break;
2746 case RMX_OFF:
2747 default:
2748 *val = DRM_MODE_SCALE_NONE;
2749 break;
2750 }
2751 ret = 0;
2752 } else if (property == adev->mode_info.underscan_hborder_property) {
2753 *val = dm_state->underscan_hborder;
2754 ret = 0;
2755 } else if (property == adev->mode_info.underscan_vborder_property) {
2756 *val = dm_state->underscan_vborder;
2757 ret = 0;
2758 } else if (property == adev->mode_info.underscan_property) {
2759 *val = dm_state->underscan_enable;
2760 ret = 0;
2761 }
2762 return ret;
2763}
2764
7578ecda 2765static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2766{
c84dec2f 2767 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2768 const struct dc_link *link = aconnector->dc_link;
2769 struct amdgpu_device *adev = connector->dev->dev_private;
2770 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 2771
e7b07cee
HW		 2772#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2773 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2774
89fc8d4e 2775 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 2776 link->type != dc_connection_none &&
2777 dm->backlight_dev) {
2778 backlight_device_unregister(dm->backlight_dev);
2779 dm->backlight_dev = NULL;
e7b07cee
HW		 2780 }
2781#endif
2782 drm_connector_unregister(connector);
2783 drm_connector_cleanup(connector);
2784 kfree(connector);
2785}
2786
2787void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2788{
2789 struct dm_connector_state *state =
2790 to_dm_connector_state(connector->state);
2791
df099b9b
LSL		 2792 if (connector->state)
2793 __drm_atomic_helper_connector_destroy_state(connector->state);
2794
e7b07cee
HW		 2795 kfree(state);
2796
2797 state = kzalloc(sizeof(*state), GFP_KERNEL);
2798
2799 if (state) {
2800 state->scaling = RMX_OFF;
2801 state->underscan_enable = false;
2802 state->underscan_hborder = 0;
2803 state->underscan_vborder = 0;
2804
df099b9b 2805 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 2806 }
2807}
2808
3ee6b26b
AD		 2809struct drm_connector_state *
2810amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2811{
2812 struct dm_connector_state *state =
2813 to_dm_connector_state(connector->state);
2814
2815 struct dm_connector_state *new_state =
2816 kmemdup(state, sizeof(*state), GFP_KERNEL);
2817
98e6436d
AK		 2818 if (!new_state)
2819 return NULL;
e7b07cee 2820
98e6436d
AK		 2821 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
2822
2823 new_state->freesync_capable = state->freesync_capable;
2824 new_state->freesync_enable = state->freesync_enable;
2825
2826 return &new_state->base;
e7b07cee
HW		 2827}
2828
2829static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2830 .reset = amdgpu_dm_connector_funcs_reset,
2831 .detect = amdgpu_dm_connector_detect,
2832 .fill_modes = drm_helper_probe_single_connector_modes,
2833 .destroy = amdgpu_dm_connector_destroy,
2834 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2835 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2836 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2837 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2838};
2839
2840static struct drm_encoder *best_encoder(struct drm_connector *connector)
2841{
2842 int enc_id = connector->encoder_ids[0];
2843 struct drm_mode_object *obj;
2844 struct drm_encoder *encoder;
2845
f1ad2f5e 2846 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2847
2848 /* pick the encoder ids */
2849 if (enc_id) {
bd21a37d 2850 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2851 if (!obj) {
2852 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2853 return NULL;
2854 }
2855 encoder = obj_to_encoder(obj);
2856 return encoder;
2857 }
2858 DRM_ERROR("No encoder id\n");
2859 return NULL;
2860}
2861
2862static int get_modes(struct drm_connector *connector)
2863{
2864 return amdgpu_dm_connector_get_modes(connector);
2865}
2866
c84dec2f 2867static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2868{
2869 struct dc_sink_init_data init_params = {
2870 .link = aconnector->dc_link,
2871 .sink_signal = SIGNAL_TYPE_VIRTUAL
2872 };
70e8ffc5 2873 struct edid *edid;
e7b07cee 2874
a89ff457 2875 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 2876 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2877 aconnector->base.name);
2878
2879 aconnector->base.force = DRM_FORCE_OFF;
2880 aconnector->base.override_edid = false;
2881 return;
2882 }
2883
70e8ffc5
HW		 2884 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2885
e7b07cee
HW		 2886 aconnector->edid = edid;
2887
2888 aconnector->dc_em_sink = dc_link_add_remote_sink(
2889 aconnector->dc_link,
2890 (uint8_t *)edid,
2891 (edid->extensions + 1) * EDID_LENGTH,
2892 &init_params);
2893
a68d90e7 2894 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 2895 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2896 aconnector->dc_link->local_sink :
2897 aconnector->dc_em_sink;
2898}
2899
c84dec2f 2900static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2901{
2902 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2903
2904 /* In case of headless boot with force on for DP managed connector
2905 * Those settings have to be != 0 to get initial modeset
2906 */
2907 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2908 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2909 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2910 }
2911
2912
2913 aconnector->base.override_edid = true;
2914 create_eml_sink(aconnector);
2915}
2916
ba9ca088 2917enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 2918 struct drm_display_mode *mode)
e7b07cee
HW		 2919{
2920 int result = MODE_ERROR;
2921 struct dc_sink *dc_sink;
2922 struct amdgpu_device *adev = connector->dev->dev_private;
2923 /* TODO: Unhardcode stream count */
0971c40e 2924 struct dc_stream_state *stream;
c84dec2f 2925 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 2926 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 2927
2928 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2929 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2930 return result;
2931
2932 /* Only run this the first time mode_valid is called to initilialize
2933 * EDID mgmt
2934 */
2935 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2936 !aconnector->dc_em_sink)
2937 handle_edid_mgmt(aconnector);
2938
c84dec2f 2939 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2940
b830ebc9 2941 if (dc_sink == NULL) {
e7b07cee
HW		 2942 DRM_ERROR("dc_sink is NULL!\n");
2943 goto fail;
2944 }
2945
f4791779 2946 stream = create_stream_for_sink(aconnector, mode, NULL);
b830ebc9 2947 if (stream == NULL) {
e7b07cee
HW		 2948 DRM_ERROR("Failed to create stream for sink!\n");
2949 goto fail;
2950 }
2951
a39438f0
HW		 2952 dc_result = dc_validate_stream(adev->dm.dc, stream);
2953
2954 if (dc_result == DC_OK)
e7b07cee 2955 result = MODE_OK;
a39438f0 2956 else
9f921b14 2957 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 2958 mode->vdisplay,
2959 mode->hdisplay,
9f921b14
HW		 2960 mode->clock,
2961 dc_result);
e7b07cee
HW		 2962
2963 dc_stream_release(stream);
2964
2965fail:
2966 /* TODO: error handling*/
2967 return result;
2968}
2969
2970static const struct drm_connector_helper_funcs
2971amdgpu_dm_connector_helper_funcs = {
2972 /*
b830ebc9
HW		 2973 * If hotplug a second bigger display in FB Con mode, bigger resolution
2974 * modes will be filtered by drm_mode_validate_size(), and those modes
2975 * is missing after user start lightdm. So we need to renew modes list.
2976 * in get_modes call back, not just return the modes count
2977 */
e7b07cee
HW		 2978 .get_modes = get_modes,
2979 .mode_valid = amdgpu_dm_connector_mode_valid,
2980 .best_encoder = best_encoder
2981};
2982
2983static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2984{
2985}
2986
3ee6b26b
AD		 2987static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2988 struct drm_crtc_state *state)
e7b07cee
HW		 2989{
2990 struct amdgpu_device *adev = crtc->dev->dev_private;
2991 struct dc *dc = adev->dm.dc;
2992 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2993 int ret = -EINVAL;
2994
9b690ef3
BL		 2995 if (unlikely(!dm_crtc_state->stream &&
2996 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2997 WARN_ON(1);
2998 return ret;
2999 }
3000
3001 /* In some use cases, like reset, no stream is attached */
3002 if (!dm_crtc_state->stream)
3003 return 0;
3004
62c933f9 3005 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 3006 return 0;
3007
3008 return ret;
3009}
3010
3ee6b26b
AD		 3011static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3012 const struct drm_display_mode *mode,
3013 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 3014{
3015 return true;
3016}
3017
3018static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3019 .disable = dm_crtc_helper_disable,
3020 .atomic_check = dm_crtc_helper_atomic_check,
3021 .mode_fixup = dm_crtc_helper_mode_fixup
3022};
3023
3024static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3025{
3026
3027}
3028
3ee6b26b
AD		 3029static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3030 struct drm_crtc_state *crtc_state,
3031 struct drm_connector_state *conn_state)
e7b07cee
HW		 3032{
3033 return 0;
3034}
3035
3036const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3037 .disable = dm_encoder_helper_disable,
3038 .atomic_check = dm_encoder_helper_atomic_check
3039};
3040
3041static void dm_drm_plane_reset(struct drm_plane *plane)
3042{
3043 struct dm_plane_state *amdgpu_state = NULL;
3044
3045 if (plane->state)
3046 plane->funcs->atomic_destroy_state(plane, plane->state);
3047
3048 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d
TSD		 3049 WARN_ON(amdgpu_state == NULL);
3050
e7b07cee
HW		 3051 if (amdgpu_state) {
3052 plane->state = &amdgpu_state->base;
3053 plane->state->plane = plane;
3054 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 3055 }
e7b07cee
HW		 3056}
3057
3058static struct drm_plane_state *
3059dm_drm_plane_duplicate_state(struct drm_plane *plane)
3060{
3061 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3062
3063 old_dm_plane_state = to_dm_plane_state(plane->state);
3064 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3065 if (!dm_plane_state)
3066 return NULL;
3067
3068 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3069
3be5262e
HW		 3070 if (old_dm_plane_state->dc_state) {
3071 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3072 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 3073 }
3074
3075 return &dm_plane_state->base;
3076}
3077
3078void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 3079 struct drm_plane_state *state)
e7b07cee
HW		 3080{
3081 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3082
3be5262e
HW		 3083 if (dm_plane_state->dc_state)
3084 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 3085
0627bbd3 3086 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 3087}
3088
3089static const struct drm_plane_funcs dm_plane_funcs = {
3090 .update_plane = drm_atomic_helper_update_plane,
3091 .disable_plane = drm_atomic_helper_disable_plane,
3092 .destroy = drm_plane_cleanup,
3093 .reset = dm_drm_plane_reset,
3094 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3095 .atomic_destroy_state = dm_drm_plane_destroy_state,
3096};
3097
3ee6b26b
AD		 3098static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3099 struct drm_plane_state *new_state)
e7b07cee
HW		 3100{
3101 struct amdgpu_framebuffer *afb;
3102 struct drm_gem_object *obj;
5d43be0c 3103 struct amdgpu_device *adev;
e7b07cee 3104 struct amdgpu_bo *rbo;
56087b31 3105 uint64_t chroma_addr = 0;
e7b07cee
HW		 3106 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3107 unsigned int awidth;
5d43be0c
CK		 3108 uint32_t domain;
3109 int r;
e7b07cee
HW		 3110
3111 dm_plane_state_old = to_dm_plane_state(plane->state);
3112 dm_plane_state_new = to_dm_plane_state(new_state);
3113
3114 if (!new_state->fb) {
f1ad2f5e 3115 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3116 return 0;
3117 }
3118
3119 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 3120 obj = new_state->fb->obj[0];
e7b07cee 3121 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3122 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3123 r = amdgpu_bo_reserve(rbo, false);
3124 if (unlikely(r != 0))
3125 return r;
3126
5d43be0c 3127 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 3128 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 3129 else
3130 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3131
7b7c6c81 3132 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 3133 if (unlikely(r != 0)) {
30b7c614
HW		 3134 if (r != -ERESTARTSYS)
3135 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
bb812f1e 3136 amdgpu_bo_unreserve(rbo);
e7b07cee
HW		 3137 return r;
3138 }
3139
bb812f1e
JZ		 3140 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3141 if (unlikely(r != 0)) {
3142 amdgpu_bo_unpin(rbo);
3143 amdgpu_bo_unreserve(rbo);
3144 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 3145 return r;
3146 }
bb812f1e
JZ		 3147 amdgpu_bo_unreserve(rbo);
3148
7b7c6c81 3149 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 3150
3151 amdgpu_bo_ref(rbo);
3152
3be5262e
HW		 3153 if (dm_plane_state_new->dc_state &&
3154 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3155 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3156
3be5262e
HW		 3157 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3158 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3159 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 3160 } else {
3161 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3162 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3163 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3164 = lower_32_bits(afb->address);
56087b31
S		 3165 plane_state->address.video_progressive.luma_addr.high_part
3166 = upper_32_bits(afb->address);
35888630 3167 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3168 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3169 = lower_32_bits(chroma_addr);
3170 plane_state->address.video_progressive.chroma_addr.high_part
3171 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3172 }
3173 }
3174
e7b07cee
HW		 3175 return 0;
3176}
3177
3ee6b26b
AD		 3178static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3179 struct drm_plane_state *old_state)
e7b07cee
HW		 3180{
3181 struct amdgpu_bo *rbo;
e7b07cee
HW		 3182 int r;
3183
3184 if (!old_state->fb)
3185 return;
3186
e68d14dd 3187 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 3188 r = amdgpu_bo_reserve(rbo, false);
3189 if (unlikely(r)) {
3190 DRM_ERROR("failed to reserve rbo before unpin\n");
3191 return;
b830ebc9
HW		 3192 }
3193
3194 amdgpu_bo_unpin(rbo);
3195 amdgpu_bo_unreserve(rbo);
3196 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3197}
3198
7578ecda
AD		 3199static int dm_plane_atomic_check(struct drm_plane *plane,
3200 struct drm_plane_state *state)
cbd19488
AG		 3201{
3202 struct amdgpu_device *adev = plane->dev->dev_private;
3203 struct dc *dc = adev->dm.dc;
3204 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3205
3be5262e 3206 if (!dm_plane_state->dc_state)
9a3329b1 3207 return 0;
cbd19488 3208
a05bcff1
S		 3209 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3210 return -EINVAL;
3211
62c933f9 3212 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3213 return 0;
3214
3215 return -EINVAL;
3216}
3217
e7b07cee
HW		 3218static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3219 .prepare_fb = dm_plane_helper_prepare_fb,
3220 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3221 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3222};
3223
3224/*
3225 * TODO: these are currently initialized to rgb formats only.
3226 * For future use cases we should either initialize them dynamically based on
3227 * plane capabilities, or initialize this array to all formats, so internal drm
3228 * check will succeed, and let DC to implement proper check
3229 */
d90371b0 3230static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3231 DRM_FORMAT_RGB888,
3232 DRM_FORMAT_XRGB8888,
3233 DRM_FORMAT_ARGB8888,
3234 DRM_FORMAT_RGBA8888,
3235 DRM_FORMAT_XRGB2101010,
3236 DRM_FORMAT_XBGR2101010,
3237 DRM_FORMAT_ARGB2101010,
3238 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 3239 DRM_FORMAT_XBGR8888,
3240 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 3241};
3242
99d1abf8 3243static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3244 DRM_FORMAT_NV12,
3245 DRM_FORMAT_NV21,
3246};
3247
3248static const u32 cursor_formats[] = {
3249 DRM_FORMAT_ARGB8888
3250};
3251
7578ecda
AD		 3252static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3253 struct amdgpu_plane *aplane,
3254 unsigned long possible_crtcs)
e7b07cee
HW		 3255{
3256 int res = -EPERM;
3257
3258 switch (aplane->base.type) {
3259 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3260 res = drm_universal_plane_init(
3261 dm->adev->ddev,
3262 &aplane->base,
3263 possible_crtcs,
3264 &dm_plane_funcs,
3265 rgb_formats,
3266 ARRAY_SIZE(rgb_formats),
3267 NULL, aplane->base.type, NULL);
3268 break;
3269 case DRM_PLANE_TYPE_OVERLAY:
3270 res = drm_universal_plane_init(
3271 dm->adev->ddev,
3272 &aplane->base,
3273 possible_crtcs,
3274 &dm_plane_funcs,
3275 yuv_formats,
3276 ARRAY_SIZE(yuv_formats),
3277 NULL, aplane->base.type, NULL);
3278 break;
3279 case DRM_PLANE_TYPE_CURSOR:
3280 res = drm_universal_plane_init(
3281 dm->adev->ddev,
3282 &aplane->base,
3283 possible_crtcs,
3284 &dm_plane_funcs,
3285 cursor_formats,
3286 ARRAY_SIZE(cursor_formats),
3287 NULL, aplane->base.type, NULL);
3288 break;
3289 }
3290
3291 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3292
96719c54
HW		 3293 /* Create (reset) the plane state */
3294 if (aplane->base.funcs->reset)
3295 aplane->base.funcs->reset(&aplane->base);
3296
3297
e7b07cee
HW		 3298 return res;
3299}
3300
7578ecda
AD		 3301static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3302 struct drm_plane *plane,
3303 uint32_t crtc_index)
e7b07cee
HW		 3304{
3305 struct amdgpu_crtc *acrtc = NULL;
3306 struct amdgpu_plane *cursor_plane;
3307
3308 int res = -ENOMEM;
3309
3310 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3311 if (!cursor_plane)
3312 goto fail;
3313
3314 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3315 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3316
3317 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3318 if (!acrtc)
3319 goto fail;
3320
3321 res = drm_crtc_init_with_planes(
3322 dm->ddev,
3323 &acrtc->base,
3324 plane,
3325 &cursor_plane->base,
3326 &amdgpu_dm_crtc_funcs, NULL);
3327
3328 if (res)
3329 goto fail;
3330
3331 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3332
96719c54
HW		 3333 /* Create (reset) the plane state */
3334 if (acrtc->base.funcs->reset)
3335 acrtc->base.funcs->reset(&acrtc->base);
3336
e7b07cee
HW		 3337 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3338 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3339
3340 acrtc->crtc_id = crtc_index;
3341 acrtc->base.enabled = false;
3342
3343 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3344 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3345 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3346 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3347
3348 return 0;
3349
3350fail:
b830ebc9
HW		 3351 kfree(acrtc);
3352 kfree(cursor_plane);
e7b07cee
HW		 3353 return res;
3354}
3355
3356
3357static int to_drm_connector_type(enum signal_type st)
3358{
3359 switch (st) {
3360 case SIGNAL_TYPE_HDMI_TYPE_A:
3361 return DRM_MODE_CONNECTOR_HDMIA;
3362 case SIGNAL_TYPE_EDP:
3363 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 3364 case SIGNAL_TYPE_LVDS:
3365 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 3366 case SIGNAL_TYPE_RGB:
3367 return DRM_MODE_CONNECTOR_VGA;
3368 case SIGNAL_TYPE_DISPLAY_PORT:
3369 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3370 return DRM_MODE_CONNECTOR_DisplayPort;
3371 case SIGNAL_TYPE_DVI_DUAL_LINK:
3372 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3373 return DRM_MODE_CONNECTOR_DVID;
3374 case SIGNAL_TYPE_VIRTUAL:
3375 return DRM_MODE_CONNECTOR_VIRTUAL;
3376
3377 default:
3378 return DRM_MODE_CONNECTOR_Unknown;
3379 }
3380}
3381
3382static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3383{
3384 const struct drm_connector_helper_funcs *helper =
3385 connector->helper_private;
3386 struct drm_encoder *encoder;
3387 struct amdgpu_encoder *amdgpu_encoder;
3388
3389 encoder = helper->best_encoder(connector);
3390
3391 if (encoder == NULL)
3392 return;
3393
3394 amdgpu_encoder = to_amdgpu_encoder(encoder);
3395
3396 amdgpu_encoder->native_mode.clock = 0;
3397
3398 if (!list_empty(&connector->probed_modes)) {
3399 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3400
e7b07cee 3401 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3402 &connector->probed_modes,
3403 head) {
3404 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3405 amdgpu_encoder->native_mode = *preferred_mode;
3406
e7b07cee
HW		 3407 break;
3408 }
3409
3410 }
3411}
3412
3ee6b26b
AD		 3413static struct drm_display_mode *
3414amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3415 char *name,
3416 int hdisplay, int vdisplay)
e7b07cee
HW		 3417{
3418 struct drm_device *dev = encoder->dev;
3419 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3420 struct drm_display_mode *mode = NULL;
3421 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3422
3423 mode = drm_mode_duplicate(dev, native_mode);
3424
b830ebc9 3425 if (mode == NULL)
e7b07cee
HW		 3426 return NULL;
3427
3428 mode->hdisplay = hdisplay;
3429 mode->vdisplay = vdisplay;
3430 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3431 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3432
3433 return mode;
3434
3435}
3436
3437static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3438 struct drm_connector *connector)
e7b07cee
HW		 3439{
3440 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3441 struct drm_display_mode *mode = NULL;
3442 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3443 struct amdgpu_dm_connector *amdgpu_dm_connector =
3444 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3445 int i;
3446 int n;
3447 struct mode_size {
3448 char name[DRM_DISPLAY_MODE_LEN];
3449 int w;
3450 int h;
b830ebc9 3451 } common_modes[] = {
e7b07cee
HW		 3452 { "640x480", 640, 480},
3453 { "800x600", 800, 600},
3454 { "1024x768", 1024, 768},
3455 { "1280x720", 1280, 720},
3456 { "1280x800", 1280, 800},
3457 {"1280x1024", 1280, 1024},
3458 { "1440x900", 1440, 900},
3459 {"1680x1050", 1680, 1050},
3460 {"1600x1200", 1600, 1200},
3461 {"1920x1080", 1920, 1080},
3462 {"1920x1200", 1920, 1200}
3463 };
3464
b830ebc9 3465 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3466
3467 for (i = 0; i < n; i++) {
3468 struct drm_display_mode *curmode = NULL;
3469 bool mode_existed = false;
3470
3471 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3472 common_modes[i].h > native_mode->vdisplay ||
3473 (common_modes[i].w == native_mode->hdisplay &&
3474 common_modes[i].h == native_mode->vdisplay))
3475 continue;
e7b07cee
HW		 3476
3477 list_for_each_entry(curmode, &connector->probed_modes, head) {
3478 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3479 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3480 mode_existed = true;
3481 break;
3482 }
3483 }
3484
3485 if (mode_existed)
3486 continue;
3487
3488 mode = amdgpu_dm_create_common_mode(encoder,
3489 common_modes[i].name, common_modes[i].w,
3490 common_modes[i].h);
3491 drm_mode_probed_add(connector, mode);
c84dec2f 3492 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3493 }
3494}
3495
3ee6b26b
AD		 3496static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3497 struct edid *edid)
e7b07cee 3498{
c84dec2f
HW		 3499 struct amdgpu_dm_connector *amdgpu_dm_connector =
3500 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3501
3502 if (edid) {
3503 /* empty probed_modes */
3504 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3505 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3506 drm_add_edid_modes(connector, edid);
3507
e7b07cee 3508 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3509 } else {
c84dec2f 3510 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3511 }
e7b07cee
HW		 3512}
3513
7578ecda 3514static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3515{
3516 const struct drm_connector_helper_funcs *helper =
3517 connector->helper_private;
c84dec2f
HW		 3518 struct amdgpu_dm_connector *amdgpu_dm_connector =
3519 to_amdgpu_dm_connector(connector);
e7b07cee 3520 struct drm_encoder *encoder;
c84dec2f 3521 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3522
3523 encoder = helper->best_encoder(connector);
3e332d3a 3524
85ee15d6 3525 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 3526 amdgpu_dm_connector->num_modes =
3527 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 3528 } else {
3529 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3530 amdgpu_dm_connector_add_common_modes(encoder, connector);
3531 }
3e332d3a 3532 amdgpu_dm_fbc_init(connector);
5099114b 3533
c84dec2f 3534 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3535}
3536
3ee6b26b
AD		 3537void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3538 struct amdgpu_dm_connector *aconnector,
3539 int connector_type,
3540 struct dc_link *link,
3541 int link_index)
e7b07cee
HW		 3542{
3543 struct amdgpu_device *adev = dm->ddev->dev_private;
3544
3545 aconnector->connector_id = link_index;
3546 aconnector->dc_link = link;
3547 aconnector->base.interlace_allowed = false;
3548 aconnector->base.doublescan_allowed = false;
3549 aconnector->base.stereo_allowed = false;
3550 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3551 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
e7b07cee
HW		 3552 mutex_init(&aconnector->hpd_lock);
3553
b830ebc9
HW		 3554 /* configure support HPD hot plug connector_>polled default value is 0
3555 * which means HPD hot plug not supported
3556 */
e7b07cee
HW		 3557 switch (connector_type) {
3558 case DRM_MODE_CONNECTOR_HDMIA:
3559 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c
JFZ		 3560 aconnector->base.ycbcr_420_allowed =
3561 link->link_enc->features.ycbcr420_supported ? true : false;
e7b07cee
HW		 3562 break;
3563 case DRM_MODE_CONNECTOR_DisplayPort:
3564 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c
JFZ		 3565 aconnector->base.ycbcr_420_allowed =
3566 link->link_enc->features.ycbcr420_supported ? true : false;
e7b07cee
HW		 3567 break;
3568 case DRM_MODE_CONNECTOR_DVID:
3569 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3570 break;
3571 default:
3572 break;
3573 }
3574
3575 drm_object_attach_property(&aconnector->base.base,
3576 dm->ddev->mode_config.scaling_mode_property,
3577 DRM_MODE_SCALE_NONE);
3578
3579 drm_object_attach_property(&aconnector->base.base,
3580 adev->mode_info.underscan_property,
3581 UNDERSCAN_OFF);
3582 drm_object_attach_property(&aconnector->base.base,
3583 adev->mode_info.underscan_hborder_property,
3584 0);
3585 drm_object_attach_property(&aconnector->base.base,
3586 adev->mode_info.underscan_vborder_property,
3587 0);
3588
3589}
3590
7578ecda
AD		 3591static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3592 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3593{
3594 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3595 struct ddc_service *ddc_service = i2c->ddc_service;
3596 struct i2c_command cmd;
3597 int i;
3598 int result = -EIO;
3599
b830ebc9 3600 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3601
3602 if (!cmd.payloads)
3603 return result;
3604
3605 cmd.number_of_payloads = num;
3606 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3607 cmd.speed = 100;
3608
3609 for (i = 0; i < num; i++) {
3610 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3611 cmd.payloads[i].address = msgs[i].addr;
3612 cmd.payloads[i].length = msgs[i].len;
3613 cmd.payloads[i].data = msgs[i].buf;
3614 }
3615
c85e6e54
DF		 3616 if (dc_submit_i2c(
3617 ddc_service->ctx->dc,
3618 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 3619 &cmd))
3620 result = num;
3621
3622 kfree(cmd.payloads);
3623 return result;
3624}
3625
7578ecda 3626static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3627{
3628 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3629}
3630
3631static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3632 .master_xfer = amdgpu_dm_i2c_xfer,
3633 .functionality = amdgpu_dm_i2c_func,
3634};
3635
3ee6b26b
AD		 3636static struct amdgpu_i2c_adapter *
3637create_i2c(struct ddc_service *ddc_service,
3638 int link_index,
3639 int *res)
e7b07cee
HW		 3640{
3641 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3642 struct amdgpu_i2c_adapter *i2c;
3643
b830ebc9 3644 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 3645 if (!i2c)
3646 return NULL;
e7b07cee
HW		 3647 i2c->base.owner = THIS_MODULE;
3648 i2c->base.class = I2C_CLASS_DDC;
3649 i2c->base.dev.parent = &adev->pdev->dev;
3650 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3651 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3652 i2c_set_adapdata(&i2c->base, i2c);
3653 i2c->ddc_service = ddc_service;
c85e6e54 3654 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 3655
3656 return i2c;
3657}
3658
89fc8d4e 3659
e7b07cee 3660/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3661 * dc_link which will be represented by this aconnector.
3662 */
7578ecda
AD		 3663static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3664 struct amdgpu_dm_connector *aconnector,
3665 uint32_t link_index,
3666 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3667{
3668 int res = 0;
3669 int connector_type;
3670 struct dc *dc = dm->dc;
3671 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3672 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 3673
3674 link->priv = aconnector;
e7b07cee 3675
f1ad2f5e 3676 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3677
3678 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 3679 if (!i2c) {
3680 DRM_ERROR("Failed to create i2c adapter data\n");
3681 return -ENOMEM;
3682 }
3683
e7b07cee
HW		 3684 aconnector->i2c = i2c;
3685 res = i2c_add_adapter(&i2c->base);
3686
3687 if (res) {
3688 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3689 goto out_free;
3690 }
3691
3692 connector_type = to_drm_connector_type(link->connector_signal);
3693
3694 res = drm_connector_init(
3695 dm->ddev,
3696 &aconnector->base,
3697 &amdgpu_dm_connector_funcs,
3698 connector_type);
3699
3700 if (res) {
3701 DRM_ERROR("connector_init failed\n");
3702 aconnector->connector_id = -1;
3703 goto out_free;
3704 }
3705
3706 drm_connector_helper_add(
3707 &aconnector->base,
3708 &amdgpu_dm_connector_helper_funcs);
3709
96719c54
HW		 3710 if (aconnector->base.funcs->reset)
3711 aconnector->base.funcs->reset(&aconnector->base);
3712
e7b07cee
HW		 3713 amdgpu_dm_connector_init_helper(
3714 dm,
3715 aconnector,
3716 connector_type,
3717 link,
3718 link_index);
3719
cde4c44d 3720 drm_connector_attach_encoder(
e7b07cee
HW		 3721 &aconnector->base, &aencoder->base);
3722
3723 drm_connector_register(&aconnector->base);
dc38fd9d
DF		 3724#if defined(CONFIG_DEBUG_FS)
3725 res = connector_debugfs_init(aconnector);
3726 if (res) {
3727 DRM_ERROR("Failed to create debugfs for connector");
3728 goto out_free;
3729 }
3730#endif
e7b07cee
HW		 3731
3732 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3733 || connector_type == DRM_MODE_CONNECTOR_eDP)
3734 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3735
e7b07cee
HW		 3736out_free:
3737 if (res) {
3738 kfree(i2c);
3739 aconnector->i2c = NULL;
3740 }
3741 return res;
3742}
3743
3744int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3745{
3746 switch (adev->mode_info.num_crtc) {
3747 case 1:
3748 return 0x1;
3749 case 2:
3750 return 0x3;
3751 case 3:
3752 return 0x7;
3753 case 4:
3754 return 0xf;
3755 case 5:
3756 return 0x1f;
3757 case 6:
3758 default:
3759 return 0x3f;
3760 }
3761}
3762
7578ecda
AD		 3763static int amdgpu_dm_encoder_init(struct drm_device *dev,
3764 struct amdgpu_encoder *aencoder,
3765 uint32_t link_index)
e7b07cee
HW		 3766{
3767 struct amdgpu_device *adev = dev->dev_private;
3768
3769 int res = drm_encoder_init(dev,
3770 &aencoder->base,
3771 &amdgpu_dm_encoder_funcs,
3772 DRM_MODE_ENCODER_TMDS,
3773 NULL);
3774
3775 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3776
3777 if (!res)
3778 aencoder->encoder_id = link_index;
3779 else
3780 aencoder->encoder_id = -1;
3781
3782 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3783
3784 return res;
3785}
3786
3ee6b26b
AD		 3787static void manage_dm_interrupts(struct amdgpu_device *adev,
3788 struct amdgpu_crtc *acrtc,
3789 bool enable)
e7b07cee
HW		 3790{
3791 /*
3792 * this is not correct translation but will work as soon as VBLANK
3793 * constant is the same as PFLIP
3794 */
3795 int irq_type =
734dd01d 3796 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 3797 adev,
3798 acrtc->crtc_id);
3799
3800 if (enable) {
3801 drm_crtc_vblank_on(&acrtc->base);
3802 amdgpu_irq_get(
3803 adev,
3804 &adev->pageflip_irq,
3805 irq_type);
3806 } else {
3807
3808 amdgpu_irq_put(
3809 adev,
3810 &adev->pageflip_irq,
3811 irq_type);
3812 drm_crtc_vblank_off(&acrtc->base);
3813 }
3814}
3815
3ee6b26b
AD		 3816static bool
3817is_scaling_state_different(const struct dm_connector_state *dm_state,
3818 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3819{
3820 if (dm_state->scaling != old_dm_state->scaling)
3821 return true;
3822 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3823 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3824 return true;
3825 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3826 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3827 return true;
b830ebc9
HW		 3828 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3829 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3830 return true;
e7b07cee
HW		 3831 return false;
3832}
3833
3ee6b26b
AD		 3834static void remove_stream(struct amdgpu_device *adev,
3835 struct amdgpu_crtc *acrtc,
3836 struct dc_stream_state *stream)
e7b07cee
HW		 3837{
3838 /* this is the update mode case */
e7b07cee
HW		 3839
3840 acrtc->otg_inst = -1;
3841 acrtc->enabled = false;
3842}
3843
7578ecda
AD		 3844static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3845 struct dc_cursor_position *position)
2a8f6ccb 3846{
f4c2cc43 3847 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 3848 int x, y;
3849 int xorigin = 0, yorigin = 0;
3850
3851 if (!crtc || !plane->state->fb) {
3852 position->enable = false;
3853 position->x = 0;
3854 position->y = 0;
3855 return 0;
3856 }
3857
3858 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3859 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3860 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3861 __func__,
3862 plane->state->crtc_w,
3863 plane->state->crtc_h);
3864 return -EINVAL;
3865 }
3866
3867 x = plane->state->crtc_x;
3868 y = plane->state->crtc_y;
3869 /* avivo cursor are offset into the total surface */
3870 x += crtc->primary->state->src_x >> 16;
3871 y += crtc->primary->state->src_y >> 16;
3872 if (x < 0) {
3873 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3874 x = 0;
3875 }
3876 if (y < 0) {
3877 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3878 y = 0;
3879 }
3880 position->enable = true;
3881 position->x = x;
3882 position->y = y;
3883 position->x_hotspot = xorigin;
3884 position->y_hotspot = yorigin;
3885
3886 return 0;
3887}
3888
3ee6b26b
AD		 3889static void handle_cursor_update(struct drm_plane *plane,
3890 struct drm_plane_state *old_plane_state)
e7b07cee 3891{
2a8f6ccb
HW		 3892 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3893 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3894 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3895 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3896 uint64_t address = afb ? afb->address : 0;
3897 struct dc_cursor_position position;
3898 struct dc_cursor_attributes attributes;
3899 int ret;
3900
e7b07cee
HW		 3901 if (!plane->state->fb && !old_plane_state->fb)
3902 return;
3903
f1ad2f5e 3904 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3905 __func__,
3906 amdgpu_crtc->crtc_id,
3907 plane->state->crtc_w,
3908 plane->state->crtc_h);
2a8f6ccb
HW		 3909
3910 ret = get_cursor_position(plane, crtc, &position);
3911 if (ret)
3912 return;
3913
3914 if (!position.enable) {
3915 /* turn off cursor */
3916 if (crtc_state && crtc_state->stream)
3917 dc_stream_set_cursor_position(crtc_state->stream,
3918 &position);
3919 return;
e7b07cee 3920 }
e7b07cee 3921
2a8f6ccb
HW		 3922 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3923 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3924
3925 attributes.address.high_part = upper_32_bits(address);
3926 attributes.address.low_part = lower_32_bits(address);
3927 attributes.width = plane->state->crtc_w;
3928 attributes.height = plane->state->crtc_h;
3929 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3930 attributes.rotation_angle = 0;
3931 attributes.attribute_flags.value = 0;
3932
3933 attributes.pitch = attributes.width;
3934
886daac9
JZ		 3935 if (crtc_state->stream) {
3936 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3937 &attributes))
3938 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3939
2a8f6ccb
HW		 3940 if (!dc_stream_set_cursor_position(crtc_state->stream,
3941 &position))
3942 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3943 }
2a8f6ccb 3944}
e7b07cee
HW		 3945
3946static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3947{
3948
3949 assert_spin_locked(&acrtc->base.dev->event_lock);
3950 WARN_ON(acrtc->event);
3951
3952 acrtc->event = acrtc->base.state->event;
3953
3954 /* Set the flip status */
3955 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3956
3957 /* Mark this event as consumed */
3958 acrtc->base.state->event = NULL;
3959
3960 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3961 acrtc->crtc_id);
3962}
3963
3964/*
3965 * Executes flip
3966 *
3967 * Waits on all BO's fences and for proper vblank count
3968 */
3ee6b26b
AD		 3969static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3970 struct drm_framebuffer *fb,
bc6828e0
BL		 3971 uint32_t target,
3972 struct dc_state *state)
e7b07cee
HW		 3973{
3974 unsigned long flags;
3975 uint32_t target_vblank;
3976 int r, vpos, hpos;
3977 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3978 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
e68d14dd 3979 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
e7b07cee 3980 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3981 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3982 struct dc_flip_addrs addr = { {0} };
3be5262e 3983 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3984 struct dc_surface_update surface_updates[1] = { {0} };
3985 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3986
3987
3988 /* Prepare wait for target vblank early - before the fence-waits */
23effc11 3989 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
e7b07cee
HW		 3990 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3991
b830ebc9 3992 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3993 * explicitly on fences instead
3994 * and in general should be called for
3995 * blocking commit to as per framework helpers
b830ebc9 3996 */
e7b07cee
HW		 3997 r = amdgpu_bo_reserve(abo, true);
3998 if (unlikely(r != 0)) {
3999 DRM_ERROR("failed to reserve buffer before flip\n");
4000 WARN_ON(1);
4001 }
4002
4003 /* Wait for all fences on this FB */
4004 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
4005 MAX_SCHEDULE_TIMEOUT) < 0);
4006
4007 amdgpu_bo_unreserve(abo);
4008
4009 /* Wait until we're out of the vertical blank period before the one
4010 * targeted by the flip
4011 */
4012 while ((acrtc->enabled &&
aa8e286a
SL		 4013 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
4014 0, &vpos, &hpos, NULL,
4015 NULL, &crtc->hwmode)
e7b07cee
HW		 4016 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4017 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4018 (int)(target_vblank -
4019 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
4020 usleep_range(1000, 1100);
4021 }
4022
4023 /* Flip */
4024 spin_lock_irqsave(&crtc->dev->event_lock, flags);
e7b07cee
HW		 4025
4026 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
4027 WARN_ON(!acrtc_state->stream);
4028
4029 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
4030 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
4031 addr.flip_immediate = async_flip;
4032
4033
4034 if (acrtc->base.state->event)
4035 prepare_flip_isr(acrtc);
4036
4de9f38b
S		 4037 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4038
3be5262e 4039 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 4040 surface_updates->flip_addr = &addr;
4041
bc6828e0
BL		 4042 dc_commit_updates_for_stream(adev->dm.dc,
4043 surface_updates,
4044 1,
4045 acrtc_state->stream,
4046 NULL,
4047 &surface_updates->surface,
4048 state);
e7b07cee
HW		 4049
4050 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
4051 __func__,
4052 addr.address.grph.addr.high_part,
4053 addr.address.grph.addr.low_part);
e7b07cee
HW		 4054}
4055
44d09c6a
HW		 4056/*
4057 * TODO this whole function needs to go
4058 *
4059 * dc_surface_update is needlessly complex. See if we can just replace this
4060 * with a dc_plane_state and follow the atomic model a bit more closely here.
4061 */
4062static bool commit_planes_to_stream(
4063 struct dc *dc,
4064 struct dc_plane_state **plane_states,
4065 uint8_t new_plane_count,
4066 struct dm_crtc_state *dm_new_crtc_state,
4067 struct dm_crtc_state *dm_old_crtc_state,
4068 struct dc_state *state)
4069{
4070 /* no need to dynamically allocate this. it's pretty small */
4071 struct dc_surface_update updates[MAX_SURFACES];
4072 struct dc_flip_addrs *flip_addr;
4073 struct dc_plane_info *plane_info;
4074 struct dc_scaling_info *scaling_info;
4075 int i;
4076 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
4077 struct dc_stream_update *stream_update =
4078 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
4079
4080 if (!stream_update) {
4081 BREAK_TO_DEBUGGER();
4082 return false;
4083 }
4084
4085 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
4086 GFP_KERNEL);
4087 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
4088 GFP_KERNEL);
4089 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
4090 GFP_KERNEL);
4091
4092 if (!flip_addr || !plane_info || !scaling_info) {
4093 kfree(flip_addr);
4094 kfree(plane_info);
4095 kfree(scaling_info);
4096 kfree(stream_update);
4097 return false;
4098 }
4099
4100 memset(updates, 0, sizeof(updates));
4101
4102 stream_update->src = dc_stream->src;
4103 stream_update->dst = dc_stream->dst;
4104 stream_update->out_transfer_func = dc_stream->out_transfer_func;
4105
98e6436d
AK		 4106 if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) {
4107 stream_update->vrr_infopacket = &dc_stream->vrr_infopacket;
4108 stream_update->adjust = &dc_stream->adjust;
4109 }
4110
44d09c6a
HW		 4111 for (i = 0; i < new_plane_count; i++) {
4112 updates[i].surface = plane_states[i];
4113 updates[i].gamma =
4114 (struct dc_gamma *)plane_states[i]->gamma_correction;
4115 updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4116 flip_addr[i].address = plane_states[i]->address;
4117 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4118 plane_info[i].color_space = plane_states[i]->color_space;
44d09c6a
HW		 4119 plane_info[i].format = plane_states[i]->format;
4120 plane_info[i].plane_size = plane_states[i]->plane_size;
4121 plane_info[i].rotation = plane_states[i]->rotation;
4122 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4123 plane_info[i].stereo_format = plane_states[i]->stereo_format;
4124 plane_info[i].tiling_info = plane_states[i]->tiling_info;
4125 plane_info[i].visible = plane_states[i]->visible;
4126 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4127 plane_info[i].dcc = plane_states[i]->dcc;
4128 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4129 scaling_info[i].src_rect = plane_states[i]->src_rect;
4130 scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4131 scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4132
4133 updates[i].flip_addr = &flip_addr[i];
4134 updates[i].plane_info = &plane_info[i];
4135 updates[i].scaling_info = &scaling_info[i];
4136 }
4137
4138 dc_commit_updates_for_stream(
4139 dc,
4140 updates,
4141 new_plane_count,
4142 dc_stream, stream_update, plane_states, state);
4143
4144 kfree(flip_addr);
4145 kfree(plane_info);
4146 kfree(scaling_info);
4147 kfree(stream_update);
4148 return true;
4149}
4150
3be5262e 4151static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 4152 struct drm_device *dev,
4153 struct amdgpu_display_manager *dm,
4154 struct drm_crtc *pcrtc,
4155 bool *wait_for_vblank)
e7b07cee
HW		 4156{
4157 uint32_t i;
4158 struct drm_plane *plane;
0bc9706d 4159 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 4160 struct dc_stream_state *dc_stream_attach;
3be5262e 4161 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 4162 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 4163 struct drm_crtc_state *new_pcrtc_state =
4164 drm_atomic_get_new_crtc_state(state, pcrtc);
4165 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 4166 struct dm_crtc_state *dm_old_crtc_state =
4167 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
bc6828e0 4168 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 4169 int planes_count = 0;
4170 unsigned long flags;
4171
4172 /* update planes when needed */
0bc9706d
LSL		 4173 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4174 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 4175 struct drm_crtc_state *new_crtc_state;
0bc9706d 4176 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 4177 bool pflip_needed;
54d76575 4178 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 4179
4180 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4181 handle_cursor_update(plane, old_plane_state);
4182 continue;
4183 }
4184
f5ba60fe
DD		 4185 if (!fb || !crtc || pcrtc != crtc)
4186 continue;
4187
4188 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4189 if (!new_crtc_state->active)
e7b07cee
HW		 4190 continue;
4191
4192 pflip_needed = !state->allow_modeset;
4193
4194 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4195 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 4196 DRM_ERROR("%s: acrtc %d, already busy\n",
4197 __func__,
4198 acrtc_attach->crtc_id);
b830ebc9 4199 /* In commit tail framework this cannot happen */
e7b07cee
HW		 4200 WARN_ON(1);
4201 }
4202 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4203
a2a330ad 4204 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
54d76575 4205 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 4206
54d76575 4207 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 4208
4209 dc_stream_attach = acrtc_state->stream;
4210 planes_count++;
4211
0bc9706d 4212 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 4213 /* Assume even ONE crtc with immediate flip means
4214 * entire can't wait for VBLANK
4215 * TODO Check if it's correct
4216 */
4217 *wait_for_vblank =
0bc9706d 4218 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 4219 false : true;
4220
4221 /* TODO: Needs rework for multiplane flip */
4222 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4223 drm_crtc_vblank_get(crtc);
4224
4225 amdgpu_dm_do_flip(
4226 crtc,
4227 fb,
23effc11 4228 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
bc6828e0 4229 dm_state->context);
e7b07cee
HW		 4230 }
4231
4232 }
4233
4234 if (planes_count) {
4235 unsigned long flags;
4236
0bc9706d 4237 if (new_pcrtc_state->event) {
e7b07cee
HW		 4238
4239 drm_crtc_vblank_get(pcrtc);
4240
4241 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4242 prepare_flip_isr(acrtc_attach);
4243 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4244 }
4245
98e6436d
AK		 4246 dc_stream_attach->adjust = acrtc_state->adjust;
4247 dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket;
44d09c6a
HW		 4248
4249 if (false == commit_planes_to_stream(dm->dc,
3be5262e
HW		 4250 plane_states_constructed,
4251 planes_count,
44d09c6a
HW		 4252 acrtc_state,
4253 dm_old_crtc_state,
bc6828e0 4254 dm_state->context))
3be5262e 4255 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4256 } else {
4257 /*TODO BUG Here should go disable planes on CRTC. */
4258 }
4259}
4260
27b3f4fc
LSL		 4261/**
4262 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4263 * @crtc_state: the DRM CRTC state
4264 * @stream_state: the DC stream state.
4265 *
4266 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4267 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4268 */
4269static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4270 struct dc_stream_state *stream_state)
4271{
4272 stream_state->mode_changed = crtc_state->mode_changed;
4273}
e7b07cee 4274
7578ecda
AD		 4275static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4276 struct drm_atomic_state *state,
4277 bool nonblock)
e7b07cee
HW		 4278{
4279 struct drm_crtc *crtc;
c2cea706 4280 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4281 struct amdgpu_device *adev = dev->dev_private;
4282 int i;
4283
4284 /*
4285 * We evade vblanks and pflips on crtc that
4286 * should be changed. We do it here to flush & disable
4287 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4288 * it will update crtc->dm_crtc_state->stream pointer which is used in
4289 * the ISRs.
4290 */
c2cea706 4291 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4292 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 4293 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4294
54d76575 4295 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 4296 manage_dm_interrupts(adev, acrtc, false);
4297 }
fc9e9920
S		 4298 /* Add check here for SoC's that support hardware cursor plane, to
4299 * unset legacy_cursor_update */
e7b07cee
HW		 4300
4301 return drm_atomic_helper_commit(dev, state, nonblock);
4302
4303 /*TODO Handle EINTR, reenable IRQ*/
4304}
4305
7578ecda 4306static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4307{
4308 struct drm_device *dev = state->dev;
4309 struct amdgpu_device *adev = dev->dev_private;
4310 struct amdgpu_display_manager *dm = &adev->dm;
4311 struct dm_atomic_state *dm_state;
4312 uint32_t i, j;
5cc6dcbd 4313 struct drm_crtc *crtc;
0bc9706d 4314 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4315 unsigned long flags;
4316 bool wait_for_vblank = true;
4317 struct drm_connector *connector;
c2cea706 4318 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4319 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 4320 int crtc_disable_count = 0;
e7b07cee
HW		 4321
4322 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4323
4324 dm_state = to_dm_atomic_state(state);
4325
4326 /* update changed items */
0bc9706d 4327 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4328 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4329
54d76575
LSL		 4330 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4331 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4332
f1ad2f5e 4333 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4334 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4335 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4336 "connectors_changed:%d\n",
4337 acrtc->crtc_id,
0bc9706d
LSL		 4338 new_crtc_state->enable,
4339 new_crtc_state->active,
4340 new_crtc_state->planes_changed,
4341 new_crtc_state->mode_changed,
4342 new_crtc_state->active_changed,
4343 new_crtc_state->connectors_changed);
e7b07cee 4344
27b3f4fc
LSL		 4345 /* Copy all transient state flags into dc state */
4346 if (dm_new_crtc_state->stream) {
4347 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4348 dm_new_crtc_state->stream);
4349 }
4350
e7b07cee
HW		 4351 /* handles headless hotplug case, updating new_state and
4352 * aconnector as needed
4353 */
4354
54d76575 4355 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4356
f1ad2f5e 4357 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4358
54d76575 4359 if (!dm_new_crtc_state->stream) {
e7b07cee 4360 /*
b830ebc9
HW		 4361 * this could happen because of issues with
4362 * userspace notifications delivery.
4363 * In this case userspace tries to set mode on
4364 * display which is disconnect in fact.
4365 * dc_sink in NULL in this case on aconnector.
4366 * We expect reset mode will come soon.
4367 *
4368 * This can also happen when unplug is done
4369 * during resume sequence ended
4370 *
4371 * In this case, we want to pretend we still
4372 * have a sink to keep the pipe running so that
4373 * hw state is consistent with the sw state
4374 */
f1ad2f5e 4375 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4376 __func__, acrtc->base.base.id);
4377 continue;
4378 }
4379
54d76575
LSL		 4380 if (dm_old_crtc_state->stream)
4381 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 4382
97028037
LP		 4383 pm_runtime_get_noresume(dev->dev);
4384
e7b07cee 4385 acrtc->enabled = true;
0bc9706d
LSL		 4386 acrtc->hw_mode = new_crtc_state->mode;
4387 crtc->hwmode = new_crtc_state->mode;
4388 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4389 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4390
4391 /* i.e. reset mode */
54d76575
LSL		 4392 if (dm_old_crtc_state->stream)
4393 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4394 }
4395 } /* for_each_crtc_in_state() */
4396
fa2123db
ML		 4397 if (dm_state->context) {
4398 dm_enable_per_frame_crtc_master_sync(dm_state->context);
608ac7bb 4399 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
fa2123db 4400 }
e7b07cee 4401
0bc9706d 4402 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4403 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4404
54d76575 4405 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4406
54d76575 4407 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4408 const struct dc_stream_status *status =
54d76575 4409 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4410
4411 if (!status)
54d76575 4412 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4413 else
4414 acrtc->otg_inst = status->primary_otg_inst;
4415 }
4416 }
4417
ebdd27e1 4418 /* Handle scaling and underscan changes*/
c2cea706 4419 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4420 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4421 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4422 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4423 struct dc_stream_status *status = NULL;
4424
44d09c6a 4425 if (acrtc) {
0bc9706d 4426 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 4427 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
4428 }
0bc9706d 4429
e7b07cee 4430 /* Skip any modesets/resets */
0bc9706d 4431 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4432 continue;
4433
4434 /* Skip any thing not scale or underscan changes */
54d76575 4435 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4436 continue;
4437
54d76575 4438 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4439
54d76575
LSL		 4440 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4441 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4442
70e8ffc5
HW		 4443 if (!dm_new_crtc_state->stream)
4444 continue;
4445
54d76575 4446 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4447 WARN_ON(!status);
3be5262e 4448 WARN_ON(!status->plane_count);
e7b07cee 4449
98e6436d
AK		 4450 dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust;
4451 dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket;
4452
e7b07cee 4453 /*TODO How it works with MPO ?*/
44d09c6a 4454 if (!commit_planes_to_stream(
e7b07cee 4455 dm->dc,
3be5262e
HW		 4456 status->plane_states,
4457 status->plane_count,
44d09c6a
HW		 4458 dm_new_crtc_state,
4459 to_dm_crtc_state(old_crtc_state),
bc6828e0 4460 dm_state->context))
e7b07cee
HW		 4461 dm_error("%s: Failed to update stream scaling!\n", __func__);
4462 }
4463
e1fc2dca
LSL		 4464 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4465 new_crtc_state, i) {
e7b07cee
HW		 4466 /*
4467 * loop to enable interrupts on newly arrived crtc
4468 */
e1fc2dca
LSL		 4469 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4470 bool modeset_needed;
b830ebc9 4471
fe2a1965
LP		 4472 if (old_crtc_state->active && !new_crtc_state->active)
4473 crtc_disable_count++;
4474
54d76575 4475 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 4476 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4477 modeset_needed = modeset_required(
4478 new_crtc_state,
4479 dm_new_crtc_state->stream,
4480 dm_old_crtc_state->stream);
4481
4482 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4483 continue;
e7b07cee 4484
e7b07cee
HW		 4485 manage_dm_interrupts(adev, acrtc, true);
4486 }
4487
4488 /* update planes when needed per crtc*/
5cc6dcbd 4489 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4490 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4491
54d76575 4492 if (dm_new_crtc_state->stream)
5cc6dcbd 4493 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4494 }
4495
4496
4497 /*
4498 * send vblank event on all events not handled in flip and
4499 * mark consumed event for drm_atomic_helper_commit_hw_done
4500 */
4501 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4502 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4503
0bc9706d
LSL		 4504 if (new_crtc_state->event)
4505 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4506
0bc9706d 4507 new_crtc_state->event = NULL;
e7b07cee
HW		 4508 }
4509 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4510
4511 /* Signal HW programming completion */
4512 drm_atomic_helper_commit_hw_done(state);
4513
4514 if (wait_for_vblank)
320a1274 4515 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 4516
4517 drm_atomic_helper_cleanup_planes(dev, state);
97028037
LP		 4518
4519 /* Finally, drop a runtime PM reference for each newly disabled CRTC,
4520 * so we can put the GPU into runtime suspend if we're not driving any
4521 * displays anymore
4522 */
fe2a1965
LP		 4523 for (i = 0; i < crtc_disable_count; i++)
4524 pm_runtime_put_autosuspend(dev->dev);
97028037 4525 pm_runtime_mark_last_busy(dev->dev);
e7b07cee
HW		 4526}
4527
4528
4529static int dm_force_atomic_commit(struct drm_connector *connector)
4530{
4531 int ret = 0;
4532 struct drm_device *ddev = connector->dev;
4533 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4534 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4535 struct drm_plane *plane = disconnected_acrtc->base.primary;
4536 struct drm_connector_state *conn_state;
4537 struct drm_crtc_state *crtc_state;
4538 struct drm_plane_state *plane_state;
4539
4540 if (!state)
4541 return -ENOMEM;
4542
4543 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4544
4545 /* Construct an atomic state to restore previous display setting */
4546
4547 /*
4548 * Attach connectors to drm_atomic_state
4549 */
4550 conn_state = drm_atomic_get_connector_state(state, connector);
4551
4552 ret = PTR_ERR_OR_ZERO(conn_state);
4553 if (ret)
4554 goto err;
4555
4556 /* Attach crtc to drm_atomic_state*/
4557 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4558
4559 ret = PTR_ERR_OR_ZERO(crtc_state);
4560 if (ret)
4561 goto err;
4562
4563 /* force a restore */
4564 crtc_state->mode_changed = true;
4565
4566 /* Attach plane to drm_atomic_state */
4567 plane_state = drm_atomic_get_plane_state(state, plane);
4568
4569 ret = PTR_ERR_OR_ZERO(plane_state);
4570 if (ret)
4571 goto err;
4572
4573
4574 /* Call commit internally with the state we just constructed */
4575 ret = drm_atomic_commit(state);
4576 if (!ret)
4577 return 0;
4578
4579err:
4580 DRM_ERROR("Restoring old state failed with %i\n", ret);
4581 drm_atomic_state_put(state);
4582
4583 return ret;
4584}
4585
4586/*
4587 * This functions handle all cases when set mode does not come upon hotplug.
4588 * This include when the same display is unplugged then plugged back into the
4589 * same port and when we are running without usermode desktop manager supprot
4590 */
3ee6b26b
AD		 4591void dm_restore_drm_connector_state(struct drm_device *dev,
4592 struct drm_connector *connector)
e7b07cee 4593{
c84dec2f 4594 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4595 struct amdgpu_crtc *disconnected_acrtc;
4596 struct dm_crtc_state *acrtc_state;
4597
4598 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4599 return;
4600
4601 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 4602 if (!disconnected_acrtc)
4603 return;
e7b07cee 4604
70e8ffc5
HW		 4605 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4606 if (!acrtc_state->stream)
e7b07cee
HW		 4607 return;
4608
4609 /*
4610 * If the previous sink is not released and different from the current,
4611 * we deduce we are in a state where we can not rely on usermode call
4612 * to turn on the display, so we do it here
4613 */
4614 if (acrtc_state->stream->sink != aconnector->dc_sink)
4615 dm_force_atomic_commit(&aconnector->base);
4616}
4617
e7b07cee
HW		 4618/*`
4619 * Grabs all modesetting locks to serialize against any blocking commits,
4620 * Waits for completion of all non blocking commits.
4621 */
3ee6b26b
AD		 4622static int do_aquire_global_lock(struct drm_device *dev,
4623 struct drm_atomic_state *state)
e7b07cee
HW		 4624{
4625 struct drm_crtc *crtc;
4626 struct drm_crtc_commit *commit;
4627 long ret;
4628
4629 /* Adding all modeset locks to aquire_ctx will
4630 * ensure that when the framework release it the
4631 * extra locks we are locking here will get released to
4632 */
4633 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4634 if (ret)
4635 return ret;
4636
4637 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4638 spin_lock(&crtc->commit_lock);
4639 commit = list_first_entry_or_null(&crtc->commit_list,
4640 struct drm_crtc_commit, commit_entry);
4641 if (commit)
4642 drm_crtc_commit_get(commit);
4643 spin_unlock(&crtc->commit_lock);
4644
4645 if (!commit)
4646 continue;
4647
4648 /* Make sure all pending HW programming completed and
4649 * page flips done
4650 */
4651 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4652
4653 if (ret > 0)
4654 ret = wait_for_completion_interruptible_timeout(
4655 &commit->flip_done, 10*HZ);
4656
4657 if (ret == 0)
4658 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4659 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4660
4661 drm_crtc_commit_put(commit);
4662 }
4663
4664 return ret < 0 ? ret : 0;
4665}
4666
98e6436d
AK		 4667void set_freesync_on_stream(struct amdgpu_display_manager *dm,
4668 struct dm_crtc_state *new_crtc_state,
4669 struct dm_connector_state *new_con_state,
4670 struct dc_stream_state *new_stream)
4671{
4672 struct mod_freesync_config config = {0};
4673 struct mod_vrr_params vrr = {0};
4674 struct dc_info_packet vrr_infopacket = {0};
4675 struct amdgpu_dm_connector *aconnector =
4676 to_amdgpu_dm_connector(new_con_state->base.connector);
4677
4678 if (new_con_state->freesync_capable &&
4679 new_con_state->freesync_enable) {
4680 config.state = new_crtc_state->freesync_enabled ?
4681 VRR_STATE_ACTIVE_VARIABLE :
4682 VRR_STATE_INACTIVE;
4683 config.min_refresh_in_uhz =
4684 aconnector->min_vfreq * 1000000;
4685 config.max_refresh_in_uhz =
4686 aconnector->max_vfreq * 1000000;
69ff8845 4687 config.vsif_supported = true;
98e6436d
AK		 4688 }
4689
4690 mod_freesync_build_vrr_params(dm->freesync_module,
4691 new_stream,
4692 &config, &vrr);
4693
4694 mod_freesync_build_vrr_infopacket(dm->freesync_module,
4695 new_stream,
4696 &vrr,
4697 &vrr_infopacket);
4698
4699 new_crtc_state->adjust = vrr.adjust;
4700 new_crtc_state->vrr_infopacket = vrr_infopacket;
4701}
4702
4703static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
3ee6b26b
AD		 4704 struct drm_atomic_state *state,
4705 bool enable,
4706 bool *lock_and_validation_needed)
e7b07cee 4707{
e7b07cee 4708 struct drm_crtc *crtc;
c2cea706 4709 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4710 int i;
54d76575 4711 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4712 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4713 struct dc_stream_state *new_stream;
62f55537 4714 int ret = 0;
d4d4a645 4715
62f55537
AG		 4716 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4717 /* update changed items */
c2cea706 4718 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4719 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4720 struct amdgpu_dm_connector *aconnector = NULL;
a9e8d275
DF		 4721 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
4722 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
f2877656 4723 struct drm_plane_state *new_plane_state = NULL;
e7b07cee 4724
9635b754
DS		 4725 new_stream = NULL;
4726
54d76575
LSL		 4727 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4728 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4729 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4730
f2877656
HW		 4731 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
4732
4733 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
4734 ret = -EINVAL;
4735 goto fail;
4736 }
4737
1daf8c63 4738 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4739
62f55537 4740 /* TODO This hack should go away */
f4ac176e
JZ		 4741 if (aconnector && enable) {
4742 // Make sure fake sink is created in plug-in scenario
a9e8d275 4743 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
c2cea706 4744 &aconnector->base);
a9e8d275
DF		 4745 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
4746 &aconnector->base);
19f89e23 4747
a9e8d275
DF		 4748 if (IS_ERR(drm_new_conn_state)) {
4749 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
62f55537
AG		 4750 break;
4751 }
19f89e23 4752
a9e8d275
DF		 4753 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
4754 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 4755
62f55537 4756 new_stream = create_stream_for_sink(aconnector,
c2cea706 4757 &new_crtc_state->mode,
a9e8d275 4758 dm_new_conn_state);
19f89e23 4759
62f55537
AG		 4760 /*
4761 * we can have no stream on ACTION_SET if a display
4762 * was disconnected during S3, in this case it not and
4763 * error, the OS will be updated after detection, and
4764 * do the right thing on next atomic commit
4765 */
19f89e23 4766
62f55537 4767 if (!new_stream) {
f1ad2f5e 4768 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4769 __func__, acrtc->base.base.id);
4770 break;
19f89e23 4771 }
e7b07cee 4772
98e6436d
AK		 4773 set_freesync_on_stream(dm, dm_new_crtc_state,
4774 dm_new_conn_state, new_stream);
4775
a97599a4
LSL		 4776 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4777 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4778 new_crtc_state->mode_changed = false;
4779 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4780 new_crtc_state->mode_changed);
4781 }
62f55537 4782 }
b830ebc9 4783
98e6436d
AK		 4784 if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled)
4785 new_crtc_state->mode_changed = true;
4786
c2cea706 4787 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4788 goto next_crtc;
e7b07cee 4789
f1ad2f5e 4790 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4791 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4792 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4793 "connectors_changed:%d\n",
4794 acrtc->crtc_id,
c2cea706
LSL		 4795 new_crtc_state->enable,
4796 new_crtc_state->active,
4797 new_crtc_state->planes_changed,
4798 new_crtc_state->mode_changed,
4799 new_crtc_state->active_changed,
4800 new_crtc_state->connectors_changed);
e7b07cee 4801
62f55537
AG		 4802 /* Remove stream for any changed/disabled CRTC */
4803 if (!enable) {
4804
54d76575 4805 if (!dm_old_crtc_state->stream)
9635b754 4806 goto next_crtc;
62f55537 4807
f1ad2f5e 4808 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4809 crtc->base.id);
e7b07cee 4810
1dc90497 4811 /* i.e. reset mode */
62c933f9 4812 if (dc_remove_stream_from_ctx(
98e6436d 4813 dm->dc,
62f55537 4814 dm_state->context,
62c933f9 4815 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4816 ret = -EINVAL;
9635b754 4817 goto fail;
62f55537
AG		 4818 }
4819
54d76575
LSL		 4820 dc_stream_release(dm_old_crtc_state->stream);
4821 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4822
4823 *lock_and_validation_needed = true;
4824
4825 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4826 /*
4827 * Quick fix to prevent NULL pointer on new_stream when
4828 * added MST connectors not found in existing crtc_state in the chained mode
4829 * TODO: need to dig out the root cause of that
4830 */
4831 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4832 goto next_crtc;
62f55537 4833
c2cea706 4834 if (modereset_required(new_crtc_state))
9635b754 4835 goto next_crtc;
62f55537 4836
c2cea706 4837 if (modeset_required(new_crtc_state, new_stream,
54d76575 4838 dm_old_crtc_state->stream)) {
62f55537 4839
54d76575 4840 WARN_ON(dm_new_crtc_state->stream);
62f55537 4841
54d76575 4842 dm_new_crtc_state->stream = new_stream;
27b3f4fc 4843
62f55537
AG		 4844 dc_stream_retain(new_stream);
4845
f1ad2f5e 4846 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4847 crtc->base.id);
1dc90497 4848
13ab1b44 4849 if (dc_add_stream_to_ctx(
98e6436d 4850 dm->dc,
1dc90497 4851 dm_state->context,
13ab1b44 4852 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4853 ret = -EINVAL;
9635b754 4854 goto fail;
1dc90497
AG		 4855 }
4856
62f55537 4857 *lock_and_validation_needed = true;
9b690ef3 4858 }
62f55537 4859 }
9b690ef3 4860
9635b754 4861next_crtc:
62f55537
AG		 4862 /* Release extra reference */
4863 if (new_stream)
4864 dc_stream_release(new_stream);
e277adc5
LSL		 4865
4866 /*
4867 * We want to do dc stream updates that do not require a
4868 * full modeset below.
4869 */
20fa2ff0
LSL		 4870 if (!(enable && aconnector && new_crtc_state->enable &&
4871 new_crtc_state->active))
e277adc5
LSL		 4872 continue;
4873 /*
4874 * Given above conditions, the dc state cannot be NULL because:
20fa2ff0
LSL		 4875 * 1. We're in the process of enabling CRTCs (just been added
4876 * to the dc context, or already is on the context)
4877 * 2. Has a valid connector attached, and
4878 * 3. Is currently active and enabled.
4879 * => The dc stream state currently exists.
e277adc5
LSL		 4880 */
4881 BUG_ON(dm_new_crtc_state->stream == NULL);
4882
a9e8d275
DF		 4883 /* Scaling or underscan settings */
4884 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
4885 update_stream_scaling_settings(
4886 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
4887
bc13f2f8
LSL		 4888 /*
4889 * Color management settings. We also update color properties
4890 * when a modeset is needed, to ensure it gets reprogrammed.
4891 */
4892 if (dm_new_crtc_state->base.color_mgmt_changed ||
4893 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
e277adc5
LSL		 4894 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
4895 if (ret)
4896 goto fail;
4897 amdgpu_dm_set_ctm(dm_new_crtc_state);
4898 }
98e6436d
AK		 4899
4900
62f55537 4901 }
e7b07cee 4902
62f55537 4903 return ret;
9635b754
DS		 4904
4905fail:
4906 if (new_stream)
4907 dc_stream_release(new_stream);
4908 return ret;
62f55537 4909}
9b690ef3 4910
3ee6b26b
AD		 4911static int dm_update_planes_state(struct dc *dc,
4912 struct drm_atomic_state *state,
4913 bool enable,
4914 bool *lock_and_validation_needed)
62f55537
AG		 4915{
4916 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4917 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4918 struct drm_plane *plane;
4919 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4920 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4921 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4922 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4923 int i ;
4924 /* TODO return page_flip_needed() function */
4925 bool pflip_needed = !state->allow_modeset;
4926 int ret = 0;
e7b07cee 4927
9b690ef3 4928
df534fff
S		 4929 /* Add new planes, in reverse order as DC expectation */
4930 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
62f55537
AG		 4931 new_plane_crtc = new_plane_state->crtc;
4932 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4933 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4934 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4935
4936 /*TODO Implement atomic check for cursor plane */
4937 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4938 continue;
9b690ef3 4939
62f55537
AG		 4940 /* Remove any changed/removed planes */
4941 if (!enable) {
a2a330ad
S		 4942 if (pflip_needed &&
4943 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 4944 continue;
a7b06724 4945
62f55537
AG		 4946 if (!old_plane_crtc)
4947 continue;
4948
0bc9706d
LSL		 4949 old_crtc_state = drm_atomic_get_old_crtc_state(
4950 state, old_plane_crtc);
54d76575 4951 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4952
54d76575 4953 if (!dm_old_crtc_state->stream)
62f55537
AG		 4954 continue;
4955
f2877656 4956 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4957 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4958
62f55537
AG		 4959 if (!dc_remove_plane_from_context(
4960 dc,
54d76575
LSL		 4961 dm_old_crtc_state->stream,
4962 dm_old_plane_state->dc_state,
62f55537
AG		 4963 dm_state->context)) {
4964
4965 ret = EINVAL;
4966 return ret;
e7b07cee
HW		 4967 }
4968
9b690ef3 4969
54d76575
LSL		 4970 dc_plane_state_release(dm_old_plane_state->dc_state);
4971 dm_new_plane_state->dc_state = NULL;
1dc90497 4972
62f55537 4973 *lock_and_validation_needed = true;
1dc90497 4974
62f55537 4975 } else { /* Add new planes */
8c45c5db 4976 struct dc_plane_state *dc_new_plane_state;
1dc90497 4977
62f55537
AG		 4978 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4979 continue;
e7b07cee 4980
62f55537
AG		 4981 if (!new_plane_crtc)
4982 continue;
e7b07cee 4983
62f55537 4984 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4985 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4986
54d76575 4987 if (!dm_new_crtc_state->stream)
62f55537
AG		 4988 continue;
4989
a2a330ad
S		 4990 if (pflip_needed &&
4991 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 4992 continue;
62f55537 4993
54d76575 4994 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4995
8c45c5db 4996 dc_new_plane_state = dc_create_plane_state(dc);
d5400aab
LSL		 4997 if (!dc_new_plane_state)
4998 return -ENOMEM;
62f55537 4999
8c45c5db
LSL		 5000 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5001 plane->base.id, new_plane_crtc->base.id);
5002
62f55537
AG		 5003 ret = fill_plane_attributes(
5004 new_plane_crtc->dev->dev_private,
8c45c5db 5005 dc_new_plane_state,
62f55537 5006 new_plane_state,
9817d5f5 5007 new_crtc_state);
8c45c5db
LSL		 5008 if (ret) {
5009 dc_plane_state_release(dc_new_plane_state);
62f55537 5010 return ret;
8c45c5db 5011 }
62f55537 5012
8c45c5db
LSL		 5013 /*
5014 * Any atomic check errors that occur after this will
5015 * not need a release. The plane state will be attached
5016 * to the stream, and therefore part of the atomic
5017 * state. It'll be released when the atomic state is
5018 * cleaned.
5019 */
62f55537
AG		 5020 if (!dc_add_plane_to_context(
5021 dc,
54d76575 5022 dm_new_crtc_state->stream,
8c45c5db 5023 dc_new_plane_state,
62f55537
AG		 5024 dm_state->context)) {
5025
8c45c5db 5026 dc_plane_state_release(dc_new_plane_state);
d5400aab 5027 return -EINVAL;
e7b07cee 5028 }
62f55537 5029
8c45c5db
LSL		 5030 dm_new_plane_state->dc_state = dc_new_plane_state;
5031
000b59ea
LSL		 5032 /* Tell DC to do a full surface update every time there
5033 * is a plane change. Inefficient, but works for now.
5034 */
5035 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5036
62f55537 5037 *lock_and_validation_needed = true;
e7b07cee 5038 }
62f55537 5039 }
e7b07cee
HW		 5040
5041
62f55537
AG		 5042 return ret;
5043}
5044
7578ecda
AD		 5045static int amdgpu_dm_atomic_check(struct drm_device *dev,
5046 struct drm_atomic_state *state)
62f55537 5047{
62f55537
AG		 5048 struct amdgpu_device *adev = dev->dev_private;
5049 struct dc *dc = adev->dm.dc;
5050 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
5051 struct drm_connector *connector;
c2cea706 5052 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 5053 struct drm_crtc *crtc;
fc9e9920 5054 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1e88ad0a 5055 int ret, i;
e7b07cee 5056
62f55537
AG		 5057 /*
5058 * This bool will be set for true for any modeset/reset
5059 * or plane update which implies non fast surface update.
5060 */
5061 bool lock_and_validation_needed = false;
5062
5063 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 5064 if (ret)
5065 goto fail;
62f55537 5066
1e88ad0a 5067 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
98e6436d
AK		 5068 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5069 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5070
1e88ad0a 5071 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d
AK		 5072 !new_crtc_state->color_mgmt_changed &&
5073 (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled))
1e88ad0a 5074 continue;
7bef1af3 5075
1e88ad0a
S		 5076 if (!new_crtc_state->enable)
5077 continue;
fc9e9920 5078
1e88ad0a
S		 5079 ret = drm_atomic_add_affected_connectors(state, crtc);
5080 if (ret)
5081 return ret;
fc9e9920 5082
1e88ad0a
S		 5083 ret = drm_atomic_add_affected_planes(state, crtc);
5084 if (ret)
5085 goto fail;
e7b07cee
HW		 5086 }
5087
62f55537
AG		 5088 dm_state->context = dc_create_state();
5089 ASSERT(dm_state->context);
f36cc577 5090 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 5091
5092 /* Remove exiting planes if they are modified */
5093 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
5094 if (ret) {
5095 goto fail;
5096 }
5097
5098 /* Disable all crtcs which require disable */
98e6436d 5099 ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed);
62f55537
AG		 5100 if (ret) {
5101 goto fail;
5102 }
5103
5104 /* Enable all crtcs which require enable */
98e6436d 5105 ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed);
62f55537
AG		 5106 if (ret) {
5107 goto fail;
5108 }
5109
5110 /* Add new/modified planes */
5111 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
5112 if (ret) {
5113 goto fail;
5114 }
5115
b349f76e
ES		 5116 /* Run this here since we want to validate the streams we created */
5117 ret = drm_atomic_helper_check_planes(dev, state);
5118 if (ret)
5119 goto fail;
62f55537 5120
ebdd27e1 5121 /* Check scaling and underscan changes*/
e7b07cee
HW		 5122 /*TODO Removed scaling changes validation due to inability to commit
5123 * new stream into context w\o causing full reset. Need to
5124 * decide how to handle.
5125 */
c2cea706 5126 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5127 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5128 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5129 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 5130
5131 /* Skip any modesets/resets */
0bc9706d
LSL		 5132 if (!acrtc || drm_atomic_crtc_needs_modeset(
5133 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 5134 continue;
5135
b830ebc9 5136 /* Skip any thing not scale or underscan changes */
54d76575 5137 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 5138 continue;
5139
5140 lock_and_validation_needed = true;
5141 }
5142
e7b07cee
HW		 5143 /*
5144 * For full updates case when
5145 * removing/adding/updating streams on once CRTC while flipping
5146 * on another CRTC,
5147 * acquiring global lock will guarantee that any such full
5148 * update commit
5149 * will wait for completion of any outstanding flip using DRMs
5150 * synchronization events.
5151 */
5152
5153 if (lock_and_validation_needed) {
5154
5155 ret = do_aquire_global_lock(dev, state);
5156 if (ret)
5157 goto fail;
1dc90497 5158
e750d56d 5159 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 5160 ret = -EINVAL;
5161 goto fail;
5162 }
5163 }
5164
5165 /* Must be success */
5166 WARN_ON(ret);
5167 return ret;
5168
5169fail:
5170 if (ret == -EDEADLK)
01e28f9c 5171 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 5172 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 5173 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 5174 else
01e28f9c 5175 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 5176
5177 return ret;
5178}
5179
3ee6b26b
AD		 5180static bool is_dp_capable_without_timing_msa(struct dc *dc,
5181 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 5182{
5183 uint8_t dpcd_data;
5184 bool capable = false;
5185
c84dec2f 5186 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 5187 dm_helpers_dp_read_dpcd(
5188 NULL,
c84dec2f 5189 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 5190 DP_DOWN_STREAM_PORT_COUNT,
5191 &dpcd_data,
5192 sizeof(dpcd_data))) {
5193 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
5194 }
5195
5196 return capable;
5197}
98e6436d
AK		 5198void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
5199 struct edid *edid)
e7b07cee
HW		 5200{
5201 int i;
e7b07cee
HW		 5202 bool edid_check_required;
5203 struct detailed_timing *timing;
5204 struct detailed_non_pixel *data;
5205 struct detailed_data_monitor_range *range;
c84dec2f
HW		 5206 struct amdgpu_dm_connector *amdgpu_dm_connector =
5207 to_amdgpu_dm_connector(connector);
8218d7f1 5208 struct dm_connector_state *dm_con_state;
e7b07cee
HW		 5209
5210 struct drm_device *dev = connector->dev;
5211 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 5212
8218d7f1
HW		 5213 if (!connector->state) {
5214 DRM_ERROR("%s - Connector has no state", __func__);
5215 return;
5216 }
5217
98e6436d
AK		 5218 if (!edid) {
5219 dm_con_state = to_dm_connector_state(connector->state);
5220
5221 amdgpu_dm_connector->min_vfreq = 0;
5222 amdgpu_dm_connector->max_vfreq = 0;
5223 amdgpu_dm_connector->pixel_clock_mhz = 0;
5224
5225 dm_con_state->freesync_capable = false;
5226 dm_con_state->freesync_enable = false;
5227 return;
5228 }
5229
8218d7f1
HW		 5230 dm_con_state = to_dm_connector_state(connector->state);
5231
e7b07cee 5232 edid_check_required = false;
c84dec2f 5233 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 5234 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
5235 return;
5236 }
5237 if (!adev->dm.freesync_module)
5238 return;
5239 /*
5240 * if edid non zero restrict freesync only for dp and edp
5241 */
5242 if (edid) {
c84dec2f
HW		 5243 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
5244 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 5245 edid_check_required = is_dp_capable_without_timing_msa(
5246 adev->dm.dc,
c84dec2f 5247 amdgpu_dm_connector);
e7b07cee
HW		 5248 }
5249 }
8218d7f1 5250 dm_con_state->freesync_capable = false;
e7b07cee
HW		 5251 if (edid_check_required == true && (edid->version > 1 ||
5252 (edid->version == 1 && edid->revision > 1))) {
5253 for (i = 0; i < 4; i++) {
5254
5255 timing = &edid->detailed_timings[i];
5256 data = &timing->data.other_data;
5257 range = &data->data.range;
5258 /*
5259 * Check if monitor has continuous frequency mode
5260 */
5261 if (data->type != EDID_DETAIL_MONITOR_RANGE)
5262 continue;
5263 /*
5264 * Check for flag range limits only. If flag == 1 then
5265 * no additional timing information provided.
5266 * Default GTF, GTF Secondary curve and CVT are not
5267 * supported
5268 */
5269 if (range->flags != 1)
5270 continue;
5271
c84dec2f
HW		 5272 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
5273 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
5274 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 5275 range->pixel_clock_mhz * 10;
5276 break;
5277 }
5278
c84dec2f 5279 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 5280 amdgpu_dm_connector->min_vfreq > 10) {
5281
8218d7f1 5282 dm_con_state->freesync_capable = true;
e7b07cee
HW		 5283 }
5284 }
e7b07cee
HW		 5285}
5286
Linux 6.x block layer and io_uring tree(s)