Commit | Line | Data |
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4562236b HW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
0cf5eb76 DF |
26 | /* The caprices of the preprocessor require that this be declared right here */ |
27 | #define CREATE_TRACE_POINTS | |
28 | ||
4562236b HW |
29 | #include "dm_services_types.h" |
30 | #include "dc.h" | |
f6e03f80 | 31 | #include "link_enc_cfg.h" |
1dc90497 | 32 | #include "dc/inc/core_types.h" |
a7669aff | 33 | #include "dal_asic_id.h" |
cdca3f21 | 34 | #include "dmub/dmub_srv.h" |
743b9786 NK |
35 | #include "dc/inc/hw/dmcu.h" |
36 | #include "dc/inc/hw/abm.h" | |
9a71c7d3 | 37 | #include "dc/dc_dmub_srv.h" |
f9b4f20c | 38 | #include "dc/dc_edid_parser.h" |
81927e28 | 39 | #include "dc/dc_stat.h" |
9d83722d | 40 | #include "amdgpu_dm_trace.h" |
028c4ccf | 41 | #include "dpcd_defs.h" |
bc33f5e5 | 42 | #include "link/protocols/link_dpcd.h" |
028c4ccf | 43 | #include "link_service_types.h" |
1e5d4d8e RL |
44 | #include "link/protocols/link_dp_capability.h" |
45 | #include "link/protocols/link_ddc.h" | |
4562236b HW |
46 | |
47 | #include "vid.h" | |
48 | #include "amdgpu.h" | |
a49dcb88 | 49 | #include "amdgpu_display.h" |
a94d5569 | 50 | #include "amdgpu_ucode.h" |
4562236b HW |
51 | #include "atom.h" |
52 | #include "amdgpu_dm.h" | |
5d945cbc | 53 | #include "amdgpu_dm_plane.h" |
473683a0 | 54 | #include "amdgpu_dm_crtc.h" |
52704fca | 55 | #include "amdgpu_dm_hdcp.h" |
6a99099f | 56 | #include <drm/display/drm_hdcp_helper.h> |
dfc03588 | 57 | #include "amdgpu_dm_wb.h" |
e7b07cee | 58 | #include "amdgpu_pm.h" |
1f579254 | 59 | #include "amdgpu_atombios.h" |
4562236b HW |
60 | |
61 | #include "amd_shared.h" | |
62 | #include "amdgpu_dm_irq.h" | |
63 | #include "dm_helpers.h" | |
e7b07cee | 64 | #include "amdgpu_dm_mst_types.h" |
dc38fd9d DF |
65 | #if defined(CONFIG_DEBUG_FS) |
66 | #include "amdgpu_dm_debugfs.h" | |
67 | #endif | |
f4594cd1 | 68 | #include "amdgpu_dm_psr.h" |
44e60b14 | 69 | #include "amdgpu_dm_replay.h" |
4562236b HW |
70 | |
71 | #include "ivsrcid/ivsrcid_vislands30.h" | |
72 | ||
a6276e92 | 73 | #include <linux/backlight.h> |
4562236b HW |
74 | #include <linux/module.h> |
75 | #include <linux/moduleparam.h> | |
e7b07cee | 76 | #include <linux/types.h> |
97028037 | 77 | #include <linux/pm_runtime.h> |
09d21852 | 78 | #include <linux/pci.h> |
a94d5569 | 79 | #include <linux/firmware.h> |
6ce8f316 | 80 | #include <linux/component.h> |
57b9f338 | 81 | #include <linux/dmi.h> |
4562236b | 82 | |
da68386d | 83 | #include <drm/display/drm_dp_mst_helper.h> |
4fc8cb47 | 84 | #include <drm/display/drm_hdmi_helper.h> |
4562236b | 85 | #include <drm/drm_atomic.h> |
674e78ac | 86 | #include <drm/drm_atomic_uapi.h> |
4562236b | 87 | #include <drm/drm_atomic_helper.h> |
90bb087f | 88 | #include <drm/drm_blend.h> |
191dc439 | 89 | #include <drm/drm_fixed.h> |
09d21852 | 90 | #include <drm/drm_fourcc.h> |
e7b07cee | 91 | #include <drm/drm_edid.h> |
439590ac | 92 | #include <drm/drm_eld.h> |
09d21852 | 93 | #include <drm/drm_vblank.h> |
6ce8f316 | 94 | #include <drm/drm_audio_component.h> |
047de3f1 | 95 | #include <drm/drm_gem_atomic_helper.h> |
30c63715 | 96 | #include <drm/drm_plane_helper.h> |
4562236b | 97 | |
da11ef83 HG |
98 | #include <acpi/video.h> |
99 | ||
5527cd06 | 100 | #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" |
ff5ef992 | 101 | |
ad941f7a FX |
102 | #include "dcn/dcn_1_0_offset.h" |
103 | #include "dcn/dcn_1_0_sh_mask.h" | |
407e7517 | 104 | #include "soc15_hw_ip.h" |
543036a2 | 105 | #include "soc15_common.h" |
407e7517 | 106 | #include "vega10_ip_offset.h" |
ff5ef992 | 107 | |
543036a2 AP |
108 | #include "gc/gc_11_0_0_offset.h" |
109 | #include "gc/gc_11_0_0_sh_mask.h" | |
110 | ||
e7b07cee | 111 | #include "modules/inc/mod_freesync.h" |
bbf854dc | 112 | #include "modules/power/power_helpers.h" |
e7b07cee | 113 | |
743b9786 NK |
114 | #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" |
115 | MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); | |
79037324 BL |
116 | #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" |
117 | MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); | |
5ce868fc BL |
118 | #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" |
119 | MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); | |
71c0fd92 RL |
120 | #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" |
121 | MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); | |
469989ca RL |
122 | #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" |
123 | MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); | |
2a411205 BL |
124 | #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" |
125 | MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); | |
656fe9b6 AP |
126 | #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" |
127 | MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); | |
1ebcaebd NK |
128 | #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" |
129 | MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); | |
e850f6b1 RL |
130 | #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" |
131 | MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); | |
b5b8ed44 QZ |
132 | #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" |
133 | MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); | |
de7cc1b4 PL |
134 | #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" |
135 | MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); | |
2200eb9e | 136 | |
577359ca AP |
137 | #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" |
138 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); | |
139 | #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" | |
140 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); | |
141 | ||
a94d5569 DF |
142 | #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" |
143 | MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); | |
e7b07cee | 144 | |
5ea23931 RL |
145 | #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" |
146 | MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); | |
147 | ||
06b1661e QZ |
148 | #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin" |
149 | MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB); | |
150 | ||
8c7aea40 NK |
151 | /* Number of bytes in PSP header for firmware. */ |
152 | #define PSP_HEADER_BYTES 0x100 | |
153 | ||
154 | /* Number of bytes in PSP footer for firmware. */ | |
155 | #define PSP_FOOTER_BYTES 0x100 | |
156 | ||
b8592b48 LL |
157 | /** |
158 | * DOC: overview | |
159 | * | |
160 | * The AMDgpu display manager, **amdgpu_dm** (or even simpler, | |
ec5c0ffa | 161 | * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM |
b8592b48 LL |
162 | * requests into DC requests, and DC responses into DRM responses. |
163 | * | |
164 | * The root control structure is &struct amdgpu_display_manager. | |
165 | */ | |
166 | ||
7578ecda AD |
167 | /* basic init/fini API */ |
168 | static int amdgpu_dm_init(struct amdgpu_device *adev); | |
169 | static void amdgpu_dm_fini(struct amdgpu_device *adev); | |
fe8858bb | 170 | static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); |
7578ecda | 171 | |
0f877894 OV |
172 | static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) |
173 | { | |
174 | switch (link->dpcd_caps.dongle_type) { | |
175 | case DISPLAY_DONGLE_NONE: | |
176 | return DRM_MODE_SUBCONNECTOR_Native; | |
177 | case DISPLAY_DONGLE_DP_VGA_CONVERTER: | |
178 | return DRM_MODE_SUBCONNECTOR_VGA; | |
179 | case DISPLAY_DONGLE_DP_DVI_CONVERTER: | |
180 | case DISPLAY_DONGLE_DP_DVI_DONGLE: | |
181 | return DRM_MODE_SUBCONNECTOR_DVID; | |
182 | case DISPLAY_DONGLE_DP_HDMI_CONVERTER: | |
183 | case DISPLAY_DONGLE_DP_HDMI_DONGLE: | |
184 | return DRM_MODE_SUBCONNECTOR_HDMIA; | |
185 | case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: | |
186 | default: | |
187 | return DRM_MODE_SUBCONNECTOR_Unknown; | |
188 | } | |
189 | } | |
190 | ||
191 | static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) | |
192 | { | |
193 | struct dc_link *link = aconnector->dc_link; | |
194 | struct drm_connector *connector = &aconnector->base; | |
195 | enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; | |
196 | ||
197 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
198 | return; | |
199 | ||
200 | if (aconnector->dc_sink) | |
201 | subconnector = get_subconnector_type(link); | |
202 | ||
203 | drm_object_property_set_value(&connector->base, | |
204 | connector->dev->mode_config.dp_subconnector_property, | |
205 | subconnector); | |
206 | } | |
207 | ||
1f6010a9 DF |
208 | /* |
209 | * initializes drm_device display related structures, based on the information | |
7578ecda AD |
210 | * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, |
211 | * drm_encoder, drm_mode_config | |
212 | * | |
213 | * Returns 0 on success | |
214 | */ | |
215 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); | |
216 | /* removes and deallocates the drm structures, created by the above function */ | |
217 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); | |
218 | ||
7578ecda AD |
219 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
220 | struct amdgpu_dm_connector *amdgpu_dm_connector, | |
ae67558b | 221 | u32 link_index, |
7578ecda AD |
222 | struct amdgpu_encoder *amdgpu_encoder); |
223 | static int amdgpu_dm_encoder_init(struct drm_device *dev, | |
224 | struct amdgpu_encoder *aencoder, | |
225 | uint32_t link_index); | |
226 | ||
227 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); | |
228 | ||
7578ecda AD |
229 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); |
230 | ||
231 | static int amdgpu_dm_atomic_check(struct drm_device *dev, | |
232 | struct drm_atomic_state *state); | |
233 | ||
e27c41d5 | 234 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); |
c40a09e5 | 235 | static void handle_hpd_rx_irq(void *param); |
e27c41d5 | 236 | |
a85ba005 NC |
237 | static bool |
238 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, | |
239 | struct drm_crtc_state *new_crtc_state); | |
4562236b HW |
240 | /* |
241 | * dm_vblank_get_counter | |
242 | * | |
243 | * @brief | |
244 | * Get counter for number of vertical blanks | |
245 | * | |
246 | * @param | |
247 | * struct amdgpu_device *adev - [in] desired amdgpu device | |
248 | * int disp_idx - [in] which CRTC to get the counter from | |
249 | * | |
250 | * @return | |
251 | * Counter for vertical blanks | |
252 | */ | |
253 | static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) | |
254 | { | |
53e1db06 SS |
255 | struct amdgpu_crtc *acrtc = NULL; |
256 | ||
4562236b HW |
257 | if (crtc >= adev->mode_info.num_crtc) |
258 | return 0; | |
4562236b | 259 | |
53e1db06 | 260 | acrtc = adev->mode_info.crtcs[crtc]; |
4562236b | 261 | |
53e1db06 SS |
262 | if (!acrtc->dm_irq_params.stream) { |
263 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", | |
264 | crtc); | |
265 | return 0; | |
4562236b | 266 | } |
53e1db06 SS |
267 | |
268 | return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); | |
4562236b HW |
269 | } |
270 | ||
271 | static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, | |
3ee6b26b | 272 | u32 *vbl, u32 *position) |
4562236b | 273 | { |
ae67558b | 274 | u32 v_blank_start, v_blank_end, h_position, v_position; |
0c2d77be | 275 | struct amdgpu_crtc *acrtc = NULL; |
81c50963 | 276 | |
4562236b HW |
277 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
278 | return -EINVAL; | |
4562236b | 279 | |
0c2d77be | 280 | acrtc = adev->mode_info.crtcs[crtc]; |
4562236b | 281 | |
0c2d77be SS |
282 | if (!acrtc->dm_irq_params.stream) { |
283 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", | |
284 | crtc); | |
285 | return 0; | |
4562236b HW |
286 | } |
287 | ||
0c2d77be SS |
288 | /* |
289 | * TODO rework base driver to use values directly. | |
290 | * for now parse it back into reg-format | |
291 | */ | |
292 | dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, | |
293 | &v_blank_start, | |
294 | &v_blank_end, | |
295 | &h_position, | |
296 | &v_position); | |
297 | ||
298 | *position = v_position | (h_position << 16); | |
299 | *vbl = v_blank_start | (v_blank_end << 16); | |
300 | ||
4562236b HW |
301 | return 0; |
302 | } | |
303 | ||
304 | static bool dm_is_idle(void *handle) | |
305 | { | |
306 | /* XXX todo */ | |
307 | return true; | |
308 | } | |
309 | ||
310 | static int dm_wait_for_idle(void *handle) | |
311 | { | |
312 | /* XXX todo */ | |
313 | return 0; | |
314 | } | |
315 | ||
316 | static bool dm_check_soft_reset(void *handle) | |
317 | { | |
318 | return false; | |
319 | } | |
320 | ||
321 | static int dm_soft_reset(void *handle) | |
322 | { | |
323 | /* XXX todo */ | |
324 | return 0; | |
325 | } | |
326 | ||
3ee6b26b AD |
327 | static struct amdgpu_crtc * |
328 | get_crtc_by_otg_inst(struct amdgpu_device *adev, | |
329 | int otg_inst) | |
4562236b | 330 | { |
4a580877 | 331 | struct drm_device *dev = adev_to_drm(adev); |
4562236b HW |
332 | struct drm_crtc *crtc; |
333 | struct amdgpu_crtc *amdgpu_crtc; | |
334 | ||
bcd74374 | 335 | if (WARN_ON(otg_inst == -1)) |
4562236b | 336 | return adev->mode_info.crtcs[0]; |
4562236b HW |
337 | |
338 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
339 | amdgpu_crtc = to_amdgpu_crtc(crtc); | |
340 | ||
341 | if (amdgpu_crtc->otg_inst == otg_inst) | |
342 | return amdgpu_crtc; | |
343 | } | |
344 | ||
345 | return NULL; | |
346 | } | |
347 | ||
a85ba005 NC |
348 | static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, |
349 | struct dm_crtc_state *new_state) | |
350 | { | |
351 | if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) | |
352 | return true; | |
6c5e25a0 | 353 | else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) |
a85ba005 NC |
354 | return true; |
355 | else | |
356 | return false; | |
357 | } | |
358 | ||
bb46a6a9 RS |
359 | static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, |
360 | int planes_count) | |
361 | { | |
362 | int i, j; | |
bb46a6a9 | 363 | |
8866d627 JC |
364 | for (i = 0, j = planes_count - 1; i < j; i++, j--) |
365 | swap(array_of_surface_update[i], array_of_surface_update[j]); | |
bb46a6a9 RS |
366 | } |
367 | ||
81f743a0 RS |
368 | /** |
369 | * update_planes_and_stream_adapter() - Send planes to be updated in DC | |
370 | * | |
371 | * DC has a generic way to update planes and stream via | |
372 | * dc_update_planes_and_stream function; however, DM might need some | |
373 | * adjustments and preparation before calling it. This function is a wrapper | |
374 | * for the dc_update_planes_and_stream that does any required configuration | |
375 | * before passing control to DC. | |
21d81681 SS |
376 | * |
377 | * @dc: Display Core control structure | |
378 | * @update_type: specify whether it is FULL/MEDIUM/FAST update | |
379 | * @planes_count: planes count to update | |
380 | * @stream: stream state | |
381 | * @stream_update: stream update | |
382 | * @array_of_surface_update: dc surface update pointer | |
383 | * | |
81f743a0 RS |
384 | */ |
385 | static inline bool update_planes_and_stream_adapter(struct dc *dc, | |
386 | int update_type, | |
387 | int planes_count, | |
388 | struct dc_stream_state *stream, | |
389 | struct dc_stream_update *stream_update, | |
390 | struct dc_surface_update *array_of_surface_update) | |
391 | { | |
bb46a6a9 RS |
392 | reverse_planes_order(array_of_surface_update, planes_count); |
393 | ||
81f743a0 RS |
394 | /* |
395 | * Previous frame finished and HW is ready for optimization. | |
396 | */ | |
397 | if (update_type == UPDATE_TYPE_FAST) | |
398 | dc_post_update_surfaces_to_stream(dc); | |
399 | ||
400 | return dc_update_planes_and_stream(dc, | |
401 | array_of_surface_update, | |
402 | planes_count, | |
403 | stream, | |
404 | stream_update); | |
405 | } | |
406 | ||
b8e8c934 HW |
407 | /** |
408 | * dm_pflip_high_irq() - Handle pageflip interrupt | |
409 | * @interrupt_params: ignored | |
410 | * | |
411 | * Handles the pageflip interrupt by notifying all interested parties | |
412 | * that the pageflip has been completed. | |
413 | */ | |
4562236b HW |
414 | static void dm_pflip_high_irq(void *interrupt_params) |
415 | { | |
4562236b HW |
416 | struct amdgpu_crtc *amdgpu_crtc; |
417 | struct common_irq_params *irq_params = interrupt_params; | |
418 | struct amdgpu_device *adev = irq_params->adev; | |
5d72e247 | 419 | struct drm_device *dev = adev_to_drm(adev); |
4562236b | 420 | unsigned long flags; |
71bbe51a | 421 | struct drm_pending_vblank_event *e; |
ae67558b | 422 | u32 vpos, hpos, v_blank_start, v_blank_end; |
71bbe51a | 423 | bool vrr_active; |
4562236b HW |
424 | |
425 | amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); | |
426 | ||
427 | /* IRQ could occur when in initial stage */ | |
1f6010a9 | 428 | /* TODO work and BO cleanup */ |
4562236b | 429 | if (amdgpu_crtc == NULL) { |
5d72e247 | 430 | drm_dbg_state(dev, "CRTC is null, returning.\n"); |
4562236b HW |
431 | return; |
432 | } | |
433 | ||
4a580877 | 434 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
4562236b | 435 | |
c82eddf8 | 436 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { |
5d72e247 HM |
437 | drm_dbg_state(dev, |
438 | "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", | |
439 | amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, | |
440 | amdgpu_crtc->crtc_id, amdgpu_crtc); | |
4a580877 | 441 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
4562236b HW |
442 | return; |
443 | } | |
444 | ||
71bbe51a MK |
445 | /* page flip completed. */ |
446 | e = amdgpu_crtc->event; | |
447 | amdgpu_crtc->event = NULL; | |
4562236b | 448 | |
bcd74374 | 449 | WARN_ON(!e); |
1159898a | 450 | |
6c5e25a0 | 451 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); |
71bbe51a MK |
452 | |
453 | /* Fixed refresh rate, or VRR scanout position outside front-porch? */ | |
454 | if (!vrr_active || | |
585d450c | 455 | !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, |
71bbe51a MK |
456 | &v_blank_end, &hpos, &vpos) || |
457 | (vpos < v_blank_start)) { | |
458 | /* Update to correct count and vblank timestamp if racing with | |
459 | * vblank irq. This also updates to the correct vblank timestamp | |
460 | * even in VRR mode, as scanout is past the front-porch atm. | |
461 | */ | |
462 | drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); | |
1159898a | 463 | |
71bbe51a MK |
464 | /* Wake up userspace by sending the pageflip event with proper |
465 | * count and timestamp of vblank of flip completion. | |
466 | */ | |
467 | if (e) { | |
468 | drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); | |
469 | ||
470 | /* Event sent, so done with vblank for this flip */ | |
471 | drm_crtc_vblank_put(&amdgpu_crtc->base); | |
472 | } | |
473 | } else if (e) { | |
474 | /* VRR active and inside front-porch: vblank count and | |
475 | * timestamp for pageflip event will only be up to date after | |
476 | * drm_crtc_handle_vblank() has been executed from late vblank | |
477 | * irq handler after start of back-porch (vline 0). We queue the | |
478 | * pageflip event for send-out by drm_crtc_handle_vblank() with | |
479 | * updated timestamp and count, once it runs after us. | |
480 | * | |
481 | * We need to open-code this instead of using the helper | |
482 | * drm_crtc_arm_vblank_event(), as that helper would | |
483 | * call drm_crtc_accurate_vblank_count(), which we must | |
484 | * not call in VRR mode while we are in front-porch! | |
485 | */ | |
486 | ||
487 | /* sequence will be replaced by real count during send-out. */ | |
488 | e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); | |
489 | e->pipe = amdgpu_crtc->crtc_id; | |
490 | ||
4a580877 | 491 | list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); |
71bbe51a MK |
492 | e = NULL; |
493 | } | |
4562236b | 494 | |
fdd1fe57 MK |
495 | /* Keep track of vblank of this flip for flip throttling. We use the |
496 | * cooked hw counter, as that one incremented at start of this vblank | |
497 | * of pageflip completion, so last_flip_vblank is the forbidden count | |
498 | * for queueing new pageflips if vsync + VRR is enabled. | |
499 | */ | |
5d1c59c4 | 500 | amdgpu_crtc->dm_irq_params.last_flip_vblank = |
e3eff4b5 | 501 | amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); |
fdd1fe57 | 502 | |
54f5499a | 503 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; |
4a580877 | 504 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
4562236b | 505 | |
5d72e247 HM |
506 | drm_dbg_state(dev, |
507 | "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", | |
508 | amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e); | |
4562236b HW |
509 | } |
510 | ||
d2574c33 MK |
511 | static void dm_vupdate_high_irq(void *interrupt_params) |
512 | { | |
513 | struct common_irq_params *irq_params = interrupt_params; | |
514 | struct amdgpu_device *adev = irq_params->adev; | |
515 | struct amdgpu_crtc *acrtc; | |
47588233 RS |
516 | struct drm_device *drm_dev; |
517 | struct drm_vblank_crtc *vblank; | |
518 | ktime_t frame_duration_ns, previous_timestamp; | |
09aef2c4 | 519 | unsigned long flags; |
585d450c | 520 | int vrr_active; |
d2574c33 MK |
521 | |
522 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); | |
523 | ||
524 | if (acrtc) { | |
6c5e25a0 | 525 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
47588233 RS |
526 | drm_dev = acrtc->base.dev; |
527 | vblank = &drm_dev->vblank[acrtc->base.index]; | |
528 | previous_timestamp = atomic64_read(&irq_params->previous_timestamp); | |
529 | frame_duration_ns = vblank->time - previous_timestamp; | |
530 | ||
531 | if (frame_duration_ns > 0) { | |
532 | trace_amdgpu_refresh_rate_track(acrtc->base.index, | |
533 | frame_duration_ns, | |
534 | ktime_divns(NSEC_PER_SEC, frame_duration_ns)); | |
535 | atomic64_set(&irq_params->previous_timestamp, vblank->time); | |
536 | } | |
d2574c33 | 537 | |
5d72e247 HM |
538 | drm_dbg_vbl(drm_dev, |
539 | "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, | |
540 | vrr_active); | |
d2574c33 MK |
541 | |
542 | /* Core vblank handling is done here after end of front-porch in | |
543 | * vrr mode, as vblank timestamping will give valid results | |
544 | * while now done after front-porch. This will also deliver | |
545 | * page-flip completion events that have been queued to us | |
546 | * if a pageflip happened inside front-porch. | |
547 | */ | |
585d450c | 548 | if (vrr_active) { |
6c5e25a0 | 549 | amdgpu_dm_crtc_handle_vblank(acrtc); |
09aef2c4 MK |
550 | |
551 | /* BTR processing for pre-DCE12 ASICs */ | |
585d450c | 552 | if (acrtc->dm_irq_params.stream && |
09aef2c4 | 553 | adev->family < AMDGPU_FAMILY_AI) { |
4a580877 | 554 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
09aef2c4 MK |
555 | mod_freesync_handle_v_update( |
556 | adev->dm.freesync_module, | |
585d450c AP |
557 | acrtc->dm_irq_params.stream, |
558 | &acrtc->dm_irq_params.vrr_params); | |
09aef2c4 MK |
559 | |
560 | dc_stream_adjust_vmin_vmax( | |
561 | adev->dm.dc, | |
585d450c AP |
562 | acrtc->dm_irq_params.stream, |
563 | &acrtc->dm_irq_params.vrr_params.adjust); | |
4a580877 | 564 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
09aef2c4 MK |
565 | } |
566 | } | |
d2574c33 MK |
567 | } |
568 | } | |
569 | ||
b8e8c934 HW |
570 | /** |
571 | * dm_crtc_high_irq() - Handles CRTC interrupt | |
2346ef47 | 572 | * @interrupt_params: used for determining the CRTC instance |
b8e8c934 HW |
573 | * |
574 | * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK | |
575 | * event handler. | |
576 | */ | |
4562236b HW |
577 | static void dm_crtc_high_irq(void *interrupt_params) |
578 | { | |
579 | struct common_irq_params *irq_params = interrupt_params; | |
580 | struct amdgpu_device *adev = irq_params->adev; | |
c81e13b9 | 581 | struct drm_writeback_job *job; |
4562236b | 582 | struct amdgpu_crtc *acrtc; |
09aef2c4 | 583 | unsigned long flags; |
585d450c | 584 | int vrr_active; |
4562236b | 585 | |
b57de80a | 586 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); |
16f17eda LL |
587 | if (!acrtc) |
588 | return; | |
589 | ||
c81e13b9 AH |
590 | if (acrtc->wb_pending) { |
591 | if (acrtc->wb_conn) { | |
592 | spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); | |
593 | job = list_first_entry_or_null(&acrtc->wb_conn->job_queue, | |
594 | struct drm_writeback_job, | |
595 | list_entry); | |
596 | spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); | |
597 | ||
87ce0e62 AH |
598 | if (job) { |
599 | unsigned int v_total, refresh_hz; | |
600 | struct dc_stream_state *stream = acrtc->dm_irq_params.stream; | |
601 | ||
602 | v_total = stream->adjust.v_total_max ? | |
603 | stream->adjust.v_total_max : stream->timing.v_total; | |
604 | refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz * | |
605 | 100LL, (v_total * stream->timing.h_total)); | |
606 | mdelay(1000 / refresh_hz); | |
607 | ||
c81e13b9 | 608 | drm_writeback_signal_completion(acrtc->wb_conn, 0); |
87ce0e62 AH |
609 | dc_stream_fc_disable_writeback(adev->dm.dc, |
610 | acrtc->dm_irq_params.stream, 0); | |
611 | } | |
c81e13b9 AH |
612 | } else |
613 | DRM_ERROR("%s: no amdgpu_crtc wb_conn\n", __func__); | |
614 | acrtc->wb_pending = false; | |
615 | } | |
616 | ||
6c5e25a0 | 617 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
16f17eda | 618 | |
5d72e247 HM |
619 | drm_dbg_vbl(adev_to_drm(adev), |
620 | "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, | |
621 | vrr_active, acrtc->dm_irq_params.active_planes); | |
16f17eda | 622 | |
2346ef47 NK |
623 | /** |
624 | * Core vblank handling at start of front-porch is only possible | |
625 | * in non-vrr mode, as only there vblank timestamping will give | |
626 | * valid results while done in front-porch. Otherwise defer it | |
627 | * to dm_vupdate_high_irq after end of front-porch. | |
628 | */ | |
585d450c | 629 | if (!vrr_active) |
6c5e25a0 | 630 | amdgpu_dm_crtc_handle_vblank(acrtc); |
2346ef47 NK |
631 | |
632 | /** | |
633 | * Following stuff must happen at start of vblank, for crc | |
634 | * computation and below-the-range btr support in vrr mode. | |
635 | */ | |
16f17eda | 636 | amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); |
2346ef47 NK |
637 | |
638 | /* BTR updates need to happen before VUPDATE on Vega and above. */ | |
639 | if (adev->family < AMDGPU_FAMILY_AI) | |
640 | return; | |
16f17eda | 641 | |
4a580877 | 642 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
16f17eda | 643 | |
585d450c AP |
644 | if (acrtc->dm_irq_params.stream && |
645 | acrtc->dm_irq_params.vrr_params.supported && | |
646 | acrtc->dm_irq_params.freesync_config.state == | |
647 | VRR_STATE_ACTIVE_VARIABLE) { | |
2346ef47 | 648 | mod_freesync_handle_v_update(adev->dm.freesync_module, |
585d450c AP |
649 | acrtc->dm_irq_params.stream, |
650 | &acrtc->dm_irq_params.vrr_params); | |
16f17eda | 651 | |
585d450c AP |
652 | dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, |
653 | &acrtc->dm_irq_params.vrr_params.adjust); | |
16f17eda LL |
654 | } |
655 | ||
2b5aed9a MK |
656 | /* |
657 | * If there aren't any active_planes then DCH HUBP may be clock-gated. | |
658 | * In that case, pageflip completion interrupts won't fire and pageflip | |
659 | * completion events won't get delivered. Prevent this by sending | |
660 | * pending pageflip events from here if a flip is still pending. | |
661 | * | |
662 | * If any planes are enabled, use dm_pflip_high_irq() instead, to | |
663 | * avoid race conditions between flip programming and completion, | |
664 | * which could cause too early flip completion events. | |
665 | */ | |
2346ef47 NK |
666 | if (adev->family >= AMDGPU_FAMILY_RV && |
667 | acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && | |
585d450c | 668 | acrtc->dm_irq_params.active_planes == 0) { |
16f17eda LL |
669 | if (acrtc->event) { |
670 | drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); | |
671 | acrtc->event = NULL; | |
672 | drm_crtc_vblank_put(&acrtc->base); | |
673 | } | |
674 | acrtc->pflip_status = AMDGPU_FLIP_NONE; | |
675 | } | |
676 | ||
4a580877 | 677 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
16f17eda LL |
678 | } |
679 | ||
9e1178ef | 680 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
86bc2219 WL |
681 | /** |
682 | * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for | |
683 | * DCN generation ASICs | |
48e01bf4 | 684 | * @interrupt_params: interrupt parameters |
86bc2219 WL |
685 | * |
686 | * Used to set crc window/read out crc value at vertical line 0 position | |
687 | */ | |
86bc2219 WL |
688 | static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) |
689 | { | |
690 | struct common_irq_params *irq_params = interrupt_params; | |
691 | struct amdgpu_device *adev = irq_params->adev; | |
692 | struct amdgpu_crtc *acrtc; | |
693 | ||
694 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); | |
695 | ||
696 | if (!acrtc) | |
697 | return; | |
698 | ||
699 | amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); | |
700 | } | |
433e5dec | 701 | #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ |
86bc2219 | 702 | |
e27c41d5 | 703 | /** |
03f2abb0 | 704 | * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. |
e27c41d5 JS |
705 | * @adev: amdgpu_device pointer |
706 | * @notify: dmub notification structure | |
707 | * | |
708 | * Dmub AUX or SET_CONFIG command completion processing callback | |
709 | * Copies dmub notification to DM which is to be read by AUX command. | |
710 | * issuing thread and also signals the event to wake up the thread. | |
711 | */ | |
240e6d25 IB |
712 | static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, |
713 | struct dmub_notification *notify) | |
e27c41d5 JS |
714 | { |
715 | if (adev->dm.dmub_notify) | |
716 | memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); | |
717 | if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) | |
718 | complete(&adev->dm.dmub_aux_transfer_done); | |
719 | } | |
720 | ||
721 | /** | |
722 | * dmub_hpd_callback - DMUB HPD interrupt processing callback. | |
723 | * @adev: amdgpu_device pointer | |
724 | * @notify: dmub notification structure | |
725 | * | |
726 | * Dmub Hpd interrupt processing callback. Gets displayindex through the | |
727 | * ink index and calls helper to do the processing. | |
728 | */ | |
240e6d25 IB |
729 | static void dmub_hpd_callback(struct amdgpu_device *adev, |
730 | struct dmub_notification *notify) | |
e27c41d5 JS |
731 | { |
732 | struct amdgpu_dm_connector *aconnector; | |
f6e03f80 | 733 | struct amdgpu_dm_connector *hpd_aconnector = NULL; |
e27c41d5 JS |
734 | struct drm_connector *connector; |
735 | struct drm_connector_list_iter iter; | |
736 | struct dc_link *link; | |
ae67558b | 737 | u8 link_index = 0; |
978ffac8 | 738 | struct drm_device *dev; |
e27c41d5 JS |
739 | |
740 | if (adev == NULL) | |
741 | return; | |
742 | ||
743 | if (notify == NULL) { | |
744 | DRM_ERROR("DMUB HPD callback notification was NULL"); | |
745 | return; | |
746 | } | |
747 | ||
748 | if (notify->link_index > adev->dm.dc->link_count) { | |
749 | DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); | |
750 | return; | |
751 | } | |
752 | ||
e27c41d5 | 753 | link_index = notify->link_index; |
e27c41d5 | 754 | link = adev->dm.dc->links[link_index]; |
978ffac8 | 755 | dev = adev->dm.ddev; |
e27c41d5 JS |
756 | |
757 | drm_connector_list_iter_begin(dev, &iter); | |
758 | drm_for_each_connector_iter(connector, &iter) { | |
7db7ade2 HW |
759 | |
760 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) | |
761 | continue; | |
762 | ||
e27c41d5 JS |
763 | aconnector = to_amdgpu_dm_connector(connector); |
764 | if (link && aconnector->dc_link == link) { | |
c416a9e4 SW |
765 | if (notify->type == DMUB_NOTIFICATION_HPD) |
766 | DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); | |
767 | else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) | |
768 | DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); | |
769 | else | |
770 | DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", | |
771 | notify->type, link_index); | |
772 | ||
f6e03f80 | 773 | hpd_aconnector = aconnector; |
e27c41d5 JS |
774 | break; |
775 | } | |
776 | } | |
777 | drm_connector_list_iter_end(&iter); | |
e27c41d5 | 778 | |
c40a09e5 NK |
779 | if (hpd_aconnector) { |
780 | if (notify->type == DMUB_NOTIFICATION_HPD) | |
781 | handle_hpd_irq_helper(hpd_aconnector); | |
782 | else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) | |
783 | handle_hpd_rx_irq(hpd_aconnector); | |
784 | } | |
e27c41d5 JS |
785 | } |
786 | ||
787 | /** | |
788 | * register_dmub_notify_callback - Sets callback for DMUB notify | |
789 | * @adev: amdgpu_device pointer | |
790 | * @type: Type of dmub notification | |
791 | * @callback: Dmub interrupt callback function | |
792 | * @dmub_int_thread_offload: offload indicator | |
793 | * | |
794 | * API to register a dmub callback handler for a dmub notification | |
795 | * Also sets indicator whether callback processing to be offloaded. | |
796 | * to dmub interrupt handling thread | |
797 | * Return: true if successfully registered, false if there is existing registration | |
798 | */ | |
240e6d25 IB |
799 | static bool register_dmub_notify_callback(struct amdgpu_device *adev, |
800 | enum dmub_notification_type type, | |
801 | dmub_notify_interrupt_callback_t callback, | |
802 | bool dmub_int_thread_offload) | |
e27c41d5 JS |
803 | { |
804 | if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { | |
805 | adev->dm.dmub_callback[type] = callback; | |
806 | adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; | |
807 | } else | |
808 | return false; | |
809 | ||
810 | return true; | |
811 | } | |
812 | ||
813 | static void dm_handle_hpd_work(struct work_struct *work) | |
814 | { | |
815 | struct dmub_hpd_work *dmub_hpd_wrk; | |
816 | ||
817 | dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); | |
818 | ||
819 | if (!dmub_hpd_wrk->dmub_notify) { | |
820 | DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); | |
821 | return; | |
822 | } | |
823 | ||
824 | if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { | |
825 | dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, | |
826 | dmub_hpd_wrk->dmub_notify); | |
827 | } | |
094b21c1 JS |
828 | |
829 | kfree(dmub_hpd_wrk->dmub_notify); | |
e27c41d5 JS |
830 | kfree(dmub_hpd_wrk); |
831 | ||
832 | } | |
833 | ||
e25515e2 | 834 | #define DMUB_TRACE_MAX_READ 64 |
81927e28 JS |
835 | /** |
836 | * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt | |
837 | * @interrupt_params: used for determining the Outbox instance | |
838 | * | |
839 | * Handles the Outbox Interrupt | |
840 | * event handler. | |
841 | */ | |
81927e28 JS |
842 | static void dm_dmub_outbox1_low_irq(void *interrupt_params) |
843 | { | |
844 | struct dmub_notification notify; | |
845 | struct common_irq_params *irq_params = interrupt_params; | |
846 | struct amdgpu_device *adev = irq_params->adev; | |
847 | struct amdgpu_display_manager *dm = &adev->dm; | |
848 | struct dmcub_trace_buf_entry entry = { 0 }; | |
ae67558b | 849 | u32 count = 0; |
e27c41d5 | 850 | struct dmub_hpd_work *dmub_hpd_wrk; |
f6e03f80 | 851 | struct dc_link *plink = NULL; |
81927e28 | 852 | |
f6e03f80 JS |
853 | if (dc_enable_dmub_notifications(adev->dm.dc) && |
854 | irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { | |
e27c41d5 | 855 | |
f6e03f80 JS |
856 | do { |
857 | dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); | |
a35faec3 | 858 | if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { |
f6e03f80 JS |
859 | DRM_ERROR("DM: notify type %d invalid!", notify.type); |
860 | continue; | |
861 | } | |
c40a09e5 NK |
862 | if (!dm->dmub_callback[notify.type]) { |
863 | DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); | |
864 | continue; | |
865 | } | |
f6e03f80 | 866 | if (dm->dmub_thread_offload[notify.type] == true) { |
094b21c1 JS |
867 | dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); |
868 | if (!dmub_hpd_wrk) { | |
869 | DRM_ERROR("Failed to allocate dmub_hpd_wrk"); | |
870 | return; | |
871 | } | |
0e909e4f CJ |
872 | dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), |
873 | GFP_ATOMIC); | |
094b21c1 JS |
874 | if (!dmub_hpd_wrk->dmub_notify) { |
875 | kfree(dmub_hpd_wrk); | |
876 | DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); | |
877 | return; | |
878 | } | |
879 | INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); | |
f6e03f80 JS |
880 | dmub_hpd_wrk->adev = adev; |
881 | if (notify.type == DMUB_NOTIFICATION_HPD) { | |
882 | plink = adev->dm.dc->links[notify.link_index]; | |
883 | if (plink) { | |
884 | plink->hpd_status = | |
b97788e5 | 885 | notify.hpd_status == DP_HPD_PLUG; |
f6e03f80 | 886 | } |
e27c41d5 | 887 | } |
f6e03f80 JS |
888 | queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); |
889 | } else { | |
890 | dm->dmub_callback[notify.type](adev, ¬ify); | |
891 | } | |
892 | } while (notify.pending_notification); | |
81927e28 JS |
893 | } |
894 | ||
895 | ||
896 | do { | |
897 | if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { | |
898 | trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, | |
899 | entry.param0, entry.param1); | |
900 | ||
901 | DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", | |
902 | entry.trace_code, entry.tick_count, entry.param0, entry.param1); | |
903 | } else | |
904 | break; | |
905 | ||
906 | count++; | |
907 | ||
908 | } while (count <= DMUB_TRACE_MAX_READ); | |
909 | ||
f6e03f80 JS |
910 | if (count > DMUB_TRACE_MAX_READ) |
911 | DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); | |
81927e28 | 912 | } |
86bc2219 | 913 | |
4562236b HW |
914 | static int dm_set_clockgating_state(void *handle, |
915 | enum amd_clockgating_state state) | |
916 | { | |
917 | return 0; | |
918 | } | |
919 | ||
920 | static int dm_set_powergating_state(void *handle, | |
921 | enum amd_powergating_state state) | |
922 | { | |
923 | return 0; | |
924 | } | |
925 | ||
926 | /* Prototypes of private functions */ | |
c82eddf8 | 927 | static int dm_early_init(void *handle); |
4562236b | 928 | |
a32e24b4 | 929 | /* Allocate memory for FBC compressed data */ |
3e332d3a | 930 | static void amdgpu_dm_fbc_init(struct drm_connector *connector) |
a32e24b4 | 931 | { |
534eee82 | 932 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
4d154b85 | 933 | struct dm_compressor_info *compressor = &adev->dm.compressor; |
3e332d3a RL |
934 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); |
935 | struct drm_display_mode *mode; | |
42e67c3b RL |
936 | unsigned long max_size = 0; |
937 | ||
938 | if (adev->dm.dc->fbc_compressor == NULL) | |
939 | return; | |
a32e24b4 | 940 | |
3e332d3a | 941 | if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) |
42e67c3b RL |
942 | return; |
943 | ||
3e332d3a RL |
944 | if (compressor->bo_ptr) |
945 | return; | |
42e67c3b | 946 | |
42e67c3b | 947 | |
3e332d3a RL |
948 | list_for_each_entry(mode, &connector->modes, head) { |
949 | if (max_size < mode->htotal * mode->vtotal) | |
950 | max_size = mode->htotal * mode->vtotal; | |
42e67c3b RL |
951 | } |
952 | ||
953 | if (max_size) { | |
954 | int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, | |
0e5916ff | 955 | AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, |
42e67c3b | 956 | &compressor->gpu_addr, &compressor->cpu_addr); |
a32e24b4 RL |
957 | |
958 | if (r) | |
42e67c3b RL |
959 | DRM_ERROR("DM: Failed to initialize FBC\n"); |
960 | else { | |
961 | adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; | |
962 | DRM_INFO("DM: FBC alloc %lu\n", max_size*4); | |
963 | } | |
964 | ||
a32e24b4 RL |
965 | } |
966 | ||
967 | } | |
a32e24b4 | 968 | |
6ce8f316 NK |
969 | static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, |
970 | int pipe, bool *enabled, | |
971 | unsigned char *buf, int max_bytes) | |
972 | { | |
973 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 974 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
975 | struct drm_connector *connector; |
976 | struct drm_connector_list_iter conn_iter; | |
977 | struct amdgpu_dm_connector *aconnector; | |
978 | int ret = 0; | |
979 | ||
980 | *enabled = false; | |
981 | ||
982 | mutex_lock(&adev->dm.audio_lock); | |
983 | ||
984 | drm_connector_list_iter_begin(dev, &conn_iter); | |
985 | drm_for_each_connector_iter(connector, &conn_iter) { | |
7db7ade2 HW |
986 | |
987 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) | |
988 | continue; | |
989 | ||
6ce8f316 NK |
990 | aconnector = to_amdgpu_dm_connector(connector); |
991 | if (aconnector->audio_inst != port) | |
992 | continue; | |
993 | ||
994 | *enabled = true; | |
995 | ret = drm_eld_size(connector->eld); | |
996 | memcpy(buf, connector->eld, min(max_bytes, ret)); | |
997 | ||
998 | break; | |
999 | } | |
1000 | drm_connector_list_iter_end(&conn_iter); | |
1001 | ||
1002 | mutex_unlock(&adev->dm.audio_lock); | |
1003 | ||
1004 | DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); | |
1005 | ||
1006 | return ret; | |
1007 | } | |
1008 | ||
1009 | static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { | |
1010 | .get_eld = amdgpu_dm_audio_component_get_eld, | |
1011 | }; | |
1012 | ||
1013 | static int amdgpu_dm_audio_component_bind(struct device *kdev, | |
1014 | struct device *hda_kdev, void *data) | |
1015 | { | |
1016 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 1017 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
1018 | struct drm_audio_component *acomp = data; |
1019 | ||
1020 | acomp->ops = &amdgpu_dm_audio_component_ops; | |
1021 | acomp->dev = kdev; | |
1022 | adev->dm.audio_component = acomp; | |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | static void amdgpu_dm_audio_component_unbind(struct device *kdev, | |
1028 | struct device *hda_kdev, void *data) | |
1029 | { | |
534eee82 | 1030 | struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev)); |
6ce8f316 NK |
1031 | struct drm_audio_component *acomp = data; |
1032 | ||
1033 | acomp->ops = NULL; | |
1034 | acomp->dev = NULL; | |
1035 | adev->dm.audio_component = NULL; | |
1036 | } | |
1037 | ||
1038 | static const struct component_ops amdgpu_dm_audio_component_bind_ops = { | |
1039 | .bind = amdgpu_dm_audio_component_bind, | |
1040 | .unbind = amdgpu_dm_audio_component_unbind, | |
1041 | }; | |
1042 | ||
1043 | static int amdgpu_dm_audio_init(struct amdgpu_device *adev) | |
1044 | { | |
1045 | int i, ret; | |
1046 | ||
1047 | if (!amdgpu_audio) | |
1048 | return 0; | |
1049 | ||
1050 | adev->mode_info.audio.enabled = true; | |
1051 | ||
1052 | adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; | |
1053 | ||
1054 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
1055 | adev->mode_info.audio.pin[i].channels = -1; | |
1056 | adev->mode_info.audio.pin[i].rate = -1; | |
1057 | adev->mode_info.audio.pin[i].bits_per_sample = -1; | |
1058 | adev->mode_info.audio.pin[i].status_bits = 0; | |
1059 | adev->mode_info.audio.pin[i].category_code = 0; | |
1060 | adev->mode_info.audio.pin[i].connected = false; | |
1061 | adev->mode_info.audio.pin[i].id = | |
1062 | adev->dm.dc->res_pool->audios[i]->inst; | |
1063 | adev->mode_info.audio.pin[i].offset = 0; | |
1064 | } | |
1065 | ||
1066 | ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); | |
1067 | if (ret < 0) | |
1068 | return ret; | |
1069 | ||
1070 | adev->dm.audio_registered = true; | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) | |
1076 | { | |
1077 | if (!amdgpu_audio) | |
1078 | return; | |
1079 | ||
1080 | if (!adev->mode_info.audio.enabled) | |
1081 | return; | |
1082 | ||
1083 | if (adev->dm.audio_registered) { | |
1084 | component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); | |
1085 | adev->dm.audio_registered = false; | |
1086 | } | |
1087 | ||
1088 | /* TODO: Disable audio? */ | |
1089 | ||
1090 | adev->mode_info.audio.enabled = false; | |
1091 | } | |
1092 | ||
dfd84d90 | 1093 | static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) |
6ce8f316 NK |
1094 | { |
1095 | struct drm_audio_component *acomp = adev->dm.audio_component; | |
1096 | ||
1097 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { | |
1098 | DRM_DEBUG_KMS("Notify ELD: %d\n", pin); | |
1099 | ||
1100 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, | |
1101 | pin, -1); | |
1102 | } | |
1103 | } | |
1104 | ||
743b9786 NK |
1105 | static int dm_dmub_hw_init(struct amdgpu_device *adev) |
1106 | { | |
743b9786 NK |
1107 | const struct dmcub_firmware_header_v1_0 *hdr; |
1108 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; | |
8c7aea40 | 1109 | struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; |
743b9786 NK |
1110 | const struct firmware *dmub_fw = adev->dm.dmub_fw; |
1111 | struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; | |
1112 | struct abm *abm = adev->dm.dc->res_pool->abm; | |
96182df9 | 1113 | struct dc_context *ctx = adev->dm.dc->ctx; |
743b9786 NK |
1114 | struct dmub_srv_hw_params hw_params; |
1115 | enum dmub_status status; | |
1116 | const unsigned char *fw_inst_const, *fw_bss_data; | |
ae67558b | 1117 | u32 i, fw_inst_const_size, fw_bss_data_size; |
743b9786 NK |
1118 | bool has_hw_support; |
1119 | ||
1120 | if (!dmub_srv) | |
1121 | /* DMUB isn't supported on the ASIC. */ | |
1122 | return 0; | |
1123 | ||
8c7aea40 NK |
1124 | if (!fb_info) { |
1125 | DRM_ERROR("No framebuffer info for DMUB service.\n"); | |
1126 | return -EINVAL; | |
1127 | } | |
1128 | ||
743b9786 NK |
1129 | if (!dmub_fw) { |
1130 | /* Firmware required for DMUB support. */ | |
1131 | DRM_ERROR("No firmware provided for DMUB.\n"); | |
1132 | return -EINVAL; | |
1133 | } | |
1134 | ||
96182df9 AP |
1135 | /* initialize register offsets for ASICs with runtime initialization available */ |
1136 | if (dmub_srv->hw_funcs.init_reg_offsets) | |
1137 | dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx); | |
1138 | ||
743b9786 NK |
1139 | status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); |
1140 | if (status != DMUB_STATUS_OK) { | |
1141 | DRM_ERROR("Error checking HW support for DMUB: %d\n", status); | |
1142 | return -EINVAL; | |
1143 | } | |
1144 | ||
1145 | if (!has_hw_support) { | |
1146 | DRM_INFO("DMUB unsupported on ASIC\n"); | |
1147 | return 0; | |
1148 | } | |
1149 | ||
47e62dbd NK |
1150 | /* Reset DMCUB if it was previously running - before we overwrite its memory. */ |
1151 | status = dmub_srv_hw_reset(dmub_srv); | |
1152 | if (status != DMUB_STATUS_OK) | |
1153 | DRM_WARN("Error resetting DMUB HW: %d\n", status); | |
1154 | ||
743b9786 NK |
1155 | hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; |
1156 | ||
743b9786 NK |
1157 | fw_inst_const = dmub_fw->data + |
1158 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
8c7aea40 | 1159 | PSP_HEADER_BYTES; |
743b9786 NK |
1160 | |
1161 | fw_bss_data = dmub_fw->data + | |
1162 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
1163 | le32_to_cpu(hdr->inst_const_bytes); | |
1164 | ||
1165 | /* Copy firmware and bios info into FB memory. */ | |
8c7aea40 NK |
1166 | fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - |
1167 | PSP_HEADER_BYTES - PSP_FOOTER_BYTES; | |
1168 | ||
1169 | fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); | |
1170 | ||
ddde28a5 HW |
1171 | /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, |
1172 | * amdgpu_ucode_init_single_fw will load dmub firmware | |
1173 | * fw_inst_const part to cw0; otherwise, the firmware back door load | |
1174 | * will be done by dm_dmub_hw_init | |
1175 | */ | |
1176 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
1177 | memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, | |
1178 | fw_inst_const_size); | |
1179 | } | |
1180 | ||
a576b345 NK |
1181 | if (fw_bss_data_size) |
1182 | memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, | |
1183 | fw_bss_data, fw_bss_data_size); | |
ddde28a5 HW |
1184 | |
1185 | /* Copy firmware bios info into FB memory. */ | |
8c7aea40 NK |
1186 | memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, |
1187 | adev->bios_size); | |
1188 | ||
1189 | /* Reset regions that need to be reset. */ | |
1190 | memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, | |
1191 | fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); | |
1192 | ||
1193 | memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, | |
1194 | fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); | |
1195 | ||
1196 | memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, | |
1197 | fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); | |
743b9786 NK |
1198 | |
1199 | /* Initialize hardware. */ | |
1200 | memset(&hw_params, 0, sizeof(hw_params)); | |
1201 | hw_params.fb_base = adev->gmc.fb_start; | |
949933b0 | 1202 | hw_params.fb_offset = adev->vm_manager.vram_base_offset; |
743b9786 | 1203 | |
31a7f4bb HW |
1204 | /* backdoor load firmware and trigger dmub running */ |
1205 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) | |
1206 | hw_params.load_inst_const = true; | |
1207 | ||
743b9786 NK |
1208 | if (dmcu) |
1209 | hw_params.psp_version = dmcu->psp_version; | |
1210 | ||
8c7aea40 NK |
1211 | for (i = 0; i < fb_info->num_fb; ++i) |
1212 | hw_params.fb[i] = &fb_info->fb[i]; | |
743b9786 | 1213 | |
4e8303cf | 1214 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
f6aa84b8 RL |
1215 | case IP_VERSION(3, 1, 3): |
1216 | case IP_VERSION(3, 1, 4): | |
06b1661e | 1217 | case IP_VERSION(3, 5, 0): |
3b36f50d | 1218 | hw_params.dpia_supported = true; |
7367540b | 1219 | hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; |
5b109397 JS |
1220 | break; |
1221 | default: | |
1222 | break; | |
1223 | } | |
1224 | ||
743b9786 NK |
1225 | status = dmub_srv_hw_init(dmub_srv, &hw_params); |
1226 | if (status != DMUB_STATUS_OK) { | |
1227 | DRM_ERROR("Error initializing DMUB HW: %d\n", status); | |
1228 | return -EINVAL; | |
1229 | } | |
1230 | ||
1231 | /* Wait for firmware load to finish. */ | |
1232 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); | |
1233 | if (status != DMUB_STATUS_OK) | |
1234 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); | |
1235 | ||
1236 | /* Init DMCU and ABM if available. */ | |
1237 | if (dmcu && abm) { | |
1238 | dmcu->funcs->dmcu_init(dmcu); | |
1239 | abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); | |
1240 | } | |
1241 | ||
051b7887 RL |
1242 | if (!adev->dm.dc->ctx->dmub_srv) |
1243 | adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); | |
9a71c7d3 NK |
1244 | if (!adev->dm.dc->ctx->dmub_srv) { |
1245 | DRM_ERROR("Couldn't allocate DC DMUB server!\n"); | |
1246 | return -ENOMEM; | |
1247 | } | |
1248 | ||
743b9786 NK |
1249 | DRM_INFO("DMUB hardware initialized: version=0x%08X\n", |
1250 | adev->dm.dmcub_fw_version); | |
1251 | ||
1252 | return 0; | |
1253 | } | |
1254 | ||
79d6b935 NK |
1255 | static void dm_dmub_hw_resume(struct amdgpu_device *adev) |
1256 | { | |
1257 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; | |
1258 | enum dmub_status status; | |
1259 | bool init; | |
1260 | ||
1261 | if (!dmub_srv) { | |
1262 | /* DMUB isn't supported on the ASIC. */ | |
1263 | return; | |
1264 | } | |
1265 | ||
1266 | status = dmub_srv_is_hw_init(dmub_srv, &init); | |
1267 | if (status != DMUB_STATUS_OK) | |
1268 | DRM_WARN("DMUB hardware init check failed: %d\n", status); | |
1269 | ||
1270 | if (status == DMUB_STATUS_OK && init) { | |
1271 | /* Wait for firmware load to finish. */ | |
1272 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); | |
1273 | if (status != DMUB_STATUS_OK) | |
1274 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); | |
1275 | } else { | |
1276 | /* Perform the full hardware initialization. */ | |
1277 | dm_dmub_hw_init(adev); | |
1278 | } | |
1279 | } | |
1280 | ||
c0fb85ae | 1281 | static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) |
c44a22b3 | 1282 | { |
ae67558b SS |
1283 | u64 pt_base; |
1284 | u32 logical_addr_low; | |
1285 | u32 logical_addr_high; | |
1286 | u32 agp_base, agp_bot, agp_top; | |
c0fb85ae | 1287 | PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; |
c44a22b3 | 1288 | |
a0f884f5 NK |
1289 | memset(pa_config, 0, sizeof(*pa_config)); |
1290 | ||
c0fb85ae YZ |
1291 | agp_base = 0; |
1292 | agp_bot = adev->gmc.agp_start >> 24; | |
1293 | agp_top = adev->gmc.agp_end >> 24; | |
c44a22b3 | 1294 | |
0294868f | 1295 | /* AGP aperture is disabled */ |
de59b699 | 1296 | if (agp_bot > agp_top) { |
4d2c6e89 | 1297 | logical_addr_low = adev->gmc.fb_start >> 18; |
0294868f AD |
1298 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1299 | /* | |
1300 | * Raven2 has a HW issue that it is unable to use the vram which | |
1301 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the | |
1302 | * workaround that increase system aperture high address (add 1) | |
1303 | * to get rid of the VM fault and hardware hang. | |
1304 | */ | |
1305 | logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; | |
1306 | else | |
4d2c6e89 | 1307 | logical_addr_high = adev->gmc.fb_end >> 18; |
0294868f | 1308 | } else { |
4d2c6e89 | 1309 | logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; |
0294868f AD |
1310 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1311 | /* | |
1312 | * Raven2 has a HW issue that it is unable to use the vram which | |
1313 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the | |
1314 | * workaround that increase system aperture high address (add 1) | |
1315 | * to get rid of the VM fault and hardware hang. | |
1316 | */ | |
1317 | logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); | |
1318 | else | |
1319 | logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; | |
1320 | } | |
1321 | ||
1322 | pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); | |
c44a22b3 | 1323 | |
ef064187 YZ |
1324 | page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> |
1325 | AMDGPU_GPU_PAGE_SHIFT); | |
1326 | page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> | |
1327 | AMDGPU_GPU_PAGE_SHIFT); | |
1328 | page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> | |
1329 | AMDGPU_GPU_PAGE_SHIFT); | |
1330 | page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> | |
1331 | AMDGPU_GPU_PAGE_SHIFT); | |
1332 | page_table_base.high_part = upper_32_bits(pt_base); | |
c0fb85ae | 1333 | page_table_base.low_part = lower_32_bits(pt_base); |
c44a22b3 | 1334 | |
c0fb85ae YZ |
1335 | pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; |
1336 | pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; | |
1337 | ||
c82eddf8 | 1338 | pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; |
c0fb85ae YZ |
1339 | pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; |
1340 | pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; | |
1341 | ||
1342 | pa_config->system_aperture.fb_base = adev->gmc.fb_start; | |
949933b0 | 1343 | pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; |
c0fb85ae YZ |
1344 | pa_config->system_aperture.fb_top = adev->gmc.fb_end; |
1345 | ||
1346 | pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; | |
1347 | pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; | |
1348 | pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; | |
1349 | ||
40e9f3f0 | 1350 | pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; |
c44a22b3 | 1351 | |
c44a22b3 | 1352 | } |
cae5c1ab | 1353 | |
028c4ccf QZ |
1354 | static void force_connector_state( |
1355 | struct amdgpu_dm_connector *aconnector, | |
1356 | enum drm_connector_force force_state) | |
1357 | { | |
1358 | struct drm_connector *connector = &aconnector->base; | |
1359 | ||
1360 | mutex_lock(&connector->dev->mode_config.mutex); | |
1361 | aconnector->base.force = force_state; | |
1362 | mutex_unlock(&connector->dev->mode_config.mutex); | |
1363 | ||
1364 | mutex_lock(&aconnector->hpd_lock); | |
1365 | drm_kms_helper_connector_hotplug_event(connector); | |
1366 | mutex_unlock(&aconnector->hpd_lock); | |
1367 | } | |
1368 | ||
8e794421 WL |
1369 | static void dm_handle_hpd_rx_offload_work(struct work_struct *work) |
1370 | { | |
1371 | struct hpd_rx_irq_offload_work *offload_work; | |
1372 | struct amdgpu_dm_connector *aconnector; | |
1373 | struct dc_link *dc_link; | |
1374 | struct amdgpu_device *adev; | |
1375 | enum dc_connection_type new_connection_type = dc_connection_none; | |
1376 | unsigned long flags; | |
028c4ccf QZ |
1377 | union test_response test_response; |
1378 | ||
1379 | memset(&test_response, 0, sizeof(test_response)); | |
8e794421 WL |
1380 | |
1381 | offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); | |
1382 | aconnector = offload_work->offload_wq->aconnector; | |
1383 | ||
1384 | if (!aconnector) { | |
1385 | DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); | |
1386 | goto skip; | |
1387 | } | |
1388 | ||
1389 | adev = drm_to_adev(aconnector->base.dev); | |
1390 | dc_link = aconnector->dc_link; | |
1391 | ||
1392 | mutex_lock(&aconnector->hpd_lock); | |
54618888 | 1393 | if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) |
8e794421 WL |
1394 | DRM_ERROR("KMS: Failed to detect connector\n"); |
1395 | mutex_unlock(&aconnector->hpd_lock); | |
1396 | ||
1397 | if (new_connection_type == dc_connection_none) | |
1398 | goto skip; | |
1399 | ||
1400 | if (amdgpu_in_reset(adev)) | |
1401 | goto skip; | |
1402 | ||
bb4fa525 WL |
1403 | if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || |
1404 | offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { | |
1405 | dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); | |
1406 | spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); | |
1407 | offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; | |
1408 | spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); | |
1409 | goto skip; | |
1410 | } | |
1411 | ||
8e794421 | 1412 | mutex_lock(&adev->dm.dc_lock); |
028c4ccf | 1413 | if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { |
8e794421 | 1414 | dc_link_dp_handle_automated_test(dc_link); |
028c4ccf QZ |
1415 | |
1416 | if (aconnector->timing_changed) { | |
1417 | /* force connector disconnect and reconnect */ | |
1418 | force_connector_state(aconnector, DRM_FORCE_OFF); | |
1419 | msleep(100); | |
1420 | force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); | |
1421 | } | |
1422 | ||
1423 | test_response.bits.ACK = 1; | |
1424 | ||
1425 | core_link_write_dpcd( | |
1426 | dc_link, | |
1427 | DP_TEST_RESPONSE, | |
1428 | &test_response.raw, | |
1429 | sizeof(test_response)); | |
c82eddf8 | 1430 | } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && |
c5a31f17 | 1431 | dc_link_check_link_loss_status(dc_link, &offload_work->data) && |
8e794421 | 1432 | dc_link_dp_allow_hpd_rx_irq(dc_link)) { |
e322843e HW |
1433 | /* offload_work->data is from handle_hpd_rx_irq-> |
1434 | * schedule_hpd_rx_offload_work.this is defer handle | |
1435 | * for hpd short pulse. upon here, link status may be | |
1436 | * changed, need get latest link status from dpcd | |
1437 | * registers. if link status is good, skip run link | |
1438 | * training again. | |
1439 | */ | |
1440 | union hpd_irq_data irq_data; | |
1441 | ||
1442 | memset(&irq_data, 0, sizeof(irq_data)); | |
1443 | ||
1444 | /* before dc_link_dp_handle_link_loss, allow new link lost handle | |
1445 | * request be added to work queue if link lost at end of dc_link_ | |
1446 | * dp_handle_link_loss | |
1447 | */ | |
8e794421 WL |
1448 | spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); |
1449 | offload_work->offload_wq->is_handling_link_loss = false; | |
1450 | spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); | |
e322843e | 1451 | |
54618888 | 1452 | if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && |
e322843e HW |
1453 | dc_link_check_link_loss_status(dc_link, &irq_data)) |
1454 | dc_link_dp_handle_link_loss(dc_link); | |
8e794421 WL |
1455 | } |
1456 | mutex_unlock(&adev->dm.dc_lock); | |
1457 | ||
1458 | skip: | |
1459 | kfree(offload_work); | |
1460 | ||
1461 | } | |
1462 | ||
1463 | static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) | |
1464 | { | |
1465 | int max_caps = dc->caps.max_links; | |
1466 | int i = 0; | |
1467 | struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; | |
1468 | ||
1469 | hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); | |
1470 | ||
1471 | if (!hpd_rx_offload_wq) | |
1472 | return NULL; | |
1473 | ||
1474 | ||
1475 | for (i = 0; i < max_caps; i++) { | |
1476 | hpd_rx_offload_wq[i].wq = | |
1477 | create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); | |
1478 | ||
1479 | if (hpd_rx_offload_wq[i].wq == NULL) { | |
1480 | DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); | |
7136f956 | 1481 | goto out_err; |
8e794421 WL |
1482 | } |
1483 | ||
1484 | spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); | |
1485 | } | |
1486 | ||
1487 | return hpd_rx_offload_wq; | |
7136f956 RM |
1488 | |
1489 | out_err: | |
1490 | for (i = 0; i < max_caps; i++) { | |
1491 | if (hpd_rx_offload_wq[i].wq) | |
1492 | destroy_workqueue(hpd_rx_offload_wq[i].wq); | |
1493 | } | |
1494 | kfree(hpd_rx_offload_wq); | |
1495 | return NULL; | |
8e794421 WL |
1496 | } |
1497 | ||
3ce51649 AD |
1498 | struct amdgpu_stutter_quirk { |
1499 | u16 chip_vendor; | |
1500 | u16 chip_device; | |
1501 | u16 subsys_vendor; | |
1502 | u16 subsys_device; | |
1503 | u8 revision; | |
1504 | }; | |
1505 | ||
1506 | static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { | |
1507 | /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ | |
1508 | { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, | |
1509 | { 0, 0, 0, 0, 0 }, | |
1510 | }; | |
1511 | ||
1512 | static bool dm_should_disable_stutter(struct pci_dev *pdev) | |
1513 | { | |
1514 | const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; | |
1515 | ||
1516 | while (p && p->chip_device != 0) { | |
1517 | if (pdev->vendor == p->chip_vendor && | |
1518 | pdev->device == p->chip_device && | |
1519 | pdev->subsystem_vendor == p->subsys_vendor && | |
1520 | pdev->subsystem_device == p->subsys_device && | |
1521 | pdev->revision == p->revision) { | |
1522 | return true; | |
1523 | } | |
1524 | ++p; | |
1525 | } | |
1526 | return false; | |
1527 | } | |
1528 | ||
57b9f338 FZ |
1529 | static const struct dmi_system_id hpd_disconnect_quirk_table[] = { |
1530 | { | |
1531 | .matches = { | |
1532 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1533 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), | |
1534 | }, | |
1535 | }, | |
1536 | { | |
1537 | .matches = { | |
1538 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1539 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), | |
1540 | }, | |
1541 | }, | |
1542 | { | |
1543 | .matches = { | |
1544 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1545 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), | |
1546 | }, | |
1547 | }, | |
503dc81c TL |
1548 | { |
1549 | .matches = { | |
1550 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1551 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), | |
1552 | }, | |
1553 | }, | |
1554 | { | |
1555 | .matches = { | |
1556 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1557 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), | |
1558 | }, | |
1559 | }, | |
1560 | { | |
1561 | .matches = { | |
1562 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1563 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), | |
1564 | }, | |
1565 | }, | |
1566 | { | |
1567 | .matches = { | |
1568 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1569 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), | |
1570 | }, | |
1571 | }, | |
1572 | { | |
1573 | .matches = { | |
1574 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1575 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), | |
1576 | }, | |
1577 | }, | |
1578 | { | |
1579 | .matches = { | |
1580 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1581 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), | |
1582 | }, | |
1583 | }, | |
57b9f338 | 1584 | {} |
503dc81c | 1585 | /* TODO: refactor this from a fixed table to a dynamic option */ |
57b9f338 FZ |
1586 | }; |
1587 | ||
1588 | static void retrieve_dmi_info(struct amdgpu_display_manager *dm) | |
1589 | { | |
1590 | const struct dmi_system_id *dmi_id; | |
1591 | ||
1592 | dm->aux_hpd_discon_quirk = false; | |
1593 | ||
1594 | dmi_id = dmi_first_match(hpd_disconnect_quirk_table); | |
1595 | if (dmi_id) { | |
1596 | dm->aux_hpd_discon_quirk = true; | |
1597 | DRM_INFO("aux_hpd_discon_quirk attached\n"); | |
1598 | } | |
1599 | } | |
1600 | ||
7578ecda | 1601 | static int amdgpu_dm_init(struct amdgpu_device *adev) |
4562236b HW |
1602 | { |
1603 | struct dc_init_data init_data; | |
52704fca | 1604 | struct dc_callback_init init_params; |
743b9786 | 1605 | int r; |
52704fca | 1606 | |
4a580877 | 1607 | adev->dm.ddev = adev_to_drm(adev); |
4562236b HW |
1608 | adev->dm.adev = adev; |
1609 | ||
4562236b HW |
1610 | /* Zero all the fields */ |
1611 | memset(&init_data, 0, sizeof(init_data)); | |
52704fca | 1612 | memset(&init_params, 0, sizeof(init_params)); |
4562236b | 1613 | |
ead08b95 | 1614 | mutex_init(&adev->dm.dpia_aux_lock); |
674e78ac | 1615 | mutex_init(&adev->dm.dc_lock); |
6ce8f316 | 1616 | mutex_init(&adev->dm.audio_lock); |
674e78ac | 1617 | |
c82eddf8 | 1618 | if (amdgpu_dm_irq_init(adev)) { |
4562236b HW |
1619 | DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); |
1620 | goto error; | |
1621 | } | |
1622 | ||
1623 | init_data.asic_id.chip_family = adev->family; | |
1624 | ||
2dc31ca1 | 1625 | init_data.asic_id.pci_revision_id = adev->pdev->revision; |
4562236b | 1626 | init_data.asic_id.hw_internal_rev = adev->external_rev_id; |
dae66a04 | 1627 | init_data.asic_id.chip_id = adev->pdev->device; |
4562236b | 1628 | |
770d13b1 | 1629 | init_data.asic_id.vram_width = adev->gmc.vram_width; |
4562236b HW |
1630 | /* TODO: initialize init_data.asic_id.vram_type here!!!! */ |
1631 | init_data.asic_id.atombios_base_address = | |
1632 | adev->mode_info.atom_context->bios; | |
1633 | ||
1634 | init_data.driver = adev; | |
1635 | ||
1636 | adev->dm.cgs_device = amdgpu_cgs_create_device(adev); | |
1637 | ||
1638 | if (!adev->dm.cgs_device) { | |
1639 | DRM_ERROR("amdgpu: failed to create cgs device.\n"); | |
1640 | goto error; | |
1641 | } | |
1642 | ||
1643 | init_data.cgs_device = adev->dm.cgs_device; | |
1644 | ||
4562236b HW |
1645 | init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; |
1646 | ||
4e8303cf | 1647 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
fd546bc5 AD |
1648 | case IP_VERSION(2, 1, 0): |
1649 | switch (adev->dm.dmcub_fw_version) { | |
1650 | case 0: /* development */ | |
1651 | case 0x1: /* linux-firmware.git hash 6d9f399 */ | |
1652 | case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ | |
1653 | init_data.flags.disable_dmcu = false; | |
1654 | break; | |
1655 | default: | |
1656 | init_data.flags.disable_dmcu = true; | |
1657 | } | |
1658 | break; | |
1659 | case IP_VERSION(2, 0, 3): | |
1660 | init_data.flags.disable_dmcu = true; | |
1661 | break; | |
1662 | default: | |
1663 | break; | |
1664 | } | |
1665 | ||
098c1307 YZ |
1666 | /* APU support S/G display by default except: |
1667 | * ASICs before Carrizo, | |
1668 | * RAVEN1 (Users reported stability issue) | |
1669 | */ | |
1670 | ||
1671 | if (adev->asic_type < CHIP_CARRIZO) { | |
169ed4ec | 1672 | init_data.flags.gpu_vm_support = false; |
098c1307 YZ |
1673 | } else if (adev->asic_type == CHIP_RAVEN) { |
1674 | if (adev->apu_flags & AMD_APU_IS_RAVEN) | |
1675 | init_data.flags.gpu_vm_support = false; | |
1676 | else | |
1677 | init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); | |
1678 | } else { | |
1679 | init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); | |
1680 | } | |
6e227308 | 1681 | |
1efdd37c | 1682 | adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; |
a7f520bf | 1683 | |
04b94af4 AD |
1684 | if (amdgpu_dc_feature_mask & DC_FBC_MASK) |
1685 | init_data.flags.fbc_support = true; | |
1686 | ||
d99f38ae AD |
1687 | if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) |
1688 | init_data.flags.multi_mon_pp_mclk_switch = true; | |
1689 | ||
eaf56410 LL |
1690 | if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) |
1691 | init_data.flags.disable_fractional_pwm = true; | |
a5148245 ZL |
1692 | |
1693 | if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) | |
1694 | init_data.flags.edp_no_power_sequencing = true; | |
eaf56410 | 1695 | |
12320274 AP |
1696 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) |
1697 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; | |
1698 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) | |
1699 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; | |
12320274 | 1700 | |
7aba117a | 1701 | init_data.flags.seamless_boot_edp_requested = false; |
78ad75f8 | 1702 | |
bb0f8429 | 1703 | if (amdgpu_device_seamless_boot_supported(adev)) { |
7aba117a | 1704 | init_data.flags.seamless_boot_edp_requested = true; |
1edf5ae1 ZL |
1705 | init_data.flags.allow_seamless_boot_optimization = true; |
1706 | DRM_INFO("Seamless boot condition check passed\n"); | |
1707 | } | |
1708 | ||
a8201902 LM |
1709 | init_data.flags.enable_mipi_converter_optimization = true; |
1710 | ||
e5028e9f | 1711 | init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; |
2a93292f | 1712 | init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; |
8774029f | 1713 | init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; |
e5028e9f | 1714 | |
198891fd HW |
1715 | /* Enable DWB for tested platforms only */ |
1716 | if (adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0)) | |
1717 | init_data.num_virtual_links = 1; | |
1718 | ||
0dd79532 | 1719 | INIT_LIST_HEAD(&adev->dm.da_list); |
57b9f338 FZ |
1720 | |
1721 | retrieve_dmi_info(&adev->dm); | |
1722 | ||
4562236b HW |
1723 | /* Display Core create. */ |
1724 | adev->dm.dc = dc_create(&init_data); | |
1725 | ||
423788c7 | 1726 | if (adev->dm.dc) { |
9788d087 | 1727 | DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, |
bf7fda0b | 1728 | dce_version_to_string(adev->dm.dc->ctx->dce_version)); |
423788c7 | 1729 | } else { |
0c3601a2 | 1730 | DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); |
423788c7 ES |
1731 | goto error; |
1732 | } | |
4562236b | 1733 | |
8a791dab HW |
1734 | if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { |
1735 | adev->dm.dc->debug.force_single_disp_pipe_split = false; | |
1736 | adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; | |
1737 | } | |
1738 | ||
f99d8762 HW |
1739 | if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) |
1740 | adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; | |
3ce51649 AD |
1741 | if (dm_should_disable_stutter(adev->pdev)) |
1742 | adev->dm.dc->debug.disable_stutter = true; | |
f99d8762 | 1743 | |
8a791dab HW |
1744 | if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) |
1745 | adev->dm.dc->debug.disable_stutter = true; | |
1746 | ||
c82eddf8 | 1747 | if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) |
8a791dab HW |
1748 | adev->dm.dc->debug.disable_dsc = true; |
1749 | ||
1750 | if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) | |
1751 | adev->dm.dc->debug.disable_clock_gate = true; | |
1752 | ||
cfb979f7 AP |
1753 | if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) |
1754 | adev->dm.dc->debug.force_subvp_mclk_switch = true; | |
1755 | ||
792a0cdd LL |
1756 | adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; |
1757 | ||
d1bc26cb FZ |
1758 | /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ |
1759 | adev->dm.dc->debug.ignore_cable_id = true; | |
1760 | ||
e3834491 FZ |
1761 | if (adev->dm.dc->caps.dp_hdmi21_pcon_support) |
1762 | DRM_INFO("DP-HDMI FRL PCON supported\n"); | |
1763 | ||
743b9786 NK |
1764 | r = dm_dmub_hw_init(adev); |
1765 | if (r) { | |
1766 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); | |
1767 | goto error; | |
1768 | } | |
1769 | ||
bb6785c1 NK |
1770 | dc_hardware_init(adev->dm.dc); |
1771 | ||
8e794421 WL |
1772 | adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); |
1773 | if (!adev->dm.hpd_rx_offload_wq) { | |
1774 | DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); | |
1775 | goto error; | |
1776 | } | |
1777 | ||
3ca001af | 1778 | if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { |
e6cd859d AD |
1779 | struct dc_phy_addr_space_config pa_config; |
1780 | ||
0b08c54b | 1781 | mmhub_read_system_context(adev, &pa_config); |
c0fb85ae | 1782 | |
0b08c54b YZ |
1783 | // Call the DC init_memory func |
1784 | dc_setup_system_context(adev->dm.dc, &pa_config); | |
1785 | } | |
c0fb85ae | 1786 | |
4562236b HW |
1787 | adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); |
1788 | if (!adev->dm.freesync_module) { | |
1789 | DRM_ERROR( | |
1790 | "amdgpu: failed to initialize freesync_module.\n"); | |
1791 | } else | |
f1ad2f5e | 1792 | DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", |
4562236b HW |
1793 | adev->dm.freesync_module); |
1794 | ||
e277adc5 LSL |
1795 | amdgpu_dm_init_color_mod(); |
1796 | ||
ea3b4242 | 1797 | if (adev->dm.dc->caps.max_links > 0) { |
09a5df6c NK |
1798 | adev->dm.vblank_control_workqueue = |
1799 | create_singlethread_workqueue("dm_vblank_control_workqueue"); | |
1800 | if (!adev->dm.vblank_control_workqueue) | |
ea3b4242 | 1801 | DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); |
ea3b4242 | 1802 | } |
ea3b4242 | 1803 | |
c08182f2 | 1804 | if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { |
e50dc171 | 1805 | adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); |
52704fca | 1806 | |
96a3b32e BL |
1807 | if (!adev->dm.hdcp_workqueue) |
1808 | DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); | |
1809 | else | |
1810 | DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); | |
52704fca | 1811 | |
96a3b32e BL |
1812 | dc_init_callbacks(adev->dm.dc, &init_params); |
1813 | } | |
11d526f1 | 1814 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
81927e28 JS |
1815 | init_completion(&adev->dm.dmub_aux_transfer_done); |
1816 | adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); | |
1817 | if (!adev->dm.dmub_notify) { | |
1818 | DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); | |
1819 | goto error; | |
1820 | } | |
e27c41d5 JS |
1821 | |
1822 | adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); | |
1823 | if (!adev->dm.delayed_hpd_wq) { | |
1824 | DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); | |
1825 | goto error; | |
1826 | } | |
1827 | ||
81927e28 | 1828 | amdgpu_dm_outbox_init(adev); |
e27c41d5 JS |
1829 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, |
1830 | dmub_aux_setconfig_callback, false)) { | |
1831 | DRM_ERROR("amdgpu: fail to register dmub aux callback"); | |
1832 | goto error; | |
1833 | } | |
1834 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) { | |
1835 | DRM_ERROR("amdgpu: fail to register dmub hpd callback"); | |
1836 | goto error; | |
1837 | } | |
c40a09e5 NK |
1838 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) { |
1839 | DRM_ERROR("amdgpu: fail to register dmub hpd callback"); | |
1840 | goto error; | |
1841 | } | |
81927e28 JS |
1842 | } |
1843 | ||
11d526f1 SW |
1844 | /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. |
1845 | * It is expected that DMUB will resend any pending notifications at this point, for | |
1846 | * example HPD from DPIA. | |
1847 | */ | |
7ce34cbf | 1848 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
11d526f1 SW |
1849 | dc_enable_dmub_outbox(adev->dm.dc); |
1850 | ||
7ce34cbf SW |
1851 | /* DPIA trace goes to dmesg logs only if outbox is enabled */ |
1852 | if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) | |
1853 | dc_dmub_srv_enable_dpia_trace(adev->dm.dc); | |
1854 | } | |
1855 | ||
1c43a48b SW |
1856 | if (amdgpu_dm_initialize_drm_device(adev)) { |
1857 | DRM_ERROR( | |
1858 | "amdgpu: failed to initialize sw for display support.\n"); | |
1859 | goto error; | |
1860 | } | |
1861 | ||
f74367e4 AD |
1862 | /* create fake encoders for MST */ |
1863 | dm_dp_create_fake_mst_encoders(adev); | |
1864 | ||
4562236b HW |
1865 | /* TODO: Add_display_info? */ |
1866 | ||
1867 | /* TODO use dynamic cursor width */ | |
4a580877 LT |
1868 | adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; |
1869 | adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; | |
4562236b | 1870 | |
4a580877 | 1871 | if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { |
4562236b HW |
1872 | DRM_ERROR( |
1873 | "amdgpu: failed to initialize sw for display support.\n"); | |
1874 | goto error; | |
1875 | } | |
1876 | ||
f477c7b5 AL |
1877 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
1878 | adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); | |
1879 | if (!adev->dm.secure_display_ctxs) | |
1880 | DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); | |
1881 | #endif | |
c0fb85ae | 1882 | |
f1ad2f5e | 1883 | DRM_DEBUG_DRIVER("KMS initialized.\n"); |
4562236b HW |
1884 | |
1885 | return 0; | |
1886 | error: | |
1887 | amdgpu_dm_fini(adev); | |
1888 | ||
59d0f396 | 1889 | return -EINVAL; |
4562236b HW |
1890 | } |
1891 | ||
e9669fb7 AG |
1892 | static int amdgpu_dm_early_fini(void *handle) |
1893 | { | |
1894 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1895 | ||
1896 | amdgpu_dm_audio_fini(adev); | |
1897 | ||
1898 | return 0; | |
1899 | } | |
1900 | ||
7578ecda | 1901 | static void amdgpu_dm_fini(struct amdgpu_device *adev) |
4562236b | 1902 | { |
f74367e4 AD |
1903 | int i; |
1904 | ||
09a5df6c NK |
1905 | if (adev->dm.vblank_control_workqueue) { |
1906 | destroy_workqueue(adev->dm.vblank_control_workqueue); | |
1907 | adev->dm.vblank_control_workqueue = NULL; | |
1908 | } | |
09a5df6c | 1909 | |
4562236b | 1910 | amdgpu_dm_destroy_drm_device(&adev->dm); |
c8bdf2b6 | 1911 | |
9a65df19 | 1912 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
1b11ff76 | 1913 | if (adev->dm.secure_display_ctxs) { |
c3d74960 | 1914 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
1b11ff76 AL |
1915 | if (adev->dm.secure_display_ctxs[i].crtc) { |
1916 | flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); | |
1917 | flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); | |
1918 | } | |
1919 | } | |
1920 | kfree(adev->dm.secure_display_ctxs); | |
1921 | adev->dm.secure_display_ctxs = NULL; | |
9a65df19 WL |
1922 | } |
1923 | #endif | |
52704fca | 1924 | if (adev->dm.hdcp_workqueue) { |
e96b1b29 | 1925 | hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); |
52704fca BL |
1926 | adev->dm.hdcp_workqueue = NULL; |
1927 | } | |
1928 | ||
1929 | if (adev->dm.dc) | |
1930 | dc_deinit_callbacks(adev->dm.dc); | |
51ba6912 | 1931 | |
52f1783f IA |
1932 | if (adev->dm.dc) |
1933 | dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); | |
9a71c7d3 | 1934 | |
81927e28 JS |
1935 | if (dc_enable_dmub_notifications(adev->dm.dc)) { |
1936 | kfree(adev->dm.dmub_notify); | |
1937 | adev->dm.dmub_notify = NULL; | |
e27c41d5 JS |
1938 | destroy_workqueue(adev->dm.delayed_hpd_wq); |
1939 | adev->dm.delayed_hpd_wq = NULL; | |
81927e28 JS |
1940 | } |
1941 | ||
743b9786 NK |
1942 | if (adev->dm.dmub_bo) |
1943 | amdgpu_bo_free_kernel(&adev->dm.dmub_bo, | |
1944 | &adev->dm.dmub_bo_gpu_addr, | |
1945 | &adev->dm.dmub_bo_cpu_addr); | |
52704fca | 1946 | |
006c26a0 AG |
1947 | if (adev->dm.hpd_rx_offload_wq) { |
1948 | for (i = 0; i < adev->dm.dc->caps.max_links; i++) { | |
1949 | if (adev->dm.hpd_rx_offload_wq[i].wq) { | |
1950 | destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); | |
1951 | adev->dm.hpd_rx_offload_wq[i].wq = NULL; | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | kfree(adev->dm.hpd_rx_offload_wq); | |
1956 | adev->dm.hpd_rx_offload_wq = NULL; | |
1957 | } | |
1958 | ||
c8bdf2b6 ED |
1959 | /* DC Destroy TODO: Replace destroy DAL */ |
1960 | if (adev->dm.dc) | |
1961 | dc_destroy(&adev->dm.dc); | |
4562236b HW |
1962 | /* |
1963 | * TODO: pageflip, vlank interrupt | |
1964 | * | |
1965 | * amdgpu_dm_irq_fini(adev); | |
1966 | */ | |
1967 | ||
1968 | if (adev->dm.cgs_device) { | |
1969 | amdgpu_cgs_destroy_device(adev->dm.cgs_device); | |
1970 | adev->dm.cgs_device = NULL; | |
1971 | } | |
1972 | if (adev->dm.freesync_module) { | |
1973 | mod_freesync_destroy(adev->dm.freesync_module); | |
1974 | adev->dm.freesync_module = NULL; | |
1975 | } | |
674e78ac | 1976 | |
6ce8f316 | 1977 | mutex_destroy(&adev->dm.audio_lock); |
674e78ac | 1978 | mutex_destroy(&adev->dm.dc_lock); |
ead08b95 | 1979 | mutex_destroy(&adev->dm.dpia_aux_lock); |
4562236b HW |
1980 | } |
1981 | ||
a94d5569 | 1982 | static int load_dmcu_fw(struct amdgpu_device *adev) |
4562236b | 1983 | { |
a7669aff | 1984 | const char *fw_name_dmcu = NULL; |
a94d5569 DF |
1985 | int r; |
1986 | const struct dmcu_firmware_header_v1_0 *hdr; | |
1987 | ||
c82eddf8 | 1988 | switch (adev->asic_type) { |
55e56389 MR |
1989 | #if defined(CONFIG_DRM_AMD_DC_SI) |
1990 | case CHIP_TAHITI: | |
1991 | case CHIP_PITCAIRN: | |
1992 | case CHIP_VERDE: | |
1993 | case CHIP_OLAND: | |
1994 | #endif | |
a94d5569 DF |
1995 | case CHIP_BONAIRE: |
1996 | case CHIP_HAWAII: | |
1997 | case CHIP_KAVERI: | |
1998 | case CHIP_KABINI: | |
1999 | case CHIP_MULLINS: | |
2000 | case CHIP_TONGA: | |
2001 | case CHIP_FIJI: | |
2002 | case CHIP_CARRIZO: | |
2003 | case CHIP_STONEY: | |
2004 | case CHIP_POLARIS11: | |
2005 | case CHIP_POLARIS10: | |
2006 | case CHIP_POLARIS12: | |
2007 | case CHIP_VEGAM: | |
2008 | case CHIP_VEGA10: | |
2009 | case CHIP_VEGA12: | |
2010 | case CHIP_VEGA20: | |
2011 | return 0; | |
5ea23931 RL |
2012 | case CHIP_NAVI12: |
2013 | fw_name_dmcu = FIRMWARE_NAVI12_DMCU; | |
2014 | break; | |
a94d5569 | 2015 | case CHIP_RAVEN: |
a7669aff HW |
2016 | if (ASICREV_IS_PICASSO(adev->external_rev_id)) |
2017 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
2018 | else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) | |
2019 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
2020 | else | |
a7669aff | 2021 | return 0; |
a94d5569 DF |
2022 | break; |
2023 | default: | |
4e8303cf | 2024 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
c08182f2 AD |
2025 | case IP_VERSION(2, 0, 2): |
2026 | case IP_VERSION(2, 0, 3): | |
2027 | case IP_VERSION(2, 0, 0): | |
2028 | case IP_VERSION(2, 1, 0): | |
2029 | case IP_VERSION(3, 0, 0): | |
2030 | case IP_VERSION(3, 0, 2): | |
2031 | case IP_VERSION(3, 0, 3): | |
2032 | case IP_VERSION(3, 0, 1): | |
2033 | case IP_VERSION(3, 1, 2): | |
2034 | case IP_VERSION(3, 1, 3): | |
f3cd57e4 | 2035 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 2036 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 2037 | case IP_VERSION(3, 1, 6): |
577359ca AP |
2038 | case IP_VERSION(3, 2, 0): |
2039 | case IP_VERSION(3, 2, 1): | |
06b1661e | 2040 | case IP_VERSION(3, 5, 0): |
c08182f2 AD |
2041 | return 0; |
2042 | default: | |
2043 | break; | |
2044 | } | |
a94d5569 | 2045 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); |
59d0f396 | 2046 | return -EINVAL; |
a94d5569 DF |
2047 | } |
2048 | ||
2049 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
2050 | DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); | |
2051 | return 0; | |
2052 | } | |
2053 | ||
46fa9075 ML |
2054 | r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); |
2055 | if (r == -ENODEV) { | |
a94d5569 DF |
2056 | /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ |
2057 | DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); | |
2058 | adev->dm.fw_dmcu = NULL; | |
2059 | return 0; | |
2060 | } | |
a94d5569 DF |
2061 | if (r) { |
2062 | dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", | |
2063 | fw_name_dmcu); | |
51526637 | 2064 | amdgpu_ucode_release(&adev->dm.fw_dmcu); |
a94d5569 DF |
2065 | return r; |
2066 | } | |
2067 | ||
2068 | hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; | |
2069 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; | |
2070 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; | |
2071 | adev->firmware.fw_size += | |
2072 | ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
2073 | ||
2074 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; | |
2075 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; | |
2076 | adev->firmware.fw_size += | |
2077 | ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
2078 | ||
ee6e89c0 DF |
2079 | adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); |
2080 | ||
a94d5569 DF |
2081 | DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); |
2082 | ||
4562236b HW |
2083 | return 0; |
2084 | } | |
2085 | ||
743b9786 NK |
2086 | static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) |
2087 | { | |
2088 | struct amdgpu_device *adev = ctx; | |
2089 | ||
2090 | return dm_read_reg(adev->dm.dc->ctx, address); | |
2091 | } | |
2092 | ||
2093 | static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, | |
2094 | uint32_t value) | |
2095 | { | |
2096 | struct amdgpu_device *adev = ctx; | |
2097 | ||
2098 | return dm_write_reg(adev->dm.dc->ctx, address, value); | |
2099 | } | |
2100 | ||
2101 | static int dm_dmub_sw_init(struct amdgpu_device *adev) | |
2102 | { | |
2103 | struct dmub_srv_create_params create_params; | |
8c7aea40 NK |
2104 | struct dmub_srv_region_params region_params; |
2105 | struct dmub_srv_region_info region_info; | |
5911d02c | 2106 | struct dmub_srv_memory_params memory_params; |
8c7aea40 NK |
2107 | struct dmub_srv_fb_info *fb_info; |
2108 | struct dmub_srv *dmub_srv; | |
743b9786 | 2109 | const struct dmcub_firmware_header_v1_0 *hdr; |
743b9786 NK |
2110 | enum dmub_asic dmub_asic; |
2111 | enum dmub_status status; | |
2112 | int r; | |
2113 | ||
4e8303cf | 2114 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
c08182f2 | 2115 | case IP_VERSION(2, 1, 0): |
743b9786 | 2116 | dmub_asic = DMUB_ASIC_DCN21; |
743b9786 | 2117 | break; |
c08182f2 | 2118 | case IP_VERSION(3, 0, 0): |
35a45d63 | 2119 | dmub_asic = DMUB_ASIC_DCN30; |
79037324 | 2120 | break; |
c08182f2 | 2121 | case IP_VERSION(3, 0, 1): |
469989ca | 2122 | dmub_asic = DMUB_ASIC_DCN301; |
469989ca | 2123 | break; |
c08182f2 | 2124 | case IP_VERSION(3, 0, 2): |
2a411205 | 2125 | dmub_asic = DMUB_ASIC_DCN302; |
2a411205 | 2126 | break; |
c08182f2 | 2127 | case IP_VERSION(3, 0, 3): |
656fe9b6 | 2128 | dmub_asic = DMUB_ASIC_DCN303; |
656fe9b6 | 2129 | break; |
c08182f2 AD |
2130 | case IP_VERSION(3, 1, 2): |
2131 | case IP_VERSION(3, 1, 3): | |
3137f792 | 2132 | dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; |
1ebcaebd | 2133 | break; |
e850f6b1 RL |
2134 | case IP_VERSION(3, 1, 4): |
2135 | dmub_asic = DMUB_ASIC_DCN314; | |
e850f6b1 | 2136 | break; |
b5b8ed44 QZ |
2137 | case IP_VERSION(3, 1, 5): |
2138 | dmub_asic = DMUB_ASIC_DCN315; | |
b5b8ed44 | 2139 | break; |
de7cc1b4 | 2140 | case IP_VERSION(3, 1, 6): |
868f4357 | 2141 | dmub_asic = DMUB_ASIC_DCN316; |
de7cc1b4 | 2142 | break; |
577359ca AP |
2143 | case IP_VERSION(3, 2, 0): |
2144 | dmub_asic = DMUB_ASIC_DCN32; | |
577359ca AP |
2145 | break; |
2146 | case IP_VERSION(3, 2, 1): | |
2147 | dmub_asic = DMUB_ASIC_DCN321; | |
577359ca | 2148 | break; |
06b1661e QZ |
2149 | case IP_VERSION(3, 5, 0): |
2150 | dmub_asic = DMUB_ASIC_DCN35; | |
2151 | break; | |
743b9786 NK |
2152 | default: |
2153 | /* ASIC doesn't support DMUB. */ | |
2154 | return 0; | |
2155 | } | |
2156 | ||
743b9786 | 2157 | hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; |
72a74a18 | 2158 | adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); |
743b9786 | 2159 | |
9a6ed547 NK |
2160 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
2161 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = | |
2162 | AMDGPU_UCODE_ID_DMCUB; | |
2163 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = | |
2164 | adev->dm.dmub_fw; | |
2165 | adev->firmware.fw_size += | |
2166 | ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); | |
743b9786 | 2167 | |
9a6ed547 NK |
2168 | DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", |
2169 | adev->dm.dmcub_fw_version); | |
2170 | } | |
2171 | ||
743b9786 | 2172 | |
8c7aea40 NK |
2173 | adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); |
2174 | dmub_srv = adev->dm.dmub_srv; | |
2175 | ||
2176 | if (!dmub_srv) { | |
2177 | DRM_ERROR("Failed to allocate DMUB service!\n"); | |
2178 | return -ENOMEM; | |
2179 | } | |
2180 | ||
2181 | memset(&create_params, 0, sizeof(create_params)); | |
2182 | create_params.user_ctx = adev; | |
2183 | create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; | |
2184 | create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; | |
2185 | create_params.asic = dmub_asic; | |
2186 | ||
2187 | /* Create the DMUB service. */ | |
2188 | status = dmub_srv_create(dmub_srv, &create_params); | |
2189 | if (status != DMUB_STATUS_OK) { | |
2190 | DRM_ERROR("Error creating DMUB service: %d\n", status); | |
2191 | return -EINVAL; | |
2192 | } | |
2193 | ||
2194 | /* Calculate the size of all the regions for the DMUB service. */ | |
2195 | memset(®ion_params, 0, sizeof(region_params)); | |
2196 | ||
2197 | region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - | |
2198 | PSP_HEADER_BYTES - PSP_FOOTER_BYTES; | |
2199 | region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); | |
2200 | region_params.vbios_size = adev->bios_size; | |
0922b899 | 2201 | region_params.fw_bss_data = region_params.bss_data_size ? |
1f0674fd NK |
2202 | adev->dm.dmub_fw->data + |
2203 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
0922b899 | 2204 | le32_to_cpu(hdr->inst_const_bytes) : NULL; |
a576b345 NK |
2205 | region_params.fw_inst_const = |
2206 | adev->dm.dmub_fw->data + | |
2207 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
2208 | PSP_HEADER_BYTES; | |
5911d02c | 2209 | region_params.is_mailbox_in_inbox = false; |
8c7aea40 NK |
2210 | |
2211 | status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, | |
2212 | ®ion_info); | |
2213 | ||
2214 | if (status != DMUB_STATUS_OK) { | |
2215 | DRM_ERROR("Error calculating DMUB region info: %d\n", status); | |
2216 | return -EINVAL; | |
2217 | } | |
2218 | ||
2219 | /* | |
2220 | * Allocate a framebuffer based on the total size of all the regions. | |
2221 | * TODO: Move this into GART. | |
2222 | */ | |
2223 | r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, | |
58ab2c08 CK |
2224 | AMDGPU_GEM_DOMAIN_VRAM | |
2225 | AMDGPU_GEM_DOMAIN_GTT, | |
2226 | &adev->dm.dmub_bo, | |
8c7aea40 NK |
2227 | &adev->dm.dmub_bo_gpu_addr, |
2228 | &adev->dm.dmub_bo_cpu_addr); | |
2229 | if (r) | |
2230 | return r; | |
2231 | ||
2232 | /* Rebase the regions on the framebuffer address. */ | |
5911d02c LH |
2233 | memset(&memory_params, 0, sizeof(memory_params)); |
2234 | memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; | |
2235 | memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; | |
2236 | memory_params.region_info = ®ion_info; | |
8c7aea40 NK |
2237 | |
2238 | adev->dm.dmub_fb_info = | |
2239 | kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); | |
2240 | fb_info = adev->dm.dmub_fb_info; | |
2241 | ||
2242 | if (!fb_info) { | |
2243 | DRM_ERROR( | |
2244 | "Failed to allocate framebuffer info for DMUB service!\n"); | |
2245 | return -ENOMEM; | |
2246 | } | |
2247 | ||
5911d02c | 2248 | status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); |
8c7aea40 NK |
2249 | if (status != DMUB_STATUS_OK) { |
2250 | DRM_ERROR("Error calculating DMUB FB info: %d\n", status); | |
2251 | return -EINVAL; | |
2252 | } | |
2253 | ||
743b9786 NK |
2254 | return 0; |
2255 | } | |
2256 | ||
a94d5569 DF |
2257 | static int dm_sw_init(void *handle) |
2258 | { | |
2259 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
743b9786 NK |
2260 | int r; |
2261 | ||
2262 | r = dm_dmub_sw_init(adev); | |
2263 | if (r) | |
2264 | return r; | |
a94d5569 DF |
2265 | |
2266 | return load_dmcu_fw(adev); | |
2267 | } | |
2268 | ||
4562236b HW |
2269 | static int dm_sw_fini(void *handle) |
2270 | { | |
a94d5569 DF |
2271 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2272 | ||
8c7aea40 NK |
2273 | kfree(adev->dm.dmub_fb_info); |
2274 | adev->dm.dmub_fb_info = NULL; | |
2275 | ||
743b9786 NK |
2276 | if (adev->dm.dmub_srv) { |
2277 | dmub_srv_destroy(adev->dm.dmub_srv); | |
2278 | adev->dm.dmub_srv = NULL; | |
2279 | } | |
2280 | ||
51526637 ML |
2281 | amdgpu_ucode_release(&adev->dm.dmub_fw); |
2282 | amdgpu_ucode_release(&adev->dm.fw_dmcu); | |
a94d5569 | 2283 | |
4562236b HW |
2284 | return 0; |
2285 | } | |
2286 | ||
7abcf6b5 | 2287 | static int detect_mst_link_for_all_connectors(struct drm_device *dev) |
4562236b | 2288 | { |
c84dec2f | 2289 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2290 | struct drm_connector *connector; |
f8d2d39e | 2291 | struct drm_connector_list_iter iter; |
7abcf6b5 | 2292 | int ret = 0; |
4562236b | 2293 | |
f8d2d39e LP |
2294 | drm_connector_list_iter_begin(dev, &iter); |
2295 | drm_for_each_connector_iter(connector, &iter) { | |
7db7ade2 HW |
2296 | |
2297 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) | |
2298 | continue; | |
2299 | ||
b349f76e | 2300 | aconnector = to_amdgpu_dm_connector(connector); |
30ec2b97 JFZ |
2301 | if (aconnector->dc_link->type == dc_connection_mst_branch && |
2302 | aconnector->mst_mgr.aux) { | |
f1ad2f5e | 2303 | DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", |
f8d2d39e LP |
2304 | aconnector, |
2305 | aconnector->base.base.id); | |
7abcf6b5 AG |
2306 | |
2307 | ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); | |
2308 | if (ret < 0) { | |
2309 | DRM_ERROR("DM_MST: Failed to start MST\n"); | |
f8d2d39e LP |
2310 | aconnector->dc_link->type = |
2311 | dc_connection_single; | |
3f6752b4 RL |
2312 | ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
2313 | aconnector->dc_link); | |
f8d2d39e | 2314 | break; |
7abcf6b5 | 2315 | } |
f8d2d39e | 2316 | } |
4562236b | 2317 | } |
f8d2d39e | 2318 | drm_connector_list_iter_end(&iter); |
4562236b | 2319 | |
7abcf6b5 AG |
2320 | return ret; |
2321 | } | |
2322 | ||
2323 | static int dm_late_init(void *handle) | |
2324 | { | |
42e67c3b | 2325 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7abcf6b5 | 2326 | |
bbf854dc DF |
2327 | struct dmcu_iram_parameters params; |
2328 | unsigned int linear_lut[16]; | |
2329 | int i; | |
17bdb4a8 | 2330 | struct dmcu *dmcu = NULL; |
bbf854dc | 2331 | |
17bdb4a8 JFZ |
2332 | dmcu = adev->dm.dc->res_pool->dmcu; |
2333 | ||
bbf854dc DF |
2334 | for (i = 0; i < 16; i++) |
2335 | linear_lut[i] = 0xFFFF * i / 15; | |
2336 | ||
2337 | params.set = 0; | |
75068994 | 2338 | params.backlight_ramping_override = false; |
bbf854dc DF |
2339 | params.backlight_ramping_start = 0xCCCC; |
2340 | params.backlight_ramping_reduction = 0xCCCCCCCC; | |
2341 | params.backlight_lut_array_size = 16; | |
2342 | params.backlight_lut_array = linear_lut; | |
2343 | ||
2ad0cdf9 AK |
2344 | /* Min backlight level after ABM reduction, Don't allow below 1% |
2345 | * 0xFFFF x 0.01 = 0x28F | |
2346 | */ | |
2347 | params.min_abm_backlight = 0x28F; | |
5cb32419 | 2348 | /* In the case where abm is implemented on dmcub, |
3335a135 UKK |
2349 | * dmcu object will be null. |
2350 | * ABM 2.4 and up are implemented on dmcub. | |
2351 | */ | |
6e568e43 JW |
2352 | if (dmcu) { |
2353 | if (!dmcu_load_iram(dmcu, params)) | |
2354 | return -EINVAL; | |
2355 | } else if (adev->dm.dc->ctx->dmub_srv) { | |
2356 | struct dc_link *edp_links[MAX_NUM_EDP]; | |
2357 | int edp_num; | |
bbf854dc | 2358 | |
7ae1dbe6 | 2359 | dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); |
6e568e43 JW |
2360 | for (i = 0; i < edp_num; i++) { |
2361 | if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) | |
2362 | return -EINVAL; | |
2363 | } | |
2364 | } | |
bbf854dc | 2365 | |
4a580877 | 2366 | return detect_mst_link_for_all_connectors(adev_to_drm(adev)); |
4562236b HW |
2367 | } |
2368 | ||
ec5fa9fc WL |
2369 | static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) |
2370 | { | |
2371 | int ret; | |
2372 | u8 guid[16]; | |
2373 | u64 tmp64; | |
2374 | ||
2375 | mutex_lock(&mgr->lock); | |
2376 | if (!mgr->mst_primary) | |
2377 | goto out_fail; | |
2378 | ||
2379 | if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { | |
2380 | drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); | |
2381 | goto out_fail; | |
2382 | } | |
2383 | ||
2384 | ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, | |
2385 | DP_MST_EN | | |
2386 | DP_UP_REQ_EN | | |
2387 | DP_UPSTREAM_IS_SRC); | |
2388 | if (ret < 0) { | |
2389 | drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); | |
2390 | goto out_fail; | |
2391 | } | |
2392 | ||
2393 | /* Some hubs forget their guids after they resume */ | |
2394 | ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16); | |
2395 | if (ret != 16) { | |
2396 | drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); | |
2397 | goto out_fail; | |
2398 | } | |
2399 | ||
2400 | if (memchr_inv(guid, 0, 16) == NULL) { | |
2401 | tmp64 = get_jiffies_64(); | |
2402 | memcpy(&guid[0], &tmp64, sizeof(u64)); | |
2403 | memcpy(&guid[8], &tmp64, sizeof(u64)); | |
2404 | ||
2405 | ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16); | |
2406 | ||
2407 | if (ret != 16) { | |
2408 | drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); | |
2409 | goto out_fail; | |
2410 | } | |
2411 | } | |
2412 | ||
2413 | memcpy(mgr->mst_primary->guid, guid, 16); | |
2414 | ||
2415 | out_fail: | |
2416 | mutex_unlock(&mgr->lock); | |
2417 | } | |
2418 | ||
4562236b HW |
2419 | static void s3_handle_mst(struct drm_device *dev, bool suspend) |
2420 | { | |
c84dec2f | 2421 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2422 | struct drm_connector *connector; |
f8d2d39e | 2423 | struct drm_connector_list_iter iter; |
fe7553be | 2424 | struct drm_dp_mst_topology_mgr *mgr; |
4562236b | 2425 | |
f8d2d39e LP |
2426 | drm_connector_list_iter_begin(dev, &iter); |
2427 | drm_for_each_connector_iter(connector, &iter) { | |
7db7ade2 HW |
2428 | |
2429 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) | |
2430 | continue; | |
2431 | ||
fe7553be LP |
2432 | aconnector = to_amdgpu_dm_connector(connector); |
2433 | if (aconnector->dc_link->type != dc_connection_mst_branch || | |
f0127cb1 | 2434 | aconnector->mst_root) |
fe7553be LP |
2435 | continue; |
2436 | ||
2437 | mgr = &aconnector->mst_mgr; | |
2438 | ||
2439 | if (suspend) { | |
2440 | drm_dp_mst_topology_mgr_suspend(mgr); | |
2441 | } else { | |
1e5d4d8e RL |
2442 | /* if extended timeout is supported in hardware, |
2443 | * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer | |
2444 | * CTS 4.2.1.1 regression introduced by CTS specs requirement update. | |
2445 | */ | |
2446 | try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); | |
2447 | if (!dp_is_lttpr_present(aconnector->dc_link)) | |
2448 | try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); | |
2449 | ||
ec5fa9fc WL |
2450 | /* TODO: move resume_mst_branch_status() into drm mst resume again |
2451 | * once topology probing work is pulled out from mst resume into mst | |
2452 | * resume 2nd step. mst resume 2nd step should be called after old | |
2453 | * state getting restored (i.e. drm_atomic_helper_resume()). | |
2454 | */ | |
2455 | resume_mst_branch_status(mgr); | |
fe7553be | 2456 | } |
4562236b | 2457 | } |
f8d2d39e | 2458 | drm_connector_list_iter_end(&iter); |
4562236b HW |
2459 | } |
2460 | ||
9340dfd3 HW |
2461 | static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) |
2462 | { | |
9340dfd3 HW |
2463 | int ret = 0; |
2464 | ||
9340dfd3 HW |
2465 | /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends |
2466 | * on window driver dc implementation. | |
2467 | * For Navi1x, clock settings of dcn watermarks are fixed. the settings | |
2468 | * should be passed to smu during boot up and resume from s3. | |
2469 | * boot up: dc calculate dcn watermark clock settings within dc_create, | |
2470 | * dcn20_resource_construct | |
2471 | * then call pplib functions below to pass the settings to smu: | |
2472 | * smu_set_watermarks_for_clock_ranges | |
2473 | * smu_set_watermarks_table | |
2474 | * navi10_set_watermarks_table | |
2475 | * smu_write_watermarks_table | |
2476 | * | |
2477 | * For Renoir, clock settings of dcn watermark are also fixed values. | |
2478 | * dc has implemented different flow for window driver: | |
2479 | * dc_hardware_init / dc_set_power_state | |
2480 | * dcn10_init_hw | |
2481 | * notify_wm_ranges | |
2482 | * set_wm_ranges | |
2483 | * -- Linux | |
2484 | * smu_set_watermarks_for_clock_ranges | |
2485 | * renoir_set_watermarks_table | |
2486 | * smu_write_watermarks_table | |
2487 | * | |
2488 | * For Linux, | |
2489 | * dc_hardware_init -> amdgpu_dm_init | |
2490 | * dc_set_power_state --> dm_resume | |
2491 | * | |
2492 | * therefore, this function apply to navi10/12/14 but not Renoir | |
2493 | * * | |
2494 | */ | |
4e8303cf | 2495 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
c08182f2 AD |
2496 | case IP_VERSION(2, 0, 2): |
2497 | case IP_VERSION(2, 0, 0): | |
9340dfd3 HW |
2498 | break; |
2499 | default: | |
2500 | return 0; | |
2501 | } | |
2502 | ||
13f5dbd6 | 2503 | ret = amdgpu_dpm_write_watermarks_table(adev); |
e7a95eea EQ |
2504 | if (ret) { |
2505 | DRM_ERROR("Failed to update WMTABLE!\n"); | |
2506 | return ret; | |
9340dfd3 HW |
2507 | } |
2508 | ||
9340dfd3 HW |
2509 | return 0; |
2510 | } | |
2511 | ||
b8592b48 LL |
2512 | /** |
2513 | * dm_hw_init() - Initialize DC device | |
28d687ea | 2514 | * @handle: The base driver device containing the amdgpu_dm device. |
b8592b48 LL |
2515 | * |
2516 | * Initialize the &struct amdgpu_display_manager device. This involves calling | |
2517 | * the initializers of each DM component, then populating the struct with them. | |
2518 | * | |
2519 | * Although the function implies hardware initialization, both hardware and | |
2520 | * software are initialized here. Splitting them out to their relevant init | |
2521 | * hooks is a future TODO item. | |
2522 | * | |
2523 | * Some notable things that are initialized here: | |
2524 | * | |
2525 | * - Display Core, both software and hardware | |
2526 | * - DC modules that we need (freesync and color management) | |
2527 | * - DRM software states | |
2528 | * - Interrupt sources and handlers | |
2529 | * - Vblank support | |
2530 | * - Debug FS entries, if enabled | |
2531 | */ | |
4562236b HW |
2532 | static int dm_hw_init(void *handle) |
2533 | { | |
2534 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
2535 | /* Create DAL display manager */ | |
2536 | amdgpu_dm_init(adev); | |
4562236b HW |
2537 | amdgpu_dm_hpd_init(adev); |
2538 | ||
4562236b HW |
2539 | return 0; |
2540 | } | |
2541 | ||
b8592b48 LL |
2542 | /** |
2543 | * dm_hw_fini() - Teardown DC device | |
28d687ea | 2544 | * @handle: The base driver device containing the amdgpu_dm device. |
b8592b48 LL |
2545 | * |
2546 | * Teardown components within &struct amdgpu_display_manager that require | |
2547 | * cleanup. This involves cleaning up the DRM device, DC, and any modules that | |
2548 | * were loaded. Also flush IRQ workqueues and disable them. | |
2549 | */ | |
4562236b HW |
2550 | static int dm_hw_fini(void *handle) |
2551 | { | |
2552 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
2553 | ||
2554 | amdgpu_dm_hpd_fini(adev); | |
2555 | ||
2556 | amdgpu_dm_irq_fini(adev); | |
21de3396 | 2557 | amdgpu_dm_fini(adev); |
4562236b HW |
2558 | return 0; |
2559 | } | |
2560 | ||
cdaae837 | 2561 | |
cdaae837 BL |
2562 | static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, |
2563 | struct dc_state *state, bool enable) | |
2564 | { | |
2565 | enum dc_irq_source irq_source; | |
2566 | struct amdgpu_crtc *acrtc; | |
2567 | int rc = -EBUSY; | |
2568 | int i = 0; | |
2569 | ||
2570 | for (i = 0; i < state->stream_count; i++) { | |
2571 | acrtc = get_crtc_by_otg_inst( | |
2572 | adev, state->stream_status[i].primary_otg_inst); | |
2573 | ||
2574 | if (acrtc && state->stream_status[i].plane_count != 0) { | |
2575 | irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; | |
2576 | rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; | |
cdaae837 BL |
2577 | if (rc) |
2578 | DRM_WARN("Failed to %s pflip interrupts\n", | |
2579 | enable ? "enable" : "disable"); | |
2580 | ||
2581 | if (enable) { | |
cd465a67 AL |
2582 | if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) |
2583 | rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); | |
2584 | } else | |
2585 | rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); | |
cdaae837 | 2586 | |
cd465a67 AL |
2587 | if (rc) |
2588 | DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); | |
cdaae837 | 2589 | |
cd465a67 AL |
2590 | irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; |
2591 | /* During gpu-reset we disable and then enable vblank irq, so | |
2592 | * don't use amdgpu_irq_get/put() to avoid refcount change. | |
2593 | */ | |
2594 | if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) | |
2595 | DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); | |
cdaae837 BL |
2596 | } |
2597 | } | |
2598 | ||
2599 | } | |
2600 | ||
dfd84d90 | 2601 | static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) |
cdaae837 BL |
2602 | { |
2603 | struct dc_state *context = NULL; | |
2604 | enum dc_status res = DC_ERROR_UNEXPECTED; | |
2605 | int i; | |
2606 | struct dc_stream_state *del_streams[MAX_PIPES]; | |
2607 | int del_streams_count = 0; | |
2608 | ||
2609 | memset(del_streams, 0, sizeof(del_streams)); | |
2610 | ||
2611 | context = dc_create_state(dc); | |
2612 | if (context == NULL) | |
2613 | goto context_alloc_fail; | |
2614 | ||
2615 | dc_resource_state_copy_construct_current(dc, context); | |
2616 | ||
2617 | /* First remove from context all streams */ | |
2618 | for (i = 0; i < context->stream_count; i++) { | |
2619 | struct dc_stream_state *stream = context->streams[i]; | |
2620 | ||
2621 | del_streams[del_streams_count++] = stream; | |
2622 | } | |
2623 | ||
2624 | /* Remove all planes for removed streams and then remove the streams */ | |
2625 | for (i = 0; i < del_streams_count; i++) { | |
2626 | if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { | |
2627 | res = DC_FAIL_DETACH_SURFACES; | |
2628 | goto fail; | |
2629 | } | |
2630 | ||
2631 | res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); | |
2632 | if (res != DC_OK) | |
2633 | goto fail; | |
2634 | } | |
2635 | ||
b8272241 | 2636 | res = dc_commit_streams(dc, context->streams, context->stream_count); |
cdaae837 BL |
2637 | |
2638 | fail: | |
2639 | dc_release_state(context); | |
2640 | ||
2641 | context_alloc_fail: | |
2642 | return res; | |
2643 | } | |
2644 | ||
8e794421 WL |
2645 | static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) |
2646 | { | |
2647 | int i; | |
2648 | ||
2649 | if (dm->hpd_rx_offload_wq) { | |
2650 | for (i = 0; i < dm->dc->caps.max_links; i++) | |
2651 | flush_workqueue(dm->hpd_rx_offload_wq[i].wq); | |
2652 | } | |
2653 | } | |
2654 | ||
4562236b HW |
2655 | static int dm_suspend(void *handle) |
2656 | { | |
2657 | struct amdgpu_device *adev = handle; | |
2658 | struct amdgpu_display_manager *dm = &adev->dm; | |
2659 | int ret = 0; | |
4562236b | 2660 | |
53b3f8f4 | 2661 | if (amdgpu_in_reset(adev)) { |
cdaae837 | 2662 | mutex_lock(&dm->dc_lock); |
98ab5f35 | 2663 | |
98ab5f35 | 2664 | dc_allow_idle_optimizations(adev->dm.dc, false); |
98ab5f35 | 2665 | |
cdaae837 BL |
2666 | dm->cached_dc_state = dc_copy_state(dm->dc->current_state); |
2667 | ||
2668 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); | |
2669 | ||
2670 | amdgpu_dm_commit_zero_streams(dm->dc); | |
2671 | ||
2672 | amdgpu_dm_irq_suspend(adev); | |
2673 | ||
8e794421 WL |
2674 | hpd_rx_irq_work_suspend(dm); |
2675 | ||
cdaae837 BL |
2676 | return ret; |
2677 | } | |
4562236b | 2678 | |
d2f0b53b | 2679 | WARN_ON(adev->dm.cached_state); |
4a580877 | 2680 | adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); |
f7fbf79f ML |
2681 | if (IS_ERR(adev->dm.cached_state)) |
2682 | return PTR_ERR(adev->dm.cached_state); | |
d2f0b53b | 2683 | |
4a580877 | 2684 | s3_handle_mst(adev_to_drm(adev), true); |
4562236b | 2685 | |
4562236b HW |
2686 | amdgpu_dm_irq_suspend(adev); |
2687 | ||
8e794421 WL |
2688 | hpd_rx_irq_work_suspend(dm); |
2689 | ||
32f5062d | 2690 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); |
4562236b | 2691 | |
1c2075d4 | 2692 | return 0; |
4562236b HW |
2693 | } |
2694 | ||
748b091d | 2695 | struct drm_connector * |
1daf8c63 AD |
2696 | amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, |
2697 | struct drm_crtc *crtc) | |
4562236b | 2698 | { |
ae67558b | 2699 | u32 i; |
c2cea706 | 2700 | struct drm_connector_state *new_con_state; |
4562236b HW |
2701 | struct drm_connector *connector; |
2702 | struct drm_crtc *crtc_from_state; | |
2703 | ||
c2cea706 LSL |
2704 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
2705 | crtc_from_state = new_con_state->crtc; | |
4562236b HW |
2706 | |
2707 | if (crtc_from_state == crtc) | |
748b091d | 2708 | return connector; |
4562236b HW |
2709 | } |
2710 | ||
2711 | return NULL; | |
2712 | } | |
2713 | ||
fbbdadf2 BL |
2714 | static void emulated_link_detect(struct dc_link *link) |
2715 | { | |
2716 | struct dc_sink_init_data sink_init_data = { 0 }; | |
2717 | struct display_sink_capability sink_caps = { 0 }; | |
2718 | enum dc_edid_status edid_status; | |
2719 | struct dc_context *dc_ctx = link->ctx; | |
5d72e247 | 2720 | struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); |
fbbdadf2 BL |
2721 | struct dc_sink *sink = NULL; |
2722 | struct dc_sink *prev_sink = NULL; | |
2723 | ||
2724 | link->type = dc_connection_none; | |
2725 | prev_sink = link->local_sink; | |
2726 | ||
30164a16 VL |
2727 | if (prev_sink) |
2728 | dc_sink_release(prev_sink); | |
fbbdadf2 BL |
2729 | |
2730 | switch (link->connector_signal) { | |
2731 | case SIGNAL_TYPE_HDMI_TYPE_A: { | |
2732 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2733 | sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; | |
2734 | break; | |
2735 | } | |
2736 | ||
2737 | case SIGNAL_TYPE_DVI_SINGLE_LINK: { | |
2738 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2739 | sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; | |
2740 | break; | |
2741 | } | |
2742 | ||
2743 | case SIGNAL_TYPE_DVI_DUAL_LINK: { | |
2744 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2745 | sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; | |
2746 | break; | |
2747 | } | |
2748 | ||
2749 | case SIGNAL_TYPE_LVDS: { | |
2750 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2751 | sink_caps.signal = SIGNAL_TYPE_LVDS; | |
2752 | break; | |
2753 | } | |
2754 | ||
2755 | case SIGNAL_TYPE_EDP: { | |
2756 | sink_caps.transaction_type = | |
2757 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
2758 | sink_caps.signal = SIGNAL_TYPE_EDP; | |
2759 | break; | |
2760 | } | |
2761 | ||
2762 | case SIGNAL_TYPE_DISPLAY_PORT: { | |
2763 | sink_caps.transaction_type = | |
2764 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
2765 | sink_caps.signal = SIGNAL_TYPE_VIRTUAL; | |
2766 | break; | |
2767 | } | |
2768 | ||
2769 | default: | |
5d72e247 | 2770 | drm_err(dev, "Invalid connector type! signal:%d\n", |
fbbdadf2 BL |
2771 | link->connector_signal); |
2772 | return; | |
2773 | } | |
2774 | ||
2775 | sink_init_data.link = link; | |
2776 | sink_init_data.sink_signal = sink_caps.signal; | |
2777 | ||
2778 | sink = dc_sink_create(&sink_init_data); | |
2779 | if (!sink) { | |
5d72e247 | 2780 | drm_err(dev, "Failed to create sink!\n"); |
fbbdadf2 BL |
2781 | return; |
2782 | } | |
2783 | ||
dcd5fb82 | 2784 | /* dc_sink_create returns a new reference */ |
fbbdadf2 BL |
2785 | link->local_sink = sink; |
2786 | ||
2787 | edid_status = dm_helpers_read_local_edid( | |
2788 | link->ctx, | |
2789 | link, | |
2790 | sink); | |
2791 | ||
2792 | if (edid_status != EDID_OK) | |
5d72e247 | 2793 | drm_err(dev, "Failed to read EDID\n"); |
fbbdadf2 BL |
2794 | |
2795 | } | |
2796 | ||
cdaae837 BL |
2797 | static void dm_gpureset_commit_state(struct dc_state *dc_state, |
2798 | struct amdgpu_display_manager *dm) | |
2799 | { | |
2800 | struct { | |
2801 | struct dc_surface_update surface_updates[MAX_SURFACES]; | |
2802 | struct dc_plane_info plane_infos[MAX_SURFACES]; | |
2803 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; | |
2804 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; | |
2805 | struct dc_stream_update stream_update; | |
c82eddf8 | 2806 | } *bundle; |
cdaae837 BL |
2807 | int k, m; |
2808 | ||
2809 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); | |
2810 | ||
2811 | if (!bundle) { | |
5d72e247 | 2812 | drm_err(dm->ddev, "Failed to allocate update bundle\n"); |
cdaae837 BL |
2813 | goto cleanup; |
2814 | } | |
2815 | ||
2816 | for (k = 0; k < dc_state->stream_count; k++) { | |
2817 | bundle->stream_update.stream = dc_state->streams[k]; | |
2818 | ||
2819 | for (m = 0; m < dc_state->stream_status->plane_count; m++) { | |
2820 | bundle->surface_updates[m].surface = | |
2821 | dc_state->stream_status->plane_states[m]; | |
2822 | bundle->surface_updates[m].surface->force_full_update = | |
2823 | true; | |
2824 | } | |
f7511289 | 2825 | |
81f743a0 RS |
2826 | update_planes_and_stream_adapter(dm->dc, |
2827 | UPDATE_TYPE_FULL, | |
2828 | dc_state->stream_status->plane_count, | |
2829 | dc_state->streams[k], | |
2830 | &bundle->stream_update, | |
2831 | bundle->surface_updates); | |
cdaae837 BL |
2832 | } |
2833 | ||
2834 | cleanup: | |
2835 | kfree(bundle); | |
cdaae837 BL |
2836 | } |
2837 | ||
4562236b HW |
2838 | static int dm_resume(void *handle) |
2839 | { | |
2840 | struct amdgpu_device *adev = handle; | |
4a580877 | 2841 | struct drm_device *ddev = adev_to_drm(adev); |
4562236b | 2842 | struct amdgpu_display_manager *dm = &adev->dm; |
c84dec2f | 2843 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2844 | struct drm_connector *connector; |
f8d2d39e | 2845 | struct drm_connector_list_iter iter; |
4562236b | 2846 | struct drm_crtc *crtc; |
c2cea706 | 2847 | struct drm_crtc_state *new_crtc_state; |
fcb4019e LSL |
2848 | struct dm_crtc_state *dm_new_crtc_state; |
2849 | struct drm_plane *plane; | |
2850 | struct drm_plane_state *new_plane_state; | |
2851 | struct dm_plane_state *dm_new_plane_state; | |
113b7a01 | 2852 | struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); |
fbbdadf2 | 2853 | enum dc_connection_type new_connection_type = dc_connection_none; |
cdaae837 | 2854 | struct dc_state *dc_state; |
ec5fa9fc WL |
2855 | int i, r, j, ret; |
2856 | bool need_hotplug = false; | |
4562236b | 2857 | |
06b1661e QZ |
2858 | if (dm->dc->caps.ips_support) { |
2859 | dc_dmub_srv_exit_low_power_state(dm->dc); | |
2860 | } | |
2861 | ||
53b3f8f4 | 2862 | if (amdgpu_in_reset(adev)) { |
cdaae837 BL |
2863 | dc_state = dm->cached_dc_state; |
2864 | ||
6d63fcc2 NK |
2865 | /* |
2866 | * The dc->current_state is backed up into dm->cached_dc_state | |
2867 | * before we commit 0 streams. | |
2868 | * | |
2869 | * DC will clear link encoder assignments on the real state | |
2870 | * but the changes won't propagate over to the copy we made | |
2871 | * before the 0 streams commit. | |
2872 | * | |
2873 | * DC expects that link encoder assignments are *not* valid | |
32685b32 NK |
2874 | * when committing a state, so as a workaround we can copy |
2875 | * off of the current state. | |
2876 | * | |
2877 | * We lose the previous assignments, but we had already | |
2878 | * commit 0 streams anyway. | |
6d63fcc2 | 2879 | */ |
32685b32 | 2880 | link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); |
6d63fcc2 | 2881 | |
cdaae837 BL |
2882 | r = dm_dmub_hw_init(adev); |
2883 | if (r) | |
2884 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); | |
2885 | ||
2886 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); | |
7441ef0b | 2887 | |
cdaae837 BL |
2888 | dc_resume(dm->dc); |
2889 | ||
2890 | amdgpu_dm_irq_resume_early(adev); | |
2891 | ||
2892 | for (i = 0; i < dc_state->stream_count; i++) { | |
2893 | dc_state->streams[i]->mode_changed = true; | |
6984fa41 NK |
2894 | for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { |
2895 | dc_state->stream_status[i].plane_states[j]->update_flags.raw | |
cdaae837 BL |
2896 | = 0xffffffff; |
2897 | } | |
2898 | } | |
2899 | ||
11d526f1 SW |
2900 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
2901 | amdgpu_dm_outbox_init(adev); | |
2902 | dc_enable_dmub_outbox(adev->dm.dc); | |
2903 | } | |
2904 | ||
b8272241 | 2905 | WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); |
4562236b | 2906 | |
cdaae837 BL |
2907 | dm_gpureset_commit_state(dm->cached_dc_state, dm); |
2908 | ||
2909 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); | |
2910 | ||
2911 | dc_release_state(dm->cached_dc_state); | |
2912 | dm->cached_dc_state = NULL; | |
2913 | ||
2914 | amdgpu_dm_irq_resume_late(adev); | |
2915 | ||
2916 | mutex_unlock(&dm->dc_lock); | |
2917 | ||
2918 | return 0; | |
2919 | } | |
113b7a01 LL |
2920 | /* Recreate dc_state - DC invalidates it when setting power state to S3. */ |
2921 | dc_release_state(dm_state->context); | |
2922 | dm_state->context = dc_create_state(dm->dc); | |
2923 | /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ | |
2924 | dc_resource_state_construct(dm->dc, dm_state->context); | |
2925 | ||
8c7aea40 | 2926 | /* Before powering on DC we need to re-initialize DMUB. */ |
79d6b935 | 2927 | dm_dmub_hw_resume(adev); |
8c7aea40 | 2928 | |
11d526f1 SW |
2929 | /* Re-enable outbox interrupts for DPIA. */ |
2930 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { | |
2931 | amdgpu_dm_outbox_init(adev); | |
2932 | dc_enable_dmub_outbox(adev->dm.dc); | |
2933 | } | |
2934 | ||
a80aa93d | 2935 | /* power on hardware */ |
b63eae94 | 2936 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); |
a80aa93d | 2937 | |
4562236b HW |
2938 | /* program HPD filter */ |
2939 | dc_resume(dm->dc); | |
2940 | ||
4562236b HW |
2941 | /* |
2942 | * early enable HPD Rx IRQ, should be done before set mode as short | |
2943 | * pulse interrupts are used for MST | |
2944 | */ | |
2945 | amdgpu_dm_irq_resume_early(adev); | |
2946 | ||
d20ebea8 | 2947 | /* On resume we need to rewrite the MSTM control bits to enable MST*/ |
684cd480 LP |
2948 | s3_handle_mst(ddev, false); |
2949 | ||
4562236b | 2950 | /* Do detection*/ |
f8d2d39e LP |
2951 | drm_connector_list_iter_begin(ddev, &iter); |
2952 | drm_for_each_connector_iter(connector, &iter) { | |
7db7ade2 HW |
2953 | |
2954 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) | |
2955 | continue; | |
2956 | ||
c84dec2f | 2957 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b | 2958 | |
7a7175a2 RL |
2959 | if (!aconnector->dc_link) |
2960 | continue; | |
2961 | ||
4562236b | 2962 | /* |
ec5fa9fc | 2963 | * this is the case when traversing through already created end sink |
4562236b HW |
2964 | * MST connectors, should be skipped |
2965 | */ | |
91b38ca1 | 2966 | if (aconnector && aconnector->mst_root) |
4562236b HW |
2967 | continue; |
2968 | ||
03ea364c | 2969 | mutex_lock(&aconnector->hpd_lock); |
54618888 | 2970 | if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) |
fbbdadf2 BL |
2971 | DRM_ERROR("KMS: Failed to detect connector\n"); |
2972 | ||
15c735e7 | 2973 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
fbbdadf2 | 2974 | emulated_link_detect(aconnector->dc_link); |
15c735e7 WL |
2975 | } else { |
2976 | mutex_lock(&dm->dc_lock); | |
fbbdadf2 | 2977 | dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); |
15c735e7 WL |
2978 | mutex_unlock(&dm->dc_lock); |
2979 | } | |
3eb4eba4 RL |
2980 | |
2981 | if (aconnector->fake_enable && aconnector->dc_link->local_sink) | |
2982 | aconnector->fake_enable = false; | |
2983 | ||
dcd5fb82 MF |
2984 | if (aconnector->dc_sink) |
2985 | dc_sink_release(aconnector->dc_sink); | |
4562236b HW |
2986 | aconnector->dc_sink = NULL; |
2987 | amdgpu_dm_update_connector_after_detect(aconnector); | |
03ea364c | 2988 | mutex_unlock(&aconnector->hpd_lock); |
4562236b | 2989 | } |
f8d2d39e | 2990 | drm_connector_list_iter_end(&iter); |
4562236b | 2991 | |
1f6010a9 | 2992 | /* Force mode set in atomic commit */ |
a80aa93d | 2993 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) |
c2cea706 | 2994 | new_crtc_state->active_changed = true; |
4f346e65 | 2995 | |
fcb4019e LSL |
2996 | /* |
2997 | * atomic_check is expected to create the dc states. We need to release | |
2998 | * them here, since they were duplicated as part of the suspend | |
2999 | * procedure. | |
3000 | */ | |
a80aa93d | 3001 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { |
fcb4019e LSL |
3002 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
3003 | if (dm_new_crtc_state->stream) { | |
3004 | WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); | |
3005 | dc_stream_release(dm_new_crtc_state->stream); | |
3006 | dm_new_crtc_state->stream = NULL; | |
3007 | } | |
3008 | } | |
3009 | ||
a80aa93d | 3010 | for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { |
fcb4019e LSL |
3011 | dm_new_plane_state = to_dm_plane_state(new_plane_state); |
3012 | if (dm_new_plane_state->dc_state) { | |
3013 | WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); | |
3014 | dc_plane_state_release(dm_new_plane_state->dc_state); | |
3015 | dm_new_plane_state->dc_state = NULL; | |
3016 | } | |
3017 | } | |
3018 | ||
2d1af6a1 | 3019 | drm_atomic_helper_resume(ddev, dm->cached_state); |
4562236b | 3020 | |
a80aa93d | 3021 | dm->cached_state = NULL; |
0a214e2f | 3022 | |
ec5fa9fc WL |
3023 | /* Do mst topology probing after resuming cached state*/ |
3024 | drm_connector_list_iter_begin(ddev, &iter); | |
3025 | drm_for_each_connector_iter(connector, &iter) { | |
3026 | aconnector = to_amdgpu_dm_connector(connector); | |
3027 | if (aconnector->dc_link->type != dc_connection_mst_branch || | |
3028 | aconnector->mst_root) | |
3029 | continue; | |
3030 | ||
3031 | ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true); | |
3032 | ||
3033 | if (ret < 0) { | |
3034 | dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, | |
3035 | aconnector->dc_link); | |
3036 | need_hotplug = true; | |
3037 | } | |
3038 | } | |
3039 | drm_connector_list_iter_end(&iter); | |
3040 | ||
3041 | if (need_hotplug) | |
3042 | drm_kms_helper_hotplug_event(ddev); | |
3043 | ||
9faa4237 | 3044 | amdgpu_dm_irq_resume_late(adev); |
4562236b | 3045 | |
9340dfd3 HW |
3046 | amdgpu_dm_smu_write_watermarks_table(adev); |
3047 | ||
2d1af6a1 | 3048 | return 0; |
4562236b HW |
3049 | } |
3050 | ||
b8592b48 LL |
3051 | /** |
3052 | * DOC: DM Lifecycle | |
3053 | * | |
3054 | * DM (and consequently DC) is registered in the amdgpu base driver as a IP | |
3055 | * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to | |
3056 | * the base driver's device list to be initialized and torn down accordingly. | |
3057 | * | |
3058 | * The functions to do so are provided as hooks in &struct amd_ip_funcs. | |
3059 | */ | |
3060 | ||
4562236b HW |
3061 | static const struct amd_ip_funcs amdgpu_dm_funcs = { |
3062 | .name = "dm", | |
3063 | .early_init = dm_early_init, | |
7abcf6b5 | 3064 | .late_init = dm_late_init, |
4562236b HW |
3065 | .sw_init = dm_sw_init, |
3066 | .sw_fini = dm_sw_fini, | |
e9669fb7 | 3067 | .early_fini = amdgpu_dm_early_fini, |
4562236b HW |
3068 | .hw_init = dm_hw_init, |
3069 | .hw_fini = dm_hw_fini, | |
3070 | .suspend = dm_suspend, | |
3071 | .resume = dm_resume, | |
3072 | .is_idle = dm_is_idle, | |
3073 | .wait_for_idle = dm_wait_for_idle, | |
3074 | .check_soft_reset = dm_check_soft_reset, | |
3075 | .soft_reset = dm_soft_reset, | |
3076 | .set_clockgating_state = dm_set_clockgating_state, | |
3077 | .set_powergating_state = dm_set_powergating_state, | |
3078 | }; | |
3079 | ||
c82eddf8 | 3080 | const struct amdgpu_ip_block_version dm_ip_block = { |
4562236b HW |
3081 | .type = AMD_IP_BLOCK_TYPE_DCE, |
3082 | .major = 1, | |
3083 | .minor = 0, | |
3084 | .rev = 0, | |
3085 | .funcs = &amdgpu_dm_funcs, | |
3086 | }; | |
3087 | ||
ca3268c4 | 3088 | |
b8592b48 LL |
3089 | /** |
3090 | * DOC: atomic | |
3091 | * | |
3092 | * *WIP* | |
3093 | */ | |
0a323b84 | 3094 | |
b3663f70 | 3095 | static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { |
4d4772f6 | 3096 | .fb_create = amdgpu_display_user_framebuffer_create, |
8bf0d9cd | 3097 | .get_format_info = amdgpu_dm_plane_get_format_info, |
4562236b | 3098 | .atomic_check = amdgpu_dm_atomic_check, |
0269764a | 3099 | .atomic_commit = drm_atomic_helper_commit, |
54f5499a AG |
3100 | }; |
3101 | ||
3102 | static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { | |
a5c2c0d1 LP |
3103 | .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, |
3104 | .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, | |
4562236b HW |
3105 | }; |
3106 | ||
94562810 RS |
3107 | static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) |
3108 | { | |
94562810 | 3109 | struct amdgpu_dm_backlight_caps *caps; |
94562810 RS |
3110 | struct drm_connector *conn_base; |
3111 | struct amdgpu_device *adev; | |
a61bb342 | 3112 | struct drm_luminance_range_info *luminance_range; |
94562810 | 3113 | |
f196198c HG |
3114 | if (aconnector->bl_idx == -1 || |
3115 | aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) | |
ec11fe37 | 3116 | return; |
3117 | ||
94562810 | 3118 | conn_base = &aconnector->base; |
1348969a | 3119 | adev = drm_to_adev(conn_base->dev); |
f196198c HG |
3120 | |
3121 | caps = &adev->dm.backlight_caps[aconnector->bl_idx]; | |
94562810 RS |
3122 | caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; |
3123 | caps->aux_support = false; | |
94562810 | 3124 | |
c82eddf8 SS |
3125 | if (caps->ext_caps->bits.oled == 1 |
3126 | /* | |
3127 | * || | |
3128 | * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || | |
3129 | * caps->ext_caps->bits.hdr_aux_backlight_control == 1 | |
3130 | */) | |
94562810 RS |
3131 | caps->aux_support = true; |
3132 | ||
7a46f05e TI |
3133 | if (amdgpu_backlight == 0) |
3134 | caps->aux_support = false; | |
3135 | else if (amdgpu_backlight == 1) | |
3136 | caps->aux_support = true; | |
3137 | ||
a61bb342 | 3138 | luminance_range = &conn_base->display_info.luminance_range; |
932698c8 SP |
3139 | |
3140 | if (luminance_range->max_luminance) { | |
3141 | caps->aux_min_input_signal = luminance_range->min_luminance; | |
3142 | caps->aux_max_input_signal = luminance_range->max_luminance; | |
3143 | } else { | |
3144 | caps->aux_min_input_signal = 0; | |
3145 | caps->aux_max_input_signal = 512; | |
3146 | } | |
94562810 RS |
3147 | } |
3148 | ||
97e51c16 HW |
3149 | void amdgpu_dm_update_connector_after_detect( |
3150 | struct amdgpu_dm_connector *aconnector) | |
4562236b HW |
3151 | { |
3152 | struct drm_connector *connector = &aconnector->base; | |
3153 | struct drm_device *dev = connector->dev; | |
b73a22d3 | 3154 | struct dc_sink *sink; |
4562236b HW |
3155 | |
3156 | /* MST handled by drm_mst framework */ | |
3157 | if (aconnector->mst_mgr.mst_state == true) | |
3158 | return; | |
3159 | ||
4562236b | 3160 | sink = aconnector->dc_link->local_sink; |
dcd5fb82 MF |
3161 | if (sink) |
3162 | dc_sink_retain(sink); | |
4562236b | 3163 | |
1f6010a9 DF |
3164 | /* |
3165 | * Edid mgmt connector gets first update only in mode_valid hook and then | |
4562236b | 3166 | * the connector sink is set to either fake or physical sink depends on link status. |
1f6010a9 | 3167 | * Skip if already done during boot. |
4562236b HW |
3168 | */ |
3169 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED | |
3170 | && aconnector->dc_em_sink) { | |
3171 | ||
1f6010a9 DF |
3172 | /* |
3173 | * For S3 resume with headless use eml_sink to fake stream | |
3174 | * because on resume connector->sink is set to NULL | |
4562236b HW |
3175 | */ |
3176 | mutex_lock(&dev->mode_config.mutex); | |
3177 | ||
3178 | if (sink) { | |
922aa1e1 | 3179 | if (aconnector->dc_sink) { |
98e6436d | 3180 | amdgpu_dm_update_freesync_caps(connector, NULL); |
1f6010a9 DF |
3181 | /* |
3182 | * retain and release below are used to | |
3183 | * bump up refcount for sink because the link doesn't point | |
3184 | * to it anymore after disconnect, so on next crtc to connector | |
922aa1e1 AG |
3185 | * reshuffle by UMD we will get into unwanted dc_sink release |
3186 | */ | |
dcd5fb82 | 3187 | dc_sink_release(aconnector->dc_sink); |
922aa1e1 | 3188 | } |
4562236b | 3189 | aconnector->dc_sink = sink; |
dcd5fb82 | 3190 | dc_sink_retain(aconnector->dc_sink); |
98e6436d AK |
3191 | amdgpu_dm_update_freesync_caps(connector, |
3192 | aconnector->edid); | |
4562236b | 3193 | } else { |
98e6436d | 3194 | amdgpu_dm_update_freesync_caps(connector, NULL); |
dcd5fb82 | 3195 | if (!aconnector->dc_sink) { |
4562236b | 3196 | aconnector->dc_sink = aconnector->dc_em_sink; |
922aa1e1 | 3197 | dc_sink_retain(aconnector->dc_sink); |
dcd5fb82 | 3198 | } |
4562236b HW |
3199 | } |
3200 | ||
3201 | mutex_unlock(&dev->mode_config.mutex); | |
dcd5fb82 MF |
3202 | |
3203 | if (sink) | |
3204 | dc_sink_release(sink); | |
4562236b HW |
3205 | return; |
3206 | } | |
3207 | ||
3208 | /* | |
3209 | * TODO: temporary guard to look for proper fix | |
3210 | * if this sink is MST sink, we should not do anything | |
3211 | */ | |
dcd5fb82 MF |
3212 | if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { |
3213 | dc_sink_release(sink); | |
4562236b | 3214 | return; |
dcd5fb82 | 3215 | } |
4562236b HW |
3216 | |
3217 | if (aconnector->dc_sink == sink) { | |
1f6010a9 DF |
3218 | /* |
3219 | * We got a DP short pulse (Link Loss, DP CTS, etc...). | |
3220 | * Do nothing!! | |
3221 | */ | |
f1ad2f5e | 3222 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", |
4562236b | 3223 | aconnector->connector_id); |
dcd5fb82 MF |
3224 | if (sink) |
3225 | dc_sink_release(sink); | |
4562236b HW |
3226 | return; |
3227 | } | |
3228 | ||
f1ad2f5e | 3229 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", |
4562236b HW |
3230 | aconnector->connector_id, aconnector->dc_sink, sink); |
3231 | ||
3232 | mutex_lock(&dev->mode_config.mutex); | |
3233 | ||
1f6010a9 DF |
3234 | /* |
3235 | * 1. Update status of the drm connector | |
3236 | * 2. Send an event and let userspace tell us what to do | |
3237 | */ | |
4562236b | 3238 | if (sink) { |
1f6010a9 DF |
3239 | /* |
3240 | * TODO: check if we still need the S3 mode update workaround. | |
3241 | * If yes, put it here. | |
3242 | */ | |
c64b0d6b | 3243 | if (aconnector->dc_sink) { |
98e6436d | 3244 | amdgpu_dm_update_freesync_caps(connector, NULL); |
c64b0d6b VL |
3245 | dc_sink_release(aconnector->dc_sink); |
3246 | } | |
4562236b HW |
3247 | |
3248 | aconnector->dc_sink = sink; | |
dcd5fb82 | 3249 | dc_sink_retain(aconnector->dc_sink); |
900b3cb1 | 3250 | if (sink->dc_edid.length == 0) { |
4562236b | 3251 | aconnector->edid = NULL; |
e6142dd5 AP |
3252 | if (aconnector->dc_link->aux_mode) { |
3253 | drm_dp_cec_unset_edid( | |
3254 | &aconnector->dm_dp_aux.aux); | |
3255 | } | |
900b3cb1 | 3256 | } else { |
4562236b | 3257 | aconnector->edid = |
e6142dd5 | 3258 | (struct edid *)sink->dc_edid.raw_edid; |
4562236b | 3259 | |
e6142dd5 AP |
3260 | if (aconnector->dc_link->aux_mode) |
3261 | drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, | |
3262 | aconnector->edid); | |
4562236b | 3263 | } |
e6142dd5 | 3264 | |
025ce392 HW |
3265 | if (!aconnector->timing_requested) { |
3266 | aconnector->timing_requested = | |
3267 | kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); | |
3268 | if (!aconnector->timing_requested) | |
5d72e247 HM |
3269 | drm_err(dev, |
3270 | "failed to create aconnector->requested_timing\n"); | |
025ce392 | 3271 | } |
028c4ccf | 3272 | |
20543be9 | 3273 | drm_connector_update_edid_property(connector, aconnector->edid); |
98e6436d | 3274 | amdgpu_dm_update_freesync_caps(connector, aconnector->edid); |
94562810 | 3275 | update_connector_ext_caps(aconnector); |
4562236b | 3276 | } else { |
e86e8947 | 3277 | drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); |
98e6436d | 3278 | amdgpu_dm_update_freesync_caps(connector, NULL); |
c555f023 | 3279 | drm_connector_update_edid_property(connector, NULL); |
4562236b | 3280 | aconnector->num_modes = 0; |
dcd5fb82 | 3281 | dc_sink_release(aconnector->dc_sink); |
4562236b | 3282 | aconnector->dc_sink = NULL; |
5326c452 | 3283 | aconnector->edid = NULL; |
028c4ccf QZ |
3284 | kfree(aconnector->timing_requested); |
3285 | aconnector->timing_requested = NULL; | |
0c8620d6 BL |
3286 | /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ |
3287 | if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) | |
3288 | connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
4562236b HW |
3289 | } |
3290 | ||
3291 | mutex_unlock(&dev->mode_config.mutex); | |
dcd5fb82 | 3292 | |
0f877894 OV |
3293 | update_subconnector_property(aconnector); |
3294 | ||
dcd5fb82 MF |
3295 | if (sink) |
3296 | dc_sink_release(sink); | |
4562236b HW |
3297 | } |
3298 | ||
e27c41d5 | 3299 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) |
4562236b | 3300 | { |
4562236b HW |
3301 | struct drm_connector *connector = &aconnector->base; |
3302 | struct drm_device *dev = connector->dev; | |
fbbdadf2 | 3303 | enum dc_connection_type new_connection_type = dc_connection_none; |
1348969a | 3304 | struct amdgpu_device *adev = drm_to_adev(dev); |
97f6c917 | 3305 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); |
15c735e7 | 3306 | bool ret = false; |
4562236b | 3307 | |
b972b4f9 HW |
3308 | if (adev->dm.disable_hpd_irq) |
3309 | return; | |
3310 | ||
1f6010a9 DF |
3311 | /* |
3312 | * In case of failure or MST no need to update connector status or notify the OS | |
3313 | * since (for MST case) MST does this in its own context. | |
4562236b HW |
3314 | */ |
3315 | mutex_lock(&aconnector->hpd_lock); | |
2e0ac3d6 | 3316 | |
97f6c917 | 3317 | if (adev->dm.hdcp_workqueue) { |
96a3b32e | 3318 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); |
97f6c917 BL |
3319 | dm_con_state->update_hdcp = true; |
3320 | } | |
2e0ac3d6 HW |
3321 | if (aconnector->fake_enable) |
3322 | aconnector->fake_enable = false; | |
3323 | ||
028c4ccf QZ |
3324 | aconnector->timing_changed = false; |
3325 | ||
54618888 | 3326 | if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) |
fbbdadf2 BL |
3327 | DRM_ERROR("KMS: Failed to detect connector\n"); |
3328 | ||
3329 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
3330 | emulated_link_detect(aconnector->dc_link); | |
3331 | ||
fbbdadf2 BL |
3332 | drm_modeset_lock_all(dev); |
3333 | dm_restore_drm_connector_state(dev, connector); | |
3334 | drm_modeset_unlock_all(dev); | |
3335 | ||
3336 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) | |
fc320a6f | 3337 | drm_kms_helper_connector_hotplug_event(connector); |
15c735e7 WL |
3338 | } else { |
3339 | mutex_lock(&adev->dm.dc_lock); | |
3340 | ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); | |
3341 | mutex_unlock(&adev->dm.dc_lock); | |
3342 | if (ret) { | |
3343 | amdgpu_dm_update_connector_after_detect(aconnector); | |
fbbdadf2 | 3344 | |
15c735e7 WL |
3345 | drm_modeset_lock_all(dev); |
3346 | dm_restore_drm_connector_state(dev, connector); | |
3347 | drm_modeset_unlock_all(dev); | |
4562236b | 3348 | |
15c735e7 WL |
3349 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) |
3350 | drm_kms_helper_connector_hotplug_event(connector); | |
3351 | } | |
4562236b HW |
3352 | } |
3353 | mutex_unlock(&aconnector->hpd_lock); | |
3354 | ||
3355 | } | |
3356 | ||
e27c41d5 JS |
3357 | static void handle_hpd_irq(void *param) |
3358 | { | |
3359 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; | |
3360 | ||
3361 | handle_hpd_irq_helper(aconnector); | |
3362 | ||
3363 | } | |
3364 | ||
8e794421 WL |
3365 | static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, |
3366 | union hpd_irq_data hpd_irq_data) | |
3367 | { | |
3368 | struct hpd_rx_irq_offload_work *offload_work = | |
3369 | kzalloc(sizeof(*offload_work), GFP_KERNEL); | |
3370 | ||
3371 | if (!offload_work) { | |
3372 | DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); | |
3373 | return; | |
3374 | } | |
3375 | ||
3376 | INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); | |
3377 | offload_work->data = hpd_irq_data; | |
3378 | offload_work->offload_wq = offload_wq; | |
3379 | ||
3380 | queue_work(offload_wq->wq, &offload_work->work); | |
3381 | DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); | |
3382 | } | |
3383 | ||
4562236b HW |
3384 | static void handle_hpd_rx_irq(void *param) |
3385 | { | |
c84dec2f | 3386 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
4562236b HW |
3387 | struct drm_connector *connector = &aconnector->base; |
3388 | struct drm_device *dev = connector->dev; | |
53cbf65c | 3389 | struct dc_link *dc_link = aconnector->dc_link; |
4562236b | 3390 | bool is_mst_root_connector = aconnector->mst_mgr.mst_state; |
c8ea79a8 | 3391 | bool result = false; |
fbbdadf2 | 3392 | enum dc_connection_type new_connection_type = dc_connection_none; |
c8ea79a8 | 3393 | struct amdgpu_device *adev = drm_to_adev(dev); |
2a0f9270 | 3394 | union hpd_irq_data hpd_irq_data; |
8e794421 WL |
3395 | bool link_loss = false; |
3396 | bool has_left_work = false; | |
e322843e | 3397 | int idx = dc_link->link_index; |
8e794421 | 3398 | struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; |
2a0f9270 BL |
3399 | |
3400 | memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); | |
4562236b | 3401 | |
b972b4f9 HW |
3402 | if (adev->dm.disable_hpd_irq) |
3403 | return; | |
3404 | ||
1f6010a9 DF |
3405 | /* |
3406 | * TODO:Temporary add mutex to protect hpd interrupt not have a gpio | |
4562236b HW |
3407 | * conflict, after implement i2c helper, this mutex should be |
3408 | * retired. | |
3409 | */ | |
b86e7eef | 3410 | mutex_lock(&aconnector->hpd_lock); |
4562236b | 3411 | |
8e794421 WL |
3412 | result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, |
3413 | &link_loss, true, &has_left_work); | |
3083a984 | 3414 | |
8e794421 WL |
3415 | if (!has_left_work) |
3416 | goto out; | |
3417 | ||
3418 | if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { | |
3419 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); | |
3420 | goto out; | |
3421 | } | |
3422 | ||
3423 | if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { | |
3424 | if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || | |
3425 | hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { | |
bb4fa525 WL |
3426 | bool skip = false; |
3427 | ||
3428 | /* | |
3429 | * DOWN_REP_MSG_RDY is also handled by polling method | |
3430 | * mgr->cbs->poll_hpd_irq() | |
3431 | */ | |
3432 | spin_lock(&offload_wq->offload_lock); | |
3433 | skip = offload_wq->is_handling_mst_msg_rdy_event; | |
3434 | ||
3435 | if (!skip) | |
3436 | offload_wq->is_handling_mst_msg_rdy_event = true; | |
3437 | ||
3438 | spin_unlock(&offload_wq->offload_lock); | |
3439 | ||
3440 | if (!skip) | |
3441 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); | |
3442 | ||
3083a984 QZ |
3443 | goto out; |
3444 | } | |
3083a984 | 3445 | |
8e794421 WL |
3446 | if (link_loss) { |
3447 | bool skip = false; | |
d2aa1356 | 3448 | |
8e794421 WL |
3449 | spin_lock(&offload_wq->offload_lock); |
3450 | skip = offload_wq->is_handling_link_loss; | |
3451 | ||
3452 | if (!skip) | |
3453 | offload_wq->is_handling_link_loss = true; | |
3454 | ||
3455 | spin_unlock(&offload_wq->offload_lock); | |
3456 | ||
3457 | if (!skip) | |
3458 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); | |
3459 | ||
3460 | goto out; | |
3461 | } | |
3462 | } | |
c8ea79a8 | 3463 | |
3083a984 | 3464 | out: |
c8ea79a8 | 3465 | if (result && !is_mst_root_connector) { |
4562236b | 3466 | /* Downstream Port status changed. */ |
54618888 | 3467 | if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) |
fbbdadf2 BL |
3468 | DRM_ERROR("KMS: Failed to detect connector\n"); |
3469 | ||
3470 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
3471 | emulated_link_detect(dc_link); | |
3472 | ||
3473 | if (aconnector->fake_enable) | |
3474 | aconnector->fake_enable = false; | |
3475 | ||
3476 | amdgpu_dm_update_connector_after_detect(aconnector); | |
3477 | ||
3478 | ||
3479 | drm_modeset_lock_all(dev); | |
3480 | dm_restore_drm_connector_state(dev, connector); | |
3481 | drm_modeset_unlock_all(dev); | |
3482 | ||
fc320a6f | 3483 | drm_kms_helper_connector_hotplug_event(connector); |
15c735e7 WL |
3484 | } else { |
3485 | bool ret = false; | |
88ac3dda | 3486 | |
15c735e7 WL |
3487 | mutex_lock(&adev->dm.dc_lock); |
3488 | ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); | |
3489 | mutex_unlock(&adev->dm.dc_lock); | |
88ac3dda | 3490 | |
15c735e7 WL |
3491 | if (ret) { |
3492 | if (aconnector->fake_enable) | |
3493 | aconnector->fake_enable = false; | |
4562236b | 3494 | |
15c735e7 | 3495 | amdgpu_dm_update_connector_after_detect(aconnector); |
4562236b | 3496 | |
15c735e7 WL |
3497 | drm_modeset_lock_all(dev); |
3498 | dm_restore_drm_connector_state(dev, connector); | |
3499 | drm_modeset_unlock_all(dev); | |
4562236b | 3500 | |
15c735e7 WL |
3501 | drm_kms_helper_connector_hotplug_event(connector); |
3502 | } | |
4562236b HW |
3503 | } |
3504 | } | |
95f247e7 DC |
3505 | if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { |
3506 | if (adev->dm.hdcp_workqueue) | |
3507 | hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); | |
3508 | } | |
4562236b | 3509 | |
b86e7eef | 3510 | if (dc_link->type != dc_connection_mst_branch) |
e86e8947 | 3511 | drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); |
b86e7eef NC |
3512 | |
3513 | mutex_unlock(&aconnector->hpd_lock); | |
4562236b HW |
3514 | } |
3515 | ||
3516 | static void register_hpd_handlers(struct amdgpu_device *adev) | |
3517 | { | |
4a580877 | 3518 | struct drm_device *dev = adev_to_drm(adev); |
4562236b | 3519 | struct drm_connector *connector; |
c84dec2f | 3520 | struct amdgpu_dm_connector *aconnector; |
4562236b HW |
3521 | const struct dc_link *dc_link; |
3522 | struct dc_interrupt_params int_params = {0}; | |
3523 | ||
3524 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3525 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3526 | ||
3527 | list_for_each_entry(connector, | |
3528 | &dev->mode_config.connector_list, head) { | |
3529 | ||
7db7ade2 HW |
3530 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
3531 | continue; | |
3532 | ||
c84dec2f | 3533 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b HW |
3534 | dc_link = aconnector->dc_link; |
3535 | ||
c82eddf8 | 3536 | if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { |
4562236b HW |
3537 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; |
3538 | int_params.irq_source = dc_link->irq_source_hpd; | |
3539 | ||
3540 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3541 | handle_hpd_irq, | |
3542 | (void *) aconnector); | |
3543 | } | |
3544 | ||
c82eddf8 | 3545 | if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { |
4562236b HW |
3546 | |
3547 | /* Also register for DP short pulse (hpd_rx). */ | |
3548 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
3549 | int_params.irq_source = dc_link->irq_source_hpd_rx; | |
3550 | ||
3551 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3552 | handle_hpd_rx_irq, | |
3553 | (void *) aconnector); | |
3554 | } | |
bb4fa525 WL |
3555 | |
3556 | if (adev->dm.hpd_rx_offload_wq) | |
3557 | adev->dm.hpd_rx_offload_wq[connector->index].aconnector = | |
3558 | aconnector; | |
4562236b HW |
3559 | } |
3560 | } | |
3561 | ||
55e56389 MR |
3562 | #if defined(CONFIG_DRM_AMD_DC_SI) |
3563 | /* Register IRQ sources and initialize IRQ callbacks */ | |
3564 | static int dce60_register_irq_handlers(struct amdgpu_device *adev) | |
3565 | { | |
3566 | struct dc *dc = adev->dm.dc; | |
3567 | struct common_irq_params *c_irq_params; | |
3568 | struct dc_interrupt_params int_params = {0}; | |
3569 | int r; | |
3570 | int i; | |
c82eddf8 | 3571 | unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
55e56389 MR |
3572 | |
3573 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3574 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3575 | ||
3576 | /* | |
3577 | * Actions of amdgpu_irq_add_id(): | |
3578 | * 1. Register a set() function with base driver. | |
3579 | * Base driver will call set() function to enable/disable an | |
3580 | * interrupt in DC hardware. | |
3581 | * 2. Register amdgpu_dm_irq_handler(). | |
3582 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3583 | * coming from DC hardware. | |
3584 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
c82eddf8 SS |
3585 | * for acknowledging and handling. |
3586 | */ | |
55e56389 MR |
3587 | |
3588 | /* Use VBLANK interrupt */ | |
3589 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
c82eddf8 | 3590 | r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); |
55e56389 MR |
3591 | if (r) { |
3592 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3593 | return r; | |
3594 | } | |
3595 | ||
3596 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3597 | int_params.irq_source = | |
c82eddf8 | 3598 | dc_interrupt_to_irq_source(dc, i + 1, 0); |
55e56389 MR |
3599 | |
3600 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; | |
3601 | ||
3602 | c_irq_params->adev = adev; | |
3603 | c_irq_params->irq_src = int_params.irq_source; | |
3604 | ||
3605 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3606 | dm_crtc_high_irq, c_irq_params); | |
3607 | } | |
3608 | ||
3609 | /* Use GRPH_PFLIP interrupt */ | |
3610 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; | |
3611 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { | |
3612 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); | |
3613 | if (r) { | |
3614 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3615 | return r; | |
3616 | } | |
3617 | ||
3618 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3619 | int_params.irq_source = | |
3620 | dc_interrupt_to_irq_source(dc, i, 0); | |
3621 | ||
3622 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3623 | ||
3624 | c_irq_params->adev = adev; | |
3625 | c_irq_params->irq_src = int_params.irq_source; | |
3626 | ||
3627 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3628 | dm_pflip_high_irq, c_irq_params); | |
3629 | ||
3630 | } | |
3631 | ||
3632 | /* HPD */ | |
3633 | r = amdgpu_irq_add_id(adev, client_id, | |
3634 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); | |
3635 | if (r) { | |
3636 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3637 | return r; | |
3638 | } | |
3639 | ||
3640 | register_hpd_handlers(adev); | |
3641 | ||
3642 | return 0; | |
3643 | } | |
3644 | #endif | |
3645 | ||
4562236b HW |
3646 | /* Register IRQ sources and initialize IRQ callbacks */ |
3647 | static int dce110_register_irq_handlers(struct amdgpu_device *adev) | |
3648 | { | |
3649 | struct dc *dc = adev->dm.dc; | |
3650 | struct common_irq_params *c_irq_params; | |
3651 | struct dc_interrupt_params int_params = {0}; | |
3652 | int r; | |
3653 | int i; | |
c82eddf8 | 3654 | unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
2c8ad2d5 | 3655 | |
c08182f2 | 3656 | if (adev->family >= AMDGPU_FAMILY_AI) |
3760f76c | 3657 | client_id = SOC15_IH_CLIENTID_DCE; |
4562236b HW |
3658 | |
3659 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3660 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3661 | ||
1f6010a9 DF |
3662 | /* |
3663 | * Actions of amdgpu_irq_add_id(): | |
4562236b HW |
3664 | * 1. Register a set() function with base driver. |
3665 | * Base driver will call set() function to enable/disable an | |
3666 | * interrupt in DC hardware. | |
3667 | * 2. Register amdgpu_dm_irq_handler(). | |
3668 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3669 | * coming from DC hardware. | |
3670 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
c82eddf8 SS |
3671 | * for acknowledging and handling. |
3672 | */ | |
4562236b | 3673 | |
b57de80a | 3674 | /* Use VBLANK interrupt */ |
e9029155 | 3675 | for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { |
2c8ad2d5 | 3676 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); |
4562236b HW |
3677 | if (r) { |
3678 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3679 | return r; | |
3680 | } | |
3681 | ||
3682 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3683 | int_params.irq_source = | |
3d761e79 | 3684 | dc_interrupt_to_irq_source(dc, i, 0); |
4562236b | 3685 | |
b57de80a | 3686 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
4562236b HW |
3687 | |
3688 | c_irq_params->adev = adev; | |
3689 | c_irq_params->irq_src = int_params.irq_source; | |
3690 | ||
3691 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3692 | dm_crtc_high_irq, c_irq_params); | |
3693 | } | |
3694 | ||
d2574c33 MK |
3695 | /* Use VUPDATE interrupt */ |
3696 | for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { | |
3697 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); | |
3698 | if (r) { | |
3699 | DRM_ERROR("Failed to add vupdate irq id!\n"); | |
3700 | return r; | |
3701 | } | |
3702 | ||
3703 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3704 | int_params.irq_source = | |
3705 | dc_interrupt_to_irq_source(dc, i, 0); | |
3706 | ||
3707 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; | |
3708 | ||
3709 | c_irq_params->adev = adev; | |
3710 | c_irq_params->irq_src = int_params.irq_source; | |
3711 | ||
3712 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3713 | dm_vupdate_high_irq, c_irq_params); | |
3714 | } | |
3715 | ||
3d761e79 | 3716 | /* Use GRPH_PFLIP interrupt */ |
4562236b HW |
3717 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; |
3718 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { | |
2c8ad2d5 | 3719 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); |
4562236b HW |
3720 | if (r) { |
3721 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3722 | return r; | |
3723 | } | |
3724 | ||
3725 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3726 | int_params.irq_source = | |
3727 | dc_interrupt_to_irq_source(dc, i, 0); | |
3728 | ||
3729 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3730 | ||
3731 | c_irq_params->adev = adev; | |
3732 | c_irq_params->irq_src = int_params.irq_source; | |
3733 | ||
3734 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3735 | dm_pflip_high_irq, c_irq_params); | |
3736 | ||
3737 | } | |
3738 | ||
3739 | /* HPD */ | |
2c8ad2d5 AD |
3740 | r = amdgpu_irq_add_id(adev, client_id, |
3741 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); | |
4562236b HW |
3742 | if (r) { |
3743 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3744 | return r; | |
3745 | } | |
3746 | ||
3747 | register_hpd_handlers(adev); | |
3748 | ||
3749 | return 0; | |
3750 | } | |
3751 | ||
ff5ef992 AD |
3752 | /* Register IRQ sources and initialize IRQ callbacks */ |
3753 | static int dcn10_register_irq_handlers(struct amdgpu_device *adev) | |
3754 | { | |
3755 | struct dc *dc = adev->dm.dc; | |
3756 | struct common_irq_params *c_irq_params; | |
3757 | struct dc_interrupt_params int_params = {0}; | |
3758 | int r; | |
3759 | int i; | |
660d5406 WL |
3760 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
3761 | static const unsigned int vrtl_int_srcid[] = { | |
3762 | DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, | |
3763 | DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, | |
3764 | DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, | |
3765 | DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, | |
3766 | DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, | |
3767 | DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL | |
3768 | }; | |
3769 | #endif | |
ff5ef992 AD |
3770 | |
3771 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3772 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3773 | ||
1f6010a9 DF |
3774 | /* |
3775 | * Actions of amdgpu_irq_add_id(): | |
ff5ef992 AD |
3776 | * 1. Register a set() function with base driver. |
3777 | * Base driver will call set() function to enable/disable an | |
3778 | * interrupt in DC hardware. | |
3779 | * 2. Register amdgpu_dm_irq_handler(). | |
3780 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3781 | * coming from DC hardware. | |
3782 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
3783 | * for acknowledging and handling. | |
1f6010a9 | 3784 | */ |
ff5ef992 AD |
3785 | |
3786 | /* Use VSTARTUP interrupt */ | |
3787 | for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; | |
3788 | i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; | |
3789 | i++) { | |
3760f76c | 3790 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); |
ff5ef992 AD |
3791 | |
3792 | if (r) { | |
3793 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3794 | return r; | |
3795 | } | |
3796 | ||
3797 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3798 | int_params.irq_source = | |
3799 | dc_interrupt_to_irq_source(dc, i, 0); | |
3800 | ||
3801 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; | |
3802 | ||
3803 | c_irq_params->adev = adev; | |
3804 | c_irq_params->irq_src = int_params.irq_source; | |
3805 | ||
2346ef47 NK |
3806 | amdgpu_dm_irq_register_interrupt( |
3807 | adev, &int_params, dm_crtc_high_irq, c_irq_params); | |
3808 | } | |
3809 | ||
86bc2219 WL |
3810 | /* Use otg vertical line interrupt */ |
3811 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) | |
660d5406 WL |
3812 | for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { |
3813 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, | |
3814 | vrtl_int_srcid[i], &adev->vline0_irq); | |
86bc2219 WL |
3815 | |
3816 | if (r) { | |
3817 | DRM_ERROR("Failed to add vline0 irq id!\n"); | |
3818 | return r; | |
3819 | } | |
3820 | ||
3821 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3822 | int_params.irq_source = | |
660d5406 WL |
3823 | dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); |
3824 | ||
3825 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { | |
3826 | DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); | |
3827 | break; | |
3828 | } | |
86bc2219 WL |
3829 | |
3830 | c_irq_params = &adev->dm.vline0_params[int_params.irq_source | |
3831 | - DC_IRQ_SOURCE_DC1_VLINE0]; | |
3832 | ||
3833 | c_irq_params->adev = adev; | |
3834 | c_irq_params->irq_src = int_params.irq_source; | |
3835 | ||
3836 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3837 | dm_dcn_vertical_interrupt0_high_irq, c_irq_params); | |
3838 | } | |
3839 | #endif | |
3840 | ||
2346ef47 NK |
3841 | /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to |
3842 | * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx | |
3843 | * to trigger at end of each vblank, regardless of state of the lock, | |
3844 | * matching DCE behaviour. | |
3845 | */ | |
3846 | for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; | |
3847 | i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; | |
3848 | i++) { | |
3849 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); | |
3850 | ||
3851 | if (r) { | |
3852 | DRM_ERROR("Failed to add vupdate irq id!\n"); | |
3853 | return r; | |
3854 | } | |
3855 | ||
3856 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3857 | int_params.irq_source = | |
3858 | dc_interrupt_to_irq_source(dc, i, 0); | |
3859 | ||
3860 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; | |
3861 | ||
3862 | c_irq_params->adev = adev; | |
3863 | c_irq_params->irq_src = int_params.irq_source; | |
3864 | ||
ff5ef992 | 3865 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
2346ef47 | 3866 | dm_vupdate_high_irq, c_irq_params); |
d2574c33 MK |
3867 | } |
3868 | ||
ff5ef992 AD |
3869 | /* Use GRPH_PFLIP interrupt */ |
3870 | for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; | |
de95753c | 3871 | i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; |
ff5ef992 | 3872 | i++) { |
3760f76c | 3873 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); |
ff5ef992 AD |
3874 | if (r) { |
3875 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3876 | return r; | |
3877 | } | |
3878 | ||
3879 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3880 | int_params.irq_source = | |
3881 | dc_interrupt_to_irq_source(dc, i, 0); | |
3882 | ||
3883 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3884 | ||
3885 | c_irq_params->adev = adev; | |
3886 | c_irq_params->irq_src = int_params.irq_source; | |
3887 | ||
3888 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3889 | dm_pflip_high_irq, c_irq_params); | |
3890 | ||
3891 | } | |
3892 | ||
81927e28 JS |
3893 | /* HPD */ |
3894 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, | |
3895 | &adev->hpd_irq); | |
3896 | if (r) { | |
3897 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3898 | return r; | |
3899 | } | |
a08f16cf | 3900 | |
81927e28 | 3901 | register_hpd_handlers(adev); |
a08f16cf | 3902 | |
81927e28 JS |
3903 | return 0; |
3904 | } | |
3905 | /* Register Outbox IRQ sources and initialize IRQ callbacks */ | |
3906 | static int register_outbox_irq_handlers(struct amdgpu_device *adev) | |
3907 | { | |
3908 | struct dc *dc = adev->dm.dc; | |
3909 | struct common_irq_params *c_irq_params; | |
3910 | struct dc_interrupt_params int_params = {0}; | |
3911 | int r, i; | |
3912 | ||
3913 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3914 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3915 | ||
3916 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, | |
3917 | &adev->dmub_outbox_irq); | |
3918 | if (r) { | |
3919 | DRM_ERROR("Failed to add outbox irq id!\n"); | |
3920 | return r; | |
3921 | } | |
3922 | ||
3923 | if (dc->ctx->dmub_srv) { | |
3924 | i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; | |
3925 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
a08f16cf | 3926 | int_params.irq_source = |
81927e28 | 3927 | dc_interrupt_to_irq_source(dc, i, 0); |
a08f16cf | 3928 | |
81927e28 | 3929 | c_irq_params = &adev->dm.dmub_outbox_params[0]; |
a08f16cf LHM |
3930 | |
3931 | c_irq_params->adev = adev; | |
3932 | c_irq_params->irq_src = int_params.irq_source; | |
3933 | ||
3934 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
81927e28 | 3935 | dm_dmub_outbox1_low_irq, c_irq_params); |
ff5ef992 AD |
3936 | } |
3937 | ||
ff5ef992 AD |
3938 | return 0; |
3939 | } | |
ff5ef992 | 3940 | |
eb3dc897 NK |
3941 | /* |
3942 | * Acquires the lock for the atomic state object and returns | |
3943 | * the new atomic state. | |
3944 | * | |
3945 | * This should only be called during atomic check. | |
3946 | */ | |
17ce8a69 RL |
3947 | int dm_atomic_get_state(struct drm_atomic_state *state, |
3948 | struct dm_atomic_state **dm_state) | |
eb3dc897 NK |
3949 | { |
3950 | struct drm_device *dev = state->dev; | |
1348969a | 3951 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 NK |
3952 | struct amdgpu_display_manager *dm = &adev->dm; |
3953 | struct drm_private_state *priv_state; | |
eb3dc897 NK |
3954 | |
3955 | if (*dm_state) | |
3956 | return 0; | |
3957 | ||
eb3dc897 NK |
3958 | priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); |
3959 | if (IS_ERR(priv_state)) | |
3960 | return PTR_ERR(priv_state); | |
3961 | ||
3962 | *dm_state = to_dm_atomic_state(priv_state); | |
3963 | ||
3964 | return 0; | |
3965 | } | |
3966 | ||
dfd84d90 | 3967 | static struct dm_atomic_state * |
eb3dc897 NK |
3968 | dm_atomic_get_new_state(struct drm_atomic_state *state) |
3969 | { | |
3970 | struct drm_device *dev = state->dev; | |
1348969a | 3971 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 NK |
3972 | struct amdgpu_display_manager *dm = &adev->dm; |
3973 | struct drm_private_obj *obj; | |
3974 | struct drm_private_state *new_obj_state; | |
3975 | int i; | |
3976 | ||
3977 | for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { | |
3978 | if (obj->funcs == dm->atomic_obj.funcs) | |
3979 | return to_dm_atomic_state(new_obj_state); | |
3980 | } | |
3981 | ||
3982 | return NULL; | |
3983 | } | |
3984 | ||
eb3dc897 NK |
3985 | static struct drm_private_state * |
3986 | dm_atomic_duplicate_state(struct drm_private_obj *obj) | |
3987 | { | |
3988 | struct dm_atomic_state *old_state, *new_state; | |
3989 | ||
3990 | new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); | |
3991 | if (!new_state) | |
3992 | return NULL; | |
3993 | ||
3994 | __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); | |
3995 | ||
813d20dc AW |
3996 | old_state = to_dm_atomic_state(obj->state); |
3997 | ||
3998 | if (old_state && old_state->context) | |
3999 | new_state->context = dc_copy_state(old_state->context); | |
4000 | ||
eb3dc897 NK |
4001 | if (!new_state->context) { |
4002 | kfree(new_state); | |
4003 | return NULL; | |
4004 | } | |
4005 | ||
eb3dc897 NK |
4006 | return &new_state->base; |
4007 | } | |
4008 | ||
4009 | static void dm_atomic_destroy_state(struct drm_private_obj *obj, | |
4010 | struct drm_private_state *state) | |
4011 | { | |
4012 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); | |
4013 | ||
4014 | if (dm_state && dm_state->context) | |
4015 | dc_release_state(dm_state->context); | |
4016 | ||
4017 | kfree(dm_state); | |
4018 | } | |
4019 | ||
4020 | static struct drm_private_state_funcs dm_atomic_state_funcs = { | |
4021 | .atomic_duplicate_state = dm_atomic_duplicate_state, | |
4022 | .atomic_destroy_state = dm_atomic_destroy_state, | |
4023 | }; | |
4024 | ||
4562236b HW |
4025 | static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) |
4026 | { | |
eb3dc897 | 4027 | struct dm_atomic_state *state; |
4562236b HW |
4028 | int r; |
4029 | ||
4030 | adev->mode_info.mode_config_initialized = true; | |
4031 | ||
4a580877 LT |
4032 | adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; |
4033 | adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; | |
4562236b | 4034 | |
4a580877 LT |
4035 | adev_to_drm(adev)->mode_config.max_width = 16384; |
4036 | adev_to_drm(adev)->mode_config.max_height = 16384; | |
4562236b | 4037 | |
4a580877 | 4038 | adev_to_drm(adev)->mode_config.preferred_depth = 24; |
a6250bdb AD |
4039 | if (adev->asic_type == CHIP_HAWAII) |
4040 | /* disable prefer shadow for now due to hibernation issues */ | |
4041 | adev_to_drm(adev)->mode_config.prefer_shadow = 0; | |
4042 | else | |
4043 | adev_to_drm(adev)->mode_config.prefer_shadow = 1; | |
1f6010a9 | 4044 | /* indicates support for immediate flip */ |
4a580877 | 4045 | adev_to_drm(adev)->mode_config.async_page_flip = true; |
4562236b | 4046 | |
eb3dc897 NK |
4047 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
4048 | if (!state) | |
4049 | return -ENOMEM; | |
4050 | ||
813d20dc | 4051 | state->context = dc_create_state(adev->dm.dc); |
eb3dc897 NK |
4052 | if (!state->context) { |
4053 | kfree(state); | |
4054 | return -ENOMEM; | |
4055 | } | |
4056 | ||
4057 | dc_resource_state_copy_construct_current(adev->dm.dc, state->context); | |
4058 | ||
4a580877 | 4059 | drm_atomic_private_obj_init(adev_to_drm(adev), |
8c1a765b | 4060 | &adev->dm.atomic_obj, |
eb3dc897 NK |
4061 | &state->base, |
4062 | &dm_atomic_state_funcs); | |
4063 | ||
3dc9b1ce | 4064 | r = amdgpu_display_modeset_create_props(adev); |
b67a468a DL |
4065 | if (r) { |
4066 | dc_release_state(state->context); | |
4067 | kfree(state); | |
4562236b | 4068 | return r; |
b67a468a | 4069 | } |
4562236b | 4070 | |
6ce8f316 | 4071 | r = amdgpu_dm_audio_init(adev); |
b67a468a DL |
4072 | if (r) { |
4073 | dc_release_state(state->context); | |
4074 | kfree(state); | |
6ce8f316 | 4075 | return r; |
b67a468a | 4076 | } |
6ce8f316 | 4077 | |
4562236b HW |
4078 | return 0; |
4079 | } | |
4080 | ||
206bbafe DF |
4081 | #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 |
4082 | #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 | |
94562810 | 4083 | #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 |
206bbafe | 4084 | |
7fd13bae AD |
4085 | static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, |
4086 | int bl_idx) | |
206bbafe DF |
4087 | { |
4088 | #if defined(CONFIG_ACPI) | |
4089 | struct amdgpu_dm_backlight_caps caps; | |
4090 | ||
58965855 FS |
4091 | memset(&caps, 0, sizeof(caps)); |
4092 | ||
7fd13bae | 4093 | if (dm->backlight_caps[bl_idx].caps_valid) |
206bbafe DF |
4094 | return; |
4095 | ||
f9b7f370 | 4096 | amdgpu_acpi_get_backlight_caps(&caps); |
206bbafe | 4097 | if (caps.caps_valid) { |
7fd13bae | 4098 | dm->backlight_caps[bl_idx].caps_valid = true; |
94562810 RS |
4099 | if (caps.aux_support) |
4100 | return; | |
7fd13bae AD |
4101 | dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; |
4102 | dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; | |
206bbafe | 4103 | } else { |
7fd13bae | 4104 | dm->backlight_caps[bl_idx].min_input_signal = |
206bbafe | 4105 | AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
7fd13bae | 4106 | dm->backlight_caps[bl_idx].max_input_signal = |
206bbafe DF |
4107 | AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; |
4108 | } | |
4109 | #else | |
7fd13bae | 4110 | if (dm->backlight_caps[bl_idx].aux_support) |
94562810 RS |
4111 | return; |
4112 | ||
7fd13bae AD |
4113 | dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
4114 | dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; | |
206bbafe DF |
4115 | #endif |
4116 | } | |
4117 | ||
69d9f427 | 4118 | static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, |
c82eddf8 | 4119 | unsigned int *min, unsigned int *max) |
94562810 | 4120 | { |
94562810 | 4121 | if (!caps) |
69d9f427 | 4122 | return 0; |
94562810 | 4123 | |
69d9f427 AM |
4124 | if (caps->aux_support) { |
4125 | // Firmware limits are in nits, DC API wants millinits. | |
4126 | *max = 1000 * caps->aux_max_input_signal; | |
4127 | *min = 1000 * caps->aux_min_input_signal; | |
94562810 | 4128 | } else { |
69d9f427 AM |
4129 | // Firmware limits are 8-bit, PWM control is 16-bit. |
4130 | *max = 0x101 * caps->max_input_signal; | |
4131 | *min = 0x101 * caps->min_input_signal; | |
94562810 | 4132 | } |
69d9f427 AM |
4133 | return 1; |
4134 | } | |
94562810 | 4135 | |
69d9f427 AM |
4136 | static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, |
4137 | uint32_t brightness) | |
4138 | { | |
c82eddf8 | 4139 | unsigned int min, max; |
94562810 | 4140 | |
69d9f427 AM |
4141 | if (!get_brightness_range(caps, &min, &max)) |
4142 | return brightness; | |
4143 | ||
4144 | // Rescale 0..255 to min..max | |
4145 | return min + DIV_ROUND_CLOSEST((max - min) * brightness, | |
4146 | AMDGPU_MAX_BL_LEVEL); | |
4147 | } | |
4148 | ||
4149 | static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, | |
4150 | uint32_t brightness) | |
4151 | { | |
c82eddf8 | 4152 | unsigned int min, max; |
69d9f427 AM |
4153 | |
4154 | if (!get_brightness_range(caps, &min, &max)) | |
4155 | return brightness; | |
4156 | ||
4157 | if (brightness < min) | |
4158 | return 0; | |
4159 | // Rescale min..max to 0..255 | |
4160 | return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), | |
4161 | max - min); | |
94562810 RS |
4162 | } |
4163 | ||
4052287a | 4164 | static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, |
7fd13bae | 4165 | int bl_idx, |
3d6c9164 | 4166 | u32 user_brightness) |
4562236b | 4167 | { |
206bbafe | 4168 | struct amdgpu_dm_backlight_caps caps; |
7fd13bae AD |
4169 | struct dc_link *link; |
4170 | u32 brightness; | |
94562810 | 4171 | bool rc; |
4562236b | 4172 | |
7fd13bae AD |
4173 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4174 | caps = dm->backlight_caps[bl_idx]; | |
94562810 | 4175 | |
7fd13bae | 4176 | dm->brightness[bl_idx] = user_brightness; |
1f579254 AD |
4177 | /* update scratch register */ |
4178 | if (bl_idx == 0) | |
4179 | amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); | |
7fd13bae AD |
4180 | brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); |
4181 | link = (struct dc_link *)dm->backlight_link[bl_idx]; | |
94562810 | 4182 | |
3d6c9164 | 4183 | /* Change brightness based on AUX property */ |
118b4627 | 4184 | if (caps.aux_support) { |
7fd13bae AD |
4185 | rc = dc_link_set_backlight_level_nits(link, true, brightness, |
4186 | AUX_BL_DEFAULT_TRANSITION_TIME_MS); | |
4187 | if (!rc) | |
4188 | DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); | |
118b4627 | 4189 | } else { |
7fd13bae AD |
4190 | rc = dc_link_set_backlight_level(link, brightness, 0); |
4191 | if (!rc) | |
4192 | DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); | |
118b4627 | 4193 | } |
94562810 | 4194 | |
4052287a S |
4195 | if (rc) |
4196 | dm->actual_brightness[bl_idx] = user_brightness; | |
4562236b HW |
4197 | } |
4198 | ||
3d6c9164 | 4199 | static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) |
4562236b | 4200 | { |
620a0d27 | 4201 | struct amdgpu_display_manager *dm = bl_get_data(bd); |
7fd13bae | 4202 | int i; |
3d6c9164 | 4203 | |
7fd13bae AD |
4204 | for (i = 0; i < dm->num_of_edps; i++) { |
4205 | if (bd == dm->backlight_dev[i]) | |
4206 | break; | |
4207 | } | |
4208 | if (i >= AMDGPU_DM_MAX_NUM_EDP) | |
4209 | i = 0; | |
4210 | amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); | |
3d6c9164 AD |
4211 | |
4212 | return 0; | |
4213 | } | |
4214 | ||
7fd13bae AD |
4215 | static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, |
4216 | int bl_idx) | |
3d6c9164 | 4217 | { |
53e1db06 | 4218 | int ret; |
0ad3e64e | 4219 | struct amdgpu_dm_backlight_caps caps; |
7fd13bae | 4220 | struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; |
0ad3e64e | 4221 | |
7fd13bae AD |
4222 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4223 | caps = dm->backlight_caps[bl_idx]; | |
620a0d27 | 4224 | |
0ad3e64e | 4225 | if (caps.aux_support) { |
0ad3e64e AD |
4226 | u32 avg, peak; |
4227 | bool rc; | |
4228 | ||
4229 | rc = dc_link_get_backlight_level_nits(link, &avg, &peak); | |
4230 | if (!rc) | |
7fd13bae | 4231 | return dm->brightness[bl_idx]; |
0ad3e64e | 4232 | return convert_brightness_to_user(&caps, avg); |
0ad3e64e | 4233 | } |
53e1db06 SS |
4234 | |
4235 | ret = dc_link_get_backlight_level(link); | |
4236 | ||
4237 | if (ret == DC_ERROR_UNEXPECTED) | |
4238 | return dm->brightness[bl_idx]; | |
4239 | ||
4240 | return convert_brightness_to_user(&caps, ret); | |
4562236b HW |
4241 | } |
4242 | ||
3d6c9164 AD |
4243 | static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) |
4244 | { | |
4245 | struct amdgpu_display_manager *dm = bl_get_data(bd); | |
7fd13bae | 4246 | int i; |
3d6c9164 | 4247 | |
7fd13bae AD |
4248 | for (i = 0; i < dm->num_of_edps; i++) { |
4249 | if (bd == dm->backlight_dev[i]) | |
4250 | break; | |
4251 | } | |
4252 | if (i >= AMDGPU_DM_MAX_NUM_EDP) | |
4253 | i = 0; | |
4254 | return amdgpu_dm_backlight_get_level(dm, i); | |
3d6c9164 AD |
4255 | } |
4256 | ||
4562236b | 4257 | static const struct backlight_ops amdgpu_dm_backlight_ops = { |
bb264220 | 4258 | .options = BL_CORE_SUSPENDRESUME, |
4562236b HW |
4259 | .get_brightness = amdgpu_dm_backlight_get_brightness, |
4260 | .update_status = amdgpu_dm_backlight_update_status, | |
4261 | }; | |
4262 | ||
7578ecda | 4263 | static void |
213eca2b | 4264 | amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) |
4562236b | 4265 | { |
213eca2b HG |
4266 | struct drm_device *drm = aconnector->base.dev; |
4267 | struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; | |
4562236b | 4268 | struct backlight_properties props = { 0 }; |
213eca2b | 4269 | char bl_name[16]; |
4562236b | 4270 | |
62f03dad HG |
4271 | if (aconnector->bl_idx == -1) |
4272 | return; | |
4273 | ||
da11ef83 | 4274 | if (!acpi_video_backlight_use_native()) { |
213eca2b | 4275 | drm_info(drm, "Skipping amdgpu DM backlight registration\n"); |
c0f50c5d HG |
4276 | /* Try registering an ACPI video backlight device instead. */ |
4277 | acpi_video_register_backlight(); | |
da11ef83 HG |
4278 | return; |
4279 | } | |
4280 | ||
4562236b | 4281 | props.max_brightness = AMDGPU_MAX_BL_LEVEL; |
53a53f86 | 4282 | props.brightness = AMDGPU_MAX_BL_LEVEL; |
4562236b HW |
4283 | props.type = BACKLIGHT_RAW; |
4284 | ||
4285 | snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", | |
213eca2b | 4286 | drm->primary->index + aconnector->bl_idx); |
4562236b | 4287 | |
213eca2b | 4288 | dm->backlight_dev[aconnector->bl_idx] = |
62f03dad | 4289 | backlight_device_register(bl_name, aconnector->base.kdev, dm, |
213eca2b | 4290 | &amdgpu_dm_backlight_ops, &props); |
4562236b | 4291 | |
213eca2b | 4292 | if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { |
4562236b | 4293 | DRM_ERROR("DM: Backlight registration failed!\n"); |
213eca2b | 4294 | dm->backlight_dev[aconnector->bl_idx] = NULL; |
4db231d7 | 4295 | } else |
f1ad2f5e | 4296 | DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); |
4562236b | 4297 | } |
4562236b | 4298 | |
df534fff | 4299 | static int initialize_plane(struct amdgpu_display_manager *dm, |
b2fddb13 | 4300 | struct amdgpu_mode_info *mode_info, int plane_id, |
cc1fec57 NK |
4301 | enum drm_plane_type plane_type, |
4302 | const struct dc_plane_cap *plane_cap) | |
df534fff | 4303 | { |
f180b4bc | 4304 | struct drm_plane *plane; |
df534fff S |
4305 | unsigned long possible_crtcs; |
4306 | int ret = 0; | |
4307 | ||
f180b4bc | 4308 | plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); |
df534fff S |
4309 | if (!plane) { |
4310 | DRM_ERROR("KMS: Failed to allocate plane\n"); | |
4311 | return -ENOMEM; | |
4312 | } | |
b2fddb13 | 4313 | plane->type = plane_type; |
df534fff S |
4314 | |
4315 | /* | |
b2fddb13 NK |
4316 | * HACK: IGT tests expect that the primary plane for a CRTC |
4317 | * can only have one possible CRTC. Only expose support for | |
4318 | * any CRTC if they're not going to be used as a primary plane | |
4319 | * for a CRTC - like overlay or underlay planes. | |
df534fff S |
4320 | */ |
4321 | possible_crtcs = 1 << plane_id; | |
4322 | if (plane_id >= dm->dc->caps.max_streams) | |
4323 | possible_crtcs = 0xff; | |
4324 | ||
cc1fec57 | 4325 | ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); |
df534fff S |
4326 | |
4327 | if (ret) { | |
4328 | DRM_ERROR("KMS: Failed to initialize plane\n"); | |
54087768 | 4329 | kfree(plane); |
df534fff S |
4330 | return ret; |
4331 | } | |
4332 | ||
54087768 NK |
4333 | if (mode_info) |
4334 | mode_info->planes[plane_id] = plane; | |
4335 | ||
df534fff S |
4336 | return ret; |
4337 | } | |
4338 | ||
89fc8d4e | 4339 | |
618e51cd HG |
4340 | static void setup_backlight_device(struct amdgpu_display_manager *dm, |
4341 | struct amdgpu_dm_connector *aconnector) | |
89fc8d4e | 4342 | { |
f196198c | 4343 | struct dc_link *link = aconnector->dc_link; |
ceb4a561 | 4344 | int bl_idx = dm->num_of_edps; |
89fc8d4e | 4345 | |
ceb4a561 HG |
4346 | if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || |
4347 | link->type == dc_connection_none) | |
4348 | return; | |
4349 | ||
4350 | if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { | |
4351 | drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); | |
4352 | return; | |
89fc8d4e | 4353 | } |
ceb4a561 | 4354 | |
f196198c HG |
4355 | aconnector->bl_idx = bl_idx; |
4356 | ||
618e51cd HG |
4357 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4358 | dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; | |
ceb4a561 HG |
4359 | dm->backlight_link[bl_idx] = link; |
4360 | dm->num_of_edps++; | |
618e51cd HG |
4361 | |
4362 | update_connector_ext_caps(aconnector); | |
89fc8d4e HW |
4363 | } |
4364 | ||
acc96ae0 | 4365 | static void amdgpu_set_panel_orientation(struct drm_connector *connector); |
89fc8d4e | 4366 | |
1f6010a9 DF |
4367 | /* |
4368 | * In this architecture, the association | |
4562236b HW |
4369 | * connector -> encoder -> crtc |
4370 | * id not really requried. The crtc and connector will hold the | |
4371 | * display_index as an abstraction to use with DAL component | |
4372 | * | |
4373 | * Returns 0 on success | |
4374 | */ | |
7578ecda | 4375 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) |
4562236b HW |
4376 | { |
4377 | struct amdgpu_display_manager *dm = &adev->dm; | |
ae67558b | 4378 | s32 i; |
c84dec2f | 4379 | struct amdgpu_dm_connector *aconnector = NULL; |
f2a0f5e6 | 4380 | struct amdgpu_encoder *aencoder = NULL; |
d4e13b0d | 4381 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
ae67558b SS |
4382 | u32 link_cnt; |
4383 | s32 primary_planes; | |
fbbdadf2 | 4384 | enum dc_connection_type new_connection_type = dc_connection_none; |
cc1fec57 | 4385 | const struct dc_plane_cap *plane; |
9470620e | 4386 | bool psr_feature_enabled = false; |
44e60b14 | 4387 | bool replay_feature_enabled = false; |
35f33086 | 4388 | int max_overlay = dm->dc->caps.max_slave_planes; |
4562236b | 4389 | |
d58159de AD |
4390 | dm->display_indexes_num = dm->dc->caps.max_streams; |
4391 | /* Update the actual used number of crtc */ | |
4392 | adev->mode_info.num_crtc = adev->dm.display_indexes_num; | |
4393 | ||
60971b20 | 4394 | amdgpu_dm_set_irq_funcs(adev); |
4395 | ||
4562236b | 4396 | link_cnt = dm->dc->caps.max_links; |
4562236b HW |
4397 | if (amdgpu_dm_mode_config_init(dm->adev)) { |
4398 | DRM_ERROR("DM: Failed to initialize mode config\n"); | |
59d0f396 | 4399 | return -EINVAL; |
4562236b HW |
4400 | } |
4401 | ||
b2fddb13 NK |
4402 | /* There is one primary plane per CRTC */ |
4403 | primary_planes = dm->dc->caps.max_streams; | |
54087768 | 4404 | ASSERT(primary_planes <= AMDGPU_MAX_PLANES); |
efa6a8b7 | 4405 | |
b2fddb13 NK |
4406 | /* |
4407 | * Initialize primary planes, implicit planes for legacy IOCTLS. | |
4408 | * Order is reversed to match iteration order in atomic check. | |
4409 | */ | |
4410 | for (i = (primary_planes - 1); i >= 0; i--) { | |
cc1fec57 NK |
4411 | plane = &dm->dc->caps.planes[i]; |
4412 | ||
b2fddb13 | 4413 | if (initialize_plane(dm, mode_info, i, |
cc1fec57 | 4414 | DRM_PLANE_TYPE_PRIMARY, plane)) { |
df534fff | 4415 | DRM_ERROR("KMS: Failed to initialize primary plane\n"); |
cd8a2ae8 | 4416 | goto fail; |
d4e13b0d | 4417 | } |
df534fff | 4418 | } |
92f3ac40 | 4419 | |
0d579c7e NK |
4420 | /* |
4421 | * Initialize overlay planes, index starting after primary planes. | |
4422 | * These planes have a higher DRM index than the primary planes since | |
4423 | * they should be considered as having a higher z-order. | |
4424 | * Order is reversed to match iteration order in atomic check. | |
cc1fec57 NK |
4425 | * |
4426 | * Only support DCN for now, and only expose one so we don't encourage | |
4427 | * userspace to use up all the pipes. | |
0d579c7e | 4428 | */ |
cc1fec57 NK |
4429 | for (i = 0; i < dm->dc->caps.max_planes; ++i) { |
4430 | struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; | |
4431 | ||
8813381a LL |
4432 | /* Do not create overlay if MPO disabled */ |
4433 | if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) | |
4434 | break; | |
4435 | ||
cc1fec57 NK |
4436 | if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) |
4437 | continue; | |
4438 | ||
ea36ad34 | 4439 | if (!plane->pixel_format_support.argb8888) |
cc1fec57 NK |
4440 | continue; |
4441 | ||
35f33086 BL |
4442 | if (max_overlay-- == 0) |
4443 | break; | |
4444 | ||
54087768 | 4445 | if (initialize_plane(dm, NULL, primary_planes + i, |
cc1fec57 | 4446 | DRM_PLANE_TYPE_OVERLAY, plane)) { |
0d579c7e | 4447 | DRM_ERROR("KMS: Failed to initialize overlay plane\n"); |
cd8a2ae8 | 4448 | goto fail; |
d4e13b0d AD |
4449 | } |
4450 | } | |
4562236b | 4451 | |
d4e13b0d | 4452 | for (i = 0; i < dm->dc->caps.max_streams; i++) |
f180b4bc | 4453 | if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { |
4562236b | 4454 | DRM_ERROR("KMS: Failed to initialize crtc\n"); |
cd8a2ae8 | 4455 | goto fail; |
4562236b | 4456 | } |
4562236b | 4457 | |
81927e28 | 4458 | /* Use Outbox interrupt */ |
4e8303cf | 4459 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
c08182f2 AD |
4460 | case IP_VERSION(3, 0, 0): |
4461 | case IP_VERSION(3, 1, 2): | |
4462 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4463 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4464 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4465 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4466 | case IP_VERSION(3, 2, 0): |
4467 | case IP_VERSION(3, 2, 1): | |
c08182f2 | 4468 | case IP_VERSION(2, 1, 0): |
06b1661e | 4469 | case IP_VERSION(3, 5, 0): |
81927e28 JS |
4470 | if (register_outbox_irq_handlers(dm->adev)) { |
4471 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4472 | goto fail; | |
4473 | } | |
4474 | break; | |
4475 | default: | |
c08182f2 | 4476 | DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", |
4e8303cf | 4477 | amdgpu_ip_version(adev, DCE_HWIP, 0)); |
81927e28 | 4478 | } |
9470620e NK |
4479 | |
4480 | /* Determine whether to enable PSR support by default. */ | |
4481 | if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { | |
4e8303cf | 4482 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
9470620e NK |
4483 | case IP_VERSION(3, 1, 2): |
4484 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4485 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4486 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4487 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4488 | case IP_VERSION(3, 2, 0): |
4489 | case IP_VERSION(3, 2, 1): | |
06b1661e | 4490 | case IP_VERSION(3, 5, 0): |
9470620e NK |
4491 | psr_feature_enabled = true; |
4492 | break; | |
4493 | default: | |
4494 | psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; | |
4495 | break; | |
4496 | } | |
4497 | } | |
81927e28 | 4498 | |
44e60b14 BL |
4499 | if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { |
4500 | switch (adev->ip_versions[DCE_HWIP][0]) { | |
4501 | case IP_VERSION(3, 1, 4): | |
4502 | case IP_VERSION(3, 1, 5): | |
4503 | case IP_VERSION(3, 1, 6): | |
4504 | case IP_VERSION(3, 2, 0): | |
4505 | case IP_VERSION(3, 2, 1): | |
4506 | replay_feature_enabled = true; | |
4507 | break; | |
4508 | default: | |
4509 | replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; | |
4510 | break; | |
4511 | } | |
4512 | } | |
4562236b HW |
4513 | /* loops over all connectors on the board */ |
4514 | for (i = 0; i < link_cnt; i++) { | |
89fc8d4e | 4515 | struct dc_link *link = NULL; |
4562236b HW |
4516 | |
4517 | if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { | |
4518 | DRM_ERROR( | |
4519 | "KMS: Cannot support more than %d display indexes\n", | |
4520 | AMDGPU_DM_MAX_DISPLAY_INDEX); | |
4521 | continue; | |
4522 | } | |
4523 | ||
198891fd HW |
4524 | link = dc_get_link_at_index(dm->dc, i); |
4525 | ||
dfc03588 | 4526 | if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { |
ff73d4cd | 4527 | struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL); |
dfc03588 AH |
4528 | |
4529 | if (!wbcon) { | |
4530 | DRM_ERROR("KMS: Failed to allocate writeback connector\n"); | |
4531 | continue; | |
4532 | } | |
4533 | ||
ff73d4cd | 4534 | if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { |
dfc03588 AH |
4535 | DRM_ERROR("KMS: Failed to initialize writeback connector\n"); |
4536 | kfree(wbcon); | |
4537 | continue; | |
4538 | } | |
4539 | ||
4540 | link->psr_settings.psr_feature_enabled = false; | |
4541 | link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; | |
4542 | ||
198891fd | 4543 | continue; |
dfc03588 | 4544 | } |
198891fd | 4545 | |
4562236b HW |
4546 | aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); |
4547 | if (!aconnector) | |
cd8a2ae8 | 4548 | goto fail; |
4562236b HW |
4549 | |
4550 | aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); | |
8440c304 | 4551 | if (!aencoder) |
cd8a2ae8 | 4552 | goto fail; |
4562236b HW |
4553 | |
4554 | if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { | |
4555 | DRM_ERROR("KMS: Failed to initialize encoder\n"); | |
cd8a2ae8 | 4556 | goto fail; |
4562236b HW |
4557 | } |
4558 | ||
4559 | if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { | |
4560 | DRM_ERROR("KMS: Failed to initialize connector\n"); | |
cd8a2ae8 | 4561 | goto fail; |
4562236b HW |
4562 | } |
4563 | ||
54618888 | 4564 | if (!dc_link_detect_connection_type(link, &new_connection_type)) |
fbbdadf2 BL |
4565 | DRM_ERROR("KMS: Failed to detect connector\n"); |
4566 | ||
4567 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
4568 | emulated_link_detect(link); | |
4569 | amdgpu_dm_update_connector_after_detect(aconnector); | |
15c735e7 WL |
4570 | } else { |
4571 | bool ret = false; | |
fbbdadf2 | 4572 | |
15c735e7 WL |
4573 | mutex_lock(&dm->dc_lock); |
4574 | ret = dc_link_detect(link, DETECT_REASON_BOOT); | |
4575 | mutex_unlock(&dm->dc_lock); | |
4576 | ||
4577 | if (ret) { | |
4578 | amdgpu_dm_update_connector_after_detect(aconnector); | |
618e51cd | 4579 | setup_backlight_device(dm, aconnector); |
89fc8d4e | 4580 | |
44e60b14 BL |
4581 | /* |
4582 | * Disable psr if replay can be enabled | |
4583 | */ | |
4584 | if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector)) | |
4585 | psr_feature_enabled = false; | |
4586 | ||
15c735e7 WL |
4587 | if (psr_feature_enabled) |
4588 | amdgpu_dm_set_psr_caps(link); | |
89fc8d4e | 4589 | |
15c735e7 WL |
4590 | /* TODO: Fix vblank control helpers to delay PSR entry to allow this when |
4591 | * PSR is also supported. | |
4592 | */ | |
4593 | if (link->psr_settings.psr_feature_enabled) | |
4594 | adev_to_drm(adev)->vblank_disable_immediate = false; | |
4595 | } | |
4596 | } | |
acc96ae0 | 4597 | amdgpu_set_panel_orientation(&aconnector->base); |
4562236b HW |
4598 | } |
4599 | ||
4600 | /* Software is initialized. Now we can register interrupt handlers. */ | |
4601 | switch (adev->asic_type) { | |
55e56389 MR |
4602 | #if defined(CONFIG_DRM_AMD_DC_SI) |
4603 | case CHIP_TAHITI: | |
4604 | case CHIP_PITCAIRN: | |
4605 | case CHIP_VERDE: | |
4606 | case CHIP_OLAND: | |
4607 | if (dce60_register_irq_handlers(dm->adev)) { | |
4608 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4609 | goto fail; | |
4610 | } | |
4611 | break; | |
4612 | #endif | |
4562236b HW |
4613 | case CHIP_BONAIRE: |
4614 | case CHIP_HAWAII: | |
cd4b356f AD |
4615 | case CHIP_KAVERI: |
4616 | case CHIP_KABINI: | |
4617 | case CHIP_MULLINS: | |
4562236b HW |
4618 | case CHIP_TONGA: |
4619 | case CHIP_FIJI: | |
4620 | case CHIP_CARRIZO: | |
4621 | case CHIP_STONEY: | |
4622 | case CHIP_POLARIS11: | |
4623 | case CHIP_POLARIS10: | |
b264d345 | 4624 | case CHIP_POLARIS12: |
7737de91 | 4625 | case CHIP_VEGAM: |
2c8ad2d5 | 4626 | case CHIP_VEGA10: |
2325ff30 | 4627 | case CHIP_VEGA12: |
1fe6bf2f | 4628 | case CHIP_VEGA20: |
4562236b HW |
4629 | if (dce110_register_irq_handlers(dm->adev)) { |
4630 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
cd8a2ae8 | 4631 | goto fail; |
4562236b HW |
4632 | } |
4633 | break; | |
4634 | default: | |
4e8303cf | 4635 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
559f591d AD |
4636 | case IP_VERSION(1, 0, 0): |
4637 | case IP_VERSION(1, 0, 1): | |
c08182f2 AD |
4638 | case IP_VERSION(2, 0, 2): |
4639 | case IP_VERSION(2, 0, 3): | |
4640 | case IP_VERSION(2, 0, 0): | |
4641 | case IP_VERSION(2, 1, 0): | |
4642 | case IP_VERSION(3, 0, 0): | |
4643 | case IP_VERSION(3, 0, 2): | |
4644 | case IP_VERSION(3, 0, 3): | |
4645 | case IP_VERSION(3, 0, 1): | |
4646 | case IP_VERSION(3, 1, 2): | |
4647 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4648 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4649 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4650 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4651 | case IP_VERSION(3, 2, 0): |
4652 | case IP_VERSION(3, 2, 1): | |
06b1661e | 4653 | case IP_VERSION(3, 5, 0): |
c08182f2 AD |
4654 | if (dcn10_register_irq_handlers(dm->adev)) { |
4655 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4656 | goto fail; | |
4657 | } | |
4658 | break; | |
4659 | default: | |
2cbc6f42 | 4660 | DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", |
4e8303cf | 4661 | amdgpu_ip_version(adev, DCE_HWIP, 0)); |
2cbc6f42 | 4662 | goto fail; |
c08182f2 | 4663 | } |
2cbc6f42 | 4664 | break; |
4562236b HW |
4665 | } |
4666 | ||
4562236b | 4667 | return 0; |
cd8a2ae8 | 4668 | fail: |
4562236b | 4669 | kfree(aencoder); |
4562236b | 4670 | kfree(aconnector); |
54087768 | 4671 | |
59d0f396 | 4672 | return -EINVAL; |
4562236b HW |
4673 | } |
4674 | ||
7578ecda | 4675 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) |
4562236b | 4676 | { |
eb3dc897 | 4677 | drm_atomic_private_obj_fini(&dm->atomic_obj); |
4562236b HW |
4678 | } |
4679 | ||
4680 | /****************************************************************************** | |
4681 | * amdgpu_display_funcs functions | |
4682 | *****************************************************************************/ | |
4683 | ||
1f6010a9 | 4684 | /* |
4562236b HW |
4685 | * dm_bandwidth_update - program display watermarks |
4686 | * | |
4687 | * @adev: amdgpu_device pointer | |
4688 | * | |
4689 | * Calculate and program the display watermarks and line buffer allocation. | |
4690 | */ | |
4691 | static void dm_bandwidth_update(struct amdgpu_device *adev) | |
4692 | { | |
49c07a99 | 4693 | /* TODO: implement later */ |
4562236b HW |
4694 | } |
4695 | ||
39cc5be2 | 4696 | static const struct amdgpu_display_funcs dm_display_funcs = { |
4562236b HW |
4697 | .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ |
4698 | .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ | |
7b42573b HW |
4699 | .backlight_set_level = NULL, /* never called for DC */ |
4700 | .backlight_get_level = NULL, /* never called for DC */ | |
4562236b HW |
4701 | .hpd_sense = NULL,/* called unconditionally */ |
4702 | .hpd_set_polarity = NULL, /* called unconditionally */ | |
4703 | .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
4704 | .page_flip_get_scanoutpos = |
4705 | dm_crtc_get_scanoutpos,/* called unconditionally */ | |
4706 | .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ | |
4707 | .add_connector = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
4708 | }; |
4709 | ||
4710 | #if defined(CONFIG_DEBUG_KERNEL_DC) | |
4711 | ||
3ee6b26b AD |
4712 | static ssize_t s3_debug_store(struct device *device, |
4713 | struct device_attribute *attr, | |
4714 | const char *buf, | |
4715 | size_t count) | |
4562236b HW |
4716 | { |
4717 | int ret; | |
4718 | int s3_state; | |
ef1de361 | 4719 | struct drm_device *drm_dev = dev_get_drvdata(device); |
1348969a | 4720 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
4562236b HW |
4721 | |
4722 | ret = kstrtoint(buf, 0, &s3_state); | |
4723 | ||
4724 | if (ret == 0) { | |
4725 | if (s3_state) { | |
4726 | dm_resume(adev); | |
4a580877 | 4727 | drm_kms_helper_hotplug_event(adev_to_drm(adev)); |
4562236b HW |
4728 | } else |
4729 | dm_suspend(adev); | |
4730 | } | |
4731 | ||
4732 | return ret == 0 ? count : 0; | |
4733 | } | |
4734 | ||
4735 | DEVICE_ATTR_WO(s3_debug); | |
4736 | ||
4737 | #endif | |
4738 | ||
a7ab3451 ML |
4739 | static int dm_init_microcode(struct amdgpu_device *adev) |
4740 | { | |
4741 | char *fw_name_dmub; | |
4742 | int r; | |
4743 | ||
4e8303cf | 4744 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
a7ab3451 ML |
4745 | case IP_VERSION(2, 1, 0): |
4746 | fw_name_dmub = FIRMWARE_RENOIR_DMUB; | |
4747 | if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) | |
4748 | fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; | |
4749 | break; | |
4750 | case IP_VERSION(3, 0, 0): | |
4e8303cf | 4751 | if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) |
a7ab3451 ML |
4752 | fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; |
4753 | else | |
4754 | fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; | |
4755 | break; | |
4756 | case IP_VERSION(3, 0, 1): | |
4757 | fw_name_dmub = FIRMWARE_VANGOGH_DMUB; | |
4758 | break; | |
4759 | case IP_VERSION(3, 0, 2): | |
4760 | fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; | |
4761 | break; | |
4762 | case IP_VERSION(3, 0, 3): | |
4763 | fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; | |
4764 | break; | |
4765 | case IP_VERSION(3, 1, 2): | |
4766 | case IP_VERSION(3, 1, 3): | |
4767 | fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; | |
4768 | break; | |
4769 | case IP_VERSION(3, 1, 4): | |
4770 | fw_name_dmub = FIRMWARE_DCN_314_DMUB; | |
4771 | break; | |
4772 | case IP_VERSION(3, 1, 5): | |
4773 | fw_name_dmub = FIRMWARE_DCN_315_DMUB; | |
4774 | break; | |
4775 | case IP_VERSION(3, 1, 6): | |
4776 | fw_name_dmub = FIRMWARE_DCN316_DMUB; | |
4777 | break; | |
4778 | case IP_VERSION(3, 2, 0): | |
4779 | fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; | |
4780 | break; | |
4781 | case IP_VERSION(3, 2, 1): | |
4782 | fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; | |
4783 | break; | |
06b1661e QZ |
4784 | case IP_VERSION(3, 5, 0): |
4785 | fw_name_dmub = FIRMWARE_DCN_35_DMUB; | |
4786 | break; | |
a7ab3451 ML |
4787 | default: |
4788 | /* ASIC doesn't support DMUB. */ | |
4789 | return 0; | |
4790 | } | |
4791 | r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); | |
a7ab3451 ML |
4792 | return r; |
4793 | } | |
4794 | ||
4562236b HW |
4795 | static int dm_early_init(void *handle) |
4796 | { | |
4797 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
44900af0 AD |
4798 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
4799 | struct atom_context *ctx = mode_info->atom_context; | |
4800 | int index = GetIndexIntoMasterTable(DATA, Object_Header); | |
4801 | u16 data_offset; | |
4802 | ||
4803 | /* if there is no object header, skip DM */ | |
4804 | if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { | |
4805 | adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; | |
4806 | dev_info(adev->dev, "No object header, skipping DM\n"); | |
4807 | return -ENOENT; | |
4808 | } | |
4562236b | 4809 | |
4562236b | 4810 | switch (adev->asic_type) { |
55e56389 MR |
4811 | #if defined(CONFIG_DRM_AMD_DC_SI) |
4812 | case CHIP_TAHITI: | |
4813 | case CHIP_PITCAIRN: | |
4814 | case CHIP_VERDE: | |
4815 | adev->mode_info.num_crtc = 6; | |
4816 | adev->mode_info.num_hpd = 6; | |
4817 | adev->mode_info.num_dig = 6; | |
4818 | break; | |
4819 | case CHIP_OLAND: | |
4820 | adev->mode_info.num_crtc = 2; | |
4821 | adev->mode_info.num_hpd = 2; | |
4822 | adev->mode_info.num_dig = 2; | |
4823 | break; | |
4824 | #endif | |
4562236b HW |
4825 | case CHIP_BONAIRE: |
4826 | case CHIP_HAWAII: | |
4827 | adev->mode_info.num_crtc = 6; | |
4828 | adev->mode_info.num_hpd = 6; | |
4829 | adev->mode_info.num_dig = 6; | |
4562236b | 4830 | break; |
cd4b356f AD |
4831 | case CHIP_KAVERI: |
4832 | adev->mode_info.num_crtc = 4; | |
4833 | adev->mode_info.num_hpd = 6; | |
4834 | adev->mode_info.num_dig = 7; | |
cd4b356f AD |
4835 | break; |
4836 | case CHIP_KABINI: | |
4837 | case CHIP_MULLINS: | |
4838 | adev->mode_info.num_crtc = 2; | |
4839 | adev->mode_info.num_hpd = 6; | |
4840 | adev->mode_info.num_dig = 6; | |
cd4b356f | 4841 | break; |
4562236b HW |
4842 | case CHIP_FIJI: |
4843 | case CHIP_TONGA: | |
4844 | adev->mode_info.num_crtc = 6; | |
4845 | adev->mode_info.num_hpd = 6; | |
4846 | adev->mode_info.num_dig = 7; | |
4562236b HW |
4847 | break; |
4848 | case CHIP_CARRIZO: | |
4849 | adev->mode_info.num_crtc = 3; | |
4850 | adev->mode_info.num_hpd = 6; | |
4851 | adev->mode_info.num_dig = 9; | |
4562236b HW |
4852 | break; |
4853 | case CHIP_STONEY: | |
4854 | adev->mode_info.num_crtc = 2; | |
4855 | adev->mode_info.num_hpd = 6; | |
4856 | adev->mode_info.num_dig = 9; | |
4562236b HW |
4857 | break; |
4858 | case CHIP_POLARIS11: | |
b264d345 | 4859 | case CHIP_POLARIS12: |
4562236b HW |
4860 | adev->mode_info.num_crtc = 5; |
4861 | adev->mode_info.num_hpd = 5; | |
4862 | adev->mode_info.num_dig = 5; | |
4562236b HW |
4863 | break; |
4864 | case CHIP_POLARIS10: | |
7737de91 | 4865 | case CHIP_VEGAM: |
4562236b HW |
4866 | adev->mode_info.num_crtc = 6; |
4867 | adev->mode_info.num_hpd = 6; | |
4868 | adev->mode_info.num_dig = 6; | |
4562236b | 4869 | break; |
2c8ad2d5 | 4870 | case CHIP_VEGA10: |
2325ff30 | 4871 | case CHIP_VEGA12: |
1fe6bf2f | 4872 | case CHIP_VEGA20: |
2c8ad2d5 AD |
4873 | adev->mode_info.num_crtc = 6; |
4874 | adev->mode_info.num_hpd = 6; | |
4875 | adev->mode_info.num_dig = 6; | |
4876 | break; | |
4562236b | 4877 | default: |
cae5c1ab | 4878 | |
4e8303cf | 4879 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
c08182f2 AD |
4880 | case IP_VERSION(2, 0, 2): |
4881 | case IP_VERSION(3, 0, 0): | |
4882 | adev->mode_info.num_crtc = 6; | |
4883 | adev->mode_info.num_hpd = 6; | |
4884 | adev->mode_info.num_dig = 6; | |
4885 | break; | |
4886 | case IP_VERSION(2, 0, 0): | |
4887 | case IP_VERSION(3, 0, 2): | |
4888 | adev->mode_info.num_crtc = 5; | |
4889 | adev->mode_info.num_hpd = 5; | |
4890 | adev->mode_info.num_dig = 5; | |
4891 | break; | |
4892 | case IP_VERSION(2, 0, 3): | |
4893 | case IP_VERSION(3, 0, 3): | |
4894 | adev->mode_info.num_crtc = 2; | |
4895 | adev->mode_info.num_hpd = 2; | |
4896 | adev->mode_info.num_dig = 2; | |
4897 | break; | |
559f591d AD |
4898 | case IP_VERSION(1, 0, 0): |
4899 | case IP_VERSION(1, 0, 1): | |
c08182f2 AD |
4900 | case IP_VERSION(3, 0, 1): |
4901 | case IP_VERSION(2, 1, 0): | |
4902 | case IP_VERSION(3, 1, 2): | |
4903 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4904 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4905 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4906 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4907 | case IP_VERSION(3, 2, 0): |
4908 | case IP_VERSION(3, 2, 1): | |
06b1661e | 4909 | case IP_VERSION(3, 5, 0): |
c08182f2 AD |
4910 | adev->mode_info.num_crtc = 4; |
4911 | adev->mode_info.num_hpd = 4; | |
4912 | adev->mode_info.num_dig = 4; | |
4913 | break; | |
4914 | default: | |
2cbc6f42 | 4915 | DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", |
4e8303cf | 4916 | amdgpu_ip_version(adev, DCE_HWIP, 0)); |
2cbc6f42 | 4917 | return -EINVAL; |
c08182f2 | 4918 | } |
2cbc6f42 | 4919 | break; |
4562236b HW |
4920 | } |
4921 | ||
39cc5be2 AD |
4922 | if (adev->mode_info.funcs == NULL) |
4923 | adev->mode_info.funcs = &dm_display_funcs; | |
4924 | ||
1f6010a9 DF |
4925 | /* |
4926 | * Note: Do NOT change adev->audio_endpt_rreg and | |
4562236b | 4927 | * adev->audio_endpt_wreg because they are initialised in |
1f6010a9 DF |
4928 | * amdgpu_device_init() |
4929 | */ | |
4562236b HW |
4930 | #if defined(CONFIG_DEBUG_KERNEL_DC) |
4931 | device_create_file( | |
4a580877 | 4932 | adev_to_drm(adev)->dev, |
4562236b HW |
4933 | &dev_attr_s3_debug); |
4934 | #endif | |
d09ef243 | 4935 | adev->dc_enabled = true; |
4562236b | 4936 | |
a7ab3451 | 4937 | return dm_init_microcode(adev); |
4562236b HW |
4938 | } |
4939 | ||
e7b07cee HW |
4940 | static bool modereset_required(struct drm_crtc_state *crtc_state) |
4941 | { | |
2afda735 | 4942 | return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); |
e7b07cee HW |
4943 | } |
4944 | ||
7578ecda | 4945 | static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) |
e7b07cee HW |
4946 | { |
4947 | drm_encoder_cleanup(encoder); | |
4948 | kfree(encoder); | |
4949 | } | |
4950 | ||
4951 | static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { | |
4952 | .destroy = amdgpu_dm_encoder_destroy, | |
4953 | }; | |
4954 | ||
5d945cbc RS |
4955 | static int |
4956 | fill_plane_color_attributes(const struct drm_plane_state *plane_state, | |
4957 | const enum surface_pixel_format format, | |
4958 | enum dc_color_space *color_space) | |
6300b3bd | 4959 | { |
5d945cbc | 4960 | bool full_range; |
6300b3bd | 4961 | |
5d945cbc RS |
4962 | *color_space = COLOR_SPACE_SRGB; |
4963 | ||
4964 | /* DRM color properties only affect non-RGB formats. */ | |
4965 | if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) | |
4966 | return 0; | |
4967 | ||
4968 | full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); | |
4969 | ||
4970 | switch (plane_state->color_encoding) { | |
4971 | case DRM_COLOR_YCBCR_BT601: | |
4972 | if (full_range) | |
4973 | *color_space = COLOR_SPACE_YCBCR601; | |
4974 | else | |
4975 | *color_space = COLOR_SPACE_YCBCR601_LIMITED; | |
6300b3bd MK |
4976 | break; |
4977 | ||
5d945cbc RS |
4978 | case DRM_COLOR_YCBCR_BT709: |
4979 | if (full_range) | |
4980 | *color_space = COLOR_SPACE_YCBCR709; | |
4981 | else | |
4982 | *color_space = COLOR_SPACE_YCBCR709_LIMITED; | |
6300b3bd MK |
4983 | break; |
4984 | ||
5d945cbc RS |
4985 | case DRM_COLOR_YCBCR_BT2020: |
4986 | if (full_range) | |
4987 | *color_space = COLOR_SPACE_2020_YCBCR; | |
4988 | else | |
4989 | return -EINVAL; | |
6300b3bd | 4990 | break; |
6300b3bd | 4991 | |
5d945cbc RS |
4992 | default: |
4993 | return -EINVAL; | |
4994 | } | |
6300b3bd | 4995 | |
5d945cbc | 4996 | return 0; |
6300b3bd MK |
4997 | } |
4998 | ||
5d945cbc RS |
4999 | static int |
5000 | fill_dc_plane_info_and_addr(struct amdgpu_device *adev, | |
5001 | const struct drm_plane_state *plane_state, | |
ae67558b | 5002 | const u64 tiling_flags, |
5d945cbc RS |
5003 | struct dc_plane_info *plane_info, |
5004 | struct dc_plane_address *address, | |
5005 | bool tmz_surface, | |
5006 | bool force_disable_dcc) | |
e7b07cee | 5007 | { |
5d945cbc RS |
5008 | const struct drm_framebuffer *fb = plane_state->fb; |
5009 | const struct amdgpu_framebuffer *afb = | |
5010 | to_amdgpu_framebuffer(plane_state->fb); | |
5011 | int ret; | |
e7b07cee | 5012 | |
5d945cbc | 5013 | memset(plane_info, 0, sizeof(*plane_info)); |
e7b07cee | 5014 | |
5d945cbc RS |
5015 | switch (fb->format->format) { |
5016 | case DRM_FORMAT_C8: | |
5017 | plane_info->format = | |
5018 | SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; | |
5019 | break; | |
5020 | case DRM_FORMAT_RGB565: | |
5021 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; | |
5022 | break; | |
5023 | case DRM_FORMAT_XRGB8888: | |
5024 | case DRM_FORMAT_ARGB8888: | |
5025 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; | |
5026 | break; | |
5027 | case DRM_FORMAT_XRGB2101010: | |
5028 | case DRM_FORMAT_ARGB2101010: | |
5029 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; | |
5030 | break; | |
5031 | case DRM_FORMAT_XBGR2101010: | |
5032 | case DRM_FORMAT_ABGR2101010: | |
5033 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; | |
5034 | break; | |
5035 | case DRM_FORMAT_XBGR8888: | |
5036 | case DRM_FORMAT_ABGR8888: | |
5037 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; | |
5038 | break; | |
5039 | case DRM_FORMAT_NV21: | |
5040 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; | |
5041 | break; | |
5042 | case DRM_FORMAT_NV12: | |
5043 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; | |
5044 | break; | |
5045 | case DRM_FORMAT_P010: | |
5046 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; | |
5047 | break; | |
5048 | case DRM_FORMAT_XRGB16161616F: | |
5049 | case DRM_FORMAT_ARGB16161616F: | |
5050 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; | |
5051 | break; | |
5052 | case DRM_FORMAT_XBGR16161616F: | |
5053 | case DRM_FORMAT_ABGR16161616F: | |
5054 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; | |
5055 | break; | |
5056 | case DRM_FORMAT_XRGB16161616: | |
5057 | case DRM_FORMAT_ARGB16161616: | |
5058 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; | |
5059 | break; | |
5060 | case DRM_FORMAT_XBGR16161616: | |
5061 | case DRM_FORMAT_ABGR16161616: | |
5062 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; | |
5063 | break; | |
5064 | default: | |
5065 | DRM_ERROR( | |
5066 | "Unsupported screen format %p4cc\n", | |
5067 | &fb->format->format); | |
d89f6048 | 5068 | return -EINVAL; |
5d945cbc | 5069 | } |
d89f6048 | 5070 | |
5d945cbc RS |
5071 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { |
5072 | case DRM_MODE_ROTATE_0: | |
5073 | plane_info->rotation = ROTATION_ANGLE_0; | |
5074 | break; | |
5075 | case DRM_MODE_ROTATE_90: | |
5076 | plane_info->rotation = ROTATION_ANGLE_90; | |
5077 | break; | |
5078 | case DRM_MODE_ROTATE_180: | |
5079 | plane_info->rotation = ROTATION_ANGLE_180; | |
5080 | break; | |
5081 | case DRM_MODE_ROTATE_270: | |
5082 | plane_info->rotation = ROTATION_ANGLE_270; | |
5083 | break; | |
5084 | default: | |
5085 | plane_info->rotation = ROTATION_ANGLE_0; | |
5086 | break; | |
5087 | } | |
695af5f9 | 5088 | |
695af5f9 | 5089 | |
5d945cbc RS |
5090 | plane_info->visible = true; |
5091 | plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; | |
e7b07cee | 5092 | |
22c42b0e | 5093 | plane_info->layer_index = plane_state->normalized_zpos; |
e7b07cee | 5094 | |
5d945cbc RS |
5095 | ret = fill_plane_color_attributes(plane_state, plane_info->format, |
5096 | &plane_info->color_space); | |
5097 | if (ret) | |
5098 | return ret; | |
e7b07cee | 5099 | |
8bf0d9cd | 5100 | ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, |
5d945cbc RS |
5101 | plane_info->rotation, tiling_flags, |
5102 | &plane_info->tiling_info, | |
5103 | &plane_info->plane_size, | |
5104 | &plane_info->dcc, address, | |
5105 | tmz_surface, force_disable_dcc); | |
5106 | if (ret) | |
5107 | return ret; | |
e7b07cee | 5108 | |
8bf0d9cd | 5109 | amdgpu_dm_plane_fill_blending_from_plane_state( |
5d945cbc RS |
5110 | plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, |
5111 | &plane_info->global_alpha, &plane_info->global_alpha_value); | |
e7b07cee | 5112 | |
5d945cbc RS |
5113 | return 0; |
5114 | } | |
e7b07cee | 5115 | |
5d945cbc RS |
5116 | static int fill_dc_plane_attributes(struct amdgpu_device *adev, |
5117 | struct dc_plane_state *dc_plane_state, | |
5118 | struct drm_plane_state *plane_state, | |
5119 | struct drm_crtc_state *crtc_state) | |
5120 | { | |
5121 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); | |
5122 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; | |
5123 | struct dc_scaling_info scaling_info; | |
5124 | struct dc_plane_info plane_info; | |
5125 | int ret; | |
5126 | bool force_disable_dcc = false; | |
6300b3bd | 5127 | |
8bf0d9cd | 5128 | ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); |
5d945cbc RS |
5129 | if (ret) |
5130 | return ret; | |
e7b07cee | 5131 | |
5d945cbc RS |
5132 | dc_plane_state->src_rect = scaling_info.src_rect; |
5133 | dc_plane_state->dst_rect = scaling_info.dst_rect; | |
5134 | dc_plane_state->clip_rect = scaling_info.clip_rect; | |
5135 | dc_plane_state->scaling_quality = scaling_info.scaling_quality; | |
6491f0c0 | 5136 | |
5d945cbc RS |
5137 | force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; |
5138 | ret = fill_dc_plane_info_and_addr(adev, plane_state, | |
5139 | afb->tiling_flags, | |
5140 | &plane_info, | |
5141 | &dc_plane_state->address, | |
5142 | afb->tmz_surface, | |
5143 | force_disable_dcc); | |
5144 | if (ret) | |
5145 | return ret; | |
6491f0c0 | 5146 | |
5d945cbc RS |
5147 | dc_plane_state->format = plane_info.format; |
5148 | dc_plane_state->color_space = plane_info.color_space; | |
5149 | dc_plane_state->format = plane_info.format; | |
5150 | dc_plane_state->plane_size = plane_info.plane_size; | |
5151 | dc_plane_state->rotation = plane_info.rotation; | |
5152 | dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; | |
5153 | dc_plane_state->stereo_format = plane_info.stereo_format; | |
5154 | dc_plane_state->tiling_info = plane_info.tiling_info; | |
5155 | dc_plane_state->visible = plane_info.visible; | |
5156 | dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; | |
5157 | dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; | |
5158 | dc_plane_state->global_alpha = plane_info.global_alpha; | |
5159 | dc_plane_state->global_alpha_value = plane_info.global_alpha_value; | |
5160 | dc_plane_state->dcc = plane_info.dcc; | |
22c42b0e | 5161 | dc_plane_state->layer_index = plane_info.layer_index; |
5d945cbc | 5162 | dc_plane_state->flip_int_enabled = true; |
6491f0c0 | 5163 | |
695af5f9 | 5164 | /* |
5d945cbc RS |
5165 | * Always set input transfer function, since plane state is refreshed |
5166 | * every time. | |
695af5f9 | 5167 | */ |
5d945cbc RS |
5168 | ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); |
5169 | if (ret) | |
5170 | return ret; | |
e7b07cee | 5171 | |
695af5f9 | 5172 | return 0; |
4562236b | 5173 | } |
695af5f9 | 5174 | |
30ebe415 HM |
5175 | static inline void fill_dc_dirty_rect(struct drm_plane *plane, |
5176 | struct rect *dirty_rect, int32_t x, | |
ae67558b | 5177 | s32 y, s32 width, s32 height, |
30ebe415 HM |
5178 | int *i, bool ffu) |
5179 | { | |
af22d6a8 | 5180 | WARN_ON(*i >= DC_MAX_DIRTY_RECTS); |
30ebe415 HM |
5181 | |
5182 | dirty_rect->x = x; | |
5183 | dirty_rect->y = y; | |
5184 | dirty_rect->width = width; | |
5185 | dirty_rect->height = height; | |
5186 | ||
5187 | if (ffu) | |
5188 | drm_dbg(plane->dev, | |
5189 | "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", | |
5190 | plane->base.id, width, height); | |
5191 | else | |
5192 | drm_dbg(plane->dev, | |
5193 | "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", | |
5194 | plane->base.id, x, y, width, height); | |
5195 | ||
30ebe415 HM |
5196 | (*i)++; |
5197 | } | |
5198 | ||
5d945cbc RS |
5199 | /** |
5200 | * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates | |
5201 | * | |
5202 | * @plane: DRM plane containing dirty regions that need to be flushed to the eDP | |
5203 | * remote fb | |
5204 | * @old_plane_state: Old state of @plane | |
5205 | * @new_plane_state: New state of @plane | |
5206 | * @crtc_state: New state of CRTC connected to the @plane | |
5207 | * @flip_addrs: DC flip tracking struct, which also tracts dirty rects | |
d6ed6d0d | 5208 | * @dirty_regions_changed: dirty regions changed |
5d945cbc RS |
5209 | * |
5210 | * For PSR SU, DC informs the DMUB uController of dirty rectangle regions | |
5211 | * (referred to as "damage clips" in DRM nomenclature) that require updating on | |
5212 | * the eDP remote buffer. The responsibility of specifying the dirty regions is | |
5213 | * amdgpu_dm's. | |
5214 | * | |
5215 | * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the | |
5216 | * plane with regions that require flushing to the eDP remote buffer. In | |
5217 | * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - | |
5218 | * implicitly provide damage clips without any client support via the plane | |
5219 | * bounds. | |
5d945cbc RS |
5220 | */ |
5221 | static void fill_dc_dirty_rects(struct drm_plane *plane, | |
5222 | struct drm_plane_state *old_plane_state, | |
5223 | struct drm_plane_state *new_plane_state, | |
5224 | struct drm_crtc_state *crtc_state, | |
d6ed6d0d TC |
5225 | struct dc_flip_addrs *flip_addrs, |
5226 | bool *dirty_regions_changed) | |
5d945cbc RS |
5227 | { |
5228 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); | |
5229 | struct rect *dirty_rects = flip_addrs->dirty_rects; | |
ae67558b | 5230 | u32 num_clips; |
30ebe415 | 5231 | struct drm_mode_rect *clips; |
5d945cbc RS |
5232 | bool bb_changed; |
5233 | bool fb_changed; | |
ae67558b | 5234 | u32 i = 0; |
d6ed6d0d | 5235 | *dirty_regions_changed = false; |
e7b07cee | 5236 | |
7cc191ee LL |
5237 | /* |
5238 | * Cursor plane has it's own dirty rect update interface. See | |
5239 | * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data | |
5240 | */ | |
5241 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
5242 | return; | |
5243 | ||
30ebe415 HM |
5244 | num_clips = drm_plane_get_damage_clips_count(new_plane_state); |
5245 | clips = drm_plane_get_damage_clips(new_plane_state); | |
5246 | ||
7cc191ee | 5247 | if (!dm_crtc_state->mpo_requested) { |
30ebe415 HM |
5248 | if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) |
5249 | goto ffu; | |
5250 | ||
5251 | for (; flip_addrs->dirty_rect_count < num_clips; clips++) | |
5252 | fill_dc_dirty_rect(new_plane_state->plane, | |
566b6577 BC |
5253 | &dirty_rects[flip_addrs->dirty_rect_count], |
5254 | clips->x1, clips->y1, | |
5255 | clips->x2 - clips->x1, clips->y2 - clips->y1, | |
30ebe415 HM |
5256 | &flip_addrs->dirty_rect_count, |
5257 | false); | |
7cc191ee LL |
5258 | return; |
5259 | } | |
5260 | ||
5261 | /* | |
5262 | * MPO is requested. Add entire plane bounding box to dirty rects if | |
5263 | * flipped to or damaged. | |
5264 | * | |
5265 | * If plane is moved or resized, also add old bounding box to dirty | |
5266 | * rects. | |
5267 | */ | |
7cc191ee LL |
5268 | fb_changed = old_plane_state->fb->base.id != |
5269 | new_plane_state->fb->base.id; | |
5270 | bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || | |
5271 | old_plane_state->crtc_y != new_plane_state->crtc_y || | |
5272 | old_plane_state->crtc_w != new_plane_state->crtc_w || | |
5273 | old_plane_state->crtc_h != new_plane_state->crtc_h); | |
5274 | ||
30ebe415 HM |
5275 | drm_dbg(plane->dev, |
5276 | "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", | |
5277 | new_plane_state->plane->base.id, | |
5278 | bb_changed, fb_changed, num_clips); | |
7cc191ee | 5279 | |
d6ed6d0d TC |
5280 | *dirty_regions_changed = bb_changed; |
5281 | ||
af22d6a8 HM |
5282 | if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) |
5283 | goto ffu; | |
5284 | ||
7cc191ee | 5285 | if (bb_changed) { |
30ebe415 HM |
5286 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], |
5287 | new_plane_state->crtc_x, | |
5288 | new_plane_state->crtc_y, | |
5289 | new_plane_state->crtc_w, | |
5290 | new_plane_state->crtc_h, &i, false); | |
5291 | ||
5292 | /* Add old plane bounding-box if plane is moved or resized */ | |
5293 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], | |
5294 | old_plane_state->crtc_x, | |
5295 | old_plane_state->crtc_y, | |
5296 | old_plane_state->crtc_w, | |
5297 | old_plane_state->crtc_h, &i, false); | |
5298 | } | |
5299 | ||
5300 | if (num_clips) { | |
5301 | for (; i < num_clips; clips++) | |
5302 | fill_dc_dirty_rect(new_plane_state->plane, | |
5303 | &dirty_rects[i], clips->x1, | |
5304 | clips->y1, clips->x2 - clips->x1, | |
5305 | clips->y2 - clips->y1, &i, false); | |
5306 | } else if (fb_changed && !bb_changed) { | |
5307 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], | |
5308 | new_plane_state->crtc_x, | |
5309 | new_plane_state->crtc_y, | |
5310 | new_plane_state->crtc_w, | |
5311 | new_plane_state->crtc_h, &i, false); | |
5312 | } | |
5313 | ||
7cc191ee | 5314 | flip_addrs->dirty_rect_count = i; |
30ebe415 HM |
5315 | return; |
5316 | ||
5317 | ffu: | |
5318 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, | |
5319 | dm_crtc_state->base.mode.crtc_hdisplay, | |
5320 | dm_crtc_state->base.mode.crtc_vdisplay, | |
5321 | &flip_addrs->dirty_rect_count, true); | |
7cc191ee LL |
5322 | } |
5323 | ||
3ee6b26b AD |
5324 | static void update_stream_scaling_settings(const struct drm_display_mode *mode, |
5325 | const struct dm_connector_state *dm_state, | |
5326 | struct dc_stream_state *stream) | |
e7b07cee HW |
5327 | { |
5328 | enum amdgpu_rmx_type rmx_type; | |
5329 | ||
5330 | struct rect src = { 0 }; /* viewport in composition space*/ | |
5331 | struct rect dst = { 0 }; /* stream addressable area */ | |
5332 | ||
5333 | /* no mode. nothing to be done */ | |
5334 | if (!mode) | |
5335 | return; | |
5336 | ||
5337 | /* Full screen scaling by default */ | |
5338 | src.width = mode->hdisplay; | |
5339 | src.height = mode->vdisplay; | |
5340 | dst.width = stream->timing.h_addressable; | |
5341 | dst.height = stream->timing.v_addressable; | |
5342 | ||
f4791779 HW |
5343 | if (dm_state) { |
5344 | rmx_type = dm_state->scaling; | |
5345 | if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { | |
5346 | if (src.width * dst.height < | |
5347 | src.height * dst.width) { | |
5348 | /* height needs less upscaling/more downscaling */ | |
5349 | dst.width = src.width * | |
5350 | dst.height / src.height; | |
5351 | } else { | |
5352 | /* width needs less upscaling/more downscaling */ | |
5353 | dst.height = src.height * | |
5354 | dst.width / src.width; | |
5355 | } | |
5356 | } else if (rmx_type == RMX_CENTER) { | |
5357 | dst = src; | |
e7b07cee | 5358 | } |
e7b07cee | 5359 | |
f4791779 HW |
5360 | dst.x = (stream->timing.h_addressable - dst.width) / 2; |
5361 | dst.y = (stream->timing.v_addressable - dst.height) / 2; | |
e7b07cee | 5362 | |
f4791779 HW |
5363 | if (dm_state->underscan_enable) { |
5364 | dst.x += dm_state->underscan_hborder / 2; | |
5365 | dst.y += dm_state->underscan_vborder / 2; | |
5366 | dst.width -= dm_state->underscan_hborder; | |
5367 | dst.height -= dm_state->underscan_vborder; | |
5368 | } | |
e7b07cee HW |
5369 | } |
5370 | ||
5371 | stream->src = src; | |
5372 | stream->dst = dst; | |
5373 | ||
4711c033 LT |
5374 | DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", |
5375 | dst.x, dst.y, dst.width, dst.height); | |
e7b07cee HW |
5376 | |
5377 | } | |
5378 | ||
3ee6b26b | 5379 | static enum dc_color_depth |
42ba01fc | 5380 | convert_color_depth_from_display_info(const struct drm_connector *connector, |
cbd14ae7 | 5381 | bool is_y420, int requested_bpc) |
e7b07cee | 5382 | { |
ae67558b | 5383 | u8 bpc; |
01c22997 | 5384 | |
1bc22f20 SW |
5385 | if (is_y420) { |
5386 | bpc = 8; | |
5387 | ||
5388 | /* Cap display bpc based on HDMI 2.0 HF-VSDB */ | |
5389 | if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) | |
5390 | bpc = 16; | |
5391 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) | |
5392 | bpc = 12; | |
5393 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) | |
5394 | bpc = 10; | |
5395 | } else { | |
5396 | bpc = (uint8_t)connector->display_info.bpc; | |
5397 | /* Assume 8 bpc by default if no bpc is specified. */ | |
5398 | bpc = bpc ? bpc : 8; | |
5399 | } | |
e7b07cee | 5400 | |
cbd14ae7 | 5401 | if (requested_bpc > 0) { |
01c22997 NK |
5402 | /* |
5403 | * Cap display bpc based on the user requested value. | |
5404 | * | |
5405 | * The value for state->max_bpc may not correctly updated | |
5406 | * depending on when the connector gets added to the state | |
5407 | * or if this was called outside of atomic check, so it | |
5408 | * can't be used directly. | |
5409 | */ | |
cbd14ae7 | 5410 | bpc = min_t(u8, bpc, requested_bpc); |
01c22997 | 5411 | |
1825fd34 NK |
5412 | /* Round down to the nearest even number. */ |
5413 | bpc = bpc - (bpc & 1); | |
5414 | } | |
07e3a1cf | 5415 | |
e7b07cee HW |
5416 | switch (bpc) { |
5417 | case 0: | |
1f6010a9 DF |
5418 | /* |
5419 | * Temporary Work around, DRM doesn't parse color depth for | |
e7b07cee HW |
5420 | * EDID revision before 1.4 |
5421 | * TODO: Fix edid parsing | |
5422 | */ | |
5423 | return COLOR_DEPTH_888; | |
5424 | case 6: | |
5425 | return COLOR_DEPTH_666; | |
5426 | case 8: | |
5427 | return COLOR_DEPTH_888; | |
5428 | case 10: | |
5429 | return COLOR_DEPTH_101010; | |
5430 | case 12: | |
5431 | return COLOR_DEPTH_121212; | |
5432 | case 14: | |
5433 | return COLOR_DEPTH_141414; | |
5434 | case 16: | |
5435 | return COLOR_DEPTH_161616; | |
5436 | default: | |
5437 | return COLOR_DEPTH_UNDEFINED; | |
5438 | } | |
5439 | } | |
5440 | ||
3ee6b26b AD |
5441 | static enum dc_aspect_ratio |
5442 | get_aspect_ratio(const struct drm_display_mode *mode_in) | |
e7b07cee | 5443 | { |
e11d4147 LSL |
5444 | /* 1-1 mapping, since both enums follow the HDMI spec. */ |
5445 | return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; | |
e7b07cee HW |
5446 | } |
5447 | ||
3ee6b26b | 5448 | static enum dc_color_space |
2e656827 HW |
5449 | get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, |
5450 | const struct drm_connector_state *connector_state) | |
e7b07cee HW |
5451 | { |
5452 | enum dc_color_space color_space = COLOR_SPACE_SRGB; | |
5453 | ||
2e656827 HW |
5454 | switch (connector_state->colorspace) { |
5455 | case DRM_MODE_COLORIMETRY_BT601_YCC: | |
5456 | if (dc_crtc_timing->flags.Y_ONLY) | |
5457 | color_space = COLOR_SPACE_YCBCR601_LIMITED; | |
5458 | else | |
5459 | color_space = COLOR_SPACE_YCBCR601; | |
5460 | break; | |
5461 | case DRM_MODE_COLORIMETRY_BT709_YCC: | |
5462 | if (dc_crtc_timing->flags.Y_ONLY) | |
5463 | color_space = COLOR_SPACE_YCBCR709_LIMITED; | |
5464 | else | |
5465 | color_space = COLOR_SPACE_YCBCR709; | |
5466 | break; | |
5467 | case DRM_MODE_COLORIMETRY_OPRGB: | |
5468 | color_space = COLOR_SPACE_ADOBERGB; | |
5469 | break; | |
5470 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
5471 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
5472 | if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) | |
5473 | color_space = COLOR_SPACE_2020_RGB_FULLRANGE; | |
5474 | else | |
5475 | color_space = COLOR_SPACE_2020_YCBCR; | |
5476 | break; | |
5477 | case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 | |
5478 | default: | |
5479 | if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { | |
5480 | color_space = COLOR_SPACE_SRGB; | |
e7b07cee HW |
5481 | /* |
5482 | * 27030khz is the separation point between HDTV and SDTV | |
5483 | * according to HDMI spec, we use YCbCr709 and YCbCr601 | |
5484 | * respectively | |
5485 | */ | |
2e656827 | 5486 | } else if (dc_crtc_timing->pix_clk_100hz > 270300) { |
e7b07cee HW |
5487 | if (dc_crtc_timing->flags.Y_ONLY) |
5488 | color_space = | |
5489 | COLOR_SPACE_YCBCR709_LIMITED; | |
5490 | else | |
5491 | color_space = COLOR_SPACE_YCBCR709; | |
5492 | } else { | |
5493 | if (dc_crtc_timing->flags.Y_ONLY) | |
5494 | color_space = | |
5495 | COLOR_SPACE_YCBCR601_LIMITED; | |
5496 | else | |
5497 | color_space = COLOR_SPACE_YCBCR601; | |
5498 | } | |
e7b07cee HW |
5499 | break; |
5500 | } | |
5501 | ||
5502 | return color_space; | |
5503 | } | |
5504 | ||
4c4583fd JA |
5505 | static enum display_content_type |
5506 | get_output_content_type(const struct drm_connector_state *connector_state) | |
5507 | { | |
5508 | switch (connector_state->content_type) { | |
5509 | default: | |
5510 | case DRM_MODE_CONTENT_TYPE_NO_DATA: | |
5511 | return DISPLAY_CONTENT_TYPE_NO_DATA; | |
5512 | case DRM_MODE_CONTENT_TYPE_GRAPHICS: | |
5513 | return DISPLAY_CONTENT_TYPE_GRAPHICS; | |
5514 | case DRM_MODE_CONTENT_TYPE_PHOTO: | |
5515 | return DISPLAY_CONTENT_TYPE_PHOTO; | |
5516 | case DRM_MODE_CONTENT_TYPE_CINEMA: | |
5517 | return DISPLAY_CONTENT_TYPE_CINEMA; | |
5518 | case DRM_MODE_CONTENT_TYPE_GAME: | |
5519 | return DISPLAY_CONTENT_TYPE_GAME; | |
5520 | } | |
5521 | } | |
5522 | ||
ea117312 TA |
5523 | static bool adjust_colour_depth_from_display_info( |
5524 | struct dc_crtc_timing *timing_out, | |
5525 | const struct drm_display_info *info) | |
400443e8 | 5526 | { |
ea117312 | 5527 | enum dc_color_depth depth = timing_out->display_color_depth; |
400443e8 | 5528 | int normalized_clk; |
c82eddf8 | 5529 | |
400443e8 | 5530 | do { |
380604e2 | 5531 | normalized_clk = timing_out->pix_clk_100hz / 10; |
400443e8 ML |
5532 | /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ |
5533 | if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) | |
5534 | normalized_clk /= 2; | |
5535 | /* Adjusting pix clock following on HDMI spec based on colour depth */ | |
ea117312 TA |
5536 | switch (depth) { |
5537 | case COLOR_DEPTH_888: | |
5538 | break; | |
400443e8 ML |
5539 | case COLOR_DEPTH_101010: |
5540 | normalized_clk = (normalized_clk * 30) / 24; | |
5541 | break; | |
5542 | case COLOR_DEPTH_121212: | |
5543 | normalized_clk = (normalized_clk * 36) / 24; | |
5544 | break; | |
5545 | case COLOR_DEPTH_161616: | |
5546 | normalized_clk = (normalized_clk * 48) / 24; | |
5547 | break; | |
5548 | default: | |
ea117312 TA |
5549 | /* The above depths are the only ones valid for HDMI. */ |
5550 | return false; | |
400443e8 | 5551 | } |
ea117312 TA |
5552 | if (normalized_clk <= info->max_tmds_clock) { |
5553 | timing_out->display_color_depth = depth; | |
5554 | return true; | |
5555 | } | |
5556 | } while (--depth > COLOR_DEPTH_666); | |
5557 | return false; | |
400443e8 | 5558 | } |
e7b07cee | 5559 | |
42ba01fc NK |
5560 | static void fill_stream_properties_from_drm_display_mode( |
5561 | struct dc_stream_state *stream, | |
5562 | const struct drm_display_mode *mode_in, | |
5563 | const struct drm_connector *connector, | |
5564 | const struct drm_connector_state *connector_state, | |
cbd14ae7 SW |
5565 | const struct dc_stream_state *old_stream, |
5566 | int requested_bpc) | |
e7b07cee HW |
5567 | { |
5568 | struct dc_crtc_timing *timing_out = &stream->timing; | |
fe61a2f1 | 5569 | const struct drm_display_info *info = &connector->display_info; |
7db7ade2 | 5570 | struct amdgpu_dm_connector *aconnector = NULL; |
1cb1d477 WL |
5571 | struct hdmi_vendor_infoframe hv_frame; |
5572 | struct hdmi_avi_infoframe avi_frame; | |
e7b07cee | 5573 | |
7db7ade2 HW |
5574 | if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) |
5575 | aconnector = to_amdgpu_dm_connector(connector); | |
5576 | ||
acf83f86 WL |
5577 | memset(&hv_frame, 0, sizeof(hv_frame)); |
5578 | memset(&avi_frame, 0, sizeof(avi_frame)); | |
5579 | ||
e7b07cee HW |
5580 | timing_out->h_border_left = 0; |
5581 | timing_out->h_border_right = 0; | |
5582 | timing_out->v_border_top = 0; | |
5583 | timing_out->v_border_bottom = 0; | |
5584 | /* TODO: un-hardcode */ | |
fe61a2f1 | 5585 | if (drm_mode_is_420_only(info, mode_in) |
ceb3dbb4 | 5586 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
fe61a2f1 | 5587 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
d4252eee | 5588 | else if (drm_mode_is_420_also(info, mode_in) |
3e094a28 | 5589 | && aconnector |
d4252eee SW |
5590 | && aconnector->force_yuv420_output) |
5591 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; | |
c03d0b52 | 5592 | else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) |
ceb3dbb4 | 5593 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
e7b07cee HW |
5594 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; |
5595 | else | |
5596 | timing_out->pixel_encoding = PIXEL_ENCODING_RGB; | |
5597 | ||
5598 | timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; | |
5599 | timing_out->display_color_depth = convert_color_depth_from_display_info( | |
cbd14ae7 SW |
5600 | connector, |
5601 | (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), | |
5602 | requested_bpc); | |
e7b07cee HW |
5603 | timing_out->scan_type = SCANNING_TYPE_NODATA; |
5604 | timing_out->hdmi_vic = 0; | |
b333730d | 5605 | |
5d945cbc | 5606 | if (old_stream) { |
b333730d BL |
5607 | timing_out->vic = old_stream->timing.vic; |
5608 | timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; | |
5609 | timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; | |
5610 | } else { | |
5611 | timing_out->vic = drm_match_cea_mode(mode_in); | |
5612 | if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) | |
5613 | timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; | |
5614 | if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) | |
5615 | timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; | |
5616 | } | |
e7b07cee | 5617 | |
1cb1d477 WL |
5618 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
5619 | drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); | |
5620 | timing_out->vic = avi_frame.video_code; | |
5621 | drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); | |
5622 | timing_out->hdmi_vic = hv_frame.vic; | |
5623 | } | |
5624 | ||
3e094a28 | 5625 | if (aconnector && is_freesync_video_mode(mode_in, aconnector)) { |
fe8858bb NC |
5626 | timing_out->h_addressable = mode_in->hdisplay; |
5627 | timing_out->h_total = mode_in->htotal; | |
5628 | timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; | |
5629 | timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; | |
5630 | timing_out->v_total = mode_in->vtotal; | |
5631 | timing_out->v_addressable = mode_in->vdisplay; | |
5632 | timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; | |
5633 | timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; | |
5634 | timing_out->pix_clk_100hz = mode_in->clock * 10; | |
5635 | } else { | |
5636 | timing_out->h_addressable = mode_in->crtc_hdisplay; | |
5637 | timing_out->h_total = mode_in->crtc_htotal; | |
5638 | timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; | |
5639 | timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; | |
5640 | timing_out->v_total = mode_in->crtc_vtotal; | |
5641 | timing_out->v_addressable = mode_in->crtc_vdisplay; | |
5642 | timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; | |
5643 | timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; | |
5644 | timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; | |
5645 | } | |
a85ba005 | 5646 | |
e7b07cee | 5647 | timing_out->aspect_ratio = get_aspect_ratio(mode_in); |
e7b07cee | 5648 | |
e43a432c AK |
5649 | stream->out_transfer_func->type = TF_TYPE_PREDEFINED; |
5650 | stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; | |
ea117312 TA |
5651 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
5652 | if (!adjust_colour_depth_from_display_info(timing_out, info) && | |
5653 | drm_mode_is_420_also(info, mode_in) && | |
5654 | timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { | |
5655 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; | |
5656 | adjust_colour_depth_from_display_info(timing_out, info); | |
5657 | } | |
5658 | } | |
766f1792 | 5659 | |
2e656827 | 5660 | stream->output_color_space = get_output_color_space(timing_out, connector_state); |
4c4583fd | 5661 | stream->content_type = get_output_content_type(connector_state); |
e7b07cee HW |
5662 | } |
5663 | ||
3ee6b26b AD |
5664 | static void fill_audio_info(struct audio_info *audio_info, |
5665 | const struct drm_connector *drm_connector, | |
5666 | const struct dc_sink *dc_sink) | |
e7b07cee HW |
5667 | { |
5668 | int i = 0; | |
5669 | int cea_revision = 0; | |
5670 | const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; | |
5671 | ||
5672 | audio_info->manufacture_id = edid_caps->manufacturer_id; | |
5673 | audio_info->product_id = edid_caps->product_id; | |
5674 | ||
5675 | cea_revision = drm_connector->display_info.cea_rev; | |
5676 | ||
090afc1e | 5677 | strscpy(audio_info->display_name, |
d2b2562c | 5678 | edid_caps->display_name, |
090afc1e | 5679 | AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); |
e7b07cee | 5680 | |
b830ebc9 | 5681 | if (cea_revision >= 3) { |
e7b07cee HW |
5682 | audio_info->mode_count = edid_caps->audio_mode_count; |
5683 | ||
5684 | for (i = 0; i < audio_info->mode_count; ++i) { | |
5685 | audio_info->modes[i].format_code = | |
5686 | (enum audio_format_code) | |
5687 | (edid_caps->audio_modes[i].format_code); | |
5688 | audio_info->modes[i].channel_count = | |
5689 | edid_caps->audio_modes[i].channel_count; | |
5690 | audio_info->modes[i].sample_rates.all = | |
5691 | edid_caps->audio_modes[i].sample_rate; | |
5692 | audio_info->modes[i].sample_size = | |
5693 | edid_caps->audio_modes[i].sample_size; | |
5694 | } | |
5695 | } | |
5696 | ||
5697 | audio_info->flags.all = edid_caps->speaker_flags; | |
5698 | ||
5699 | /* TODO: We only check for the progressive mode, check for interlace mode too */ | |
b830ebc9 | 5700 | if (drm_connector->latency_present[0]) { |
e7b07cee HW |
5701 | audio_info->video_latency = drm_connector->video_latency[0]; |
5702 | audio_info->audio_latency = drm_connector->audio_latency[0]; | |
5703 | } | |
5704 | ||
5705 | /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ | |
5706 | ||
5707 | } | |
5708 | ||
3ee6b26b AD |
5709 | static void |
5710 | copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, | |
5711 | struct drm_display_mode *dst_mode) | |
e7b07cee HW |
5712 | { |
5713 | dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; | |
5714 | dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; | |
5715 | dst_mode->crtc_clock = src_mode->crtc_clock; | |
5716 | dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; | |
5717 | dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; | |
b830ebc9 | 5718 | dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; |
e7b07cee HW |
5719 | dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; |
5720 | dst_mode->crtc_htotal = src_mode->crtc_htotal; | |
5721 | dst_mode->crtc_hskew = src_mode->crtc_hskew; | |
5722 | dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; | |
5723 | dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; | |
5724 | dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; | |
5725 | dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; | |
5726 | dst_mode->crtc_vtotal = src_mode->crtc_vtotal; | |
5727 | } | |
5728 | ||
3ee6b26b AD |
5729 | static void |
5730 | decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, | |
5731 | const struct drm_display_mode *native_mode, | |
5732 | bool scale_enabled) | |
e7b07cee HW |
5733 | { |
5734 | if (scale_enabled) { | |
5735 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
5736 | } else if (native_mode->clock == drm_mode->clock && | |
5737 | native_mode->htotal == drm_mode->htotal && | |
5738 | native_mode->vtotal == drm_mode->vtotal) { | |
5739 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
5740 | } else { | |
5741 | /* no scaling nor amdgpu inserted, no need to patch */ | |
5742 | } | |
5743 | } | |
5744 | ||
aed15309 | 5745 | static struct dc_sink * |
1fb9d7b9 | 5746 | create_fake_sink(struct dc_link *link) |
2e0ac3d6 | 5747 | { |
2e0ac3d6 | 5748 | struct dc_sink_init_data sink_init_data = { 0 }; |
aed15309 | 5749 | struct dc_sink *sink = NULL; |
c82eddf8 | 5750 | |
1fb9d7b9 HW |
5751 | sink_init_data.link = link; |
5752 | sink_init_data.sink_signal = link->connector_signal; | |
2e0ac3d6 HW |
5753 | |
5754 | sink = dc_sink_create(&sink_init_data); | |
423788c7 | 5755 | if (!sink) { |
2e0ac3d6 | 5756 | DRM_ERROR("Failed to create sink!\n"); |
aed15309 | 5757 | return NULL; |
423788c7 | 5758 | } |
2e0ac3d6 | 5759 | sink->sink_signal = SIGNAL_TYPE_VIRTUAL; |
423788c7 | 5760 | |
aed15309 | 5761 | return sink; |
2e0ac3d6 HW |
5762 | } |
5763 | ||
fa2123db ML |
5764 | static void set_multisync_trigger_params( |
5765 | struct dc_stream_state *stream) | |
5766 | { | |
ec372186 ML |
5767 | struct dc_stream_state *master = NULL; |
5768 | ||
fa2123db | 5769 | if (stream->triggered_crtc_reset.enabled) { |
ec372186 ML |
5770 | master = stream->triggered_crtc_reset.event_source; |
5771 | stream->triggered_crtc_reset.event = | |
5772 | master->timing.flags.VSYNC_POSITIVE_POLARITY ? | |
5773 | CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; | |
5774 | stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; | |
fa2123db ML |
5775 | } |
5776 | } | |
5777 | ||
5778 | static void set_master_stream(struct dc_stream_state *stream_set[], | |
5779 | int stream_count) | |
5780 | { | |
5781 | int j, highest_rfr = 0, master_stream = 0; | |
5782 | ||
5783 | for (j = 0; j < stream_count; j++) { | |
5784 | if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { | |
5785 | int refresh_rate = 0; | |
5786 | ||
380604e2 | 5787 | refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ |
fa2123db ML |
5788 | (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); |
5789 | if (refresh_rate > highest_rfr) { | |
5790 | highest_rfr = refresh_rate; | |
5791 | master_stream = j; | |
5792 | } | |
5793 | } | |
5794 | } | |
5795 | for (j = 0; j < stream_count; j++) { | |
03736f4c | 5796 | if (stream_set[j]) |
fa2123db ML |
5797 | stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; |
5798 | } | |
5799 | } | |
5800 | ||
5801 | static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) | |
5802 | { | |
5803 | int i = 0; | |
ec372186 | 5804 | struct dc_stream_state *stream; |
fa2123db ML |
5805 | |
5806 | if (context->stream_count < 2) | |
5807 | return; | |
5808 | for (i = 0; i < context->stream_count ; i++) { | |
5809 | if (!context->streams[i]) | |
5810 | continue; | |
1f6010a9 DF |
5811 | /* |
5812 | * TODO: add a function to read AMD VSDB bits and set | |
fa2123db | 5813 | * crtc_sync_master.multi_sync_enabled flag |
1f6010a9 | 5814 | * For now it's set to false |
fa2123db | 5815 | */ |
fa2123db | 5816 | } |
ec372186 | 5817 | |
fa2123db | 5818 | set_master_stream(context->streams, context->stream_count); |
ec372186 ML |
5819 | |
5820 | for (i = 0; i < context->stream_count ; i++) { | |
5821 | stream = context->streams[i]; | |
5822 | ||
5823 | if (!stream) | |
5824 | continue; | |
5825 | ||
5826 | set_multisync_trigger_params(stream); | |
5827 | } | |
fa2123db ML |
5828 | } |
5829 | ||
5d945cbc RS |
5830 | /** |
5831 | * DOC: FreeSync Video | |
5832 | * | |
5833 | * When a userspace application wants to play a video, the content follows a | |
5834 | * standard format definition that usually specifies the FPS for that format. | |
5835 | * The below list illustrates some video format and the expected FPS, | |
5836 | * respectively: | |
5837 | * | |
5838 | * - TV/NTSC (23.976 FPS) | |
5839 | * - Cinema (24 FPS) | |
5840 | * - TV/PAL (25 FPS) | |
5841 | * - TV/NTSC (29.97 FPS) | |
5842 | * - TV/NTSC (30 FPS) | |
5843 | * - Cinema HFR (48 FPS) | |
5844 | * - TV/PAL (50 FPS) | |
5845 | * - Commonly used (60 FPS) | |
5846 | * - Multiples of 24 (48,72,96 FPS) | |
5847 | * | |
5848 | * The list of standards video format is not huge and can be added to the | |
5849 | * connector modeset list beforehand. With that, userspace can leverage | |
5850 | * FreeSync to extends the front porch in order to attain the target refresh | |
5851 | * rate. Such a switch will happen seamlessly, without screen blanking or | |
5852 | * reprogramming of the output in any other way. If the userspace requests a | |
5853 | * modesetting change compatible with FreeSync modes that only differ in the | |
5854 | * refresh rate, DC will skip the full update and avoid blink during the | |
5855 | * transition. For example, the video player can change the modesetting from | |
5856 | * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without | |
5857 | * causing any display blink. This same concept can be applied to a mode | |
5858 | * setting change. | |
5859 | */ | |
5860 | static struct drm_display_mode * | |
5861 | get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, | |
5862 | bool use_probed_modes) | |
5863 | { | |
5864 | struct drm_display_mode *m, *m_pref = NULL; | |
5865 | u16 current_refresh, highest_refresh; | |
5866 | struct list_head *list_head = use_probed_modes ? | |
5867 | &aconnector->base.probed_modes : | |
5868 | &aconnector->base.modes; | |
5869 | ||
5870 | if (aconnector->freesync_vid_base.clock != 0) | |
5871 | return &aconnector->freesync_vid_base; | |
5872 | ||
5873 | /* Find the preferred mode */ | |
c82eddf8 | 5874 | list_for_each_entry(m, list_head, head) { |
5d945cbc RS |
5875 | if (m->type & DRM_MODE_TYPE_PREFERRED) { |
5876 | m_pref = m; | |
5877 | break; | |
5878 | } | |
5879 | } | |
5880 | ||
5881 | if (!m_pref) { | |
5882 | /* Probably an EDID with no preferred mode. Fallback to first entry */ | |
5883 | m_pref = list_first_entry_or_null( | |
5884 | &aconnector->base.modes, struct drm_display_mode, head); | |
5885 | if (!m_pref) { | |
5886 | DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); | |
5887 | return NULL; | |
5888 | } | |
5889 | } | |
5890 | ||
5891 | highest_refresh = drm_mode_vrefresh(m_pref); | |
5892 | ||
5893 | /* | |
5894 | * Find the mode with highest refresh rate with same resolution. | |
5895 | * For some monitors, preferred mode is not the mode with highest | |
5896 | * supported refresh rate. | |
5897 | */ | |
c82eddf8 | 5898 | list_for_each_entry(m, list_head, head) { |
5d945cbc RS |
5899 | current_refresh = drm_mode_vrefresh(m); |
5900 | ||
5901 | if (m->hdisplay == m_pref->hdisplay && | |
5902 | m->vdisplay == m_pref->vdisplay && | |
5903 | highest_refresh < current_refresh) { | |
5904 | highest_refresh = current_refresh; | |
5905 | m_pref = m; | |
5906 | } | |
5907 | } | |
5908 | ||
5909 | drm_mode_copy(&aconnector->freesync_vid_base, m_pref); | |
5910 | return m_pref; | |
5911 | } | |
5912 | ||
5913 | static bool is_freesync_video_mode(const struct drm_display_mode *mode, | |
5914 | struct amdgpu_dm_connector *aconnector) | |
5915 | { | |
5916 | struct drm_display_mode *high_mode; | |
5917 | int timing_diff; | |
5918 | ||
5919 | high_mode = get_highest_refresh_rate_mode(aconnector, false); | |
5920 | if (!high_mode || !mode) | |
5921 | return false; | |
5922 | ||
5923 | timing_diff = high_mode->vtotal - mode->vtotal; | |
5924 | ||
5925 | if (high_mode->clock == 0 || high_mode->clock != mode->clock || | |
5926 | high_mode->hdisplay != mode->hdisplay || | |
5927 | high_mode->vdisplay != mode->vdisplay || | |
5928 | high_mode->hsync_start != mode->hsync_start || | |
5929 | high_mode->hsync_end != mode->hsync_end || | |
5930 | high_mode->htotal != mode->htotal || | |
5931 | high_mode->hskew != mode->hskew || | |
5932 | high_mode->vscan != mode->vscan || | |
5933 | high_mode->vsync_start - mode->vsync_start != timing_diff || | |
5934 | high_mode->vsync_end - mode->vsync_end != timing_diff) | |
5935 | return false; | |
5936 | else | |
5937 | return true; | |
5938 | } | |
5939 | ||
998b7ad2 | 5940 | static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, |
5d945cbc RS |
5941 | struct dc_sink *sink, struct dc_stream_state *stream, |
5942 | struct dsc_dec_dpcd_caps *dsc_caps) | |
998b7ad2 FZ |
5943 | { |
5944 | stream->timing.flags.DSC = 0; | |
63ad5371 | 5945 | dsc_caps->is_dsc_supported = false; |
998b7ad2 | 5946 | |
2665f63a | 5947 | if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || |
5d945cbc | 5948 | sink->sink_signal == SIGNAL_TYPE_EDP)) { |
50b1f44e FZ |
5949 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || |
5950 | sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) | |
5951 | dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, | |
5952 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, | |
5953 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, | |
5954 | dsc_caps); | |
998b7ad2 FZ |
5955 | } |
5956 | } | |
5957 | ||
5d945cbc | 5958 | |
2665f63a ML |
5959 | static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, |
5960 | struct dc_sink *sink, struct dc_stream_state *stream, | |
5961 | struct dsc_dec_dpcd_caps *dsc_caps, | |
5962 | uint32_t max_dsc_target_bpp_limit_override) | |
5963 | { | |
5964 | const struct dc_link_settings *verified_link_cap = NULL; | |
ae67558b SS |
5965 | u32 link_bw_in_kbps; |
5966 | u32 edp_min_bpp_x16, edp_max_bpp_x16; | |
2665f63a ML |
5967 | struct dc *dc = sink->ctx->dc; |
5968 | struct dc_dsc_bw_range bw_range = {0}; | |
5969 | struct dc_dsc_config dsc_cfg = {0}; | |
de534c1c MH |
5970 | struct dc_dsc_config_options dsc_options = {0}; |
5971 | ||
5972 | dc_dsc_get_default_config_option(dc, &dsc_options); | |
5973 | dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; | |
2665f63a ML |
5974 | |
5975 | verified_link_cap = dc_link_get_link_cap(stream->link); | |
5976 | link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); | |
5977 | edp_min_bpp_x16 = 8 * 16; | |
5978 | edp_max_bpp_x16 = 8 * 16; | |
5979 | ||
5980 | if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) | |
5981 | edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; | |
5982 | ||
5983 | if (edp_max_bpp_x16 < edp_min_bpp_x16) | |
5984 | edp_min_bpp_x16 = edp_max_bpp_x16; | |
5985 | ||
5986 | if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], | |
5987 | dc->debug.dsc_min_slice_height_override, | |
5988 | edp_min_bpp_x16, edp_max_bpp_x16, | |
5989 | dsc_caps, | |
5990 | &stream->timing, | |
63c0bf99 | 5991 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
2665f63a ML |
5992 | &bw_range)) { |
5993 | ||
5994 | if (bw_range.max_kbps < link_bw_in_kbps) { | |
5995 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], | |
5996 | dsc_caps, | |
de534c1c | 5997 | &dsc_options, |
2665f63a ML |
5998 | 0, |
5999 | &stream->timing, | |
63c0bf99 | 6000 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
2665f63a ML |
6001 | &dsc_cfg)) { |
6002 | stream->timing.dsc_cfg = dsc_cfg; | |
6003 | stream->timing.flags.DSC = 1; | |
6004 | stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; | |
6005 | } | |
6006 | return; | |
6007 | } | |
6008 | } | |
6009 | ||
6010 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], | |
6011 | dsc_caps, | |
de534c1c | 6012 | &dsc_options, |
2665f63a ML |
6013 | link_bw_in_kbps, |
6014 | &stream->timing, | |
63c0bf99 | 6015 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
2665f63a ML |
6016 | &dsc_cfg)) { |
6017 | stream->timing.dsc_cfg = dsc_cfg; | |
6018 | stream->timing.flags.DSC = 1; | |
6019 | } | |
6020 | } | |
6021 | ||
5d945cbc | 6022 | |
998b7ad2 | 6023 | static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, |
5d945cbc RS |
6024 | struct dc_sink *sink, struct dc_stream_state *stream, |
6025 | struct dsc_dec_dpcd_caps *dsc_caps) | |
998b7ad2 FZ |
6026 | { |
6027 | struct drm_connector *drm_connector = &aconnector->base; | |
ae67558b | 6028 | u32 link_bandwidth_kbps; |
2665f63a | 6029 | struct dc *dc = sink->ctx->dc; |
ae67558b SS |
6030 | u32 max_supported_bw_in_kbps, timing_bw_in_kbps; |
6031 | u32 dsc_max_supported_bw_in_kbps; | |
6032 | u32 max_dsc_target_bpp_limit_override = | |
6e5abe94 | 6033 | drm_connector->display_info.max_dsc_bpp; |
de534c1c MH |
6034 | struct dc_dsc_config_options dsc_options = {0}; |
6035 | ||
6036 | dc_dsc_get_default_config_option(dc, &dsc_options); | |
6037 | dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; | |
998b7ad2 FZ |
6038 | |
6039 | link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, | |
6040 | dc_link_get_link_cap(aconnector->dc_link)); | |
de7cc1b4 | 6041 | |
998b7ad2 FZ |
6042 | /* Set DSC policy according to dsc_clock_en */ |
6043 | dc_dsc_policy_set_enable_dsc_when_not_needed( | |
6044 | aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); | |
6045 | ||
c17a34e0 IC |
6046 | if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && |
6047 | !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && | |
2665f63a ML |
6048 | dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { |
6049 | ||
6050 | apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); | |
6051 | ||
6052 | } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { | |
50b1f44e FZ |
6053 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { |
6054 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], | |
998b7ad2 | 6055 | dsc_caps, |
de534c1c | 6056 | &dsc_options, |
998b7ad2 FZ |
6057 | link_bandwidth_kbps, |
6058 | &stream->timing, | |
63c0bf99 | 6059 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
998b7ad2 | 6060 | &stream->timing.dsc_cfg)) { |
50b1f44e | 6061 | stream->timing.flags.DSC = 1; |
5d945cbc | 6062 | DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); |
50b1f44e FZ |
6063 | } |
6064 | } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { | |
63c0bf99 GS |
6065 | timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, |
6066 | dc_link_get_highest_encoding_format(aconnector->dc_link)); | |
50b1f44e FZ |
6067 | max_supported_bw_in_kbps = link_bandwidth_kbps; |
6068 | dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; | |
6069 | ||
6070 | if (timing_bw_in_kbps > max_supported_bw_in_kbps && | |
6071 | max_supported_bw_in_kbps > 0 && | |
6072 | dsc_max_supported_bw_in_kbps > 0) | |
6073 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], | |
6074 | dsc_caps, | |
de534c1c | 6075 | &dsc_options, |
50b1f44e FZ |
6076 | dsc_max_supported_bw_in_kbps, |
6077 | &stream->timing, | |
63c0bf99 | 6078 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
50b1f44e FZ |
6079 | &stream->timing.dsc_cfg)) { |
6080 | stream->timing.flags.DSC = 1; | |
6081 | DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", | |
6082 | __func__, drm_connector->name); | |
6083 | } | |
998b7ad2 FZ |
6084 | } |
6085 | } | |
6086 | ||
6087 | /* Overwrite the stream flag if DSC is enabled through debugfs */ | |
6088 | if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) | |
6089 | stream->timing.flags.DSC = 1; | |
6090 | ||
5d945cbc RS |
6091 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) |
6092 | stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; | |
a85ba005 | 6093 | |
5d945cbc RS |
6094 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) |
6095 | stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; | |
a85ba005 | 6096 | |
5d945cbc RS |
6097 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) |
6098 | stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; | |
a85ba005 NC |
6099 | } |
6100 | ||
f11d9373 | 6101 | static struct dc_stream_state * |
3e094a28 | 6102 | create_stream_for_sink(struct drm_connector *connector, |
3ee6b26b | 6103 | const struct drm_display_mode *drm_mode, |
b333730d | 6104 | const struct dm_connector_state *dm_state, |
cbd14ae7 SW |
6105 | const struct dc_stream_state *old_stream, |
6106 | int requested_bpc) | |
e7b07cee | 6107 | { |
3e094a28 | 6108 | struct amdgpu_dm_connector *aconnector = NULL; |
e7b07cee | 6109 | struct drm_display_mode *preferred_mode = NULL; |
cb841d27 | 6110 | const struct drm_connector_state *con_state = &dm_state->base; |
0971c40e | 6111 | struct dc_stream_state *stream = NULL; |
0a204ce0 | 6112 | struct drm_display_mode mode; |
a85ba005 NC |
6113 | struct drm_display_mode saved_mode; |
6114 | struct drm_display_mode *freesync_mode = NULL; | |
e7b07cee | 6115 | bool native_mode_found = false; |
b0781603 | 6116 | bool recalculate_timing = false; |
cb841d27 | 6117 | bool scale = dm_state->scaling != RMX_OFF; |
b333730d | 6118 | int mode_refresh; |
58124bf8 | 6119 | int preferred_refresh = 0; |
b1a98cf8 | 6120 | enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; |
df2f1015 | 6121 | struct dsc_dec_dpcd_caps dsc_caps; |
5d945cbc | 6122 | |
1fb9d7b9 | 6123 | struct dc_link *link = NULL; |
aed15309 | 6124 | struct dc_sink *sink = NULL; |
a85ba005 | 6125 | |
0a204ce0 | 6126 | drm_mode_init(&mode, drm_mode); |
a85ba005 NC |
6127 | memset(&saved_mode, 0, sizeof(saved_mode)); |
6128 | ||
3e094a28 HW |
6129 | if (connector == NULL) { |
6130 | DRM_ERROR("connector is NULL!\n"); | |
64245fa7 | 6131 | return stream; |
e7b07cee HW |
6132 | } |
6133 | ||
3e094a28 HW |
6134 | if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) { |
6135 | aconnector = NULL; | |
6136 | aconnector = to_amdgpu_dm_connector(connector); | |
1fb9d7b9 HW |
6137 | link = aconnector->dc_link; |
6138 | } else { | |
6139 | struct drm_writeback_connector *wbcon = NULL; | |
6140 | struct amdgpu_dm_wb_connector *dm_wbcon = NULL; | |
6141 | ||
6142 | wbcon = drm_connector_to_writeback(connector); | |
6143 | dm_wbcon = to_amdgpu_dm_wb_connector(wbcon); | |
6144 | link = dm_wbcon->link; | |
6145 | } | |
6146 | ||
6147 | if (!aconnector || !aconnector->dc_sink) { | |
6148 | sink = create_fake_sink(link); | |
6149 | if (!sink) | |
6150 | return stream; | |
6151 | ||
6152 | } else { | |
6153 | sink = aconnector->dc_sink; | |
6154 | dc_sink_retain(sink); | |
f4ac176e | 6155 | } |
2e0ac3d6 | 6156 | |
aed15309 | 6157 | stream = dc_create_stream_for_sink(sink); |
4562236b | 6158 | |
b830ebc9 | 6159 | if (stream == NULL) { |
e7b07cee | 6160 | DRM_ERROR("Failed to create stream for sink!\n"); |
aed15309 | 6161 | goto finish; |
e7b07cee HW |
6162 | } |
6163 | ||
3e094a28 | 6164 | /* We leave this NULL for writeback connectors */ |
ceb3dbb4 JL |
6165 | stream->dm_stream_context = aconnector; |
6166 | ||
4a36fcba | 6167 | stream->timing.flags.LTE_340MCSC_SCRAMBLE = |
3e094a28 | 6168 | connector->display_info.hdmi.scdc.scrambling.low_rates; |
4a36fcba | 6169 | |
3e094a28 | 6170 | list_for_each_entry(preferred_mode, &connector->modes, head) { |
e7b07cee HW |
6171 | /* Search for preferred mode */ |
6172 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { | |
6173 | native_mode_found = true; | |
6174 | break; | |
6175 | } | |
6176 | } | |
6177 | if (!native_mode_found) | |
6178 | preferred_mode = list_first_entry_or_null( | |
3e094a28 | 6179 | &connector->modes, |
e7b07cee HW |
6180 | struct drm_display_mode, |
6181 | head); | |
6182 | ||
b333730d BL |
6183 | mode_refresh = drm_mode_vrefresh(&mode); |
6184 | ||
b830ebc9 | 6185 | if (preferred_mode == NULL) { |
1f6010a9 DF |
6186 | /* |
6187 | * This may not be an error, the use case is when we have no | |
e7b07cee HW |
6188 | * usermode calls to reset and set mode upon hotplug. In this |
6189 | * case, we call set mode ourselves to restore the previous mode | |
c82eddf8 | 6190 | * and the modelist may not be filled in time. |
e7b07cee | 6191 | */ |
f1ad2f5e | 6192 | DRM_DEBUG_DRIVER("No preferred mode found\n"); |
3e094a28 | 6193 | } else if (aconnector) { |
11b92df8 | 6194 | recalculate_timing = is_freesync_video_mode(&mode, aconnector); |
a85ba005 NC |
6195 | if (recalculate_timing) { |
6196 | freesync_mode = get_highest_refresh_rate_mode(aconnector, false); | |
426c89aa VS |
6197 | drm_mode_copy(&saved_mode, &mode); |
6198 | drm_mode_copy(&mode, freesync_mode); | |
a85ba005 NC |
6199 | } else { |
6200 | decide_crtc_timing_for_drm_display_mode( | |
5d945cbc | 6201 | &mode, preferred_mode, scale); |
a85ba005 | 6202 | |
b0781603 NK |
6203 | preferred_refresh = drm_mode_vrefresh(preferred_mode); |
6204 | } | |
e7b07cee HW |
6205 | } |
6206 | ||
a85ba005 NC |
6207 | if (recalculate_timing) |
6208 | drm_mode_set_crtcinfo(&saved_mode, 0); | |
f783577c | 6209 | |
5d945cbc | 6210 | /* |
c82eddf8 SS |
6211 | * If scaling is enabled and refresh rate didn't change |
6212 | * we copy the vic and polarities of the old timings | |
6213 | */ | |
b0781603 | 6214 | if (!scale || mode_refresh != preferred_refresh) |
a85ba005 | 6215 | fill_stream_properties_from_drm_display_mode( |
3e094a28 | 6216 | stream, &mode, connector, con_state, NULL, |
a85ba005 | 6217 | requested_bpc); |
b333730d | 6218 | else |
a85ba005 | 6219 | fill_stream_properties_from_drm_display_mode( |
3e094a28 | 6220 | stream, &mode, connector, con_state, old_stream, |
a85ba005 | 6221 | requested_bpc); |
b333730d | 6222 | |
3e094a28 HW |
6223 | /* The rest isn't needed for writeback connectors */ |
6224 | if (!aconnector) | |
6225 | goto finish; | |
6226 | ||
028c4ccf | 6227 | if (aconnector->timing_changed) { |
5d72e247 HM |
6228 | drm_dbg(aconnector->base.dev, |
6229 | "overriding timing for automated test, bpc %d, changing to %d\n", | |
6230 | stream->timing.display_color_depth, | |
6231 | aconnector->timing_requested->display_color_depth); | |
028c4ccf QZ |
6232 | stream->timing = *aconnector->timing_requested; |
6233 | } | |
6234 | ||
998b7ad2 FZ |
6235 | /* SST DSC determination policy */ |
6236 | update_dsc_caps(aconnector, sink, stream, &dsc_caps); | |
6237 | if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) | |
6238 | apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); | |
39a4eb85 | 6239 | |
e7b07cee HW |
6240 | update_stream_scaling_settings(&mode, dm_state, stream); |
6241 | ||
6242 | fill_audio_info( | |
6243 | &stream->audio_info, | |
3e094a28 | 6244 | connector, |
aed15309 | 6245 | sink); |
e7b07cee | 6246 | |
ceb3dbb4 | 6247 | update_stream_signal(stream, sink); |
9182b4cb | 6248 | |
d832fc3b | 6249 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
75f77aaf WL |
6250 | mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); |
6251 | ||
81a7be79 | 6252 | if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) { |
8a488f5d RL |
6253 | // |
6254 | // should decide stream support vsc sdp colorimetry capability | |
6255 | // before building vsc info packet | |
6256 | // | |
6257 | stream->use_vsc_sdp_for_colorimetry = false; | |
6258 | if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { | |
6259 | stream->use_vsc_sdp_for_colorimetry = | |
6260 | aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; | |
6261 | } else { | |
6262 | if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) | |
6263 | stream->use_vsc_sdp_for_colorimetry = true; | |
8c322309 | 6264 | } |
b1a98cf8 MH |
6265 | if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) |
6266 | tf = TRANSFER_FUNC_GAMMA_22; | |
6267 | mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); | |
1a365683 RL |
6268 | aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; |
6269 | ||
8c322309 | 6270 | } |
aed15309 | 6271 | finish: |
dcd5fb82 | 6272 | dc_sink_release(sink); |
9e3efe3e | 6273 | |
e7b07cee HW |
6274 | return stream; |
6275 | } | |
6276 | ||
e7b07cee HW |
6277 | static enum drm_connector_status |
6278 | amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) | |
6279 | { | |
6280 | bool connected; | |
c84dec2f | 6281 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee | 6282 | |
1f6010a9 DF |
6283 | /* |
6284 | * Notes: | |
e7b07cee HW |
6285 | * 1. This interface is NOT called in context of HPD irq. |
6286 | * 2. This interface *is called* in context of user-mode ioctl. Which | |
1f6010a9 DF |
6287 | * makes it a bad place for *any* MST-related activity. |
6288 | */ | |
e7b07cee | 6289 | |
8580d60b HW |
6290 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && |
6291 | !aconnector->fake_enable) | |
e7b07cee HW |
6292 | connected = (aconnector->dc_sink != NULL); |
6293 | else | |
5d945cbc RS |
6294 | connected = (aconnector->base.force == DRM_FORCE_ON || |
6295 | aconnector->base.force == DRM_FORCE_ON_DIGITAL); | |
e7b07cee | 6296 | |
0f877894 OV |
6297 | update_subconnector_property(aconnector); |
6298 | ||
e7b07cee HW |
6299 | return (connected ? connector_status_connected : |
6300 | connector_status_disconnected); | |
6301 | } | |
6302 | ||
3ee6b26b AD |
6303 | int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, |
6304 | struct drm_connector_state *connector_state, | |
6305 | struct drm_property *property, | |
6306 | uint64_t val) | |
e7b07cee HW |
6307 | { |
6308 | struct drm_device *dev = connector->dev; | |
1348969a | 6309 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
6310 | struct dm_connector_state *dm_old_state = |
6311 | to_dm_connector_state(connector->state); | |
6312 | struct dm_connector_state *dm_new_state = | |
6313 | to_dm_connector_state(connector_state); | |
6314 | ||
6315 | int ret = -EINVAL; | |
6316 | ||
6317 | if (property == dev->mode_config.scaling_mode_property) { | |
6318 | enum amdgpu_rmx_type rmx_type; | |
6319 | ||
6320 | switch (val) { | |
6321 | case DRM_MODE_SCALE_CENTER: | |
6322 | rmx_type = RMX_CENTER; | |
6323 | break; | |
6324 | case DRM_MODE_SCALE_ASPECT: | |
6325 | rmx_type = RMX_ASPECT; | |
6326 | break; | |
6327 | case DRM_MODE_SCALE_FULLSCREEN: | |
6328 | rmx_type = RMX_FULL; | |
6329 | break; | |
6330 | case DRM_MODE_SCALE_NONE: | |
6331 | default: | |
6332 | rmx_type = RMX_OFF; | |
6333 | break; | |
6334 | } | |
6335 | ||
6336 | if (dm_old_state->scaling == rmx_type) | |
6337 | return 0; | |
6338 | ||
6339 | dm_new_state->scaling = rmx_type; | |
6340 | ret = 0; | |
6341 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
6342 | dm_new_state->underscan_hborder = val; | |
6343 | ret = 0; | |
6344 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
6345 | dm_new_state->underscan_vborder = val; | |
6346 | ret = 0; | |
6347 | } else if (property == adev->mode_info.underscan_property) { | |
6348 | dm_new_state->underscan_enable = val; | |
6349 | ret = 0; | |
c1ee92f9 | 6350 | } else if (property == adev->mode_info.abm_level_property) { |
7a6931a4 | 6351 | dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE; |
c1ee92f9 | 6352 | ret = 0; |
e7b07cee HW |
6353 | } |
6354 | ||
6355 | return ret; | |
6356 | } | |
6357 | ||
3ee6b26b AD |
6358 | int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, |
6359 | const struct drm_connector_state *state, | |
6360 | struct drm_property *property, | |
6361 | uint64_t *val) | |
e7b07cee HW |
6362 | { |
6363 | struct drm_device *dev = connector->dev; | |
1348969a | 6364 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
6365 | struct dm_connector_state *dm_state = |
6366 | to_dm_connector_state(state); | |
6367 | int ret = -EINVAL; | |
6368 | ||
6369 | if (property == dev->mode_config.scaling_mode_property) { | |
6370 | switch (dm_state->scaling) { | |
6371 | case RMX_CENTER: | |
6372 | *val = DRM_MODE_SCALE_CENTER; | |
6373 | break; | |
6374 | case RMX_ASPECT: | |
6375 | *val = DRM_MODE_SCALE_ASPECT; | |
6376 | break; | |
6377 | case RMX_FULL: | |
6378 | *val = DRM_MODE_SCALE_FULLSCREEN; | |
6379 | break; | |
6380 | case RMX_OFF: | |
6381 | default: | |
6382 | *val = DRM_MODE_SCALE_NONE; | |
6383 | break; | |
6384 | } | |
6385 | ret = 0; | |
6386 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
6387 | *val = dm_state->underscan_hborder; | |
6388 | ret = 0; | |
6389 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
6390 | *val = dm_state->underscan_vborder; | |
6391 | ret = 0; | |
6392 | } else if (property == adev->mode_info.underscan_property) { | |
6393 | *val = dm_state->underscan_enable; | |
6394 | ret = 0; | |
c1ee92f9 | 6395 | } else if (property == adev->mode_info.abm_level_property) { |
7a6931a4 HM |
6396 | *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ? |
6397 | dm_state->abm_level : 0; | |
c1ee92f9 | 6398 | ret = 0; |
e7b07cee | 6399 | } |
c1ee92f9 | 6400 | |
e7b07cee HW |
6401 | return ret; |
6402 | } | |
6403 | ||
526c654a ED |
6404 | static void amdgpu_dm_connector_unregister(struct drm_connector *connector) |
6405 | { | |
6406 | struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); | |
6407 | ||
6408 | drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); | |
6409 | } | |
6410 | ||
7578ecda | 6411 | static void amdgpu_dm_connector_destroy(struct drm_connector *connector) |
e7b07cee | 6412 | { |
c84dec2f | 6413 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
1348969a | 6414 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
e7b07cee | 6415 | struct amdgpu_display_manager *dm = &adev->dm; |
ada8ce15 | 6416 | |
5dff80bd | 6417 | /* |
5d945cbc | 6418 | * Call only if mst_mgr was initialized before since it's not done |
5dff80bd AG |
6419 | * for all connector types. |
6420 | */ | |
6421 | if (aconnector->mst_mgr.dev) | |
6422 | drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); | |
6423 | ||
f196198c HG |
6424 | if (aconnector->bl_idx != -1) { |
6425 | backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); | |
6426 | dm->backlight_dev[aconnector->bl_idx] = NULL; | |
e7b07cee | 6427 | } |
dcd5fb82 MF |
6428 | |
6429 | if (aconnector->dc_em_sink) | |
6430 | dc_sink_release(aconnector->dc_em_sink); | |
6431 | aconnector->dc_em_sink = NULL; | |
6432 | if (aconnector->dc_sink) | |
6433 | dc_sink_release(aconnector->dc_sink); | |
6434 | aconnector->dc_sink = NULL; | |
6435 | ||
e86e8947 | 6436 | drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); |
e7b07cee HW |
6437 | drm_connector_unregister(connector); |
6438 | drm_connector_cleanup(connector); | |
526c654a ED |
6439 | if (aconnector->i2c) { |
6440 | i2c_del_adapter(&aconnector->i2c->base); | |
6441 | kfree(aconnector->i2c); | |
6442 | } | |
7daec99f | 6443 | kfree(aconnector->dm_dp_aux.aux.name); |
526c654a | 6444 | |
e7b07cee HW |
6445 | kfree(connector); |
6446 | } | |
6447 | ||
6448 | void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) | |
6449 | { | |
6450 | struct dm_connector_state *state = | |
6451 | to_dm_connector_state(connector->state); | |
6452 | ||
df099b9b LSL |
6453 | if (connector->state) |
6454 | __drm_atomic_helper_connector_destroy_state(connector->state); | |
6455 | ||
e7b07cee HW |
6456 | kfree(state); |
6457 | ||
6458 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
6459 | ||
6460 | if (state) { | |
6461 | state->scaling = RMX_OFF; | |
6462 | state->underscan_enable = false; | |
6463 | state->underscan_hborder = 0; | |
6464 | state->underscan_vborder = 0; | |
01933ba4 | 6465 | state->base.max_requested_bpc = 8; |
3261e013 ML |
6466 | state->vcpi_slots = 0; |
6467 | state->pbn = 0; | |
5d945cbc | 6468 | |
c3e50f89 | 6469 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
7a6931a4 HM |
6470 | state->abm_level = amdgpu_dm_abm_level ?: |
6471 | ABM_LEVEL_IMMEDIATE_DISABLE; | |
c3e50f89 | 6472 | |
df099b9b | 6473 | __drm_atomic_helper_connector_reset(connector, &state->base); |
e7b07cee HW |
6474 | } |
6475 | } | |
6476 | ||
3ee6b26b AD |
6477 | struct drm_connector_state * |
6478 | amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) | |
e7b07cee HW |
6479 | { |
6480 | struct dm_connector_state *state = | |
6481 | to_dm_connector_state(connector->state); | |
6482 | ||
6483 | struct dm_connector_state *new_state = | |
6484 | kmemdup(state, sizeof(*state), GFP_KERNEL); | |
6485 | ||
98e6436d AK |
6486 | if (!new_state) |
6487 | return NULL; | |
e7b07cee | 6488 | |
98e6436d AK |
6489 | __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); |
6490 | ||
6491 | new_state->freesync_capable = state->freesync_capable; | |
c1ee92f9 | 6492 | new_state->abm_level = state->abm_level; |
922454c2 NK |
6493 | new_state->scaling = state->scaling; |
6494 | new_state->underscan_enable = state->underscan_enable; | |
6495 | new_state->underscan_hborder = state->underscan_hborder; | |
6496 | new_state->underscan_vborder = state->underscan_vborder; | |
3261e013 ML |
6497 | new_state->vcpi_slots = state->vcpi_slots; |
6498 | new_state->pbn = state->pbn; | |
98e6436d | 6499 | return &new_state->base; |
e7b07cee HW |
6500 | } |
6501 | ||
14f04fa4 AD |
6502 | static int |
6503 | amdgpu_dm_connector_late_register(struct drm_connector *connector) | |
6504 | { | |
6505 | struct amdgpu_dm_connector *amdgpu_dm_connector = | |
6506 | to_amdgpu_dm_connector(connector); | |
00a8037e | 6507 | int r; |
14f04fa4 | 6508 | |
62f03dad HG |
6509 | amdgpu_dm_register_backlight_device(amdgpu_dm_connector); |
6510 | ||
00a8037e AD |
6511 | if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
6512 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
6513 | amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; | |
6514 | r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); | |
6515 | if (r) | |
6516 | return r; | |
6517 | } | |
6518 | ||
6519 | #if defined(CONFIG_DEBUG_FS) | |
14f04fa4 AD |
6520 | connector_debugfs_init(amdgpu_dm_connector); |
6521 | #endif | |
6522 | ||
6523 | return 0; | |
6524 | } | |
6525 | ||
dae343b3 | 6526 | static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) |
0ba4a784 AH |
6527 | { |
6528 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
0e859faf | 6529 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); |
0ba4a784 AH |
6530 | struct dc_link *dc_link = aconnector->dc_link; |
6531 | struct dc_sink *dc_em_sink = aconnector->dc_em_sink; | |
6532 | struct edid *edid; | |
6533 | ||
0e859faf AH |
6534 | /* |
6535 | * Note: drm_get_edid gets edid in the following order: | |
6536 | * 1) override EDID if set via edid_override debugfs, | |
6537 | * 2) firmware EDID if set via edid_firmware module parameter | |
6538 | * 3) regular DDC read. | |
6539 | */ | |
6540 | edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc); | |
6541 | if (!edid) { | |
6542 | DRM_ERROR("No EDID found on connector: %s.\n", connector->name); | |
0ba4a784 | 6543 | return; |
0e859faf | 6544 | } |
0ba4a784 | 6545 | |
0ba4a784 AH |
6546 | aconnector->edid = edid; |
6547 | ||
6548 | /* Update emulated (virtual) sink's EDID */ | |
6549 | if (dc_em_sink && dc_link) { | |
6550 | memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); | |
6551 | memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); | |
6552 | dm_helpers_parse_edid_caps( | |
6553 | dc_link, | |
6554 | &dc_em_sink->dc_edid, | |
6555 | &dc_em_sink->edid_caps); | |
6556 | } | |
6557 | } | |
6558 | ||
e7b07cee HW |
6559 | static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { |
6560 | .reset = amdgpu_dm_connector_funcs_reset, | |
6561 | .detect = amdgpu_dm_connector_detect, | |
6562 | .fill_modes = drm_helper_probe_single_connector_modes, | |
6563 | .destroy = amdgpu_dm_connector_destroy, | |
6564 | .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, | |
6565 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
6566 | .atomic_set_property = amdgpu_dm_connector_atomic_set_property, | |
526c654a | 6567 | .atomic_get_property = amdgpu_dm_connector_atomic_get_property, |
14f04fa4 | 6568 | .late_register = amdgpu_dm_connector_late_register, |
0ba4a784 AH |
6569 | .early_unregister = amdgpu_dm_connector_unregister, |
6570 | .force = amdgpu_dm_connector_funcs_force | |
e7b07cee HW |
6571 | }; |
6572 | ||
e7b07cee HW |
6573 | static int get_modes(struct drm_connector *connector) |
6574 | { | |
6575 | return amdgpu_dm_connector_get_modes(connector); | |
6576 | } | |
6577 | ||
c84dec2f | 6578 | static void create_eml_sink(struct amdgpu_dm_connector *aconnector) |
e7b07cee | 6579 | { |
0e859faf AH |
6580 | struct drm_connector *connector = &aconnector->base; |
6581 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(&aconnector->base); | |
e7b07cee HW |
6582 | struct dc_sink_init_data init_params = { |
6583 | .link = aconnector->dc_link, | |
6584 | .sink_signal = SIGNAL_TYPE_VIRTUAL | |
6585 | }; | |
70e8ffc5 | 6586 | struct edid *edid; |
e7b07cee | 6587 | |
0e859faf AH |
6588 | /* |
6589 | * Note: drm_get_edid gets edid in the following order: | |
6590 | * 1) override EDID if set via edid_override debugfs, | |
6591 | * 2) firmware EDID if set via edid_firmware module parameter | |
6592 | * 3) regular DDC read. | |
6593 | */ | |
6594 | edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc); | |
6595 | if (!edid) { | |
6596 | DRM_ERROR("No EDID found on connector: %s.\n", connector->name); | |
6597 | return; | |
e7b07cee HW |
6598 | } |
6599 | ||
fc0479ac AH |
6600 | if (drm_detect_hdmi_monitor(edid)) |
6601 | init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; | |
6602 | ||
e7b07cee HW |
6603 | aconnector->edid = edid; |
6604 | ||
6605 | aconnector->dc_em_sink = dc_link_add_remote_sink( | |
6606 | aconnector->dc_link, | |
6607 | (uint8_t *)edid, | |
6608 | (edid->extensions + 1) * EDID_LENGTH, | |
6609 | &init_params); | |
6610 | ||
dcd5fb82 | 6611 | if (aconnector->base.force == DRM_FORCE_ON) { |
e7b07cee HW |
6612 | aconnector->dc_sink = aconnector->dc_link->local_sink ? |
6613 | aconnector->dc_link->local_sink : | |
6614 | aconnector->dc_em_sink; | |
dcd5fb82 MF |
6615 | dc_sink_retain(aconnector->dc_sink); |
6616 | } | |
e7b07cee HW |
6617 | } |
6618 | ||
c84dec2f | 6619 | static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
6620 | { |
6621 | struct dc_link *link = (struct dc_link *)aconnector->dc_link; | |
6622 | ||
1f6010a9 DF |
6623 | /* |
6624 | * In case of headless boot with force on for DP managed connector | |
e7b07cee HW |
6625 | * Those settings have to be != 0 to get initial modeset |
6626 | */ | |
6627 | if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { | |
6628 | link->verified_link_cap.lane_count = LANE_COUNT_FOUR; | |
6629 | link->verified_link_cap.link_rate = LINK_RATE_HIGH2; | |
6630 | } | |
6631 | ||
e7b07cee HW |
6632 | create_eml_sink(aconnector); |
6633 | } | |
6634 | ||
5468c36d FZ |
6635 | static enum dc_status dm_validate_stream_and_context(struct dc *dc, |
6636 | struct dc_stream_state *stream) | |
6637 | { | |
6638 | enum dc_status dc_result = DC_ERROR_UNEXPECTED; | |
6639 | struct dc_plane_state *dc_plane_state = NULL; | |
6640 | struct dc_state *dc_state = NULL; | |
6641 | ||
6642 | if (!stream) | |
6643 | goto cleanup; | |
6644 | ||
6645 | dc_plane_state = dc_create_plane_state(dc); | |
6646 | if (!dc_plane_state) | |
6647 | goto cleanup; | |
6648 | ||
6649 | dc_state = dc_create_state(dc); | |
6650 | if (!dc_state) | |
6651 | goto cleanup; | |
6652 | ||
6653 | /* populate stream to plane */ | |
6654 | dc_plane_state->src_rect.height = stream->src.height; | |
6655 | dc_plane_state->src_rect.width = stream->src.width; | |
6656 | dc_plane_state->dst_rect.height = stream->src.height; | |
6657 | dc_plane_state->dst_rect.width = stream->src.width; | |
6658 | dc_plane_state->clip_rect.height = stream->src.height; | |
6659 | dc_plane_state->clip_rect.width = stream->src.width; | |
6660 | dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; | |
6661 | dc_plane_state->plane_size.surface_size.height = stream->src.height; | |
6662 | dc_plane_state->plane_size.surface_size.width = stream->src.width; | |
6663 | dc_plane_state->plane_size.chroma_size.height = stream->src.height; | |
6664 | dc_plane_state->plane_size.chroma_size.width = stream->src.width; | |
5468c36d FZ |
6665 | dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; |
6666 | dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; | |
6667 | dc_plane_state->rotation = ROTATION_ANGLE_0; | |
6668 | dc_plane_state->is_tiling_rotated = false; | |
6669 | dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; | |
6670 | ||
6671 | dc_result = dc_validate_stream(dc, stream); | |
6672 | if (dc_result == DC_OK) | |
6673 | dc_result = dc_validate_plane(dc, dc_plane_state); | |
6674 | ||
6675 | if (dc_result == DC_OK) | |
6676 | dc_result = dc_add_stream_to_ctx(dc, dc_state, stream); | |
6677 | ||
6678 | if (dc_result == DC_OK && !dc_add_plane_to_context( | |
6679 | dc, | |
6680 | stream, | |
6681 | dc_plane_state, | |
6682 | dc_state)) | |
6683 | dc_result = DC_FAIL_ATTACH_SURFACES; | |
6684 | ||
6685 | if (dc_result == DC_OK) | |
6686 | dc_result = dc_validate_global_state(dc, dc_state, true); | |
6687 | ||
6688 | cleanup: | |
6689 | if (dc_state) | |
6690 | dc_release_state(dc_state); | |
6691 | ||
6692 | if (dc_plane_state) | |
6693 | dc_plane_state_release(dc_plane_state); | |
6694 | ||
6695 | return dc_result; | |
6696 | } | |
6697 | ||
17ce8a69 | 6698 | struct dc_stream_state * |
cbd14ae7 SW |
6699 | create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, |
6700 | const struct drm_display_mode *drm_mode, | |
6701 | const struct dm_connector_state *dm_state, | |
6702 | const struct dc_stream_state *old_stream) | |
6703 | { | |
6704 | struct drm_connector *connector = &aconnector->base; | |
1348969a | 6705 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
cbd14ae7 | 6706 | struct dc_stream_state *stream; |
4b7da34b SW |
6707 | const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; |
6708 | int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; | |
cbd14ae7 SW |
6709 | enum dc_status dc_result = DC_OK; |
6710 | ||
6711 | do { | |
3e094a28 | 6712 | stream = create_stream_for_sink(connector, drm_mode, |
cbd14ae7 SW |
6713 | dm_state, old_stream, |
6714 | requested_bpc); | |
6715 | if (stream == NULL) { | |
6716 | DRM_ERROR("Failed to create stream for sink!\n"); | |
6717 | break; | |
6718 | } | |
6719 | ||
dbf5d3d0 AH |
6720 | if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
6721 | return stream; | |
6722 | ||
e9a7d236 RS |
6723 | dc_result = dc_validate_stream(adev->dm.dc, stream); |
6724 | if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) | |
f04d275d | 6725 | dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); |
6726 | ||
5468c36d FZ |
6727 | if (dc_result == DC_OK) |
6728 | dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); | |
6729 | ||
cbd14ae7 | 6730 | if (dc_result != DC_OK) { |
74a16675 | 6731 | DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", |
cbd14ae7 SW |
6732 | drm_mode->hdisplay, |
6733 | drm_mode->vdisplay, | |
6734 | drm_mode->clock, | |
74a16675 RS |
6735 | dc_result, |
6736 | dc_status_to_str(dc_result)); | |
cbd14ae7 SW |
6737 | |
6738 | dc_stream_release(stream); | |
6739 | stream = NULL; | |
6740 | requested_bpc -= 2; /* lower bpc to retry validation */ | |
6741 | } | |
6742 | ||
6743 | } while (stream == NULL && requested_bpc >= 6); | |
6744 | ||
68eb3ae3 WS |
6745 | if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { |
6746 | DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); | |
6747 | ||
6748 | aconnector->force_yuv420_output = true; | |
6749 | stream = create_validate_stream_for_sink(aconnector, drm_mode, | |
6750 | dm_state, old_stream); | |
6751 | aconnector->force_yuv420_output = false; | |
6752 | } | |
6753 | ||
cbd14ae7 SW |
6754 | return stream; |
6755 | } | |
6756 | ||
ba9ca088 | 6757 | enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, |
3ee6b26b | 6758 | struct drm_display_mode *mode) |
e7b07cee HW |
6759 | { |
6760 | int result = MODE_ERROR; | |
6761 | struct dc_sink *dc_sink; | |
e7b07cee | 6762 | /* TODO: Unhardcode stream count */ |
0971c40e | 6763 | struct dc_stream_state *stream; |
c84dec2f | 6764 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
6765 | |
6766 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || | |
6767 | (mode->flags & DRM_MODE_FLAG_DBLSCAN)) | |
6768 | return result; | |
6769 | ||
1f6010a9 DF |
6770 | /* |
6771 | * Only run this the first time mode_valid is called to initilialize | |
e7b07cee HW |
6772 | * EDID mgmt |
6773 | */ | |
6774 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && | |
6775 | !aconnector->dc_em_sink) | |
6776 | handle_edid_mgmt(aconnector); | |
6777 | ||
c84dec2f | 6778 | dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; |
e7b07cee | 6779 | |
ad975f44 VL |
6780 | if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && |
6781 | aconnector->base.force != DRM_FORCE_ON) { | |
e7b07cee HW |
6782 | DRM_ERROR("dc_sink is NULL!\n"); |
6783 | goto fail; | |
6784 | } | |
6785 | ||
1101185b HM |
6786 | drm_mode_set_crtcinfo(mode, 0); |
6787 | ||
cb841d27 HW |
6788 | stream = create_validate_stream_for_sink(aconnector, mode, |
6789 | to_dm_connector_state(connector->state), | |
6790 | NULL); | |
cbd14ae7 SW |
6791 | if (stream) { |
6792 | dc_stream_release(stream); | |
e7b07cee | 6793 | result = MODE_OK; |
cbd14ae7 | 6794 | } |
e7b07cee HW |
6795 | |
6796 | fail: | |
6797 | /* TODO: error handling*/ | |
6798 | return result; | |
6799 | } | |
6800 | ||
88694af9 NK |
6801 | static int fill_hdr_info_packet(const struct drm_connector_state *state, |
6802 | struct dc_info_packet *out) | |
6803 | { | |
6804 | struct hdmi_drm_infoframe frame; | |
6805 | unsigned char buf[30]; /* 26 + 4 */ | |
6806 | ssize_t len; | |
6807 | int ret, i; | |
6808 | ||
6809 | memset(out, 0, sizeof(*out)); | |
6810 | ||
6811 | if (!state->hdr_output_metadata) | |
6812 | return 0; | |
6813 | ||
6814 | ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); | |
6815 | if (ret) | |
6816 | return ret; | |
6817 | ||
6818 | len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); | |
6819 | if (len < 0) | |
6820 | return (int)len; | |
6821 | ||
6822 | /* Static metadata is a fixed 26 bytes + 4 byte header. */ | |
6823 | if (len != 30) | |
6824 | return -EINVAL; | |
6825 | ||
6826 | /* Prepare the infopacket for DC. */ | |
6827 | switch (state->connector->connector_type) { | |
6828 | case DRM_MODE_CONNECTOR_HDMIA: | |
6829 | out->hb0 = 0x87; /* type */ | |
6830 | out->hb1 = 0x01; /* version */ | |
6831 | out->hb2 = 0x1A; /* length */ | |
6832 | out->sb[0] = buf[3]; /* checksum */ | |
6833 | i = 1; | |
6834 | break; | |
6835 | ||
6836 | case DRM_MODE_CONNECTOR_DisplayPort: | |
6837 | case DRM_MODE_CONNECTOR_eDP: | |
6838 | out->hb0 = 0x00; /* sdp id, zero */ | |
6839 | out->hb1 = 0x87; /* type */ | |
6840 | out->hb2 = 0x1D; /* payload len - 1 */ | |
6841 | out->hb3 = (0x13 << 2); /* sdp version */ | |
6842 | out->sb[0] = 0x01; /* version */ | |
6843 | out->sb[1] = 0x1A; /* length */ | |
6844 | i = 2; | |
6845 | break; | |
6846 | ||
6847 | default: | |
6848 | return -EINVAL; | |
6849 | } | |
6850 | ||
6851 | memcpy(&out->sb[i], &buf[4], 26); | |
6852 | out->valid = true; | |
6853 | ||
6854 | print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, | |
6855 | sizeof(out->sb), false); | |
6856 | ||
6857 | return 0; | |
6858 | } | |
6859 | ||
88694af9 NK |
6860 | static int |
6861 | amdgpu_dm_connector_atomic_check(struct drm_connector *conn, | |
51e857af | 6862 | struct drm_atomic_state *state) |
88694af9 | 6863 | { |
51e857af SP |
6864 | struct drm_connector_state *new_con_state = |
6865 | drm_atomic_get_new_connector_state(state, conn); | |
88694af9 NK |
6866 | struct drm_connector_state *old_con_state = |
6867 | drm_atomic_get_old_connector_state(state, conn); | |
6868 | struct drm_crtc *crtc = new_con_state->crtc; | |
6869 | struct drm_crtc_state *new_crtc_state; | |
a76eb429 | 6870 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); |
88694af9 NK |
6871 | int ret; |
6872 | ||
e8a98235 RS |
6873 | trace_amdgpu_dm_connector_atomic_check(new_con_state); |
6874 | ||
a76eb429 LP |
6875 | if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { |
6876 | ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); | |
6877 | if (ret < 0) | |
6878 | return ret; | |
6879 | } | |
6880 | ||
88694af9 NK |
6881 | if (!crtc) |
6882 | return 0; | |
6883 | ||
a0b433c8 HW |
6884 | if (new_con_state->colorspace != old_con_state->colorspace) { |
6885 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
6886 | if (IS_ERR(new_crtc_state)) | |
6887 | return PTR_ERR(new_crtc_state); | |
6888 | ||
6889 | new_crtc_state->mode_changed = true; | |
6890 | } | |
6891 | ||
4c4583fd JA |
6892 | if (new_con_state->content_type != old_con_state->content_type) { |
6893 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
6894 | if (IS_ERR(new_crtc_state)) | |
6895 | return PTR_ERR(new_crtc_state); | |
6896 | ||
6897 | new_crtc_state->mode_changed = true; | |
6898 | } | |
6899 | ||
72921cdf | 6900 | if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { |
88694af9 NK |
6901 | struct dc_info_packet hdr_infopacket; |
6902 | ||
6903 | ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); | |
6904 | if (ret) | |
6905 | return ret; | |
6906 | ||
6907 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
6908 | if (IS_ERR(new_crtc_state)) | |
6909 | return PTR_ERR(new_crtc_state); | |
6910 | ||
6911 | /* | |
6912 | * DC considers the stream backends changed if the | |
6913 | * static metadata changes. Forcing the modeset also | |
6914 | * gives a simple way for userspace to switch from | |
b232d4ed NK |
6915 | * 8bpc to 10bpc when setting the metadata to enter |
6916 | * or exit HDR. | |
6917 | * | |
6918 | * Changing the static metadata after it's been | |
6919 | * set is permissible, however. So only force a | |
6920 | * modeset if we're entering or exiting HDR. | |
88694af9 | 6921 | */ |
a0b433c8 | 6922 | new_crtc_state->mode_changed = new_crtc_state->mode_changed || |
b232d4ed NK |
6923 | !old_con_state->hdr_output_metadata || |
6924 | !new_con_state->hdr_output_metadata; | |
88694af9 NK |
6925 | } |
6926 | ||
6927 | return 0; | |
6928 | } | |
6929 | ||
e7b07cee HW |
6930 | static const struct drm_connector_helper_funcs |
6931 | amdgpu_dm_connector_helper_funcs = { | |
6932 | /* | |
1f6010a9 | 6933 | * If hotplugging a second bigger display in FB Con mode, bigger resolution |
b830ebc9 | 6934 | * modes will be filtered by drm_mode_validate_size(), and those modes |
1f6010a9 | 6935 | * are missing after user start lightdm. So we need to renew modes list. |
b830ebc9 HW |
6936 | * in get_modes call back, not just return the modes count |
6937 | */ | |
e7b07cee HW |
6938 | .get_modes = get_modes, |
6939 | .mode_valid = amdgpu_dm_connector_mode_valid, | |
88694af9 | 6940 | .atomic_check = amdgpu_dm_connector_atomic_check, |
e7b07cee HW |
6941 | }; |
6942 | ||
e7b07cee HW |
6943 | static void dm_encoder_helper_disable(struct drm_encoder *encoder) |
6944 | { | |
6945 | ||
6946 | } | |
6947 | ||
f04d275d | 6948 | int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) |
3261e013 ML |
6949 | { |
6950 | switch (display_color_depth) { | |
5d945cbc RS |
6951 | case COLOR_DEPTH_666: |
6952 | return 6; | |
6953 | case COLOR_DEPTH_888: | |
6954 | return 8; | |
6955 | case COLOR_DEPTH_101010: | |
6956 | return 10; | |
6957 | case COLOR_DEPTH_121212: | |
6958 | return 12; | |
6959 | case COLOR_DEPTH_141414: | |
6960 | return 14; | |
6961 | case COLOR_DEPTH_161616: | |
6962 | return 16; | |
6963 | default: | |
6964 | break; | |
6965 | } | |
3261e013 ML |
6966 | return 0; |
6967 | } | |
6968 | ||
3ee6b26b AD |
6969 | static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, |
6970 | struct drm_crtc_state *crtc_state, | |
6971 | struct drm_connector_state *conn_state) | |
e7b07cee | 6972 | { |
3261e013 ML |
6973 | struct drm_atomic_state *state = crtc_state->state; |
6974 | struct drm_connector *connector = conn_state->connector; | |
6975 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
6976 | struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); | |
6977 | const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; | |
6978 | struct drm_dp_mst_topology_mgr *mst_mgr; | |
6979 | struct drm_dp_mst_port *mst_port; | |
4d07b0bc | 6980 | struct drm_dp_mst_topology_state *mst_state; |
3261e013 ML |
6981 | enum dc_color_depth color_depth; |
6982 | int clock, bpp = 0; | |
1bc22f20 | 6983 | bool is_y420 = false; |
3261e013 | 6984 | |
91b38ca1 | 6985 | if (!aconnector->mst_output_port) |
3261e013 ML |
6986 | return 0; |
6987 | ||
f0127cb1 WL |
6988 | mst_port = aconnector->mst_output_port; |
6989 | mst_mgr = &aconnector->mst_root->mst_mgr; | |
3261e013 ML |
6990 | |
6991 | if (!crtc_state->connectors_changed && !crtc_state->mode_changed) | |
6992 | return 0; | |
6993 | ||
4d07b0bc LP |
6994 | mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); |
6995 | if (IS_ERR(mst_state)) | |
6996 | return PTR_ERR(mst_state); | |
6997 | ||
191dc439 ID |
6998 | if (!mst_state->pbn_div.full) |
6999 | mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); | |
4d07b0bc | 7000 | |
3261e013 | 7001 | if (!state->duplicated) { |
cbd14ae7 | 7002 | int max_bpc = conn_state->max_requested_bpc; |
c82eddf8 | 7003 | |
1bc22f20 | 7004 | is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && |
5d945cbc | 7005 | aconnector->force_yuv420_output; |
cbd14ae7 SW |
7006 | color_depth = convert_color_depth_from_display_info(connector, |
7007 | is_y420, | |
7008 | max_bpc); | |
3261e013 ML |
7009 | bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; |
7010 | clock = adjusted_mode->clock; | |
7707dd60 | 7011 | dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); |
3261e013 | 7012 | } |
4d07b0bc LP |
7013 | |
7014 | dm_new_connector_state->vcpi_slots = | |
7015 | drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, | |
7016 | dm_new_connector_state->pbn); | |
3261e013 ML |
7017 | if (dm_new_connector_state->vcpi_slots < 0) { |
7018 | DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); | |
7019 | return dm_new_connector_state->vcpi_slots; | |
7020 | } | |
e7b07cee HW |
7021 | return 0; |
7022 | } | |
7023 | ||
7024 | const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { | |
7025 | .disable = dm_encoder_helper_disable, | |
7026 | .atomic_check = dm_encoder_helper_atomic_check | |
7027 | }; | |
7028 | ||
29b9ba74 | 7029 | static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, |
6513104b HW |
7030 | struct dc_state *dc_state, |
7031 | struct dsc_mst_fairness_vars *vars) | |
29b9ba74 ML |
7032 | { |
7033 | struct dc_stream_state *stream = NULL; | |
7034 | struct drm_connector *connector; | |
5760dcb9 | 7035 | struct drm_connector_state *new_con_state; |
29b9ba74 ML |
7036 | struct amdgpu_dm_connector *aconnector; |
7037 | struct dm_connector_state *dm_conn_state; | |
7cce4cd6 | 7038 | int i, j, ret; |
a550bb16 | 7039 | int vcpi, pbn_div, pbn, slot_num = 0; |
29b9ba74 | 7040 | |
5760dcb9 | 7041 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
29b9ba74 | 7042 | |
7db7ade2 HW |
7043 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
7044 | continue; | |
7045 | ||
29b9ba74 ML |
7046 | aconnector = to_amdgpu_dm_connector(connector); |
7047 | ||
f0127cb1 | 7048 | if (!aconnector->mst_output_port) |
29b9ba74 ML |
7049 | continue; |
7050 | ||
7051 | if (!new_con_state || !new_con_state->crtc) | |
7052 | continue; | |
7053 | ||
7054 | dm_conn_state = to_dm_connector_state(new_con_state); | |
7055 | ||
7056 | for (j = 0; j < dc_state->stream_count; j++) { | |
7057 | stream = dc_state->streams[j]; | |
7058 | if (!stream) | |
7059 | continue; | |
7060 | ||
5d945cbc | 7061 | if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) |
29b9ba74 ML |
7062 | break; |
7063 | ||
7064 | stream = NULL; | |
7065 | } | |
7066 | ||
7067 | if (!stream) | |
7068 | continue; | |
7069 | ||
29b9ba74 | 7070 | pbn_div = dm_mst_get_pbn_divider(stream->link); |
6513104b HW |
7071 | /* pbn is calculated by compute_mst_dsc_configs_for_state*/ |
7072 | for (j = 0; j < dc_state->stream_count; j++) { | |
7073 | if (vars[j].aconnector == aconnector) { | |
7074 | pbn = vars[j].pbn; | |
7075 | break; | |
7076 | } | |
7077 | } | |
7078 | ||
a550bb16 HW |
7079 | if (j == dc_state->stream_count) |
7080 | continue; | |
7081 | ||
7082 | slot_num = DIV_ROUND_UP(pbn, pbn_div); | |
7083 | ||
7084 | if (stream->timing.flags.DSC != 1) { | |
7085 | dm_conn_state->pbn = pbn; | |
7086 | dm_conn_state->vcpi_slots = slot_num; | |
7087 | ||
f0127cb1 | 7088 | ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, |
7cce4cd6 LP |
7089 | dm_conn_state->pbn, false); |
7090 | if (ret < 0) | |
7091 | return ret; | |
7092 | ||
a550bb16 HW |
7093 | continue; |
7094 | } | |
7095 | ||
f0127cb1 | 7096 | vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); |
29b9ba74 ML |
7097 | if (vcpi < 0) |
7098 | return vcpi; | |
7099 | ||
7100 | dm_conn_state->pbn = pbn; | |
7101 | dm_conn_state->vcpi_slots = vcpi; | |
7102 | } | |
7103 | return 0; | |
7104 | } | |
7105 | ||
e7b07cee HW |
7106 | static int to_drm_connector_type(enum signal_type st) |
7107 | { | |
7108 | switch (st) { | |
7109 | case SIGNAL_TYPE_HDMI_TYPE_A: | |
7110 | return DRM_MODE_CONNECTOR_HDMIA; | |
7111 | case SIGNAL_TYPE_EDP: | |
7112 | return DRM_MODE_CONNECTOR_eDP; | |
11c3ee48 AD |
7113 | case SIGNAL_TYPE_LVDS: |
7114 | return DRM_MODE_CONNECTOR_LVDS; | |
e7b07cee HW |
7115 | case SIGNAL_TYPE_RGB: |
7116 | return DRM_MODE_CONNECTOR_VGA; | |
7117 | case SIGNAL_TYPE_DISPLAY_PORT: | |
7118 | case SIGNAL_TYPE_DISPLAY_PORT_MST: | |
7119 | return DRM_MODE_CONNECTOR_DisplayPort; | |
7120 | case SIGNAL_TYPE_DVI_DUAL_LINK: | |
7121 | case SIGNAL_TYPE_DVI_SINGLE_LINK: | |
7122 | return DRM_MODE_CONNECTOR_DVID; | |
7123 | case SIGNAL_TYPE_VIRTUAL: | |
7124 | return DRM_MODE_CONNECTOR_VIRTUAL; | |
7125 | ||
7126 | default: | |
7127 | return DRM_MODE_CONNECTOR_Unknown; | |
7128 | } | |
7129 | } | |
7130 | ||
2b4c1c05 DV |
7131 | static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) |
7132 | { | |
62afb4ad JRS |
7133 | struct drm_encoder *encoder; |
7134 | ||
7135 | /* There is only one encoder per connector */ | |
7136 | drm_connector_for_each_possible_encoder(connector, encoder) | |
7137 | return encoder; | |
7138 | ||
7139 | return NULL; | |
2b4c1c05 DV |
7140 | } |
7141 | ||
e7b07cee HW |
7142 | static void amdgpu_dm_get_native_mode(struct drm_connector *connector) |
7143 | { | |
e7b07cee HW |
7144 | struct drm_encoder *encoder; |
7145 | struct amdgpu_encoder *amdgpu_encoder; | |
7146 | ||
2b4c1c05 | 7147 | encoder = amdgpu_dm_connector_to_encoder(connector); |
e7b07cee HW |
7148 | |
7149 | if (encoder == NULL) | |
7150 | return; | |
7151 | ||
7152 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
7153 | ||
7154 | amdgpu_encoder->native_mode.clock = 0; | |
7155 | ||
7156 | if (!list_empty(&connector->probed_modes)) { | |
7157 | struct drm_display_mode *preferred_mode = NULL; | |
b830ebc9 | 7158 | |
e7b07cee | 7159 | list_for_each_entry(preferred_mode, |
b830ebc9 HW |
7160 | &connector->probed_modes, |
7161 | head) { | |
7162 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) | |
7163 | amdgpu_encoder->native_mode = *preferred_mode; | |
7164 | ||
e7b07cee HW |
7165 | break; |
7166 | } | |
7167 | ||
7168 | } | |
7169 | } | |
7170 | ||
3ee6b26b AD |
7171 | static struct drm_display_mode * |
7172 | amdgpu_dm_create_common_mode(struct drm_encoder *encoder, | |
7173 | char *name, | |
7174 | int hdisplay, int vdisplay) | |
e7b07cee HW |
7175 | { |
7176 | struct drm_device *dev = encoder->dev; | |
7177 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
7178 | struct drm_display_mode *mode = NULL; | |
7179 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
7180 | ||
7181 | mode = drm_mode_duplicate(dev, native_mode); | |
7182 | ||
b830ebc9 | 7183 | if (mode == NULL) |
e7b07cee HW |
7184 | return NULL; |
7185 | ||
7186 | mode->hdisplay = hdisplay; | |
7187 | mode->vdisplay = vdisplay; | |
7188 | mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
090afc1e | 7189 | strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); |
e7b07cee HW |
7190 | |
7191 | return mode; | |
7192 | ||
7193 | } | |
7194 | ||
7195 | static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, | |
3ee6b26b | 7196 | struct drm_connector *connector) |
e7b07cee HW |
7197 | { |
7198 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
7199 | struct drm_display_mode *mode = NULL; | |
7200 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
c84dec2f HW |
7201 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7202 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
7203 | int i; |
7204 | int n; | |
7205 | struct mode_size { | |
7206 | char name[DRM_DISPLAY_MODE_LEN]; | |
7207 | int w; | |
7208 | int h; | |
b830ebc9 | 7209 | } common_modes[] = { |
e7b07cee HW |
7210 | { "640x480", 640, 480}, |
7211 | { "800x600", 800, 600}, | |
7212 | { "1024x768", 1024, 768}, | |
7213 | { "1280x720", 1280, 720}, | |
7214 | { "1280x800", 1280, 800}, | |
7215 | {"1280x1024", 1280, 1024}, | |
7216 | { "1440x900", 1440, 900}, | |
7217 | {"1680x1050", 1680, 1050}, | |
7218 | {"1600x1200", 1600, 1200}, | |
7219 | {"1920x1080", 1920, 1080}, | |
7220 | {"1920x1200", 1920, 1200} | |
7221 | }; | |
7222 | ||
b830ebc9 | 7223 | n = ARRAY_SIZE(common_modes); |
e7b07cee HW |
7224 | |
7225 | for (i = 0; i < n; i++) { | |
7226 | struct drm_display_mode *curmode = NULL; | |
7227 | bool mode_existed = false; | |
7228 | ||
7229 | if (common_modes[i].w > native_mode->hdisplay || | |
b830ebc9 HW |
7230 | common_modes[i].h > native_mode->vdisplay || |
7231 | (common_modes[i].w == native_mode->hdisplay && | |
7232 | common_modes[i].h == native_mode->vdisplay)) | |
7233 | continue; | |
e7b07cee HW |
7234 | |
7235 | list_for_each_entry(curmode, &connector->probed_modes, head) { | |
7236 | if (common_modes[i].w == curmode->hdisplay && | |
b830ebc9 | 7237 | common_modes[i].h == curmode->vdisplay) { |
e7b07cee HW |
7238 | mode_existed = true; |
7239 | break; | |
7240 | } | |
7241 | } | |
7242 | ||
7243 | if (mode_existed) | |
7244 | continue; | |
7245 | ||
7246 | mode = amdgpu_dm_create_common_mode(encoder, | |
7247 | common_modes[i].name, common_modes[i].w, | |
7248 | common_modes[i].h); | |
588a7017 ZQ |
7249 | if (!mode) |
7250 | continue; | |
7251 | ||
e7b07cee | 7252 | drm_mode_probed_add(connector, mode); |
c84dec2f | 7253 | amdgpu_dm_connector->num_modes++; |
e7b07cee HW |
7254 | } |
7255 | } | |
7256 | ||
d77de788 SS |
7257 | static void amdgpu_set_panel_orientation(struct drm_connector *connector) |
7258 | { | |
7259 | struct drm_encoder *encoder; | |
7260 | struct amdgpu_encoder *amdgpu_encoder; | |
7261 | const struct drm_display_mode *native_mode; | |
7262 | ||
7263 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && | |
7264 | connector->connector_type != DRM_MODE_CONNECTOR_LVDS) | |
7265 | return; | |
7266 | ||
acc96ae0 MW |
7267 | mutex_lock(&connector->dev->mode_config.mutex); |
7268 | amdgpu_dm_connector_get_modes(connector); | |
7269 | mutex_unlock(&connector->dev->mode_config.mutex); | |
7270 | ||
d77de788 SS |
7271 | encoder = amdgpu_dm_connector_to_encoder(connector); |
7272 | if (!encoder) | |
7273 | return; | |
7274 | ||
7275 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
7276 | ||
7277 | native_mode = &amdgpu_encoder->native_mode; | |
7278 | if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) | |
7279 | return; | |
7280 | ||
7281 | drm_connector_set_panel_orientation_with_quirk(connector, | |
7282 | DRM_MODE_PANEL_ORIENTATION_UNKNOWN, | |
7283 | native_mode->hdisplay, | |
7284 | native_mode->vdisplay); | |
7285 | } | |
7286 | ||
3ee6b26b AD |
7287 | static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, |
7288 | struct edid *edid) | |
e7b07cee | 7289 | { |
c84dec2f HW |
7290 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7291 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
7292 | |
7293 | if (edid) { | |
7294 | /* empty probed_modes */ | |
7295 | INIT_LIST_HEAD(&connector->probed_modes); | |
c84dec2f | 7296 | amdgpu_dm_connector->num_modes = |
e7b07cee HW |
7297 | drm_add_edid_modes(connector, edid); |
7298 | ||
f1e5e913 YMM |
7299 | /* sorting the probed modes before calling function |
7300 | * amdgpu_dm_get_native_mode() since EDID can have | |
7301 | * more than one preferred mode. The modes that are | |
7302 | * later in the probed mode list could be of higher | |
7303 | * and preferred resolution. For example, 3840x2160 | |
7304 | * resolution in base EDID preferred timing and 4096x2160 | |
7305 | * preferred resolution in DID extension block later. | |
7306 | */ | |
7307 | drm_mode_sort(&connector->probed_modes); | |
e7b07cee | 7308 | amdgpu_dm_get_native_mode(connector); |
f9b4f20c SW |
7309 | |
7310 | /* Freesync capabilities are reset by calling | |
7311 | * drm_add_edid_modes() and need to be | |
7312 | * restored here. | |
7313 | */ | |
7314 | amdgpu_dm_update_freesync_caps(connector, edid); | |
a8d8d3dc | 7315 | } else { |
c84dec2f | 7316 | amdgpu_dm_connector->num_modes = 0; |
a8d8d3dc | 7317 | } |
e7b07cee HW |
7318 | } |
7319 | ||
a85ba005 NC |
7320 | static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, |
7321 | struct drm_display_mode *mode) | |
7322 | { | |
7323 | struct drm_display_mode *m; | |
7324 | ||
c82eddf8 | 7325 | list_for_each_entry(m, &aconnector->base.probed_modes, head) { |
a85ba005 NC |
7326 | if (drm_mode_equal(m, mode)) |
7327 | return true; | |
7328 | } | |
7329 | ||
7330 | return false; | |
7331 | } | |
7332 | ||
7333 | static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) | |
7334 | { | |
7335 | const struct drm_display_mode *m; | |
7336 | struct drm_display_mode *new_mode; | |
7337 | uint i; | |
ae67558b | 7338 | u32 new_modes_count = 0; |
a85ba005 NC |
7339 | |
7340 | /* Standard FPS values | |
7341 | * | |
12cdff6b | 7342 | * 23.976 - TV/NTSC |
3335a135 UKK |
7343 | * 24 - Cinema |
7344 | * 25 - TV/PAL | |
12cdff6b | 7345 | * 29.97 - TV/NTSC |
3335a135 UKK |
7346 | * 30 - TV/NTSC |
7347 | * 48 - Cinema HFR | |
7348 | * 50 - TV/PAL | |
7349 | * 60 - Commonly used | |
12cdff6b | 7350 | * 48,72,96,120 - Multiples of 24 |
a85ba005 | 7351 | */ |
ae67558b | 7352 | static const u32 common_rates[] = { |
9ce5ed6e | 7353 | 23976, 24000, 25000, 29970, 30000, |
12cdff6b | 7354 | 48000, 50000, 60000, 72000, 96000, 120000 |
9ce5ed6e | 7355 | }; |
a85ba005 NC |
7356 | |
7357 | /* | |
7358 | * Find mode with highest refresh rate with the same resolution | |
7359 | * as the preferred mode. Some monitors report a preferred mode | |
7360 | * with lower resolution than the highest refresh rate supported. | |
7361 | */ | |
7362 | ||
7363 | m = get_highest_refresh_rate_mode(aconnector, true); | |
7364 | if (!m) | |
7365 | return 0; | |
7366 | ||
7367 | for (i = 0; i < ARRAY_SIZE(common_rates); i++) { | |
ae67558b SS |
7368 | u64 target_vtotal, target_vtotal_diff; |
7369 | u64 num, den; | |
a85ba005 NC |
7370 | |
7371 | if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) | |
7372 | continue; | |
7373 | ||
7374 | if (common_rates[i] < aconnector->min_vfreq * 1000 || | |
7375 | common_rates[i] > aconnector->max_vfreq * 1000) | |
7376 | continue; | |
7377 | ||
7378 | num = (unsigned long long)m->clock * 1000 * 1000; | |
7379 | den = common_rates[i] * (unsigned long long)m->htotal; | |
7380 | target_vtotal = div_u64(num, den); | |
7381 | target_vtotal_diff = target_vtotal - m->vtotal; | |
7382 | ||
7383 | /* Check for illegal modes */ | |
7384 | if (m->vsync_start + target_vtotal_diff < m->vdisplay || | |
7385 | m->vsync_end + target_vtotal_diff < m->vsync_start || | |
7386 | m->vtotal + target_vtotal_diff < m->vsync_end) | |
7387 | continue; | |
7388 | ||
7389 | new_mode = drm_mode_duplicate(aconnector->base.dev, m); | |
7390 | if (!new_mode) | |
7391 | goto out; | |
7392 | ||
7393 | new_mode->vtotal += (u16)target_vtotal_diff; | |
7394 | new_mode->vsync_start += (u16)target_vtotal_diff; | |
7395 | new_mode->vsync_end += (u16)target_vtotal_diff; | |
7396 | new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
7397 | new_mode->type |= DRM_MODE_TYPE_DRIVER; | |
7398 | ||
7399 | if (!is_duplicate_mode(aconnector, new_mode)) { | |
7400 | drm_mode_probed_add(&aconnector->base, new_mode); | |
7401 | new_modes_count += 1; | |
7402 | } else | |
7403 | drm_mode_destroy(aconnector->base.dev, new_mode); | |
7404 | } | |
7405 | out: | |
7406 | return new_modes_count; | |
7407 | } | |
7408 | ||
7409 | static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, | |
7410 | struct edid *edid) | |
7411 | { | |
7412 | struct amdgpu_dm_connector *amdgpu_dm_connector = | |
7413 | to_amdgpu_dm_connector(connector); | |
7414 | ||
11b92df8 | 7415 | if (!edid) |
a85ba005 | 7416 | return; |
fe8858bb | 7417 | |
a85ba005 NC |
7418 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) |
7419 | amdgpu_dm_connector->num_modes += | |
7420 | add_fs_modes(amdgpu_dm_connector); | |
7421 | } | |
7422 | ||
7578ecda | 7423 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) |
e7b07cee | 7424 | { |
c84dec2f HW |
7425 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7426 | to_amdgpu_dm_connector(connector); | |
e7b07cee | 7427 | struct drm_encoder *encoder; |
c84dec2f | 7428 | struct edid *edid = amdgpu_dm_connector->edid; |
c32699ca JD |
7429 | struct dc_link_settings *verified_link_cap = |
7430 | &amdgpu_dm_connector->dc_link->verified_link_cap; | |
98ce7d32 | 7431 | const struct dc *dc = amdgpu_dm_connector->dc_link->dc; |
e7b07cee | 7432 | |
2b4c1c05 | 7433 | encoder = amdgpu_dm_connector_to_encoder(connector); |
3e332d3a | 7434 | |
5c0e6840 | 7435 | if (!drm_edid_is_valid(edid)) { |
1b369d3c ML |
7436 | amdgpu_dm_connector->num_modes = |
7437 | drm_add_modes_noedid(connector, 640, 480); | |
98ce7d32 | 7438 | if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) |
c32699ca JD |
7439 | amdgpu_dm_connector->num_modes += |
7440 | drm_add_modes_noedid(connector, 1920, 1080); | |
85ee15d6 ML |
7441 | } else { |
7442 | amdgpu_dm_connector_ddc_get_modes(connector, edid); | |
d6149086 | 7443 | amdgpu_dm_connector_add_common_modes(encoder, connector); |
a85ba005 | 7444 | amdgpu_dm_connector_add_freesync_modes(connector, edid); |
85ee15d6 | 7445 | } |
3e332d3a | 7446 | amdgpu_dm_fbc_init(connector); |
5099114b | 7447 | |
c84dec2f | 7448 | return amdgpu_dm_connector->num_modes; |
e7b07cee HW |
7449 | } |
7450 | ||
15f9dfd5 HW |
7451 | static const u32 supported_colorspaces = |
7452 | BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | | |
7453 | BIT(DRM_MODE_COLORIMETRY_OPRGB) | | |
7454 | BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | | |
7455 | BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); | |
7456 | ||
3ee6b26b AD |
7457 | void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, |
7458 | struct amdgpu_dm_connector *aconnector, | |
7459 | int connector_type, | |
7460 | struct dc_link *link, | |
7461 | int link_index) | |
e7b07cee | 7462 | { |
1348969a | 7463 | struct amdgpu_device *adev = drm_to_adev(dm->ddev); |
e7b07cee | 7464 | |
f04bee34 NK |
7465 | /* |
7466 | * Some of the properties below require access to state, like bpc. | |
7467 | * Allocate some default initial connector state with our reset helper. | |
7468 | */ | |
7469 | if (aconnector->base.funcs->reset) | |
7470 | aconnector->base.funcs->reset(&aconnector->base); | |
7471 | ||
e7b07cee | 7472 | aconnector->connector_id = link_index; |
f196198c | 7473 | aconnector->bl_idx = -1; |
e7b07cee HW |
7474 | aconnector->dc_link = link; |
7475 | aconnector->base.interlace_allowed = false; | |
7476 | aconnector->base.doublescan_allowed = false; | |
7477 | aconnector->base.stereo_allowed = false; | |
7478 | aconnector->base.dpms = DRM_MODE_DPMS_OFF; | |
7479 | aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ | |
6ce8f316 | 7480 | aconnector->audio_inst = -1; |
5b49da02 SJK |
7481 | aconnector->pack_sdp_v1_3 = false; |
7482 | aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; | |
7483 | memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); | |
e7b07cee | 7484 | mutex_init(&aconnector->hpd_lock); |
bb4fa525 | 7485 | mutex_init(&aconnector->handle_mst_msg_ready); |
e7b07cee | 7486 | |
1f6010a9 DF |
7487 | /* |
7488 | * configure support HPD hot plug connector_>polled default value is 0 | |
b830ebc9 HW |
7489 | * which means HPD hot plug not supported |
7490 | */ | |
e7b07cee HW |
7491 | switch (connector_type) { |
7492 | case DRM_MODE_CONNECTOR_HDMIA: | |
7493 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
e7baae1c | 7494 | aconnector->base.ycbcr_420_allowed = |
9ea59d5a | 7495 | link->link_enc->features.hdmi_ycbcr420_supported ? true : false; |
e7b07cee HW |
7496 | break; |
7497 | case DRM_MODE_CONNECTOR_DisplayPort: | |
7498 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
d715c9a2 | 7499 | link->link_enc = link_enc_cfg_get_link_enc(link); |
7b201d53 | 7500 | ASSERT(link->link_enc); |
f6e03f80 JS |
7501 | if (link->link_enc) |
7502 | aconnector->base.ycbcr_420_allowed = | |
9ea59d5a | 7503 | link->link_enc->features.dp_ycbcr420_supported ? true : false; |
e7b07cee HW |
7504 | break; |
7505 | case DRM_MODE_CONNECTOR_DVID: | |
7506 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
7507 | break; | |
7508 | default: | |
7509 | break; | |
7510 | } | |
7511 | ||
7512 | drm_object_attach_property(&aconnector->base.base, | |
7513 | dm->ddev->mode_config.scaling_mode_property, | |
7514 | DRM_MODE_SCALE_NONE); | |
7515 | ||
7516 | drm_object_attach_property(&aconnector->base.base, | |
7517 | adev->mode_info.underscan_property, | |
7518 | UNDERSCAN_OFF); | |
7519 | drm_object_attach_property(&aconnector->base.base, | |
7520 | adev->mode_info.underscan_hborder_property, | |
7521 | 0); | |
7522 | drm_object_attach_property(&aconnector->base.base, | |
7523 | adev->mode_info.underscan_vborder_property, | |
7524 | 0); | |
1825fd34 | 7525 | |
f0127cb1 | 7526 | if (!aconnector->mst_root) |
8c61b31e | 7527 | drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); |
1825fd34 | 7528 | |
e47f1691 | 7529 | aconnector->base.state->max_bpc = 16; |
4a8ca46b | 7530 | aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; |
e7b07cee | 7531 | |
c1ee92f9 | 7532 | if (connector_type == DRM_MODE_CONNECTOR_eDP && |
5cb32419 | 7533 | (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { |
c1ee92f9 DF |
7534 | drm_object_attach_property(&aconnector->base.base, |
7535 | adev->mode_info.abm_level_property, 0); | |
7536 | } | |
bb47de73 | 7537 | |
4c4583fd JA |
7538 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
7539 | /* Content Type is currently only implemented for HDMI. */ | |
7540 | drm_connector_attach_content_type_property(&aconnector->base); | |
7541 | } | |
7542 | ||
15f9dfd5 HW |
7543 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
7544 | if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) | |
7545 | drm_connector_attach_colorspace_property(&aconnector->base); | |
69a95961 | 7546 | } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || |
15f9dfd5 HW |
7547 | connector_type == DRM_MODE_CONNECTOR_eDP) { |
7548 | if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) | |
7549 | drm_connector_attach_colorspace_property(&aconnector->base); | |
7550 | } | |
7551 | ||
bb47de73 | 7552 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA || |
7fad8da1 NK |
7553 | connector_type == DRM_MODE_CONNECTOR_DisplayPort || |
7554 | connector_type == DRM_MODE_CONNECTOR_eDP) { | |
e057b52c | 7555 | drm_connector_attach_hdr_output_metadata_property(&aconnector->base); |
88694af9 | 7556 | |
f0127cb1 | 7557 | if (!aconnector->mst_root) |
8c61b31e JFZ |
7558 | drm_connector_attach_vrr_capable_property(&aconnector->base); |
7559 | ||
e22bb562 | 7560 | if (adev->dm.hdcp_workqueue) |
53e108aa | 7561 | drm_connector_attach_content_protection_property(&aconnector->base, true); |
bb47de73 | 7562 | } |
e7b07cee HW |
7563 | } |
7564 | ||
7578ecda AD |
7565 | static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, |
7566 | struct i2c_msg *msgs, int num) | |
e7b07cee HW |
7567 | { |
7568 | struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); | |
7569 | struct ddc_service *ddc_service = i2c->ddc_service; | |
7570 | struct i2c_command cmd; | |
7571 | int i; | |
7572 | int result = -EIO; | |
7573 | ||
b71f4ade ML |
7574 | if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) |
7575 | return result; | |
7576 | ||
b830ebc9 | 7577 | cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); |
e7b07cee HW |
7578 | |
7579 | if (!cmd.payloads) | |
7580 | return result; | |
7581 | ||
7582 | cmd.number_of_payloads = num; | |
7583 | cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; | |
7584 | cmd.speed = 100; | |
7585 | ||
7586 | for (i = 0; i < num; i++) { | |
7587 | cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); | |
7588 | cmd.payloads[i].address = msgs[i].addr; | |
7589 | cmd.payloads[i].length = msgs[i].len; | |
7590 | cmd.payloads[i].data = msgs[i].buf; | |
7591 | } | |
7592 | ||
c85e6e54 DF |
7593 | if (dc_submit_i2c( |
7594 | ddc_service->ctx->dc, | |
22676bc5 | 7595 | ddc_service->link->link_index, |
e7b07cee HW |
7596 | &cmd)) |
7597 | result = num; | |
7598 | ||
7599 | kfree(cmd.payloads); | |
7600 | return result; | |
7601 | } | |
7602 | ||
7578ecda | 7603 | static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) |
e7b07cee HW |
7604 | { |
7605 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
7606 | } | |
7607 | ||
7608 | static const struct i2c_algorithm amdgpu_dm_i2c_algo = { | |
7609 | .master_xfer = amdgpu_dm_i2c_xfer, | |
7610 | .functionality = amdgpu_dm_i2c_func, | |
7611 | }; | |
7612 | ||
3ee6b26b AD |
7613 | static struct amdgpu_i2c_adapter * |
7614 | create_i2c(struct ddc_service *ddc_service, | |
7615 | int link_index, | |
7616 | int *res) | |
e7b07cee HW |
7617 | { |
7618 | struct amdgpu_device *adev = ddc_service->ctx->driver_context; | |
7619 | struct amdgpu_i2c_adapter *i2c; | |
7620 | ||
b830ebc9 | 7621 | i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); |
2a55f096 ES |
7622 | if (!i2c) |
7623 | return NULL; | |
e7b07cee HW |
7624 | i2c->base.owner = THIS_MODULE; |
7625 | i2c->base.class = I2C_CLASS_DDC; | |
7626 | i2c->base.dev.parent = &adev->pdev->dev; | |
7627 | i2c->base.algo = &amdgpu_dm_i2c_algo; | |
b830ebc9 | 7628 | snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); |
e7b07cee HW |
7629 | i2c_set_adapdata(&i2c->base, i2c); |
7630 | i2c->ddc_service = ddc_service; | |
7631 | ||
7632 | return i2c; | |
7633 | } | |
7634 | ||
89fc8d4e | 7635 | |
1f6010a9 DF |
7636 | /* |
7637 | * Note: this function assumes that dc_link_detect() was called for the | |
b830ebc9 HW |
7638 | * dc_link which will be represented by this aconnector. |
7639 | */ | |
7578ecda AD |
7640 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
7641 | struct amdgpu_dm_connector *aconnector, | |
ae67558b | 7642 | u32 link_index, |
7578ecda | 7643 | struct amdgpu_encoder *aencoder) |
e7b07cee HW |
7644 | { |
7645 | int res = 0; | |
7646 | int connector_type; | |
7647 | struct dc *dc = dm->dc; | |
7648 | struct dc_link *link = dc_get_link_at_index(dc, link_index); | |
7649 | struct amdgpu_i2c_adapter *i2c; | |
9a227d26 | 7650 | |
ff73d4cd | 7651 | /* Not needed for writeback connector */ |
9a227d26 | 7652 | link->priv = aconnector; |
e7b07cee | 7653 | |
e7b07cee HW |
7654 | |
7655 | i2c = create_i2c(link->ddc, link->link_index, &res); | |
2a55f096 ES |
7656 | if (!i2c) { |
7657 | DRM_ERROR("Failed to create i2c adapter data\n"); | |
7658 | return -ENOMEM; | |
7659 | } | |
7660 | ||
e7b07cee HW |
7661 | aconnector->i2c = i2c; |
7662 | res = i2c_add_adapter(&i2c->base); | |
7663 | ||
7664 | if (res) { | |
7665 | DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); | |
7666 | goto out_free; | |
7667 | } | |
7668 | ||
7669 | connector_type = to_drm_connector_type(link->connector_signal); | |
7670 | ||
17165de2 | 7671 | res = drm_connector_init_with_ddc( |
e7b07cee HW |
7672 | dm->ddev, |
7673 | &aconnector->base, | |
7674 | &amdgpu_dm_connector_funcs, | |
17165de2 AP |
7675 | connector_type, |
7676 | &i2c->base); | |
e7b07cee HW |
7677 | |
7678 | if (res) { | |
7679 | DRM_ERROR("connector_init failed\n"); | |
7680 | aconnector->connector_id = -1; | |
7681 | goto out_free; | |
7682 | } | |
7683 | ||
7684 | drm_connector_helper_add( | |
7685 | &aconnector->base, | |
7686 | &amdgpu_dm_connector_helper_funcs); | |
7687 | ||
7688 | amdgpu_dm_connector_init_helper( | |
7689 | dm, | |
7690 | aconnector, | |
7691 | connector_type, | |
7692 | link, | |
7693 | link_index); | |
7694 | ||
cde4c44d | 7695 | drm_connector_attach_encoder( |
e7b07cee HW |
7696 | &aconnector->base, &aencoder->base); |
7697 | ||
e7b07cee HW |
7698 | if (connector_type == DRM_MODE_CONNECTOR_DisplayPort |
7699 | || connector_type == DRM_MODE_CONNECTOR_eDP) | |
7daec99f | 7700 | amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); |
e7b07cee | 7701 | |
e7b07cee HW |
7702 | out_free: |
7703 | if (res) { | |
7704 | kfree(i2c); | |
7705 | aconnector->i2c = NULL; | |
7706 | } | |
7707 | return res; | |
7708 | } | |
7709 | ||
7710 | int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) | |
7711 | { | |
7712 | switch (adev->mode_info.num_crtc) { | |
7713 | case 1: | |
7714 | return 0x1; | |
7715 | case 2: | |
7716 | return 0x3; | |
7717 | case 3: | |
7718 | return 0x7; | |
7719 | case 4: | |
7720 | return 0xf; | |
7721 | case 5: | |
7722 | return 0x1f; | |
7723 | case 6: | |
7724 | default: | |
7725 | return 0x3f; | |
7726 | } | |
7727 | } | |
7728 | ||
7578ecda AD |
7729 | static int amdgpu_dm_encoder_init(struct drm_device *dev, |
7730 | struct amdgpu_encoder *aencoder, | |
7731 | uint32_t link_index) | |
e7b07cee | 7732 | { |
1348969a | 7733 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
7734 | |
7735 | int res = drm_encoder_init(dev, | |
7736 | &aencoder->base, | |
7737 | &amdgpu_dm_encoder_funcs, | |
7738 | DRM_MODE_ENCODER_TMDS, | |
7739 | NULL); | |
7740 | ||
7741 | aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); | |
7742 | ||
7743 | if (!res) | |
7744 | aencoder->encoder_id = link_index; | |
7745 | else | |
7746 | aencoder->encoder_id = -1; | |
7747 | ||
7748 | drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); | |
7749 | ||
7750 | return res; | |
7751 | } | |
7752 | ||
3ee6b26b AD |
7753 | static void manage_dm_interrupts(struct amdgpu_device *adev, |
7754 | struct amdgpu_crtc *acrtc, | |
7755 | bool enable) | |
e7b07cee HW |
7756 | { |
7757 | /* | |
8fe684e9 NK |
7758 | * We have no guarantee that the frontend index maps to the same |
7759 | * backend index - some even map to more than one. | |
7760 | * | |
7761 | * TODO: Use a different interrupt or check DC itself for the mapping. | |
e7b07cee HW |
7762 | */ |
7763 | int irq_type = | |
734dd01d | 7764 | amdgpu_display_crtc_idx_to_irq_type( |
e7b07cee HW |
7765 | adev, |
7766 | acrtc->crtc_id); | |
7767 | ||
7768 | if (enable) { | |
7769 | drm_crtc_vblank_on(&acrtc->base); | |
7770 | amdgpu_irq_get( | |
7771 | adev, | |
7772 | &adev->pageflip_irq, | |
7773 | irq_type); | |
86bc2219 WL |
7774 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
7775 | amdgpu_irq_get( | |
7776 | adev, | |
7777 | &adev->vline0_irq, | |
7778 | irq_type); | |
7779 | #endif | |
e7b07cee | 7780 | } else { |
86bc2219 WL |
7781 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
7782 | amdgpu_irq_put( | |
7783 | adev, | |
7784 | &adev->vline0_irq, | |
7785 | irq_type); | |
7786 | #endif | |
e7b07cee HW |
7787 | amdgpu_irq_put( |
7788 | adev, | |
7789 | &adev->pageflip_irq, | |
7790 | irq_type); | |
7791 | drm_crtc_vblank_off(&acrtc->base); | |
7792 | } | |
7793 | } | |
7794 | ||
8fe684e9 NK |
7795 | static void dm_update_pflip_irq_state(struct amdgpu_device *adev, |
7796 | struct amdgpu_crtc *acrtc) | |
7797 | { | |
7798 | int irq_type = | |
7799 | amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); | |
7800 | ||
7801 | /** | |
7802 | * This reads the current state for the IRQ and force reapplies | |
7803 | * the setting to hardware. | |
7804 | */ | |
7805 | amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); | |
7806 | } | |
7807 | ||
3ee6b26b AD |
7808 | static bool |
7809 | is_scaling_state_different(const struct dm_connector_state *dm_state, | |
7810 | const struct dm_connector_state *old_dm_state) | |
e7b07cee HW |
7811 | { |
7812 | if (dm_state->scaling != old_dm_state->scaling) | |
7813 | return true; | |
7814 | if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { | |
7815 | if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) | |
7816 | return true; | |
7817 | } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { | |
7818 | if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) | |
7819 | return true; | |
b830ebc9 HW |
7820 | } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || |
7821 | dm_state->underscan_vborder != old_dm_state->underscan_vborder) | |
7822 | return true; | |
e7b07cee HW |
7823 | return false; |
7824 | } | |
7825 | ||
e8fd3eeb | 7826 | static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, |
7827 | struct drm_crtc_state *old_crtc_state, | |
7828 | struct drm_connector_state *new_conn_state, | |
7829 | struct drm_connector_state *old_conn_state, | |
7830 | const struct drm_connector *connector, | |
7831 | struct hdcp_workqueue *hdcp_w) | |
0c8620d6 BL |
7832 | { |
7833 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
97f6c917 | 7834 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); |
0c8620d6 | 7835 | |
e8fd3eeb | 7836 | pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", |
7837 | connector->index, connector->status, connector->dpms); | |
7838 | pr_debug("[HDCP_DM] state protection old: %x new: %x\n", | |
7839 | old_conn_state->content_protection, new_conn_state->content_protection); | |
7840 | ||
7841 | if (old_crtc_state) | |
7842 | pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
7843 | old_crtc_state->enable, | |
7844 | old_crtc_state->active, | |
7845 | old_crtc_state->mode_changed, | |
7846 | old_crtc_state->active_changed, | |
7847 | old_crtc_state->connectors_changed); | |
7848 | ||
7849 | if (new_crtc_state) | |
7850 | pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
7851 | new_crtc_state->enable, | |
7852 | new_crtc_state->active, | |
7853 | new_crtc_state->mode_changed, | |
7854 | new_crtc_state->active_changed, | |
7855 | new_crtc_state->connectors_changed); | |
7856 | ||
7857 | /* hdcp content type change */ | |
7858 | if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && | |
7859 | new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { | |
7860 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
7861 | pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); | |
53e108aa BL |
7862 | return true; |
7863 | } | |
7864 | ||
e8fd3eeb | 7865 | /* CP is being re enabled, ignore this */ |
7866 | if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && | |
7867 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { | |
7868 | if (new_crtc_state && new_crtc_state->mode_changed) { | |
7869 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
7870 | pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); | |
7871 | return true; | |
0b8f42ab | 7872 | } |
e8fd3eeb | 7873 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; |
7874 | pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); | |
0c8620d6 BL |
7875 | return false; |
7876 | } | |
7877 | ||
31c0ed90 BL |
7878 | /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED |
7879 | * | |
7880 | * Handles: UNDESIRED -> ENABLED | |
7881 | */ | |
e8fd3eeb | 7882 | if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && |
7883 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) | |
7884 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
0c8620d6 | 7885 | |
0d9a947b QZ |
7886 | /* Stream removed and re-enabled |
7887 | * | |
7888 | * Can sometimes overlap with the HPD case, | |
7889 | * thus set update_hdcp to false to avoid | |
7890 | * setting HDCP multiple times. | |
7891 | * | |
7892 | * Handles: DESIRED -> DESIRED (Special case) | |
7893 | */ | |
e8fd3eeb | 7894 | if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && |
7895 | new_conn_state->crtc && new_conn_state->crtc->enabled && | |
0d9a947b QZ |
7896 | connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { |
7897 | dm_con_state->update_hdcp = false; | |
e8fd3eeb | 7898 | pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", |
7899 | __func__); | |
0d9a947b QZ |
7900 | return true; |
7901 | } | |
7902 | ||
7903 | /* Hot-plug, headless s3, dpms | |
7904 | * | |
7905 | * Only start HDCP if the display is connected/enabled. | |
7906 | * update_hdcp flag will be set to false until the next | |
7907 | * HPD comes in. | |
31c0ed90 BL |
7908 | * |
7909 | * Handles: DESIRED -> DESIRED (Special case) | |
0c8620d6 | 7910 | */ |
e8fd3eeb | 7911 | if (dm_con_state->update_hdcp && |
7912 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && | |
7913 | connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { | |
97f6c917 | 7914 | dm_con_state->update_hdcp = false; |
e8fd3eeb | 7915 | pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", |
7916 | __func__); | |
0c8620d6 | 7917 | return true; |
97f6c917 | 7918 | } |
0c8620d6 | 7919 | |
e8fd3eeb | 7920 | if (old_conn_state->content_protection == new_conn_state->content_protection) { |
7921 | if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { | |
7922 | if (new_crtc_state && new_crtc_state->mode_changed) { | |
7923 | pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", | |
7924 | __func__); | |
7925 | return true; | |
0b8f42ab | 7926 | } |
e8fd3eeb | 7927 | pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", |
7928 | __func__); | |
7929 | return false; | |
0b8f42ab | 7930 | } |
e8fd3eeb | 7931 | |
7932 | pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); | |
0c8620d6 | 7933 | return false; |
e8fd3eeb | 7934 | } |
0c8620d6 | 7935 | |
e8fd3eeb | 7936 | if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { |
7937 | pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", | |
7938 | __func__); | |
0c8620d6 | 7939 | return true; |
e8fd3eeb | 7940 | } |
0c8620d6 | 7941 | |
e8fd3eeb | 7942 | pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); |
0c8620d6 BL |
7943 | return false; |
7944 | } | |
e8fd3eeb | 7945 | |
3ee6b26b AD |
7946 | static void remove_stream(struct amdgpu_device *adev, |
7947 | struct amdgpu_crtc *acrtc, | |
7948 | struct dc_stream_state *stream) | |
e7b07cee HW |
7949 | { |
7950 | /* this is the update mode case */ | |
e7b07cee HW |
7951 | |
7952 | acrtc->otg_inst = -1; | |
7953 | acrtc->enabled = false; | |
7954 | } | |
7955 | ||
e7b07cee HW |
7956 | static void prepare_flip_isr(struct amdgpu_crtc *acrtc) |
7957 | { | |
7958 | ||
7959 | assert_spin_locked(&acrtc->base.dev->event_lock); | |
7960 | WARN_ON(acrtc->event); | |
7961 | ||
7962 | acrtc->event = acrtc->base.state->event; | |
7963 | ||
7964 | /* Set the flip status */ | |
7965 | acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; | |
7966 | ||
7967 | /* Mark this event as consumed */ | |
7968 | acrtc->base.state->event = NULL; | |
7969 | ||
5d72e247 HM |
7970 | drm_dbg_state(acrtc->base.dev, |
7971 | "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", | |
7972 | acrtc->crtc_id); | |
e7b07cee HW |
7973 | } |
7974 | ||
bb47de73 NK |
7975 | static void update_freesync_state_on_stream( |
7976 | struct amdgpu_display_manager *dm, | |
7977 | struct dm_crtc_state *new_crtc_state, | |
180db303 NK |
7978 | struct dc_stream_state *new_stream, |
7979 | struct dc_plane_state *surface, | |
7980 | u32 flip_timestamp_in_us) | |
bb47de73 | 7981 | { |
09aef2c4 | 7982 | struct mod_vrr_params vrr_params; |
bb47de73 | 7983 | struct dc_info_packet vrr_infopacket = {0}; |
09aef2c4 | 7984 | struct amdgpu_device *adev = dm->adev; |
585d450c | 7985 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); |
09aef2c4 | 7986 | unsigned long flags; |
4cda3243 | 7987 | bool pack_sdp_v1_3 = false; |
5b49da02 SJK |
7988 | struct amdgpu_dm_connector *aconn; |
7989 | enum vrr_packet_type packet_type = PACKET_TYPE_VRR; | |
bb47de73 NK |
7990 | |
7991 | if (!new_stream) | |
7992 | return; | |
7993 | ||
7994 | /* | |
7995 | * TODO: Determine why min/max totals and vrefresh can be 0 here. | |
7996 | * For now it's sufficient to just guard against these conditions. | |
7997 | */ | |
7998 | ||
7999 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) | |
8000 | return; | |
8001 | ||
4a580877 | 8002 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
3335a135 | 8003 | vrr_params = acrtc->dm_irq_params.vrr_params; |
09aef2c4 | 8004 | |
180db303 NK |
8005 | if (surface) { |
8006 | mod_freesync_handle_preflip( | |
8007 | dm->freesync_module, | |
8008 | surface, | |
8009 | new_stream, | |
8010 | flip_timestamp_in_us, | |
8011 | &vrr_params); | |
09aef2c4 MK |
8012 | |
8013 | if (adev->family < AMDGPU_FAMILY_AI && | |
6c5e25a0 | 8014 | amdgpu_dm_crtc_vrr_active(new_crtc_state)) { |
09aef2c4 MK |
8015 | mod_freesync_handle_v_update(dm->freesync_module, |
8016 | new_stream, &vrr_params); | |
e63e2491 EB |
8017 | |
8018 | /* Need to call this before the frame ends. */ | |
8019 | dc_stream_adjust_vmin_vmax(dm->dc, | |
8020 | new_crtc_state->stream, | |
8021 | &vrr_params.adjust); | |
09aef2c4 | 8022 | } |
180db303 | 8023 | } |
bb47de73 | 8024 | |
5b49da02 SJK |
8025 | aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; |
8026 | ||
81a7be79 | 8027 | if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { |
5b49da02 SJK |
8028 | pack_sdp_v1_3 = aconn->pack_sdp_v1_3; |
8029 | ||
8030 | if (aconn->vsdb_info.amd_vsdb_version == 1) | |
8031 | packet_type = PACKET_TYPE_FS_V1; | |
8032 | else if (aconn->vsdb_info.amd_vsdb_version == 2) | |
8033 | packet_type = PACKET_TYPE_FS_V2; | |
8034 | else if (aconn->vsdb_info.amd_vsdb_version == 3) | |
8035 | packet_type = PACKET_TYPE_FS_V3; | |
8036 | ||
8037 | mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, | |
8038 | &new_stream->adaptive_sync_infopacket); | |
8039 | } | |
8040 | ||
bb47de73 NK |
8041 | mod_freesync_build_vrr_infopacket( |
8042 | dm->freesync_module, | |
8043 | new_stream, | |
180db303 | 8044 | &vrr_params, |
5b49da02 | 8045 | packet_type, |
ecd0136b | 8046 | TRANSFER_FUNC_UNKNOWN, |
4cda3243 MT |
8047 | &vrr_infopacket, |
8048 | pack_sdp_v1_3); | |
bb47de73 | 8049 | |
8a48b44c | 8050 | new_crtc_state->freesync_vrr_info_changed |= |
bb47de73 NK |
8051 | (memcmp(&new_crtc_state->vrr_infopacket, |
8052 | &vrr_infopacket, | |
8053 | sizeof(vrr_infopacket)) != 0); | |
8054 | ||
585d450c | 8055 | acrtc->dm_irq_params.vrr_params = vrr_params; |
bb47de73 NK |
8056 | new_crtc_state->vrr_infopacket = vrr_infopacket; |
8057 | ||
bb47de73 | 8058 | new_stream->vrr_infopacket = vrr_infopacket; |
7eaef116 | 8059 | new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); |
bb47de73 NK |
8060 | |
8061 | if (new_crtc_state->freesync_vrr_info_changed) | |
8062 | DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", | |
8063 | new_crtc_state->base.crtc->base.id, | |
8064 | (int)new_crtc_state->base.vrr_enabled, | |
180db303 | 8065 | (int)vrr_params.state); |
09aef2c4 | 8066 | |
4a580877 | 8067 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
bb47de73 NK |
8068 | } |
8069 | ||
585d450c | 8070 | static void update_stream_irq_parameters( |
e854194c MK |
8071 | struct amdgpu_display_manager *dm, |
8072 | struct dm_crtc_state *new_crtc_state) | |
8073 | { | |
8074 | struct dc_stream_state *new_stream = new_crtc_state->stream; | |
09aef2c4 | 8075 | struct mod_vrr_params vrr_params; |
e854194c | 8076 | struct mod_freesync_config config = new_crtc_state->freesync_config; |
09aef2c4 | 8077 | struct amdgpu_device *adev = dm->adev; |
585d450c | 8078 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); |
09aef2c4 | 8079 | unsigned long flags; |
e854194c MK |
8080 | |
8081 | if (!new_stream) | |
8082 | return; | |
8083 | ||
8084 | /* | |
8085 | * TODO: Determine why min/max totals and vrefresh can be 0 here. | |
8086 | * For now it's sufficient to just guard against these conditions. | |
8087 | */ | |
8088 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) | |
8089 | return; | |
8090 | ||
4a580877 | 8091 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
585d450c | 8092 | vrr_params = acrtc->dm_irq_params.vrr_params; |
09aef2c4 | 8093 | |
e854194c MK |
8094 | if (new_crtc_state->vrr_supported && |
8095 | config.min_refresh_in_uhz && | |
8096 | config.max_refresh_in_uhz) { | |
a85ba005 NC |
8097 | /* |
8098 | * if freesync compatible mode was set, config.state will be set | |
8099 | * in atomic check | |
8100 | */ | |
8101 | if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && | |
8102 | (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || | |
8103 | new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { | |
8104 | vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; | |
8105 | vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; | |
8106 | vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; | |
8107 | vrr_params.state = VRR_STATE_ACTIVE_FIXED; | |
8108 | } else { | |
8109 | config.state = new_crtc_state->base.vrr_enabled ? | |
8110 | VRR_STATE_ACTIVE_VARIABLE : | |
8111 | VRR_STATE_INACTIVE; | |
8112 | } | |
e854194c MK |
8113 | } else { |
8114 | config.state = VRR_STATE_UNSUPPORTED; | |
8115 | } | |
8116 | ||
8117 | mod_freesync_build_vrr_params(dm->freesync_module, | |
8118 | new_stream, | |
8119 | &config, &vrr_params); | |
8120 | ||
585d450c AP |
8121 | new_crtc_state->freesync_config = config; |
8122 | /* Copy state for access from DM IRQ handler */ | |
8123 | acrtc->dm_irq_params.freesync_config = config; | |
8124 | acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; | |
8125 | acrtc->dm_irq_params.vrr_params = vrr_params; | |
4a580877 | 8126 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
e854194c MK |
8127 | } |
8128 | ||
66b0c973 MK |
8129 | static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, |
8130 | struct dm_crtc_state *new_state) | |
8131 | { | |
6c5e25a0 DT |
8132 | bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); |
8133 | bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); | |
66b0c973 MK |
8134 | |
8135 | if (!old_vrr_active && new_vrr_active) { | |
8136 | /* Transition VRR inactive -> active: | |
8137 | * While VRR is active, we must not disable vblank irq, as a | |
8138 | * reenable after disable would compute bogus vblank/pflip | |
8139 | * timestamps if it likely happened inside display front-porch. | |
d2574c33 MK |
8140 | * |
8141 | * We also need vupdate irq for the actual core vblank handling | |
8142 | * at end of vblank. | |
66b0c973 | 8143 | */ |
6c5e25a0 | 8144 | WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); |
8799c0be | 8145 | WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); |
66b0c973 MK |
8146 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", |
8147 | __func__, new_state->base.crtc->base.id); | |
8148 | } else if (old_vrr_active && !new_vrr_active) { | |
8149 | /* Transition VRR active -> inactive: | |
8150 | * Allow vblank irq disable again for fixed refresh rate. | |
8151 | */ | |
6c5e25a0 | 8152 | WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); |
66b0c973 MK |
8153 | drm_crtc_vblank_put(new_state->base.crtc); |
8154 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", | |
8155 | __func__, new_state->base.crtc->base.id); | |
8156 | } | |
8157 | } | |
8158 | ||
8ad27806 NK |
8159 | static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) |
8160 | { | |
8161 | struct drm_plane *plane; | |
5760dcb9 | 8162 | struct drm_plane_state *old_plane_state; |
8ad27806 NK |
8163 | int i; |
8164 | ||
8165 | /* | |
8166 | * TODO: Make this per-stream so we don't issue redundant updates for | |
8167 | * commits with multiple streams. | |
8168 | */ | |
5760dcb9 | 8169 | for_each_old_plane_in_state(state, plane, old_plane_state, i) |
8ad27806 | 8170 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
8bf0d9cd | 8171 | amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); |
8ad27806 NK |
8172 | } |
8173 | ||
08da1821 HM |
8174 | static inline uint32_t get_mem_type(struct drm_framebuffer *fb) |
8175 | { | |
8176 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); | |
8177 | ||
8178 | return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; | |
8179 | } | |
8180 | ||
3be5262e | 8181 | static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, |
3ee6b26b AD |
8182 | struct drm_device *dev, |
8183 | struct amdgpu_display_manager *dm, | |
8184 | struct drm_crtc *pcrtc, | |
420cd472 | 8185 | bool wait_for_vblank) |
e7b07cee | 8186 | { |
ae67558b | 8187 | u32 i; |
d6ed6d0d | 8188 | u64 timestamp_ns = ktime_get_ns(); |
e7b07cee | 8189 | struct drm_plane *plane; |
0bc9706d | 8190 | struct drm_plane_state *old_plane_state, *new_plane_state; |
e7b07cee | 8191 | struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); |
0bc9706d LSL |
8192 | struct drm_crtc_state *new_pcrtc_state = |
8193 | drm_atomic_get_new_crtc_state(state, pcrtc); | |
8194 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); | |
44d09c6a HW |
8195 | struct dm_crtc_state *dm_old_crtc_state = |
8196 | to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); | |
74aa7bd4 | 8197 | int planes_count = 0, vpos, hpos; |
e7b07cee | 8198 | unsigned long flags; |
ae67558b | 8199 | u32 target_vblank, last_flip_vblank; |
6c5e25a0 | 8200 | bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); |
cc79950b | 8201 | bool cursor_update = false; |
74aa7bd4 | 8202 | bool pflip_present = false; |
d6ed6d0d | 8203 | bool dirty_rects_changed = false; |
bc7f670e DF |
8204 | struct { |
8205 | struct dc_surface_update surface_updates[MAX_SURFACES]; | |
8206 | struct dc_plane_info plane_infos[MAX_SURFACES]; | |
8207 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; | |
74aa7bd4 | 8208 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; |
bc7f670e | 8209 | struct dc_stream_update stream_update; |
74aa7bd4 | 8210 | } *bundle; |
bc7f670e | 8211 | |
74aa7bd4 | 8212 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); |
8a48b44c | 8213 | |
74aa7bd4 | 8214 | if (!bundle) { |
5d72e247 | 8215 | drm_err(dev, "Failed to allocate update bundle\n"); |
4b510503 NK |
8216 | goto cleanup; |
8217 | } | |
e7b07cee | 8218 | |
8ad27806 NK |
8219 | /* |
8220 | * Disable the cursor first if we're disabling all the planes. | |
8221 | * It'll remain on the screen after the planes are re-enabled | |
8222 | * if we don't. | |
8223 | */ | |
8224 | if (acrtc_state->active_planes == 0) | |
8225 | amdgpu_dm_commit_cursors(state); | |
8226 | ||
e7b07cee | 8227 | /* update planes when needed */ |
efc8278e | 8228 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { |
0bc9706d | 8229 | struct drm_crtc *crtc = new_plane_state->crtc; |
f5ba60fe | 8230 | struct drm_crtc_state *new_crtc_state; |
0bc9706d | 8231 | struct drm_framebuffer *fb = new_plane_state->fb; |
6eed95b0 | 8232 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; |
34bafd27 | 8233 | bool plane_needs_flip; |
c7af5f77 | 8234 | struct dc_plane_state *dc_plane; |
54d76575 | 8235 | struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); |
e7b07cee | 8236 | |
80c218d5 | 8237 | /* Cursor plane is handled after stream updates */ |
cc79950b MD |
8238 | if (plane->type == DRM_PLANE_TYPE_CURSOR) { |
8239 | if ((fb && crtc == pcrtc) || | |
8240 | (old_plane_state->fb && old_plane_state->crtc == pcrtc)) | |
8241 | cursor_update = true; | |
8242 | ||
e7b07cee | 8243 | continue; |
cc79950b | 8244 | } |
e7b07cee | 8245 | |
f5ba60fe DD |
8246 | if (!fb || !crtc || pcrtc != crtc) |
8247 | continue; | |
8248 | ||
8249 | new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); | |
8250 | if (!new_crtc_state->active) | |
e7b07cee HW |
8251 | continue; |
8252 | ||
bc7f670e | 8253 | dc_plane = dm_new_plane_state->dc_state; |
da5e1490 AP |
8254 | if (!dc_plane) |
8255 | continue; | |
e7b07cee | 8256 | |
74aa7bd4 | 8257 | bundle->surface_updates[planes_count].surface = dc_plane; |
bc7f670e | 8258 | if (new_pcrtc_state->color_mgmt_changed) { |
74aa7bd4 DF |
8259 | bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; |
8260 | bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; | |
44efb784 | 8261 | bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; |
bc7f670e | 8262 | } |
8a48b44c | 8263 | |
8bf0d9cd | 8264 | amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, |
695af5f9 | 8265 | &bundle->scaling_infos[planes_count]); |
8a48b44c | 8266 | |
695af5f9 NK |
8267 | bundle->surface_updates[planes_count].scaling_info = |
8268 | &bundle->scaling_infos[planes_count]; | |
8a48b44c | 8269 | |
f5031000 | 8270 | plane_needs_flip = old_plane_state->fb && new_plane_state->fb; |
8a48b44c | 8271 | |
f5031000 | 8272 | pflip_present = pflip_present || plane_needs_flip; |
8a48b44c | 8273 | |
f5031000 DF |
8274 | if (!plane_needs_flip) { |
8275 | planes_count += 1; | |
8276 | continue; | |
8277 | } | |
8a48b44c | 8278 | |
695af5f9 | 8279 | fill_dc_plane_info_and_addr( |
8ce5d842 | 8280 | dm->adev, new_plane_state, |
6eed95b0 | 8281 | afb->tiling_flags, |
695af5f9 | 8282 | &bundle->plane_infos[planes_count], |
87b7ebc2 | 8283 | &bundle->flip_addrs[planes_count].address, |
6eed95b0 | 8284 | afb->tmz_surface, false); |
87b7ebc2 | 8285 | |
9f07550b | 8286 | drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", |
87b7ebc2 RS |
8287 | new_plane_state->plane->index, |
8288 | bundle->plane_infos[planes_count].dcc.enable); | |
695af5f9 NK |
8289 | |
8290 | bundle->surface_updates[planes_count].plane_info = | |
8291 | &bundle->plane_infos[planes_count]; | |
8a48b44c | 8292 | |
679fc891 BL |
8293 | if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || |
8294 | acrtc_state->stream->link->replay_settings.replay_feature_enabled) { | |
d852871c HM |
8295 | fill_dc_dirty_rects(plane, old_plane_state, |
8296 | new_plane_state, new_crtc_state, | |
d6ed6d0d TC |
8297 | &bundle->flip_addrs[planes_count], |
8298 | &dirty_rects_changed); | |
8299 | ||
8300 | /* | |
8301 | * If the dirty regions changed, PSR-SU need to be disabled temporarily | |
8302 | * and enabled it again after dirty regions are stable to avoid video glitch. | |
8303 | * PSR-SU will be enabled in vblank_control_worker() if user pause the video | |
8304 | * during the PSR-SU was disabled. | |
8305 | */ | |
8306 | if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && | |
8307 | acrtc_attach->dm_irq_params.allow_psr_entry && | |
8308 | #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY | |
8309 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && | |
8310 | #endif | |
8311 | dirty_rects_changed) { | |
8312 | mutex_lock(&dm->dc_lock); | |
8313 | acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = | |
8314 | timestamp_ns; | |
8315 | if (acrtc_state->stream->link->psr_settings.psr_allow_active) | |
8316 | amdgpu_dm_psr_disable(acrtc_state->stream); | |
8317 | mutex_unlock(&dm->dc_lock); | |
8318 | } | |
8319 | } | |
7cc191ee | 8320 | |
caff0e66 NK |
8321 | /* |
8322 | * Only allow immediate flips for fast updates that don't | |
08da1821 HM |
8323 | * change memory domain, FB pitch, DCC state, rotation or |
8324 | * mirroring. | |
c1e18c44 SS |
8325 | * |
8326 | * dm_crtc_helper_atomic_check() only accepts async flips with | |
8327 | * fast updates. | |
caff0e66 | 8328 | */ |
c1e18c44 | 8329 | if (crtc->state->async_flip && |
a7c0cad0 HM |
8330 | (acrtc_state->update_type != UPDATE_TYPE_FAST || |
8331 | get_mem_type(old_plane_state->fb) != get_mem_type(fb))) | |
c1e18c44 SS |
8332 | drm_warn_once(state->dev, |
8333 | "[PLANE:%d:%s] async flip with non-fast update\n", | |
8334 | plane->base.id, plane->name); | |
a7c0cad0 | 8335 | |
f5031000 | 8336 | bundle->flip_addrs[planes_count].flip_immediate = |
4d85f45c | 8337 | crtc->state->async_flip && |
08da1821 HM |
8338 | acrtc_state->update_type == UPDATE_TYPE_FAST && |
8339 | get_mem_type(old_plane_state->fb) == get_mem_type(fb); | |
8a48b44c | 8340 | |
f5031000 DF |
8341 | timestamp_ns = ktime_get_ns(); |
8342 | bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); | |
8343 | bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; | |
8344 | bundle->surface_updates[planes_count].surface = dc_plane; | |
8a48b44c | 8345 | |
f5031000 DF |
8346 | if (!bundle->surface_updates[planes_count].surface) { |
8347 | DRM_ERROR("No surface for CRTC: id=%d\n", | |
8348 | acrtc_attach->crtc_id); | |
8349 | continue; | |
bc7f670e DF |
8350 | } |
8351 | ||
f5031000 DF |
8352 | if (plane == pcrtc->primary) |
8353 | update_freesync_state_on_stream( | |
8354 | dm, | |
8355 | acrtc_state, | |
8356 | acrtc_state->stream, | |
8357 | dc_plane, | |
8358 | bundle->flip_addrs[planes_count].flip_timestamp_in_us); | |
bc7f670e | 8359 | |
9f07550b | 8360 | drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", |
f5031000 DF |
8361 | __func__, |
8362 | bundle->flip_addrs[planes_count].address.grph.addr.high_part, | |
8363 | bundle->flip_addrs[planes_count].address.grph.addr.low_part); | |
bc7f670e DF |
8364 | |
8365 | planes_count += 1; | |
8366 | ||
8a48b44c DF |
8367 | } |
8368 | ||
74aa7bd4 | 8369 | if (pflip_present) { |
634092b1 MK |
8370 | if (!vrr_active) { |
8371 | /* Use old throttling in non-vrr fixed refresh rate mode | |
8372 | * to keep flip scheduling based on target vblank counts | |
8373 | * working in a backwards compatible way, e.g., for | |
8374 | * clients using the GLX_OML_sync_control extension or | |
8375 | * DRI3/Present extension with defined target_msc. | |
8376 | */ | |
e3eff4b5 | 8377 | last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); |
c82eddf8 | 8378 | } else { |
634092b1 MK |
8379 | /* For variable refresh rate mode only: |
8380 | * Get vblank of last completed flip to avoid > 1 vrr | |
8381 | * flips per video frame by use of throttling, but allow | |
8382 | * flip programming anywhere in the possibly large | |
8383 | * variable vrr vblank interval for fine-grained flip | |
8384 | * timing control and more opportunity to avoid stutter | |
8385 | * on late submission of flips. | |
8386 | */ | |
8387 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
5d1c59c4 | 8388 | last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; |
634092b1 MK |
8389 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
8390 | } | |
8391 | ||
fdd1fe57 | 8392 | target_vblank = last_flip_vblank + wait_for_vblank; |
8a48b44c DF |
8393 | |
8394 | /* | |
8395 | * Wait until we're out of the vertical blank period before the one | |
8396 | * targeted by the flip | |
8397 | */ | |
8398 | while ((acrtc_attach->enabled && | |
8399 | (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, | |
8400 | 0, &vpos, &hpos, NULL, | |
8401 | NULL, &pcrtc->hwmode) | |
8402 | & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == | |
8403 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && | |
8404 | (int)(target_vblank - | |
e3eff4b5 | 8405 | amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { |
8a48b44c DF |
8406 | usleep_range(1000, 1100); |
8407 | } | |
8408 | ||
8fe684e9 NK |
8409 | /** |
8410 | * Prepare the flip event for the pageflip interrupt to handle. | |
8411 | * | |
8412 | * This only works in the case where we've already turned on the | |
8413 | * appropriate hardware blocks (eg. HUBP) so in the transition case | |
8414 | * from 0 -> n planes we have to skip a hardware generated event | |
8415 | * and rely on sending it from software. | |
8416 | */ | |
8417 | if (acrtc_attach->base.state->event && | |
10a36226 | 8418 | acrtc_state->active_planes > 0) { |
8a48b44c DF |
8419 | drm_crtc_vblank_get(pcrtc); |
8420 | ||
8421 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
8422 | ||
8423 | WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); | |
8424 | prepare_flip_isr(acrtc_attach); | |
8425 | ||
8426 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
8427 | } | |
8428 | ||
8429 | if (acrtc_state->stream) { | |
8a48b44c | 8430 | if (acrtc_state->freesync_vrr_info_changed) |
74aa7bd4 | 8431 | bundle->stream_update.vrr_infopacket = |
8a48b44c | 8432 | &acrtc_state->stream->vrr_infopacket; |
e7b07cee | 8433 | } |
cc79950b MD |
8434 | } else if (cursor_update && acrtc_state->active_planes > 0 && |
8435 | acrtc_attach->base.state->event) { | |
8436 | drm_crtc_vblank_get(pcrtc); | |
8437 | ||
8438 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
8439 | ||
8440 | acrtc_attach->event = acrtc_attach->base.state->event; | |
8441 | acrtc_attach->base.state->event = NULL; | |
8442 | ||
8443 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
e7b07cee HW |
8444 | } |
8445 | ||
bc92c065 | 8446 | /* Update the planes if changed or disable if we don't have any. */ |
ed9656fb ES |
8447 | if ((planes_count || acrtc_state->active_planes == 0) && |
8448 | acrtc_state->stream) { | |
58aa1c50 NK |
8449 | /* |
8450 | * If PSR or idle optimizations are enabled then flush out | |
8451 | * any pending work before hardware programming. | |
8452 | */ | |
06dd1888 NK |
8453 | if (dm->vblank_control_workqueue) |
8454 | flush_workqueue(dm->vblank_control_workqueue); | |
58aa1c50 | 8455 | |
b6e881c9 | 8456 | bundle->stream_update.stream = acrtc_state->stream; |
bc7f670e | 8457 | if (new_pcrtc_state->mode_changed) { |
74aa7bd4 DF |
8458 | bundle->stream_update.src = acrtc_state->stream->src; |
8459 | bundle->stream_update.dst = acrtc_state->stream->dst; | |
e7b07cee HW |
8460 | } |
8461 | ||
cf020d49 NK |
8462 | if (new_pcrtc_state->color_mgmt_changed) { |
8463 | /* | |
8464 | * TODO: This isn't fully correct since we've actually | |
8465 | * already modified the stream in place. | |
8466 | */ | |
8467 | bundle->stream_update.gamut_remap = | |
8468 | &acrtc_state->stream->gamut_remap_matrix; | |
8469 | bundle->stream_update.output_csc_transform = | |
8470 | &acrtc_state->stream->csc_color_matrix; | |
8471 | bundle->stream_update.out_transfer_func = | |
8472 | acrtc_state->stream->out_transfer_func; | |
8473 | } | |
bc7f670e | 8474 | |
8a48b44c | 8475 | acrtc_state->stream->abm_level = acrtc_state->abm_level; |
bc7f670e | 8476 | if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) |
74aa7bd4 | 8477 | bundle->stream_update.abm_level = &acrtc_state->abm_level; |
44d09c6a | 8478 | |
f3081166 TC |
8479 | mutex_lock(&dm->dc_lock); |
8480 | if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && | |
8481 | acrtc_state->stream->link->psr_settings.psr_allow_active) | |
8482 | amdgpu_dm_psr_disable(acrtc_state->stream); | |
8483 | mutex_unlock(&dm->dc_lock); | |
8484 | ||
e63e2491 EB |
8485 | /* |
8486 | * If FreeSync state on the stream has changed then we need to | |
8487 | * re-adjust the min/max bounds now that DC doesn't handle this | |
8488 | * as part of commit. | |
8489 | */ | |
a85ba005 | 8490 | if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { |
e63e2491 EB |
8491 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); |
8492 | dc_stream_adjust_vmin_vmax( | |
8493 | dm->dc, acrtc_state->stream, | |
585d450c | 8494 | &acrtc_attach->dm_irq_params.vrr_params.adjust); |
e63e2491 EB |
8495 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
8496 | } | |
bc7f670e | 8497 | mutex_lock(&dm->dc_lock); |
81f743a0 RS |
8498 | update_planes_and_stream_adapter(dm->dc, |
8499 | acrtc_state->update_type, | |
8500 | planes_count, | |
8501 | acrtc_state->stream, | |
8502 | &bundle->stream_update, | |
8503 | bundle->surface_updates); | |
8c322309 | 8504 | |
8fe684e9 NK |
8505 | /** |
8506 | * Enable or disable the interrupts on the backend. | |
8507 | * | |
8508 | * Most pipes are put into power gating when unused. | |
8509 | * | |
8510 | * When power gating is enabled on a pipe we lose the | |
8511 | * interrupt enablement state when power gating is disabled. | |
8512 | * | |
8513 | * So we need to update the IRQ control state in hardware | |
8514 | * whenever the pipe turns on (since it could be previously | |
8515 | * power gated) or off (since some pipes can't be power gated | |
8516 | * on some ASICs). | |
8517 | */ | |
8518 | if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) | |
1348969a LT |
8519 | dm_update_pflip_irq_state(drm_to_adev(dev), |
8520 | acrtc_attach); | |
8fe684e9 | 8521 | |
8c322309 | 8522 | if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && |
1cfbbdde | 8523 | acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && |
d1ebfdd8 | 8524 | !acrtc_state->stream->link->psr_settings.psr_feature_enabled) |
8c322309 | 8525 | amdgpu_dm_link_setup_psr(acrtc_state->stream); |
58aa1c50 NK |
8526 | |
8527 | /* Decrement skip count when PSR is enabled and we're doing fast updates. */ | |
8528 | if (acrtc_state->update_type == UPDATE_TYPE_FAST && | |
8529 | acrtc_state->stream->link->psr_settings.psr_feature_enabled) { | |
8530 | struct amdgpu_dm_connector *aconn = | |
8531 | (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; | |
1a365683 RL |
8532 | |
8533 | if (aconn->psr_skip_count > 0) | |
8534 | aconn->psr_skip_count--; | |
58aa1c50 NK |
8535 | |
8536 | /* Allow PSR when skip count is 0. */ | |
8537 | acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; | |
7cc191ee LL |
8538 | |
8539 | /* | |
8540 | * If sink supports PSR SU, there is no need to rely on | |
8541 | * a vblank event disable request to enable PSR. PSR SU | |
8542 | * can be enabled immediately once OS demonstrates an | |
8543 | * adequate number of fast atomic commits to notify KMD | |
8544 | * of update events. See `vblank_control_worker()`. | |
8545 | */ | |
8546 | if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && | |
8547 | acrtc_attach->dm_irq_params.allow_psr_entry && | |
c0459bdd AL |
8548 | #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY |
8549 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && | |
8550 | #endif | |
d6ed6d0d TC |
8551 | !acrtc_state->stream->link->psr_settings.psr_allow_active && |
8552 | (timestamp_ns - | |
8553 | acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > | |
8554 | 500000000) | |
7cc191ee | 8555 | amdgpu_dm_psr_enable(acrtc_state->stream); |
58aa1c50 NK |
8556 | } else { |
8557 | acrtc_attach->dm_irq_params.allow_psr_entry = false; | |
8c322309 RL |
8558 | } |
8559 | ||
bc7f670e | 8560 | mutex_unlock(&dm->dc_lock); |
e7b07cee | 8561 | } |
4b510503 | 8562 | |
8ad27806 NK |
8563 | /* |
8564 | * Update cursor state *after* programming all the planes. | |
8565 | * This avoids redundant programming in the case where we're going | |
8566 | * to be disabling a single plane - those pipes are being disabled. | |
8567 | */ | |
8568 | if (acrtc_state->active_planes) | |
8569 | amdgpu_dm_commit_cursors(state); | |
80c218d5 | 8570 | |
4b510503 | 8571 | cleanup: |
74aa7bd4 | 8572 | kfree(bundle); |
e7b07cee HW |
8573 | } |
8574 | ||
6ce8f316 NK |
8575 | static void amdgpu_dm_commit_audio(struct drm_device *dev, |
8576 | struct drm_atomic_state *state) | |
8577 | { | |
1348969a | 8578 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
8579 | struct amdgpu_dm_connector *aconnector; |
8580 | struct drm_connector *connector; | |
8581 | struct drm_connector_state *old_con_state, *new_con_state; | |
8582 | struct drm_crtc_state *new_crtc_state; | |
8583 | struct dm_crtc_state *new_dm_crtc_state; | |
8584 | const struct dc_stream_status *status; | |
8585 | int i, inst; | |
8586 | ||
8587 | /* Notify device removals. */ | |
8588 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
8589 | if (old_con_state->crtc != new_con_state->crtc) { | |
8590 | /* CRTC changes require notification. */ | |
8591 | goto notify; | |
8592 | } | |
8593 | ||
8594 | if (!new_con_state->crtc) | |
8595 | continue; | |
8596 | ||
8597 | new_crtc_state = drm_atomic_get_new_crtc_state( | |
8598 | state, new_con_state->crtc); | |
8599 | ||
8600 | if (!new_crtc_state) | |
8601 | continue; | |
8602 | ||
8603 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
8604 | continue; | |
8605 | ||
7db7ade2 HW |
8606 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
8607 | continue; | |
8608 | ||
3335a135 | 8609 | notify: |
6ce8f316 NK |
8610 | aconnector = to_amdgpu_dm_connector(connector); |
8611 | ||
8612 | mutex_lock(&adev->dm.audio_lock); | |
8613 | inst = aconnector->audio_inst; | |
8614 | aconnector->audio_inst = -1; | |
8615 | mutex_unlock(&adev->dm.audio_lock); | |
8616 | ||
8617 | amdgpu_dm_audio_eld_notify(adev, inst); | |
8618 | } | |
8619 | ||
8620 | /* Notify audio device additions. */ | |
8621 | for_each_new_connector_in_state(state, connector, new_con_state, i) { | |
8622 | if (!new_con_state->crtc) | |
8623 | continue; | |
8624 | ||
8625 | new_crtc_state = drm_atomic_get_new_crtc_state( | |
8626 | state, new_con_state->crtc); | |
8627 | ||
8628 | if (!new_crtc_state) | |
8629 | continue; | |
8630 | ||
8631 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
8632 | continue; | |
8633 | ||
8634 | new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); | |
8635 | if (!new_dm_crtc_state->stream) | |
8636 | continue; | |
8637 | ||
8638 | status = dc_stream_get_status(new_dm_crtc_state->stream); | |
8639 | if (!status) | |
8640 | continue; | |
8641 | ||
7db7ade2 HW |
8642 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
8643 | continue; | |
8644 | ||
6ce8f316 NK |
8645 | aconnector = to_amdgpu_dm_connector(connector); |
8646 | ||
8647 | mutex_lock(&adev->dm.audio_lock); | |
8648 | inst = status->audio_inst; | |
8649 | aconnector->audio_inst = inst; | |
8650 | mutex_unlock(&adev->dm.audio_lock); | |
8651 | ||
8652 | amdgpu_dm_audio_eld_notify(adev, inst); | |
8653 | } | |
8654 | } | |
8655 | ||
1f6010a9 | 8656 | /* |
27b3f4fc LSL |
8657 | * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC |
8658 | * @crtc_state: the DRM CRTC state | |
8659 | * @stream_state: the DC stream state. | |
8660 | * | |
8661 | * Copy the mirrored transient state flags from DRM, to DC. It is used to bring | |
8662 | * a dc_stream_state's flags in sync with a drm_crtc_state's flags. | |
8663 | */ | |
8664 | static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, | |
8665 | struct dc_stream_state *stream_state) | |
8666 | { | |
b9952f93 | 8667 | stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); |
27b3f4fc | 8668 | } |
e7b07cee | 8669 | |
c81e13b9 AH |
8670 | static void dm_clear_writeback(struct amdgpu_display_manager *dm, |
8671 | struct dm_crtc_state *crtc_state) | |
8672 | { | |
8673 | dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); | |
8674 | } | |
8675 | ||
fff7b95a AL |
8676 | static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, |
8677 | struct dc_state *dc_state) | |
e7b07cee HW |
8678 | { |
8679 | struct drm_device *dev = state->dev; | |
1348969a | 8680 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee | 8681 | struct amdgpu_display_manager *dm = &adev->dm; |
5cc6dcbd | 8682 | struct drm_crtc *crtc; |
0bc9706d | 8683 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
54d76575 | 8684 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
c81e13b9 AH |
8685 | struct drm_connector_state *old_con_state; |
8686 | struct drm_connector *connector; | |
6ee90e88 | 8687 | bool mode_set_reset_required = false; |
fff7b95a | 8688 | u32 i; |
e7b07cee | 8689 | |
c81e13b9 AH |
8690 | /* Disable writeback */ |
8691 | for_each_old_connector_in_state(state, connector, old_con_state, i) { | |
8692 | struct dm_connector_state *dm_old_con_state; | |
8693 | struct amdgpu_crtc *acrtc; | |
8694 | ||
8695 | if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) | |
8696 | continue; | |
8697 | ||
8698 | old_crtc_state = NULL; | |
8699 | ||
8700 | dm_old_con_state = to_dm_connector_state(old_con_state); | |
8701 | if (!dm_old_con_state->base.crtc) | |
8702 | continue; | |
8703 | ||
8704 | acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); | |
8705 | if (acrtc) | |
8706 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); | |
8707 | ||
f872e2f5 AH |
8708 | if (!acrtc->wb_enabled) |
8709 | continue; | |
8710 | ||
c81e13b9 AH |
8711 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
8712 | ||
8713 | dm_clear_writeback(dm, dm_old_crtc_state); | |
f872e2f5 | 8714 | acrtc->wb_enabled = false; |
c81e13b9 AH |
8715 | } |
8716 | ||
c82eddf8 SS |
8717 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, |
8718 | new_crtc_state, i) { | |
6d90a208 AP |
8719 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
8720 | ||
8721 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
8722 | ||
8723 | if (old_crtc_state->active && | |
8724 | (!new_crtc_state->active || | |
8725 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
8726 | manage_dm_interrupts(adev, acrtc, false); | |
8727 | dc_stream_release(dm_old_crtc_state->stream); | |
8728 | } | |
8729 | } | |
8730 | ||
8976f73b RS |
8731 | drm_atomic_helper_calc_timestamping_constants(state); |
8732 | ||
e7b07cee | 8733 | /* update changed items */ |
0bc9706d | 8734 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
e7b07cee | 8735 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 8736 | |
54d76575 LSL |
8737 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
8738 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
e7b07cee | 8739 | |
9f07550b | 8740 | drm_dbg_state(state->dev, |
c82eddf8 | 8741 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", |
e7b07cee | 8742 | acrtc->crtc_id, |
0bc9706d LSL |
8743 | new_crtc_state->enable, |
8744 | new_crtc_state->active, | |
8745 | new_crtc_state->planes_changed, | |
8746 | new_crtc_state->mode_changed, | |
8747 | new_crtc_state->active_changed, | |
8748 | new_crtc_state->connectors_changed); | |
e7b07cee | 8749 | |
5c68c652 VL |
8750 | /* Disable cursor if disabling crtc */ |
8751 | if (old_crtc_state->active && !new_crtc_state->active) { | |
8752 | struct dc_cursor_position position; | |
8753 | ||
8754 | memset(&position, 0, sizeof(position)); | |
8755 | mutex_lock(&dm->dc_lock); | |
8756 | dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); | |
8757 | mutex_unlock(&dm->dc_lock); | |
8758 | } | |
8759 | ||
27b3f4fc LSL |
8760 | /* Copy all transient state flags into dc state */ |
8761 | if (dm_new_crtc_state->stream) { | |
8762 | amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, | |
8763 | dm_new_crtc_state->stream); | |
8764 | } | |
8765 | ||
e7b07cee HW |
8766 | /* handles headless hotplug case, updating new_state and |
8767 | * aconnector as needed | |
8768 | */ | |
8769 | ||
6c5e25a0 | 8770 | if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { |
e7b07cee | 8771 | |
4711c033 | 8772 | DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee | 8773 | |
54d76575 | 8774 | if (!dm_new_crtc_state->stream) { |
e7b07cee | 8775 | /* |
b830ebc9 HW |
8776 | * this could happen because of issues with |
8777 | * userspace notifications delivery. | |
8778 | * In this case userspace tries to set mode on | |
1f6010a9 DF |
8779 | * display which is disconnected in fact. |
8780 | * dc_sink is NULL in this case on aconnector. | |
b830ebc9 HW |
8781 | * We expect reset mode will come soon. |
8782 | * | |
8783 | * This can also happen when unplug is done | |
8784 | * during resume sequence ended | |
8785 | * | |
8786 | * In this case, we want to pretend we still | |
8787 | * have a sink to keep the pipe running so that | |
8788 | * hw state is consistent with the sw state | |
8789 | */ | |
f1ad2f5e | 8790 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", |
e7b07cee HW |
8791 | __func__, acrtc->base.base.id); |
8792 | continue; | |
8793 | } | |
8794 | ||
54d76575 LSL |
8795 | if (dm_old_crtc_state->stream) |
8796 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); | |
e7b07cee | 8797 | |
97028037 LP |
8798 | pm_runtime_get_noresume(dev->dev); |
8799 | ||
e7b07cee | 8800 | acrtc->enabled = true; |
0bc9706d LSL |
8801 | acrtc->hw_mode = new_crtc_state->mode; |
8802 | crtc->hwmode = new_crtc_state->mode; | |
6ee90e88 | 8803 | mode_set_reset_required = true; |
0bc9706d | 8804 | } else if (modereset_required(new_crtc_state)) { |
4711c033 | 8805 | DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee | 8806 | /* i.e. reset mode */ |
6ee90e88 | 8807 | if (dm_old_crtc_state->stream) |
54d76575 | 8808 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); |
a85ba005 | 8809 | |
6ee90e88 | 8810 | mode_set_reset_required = true; |
e7b07cee HW |
8811 | } |
8812 | } /* for_each_crtc_in_state() */ | |
8813 | ||
fff7b95a AL |
8814 | /* if there mode set or reset, disable eDP PSR */ |
8815 | if (mode_set_reset_required) { | |
8816 | if (dm->vblank_control_workqueue) | |
8817 | flush_workqueue(dm->vblank_control_workqueue); | |
cae5c1ab | 8818 | |
fff7b95a AL |
8819 | amdgpu_dm_psr_disable_all(dm); |
8820 | } | |
6ee90e88 | 8821 | |
fff7b95a AL |
8822 | dm_enable_per_frame_crtc_master_sync(dc_state); |
8823 | mutex_lock(&dm->dc_lock); | |
8824 | WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); | |
f3106c94 | 8825 | |
fff7b95a AL |
8826 | /* Allow idle optimization when vblank count is 0 for display off */ |
8827 | if (dm->active_vblank_irq_count == 0) | |
8828 | dc_allow_idle_optimizations(dm->dc, true); | |
8829 | mutex_unlock(&dm->dc_lock); | |
fe8858bb | 8830 | |
0bc9706d | 8831 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 8832 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 8833 | |
54d76575 | 8834 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 8835 | |
54d76575 | 8836 | if (dm_new_crtc_state->stream != NULL) { |
e7b07cee | 8837 | const struct dc_stream_status *status = |
54d76575 | 8838 | dc_stream_get_status(dm_new_crtc_state->stream); |
e7b07cee | 8839 | |
eb3dc897 | 8840 | if (!status) |
09f609c3 LL |
8841 | status = dc_stream_get_status_from_state(dc_state, |
8842 | dm_new_crtc_state->stream); | |
e7b07cee | 8843 | if (!status) |
5d72e247 HM |
8844 | drm_err(dev, |
8845 | "got no status for stream %p on acrtc%p\n", | |
8846 | dm_new_crtc_state->stream, acrtc); | |
e7b07cee HW |
8847 | else |
8848 | acrtc->otg_inst = status->primary_otg_inst; | |
8849 | } | |
8850 | } | |
fff7b95a AL |
8851 | } |
8852 | ||
c81e13b9 AH |
8853 | static void dm_set_writeback(struct amdgpu_display_manager *dm, |
8854 | struct dm_crtc_state *crtc_state, | |
8855 | struct drm_connector *connector, | |
8856 | struct drm_connector_state *new_con_state) | |
8857 | { | |
8858 | struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); | |
fdf43d25 | 8859 | struct amdgpu_device *adev = dm->adev; |
c81e13b9 AH |
8860 | struct amdgpu_crtc *acrtc; |
8861 | struct dc_writeback_info *wb_info; | |
8862 | struct pipe_ctx *pipe = NULL; | |
8863 | struct amdgpu_framebuffer *afb; | |
8864 | int i = 0; | |
8865 | ||
8866 | wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); | |
8867 | if (!wb_info) { | |
8868 | DRM_ERROR("Failed to allocate wb_info\n"); | |
8869 | return; | |
8870 | } | |
8871 | ||
8872 | acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); | |
8873 | if (!acrtc) { | |
8874 | DRM_ERROR("no amdgpu_crtc found\n"); | |
8875 | return; | |
8876 | } | |
8877 | ||
8878 | afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); | |
8879 | if (!afb) { | |
8880 | DRM_ERROR("No amdgpu_framebuffer found\n"); | |
8881 | return; | |
8882 | } | |
8883 | ||
8884 | for (i = 0; i < MAX_PIPES; i++) { | |
8885 | if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { | |
8886 | pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; | |
8887 | break; | |
8888 | } | |
8889 | } | |
8890 | ||
8891 | /* fill in wb_info */ | |
8892 | wb_info->wb_enabled = true; | |
8893 | ||
8894 | wb_info->dwb_pipe_inst = 0; | |
8895 | wb_info->dwb_params.dwbscl_black_color = 0; | |
8896 | wb_info->dwb_params.hdr_mult = 0x1F000; | |
8897 | wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; | |
8898 | wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; | |
8899 | wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; | |
8900 | wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; | |
8901 | ||
8902 | /* width & height from crtc */ | |
8903 | wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; | |
8904 | wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; | |
8905 | wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; | |
8906 | wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; | |
8907 | ||
8908 | wb_info->dwb_params.cnv_params.crop_en = false; | |
8909 | wb_info->dwb_params.stereo_params.stereo_enabled = false; | |
8910 | ||
8911 | wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits | |
8912 | wb_info->dwb_params.cnv_params.out_min_pix_val = 0; | |
8913 | wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; | |
8914 | wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; | |
8915 | ||
8916 | wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; | |
8917 | ||
8918 | wb_info->dwb_params.capture_rate = dwb_capture_rate_0; | |
8919 | ||
8920 | wb_info->dwb_params.scaler_taps.h_taps = 4; | |
8921 | wb_info->dwb_params.scaler_taps.v_taps = 4; | |
8922 | wb_info->dwb_params.scaler_taps.h_taps_c = 2; | |
8923 | wb_info->dwb_params.scaler_taps.v_taps_c = 2; | |
8924 | wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; | |
8925 | ||
8926 | wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; | |
8927 | wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; | |
8928 | ||
8929 | for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { | |
8930 | wb_info->mcif_buf_params.luma_address[i] = afb->address; | |
8931 | wb_info->mcif_buf_params.chroma_address[i] = 0; | |
8932 | } | |
8933 | ||
8934 | wb_info->mcif_buf_params.p_vmid = 1; | |
fdf43d25 AH |
8935 | if (adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0)) { |
8936 | wb_info->mcif_warmup_params.start_address.quad_part = afb->address; | |
8937 | wb_info->mcif_warmup_params.region_size = | |
8938 | wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; | |
8939 | } | |
c81e13b9 AH |
8940 | wb_info->mcif_warmup_params.p_vmid = 1; |
8941 | wb_info->writeback_source_plane = pipe->plane_state; | |
8942 | ||
8943 | dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); | |
8944 | ||
8945 | acrtc->wb_pending = true; | |
8946 | acrtc->wb_conn = wb_conn; | |
8947 | drm_writeback_queue_job(wb_conn, new_con_state); | |
8948 | } | |
8949 | ||
fff7b95a AL |
8950 | /** |
8951 | * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. | |
8952 | * @state: The atomic state to commit | |
8953 | * | |
8954 | * This will tell DC to commit the constructed DC state from atomic_check, | |
8955 | * programming the hardware. Any failures here implies a hardware failure, since | |
8956 | * atomic check should have filtered anything non-kosher. | |
8957 | */ | |
8958 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) | |
8959 | { | |
8960 | struct drm_device *dev = state->dev; | |
8961 | struct amdgpu_device *adev = drm_to_adev(dev); | |
8962 | struct amdgpu_display_manager *dm = &adev->dm; | |
8963 | struct dm_atomic_state *dm_state; | |
8964 | struct dc_state *dc_state = NULL; | |
8965 | u32 i, j; | |
8966 | struct drm_crtc *crtc; | |
8967 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; | |
8968 | unsigned long flags; | |
8969 | bool wait_for_vblank = true; | |
8970 | struct drm_connector *connector; | |
8971 | struct drm_connector_state *old_con_state, *new_con_state; | |
8972 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; | |
8973 | int crtc_disable_count = 0; | |
8974 | ||
8975 | trace_amdgpu_dm_atomic_commit_tail_begin(state); | |
8976 | ||
06b1661e QZ |
8977 | if (dm->dc->caps.ips_support) { |
8978 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
8979 | if (new_con_state->crtc && | |
8980 | new_con_state->crtc->state->active && | |
8981 | drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) { | |
8982 | dc_dmub_srv_exit_low_power_state(dm->dc); | |
8983 | break; | |
8984 | } | |
8985 | } | |
8986 | } | |
8987 | ||
fff7b95a AL |
8988 | drm_atomic_helper_update_legacy_modeset_state(dev, state); |
8989 | drm_dp_mst_atomic_wait_for_dependencies(state); | |
8990 | ||
8991 | dm_state = dm_atomic_get_new_state(state); | |
8992 | if (dm_state && dm_state->context) { | |
8993 | dc_state = dm_state->context; | |
8994 | amdgpu_dm_commit_streams(state, dc_state); | |
8995 | } | |
8996 | ||
0c8620d6 BL |
8997 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
8998 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
8999 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
7db7ade2 HW |
9000 | struct amdgpu_dm_connector *aconnector; |
9001 | ||
9002 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) | |
9003 | continue; | |
9004 | ||
9005 | aconnector = to_amdgpu_dm_connector(connector); | |
0c8620d6 | 9006 | |
3cf7cd3f HW |
9007 | if (!adev->dm.hdcp_workqueue) |
9008 | continue; | |
9009 | ||
e8fd3eeb | 9010 | pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); |
9011 | ||
9012 | if (!connector) | |
9013 | continue; | |
9014 | ||
9015 | pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", | |
9016 | connector->index, connector->status, connector->dpms); | |
9017 | pr_debug("[HDCP_DM] state protection old: %x new: %x\n", | |
9018 | old_con_state->content_protection, new_con_state->content_protection); | |
9019 | ||
9020 | if (aconnector->dc_sink) { | |
9021 | if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && | |
9022 | aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { | |
9023 | pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", | |
9024 | aconnector->dc_sink->edid_caps.display_name); | |
9025 | } | |
9026 | } | |
9027 | ||
0c8620d6 | 9028 | new_crtc_state = NULL; |
e8fd3eeb | 9029 | old_crtc_state = NULL; |
0c8620d6 | 9030 | |
e8fd3eeb | 9031 | if (acrtc) { |
0c8620d6 | 9032 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
e8fd3eeb | 9033 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
9034 | } | |
9035 | ||
9036 | if (old_crtc_state) | |
9037 | pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
9038 | old_crtc_state->enable, | |
9039 | old_crtc_state->active, | |
9040 | old_crtc_state->mode_changed, | |
9041 | old_crtc_state->active_changed, | |
9042 | old_crtc_state->connectors_changed); | |
9043 | ||
9044 | if (new_crtc_state) | |
9045 | pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
9046 | new_crtc_state->enable, | |
9047 | new_crtc_state->active, | |
9048 | new_crtc_state->mode_changed, | |
9049 | new_crtc_state->active_changed, | |
9050 | new_crtc_state->connectors_changed); | |
9051 | } | |
9052 | ||
9053 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
9054 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
9055 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
9056 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
9057 | ||
3cf7cd3f HW |
9058 | if (!adev->dm.hdcp_workqueue) |
9059 | continue; | |
9060 | ||
e8fd3eeb | 9061 | new_crtc_state = NULL; |
9062 | old_crtc_state = NULL; | |
9063 | ||
9064 | if (acrtc) { | |
9065 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); | |
9066 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); | |
9067 | } | |
0c8620d6 BL |
9068 | |
9069 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
9070 | ||
9071 | if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && | |
9072 | connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { | |
9073 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); | |
9074 | new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
97f6c917 | 9075 | dm_new_con_state->update_hdcp = true; |
0c8620d6 BL |
9076 | continue; |
9077 | } | |
9078 | ||
e8fd3eeb | 9079 | if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, |
9080 | old_con_state, connector, adev->dm.hdcp_workqueue)) { | |
82986fd6 | 9081 | /* when display is unplugged from mst hub, connctor will |
9082 | * be destroyed within dm_dp_mst_connector_destroy. connector | |
9083 | * hdcp perperties, like type, undesired, desired, enabled, | |
9084 | * will be lost. So, save hdcp properties into hdcp_work within | |
9085 | * amdgpu_dm_atomic_commit_tail. if the same display is | |
9086 | * plugged back with same display index, its hdcp properties | |
9087 | * will be retrieved from hdcp_work within dm_dp_mst_get_modes | |
9088 | */ | |
9089 | ||
e8fd3eeb | 9090 | bool enable_encryption = false; |
9091 | ||
9092 | if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) | |
9093 | enable_encryption = true; | |
9094 | ||
82986fd6 | 9095 | if (aconnector->dc_link && aconnector->dc_sink && |
9096 | aconnector->dc_link->type == dc_connection_mst_branch) { | |
9097 | struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; | |
9098 | struct hdcp_workqueue *hdcp_w = | |
9099 | &hdcp_work[aconnector->dc_link->link_index]; | |
9100 | ||
9101 | hdcp_w->hdcp_content_type[connector->index] = | |
9102 | new_con_state->hdcp_content_type; | |
9103 | hdcp_w->content_protection[connector->index] = | |
9104 | new_con_state->content_protection; | |
9105 | } | |
9106 | ||
e8fd3eeb | 9107 | if (new_crtc_state && new_crtc_state->mode_changed && |
9108 | new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) | |
9109 | enable_encryption = true; | |
9110 | ||
9111 | DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); | |
9112 | ||
b1abe558 BL |
9113 | hdcp_update_display( |
9114 | adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, | |
e8fd3eeb | 9115 | new_con_state->hdcp_content_type, enable_encryption); |
9116 | } | |
0c8620d6 | 9117 | } |
e7b07cee | 9118 | |
02d6a6fc | 9119 | /* Handle connector state changes */ |
c2cea706 | 9120 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
9121 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
9122 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); | |
9123 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
135fd1b3 | 9124 | struct dc_surface_update *dummy_updates; |
19afd799 | 9125 | struct dc_stream_update stream_update; |
b232d4ed | 9126 | struct dc_info_packet hdr_packet; |
e7b07cee | 9127 | struct dc_stream_status *status = NULL; |
b232d4ed | 9128 | bool abm_changed, hdr_changed, scaling_changed; |
e7b07cee | 9129 | |
19afd799 NC |
9130 | memset(&stream_update, 0, sizeof(stream_update)); |
9131 | ||
44d09c6a | 9132 | if (acrtc) { |
0bc9706d | 9133 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
44d09c6a HW |
9134 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
9135 | } | |
0bc9706d | 9136 | |
e7b07cee | 9137 | /* Skip any modesets/resets */ |
0bc9706d | 9138 | if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) |
e7b07cee HW |
9139 | continue; |
9140 | ||
54d76575 | 9141 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
c1ee92f9 DF |
9142 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
9143 | ||
b232d4ed NK |
9144 | scaling_changed = is_scaling_state_different(dm_new_con_state, |
9145 | dm_old_con_state); | |
9146 | ||
9147 | abm_changed = dm_new_crtc_state->abm_level != | |
9148 | dm_old_crtc_state->abm_level; | |
9149 | ||
9150 | hdr_changed = | |
72921cdf | 9151 | !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); |
b232d4ed NK |
9152 | |
9153 | if (!scaling_changed && !abm_changed && !hdr_changed) | |
c1ee92f9 | 9154 | continue; |
e7b07cee | 9155 | |
b6e881c9 | 9156 | stream_update.stream = dm_new_crtc_state->stream; |
b232d4ed | 9157 | if (scaling_changed) { |
02d6a6fc | 9158 | update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, |
b6e881c9 | 9159 | dm_new_con_state, dm_new_crtc_state->stream); |
e7b07cee | 9160 | |
02d6a6fc DF |
9161 | stream_update.src = dm_new_crtc_state->stream->src; |
9162 | stream_update.dst = dm_new_crtc_state->stream->dst; | |
9163 | } | |
9164 | ||
b232d4ed | 9165 | if (abm_changed) { |
02d6a6fc DF |
9166 | dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; |
9167 | ||
9168 | stream_update.abm_level = &dm_new_crtc_state->abm_level; | |
9169 | } | |
70e8ffc5 | 9170 | |
b232d4ed NK |
9171 | if (hdr_changed) { |
9172 | fill_hdr_info_packet(new_con_state, &hdr_packet); | |
9173 | stream_update.hdr_static_metadata = &hdr_packet; | |
9174 | } | |
9175 | ||
54d76575 | 9176 | status = dc_stream_get_status(dm_new_crtc_state->stream); |
57738ae4 ND |
9177 | |
9178 | if (WARN_ON(!status)) | |
9179 | continue; | |
9180 | ||
3be5262e | 9181 | WARN_ON(!status->plane_count); |
e7b07cee | 9182 | |
02d6a6fc DF |
9183 | /* |
9184 | * TODO: DC refuses to perform stream updates without a dc_surface_update. | |
9185 | * Here we create an empty update on each plane. | |
9186 | * To fix this, DC should permit updating only stream properties. | |
9187 | */ | |
135fd1b3 | 9188 | dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); |
02d6a6fc | 9189 | for (j = 0; j < status->plane_count; j++) |
efc8278e | 9190 | dummy_updates[j].surface = status->plane_states[0]; |
02d6a6fc DF |
9191 | |
9192 | ||
9193 | mutex_lock(&dm->dc_lock); | |
f7511289 RS |
9194 | dc_update_planes_and_stream(dm->dc, |
9195 | dummy_updates, | |
9196 | status->plane_count, | |
9197 | dm_new_crtc_state->stream, | |
9198 | &stream_update); | |
02d6a6fc | 9199 | mutex_unlock(&dm->dc_lock); |
135fd1b3 | 9200 | kfree(dummy_updates); |
e7b07cee HW |
9201 | } |
9202 | ||
8fe684e9 NK |
9203 | /** |
9204 | * Enable interrupts for CRTCs that are newly enabled or went through | |
9205 | * a modeset. It was intentionally deferred until after the front end | |
9206 | * state was modified to wait until the OTG was on and so the IRQ | |
9207 | * handlers didn't access stale or invalid state. | |
9208 | */ | |
9209 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { | |
9210 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); | |
8e7b6fee WL |
9211 | #ifdef CONFIG_DEBUG_FS |
9212 | enum amdgpu_dm_pipe_crc_source cur_crc_src; | |
8799c0be YL |
9213 | #endif |
9214 | /* Count number of newly disabled CRTCs for dropping PM refs later. */ | |
9215 | if (old_crtc_state->active && !new_crtc_state->active) | |
9216 | crtc_disable_count++; | |
9217 | ||
9218 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
9219 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
9220 | ||
9221 | /* For freesync config update on crtc state and params for irq */ | |
9222 | update_stream_irq_parameters(dm, dm_new_crtc_state); | |
9223 | ||
9224 | #ifdef CONFIG_DEBUG_FS | |
d98af272 WL |
9225 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
9226 | cur_crc_src = acrtc->dm_irq_params.crc_src; | |
9227 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); | |
8e7b6fee | 9228 | #endif |
585d450c | 9229 | |
8fe684e9 NK |
9230 | if (new_crtc_state->active && |
9231 | (!old_crtc_state->active || | |
9232 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
585d450c AP |
9233 | dc_stream_retain(dm_new_crtc_state->stream); |
9234 | acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; | |
8fe684e9 | 9235 | manage_dm_interrupts(adev, acrtc, true); |
8799c0be YL |
9236 | } |
9237 | /* Handle vrr on->off / off->on transitions */ | |
9238 | amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); | |
e2881d6d | 9239 | |
24eb9374 | 9240 | #ifdef CONFIG_DEBUG_FS |
8799c0be YL |
9241 | if (new_crtc_state->active && |
9242 | (!old_crtc_state->active || | |
9243 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
8fe684e9 NK |
9244 | /** |
9245 | * Frontend may have changed so reapply the CRC capture | |
9246 | * settings for the stream. | |
9247 | */ | |
8e7b6fee | 9248 | if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { |
86bc2219 | 9249 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
d98af272 WL |
9250 | if (amdgpu_dm_crc_window_is_activated(crtc)) { |
9251 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); | |
c0459bdd | 9252 | acrtc->dm_irq_params.window_param.update_win = true; |
1b11ff76 AL |
9253 | |
9254 | /** | |
9255 | * It takes 2 frames for HW to stably generate CRC when | |
9256 | * resuming from suspend, so we set skip_frame_cnt 2. | |
9257 | */ | |
c0459bdd | 9258 | acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; |
d98af272 WL |
9259 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
9260 | } | |
86bc2219 | 9261 | #endif |
bbc49fc0 WL |
9262 | if (amdgpu_dm_crtc_configure_crc_source( |
9263 | crtc, dm_new_crtc_state, cur_crc_src)) | |
9264 | DRM_DEBUG_DRIVER("Failed to configure crc source"); | |
8799c0be | 9265 | } |
8fe684e9 | 9266 | } |
2130b87b | 9267 | #endif |
8fe684e9 | 9268 | } |
e7b07cee | 9269 | |
420cd472 | 9270 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) |
4d85f45c | 9271 | if (new_crtc_state->async_flip) |
420cd472 DF |
9272 | wait_for_vblank = false; |
9273 | ||
e7b07cee | 9274 | /* update planes when needed per crtc*/ |
5cc6dcbd | 9275 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { |
54d76575 | 9276 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 9277 | |
54d76575 | 9278 | if (dm_new_crtc_state->stream) |
fff7b95a | 9279 | amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); |
e7b07cee HW |
9280 | } |
9281 | ||
c81e13b9 AH |
9282 | /* Enable writeback */ |
9283 | for_each_new_connector_in_state(state, connector, new_con_state, i) { | |
9284 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
9285 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
9286 | ||
9287 | if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) | |
9288 | continue; | |
9289 | ||
9290 | if (!new_con_state->writeback_job) | |
9291 | continue; | |
9292 | ||
9293 | new_crtc_state = NULL; | |
9294 | ||
9295 | if (acrtc) | |
9296 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); | |
9297 | ||
f872e2f5 AH |
9298 | if (acrtc->wb_enabled) |
9299 | continue; | |
9300 | ||
c81e13b9 AH |
9301 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
9302 | ||
9303 | dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); | |
f872e2f5 | 9304 | acrtc->wb_enabled = true; |
c81e13b9 AH |
9305 | } |
9306 | ||
6ce8f316 NK |
9307 | /* Update audio instances for each connector. */ |
9308 | amdgpu_dm_commit_audio(dev, state); | |
9309 | ||
7230362c | 9310 | /* restore the backlight level */ |
7fd13bae AD |
9311 | for (i = 0; i < dm->num_of_edps; i++) { |
9312 | if (dm->backlight_dev[i] && | |
4052287a | 9313 | (dm->actual_brightness[i] != dm->brightness[i])) |
7fd13bae AD |
9314 | amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); |
9315 | } | |
83a3439d | 9316 | |
e7b07cee HW |
9317 | /* |
9318 | * send vblank event on all events not handled in flip and | |
9319 | * mark consumed event for drm_atomic_helper_commit_hw_done | |
9320 | */ | |
4a580877 | 9321 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
0bc9706d | 9322 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 9323 | |
0bc9706d LSL |
9324 | if (new_crtc_state->event) |
9325 | drm_send_event_locked(dev, &new_crtc_state->event->base); | |
e7b07cee | 9326 | |
0bc9706d | 9327 | new_crtc_state->event = NULL; |
e7b07cee | 9328 | } |
4a580877 | 9329 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
e7b07cee | 9330 | |
29c8f234 LL |
9331 | /* Signal HW programming completion */ |
9332 | drm_atomic_helper_commit_hw_done(state); | |
e7b07cee HW |
9333 | |
9334 | if (wait_for_vblank) | |
320a1274 | 9335 | drm_atomic_helper_wait_for_flip_done(dev, state); |
e7b07cee HW |
9336 | |
9337 | drm_atomic_helper_cleanup_planes(dev, state); | |
97028037 | 9338 | |
e6b27cf5 AD |
9339 | /* Don't free the memory if we are hitting this as part of suspend. |
9340 | * This way we don't free any memory during suspend; see | |
9341 | * amdgpu_bo_free_kernel(). The memory will be freed in the first | |
9342 | * non-suspend modeset or when the driver is torn down. | |
9343 | */ | |
9344 | if (!adev->in_suspend) { | |
9345 | /* return the stolen vga memory back to VRAM */ | |
9346 | if (!adev->mman.keep_stolen_vga_memory) | |
9347 | amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); | |
9348 | amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); | |
9349 | } | |
5f6fab24 | 9350 | |
1f6010a9 DF |
9351 | /* |
9352 | * Finally, drop a runtime PM reference for each newly disabled CRTC, | |
97028037 LP |
9353 | * so we can put the GPU into runtime suspend if we're not driving any |
9354 | * displays anymore | |
9355 | */ | |
fe2a1965 LP |
9356 | for (i = 0; i < crtc_disable_count; i++) |
9357 | pm_runtime_put_autosuspend(dev->dev); | |
97028037 | 9358 | pm_runtime_mark_last_busy(dev->dev); |
e7b07cee HW |
9359 | } |
9360 | ||
e7b07cee HW |
9361 | static int dm_force_atomic_commit(struct drm_connector *connector) |
9362 | { | |
9363 | int ret = 0; | |
9364 | struct drm_device *ddev = connector->dev; | |
9365 | struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); | |
9366 | struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
9367 | struct drm_plane *plane = disconnected_acrtc->base.primary; | |
9368 | struct drm_connector_state *conn_state; | |
9369 | struct drm_crtc_state *crtc_state; | |
9370 | struct drm_plane_state *plane_state; | |
9371 | ||
9372 | if (!state) | |
9373 | return -ENOMEM; | |
9374 | ||
9375 | state->acquire_ctx = ddev->mode_config.acquire_ctx; | |
9376 | ||
9377 | /* Construct an atomic state to restore previous display setting */ | |
9378 | ||
9379 | /* | |
9380 | * Attach connectors to drm_atomic_state | |
9381 | */ | |
9382 | conn_state = drm_atomic_get_connector_state(state, connector); | |
9383 | ||
9384 | ret = PTR_ERR_OR_ZERO(conn_state); | |
9385 | if (ret) | |
2dc39051 | 9386 | goto out; |
e7b07cee HW |
9387 | |
9388 | /* Attach crtc to drm_atomic_state*/ | |
9389 | crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); | |
9390 | ||
9391 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
9392 | if (ret) | |
2dc39051 | 9393 | goto out; |
e7b07cee HW |
9394 | |
9395 | /* force a restore */ | |
9396 | crtc_state->mode_changed = true; | |
9397 | ||
9398 | /* Attach plane to drm_atomic_state */ | |
9399 | plane_state = drm_atomic_get_plane_state(state, plane); | |
9400 | ||
9401 | ret = PTR_ERR_OR_ZERO(plane_state); | |
9402 | if (ret) | |
2dc39051 | 9403 | goto out; |
e7b07cee HW |
9404 | |
9405 | /* Call commit internally with the state we just constructed */ | |
9406 | ret = drm_atomic_commit(state); | |
e7b07cee | 9407 | |
2dc39051 | 9408 | out: |
e7b07cee | 9409 | drm_atomic_state_put(state); |
2dc39051 VL |
9410 | if (ret) |
9411 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
e7b07cee HW |
9412 | |
9413 | return ret; | |
9414 | } | |
9415 | ||
9416 | /* | |
1f6010a9 DF |
9417 | * This function handles all cases when set mode does not come upon hotplug. |
9418 | * This includes when a display is unplugged then plugged back into the | |
9419 | * same port and when running without usermode desktop manager supprot | |
e7b07cee | 9420 | */ |
3ee6b26b AD |
9421 | void dm_restore_drm_connector_state(struct drm_device *dev, |
9422 | struct drm_connector *connector) | |
e7b07cee | 9423 | { |
7db7ade2 | 9424 | struct amdgpu_dm_connector *aconnector; |
e7b07cee HW |
9425 | struct amdgpu_crtc *disconnected_acrtc; |
9426 | struct dm_crtc_state *acrtc_state; | |
9427 | ||
7db7ade2 HW |
9428 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
9429 | return; | |
9430 | ||
9431 | aconnector = to_amdgpu_dm_connector(connector); | |
9432 | ||
e7b07cee HW |
9433 | if (!aconnector->dc_sink || !connector->state || !connector->encoder) |
9434 | return; | |
9435 | ||
9436 | disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
70e8ffc5 HW |
9437 | if (!disconnected_acrtc) |
9438 | return; | |
e7b07cee | 9439 | |
70e8ffc5 HW |
9440 | acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); |
9441 | if (!acrtc_state->stream) | |
e7b07cee HW |
9442 | return; |
9443 | ||
9444 | /* | |
9445 | * If the previous sink is not released and different from the current, | |
9446 | * we deduce we are in a state where we can not rely on usermode call | |
9447 | * to turn on the display, so we do it here | |
9448 | */ | |
9449 | if (acrtc_state->stream->sink != aconnector->dc_sink) | |
9450 | dm_force_atomic_commit(&aconnector->base); | |
9451 | } | |
9452 | ||
1f6010a9 | 9453 | /* |
e7b07cee HW |
9454 | * Grabs all modesetting locks to serialize against any blocking commits, |
9455 | * Waits for completion of all non blocking commits. | |
9456 | */ | |
3ee6b26b AD |
9457 | static int do_aquire_global_lock(struct drm_device *dev, |
9458 | struct drm_atomic_state *state) | |
e7b07cee HW |
9459 | { |
9460 | struct drm_crtc *crtc; | |
9461 | struct drm_crtc_commit *commit; | |
9462 | long ret; | |
9463 | ||
1f6010a9 DF |
9464 | /* |
9465 | * Adding all modeset locks to aquire_ctx will | |
e7b07cee HW |
9466 | * ensure that when the framework release it the |
9467 | * extra locks we are locking here will get released to | |
9468 | */ | |
9469 | ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); | |
9470 | if (ret) | |
9471 | return ret; | |
9472 | ||
9473 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9474 | spin_lock(&crtc->commit_lock); | |
9475 | commit = list_first_entry_or_null(&crtc->commit_list, | |
9476 | struct drm_crtc_commit, commit_entry); | |
9477 | if (commit) | |
9478 | drm_crtc_commit_get(commit); | |
9479 | spin_unlock(&crtc->commit_lock); | |
9480 | ||
9481 | if (!commit) | |
9482 | continue; | |
9483 | ||
1f6010a9 DF |
9484 | /* |
9485 | * Make sure all pending HW programming completed and | |
e7b07cee HW |
9486 | * page flips done |
9487 | */ | |
9488 | ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); | |
9489 | ||
9490 | if (ret > 0) | |
9491 | ret = wait_for_completion_interruptible_timeout( | |
9492 | &commit->flip_done, 10*HZ); | |
9493 | ||
9494 | if (ret == 0) | |
c82eddf8 SS |
9495 | DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", |
9496 | crtc->base.id, crtc->name); | |
e7b07cee HW |
9497 | |
9498 | drm_crtc_commit_put(commit); | |
9499 | } | |
9500 | ||
9501 | return ret < 0 ? ret : 0; | |
9502 | } | |
9503 | ||
bb47de73 NK |
9504 | static void get_freesync_config_for_crtc( |
9505 | struct dm_crtc_state *new_crtc_state, | |
9506 | struct dm_connector_state *new_con_state) | |
98e6436d AK |
9507 | { |
9508 | struct mod_freesync_config config = {0}; | |
7db7ade2 | 9509 | struct amdgpu_dm_connector *aconnector; |
a057ec46 | 9510 | struct drm_display_mode *mode = &new_crtc_state->base.mode; |
0ab925d3 | 9511 | int vrefresh = drm_mode_vrefresh(mode); |
a85ba005 | 9512 | bool fs_vid_mode = false; |
98e6436d | 9513 | |
7db7ade2 HW |
9514 | if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
9515 | return; | |
9516 | ||
9517 | aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); | |
9518 | ||
a057ec46 | 9519 | new_crtc_state->vrr_supported = new_con_state->freesync_capable && |
0ab925d3 NK |
9520 | vrefresh >= aconnector->min_vfreq && |
9521 | vrefresh <= aconnector->max_vfreq; | |
bb47de73 | 9522 | |
6ffa6799 | 9523 | if (new_crtc_state->vrr_supported) { |
7e5098ab | 9524 | new_crtc_state->stream->ignore_msa_timing_param = true; |
6ffa6799 | 9525 | fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; |
7e5098ab | 9526 | |
a85ba005 NC |
9527 | config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; |
9528 | config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; | |
69ff8845 | 9529 | config.vsif_supported = true; |
180db303 | 9530 | config.btr = true; |
98e6436d | 9531 | |
a85ba005 NC |
9532 | if (fs_vid_mode) { |
9533 | config.state = VRR_STATE_ACTIVE_FIXED; | |
9534 | config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; | |
9535 | goto out; | |
9536 | } else if (new_crtc_state->base.vrr_enabled) { | |
9537 | config.state = VRR_STATE_ACTIVE_VARIABLE; | |
9538 | } else { | |
9539 | config.state = VRR_STATE_INACTIVE; | |
9540 | } | |
9541 | } | |
9542 | out: | |
bb47de73 NK |
9543 | new_crtc_state->freesync_config = config; |
9544 | } | |
98e6436d | 9545 | |
bb47de73 NK |
9546 | static void reset_freesync_config_for_crtc( |
9547 | struct dm_crtc_state *new_crtc_state) | |
9548 | { | |
9549 | new_crtc_state->vrr_supported = false; | |
98e6436d | 9550 | |
bb47de73 NK |
9551 | memset(&new_crtc_state->vrr_infopacket, 0, |
9552 | sizeof(new_crtc_state->vrr_infopacket)); | |
98e6436d AK |
9553 | } |
9554 | ||
a85ba005 NC |
9555 | static bool |
9556 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, | |
9557 | struct drm_crtc_state *new_crtc_state) | |
9558 | { | |
1cbd7887 | 9559 | const struct drm_display_mode *old_mode, *new_mode; |
a85ba005 NC |
9560 | |
9561 | if (!old_crtc_state || !new_crtc_state) | |
9562 | return false; | |
9563 | ||
1cbd7887 VS |
9564 | old_mode = &old_crtc_state->mode; |
9565 | new_mode = &new_crtc_state->mode; | |
9566 | ||
9567 | if (old_mode->clock == new_mode->clock && | |
9568 | old_mode->hdisplay == new_mode->hdisplay && | |
9569 | old_mode->vdisplay == new_mode->vdisplay && | |
9570 | old_mode->htotal == new_mode->htotal && | |
9571 | old_mode->vtotal != new_mode->vtotal && | |
9572 | old_mode->hsync_start == new_mode->hsync_start && | |
9573 | old_mode->vsync_start != new_mode->vsync_start && | |
9574 | old_mode->hsync_end == new_mode->hsync_end && | |
9575 | old_mode->vsync_end != new_mode->vsync_end && | |
9576 | old_mode->hskew == new_mode->hskew && | |
9577 | old_mode->vscan == new_mode->vscan && | |
9578 | (old_mode->vsync_end - old_mode->vsync_start) == | |
9579 | (new_mode->vsync_end - new_mode->vsync_start)) | |
a85ba005 NC |
9580 | return true; |
9581 | ||
9582 | return false; | |
9583 | } | |
9584 | ||
c82eddf8 SS |
9585 | static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) |
9586 | { | |
ae67558b | 9587 | u64 num, den, res; |
a85ba005 NC |
9588 | struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; |
9589 | ||
9590 | dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; | |
9591 | ||
9592 | num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; | |
9593 | den = (unsigned long long)new_crtc_state->mode.htotal * | |
9594 | (unsigned long long)new_crtc_state->mode.vtotal; | |
9595 | ||
9596 | res = div_u64(num, den); | |
9597 | dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; | |
9598 | } | |
9599 | ||
f11d9373 | 9600 | static int dm_update_crtc_state(struct amdgpu_display_manager *dm, |
17ce8a69 RL |
9601 | struct drm_atomic_state *state, |
9602 | struct drm_crtc *crtc, | |
9603 | struct drm_crtc_state *old_crtc_state, | |
9604 | struct drm_crtc_state *new_crtc_state, | |
9605 | bool enable, | |
9606 | bool *lock_and_validation_needed) | |
e7b07cee | 9607 | { |
eb3dc897 | 9608 | struct dm_atomic_state *dm_state = NULL; |
54d76575 | 9609 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
9635b754 | 9610 | struct dc_stream_state *new_stream; |
62f55537 | 9611 | int ret = 0; |
d4d4a645 | 9612 | |
1f6010a9 DF |
9613 | /* |
9614 | * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set | |
9615 | * update changed items | |
9616 | */ | |
4b9674e5 | 9617 | struct amdgpu_crtc *acrtc = NULL; |
748b091d | 9618 | struct drm_connector *connector = NULL; |
4b9674e5 LL |
9619 | struct amdgpu_dm_connector *aconnector = NULL; |
9620 | struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; | |
9621 | struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; | |
e7b07cee | 9622 | |
4b9674e5 | 9623 | new_stream = NULL; |
9635b754 | 9624 | |
4b9674e5 LL |
9625 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
9626 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
9627 | acrtc = to_amdgpu_crtc(crtc); | |
748b091d | 9628 | connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); |
dbf5d3d0 | 9629 | if (connector) |
3e094a28 | 9630 | aconnector = to_amdgpu_dm_connector(connector); |
19f89e23 | 9631 | |
4b9674e5 | 9632 | /* TODO This hack should go away */ |
3e094a28 | 9633 | if (connector && enable) { |
4b9674e5 LL |
9634 | /* Make sure fake sink is created in plug-in scenario */ |
9635 | drm_new_conn_state = drm_atomic_get_new_connector_state(state, | |
3e094a28 | 9636 | connector); |
4b9674e5 | 9637 | drm_old_conn_state = drm_atomic_get_old_connector_state(state, |
3e094a28 | 9638 | connector); |
19f89e23 | 9639 | |
4b9674e5 LL |
9640 | if (IS_ERR(drm_new_conn_state)) { |
9641 | ret = PTR_ERR_OR_ZERO(drm_new_conn_state); | |
9642 | goto fail; | |
9643 | } | |
19f89e23 | 9644 | |
4b9674e5 LL |
9645 | dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); |
9646 | dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); | |
19f89e23 | 9647 | |
02d35a67 JFZ |
9648 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9649 | goto skip_modeset; | |
9650 | ||
cbd14ae7 SW |
9651 | new_stream = create_validate_stream_for_sink(aconnector, |
9652 | &new_crtc_state->mode, | |
9653 | dm_new_conn_state, | |
9654 | dm_old_crtc_state->stream); | |
19f89e23 | 9655 | |
4b9674e5 LL |
9656 | /* |
9657 | * we can have no stream on ACTION_SET if a display | |
9658 | * was disconnected during S3, in this case it is not an | |
9659 | * error, the OS will be updated after detection, and | |
9660 | * will do the right thing on next atomic commit | |
9661 | */ | |
19f89e23 | 9662 | |
4b9674e5 LL |
9663 | if (!new_stream) { |
9664 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", | |
9665 | __func__, acrtc->base.base.id); | |
9666 | ret = -ENOMEM; | |
9667 | goto fail; | |
9668 | } | |
e7b07cee | 9669 | |
3d4e52d0 VL |
9670 | /* |
9671 | * TODO: Check VSDB bits to decide whether this should | |
9672 | * be enabled or not. | |
9673 | */ | |
9674 | new_stream->triggered_crtc_reset.enabled = | |
9675 | dm->force_timing_sync; | |
9676 | ||
4b9674e5 | 9677 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; |
98e6436d | 9678 | |
88694af9 NK |
9679 | ret = fill_hdr_info_packet(drm_new_conn_state, |
9680 | &new_stream->hdr_static_metadata); | |
9681 | if (ret) | |
9682 | goto fail; | |
9683 | ||
7e930949 NK |
9684 | /* |
9685 | * If we already removed the old stream from the context | |
9686 | * (and set the new stream to NULL) then we can't reuse | |
9687 | * the old stream even if the stream and scaling are unchanged. | |
9688 | * We'll hit the BUG_ON and black screen. | |
9689 | * | |
9690 | * TODO: Refactor this function to allow this check to work | |
9691 | * in all conditions. | |
9692 | */ | |
11b92df8 | 9693 | if (dm_new_crtc_state->stream && |
a85ba005 NC |
9694 | is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) |
9695 | goto skip_modeset; | |
9696 | ||
7e930949 NK |
9697 | if (dm_new_crtc_state->stream && |
9698 | dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && | |
4b9674e5 LL |
9699 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { |
9700 | new_crtc_state->mode_changed = false; | |
9701 | DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", | |
9702 | new_crtc_state->mode_changed); | |
62f55537 | 9703 | } |
4b9674e5 | 9704 | } |
b830ebc9 | 9705 | |
02d35a67 | 9706 | /* mode_changed flag may get updated above, need to check again */ |
4b9674e5 LL |
9707 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9708 | goto skip_modeset; | |
e7b07cee | 9709 | |
9f07550b | 9710 | drm_dbg_state(state->dev, |
c82eddf8 | 9711 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", |
4b9674e5 LL |
9712 | acrtc->crtc_id, |
9713 | new_crtc_state->enable, | |
9714 | new_crtc_state->active, | |
9715 | new_crtc_state->planes_changed, | |
9716 | new_crtc_state->mode_changed, | |
9717 | new_crtc_state->active_changed, | |
9718 | new_crtc_state->connectors_changed); | |
62f55537 | 9719 | |
4b9674e5 LL |
9720 | /* Remove stream for any changed/disabled CRTC */ |
9721 | if (!enable) { | |
62f55537 | 9722 | |
4b9674e5 LL |
9723 | if (!dm_old_crtc_state->stream) |
9724 | goto skip_modeset; | |
eb3dc897 | 9725 | |
0f5f1ee4 AP |
9726 | /* Unset freesync video if it was active before */ |
9727 | if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { | |
9728 | dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; | |
9729 | dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; | |
9730 | } | |
9731 | ||
9732 | /* Now check if we should set freesync video mode */ | |
11b92df8 | 9733 | if (dm_new_crtc_state->stream && |
b18f05a0 AP |
9734 | dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && |
9735 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && | |
a85ba005 NC |
9736 | is_timing_unchanged_for_freesync(new_crtc_state, |
9737 | old_crtc_state)) { | |
9738 | new_crtc_state->mode_changed = false; | |
9739 | DRM_DEBUG_DRIVER( | |
c82eddf8 | 9740 | "Mode change not required for front porch change, setting mode_changed to %d", |
a85ba005 NC |
9741 | new_crtc_state->mode_changed); |
9742 | ||
9743 | set_freesync_fixed_config(dm_new_crtc_state); | |
9744 | ||
9745 | goto skip_modeset; | |
11b92df8 | 9746 | } else if (aconnector && |
a85ba005 NC |
9747 | is_freesync_video_mode(&new_crtc_state->mode, |
9748 | aconnector)) { | |
e88ebd83 SC |
9749 | struct drm_display_mode *high_mode; |
9750 | ||
9751 | high_mode = get_highest_refresh_rate_mode(aconnector, false); | |
c82eddf8 | 9752 | if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) |
e88ebd83 | 9753 | set_freesync_fixed_config(dm_new_crtc_state); |
a85ba005 NC |
9754 | } |
9755 | ||
4b9674e5 LL |
9756 | ret = dm_atomic_get_state(state, &dm_state); |
9757 | if (ret) | |
9758 | goto fail; | |
e7b07cee | 9759 | |
4b9674e5 LL |
9760 | DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", |
9761 | crtc->base.id); | |
62f55537 | 9762 | |
4b9674e5 LL |
9763 | /* i.e. reset mode */ |
9764 | if (dc_remove_stream_from_ctx( | |
9765 | dm->dc, | |
9766 | dm_state->context, | |
9767 | dm_old_crtc_state->stream) != DC_OK) { | |
9768 | ret = -EINVAL; | |
9769 | goto fail; | |
9770 | } | |
62f55537 | 9771 | |
4b9674e5 LL |
9772 | dc_stream_release(dm_old_crtc_state->stream); |
9773 | dm_new_crtc_state->stream = NULL; | |
bb47de73 | 9774 | |
4b9674e5 | 9775 | reset_freesync_config_for_crtc(dm_new_crtc_state); |
62f55537 | 9776 | |
4b9674e5 | 9777 | *lock_and_validation_needed = true; |
62f55537 | 9778 | |
4b9674e5 LL |
9779 | } else {/* Add stream for any updated/enabled CRTC */ |
9780 | /* | |
9781 | * Quick fix to prevent NULL pointer on new_stream when | |
9782 | * added MST connectors not found in existing crtc_state in the chained mode | |
9783 | * TODO: need to dig out the root cause of that | |
9784 | */ | |
3e094a28 | 9785 | if (!connector) |
4b9674e5 | 9786 | goto skip_modeset; |
62f55537 | 9787 | |
4b9674e5 LL |
9788 | if (modereset_required(new_crtc_state)) |
9789 | goto skip_modeset; | |
62f55537 | 9790 | |
6c5e25a0 | 9791 | if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, |
4b9674e5 | 9792 | dm_old_crtc_state->stream)) { |
62f55537 | 9793 | |
4b9674e5 | 9794 | WARN_ON(dm_new_crtc_state->stream); |
eb3dc897 | 9795 | |
4b9674e5 LL |
9796 | ret = dm_atomic_get_state(state, &dm_state); |
9797 | if (ret) | |
9798 | goto fail; | |
27b3f4fc | 9799 | |
4b9674e5 | 9800 | dm_new_crtc_state->stream = new_stream; |
62f55537 | 9801 | |
4b9674e5 | 9802 | dc_stream_retain(new_stream); |
1dc90497 | 9803 | |
4711c033 LT |
9804 | DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", |
9805 | crtc->base.id); | |
1dc90497 | 9806 | |
4b9674e5 LL |
9807 | if (dc_add_stream_to_ctx( |
9808 | dm->dc, | |
9809 | dm_state->context, | |
9810 | dm_new_crtc_state->stream) != DC_OK) { | |
9811 | ret = -EINVAL; | |
9812 | goto fail; | |
9b690ef3 BL |
9813 | } |
9814 | ||
4b9674e5 LL |
9815 | *lock_and_validation_needed = true; |
9816 | } | |
9817 | } | |
e277adc5 | 9818 | |
4b9674e5 LL |
9819 | skip_modeset: |
9820 | /* Release extra reference */ | |
9821 | if (new_stream) | |
3335a135 | 9822 | dc_stream_release(new_stream); |
e277adc5 | 9823 | |
4b9674e5 LL |
9824 | /* |
9825 | * We want to do dc stream updates that do not require a | |
9826 | * full modeset below. | |
9827 | */ | |
3e094a28 | 9828 | if (!(enable && connector && new_crtc_state->active)) |
4b9674e5 LL |
9829 | return 0; |
9830 | /* | |
9831 | * Given above conditions, the dc state cannot be NULL because: | |
9832 | * 1. We're in the process of enabling CRTCs (just been added | |
9833 | * to the dc context, or already is on the context) | |
9834 | * 2. Has a valid connector attached, and | |
9835 | * 3. Is currently active and enabled. | |
9836 | * => The dc stream state currently exists. | |
9837 | */ | |
9838 | BUG_ON(dm_new_crtc_state->stream == NULL); | |
a9e8d275 | 9839 | |
4b9674e5 | 9840 | /* Scaling or underscan settings */ |
c521fc31 RL |
9841 | if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || |
9842 | drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
4b9674e5 LL |
9843 | update_stream_scaling_settings( |
9844 | &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); | |
98e6436d | 9845 | |
b05e2c5e DF |
9846 | /* ABM settings */ |
9847 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; | |
9848 | ||
4b9674e5 LL |
9849 | /* |
9850 | * Color management settings. We also update color properties | |
9851 | * when a modeset is needed, to ensure it gets reprogrammed. | |
9852 | */ | |
9853 | if (dm_new_crtc_state->base.color_mgmt_changed || | |
9854 | drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
cf020d49 | 9855 | ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); |
4b9674e5 LL |
9856 | if (ret) |
9857 | goto fail; | |
62f55537 | 9858 | } |
e7b07cee | 9859 | |
4b9674e5 LL |
9860 | /* Update Freesync settings. */ |
9861 | get_freesync_config_for_crtc(dm_new_crtc_state, | |
9862 | dm_new_conn_state); | |
9863 | ||
62f55537 | 9864 | return ret; |
9635b754 DS |
9865 | |
9866 | fail: | |
9867 | if (new_stream) | |
9868 | dc_stream_release(new_stream); | |
9869 | return ret; | |
62f55537 | 9870 | } |
9b690ef3 | 9871 | |
f6ff2a08 NK |
9872 | static bool should_reset_plane(struct drm_atomic_state *state, |
9873 | struct drm_plane *plane, | |
9874 | struct drm_plane_state *old_plane_state, | |
9875 | struct drm_plane_state *new_plane_state) | |
9876 | { | |
9877 | struct drm_plane *other; | |
9878 | struct drm_plane_state *old_other_state, *new_other_state; | |
9879 | struct drm_crtc_state *new_crtc_state; | |
435f5b36 | 9880 | struct amdgpu_device *adev = drm_to_adev(plane->dev); |
f6ff2a08 NK |
9881 | int i; |
9882 | ||
70a1efac | 9883 | /* |
435f5b36 TY |
9884 | * TODO: Remove this hack for all asics once it proves that the |
9885 | * fast updates works fine on DCN3.2+. | |
70a1efac | 9886 | */ |
435f5b36 | 9887 | if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset) |
70a1efac NK |
9888 | return true; |
9889 | ||
f6ff2a08 NK |
9890 | /* Exit early if we know that we're adding or removing the plane. */ |
9891 | if (old_plane_state->crtc != new_plane_state->crtc) | |
9892 | return true; | |
9893 | ||
9894 | /* old crtc == new_crtc == NULL, plane not in context. */ | |
9895 | if (!new_plane_state->crtc) | |
9896 | return false; | |
9897 | ||
9898 | new_crtc_state = | |
9899 | drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); | |
9900 | ||
9901 | if (!new_crtc_state) | |
9902 | return true; | |
9903 | ||
7316c4ad NK |
9904 | /* CRTC Degamma changes currently require us to recreate planes. */ |
9905 | if (new_crtc_state->color_mgmt_changed) | |
9906 | return true; | |
9907 | ||
f6ff2a08 NK |
9908 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9909 | return true; | |
9910 | ||
9911 | /* | |
9912 | * If there are any new primary or overlay planes being added or | |
9913 | * removed then the z-order can potentially change. To ensure | |
9914 | * correct z-order and pipe acquisition the current DC architecture | |
9915 | * requires us to remove and recreate all existing planes. | |
9916 | * | |
9917 | * TODO: Come up with a more elegant solution for this. | |
9918 | */ | |
9919 | for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { | |
6eed95b0 | 9920 | struct amdgpu_framebuffer *old_afb, *new_afb; |
c82eddf8 | 9921 | |
f6ff2a08 NK |
9922 | if (other->type == DRM_PLANE_TYPE_CURSOR) |
9923 | continue; | |
9924 | ||
9925 | if (old_other_state->crtc != new_plane_state->crtc && | |
9926 | new_other_state->crtc != new_plane_state->crtc) | |
9927 | continue; | |
9928 | ||
9929 | if (old_other_state->crtc != new_other_state->crtc) | |
9930 | return true; | |
9931 | ||
dc4cb30d NK |
9932 | /* Src/dst size and scaling updates. */ |
9933 | if (old_other_state->src_w != new_other_state->src_w || | |
9934 | old_other_state->src_h != new_other_state->src_h || | |
9935 | old_other_state->crtc_w != new_other_state->crtc_w || | |
9936 | old_other_state->crtc_h != new_other_state->crtc_h) | |
9937 | return true; | |
9938 | ||
9939 | /* Rotation / mirroring updates. */ | |
9940 | if (old_other_state->rotation != new_other_state->rotation) | |
9941 | return true; | |
9942 | ||
9943 | /* Blending updates. */ | |
9944 | if (old_other_state->pixel_blend_mode != | |
9945 | new_other_state->pixel_blend_mode) | |
9946 | return true; | |
9947 | ||
9948 | /* Alpha updates. */ | |
9949 | if (old_other_state->alpha != new_other_state->alpha) | |
9950 | return true; | |
9951 | ||
9952 | /* Colorspace changes. */ | |
9953 | if (old_other_state->color_range != new_other_state->color_range || | |
9954 | old_other_state->color_encoding != new_other_state->color_encoding) | |
9955 | return true; | |
9956 | ||
9a81cc60 NK |
9957 | /* Framebuffer checks fall at the end. */ |
9958 | if (!old_other_state->fb || !new_other_state->fb) | |
9959 | continue; | |
9960 | ||
9961 | /* Pixel format changes can require bandwidth updates. */ | |
9962 | if (old_other_state->fb->format != new_other_state->fb->format) | |
9963 | return true; | |
9964 | ||
6eed95b0 BN |
9965 | old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; |
9966 | new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; | |
9a81cc60 NK |
9967 | |
9968 | /* Tiling and DCC changes also require bandwidth updates. */ | |
37384b3f BN |
9969 | if (old_afb->tiling_flags != new_afb->tiling_flags || |
9970 | old_afb->base.modifier != new_afb->base.modifier) | |
f6ff2a08 NK |
9971 | return true; |
9972 | } | |
9973 | ||
9974 | return false; | |
9975 | } | |
9976 | ||
b0455fda SS |
9977 | static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, |
9978 | struct drm_plane_state *new_plane_state, | |
9979 | struct drm_framebuffer *fb) | |
9980 | { | |
e72868c4 SS |
9981 | struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); |
9982 | struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); | |
b0455fda | 9983 | unsigned int pitch; |
e72868c4 | 9984 | bool linear; |
b0455fda SS |
9985 | |
9986 | if (fb->width > new_acrtc->max_cursor_width || | |
9987 | fb->height > new_acrtc->max_cursor_height) { | |
9988 | DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", | |
9989 | new_plane_state->fb->width, | |
9990 | new_plane_state->fb->height); | |
9991 | return -EINVAL; | |
9992 | } | |
9993 | if (new_plane_state->src_w != fb->width << 16 || | |
9994 | new_plane_state->src_h != fb->height << 16) { | |
9995 | DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); | |
9996 | return -EINVAL; | |
9997 | } | |
9998 | ||
9999 | /* Pitch in pixels */ | |
10000 | pitch = fb->pitches[0] / fb->format->cpp[0]; | |
10001 | ||
10002 | if (fb->width != pitch) { | |
10003 | DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", | |
10004 | fb->width, pitch); | |
10005 | return -EINVAL; | |
10006 | } | |
10007 | ||
10008 | switch (pitch) { | |
10009 | case 64: | |
10010 | case 128: | |
10011 | case 256: | |
10012 | /* FB pitch is supported by cursor plane */ | |
10013 | break; | |
10014 | default: | |
10015 | DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); | |
10016 | return -EINVAL; | |
10017 | } | |
10018 | ||
e72868c4 | 10019 | /* Core DRM takes care of checking FB modifiers, so we only need to |
c82eddf8 SS |
10020 | * check tiling flags when the FB doesn't have a modifier. |
10021 | */ | |
e72868c4 SS |
10022 | if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { |
10023 | if (adev->family < AMDGPU_FAMILY_AI) { | |
10024 | linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && | |
c82eddf8 | 10025 | AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && |
e72868c4 SS |
10026 | AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; |
10027 | } else { | |
10028 | linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; | |
10029 | } | |
10030 | if (!linear) { | |
10031 | DRM_DEBUG_ATOMIC("Cursor FB not linear"); | |
10032 | return -EINVAL; | |
10033 | } | |
10034 | } | |
10035 | ||
b0455fda SS |
10036 | return 0; |
10037 | } | |
10038 | ||
9e869063 LL |
10039 | static int dm_update_plane_state(struct dc *dc, |
10040 | struct drm_atomic_state *state, | |
10041 | struct drm_plane *plane, | |
10042 | struct drm_plane_state *old_plane_state, | |
10043 | struct drm_plane_state *new_plane_state, | |
10044 | bool enable, | |
35f33086 BL |
10045 | bool *lock_and_validation_needed, |
10046 | bool *is_top_most_overlay) | |
62f55537 | 10047 | { |
eb3dc897 NK |
10048 | |
10049 | struct dm_atomic_state *dm_state = NULL; | |
62f55537 | 10050 | struct drm_crtc *new_plane_crtc, *old_plane_crtc; |
0bc9706d | 10051 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
54d76575 | 10052 | struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; |
54d76575 | 10053 | struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; |
626bf90f | 10054 | struct amdgpu_crtc *new_acrtc; |
f6ff2a08 | 10055 | bool needs_reset; |
62f55537 | 10056 | int ret = 0; |
e7b07cee | 10057 | |
9b690ef3 | 10058 | |
9e869063 LL |
10059 | new_plane_crtc = new_plane_state->crtc; |
10060 | old_plane_crtc = old_plane_state->crtc; | |
10061 | dm_new_plane_state = to_dm_plane_state(new_plane_state); | |
10062 | dm_old_plane_state = to_dm_plane_state(old_plane_state); | |
62f55537 | 10063 | |
626bf90f SS |
10064 | if (plane->type == DRM_PLANE_TYPE_CURSOR) { |
10065 | if (!enable || !new_plane_crtc || | |
10066 | drm_atomic_plane_disabling(plane->state, new_plane_state)) | |
10067 | return 0; | |
10068 | ||
10069 | new_acrtc = to_amdgpu_crtc(new_plane_crtc); | |
10070 | ||
5f581248 SS |
10071 | if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { |
10072 | DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); | |
10073 | return -EINVAL; | |
10074 | } | |
10075 | ||
24f99d2b | 10076 | if (new_plane_state->fb) { |
b0455fda SS |
10077 | ret = dm_check_cursor_fb(new_acrtc, new_plane_state, |
10078 | new_plane_state->fb); | |
10079 | if (ret) | |
10080 | return ret; | |
24f99d2b SS |
10081 | } |
10082 | ||
9e869063 | 10083 | return 0; |
626bf90f | 10084 | } |
9b690ef3 | 10085 | |
f6ff2a08 NK |
10086 | needs_reset = should_reset_plane(state, plane, old_plane_state, |
10087 | new_plane_state); | |
10088 | ||
9e869063 LL |
10089 | /* Remove any changed/removed planes */ |
10090 | if (!enable) { | |
f6ff2a08 | 10091 | if (!needs_reset) |
9e869063 | 10092 | return 0; |
a7b06724 | 10093 | |
9e869063 LL |
10094 | if (!old_plane_crtc) |
10095 | return 0; | |
62f55537 | 10096 | |
9e869063 LL |
10097 | old_crtc_state = drm_atomic_get_old_crtc_state( |
10098 | state, old_plane_crtc); | |
10099 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
9b690ef3 | 10100 | |
9e869063 LL |
10101 | if (!dm_old_crtc_state->stream) |
10102 | return 0; | |
62f55537 | 10103 | |
9e869063 LL |
10104 | DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", |
10105 | plane->base.id, old_plane_crtc->base.id); | |
9b690ef3 | 10106 | |
9e869063 LL |
10107 | ret = dm_atomic_get_state(state, &dm_state); |
10108 | if (ret) | |
10109 | return ret; | |
eb3dc897 | 10110 | |
9e869063 LL |
10111 | if (!dc_remove_plane_from_context( |
10112 | dc, | |
10113 | dm_old_crtc_state->stream, | |
10114 | dm_old_plane_state->dc_state, | |
10115 | dm_state->context)) { | |
62f55537 | 10116 | |
c3537613 | 10117 | return -EINVAL; |
9e869063 | 10118 | } |
e7b07cee | 10119 | |
da5e1490 AP |
10120 | if (dm_old_plane_state->dc_state) |
10121 | dc_plane_state_release(dm_old_plane_state->dc_state); | |
9b690ef3 | 10122 | |
9e869063 | 10123 | dm_new_plane_state->dc_state = NULL; |
1dc90497 | 10124 | |
9e869063 | 10125 | *lock_and_validation_needed = true; |
1dc90497 | 10126 | |
9e869063 LL |
10127 | } else { /* Add new planes */ |
10128 | struct dc_plane_state *dc_new_plane_state; | |
1dc90497 | 10129 | |
9e869063 LL |
10130 | if (drm_atomic_plane_disabling(plane->state, new_plane_state)) |
10131 | return 0; | |
e7b07cee | 10132 | |
9e869063 LL |
10133 | if (!new_plane_crtc) |
10134 | return 0; | |
e7b07cee | 10135 | |
9e869063 LL |
10136 | new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); |
10137 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
1dc90497 | 10138 | |
9e869063 LL |
10139 | if (!dm_new_crtc_state->stream) |
10140 | return 0; | |
62f55537 | 10141 | |
f6ff2a08 | 10142 | if (!needs_reset) |
9e869063 | 10143 | return 0; |
62f55537 | 10144 | |
8bf0d9cd | 10145 | ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); |
8c44515b AP |
10146 | if (ret) |
10147 | return ret; | |
10148 | ||
9e869063 | 10149 | WARN_ON(dm_new_plane_state->dc_state); |
9b690ef3 | 10150 | |
9e869063 LL |
10151 | dc_new_plane_state = dc_create_plane_state(dc); |
10152 | if (!dc_new_plane_state) | |
10153 | return -ENOMEM; | |
62f55537 | 10154 | |
35f33086 BL |
10155 | /* Block top most plane from being a video plane */ |
10156 | if (plane->type == DRM_PLANE_TYPE_OVERLAY) { | |
c4066d8b | 10157 | if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay) |
35f33086 | 10158 | return -EINVAL; |
44a4f50d SS |
10159 | |
10160 | *is_top_most_overlay = false; | |
35f33086 BL |
10161 | } |
10162 | ||
4711c033 LT |
10163 | DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", |
10164 | plane->base.id, new_plane_crtc->base.id); | |
8c45c5db | 10165 | |
695af5f9 | 10166 | ret = fill_dc_plane_attributes( |
1348969a | 10167 | drm_to_adev(new_plane_crtc->dev), |
9e869063 LL |
10168 | dc_new_plane_state, |
10169 | new_plane_state, | |
10170 | new_crtc_state); | |
10171 | if (ret) { | |
10172 | dc_plane_state_release(dc_new_plane_state); | |
10173 | return ret; | |
10174 | } | |
62f55537 | 10175 | |
9e869063 LL |
10176 | ret = dm_atomic_get_state(state, &dm_state); |
10177 | if (ret) { | |
10178 | dc_plane_state_release(dc_new_plane_state); | |
10179 | return ret; | |
10180 | } | |
eb3dc897 | 10181 | |
9e869063 LL |
10182 | /* |
10183 | * Any atomic check errors that occur after this will | |
10184 | * not need a release. The plane state will be attached | |
10185 | * to the stream, and therefore part of the atomic | |
10186 | * state. It'll be released when the atomic state is | |
10187 | * cleaned. | |
10188 | */ | |
10189 | if (!dc_add_plane_to_context( | |
10190 | dc, | |
10191 | dm_new_crtc_state->stream, | |
10192 | dc_new_plane_state, | |
10193 | dm_state->context)) { | |
62f55537 | 10194 | |
9e869063 LL |
10195 | dc_plane_state_release(dc_new_plane_state); |
10196 | return -EINVAL; | |
10197 | } | |
8c45c5db | 10198 | |
9e869063 | 10199 | dm_new_plane_state->dc_state = dc_new_plane_state; |
000b59ea | 10200 | |
214993e1 ML |
10201 | dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); |
10202 | ||
9e869063 LL |
10203 | /* Tell DC to do a full surface update every time there |
10204 | * is a plane change. Inefficient, but works for now. | |
10205 | */ | |
10206 | dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; | |
10207 | ||
10208 | *lock_and_validation_needed = true; | |
62f55537 | 10209 | } |
e7b07cee HW |
10210 | |
10211 | ||
62f55537 AG |
10212 | return ret; |
10213 | } | |
a87fa993 | 10214 | |
69cb5629 VZ |
10215 | static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, |
10216 | int *src_w, int *src_h) | |
10217 | { | |
10218 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { | |
10219 | case DRM_MODE_ROTATE_90: | |
10220 | case DRM_MODE_ROTATE_270: | |
10221 | *src_w = plane_state->src_h >> 16; | |
10222 | *src_h = plane_state->src_w >> 16; | |
10223 | break; | |
10224 | case DRM_MODE_ROTATE_0: | |
10225 | case DRM_MODE_ROTATE_180: | |
10226 | default: | |
10227 | *src_w = plane_state->src_w >> 16; | |
10228 | *src_h = plane_state->src_h >> 16; | |
10229 | break; | |
10230 | } | |
10231 | } | |
10232 | ||
ec4d770b MD |
10233 | static void |
10234 | dm_get_plane_scale(struct drm_plane_state *plane_state, | |
10235 | int *out_plane_scale_w, int *out_plane_scale_h) | |
10236 | { | |
10237 | int plane_src_w, plane_src_h; | |
10238 | ||
10239 | dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); | |
10240 | *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w; | |
10241 | *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h; | |
10242 | } | |
10243 | ||
12f4849a SS |
10244 | static int dm_check_crtc_cursor(struct drm_atomic_state *state, |
10245 | struct drm_crtc *crtc, | |
10246 | struct drm_crtc_state *new_crtc_state) | |
10247 | { | |
bc0b79ce MD |
10248 | struct drm_plane *cursor = crtc->cursor, *plane, *underlying; |
10249 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
d1bfbe8a SS |
10250 | struct drm_plane_state *new_cursor_state, *new_underlying_state; |
10251 | int i; | |
10252 | int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; | |
bc0b79ce | 10253 | bool any_relevant_change = false; |
12f4849a SS |
10254 | |
10255 | /* On DCE and DCN there is no dedicated hardware cursor plane. We get a | |
10256 | * cursor per pipe but it's going to inherit the scaling and | |
10257 | * positioning from the underlying pipe. Check the cursor plane's | |
c82eddf8 SS |
10258 | * blending properties match the underlying planes'. |
10259 | */ | |
12f4849a | 10260 | |
bc0b79ce MD |
10261 | /* If no plane was enabled or changed scaling, no need to check again */ |
10262 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { | |
10263 | int new_scale_w, new_scale_h, old_scale_w, old_scale_h; | |
10264 | ||
10265 | if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc) | |
10266 | continue; | |
10267 | ||
10268 | if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) { | |
10269 | any_relevant_change = true; | |
10270 | break; | |
10271 | } | |
10272 | ||
10273 | if (new_plane_state->fb == old_plane_state->fb && | |
10274 | new_plane_state->crtc_w == old_plane_state->crtc_w && | |
10275 | new_plane_state->crtc_h == old_plane_state->crtc_h) | |
10276 | continue; | |
10277 | ||
10278 | dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h); | |
10279 | dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); | |
10280 | ||
10281 | if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { | |
10282 | any_relevant_change = true; | |
10283 | break; | |
10284 | } | |
10285 | } | |
10286 | ||
10287 | if (!any_relevant_change) | |
10288 | return 0; | |
10289 | ||
003048dd MD |
10290 | new_cursor_state = drm_atomic_get_plane_state(state, cursor); |
10291 | if (IS_ERR(new_cursor_state)) | |
10292 | return PTR_ERR(new_cursor_state); | |
10293 | ||
10294 | if (!new_cursor_state->fb) | |
12f4849a | 10295 | return 0; |
12f4849a | 10296 | |
ec4d770b | 10297 | dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h); |
12f4849a | 10298 | |
003048dd MD |
10299 | /* Need to check all enabled planes, even if this commit doesn't change |
10300 | * their state | |
10301 | */ | |
10302 | i = drm_atomic_add_affected_planes(state, crtc); | |
10303 | if (i) | |
10304 | return i; | |
12f4849a | 10305 | |
d1bfbe8a SS |
10306 | for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { |
10307 | /* Narrow down to non-cursor planes on the same CRTC as the cursor */ | |
10308 | if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) | |
10309 | continue; | |
12f4849a | 10310 | |
d1bfbe8a SS |
10311 | /* Ignore disabled planes */ |
10312 | if (!new_underlying_state->fb) | |
10313 | continue; | |
10314 | ||
ec4d770b MD |
10315 | dm_get_plane_scale(new_underlying_state, |
10316 | &underlying_scale_w, &underlying_scale_h); | |
d1bfbe8a SS |
10317 | |
10318 | if (cursor_scale_w != underlying_scale_w || | |
10319 | cursor_scale_h != underlying_scale_h) { | |
10320 | drm_dbg_atomic(crtc->dev, | |
10321 | "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", | |
10322 | cursor->base.id, cursor->name, underlying->base.id, underlying->name); | |
10323 | return -EINVAL; | |
10324 | } | |
10325 | ||
10326 | /* If this plane covers the whole CRTC, no need to check planes underneath */ | |
10327 | if (new_underlying_state->crtc_x <= 0 && | |
10328 | new_underlying_state->crtc_y <= 0 && | |
10329 | new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && | |
10330 | new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) | |
10331 | break; | |
12f4849a SS |
10332 | } |
10333 | ||
10334 | return 0; | |
10335 | } | |
10336 | ||
44be939f ML |
10337 | static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) |
10338 | { | |
10339 | struct drm_connector *connector; | |
128f8ed5 | 10340 | struct drm_connector_state *conn_state, *old_conn_state; |
44be939f ML |
10341 | struct amdgpu_dm_connector *aconnector = NULL; |
10342 | int i; | |
c82eddf8 | 10343 | |
128f8ed5 RL |
10344 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { |
10345 | if (!conn_state->crtc) | |
10346 | conn_state = old_conn_state; | |
10347 | ||
44be939f ML |
10348 | if (conn_state->crtc != crtc) |
10349 | continue; | |
10350 | ||
7db7ade2 HW |
10351 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
10352 | continue; | |
10353 | ||
44be939f | 10354 | aconnector = to_amdgpu_dm_connector(connector); |
f0127cb1 | 10355 | if (!aconnector->mst_output_port || !aconnector->mst_root) |
44be939f ML |
10356 | aconnector = NULL; |
10357 | else | |
10358 | break; | |
10359 | } | |
10360 | ||
10361 | if (!aconnector) | |
10362 | return 0; | |
10363 | ||
f0127cb1 | 10364 | return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); |
44be939f ML |
10365 | } |
10366 | ||
b8592b48 LL |
10367 | /** |
10368 | * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. | |
c620e79b | 10369 | * |
b8592b48 LL |
10370 | * @dev: The DRM device |
10371 | * @state: The atomic state to commit | |
10372 | * | |
10373 | * Validate that the given atomic state is programmable by DC into hardware. | |
10374 | * This involves constructing a &struct dc_state reflecting the new hardware | |
10375 | * state we wish to commit, then querying DC to see if it is programmable. It's | |
10376 | * important not to modify the existing DC state. Otherwise, atomic_check | |
10377 | * may unexpectedly commit hardware changes. | |
10378 | * | |
10379 | * When validating the DC state, it's important that the right locks are | |
10380 | * acquired. For full updates case which removes/adds/updates streams on one | |
10381 | * CRTC while flipping on another CRTC, acquiring global lock will guarantee | |
10382 | * that any such full update commit will wait for completion of any outstanding | |
f6d7c7fa | 10383 | * flip using DRMs synchronization events. |
b8592b48 LL |
10384 | * |
10385 | * Note that DM adds the affected connectors for all CRTCs in state, when that | |
10386 | * might not seem necessary. This is because DC stream creation requires the | |
10387 | * DC sink, which is tied to the DRM connector state. Cleaning this up should | |
10388 | * be possible but non-trivial - a possible TODO item. | |
10389 | * | |
10390 | * Return: -Error code if validation failed. | |
10391 | */ | |
7578ecda AD |
10392 | static int amdgpu_dm_atomic_check(struct drm_device *dev, |
10393 | struct drm_atomic_state *state) | |
62f55537 | 10394 | { |
1348969a | 10395 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 | 10396 | struct dm_atomic_state *dm_state = NULL; |
62f55537 | 10397 | struct dc *dc = adev->dm.dc; |
62f55537 | 10398 | struct drm_connector *connector; |
c2cea706 | 10399 | struct drm_connector_state *old_con_state, *new_con_state; |
62f55537 | 10400 | struct drm_crtc *crtc; |
fc9e9920 | 10401 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
9e869063 LL |
10402 | struct drm_plane *plane; |
10403 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
74a16675 | 10404 | enum dc_status status; |
1e88ad0a | 10405 | int ret, i; |
62f55537 | 10406 | bool lock_and_validation_needed = false; |
35f33086 | 10407 | bool is_top_most_overlay = true; |
214993e1 | 10408 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
cdf657fc DA |
10409 | struct drm_dp_mst_topology_mgr *mgr; |
10410 | struct drm_dp_mst_topology_state *mst_state; | |
6513104b | 10411 | struct dsc_mst_fairness_vars vars[MAX_PIPES]; |
62f55537 | 10412 | |
e8a98235 | 10413 | trace_amdgpu_dm_atomic_check_begin(state); |
c44a22b3 | 10414 | |
62f55537 | 10415 | ret = drm_atomic_helper_check_modeset(dev, state); |
68ca1c3e S |
10416 | if (ret) { |
10417 | DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); | |
01e28f9c | 10418 | goto fail; |
68ca1c3e | 10419 | } |
62f55537 | 10420 | |
c5892a10 SW |
10421 | /* Check connector changes */ |
10422 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
10423 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); | |
10424 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
10425 | ||
10426 | /* Skip connectors that are disabled or part of modeset already. */ | |
c5892a10 SW |
10427 | if (!new_con_state->crtc) |
10428 | continue; | |
10429 | ||
10430 | new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); | |
10431 | if (IS_ERR(new_crtc_state)) { | |
68ca1c3e | 10432 | DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); |
c5892a10 SW |
10433 | ret = PTR_ERR(new_crtc_state); |
10434 | goto fail; | |
10435 | } | |
10436 | ||
3c6d1aeb | 10437 | if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || |
10438 | dm_old_con_state->scaling != dm_new_con_state->scaling) | |
c5892a10 SW |
10439 | new_crtc_state->connectors_changed = true; |
10440 | } | |
10441 | ||
349a19b2 | 10442 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
44be939f ML |
10443 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
10444 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
10445 | ret = add_affected_mst_dsc_crtcs(state, crtc); | |
68ca1c3e S |
10446 | if (ret) { |
10447 | DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); | |
44be939f | 10448 | goto fail; |
68ca1c3e | 10449 | } |
44be939f ML |
10450 | } |
10451 | } | |
10452 | } | |
1e88ad0a | 10453 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
886876ec EB |
10454 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
10455 | ||
1e88ad0a | 10456 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && |
98e6436d | 10457 | !new_crtc_state->color_mgmt_changed && |
886876ec EB |
10458 | old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && |
10459 | dm_old_crtc_state->dsc_force_changed == false) | |
1e88ad0a | 10460 | continue; |
7bef1af3 | 10461 | |
03fc4cf4 | 10462 | ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); |
68ca1c3e S |
10463 | if (ret) { |
10464 | DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); | |
03fc4cf4 | 10465 | goto fail; |
68ca1c3e | 10466 | } |
03fc4cf4 | 10467 | |
1e88ad0a S |
10468 | if (!new_crtc_state->enable) |
10469 | continue; | |
fc9e9920 | 10470 | |
1e88ad0a | 10471 | ret = drm_atomic_add_affected_connectors(state, crtc); |
68ca1c3e S |
10472 | if (ret) { |
10473 | DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); | |
706bc8c5 | 10474 | goto fail; |
68ca1c3e | 10475 | } |
fc9e9920 | 10476 | |
1e88ad0a | 10477 | ret = drm_atomic_add_affected_planes(state, crtc); |
68ca1c3e S |
10478 | if (ret) { |
10479 | DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); | |
1e88ad0a | 10480 | goto fail; |
68ca1c3e | 10481 | } |
115a385c | 10482 | |
cbac53f7 | 10483 | if (dm_old_crtc_state->dsc_force_changed) |
115a385c | 10484 | new_crtc_state->mode_changed = true; |
e7b07cee HW |
10485 | } |
10486 | ||
2d9e6431 NK |
10487 | /* |
10488 | * Add all primary and overlay planes on the CRTC to the state | |
10489 | * whenever a plane is enabled to maintain correct z-ordering | |
10490 | * and to enable fast surface updates. | |
10491 | */ | |
10492 | drm_for_each_crtc(crtc, dev) { | |
10493 | bool modified = false; | |
10494 | ||
10495 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { | |
10496 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
10497 | continue; | |
10498 | ||
10499 | if (new_plane_state->crtc == crtc || | |
10500 | old_plane_state->crtc == crtc) { | |
10501 | modified = true; | |
10502 | break; | |
10503 | } | |
10504 | } | |
10505 | ||
10506 | if (!modified) | |
10507 | continue; | |
10508 | ||
10509 | drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { | |
10510 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
10511 | continue; | |
10512 | ||
10513 | new_plane_state = | |
10514 | drm_atomic_get_plane_state(state, plane); | |
10515 | ||
10516 | if (IS_ERR(new_plane_state)) { | |
10517 | ret = PTR_ERR(new_plane_state); | |
68ca1c3e | 10518 | DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); |
2d9e6431 NK |
10519 | goto fail; |
10520 | } | |
10521 | } | |
10522 | } | |
10523 | ||
22c42b0e LL |
10524 | /* |
10525 | * DC consults the zpos (layer_index in DC terminology) to determine the | |
10526 | * hw plane on which to enable the hw cursor (see | |
10527 | * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in | |
10528 | * atomic state, so call drm helper to normalize zpos. | |
10529 | */ | |
ac0bb08d LL |
10530 | ret = drm_atomic_normalize_zpos(dev, state); |
10531 | if (ret) { | |
10532 | drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); | |
10533 | goto fail; | |
10534 | } | |
22c42b0e | 10535 | |
62f55537 | 10536 | /* Remove exiting planes if they are modified */ |
9e869063 | 10537 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { |
a7c0cad0 HM |
10538 | if (old_plane_state->fb && new_plane_state->fb && |
10539 | get_mem_type(old_plane_state->fb) != | |
10540 | get_mem_type(new_plane_state->fb)) | |
10541 | lock_and_validation_needed = true; | |
10542 | ||
9e869063 LL |
10543 | ret = dm_update_plane_state(dc, state, plane, |
10544 | old_plane_state, | |
10545 | new_plane_state, | |
10546 | false, | |
35f33086 BL |
10547 | &lock_and_validation_needed, |
10548 | &is_top_most_overlay); | |
68ca1c3e S |
10549 | if (ret) { |
10550 | DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); | |
9e869063 | 10551 | goto fail; |
68ca1c3e | 10552 | } |
62f55537 AG |
10553 | } |
10554 | ||
10555 | /* Disable all crtcs which require disable */ | |
4b9674e5 LL |
10556 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
10557 | ret = dm_update_crtc_state(&adev->dm, state, crtc, | |
10558 | old_crtc_state, | |
10559 | new_crtc_state, | |
10560 | false, | |
10561 | &lock_and_validation_needed); | |
68ca1c3e S |
10562 | if (ret) { |
10563 | DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); | |
4b9674e5 | 10564 | goto fail; |
68ca1c3e | 10565 | } |
62f55537 AG |
10566 | } |
10567 | ||
10568 | /* Enable all crtcs which require enable */ | |
4b9674e5 LL |
10569 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
10570 | ret = dm_update_crtc_state(&adev->dm, state, crtc, | |
10571 | old_crtc_state, | |
10572 | new_crtc_state, | |
10573 | true, | |
10574 | &lock_and_validation_needed); | |
68ca1c3e S |
10575 | if (ret) { |
10576 | DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); | |
4b9674e5 | 10577 | goto fail; |
68ca1c3e | 10578 | } |
62f55537 AG |
10579 | } |
10580 | ||
10581 | /* Add new/modified planes */ | |
9e869063 LL |
10582 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { |
10583 | ret = dm_update_plane_state(dc, state, plane, | |
10584 | old_plane_state, | |
10585 | new_plane_state, | |
10586 | true, | |
35f33086 BL |
10587 | &lock_and_validation_needed, |
10588 | &is_top_most_overlay); | |
68ca1c3e S |
10589 | if (ret) { |
10590 | DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); | |
9e869063 | 10591 | goto fail; |
68ca1c3e | 10592 | } |
62f55537 AG |
10593 | } |
10594 | ||
876fcc42 | 10595 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
7cce4cd6 LP |
10596 | ret = pre_validate_dsc(state, &dm_state, vars); |
10597 | if (ret != 0) | |
876fcc42 | 10598 | goto fail; |
876fcc42 | 10599 | } |
876fcc42 | 10600 | |
b349f76e ES |
10601 | /* Run this here since we want to validate the streams we created */ |
10602 | ret = drm_atomic_helper_check_planes(dev, state); | |
68ca1c3e S |
10603 | if (ret) { |
10604 | DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); | |
b349f76e | 10605 | goto fail; |
68ca1c3e | 10606 | } |
62f55537 | 10607 | |
214993e1 ML |
10608 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
10609 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
10610 | if (dm_new_crtc_state->mpo_requested) | |
10611 | DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); | |
10612 | } | |
10613 | ||
12f4849a SS |
10614 | /* Check cursor planes scaling */ |
10615 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { | |
10616 | ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); | |
68ca1c3e S |
10617 | if (ret) { |
10618 | DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); | |
12f4849a | 10619 | goto fail; |
68ca1c3e | 10620 | } |
12f4849a SS |
10621 | } |
10622 | ||
43d10d30 NK |
10623 | if (state->legacy_cursor_update) { |
10624 | /* | |
10625 | * This is a fast cursor update coming from the plane update | |
10626 | * helper, check if it can be done asynchronously for better | |
10627 | * performance. | |
10628 | */ | |
10629 | state->async_update = | |
10630 | !drm_atomic_helper_async_check(dev, state); | |
10631 | ||
10632 | /* | |
10633 | * Skip the remaining global validation if this is an async | |
10634 | * update. Cursor updates can be done without affecting | |
10635 | * state or bandwidth calcs and this avoids the performance | |
10636 | * penalty of locking the private state object and | |
10637 | * allocating a new dc_state. | |
10638 | */ | |
10639 | if (state->async_update) | |
10640 | return 0; | |
10641 | } | |
10642 | ||
ebdd27e1 | 10643 | /* Check scaling and underscan changes*/ |
1f6010a9 | 10644 | /* TODO Removed scaling changes validation due to inability to commit |
e7b07cee HW |
10645 | * new stream into context w\o causing full reset. Need to |
10646 | * decide how to handle. | |
10647 | */ | |
c2cea706 | 10648 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
10649 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); |
10650 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
10651 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
e7b07cee HW |
10652 | |
10653 | /* Skip any modesets/resets */ | |
0bc9706d LSL |
10654 | if (!acrtc || drm_atomic_crtc_needs_modeset( |
10655 | drm_atomic_get_new_crtc_state(state, &acrtc->base))) | |
e7b07cee HW |
10656 | continue; |
10657 | ||
b830ebc9 | 10658 | /* Skip any thing not scale or underscan changes */ |
54d76575 | 10659 | if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) |
e7b07cee HW |
10660 | continue; |
10661 | ||
10662 | lock_and_validation_needed = true; | |
10663 | } | |
10664 | ||
c689e1e3 LP |
10665 | /* set the slot info for each mst_state based on the link encoding format */ |
10666 | for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { | |
10667 | struct amdgpu_dm_connector *aconnector; | |
10668 | struct drm_connector *connector; | |
10669 | struct drm_connector_list_iter iter; | |
10670 | u8 link_coding_cap; | |
10671 | ||
10672 | drm_connector_list_iter_begin(dev, &iter); | |
10673 | drm_for_each_connector_iter(connector, &iter) { | |
10674 | if (connector->index == mst_state->mgr->conn_base_id) { | |
10675 | aconnector = to_amdgpu_dm_connector(connector); | |
10676 | link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); | |
10677 | drm_dp_mst_update_slots(mst_state, link_coding_cap); | |
10678 | ||
10679 | break; | |
10680 | } | |
10681 | } | |
10682 | drm_connector_list_iter_end(&iter); | |
10683 | } | |
c689e1e3 | 10684 | |
f6d7c7fa NK |
10685 | /** |
10686 | * Streams and planes are reset when there are changes that affect | |
10687 | * bandwidth. Anything that affects bandwidth needs to go through | |
10688 | * DC global validation to ensure that the configuration can be applied | |
10689 | * to hardware. | |
10690 | * | |
10691 | * We have to currently stall out here in atomic_check for outstanding | |
10692 | * commits to finish in this case because our IRQ handlers reference | |
10693 | * DRM state directly - we can end up disabling interrupts too early | |
10694 | * if we don't. | |
10695 | * | |
10696 | * TODO: Remove this stall and drop DM state private objects. | |
a87fa993 | 10697 | */ |
f6d7c7fa | 10698 | if (lock_and_validation_needed) { |
eb3dc897 | 10699 | ret = dm_atomic_get_state(state, &dm_state); |
68ca1c3e S |
10700 | if (ret) { |
10701 | DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); | |
eb3dc897 | 10702 | goto fail; |
68ca1c3e | 10703 | } |
e7b07cee HW |
10704 | |
10705 | ret = do_aquire_global_lock(dev, state); | |
68ca1c3e S |
10706 | if (ret) { |
10707 | DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); | |
e7b07cee | 10708 | goto fail; |
68ca1c3e | 10709 | } |
1dc90497 | 10710 | |
7cce4cd6 LP |
10711 | ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); |
10712 | if (ret) { | |
68ca1c3e | 10713 | DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); |
dd24662d | 10714 | ret = -EINVAL; |
8c20a1ed | 10715 | goto fail; |
68ca1c3e | 10716 | } |
8c20a1ed | 10717 | |
6513104b | 10718 | ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); |
68ca1c3e S |
10719 | if (ret) { |
10720 | DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); | |
29b9ba74 | 10721 | goto fail; |
68ca1c3e | 10722 | } |
29b9ba74 | 10723 | |
ded58c7b ZL |
10724 | /* |
10725 | * Perform validation of MST topology in the state: | |
10726 | * We need to perform MST atomic check before calling | |
10727 | * dc_validate_global_state(), or there is a chance | |
10728 | * to get stuck in an infinite loop and hang eventually. | |
10729 | */ | |
10730 | ret = drm_dp_mst_atomic_check(state); | |
68ca1c3e S |
10731 | if (ret) { |
10732 | DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); | |
ded58c7b | 10733 | goto fail; |
68ca1c3e | 10734 | } |
85fb8bb9 | 10735 | status = dc_validate_global_state(dc, dm_state->context, true); |
74a16675 | 10736 | if (status != DC_OK) { |
68ca1c3e | 10737 | DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", |
74a16675 | 10738 | dc_status_to_str(status), status); |
e7b07cee HW |
10739 | ret = -EINVAL; |
10740 | goto fail; | |
10741 | } | |
bd200d19 | 10742 | } else { |
674e78ac | 10743 | /* |
bd200d19 NK |
10744 | * The commit is a fast update. Fast updates shouldn't change |
10745 | * the DC context, affect global validation, and can have their | |
10746 | * commit work done in parallel with other commits not touching | |
10747 | * the same resource. If we have a new DC context as part of | |
10748 | * the DM atomic state from validation we need to free it and | |
10749 | * retain the existing one instead. | |
fde9f39a MR |
10750 | * |
10751 | * Furthermore, since the DM atomic state only contains the DC | |
10752 | * context and can safely be annulled, we can free the state | |
10753 | * and clear the associated private object now to free | |
10754 | * some memory and avoid a possible use-after-free later. | |
674e78ac | 10755 | */ |
bd200d19 | 10756 | |
fde9f39a MR |
10757 | for (i = 0; i < state->num_private_objs; i++) { |
10758 | struct drm_private_obj *obj = state->private_objs[i].ptr; | |
bd200d19 | 10759 | |
fde9f39a MR |
10760 | if (obj->funcs == adev->dm.atomic_obj.funcs) { |
10761 | int j = state->num_private_objs-1; | |
bd200d19 | 10762 | |
fde9f39a MR |
10763 | dm_atomic_destroy_state(obj, |
10764 | state->private_objs[i].state); | |
10765 | ||
10766 | /* If i is not at the end of the array then the | |
10767 | * last element needs to be moved to where i was | |
10768 | * before the array can safely be truncated. | |
10769 | */ | |
10770 | if (i != j) | |
10771 | state->private_objs[i] = | |
10772 | state->private_objs[j]; | |
bd200d19 | 10773 | |
fde9f39a MR |
10774 | state->private_objs[j].ptr = NULL; |
10775 | state->private_objs[j].state = NULL; | |
10776 | state->private_objs[j].old_state = NULL; | |
10777 | state->private_objs[j].new_state = NULL; | |
10778 | ||
10779 | state->num_private_objs = j; | |
10780 | break; | |
10781 | } | |
bd200d19 | 10782 | } |
e7b07cee HW |
10783 | } |
10784 | ||
caff0e66 | 10785 | /* Store the overall update type for use later in atomic check. */ |
c82eddf8 | 10786 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
caff0e66 NK |
10787 | struct dm_crtc_state *dm_new_crtc_state = |
10788 | to_dm_crtc_state(new_crtc_state); | |
10789 | ||
a7c0cad0 HM |
10790 | /* |
10791 | * Only allow async flips for fast updates that don't change | |
10792 | * the FB pitch, the DCC state, rotation, etc. | |
10793 | */ | |
10794 | if (new_crtc_state->async_flip && lock_and_validation_needed) { | |
10795 | drm_dbg_atomic(crtc->dev, | |
10796 | "[CRTC:%d:%s] async flips are only supported for fast updates\n", | |
10797 | crtc->base.id, crtc->name); | |
10798 | ret = -EINVAL; | |
10799 | goto fail; | |
10800 | } | |
10801 | ||
f6d7c7fa | 10802 | dm_new_crtc_state->update_type = lock_and_validation_needed ? |
a7c0cad0 | 10803 | UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; |
e7b07cee HW |
10804 | } |
10805 | ||
10806 | /* Must be success */ | |
10807 | WARN_ON(ret); | |
e8a98235 RS |
10808 | |
10809 | trace_amdgpu_dm_atomic_check_finish(state, ret); | |
10810 | ||
e7b07cee HW |
10811 | return ret; |
10812 | ||
10813 | fail: | |
10814 | if (ret == -EDEADLK) | |
01e28f9c | 10815 | DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); |
e7b07cee | 10816 | else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) |
01e28f9c | 10817 | DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); |
e7b07cee | 10818 | else |
c82eddf8 | 10819 | DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret); |
e7b07cee | 10820 | |
e8a98235 RS |
10821 | trace_amdgpu_dm_atomic_check_finish(state, ret); |
10822 | ||
e7b07cee HW |
10823 | return ret; |
10824 | } | |
10825 | ||
3ee6b26b AD |
10826 | static bool is_dp_capable_without_timing_msa(struct dc *dc, |
10827 | struct amdgpu_dm_connector *amdgpu_dm_connector) | |
e7b07cee | 10828 | { |
ae67558b | 10829 | u8 dpcd_data; |
e7b07cee HW |
10830 | bool capable = false; |
10831 | ||
c84dec2f | 10832 | if (amdgpu_dm_connector->dc_link && |
e7b07cee HW |
10833 | dm_helpers_dp_read_dpcd( |
10834 | NULL, | |
c84dec2f | 10835 | amdgpu_dm_connector->dc_link, |
e7b07cee HW |
10836 | DP_DOWN_STREAM_PORT_COUNT, |
10837 | &dpcd_data, | |
10838 | sizeof(dpcd_data))) { | |
10839 | capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; | |
10840 | } | |
10841 | ||
10842 | return capable; | |
10843 | } | |
f9b4f20c | 10844 | |
46db138d SW |
10845 | static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, |
10846 | unsigned int offset, | |
10847 | unsigned int total_length, | |
ae67558b | 10848 | u8 *data, |
46db138d SW |
10849 | unsigned int length, |
10850 | struct amdgpu_hdmi_vsdb_info *vsdb) | |
10851 | { | |
10852 | bool res; | |
10853 | union dmub_rb_cmd cmd; | |
10854 | struct dmub_cmd_send_edid_cea *input; | |
10855 | struct dmub_cmd_edid_cea_output *output; | |
10856 | ||
10857 | if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) | |
10858 | return false; | |
10859 | ||
10860 | memset(&cmd, 0, sizeof(cmd)); | |
10861 | ||
10862 | input = &cmd.edid_cea.data.input; | |
10863 | ||
10864 | cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; | |
10865 | cmd.edid_cea.header.sub_type = 0; | |
10866 | cmd.edid_cea.header.payload_bytes = | |
10867 | sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); | |
10868 | input->offset = offset; | |
10869 | input->length = length; | |
eb9e59eb | 10870 | input->cea_total_length = total_length; |
46db138d SW |
10871 | memcpy(input->payload, data, length); |
10872 | ||
e97cc04f | 10873 | res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); |
46db138d SW |
10874 | if (!res) { |
10875 | DRM_ERROR("EDID CEA parser failed\n"); | |
10876 | return false; | |
10877 | } | |
10878 | ||
10879 | output = &cmd.edid_cea.data.output; | |
10880 | ||
10881 | if (output->type == DMUB_CMD__EDID_CEA_ACK) { | |
10882 | if (!output->ack.success) { | |
10883 | DRM_ERROR("EDID CEA ack failed at offset %d\n", | |
10884 | output->ack.offset); | |
10885 | } | |
10886 | } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { | |
10887 | if (!output->amd_vsdb.vsdb_found) | |
10888 | return false; | |
10889 | ||
10890 | vsdb->freesync_supported = output->amd_vsdb.freesync_supported; | |
10891 | vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; | |
10892 | vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; | |
10893 | vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; | |
10894 | } else { | |
b76a8062 | 10895 | DRM_WARN("Unknown EDID CEA parser results\n"); |
46db138d SW |
10896 | return false; |
10897 | } | |
10898 | ||
10899 | return true; | |
10900 | } | |
10901 | ||
10902 | static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, | |
ae67558b | 10903 | u8 *edid_ext, int len, |
f9b4f20c SW |
10904 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10905 | { | |
10906 | int i; | |
f9b4f20c SW |
10907 | |
10908 | /* send extension block to DMCU for parsing */ | |
10909 | for (i = 0; i < len; i += 8) { | |
10910 | bool res; | |
10911 | int offset; | |
10912 | ||
10913 | /* send 8 bytes a time */ | |
46db138d | 10914 | if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) |
f9b4f20c SW |
10915 | return false; |
10916 | ||
10917 | if (i+8 == len) { | |
10918 | /* EDID block sent completed, expect result */ | |
10919 | int version, min_rate, max_rate; | |
10920 | ||
46db138d | 10921 | res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); |
f9b4f20c SW |
10922 | if (res) { |
10923 | /* amd vsdb found */ | |
10924 | vsdb_info->freesync_supported = 1; | |
10925 | vsdb_info->amd_vsdb_version = version; | |
10926 | vsdb_info->min_refresh_rate_hz = min_rate; | |
10927 | vsdb_info->max_refresh_rate_hz = max_rate; | |
10928 | return true; | |
10929 | } | |
10930 | /* not amd vsdb */ | |
10931 | return false; | |
10932 | } | |
10933 | ||
10934 | /* check for ack*/ | |
46db138d | 10935 | res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); |
f9b4f20c SW |
10936 | if (!res) |
10937 | return false; | |
10938 | } | |
10939 | ||
10940 | return false; | |
10941 | } | |
10942 | ||
46db138d | 10943 | static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, |
ae67558b | 10944 | u8 *edid_ext, int len, |
46db138d SW |
10945 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10946 | { | |
10947 | int i; | |
10948 | ||
10949 | /* send extension block to DMCU for parsing */ | |
10950 | for (i = 0; i < len; i += 8) { | |
10951 | /* send 8 bytes a time */ | |
10952 | if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) | |
10953 | return false; | |
10954 | } | |
10955 | ||
10956 | return vsdb_info->freesync_supported; | |
10957 | } | |
10958 | ||
10959 | static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, | |
ae67558b | 10960 | u8 *edid_ext, int len, |
46db138d SW |
10961 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10962 | { | |
10963 | struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); | |
53f4da73 | 10964 | bool ret; |
46db138d | 10965 | |
53f4da73 | 10966 | mutex_lock(&adev->dm.dc_lock); |
46db138d | 10967 | if (adev->dm.dmub_srv) |
53f4da73 | 10968 | ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); |
46db138d | 10969 | else |
53f4da73 SW |
10970 | ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); |
10971 | mutex_unlock(&adev->dm.dc_lock); | |
10972 | return ret; | |
46db138d SW |
10973 | } |
10974 | ||
ec8e59cb BL |
10975 | static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, |
10976 | struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) | |
10977 | { | |
10978 | u8 *edid_ext = NULL; | |
10979 | int i; | |
10980 | int j = 0; | |
10981 | ||
10982 | if (edid == NULL || edid->extensions == 0) | |
10983 | return -ENODEV; | |
10984 | ||
10985 | /* Find DisplayID extension */ | |
10986 | for (i = 0; i < edid->extensions; i++) { | |
10987 | edid_ext = (void *)(edid + (i + 1)); | |
10988 | if (edid_ext[0] == DISPLAYID_EXT) | |
10989 | break; | |
10990 | } | |
10991 | ||
10992 | while (j < EDID_LENGTH) { | |
10993 | struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; | |
10994 | unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); | |
10995 | ||
10996 | if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && | |
10997 | amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { | |
10998 | vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; | |
10999 | vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; | |
11000 | DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); | |
11001 | ||
11002 | return true; | |
11003 | } | |
11004 | j++; | |
11005 | } | |
11006 | ||
11007 | return false; | |
11008 | } | |
11009 | ||
7c7dd774 | 11010 | static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, |
f9b4f20c SW |
11011 | struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) |
11012 | { | |
ae67558b | 11013 | u8 *edid_ext = NULL; |
f9b4f20c SW |
11014 | int i; |
11015 | bool valid_vsdb_found = false; | |
11016 | ||
11017 | /*----- drm_find_cea_extension() -----*/ | |
11018 | /* No EDID or EDID extensions */ | |
11019 | if (edid == NULL || edid->extensions == 0) | |
7c7dd774 | 11020 | return -ENODEV; |
f9b4f20c SW |
11021 | |
11022 | /* Find CEA extension */ | |
11023 | for (i = 0; i < edid->extensions; i++) { | |
11024 | edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); | |
11025 | if (edid_ext[0] == CEA_EXT) | |
11026 | break; | |
11027 | } | |
11028 | ||
11029 | if (i == edid->extensions) | |
7c7dd774 | 11030 | return -ENODEV; |
f9b4f20c SW |
11031 | |
11032 | /*----- cea_db_offsets() -----*/ | |
11033 | if (edid_ext[0] != CEA_EXT) | |
7c7dd774 | 11034 | return -ENODEV; |
f9b4f20c SW |
11035 | |
11036 | valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); | |
7c7dd774 AB |
11037 | |
11038 | return valid_vsdb_found ? i : -ENODEV; | |
f9b4f20c SW |
11039 | } |
11040 | ||
c620e79b RS |
11041 | /** |
11042 | * amdgpu_dm_update_freesync_caps - Update Freesync capabilities | |
11043 | * | |
41ee1f18 AD |
11044 | * @connector: Connector to query. |
11045 | * @edid: EDID from monitor | |
c620e79b RS |
11046 | * |
11047 | * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep | |
11048 | * track of some of the display information in the internal data struct used by | |
11049 | * amdgpu_dm. This function checks which type of connector we need to set the | |
11050 | * FreeSync parameters. | |
11051 | */ | |
98e6436d | 11052 | void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
c620e79b | 11053 | struct edid *edid) |
e7b07cee | 11054 | { |
eb0709ba | 11055 | int i = 0; |
e7b07cee HW |
11056 | struct detailed_timing *timing; |
11057 | struct detailed_non_pixel *data; | |
11058 | struct detailed_data_monitor_range *range; | |
c84dec2f HW |
11059 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
11060 | to_amdgpu_dm_connector(connector); | |
bb47de73 | 11061 | struct dm_connector_state *dm_con_state = NULL; |
9ad54467 | 11062 | struct dc_sink *sink; |
e7b07cee | 11063 | |
534eee82 | 11064 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
f9b4f20c | 11065 | struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; |
c620e79b | 11066 | bool freesync_capable = false; |
5b49da02 | 11067 | enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; |
b830ebc9 | 11068 | |
8218d7f1 HW |
11069 | if (!connector->state) { |
11070 | DRM_ERROR("%s - Connector has no state", __func__); | |
bb47de73 | 11071 | goto update; |
8218d7f1 HW |
11072 | } |
11073 | ||
9b2fdc33 AP |
11074 | sink = amdgpu_dm_connector->dc_sink ? |
11075 | amdgpu_dm_connector->dc_sink : | |
11076 | amdgpu_dm_connector->dc_em_sink; | |
11077 | ||
11078 | if (!edid || !sink) { | |
98e6436d AK |
11079 | dm_con_state = to_dm_connector_state(connector->state); |
11080 | ||
11081 | amdgpu_dm_connector->min_vfreq = 0; | |
11082 | amdgpu_dm_connector->max_vfreq = 0; | |
11083 | amdgpu_dm_connector->pixel_clock_mhz = 0; | |
9b2fdc33 AP |
11084 | connector->display_info.monitor_range.min_vfreq = 0; |
11085 | connector->display_info.monitor_range.max_vfreq = 0; | |
11086 | freesync_capable = false; | |
98e6436d | 11087 | |
bb47de73 | 11088 | goto update; |
98e6436d AK |
11089 | } |
11090 | ||
8218d7f1 HW |
11091 | dm_con_state = to_dm_connector_state(connector->state); |
11092 | ||
e7b07cee | 11093 | if (!adev->dm.freesync_module) |
bb47de73 | 11094 | goto update; |
f9b4f20c | 11095 | |
9b2fdc33 AP |
11096 | if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT |
11097 | || sink->sink_signal == SIGNAL_TYPE_EDP) { | |
f9b4f20c SW |
11098 | bool edid_check_required = false; |
11099 | ||
11100 | if (edid) { | |
e7b07cee HW |
11101 | edid_check_required = is_dp_capable_without_timing_msa( |
11102 | adev->dm.dc, | |
c84dec2f | 11103 | amdgpu_dm_connector); |
e7b07cee | 11104 | } |
e7b07cee | 11105 | |
f9b4f20c SW |
11106 | if (edid_check_required == true && (edid->version > 1 || |
11107 | (edid->version == 1 && edid->revision > 1))) { | |
11108 | for (i = 0; i < 4; i++) { | |
e7b07cee | 11109 | |
f9b4f20c SW |
11110 | timing = &edid->detailed_timings[i]; |
11111 | data = &timing->data.other_data; | |
11112 | range = &data->data.range; | |
11113 | /* | |
11114 | * Check if monitor has continuous frequency mode | |
11115 | */ | |
11116 | if (data->type != EDID_DETAIL_MONITOR_RANGE) | |
11117 | continue; | |
11118 | /* | |
11119 | * Check for flag range limits only. If flag == 1 then | |
11120 | * no additional timing information provided. | |
11121 | * Default GTF, GTF Secondary curve and CVT are not | |
11122 | * supported | |
11123 | */ | |
11124 | if (range->flags != 1) | |
11125 | continue; | |
a0ffc3fd | 11126 | |
f9b4f20c SW |
11127 | amdgpu_dm_connector->min_vfreq = range->min_vfreq; |
11128 | amdgpu_dm_connector->max_vfreq = range->max_vfreq; | |
11129 | amdgpu_dm_connector->pixel_clock_mhz = | |
11130 | range->pixel_clock_mhz * 10; | |
a0ffc3fd | 11131 | |
f9b4f20c SW |
11132 | connector->display_info.monitor_range.min_vfreq = range->min_vfreq; |
11133 | connector->display_info.monitor_range.max_vfreq = range->max_vfreq; | |
e7b07cee | 11134 | |
f9b4f20c SW |
11135 | break; |
11136 | } | |
98e6436d | 11137 | |
f9b4f20c SW |
11138 | if (amdgpu_dm_connector->max_vfreq - |
11139 | amdgpu_dm_connector->min_vfreq > 10) { | |
98e6436d | 11140 | |
f9b4f20c SW |
11141 | freesync_capable = true; |
11142 | } | |
11143 | } | |
ec8e59cb BL |
11144 | parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); |
11145 | ||
11146 | if (vsdb_info.replay_mode) { | |
11147 | amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; | |
11148 | amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; | |
11149 | amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; | |
11150 | } | |
11151 | ||
9b2fdc33 | 11152 | } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
7c7dd774 AB |
11153 | i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); |
11154 | if (i >= 0 && vsdb_info.freesync_supported) { | |
f9b4f20c SW |
11155 | timing = &edid->detailed_timings[i]; |
11156 | data = &timing->data.other_data; | |
11157 | ||
11158 | amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; | |
5b49da02 SJK |
11159 | amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; |
11160 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) | |
11161 | freesync_capable = true; | |
11162 | ||
11163 | connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; | |
11164 | connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; | |
11165 | } | |
11166 | } | |
11167 | ||
11168 | as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); | |
11169 | ||
11170 | if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { | |
11171 | i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); | |
11172 | if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { | |
11173 | ||
11174 | amdgpu_dm_connector->pack_sdp_v1_3 = true; | |
11175 | amdgpu_dm_connector->as_type = as_type; | |
11176 | amdgpu_dm_connector->vsdb_info = vsdb_info; | |
11177 | ||
11178 | amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; | |
f9b4f20c SW |
11179 | amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; |
11180 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) | |
11181 | freesync_capable = true; | |
11182 | ||
11183 | connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; | |
11184 | connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; | |
e7b07cee HW |
11185 | } |
11186 | } | |
bb47de73 NK |
11187 | |
11188 | update: | |
11189 | if (dm_con_state) | |
11190 | dm_con_state->freesync_capable = freesync_capable; | |
11191 | ||
11192 | if (connector->vrr_capable_property) | |
11193 | drm_connector_set_vrr_capable_property(connector, | |
11194 | freesync_capable); | |
e7b07cee HW |
11195 | } |
11196 | ||
3d4e52d0 VL |
11197 | void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) |
11198 | { | |
1348969a | 11199 | struct amdgpu_device *adev = drm_to_adev(dev); |
3d4e52d0 VL |
11200 | struct dc *dc = adev->dm.dc; |
11201 | int i; | |
11202 | ||
11203 | mutex_lock(&adev->dm.dc_lock); | |
11204 | if (dc->current_state) { | |
11205 | for (i = 0; i < dc->current_state->stream_count; ++i) | |
11206 | dc->current_state->streams[i] | |
11207 | ->triggered_crtc_reset.enabled = | |
11208 | adev->dm.force_timing_sync; | |
11209 | ||
11210 | dm_enable_per_frame_crtc_master_sync(dc->current_state); | |
11211 | dc_trigger_sync(dc, dc->current_state); | |
11212 | } | |
11213 | mutex_unlock(&adev->dm.dc_lock); | |
11214 | } | |
9d83722d RS |
11215 | |
11216 | void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, | |
ae67558b | 11217 | u32 value, const char *func_name) |
9d83722d RS |
11218 | { |
11219 | #ifdef DM_CHECK_ADDR_0 | |
11220 | if (address == 0) { | |
5d72e247 HM |
11221 | drm_err(adev_to_drm(ctx->driver_context), |
11222 | "invalid register write. address = 0"); | |
9d83722d RS |
11223 | return; |
11224 | } | |
11225 | #endif | |
11226 | cgs_write_register(ctx->cgs_device, address, value); | |
11227 | trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); | |
11228 | } | |
11229 | ||
11230 | uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, | |
11231 | const char *func_name) | |
11232 | { | |
ae67558b | 11233 | u32 value; |
9d83722d RS |
11234 | #ifdef DM_CHECK_ADDR_0 |
11235 | if (address == 0) { | |
5d72e247 HM |
11236 | drm_err(adev_to_drm(ctx->driver_context), |
11237 | "invalid register read; address = 0\n"); | |
9d83722d RS |
11238 | return 0; |
11239 | } | |
11240 | #endif | |
11241 | ||
11242 | if (ctx->dmub_srv && | |
11243 | ctx->dmub_srv->reg_helper_offload.gather_in_progress && | |
11244 | !ctx->dmub_srv->reg_helper_offload.should_burst_write) { | |
11245 | ASSERT(false); | |
11246 | return 0; | |
11247 | } | |
11248 | ||
11249 | value = cgs_read_register(ctx->cgs_device, address); | |
11250 | ||
11251 | trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); | |
11252 | ||
11253 | return value; | |
11254 | } | |
81927e28 | 11255 | |
ead08b95 SW |
11256 | int amdgpu_dm_process_dmub_aux_transfer_sync( |
11257 | struct dc_context *ctx, | |
11258 | unsigned int link_index, | |
11259 | struct aux_payload *payload, | |
11260 | enum aux_return_code_type *operation_result) | |
88f52b1f JS |
11261 | { |
11262 | struct amdgpu_device *adev = ctx->driver_context; | |
88f52b1f | 11263 | struct dmub_notification *p_notify = adev->dm.dmub_notify; |
ead08b95 | 11264 | int ret = -1; |
88f52b1f | 11265 | |
ead08b95 SW |
11266 | mutex_lock(&adev->dm.dpia_aux_lock); |
11267 | if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { | |
11268 | *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; | |
11269 | goto out; | |
3335a135 | 11270 | } |
ead08b95 SW |
11271 | |
11272 | if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { | |
11273 | DRM_ERROR("wait_for_completion_timeout timeout!"); | |
11274 | *operation_result = AUX_RET_ERROR_TIMEOUT; | |
11275 | goto out; | |
11276 | } | |
11277 | ||
11278 | if (p_notify->result != AUX_RET_SUCCESS) { | |
11279 | /* | |
11280 | * Transient states before tunneling is enabled could | |
11281 | * lead to this error. We can ignore this for now. | |
11282 | */ | |
11283 | if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { | |
11284 | DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", | |
11285 | payload->address, payload->length, | |
11286 | p_notify->result); | |
88f52b1f | 11287 | } |
ead08b95 SW |
11288 | *operation_result = AUX_RET_ERROR_INVALID_REPLY; |
11289 | goto out; | |
11290 | } | |
11291 | ||
11292 | ||
11293 | payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; | |
11294 | if (!payload->write && p_notify->aux_reply.length && | |
11295 | (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { | |
11296 | ||
11297 | if (payload->length != p_notify->aux_reply.length) { | |
11298 | DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", | |
11299 | p_notify->aux_reply.length, | |
11300 | payload->address, payload->length); | |
11301 | *operation_result = AUX_RET_ERROR_INVALID_REPLY; | |
11302 | goto out; | |
88f52b1f | 11303 | } |
ead08b95 SW |
11304 | |
11305 | memcpy(payload->data, p_notify->aux_reply.data, | |
11306 | p_notify->aux_reply.length); | |
88f52b1f JS |
11307 | } |
11308 | ||
ead08b95 SW |
11309 | /* success */ |
11310 | ret = p_notify->aux_reply.length; | |
11311 | *operation_result = p_notify->result; | |
11312 | out: | |
0cf8307a | 11313 | reinit_completion(&adev->dm.dmub_aux_transfer_done); |
ead08b95 SW |
11314 | mutex_unlock(&adev->dm.dpia_aux_lock); |
11315 | return ret; | |
88f52b1f JS |
11316 | } |
11317 | ||
ead08b95 SW |
11318 | int amdgpu_dm_process_dmub_set_config_sync( |
11319 | struct dc_context *ctx, | |
11320 | unsigned int link_index, | |
11321 | struct set_config_cmd_payload *payload, | |
11322 | enum set_config_status *operation_result) | |
81927e28 JS |
11323 | { |
11324 | struct amdgpu_device *adev = ctx->driver_context; | |
ead08b95 SW |
11325 | bool is_cmd_complete; |
11326 | int ret; | |
81927e28 | 11327 | |
ead08b95 SW |
11328 | mutex_lock(&adev->dm.dpia_aux_lock); |
11329 | is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, | |
11330 | link_index, payload, adev->dm.dmub_notify); | |
88f52b1f | 11331 | |
ead08b95 SW |
11332 | if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { |
11333 | ret = 0; | |
11334 | *operation_result = adev->dm.dmub_notify->sc_status; | |
11335 | } else { | |
9e3a50d2 | 11336 | DRM_ERROR("wait_for_completion_timeout timeout!"); |
ead08b95 SW |
11337 | ret = -1; |
11338 | *operation_result = SET_CONFIG_UNKNOWN_ERROR; | |
81927e28 JS |
11339 | } |
11340 | ||
0cf8307a SW |
11341 | if (!is_cmd_complete) |
11342 | reinit_completion(&adev->dm.dmub_aux_transfer_done); | |
ead08b95 SW |
11343 | mutex_unlock(&adev->dm.dpia_aux_lock); |
11344 | return ret; | |
81927e28 | 11345 | } |
1edf5ae1 | 11346 | |
e97cc04f JP |
11347 | bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) |
11348 | { | |
11349 | return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); | |
11350 | } | |
11351 | ||
11352 | bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) | |
11353 | { | |
11354 | return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); | |
11355 | } |