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Merge remote-tracking branches 'asoc/topic/wm8753', 'asoc/topic/wm8770', 'asoc/topic...
[linux-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
ad941f7a
FX		 62#include "dcn/dcn_1_0_offset.h"
63#include "dcn/dcn_1_0_sh_mask.h"
fb960bd2 64#include "soc15ip.h"
ff5ef992
AD		 65
66#include "soc15_common.h"
67#endif
68
e7b07cee
HW		 69#include "modules/inc/mod_freesync.h"
70
71#include "i2caux_interface.h"
72
7578ecda
AD		 73/* basic init/fini API */
74static int amdgpu_dm_init(struct amdgpu_device *adev);
75static void amdgpu_dm_fini(struct amdgpu_device *adev);
76
77/* initializes drm_device display related structures, based on the information
78 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
79 * drm_encoder, drm_mode_config
80 *
81 * Returns 0 on success
82 */
83static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
84/* removes and deallocates the drm structures, created by the above function */
85static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
86
87static void
88amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
89
90static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
91 struct amdgpu_plane *aplane,
92 unsigned long possible_crtcs);
93static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
94 struct drm_plane *plane,
95 uint32_t link_index);
96static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
97 struct amdgpu_dm_connector *amdgpu_dm_connector,
98 uint32_t link_index,
99 struct amdgpu_encoder *amdgpu_encoder);
100static int amdgpu_dm_encoder_init(struct drm_device *dev,
101 struct amdgpu_encoder *aencoder,
102 uint32_t link_index);
103
104static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
105
106static int amdgpu_dm_atomic_commit(struct drm_device *dev,
107 struct drm_atomic_state *state,
108 bool nonblock);
109
110static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
111
112static int amdgpu_dm_atomic_check(struct drm_device *dev,
113 struct drm_atomic_state *state);
114
115
116
e7b07cee 117
e04a6123 118static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 119 DRM_PLANE_TYPE_PRIMARY,
120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125};
126
e04a6123 127static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 128 DRM_PLANE_TYPE_PRIMARY,
129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
132};
133
e04a6123 134static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 135 DRM_PLANE_TYPE_PRIMARY,
136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
138};
139
4562236b
HW		 140/*
141 * dm_vblank_get_counter
142 *
143 * @brief
144 * Get counter for number of vertical blanks
145 *
146 * @param
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
149 *
150 * @return
151 * Counter for vertical blanks
152 */
153static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
154{
155 if (crtc >= adev->mode_info.num_crtc)
156 return 0;
157 else {
158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
160 acrtc->base.state);
4562236b 161
da5c47f6
AG		 162
163 if (acrtc_state->stream == NULL) {
0971c40e
HW		 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
165 crtc);
4562236b
HW		 166 return 0;
167 }
168
da5c47f6 169 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 170 }
171}
172
173static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 174 u32 *vbl, u32 *position)
4562236b 175{
81c50963
ST		 176 uint32_t v_blank_start, v_blank_end, h_position, v_position;
177
4562236b
HW		 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
179 return -EINVAL;
180 else {
181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
183 acrtc->base.state);
4562236b 184
da5c47f6 185 if (acrtc_state->stream == NULL) {
0971c40e
HW		 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
187 crtc);
4562236b
HW		 188 return 0;
189 }
190
81c50963
ST		 191 /*
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
194 */
da5c47f6 195 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 196 &v_blank_start,
197 &v_blank_end,
198 &h_position,
199 &v_position);
200
e806208d
AG		 201 *position = v_position | (h_position << 16);
202 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 203 }
204
205 return 0;
206}
207
208static bool dm_is_idle(void *handle)
209{
210 /* XXX todo */
211 return true;
212}
213
214static int dm_wait_for_idle(void *handle)
215{
216 /* XXX todo */
217 return 0;
218}
219
220static bool dm_check_soft_reset(void *handle)
221{
222 return false;
223}
224
225static int dm_soft_reset(void *handle)
226{
227 /* XXX todo */
228 return 0;
229}
230
3ee6b26b
AD		 231static struct amdgpu_crtc *
232get_crtc_by_otg_inst(struct amdgpu_device *adev,
233 int otg_inst)
4562236b
HW		 234{
235 struct drm_device *dev = adev->ddev;
236 struct drm_crtc *crtc;
237 struct amdgpu_crtc *amdgpu_crtc;
238
239 /*
240 * following if is check inherited from both functions where this one is
241 * used now. Need to be checked why it could happen.
242 */
243 if (otg_inst == -1) {
244 WARN_ON(1);
245 return adev->mode_info.crtcs[0];
246 }
247
248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
249 amdgpu_crtc = to_amdgpu_crtc(crtc);
250
251 if (amdgpu_crtc->otg_inst == otg_inst)
252 return amdgpu_crtc;
253 }
254
255 return NULL;
256}
257
258static void dm_pflip_high_irq(void *interrupt_params)
259{
4562236b
HW		 260 struct amdgpu_crtc *amdgpu_crtc;
261 struct common_irq_params *irq_params = interrupt_params;
262 struct amdgpu_device *adev = irq_params->adev;
263 unsigned long flags;
264
265 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
266
267 /* IRQ could occur when in initial stage */
268 /*TODO work and BO cleanup */
269 if (amdgpu_crtc == NULL) {
270 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
271 return;
272 }
273
274 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 275
276 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
277 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
278 amdgpu_crtc->pflip_status,
279 AMDGPU_FLIP_SUBMITTED,
280 amdgpu_crtc->crtc_id,
281 amdgpu_crtc);
282 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
283 return;
284 }
285
4562236b
HW		 286
287 /* wakeup usersapce */
1159898a 288 if (amdgpu_crtc->event) {
753c66c9
MK		 289 /* Update to correct count/ts if racing with vblank irq */
290 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
291
54f5499a 292 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 293
54f5499a
AG		 294 /* page flip completed. clean up */
295 amdgpu_crtc->event = NULL;
1159898a 296
54f5499a
AG		 297 } else
298 WARN_ON(1);
4562236b 299
54f5499a 300 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 301 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
302
54f5499a
AG		 303 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
304 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 305
306 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 307}
308
309static void dm_crtc_high_irq(void *interrupt_params)
310{
311 struct common_irq_params *irq_params = interrupt_params;
312 struct amdgpu_device *adev = irq_params->adev;
313 uint8_t crtc_index = 0;
314 struct amdgpu_crtc *acrtc;
315
b57de80a 316 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 317
318 if (acrtc)
319 crtc_index = acrtc->crtc_id;
320
321 drm_handle_vblank(adev->ddev, crtc_index);
322}
323
324static int dm_set_clockgating_state(void *handle,
325 enum amd_clockgating_state state)
326{
327 return 0;
328}
329
330static int dm_set_powergating_state(void *handle,
331 enum amd_powergating_state state)
332{
333 return 0;
334}
335
336/* Prototypes of private functions */
337static int dm_early_init(void* handle);
338
339static void hotplug_notify_work_func(struct work_struct *work)
340{
341 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
342 struct drm_device *dev = dm->ddev;
343
344 drm_kms_helper_hotplug_event(dev);
345}
346
6ef39a62 347#if defined(CONFIG_DRM_AMD_DC_FBC)
a32e24b4
RL		 348#include "dal_asic_id.h"
349/* Allocate memory for FBC compressed data */
350/* TODO: Dynamic allocation */
351#define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
352
7578ecda 353static void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
a32e24b4
RL		 354{
355 int r;
356 struct dm_comressor_info *compressor = &adev->dm.compressor;
357
358 if (!compressor->bo_ptr) {
359 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
360 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
361 &compressor->gpu_addr, &compressor->cpu_addr);
362
363 if (r)
364 DRM_ERROR("DM: Failed to initialize fbc\n");
365 }
366
367}
368#endif
369
370
4562236b
HW		 371/* Init display KMS
372 *
373 * Returns 0 on success
374 */
7578ecda 375static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 376{
377 struct dc_init_data init_data;
378 adev->dm.ddev = adev->ddev;
379 adev->dm.adev = adev;
380
4562236b
HW		 381 /* Zero all the fields */
382 memset(&init_data, 0, sizeof(init_data));
383
384 /* initialize DAL's lock (for SYNC context use) */
385 spin_lock_init(&adev->dm.dal_lock);
386
387 /* initialize DAL's mutex */
388 mutex_init(&adev->dm.dal_mutex);
389
390 if(amdgpu_dm_irq_init(adev)) {
391 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
392 goto error;
393 }
394
395 init_data.asic_id.chip_family = adev->family;
396
397 init_data.asic_id.pci_revision_id = adev->rev_id;
398 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
399
400 init_data.asic_id.vram_width = adev->mc.vram_width;
401 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
402 init_data.asic_id.atombios_base_address =
403 adev->mode_info.atom_context->bios;
404
405 init_data.driver = adev;
406
407 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
408
409 if (!adev->dm.cgs_device) {
410 DRM_ERROR("amdgpu: failed to create cgs device.\n");
411 goto error;
412 }
413
414 init_data.cgs_device = adev->dm.cgs_device;
415
416 adev->dm.dal = NULL;
417
418 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
419
f1ad2f5e
HW		 420 if (amdgpu_dc_log)
421 init_data.log_mask = DC_DEFAULT_LOG_MASK;
422 else
423 init_data.log_mask = DC_MIN_LOG_MASK;
01a526f3 424
6ef39a62 425#if defined(CONFIG_DRM_AMD_DC_FBC)
a32e24b4
RL		 426 if (adev->family == FAMILY_CZ)
427 amdgpu_dm_initialize_fbc(adev);
428 init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
429#endif
4562236b
HW		 430 /* Display Core create. */
431 adev->dm.dc = dc_create(&init_data);
432
423788c7 433 if (adev->dm.dc) {
76121231 434 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 435 } else {
76121231 436 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 437 goto error;
438 }
4562236b
HW		 439
440 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
441
442 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
443 if (!adev->dm.freesync_module) {
444 DRM_ERROR(
445 "amdgpu: failed to initialize freesync_module.\n");
446 } else
f1ad2f5e 447 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 448 adev->dm.freesync_module);
449
450 if (amdgpu_dm_initialize_drm_device(adev)) {
451 DRM_ERROR(
452 "amdgpu: failed to initialize sw for display support.\n");
453 goto error;
454 }
455
456 /* Update the actual used number of crtc */
457 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
458
459 /* TODO: Add_display_info? */
460
461 /* TODO use dynamic cursor width */
ce75805e
AG		 462 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
463 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 464
465 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
466 DRM_ERROR(
467 "amdgpu: failed to initialize sw for display support.\n");
468 goto error;
469 }
470
f1ad2f5e 471 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 472
473 return 0;
474error:
475 amdgpu_dm_fini(adev);
476
477 return -1;
478}
479
7578ecda 480static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 481{
482 amdgpu_dm_destroy_drm_device(&adev->dm);
483 /*
484 * TODO: pageflip, vlank interrupt
485 *
486 * amdgpu_dm_irq_fini(adev);
487 */
488
489 if (adev->dm.cgs_device) {
490 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
491 adev->dm.cgs_device = NULL;
492 }
493 if (adev->dm.freesync_module) {
494 mod_freesync_destroy(adev->dm.freesync_module);
495 adev->dm.freesync_module = NULL;
496 }
497 /* DC Destroy TODO: Replace destroy DAL */
21de3396 498 if (adev->dm.dc)
4562236b 499 dc_destroy(&adev->dm.dc);
4562236b
HW		 500 return;
501}
502
4562236b
HW		 503static int dm_sw_init(void *handle)
504{
505 return 0;
506}
507
508static int dm_sw_fini(void *handle)
509{
510 return 0;
511}
512
7abcf6b5 513static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 514{
c84dec2f 515 struct amdgpu_dm_connector *aconnector;
4562236b 516 struct drm_connector *connector;
7abcf6b5 517 int ret = 0;
4562236b
HW		 518
519 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
520
521 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 522 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 523 if (aconnector->dc_link->type == dc_connection_mst_branch &&
524 aconnector->mst_mgr.aux) {
f1ad2f5e 525 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 526 aconnector, aconnector->base.base.id);
527
528 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
529 if (ret < 0) {
530 DRM_ERROR("DM_MST: Failed to start MST\n");
531 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
532 return ret;
4562236b 533 }
7abcf6b5 534 }
4562236b
HW		 535 }
536
537 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 538 return ret;
539}
540
541static int dm_late_init(void *handle)
542{
543 struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
7abcf6b5 544
33be2785 545 return detect_mst_link_for_all_connectors(dev);
4562236b
HW		 546}
547
548static void s3_handle_mst(struct drm_device *dev, bool suspend)
549{
c84dec2f 550 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 551 struct drm_connector *connector;
552
553 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
554
555 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 556 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 557 if (aconnector->dc_link->type == dc_connection_mst_branch &&
558 !aconnector->mst_port) {
559
560 if (suspend)
561 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
562 else
563 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
564 }
565 }
566
567 drm_modeset_unlock(&dev->mode_config.connection_mutex);
568}
569
570static int dm_hw_init(void *handle)
571{
572 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
573 /* Create DAL display manager */
574 amdgpu_dm_init(adev);
4562236b
HW		 575 amdgpu_dm_hpd_init(adev);
576
4562236b
HW		 577 return 0;
578}
579
580static int dm_hw_fini(void *handle)
581{
582 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
583
584 amdgpu_dm_hpd_fini(adev);
585
586 amdgpu_dm_irq_fini(adev);
21de3396 587 amdgpu_dm_fini(adev);
4562236b
HW		 588 return 0;
589}
590
591static int dm_suspend(void *handle)
592{
593 struct amdgpu_device *adev = handle;
594 struct amdgpu_display_manager *dm = &adev->dm;
595 int ret = 0;
4562236b
HW		 596
597 s3_handle_mst(adev->ddev, true);
598
4562236b
HW		 599 amdgpu_dm_irq_suspend(adev);
600
0a214e2f 601 WARN_ON(adev->dm.cached_state);
a3621485
AG		 602 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
603
32f5062d 604 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 605
606 return ret;
607}
608
1daf8c63
AD		 609static struct amdgpu_dm_connector *
610amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
611 struct drm_crtc *crtc)
4562236b
HW		 612{
613 uint32_t i;
c2cea706 614 struct drm_connector_state *new_con_state;
4562236b
HW		 615 struct drm_connector *connector;
616 struct drm_crtc *crtc_from_state;
617
c2cea706
LSL		 618 for_each_new_connector_in_state(state, connector, new_con_state, i) {
619 crtc_from_state = new_con_state->crtc;
4562236b
HW		 620
621 if (crtc_from_state == crtc)
c84dec2f 622 return to_amdgpu_dm_connector(connector);
4562236b
HW		 623 }
624
625 return NULL;
626}
627
4562236b
HW		 628static int dm_resume(void *handle)
629{
630 struct amdgpu_device *adev = handle;
631 struct amdgpu_display_manager *dm = &adev->dm;
09c381e0 632 int ret = 0;
4562236b
HW		 633
634 /* power on hardware */
1fb0c9cc 635 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
4562236b 636
09c381e0
ML		 637 ret = amdgpu_dm_display_resume(adev);
638 return ret;
4562236b
HW		 639}
640
1ecfc3da 641int amdgpu_dm_display_resume(struct amdgpu_device *adev)
4562236b
HW		 642{
643 struct drm_device *ddev = adev->ddev;
644 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 645 struct amdgpu_dm_connector *aconnector;
4562236b 646 struct drm_connector *connector;
4562236b 647 struct drm_crtc *crtc;
c2cea706 648 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 649 struct dm_crtc_state *dm_new_crtc_state;
650 struct drm_plane *plane;
651 struct drm_plane_state *new_plane_state;
652 struct dm_plane_state *dm_new_plane_state;
653
a3621485
AG		 654 int ret = 0;
655 int i;
4562236b
HW		 656
657 /* program HPD filter */
658 dc_resume(dm->dc);
659
660 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
661 s3_handle_mst(ddev, false);
662
663 /*
664 * early enable HPD Rx IRQ, should be done before set mode as short
665 * pulse interrupts are used for MST
666 */
667 amdgpu_dm_irq_resume_early(adev);
668
4562236b
HW		 669 /* Do detection*/
670 list_for_each_entry(connector,
671 &ddev->mode_config.connector_list, head) {
c84dec2f 672 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 673
674 /*
675 * this is the case when traversing through already created
676 * MST connectors, should be skipped
677 */
678 if (aconnector->mst_port)
679 continue;
680
03ea364c 681 mutex_lock(&aconnector->hpd_lock);
8f38b66c 682 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 683
684 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
685 aconnector->fake_enable = false;
686
4562236b
HW		 687 aconnector->dc_sink = NULL;
688 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 689 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 690 }
691
a3621485 692 /* Force mode set in atomic comit */
c2cea706
LSL		 693 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
694 new_crtc_state->active_changed = true;
4f346e65 695
fcb4019e
LSL		 696 /*
697 * atomic_check is expected to create the dc states. We need to release
698 * them here, since they were duplicated as part of the suspend
699 * procedure.
700 */
701 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
702 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
703 if (dm_new_crtc_state->stream) {
704 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
705 dc_stream_release(dm_new_crtc_state->stream);
706 dm_new_crtc_state->stream = NULL;
707 }
708 }
709
710 for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
711 dm_new_plane_state = to_dm_plane_state(new_plane_state);
712 if (dm_new_plane_state->dc_state) {
713 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
714 dc_plane_state_release(dm_new_plane_state->dc_state);
715 dm_new_plane_state->dc_state = NULL;
716 }
717 }
718
a3621485 719 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 720
0a214e2f
AG		 721 adev->dm.cached_state = NULL;
722
9faa4237 723 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 724
725 return ret;
726}
727
728static const struct amd_ip_funcs amdgpu_dm_funcs = {
729 .name = "dm",
730 .early_init = dm_early_init,
7abcf6b5 731 .late_init = dm_late_init,
4562236b
HW		 732 .sw_init = dm_sw_init,
733 .sw_fini = dm_sw_fini,
734 .hw_init = dm_hw_init,
735 .hw_fini = dm_hw_fini,
736 .suspend = dm_suspend,
737 .resume = dm_resume,
738 .is_idle = dm_is_idle,
739 .wait_for_idle = dm_wait_for_idle,
740 .check_soft_reset = dm_check_soft_reset,
741 .soft_reset = dm_soft_reset,
742 .set_clockgating_state = dm_set_clockgating_state,
743 .set_powergating_state = dm_set_powergating_state,
744};
745
746const struct amdgpu_ip_block_version dm_ip_block =
747{
748 .type = AMD_IP_BLOCK_TYPE_DCE,
749 .major = 1,
750 .minor = 0,
751 .rev = 0,
752 .funcs = &amdgpu_dm_funcs,
753};
754
ca3268c4 755
7578ecda 756static struct drm_atomic_state *
ca3268c4
HW		 757dm_atomic_state_alloc(struct drm_device *dev)
758{
759 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
760
1dc90497 761 if (!state)
ca3268c4 762 return NULL;
1dc90497
AG		 763
764 if (drm_atomic_state_init(dev, &state->base) < 0)
765 goto fail;
766
ca3268c4 767 return &state->base;
1dc90497
AG		 768
769fail:
770 kfree(state);
771 return NULL;
ca3268c4
HW		 772}
773
0a323b84
AG		 774static void
775dm_atomic_state_clear(struct drm_atomic_state *state)
776{
777 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
778
779 if (dm_state->context) {
608ac7bb 780 dc_release_state(dm_state->context);
0a323b84
AG		 781 dm_state->context = NULL;
782 }
783
784 drm_atomic_state_default_clear(state);
785}
786
787static void
788dm_atomic_state_alloc_free(struct drm_atomic_state *state)
789{
790 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
791 drm_atomic_state_default_release(state);
792 kfree(dm_state);
793}
794
b3663f70 795static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
a49dcb88 796 .fb_create = amdgpu_user_framebuffer_create,
366c1baa 797 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 798 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 799 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 800 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 801 .atomic_state_clear = dm_atomic_state_clear,
802 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 803};
804
805static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
806 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 807};
808
7578ecda 809static void
3ee6b26b 810amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 811{
812 struct drm_connector *connector = &aconnector->base;
813 struct drm_device *dev = connector->dev;
b73a22d3 814 struct dc_sink *sink;
4562236b
HW		 815
816 /* MST handled by drm_mst framework */
817 if (aconnector->mst_mgr.mst_state == true)
818 return;
819
820
821 sink = aconnector->dc_link->local_sink;
822
823 /* Edid mgmt connector gets first update only in mode_valid hook and then
824 * the connector sink is set to either fake or physical sink depends on link status.
825 * don't do it here if u are during boot
826 */
827 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
828 && aconnector->dc_em_sink) {
829
ab2541b6 830 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 831 * because on resume connecotr->sink is set ti NULL
832 */
833 mutex_lock(&dev->mode_config.mutex);
834
835 if (sink) {
922aa1e1 836 if (aconnector->dc_sink) {
4562236b
HW		 837 amdgpu_dm_remove_sink_from_freesync_module(
838 connector);
922aa1e1
AG		 839 /* retain and release bellow are used for
840 * bump up refcount for sink because the link don't point
841 * to it anymore after disconnect so on next crtc to connector
842 * reshuffle by UMD we will get into unwanted dc_sink release
843 */
844 if (aconnector->dc_sink != aconnector->dc_em_sink)
845 dc_sink_release(aconnector->dc_sink);
846 }
4562236b
HW		 847 aconnector->dc_sink = sink;
848 amdgpu_dm_add_sink_to_freesync_module(
849 connector, aconnector->edid);
850 } else {
851 amdgpu_dm_remove_sink_from_freesync_module(connector);
852 if (!aconnector->dc_sink)
853 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 854 else if (aconnector->dc_sink != aconnector->dc_em_sink)
855 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 856 }
857
858 mutex_unlock(&dev->mode_config.mutex);
859 return;
860 }
861
862 /*
863 * TODO: temporary guard to look for proper fix
864 * if this sink is MST sink, we should not do anything
865 */
866 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
867 return;
868
869 if (aconnector->dc_sink == sink) {
870 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
871 * Do nothing!! */
f1ad2f5e 872 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 873 aconnector->connector_id);
874 return;
875 }
876
f1ad2f5e 877 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 878 aconnector->connector_id, aconnector->dc_sink, sink);
879
880 mutex_lock(&dev->mode_config.mutex);
881
882 /* 1. Update status of the drm connector
883 * 2. Send an event and let userspace tell us what to do */
884 if (sink) {
885 /* TODO: check if we still need the S3 mode update workaround.
886 * If yes, put it here. */
887 if (aconnector->dc_sink)
888 amdgpu_dm_remove_sink_from_freesync_module(
889 connector);
890
891 aconnector->dc_sink = sink;
900b3cb1 892 if (sink->dc_edid.length == 0) {
4562236b 893 aconnector->edid = NULL;
900b3cb1 894 } else {
4562236b
HW		 895 aconnector->edid =
896 (struct edid *) sink->dc_edid.raw_edid;
897
898
899 drm_mode_connector_update_edid_property(connector,
900 aconnector->edid);
901 }
902 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
903
904 } else {
905 amdgpu_dm_remove_sink_from_freesync_module(connector);
906 drm_mode_connector_update_edid_property(connector, NULL);
907 aconnector->num_modes = 0;
908 aconnector->dc_sink = NULL;
909 }
910
911 mutex_unlock(&dev->mode_config.mutex);
912}
913
914static void handle_hpd_irq(void *param)
915{
c84dec2f 916 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 917 struct drm_connector *connector = &aconnector->base;
918 struct drm_device *dev = connector->dev;
919
920 /* In case of failure or MST no need to update connector status or notify the OS
921 * since (for MST case) MST does this in it's own context.
922 */
923 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 924
925 if (aconnector->fake_enable)
926 aconnector->fake_enable = false;
927
8f38b66c 928 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 929 amdgpu_dm_update_connector_after_detect(aconnector);
930
931
932 drm_modeset_lock_all(dev);
933 dm_restore_drm_connector_state(dev, connector);
934 drm_modeset_unlock_all(dev);
935
936 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
937 drm_kms_helper_hotplug_event(dev);
938 }
939 mutex_unlock(&aconnector->hpd_lock);
940
941}
942
c84dec2f 943static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 944{
945 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
946 uint8_t dret;
947 bool new_irq_handled = false;
948 int dpcd_addr;
949 int dpcd_bytes_to_read;
950
951 const int max_process_count = 30;
952 int process_count = 0;
953
954 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
955
956 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
957 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
958 /* DPCD 0x200 - 0x201 for downstream IRQ */
959 dpcd_addr = DP_SINK_COUNT;
960 } else {
961 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
962 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
963 dpcd_addr = DP_SINK_COUNT_ESI;
964 }
965
966 dret = drm_dp_dpcd_read(
967 &aconnector->dm_dp_aux.aux,
968 dpcd_addr,
969 esi,
970 dpcd_bytes_to_read);
971
972 while (dret == dpcd_bytes_to_read &&
973 process_count < max_process_count) {
974 uint8_t retry;
975 dret = 0;
976
977 process_count++;
978
f1ad2f5e 979 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 980 /* handle HPD short pulse irq */
981 if (aconnector->mst_mgr.mst_state)
982 drm_dp_mst_hpd_irq(
983 &aconnector->mst_mgr,
984 esi,
985 &new_irq_handled);
4562236b
HW		 986
987 if (new_irq_handled) {
988 /* ACK at DPCD to notify down stream */
989 const int ack_dpcd_bytes_to_write =
990 dpcd_bytes_to_read - 1;
991
992 for (retry = 0; retry < 3; retry++) {
993 uint8_t wret;
994
995 wret = drm_dp_dpcd_write(
996 &aconnector->dm_dp_aux.aux,
997 dpcd_addr + 1,
998 &esi[1],
999 ack_dpcd_bytes_to_write);
1000 if (wret == ack_dpcd_bytes_to_write)
1001 break;
1002 }
1003
1004 /* check if there is new irq to be handle */
1005 dret = drm_dp_dpcd_read(
1006 &aconnector->dm_dp_aux.aux,
1007 dpcd_addr,
1008 esi,
1009 dpcd_bytes_to_read);
1010
1011 new_irq_handled = false;
d4a6e8a9 1012 } else {
4562236b 1013 break;
d4a6e8a9 1014 }
4562236b
HW		 1015 }
1016
1017 if (process_count == max_process_count)
f1ad2f5e 1018 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1019}
1020
1021static void handle_hpd_rx_irq(void *param)
1022{
c84dec2f 1023 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1024 struct drm_connector *connector = &aconnector->base;
1025 struct drm_device *dev = connector->dev;
53cbf65c 1026 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 1027 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1028
1029 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1030 * conflict, after implement i2c helper, this mutex should be
1031 * retired.
1032 */
53cbf65c 1033 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1034 mutex_lock(&aconnector->hpd_lock);
1035
53cbf65c 1036 if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
4562236b
HW		 1037 !is_mst_root_connector) {
1038 /* Downstream Port status changed. */
53cbf65c 1039 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
c36aaba6
RL		 1040
1041 if (aconnector->fake_enable)
1042 aconnector->fake_enable = false;
1043
4562236b
HW		 1044 amdgpu_dm_update_connector_after_detect(aconnector);
1045
1046
1047 drm_modeset_lock_all(dev);
1048 dm_restore_drm_connector_state(dev, connector);
1049 drm_modeset_unlock_all(dev);
1050
1051 drm_kms_helper_hotplug_event(dev);
1052 }
1053 }
1054 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1055 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1056 dm_handle_hpd_rx_irq(aconnector);
1057
53cbf65c 1058 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1059 mutex_unlock(&aconnector->hpd_lock);
1060}
1061
1062static void register_hpd_handlers(struct amdgpu_device *adev)
1063{
1064 struct drm_device *dev = adev->ddev;
1065 struct drm_connector *connector;
c84dec2f 1066 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1067 const struct dc_link *dc_link;
1068 struct dc_interrupt_params int_params = {0};
1069
1070 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1071 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1072
1073 list_for_each_entry(connector,
1074 &dev->mode_config.connector_list, head) {
1075
c84dec2f 1076 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1077 dc_link = aconnector->dc_link;
1078
1079 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1080 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1081 int_params.irq_source = dc_link->irq_source_hpd;
1082
1083 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1084 handle_hpd_irq,
1085 (void *) aconnector);
1086 }
1087
1088 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1089
1090 /* Also register for DP short pulse (hpd_rx). */
1091 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1092 int_params.irq_source = dc_link->irq_source_hpd_rx;
1093
1094 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1095 handle_hpd_rx_irq,
1096 (void *) aconnector);
1097 }
1098 }
1099}
1100
1101/* Register IRQ sources and initialize IRQ callbacks */
1102static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1103{
1104 struct dc *dc = adev->dm.dc;
1105 struct common_irq_params *c_irq_params;
1106 struct dc_interrupt_params int_params = {0};
1107 int r;
1108 int i;
2c8ad2d5
AD		 1109 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1110
ff5ef992
AD		 1111 if (adev->asic_type == CHIP_VEGA10 ||
1112 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1113 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1114
1115 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1116 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1117
1118 /* Actions of amdgpu_irq_add_id():
1119 * 1. Register a set() function with base driver.
1120 * Base driver will call set() function to enable/disable an
1121 * interrupt in DC hardware.
1122 * 2. Register amdgpu_dm_irq_handler().
1123 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1124 * coming from DC hardware.
1125 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1126 * for acknowledging and handling. */
1127
b57de80a 1128 /* Use VBLANK interrupt */
e9029155 1129 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1130 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1131 if (r) {
1132 DRM_ERROR("Failed to add crtc irq id!\n");
1133 return r;
1134 }
1135
1136 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1137 int_params.irq_source =
3d761e79 1138 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1139
b57de80a 1140 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1141
1142 c_irq_params->adev = adev;
1143 c_irq_params->irq_src = int_params.irq_source;
1144
1145 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1146 dm_crtc_high_irq, c_irq_params);
1147 }
1148
3d761e79 1149 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1150 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1151 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1152 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1153 if (r) {
1154 DRM_ERROR("Failed to add page flip irq id!\n");
1155 return r;
1156 }
1157
1158 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1159 int_params.irq_source =
1160 dc_interrupt_to_irq_source(dc, i, 0);
1161
1162 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1163
1164 c_irq_params->adev = adev;
1165 c_irq_params->irq_src = int_params.irq_source;
1166
1167 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1168 dm_pflip_high_irq, c_irq_params);
1169
1170 }
1171
1172 /* HPD */
2c8ad2d5
AD		 1173 r = amdgpu_irq_add_id(adev, client_id,
1174 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1175 if (r) {
1176 DRM_ERROR("Failed to add hpd irq id!\n");
1177 return r;
1178 }
1179
1180 register_hpd_handlers(adev);
1181
1182 return 0;
1183}
1184
ff5ef992
AD		 1185#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1186/* Register IRQ sources and initialize IRQ callbacks */
1187static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1188{
1189 struct dc *dc = adev->dm.dc;
1190 struct common_irq_params *c_irq_params;
1191 struct dc_interrupt_params int_params = {0};
1192 int r;
1193 int i;
1194
1195 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1196 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1197
1198 /* Actions of amdgpu_irq_add_id():
1199 * 1. Register a set() function with base driver.
1200 * Base driver will call set() function to enable/disable an
1201 * interrupt in DC hardware.
1202 * 2. Register amdgpu_dm_irq_handler().
1203 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1204 * coming from DC hardware.
1205 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1206 * for acknowledging and handling.
1207 * */
1208
1209 /* Use VSTARTUP interrupt */
1210 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1211 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1212 i++) {
1213 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1214
1215 if (r) {
1216 DRM_ERROR("Failed to add crtc irq id!\n");
1217 return r;
1218 }
1219
1220 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1221 int_params.irq_source =
1222 dc_interrupt_to_irq_source(dc, i, 0);
1223
1224 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1225
1226 c_irq_params->adev = adev;
1227 c_irq_params->irq_src = int_params.irq_source;
1228
1229 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1230 dm_crtc_high_irq, c_irq_params);
1231 }
1232
1233 /* Use GRPH_PFLIP interrupt */
1234 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1235 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1236 i++) {
1237 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1238 if (r) {
1239 DRM_ERROR("Failed to add page flip irq id!\n");
1240 return r;
1241 }
1242
1243 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1244 int_params.irq_source =
1245 dc_interrupt_to_irq_source(dc, i, 0);
1246
1247 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1248
1249 c_irq_params->adev = adev;
1250 c_irq_params->irq_src = int_params.irq_source;
1251
1252 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1253 dm_pflip_high_irq, c_irq_params);
1254
1255 }
1256
1257 /* HPD */
1258 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1259 &adev->hpd_irq);
1260 if (r) {
1261 DRM_ERROR("Failed to add hpd irq id!\n");
1262 return r;
1263 }
1264
1265 register_hpd_handlers(adev);
1266
1267 return 0;
1268}
1269#endif
1270
4562236b
HW		 1271static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1272{
1273 int r;
1274
1275 adev->mode_info.mode_config_initialized = true;
1276
4562236b 1277 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1278 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1279
1280 adev->ddev->mode_config.max_width = 16384;
1281 adev->ddev->mode_config.max_height = 16384;
1282
1283 adev->ddev->mode_config.preferred_depth = 24;
1284 adev->ddev->mode_config.prefer_shadow = 1;
1285 /* indicate support of immediate flip */
1286 adev->ddev->mode_config.async_page_flip = true;
1287
1288 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1289
1290 r = amdgpu_modeset_create_props(adev);
1291 if (r)
1292 return r;
1293
1294 return 0;
1295}
1296
1297#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1298 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1299
1300static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1301{
1302 struct amdgpu_display_manager *dm = bl_get_data(bd);
1303
1304 if (dc_link_set_backlight_level(dm->backlight_link,
1305 bd->props.brightness, 0, 0))
1306 return 0;
1307 else
1308 return 1;
1309}
1310
1311static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1312{
1313 return bd->props.brightness;
1314}
1315
1316static const struct backlight_ops amdgpu_dm_backlight_ops = {
1317 .get_brightness = amdgpu_dm_backlight_get_brightness,
1318 .update_status = amdgpu_dm_backlight_update_status,
1319};
1320
7578ecda
AD		 1321static void
1322amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1323{
1324 char bl_name[16];
1325 struct backlight_properties props = { 0 };
1326
1327 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1328 props.type = BACKLIGHT_RAW;
1329
1330 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1331 dm->adev->ddev->primary->index);
1332
1333 dm->backlight_dev = backlight_device_register(bl_name,
1334 dm->adev->ddev->dev,
1335 dm,
1336 &amdgpu_dm_backlight_ops,
1337 &props);
1338
74baea42 1339 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1340 DRM_ERROR("DM: Backlight registration failed!\n");
1341 else
f1ad2f5e 1342 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1343}
1344
1345#endif
1346
1347/* In this architecture, the association
1348 * connector -> encoder -> crtc
1349 * id not really requried. The crtc and connector will hold the
1350 * display_index as an abstraction to use with DAL component
1351 *
1352 * Returns 0 on success
1353 */
7578ecda 1354static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1355{
1356 struct amdgpu_display_manager *dm = &adev->dm;
1357 uint32_t i;
c84dec2f 1358 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1359 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1360 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1361 uint32_t link_cnt;
92f3ac40 1362 unsigned long possible_crtcs;
4562236b
HW		 1363
1364 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1365 if (amdgpu_dm_mode_config_init(dm->adev)) {
1366 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1367 return -1;
4562236b
HW		 1368 }
1369
3be5262e 1370 for (i = 0; i < dm->dc->caps.max_planes; i++) {
efa6a8b7
HW		 1371 struct amdgpu_plane *plane;
1372
1373 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1374 mode_info->planes[i] = plane;
1375
1376 if (!plane) {
3be5262e 1377 DRM_ERROR("KMS: Failed to allocate plane\n");
cd8a2ae8 1378 goto fail;
d4e13b0d 1379 }
efa6a8b7 1380 plane->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1381
1382 /*
1383 * HACK: IGT tests expect that each plane can only have one
1384 * one possible CRTC. For now, set one CRTC for each
1385 * plane that is not an underlay, but still allow multiple
1386 * CRTCs for underlay planes.
1387 */
1388 possible_crtcs = 1 << i;
1389 if (i >= dm->dc->caps.max_streams)
1390 possible_crtcs = 0xff;
1391
1392 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d 1393 DRM_ERROR("KMS: Failed to initialize plane\n");
cd8a2ae8 1394 goto fail;
d4e13b0d
AD		 1395 }
1396 }
4562236b 1397
d4e13b0d
AD		 1398 for (i = 0; i < dm->dc->caps.max_streams; i++)
1399 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1400 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1401 goto fail;
4562236b 1402 }
4562236b 1403
ab2541b6 1404 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1405
1406 /* loops over all connectors on the board */
1407 for (i = 0; i < link_cnt; i++) {
1408
1409 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1410 DRM_ERROR(
1411 "KMS: Cannot support more than %d display indexes\n",
1412 AMDGPU_DM_MAX_DISPLAY_INDEX);
1413 continue;
1414 }
1415
1416 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1417 if (!aconnector)
cd8a2ae8 1418 goto fail;
4562236b
HW		 1419
1420 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1421 if (!aencoder)
cd8a2ae8 1422 goto fail;
4562236b
HW		 1423
1424 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1425 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1426 goto fail;
4562236b
HW		 1427 }
1428
1429 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1430 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1431 goto fail;
4562236b
HW		 1432 }
1433
8f38b66c
HW		 1434 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1435 DETECT_REASON_BOOT))
4562236b
HW		 1436 amdgpu_dm_update_connector_after_detect(aconnector);
1437 }
1438
1439 /* Software is initialized. Now we can register interrupt handlers. */
1440 switch (adev->asic_type) {
1441 case CHIP_BONAIRE:
1442 case CHIP_HAWAII:
cd4b356f
AD		 1443 case CHIP_KAVERI:
1444 case CHIP_KABINI:
1445 case CHIP_MULLINS:
4562236b
HW		 1446 case CHIP_TONGA:
1447 case CHIP_FIJI:
1448 case CHIP_CARRIZO:
1449 case CHIP_STONEY:
1450 case CHIP_POLARIS11:
1451 case CHIP_POLARIS10:
b264d345 1452 case CHIP_POLARIS12:
2c8ad2d5 1453 case CHIP_VEGA10:
4562236b
HW		 1454 if (dce110_register_irq_handlers(dm->adev)) {
1455 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1456 goto fail;
4562236b
HW		 1457 }
1458 break;
ff5ef992
AD		 1459#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1460 case CHIP_RAVEN:
1461 if (dcn10_register_irq_handlers(dm->adev)) {
1462 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1463 goto fail;
ff5ef992 1464 }
79c24086
BL		 1465 /*
1466 * Temporary disable until pplib/smu interaction is implemented
1467 */
1468 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1469 break;
1470#endif
4562236b
HW		 1471 default:
1472 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 1473 goto fail;
4562236b
HW		 1474 }
1475
4562236b 1476 return 0;
cd8a2ae8 1477fail:
4562236b 1478 kfree(aencoder);
4562236b 1479 kfree(aconnector);
3be5262e 1480 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1481 kfree(mode_info->planes[i]);
4562236b
HW		 1482 return -1;
1483}
1484
7578ecda 1485static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1486{
1487 drm_mode_config_cleanup(dm->ddev);
1488 return;
1489}
1490
1491/******************************************************************************
1492 * amdgpu_display_funcs functions
1493 *****************************************************************************/
1494
1495/**
1496 * dm_bandwidth_update - program display watermarks
1497 *
1498 * @adev: amdgpu_device pointer
1499 *
1500 * Calculate and program the display watermarks and line buffer allocation.
1501 */
1502static void dm_bandwidth_update(struct amdgpu_device *adev)
1503{
49c07a99 1504 /* TODO: implement later */
4562236b
HW		 1505}
1506
1507static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1508 u8 level)
1509{
1510 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1511}
1512
1513static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1514{
1515 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1516 return 0;
1517}
1518
4562236b
HW		 1519static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1520 struct drm_file *filp)
1521{
1522 struct mod_freesync_params freesync_params;
ab2541b6 1523 uint8_t num_streams;
4562236b 1524 uint8_t i;
4562236b
HW		 1525
1526 struct amdgpu_device *adev = dev->dev_private;
1527 int r = 0;
1528
1529 /* Get freesync enable flag from DRM */
1530
ab2541b6 1531 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1532
ab2541b6 1533 for (i = 0; i < num_streams; i++) {
0971c40e 1534 struct dc_stream_state *stream;
ab2541b6 1535 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1536
1537 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1538 &stream, 1, &freesync_params);
4562236b
HW		 1539 }
1540
1541 return r;
1542}
1543
39cc5be2 1544static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1545 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1546 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1547 .vblank_wait = NULL,
1548 .backlight_set_level =
1549 dm_set_backlight_level,/* called unconditionally */
1550 .backlight_get_level =
1551 dm_get_backlight_level,/* called unconditionally */
1552 .hpd_sense = NULL,/* called unconditionally */
1553 .hpd_set_polarity = NULL, /* called unconditionally */
1554 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1555 .page_flip_get_scanoutpos =
1556 dm_crtc_get_scanoutpos,/* called unconditionally */
1557 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1558 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1559 .notify_freesync = amdgpu_notify_freesync,
1560
1561};
1562
1563#if defined(CONFIG_DEBUG_KERNEL_DC)
1564
3ee6b26b
AD		 1565static ssize_t s3_debug_store(struct device *device,
1566 struct device_attribute *attr,
1567 const char *buf,
1568 size_t count)
4562236b
HW		 1569{
1570 int ret;
1571 int s3_state;
1572 struct pci_dev *pdev = to_pci_dev(device);
1573 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1574 struct amdgpu_device *adev = drm_dev->dev_private;
1575
1576 ret = kstrtoint(buf, 0, &s3_state);
1577
1578 if (ret == 0) {
1579 if (s3_state) {
1580 dm_resume(adev);
1581 amdgpu_dm_display_resume(adev);
1582 drm_kms_helper_hotplug_event(adev->ddev);
1583 } else
1584 dm_suspend(adev);
1585 }
1586
1587 return ret == 0 ? count : 0;
1588}
1589
1590DEVICE_ATTR_WO(s3_debug);
1591
1592#endif
1593
1594static int dm_early_init(void *handle)
1595{
1596 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1597
d7ec53d9 1598 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
4562236b
HW		 1599
1600 switch (adev->asic_type) {
1601 case CHIP_BONAIRE:
1602 case CHIP_HAWAII:
1603 adev->mode_info.num_crtc = 6;
1604 adev->mode_info.num_hpd = 6;
1605 adev->mode_info.num_dig = 6;
3be5262e 1606 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1607 break;
cd4b356f
AD		 1608 case CHIP_KAVERI:
1609 adev->mode_info.num_crtc = 4;
1610 adev->mode_info.num_hpd = 6;
1611 adev->mode_info.num_dig = 7;
1612 adev->mode_info.plane_type = dm_plane_type_default;
1613 break;
1614 case CHIP_KABINI:
1615 case CHIP_MULLINS:
1616 adev->mode_info.num_crtc = 2;
1617 adev->mode_info.num_hpd = 6;
1618 adev->mode_info.num_dig = 6;
1619 adev->mode_info.plane_type = dm_plane_type_default;
1620 break;
4562236b
HW		 1621 case CHIP_FIJI:
1622 case CHIP_TONGA:
1623 adev->mode_info.num_crtc = 6;
1624 adev->mode_info.num_hpd = 6;
1625 adev->mode_info.num_dig = 7;
3be5262e 1626 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1627 break;
1628 case CHIP_CARRIZO:
1629 adev->mode_info.num_crtc = 3;
1630 adev->mode_info.num_hpd = 6;
1631 adev->mode_info.num_dig = 9;
3be5262e 1632 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1633 break;
1634 case CHIP_STONEY:
1635 adev->mode_info.num_crtc = 2;
1636 adev->mode_info.num_hpd = 6;
1637 adev->mode_info.num_dig = 9;
3be5262e 1638 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1639 break;
1640 case CHIP_POLARIS11:
b264d345 1641 case CHIP_POLARIS12:
4562236b
HW		 1642 adev->mode_info.num_crtc = 5;
1643 adev->mode_info.num_hpd = 5;
1644 adev->mode_info.num_dig = 5;
3be5262e 1645 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1646 break;
1647 case CHIP_POLARIS10:
1648 adev->mode_info.num_crtc = 6;
1649 adev->mode_info.num_hpd = 6;
1650 adev->mode_info.num_dig = 6;
3be5262e 1651 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1652 break;
2c8ad2d5
AD		 1653 case CHIP_VEGA10:
1654 adev->mode_info.num_crtc = 6;
1655 adev->mode_info.num_hpd = 6;
1656 adev->mode_info.num_dig = 6;
3be5262e 1657 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1658 break;
ff5ef992
AD		 1659#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1660 case CHIP_RAVEN:
1661 adev->mode_info.num_crtc = 4;
1662 adev->mode_info.num_hpd = 4;
1663 adev->mode_info.num_dig = 4;
3be5262e 1664 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1665 break;
1666#endif
4562236b
HW		 1667 default:
1668 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1669 return -EINVAL;
1670 }
1671
c8dd5715
MD		 1672 amdgpu_dm_set_irq_funcs(adev);
1673
39cc5be2
AD		 1674 if (adev->mode_info.funcs == NULL)
1675 adev->mode_info.funcs = &dm_display_funcs;
1676
4562236b
HW		 1677 /* Note: Do NOT change adev->audio_endpt_rreg and
1678 * adev->audio_endpt_wreg because they are initialised in
1679 * amdgpu_device_init() */
1680#if defined(CONFIG_DEBUG_KERNEL_DC)
1681 device_create_file(
1682 adev->ddev->dev,
1683 &dev_attr_s3_debug);
1684#endif
1685
1686 return 0;
1687}
1688
9b690ef3 1689static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1690 struct dc_stream_state *new_stream,
1691 struct dc_stream_state *old_stream)
9b690ef3 1692{
e7b07cee
HW		 1693 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1694 return false;
1695
1696 if (!crtc_state->enable)
1697 return false;
1698
1699 return crtc_state->active;
1700}
1701
1702static bool modereset_required(struct drm_crtc_state *crtc_state)
1703{
1704 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1705 return false;
1706
1707 return !crtc_state->enable || !crtc_state->active;
1708}
1709
7578ecda 1710static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1711{
1712 drm_encoder_cleanup(encoder);
1713 kfree(encoder);
1714}
1715
1716static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1717 .destroy = amdgpu_dm_encoder_destroy,
1718};
1719
3ee6b26b
AD		 1720static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1721 struct dc_plane_state *plane_state)
e7b07cee 1722{
3be5262e
HW		 1723 plane_state->src_rect.x = state->src_x >> 16;
1724 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1725 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1726 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1727
3be5262e 1728 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1729 return false;
1730
3be5262e
HW		 1731 plane_state->src_rect.height = state->src_h >> 16;
1732 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1733 return false;
1734
3be5262e
HW		 1735 plane_state->dst_rect.x = state->crtc_x;
1736 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1737
1738 if (state->crtc_w == 0)
1739 return false;
1740
3be5262e 1741 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1742
1743 if (state->crtc_h == 0)
1744 return false;
1745
3be5262e 1746 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1747
3be5262e 1748 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1749
1750 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1751 case DRM_MODE_ROTATE_0:
3be5262e 1752 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1753 break;
1754 case DRM_MODE_ROTATE_90:
3be5262e 1755 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1756 break;
1757 case DRM_MODE_ROTATE_180:
3be5262e 1758 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1759 break;
1760 case DRM_MODE_ROTATE_270:
3be5262e 1761 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1762 break;
1763 default:
3be5262e 1764 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1765 break;
1766 }
1767
4562236b
HW		 1768 return true;
1769}
3ee6b26b 1770static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 1771 uint64_t *tiling_flags)
e7b07cee
HW		 1772{
1773 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1774 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1775
e7b07cee 1776 if (unlikely(r)) {
9bbc3031
JZ		 1777 // Don't show error msg. when return -ERESTARTSYS
1778 if (r != -ERESTARTSYS)
1779 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1780 return r;
1781 }
1782
e7b07cee
HW		 1783 if (tiling_flags)
1784 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1785
1786 amdgpu_bo_unreserve(rbo);
1787
1788 return r;
1789}
1790
3ee6b26b
AD		 1791static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1792 struct dc_plane_state *plane_state,
9817d5f5 1793 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 1794{
1795 uint64_t tiling_flags;
e7b07cee
HW		 1796 unsigned int awidth;
1797 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1798 int ret = 0;
1799 struct drm_format_name_buf format_name;
1800
1801 ret = get_fb_info(
1802 amdgpu_fb,
9817d5f5 1803 &tiling_flags);
e7b07cee
HW		 1804
1805 if (ret)
1806 return ret;
1807
1808 switch (fb->format->format) {
1809 case DRM_FORMAT_C8:
3be5262e 1810 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1811 break;
1812 case DRM_FORMAT_RGB565:
3be5262e 1813 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1814 break;
1815 case DRM_FORMAT_XRGB8888:
1816 case DRM_FORMAT_ARGB8888:
3be5262e 1817 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1818 break;
1819 case DRM_FORMAT_XRGB2101010:
1820 case DRM_FORMAT_ARGB2101010:
3be5262e 1821 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1822 break;
1823 case DRM_FORMAT_XBGR2101010:
1824 case DRM_FORMAT_ABGR2101010:
3be5262e 1825 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1826 break;
1827 case DRM_FORMAT_NV21:
3be5262e 1828 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1829 break;
1830 case DRM_FORMAT_NV12:
3be5262e 1831 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1832 break;
1833 default:
1834 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1835 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1836 return -EINVAL;
1837 }
1838
3be5262e
HW		 1839 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1840 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 1841 plane_state->plane_size.grph.surface_size.x = 0;
1842 plane_state->plane_size.grph.surface_size.y = 0;
1843 plane_state->plane_size.grph.surface_size.width = fb->width;
1844 plane_state->plane_size.grph.surface_size.height = fb->height;
1845 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1846 fb->pitches[0] / fb->format->cpp[0];
1847 /* TODO: unhardcode */
3be5262e 1848 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1849
1850 } else {
1851 awidth = ALIGN(fb->width, 64);
3be5262e 1852 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 1853 plane_state->plane_size.video.luma_size.x = 0;
1854 plane_state->plane_size.video.luma_size.y = 0;
1855 plane_state->plane_size.video.luma_size.width = awidth;
1856 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1857 /* TODO: unhardcode */
3be5262e 1858 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1859
3be5262e
HW		 1860 plane_state->plane_size.video.chroma_size.x = 0;
1861 plane_state->plane_size.video.chroma_size.y = 0;
1862 plane_state->plane_size.video.chroma_size.width = awidth;
1863 plane_state->plane_size.video.chroma_size.height = fb->height;
1864 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1865
1866 /* TODO: unhardcode */
3be5262e 1867 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1868 }
1869
3be5262e 1870 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1871
b830ebc9
HW		 1872 /* Fill GFX8 params */
1873 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1874 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1875
1876 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1877 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1878 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1879 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1880 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1881
1882 /* XXX fix me for VI */
3be5262e
HW		 1883 plane_state->tiling_info.gfx8.num_banks = num_banks;
1884 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1885 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1886 plane_state->tiling_info.gfx8.tile_split = tile_split;
1887 plane_state->tiling_info.gfx8.bank_width = bankw;
1888 plane_state->tiling_info.gfx8.bank_height = bankh;
1889 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1890 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1891 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1892 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1893 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1894 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1895 }
1896
3be5262e 1897 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1898 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1899
1900 if (adev->asic_type == CHIP_VEGA10 ||
1901 adev->asic_type == CHIP_RAVEN) {
1902 /* Fill GFX9 params */
3be5262e 1903 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1904 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1905 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1906 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1907 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1908 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1909 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1910 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1911 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1912 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1913 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1914 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1915 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1916 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1917 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1918 }
1919
3be5262e
HW		 1920 plane_state->visible = true;
1921 plane_state->scaling_quality.h_taps_c = 0;
1922 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1923
3be5262e
HW		 1924 /* is this needed? is plane_state zeroed at allocation? */
1925 plane_state->scaling_quality.h_taps = 0;
1926 plane_state->scaling_quality.v_taps = 0;
1927 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1928
1929 return ret;
1930
1931}
1932
3ee6b26b
AD		 1933static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state,
1934 struct dc_plane_state *plane_state)
e7b07cee
HW		 1935{
1936 int i;
1937 struct dc_gamma *gamma;
d66cf5f5
AK		 1938 struct drm_color_lut *lut =
1939 (struct drm_color_lut *) crtc_state->gamma_lut->data;
e7b07cee
HW		 1940
1941 gamma = dc_create_gamma();
1942
1943 if (gamma == NULL) {
1944 WARN_ON(1);
1945 return;
1946 }
1947
7483bed4
HW		 1948 gamma->type = GAMMA_RGB_256;
1949 gamma->num_entries = GAMMA_RGB_256_ENTRIES;
d66cf5f5
AK		 1950 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1951 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1952 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1953 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
e7b07cee
HW		 1954 }
1955
3be5262e 1956 plane_state->gamma_correction = gamma;
e7b07cee
HW		 1957}
1958
3ee6b26b
AD		 1959static int fill_plane_attributes(struct amdgpu_device *adev,
1960 struct dc_plane_state *dc_plane_state,
1961 struct drm_plane_state *plane_state,
9817d5f5 1962 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 1963{
1964 const struct amdgpu_framebuffer *amdgpu_fb =
1965 to_amdgpu_framebuffer(plane_state->fb);
1966 const struct drm_crtc *crtc = plane_state->crtc;
1967 struct dc_transfer_func *input_tf;
1968 int ret = 0;
1969
3be5262e 1970 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1971 return -EINVAL;
1972
1973 ret = fill_plane_attributes_from_fb(
1974 crtc->dev->dev_private,
3be5262e 1975 dc_plane_state,
9817d5f5 1976 amdgpu_fb);
e7b07cee
HW		 1977
1978 if (ret)
1979 return ret;
1980
1981 input_tf = dc_create_transfer_func();
1982
1983 if (input_tf == NULL)
1984 return -ENOMEM;
1985
1986 input_tf->type = TF_TYPE_PREDEFINED;
1987 input_tf->tf = TRANSFER_FUNCTION_SRGB;
1988
3be5262e 1989 dc_plane_state->in_transfer_func = input_tf;
e7b07cee
HW		 1990
1991 /* In case of gamma set, update gamma value */
1992 if (crtc_state->gamma_lut)
3be5262e 1993 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
e7b07cee
HW		 1994
1995 return ret;
1996}
1997
1998/*****************************************************************************/
1999
3ee6b26b
AD		 2000static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2001 const struct dm_connector_state *dm_state,
2002 struct dc_stream_state *stream)
e7b07cee
HW		 2003{
2004 enum amdgpu_rmx_type rmx_type;
2005
2006 struct rect src = { 0 }; /* viewport in composition space*/
2007 struct rect dst = { 0 }; /* stream addressable area */
2008
2009 /* no mode. nothing to be done */
2010 if (!mode)
2011 return;
2012
2013 /* Full screen scaling by default */
2014 src.width = mode->hdisplay;
2015 src.height = mode->vdisplay;
2016 dst.width = stream->timing.h_addressable;
2017 dst.height = stream->timing.v_addressable;
2018
52f401f9
HW		 2019 if (dm_state) {
2020 rmx_type = dm_state->scaling;
2021 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2022 if (src.width * dst.height <
2023 src.height * dst.width) {
2024 /* height needs less upscaling/more downscaling */
2025 dst.width = src.width *
2026 dst.height / src.height;
2027 } else {
2028 /* width needs less upscaling/more downscaling */
2029 dst.height = src.height *
2030 dst.width / src.width;
2031 }
2032 } else if (rmx_type == RMX_CENTER) {
2033 dst = src;
e7b07cee 2034 }
e7b07cee 2035
52f401f9
HW		 2036 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2037 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2038
52f401f9
HW		 2039 if (dm_state->underscan_enable) {
2040 dst.x += dm_state->underscan_hborder / 2;
2041 dst.y += dm_state->underscan_vborder / 2;
2042 dst.width -= dm_state->underscan_hborder;
2043 dst.height -= dm_state->underscan_vborder;
2044 }
e7b07cee
HW		 2045 }
2046
2047 stream->src = src;
2048 stream->dst = dst;
2049
f1ad2f5e 2050 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2051 dst.x, dst.y, dst.width, dst.height);
2052
2053}
2054
3ee6b26b
AD		 2055static enum dc_color_depth
2056convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2057{
2058 uint32_t bpc = connector->display_info.bpc;
2059
2060 /* Limited color depth to 8bit
b830ebc9
HW		 2061 * TODO: Still need to handle deep color
2062 */
e7b07cee
HW		 2063 if (bpc > 8)
2064 bpc = 8;
2065
2066 switch (bpc) {
2067 case 0:
2068 /* Temporary Work around, DRM don't parse color depth for
2069 * EDID revision before 1.4
2070 * TODO: Fix edid parsing
2071 */
2072 return COLOR_DEPTH_888;
2073 case 6:
2074 return COLOR_DEPTH_666;
2075 case 8:
2076 return COLOR_DEPTH_888;
2077 case 10:
2078 return COLOR_DEPTH_101010;
2079 case 12:
2080 return COLOR_DEPTH_121212;
2081 case 14:
2082 return COLOR_DEPTH_141414;
2083 case 16:
2084 return COLOR_DEPTH_161616;
2085 default:
2086 return COLOR_DEPTH_UNDEFINED;
2087 }
2088}
2089
3ee6b26b
AD		 2090static enum dc_aspect_ratio
2091get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2092{
2093 int32_t width = mode_in->crtc_hdisplay * 9;
2094 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2095
e7b07cee
HW		 2096 if ((width - height) < 10 && (width - height) > -10)
2097 return ASPECT_RATIO_16_9;
2098 else
2099 return ASPECT_RATIO_4_3;
2100}
2101
3ee6b26b
AD		 2102static enum dc_color_space
2103get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2104{
2105 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2106
2107 switch (dc_crtc_timing->pixel_encoding) {
2108 case PIXEL_ENCODING_YCBCR422:
2109 case PIXEL_ENCODING_YCBCR444:
2110 case PIXEL_ENCODING_YCBCR420:
2111 {
2112 /*
2113 * 27030khz is the separation point between HDTV and SDTV
2114 * according to HDMI spec, we use YCbCr709 and YCbCr601
2115 * respectively
2116 */
2117 if (dc_crtc_timing->pix_clk_khz > 27030) {
2118 if (dc_crtc_timing->flags.Y_ONLY)
2119 color_space =
2120 COLOR_SPACE_YCBCR709_LIMITED;
2121 else
2122 color_space = COLOR_SPACE_YCBCR709;
2123 } else {
2124 if (dc_crtc_timing->flags.Y_ONLY)
2125 color_space =
2126 COLOR_SPACE_YCBCR601_LIMITED;
2127 else
2128 color_space = COLOR_SPACE_YCBCR601;
2129 }
2130
2131 }
2132 break;
2133 case PIXEL_ENCODING_RGB:
2134 color_space = COLOR_SPACE_SRGB;
2135 break;
2136
2137 default:
2138 WARN_ON(1);
2139 break;
2140 }
2141
2142 return color_space;
2143}
2144
2145/*****************************************************************************/
2146
3ee6b26b
AD		 2147static void
2148fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2149 const struct drm_display_mode *mode_in,
2150 const struct drm_connector *connector)
e7b07cee
HW		 2151{
2152 struct dc_crtc_timing *timing_out = &stream->timing;
a6114e85 2153 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2154
e7b07cee
HW		 2155 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2156
2157 timing_out->h_border_left = 0;
2158 timing_out->h_border_right = 0;
2159 timing_out->v_border_top = 0;
2160 timing_out->v_border_bottom = 0;
2161 /* TODO: un-hardcode */
2162
2163 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2164 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2165 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2166 else
2167 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2168
2169 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2170 timing_out->display_color_depth = convert_color_depth_from_display_info(
2171 connector);
2172 timing_out->scan_type = SCANNING_TYPE_NODATA;
2173 timing_out->hdmi_vic = 0;
2174 timing_out->vic = drm_match_cea_mode(mode_in);
2175
2176 timing_out->h_addressable = mode_in->crtc_hdisplay;
2177 timing_out->h_total = mode_in->crtc_htotal;
2178 timing_out->h_sync_width =
2179 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2180 timing_out->h_front_porch =
2181 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2182 timing_out->v_total = mode_in->crtc_vtotal;
2183 timing_out->v_addressable = mode_in->crtc_vdisplay;
2184 timing_out->v_front_porch =
2185 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2186 timing_out->v_sync_width =
2187 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2188 timing_out->pix_clk_khz = mode_in->crtc_clock;
2189 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2190 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2191 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2192 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2193 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2194
2195 stream->output_color_space = get_output_color_space(timing_out);
2196
a6114e85
HW		 2197 tf->type = TF_TYPE_PREDEFINED;
2198 tf->tf = TRANSFER_FUNCTION_SRGB;
2199 stream->out_transfer_func = tf;
e7b07cee
HW		 2200}
2201
3ee6b26b
AD		 2202static void fill_audio_info(struct audio_info *audio_info,
2203 const struct drm_connector *drm_connector,
2204 const struct dc_sink *dc_sink)
e7b07cee
HW		 2205{
2206 int i = 0;
2207 int cea_revision = 0;
2208 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2209
2210 audio_info->manufacture_id = edid_caps->manufacturer_id;
2211 audio_info->product_id = edid_caps->product_id;
2212
2213 cea_revision = drm_connector->display_info.cea_rev;
2214
d2b2562c
TSD		 2215 strncpy(audio_info->display_name,
2216 edid_caps->display_name,
2217 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2218
b830ebc9 2219 if (cea_revision >= 3) {
e7b07cee
HW		 2220 audio_info->mode_count = edid_caps->audio_mode_count;
2221
2222 for (i = 0; i < audio_info->mode_count; ++i) {
2223 audio_info->modes[i].format_code =
2224 (enum audio_format_code)
2225 (edid_caps->audio_modes[i].format_code);
2226 audio_info->modes[i].channel_count =
2227 edid_caps->audio_modes[i].channel_count;
2228 audio_info->modes[i].sample_rates.all =
2229 edid_caps->audio_modes[i].sample_rate;
2230 audio_info->modes[i].sample_size =
2231 edid_caps->audio_modes[i].sample_size;
2232 }
2233 }
2234
2235 audio_info->flags.all = edid_caps->speaker_flags;
2236
2237 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2238 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2239 audio_info->video_latency = drm_connector->video_latency[0];
2240 audio_info->audio_latency = drm_connector->audio_latency[0];
2241 }
2242
2243 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2244
2245}
2246
3ee6b26b
AD		 2247static void
2248copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2249 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2250{
2251 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2252 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2253 dst_mode->crtc_clock = src_mode->crtc_clock;
2254 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2255 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2256 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2257 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2258 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2259 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2260 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2261 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2262 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2263 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2264 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2265}
2266
3ee6b26b
AD		 2267static void
2268decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2269 const struct drm_display_mode *native_mode,
2270 bool scale_enabled)
e7b07cee
HW		 2271{
2272 if (scale_enabled) {
2273 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2274 } else if (native_mode->clock == drm_mode->clock &&
2275 native_mode->htotal == drm_mode->htotal &&
2276 native_mode->vtotal == drm_mode->vtotal) {
2277 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2278 } else {
2279 /* no scaling nor amdgpu inserted, no need to patch */
2280 }
2281}
2282
423788c7 2283static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6
HW		 2284{
2285 struct dc_sink *sink = NULL;
2286 struct dc_sink_init_data sink_init_data = { 0 };
2287
2288 sink_init_data.link = aconnector->dc_link;
2289 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2290
2291 sink = dc_sink_create(&sink_init_data);
423788c7 2292 if (!sink) {
2e0ac3d6 2293 DRM_ERROR("Failed to create sink!\n");
423788c7
ES		 2294 return -ENOMEM;
2295 }
2e0ac3d6
HW		 2296
2297 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2298 aconnector->fake_enable = true;
2299
2300 aconnector->dc_sink = sink;
2301 aconnector->dc_link->local_sink = sink;
423788c7
ES		 2302
2303 return 0;
2e0ac3d6
HW		 2304}
2305
fa2123db
ML		 2306static void set_multisync_trigger_params(
2307 struct dc_stream_state *stream)
2308{
2309 if (stream->triggered_crtc_reset.enabled) {
2310 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2311 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2312 }
2313}
2314
2315static void set_master_stream(struct dc_stream_state *stream_set[],
2316 int stream_count)
2317{
2318 int j, highest_rfr = 0, master_stream = 0;
2319
2320 for (j = 0; j < stream_count; j++) {
2321 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2322 int refresh_rate = 0;
2323
2324 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2325 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2326 if (refresh_rate > highest_rfr) {
2327 highest_rfr = refresh_rate;
2328 master_stream = j;
2329 }
2330 }
2331 }
2332 for (j = 0; j < stream_count; j++) {
2333 if (stream_set[j] && j != master_stream)
2334 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2335 }
2336}
2337
2338static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2339{
2340 int i = 0;
2341
2342 if (context->stream_count < 2)
2343 return;
2344 for (i = 0; i < context->stream_count ; i++) {
2345 if (!context->streams[i])
2346 continue;
2347 /* TODO: add a function to read AMD VSDB bits and will set
2348 * crtc_sync_master.multi_sync_enabled flag
2349 * For now its set to false
2350 */
2351 set_multisync_trigger_params(context->streams[i]);
2352 }
2353 set_master_stream(context->streams, context->stream_count);
2354}
2355
3ee6b26b
AD		 2356static struct dc_stream_state *
2357create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2358 const struct drm_display_mode *drm_mode,
2359 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2360{
2361 struct drm_display_mode *preferred_mode = NULL;
391ef035 2362 struct drm_connector *drm_connector;
0971c40e 2363 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2364 struct drm_display_mode mode = *drm_mode;
2365 bool native_mode_found = false;
2366
b830ebc9 2367 if (aconnector == NULL) {
e7b07cee 2368 DRM_ERROR("aconnector is NULL!\n");
0b395ddb 2369 return stream;
e7b07cee
HW		 2370 }
2371
e7b07cee 2372 drm_connector = &aconnector->base;
2e0ac3d6 2373
f4ac176e
JZ		 2374 if (!aconnector->dc_sink) {
2375 /*
391ef035
JFZ		 2376 * Create dc_sink when necessary to MST
2377 * Don't apply fake_sink to MST
f4ac176e 2378 */
391ef035
JFZ		 2379 if (aconnector->mst_port) {
2380 dm_dp_mst_dc_sink_create(drm_connector);
0b395ddb 2381 return stream;
391ef035 2382 }
f4ac176e 2383
423788c7 2384 if (create_fake_sink(aconnector))
0b395ddb 2385 return stream;
f4ac176e 2386 }
2e0ac3d6 2387
e7b07cee 2388 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2389
b830ebc9 2390 if (stream == NULL) {
e7b07cee 2391 DRM_ERROR("Failed to create stream for sink!\n");
0b395ddb 2392 return stream;
e7b07cee
HW		 2393 }
2394
2395 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2396 /* Search for preferred mode */
2397 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2398 native_mode_found = true;
2399 break;
2400 }
2401 }
2402 if (!native_mode_found)
2403 preferred_mode = list_first_entry_or_null(
2404 &aconnector->base.modes,
2405 struct drm_display_mode,
2406 head);
2407
b830ebc9 2408 if (preferred_mode == NULL) {
e7b07cee
HW		 2409 /* This may not be an error, the use case is when we we have no
2410 * usermode calls to reset and set mode upon hotplug. In this
2411 * case, we call set mode ourselves to restore the previous mode
2412 * and the modelist may not be filled in in time.
2413 */
f1ad2f5e 2414 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2415 } else {
2416 decide_crtc_timing_for_drm_display_mode(
2417 &mode, preferred_mode,
52f401f9 2418 dm_state ? (dm_state->scaling != RMX_OFF) : false);
e7b07cee
HW		 2419 }
2420
4a2df0d1
JFZ		 2421 if (!dm_state)
2422 drm_mode_set_crtcinfo(&mode, 0);
2423
e7b07cee
HW		 2424 fill_stream_properties_from_drm_display_mode(stream,
2425 &mode, &aconnector->base);
2426 update_stream_scaling_settings(&mode, dm_state, stream);
2427
2428 fill_audio_info(
2429 &stream->audio_info,
2430 drm_connector,
2431 aconnector->dc_sink);
2432
3549130e
HW		 2433 update_stream_signal(stream);
2434
e7b07cee
HW		 2435 return stream;
2436}
2437
7578ecda 2438static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2439{
2440 drm_crtc_cleanup(crtc);
2441 kfree(crtc);
2442}
2443
2444static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2445 struct drm_crtc_state *state)
e7b07cee
HW		 2446{
2447 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2448
2449 /* TODO Destroy dc_stream objects are stream object is flattened */
2450 if (cur->stream)
2451 dc_stream_release(cur->stream);
2452
2453
2454 __drm_atomic_helper_crtc_destroy_state(state);
2455
2456
2457 kfree(state);
2458}
2459
2460static void dm_crtc_reset_state(struct drm_crtc *crtc)
2461{
2462 struct dm_crtc_state *state;
2463
2464 if (crtc->state)
2465 dm_crtc_destroy_state(crtc, crtc->state);
2466
2467 state = kzalloc(sizeof(*state), GFP_KERNEL);
2468 if (WARN_ON(!state))
2469 return;
2470
2471 crtc->state = &state->base;
2472 crtc->state->crtc = crtc;
2473
2474}
2475
2476static struct drm_crtc_state *
2477dm_crtc_duplicate_state(struct drm_crtc *crtc)
2478{
2479 struct dm_crtc_state *state, *cur;
2480
2481 cur = to_dm_crtc_state(crtc->state);
2482
2483 if (WARN_ON(!crtc->state))
2484 return NULL;
2485
2004f45e 2486 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 2487 if (!state)
2488 return NULL;
e7b07cee
HW		 2489
2490 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2491
2492 if (cur->stream) {
2493 state->stream = cur->stream;
2494 dc_stream_retain(state->stream);
2495 }
2496
2497 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2498
2499 return &state->base;
2500}
2501
c0ec5644
HW		 2502
2503static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2504{
2505 enum dc_irq_source irq_source;
2506 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2507 struct amdgpu_device *adev = crtc->dev->dev_private;
2508
2509 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
c0e463d3 2510 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
c0ec5644
HW		 2511}
2512
2513static int dm_enable_vblank(struct drm_crtc *crtc)
2514{
2515 return dm_set_vblank(crtc, true);
2516}
2517
2518static void dm_disable_vblank(struct drm_crtc *crtc)
2519{
2520 dm_set_vblank(crtc, false);
2521}
2522
e7b07cee
HW		 2523/* Implemented only the options currently availible for the driver */
2524static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2525 .reset = dm_crtc_reset_state,
2526 .destroy = amdgpu_dm_crtc_destroy,
2527 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2528 .set_config = drm_atomic_helper_set_config,
2529 .page_flip = drm_atomic_helper_page_flip,
2530 .atomic_duplicate_state = dm_crtc_duplicate_state,
2531 .atomic_destroy_state = dm_crtc_destroy_state,
c0ec5644
HW		 2532 .enable_vblank = dm_enable_vblank,
2533 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 2534};
2535
2536static enum drm_connector_status
2537amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2538{
2539 bool connected;
c84dec2f 2540 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2541
2542 /* Notes:
2543 * 1. This interface is NOT called in context of HPD irq.
2544 * 2. This interface *is called* in context of user-mode ioctl. Which
2545 * makes it a bad place for *any* MST-related activit. */
2546
8580d60b
HW		 2547 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2548 !aconnector->fake_enable)
e7b07cee
HW		 2549 connected = (aconnector->dc_sink != NULL);
2550 else
2551 connected = (aconnector->base.force == DRM_FORCE_ON);
2552
2553 return (connected ? connector_status_connected :
2554 connector_status_disconnected);
2555}
2556
3ee6b26b
AD		 2557int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2558 struct drm_connector_state *connector_state,
2559 struct drm_property *property,
2560 uint64_t val)
e7b07cee
HW		 2561{
2562 struct drm_device *dev = connector->dev;
2563 struct amdgpu_device *adev = dev->dev_private;
2564 struct dm_connector_state *dm_old_state =
2565 to_dm_connector_state(connector->state);
2566 struct dm_connector_state *dm_new_state =
2567 to_dm_connector_state(connector_state);
2568
2569 int ret = -EINVAL;
2570
2571 if (property == dev->mode_config.scaling_mode_property) {
2572 enum amdgpu_rmx_type rmx_type;
2573
2574 switch (val) {
2575 case DRM_MODE_SCALE_CENTER:
2576 rmx_type = RMX_CENTER;
2577 break;
2578 case DRM_MODE_SCALE_ASPECT:
2579 rmx_type = RMX_ASPECT;
2580 break;
2581 case DRM_MODE_SCALE_FULLSCREEN:
2582 rmx_type = RMX_FULL;
2583 break;
2584 case DRM_MODE_SCALE_NONE:
2585 default:
2586 rmx_type = RMX_OFF;
2587 break;
2588 }
2589
2590 if (dm_old_state->scaling == rmx_type)
2591 return 0;
2592
2593 dm_new_state->scaling = rmx_type;
2594 ret = 0;
2595 } else if (property == adev->mode_info.underscan_hborder_property) {
2596 dm_new_state->underscan_hborder = val;
2597 ret = 0;
2598 } else if (property == adev->mode_info.underscan_vborder_property) {
2599 dm_new_state->underscan_vborder = val;
2600 ret = 0;
2601 } else if (property == adev->mode_info.underscan_property) {
2602 dm_new_state->underscan_enable = val;
2603 ret = 0;
2604 }
2605
2606 return ret;
2607}
2608
3ee6b26b
AD		 2609int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2610 const struct drm_connector_state *state,
2611 struct drm_property *property,
2612 uint64_t *val)
e7b07cee
HW		 2613{
2614 struct drm_device *dev = connector->dev;
2615 struct amdgpu_device *adev = dev->dev_private;
2616 struct dm_connector_state *dm_state =
2617 to_dm_connector_state(state);
2618 int ret = -EINVAL;
2619
2620 if (property == dev->mode_config.scaling_mode_property) {
2621 switch (dm_state->scaling) {
2622 case RMX_CENTER:
2623 *val = DRM_MODE_SCALE_CENTER;
2624 break;
2625 case RMX_ASPECT:
2626 *val = DRM_MODE_SCALE_ASPECT;
2627 break;
2628 case RMX_FULL:
2629 *val = DRM_MODE_SCALE_FULLSCREEN;
2630 break;
2631 case RMX_OFF:
2632 default:
2633 *val = DRM_MODE_SCALE_NONE;
2634 break;
2635 }
2636 ret = 0;
2637 } else if (property == adev->mode_info.underscan_hborder_property) {
2638 *val = dm_state->underscan_hborder;
2639 ret = 0;
2640 } else if (property == adev->mode_info.underscan_vborder_property) {
2641 *val = dm_state->underscan_vborder;
2642 ret = 0;
2643 } else if (property == adev->mode_info.underscan_property) {
2644 *val = dm_state->underscan_enable;
2645 ret = 0;
2646 }
2647 return ret;
2648}
2649
7578ecda 2650static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2651{
c84dec2f 2652 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2653 const struct dc_link *link = aconnector->dc_link;
2654 struct amdgpu_device *adev = connector->dev->dev_private;
2655 struct amdgpu_display_manager *dm = &adev->dm;
2656#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2657 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2658
2659 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2660 amdgpu_dm_register_backlight_device(dm);
2661
2662 if (dm->backlight_dev) {
2663 backlight_device_unregister(dm->backlight_dev);
2664 dm->backlight_dev = NULL;
2665 }
2666
2667 }
2668#endif
2669 drm_connector_unregister(connector);
2670 drm_connector_cleanup(connector);
2671 kfree(connector);
2672}
2673
2674void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2675{
2676 struct dm_connector_state *state =
2677 to_dm_connector_state(connector->state);
2678
2679 kfree(state);
2680
2681 state = kzalloc(sizeof(*state), GFP_KERNEL);
2682
2683 if (state) {
2684 state->scaling = RMX_OFF;
2685 state->underscan_enable = false;
2686 state->underscan_hborder = 0;
2687 state->underscan_vborder = 0;
2688
2689 connector->state = &state->base;
2690 connector->state->connector = connector;
2691 }
2692}
2693
3ee6b26b
AD		 2694struct drm_connector_state *
2695amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2696{
2697 struct dm_connector_state *state =
2698 to_dm_connector_state(connector->state);
2699
2700 struct dm_connector_state *new_state =
2701 kmemdup(state, sizeof(*state), GFP_KERNEL);
2702
2703 if (new_state) {
2704 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2705 &new_state->base);
e7b07cee
HW		 2706 return &new_state->base;
2707 }
2708
2709 return NULL;
2710}
2711
2712static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2713 .reset = amdgpu_dm_connector_funcs_reset,
2714 .detect = amdgpu_dm_connector_detect,
2715 .fill_modes = drm_helper_probe_single_connector_modes,
2716 .destroy = amdgpu_dm_connector_destroy,
2717 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2718 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2719 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2720 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2721};
2722
2723static struct drm_encoder *best_encoder(struct drm_connector *connector)
2724{
2725 int enc_id = connector->encoder_ids[0];
2726 struct drm_mode_object *obj;
2727 struct drm_encoder *encoder;
2728
f1ad2f5e 2729 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2730
2731 /* pick the encoder ids */
2732 if (enc_id) {
bd21a37d 2733 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2734 if (!obj) {
2735 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2736 return NULL;
2737 }
2738 encoder = obj_to_encoder(obj);
2739 return encoder;
2740 }
2741 DRM_ERROR("No encoder id\n");
2742 return NULL;
2743}
2744
2745static int get_modes(struct drm_connector *connector)
2746{
2747 return amdgpu_dm_connector_get_modes(connector);
2748}
2749
c84dec2f 2750static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2751{
2752 struct dc_sink_init_data init_params = {
2753 .link = aconnector->dc_link,
2754 .sink_signal = SIGNAL_TYPE_VIRTUAL
2755 };
70e8ffc5 2756 struct edid *edid;
e7b07cee 2757
a89ff457 2758 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 2759 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2760 aconnector->base.name);
2761
2762 aconnector->base.force = DRM_FORCE_OFF;
2763 aconnector->base.override_edid = false;
2764 return;
2765 }
2766
70e8ffc5
HW		 2767 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2768
e7b07cee
HW		 2769 aconnector->edid = edid;
2770
2771 aconnector->dc_em_sink = dc_link_add_remote_sink(
2772 aconnector->dc_link,
2773 (uint8_t *)edid,
2774 (edid->extensions + 1) * EDID_LENGTH,
2775 &init_params);
2776
a68d90e7 2777 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 2778 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2779 aconnector->dc_link->local_sink :
2780 aconnector->dc_em_sink;
2781}
2782
c84dec2f 2783static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2784{
2785 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2786
2787 /* In case of headless boot with force on for DP managed connector
2788 * Those settings have to be != 0 to get initial modeset
2789 */
2790 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2791 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2792 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2793 }
2794
2795
2796 aconnector->base.override_edid = true;
2797 create_eml_sink(aconnector);
2798}
2799
3ee6b26b
AD		 2800int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2801 struct drm_display_mode *mode)
e7b07cee
HW		 2802{
2803 int result = MODE_ERROR;
2804 struct dc_sink *dc_sink;
2805 struct amdgpu_device *adev = connector->dev->dev_private;
2806 /* TODO: Unhardcode stream count */
0971c40e 2807 struct dc_stream_state *stream;
c84dec2f 2808 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2809
2810 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2811 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2812 return result;
2813
2814 /* Only run this the first time mode_valid is called to initilialize
2815 * EDID mgmt
2816 */
2817 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2818 !aconnector->dc_em_sink)
2819 handle_edid_mgmt(aconnector);
2820
c84dec2f 2821 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2822
b830ebc9 2823 if (dc_sink == NULL) {
e7b07cee
HW		 2824 DRM_ERROR("dc_sink is NULL!\n");
2825 goto fail;
2826 }
2827
52f401f9 2828 stream = create_stream_for_sink(aconnector, mode, NULL);
b830ebc9 2829 if (stream == NULL) {
e7b07cee
HW		 2830 DRM_ERROR("Failed to create stream for sink!\n");
2831 goto fail;
2832 }
2833
2834 drm_mode_set_crtcinfo(mode, 0);
2835 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2836
2837 stream->src.width = mode->hdisplay;
2838 stream->src.height = mode->vdisplay;
2839 stream->dst = stream->src;
2840
62c933f9 2841 if (dc_validate_stream(adev->dm.dc, stream) == DC_OK)
e7b07cee
HW		 2842 result = MODE_OK;
2843
2844 dc_stream_release(stream);
2845
2846fail:
2847 /* TODO: error handling*/
2848 return result;
2849}
2850
2851static const struct drm_connector_helper_funcs
2852amdgpu_dm_connector_helper_funcs = {
2853 /*
b830ebc9
HW		 2854 * If hotplug a second bigger display in FB Con mode, bigger resolution
2855 * modes will be filtered by drm_mode_validate_size(), and those modes
2856 * is missing after user start lightdm. So we need to renew modes list.
2857 * in get_modes call back, not just return the modes count
2858 */
e7b07cee
HW		 2859 .get_modes = get_modes,
2860 .mode_valid = amdgpu_dm_connector_mode_valid,
2861 .best_encoder = best_encoder
2862};
2863
2864static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2865{
2866}
2867
3ee6b26b
AD		 2868static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2869 struct drm_crtc_state *state)
e7b07cee
HW		 2870{
2871 struct amdgpu_device *adev = crtc->dev->dev_private;
2872 struct dc *dc = adev->dm.dc;
2873 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2874 int ret = -EINVAL;
2875
9b690ef3
BL		 2876 if (unlikely(!dm_crtc_state->stream &&
2877 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2878 WARN_ON(1);
2879 return ret;
2880 }
2881
2882 /* In some use cases, like reset, no stream is attached */
2883 if (!dm_crtc_state->stream)
2884 return 0;
2885
62c933f9 2886 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 2887 return 0;
2888
2889 return ret;
2890}
2891
3ee6b26b
AD		 2892static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2893 const struct drm_display_mode *mode,
2894 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2895{
2896 return true;
2897}
2898
2899static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2900 .disable = dm_crtc_helper_disable,
2901 .atomic_check = dm_crtc_helper_atomic_check,
2902 .mode_fixup = dm_crtc_helper_mode_fixup
2903};
2904
2905static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2906{
2907
2908}
2909
3ee6b26b
AD		 2910static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2911 struct drm_crtc_state *crtc_state,
2912 struct drm_connector_state *conn_state)
e7b07cee
HW		 2913{
2914 return 0;
2915}
2916
2917const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2918 .disable = dm_encoder_helper_disable,
2919 .atomic_check = dm_encoder_helper_atomic_check
2920};
2921
2922static void dm_drm_plane_reset(struct drm_plane *plane)
2923{
2924 struct dm_plane_state *amdgpu_state = NULL;
2925
2926 if (plane->state)
2927 plane->funcs->atomic_destroy_state(plane, plane->state);
2928
2929 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d
TSD		 2930 WARN_ON(amdgpu_state == NULL);
2931
e7b07cee
HW		 2932 if (amdgpu_state) {
2933 plane->state = &amdgpu_state->base;
2934 plane->state->plane = plane;
2935 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 2936 }
e7b07cee
HW		 2937}
2938
2939static struct drm_plane_state *
2940dm_drm_plane_duplicate_state(struct drm_plane *plane)
2941{
2942 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2943
2944 old_dm_plane_state = to_dm_plane_state(plane->state);
2945 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2946 if (!dm_plane_state)
2947 return NULL;
2948
2949 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2950
3be5262e
HW		 2951 if (old_dm_plane_state->dc_state) {
2952 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2953 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2954 }
2955
2956 return &dm_plane_state->base;
2957}
2958
2959void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2960 struct drm_plane_state *state)
e7b07cee
HW		 2961{
2962 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2963
3be5262e
HW		 2964 if (dm_plane_state->dc_state)
2965 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2966
0627bbd3 2967 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2968}
2969
2970static const struct drm_plane_funcs dm_plane_funcs = {
2971 .update_plane = drm_atomic_helper_update_plane,
2972 .disable_plane = drm_atomic_helper_disable_plane,
2973 .destroy = drm_plane_cleanup,
2974 .reset = dm_drm_plane_reset,
2975 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2976 .atomic_destroy_state = dm_drm_plane_destroy_state,
2977};
2978
3ee6b26b
AD		 2979static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2980 struct drm_plane_state *new_state)
e7b07cee
HW		 2981{
2982 struct amdgpu_framebuffer *afb;
2983 struct drm_gem_object *obj;
2984 struct amdgpu_bo *rbo;
56087b31 2985 uint64_t chroma_addr = 0;
e7b07cee
HW		 2986 int r;
2987 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2988 unsigned int awidth;
2989
2990 dm_plane_state_old = to_dm_plane_state(plane->state);
2991 dm_plane_state_new = to_dm_plane_state(new_state);
2992
2993 if (!new_state->fb) {
f1ad2f5e 2994 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 2995 return 0;
2996 }
2997
2998 afb = to_amdgpu_framebuffer(new_state->fb);
2999
3000 obj = afb->obj;
3001 rbo = gem_to_amdgpu_bo(obj);
3002 r = amdgpu_bo_reserve(rbo, false);
3003 if (unlikely(r != 0))
3004 return r;
3005
3006 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
3007
3008
3009 amdgpu_bo_unreserve(rbo);
3010
3011 if (unlikely(r != 0)) {
30b7c614
HW		 3012 if (r != -ERESTARTSYS)
3013 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
e7b07cee
HW		 3014 return r;
3015 }
3016
3017 amdgpu_bo_ref(rbo);
3018
3be5262e
HW		 3019 if (dm_plane_state_new->dc_state &&
3020 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3021 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3022
3be5262e
HW		 3023 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3024 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3025 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 3026 } else {
3027 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3028 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3029 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3030 = lower_32_bits(afb->address);
56087b31
S		 3031 plane_state->address.video_progressive.luma_addr.high_part
3032 = upper_32_bits(afb->address);
35888630 3033 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3034 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3035 = lower_32_bits(chroma_addr);
3036 plane_state->address.video_progressive.chroma_addr.high_part
3037 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3038 }
3039 }
3040
3041 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
3042 * prepare and cleanup in drm_atomic_helper_prepare_planes
3043 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
3044 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
3045 * code touching fram buffers should be avoided for DC.
3046 */
3047 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3048 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
3049
3050 acrtc->cursor_bo = obj;
3051 }
3052 return 0;
3053}
3054
3ee6b26b
AD		 3055static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3056 struct drm_plane_state *old_state)
e7b07cee
HW		 3057{
3058 struct amdgpu_bo *rbo;
3059 struct amdgpu_framebuffer *afb;
3060 int r;
3061
3062 if (!old_state->fb)
3063 return;
3064
3065 afb = to_amdgpu_framebuffer(old_state->fb);
3066 rbo = gem_to_amdgpu_bo(afb->obj);
3067 r = amdgpu_bo_reserve(rbo, false);
3068 if (unlikely(r)) {
3069 DRM_ERROR("failed to reserve rbo before unpin\n");
3070 return;
b830ebc9
HW		 3071 }
3072
3073 amdgpu_bo_unpin(rbo);
3074 amdgpu_bo_unreserve(rbo);
3075 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3076}
3077
7578ecda
AD		 3078static int dm_plane_atomic_check(struct drm_plane *plane,
3079 struct drm_plane_state *state)
cbd19488
AG		 3080{
3081 struct amdgpu_device *adev = plane->dev->dev_private;
3082 struct dc *dc = adev->dm.dc;
3083 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3084
3be5262e 3085 if (!dm_plane_state->dc_state)
9a3329b1 3086 return 0;
cbd19488 3087
5449e07c
S		 3088 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3089 return -EINVAL;
3090
62c933f9 3091 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3092 return 0;
3093
3094 return -EINVAL;
3095}
3096
e7b07cee
HW		 3097static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3098 .prepare_fb = dm_plane_helper_prepare_fb,
3099 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3100 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3101};
3102
3103/*
3104 * TODO: these are currently initialized to rgb formats only.
3105 * For future use cases we should either initialize them dynamically based on
3106 * plane capabilities, or initialize this array to all formats, so internal drm
3107 * check will succeed, and let DC to implement proper check
3108 */
d90371b0 3109static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3110 DRM_FORMAT_RGB888,
3111 DRM_FORMAT_XRGB8888,
3112 DRM_FORMAT_ARGB8888,
3113 DRM_FORMAT_RGBA8888,
3114 DRM_FORMAT_XRGB2101010,
3115 DRM_FORMAT_XBGR2101010,
3116 DRM_FORMAT_ARGB2101010,
3117 DRM_FORMAT_ABGR2101010,
3118};
3119
99d1abf8 3120static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3121 DRM_FORMAT_NV12,
3122 DRM_FORMAT_NV21,
3123};
3124
3125static const u32 cursor_formats[] = {
3126 DRM_FORMAT_ARGB8888
3127};
3128
7578ecda
AD		 3129static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3130 struct amdgpu_plane *aplane,
3131 unsigned long possible_crtcs)
e7b07cee
HW		 3132{
3133 int res = -EPERM;
3134
3135 switch (aplane->base.type) {
3136 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3137 res = drm_universal_plane_init(
3138 dm->adev->ddev,
3139 &aplane->base,
3140 possible_crtcs,
3141 &dm_plane_funcs,
3142 rgb_formats,
3143 ARRAY_SIZE(rgb_formats),
3144 NULL, aplane->base.type, NULL);
3145 break;
3146 case DRM_PLANE_TYPE_OVERLAY:
3147 res = drm_universal_plane_init(
3148 dm->adev->ddev,
3149 &aplane->base,
3150 possible_crtcs,
3151 &dm_plane_funcs,
3152 yuv_formats,
3153 ARRAY_SIZE(yuv_formats),
3154 NULL, aplane->base.type, NULL);
3155 break;
3156 case DRM_PLANE_TYPE_CURSOR:
3157 res = drm_universal_plane_init(
3158 dm->adev->ddev,
3159 &aplane->base,
3160 possible_crtcs,
3161 &dm_plane_funcs,
3162 cursor_formats,
3163 ARRAY_SIZE(cursor_formats),
3164 NULL, aplane->base.type, NULL);
3165 break;
3166 }
3167
3168 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3169
96719c54
HW		 3170 /* Create (reset) the plane state */
3171 if (aplane->base.funcs->reset)
3172 aplane->base.funcs->reset(&aplane->base);
3173
3174
e7b07cee
HW		 3175 return res;
3176}
3177
7578ecda
AD		 3178static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3179 struct drm_plane *plane,
3180 uint32_t crtc_index)
e7b07cee
HW		 3181{
3182 struct amdgpu_crtc *acrtc = NULL;
3183 struct amdgpu_plane *cursor_plane;
3184
3185 int res = -ENOMEM;
3186
3187 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3188 if (!cursor_plane)
3189 goto fail;
3190
3191 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3192 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3193
3194 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3195 if (!acrtc)
3196 goto fail;
3197
3198 res = drm_crtc_init_with_planes(
3199 dm->ddev,
3200 &acrtc->base,
3201 plane,
3202 &cursor_plane->base,
3203 &amdgpu_dm_crtc_funcs, NULL);
3204
3205 if (res)
3206 goto fail;
3207
3208 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3209
96719c54
HW		 3210 /* Create (reset) the plane state */
3211 if (acrtc->base.funcs->reset)
3212 acrtc->base.funcs->reset(&acrtc->base);
3213
e7b07cee
HW		 3214 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3215 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3216
3217 acrtc->crtc_id = crtc_index;
3218 acrtc->base.enabled = false;
3219
3220 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3221 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3222
3223 return 0;
3224
3225fail:
b830ebc9
HW		 3226 kfree(acrtc);
3227 kfree(cursor_plane);
e7b07cee
HW		 3228 return res;
3229}
3230
3231
3232static int to_drm_connector_type(enum signal_type st)
3233{
3234 switch (st) {
3235 case SIGNAL_TYPE_HDMI_TYPE_A:
3236 return DRM_MODE_CONNECTOR_HDMIA;
3237 case SIGNAL_TYPE_EDP:
3238 return DRM_MODE_CONNECTOR_eDP;
3239 case SIGNAL_TYPE_RGB:
3240 return DRM_MODE_CONNECTOR_VGA;
3241 case SIGNAL_TYPE_DISPLAY_PORT:
3242 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3243 return DRM_MODE_CONNECTOR_DisplayPort;
3244 case SIGNAL_TYPE_DVI_DUAL_LINK:
3245 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3246 return DRM_MODE_CONNECTOR_DVID;
3247 case SIGNAL_TYPE_VIRTUAL:
3248 return DRM_MODE_CONNECTOR_VIRTUAL;
3249
3250 default:
3251 return DRM_MODE_CONNECTOR_Unknown;
3252 }
3253}
3254
3255static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3256{
3257 const struct drm_connector_helper_funcs *helper =
3258 connector->helper_private;
3259 struct drm_encoder *encoder;
3260 struct amdgpu_encoder *amdgpu_encoder;
3261
3262 encoder = helper->best_encoder(connector);
3263
3264 if (encoder == NULL)
3265 return;
3266
3267 amdgpu_encoder = to_amdgpu_encoder(encoder);
3268
3269 amdgpu_encoder->native_mode.clock = 0;
3270
3271 if (!list_empty(&connector->probed_modes)) {
3272 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3273
e7b07cee 3274 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3275 &connector->probed_modes,
3276 head) {
3277 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3278 amdgpu_encoder->native_mode = *preferred_mode;
3279
e7b07cee
HW		 3280 break;
3281 }
3282
3283 }
3284}
3285
3ee6b26b
AD		 3286static struct drm_display_mode *
3287amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3288 char *name,
3289 int hdisplay, int vdisplay)
e7b07cee
HW		 3290{
3291 struct drm_device *dev = encoder->dev;
3292 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3293 struct drm_display_mode *mode = NULL;
3294 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3295
3296 mode = drm_mode_duplicate(dev, native_mode);
3297
b830ebc9 3298 if (mode == NULL)
e7b07cee
HW		 3299 return NULL;
3300
3301 mode->hdisplay = hdisplay;
3302 mode->vdisplay = vdisplay;
3303 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3304 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3305
3306 return mode;
3307
3308}
3309
3310static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3311 struct drm_connector *connector)
e7b07cee
HW		 3312{
3313 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3314 struct drm_display_mode *mode = NULL;
3315 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3316 struct amdgpu_dm_connector *amdgpu_dm_connector =
3317 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3318 int i;
3319 int n;
3320 struct mode_size {
3321 char name[DRM_DISPLAY_MODE_LEN];
3322 int w;
3323 int h;
b830ebc9 3324 } common_modes[] = {
e7b07cee
HW		 3325 { "640x480", 640, 480},
3326 { "800x600", 800, 600},
3327 { "1024x768", 1024, 768},
3328 { "1280x720", 1280, 720},
3329 { "1280x800", 1280, 800},
3330 {"1280x1024", 1280, 1024},
3331 { "1440x900", 1440, 900},
3332 {"1680x1050", 1680, 1050},
3333 {"1600x1200", 1600, 1200},
3334 {"1920x1080", 1920, 1080},
3335 {"1920x1200", 1920, 1200}
3336 };
3337
b830ebc9 3338 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3339
3340 for (i = 0; i < n; i++) {
3341 struct drm_display_mode *curmode = NULL;
3342 bool mode_existed = false;
3343
3344 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3345 common_modes[i].h > native_mode->vdisplay ||
3346 (common_modes[i].w == native_mode->hdisplay &&
3347 common_modes[i].h == native_mode->vdisplay))
3348 continue;
e7b07cee
HW		 3349
3350 list_for_each_entry(curmode, &connector->probed_modes, head) {
3351 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3352 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3353 mode_existed = true;
3354 break;
3355 }
3356 }
3357
3358 if (mode_existed)
3359 continue;
3360
3361 mode = amdgpu_dm_create_common_mode(encoder,
3362 common_modes[i].name, common_modes[i].w,
3363 common_modes[i].h);
3364 drm_mode_probed_add(connector, mode);
c84dec2f 3365 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3366 }
3367}
3368
3ee6b26b
AD		 3369static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3370 struct edid *edid)
e7b07cee 3371{
c84dec2f
HW		 3372 struct amdgpu_dm_connector *amdgpu_dm_connector =
3373 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3374
3375 if (edid) {
3376 /* empty probed_modes */
3377 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3378 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3379 drm_add_edid_modes(connector, edid);
3380
e7b07cee 3381 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3382 } else {
c84dec2f 3383 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3384 }
e7b07cee
HW		 3385}
3386
7578ecda 3387static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3388{
3389 const struct drm_connector_helper_funcs *helper =
3390 connector->helper_private;
c84dec2f
HW		 3391 struct amdgpu_dm_connector *amdgpu_dm_connector =
3392 to_amdgpu_dm_connector(connector);
e7b07cee 3393 struct drm_encoder *encoder;
c84dec2f 3394 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3395
3396 encoder = helper->best_encoder(connector);
3397
3398 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3399 amdgpu_dm_connector_add_common_modes(encoder, connector);
c84dec2f 3400 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3401}
3402
3ee6b26b
AD		 3403void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3404 struct amdgpu_dm_connector *aconnector,
3405 int connector_type,
3406 struct dc_link *link,
3407 int link_index)
e7b07cee
HW		 3408{
3409 struct amdgpu_device *adev = dm->ddev->dev_private;
3410
3411 aconnector->connector_id = link_index;
3412 aconnector->dc_link = link;
3413 aconnector->base.interlace_allowed = false;
3414 aconnector->base.doublescan_allowed = false;
3415 aconnector->base.stereo_allowed = false;
3416 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3417 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3418
3419 mutex_init(&aconnector->hpd_lock);
3420
b830ebc9
HW		 3421 /* configure support HPD hot plug connector_>polled default value is 0
3422 * which means HPD hot plug not supported
3423 */
e7b07cee
HW		 3424 switch (connector_type) {
3425 case DRM_MODE_CONNECTOR_HDMIA:
3426 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3427 break;
3428 case DRM_MODE_CONNECTOR_DisplayPort:
3429 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3430 break;
3431 case DRM_MODE_CONNECTOR_DVID:
3432 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3433 break;
3434 default:
3435 break;
3436 }
3437
3438 drm_object_attach_property(&aconnector->base.base,
3439 dm->ddev->mode_config.scaling_mode_property,
3440 DRM_MODE_SCALE_NONE);
3441
3442 drm_object_attach_property(&aconnector->base.base,
3443 adev->mode_info.underscan_property,
3444 UNDERSCAN_OFF);
3445 drm_object_attach_property(&aconnector->base.base,
3446 adev->mode_info.underscan_hborder_property,
3447 0);
3448 drm_object_attach_property(&aconnector->base.base,
3449 adev->mode_info.underscan_vborder_property,
3450 0);
3451
3452}
3453
7578ecda
AD		 3454static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3455 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3456{
3457 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3458 struct ddc_service *ddc_service = i2c->ddc_service;
3459 struct i2c_command cmd;
3460 int i;
3461 int result = -EIO;
3462
b830ebc9 3463 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3464
3465 if (!cmd.payloads)
3466 return result;
3467
3468 cmd.number_of_payloads = num;
3469 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3470 cmd.speed = 100;
3471
3472 for (i = 0; i < num; i++) {
3473 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3474 cmd.payloads[i].address = msgs[i].addr;
3475 cmd.payloads[i].length = msgs[i].len;
3476 cmd.payloads[i].data = msgs[i].buf;
3477 }
3478
3479 if (dal_i2caux_submit_i2c_command(
3480 ddc_service->ctx->i2caux,
3481 ddc_service->ddc_pin,
3482 &cmd))
3483 result = num;
3484
3485 kfree(cmd.payloads);
3486 return result;
3487}
3488
7578ecda 3489static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3490{
3491 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3492}
3493
3494static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3495 .master_xfer = amdgpu_dm_i2c_xfer,
3496 .functionality = amdgpu_dm_i2c_func,
3497};
3498
3ee6b26b
AD		 3499static struct amdgpu_i2c_adapter *
3500create_i2c(struct ddc_service *ddc_service,
3501 int link_index,
3502 int *res)
e7b07cee
HW		 3503{
3504 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3505 struct amdgpu_i2c_adapter *i2c;
3506
b830ebc9 3507 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 3508 if (!i2c)
3509 return NULL;
e7b07cee
HW		 3510 i2c->base.owner = THIS_MODULE;
3511 i2c->base.class = I2C_CLASS_DDC;
3512 i2c->base.dev.parent = &adev->pdev->dev;
3513 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3514 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3515 i2c_set_adapdata(&i2c->base, i2c);
3516 i2c->ddc_service = ddc_service;
3517
3518 return i2c;
3519}
3520
3521/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3522 * dc_link which will be represented by this aconnector.
3523 */
7578ecda
AD		 3524static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3525 struct amdgpu_dm_connector *aconnector,
3526 uint32_t link_index,
3527 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3528{
3529 int res = 0;
3530 int connector_type;
3531 struct dc *dc = dm->dc;
3532 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3533 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 3534
3535 link->priv = aconnector;
e7b07cee 3536
f1ad2f5e 3537 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3538
3539 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 3540 if (!i2c) {
3541 DRM_ERROR("Failed to create i2c adapter data\n");
3542 return -ENOMEM;
3543 }
3544
e7b07cee
HW		 3545 aconnector->i2c = i2c;
3546 res = i2c_add_adapter(&i2c->base);
3547
3548 if (res) {
3549 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3550 goto out_free;
3551 }
3552
3553 connector_type = to_drm_connector_type(link->connector_signal);
3554
3555 res = drm_connector_init(
3556 dm->ddev,
3557 &aconnector->base,
3558 &amdgpu_dm_connector_funcs,
3559 connector_type);
3560
3561 if (res) {
3562 DRM_ERROR("connector_init failed\n");
3563 aconnector->connector_id = -1;
3564 goto out_free;
3565 }
3566
3567 drm_connector_helper_add(
3568 &aconnector->base,
3569 &amdgpu_dm_connector_helper_funcs);
3570
96719c54
HW		 3571 if (aconnector->base.funcs->reset)
3572 aconnector->base.funcs->reset(&aconnector->base);
3573
e7b07cee
HW		 3574 amdgpu_dm_connector_init_helper(
3575 dm,
3576 aconnector,
3577 connector_type,
3578 link,
3579 link_index);
3580
3581 drm_mode_connector_attach_encoder(
3582 &aconnector->base, &aencoder->base);
3583
3584 drm_connector_register(&aconnector->base);
3585
3586 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3587 || connector_type == DRM_MODE_CONNECTOR_eDP)
3588 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3589
3590#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3591 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3592
3593 /* NOTE: this currently will create backlight device even if a panel
3594 * is not connected to the eDP/LVDS connector.
3595 *
3596 * This is less than ideal but we don't have sink information at this
3597 * stage since detection happens after. We can't do detection earlier
3598 * since MST detection needs connectors to be created first.
3599 */
3600 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3601 /* Event if registration failed, we should continue with
3602 * DM initialization because not having a backlight control
b830ebc9
HW		 3603 * is better then a black screen.
3604 */
e7b07cee
HW		 3605 amdgpu_dm_register_backlight_device(dm);
3606
3607 if (dm->backlight_dev)
3608 dm->backlight_link = link;
3609 }
3610#endif
3611
3612out_free:
3613 if (res) {
3614 kfree(i2c);
3615 aconnector->i2c = NULL;
3616 }
3617 return res;
3618}
3619
3620int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3621{
3622 switch (adev->mode_info.num_crtc) {
3623 case 1:
3624 return 0x1;
3625 case 2:
3626 return 0x3;
3627 case 3:
3628 return 0x7;
3629 case 4:
3630 return 0xf;
3631 case 5:
3632 return 0x1f;
3633 case 6:
3634 default:
3635 return 0x3f;
3636 }
3637}
3638
7578ecda
AD		 3639static int amdgpu_dm_encoder_init(struct drm_device *dev,
3640 struct amdgpu_encoder *aencoder,
3641 uint32_t link_index)
e7b07cee
HW		 3642{
3643 struct amdgpu_device *adev = dev->dev_private;
3644
3645 int res = drm_encoder_init(dev,
3646 &aencoder->base,
3647 &amdgpu_dm_encoder_funcs,
3648 DRM_MODE_ENCODER_TMDS,
3649 NULL);
3650
3651 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3652
3653 if (!res)
3654 aencoder->encoder_id = link_index;
3655 else
3656 aencoder->encoder_id = -1;
3657
3658 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3659
3660 return res;
3661}
3662
3ee6b26b
AD		 3663static void manage_dm_interrupts(struct amdgpu_device *adev,
3664 struct amdgpu_crtc *acrtc,
3665 bool enable)
e7b07cee
HW		 3666{
3667 /*
3668 * this is not correct translation but will work as soon as VBLANK
3669 * constant is the same as PFLIP
3670 */
3671 int irq_type =
3672 amdgpu_crtc_idx_to_irq_type(
3673 adev,
3674 acrtc->crtc_id);
3675
3676 if (enable) {
3677 drm_crtc_vblank_on(&acrtc->base);
3678 amdgpu_irq_get(
3679 adev,
3680 &adev->pageflip_irq,
3681 irq_type);
3682 } else {
3683
3684 amdgpu_irq_put(
3685 adev,
3686 &adev->pageflip_irq,
3687 irq_type);
3688 drm_crtc_vblank_off(&acrtc->base);
3689 }
3690}
3691
3ee6b26b
AD		 3692static bool
3693is_scaling_state_different(const struct dm_connector_state *dm_state,
3694 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3695{
3696 if (dm_state->scaling != old_dm_state->scaling)
3697 return true;
3698 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3699 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3700 return true;
3701 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3702 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3703 return true;
b830ebc9
HW		 3704 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3705 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3706 return true;
e7b07cee
HW		 3707 return false;
3708}
3709
3ee6b26b
AD		 3710static void remove_stream(struct amdgpu_device *adev,
3711 struct amdgpu_crtc *acrtc,
3712 struct dc_stream_state *stream)
e7b07cee
HW		 3713{
3714 /* this is the update mode case */
3715 if (adev->dm.freesync_module)
3716 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3717
3718 acrtc->otg_inst = -1;
3719 acrtc->enabled = false;
3720}
3721
7578ecda
AD		 3722static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3723 struct dc_cursor_position *position)
2a8f6ccb
HW		 3724{
3725 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3726 int x, y;
3727 int xorigin = 0, yorigin = 0;
3728
3729 if (!crtc || !plane->state->fb) {
3730 position->enable = false;
3731 position->x = 0;
3732 position->y = 0;
3733 return 0;
3734 }
3735
3736 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3737 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3738 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3739 __func__,
3740 plane->state->crtc_w,
3741 plane->state->crtc_h);
3742 return -EINVAL;
3743 }
3744
3745 x = plane->state->crtc_x;
3746 y = plane->state->crtc_y;
3747 /* avivo cursor are offset into the total surface */
3748 x += crtc->primary->state->src_x >> 16;
3749 y += crtc->primary->state->src_y >> 16;
3750 if (x < 0) {
3751 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3752 x = 0;
3753 }
3754 if (y < 0) {
3755 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3756 y = 0;
3757 }
3758 position->enable = true;
3759 position->x = x;
3760 position->y = y;
3761 position->x_hotspot = xorigin;
3762 position->y_hotspot = yorigin;
3763
3764 return 0;
3765}
3766
3ee6b26b
AD		 3767static void handle_cursor_update(struct drm_plane *plane,
3768 struct drm_plane_state *old_plane_state)
e7b07cee 3769{
2a8f6ccb
HW		 3770 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3771 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3772 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3773 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3774 uint64_t address = afb ? afb->address : 0;
3775 struct dc_cursor_position position;
3776 struct dc_cursor_attributes attributes;
3777 int ret;
3778
e7b07cee
HW		 3779 if (!plane->state->fb && !old_plane_state->fb)
3780 return;
3781
f1ad2f5e 3782 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3783 __func__,
3784 amdgpu_crtc->crtc_id,
3785 plane->state->crtc_w,
3786 plane->state->crtc_h);
2a8f6ccb
HW		 3787
3788 ret = get_cursor_position(plane, crtc, &position);
3789 if (ret)
3790 return;
3791
3792 if (!position.enable) {
3793 /* turn off cursor */
3794 if (crtc_state && crtc_state->stream)
3795 dc_stream_set_cursor_position(crtc_state->stream,
3796 &position);
3797 return;
e7b07cee 3798 }
e7b07cee 3799
2a8f6ccb
HW		 3800 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3801 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3802
3803 attributes.address.high_part = upper_32_bits(address);
3804 attributes.address.low_part = lower_32_bits(address);
3805 attributes.width = plane->state->crtc_w;
3806 attributes.height = plane->state->crtc_h;
3807 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3808 attributes.rotation_angle = 0;
3809 attributes.attribute_flags.value = 0;
3810
3811 attributes.pitch = attributes.width;
3812
886daac9
JZ		 3813 if (crtc_state->stream) {
3814 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3815 &attributes))
3816 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3817
2a8f6ccb
HW		 3818 if (!dc_stream_set_cursor_position(crtc_state->stream,
3819 &position))
3820 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3821 }
2a8f6ccb 3822}
e7b07cee
HW		 3823
3824static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3825{
3826
3827 assert_spin_locked(&acrtc->base.dev->event_lock);
3828 WARN_ON(acrtc->event);
3829
3830 acrtc->event = acrtc->base.state->event;
3831
3832 /* Set the flip status */
3833 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3834
3835 /* Mark this event as consumed */
3836 acrtc->base.state->event = NULL;
3837
3838 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3839 acrtc->crtc_id);
3840}
3841
3842/*
3843 * Executes flip
3844 *
3845 * Waits on all BO's fences and for proper vblank count
3846 */
3ee6b26b
AD		 3847static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3848 struct drm_framebuffer *fb,
bc6828e0
BL		 3849 uint32_t target,
3850 struct dc_state *state)
e7b07cee
HW		 3851{
3852 unsigned long flags;
3853 uint32_t target_vblank;
3854 int r, vpos, hpos;
3855 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3856 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3857 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3858 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3859 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3860 struct dc_flip_addrs addr = { {0} };
3be5262e 3861 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3862 struct dc_surface_update surface_updates[1] = { {0} };
3863 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3864
3865
3866 /* Prepare wait for target vblank early - before the fence-waits */
3867 target_vblank = target - drm_crtc_vblank_count(crtc) +
3868 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3869
b830ebc9 3870 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3871 * explicitly on fences instead
3872 * and in general should be called for
3873 * blocking commit to as per framework helpers
b830ebc9 3874 */
e7b07cee
HW		 3875 r = amdgpu_bo_reserve(abo, true);
3876 if (unlikely(r != 0)) {
3877 DRM_ERROR("failed to reserve buffer before flip\n");
3878 WARN_ON(1);
3879 }
3880
3881 /* Wait for all fences on this FB */
3882 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3883 MAX_SCHEDULE_TIMEOUT) < 0);
3884
3885 amdgpu_bo_unreserve(abo);
3886
3887 /* Wait until we're out of the vertical blank period before the one
3888 * targeted by the flip
3889 */
3890 while ((acrtc->enabled &&
3891 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3892 &vpos, &hpos, NULL, NULL,
3893 &crtc->hwmode)
3894 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3895 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3896 (int)(target_vblank -
3897 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3898 usleep_range(1000, 1100);
3899 }
3900
3901 /* Flip */
3902 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3903 /* update crtc fb */
3904 crtc->primary->fb = fb;
3905
3906 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3907 WARN_ON(!acrtc_state->stream);
3908
3909 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3910 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3911 addr.flip_immediate = async_flip;
3912
3913
3914 if (acrtc->base.state->event)
3915 prepare_flip_isr(acrtc);
3916
3be5262e 3917 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3918 surface_updates->flip_addr = &addr;
3919
3920
bc6828e0
BL		 3921 dc_commit_updates_for_stream(adev->dm.dc,
3922 surface_updates,
3923 1,
3924 acrtc_state->stream,
3925 NULL,
3926 &surface_updates->surface,
3927 state);
e7b07cee
HW		 3928
3929 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3930 __func__,
3931 addr.address.grph.addr.high_part,
3932 addr.address.grph.addr.low_part);
3933
3934
3935 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3936}
3937
3be5262e 3938static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 3939 struct drm_device *dev,
3940 struct amdgpu_display_manager *dm,
3941 struct drm_crtc *pcrtc,
3942 bool *wait_for_vblank)
e7b07cee
HW		 3943{
3944 uint32_t i;
3945 struct drm_plane *plane;
0bc9706d 3946 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 3947 struct dc_stream_state *dc_stream_attach;
3be5262e 3948 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 3949 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 3950 struct drm_crtc_state *new_pcrtc_state =
3951 drm_atomic_get_new_crtc_state(state, pcrtc);
3952 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
bc6828e0 3953 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 3954 int planes_count = 0;
3955 unsigned long flags;
3956
3957 /* update planes when needed */
0bc9706d
LSL		 3958 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3959 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 3960 struct drm_crtc_state *new_crtc_state;
0bc9706d 3961 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 3962 bool pflip_needed;
54d76575 3963 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 3964
3965 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3966 handle_cursor_update(plane, old_plane_state);
3967 continue;
3968 }
3969
f5ba60fe
DD		 3970 if (!fb || !crtc || pcrtc != crtc)
3971 continue;
3972
3973 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
3974 if (!new_crtc_state->active)
e7b07cee
HW		 3975 continue;
3976
3977 pflip_needed = !state->allow_modeset;
3978
3979 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3980 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3981 DRM_ERROR("%s: acrtc %d, already busy\n",
3982 __func__,
3983 acrtc_attach->crtc_id);
b830ebc9 3984 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3985 WARN_ON(1);
3986 }
3987 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3988
3989 if (!pflip_needed) {
54d76575 3990 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 3991
54d76575 3992 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 3993
3994 dc_stream_attach = acrtc_state->stream;
3995 planes_count++;
3996
0bc9706d 3997 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 3998 /* Assume even ONE crtc with immediate flip means
3999 * entire can't wait for VBLANK
4000 * TODO Check if it's correct
4001 */
4002 *wait_for_vblank =
0bc9706d 4003 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 4004 false : true;
4005
4006 /* TODO: Needs rework for multiplane flip */
4007 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4008 drm_crtc_vblank_get(crtc);
4009
4010 amdgpu_dm_do_flip(
4011 crtc,
4012 fb,
bc6828e0
BL		 4013 drm_crtc_vblank_count(crtc) + *wait_for_vblank,
4014 dm_state->context);
e7b07cee
HW		 4015 }
4016
4017 }
4018
4019 if (planes_count) {
4020 unsigned long flags;
4021
0bc9706d 4022 if (new_pcrtc_state->event) {
e7b07cee
HW		 4023
4024 drm_crtc_vblank_get(pcrtc);
4025
4026 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4027 prepare_flip_isr(acrtc_attach);
4028 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4029 }
4030
3be5262e
HW		 4031 if (false == dc_commit_planes_to_stream(dm->dc,
4032 plane_states_constructed,
4033 planes_count,
bc6828e0
BL		 4034 dc_stream_attach,
4035 dm_state->context))
3be5262e 4036 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4037 } else {
4038 /*TODO BUG Here should go disable planes on CRTC. */
4039 }
4040}
4041
27b3f4fc
LSL		 4042/**
4043 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4044 * @crtc_state: the DRM CRTC state
4045 * @stream_state: the DC stream state.
4046 *
4047 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4048 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4049 */
4050static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4051 struct dc_stream_state *stream_state)
4052{
4053 stream_state->mode_changed = crtc_state->mode_changed;
4054}
e7b07cee 4055
7578ecda
AD		 4056static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4057 struct drm_atomic_state *state,
4058 bool nonblock)
e7b07cee
HW		 4059{
4060 struct drm_crtc *crtc;
c2cea706 4061 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4062 struct amdgpu_device *adev = dev->dev_private;
4063 int i;
4064
4065 /*
4066 * We evade vblanks and pflips on crtc that
4067 * should be changed. We do it here to flush & disable
4068 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4069 * it will update crtc->dm_crtc_state->stream pointer which is used in
4070 * the ISRs.
4071 */
c2cea706 4072 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4073 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 4074 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4075
54d76575 4076 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 4077 manage_dm_interrupts(adev, acrtc, false);
4078 }
fc9e9920
S		 4079 /* Add check here for SoC's that support hardware cursor plane, to
4080 * unset legacy_cursor_update */
e7b07cee
HW		 4081
4082 return drm_atomic_helper_commit(dev, state, nonblock);
4083
4084 /*TODO Handle EINTR, reenable IRQ*/
4085}
4086
7578ecda 4087static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4088{
4089 struct drm_device *dev = state->dev;
4090 struct amdgpu_device *adev = dev->dev_private;
4091 struct amdgpu_display_manager *dm = &adev->dm;
4092 struct dm_atomic_state *dm_state;
4093 uint32_t i, j;
5cc6dcbd 4094 struct drm_crtc *crtc;
0bc9706d 4095 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4096 unsigned long flags;
4097 bool wait_for_vblank = true;
4098 struct drm_connector *connector;
c2cea706 4099 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4100 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
e7b07cee
HW		 4101
4102 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4103
4104 dm_state = to_dm_atomic_state(state);
4105
4106 /* update changed items */
0bc9706d 4107 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4108 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4109
54d76575
LSL		 4110 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4111 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4112
f1ad2f5e 4113 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4114 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4115 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4116 "connectors_changed:%d\n",
4117 acrtc->crtc_id,
0bc9706d
LSL		 4118 new_crtc_state->enable,
4119 new_crtc_state->active,
4120 new_crtc_state->planes_changed,
4121 new_crtc_state->mode_changed,
4122 new_crtc_state->active_changed,
4123 new_crtc_state->connectors_changed);
e7b07cee 4124
27b3f4fc
LSL		 4125 /* Copy all transient state flags into dc state */
4126 if (dm_new_crtc_state->stream) {
4127 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4128 dm_new_crtc_state->stream);
4129 }
4130
e7b07cee
HW		 4131 /* handles headless hotplug case, updating new_state and
4132 * aconnector as needed
4133 */
4134
54d76575 4135 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4136
f1ad2f5e 4137 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4138
54d76575 4139 if (!dm_new_crtc_state->stream) {
e7b07cee 4140 /*
b830ebc9
HW		 4141 * this could happen because of issues with
4142 * userspace notifications delivery.
4143 * In this case userspace tries to set mode on
4144 * display which is disconnect in fact.
4145 * dc_sink in NULL in this case on aconnector.
4146 * We expect reset mode will come soon.
4147 *
4148 * This can also happen when unplug is done
4149 * during resume sequence ended
4150 *
4151 * In this case, we want to pretend we still
4152 * have a sink to keep the pipe running so that
4153 * hw state is consistent with the sw state
4154 */
f1ad2f5e 4155 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4156 __func__, acrtc->base.base.id);
4157 continue;
4158 }
4159
54d76575
LSL		 4160 if (dm_old_crtc_state->stream)
4161 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 4162
e7b07cee 4163 acrtc->enabled = true;
0bc9706d
LSL		 4164 acrtc->hw_mode = new_crtc_state->mode;
4165 crtc->hwmode = new_crtc_state->mode;
4166 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4167 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4168
4169 /* i.e. reset mode */
54d76575
LSL		 4170 if (dm_old_crtc_state->stream)
4171 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4172 }
4173 } /* for_each_crtc_in_state() */
4174
4175 /*
4176 * Add streams after required streams from new and replaced streams
4177 * are removed from freesync module
4178 */
4179 if (adev->dm.freesync_module) {
8b8f27f9
LSL		 4180 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4181 new_crtc_state, i) {
c84dec2f 4182 struct amdgpu_dm_connector *aconnector = NULL;
f01a2cf0
LSL		 4183 struct dm_connector_state *dm_new_con_state = NULL;
4184 struct amdgpu_crtc *acrtc = NULL;
1c77d4ee 4185 bool modeset_needed;
b830ebc9 4186
54d76575 4187 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1c77d4ee
LSL		 4188 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4189 modeset_needed = modeset_required(
4190 new_crtc_state,
4191 dm_new_crtc_state->stream,
4192 dm_old_crtc_state->stream);
4193 /* We add stream to freesync if:
4194 * 1. Said stream is not null, and
4195 * 2. A modeset is requested. This means that the
4196 * stream was removed previously, and needs to be
4197 * replaced.
4198 */
4199 if (dm_new_crtc_state->stream == NULL ||
4200 !modeset_needed)
4201 continue;
4202
f01a2cf0 4203 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4204
f01a2cf0
LSL		 4205 aconnector =
4206 amdgpu_dm_find_first_crtc_matching_connector(
4207 state, crtc);
e7b07cee 4208 if (!aconnector) {
8b8f27f9
LSL		 4209 DRM_DEBUG_DRIVER("Atomic commit: Failed to "
4210 "find connector for acrtc "
4211 "id:%d skipping freesync "
4212 "init\n",
4213 acrtc->crtc_id);
e7b07cee
HW		 4214 continue;
4215 }
4216
4217 mod_freesync_add_stream(adev->dm.freesync_module,
f01a2cf0
LSL		 4218 dm_new_crtc_state->stream,
4219 &aconnector->caps);
4220 new_con_state = drm_atomic_get_new_connector_state(
4221 state, &aconnector->base);
4222 dm_new_con_state = to_dm_connector_state(new_con_state);
4223
1c77d4ee
LSL		 4224 mod_freesync_set_user_enable(adev->dm.freesync_module,
4225 &dm_new_crtc_state->stream,
4226 1,
4227 &dm_new_con_state->user_enable);
bfe1708c 4228 }
e7b07cee
HW		 4229 }
4230
fa2123db
ML		 4231 if (dm_state->context) {
4232 dm_enable_per_frame_crtc_master_sync(dm_state->context);
608ac7bb 4233 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
fa2123db 4234 }
e7b07cee 4235
0bc9706d 4236 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4237 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4238
54d76575 4239 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4240
54d76575 4241 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4242 const struct dc_stream_status *status =
54d76575 4243 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4244
4245 if (!status)
54d76575 4246 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4247 else
4248 acrtc->otg_inst = status->primary_otg_inst;
4249 }
4250 }
4251
ebdd27e1 4252 /* Handle scaling and underscan changes*/
c2cea706 4253 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4254 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4255 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4256 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4257 struct dc_stream_status *status = NULL;
4258
0bc9706d
LSL		 4259 if (acrtc)
4260 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4261
e7b07cee 4262 /* Skip any modesets/resets */
0bc9706d 4263 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4264 continue;
4265
4266 /* Skip any thing not scale or underscan changes */
54d76575 4267 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4268 continue;
4269
54d76575 4270 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4271
54d76575
LSL		 4272 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4273 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4274
70e8ffc5
HW		 4275 if (!dm_new_crtc_state->stream)
4276 continue;
4277
54d76575 4278 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4279 WARN_ON(!status);
3be5262e 4280 WARN_ON(!status->plane_count);
e7b07cee 4281
e7b07cee 4282 /*TODO How it works with MPO ?*/
3be5262e 4283 if (!dc_commit_planes_to_stream(
e7b07cee 4284 dm->dc,
3be5262e
HW		 4285 status->plane_states,
4286 status->plane_count,
bc6828e0
BL		 4287 dm_new_crtc_state->stream,
4288 dm_state->context))
e7b07cee
HW		 4289 dm_error("%s: Failed to update stream scaling!\n", __func__);
4290 }
4291
e1fc2dca
LSL		 4292 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4293 new_crtc_state, i) {
e7b07cee
HW		 4294 /*
4295 * loop to enable interrupts on newly arrived crtc
4296 */
e1fc2dca
LSL		 4297 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4298 bool modeset_needed;
b830ebc9 4299
54d76575 4300 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 4301 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4302 modeset_needed = modeset_required(
4303 new_crtc_state,
4304 dm_new_crtc_state->stream,
4305 dm_old_crtc_state->stream);
4306
4307 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4308 continue;
e7b07cee
HW		 4309
4310 if (adev->dm.freesync_module)
4311 mod_freesync_notify_mode_change(
e1fc2dca
LSL		 4312 adev->dm.freesync_module,
4313 &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4314
4315 manage_dm_interrupts(adev, acrtc, true);
4316 }
4317
4318 /* update planes when needed per crtc*/
5cc6dcbd 4319 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4320 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4321
54d76575 4322 if (dm_new_crtc_state->stream)
5cc6dcbd 4323 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4324 }
4325
4326
4327 /*
4328 * send vblank event on all events not handled in flip and
4329 * mark consumed event for drm_atomic_helper_commit_hw_done
4330 */
4331 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4332 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4333
0bc9706d
LSL		 4334 if (new_crtc_state->event)
4335 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4336
0bc9706d 4337 new_crtc_state->event = NULL;
e7b07cee
HW		 4338 }
4339 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4340
4341 /* Signal HW programming completion */
4342 drm_atomic_helper_commit_hw_done(state);
4343
4344 if (wait_for_vblank)
320a1274 4345 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 4346
4347 drm_atomic_helper_cleanup_planes(dev, state);
4348}
4349
4350
4351static int dm_force_atomic_commit(struct drm_connector *connector)
4352{
4353 int ret = 0;
4354 struct drm_device *ddev = connector->dev;
4355 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4356 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4357 struct drm_plane *plane = disconnected_acrtc->base.primary;
4358 struct drm_connector_state *conn_state;
4359 struct drm_crtc_state *crtc_state;
4360 struct drm_plane_state *plane_state;
4361
4362 if (!state)
4363 return -ENOMEM;
4364
4365 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4366
4367 /* Construct an atomic state to restore previous display setting */
4368
4369 /*
4370 * Attach connectors to drm_atomic_state
4371 */
4372 conn_state = drm_atomic_get_connector_state(state, connector);
4373
4374 ret = PTR_ERR_OR_ZERO(conn_state);
4375 if (ret)
4376 goto err;
4377
4378 /* Attach crtc to drm_atomic_state*/
4379 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4380
4381 ret = PTR_ERR_OR_ZERO(crtc_state);
4382 if (ret)
4383 goto err;
4384
4385 /* force a restore */
4386 crtc_state->mode_changed = true;
4387
4388 /* Attach plane to drm_atomic_state */
4389 plane_state = drm_atomic_get_plane_state(state, plane);
4390
4391 ret = PTR_ERR_OR_ZERO(plane_state);
4392 if (ret)
4393 goto err;
4394
4395
4396 /* Call commit internally with the state we just constructed */
4397 ret = drm_atomic_commit(state);
4398 if (!ret)
4399 return 0;
4400
4401err:
4402 DRM_ERROR("Restoring old state failed with %i\n", ret);
4403 drm_atomic_state_put(state);
4404
4405 return ret;
4406}
4407
4408/*
4409 * This functions handle all cases when set mode does not come upon hotplug.
4410 * This include when the same display is unplugged then plugged back into the
4411 * same port and when we are running without usermode desktop manager supprot
4412 */
3ee6b26b
AD		 4413void dm_restore_drm_connector_state(struct drm_device *dev,
4414 struct drm_connector *connector)
e7b07cee 4415{
c84dec2f 4416 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4417 struct amdgpu_crtc *disconnected_acrtc;
4418 struct dm_crtc_state *acrtc_state;
4419
4420 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4421 return;
4422
4423 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 4424 if (!disconnected_acrtc)
4425 return;
e7b07cee 4426
70e8ffc5
HW		 4427 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4428 if (!acrtc_state->stream)
e7b07cee
HW		 4429 return;
4430
4431 /*
4432 * If the previous sink is not released and different from the current,
4433 * we deduce we are in a state where we can not rely on usermode call
4434 * to turn on the display, so we do it here
4435 */
4436 if (acrtc_state->stream->sink != aconnector->dc_sink)
4437 dm_force_atomic_commit(&aconnector->base);
4438}
4439
e7b07cee
HW		 4440/*`
4441 * Grabs all modesetting locks to serialize against any blocking commits,
4442 * Waits for completion of all non blocking commits.
4443 */
3ee6b26b
AD		 4444static int do_aquire_global_lock(struct drm_device *dev,
4445 struct drm_atomic_state *state)
e7b07cee
HW		 4446{
4447 struct drm_crtc *crtc;
4448 struct drm_crtc_commit *commit;
4449 long ret;
4450
4451 /* Adding all modeset locks to aquire_ctx will
4452 * ensure that when the framework release it the
4453 * extra locks we are locking here will get released to
4454 */
4455 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4456 if (ret)
4457 return ret;
4458
4459 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4460 spin_lock(&crtc->commit_lock);
4461 commit = list_first_entry_or_null(&crtc->commit_list,
4462 struct drm_crtc_commit, commit_entry);
4463 if (commit)
4464 drm_crtc_commit_get(commit);
4465 spin_unlock(&crtc->commit_lock);
4466
4467 if (!commit)
4468 continue;
4469
4470 /* Make sure all pending HW programming completed and
4471 * page flips done
4472 */
4473 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4474
4475 if (ret > 0)
4476 ret = wait_for_completion_interruptible_timeout(
4477 &commit->flip_done, 10*HZ);
4478
4479 if (ret == 0)
4480 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4481 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4482
4483 drm_crtc_commit_put(commit);
4484 }
4485
4486 return ret < 0 ? ret : 0;
4487}
4488
3ee6b26b
AD		 4489static int dm_update_crtcs_state(struct dc *dc,
4490 struct drm_atomic_state *state,
4491 bool enable,
4492 bool *lock_and_validation_needed)
e7b07cee 4493{
e7b07cee 4494 struct drm_crtc *crtc;
c2cea706 4495 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4496 int i;
54d76575 4497 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4498 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4499 struct dc_stream_state *new_stream;
62f55537 4500 int ret = 0;
d4d4a645 4501
62f55537
AG		 4502 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4503 /* update changed items */
c2cea706 4504 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4505 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4506 struct amdgpu_dm_connector *aconnector = NULL;
c2cea706 4507 struct drm_connector_state *new_con_state = NULL;
62f55537 4508 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4509
9635b754
DS		 4510 new_stream = NULL;
4511
54d76575
LSL		 4512 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4513 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4514 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4515
1daf8c63 4516 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4517
62f55537 4518 /* TODO This hack should go away */
f4ac176e
JZ		 4519 if (aconnector && enable) {
4520 // Make sure fake sink is created in plug-in scenario
c2cea706
LSL		 4521 new_con_state = drm_atomic_get_connector_state(state,
4522 &aconnector->base);
19f89e23 4523
c2cea706
LSL		 4524 if (IS_ERR(new_con_state)) {
4525 ret = PTR_ERR_OR_ZERO(new_con_state);
62f55537
AG		 4526 break;
4527 }
19f89e23 4528
c2cea706 4529 dm_conn_state = to_dm_connector_state(new_con_state);
19f89e23 4530
62f55537 4531 new_stream = create_stream_for_sink(aconnector,
c2cea706 4532 &new_crtc_state->mode,
62f55537 4533 dm_conn_state);
19f89e23 4534
62f55537
AG		 4535 /*
4536 * we can have no stream on ACTION_SET if a display
4537 * was disconnected during S3, in this case it not and
4538 * error, the OS will be updated after detection, and
4539 * do the right thing on next atomic commit
4540 */
19f89e23 4541
62f55537 4542 if (!new_stream) {
f1ad2f5e 4543 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4544 __func__, acrtc->base.base.id);
4545 break;
19f89e23 4546 }
e7b07cee 4547
a97599a4
LSL		 4548 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4549 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4550 new_crtc_state->mode_changed = false;
4551 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4552 new_crtc_state->mode_changed);
4553 }
62f55537 4554 }
b830ebc9 4555
c2cea706 4556 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4557 goto next_crtc;
e7b07cee 4558
f1ad2f5e 4559 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4560 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4561 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4562 "connectors_changed:%d\n",
4563 acrtc->crtc_id,
c2cea706
LSL		 4564 new_crtc_state->enable,
4565 new_crtc_state->active,
4566 new_crtc_state->planes_changed,
4567 new_crtc_state->mode_changed,
4568 new_crtc_state->active_changed,
4569 new_crtc_state->connectors_changed);
e7b07cee 4570
62f55537
AG		 4571 /* Remove stream for any changed/disabled CRTC */
4572 if (!enable) {
4573
54d76575 4574 if (!dm_old_crtc_state->stream)
9635b754 4575 goto next_crtc;
62f55537 4576
f1ad2f5e 4577 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4578 crtc->base.id);
e7b07cee 4579
1dc90497 4580 /* i.e. reset mode */
62c933f9 4581 if (dc_remove_stream_from_ctx(
62f55537
AG		 4582 dc,
4583 dm_state->context,
62c933f9 4584 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4585 ret = -EINVAL;
9635b754 4586 goto fail;
62f55537
AG		 4587 }
4588
54d76575
LSL		 4589 dc_stream_release(dm_old_crtc_state->stream);
4590 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4591
4592 *lock_and_validation_needed = true;
4593
4594 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4595 /*
4596 * Quick fix to prevent NULL pointer on new_stream when
4597 * added MST connectors not found in existing crtc_state in the chained mode
4598 * TODO: need to dig out the root cause of that
4599 */
4600 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4601 goto next_crtc;
62f55537 4602
c2cea706 4603 if (modereset_required(new_crtc_state))
9635b754 4604 goto next_crtc;
62f55537 4605
c2cea706 4606 if (modeset_required(new_crtc_state, new_stream,
54d76575 4607 dm_old_crtc_state->stream)) {
62f55537 4608
54d76575 4609 WARN_ON(dm_new_crtc_state->stream);
62f55537 4610
54d76575 4611 dm_new_crtc_state->stream = new_stream;
27b3f4fc 4612
62f55537
AG		 4613 dc_stream_retain(new_stream);
4614
f1ad2f5e 4615 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4616 crtc->base.id);
1dc90497 4617
13ab1b44 4618 if (dc_add_stream_to_ctx(
1dc90497
AG		 4619 dc,
4620 dm_state->context,
13ab1b44 4621 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4622 ret = -EINVAL;
9635b754 4623 goto fail;
1dc90497
AG		 4624 }
4625
62f55537 4626 *lock_and_validation_needed = true;
9b690ef3 4627 }
62f55537 4628 }
9b690ef3 4629
9635b754 4630next_crtc:
62f55537
AG		 4631 /* Release extra reference */
4632 if (new_stream)
4633 dc_stream_release(new_stream);
4634 }
e7b07cee 4635
62f55537 4636 return ret;
9635b754
DS		 4637
4638fail:
4639 if (new_stream)
4640 dc_stream_release(new_stream);
4641 return ret;
62f55537 4642}
9b690ef3 4643
3ee6b26b
AD		 4644static int dm_update_planes_state(struct dc *dc,
4645 struct drm_atomic_state *state,
4646 bool enable,
4647 bool *lock_and_validation_needed)
62f55537
AG		 4648{
4649 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4650 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4651 struct drm_plane *plane;
4652 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4653 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4654 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4655 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4656 int i ;
4657 /* TODO return page_flip_needed() function */
4658 bool pflip_needed = !state->allow_modeset;
4659 int ret = 0;
e7b07cee 4660
9b690ef3 4661
62f55537
AG		 4662 /* Add new planes */
4663 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4664 new_plane_crtc = new_plane_state->crtc;
4665 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4666 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4667 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4668
4669 /*TODO Implement atomic check for cursor plane */
4670 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4671 continue;
9b690ef3 4672
62f55537
AG		 4673 /* Remove any changed/removed planes */
4674 if (!enable) {
843e3c7d
S		 4675 if (pflip_needed)
4676 continue;
a7b06724 4677
62f55537
AG		 4678 if (!old_plane_crtc)
4679 continue;
4680
0bc9706d
LSL		 4681 old_crtc_state = drm_atomic_get_old_crtc_state(
4682 state, old_plane_crtc);
54d76575 4683 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4684
54d76575 4685 if (!dm_old_crtc_state->stream)
62f55537
AG		 4686 continue;
4687
f1ad2f5e 4688 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4689 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4690
62f55537
AG		 4691 if (!dc_remove_plane_from_context(
4692 dc,
54d76575
LSL		 4693 dm_old_crtc_state->stream,
4694 dm_old_plane_state->dc_state,
62f55537
AG		 4695 dm_state->context)) {
4696
4697 ret = EINVAL;
4698 return ret;
e7b07cee
HW		 4699 }
4700
9b690ef3 4701
54d76575
LSL		 4702 dc_plane_state_release(dm_old_plane_state->dc_state);
4703 dm_new_plane_state->dc_state = NULL;
1dc90497 4704
62f55537 4705 *lock_and_validation_needed = true;
1dc90497 4706
62f55537 4707 } else { /* Add new planes */
9fe8f03b 4708 struct dc_plane_state *dc_new_plane_state;
1dc90497 4709
62f55537
AG		 4710 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4711 continue;
e7b07cee 4712
62f55537
AG		 4713 if (!new_plane_crtc)
4714 continue;
e7b07cee 4715
62f55537 4716 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4717 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4718
54d76575 4719 if (!dm_new_crtc_state->stream)
62f55537
AG		 4720 continue;
4721
843e3c7d
S		 4722 if (pflip_needed)
4723 continue;
62f55537 4724
54d76575 4725 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4726
9fe8f03b
LSL		 4727 dc_new_plane_state = dc_create_plane_state(dc);
4728 if (!dc_new_plane_state) {
62f55537
AG		 4729 ret = -EINVAL;
4730 return ret;
4731 }
4732
9fe8f03b
LSL		 4733 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4734 plane->base.id, new_plane_crtc->base.id);
4735
62f55537
AG		 4736 ret = fill_plane_attributes(
4737 new_plane_crtc->dev->dev_private,
9fe8f03b 4738 dc_new_plane_state,
62f55537 4739 new_plane_state,
9817d5f5 4740 new_crtc_state);
9fe8f03b
LSL		 4741 if (ret) {
4742 dc_plane_state_release(dc_new_plane_state);
62f55537 4743 return ret;
9fe8f03b 4744 }
62f55537 4745
9fe8f03b
LSL		 4746 /*
4747 * Any atomic check errors that occur after this will
4748 * not need a release. The plane state will be attached
4749 * to the stream, and therefore part of the atomic
4750 * state. It'll be released when the atomic state is
4751 * cleaned.
4752 */
62f55537
AG		 4753 if (!dc_add_plane_to_context(
4754 dc,
54d76575 4755 dm_new_crtc_state->stream,
9fe8f03b 4756 dc_new_plane_state,
62f55537
AG		 4757 dm_state->context)) {
4758
9fe8f03b 4759 dc_plane_state_release(dc_new_plane_state);
62f55537
AG		 4760 ret = -EINVAL;
4761 return ret;
e7b07cee 4762 }
62f55537 4763
9fe8f03b
LSL		 4764 dm_new_plane_state->dc_state = dc_new_plane_state;
4765
000b59ea
LSL		 4766 /* Tell DC to do a full surface update every time there
4767 * is a plane change. Inefficient, but works for now.
4768 */
4769 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
4770
62f55537 4771 *lock_and_validation_needed = true;
e7b07cee 4772 }
62f55537 4773 }
e7b07cee
HW		 4774
4775
62f55537
AG		 4776 return ret;
4777}
4778
36cc549d
S		 4779static int dm_atomic_check_plane_state_fb(struct drm_atomic_state *state,
4780 struct drm_crtc *crtc)
4781{
4782 struct drm_plane *plane;
4783 struct drm_crtc_state *crtc_state;
4784
4785 WARN_ON(!drm_atomic_get_new_crtc_state(state, crtc));
4786
4787 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
4788 struct drm_plane_state *plane_state =
4789 drm_atomic_get_plane_state(state, plane);
4790
4791 if (IS_ERR(plane_state))
4792 return -EDEADLK;
4793
4794 crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc);
cd2d6c92
S		 4795 if (IS_ERR(crtc_state))
4796 return PTR_ERR(crtc_state);
4797
36cc549d
S		 4798 if (crtc->primary == plane && crtc_state->active) {
4799 if (!plane_state->fb)
4800 return -EINVAL;
4801 }
4802 }
4803 return 0;
4804}
4805
7578ecda
AD		 4806static int amdgpu_dm_atomic_check(struct drm_device *dev,
4807 struct drm_atomic_state *state)
62f55537 4808{
62f55537
AG		 4809 struct amdgpu_device *adev = dev->dev_private;
4810 struct dc *dc = adev->dm.dc;
4811 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4812 struct drm_connector *connector;
c2cea706 4813 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4814 struct drm_crtc *crtc;
fc9e9920 4815 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1e88ad0a 4816 int ret, i;
e7b07cee 4817
62f55537
AG		 4818 /*
4819 * This bool will be set for true for any modeset/reset
4820 * or plane update which implies non fast surface update.
4821 */
4822 bool lock_and_validation_needed = false;
4823
4824 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 4825 if (ret)
4826 goto fail;
62f55537 4827
1e88ad0a 4828 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
36cc549d
S		 4829 ret = dm_atomic_check_plane_state_fb(state, crtc);
4830 if (ret)
4831 goto fail;
4832
1e88ad0a
S		 4833 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
4834 !new_crtc_state->color_mgmt_changed)
4835 continue;
7bef1af3 4836
1e88ad0a
S		 4837 if (!new_crtc_state->enable)
4838 continue;
fc9e9920 4839
1e88ad0a
S		 4840 ret = drm_atomic_add_affected_connectors(state, crtc);
4841 if (ret)
4842 return ret;
fc9e9920 4843
1e88ad0a
S		 4844 ret = drm_atomic_add_affected_planes(state, crtc);
4845 if (ret)
4846 goto fail;
e7b07cee
HW		 4847 }
4848
62f55537
AG		 4849 dm_state->context = dc_create_state();
4850 ASSERT(dm_state->context);
f36cc577 4851 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4852
4853 /* Remove exiting planes if they are modified */
4854 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4855 if (ret) {
4856 goto fail;
4857 }
4858
4859 /* Disable all crtcs which require disable */
4860 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4861 if (ret) {
4862 goto fail;
4863 }
4864
4865 /* Enable all crtcs which require enable */
4866 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4867 if (ret) {
4868 goto fail;
4869 }
4870
4871 /* Add new/modified planes */
4872 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4873 if (ret) {
4874 goto fail;
4875 }
4876
b349f76e
ES		 4877 /* Run this here since we want to validate the streams we created */
4878 ret = drm_atomic_helper_check_planes(dev, state);
4879 if (ret)
4880 goto fail;
62f55537 4881
ebdd27e1 4882 /* Check scaling and underscan changes*/
e7b07cee
HW		 4883 /*TODO Removed scaling changes validation due to inability to commit
4884 * new stream into context w\o causing full reset. Need to
4885 * decide how to handle.
4886 */
c2cea706 4887 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4888 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4889 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4890 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4891
4892 /* Skip any modesets/resets */
0bc9706d
LSL		 4893 if (!acrtc || drm_atomic_crtc_needs_modeset(
4894 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 4895 continue;
4896
b830ebc9 4897 /* Skip any thing not scale or underscan changes */
54d76575 4898 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4899 continue;
4900
4901 lock_and_validation_needed = true;
4902 }
4903
e7b07cee
HW		 4904 /*
4905 * For full updates case when
4906 * removing/adding/updating streams on once CRTC while flipping
4907 * on another CRTC,
4908 * acquiring global lock will guarantee that any such full
4909 * update commit
4910 * will wait for completion of any outstanding flip using DRMs
4911 * synchronization events.
4912 */
4913
4914 if (lock_and_validation_needed) {
4915
4916 ret = do_aquire_global_lock(dev, state);
4917 if (ret)
4918 goto fail;
1dc90497 4919
e750d56d 4920 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 4921 ret = -EINVAL;
4922 goto fail;
4923 }
4924 }
4925
4926 /* Must be success */
4927 WARN_ON(ret);
4928 return ret;
4929
4930fail:
4931 if (ret == -EDEADLK)
01e28f9c 4932 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 4933 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 4934 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 4935 else
01e28f9c 4936 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 4937
4938 return ret;
4939}
4940
3ee6b26b
AD		 4941static bool is_dp_capable_without_timing_msa(struct dc *dc,
4942 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 4943{
4944 uint8_t dpcd_data;
4945 bool capable = false;
4946
c84dec2f 4947 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 4948 dm_helpers_dp_read_dpcd(
4949 NULL,
c84dec2f 4950 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 4951 DP_DOWN_STREAM_PORT_COUNT,
4952 &dpcd_data,
4953 sizeof(dpcd_data))) {
4954 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4955 }
4956
4957 return capable;
4958}
3ee6b26b
AD		 4959void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4960 struct edid *edid)
e7b07cee
HW		 4961{
4962 int i;
4963 uint64_t val_capable;
4964 bool edid_check_required;
4965 struct detailed_timing *timing;
4966 struct detailed_non_pixel *data;
4967 struct detailed_data_monitor_range *range;
c84dec2f
HW		 4968 struct amdgpu_dm_connector *amdgpu_dm_connector =
4969 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4970
4971 struct drm_device *dev = connector->dev;
4972 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4973
e7b07cee 4974 edid_check_required = false;
c84dec2f 4975 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 4976 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4977 return;
4978 }
4979 if (!adev->dm.freesync_module)
4980 return;
4981 /*
4982 * if edid non zero restrict freesync only for dp and edp
4983 */
4984 if (edid) {
c84dec2f
HW		 4985 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4986 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 4987 edid_check_required = is_dp_capable_without_timing_msa(
4988 adev->dm.dc,
c84dec2f 4989 amdgpu_dm_connector);
e7b07cee
HW		 4990 }
4991 }
4992 val_capable = 0;
4993 if (edid_check_required == true && (edid->version > 1 ||
4994 (edid->version == 1 && edid->revision > 1))) {
4995 for (i = 0; i < 4; i++) {
4996
4997 timing = &edid->detailed_timings[i];
4998 data = &timing->data.other_data;
4999 range = &data->data.range;
5000 /*
5001 * Check if monitor has continuous frequency mode
5002 */
5003 if (data->type != EDID_DETAIL_MONITOR_RANGE)
5004 continue;
5005 /*
5006 * Check for flag range limits only. If flag == 1 then
5007 * no additional timing information provided.
5008 * Default GTF, GTF Secondary curve and CVT are not
5009 * supported
5010 */
5011 if (range->flags != 1)
5012 continue;
5013
c84dec2f
HW		 5014 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
5015 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
5016 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 5017 range->pixel_clock_mhz * 10;
5018 break;
5019 }
5020
c84dec2f
HW		 5021 if (amdgpu_dm_connector->max_vfreq -
5022 amdgpu_dm_connector->min_vfreq > 10) {
5023 amdgpu_dm_connector->caps.supported = true;
5024 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
5025 amdgpu_dm_connector->min_vfreq * 1000000;
5026 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
5027 amdgpu_dm_connector->max_vfreq * 1000000;
e7b07cee
HW		 5028 val_capable = 1;
5029 }
5030 }
5031
5032 /*
5033 * TODO figure out how to notify user-mode or DRM of freesync caps
5034 * once we figure out how to deal with freesync in an upstreamable
5035 * fashion
5036 */
5037
5038}
5039
3ee6b26b 5040void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 5041{
5042 /*
5043 * TODO fill in once we figure out how to deal with freesync in
5044 * an upstreamable fashion
5045 */
5046}
Linux 6.x block layer and io_uring tree(s)