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drm/amd/display: drop unused dm_delay_in_microseconds
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
62#include "raven1/DCN/dcn_1_0_offset.h"
63#include "raven1/DCN/dcn_1_0_sh_mask.h"
64#include "vega10/soc15ip.h"
65
66#include "soc15_common.h"
67#endif
68
e7b07cee
HW		 69#include "modules/inc/mod_freesync.h"
70
71#include "i2caux_interface.h"
72
7578ecda
AD		 73/* basic init/fini API */
74static int amdgpu_dm_init(struct amdgpu_device *adev);
75static void amdgpu_dm_fini(struct amdgpu_device *adev);
76
77/* initializes drm_device display related structures, based on the information
78 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
79 * drm_encoder, drm_mode_config
80 *
81 * Returns 0 on success
82 */
83static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
84/* removes and deallocates the drm structures, created by the above function */
85static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
86
87static void
88amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
89
90static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
91 struct amdgpu_plane *aplane,
92 unsigned long possible_crtcs);
93static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
94 struct drm_plane *plane,
95 uint32_t link_index);
96static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
97 struct amdgpu_dm_connector *amdgpu_dm_connector,
98 uint32_t link_index,
99 struct amdgpu_encoder *amdgpu_encoder);
100static int amdgpu_dm_encoder_init(struct drm_device *dev,
101 struct amdgpu_encoder *aencoder,
102 uint32_t link_index);
103
104static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
105
106static int amdgpu_dm_atomic_commit(struct drm_device *dev,
107 struct drm_atomic_state *state,
108 bool nonblock);
109
110static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
111
112static int amdgpu_dm_atomic_check(struct drm_device *dev,
113 struct drm_atomic_state *state);
114
115
116
e7b07cee 117
e04a6123 118static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 119 DRM_PLANE_TYPE_PRIMARY,
120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125};
126
e04a6123 127static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 128 DRM_PLANE_TYPE_PRIMARY,
129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
132};
133
e04a6123 134static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 135 DRM_PLANE_TYPE_PRIMARY,
136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
138};
139
4562236b
HW		 140/*
141 * dm_vblank_get_counter
142 *
143 * @brief
144 * Get counter for number of vertical blanks
145 *
146 * @param
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
149 *
150 * @return
151 * Counter for vertical blanks
152 */
153static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
154{
155 if (crtc >= adev->mode_info.num_crtc)
156 return 0;
157 else {
158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
160 acrtc->base.state);
4562236b 161
da5c47f6
AG		 162
163 if (acrtc_state->stream == NULL) {
0971c40e
HW		 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
165 crtc);
4562236b
HW		 166 return 0;
167 }
168
da5c47f6 169 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 170 }
171}
172
173static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 174 u32 *vbl, u32 *position)
4562236b 175{
81c50963
ST		 176 uint32_t v_blank_start, v_blank_end, h_position, v_position;
177
4562236b
HW		 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
179 return -EINVAL;
180 else {
181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
183 acrtc->base.state);
4562236b 184
da5c47f6 185 if (acrtc_state->stream == NULL) {
0971c40e
HW		 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
187 crtc);
4562236b
HW		 188 return 0;
189 }
190
81c50963
ST		 191 /*
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
194 */
da5c47f6 195 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 196 &v_blank_start,
197 &v_blank_end,
198 &h_position,
199 &v_position);
200
e806208d
AG		 201 *position = v_position | (h_position << 16);
202 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 203 }
204
205 return 0;
206}
207
208static bool dm_is_idle(void *handle)
209{
210 /* XXX todo */
211 return true;
212}
213
214static int dm_wait_for_idle(void *handle)
215{
216 /* XXX todo */
217 return 0;
218}
219
220static bool dm_check_soft_reset(void *handle)
221{
222 return false;
223}
224
225static int dm_soft_reset(void *handle)
226{
227 /* XXX todo */
228 return 0;
229}
230
3ee6b26b
AD		 231static struct amdgpu_crtc *
232get_crtc_by_otg_inst(struct amdgpu_device *adev,
233 int otg_inst)
4562236b
HW		 234{
235 struct drm_device *dev = adev->ddev;
236 struct drm_crtc *crtc;
237 struct amdgpu_crtc *amdgpu_crtc;
238
239 /*
240 * following if is check inherited from both functions where this one is
241 * used now. Need to be checked why it could happen.
242 */
243 if (otg_inst == -1) {
244 WARN_ON(1);
245 return adev->mode_info.crtcs[0];
246 }
247
248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
249 amdgpu_crtc = to_amdgpu_crtc(crtc);
250
251 if (amdgpu_crtc->otg_inst == otg_inst)
252 return amdgpu_crtc;
253 }
254
255 return NULL;
256}
257
258static void dm_pflip_high_irq(void *interrupt_params)
259{
4562236b
HW		 260 struct amdgpu_crtc *amdgpu_crtc;
261 struct common_irq_params *irq_params = interrupt_params;
262 struct amdgpu_device *adev = irq_params->adev;
263 unsigned long flags;
264
265 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
266
267 /* IRQ could occur when in initial stage */
268 /*TODO work and BO cleanup */
269 if (amdgpu_crtc == NULL) {
270 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
271 return;
272 }
273
274 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 275
276 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
277 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
278 amdgpu_crtc->pflip_status,
279 AMDGPU_FLIP_SUBMITTED,
280 amdgpu_crtc->crtc_id,
281 amdgpu_crtc);
282 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
283 return;
284 }
285
4562236b
HW		 286
287 /* wakeup usersapce */
1159898a 288 if (amdgpu_crtc->event) {
753c66c9
MK		 289 /* Update to correct count/ts if racing with vblank irq */
290 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
291
54f5499a 292 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 293
54f5499a
AG		 294 /* page flip completed. clean up */
295 amdgpu_crtc->event = NULL;
1159898a 296
54f5499a
AG		 297 } else
298 WARN_ON(1);
4562236b 299
54f5499a 300 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 301 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
302
54f5499a
AG		 303 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
304 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 305
306 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 307}
308
309static void dm_crtc_high_irq(void *interrupt_params)
310{
311 struct common_irq_params *irq_params = interrupt_params;
312 struct amdgpu_device *adev = irq_params->adev;
313 uint8_t crtc_index = 0;
314 struct amdgpu_crtc *acrtc;
315
b57de80a 316 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 317
318 if (acrtc)
319 crtc_index = acrtc->crtc_id;
320
321 drm_handle_vblank(adev->ddev, crtc_index);
322}
323
324static int dm_set_clockgating_state(void *handle,
325 enum amd_clockgating_state state)
326{
327 return 0;
328}
329
330static int dm_set_powergating_state(void *handle,
331 enum amd_powergating_state state)
332{
333 return 0;
334}
335
336/* Prototypes of private functions */
337static int dm_early_init(void* handle);
338
339static void hotplug_notify_work_func(struct work_struct *work)
340{
341 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
342 struct drm_device *dev = dm->ddev;
343
344 drm_kms_helper_hotplug_event(dev);
345}
346
a32e24b4
RL		 347#ifdef ENABLE_FBC
348#include "dal_asic_id.h"
349/* Allocate memory for FBC compressed data */
350/* TODO: Dynamic allocation */
351#define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
352
7578ecda 353static void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
a32e24b4
RL		 354{
355 int r;
356 struct dm_comressor_info *compressor = &adev->dm.compressor;
357
358 if (!compressor->bo_ptr) {
359 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
360 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
361 &compressor->gpu_addr, &compressor->cpu_addr);
362
363 if (r)
364 DRM_ERROR("DM: Failed to initialize fbc\n");
365 }
366
367}
368#endif
369
370
4562236b
HW		 371/* Init display KMS
372 *
373 * Returns 0 on success
374 */
7578ecda 375static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 376{
377 struct dc_init_data init_data;
378 adev->dm.ddev = adev->ddev;
379 adev->dm.adev = adev;
380
4562236b
HW		 381 /* Zero all the fields */
382 memset(&init_data, 0, sizeof(init_data));
383
384 /* initialize DAL's lock (for SYNC context use) */
385 spin_lock_init(&adev->dm.dal_lock);
386
387 /* initialize DAL's mutex */
388 mutex_init(&adev->dm.dal_mutex);
389
390 if(amdgpu_dm_irq_init(adev)) {
391 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
392 goto error;
393 }
394
395 init_data.asic_id.chip_family = adev->family;
396
397 init_data.asic_id.pci_revision_id = adev->rev_id;
398 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
399
400 init_data.asic_id.vram_width = adev->mc.vram_width;
401 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
402 init_data.asic_id.atombios_base_address =
403 adev->mode_info.atom_context->bios;
404
405 init_data.driver = adev;
406
407 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
408
409 if (!adev->dm.cgs_device) {
410 DRM_ERROR("amdgpu: failed to create cgs device.\n");
411 goto error;
412 }
413
414 init_data.cgs_device = adev->dm.cgs_device;
415
416 adev->dm.dal = NULL;
417
418 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
419
f1ad2f5e
HW		 420 if (amdgpu_dc_log)
421 init_data.log_mask = DC_DEFAULT_LOG_MASK;
422 else
423 init_data.log_mask = DC_MIN_LOG_MASK;
01a526f3 424
a32e24b4
RL		 425#ifdef ENABLE_FBC
426 if (adev->family == FAMILY_CZ)
427 amdgpu_dm_initialize_fbc(adev);
428 init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
429#endif
4562236b
HW		 430 /* Display Core create. */
431 adev->dm.dc = dc_create(&init_data);
432
f1ad2f5e
HW		 433 if (adev->dm.dc)
434 DRM_INFO("Display Core initialized!\n");
435 else
4562236b
HW		 436 DRM_INFO("Display Core failed to initialize!\n");
437
438 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
439
440 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
441 if (!adev->dm.freesync_module) {
442 DRM_ERROR(
443 "amdgpu: failed to initialize freesync_module.\n");
444 } else
f1ad2f5e 445 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 446 adev->dm.freesync_module);
447
448 if (amdgpu_dm_initialize_drm_device(adev)) {
449 DRM_ERROR(
450 "amdgpu: failed to initialize sw for display support.\n");
451 goto error;
452 }
453
454 /* Update the actual used number of crtc */
455 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
456
457 /* TODO: Add_display_info? */
458
459 /* TODO use dynamic cursor width */
ce75805e
AG		 460 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
461 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 462
463 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
464 DRM_ERROR(
465 "amdgpu: failed to initialize sw for display support.\n");
466 goto error;
467 }
468
f1ad2f5e 469 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 470
471 return 0;
472error:
473 amdgpu_dm_fini(adev);
474
475 return -1;
476}
477
7578ecda 478static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 479{
480 amdgpu_dm_destroy_drm_device(&adev->dm);
481 /*
482 * TODO: pageflip, vlank interrupt
483 *
484 * amdgpu_dm_irq_fini(adev);
485 */
486
487 if (adev->dm.cgs_device) {
488 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
489 adev->dm.cgs_device = NULL;
490 }
491 if (adev->dm.freesync_module) {
492 mod_freesync_destroy(adev->dm.freesync_module);
493 adev->dm.freesync_module = NULL;
494 }
495 /* DC Destroy TODO: Replace destroy DAL */
21de3396 496 if (adev->dm.dc)
4562236b 497 dc_destroy(&adev->dm.dc);
4562236b
HW		 498 return;
499}
500
4562236b
HW		 501static int dm_sw_init(void *handle)
502{
503 return 0;
504}
505
506static int dm_sw_fini(void *handle)
507{
508 return 0;
509}
510
7abcf6b5 511static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 512{
c84dec2f 513 struct amdgpu_dm_connector *aconnector;
4562236b 514 struct drm_connector *connector;
7abcf6b5 515 int ret = 0;
4562236b
HW		 516
517 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
518
519 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 520 aconnector = to_amdgpu_dm_connector(connector);
7abcf6b5 521 if (aconnector->dc_link->type == dc_connection_mst_branch) {
f1ad2f5e 522 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 523 aconnector, aconnector->base.base.id);
524
525 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
526 if (ret < 0) {
527 DRM_ERROR("DM_MST: Failed to start MST\n");
528 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
529 return ret;
4562236b 530 }
7abcf6b5 531 }
4562236b
HW		 532 }
533
534 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 535 return ret;
536}
537
538static int dm_late_init(void *handle)
539{
540 struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
541 int r = detect_mst_link_for_all_connectors(dev);
542
543 return r;
4562236b
HW		 544}
545
546static void s3_handle_mst(struct drm_device *dev, bool suspend)
547{
c84dec2f 548 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 549 struct drm_connector *connector;
550
551 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
552
553 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 554 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 555 if (aconnector->dc_link->type == dc_connection_mst_branch &&
556 !aconnector->mst_port) {
557
558 if (suspend)
559 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
560 else
561 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
562 }
563 }
564
565 drm_modeset_unlock(&dev->mode_config.connection_mutex);
566}
567
568static int dm_hw_init(void *handle)
569{
570 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
571 /* Create DAL display manager */
572 amdgpu_dm_init(adev);
4562236b
HW		 573 amdgpu_dm_hpd_init(adev);
574
4562236b
HW		 575 return 0;
576}
577
578static int dm_hw_fini(void *handle)
579{
580 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
581
582 amdgpu_dm_hpd_fini(adev);
583
584 amdgpu_dm_irq_fini(adev);
21de3396 585 amdgpu_dm_fini(adev);
4562236b
HW		 586 return 0;
587}
588
589static int dm_suspend(void *handle)
590{
591 struct amdgpu_device *adev = handle;
592 struct amdgpu_display_manager *dm = &adev->dm;
593 int ret = 0;
4562236b
HW		 594
595 s3_handle_mst(adev->ddev, true);
596
4562236b
HW		 597 amdgpu_dm_irq_suspend(adev);
598
0a214e2f 599 WARN_ON(adev->dm.cached_state);
a3621485
AG		 600 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
601
4562236b
HW		 602 dc_set_power_state(
603 dm->dc,
a3621485
AG		 604 DC_ACPI_CM_POWER_STATE_D3
605 );
4562236b
HW		 606
607 return ret;
608}
609
1daf8c63
AD		 610static struct amdgpu_dm_connector *
611amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
612 struct drm_crtc *crtc)
4562236b
HW		 613{
614 uint32_t i;
c2cea706 615 struct drm_connector_state *new_con_state;
4562236b
HW		 616 struct drm_connector *connector;
617 struct drm_crtc *crtc_from_state;
618
c2cea706
LSL		 619 for_each_new_connector_in_state(state, connector, new_con_state, i) {
620 crtc_from_state = new_con_state->crtc;
4562236b
HW		 621
622 if (crtc_from_state == crtc)
c84dec2f 623 return to_amdgpu_dm_connector(connector);
4562236b
HW		 624 }
625
626 return NULL;
627}
628
4562236b
HW		 629static int dm_resume(void *handle)
630{
631 struct amdgpu_device *adev = handle;
632 struct amdgpu_display_manager *dm = &adev->dm;
633
634 /* power on hardware */
635 dc_set_power_state(
636 dm->dc,
a3621485
AG		 637 DC_ACPI_CM_POWER_STATE_D0
638 );
4562236b
HW		 639
640 return 0;
641}
642
1ecfc3da 643int amdgpu_dm_display_resume(struct amdgpu_device *adev)
4562236b
HW		 644{
645 struct drm_device *ddev = adev->ddev;
646 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 647 struct amdgpu_dm_connector *aconnector;
4562236b 648 struct drm_connector *connector;
4562236b 649 struct drm_crtc *crtc;
c2cea706 650 struct drm_crtc_state *new_crtc_state;
a3621485
AG		 651 int ret = 0;
652 int i;
4562236b
HW		 653
654 /* program HPD filter */
655 dc_resume(dm->dc);
656
657 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
658 s3_handle_mst(ddev, false);
659
660 /*
661 * early enable HPD Rx IRQ, should be done before set mode as short
662 * pulse interrupts are used for MST
663 */
664 amdgpu_dm_irq_resume_early(adev);
665
4562236b
HW		 666 /* Do detection*/
667 list_for_each_entry(connector,
668 &ddev->mode_config.connector_list, head) {
c84dec2f 669 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 670
671 /*
672 * this is the case when traversing through already created
673 * MST connectors, should be skipped
674 */
675 if (aconnector->mst_port)
676 continue;
677
03ea364c 678 mutex_lock(&aconnector->hpd_lock);
8f38b66c 679 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
4562236b
HW		 680 aconnector->dc_sink = NULL;
681 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 682 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 683 }
684
a3621485 685 /* Force mode set in atomic comit */
c2cea706
LSL		 686 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
687 new_crtc_state->active_changed = true;
a3621485
AG		 688
689 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 690
0a214e2f
AG		 691 drm_atomic_state_put(adev->dm.cached_state);
692 adev->dm.cached_state = NULL;
693
9faa4237 694 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 695
696 return ret;
697}
698
699static const struct amd_ip_funcs amdgpu_dm_funcs = {
700 .name = "dm",
701 .early_init = dm_early_init,
7abcf6b5 702 .late_init = dm_late_init,
4562236b
HW		 703 .sw_init = dm_sw_init,
704 .sw_fini = dm_sw_fini,
705 .hw_init = dm_hw_init,
706 .hw_fini = dm_hw_fini,
707 .suspend = dm_suspend,
708 .resume = dm_resume,
709 .is_idle = dm_is_idle,
710 .wait_for_idle = dm_wait_for_idle,
711 .check_soft_reset = dm_check_soft_reset,
712 .soft_reset = dm_soft_reset,
713 .set_clockgating_state = dm_set_clockgating_state,
714 .set_powergating_state = dm_set_powergating_state,
715};
716
717const struct amdgpu_ip_block_version dm_ip_block =
718{
719 .type = AMD_IP_BLOCK_TYPE_DCE,
720 .major = 1,
721 .minor = 0,
722 .rev = 0,
723 .funcs = &amdgpu_dm_funcs,
724};
725
ca3268c4 726
7578ecda 727static struct drm_atomic_state *
ca3268c4
HW		 728dm_atomic_state_alloc(struct drm_device *dev)
729{
730 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
731
1dc90497 732 if (!state)
ca3268c4 733 return NULL;
1dc90497
AG		 734
735 if (drm_atomic_state_init(dev, &state->base) < 0)
736 goto fail;
737
ca3268c4 738 return &state->base;
1dc90497
AG		 739
740fail:
741 kfree(state);
742 return NULL;
ca3268c4
HW		 743}
744
0a323b84
AG		 745static void
746dm_atomic_state_clear(struct drm_atomic_state *state)
747{
748 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
749
750 if (dm_state->context) {
608ac7bb 751 dc_release_state(dm_state->context);
0a323b84
AG		 752 dm_state->context = NULL;
753 }
754
755 drm_atomic_state_default_clear(state);
756}
757
758static void
759dm_atomic_state_alloc_free(struct drm_atomic_state *state)
760{
761 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
762 drm_atomic_state_default_release(state);
763 kfree(dm_state);
764}
765
b3663f70 766static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
a49dcb88
HW		 767 .fb_create = amdgpu_user_framebuffer_create,
768 .output_poll_changed = amdgpu_output_poll_changed,
4562236b 769 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 770 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 771 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 772 .atomic_state_clear = dm_atomic_state_clear,
773 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 774};
775
776static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
777 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 778};
779
7578ecda 780static void
3ee6b26b 781amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 782{
783 struct drm_connector *connector = &aconnector->base;
784 struct drm_device *dev = connector->dev;
b73a22d3 785 struct dc_sink *sink;
4562236b
HW		 786
787 /* MST handled by drm_mst framework */
788 if (aconnector->mst_mgr.mst_state == true)
789 return;
790
791
792 sink = aconnector->dc_link->local_sink;
793
794 /* Edid mgmt connector gets first update only in mode_valid hook and then
795 * the connector sink is set to either fake or physical sink depends on link status.
796 * don't do it here if u are during boot
797 */
798 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
799 && aconnector->dc_em_sink) {
800
ab2541b6 801 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 802 * because on resume connecotr->sink is set ti NULL
803 */
804 mutex_lock(&dev->mode_config.mutex);
805
806 if (sink) {
922aa1e1 807 if (aconnector->dc_sink) {
4562236b
HW		 808 amdgpu_dm_remove_sink_from_freesync_module(
809 connector);
922aa1e1
AG		 810 /* retain and release bellow are used for
811 * bump up refcount for sink because the link don't point
812 * to it anymore after disconnect so on next crtc to connector
813 * reshuffle by UMD we will get into unwanted dc_sink release
814 */
815 if (aconnector->dc_sink != aconnector->dc_em_sink)
816 dc_sink_release(aconnector->dc_sink);
817 }
4562236b
HW		 818 aconnector->dc_sink = sink;
819 amdgpu_dm_add_sink_to_freesync_module(
820 connector, aconnector->edid);
821 } else {
822 amdgpu_dm_remove_sink_from_freesync_module(connector);
823 if (!aconnector->dc_sink)
824 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 825 else if (aconnector->dc_sink != aconnector->dc_em_sink)
826 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 827 }
828
829 mutex_unlock(&dev->mode_config.mutex);
830 return;
831 }
832
833 /*
834 * TODO: temporary guard to look for proper fix
835 * if this sink is MST sink, we should not do anything
836 */
837 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
838 return;
839
840 if (aconnector->dc_sink == sink) {
841 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
842 * Do nothing!! */
f1ad2f5e 843 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 844 aconnector->connector_id);
845 return;
846 }
847
f1ad2f5e 848 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 849 aconnector->connector_id, aconnector->dc_sink, sink);
850
851 mutex_lock(&dev->mode_config.mutex);
852
853 /* 1. Update status of the drm connector
854 * 2. Send an event and let userspace tell us what to do */
855 if (sink) {
856 /* TODO: check if we still need the S3 mode update workaround.
857 * If yes, put it here. */
858 if (aconnector->dc_sink)
859 amdgpu_dm_remove_sink_from_freesync_module(
860 connector);
861
862 aconnector->dc_sink = sink;
863 if (sink->dc_edid.length == 0)
864 aconnector->edid = NULL;
865 else {
866 aconnector->edid =
867 (struct edid *) sink->dc_edid.raw_edid;
868
869
870 drm_mode_connector_update_edid_property(connector,
871 aconnector->edid);
872 }
873 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
874
875 } else {
876 amdgpu_dm_remove_sink_from_freesync_module(connector);
877 drm_mode_connector_update_edid_property(connector, NULL);
878 aconnector->num_modes = 0;
879 aconnector->dc_sink = NULL;
880 }
881
882 mutex_unlock(&dev->mode_config.mutex);
883}
884
885static void handle_hpd_irq(void *param)
886{
c84dec2f 887 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 888 struct drm_connector *connector = &aconnector->base;
889 struct drm_device *dev = connector->dev;
890
891 /* In case of failure or MST no need to update connector status or notify the OS
892 * since (for MST case) MST does this in it's own context.
893 */
894 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 895
896 if (aconnector->fake_enable)
897 aconnector->fake_enable = false;
898
8f38b66c 899 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 900 amdgpu_dm_update_connector_after_detect(aconnector);
901
902
903 drm_modeset_lock_all(dev);
904 dm_restore_drm_connector_state(dev, connector);
905 drm_modeset_unlock_all(dev);
906
907 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
908 drm_kms_helper_hotplug_event(dev);
909 }
910 mutex_unlock(&aconnector->hpd_lock);
911
912}
913
c84dec2f 914static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 915{
916 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
917 uint8_t dret;
918 bool new_irq_handled = false;
919 int dpcd_addr;
920 int dpcd_bytes_to_read;
921
922 const int max_process_count = 30;
923 int process_count = 0;
924
925 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
926
927 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
928 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
929 /* DPCD 0x200 - 0x201 for downstream IRQ */
930 dpcd_addr = DP_SINK_COUNT;
931 } else {
932 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
933 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
934 dpcd_addr = DP_SINK_COUNT_ESI;
935 }
936
937 dret = drm_dp_dpcd_read(
938 &aconnector->dm_dp_aux.aux,
939 dpcd_addr,
940 esi,
941 dpcd_bytes_to_read);
942
943 while (dret == dpcd_bytes_to_read &&
944 process_count < max_process_count) {
945 uint8_t retry;
946 dret = 0;
947
948 process_count++;
949
f1ad2f5e 950 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 951 /* handle HPD short pulse irq */
952 if (aconnector->mst_mgr.mst_state)
953 drm_dp_mst_hpd_irq(
954 &aconnector->mst_mgr,
955 esi,
956 &new_irq_handled);
4562236b
HW		 957
958 if (new_irq_handled) {
959 /* ACK at DPCD to notify down stream */
960 const int ack_dpcd_bytes_to_write =
961 dpcd_bytes_to_read - 1;
962
963 for (retry = 0; retry < 3; retry++) {
964 uint8_t wret;
965
966 wret = drm_dp_dpcd_write(
967 &aconnector->dm_dp_aux.aux,
968 dpcd_addr + 1,
969 &esi[1],
970 ack_dpcd_bytes_to_write);
971 if (wret == ack_dpcd_bytes_to_write)
972 break;
973 }
974
975 /* check if there is new irq to be handle */
976 dret = drm_dp_dpcd_read(
977 &aconnector->dm_dp_aux.aux,
978 dpcd_addr,
979 esi,
980 dpcd_bytes_to_read);
981
982 new_irq_handled = false;
983 } else
984 break;
985 }
986
987 if (process_count == max_process_count)
f1ad2f5e 988 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 989}
990
991static void handle_hpd_rx_irq(void *param)
992{
c84dec2f 993 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 994 struct drm_connector *connector = &aconnector->base;
995 struct drm_device *dev = connector->dev;
996 const struct dc_link *dc_link = aconnector->dc_link;
997 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
998
999 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1000 * conflict, after implement i2c helper, this mutex should be
1001 * retired.
1002 */
1003 if (aconnector->dc_link->type != dc_connection_mst_branch)
1004 mutex_lock(&aconnector->hpd_lock);
1005
8ee65d7c 1006 if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) &&
4562236b
HW		 1007 !is_mst_root_connector) {
1008 /* Downstream Port status changed. */
8f38b66c 1009 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPDRX)) {
4562236b
HW		 1010 amdgpu_dm_update_connector_after_detect(aconnector);
1011
1012
1013 drm_modeset_lock_all(dev);
1014 dm_restore_drm_connector_state(dev, connector);
1015 drm_modeset_unlock_all(dev);
1016
1017 drm_kms_helper_hotplug_event(dev);
1018 }
1019 }
1020 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1021 (dc_link->type == dc_connection_mst_branch))
1022 dm_handle_hpd_rx_irq(aconnector);
1023
1024 if (aconnector->dc_link->type != dc_connection_mst_branch)
1025 mutex_unlock(&aconnector->hpd_lock);
1026}
1027
1028static void register_hpd_handlers(struct amdgpu_device *adev)
1029{
1030 struct drm_device *dev = adev->ddev;
1031 struct drm_connector *connector;
c84dec2f 1032 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1033 const struct dc_link *dc_link;
1034 struct dc_interrupt_params int_params = {0};
1035
1036 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1037 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1038
1039 list_for_each_entry(connector,
1040 &dev->mode_config.connector_list, head) {
1041
c84dec2f 1042 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1043 dc_link = aconnector->dc_link;
1044
1045 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1046 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1047 int_params.irq_source = dc_link->irq_source_hpd;
1048
1049 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1050 handle_hpd_irq,
1051 (void *) aconnector);
1052 }
1053
1054 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1055
1056 /* Also register for DP short pulse (hpd_rx). */
1057 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1058 int_params.irq_source = dc_link->irq_source_hpd_rx;
1059
1060 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1061 handle_hpd_rx_irq,
1062 (void *) aconnector);
1063 }
1064 }
1065}
1066
1067/* Register IRQ sources and initialize IRQ callbacks */
1068static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1069{
1070 struct dc *dc = adev->dm.dc;
1071 struct common_irq_params *c_irq_params;
1072 struct dc_interrupt_params int_params = {0};
1073 int r;
1074 int i;
2c8ad2d5
AD		 1075 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1076
ff5ef992
AD		 1077 if (adev->asic_type == CHIP_VEGA10 ||
1078 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1079 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1080
1081 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1082 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1083
1084 /* Actions of amdgpu_irq_add_id():
1085 * 1. Register a set() function with base driver.
1086 * Base driver will call set() function to enable/disable an
1087 * interrupt in DC hardware.
1088 * 2. Register amdgpu_dm_irq_handler().
1089 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1090 * coming from DC hardware.
1091 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1092 * for acknowledging and handling. */
1093
b57de80a 1094 /* Use VBLANK interrupt */
e9029155 1095 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1096 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1097 if (r) {
1098 DRM_ERROR("Failed to add crtc irq id!\n");
1099 return r;
1100 }
1101
1102 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1103 int_params.irq_source =
3d761e79 1104 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1105
b57de80a 1106 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1107
1108 c_irq_params->adev = adev;
1109 c_irq_params->irq_src = int_params.irq_source;
1110
1111 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1112 dm_crtc_high_irq, c_irq_params);
1113 }
1114
3d761e79 1115 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1116 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1117 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1118 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1119 if (r) {
1120 DRM_ERROR("Failed to add page flip irq id!\n");
1121 return r;
1122 }
1123
1124 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1125 int_params.irq_source =
1126 dc_interrupt_to_irq_source(dc, i, 0);
1127
1128 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1129
1130 c_irq_params->adev = adev;
1131 c_irq_params->irq_src = int_params.irq_source;
1132
1133 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1134 dm_pflip_high_irq, c_irq_params);
1135
1136 }
1137
1138 /* HPD */
2c8ad2d5
AD		 1139 r = amdgpu_irq_add_id(adev, client_id,
1140 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1141 if (r) {
1142 DRM_ERROR("Failed to add hpd irq id!\n");
1143 return r;
1144 }
1145
1146 register_hpd_handlers(adev);
1147
1148 return 0;
1149}
1150
ff5ef992
AD		 1151#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1152/* Register IRQ sources and initialize IRQ callbacks */
1153static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1154{
1155 struct dc *dc = adev->dm.dc;
1156 struct common_irq_params *c_irq_params;
1157 struct dc_interrupt_params int_params = {0};
1158 int r;
1159 int i;
1160
1161 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1162 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1163
1164 /* Actions of amdgpu_irq_add_id():
1165 * 1. Register a set() function with base driver.
1166 * Base driver will call set() function to enable/disable an
1167 * interrupt in DC hardware.
1168 * 2. Register amdgpu_dm_irq_handler().
1169 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1170 * coming from DC hardware.
1171 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1172 * for acknowledging and handling.
1173 * */
1174
1175 /* Use VSTARTUP interrupt */
1176 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1177 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1178 i++) {
1179 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1180
1181 if (r) {
1182 DRM_ERROR("Failed to add crtc irq id!\n");
1183 return r;
1184 }
1185
1186 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1187 int_params.irq_source =
1188 dc_interrupt_to_irq_source(dc, i, 0);
1189
1190 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1191
1192 c_irq_params->adev = adev;
1193 c_irq_params->irq_src = int_params.irq_source;
1194
1195 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1196 dm_crtc_high_irq, c_irq_params);
1197 }
1198
1199 /* Use GRPH_PFLIP interrupt */
1200 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1201 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1202 i++) {
1203 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1204 if (r) {
1205 DRM_ERROR("Failed to add page flip irq id!\n");
1206 return r;
1207 }
1208
1209 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1210 int_params.irq_source =
1211 dc_interrupt_to_irq_source(dc, i, 0);
1212
1213 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1214
1215 c_irq_params->adev = adev;
1216 c_irq_params->irq_src = int_params.irq_source;
1217
1218 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1219 dm_pflip_high_irq, c_irq_params);
1220
1221 }
1222
1223 /* HPD */
1224 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1225 &adev->hpd_irq);
1226 if (r) {
1227 DRM_ERROR("Failed to add hpd irq id!\n");
1228 return r;
1229 }
1230
1231 register_hpd_handlers(adev);
1232
1233 return 0;
1234}
1235#endif
1236
4562236b
HW		 1237static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1238{
1239 int r;
1240
1241 adev->mode_info.mode_config_initialized = true;
1242
4562236b 1243 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1244 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1245
1246 adev->ddev->mode_config.max_width = 16384;
1247 adev->ddev->mode_config.max_height = 16384;
1248
1249 adev->ddev->mode_config.preferred_depth = 24;
1250 adev->ddev->mode_config.prefer_shadow = 1;
1251 /* indicate support of immediate flip */
1252 adev->ddev->mode_config.async_page_flip = true;
1253
1254 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1255
1256 r = amdgpu_modeset_create_props(adev);
1257 if (r)
1258 return r;
1259
1260 return 0;
1261}
1262
1263#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1264 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1265
1266static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1267{
1268 struct amdgpu_display_manager *dm = bl_get_data(bd);
1269
1270 if (dc_link_set_backlight_level(dm->backlight_link,
1271 bd->props.brightness, 0, 0))
1272 return 0;
1273 else
1274 return 1;
1275}
1276
1277static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1278{
1279 return bd->props.brightness;
1280}
1281
1282static const struct backlight_ops amdgpu_dm_backlight_ops = {
1283 .get_brightness = amdgpu_dm_backlight_get_brightness,
1284 .update_status = amdgpu_dm_backlight_update_status,
1285};
1286
7578ecda
AD		 1287static void
1288amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1289{
1290 char bl_name[16];
1291 struct backlight_properties props = { 0 };
1292
1293 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1294 props.type = BACKLIGHT_RAW;
1295
1296 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1297 dm->adev->ddev->primary->index);
1298
1299 dm->backlight_dev = backlight_device_register(bl_name,
1300 dm->adev->ddev->dev,
1301 dm,
1302 &amdgpu_dm_backlight_ops,
1303 &props);
1304
1305 if (NULL == dm->backlight_dev)
1306 DRM_ERROR("DM: Backlight registration failed!\n");
1307 else
f1ad2f5e 1308 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1309}
1310
1311#endif
1312
1313/* In this architecture, the association
1314 * connector -> encoder -> crtc
1315 * id not really requried. The crtc and connector will hold the
1316 * display_index as an abstraction to use with DAL component
1317 *
1318 * Returns 0 on success
1319 */
7578ecda 1320static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1321{
1322 struct amdgpu_display_manager *dm = &adev->dm;
1323 uint32_t i;
c84dec2f 1324 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1325 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1326 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1327 uint32_t link_cnt;
92f3ac40 1328 unsigned long possible_crtcs;
4562236b
HW		 1329
1330 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1331 if (amdgpu_dm_mode_config_init(dm->adev)) {
1332 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1333 return -1;
4562236b
HW		 1334 }
1335
3be5262e 1336 for (i = 0; i < dm->dc->caps.max_planes; i++) {
d4e13b0d
AD		 1337 mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),
1338 GFP_KERNEL);
1339 if (!mode_info->planes[i]) {
3be5262e 1340 DRM_ERROR("KMS: Failed to allocate plane\n");
d4e13b0d
AD		 1341 goto fail_free_planes;
1342 }
1605b3be 1343 mode_info->planes[i]->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1344
1345 /*
1346 * HACK: IGT tests expect that each plane can only have one
1347 * one possible CRTC. For now, set one CRTC for each
1348 * plane that is not an underlay, but still allow multiple
1349 * CRTCs for underlay planes.
1350 */
1351 possible_crtcs = 1 << i;
1352 if (i >= dm->dc->caps.max_streams)
1353 possible_crtcs = 0xff;
1354
1355 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d
AD		 1356 DRM_ERROR("KMS: Failed to initialize plane\n");
1357 goto fail_free_planes;
1358 }
1359 }
4562236b 1360
d4e13b0d
AD		 1361 for (i = 0; i < dm->dc->caps.max_streams; i++)
1362 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1363 DRM_ERROR("KMS: Failed to initialize crtc\n");
d4e13b0d 1364 goto fail_free_planes;
4562236b 1365 }
4562236b 1366
ab2541b6 1367 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1368
1369 /* loops over all connectors on the board */
1370 for (i = 0; i < link_cnt; i++) {
1371
1372 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1373 DRM_ERROR(
1374 "KMS: Cannot support more than %d display indexes\n",
1375 AMDGPU_DM_MAX_DISPLAY_INDEX);
1376 continue;
1377 }
1378
1379 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1380 if (!aconnector)
f2a0f5e6 1381 goto fail_free_planes;
4562236b
HW		 1382
1383 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1384 if (!aencoder) {
1385 goto fail_free_connector;
1386 }
1387
1388 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1389 DRM_ERROR("KMS: Failed to initialize encoder\n");
1390 goto fail_free_encoder;
1391 }
1392
1393 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1394 DRM_ERROR("KMS: Failed to initialize connector\n");
f2a0f5e6 1395 goto fail_free_encoder;
4562236b
HW		 1396 }
1397
8f38b66c
HW		 1398 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1399 DETECT_REASON_BOOT))
4562236b
HW		 1400 amdgpu_dm_update_connector_after_detect(aconnector);
1401 }
1402
1403 /* Software is initialized. Now we can register interrupt handlers. */
1404 switch (adev->asic_type) {
1405 case CHIP_BONAIRE:
1406 case CHIP_HAWAII:
cd4b356f
AD		 1407 case CHIP_KAVERI:
1408 case CHIP_KABINI:
1409 case CHIP_MULLINS:
4562236b
HW		 1410 case CHIP_TONGA:
1411 case CHIP_FIJI:
1412 case CHIP_CARRIZO:
1413 case CHIP_STONEY:
1414 case CHIP_POLARIS11:
1415 case CHIP_POLARIS10:
b264d345 1416 case CHIP_POLARIS12:
2c8ad2d5 1417 case CHIP_VEGA10:
4562236b
HW		 1418 if (dce110_register_irq_handlers(dm->adev)) {
1419 DRM_ERROR("DM: Failed to initialize IRQ\n");
d4e13b0d 1420 goto fail_free_encoder;
4562236b
HW		 1421 }
1422 break;
ff5ef992
AD		 1423#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1424 case CHIP_RAVEN:
1425 if (dcn10_register_irq_handlers(dm->adev)) {
1426 DRM_ERROR("DM: Failed to initialize IRQ\n");
1427 goto fail_free_encoder;
1428 }
79c24086
BL		 1429 /*
1430 * Temporary disable until pplib/smu interaction is implemented
1431 */
1432 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1433 break;
1434#endif
4562236b
HW		 1435 default:
1436 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
d4e13b0d 1437 goto fail_free_encoder;
4562236b
HW		 1438 }
1439
1440 drm_mode_config_reset(dm->ddev);
1441
1442 return 0;
1443fail_free_encoder:
1444 kfree(aencoder);
1445fail_free_connector:
1446 kfree(aconnector);
d4e13b0d 1447fail_free_planes:
3be5262e 1448 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1449 kfree(mode_info->planes[i]);
4562236b
HW		 1450 return -1;
1451}
1452
7578ecda 1453static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1454{
1455 drm_mode_config_cleanup(dm->ddev);
1456 return;
1457}
1458
1459/******************************************************************************
1460 * amdgpu_display_funcs functions
1461 *****************************************************************************/
1462
1463/**
1464 * dm_bandwidth_update - program display watermarks
1465 *
1466 * @adev: amdgpu_device pointer
1467 *
1468 * Calculate and program the display watermarks and line buffer allocation.
1469 */
1470static void dm_bandwidth_update(struct amdgpu_device *adev)
1471{
49c07a99 1472 /* TODO: implement later */
4562236b
HW		 1473}
1474
1475static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1476 u8 level)
1477{
1478 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1479}
1480
1481static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1482{
1483 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1484 return 0;
1485}
1486
4562236b
HW		 1487static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1488 struct drm_file *filp)
1489{
1490 struct mod_freesync_params freesync_params;
ab2541b6 1491 uint8_t num_streams;
4562236b 1492 uint8_t i;
4562236b
HW		 1493
1494 struct amdgpu_device *adev = dev->dev_private;
1495 int r = 0;
1496
1497 /* Get freesync enable flag from DRM */
1498
ab2541b6 1499 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1500
ab2541b6 1501 for (i = 0; i < num_streams; i++) {
0971c40e 1502 struct dc_stream_state *stream;
ab2541b6 1503 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1504
1505 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1506 &stream, 1, &freesync_params);
4562236b
HW		 1507 }
1508
1509 return r;
1510}
1511
39cc5be2 1512static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1513 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1514 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1515 .vblank_wait = NULL,
1516 .backlight_set_level =
1517 dm_set_backlight_level,/* called unconditionally */
1518 .backlight_get_level =
1519 dm_get_backlight_level,/* called unconditionally */
1520 .hpd_sense = NULL,/* called unconditionally */
1521 .hpd_set_polarity = NULL, /* called unconditionally */
1522 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1523 .page_flip_get_scanoutpos =
1524 dm_crtc_get_scanoutpos,/* called unconditionally */
1525 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1526 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1527 .notify_freesync = amdgpu_notify_freesync,
1528
1529};
1530
1531#if defined(CONFIG_DEBUG_KERNEL_DC)
1532
3ee6b26b
AD		 1533static ssize_t s3_debug_store(struct device *device,
1534 struct device_attribute *attr,
1535 const char *buf,
1536 size_t count)
4562236b
HW		 1537{
1538 int ret;
1539 int s3_state;
1540 struct pci_dev *pdev = to_pci_dev(device);
1541 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1542 struct amdgpu_device *adev = drm_dev->dev_private;
1543
1544 ret = kstrtoint(buf, 0, &s3_state);
1545
1546 if (ret == 0) {
1547 if (s3_state) {
1548 dm_resume(adev);
1549 amdgpu_dm_display_resume(adev);
1550 drm_kms_helper_hotplug_event(adev->ddev);
1551 } else
1552 dm_suspend(adev);
1553 }
1554
1555 return ret == 0 ? count : 0;
1556}
1557
1558DEVICE_ATTR_WO(s3_debug);
1559
1560#endif
1561
1562static int dm_early_init(void *handle)
1563{
1564 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1565
d7ec53d9 1566 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
4562236b
HW		 1567 amdgpu_dm_set_irq_funcs(adev);
1568
1569 switch (adev->asic_type) {
1570 case CHIP_BONAIRE:
1571 case CHIP_HAWAII:
1572 adev->mode_info.num_crtc = 6;
1573 adev->mode_info.num_hpd = 6;
1574 adev->mode_info.num_dig = 6;
3be5262e 1575 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1576 break;
cd4b356f
AD		 1577 case CHIP_KAVERI:
1578 adev->mode_info.num_crtc = 4;
1579 adev->mode_info.num_hpd = 6;
1580 adev->mode_info.num_dig = 7;
1581 adev->mode_info.plane_type = dm_plane_type_default;
1582 break;
1583 case CHIP_KABINI:
1584 case CHIP_MULLINS:
1585 adev->mode_info.num_crtc = 2;
1586 adev->mode_info.num_hpd = 6;
1587 adev->mode_info.num_dig = 6;
1588 adev->mode_info.plane_type = dm_plane_type_default;
1589 break;
4562236b
HW		 1590 case CHIP_FIJI:
1591 case CHIP_TONGA:
1592 adev->mode_info.num_crtc = 6;
1593 adev->mode_info.num_hpd = 6;
1594 adev->mode_info.num_dig = 7;
3be5262e 1595 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1596 break;
1597 case CHIP_CARRIZO:
1598 adev->mode_info.num_crtc = 3;
1599 adev->mode_info.num_hpd = 6;
1600 adev->mode_info.num_dig = 9;
3be5262e 1601 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1602 break;
1603 case CHIP_STONEY:
1604 adev->mode_info.num_crtc = 2;
1605 adev->mode_info.num_hpd = 6;
1606 adev->mode_info.num_dig = 9;
3be5262e 1607 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1608 break;
1609 case CHIP_POLARIS11:
b264d345 1610 case CHIP_POLARIS12:
4562236b
HW		 1611 adev->mode_info.num_crtc = 5;
1612 adev->mode_info.num_hpd = 5;
1613 adev->mode_info.num_dig = 5;
3be5262e 1614 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1615 break;
1616 case CHIP_POLARIS10:
1617 adev->mode_info.num_crtc = 6;
1618 adev->mode_info.num_hpd = 6;
1619 adev->mode_info.num_dig = 6;
3be5262e 1620 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1621 break;
2c8ad2d5
AD		 1622 case CHIP_VEGA10:
1623 adev->mode_info.num_crtc = 6;
1624 adev->mode_info.num_hpd = 6;
1625 adev->mode_info.num_dig = 6;
3be5262e 1626 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1627 break;
ff5ef992
AD		 1628#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1629 case CHIP_RAVEN:
1630 adev->mode_info.num_crtc = 4;
1631 adev->mode_info.num_hpd = 4;
1632 adev->mode_info.num_dig = 4;
3be5262e 1633 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1634 break;
1635#endif
4562236b
HW		 1636 default:
1637 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1638 return -EINVAL;
1639 }
1640
39cc5be2
AD		 1641 if (adev->mode_info.funcs == NULL)
1642 adev->mode_info.funcs = &dm_display_funcs;
1643
4562236b
HW		 1644 /* Note: Do NOT change adev->audio_endpt_rreg and
1645 * adev->audio_endpt_wreg because they are initialised in
1646 * amdgpu_device_init() */
1647#if defined(CONFIG_DEBUG_KERNEL_DC)
1648 device_create_file(
1649 adev->ddev->dev,
1650 &dev_attr_s3_debug);
1651#endif
1652
1653 return 0;
1654}
1655
e7b07cee
HW		 1656struct dm_connector_state {
1657 struct drm_connector_state base;
1658
1659 enum amdgpu_rmx_type scaling;
1660 uint8_t underscan_vborder;
1661 uint8_t underscan_hborder;
1662 bool underscan_enable;
1663};
1664
1665#define to_dm_connector_state(x)\
1666 container_of((x), struct dm_connector_state, base)
1667
9b690ef3 1668static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1669 struct dc_stream_state *new_stream,
1670 struct dc_stream_state *old_stream)
9b690ef3 1671{
e7b07cee
HW		 1672 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1673 return false;
1674
1675 if (!crtc_state->enable)
1676 return false;
1677
1678 return crtc_state->active;
1679}
1680
1681static bool modereset_required(struct drm_crtc_state *crtc_state)
1682{
1683 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1684 return false;
1685
1686 return !crtc_state->enable || !crtc_state->active;
1687}
1688
7578ecda 1689static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1690{
1691 drm_encoder_cleanup(encoder);
1692 kfree(encoder);
1693}
1694
1695static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1696 .destroy = amdgpu_dm_encoder_destroy,
1697};
1698
3ee6b26b
AD		 1699static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1700 struct dc_plane_state *plane_state)
e7b07cee 1701{
3be5262e
HW		 1702 plane_state->src_rect.x = state->src_x >> 16;
1703 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1704 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1705 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1706
3be5262e 1707 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1708 return false;
1709
3be5262e
HW		 1710 plane_state->src_rect.height = state->src_h >> 16;
1711 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1712 return false;
1713
3be5262e
HW		 1714 plane_state->dst_rect.x = state->crtc_x;
1715 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1716
1717 if (state->crtc_w == 0)
1718 return false;
1719
3be5262e 1720 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1721
1722 if (state->crtc_h == 0)
1723 return false;
1724
3be5262e 1725 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1726
3be5262e 1727 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1728
1729 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1730 case DRM_MODE_ROTATE_0:
3be5262e 1731 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1732 break;
1733 case DRM_MODE_ROTATE_90:
3be5262e 1734 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1735 break;
1736 case DRM_MODE_ROTATE_180:
3be5262e 1737 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1738 break;
1739 case DRM_MODE_ROTATE_270:
3be5262e 1740 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1741 break;
1742 default:
3be5262e 1743 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1744 break;
1745 }
1746
4562236b
HW		 1747 return true;
1748}
3ee6b26b
AD		 1749static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1750 uint64_t *tiling_flags,
1751 uint64_t *fb_location)
e7b07cee
HW		 1752{
1753 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1754 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1755
e7b07cee
HW		 1756 if (unlikely(r)) {
1757 DRM_ERROR("Unable to reserve buffer\n");
1758 return r;
1759 }
1760
1761 if (fb_location)
1762 *fb_location = amdgpu_bo_gpu_offset(rbo);
1763
1764 if (tiling_flags)
1765 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1766
1767 amdgpu_bo_unreserve(rbo);
1768
1769 return r;
1770}
1771
3ee6b26b
AD		 1772static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1773 struct dc_plane_state *plane_state,
1774 const struct amdgpu_framebuffer *amdgpu_fb,
1775 bool addReq)
e7b07cee
HW		 1776{
1777 uint64_t tiling_flags;
1778 uint64_t fb_location = 0;
1779 unsigned int awidth;
1780 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1781 int ret = 0;
1782 struct drm_format_name_buf format_name;
1783
1784 ret = get_fb_info(
1785 amdgpu_fb,
1786 &tiling_flags,
1787 addReq == true ? &fb_location:NULL);
1788
1789 if (ret)
1790 return ret;
1791
1792 switch (fb->format->format) {
1793 case DRM_FORMAT_C8:
3be5262e 1794 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1795 break;
1796 case DRM_FORMAT_RGB565:
3be5262e 1797 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1798 break;
1799 case DRM_FORMAT_XRGB8888:
1800 case DRM_FORMAT_ARGB8888:
3be5262e 1801 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1802 break;
1803 case DRM_FORMAT_XRGB2101010:
1804 case DRM_FORMAT_ARGB2101010:
3be5262e 1805 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1806 break;
1807 case DRM_FORMAT_XBGR2101010:
1808 case DRM_FORMAT_ABGR2101010:
3be5262e 1809 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1810 break;
1811 case DRM_FORMAT_NV21:
3be5262e 1812 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1813 break;
1814 case DRM_FORMAT_NV12:
3be5262e 1815 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1816 break;
1817 default:
1818 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1819 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1820 return -EINVAL;
1821 }
1822
3be5262e
HW		 1823 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1824 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1825 plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
1826 plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
1827 plane_state->plane_size.grph.surface_size.x = 0;
1828 plane_state->plane_size.grph.surface_size.y = 0;
1829 plane_state->plane_size.grph.surface_size.width = fb->width;
1830 plane_state->plane_size.grph.surface_size.height = fb->height;
1831 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1832 fb->pitches[0] / fb->format->cpp[0];
1833 /* TODO: unhardcode */
3be5262e 1834 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1835
1836 } else {
1837 awidth = ALIGN(fb->width, 64);
3be5262e
HW		 1838 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1839 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 1840 = lower_32_bits(fb_location);
3be5262e 1841 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 1842 = lower_32_bits(fb_location) +
1843 (awidth * fb->height);
3be5262e
HW		 1844 plane_state->plane_size.video.luma_size.x = 0;
1845 plane_state->plane_size.video.luma_size.y = 0;
1846 plane_state->plane_size.video.luma_size.width = awidth;
1847 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1848 /* TODO: unhardcode */
3be5262e 1849 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1850
3be5262e
HW		 1851 plane_state->plane_size.video.chroma_size.x = 0;
1852 plane_state->plane_size.video.chroma_size.y = 0;
1853 plane_state->plane_size.video.chroma_size.width = awidth;
1854 plane_state->plane_size.video.chroma_size.height = fb->height;
1855 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1856
1857 /* TODO: unhardcode */
3be5262e 1858 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1859 }
1860
3be5262e 1861 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1862
b830ebc9
HW		 1863 /* Fill GFX8 params */
1864 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1865 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1866
1867 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1868 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1869 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1870 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1871 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1872
1873 /* XXX fix me for VI */
3be5262e
HW		 1874 plane_state->tiling_info.gfx8.num_banks = num_banks;
1875 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1876 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1877 plane_state->tiling_info.gfx8.tile_split = tile_split;
1878 plane_state->tiling_info.gfx8.bank_width = bankw;
1879 plane_state->tiling_info.gfx8.bank_height = bankh;
1880 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1881 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1882 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1883 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1884 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1885 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1886 }
1887
3be5262e 1888 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1889 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1890
1891 if (adev->asic_type == CHIP_VEGA10 ||
1892 adev->asic_type == CHIP_RAVEN) {
1893 /* Fill GFX9 params */
3be5262e 1894 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1895 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1896 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1897 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1898 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1899 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1900 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1901 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1902 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1903 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1904 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1905 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1906 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1907 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1908 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1909 }
1910
3be5262e
HW		 1911 plane_state->visible = true;
1912 plane_state->scaling_quality.h_taps_c = 0;
1913 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1914
3be5262e
HW		 1915 /* is this needed? is plane_state zeroed at allocation? */
1916 plane_state->scaling_quality.h_taps = 0;
1917 plane_state->scaling_quality.v_taps = 0;
1918 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1919
1920 return ret;
1921
1922}
1923
3ee6b26b
AD		 1924static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state,
1925 struct dc_plane_state *plane_state)
e7b07cee
HW		 1926{
1927 int i;
1928 struct dc_gamma *gamma;
d66cf5f5
AK		 1929 struct drm_color_lut *lut =
1930 (struct drm_color_lut *) crtc_state->gamma_lut->data;
e7b07cee
HW		 1931
1932 gamma = dc_create_gamma();
1933
1934 if (gamma == NULL) {
1935 WARN_ON(1);
1936 return;
1937 }
1938
7483bed4
HW		 1939 gamma->type = GAMMA_RGB_256;
1940 gamma->num_entries = GAMMA_RGB_256_ENTRIES;
d66cf5f5
AK		 1941 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1942 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1943 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1944 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
e7b07cee
HW		 1945 }
1946
3be5262e 1947 plane_state->gamma_correction = gamma;
e7b07cee
HW		 1948}
1949
3ee6b26b
AD		 1950static int fill_plane_attributes(struct amdgpu_device *adev,
1951 struct dc_plane_state *dc_plane_state,
1952 struct drm_plane_state *plane_state,
1953 struct drm_crtc_state *crtc_state,
1954 bool addrReq)
e7b07cee
HW		 1955{
1956 const struct amdgpu_framebuffer *amdgpu_fb =
1957 to_amdgpu_framebuffer(plane_state->fb);
1958 const struct drm_crtc *crtc = plane_state->crtc;
1959 struct dc_transfer_func *input_tf;
1960 int ret = 0;
1961
3be5262e 1962 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1963 return -EINVAL;
1964
1965 ret = fill_plane_attributes_from_fb(
1966 crtc->dev->dev_private,
3be5262e 1967 dc_plane_state,
e7b07cee
HW		 1968 amdgpu_fb,
1969 addrReq);
1970
1971 if (ret)
1972 return ret;
1973
1974 input_tf = dc_create_transfer_func();
1975
1976 if (input_tf == NULL)
1977 return -ENOMEM;
1978
1979 input_tf->type = TF_TYPE_PREDEFINED;
1980 input_tf->tf = TRANSFER_FUNCTION_SRGB;
1981
3be5262e 1982 dc_plane_state->in_transfer_func = input_tf;
e7b07cee
HW		 1983
1984 /* In case of gamma set, update gamma value */
1985 if (crtc_state->gamma_lut)
3be5262e 1986 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
e7b07cee
HW		 1987
1988 return ret;
1989}
1990
1991/*****************************************************************************/
1992
3ee6b26b
AD		 1993static void update_stream_scaling_settings(const struct drm_display_mode *mode,
1994 const struct dm_connector_state *dm_state,
1995 struct dc_stream_state *stream)
e7b07cee
HW		 1996{
1997 enum amdgpu_rmx_type rmx_type;
1998
1999 struct rect src = { 0 }; /* viewport in composition space*/
2000 struct rect dst = { 0 }; /* stream addressable area */
2001
2002 /* no mode. nothing to be done */
2003 if (!mode)
2004 return;
2005
2006 /* Full screen scaling by default */
2007 src.width = mode->hdisplay;
2008 src.height = mode->vdisplay;
2009 dst.width = stream->timing.h_addressable;
2010 dst.height = stream->timing.v_addressable;
2011
2012 rmx_type = dm_state->scaling;
2013 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2014 if (src.width * dst.height <
2015 src.height * dst.width) {
2016 /* height needs less upscaling/more downscaling */
2017 dst.width = src.width *
2018 dst.height / src.height;
2019 } else {
2020 /* width needs less upscaling/more downscaling */
2021 dst.height = src.height *
2022 dst.width / src.width;
2023 }
2024 } else if (rmx_type == RMX_CENTER) {
2025 dst = src;
2026 }
2027
2028 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2029 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2030
2031 if (dm_state->underscan_enable) {
2032 dst.x += dm_state->underscan_hborder / 2;
2033 dst.y += dm_state->underscan_vborder / 2;
2034 dst.width -= dm_state->underscan_hborder;
2035 dst.height -= dm_state->underscan_vborder;
2036 }
2037
2038 stream->src = src;
2039 stream->dst = dst;
2040
f1ad2f5e 2041 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2042 dst.x, dst.y, dst.width, dst.height);
2043
2044}
2045
3ee6b26b
AD		 2046static enum dc_color_depth
2047convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2048{
2049 uint32_t bpc = connector->display_info.bpc;
2050
2051 /* Limited color depth to 8bit
b830ebc9
HW		 2052 * TODO: Still need to handle deep color
2053 */
e7b07cee
HW		 2054 if (bpc > 8)
2055 bpc = 8;
2056
2057 switch (bpc) {
2058 case 0:
2059 /* Temporary Work around, DRM don't parse color depth for
2060 * EDID revision before 1.4
2061 * TODO: Fix edid parsing
2062 */
2063 return COLOR_DEPTH_888;
2064 case 6:
2065 return COLOR_DEPTH_666;
2066 case 8:
2067 return COLOR_DEPTH_888;
2068 case 10:
2069 return COLOR_DEPTH_101010;
2070 case 12:
2071 return COLOR_DEPTH_121212;
2072 case 14:
2073 return COLOR_DEPTH_141414;
2074 case 16:
2075 return COLOR_DEPTH_161616;
2076 default:
2077 return COLOR_DEPTH_UNDEFINED;
2078 }
2079}
2080
3ee6b26b
AD		 2081static enum dc_aspect_ratio
2082get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2083{
2084 int32_t width = mode_in->crtc_hdisplay * 9;
2085 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2086
e7b07cee
HW		 2087 if ((width - height) < 10 && (width - height) > -10)
2088 return ASPECT_RATIO_16_9;
2089 else
2090 return ASPECT_RATIO_4_3;
2091}
2092
3ee6b26b
AD		 2093static enum dc_color_space
2094get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2095{
2096 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2097
2098 switch (dc_crtc_timing->pixel_encoding) {
2099 case PIXEL_ENCODING_YCBCR422:
2100 case PIXEL_ENCODING_YCBCR444:
2101 case PIXEL_ENCODING_YCBCR420:
2102 {
2103 /*
2104 * 27030khz is the separation point between HDTV and SDTV
2105 * according to HDMI spec, we use YCbCr709 and YCbCr601
2106 * respectively
2107 */
2108 if (dc_crtc_timing->pix_clk_khz > 27030) {
2109 if (dc_crtc_timing->flags.Y_ONLY)
2110 color_space =
2111 COLOR_SPACE_YCBCR709_LIMITED;
2112 else
2113 color_space = COLOR_SPACE_YCBCR709;
2114 } else {
2115 if (dc_crtc_timing->flags.Y_ONLY)
2116 color_space =
2117 COLOR_SPACE_YCBCR601_LIMITED;
2118 else
2119 color_space = COLOR_SPACE_YCBCR601;
2120 }
2121
2122 }
2123 break;
2124 case PIXEL_ENCODING_RGB:
2125 color_space = COLOR_SPACE_SRGB;
2126 break;
2127
2128 default:
2129 WARN_ON(1);
2130 break;
2131 }
2132
2133 return color_space;
2134}
2135
2136/*****************************************************************************/
2137
3ee6b26b
AD		 2138static void
2139fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2140 const struct drm_display_mode *mode_in,
2141 const struct drm_connector *connector)
e7b07cee
HW		 2142{
2143 struct dc_crtc_timing *timing_out = &stream->timing;
b830ebc9 2144
e7b07cee
HW		 2145 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2146
2147 timing_out->h_border_left = 0;
2148 timing_out->h_border_right = 0;
2149 timing_out->v_border_top = 0;
2150 timing_out->v_border_bottom = 0;
2151 /* TODO: un-hardcode */
2152
2153 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2154 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2155 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2156 else
2157 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2158
2159 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2160 timing_out->display_color_depth = convert_color_depth_from_display_info(
2161 connector);
2162 timing_out->scan_type = SCANNING_TYPE_NODATA;
2163 timing_out->hdmi_vic = 0;
2164 timing_out->vic = drm_match_cea_mode(mode_in);
2165
2166 timing_out->h_addressable = mode_in->crtc_hdisplay;
2167 timing_out->h_total = mode_in->crtc_htotal;
2168 timing_out->h_sync_width =
2169 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2170 timing_out->h_front_porch =
2171 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2172 timing_out->v_total = mode_in->crtc_vtotal;
2173 timing_out->v_addressable = mode_in->crtc_vdisplay;
2174 timing_out->v_front_porch =
2175 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2176 timing_out->v_sync_width =
2177 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2178 timing_out->pix_clk_khz = mode_in->crtc_clock;
2179 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2180 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2181 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2182 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2183 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2184
2185 stream->output_color_space = get_output_color_space(timing_out);
2186
2187 {
2188 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2189
e7b07cee
HW		 2190 tf->type = TF_TYPE_PREDEFINED;
2191 tf->tf = TRANSFER_FUNCTION_SRGB;
2192 stream->out_transfer_func = tf;
2193 }
2194}
2195
3ee6b26b
AD		 2196static void fill_audio_info(struct audio_info *audio_info,
2197 const struct drm_connector *drm_connector,
2198 const struct dc_sink *dc_sink)
e7b07cee
HW		 2199{
2200 int i = 0;
2201 int cea_revision = 0;
2202 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2203
2204 audio_info->manufacture_id = edid_caps->manufacturer_id;
2205 audio_info->product_id = edid_caps->product_id;
2206
2207 cea_revision = drm_connector->display_info.cea_rev;
2208
2209 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
2210 edid_caps->display_name[i]) {
2211 audio_info->display_name[i] = edid_caps->display_name[i];
2212 i++;
2213 }
2214
b830ebc9 2215 if (cea_revision >= 3) {
e7b07cee
HW		 2216 audio_info->mode_count = edid_caps->audio_mode_count;
2217
2218 for (i = 0; i < audio_info->mode_count; ++i) {
2219 audio_info->modes[i].format_code =
2220 (enum audio_format_code)
2221 (edid_caps->audio_modes[i].format_code);
2222 audio_info->modes[i].channel_count =
2223 edid_caps->audio_modes[i].channel_count;
2224 audio_info->modes[i].sample_rates.all =
2225 edid_caps->audio_modes[i].sample_rate;
2226 audio_info->modes[i].sample_size =
2227 edid_caps->audio_modes[i].sample_size;
2228 }
2229 }
2230
2231 audio_info->flags.all = edid_caps->speaker_flags;
2232
2233 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2234 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2235 audio_info->video_latency = drm_connector->video_latency[0];
2236 audio_info->audio_latency = drm_connector->audio_latency[0];
2237 }
2238
2239 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2240
2241}
2242
3ee6b26b
AD		 2243static void
2244copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2245 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2246{
2247 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2248 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2249 dst_mode->crtc_clock = src_mode->crtc_clock;
2250 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2251 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2252 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2253 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2254 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2255 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2256 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2257 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2258 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2259 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2260 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2261}
2262
3ee6b26b
AD		 2263static void
2264decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2265 const struct drm_display_mode *native_mode,
2266 bool scale_enabled)
e7b07cee
HW		 2267{
2268 if (scale_enabled) {
2269 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2270 } else if (native_mode->clock == drm_mode->clock &&
2271 native_mode->htotal == drm_mode->htotal &&
2272 native_mode->vtotal == drm_mode->vtotal) {
2273 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2274 } else {
2275 /* no scaling nor amdgpu inserted, no need to patch */
2276 }
2277}
2278
2e0ac3d6
HW		 2279static void create_fake_sink(struct amdgpu_dm_connector *aconnector)
2280{
2281 struct dc_sink *sink = NULL;
2282 struct dc_sink_init_data sink_init_data = { 0 };
2283
2284 sink_init_data.link = aconnector->dc_link;
2285 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2286
2287 sink = dc_sink_create(&sink_init_data);
2288 if (!sink)
2289 DRM_ERROR("Failed to create sink!\n");
2290
2291 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2292 aconnector->fake_enable = true;
2293
2294 aconnector->dc_sink = sink;
2295 aconnector->dc_link->local_sink = sink;
2296}
2297
3ee6b26b
AD		 2298static struct dc_stream_state *
2299create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2300 const struct drm_display_mode *drm_mode,
2301 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2302{
2303 struct drm_display_mode *preferred_mode = NULL;
2304 const struct drm_connector *drm_connector;
0971c40e 2305 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2306 struct drm_display_mode mode = *drm_mode;
2307 bool native_mode_found = false;
2308
b830ebc9 2309 if (aconnector == NULL) {
e7b07cee
HW		 2310 DRM_ERROR("aconnector is NULL!\n");
2311 goto drm_connector_null;
2312 }
2313
b830ebc9 2314 if (dm_state == NULL) {
e7b07cee
HW		 2315 DRM_ERROR("dm_state is NULL!\n");
2316 goto dm_state_null;
2317 }
4562236b 2318
e7b07cee 2319 drm_connector = &aconnector->base;
2e0ac3d6
HW		 2320
2321 if (!aconnector->dc_sink)
2322 create_fake_sink(aconnector);
2323
e7b07cee 2324 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2325
b830ebc9 2326 if (stream == NULL) {
e7b07cee
HW		 2327 DRM_ERROR("Failed to create stream for sink!\n");
2328 goto stream_create_fail;
2329 }
2330
2331 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2332 /* Search for preferred mode */
2333 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2334 native_mode_found = true;
2335 break;
2336 }
2337 }
2338 if (!native_mode_found)
2339 preferred_mode = list_first_entry_or_null(
2340 &aconnector->base.modes,
2341 struct drm_display_mode,
2342 head);
2343
b830ebc9 2344 if (preferred_mode == NULL) {
e7b07cee
HW		 2345 /* This may not be an error, the use case is when we we have no
2346 * usermode calls to reset and set mode upon hotplug. In this
2347 * case, we call set mode ourselves to restore the previous mode
2348 * and the modelist may not be filled in in time.
2349 */
f1ad2f5e 2350 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2351 } else {
2352 decide_crtc_timing_for_drm_display_mode(
2353 &mode, preferred_mode,
2354 dm_state->scaling != RMX_OFF);
2355 }
2356
2357 fill_stream_properties_from_drm_display_mode(stream,
2358 &mode, &aconnector->base);
2359 update_stream_scaling_settings(&mode, dm_state, stream);
2360
2361 fill_audio_info(
2362 &stream->audio_info,
2363 drm_connector,
2364 aconnector->dc_sink);
2365
2366stream_create_fail:
2367dm_state_null:
2368drm_connector_null:
2369 return stream;
2370}
2371
7578ecda 2372static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2373{
2374 drm_crtc_cleanup(crtc);
2375 kfree(crtc);
2376}
2377
2378static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2379 struct drm_crtc_state *state)
e7b07cee
HW		 2380{
2381 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2382
2383 /* TODO Destroy dc_stream objects are stream object is flattened */
2384 if (cur->stream)
2385 dc_stream_release(cur->stream);
2386
2387
2388 __drm_atomic_helper_crtc_destroy_state(state);
2389
2390
2391 kfree(state);
2392}
2393
2394static void dm_crtc_reset_state(struct drm_crtc *crtc)
2395{
2396 struct dm_crtc_state *state;
2397
2398 if (crtc->state)
2399 dm_crtc_destroy_state(crtc, crtc->state);
2400
2401 state = kzalloc(sizeof(*state), GFP_KERNEL);
2402 if (WARN_ON(!state))
2403 return;
2404
2405 crtc->state = &state->base;
2406 crtc->state->crtc = crtc;
2407
2408}
2409
2410static struct drm_crtc_state *
2411dm_crtc_duplicate_state(struct drm_crtc *crtc)
2412{
2413 struct dm_crtc_state *state, *cur;
2414
2415 cur = to_dm_crtc_state(crtc->state);
2416
2417 if (WARN_ON(!crtc->state))
2418 return NULL;
2419
2004f45e 2420 state = kzalloc(sizeof(*state), GFP_KERNEL);
e7b07cee
HW		 2421
2422 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2423
2424 if (cur->stream) {
2425 state->stream = cur->stream;
2426 dc_stream_retain(state->stream);
2427 }
2428
2429 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2430
2431 return &state->base;
2432}
2433
2434/* Implemented only the options currently availible for the driver */
2435static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2436 .reset = dm_crtc_reset_state,
2437 .destroy = amdgpu_dm_crtc_destroy,
2438 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2439 .set_config = drm_atomic_helper_set_config,
2440 .page_flip = drm_atomic_helper_page_flip,
2441 .atomic_duplicate_state = dm_crtc_duplicate_state,
2442 .atomic_destroy_state = dm_crtc_destroy_state,
2443};
2444
2445static enum drm_connector_status
2446amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2447{
2448 bool connected;
c84dec2f 2449 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2450
2451 /* Notes:
2452 * 1. This interface is NOT called in context of HPD irq.
2453 * 2. This interface *is called* in context of user-mode ioctl. Which
2454 * makes it a bad place for *any* MST-related activit. */
2455
2456 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2457 connected = (aconnector->dc_sink != NULL);
2458 else
2459 connected = (aconnector->base.force == DRM_FORCE_ON);
2460
2461 return (connected ? connector_status_connected :
2462 connector_status_disconnected);
2463}
2464
3ee6b26b
AD		 2465int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2466 struct drm_connector_state *connector_state,
2467 struct drm_property *property,
2468 uint64_t val)
e7b07cee
HW		 2469{
2470 struct drm_device *dev = connector->dev;
2471 struct amdgpu_device *adev = dev->dev_private;
2472 struct dm_connector_state *dm_old_state =
2473 to_dm_connector_state(connector->state);
2474 struct dm_connector_state *dm_new_state =
2475 to_dm_connector_state(connector_state);
2476
2477 int ret = -EINVAL;
2478
2479 if (property == dev->mode_config.scaling_mode_property) {
2480 enum amdgpu_rmx_type rmx_type;
2481
2482 switch (val) {
2483 case DRM_MODE_SCALE_CENTER:
2484 rmx_type = RMX_CENTER;
2485 break;
2486 case DRM_MODE_SCALE_ASPECT:
2487 rmx_type = RMX_ASPECT;
2488 break;
2489 case DRM_MODE_SCALE_FULLSCREEN:
2490 rmx_type = RMX_FULL;
2491 break;
2492 case DRM_MODE_SCALE_NONE:
2493 default:
2494 rmx_type = RMX_OFF;
2495 break;
2496 }
2497
2498 if (dm_old_state->scaling == rmx_type)
2499 return 0;
2500
2501 dm_new_state->scaling = rmx_type;
2502 ret = 0;
2503 } else if (property == adev->mode_info.underscan_hborder_property) {
2504 dm_new_state->underscan_hborder = val;
2505 ret = 0;
2506 } else if (property == adev->mode_info.underscan_vborder_property) {
2507 dm_new_state->underscan_vborder = val;
2508 ret = 0;
2509 } else if (property == adev->mode_info.underscan_property) {
2510 dm_new_state->underscan_enable = val;
2511 ret = 0;
2512 }
2513
2514 return ret;
2515}
2516
3ee6b26b
AD		 2517int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2518 const struct drm_connector_state *state,
2519 struct drm_property *property,
2520 uint64_t *val)
e7b07cee
HW		 2521{
2522 struct drm_device *dev = connector->dev;
2523 struct amdgpu_device *adev = dev->dev_private;
2524 struct dm_connector_state *dm_state =
2525 to_dm_connector_state(state);
2526 int ret = -EINVAL;
2527
2528 if (property == dev->mode_config.scaling_mode_property) {
2529 switch (dm_state->scaling) {
2530 case RMX_CENTER:
2531 *val = DRM_MODE_SCALE_CENTER;
2532 break;
2533 case RMX_ASPECT:
2534 *val = DRM_MODE_SCALE_ASPECT;
2535 break;
2536 case RMX_FULL:
2537 *val = DRM_MODE_SCALE_FULLSCREEN;
2538 break;
2539 case RMX_OFF:
2540 default:
2541 *val = DRM_MODE_SCALE_NONE;
2542 break;
2543 }
2544 ret = 0;
2545 } else if (property == adev->mode_info.underscan_hborder_property) {
2546 *val = dm_state->underscan_hborder;
2547 ret = 0;
2548 } else if (property == adev->mode_info.underscan_vborder_property) {
2549 *val = dm_state->underscan_vborder;
2550 ret = 0;
2551 } else if (property == adev->mode_info.underscan_property) {
2552 *val = dm_state->underscan_enable;
2553 ret = 0;
2554 }
2555 return ret;
2556}
2557
7578ecda 2558static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2559{
c84dec2f 2560 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2561 const struct dc_link *link = aconnector->dc_link;
2562 struct amdgpu_device *adev = connector->dev->dev_private;
2563 struct amdgpu_display_manager *dm = &adev->dm;
2564#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2565 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2566
2567 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2568 amdgpu_dm_register_backlight_device(dm);
2569
2570 if (dm->backlight_dev) {
2571 backlight_device_unregister(dm->backlight_dev);
2572 dm->backlight_dev = NULL;
2573 }
2574
2575 }
2576#endif
2577 drm_connector_unregister(connector);
2578 drm_connector_cleanup(connector);
2579 kfree(connector);
2580}
2581
2582void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2583{
2584 struct dm_connector_state *state =
2585 to_dm_connector_state(connector->state);
2586
2587 kfree(state);
2588
2589 state = kzalloc(sizeof(*state), GFP_KERNEL);
2590
2591 if (state) {
2592 state->scaling = RMX_OFF;
2593 state->underscan_enable = false;
2594 state->underscan_hborder = 0;
2595 state->underscan_vborder = 0;
2596
2597 connector->state = &state->base;
2598 connector->state->connector = connector;
2599 }
2600}
2601
3ee6b26b
AD		 2602struct drm_connector_state *
2603amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2604{
2605 struct dm_connector_state *state =
2606 to_dm_connector_state(connector->state);
2607
2608 struct dm_connector_state *new_state =
2609 kmemdup(state, sizeof(*state), GFP_KERNEL);
2610
2611 if (new_state) {
2612 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2613 &new_state->base);
e7b07cee
HW		 2614 return &new_state->base;
2615 }
2616
2617 return NULL;
2618}
2619
2620static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2621 .reset = amdgpu_dm_connector_funcs_reset,
2622 .detect = amdgpu_dm_connector_detect,
2623 .fill_modes = drm_helper_probe_single_connector_modes,
2624 .destroy = amdgpu_dm_connector_destroy,
2625 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2626 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2627 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2628 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2629};
2630
2631static struct drm_encoder *best_encoder(struct drm_connector *connector)
2632{
2633 int enc_id = connector->encoder_ids[0];
2634 struct drm_mode_object *obj;
2635 struct drm_encoder *encoder;
2636
f1ad2f5e 2637 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2638
2639 /* pick the encoder ids */
2640 if (enc_id) {
2641 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
2642 if (!obj) {
2643 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2644 return NULL;
2645 }
2646 encoder = obj_to_encoder(obj);
2647 return encoder;
2648 }
2649 DRM_ERROR("No encoder id\n");
2650 return NULL;
2651}
2652
2653static int get_modes(struct drm_connector *connector)
2654{
2655 return amdgpu_dm_connector_get_modes(connector);
2656}
2657
c84dec2f 2658static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2659{
2660 struct dc_sink_init_data init_params = {
2661 .link = aconnector->dc_link,
2662 .sink_signal = SIGNAL_TYPE_VIRTUAL
2663 };
2664 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2665
2666 if (!aconnector->base.edid_blob_ptr ||
2667 !aconnector->base.edid_blob_ptr->data) {
2668 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2669 aconnector->base.name);
2670
2671 aconnector->base.force = DRM_FORCE_OFF;
2672 aconnector->base.override_edid = false;
2673 return;
2674 }
2675
2676 aconnector->edid = edid;
2677
2678 aconnector->dc_em_sink = dc_link_add_remote_sink(
2679 aconnector->dc_link,
2680 (uint8_t *)edid,
2681 (edid->extensions + 1) * EDID_LENGTH,
2682 &init_params);
2683
2684 if (aconnector->base.force
2685 == DRM_FORCE_ON)
2686 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2687 aconnector->dc_link->local_sink :
2688 aconnector->dc_em_sink;
2689}
2690
c84dec2f 2691static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2692{
2693 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2694
2695 /* In case of headless boot with force on for DP managed connector
2696 * Those settings have to be != 0 to get initial modeset
2697 */
2698 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2699 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2700 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2701 }
2702
2703
2704 aconnector->base.override_edid = true;
2705 create_eml_sink(aconnector);
2706}
2707
3ee6b26b
AD		 2708int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2709 struct drm_display_mode *mode)
e7b07cee
HW		 2710{
2711 int result = MODE_ERROR;
2712 struct dc_sink *dc_sink;
2713 struct amdgpu_device *adev = connector->dev->dev_private;
2714 /* TODO: Unhardcode stream count */
0971c40e 2715 struct dc_stream_state *stream;
c84dec2f 2716 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2717
2718 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2719 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2720 return result;
2721
2722 /* Only run this the first time mode_valid is called to initilialize
2723 * EDID mgmt
2724 */
2725 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2726 !aconnector->dc_em_sink)
2727 handle_edid_mgmt(aconnector);
2728
c84dec2f 2729 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2730
b830ebc9 2731 if (dc_sink == NULL) {
e7b07cee
HW		 2732 DRM_ERROR("dc_sink is NULL!\n");
2733 goto fail;
2734 }
2735
2736 stream = dc_create_stream_for_sink(dc_sink);
b830ebc9 2737 if (stream == NULL) {
e7b07cee
HW		 2738 DRM_ERROR("Failed to create stream for sink!\n");
2739 goto fail;
2740 }
2741
2742 drm_mode_set_crtcinfo(mode, 0);
2743 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2744
2745 stream->src.width = mode->hdisplay;
2746 stream->src.height = mode->vdisplay;
2747 stream->dst = stream->src;
2748
2749 if (dc_validate_stream(adev->dm.dc, stream))
2750 result = MODE_OK;
2751
2752 dc_stream_release(stream);
2753
2754fail:
2755 /* TODO: error handling*/
2756 return result;
2757}
2758
2759static const struct drm_connector_helper_funcs
2760amdgpu_dm_connector_helper_funcs = {
2761 /*
b830ebc9
HW		 2762 * If hotplug a second bigger display in FB Con mode, bigger resolution
2763 * modes will be filtered by drm_mode_validate_size(), and those modes
2764 * is missing after user start lightdm. So we need to renew modes list.
2765 * in get_modes call back, not just return the modes count
2766 */
e7b07cee
HW		 2767 .get_modes = get_modes,
2768 .mode_valid = amdgpu_dm_connector_mode_valid,
2769 .best_encoder = best_encoder
2770};
2771
2772static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2773{
2774}
2775
3ee6b26b
AD		 2776static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2777 struct drm_crtc_state *state)
e7b07cee
HW		 2778{
2779 struct amdgpu_device *adev = crtc->dev->dev_private;
2780 struct dc *dc = adev->dm.dc;
2781 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2782 int ret = -EINVAL;
2783
9b690ef3
BL		 2784 if (unlikely(!dm_crtc_state->stream &&
2785 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2786 WARN_ON(1);
2787 return ret;
2788 }
2789
2790 /* In some use cases, like reset, no stream is attached */
2791 if (!dm_crtc_state->stream)
2792 return 0;
2793
2794 if (dc_validate_stream(dc, dm_crtc_state->stream))
2795 return 0;
2796
2797 return ret;
2798}
2799
3ee6b26b
AD		 2800static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2801 const struct drm_display_mode *mode,
2802 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2803{
2804 return true;
2805}
2806
2807static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2808 .disable = dm_crtc_helper_disable,
2809 .atomic_check = dm_crtc_helper_atomic_check,
2810 .mode_fixup = dm_crtc_helper_mode_fixup
2811};
2812
2813static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2814{
2815
2816}
2817
3ee6b26b
AD		 2818static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2819 struct drm_crtc_state *crtc_state,
2820 struct drm_connector_state *conn_state)
e7b07cee
HW		 2821{
2822 return 0;
2823}
2824
2825const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2826 .disable = dm_encoder_helper_disable,
2827 .atomic_check = dm_encoder_helper_atomic_check
2828};
2829
2830static void dm_drm_plane_reset(struct drm_plane *plane)
2831{
2832 struct dm_plane_state *amdgpu_state = NULL;
2833
2834 if (plane->state)
2835 plane->funcs->atomic_destroy_state(plane, plane->state);
2836
2837 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2838
2839 if (amdgpu_state) {
2840 plane->state = &amdgpu_state->base;
2841 plane->state->plane = plane;
2842 plane->state->rotation = DRM_MODE_ROTATE_0;
2843 } else
2844 WARN_ON(1);
2845}
2846
2847static struct drm_plane_state *
2848dm_drm_plane_duplicate_state(struct drm_plane *plane)
2849{
2850 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2851
2852 old_dm_plane_state = to_dm_plane_state(plane->state);
2853 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2854 if (!dm_plane_state)
2855 return NULL;
2856
2857 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2858
3be5262e
HW		 2859 if (old_dm_plane_state->dc_state) {
2860 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2861 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2862 }
2863
2864 return &dm_plane_state->base;
2865}
2866
2867void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2868 struct drm_plane_state *state)
e7b07cee
HW		 2869{
2870 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2871
3be5262e
HW		 2872 if (dm_plane_state->dc_state)
2873 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2874
0627bbd3 2875 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2876}
2877
2878static const struct drm_plane_funcs dm_plane_funcs = {
2879 .update_plane = drm_atomic_helper_update_plane,
2880 .disable_plane = drm_atomic_helper_disable_plane,
2881 .destroy = drm_plane_cleanup,
2882 .reset = dm_drm_plane_reset,
2883 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2884 .atomic_destroy_state = dm_drm_plane_destroy_state,
2885};
2886
3ee6b26b
AD		 2887static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2888 struct drm_plane_state *new_state)
e7b07cee
HW		 2889{
2890 struct amdgpu_framebuffer *afb;
2891 struct drm_gem_object *obj;
2892 struct amdgpu_bo *rbo;
2893 int r;
2894 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2895 unsigned int awidth;
2896
2897 dm_plane_state_old = to_dm_plane_state(plane->state);
2898 dm_plane_state_new = to_dm_plane_state(new_state);
2899
2900 if (!new_state->fb) {
f1ad2f5e 2901 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 2902 return 0;
2903 }
2904
2905 afb = to_amdgpu_framebuffer(new_state->fb);
2906
2907 obj = afb->obj;
2908 rbo = gem_to_amdgpu_bo(obj);
2909 r = amdgpu_bo_reserve(rbo, false);
2910 if (unlikely(r != 0))
2911 return r;
2912
2913 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
2914
2915
2916 amdgpu_bo_unreserve(rbo);
2917
2918 if (unlikely(r != 0)) {
2919 DRM_ERROR("Failed to pin framebuffer\n");
2920 return r;
2921 }
2922
2923 amdgpu_bo_ref(rbo);
2924
3be5262e
HW		 2925 if (dm_plane_state_new->dc_state &&
2926 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2927 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 2928
3be5262e
HW		 2929 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2930 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
2931 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 2932 } else {
2933 awidth = ALIGN(new_state->fb->width, 64);
3be5262e 2934 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 2935 = lower_32_bits(afb->address);
3be5262e 2936 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 2937 = lower_32_bits(afb->address) +
2938 (awidth * new_state->fb->height);
2939 }
2940 }
2941
2942 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
2943 * prepare and cleanup in drm_atomic_helper_prepare_planes
2944 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
2945 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
2946 * code touching fram buffers should be avoided for DC.
2947 */
2948 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2949 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
2950
2951 acrtc->cursor_bo = obj;
2952 }
2953 return 0;
2954}
2955
3ee6b26b
AD		 2956static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
2957 struct drm_plane_state *old_state)
e7b07cee
HW		 2958{
2959 struct amdgpu_bo *rbo;
2960 struct amdgpu_framebuffer *afb;
2961 int r;
2962
2963 if (!old_state->fb)
2964 return;
2965
2966 afb = to_amdgpu_framebuffer(old_state->fb);
2967 rbo = gem_to_amdgpu_bo(afb->obj);
2968 r = amdgpu_bo_reserve(rbo, false);
2969 if (unlikely(r)) {
2970 DRM_ERROR("failed to reserve rbo before unpin\n");
2971 return;
b830ebc9
HW		 2972 }
2973
2974 amdgpu_bo_unpin(rbo);
2975 amdgpu_bo_unreserve(rbo);
2976 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 2977}
2978
7578ecda
AD		 2979static int dm_plane_atomic_check(struct drm_plane *plane,
2980 struct drm_plane_state *state)
cbd19488
AG		 2981{
2982 struct amdgpu_device *adev = plane->dev->dev_private;
2983 struct dc *dc = adev->dm.dc;
2984 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2985
3be5262e 2986 if (!dm_plane_state->dc_state)
9a3329b1 2987 return 0;
cbd19488 2988
3be5262e 2989 if (dc_validate_plane(dc, dm_plane_state->dc_state))
cbd19488
AG		 2990 return 0;
2991
2992 return -EINVAL;
2993}
2994
e7b07cee
HW		 2995static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
2996 .prepare_fb = dm_plane_helper_prepare_fb,
2997 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 2998 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 2999};
3000
3001/*
3002 * TODO: these are currently initialized to rgb formats only.
3003 * For future use cases we should either initialize them dynamically based on
3004 * plane capabilities, or initialize this array to all formats, so internal drm
3005 * check will succeed, and let DC to implement proper check
3006 */
d90371b0 3007static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3008 DRM_FORMAT_RGB888,
3009 DRM_FORMAT_XRGB8888,
3010 DRM_FORMAT_ARGB8888,
3011 DRM_FORMAT_RGBA8888,
3012 DRM_FORMAT_XRGB2101010,
3013 DRM_FORMAT_XBGR2101010,
3014 DRM_FORMAT_ARGB2101010,
3015 DRM_FORMAT_ABGR2101010,
3016};
3017
99d1abf8 3018static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3019 DRM_FORMAT_NV12,
3020 DRM_FORMAT_NV21,
3021};
3022
3023static const u32 cursor_formats[] = {
3024 DRM_FORMAT_ARGB8888
3025};
3026
7578ecda
AD		 3027static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3028 struct amdgpu_plane *aplane,
3029 unsigned long possible_crtcs)
e7b07cee
HW		 3030{
3031 int res = -EPERM;
3032
3033 switch (aplane->base.type) {
3034 case DRM_PLANE_TYPE_PRIMARY:
3035 aplane->base.format_default = true;
3036
3037 res = drm_universal_plane_init(
3038 dm->adev->ddev,
3039 &aplane->base,
3040 possible_crtcs,
3041 &dm_plane_funcs,
3042 rgb_formats,
3043 ARRAY_SIZE(rgb_formats),
3044 NULL, aplane->base.type, NULL);
3045 break;
3046 case DRM_PLANE_TYPE_OVERLAY:
3047 res = drm_universal_plane_init(
3048 dm->adev->ddev,
3049 &aplane->base,
3050 possible_crtcs,
3051 &dm_plane_funcs,
3052 yuv_formats,
3053 ARRAY_SIZE(yuv_formats),
3054 NULL, aplane->base.type, NULL);
3055 break;
3056 case DRM_PLANE_TYPE_CURSOR:
3057 res = drm_universal_plane_init(
3058 dm->adev->ddev,
3059 &aplane->base,
3060 possible_crtcs,
3061 &dm_plane_funcs,
3062 cursor_formats,
3063 ARRAY_SIZE(cursor_formats),
3064 NULL, aplane->base.type, NULL);
3065 break;
3066 }
3067
3068 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3069
3070 return res;
3071}
3072
7578ecda
AD		 3073static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3074 struct drm_plane *plane,
3075 uint32_t crtc_index)
e7b07cee
HW		 3076{
3077 struct amdgpu_crtc *acrtc = NULL;
3078 struct amdgpu_plane *cursor_plane;
3079
3080 int res = -ENOMEM;
3081
3082 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3083 if (!cursor_plane)
3084 goto fail;
3085
3086 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3087 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3088
3089 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3090 if (!acrtc)
3091 goto fail;
3092
3093 res = drm_crtc_init_with_planes(
3094 dm->ddev,
3095 &acrtc->base,
3096 plane,
3097 &cursor_plane->base,
3098 &amdgpu_dm_crtc_funcs, NULL);
3099
3100 if (res)
3101 goto fail;
3102
3103 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3104
3105 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3106 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3107
3108 acrtc->crtc_id = crtc_index;
3109 acrtc->base.enabled = false;
3110
3111 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3112 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3113
3114 return 0;
3115
3116fail:
b830ebc9
HW		 3117 kfree(acrtc);
3118 kfree(cursor_plane);
e7b07cee
HW		 3119 return res;
3120}
3121
3122
3123static int to_drm_connector_type(enum signal_type st)
3124{
3125 switch (st) {
3126 case SIGNAL_TYPE_HDMI_TYPE_A:
3127 return DRM_MODE_CONNECTOR_HDMIA;
3128 case SIGNAL_TYPE_EDP:
3129 return DRM_MODE_CONNECTOR_eDP;
3130 case SIGNAL_TYPE_RGB:
3131 return DRM_MODE_CONNECTOR_VGA;
3132 case SIGNAL_TYPE_DISPLAY_PORT:
3133 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3134 return DRM_MODE_CONNECTOR_DisplayPort;
3135 case SIGNAL_TYPE_DVI_DUAL_LINK:
3136 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3137 return DRM_MODE_CONNECTOR_DVID;
3138 case SIGNAL_TYPE_VIRTUAL:
3139 return DRM_MODE_CONNECTOR_VIRTUAL;
3140
3141 default:
3142 return DRM_MODE_CONNECTOR_Unknown;
3143 }
3144}
3145
3146static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3147{
3148 const struct drm_connector_helper_funcs *helper =
3149 connector->helper_private;
3150 struct drm_encoder *encoder;
3151 struct amdgpu_encoder *amdgpu_encoder;
3152
3153 encoder = helper->best_encoder(connector);
3154
3155 if (encoder == NULL)
3156 return;
3157
3158 amdgpu_encoder = to_amdgpu_encoder(encoder);
3159
3160 amdgpu_encoder->native_mode.clock = 0;
3161
3162 if (!list_empty(&connector->probed_modes)) {
3163 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3164
e7b07cee 3165 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3166 &connector->probed_modes,
3167 head) {
3168 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3169 amdgpu_encoder->native_mode = *preferred_mode;
3170
e7b07cee
HW		 3171 break;
3172 }
3173
3174 }
3175}
3176
3ee6b26b
AD		 3177static struct drm_display_mode *
3178amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3179 char *name,
3180 int hdisplay, int vdisplay)
e7b07cee
HW		 3181{
3182 struct drm_device *dev = encoder->dev;
3183 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3184 struct drm_display_mode *mode = NULL;
3185 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3186
3187 mode = drm_mode_duplicate(dev, native_mode);
3188
b830ebc9 3189 if (mode == NULL)
e7b07cee
HW		 3190 return NULL;
3191
3192 mode->hdisplay = hdisplay;
3193 mode->vdisplay = vdisplay;
3194 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3195 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3196
3197 return mode;
3198
3199}
3200
3201static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3202 struct drm_connector *connector)
e7b07cee
HW		 3203{
3204 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3205 struct drm_display_mode *mode = NULL;
3206 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3207 struct amdgpu_dm_connector *amdgpu_dm_connector =
3208 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3209 int i;
3210 int n;
3211 struct mode_size {
3212 char name[DRM_DISPLAY_MODE_LEN];
3213 int w;
3214 int h;
b830ebc9 3215 } common_modes[] = {
e7b07cee
HW		 3216 { "640x480", 640, 480},
3217 { "800x600", 800, 600},
3218 { "1024x768", 1024, 768},
3219 { "1280x720", 1280, 720},
3220 { "1280x800", 1280, 800},
3221 {"1280x1024", 1280, 1024},
3222 { "1440x900", 1440, 900},
3223 {"1680x1050", 1680, 1050},
3224 {"1600x1200", 1600, 1200},
3225 {"1920x1080", 1920, 1080},
3226 {"1920x1200", 1920, 1200}
3227 };
3228
b830ebc9 3229 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3230
3231 for (i = 0; i < n; i++) {
3232 struct drm_display_mode *curmode = NULL;
3233 bool mode_existed = false;
3234
3235 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3236 common_modes[i].h > native_mode->vdisplay ||
3237 (common_modes[i].w == native_mode->hdisplay &&
3238 common_modes[i].h == native_mode->vdisplay))
3239 continue;
e7b07cee
HW		 3240
3241 list_for_each_entry(curmode, &connector->probed_modes, head) {
3242 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3243 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3244 mode_existed = true;
3245 break;
3246 }
3247 }
3248
3249 if (mode_existed)
3250 continue;
3251
3252 mode = amdgpu_dm_create_common_mode(encoder,
3253 common_modes[i].name, common_modes[i].w,
3254 common_modes[i].h);
3255 drm_mode_probed_add(connector, mode);
c84dec2f 3256 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3257 }
3258}
3259
3ee6b26b
AD		 3260static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3261 struct edid *edid)
e7b07cee 3262{
c84dec2f
HW		 3263 struct amdgpu_dm_connector *amdgpu_dm_connector =
3264 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3265
3266 if (edid) {
3267 /* empty probed_modes */
3268 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3269 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3270 drm_add_edid_modes(connector, edid);
3271
3272 drm_edid_to_eld(connector, edid);
3273
3274 amdgpu_dm_get_native_mode(connector);
3275 } else
c84dec2f 3276 amdgpu_dm_connector->num_modes = 0;
e7b07cee
HW		 3277}
3278
7578ecda 3279static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3280{
3281 const struct drm_connector_helper_funcs *helper =
3282 connector->helper_private;
c84dec2f
HW		 3283 struct amdgpu_dm_connector *amdgpu_dm_connector =
3284 to_amdgpu_dm_connector(connector);
e7b07cee 3285 struct drm_encoder *encoder;
c84dec2f 3286 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3287
3288 encoder = helper->best_encoder(connector);
3289
3290 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3291 amdgpu_dm_connector_add_common_modes(encoder, connector);
c84dec2f 3292 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3293}
3294
3ee6b26b
AD		 3295void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3296 struct amdgpu_dm_connector *aconnector,
3297 int connector_type,
3298 struct dc_link *link,
3299 int link_index)
e7b07cee
HW		 3300{
3301 struct amdgpu_device *adev = dm->ddev->dev_private;
3302
3303 aconnector->connector_id = link_index;
3304 aconnector->dc_link = link;
3305 aconnector->base.interlace_allowed = false;
3306 aconnector->base.doublescan_allowed = false;
3307 aconnector->base.stereo_allowed = false;
3308 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3309 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3310
3311 mutex_init(&aconnector->hpd_lock);
3312
b830ebc9
HW		 3313 /* configure support HPD hot plug connector_>polled default value is 0
3314 * which means HPD hot plug not supported
3315 */
e7b07cee
HW		 3316 switch (connector_type) {
3317 case DRM_MODE_CONNECTOR_HDMIA:
3318 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3319 break;
3320 case DRM_MODE_CONNECTOR_DisplayPort:
3321 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3322 break;
3323 case DRM_MODE_CONNECTOR_DVID:
3324 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3325 break;
3326 default:
3327 break;
3328 }
3329
3330 drm_object_attach_property(&aconnector->base.base,
3331 dm->ddev->mode_config.scaling_mode_property,
3332 DRM_MODE_SCALE_NONE);
3333
3334 drm_object_attach_property(&aconnector->base.base,
3335 adev->mode_info.underscan_property,
3336 UNDERSCAN_OFF);
3337 drm_object_attach_property(&aconnector->base.base,
3338 adev->mode_info.underscan_hborder_property,
3339 0);
3340 drm_object_attach_property(&aconnector->base.base,
3341 adev->mode_info.underscan_vborder_property,
3342 0);
3343
3344}
3345
7578ecda
AD		 3346static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3347 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3348{
3349 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3350 struct ddc_service *ddc_service = i2c->ddc_service;
3351 struct i2c_command cmd;
3352 int i;
3353 int result = -EIO;
3354
b830ebc9 3355 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3356
3357 if (!cmd.payloads)
3358 return result;
3359
3360 cmd.number_of_payloads = num;
3361 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3362 cmd.speed = 100;
3363
3364 for (i = 0; i < num; i++) {
3365 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3366 cmd.payloads[i].address = msgs[i].addr;
3367 cmd.payloads[i].length = msgs[i].len;
3368 cmd.payloads[i].data = msgs[i].buf;
3369 }
3370
3371 if (dal_i2caux_submit_i2c_command(
3372 ddc_service->ctx->i2caux,
3373 ddc_service->ddc_pin,
3374 &cmd))
3375 result = num;
3376
3377 kfree(cmd.payloads);
3378 return result;
3379}
3380
7578ecda 3381static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3382{
3383 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3384}
3385
3386static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3387 .master_xfer = amdgpu_dm_i2c_xfer,
3388 .functionality = amdgpu_dm_i2c_func,
3389};
3390
3ee6b26b
AD		 3391static struct amdgpu_i2c_adapter *
3392create_i2c(struct ddc_service *ddc_service,
3393 int link_index,
3394 int *res)
e7b07cee
HW		 3395{
3396 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3397 struct amdgpu_i2c_adapter *i2c;
3398
b830ebc9 3399 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
e7b07cee
HW		 3400 i2c->base.owner = THIS_MODULE;
3401 i2c->base.class = I2C_CLASS_DDC;
3402 i2c->base.dev.parent = &adev->pdev->dev;
3403 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3404 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3405 i2c_set_adapdata(&i2c->base, i2c);
3406 i2c->ddc_service = ddc_service;
3407
3408 return i2c;
3409}
3410
3411/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3412 * dc_link which will be represented by this aconnector.
3413 */
7578ecda
AD		 3414static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3415 struct amdgpu_dm_connector *aconnector,
3416 uint32_t link_index,
3417 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3418{
3419 int res = 0;
3420 int connector_type;
3421 struct dc *dc = dm->dc;
3422 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3423 struct amdgpu_i2c_adapter *i2c;
3424 ((struct dc_link *)link)->priv = aconnector;
3425
f1ad2f5e 3426 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3427
3428 i2c = create_i2c(link->ddc, link->link_index, &res);
3429 aconnector->i2c = i2c;
3430 res = i2c_add_adapter(&i2c->base);
3431
3432 if (res) {
3433 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3434 goto out_free;
3435 }
3436
3437 connector_type = to_drm_connector_type(link->connector_signal);
3438
3439 res = drm_connector_init(
3440 dm->ddev,
3441 &aconnector->base,
3442 &amdgpu_dm_connector_funcs,
3443 connector_type);
3444
3445 if (res) {
3446 DRM_ERROR("connector_init failed\n");
3447 aconnector->connector_id = -1;
3448 goto out_free;
3449 }
3450
3451 drm_connector_helper_add(
3452 &aconnector->base,
3453 &amdgpu_dm_connector_helper_funcs);
3454
3455 amdgpu_dm_connector_init_helper(
3456 dm,
3457 aconnector,
3458 connector_type,
3459 link,
3460 link_index);
3461
3462 drm_mode_connector_attach_encoder(
3463 &aconnector->base, &aencoder->base);
3464
3465 drm_connector_register(&aconnector->base);
3466
3467 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3468 || connector_type == DRM_MODE_CONNECTOR_eDP)
3469 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3470
3471#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3472 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3473
3474 /* NOTE: this currently will create backlight device even if a panel
3475 * is not connected to the eDP/LVDS connector.
3476 *
3477 * This is less than ideal but we don't have sink information at this
3478 * stage since detection happens after. We can't do detection earlier
3479 * since MST detection needs connectors to be created first.
3480 */
3481 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3482 /* Event if registration failed, we should continue with
3483 * DM initialization because not having a backlight control
b830ebc9
HW		 3484 * is better then a black screen.
3485 */
e7b07cee
HW		 3486 amdgpu_dm_register_backlight_device(dm);
3487
3488 if (dm->backlight_dev)
3489 dm->backlight_link = link;
3490 }
3491#endif
3492
3493out_free:
3494 if (res) {
3495 kfree(i2c);
3496 aconnector->i2c = NULL;
3497 }
3498 return res;
3499}
3500
3501int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3502{
3503 switch (adev->mode_info.num_crtc) {
3504 case 1:
3505 return 0x1;
3506 case 2:
3507 return 0x3;
3508 case 3:
3509 return 0x7;
3510 case 4:
3511 return 0xf;
3512 case 5:
3513 return 0x1f;
3514 case 6:
3515 default:
3516 return 0x3f;
3517 }
3518}
3519
7578ecda
AD		 3520static int amdgpu_dm_encoder_init(struct drm_device *dev,
3521 struct amdgpu_encoder *aencoder,
3522 uint32_t link_index)
e7b07cee
HW		 3523{
3524 struct amdgpu_device *adev = dev->dev_private;
3525
3526 int res = drm_encoder_init(dev,
3527 &aencoder->base,
3528 &amdgpu_dm_encoder_funcs,
3529 DRM_MODE_ENCODER_TMDS,
3530 NULL);
3531
3532 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3533
3534 if (!res)
3535 aencoder->encoder_id = link_index;
3536 else
3537 aencoder->encoder_id = -1;
3538
3539 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3540
3541 return res;
3542}
3543
3ee6b26b
AD		 3544static void manage_dm_interrupts(struct amdgpu_device *adev,
3545 struct amdgpu_crtc *acrtc,
3546 bool enable)
e7b07cee
HW		 3547{
3548 /*
3549 * this is not correct translation but will work as soon as VBLANK
3550 * constant is the same as PFLIP
3551 */
3552 int irq_type =
3553 amdgpu_crtc_idx_to_irq_type(
3554 adev,
3555 acrtc->crtc_id);
3556
3557 if (enable) {
3558 drm_crtc_vblank_on(&acrtc->base);
3559 amdgpu_irq_get(
3560 adev,
3561 &adev->pageflip_irq,
3562 irq_type);
3563 } else {
3564
3565 amdgpu_irq_put(
3566 adev,
3567 &adev->pageflip_irq,
3568 irq_type);
3569 drm_crtc_vblank_off(&acrtc->base);
3570 }
3571}
3572
3ee6b26b
AD		 3573static bool
3574is_scaling_state_different(const struct dm_connector_state *dm_state,
3575 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3576{
3577 if (dm_state->scaling != old_dm_state->scaling)
3578 return true;
3579 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3580 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3581 return true;
3582 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3583 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3584 return true;
b830ebc9
HW		 3585 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3586 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3587 return true;
e7b07cee
HW		 3588 return false;
3589}
3590
3ee6b26b
AD		 3591static void remove_stream(struct amdgpu_device *adev,
3592 struct amdgpu_crtc *acrtc,
3593 struct dc_stream_state *stream)
e7b07cee
HW		 3594{
3595 /* this is the update mode case */
3596 if (adev->dm.freesync_module)
3597 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3598
3599 acrtc->otg_inst = -1;
3600 acrtc->enabled = false;
3601}
3602
7578ecda
AD		 3603static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3604 struct dc_cursor_position *position)
2a8f6ccb
HW		 3605{
3606 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3607 int x, y;
3608 int xorigin = 0, yorigin = 0;
3609
3610 if (!crtc || !plane->state->fb) {
3611 position->enable = false;
3612 position->x = 0;
3613 position->y = 0;
3614 return 0;
3615 }
3616
3617 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3618 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3619 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3620 __func__,
3621 plane->state->crtc_w,
3622 plane->state->crtc_h);
3623 return -EINVAL;
3624 }
3625
3626 x = plane->state->crtc_x;
3627 y = plane->state->crtc_y;
3628 /* avivo cursor are offset into the total surface */
3629 x += crtc->primary->state->src_x >> 16;
3630 y += crtc->primary->state->src_y >> 16;
3631 if (x < 0) {
3632 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3633 x = 0;
3634 }
3635 if (y < 0) {
3636 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3637 y = 0;
3638 }
3639 position->enable = true;
3640 position->x = x;
3641 position->y = y;
3642 position->x_hotspot = xorigin;
3643 position->y_hotspot = yorigin;
3644
3645 return 0;
3646}
3647
3ee6b26b
AD		 3648static void handle_cursor_update(struct drm_plane *plane,
3649 struct drm_plane_state *old_plane_state)
e7b07cee 3650{
2a8f6ccb
HW		 3651 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3652 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3653 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3654 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3655 uint64_t address = afb ? afb->address : 0;
3656 struct dc_cursor_position position;
3657 struct dc_cursor_attributes attributes;
3658 int ret;
3659
e7b07cee
HW		 3660 if (!plane->state->fb && !old_plane_state->fb)
3661 return;
3662
f1ad2f5e
HW		 3663 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
3664 __func__,
3665 amdgpu_crtc->crtc_id,
3666 plane->state->crtc_w,
3667 plane->state->crtc_h);
2a8f6ccb
HW		 3668
3669 ret = get_cursor_position(plane, crtc, &position);
3670 if (ret)
3671 return;
3672
3673 if (!position.enable) {
3674 /* turn off cursor */
3675 if (crtc_state && crtc_state->stream)
3676 dc_stream_set_cursor_position(crtc_state->stream,
3677 &position);
3678 return;
e7b07cee 3679 }
e7b07cee 3680
2a8f6ccb
HW		 3681 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3682 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3683
3684 attributes.address.high_part = upper_32_bits(address);
3685 attributes.address.low_part = lower_32_bits(address);
3686 attributes.width = plane->state->crtc_w;
3687 attributes.height = plane->state->crtc_h;
3688 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3689 attributes.rotation_angle = 0;
3690 attributes.attribute_flags.value = 0;
3691
3692 attributes.pitch = attributes.width;
3693
3694 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3695 &attributes))
3696 DRM_ERROR("DC failed to set cursor attributes\n");
3697
3698 if (crtc_state->stream)
3699 if (!dc_stream_set_cursor_position(crtc_state->stream,
3700 &position))
3701 DRM_ERROR("DC failed to set cursor position\n");
3702}
e7b07cee
HW		 3703
3704static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3705{
3706
3707 assert_spin_locked(&acrtc->base.dev->event_lock);
3708 WARN_ON(acrtc->event);
3709
3710 acrtc->event = acrtc->base.state->event;
3711
3712 /* Set the flip status */
3713 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3714
3715 /* Mark this event as consumed */
3716 acrtc->base.state->event = NULL;
3717
3718 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3719 acrtc->crtc_id);
3720}
3721
3722/*
3723 * Executes flip
3724 *
3725 * Waits on all BO's fences and for proper vblank count
3726 */
3ee6b26b
AD		 3727static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3728 struct drm_framebuffer *fb,
3729 uint32_t target)
e7b07cee
HW		 3730{
3731 unsigned long flags;
3732 uint32_t target_vblank;
3733 int r, vpos, hpos;
3734 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3735 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3736 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3737 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3738 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3739 struct dc_flip_addrs addr = { {0} };
3be5262e 3740 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3741 struct dc_surface_update surface_updates[1] = { {0} };
3742 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3743
3744
3745 /* Prepare wait for target vblank early - before the fence-waits */
3746 target_vblank = target - drm_crtc_vblank_count(crtc) +
3747 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3748
b830ebc9 3749 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3750 * explicitly on fences instead
3751 * and in general should be called for
3752 * blocking commit to as per framework helpers
b830ebc9 3753 */
e7b07cee
HW		 3754 r = amdgpu_bo_reserve(abo, true);
3755 if (unlikely(r != 0)) {
3756 DRM_ERROR("failed to reserve buffer before flip\n");
3757 WARN_ON(1);
3758 }
3759
3760 /* Wait for all fences on this FB */
3761 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3762 MAX_SCHEDULE_TIMEOUT) < 0);
3763
3764 amdgpu_bo_unreserve(abo);
3765
3766 /* Wait until we're out of the vertical blank period before the one
3767 * targeted by the flip
3768 */
3769 while ((acrtc->enabled &&
3770 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3771 &vpos, &hpos, NULL, NULL,
3772 &crtc->hwmode)
3773 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3774 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3775 (int)(target_vblank -
3776 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3777 usleep_range(1000, 1100);
3778 }
3779
3780 /* Flip */
3781 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3782 /* update crtc fb */
3783 crtc->primary->fb = fb;
3784
3785 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3786 WARN_ON(!acrtc_state->stream);
3787
3788 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3789 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3790 addr.flip_immediate = async_flip;
3791
3792
3793 if (acrtc->base.state->event)
3794 prepare_flip_isr(acrtc);
3795
3be5262e 3796 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3797 surface_updates->flip_addr = &addr;
3798
3799
3be5262e 3800 dc_update_planes_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL);
e7b07cee
HW		 3801
3802 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3803 __func__,
3804 addr.address.grph.addr.high_part,
3805 addr.address.grph.addr.low_part);
3806
3807
3808 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3809}
3810
3be5262e 3811static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 3812 struct drm_device *dev,
3813 struct amdgpu_display_manager *dm,
3814 struct drm_crtc *pcrtc,
3815 bool *wait_for_vblank)
e7b07cee
HW		 3816{
3817 uint32_t i;
3818 struct drm_plane *plane;
0bc9706d 3819 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 3820 struct dc_stream_state *dc_stream_attach;
3be5262e 3821 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 3822 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 3823 struct drm_crtc_state *new_pcrtc_state =
3824 drm_atomic_get_new_crtc_state(state, pcrtc);
3825 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
e7b07cee
HW		 3826 int planes_count = 0;
3827 unsigned long flags;
3828
3829 /* update planes when needed */
0bc9706d
LSL		 3830 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3831 struct drm_crtc *crtc = new_plane_state->crtc;
3832 struct drm_crtc_state *new_crtc_state =
3833 drm_atomic_get_new_crtc_state(state, crtc);
3834 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 3835 bool pflip_needed;
54d76575 3836 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 3837
3838 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3839 handle_cursor_update(plane, old_plane_state);
3840 continue;
3841 }
3842
0bc9706d 3843 if (!fb || !crtc || pcrtc != crtc || !new_crtc_state->active)
e7b07cee
HW		 3844 continue;
3845
3846 pflip_needed = !state->allow_modeset;
3847
3848 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3849 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3850 DRM_ERROR("%s: acrtc %d, already busy\n",
3851 __func__,
3852 acrtc_attach->crtc_id);
e7b07cee 3853 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
b830ebc9 3854 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3855 WARN_ON(1);
3856 }
3857 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3858
3859 if (!pflip_needed) {
54d76575 3860 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 3861
54d76575 3862 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 3863
3864 dc_stream_attach = acrtc_state->stream;
3865 planes_count++;
3866
0bc9706d 3867 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 3868 /* Assume even ONE crtc with immediate flip means
3869 * entire can't wait for VBLANK
3870 * TODO Check if it's correct
3871 */
3872 *wait_for_vblank =
0bc9706d 3873 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 3874 false : true;
3875
3876 /* TODO: Needs rework for multiplane flip */
3877 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3878 drm_crtc_vblank_get(crtc);
3879
3880 amdgpu_dm_do_flip(
3881 crtc,
3882 fb,
3883 drm_crtc_vblank_count(crtc) + *wait_for_vblank);
e7b07cee
HW		 3884 }
3885
3886 }
3887
3888 if (planes_count) {
3889 unsigned long flags;
3890
0bc9706d 3891 if (new_pcrtc_state->event) {
e7b07cee
HW		 3892
3893 drm_crtc_vblank_get(pcrtc);
3894
3895 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
3896 prepare_flip_isr(acrtc_attach);
3897 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
3898 }
3899
3be5262e
HW		 3900 if (false == dc_commit_planes_to_stream(dm->dc,
3901 plane_states_constructed,
3902 planes_count,
3903 dc_stream_attach))
3904 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 3905 } else {
3906 /*TODO BUG Here should go disable planes on CRTC. */
3907 }
3908}
3909
3910
7578ecda
AD		 3911static int amdgpu_dm_atomic_commit(struct drm_device *dev,
3912 struct drm_atomic_state *state,
3913 bool nonblock)
e7b07cee
HW		 3914{
3915 struct drm_crtc *crtc;
c2cea706 3916 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 3917 struct amdgpu_device *adev = dev->dev_private;
3918 int i;
3919
3920 /*
3921 * We evade vblanks and pflips on crtc that
3922 * should be changed. We do it here to flush & disable
3923 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
3924 * it will update crtc->dm_crtc_state->stream pointer which is used in
3925 * the ISRs.
3926 */
c2cea706 3927 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 3928 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 3929 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3930
54d76575 3931 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 3932 manage_dm_interrupts(adev, acrtc, false);
3933 }
3934
3935 return drm_atomic_helper_commit(dev, state, nonblock);
3936
3937 /*TODO Handle EINTR, reenable IRQ*/
3938}
3939
7578ecda 3940static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 3941{
3942 struct drm_device *dev = state->dev;
3943 struct amdgpu_device *adev = dev->dev_private;
3944 struct amdgpu_display_manager *dm = &adev->dm;
3945 struct dm_atomic_state *dm_state;
3946 uint32_t i, j;
3947 uint32_t new_crtcs_count = 0;
5cc6dcbd 3948 struct drm_crtc *crtc;
0bc9706d 3949 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee 3950 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
0971c40e 3951 struct dc_stream_state *new_stream = NULL;
e7b07cee
HW		 3952 unsigned long flags;
3953 bool wait_for_vblank = true;
3954 struct drm_connector *connector;
c2cea706 3955 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 3956 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
e7b07cee
HW		 3957
3958 drm_atomic_helper_update_legacy_modeset_state(dev, state);
3959
3960 dm_state = to_dm_atomic_state(state);
3961
3962 /* update changed items */
0bc9706d 3963 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 3964 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 3965
54d76575
LSL		 3966 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
3967 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 3968
f1ad2f5e 3969 DRM_DEBUG_DRIVER(
e7b07cee
HW		 3970 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
3971 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
3972 "connectors_changed:%d\n",
3973 acrtc->crtc_id,
0bc9706d
LSL		 3974 new_crtc_state->enable,
3975 new_crtc_state->active,
3976 new_crtc_state->planes_changed,
3977 new_crtc_state->mode_changed,
3978 new_crtc_state->active_changed,
3979 new_crtc_state->connectors_changed);
e7b07cee
HW		 3980
3981 /* handles headless hotplug case, updating new_state and
3982 * aconnector as needed
3983 */
3984
54d76575 3985 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 3986
f1ad2f5e 3987 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 3988
54d76575 3989 if (!dm_new_crtc_state->stream) {
e7b07cee 3990 /*
b830ebc9
HW		 3991 * this could happen because of issues with
3992 * userspace notifications delivery.
3993 * In this case userspace tries to set mode on
3994 * display which is disconnect in fact.
3995 * dc_sink in NULL in this case on aconnector.
3996 * We expect reset mode will come soon.
3997 *
3998 * This can also happen when unplug is done
3999 * during resume sequence ended
4000 *
4001 * In this case, we want to pretend we still
4002 * have a sink to keep the pipe running so that
4003 * hw state is consistent with the sw state
4004 */
f1ad2f5e 4005 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4006 __func__, acrtc->base.base.id);
4007 continue;
4008 }
4009
4010
54d76575
LSL		 4011 if (dm_old_crtc_state->stream)
4012 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4013
4014
4015 /*
4016 * this loop saves set mode crtcs
4017 * we needed to enable vblanks once all
4018 * resources acquired in dc after dc_commit_streams
4019 */
4020
4021 /*TODO move all this into dm_crtc_state, get rid of
4022 * new_crtcs array and use old and new atomic states
4023 * instead
4024 */
4025 new_crtcs[new_crtcs_count] = acrtc;
4026 new_crtcs_count++;
4027
0bc9706d 4028 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
e7b07cee 4029 acrtc->enabled = true;
0bc9706d
LSL		 4030 acrtc->hw_mode = new_crtc_state->mode;
4031 crtc->hwmode = new_crtc_state->mode;
4032 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4033 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4034
4035 /* i.e. reset mode */
54d76575
LSL		 4036 if (dm_old_crtc_state->stream)
4037 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4038 }
4039 } /* for_each_crtc_in_state() */
4040
4041 /*
4042 * Add streams after required streams from new and replaced streams
4043 * are removed from freesync module
4044 */
4045 if (adev->dm.freesync_module) {
4046 for (i = 0; i < new_crtcs_count; i++) {
c84dec2f 4047 struct amdgpu_dm_connector *aconnector = NULL;
b830ebc9 4048
0bc9706d
LSL		 4049 new_crtc_state = drm_atomic_get_new_crtc_state(state,
4050 &new_crtcs[i]->base);
54d76575 4051 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4052
54d76575 4053 new_stream = dm_new_crtc_state->stream;
1daf8c63 4054 aconnector = amdgpu_dm_find_first_crtc_matching_connector(
e7b07cee 4055 state,
9ba29fcb 4056 &new_crtcs[i]->base);
e7b07cee 4057 if (!aconnector) {
f1ad2f5e 4058 DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d "
b830ebc9
HW		 4059 "skipping freesync init\n",
4060 new_crtcs[i]->crtc_id);
e7b07cee
HW		 4061 continue;
4062 }
4063
4064 mod_freesync_add_stream(adev->dm.freesync_module,
4065 new_stream, &aconnector->caps);
4066 }
4067 }
4068
4069 if (dm_state->context)
608ac7bb 4070 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
e7b07cee 4071
0bc9706d 4072 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4073 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4074
54d76575 4075 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4076
54d76575 4077 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4078 const struct dc_stream_status *status =
54d76575 4079 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4080
4081 if (!status)
54d76575 4082 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4083 else
4084 acrtc->otg_inst = status->primary_otg_inst;
4085 }
4086 }
4087
ebdd27e1 4088 /* Handle scaling and underscan changes*/
c2cea706 4089 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4090 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4091 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4092 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4093 struct dc_stream_status *status = NULL;
4094
0bc9706d
LSL		 4095 if (acrtc)
4096 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4097
e7b07cee 4098 /* Skip any modesets/resets */
0bc9706d 4099 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4100 continue;
4101
4102 /* Skip any thing not scale or underscan changes */
54d76575 4103 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4104 continue;
4105
54d76575 4106 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4107
54d76575
LSL		 4108 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4109 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4110
54d76575 4111 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4112 WARN_ON(!status);
3be5262e 4113 WARN_ON(!status->plane_count);
e7b07cee 4114
54d76575 4115 if (!dm_new_crtc_state->stream)
e7b07cee
HW		 4116 continue;
4117
4118 /*TODO How it works with MPO ?*/
3be5262e 4119 if (!dc_commit_planes_to_stream(
e7b07cee 4120 dm->dc,
3be5262e
HW		 4121 status->plane_states,
4122 status->plane_count,
54d76575 4123 dm_new_crtc_state->stream))
e7b07cee
HW		 4124 dm_error("%s: Failed to update stream scaling!\n", __func__);
4125 }
4126
4127 for (i = 0; i < new_crtcs_count; i++) {
4128 /*
4129 * loop to enable interrupts on newly arrived crtc
4130 */
4131 struct amdgpu_crtc *acrtc = new_crtcs[i];
b830ebc9 4132
0bc9706d 4133 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
54d76575 4134 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 4135
4136 if (adev->dm.freesync_module)
4137 mod_freesync_notify_mode_change(
54d76575 4138 adev->dm.freesync_module, &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4139
4140 manage_dm_interrupts(adev, acrtc, true);
4141 }
4142
4143 /* update planes when needed per crtc*/
5cc6dcbd 4144 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4145 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4146
54d76575 4147 if (dm_new_crtc_state->stream)
5cc6dcbd 4148 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4149 }
4150
4151
4152 /*
4153 * send vblank event on all events not handled in flip and
4154 * mark consumed event for drm_atomic_helper_commit_hw_done
4155 */
4156 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4157 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4158
0bc9706d
LSL		 4159 if (new_crtc_state->event)
4160 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4161
0bc9706d 4162 new_crtc_state->event = NULL;
e7b07cee
HW		 4163 }
4164 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4165
4166 /* Signal HW programming completion */
4167 drm_atomic_helper_commit_hw_done(state);
4168
4169 if (wait_for_vblank)
4170 drm_atomic_helper_wait_for_vblanks(dev, state);
4171
4172 drm_atomic_helper_cleanup_planes(dev, state);
4173}
4174
4175
4176static int dm_force_atomic_commit(struct drm_connector *connector)
4177{
4178 int ret = 0;
4179 struct drm_device *ddev = connector->dev;
4180 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4181 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4182 struct drm_plane *plane = disconnected_acrtc->base.primary;
4183 struct drm_connector_state *conn_state;
4184 struct drm_crtc_state *crtc_state;
4185 struct drm_plane_state *plane_state;
4186
4187 if (!state)
4188 return -ENOMEM;
4189
4190 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4191
4192 /* Construct an atomic state to restore previous display setting */
4193
4194 /*
4195 * Attach connectors to drm_atomic_state
4196 */
4197 conn_state = drm_atomic_get_connector_state(state, connector);
4198
4199 ret = PTR_ERR_OR_ZERO(conn_state);
4200 if (ret)
4201 goto err;
4202
4203 /* Attach crtc to drm_atomic_state*/
4204 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4205
4206 ret = PTR_ERR_OR_ZERO(crtc_state);
4207 if (ret)
4208 goto err;
4209
4210 /* force a restore */
4211 crtc_state->mode_changed = true;
4212
4213 /* Attach plane to drm_atomic_state */
4214 plane_state = drm_atomic_get_plane_state(state, plane);
4215
4216 ret = PTR_ERR_OR_ZERO(plane_state);
4217 if (ret)
4218 goto err;
4219
4220
4221 /* Call commit internally with the state we just constructed */
4222 ret = drm_atomic_commit(state);
4223 if (!ret)
4224 return 0;
4225
4226err:
4227 DRM_ERROR("Restoring old state failed with %i\n", ret);
4228 drm_atomic_state_put(state);
4229
4230 return ret;
4231}
4232
4233/*
4234 * This functions handle all cases when set mode does not come upon hotplug.
4235 * This include when the same display is unplugged then plugged back into the
4236 * same port and when we are running without usermode desktop manager supprot
4237 */
3ee6b26b
AD		 4238void dm_restore_drm_connector_state(struct drm_device *dev,
4239 struct drm_connector *connector)
e7b07cee 4240{
c84dec2f 4241 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4242 struct amdgpu_crtc *disconnected_acrtc;
4243 struct dm_crtc_state *acrtc_state;
4244
4245 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4246 return;
4247
4248 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4249 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4250
4251 if (!disconnected_acrtc || !acrtc_state->stream)
4252 return;
4253
4254 /*
4255 * If the previous sink is not released and different from the current,
4256 * we deduce we are in a state where we can not rely on usermode call
4257 * to turn on the display, so we do it here
4258 */
4259 if (acrtc_state->stream->sink != aconnector->dc_sink)
4260 dm_force_atomic_commit(&aconnector->base);
4261}
4262
e7b07cee
HW		 4263/*`
4264 * Grabs all modesetting locks to serialize against any blocking commits,
4265 * Waits for completion of all non blocking commits.
4266 */
3ee6b26b
AD		 4267static int do_aquire_global_lock(struct drm_device *dev,
4268 struct drm_atomic_state *state)
e7b07cee
HW		 4269{
4270 struct drm_crtc *crtc;
4271 struct drm_crtc_commit *commit;
4272 long ret;
4273
4274 /* Adding all modeset locks to aquire_ctx will
4275 * ensure that when the framework release it the
4276 * extra locks we are locking here will get released to
4277 */
4278 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4279 if (ret)
4280 return ret;
4281
4282 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4283 spin_lock(&crtc->commit_lock);
4284 commit = list_first_entry_or_null(&crtc->commit_list,
4285 struct drm_crtc_commit, commit_entry);
4286 if (commit)
4287 drm_crtc_commit_get(commit);
4288 spin_unlock(&crtc->commit_lock);
4289
4290 if (!commit)
4291 continue;
4292
4293 /* Make sure all pending HW programming completed and
4294 * page flips done
4295 */
4296 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4297
4298 if (ret > 0)
4299 ret = wait_for_completion_interruptible_timeout(
4300 &commit->flip_done, 10*HZ);
4301
4302 if (ret == 0)
4303 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4304 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4305
4306 drm_crtc_commit_put(commit);
4307 }
4308
4309 return ret < 0 ? ret : 0;
4310}
4311
3ee6b26b
AD		 4312static int dm_update_crtcs_state(struct dc *dc,
4313 struct drm_atomic_state *state,
4314 bool enable,
4315 bool *lock_and_validation_needed)
e7b07cee 4316{
e7b07cee 4317 struct drm_crtc *crtc;
c2cea706 4318 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4319 int i;
54d76575 4320 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4321 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4322 struct dc_stream_state *new_stream;
62f55537 4323 int ret = 0;
d4d4a645 4324
62f55537
AG		 4325 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4326 /* update changed items */
c2cea706 4327 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4328 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4329 struct amdgpu_dm_connector *aconnector = NULL;
c2cea706 4330 struct drm_connector_state *new_con_state = NULL;
62f55537 4331 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4332
9635b754
DS		 4333 new_stream = NULL;
4334
54d76575
LSL		 4335 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4336 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4337 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4338
1daf8c63 4339 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4340
62f55537 4341 /* TODO This hack should go away */
2e0ac3d6 4342 if (aconnector) {
c2cea706
LSL		 4343 new_con_state = drm_atomic_get_connector_state(state,
4344 &aconnector->base);
19f89e23 4345
c2cea706
LSL		 4346 if (IS_ERR(new_con_state)) {
4347 ret = PTR_ERR_OR_ZERO(new_con_state);
62f55537
AG		 4348 break;
4349 }
19f89e23 4350
c2cea706 4351 dm_conn_state = to_dm_connector_state(new_con_state);
19f89e23 4352
62f55537 4353 new_stream = create_stream_for_sink(aconnector,
c2cea706 4354 &new_crtc_state->mode,
62f55537 4355 dm_conn_state);
19f89e23 4356
62f55537
AG		 4357 /*
4358 * we can have no stream on ACTION_SET if a display
4359 * was disconnected during S3, in this case it not and
4360 * error, the OS will be updated after detection, and
4361 * do the right thing on next atomic commit
4362 */
19f89e23 4363
62f55537 4364 if (!new_stream) {
f1ad2f5e 4365 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4366 __func__, acrtc->base.base.id);
4367 break;
19f89e23 4368 }
62f55537 4369 }
19f89e23 4370
54d76575 4371 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream)) {
19f89e23 4372
c2cea706 4373 new_crtc_state->mode_changed = false;
e7b07cee 4374
c2cea706
LSL		 4375 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4376 new_crtc_state->mode_changed);
62f55537 4377 }
b830ebc9 4378
e7b07cee 4379
c2cea706 4380 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4381 goto next_crtc;
e7b07cee 4382
f1ad2f5e 4383 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4384 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4385 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4386 "connectors_changed:%d\n",
4387 acrtc->crtc_id,
c2cea706
LSL		 4388 new_crtc_state->enable,
4389 new_crtc_state->active,
4390 new_crtc_state->planes_changed,
4391 new_crtc_state->mode_changed,
4392 new_crtc_state->active_changed,
4393 new_crtc_state->connectors_changed);
e7b07cee 4394
62f55537
AG		 4395 /* Remove stream for any changed/disabled CRTC */
4396 if (!enable) {
4397
54d76575 4398 if (!dm_old_crtc_state->stream)
9635b754 4399 goto next_crtc;
62f55537 4400
f1ad2f5e 4401 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4402 crtc->base.id);
e7b07cee 4403
1dc90497 4404 /* i.e. reset mode */
62f55537
AG		 4405 if (!dc_remove_stream_from_ctx(
4406 dc,
4407 dm_state->context,
54d76575 4408 dm_old_crtc_state->stream)) {
62f55537 4409 ret = -EINVAL;
9635b754 4410 goto fail;
62f55537
AG		 4411 }
4412
54d76575
LSL		 4413 dc_stream_release(dm_old_crtc_state->stream);
4414 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4415
4416 *lock_and_validation_needed = true;
4417
4418 } else {/* Add stream for any updated/enabled CRTC */
4419
c2cea706 4420 if (modereset_required(new_crtc_state))
9635b754 4421 goto next_crtc;
62f55537 4422
c2cea706 4423 if (modeset_required(new_crtc_state, new_stream,
54d76575 4424 dm_old_crtc_state->stream)) {
62f55537 4425
54d76575 4426 WARN_ON(dm_new_crtc_state->stream);
62f55537 4427
54d76575 4428 dm_new_crtc_state->stream = new_stream;
62f55537
AG		 4429 dc_stream_retain(new_stream);
4430
f1ad2f5e 4431 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4432 crtc->base.id);
1dc90497 4433
62f55537 4434 if (!dc_add_stream_to_ctx(
1dc90497
AG		 4435 dc,
4436 dm_state->context,
54d76575 4437 dm_new_crtc_state->stream)) {
1dc90497 4438 ret = -EINVAL;
9635b754 4439 goto fail;
1dc90497
AG		 4440 }
4441
62f55537 4442 *lock_and_validation_needed = true;
9b690ef3 4443 }
62f55537 4444 }
9b690ef3 4445
9635b754 4446next_crtc:
62f55537
AG		 4447 /* Release extra reference */
4448 if (new_stream)
4449 dc_stream_release(new_stream);
4450 }
e7b07cee 4451
62f55537 4452 return ret;
9635b754
DS		 4453
4454fail:
4455 if (new_stream)
4456 dc_stream_release(new_stream);
4457 return ret;
62f55537 4458}
9b690ef3 4459
3ee6b26b
AD		 4460static int dm_update_planes_state(struct dc *dc,
4461 struct drm_atomic_state *state,
4462 bool enable,
4463 bool *lock_and_validation_needed)
62f55537
AG		 4464{
4465 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4466 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4467 struct drm_plane *plane;
4468 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4469 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4470 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4471 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4472 int i ;
4473 /* TODO return page_flip_needed() function */
4474 bool pflip_needed = !state->allow_modeset;
4475 int ret = 0;
e7b07cee 4476
62f55537
AG		 4477 if (pflip_needed)
4478 return ret;
9b690ef3 4479
62f55537
AG		 4480 /* Add new planes */
4481 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4482 new_plane_crtc = new_plane_state->crtc;
4483 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4484 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4485 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4486
4487 /*TODO Implement atomic check for cursor plane */
4488 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4489 continue;
9b690ef3 4490
62f55537
AG		 4491 /* Remove any changed/removed planes */
4492 if (!enable) {
a7b06724 4493
62f55537
AG		 4494 if (!old_plane_crtc)
4495 continue;
4496
0bc9706d
LSL		 4497 old_crtc_state = drm_atomic_get_old_crtc_state(
4498 state, old_plane_crtc);
54d76575 4499 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4500
54d76575 4501 if (!dm_old_crtc_state->stream)
62f55537
AG		 4502 continue;
4503
f1ad2f5e 4504 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4505 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4506
62f55537
AG		 4507 if (!dc_remove_plane_from_context(
4508 dc,
54d76575
LSL		 4509 dm_old_crtc_state->stream,
4510 dm_old_plane_state->dc_state,
62f55537
AG		 4511 dm_state->context)) {
4512
4513 ret = EINVAL;
4514 return ret;
e7b07cee
HW		 4515 }
4516
9b690ef3 4517
54d76575
LSL		 4518 dc_plane_state_release(dm_old_plane_state->dc_state);
4519 dm_new_plane_state->dc_state = NULL;
1dc90497 4520
62f55537 4521 *lock_and_validation_needed = true;
1dc90497 4522
62f55537 4523 } else { /* Add new planes */
1dc90497 4524
62f55537
AG		 4525 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4526 continue;
e7b07cee 4527
62f55537
AG		 4528 if (!new_plane_crtc)
4529 continue;
e7b07cee 4530
62f55537 4531 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4532 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4533
54d76575 4534 if (!dm_new_crtc_state->stream)
62f55537
AG		 4535 continue;
4536
4537
54d76575 4538 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4539
54d76575 4540 dm_new_plane_state->dc_state = dc_create_plane_state(dc);
62f55537 4541
f1ad2f5e 4542 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
62f55537
AG		 4543 plane->base.id, new_plane_crtc->base.id);
4544
54d76575 4545 if (!dm_new_plane_state->dc_state) {
62f55537
AG		 4546 ret = -EINVAL;
4547 return ret;
4548 }
4549
4550 ret = fill_plane_attributes(
4551 new_plane_crtc->dev->dev_private,
54d76575 4552 dm_new_plane_state->dc_state,
62f55537
AG		 4553 new_plane_state,
4554 new_crtc_state,
4555 false);
4556 if (ret)
4557 return ret;
4558
4559
4560 if (!dc_add_plane_to_context(
4561 dc,
54d76575
LSL		 4562 dm_new_crtc_state->stream,
4563 dm_new_plane_state->dc_state,
62f55537
AG		 4564 dm_state->context)) {
4565
4566 ret = -EINVAL;
4567 return ret;
e7b07cee 4568 }
62f55537
AG		 4569
4570 *lock_and_validation_needed = true;
e7b07cee 4571 }
62f55537 4572 }
e7b07cee
HW		 4573
4574
62f55537
AG		 4575 return ret;
4576}
4577
7578ecda
AD		 4578static int amdgpu_dm_atomic_check(struct drm_device *dev,
4579 struct drm_atomic_state *state)
62f55537
AG		 4580{
4581 int i;
4582 int ret;
4583 struct amdgpu_device *adev = dev->dev_private;
4584 struct dc *dc = adev->dm.dc;
4585 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4586 struct drm_connector *connector;
c2cea706 4587 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4588 struct drm_crtc *crtc;
c2cea706 4589 struct drm_crtc_state *new_crtc_state;
e7b07cee 4590
62f55537
AG		 4591 /*
4592 * This bool will be set for true for any modeset/reset
4593 * or plane update which implies non fast surface update.
4594 */
4595 bool lock_and_validation_needed = false;
4596
4597 ret = drm_atomic_helper_check_modeset(dev, state);
4598
4599 if (ret) {
4600 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret);
4601 return ret;
4602 }
4603
4604 /*
4605 * Hack: Commit needs planes right now, specifically for gamma
4606 * TODO rework commit to check CRTC for gamma change
4607 */
c2cea706
LSL		 4608 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4609 if (new_crtc_state->color_mgmt_changed) {
e7b07cee
HW		 4610 ret = drm_atomic_add_affected_planes(state, crtc);
4611 if (ret)
4612 goto fail;
4613 }
4614 }
4615
62f55537
AG		 4616 dm_state->context = dc_create_state();
4617 ASSERT(dm_state->context);
f36cc577 4618 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4619
4620 /* Remove exiting planes if they are modified */
4621 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4622 if (ret) {
4623 goto fail;
4624 }
4625
4626 /* Disable all crtcs which require disable */
4627 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4628 if (ret) {
4629 goto fail;
4630 }
4631
4632 /* Enable all crtcs which require enable */
4633 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4634 if (ret) {
4635 goto fail;
4636 }
4637
4638 /* Add new/modified planes */
4639 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4640 if (ret) {
4641 goto fail;
4642 }
4643
4644 /* Run this here since we want to validate the streams we created */
4645 ret = drm_atomic_helper_check_planes(dev, state);
4646 if (ret)
4647 goto fail;
4648
ebdd27e1 4649 /* Check scaling and underscan changes*/
e7b07cee
HW		 4650 /*TODO Removed scaling changes validation due to inability to commit
4651 * new stream into context w\o causing full reset. Need to
4652 * decide how to handle.
4653 */
c2cea706 4654 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4655 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4656 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4657 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4658
4659 /* Skip any modesets/resets */
0bc9706d
LSL		 4660 if (!acrtc || drm_atomic_crtc_needs_modeset(
4661 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 4662 continue;
4663
b830ebc9 4664 /* Skip any thing not scale or underscan changes */
54d76575 4665 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4666 continue;
4667
4668 lock_and_validation_needed = true;
4669 }
4670
e7b07cee
HW		 4671 /*
4672 * For full updates case when
4673 * removing/adding/updating streams on once CRTC while flipping
4674 * on another CRTC,
4675 * acquiring global lock will guarantee that any such full
4676 * update commit
4677 * will wait for completion of any outstanding flip using DRMs
4678 * synchronization events.
4679 */
4680
4681 if (lock_and_validation_needed) {
4682
4683 ret = do_aquire_global_lock(dev, state);
4684 if (ret)
4685 goto fail;
1dc90497 4686
19f89e23 4687 if (!dc_validate_global_state(dc, dm_state->context)) {
e7b07cee
HW		 4688 ret = -EINVAL;
4689 goto fail;
4690 }
4691 }
4692
4693 /* Must be success */
4694 WARN_ON(ret);
4695 return ret;
4696
4697fail:
4698 if (ret == -EDEADLK)
f1ad2f5e 4699 DRM_DEBUG_DRIVER("Atomic check stopped due to to deadlock.\n");
e7b07cee 4700 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
f1ad2f5e 4701 DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n");
e7b07cee 4702 else
62f55537 4703 DRM_ERROR("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 4704
4705 return ret;
4706}
4707
3ee6b26b
AD		 4708static bool is_dp_capable_without_timing_msa(struct dc *dc,
4709 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 4710{
4711 uint8_t dpcd_data;
4712 bool capable = false;
4713
c84dec2f 4714 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 4715 dm_helpers_dp_read_dpcd(
4716 NULL,
c84dec2f 4717 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 4718 DP_DOWN_STREAM_PORT_COUNT,
4719 &dpcd_data,
4720 sizeof(dpcd_data))) {
4721 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4722 }
4723
4724 return capable;
4725}
3ee6b26b
AD		 4726void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4727 struct edid *edid)
e7b07cee
HW		 4728{
4729 int i;
4730 uint64_t val_capable;
4731 bool edid_check_required;
4732 struct detailed_timing *timing;
4733 struct detailed_non_pixel *data;
4734 struct detailed_data_monitor_range *range;
c84dec2f
HW		 4735 struct amdgpu_dm_connector *amdgpu_dm_connector =
4736 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4737
4738 struct drm_device *dev = connector->dev;
4739 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4740
e7b07cee 4741 edid_check_required = false;
c84dec2f 4742 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 4743 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4744 return;
4745 }
4746 if (!adev->dm.freesync_module)
4747 return;
4748 /*
4749 * if edid non zero restrict freesync only for dp and edp
4750 */
4751 if (edid) {
c84dec2f
HW		 4752 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4753 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 4754 edid_check_required = is_dp_capable_without_timing_msa(
4755 adev->dm.dc,
c84dec2f 4756 amdgpu_dm_connector);
e7b07cee
HW		 4757 }
4758 }
4759 val_capable = 0;
4760 if (edid_check_required == true && (edid->version > 1 ||
4761 (edid->version == 1 && edid->revision > 1))) {
4762 for (i = 0; i < 4; i++) {
4763
4764 timing = &edid->detailed_timings[i];
4765 data = &timing->data.other_data;
4766 range = &data->data.range;
4767 /*
4768 * Check if monitor has continuous frequency mode
4769 */
4770 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4771 continue;
4772 /*
4773 * Check for flag range limits only. If flag == 1 then
4774 * no additional timing information provided.
4775 * Default GTF, GTF Secondary curve and CVT are not
4776 * supported
4777 */
4778 if (range->flags != 1)
4779 continue;
4780
c84dec2f
HW		 4781 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
4782 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
4783 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 4784 range->pixel_clock_mhz * 10;
4785 break;
4786 }
4787
c84dec2f
HW		 4788 if (amdgpu_dm_connector->max_vfreq -
4789 amdgpu_dm_connector->min_vfreq > 10) {
4790 amdgpu_dm_connector->caps.supported = true;
4791 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
4792 amdgpu_dm_connector->min_vfreq * 1000000;
4793 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
4794 amdgpu_dm_connector->max_vfreq * 1000000;
e7b07cee
HW		 4795 val_capable = 1;
4796 }
4797 }
4798
4799 /*
4800 * TODO figure out how to notify user-mode or DRM of freesync caps
4801 * once we figure out how to deal with freesync in an upstreamable
4802 * fashion
4803 */
4804
4805}
4806
3ee6b26b 4807void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 4808{
4809 /*
4810 * TODO fill in once we figure out how to deal with freesync in
4811 * an upstreamable fashion
4812 */
4813}
Linux 6.x block layer and io_uring tree(s)