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drm/radeon: Do not evict VRAM on APUs with disabled HIBERNATE
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 42#if defined(CONFIG_DEBUG_FS)
43#include "amdgpu_dm_debugfs.h"
44#endif
4562236b
HW		 45
46#include "ivsrcid/ivsrcid_vislands30.h"
47
48#include <linux/module.h>
49#include <linux/moduleparam.h>
50#include <linux/version.h>
e7b07cee 51#include <linux/types.h>
97028037 52#include <linux/pm_runtime.h>
4562236b 53
e7b07cee 54#include <drm/drmP.h>
4562236b
HW		 55#include <drm/drm_atomic.h>
56#include <drm/drm_atomic_helper.h>
57#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 58#include <drm/drm_fb_helper.h>
59#include <drm/drm_edid.h>
4562236b 60
dc37a9a0 61#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 62#include "ivsrcid/irqsrcs_dcn_1_0.h"
63
ad941f7a
FX		 64#include "dcn/dcn_1_0_offset.h"
65#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 66#include "soc15_hw_ip.h"
67#include "vega10_ip_offset.h"
ff5ef992
AD		 68
69#include "soc15_common.h"
70#endif
71
e7b07cee
HW		 72#include "modules/inc/mod_freesync.h"
73
74#include "i2caux_interface.h"
75
7578ecda
AD		 76/* basic init/fini API */
77static int amdgpu_dm_init(struct amdgpu_device *adev);
78static void amdgpu_dm_fini(struct amdgpu_device *adev);
79
80/* initializes drm_device display related structures, based on the information
81 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
82 * drm_encoder, drm_mode_config
83 *
84 * Returns 0 on success
85 */
86static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
87/* removes and deallocates the drm structures, created by the above function */
88static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
89
90static void
91amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
92
93static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
94 struct amdgpu_plane *aplane,
95 unsigned long possible_crtcs);
96static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
97 struct drm_plane *plane,
98 uint32_t link_index);
99static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
100 struct amdgpu_dm_connector *amdgpu_dm_connector,
101 uint32_t link_index,
102 struct amdgpu_encoder *amdgpu_encoder);
103static int amdgpu_dm_encoder_init(struct drm_device *dev,
104 struct amdgpu_encoder *aencoder,
105 uint32_t link_index);
106
107static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
108
109static int amdgpu_dm_atomic_commit(struct drm_device *dev,
110 struct drm_atomic_state *state,
111 bool nonblock);
112
113static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
114
115static int amdgpu_dm_atomic_check(struct drm_device *dev,
116 struct drm_atomic_state *state);
117
118
119
e7b07cee 120
e04a6123 121static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125 DRM_PLANE_TYPE_PRIMARY,
126 DRM_PLANE_TYPE_PRIMARY,
127 DRM_PLANE_TYPE_PRIMARY,
128};
129
e04a6123 130static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 131 DRM_PLANE_TYPE_PRIMARY,
132 DRM_PLANE_TYPE_PRIMARY,
133 DRM_PLANE_TYPE_PRIMARY,
134 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
135};
136
e04a6123 137static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 138 DRM_PLANE_TYPE_PRIMARY,
139 DRM_PLANE_TYPE_PRIMARY,
140 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
141};
142
4562236b
HW		 143/*
144 * dm_vblank_get_counter
145 *
146 * @brief
147 * Get counter for number of vertical blanks
148 *
149 * @param
150 * struct amdgpu_device *adev - [in] desired amdgpu device
151 * int disp_idx - [in] which CRTC to get the counter from
152 *
153 * @return
154 * Counter for vertical blanks
155 */
156static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
157{
158 if (crtc >= adev->mode_info.num_crtc)
159 return 0;
160 else {
161 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 162 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
163 acrtc->base.state);
4562236b 164
da5c47f6
AG		 165
166 if (acrtc_state->stream == NULL) {
0971c40e
HW		 167 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
168 crtc);
4562236b
HW		 169 return 0;
170 }
171
da5c47f6 172 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 173 }
174}
175
176static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 177 u32 *vbl, u32 *position)
4562236b 178{
81c50963
ST		 179 uint32_t v_blank_start, v_blank_end, h_position, v_position;
180
4562236b
HW		 181 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
182 return -EINVAL;
183 else {
184 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 185 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
186 acrtc->base.state);
4562236b 187
da5c47f6 188 if (acrtc_state->stream == NULL) {
0971c40e
HW		 189 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
190 crtc);
4562236b
HW		 191 return 0;
192 }
193
81c50963
ST		 194 /*
195 * TODO rework base driver to use values directly.
196 * for now parse it back into reg-format
197 */
da5c47f6 198 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 199 &v_blank_start,
200 &v_blank_end,
201 &h_position,
202 &v_position);
203
e806208d
AG		 204 *position = v_position | (h_position << 16);
205 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 206 }
207
208 return 0;
209}
210
211static bool dm_is_idle(void *handle)
212{
213 /* XXX todo */
214 return true;
215}
216
217static int dm_wait_for_idle(void *handle)
218{
219 /* XXX todo */
220 return 0;
221}
222
223static bool dm_check_soft_reset(void *handle)
224{
225 return false;
226}
227
228static int dm_soft_reset(void *handle)
229{
230 /* XXX todo */
231 return 0;
232}
233
3ee6b26b
AD		 234static struct amdgpu_crtc *
235get_crtc_by_otg_inst(struct amdgpu_device *adev,
236 int otg_inst)
4562236b
HW		 237{
238 struct drm_device *dev = adev->ddev;
239 struct drm_crtc *crtc;
240 struct amdgpu_crtc *amdgpu_crtc;
241
242 /*
243 * following if is check inherited from both functions where this one is
244 * used now. Need to be checked why it could happen.
245 */
246 if (otg_inst == -1) {
247 WARN_ON(1);
248 return adev->mode_info.crtcs[0];
249 }
250
251 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
252 amdgpu_crtc = to_amdgpu_crtc(crtc);
253
254 if (amdgpu_crtc->otg_inst == otg_inst)
255 return amdgpu_crtc;
256 }
257
258 return NULL;
259}
260
261static void dm_pflip_high_irq(void *interrupt_params)
262{
4562236b
HW		 263 struct amdgpu_crtc *amdgpu_crtc;
264 struct common_irq_params *irq_params = interrupt_params;
265 struct amdgpu_device *adev = irq_params->adev;
266 unsigned long flags;
267
268 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
269
270 /* IRQ could occur when in initial stage */
271 /*TODO work and BO cleanup */
272 if (amdgpu_crtc == NULL) {
273 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
274 return;
275 }
276
277 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 278
279 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
280 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
281 amdgpu_crtc->pflip_status,
282 AMDGPU_FLIP_SUBMITTED,
283 amdgpu_crtc->crtc_id,
284 amdgpu_crtc);
285 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
286 return;
287 }
288
4562236b
HW		 289
290 /* wakeup usersapce */
1159898a 291 if (amdgpu_crtc->event) {
753c66c9
MK		 292 /* Update to correct count/ts if racing with vblank irq */
293 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
294
54f5499a 295 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 296
54f5499a
AG		 297 /* page flip completed. clean up */
298 amdgpu_crtc->event = NULL;
1159898a 299
54f5499a
AG		 300 } else
301 WARN_ON(1);
4562236b 302
54f5499a 303 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 304 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
305
54f5499a
AG		 306 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
307 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 308
309 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 310}
311
312static void dm_crtc_high_irq(void *interrupt_params)
313{
314 struct common_irq_params *irq_params = interrupt_params;
315 struct amdgpu_device *adev = irq_params->adev;
316 uint8_t crtc_index = 0;
317 struct amdgpu_crtc *acrtc;
318
b57de80a 319 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 320
321 if (acrtc)
322 crtc_index = acrtc->crtc_id;
323
324 drm_handle_vblank(adev->ddev, crtc_index);
31aec354 325 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
4562236b
HW		 326}
327
328static int dm_set_clockgating_state(void *handle,
329 enum amd_clockgating_state state)
330{
331 return 0;
332}
333
334static int dm_set_powergating_state(void *handle,
335 enum amd_powergating_state state)
336{
337 return 0;
338}
339
340/* Prototypes of private functions */
341static int dm_early_init(void* handle);
342
343static void hotplug_notify_work_func(struct work_struct *work)
344{
345 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
346 struct drm_device *dev = dm->ddev;
347
348 drm_kms_helper_hotplug_event(dev);
349}
350
a32e24b4 351/* Allocate memory for FBC compressed data */
3e332d3a 352static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 353{
3e332d3a
RL		 354 struct drm_device *dev = connector->dev;
355 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 356 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 357 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
358 struct drm_display_mode *mode;
42e67c3b
RL		 359 unsigned long max_size = 0;
360
361 if (adev->dm.dc->fbc_compressor == NULL)
362 return;
a32e24b4 363
3e332d3a 364 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 365 return;
366
3e332d3a
RL		 367 if (compressor->bo_ptr)
368 return;
42e67c3b 369
42e67c3b 370
3e332d3a
RL		 371 list_for_each_entry(mode, &connector->modes, head) {
372 if (max_size < mode->htotal * mode->vtotal)
373 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 374 }
375
376 if (max_size) {
377 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 378 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 379 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 380
381 if (r)
42e67c3b
RL		 382 DRM_ERROR("DM: Failed to initialize FBC\n");
383 else {
384 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
385 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
386 }
387
a32e24b4
RL		 388 }
389
390}
a32e24b4
RL		 391
392
4562236b
HW		 393/* Init display KMS
394 *
395 * Returns 0 on success
396 */
7578ecda 397static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 398{
399 struct dc_init_data init_data;
400 adev->dm.ddev = adev->ddev;
401 adev->dm.adev = adev;
402
4562236b
HW		 403 /* Zero all the fields */
404 memset(&init_data, 0, sizeof(init_data));
405
4562236b
HW		 406 if(amdgpu_dm_irq_init(adev)) {
407 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
408 goto error;
409 }
410
411 init_data.asic_id.chip_family = adev->family;
412
413 init_data.asic_id.pci_revision_id = adev->rev_id;
414 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
415
770d13b1 416 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 417 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
418 init_data.asic_id.atombios_base_address =
419 adev->mode_info.atom_context->bios;
420
421 init_data.driver = adev;
422
423 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
424
425 if (!adev->dm.cgs_device) {
426 DRM_ERROR("amdgpu: failed to create cgs device.\n");
427 goto error;
428 }
429
430 init_data.cgs_device = adev->dm.cgs_device;
431
432 adev->dm.dal = NULL;
433
434 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
435
6e227308
HW		 436 /*
437 * TODO debug why this doesn't work on Raven
438 */
439 if (adev->flags & AMD_IS_APU &&
440 adev->asic_type >= CHIP_CARRIZO &&
441 adev->asic_type < CHIP_RAVEN)
442 init_data.flags.gpu_vm_support = true;
443
4562236b
HW		 444 /* Display Core create. */
445 adev->dm.dc = dc_create(&init_data);
446
423788c7 447 if (adev->dm.dc) {
76121231 448 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 449 } else {
76121231 450 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 451 goto error;
452 }
4562236b
HW		 453
454 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
455
456 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
457 if (!adev->dm.freesync_module) {
458 DRM_ERROR(
459 "amdgpu: failed to initialize freesync_module.\n");
460 } else
f1ad2f5e 461 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 462 adev->dm.freesync_module);
463
e277adc5
LSL		 464 amdgpu_dm_init_color_mod();
465
4562236b
HW		 466 if (amdgpu_dm_initialize_drm_device(adev)) {
467 DRM_ERROR(
468 "amdgpu: failed to initialize sw for display support.\n");
469 goto error;
470 }
471
472 /* Update the actual used number of crtc */
473 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
474
475 /* TODO: Add_display_info? */
476
477 /* TODO use dynamic cursor width */
ce75805e
AG		 478 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
479 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 480
481 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
482 DRM_ERROR(
483 "amdgpu: failed to initialize sw for display support.\n");
484 goto error;
485 }
486
f1ad2f5e 487 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 488
489 return 0;
490error:
491 amdgpu_dm_fini(adev);
492
493 return -1;
494}
495
7578ecda 496static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 497{
498 amdgpu_dm_destroy_drm_device(&adev->dm);
499 /*
500 * TODO: pageflip, vlank interrupt
501 *
502 * amdgpu_dm_irq_fini(adev);
503 */
504
505 if (adev->dm.cgs_device) {
506 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
507 adev->dm.cgs_device = NULL;
508 }
509 if (adev->dm.freesync_module) {
510 mod_freesync_destroy(adev->dm.freesync_module);
511 adev->dm.freesync_module = NULL;
512 }
513 /* DC Destroy TODO: Replace destroy DAL */
21de3396 514 if (adev->dm.dc)
4562236b 515 dc_destroy(&adev->dm.dc);
4562236b
HW		 516 return;
517}
518
4562236b
HW		 519static int dm_sw_init(void *handle)
520{
521 return 0;
522}
523
524static int dm_sw_fini(void *handle)
525{
526 return 0;
527}
528
7abcf6b5 529static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 530{
c84dec2f 531 struct amdgpu_dm_connector *aconnector;
4562236b 532 struct drm_connector *connector;
7abcf6b5 533 int ret = 0;
4562236b
HW		 534
535 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
536
537 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 538 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 539 if (aconnector->dc_link->type == dc_connection_mst_branch &&
540 aconnector->mst_mgr.aux) {
f1ad2f5e 541 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 542 aconnector, aconnector->base.base.id);
543
544 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
545 if (ret < 0) {
546 DRM_ERROR("DM_MST: Failed to start MST\n");
547 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
548 return ret;
4562236b 549 }
7abcf6b5 550 }
4562236b
HW		 551 }
552
553 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 554 return ret;
555}
556
557static int dm_late_init(void *handle)
558{
42e67c3b 559 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 560
42e67c3b 561 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 562}
563
564static void s3_handle_mst(struct drm_device *dev, bool suspend)
565{
c84dec2f 566 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 567 struct drm_connector *connector;
568
569 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
570
571 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 572 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 573 if (aconnector->dc_link->type == dc_connection_mst_branch &&
574 !aconnector->mst_port) {
575
576 if (suspend)
577 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
578 else
579 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
580 }
581 }
582
583 drm_modeset_unlock(&dev->mode_config.connection_mutex);
584}
585
586static int dm_hw_init(void *handle)
587{
588 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
589 /* Create DAL display manager */
590 amdgpu_dm_init(adev);
4562236b
HW		 591 amdgpu_dm_hpd_init(adev);
592
4562236b
HW		 593 return 0;
594}
595
596static int dm_hw_fini(void *handle)
597{
598 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
599
600 amdgpu_dm_hpd_fini(adev);
601
602 amdgpu_dm_irq_fini(adev);
21de3396 603 amdgpu_dm_fini(adev);
4562236b
HW		 604 return 0;
605}
606
607static int dm_suspend(void *handle)
608{
609 struct amdgpu_device *adev = handle;
610 struct amdgpu_display_manager *dm = &adev->dm;
611 int ret = 0;
4562236b
HW		 612
613 s3_handle_mst(adev->ddev, true);
614
4562236b
HW		 615 amdgpu_dm_irq_suspend(adev);
616
0a214e2f 617 WARN_ON(adev->dm.cached_state);
a3621485
AG		 618 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
619
32f5062d 620 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 621
622 return ret;
623}
624
1daf8c63
AD		 625static struct amdgpu_dm_connector *
626amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
627 struct drm_crtc *crtc)
4562236b
HW		 628{
629 uint32_t i;
c2cea706 630 struct drm_connector_state *new_con_state;
4562236b
HW		 631 struct drm_connector *connector;
632 struct drm_crtc *crtc_from_state;
633
c2cea706
LSL		 634 for_each_new_connector_in_state(state, connector, new_con_state, i) {
635 crtc_from_state = new_con_state->crtc;
4562236b
HW		 636
637 if (crtc_from_state == crtc)
c84dec2f 638 return to_amdgpu_dm_connector(connector);
4562236b
HW		 639 }
640
641 return NULL;
642}
643
4562236b
HW		 644static int dm_resume(void *handle)
645{
646 struct amdgpu_device *adev = handle;
4562236b
HW		 647 struct drm_device *ddev = adev->ddev;
648 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 649 struct amdgpu_dm_connector *aconnector;
4562236b 650 struct drm_connector *connector;
4562236b 651 struct drm_crtc *crtc;
c2cea706 652 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 653 struct dm_crtc_state *dm_new_crtc_state;
654 struct drm_plane *plane;
655 struct drm_plane_state *new_plane_state;
656 struct dm_plane_state *dm_new_plane_state;
a80aa93d 657 int ret;
a3621485 658 int i;
4562236b 659
a80aa93d
ML		 660 /* power on hardware */
661 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
662
4562236b
HW		 663 /* program HPD filter */
664 dc_resume(dm->dc);
665
666 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
667 s3_handle_mst(ddev, false);
668
669 /*
670 * early enable HPD Rx IRQ, should be done before set mode as short
671 * pulse interrupts are used for MST
672 */
673 amdgpu_dm_irq_resume_early(adev);
674
4562236b 675 /* Do detection*/
a80aa93d 676 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 677 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 678
679 /*
680 * this is the case when traversing through already created
681 * MST connectors, should be skipped
682 */
683 if (aconnector->mst_port)
684 continue;
685
03ea364c 686 mutex_lock(&aconnector->hpd_lock);
8f38b66c 687 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 688
689 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
690 aconnector->fake_enable = false;
691
4562236b
HW		 692 aconnector->dc_sink = NULL;
693 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 694 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 695 }
696
a3621485 697 /* Force mode set in atomic comit */
a80aa93d 698 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 699 new_crtc_state->active_changed = true;
4f346e65 700
fcb4019e
LSL		 701 /*
702 * atomic_check is expected to create the dc states. We need to release
703 * them here, since they were duplicated as part of the suspend
704 * procedure.
705 */
a80aa93d 706 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 707 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
708 if (dm_new_crtc_state->stream) {
709 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
710 dc_stream_release(dm_new_crtc_state->stream);
711 dm_new_crtc_state->stream = NULL;
712 }
713 }
714
a80aa93d 715 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 716 dm_new_plane_state = to_dm_plane_state(new_plane_state);
717 if (dm_new_plane_state->dc_state) {
718 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
719 dc_plane_state_release(dm_new_plane_state->dc_state);
720 dm_new_plane_state->dc_state = NULL;
721 }
722 }
723
a80aa93d 724 ret = drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 725
a80aa93d 726 dm->cached_state = NULL;
0a214e2f 727
9faa4237 728 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 729
730 return ret;
731}
732
733static const struct amd_ip_funcs amdgpu_dm_funcs = {
734 .name = "dm",
735 .early_init = dm_early_init,
7abcf6b5 736 .late_init = dm_late_init,
4562236b
HW		 737 .sw_init = dm_sw_init,
738 .sw_fini = dm_sw_fini,
739 .hw_init = dm_hw_init,
740 .hw_fini = dm_hw_fini,
741 .suspend = dm_suspend,
742 .resume = dm_resume,
743 .is_idle = dm_is_idle,
744 .wait_for_idle = dm_wait_for_idle,
745 .check_soft_reset = dm_check_soft_reset,
746 .soft_reset = dm_soft_reset,
747 .set_clockgating_state = dm_set_clockgating_state,
748 .set_powergating_state = dm_set_powergating_state,
749};
750
751const struct amdgpu_ip_block_version dm_ip_block =
752{
753 .type = AMD_IP_BLOCK_TYPE_DCE,
754 .major = 1,
755 .minor = 0,
756 .rev = 0,
757 .funcs = &amdgpu_dm_funcs,
758};
759
ca3268c4 760
7578ecda 761static struct drm_atomic_state *
ca3268c4
HW		 762dm_atomic_state_alloc(struct drm_device *dev)
763{
764 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
765
1dc90497 766 if (!state)
ca3268c4 767 return NULL;
1dc90497
AG		 768
769 if (drm_atomic_state_init(dev, &state->base) < 0)
770 goto fail;
771
ca3268c4 772 return &state->base;
1dc90497
AG		 773
774fail:
775 kfree(state);
776 return NULL;
ca3268c4
HW		 777}
778
0a323b84
AG		 779static void
780dm_atomic_state_clear(struct drm_atomic_state *state)
781{
782 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
783
784 if (dm_state->context) {
608ac7bb 785 dc_release_state(dm_state->context);
0a323b84
AG		 786 dm_state->context = NULL;
787 }
788
789 drm_atomic_state_default_clear(state);
790}
791
792static void
793dm_atomic_state_alloc_free(struct drm_atomic_state *state)
794{
795 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
796 drm_atomic_state_default_release(state);
797 kfree(dm_state);
798}
799
b3663f70 800static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 801 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 802 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 803 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 804 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 805 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 806 .atomic_state_clear = dm_atomic_state_clear,
807 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 808};
809
810static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
811 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 812};
813
7578ecda 814static void
3ee6b26b 815amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 816{
817 struct drm_connector *connector = &aconnector->base;
818 struct drm_device *dev = connector->dev;
b73a22d3 819 struct dc_sink *sink;
4562236b
HW		 820
821 /* MST handled by drm_mst framework */
822 if (aconnector->mst_mgr.mst_state == true)
823 return;
824
825
826 sink = aconnector->dc_link->local_sink;
827
828 /* Edid mgmt connector gets first update only in mode_valid hook and then
829 * the connector sink is set to either fake or physical sink depends on link status.
830 * don't do it here if u are during boot
831 */
832 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
833 && aconnector->dc_em_sink) {
834
ab2541b6 835 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 836 * because on resume connecotr->sink is set ti NULL
837 */
838 mutex_lock(&dev->mode_config.mutex);
839
840 if (sink) {
922aa1e1 841 if (aconnector->dc_sink) {
98e6436d 842 amdgpu_dm_update_freesync_caps(connector, NULL);
922aa1e1
AG		 843 /* retain and release bellow are used for
844 * bump up refcount for sink because the link don't point
845 * to it anymore after disconnect so on next crtc to connector
846 * reshuffle by UMD we will get into unwanted dc_sink release
847 */
848 if (aconnector->dc_sink != aconnector->dc_em_sink)
849 dc_sink_release(aconnector->dc_sink);
850 }
4562236b 851 aconnector->dc_sink = sink;
98e6436d
AK		 852 amdgpu_dm_update_freesync_caps(connector,
853 aconnector->edid);
4562236b 854 } else {
98e6436d 855 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 856 if (!aconnector->dc_sink)
857 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 858 else if (aconnector->dc_sink != aconnector->dc_em_sink)
859 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 860 }
861
862 mutex_unlock(&dev->mode_config.mutex);
863 return;
864 }
865
866 /*
867 * TODO: temporary guard to look for proper fix
868 * if this sink is MST sink, we should not do anything
869 */
870 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
871 return;
872
873 if (aconnector->dc_sink == sink) {
874 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
875 * Do nothing!! */
f1ad2f5e 876 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 877 aconnector->connector_id);
878 return;
879 }
880
f1ad2f5e 881 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 882 aconnector->connector_id, aconnector->dc_sink, sink);
883
884 mutex_lock(&dev->mode_config.mutex);
885
886 /* 1. Update status of the drm connector
887 * 2. Send an event and let userspace tell us what to do */
888 if (sink) {
889 /* TODO: check if we still need the S3 mode update workaround.
890 * If yes, put it here. */
891 if (aconnector->dc_sink)
98e6436d 892 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 893
894 aconnector->dc_sink = sink;
900b3cb1 895 if (sink->dc_edid.length == 0) {
4562236b 896 aconnector->edid = NULL;
900b3cb1 897 } else {
4562236b
HW		 898 aconnector->edid =
899 (struct edid *) sink->dc_edid.raw_edid;
900
901
c555f023 902 drm_connector_update_edid_property(connector,
4562236b
HW		 903 aconnector->edid);
904 }
98e6436d 905 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 906
907 } else {
98e6436d 908 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 909 drm_connector_update_edid_property(connector, NULL);
4562236b
HW		 910 aconnector->num_modes = 0;
911 aconnector->dc_sink = NULL;
5326c452 912 aconnector->edid = NULL;
4562236b
HW		 913 }
914
915 mutex_unlock(&dev->mode_config.mutex);
916}
917
918static void handle_hpd_irq(void *param)
919{
c84dec2f 920 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 921 struct drm_connector *connector = &aconnector->base;
922 struct drm_device *dev = connector->dev;
923
924 /* In case of failure or MST no need to update connector status or notify the OS
925 * since (for MST case) MST does this in it's own context.
926 */
927 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 928
929 if (aconnector->fake_enable)
930 aconnector->fake_enable = false;
931
8f38b66c 932 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 933 amdgpu_dm_update_connector_after_detect(aconnector);
934
935
936 drm_modeset_lock_all(dev);
937 dm_restore_drm_connector_state(dev, connector);
938 drm_modeset_unlock_all(dev);
939
940 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
941 drm_kms_helper_hotplug_event(dev);
942 }
943 mutex_unlock(&aconnector->hpd_lock);
944
945}
946
c84dec2f 947static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 948{
949 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
950 uint8_t dret;
951 bool new_irq_handled = false;
952 int dpcd_addr;
953 int dpcd_bytes_to_read;
954
955 const int max_process_count = 30;
956 int process_count = 0;
957
958 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
959
960 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
961 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
962 /* DPCD 0x200 - 0x201 for downstream IRQ */
963 dpcd_addr = DP_SINK_COUNT;
964 } else {
965 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
966 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
967 dpcd_addr = DP_SINK_COUNT_ESI;
968 }
969
970 dret = drm_dp_dpcd_read(
971 &aconnector->dm_dp_aux.aux,
972 dpcd_addr,
973 esi,
974 dpcd_bytes_to_read);
975
976 while (dret == dpcd_bytes_to_read &&
977 process_count < max_process_count) {
978 uint8_t retry;
979 dret = 0;
980
981 process_count++;
982
f1ad2f5e 983 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 984 /* handle HPD short pulse irq */
985 if (aconnector->mst_mgr.mst_state)
986 drm_dp_mst_hpd_irq(
987 &aconnector->mst_mgr,
988 esi,
989 &new_irq_handled);
4562236b
HW		 990
991 if (new_irq_handled) {
992 /* ACK at DPCD to notify down stream */
993 const int ack_dpcd_bytes_to_write =
994 dpcd_bytes_to_read - 1;
995
996 for (retry = 0; retry < 3; retry++) {
997 uint8_t wret;
998
999 wret = drm_dp_dpcd_write(
1000 &aconnector->dm_dp_aux.aux,
1001 dpcd_addr + 1,
1002 &esi[1],
1003 ack_dpcd_bytes_to_write);
1004 if (wret == ack_dpcd_bytes_to_write)
1005 break;
1006 }
1007
1008 /* check if there is new irq to be handle */
1009 dret = drm_dp_dpcd_read(
1010 &aconnector->dm_dp_aux.aux,
1011 dpcd_addr,
1012 esi,
1013 dpcd_bytes_to_read);
1014
1015 new_irq_handled = false;
d4a6e8a9 1016 } else {
4562236b 1017 break;
d4a6e8a9 1018 }
4562236b
HW		 1019 }
1020
1021 if (process_count == max_process_count)
f1ad2f5e 1022 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1023}
1024
1025static void handle_hpd_rx_irq(void *param)
1026{
c84dec2f 1027 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1028 struct drm_connector *connector = &aconnector->base;
1029 struct drm_device *dev = connector->dev;
53cbf65c 1030 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 1031 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1032
1033 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1034 * conflict, after implement i2c helper, this mutex should be
1035 * retired.
1036 */
53cbf65c 1037 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1038 mutex_lock(&aconnector->hpd_lock);
1039
4e18814e 1040 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1041 !is_mst_root_connector) {
1042 /* Downstream Port status changed. */
53cbf65c 1043 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1044
1045 if (aconnector->fake_enable)
1046 aconnector->fake_enable = false;
1047
4562236b
HW		 1048 amdgpu_dm_update_connector_after_detect(aconnector);
1049
1050
1051 drm_modeset_lock_all(dev);
1052 dm_restore_drm_connector_state(dev, connector);
1053 drm_modeset_unlock_all(dev);
1054
1055 drm_kms_helper_hotplug_event(dev);
1056 }
1057 }
1058 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1059 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1060 dm_handle_hpd_rx_irq(aconnector);
1061
53cbf65c 1062 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1063 mutex_unlock(&aconnector->hpd_lock);
1064}
1065
1066static void register_hpd_handlers(struct amdgpu_device *adev)
1067{
1068 struct drm_device *dev = adev->ddev;
1069 struct drm_connector *connector;
c84dec2f 1070 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1071 const struct dc_link *dc_link;
1072 struct dc_interrupt_params int_params = {0};
1073
1074 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1075 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1076
1077 list_for_each_entry(connector,
1078 &dev->mode_config.connector_list, head) {
1079
c84dec2f 1080 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1081 dc_link = aconnector->dc_link;
1082
1083 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1084 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1085 int_params.irq_source = dc_link->irq_source_hpd;
1086
1087 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1088 handle_hpd_irq,
1089 (void *) aconnector);
1090 }
1091
1092 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1093
1094 /* Also register for DP short pulse (hpd_rx). */
1095 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1096 int_params.irq_source = dc_link->irq_source_hpd_rx;
1097
1098 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1099 handle_hpd_rx_irq,
1100 (void *) aconnector);
1101 }
1102 }
1103}
1104
1105/* Register IRQ sources and initialize IRQ callbacks */
1106static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1107{
1108 struct dc *dc = adev->dm.dc;
1109 struct common_irq_params *c_irq_params;
1110 struct dc_interrupt_params int_params = {0};
1111 int r;
1112 int i;
2c8ad2d5
AD		 1113 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1114
ff5ef992 1115 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1116 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1117 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1118 adev->asic_type == CHIP_RAVEN)
3760f76c 1119 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1120
1121 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1122 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1123
1124 /* Actions of amdgpu_irq_add_id():
1125 * 1. Register a set() function with base driver.
1126 * Base driver will call set() function to enable/disable an
1127 * interrupt in DC hardware.
1128 * 2. Register amdgpu_dm_irq_handler().
1129 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1130 * coming from DC hardware.
1131 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1132 * for acknowledging and handling. */
1133
b57de80a 1134 /* Use VBLANK interrupt */
e9029155 1135 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1136 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1137 if (r) {
1138 DRM_ERROR("Failed to add crtc irq id!\n");
1139 return r;
1140 }
1141
1142 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1143 int_params.irq_source =
3d761e79 1144 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1145
b57de80a 1146 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1147
1148 c_irq_params->adev = adev;
1149 c_irq_params->irq_src = int_params.irq_source;
1150
1151 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1152 dm_crtc_high_irq, c_irq_params);
1153 }
1154
3d761e79 1155 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1156 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1157 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1158 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1159 if (r) {
1160 DRM_ERROR("Failed to add page flip irq id!\n");
1161 return r;
1162 }
1163
1164 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1165 int_params.irq_source =
1166 dc_interrupt_to_irq_source(dc, i, 0);
1167
1168 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1169
1170 c_irq_params->adev = adev;
1171 c_irq_params->irq_src = int_params.irq_source;
1172
1173 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1174 dm_pflip_high_irq, c_irq_params);
1175
1176 }
1177
1178 /* HPD */
2c8ad2d5
AD		 1179 r = amdgpu_irq_add_id(adev, client_id,
1180 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1181 if (r) {
1182 DRM_ERROR("Failed to add hpd irq id!\n");
1183 return r;
1184 }
1185
1186 register_hpd_handlers(adev);
1187
1188 return 0;
1189}
1190
dc37a9a0 1191#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 1192/* Register IRQ sources and initialize IRQ callbacks */
1193static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1194{
1195 struct dc *dc = adev->dm.dc;
1196 struct common_irq_params *c_irq_params;
1197 struct dc_interrupt_params int_params = {0};
1198 int r;
1199 int i;
1200
1201 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1202 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1203
1204 /* Actions of amdgpu_irq_add_id():
1205 * 1. Register a set() function with base driver.
1206 * Base driver will call set() function to enable/disable an
1207 * interrupt in DC hardware.
1208 * 2. Register amdgpu_dm_irq_handler().
1209 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1210 * coming from DC hardware.
1211 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1212 * for acknowledging and handling.
1213 * */
1214
1215 /* Use VSTARTUP interrupt */
1216 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1217 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1218 i++) {
3760f76c 1219 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1220
1221 if (r) {
1222 DRM_ERROR("Failed to add crtc irq id!\n");
1223 return r;
1224 }
1225
1226 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1227 int_params.irq_source =
1228 dc_interrupt_to_irq_source(dc, i, 0);
1229
1230 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1231
1232 c_irq_params->adev = adev;
1233 c_irq_params->irq_src = int_params.irq_source;
1234
1235 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1236 dm_crtc_high_irq, c_irq_params);
1237 }
1238
1239 /* Use GRPH_PFLIP interrupt */
1240 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1241 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1242 i++) {
3760f76c 1243 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1244 if (r) {
1245 DRM_ERROR("Failed to add page flip irq id!\n");
1246 return r;
1247 }
1248
1249 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1250 int_params.irq_source =
1251 dc_interrupt_to_irq_source(dc, i, 0);
1252
1253 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1254
1255 c_irq_params->adev = adev;
1256 c_irq_params->irq_src = int_params.irq_source;
1257
1258 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1259 dm_pflip_high_irq, c_irq_params);
1260
1261 }
1262
1263 /* HPD */
3760f76c 1264 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1265 &adev->hpd_irq);
1266 if (r) {
1267 DRM_ERROR("Failed to add hpd irq id!\n");
1268 return r;
1269 }
1270
1271 register_hpd_handlers(adev);
1272
1273 return 0;
1274}
1275#endif
1276
4562236b
HW		 1277static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1278{
1279 int r;
1280
1281 adev->mode_info.mode_config_initialized = true;
1282
4562236b 1283 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1284 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1285
1286 adev->ddev->mode_config.max_width = 16384;
1287 adev->ddev->mode_config.max_height = 16384;
1288
1289 adev->ddev->mode_config.preferred_depth = 24;
1290 adev->ddev->mode_config.prefer_shadow = 1;
1291 /* indicate support of immediate flip */
1292 adev->ddev->mode_config.async_page_flip = true;
1293
770d13b1 1294 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1295
3dc9b1ce 1296 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1297 if (r)
1298 return r;
1299
1300 return 0;
1301}
1302
1303#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1304 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1305
1306static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1307{
1308 struct amdgpu_display_manager *dm = bl_get_data(bd);
1309
1310 if (dc_link_set_backlight_level(dm->backlight_link,
1311 bd->props.brightness, 0, 0))
1312 return 0;
1313 else
1314 return 1;
1315}
1316
1317static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1318{
620a0d27
DF		 1319 struct amdgpu_display_manager *dm = bl_get_data(bd);
1320 int ret = dc_link_get_backlight_level(dm->backlight_link);
1321
1322 if (ret == DC_ERROR_UNEXPECTED)
1323 return bd->props.brightness;
1324 return ret;
4562236b
HW		 1325}
1326
1327static const struct backlight_ops amdgpu_dm_backlight_ops = {
1328 .get_brightness = amdgpu_dm_backlight_get_brightness,
1329 .update_status = amdgpu_dm_backlight_update_status,
1330};
1331
7578ecda
AD		 1332static void
1333amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1334{
1335 char bl_name[16];
1336 struct backlight_properties props = { 0 };
1337
1338 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 1339 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 1340 props.type = BACKLIGHT_RAW;
1341
1342 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1343 dm->adev->ddev->primary->index);
1344
1345 dm->backlight_dev = backlight_device_register(bl_name,
1346 dm->adev->ddev->dev,
1347 dm,
1348 &amdgpu_dm_backlight_ops,
1349 &props);
1350
74baea42 1351 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1352 DRM_ERROR("DM: Backlight registration failed!\n");
1353 else
f1ad2f5e 1354 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1355}
1356
1357#endif
1358
df534fff
S		 1359static int initialize_plane(struct amdgpu_display_manager *dm,
1360 struct amdgpu_mode_info *mode_info,
1361 int plane_id)
1362{
1363 struct amdgpu_plane *plane;
1364 unsigned long possible_crtcs;
1365 int ret = 0;
1366
1367 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1368 mode_info->planes[plane_id] = plane;
1369
1370 if (!plane) {
1371 DRM_ERROR("KMS: Failed to allocate plane\n");
1372 return -ENOMEM;
1373 }
1374 plane->base.type = mode_info->plane_type[plane_id];
1375
1376 /*
1377 * HACK: IGT tests expect that each plane can only have one
1378 * one possible CRTC. For now, set one CRTC for each
1379 * plane that is not an underlay, but still allow multiple
1380 * CRTCs for underlay planes.
1381 */
1382 possible_crtcs = 1 << plane_id;
1383 if (plane_id >= dm->dc->caps.max_streams)
1384 possible_crtcs = 0xff;
1385
1386 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1387
1388 if (ret) {
1389 DRM_ERROR("KMS: Failed to initialize plane\n");
1390 return ret;
1391 }
1392
1393 return ret;
1394}
1395
89fc8d4e
HW		 1396
1397static void register_backlight_device(struct amdgpu_display_manager *dm,
1398 struct dc_link *link)
1399{
1400#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1401 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1402
1403 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1404 link->type != dc_connection_none) {
1405 /* Event if registration failed, we should continue with
1406 * DM initialization because not having a backlight control
1407 * is better then a black screen.
1408 */
1409 amdgpu_dm_register_backlight_device(dm);
1410
1411 if (dm->backlight_dev)
1412 dm->backlight_link = link;
1413 }
1414#endif
1415}
1416
1417
4562236b
HW		 1418/* In this architecture, the association
1419 * connector -> encoder -> crtc
1420 * id not really requried. The crtc and connector will hold the
1421 * display_index as an abstraction to use with DAL component
1422 *
1423 * Returns 0 on success
1424 */
7578ecda 1425static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1426{
1427 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 1428 int32_t i;
c84dec2f 1429 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1430 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1431 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1432 uint32_t link_cnt;
df534fff 1433 int32_t total_overlay_planes, total_primary_planes;
4562236b
HW		 1434
1435 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1436 if (amdgpu_dm_mode_config_init(dm->adev)) {
1437 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1438 return -1;
4562236b
HW		 1439 }
1440
df534fff
S		 1441 /* Identify the number of planes to be initialized */
1442 total_overlay_planes = dm->dc->caps.max_slave_planes;
1443 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
efa6a8b7 1444
df534fff
S		 1445 /* First initialize overlay planes, index starting after primary planes */
1446 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1447 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1448 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 1449 goto fail;
d4e13b0d 1450 }
df534fff 1451 }
92f3ac40 1452
df534fff
S		 1453 /* Initialize primary planes */
1454 for (i = (total_primary_planes - 1); i >= 0; i--) {
1455 if (initialize_plane(dm, mode_info, i)) {
1456 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 1457 goto fail;
d4e13b0d
AD		 1458 }
1459 }
4562236b 1460
d4e13b0d
AD		 1461 for (i = 0; i < dm->dc->caps.max_streams; i++)
1462 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1463 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1464 goto fail;
4562236b 1465 }
4562236b 1466
ab2541b6 1467 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1468
1469 /* loops over all connectors on the board */
1470 for (i = 0; i < link_cnt; i++) {
89fc8d4e 1471 struct dc_link *link = NULL;
4562236b
HW		 1472
1473 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1474 DRM_ERROR(
1475 "KMS: Cannot support more than %d display indexes\n",
1476 AMDGPU_DM_MAX_DISPLAY_INDEX);
1477 continue;
1478 }
1479
1480 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1481 if (!aconnector)
cd8a2ae8 1482 goto fail;
4562236b
HW		 1483
1484 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1485 if (!aencoder)
cd8a2ae8 1486 goto fail;
4562236b
HW		 1487
1488 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1489 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1490 goto fail;
4562236b
HW		 1491 }
1492
1493 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1494 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1495 goto fail;
4562236b
HW		 1496 }
1497
89fc8d4e
HW		 1498 link = dc_get_link_at_index(dm->dc, i);
1499
1500 if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 1501 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 1502 register_backlight_device(dm, link);
1503 }
1504
1505
4562236b
HW		 1506 }
1507
1508 /* Software is initialized. Now we can register interrupt handlers. */
1509 switch (adev->asic_type) {
1510 case CHIP_BONAIRE:
1511 case CHIP_HAWAII:
cd4b356f
AD		 1512 case CHIP_KAVERI:
1513 case CHIP_KABINI:
1514 case CHIP_MULLINS:
4562236b
HW		 1515 case CHIP_TONGA:
1516 case CHIP_FIJI:
1517 case CHIP_CARRIZO:
1518 case CHIP_STONEY:
1519 case CHIP_POLARIS11:
1520 case CHIP_POLARIS10:
b264d345 1521 case CHIP_POLARIS12:
7737de91 1522 case CHIP_VEGAM:
2c8ad2d5 1523 case CHIP_VEGA10:
2325ff30 1524 case CHIP_VEGA12:
1fe6bf2f 1525 case CHIP_VEGA20:
4562236b
HW		 1526 if (dce110_register_irq_handlers(dm->adev)) {
1527 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1528 goto fail;
4562236b
HW		 1529 }
1530 break;
dc37a9a0 1531#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 1532 case CHIP_RAVEN:
1533 if (dcn10_register_irq_handlers(dm->adev)) {
1534 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1535 goto fail;
ff5ef992
AD		 1536 }
1537 break;
1538#endif
4562236b 1539 default:
e63f8673 1540 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 1541 goto fail;
4562236b
HW		 1542 }
1543
1bc460a4
HW		 1544 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1545 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1546
4562236b 1547 return 0;
cd8a2ae8 1548fail:
4562236b 1549 kfree(aencoder);
4562236b 1550 kfree(aconnector);
3be5262e 1551 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1552 kfree(mode_info->planes[i]);
4562236b
HW		 1553 return -1;
1554}
1555
7578ecda 1556static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1557{
1558 drm_mode_config_cleanup(dm->ddev);
1559 return;
1560}
1561
1562/******************************************************************************
1563 * amdgpu_display_funcs functions
1564 *****************************************************************************/
1565
1566/**
1567 * dm_bandwidth_update - program display watermarks
1568 *
1569 * @adev: amdgpu_device pointer
1570 *
1571 * Calculate and program the display watermarks and line buffer allocation.
1572 */
1573static void dm_bandwidth_update(struct amdgpu_device *adev)
1574{
49c07a99 1575 /* TODO: implement later */
4562236b
HW		 1576}
1577
4562236b
HW		 1578static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1579 struct drm_file *filp)
1580{
98e6436d
AK		 1581 struct drm_atomic_state *state;
1582 struct drm_modeset_acquire_ctx ctx;
1583 struct drm_crtc *crtc;
1584 struct drm_connector *connector;
1585 struct drm_connector_state *old_con_state, *new_con_state;
1586 int ret = 0;
4562236b 1587 uint8_t i;
98e6436d 1588 bool enable = false;
4562236b 1589
98e6436d
AK		 1590 drm_modeset_acquire_init(&ctx, 0);
1591
1592 state = drm_atomic_state_alloc(dev);
1593 if (!state) {
1594 ret = -ENOMEM;
1595 goto out;
1596 }
1597 state->acquire_ctx = &ctx;
1598
1599retry:
1600 drm_for_each_crtc(crtc, dev) {
1601 ret = drm_atomic_add_affected_connectors(state, crtc);
1602 if (ret)
1603 goto fail;
1604
1605 /* TODO rework amdgpu_dm_commit_planes so we don't need this */
1606 ret = drm_atomic_add_affected_planes(state, crtc);
1607 if (ret)
1608 goto fail;
1609 }
4562236b 1610
98e6436d
AK		 1611 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
1612 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
1613 struct drm_crtc_state *new_crtc_state;
1614 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
1615 struct dm_crtc_state *dm_new_crtc_state;
4562236b 1616
98e6436d
AK		 1617 if (!acrtc) {
1618 ASSERT(0);
1619 continue;
1620 }
4562236b 1621
98e6436d
AK		 1622 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
1623 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4562236b 1624
98e6436d 1625 dm_new_crtc_state->freesync_enabled = enable;
4562236b
HW		 1626 }
1627
98e6436d
AK		 1628 ret = drm_atomic_commit(state);
1629
1630fail:
1631 if (ret == -EDEADLK) {
1632 drm_atomic_state_clear(state);
1633 drm_modeset_backoff(&ctx);
1634 goto retry;
1635 }
1636
1637 drm_atomic_state_put(state);
1638
1639out:
1640 drm_modeset_drop_locks(&ctx);
1641 drm_modeset_acquire_fini(&ctx);
1642 return ret;
4562236b
HW		 1643}
1644
39cc5be2 1645static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1646 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1647 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 1648 .backlight_set_level = NULL, /* never called for DC */
1649 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 1650 .hpd_sense = NULL,/* called unconditionally */
1651 .hpd_set_polarity = NULL, /* called unconditionally */
1652 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1653 .page_flip_get_scanoutpos =
1654 dm_crtc_get_scanoutpos,/* called unconditionally */
1655 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1656 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1657 .notify_freesync = amdgpu_notify_freesync,
1658
1659};
1660
1661#if defined(CONFIG_DEBUG_KERNEL_DC)
1662
3ee6b26b
AD		 1663static ssize_t s3_debug_store(struct device *device,
1664 struct device_attribute *attr,
1665 const char *buf,
1666 size_t count)
4562236b
HW		 1667{
1668 int ret;
1669 int s3_state;
1670 struct pci_dev *pdev = to_pci_dev(device);
1671 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1672 struct amdgpu_device *adev = drm_dev->dev_private;
1673
1674 ret = kstrtoint(buf, 0, &s3_state);
1675
1676 if (ret == 0) {
1677 if (s3_state) {
1678 dm_resume(adev);
4562236b
HW		 1679 drm_kms_helper_hotplug_event(adev->ddev);
1680 } else
1681 dm_suspend(adev);
1682 }
1683
1684 return ret == 0 ? count : 0;
1685}
1686
1687DEVICE_ATTR_WO(s3_debug);
1688
1689#endif
1690
1691static int dm_early_init(void *handle)
1692{
1693 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1694
4562236b
HW		 1695 switch (adev->asic_type) {
1696 case CHIP_BONAIRE:
1697 case CHIP_HAWAII:
1698 adev->mode_info.num_crtc = 6;
1699 adev->mode_info.num_hpd = 6;
1700 adev->mode_info.num_dig = 6;
3be5262e 1701 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1702 break;
cd4b356f
AD		 1703 case CHIP_KAVERI:
1704 adev->mode_info.num_crtc = 4;
1705 adev->mode_info.num_hpd = 6;
1706 adev->mode_info.num_dig = 7;
1707 adev->mode_info.plane_type = dm_plane_type_default;
1708 break;
1709 case CHIP_KABINI:
1710 case CHIP_MULLINS:
1711 adev->mode_info.num_crtc = 2;
1712 adev->mode_info.num_hpd = 6;
1713 adev->mode_info.num_dig = 6;
1714 adev->mode_info.plane_type = dm_plane_type_default;
1715 break;
4562236b
HW		 1716 case CHIP_FIJI:
1717 case CHIP_TONGA:
1718 adev->mode_info.num_crtc = 6;
1719 adev->mode_info.num_hpd = 6;
1720 adev->mode_info.num_dig = 7;
3be5262e 1721 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1722 break;
1723 case CHIP_CARRIZO:
1724 adev->mode_info.num_crtc = 3;
1725 adev->mode_info.num_hpd = 6;
1726 adev->mode_info.num_dig = 9;
3be5262e 1727 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1728 break;
1729 case CHIP_STONEY:
1730 adev->mode_info.num_crtc = 2;
1731 adev->mode_info.num_hpd = 6;
1732 adev->mode_info.num_dig = 9;
3be5262e 1733 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1734 break;
1735 case CHIP_POLARIS11:
b264d345 1736 case CHIP_POLARIS12:
4562236b
HW		 1737 adev->mode_info.num_crtc = 5;
1738 adev->mode_info.num_hpd = 5;
1739 adev->mode_info.num_dig = 5;
3be5262e 1740 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1741 break;
1742 case CHIP_POLARIS10:
7737de91 1743 case CHIP_VEGAM:
4562236b
HW		 1744 adev->mode_info.num_crtc = 6;
1745 adev->mode_info.num_hpd = 6;
1746 adev->mode_info.num_dig = 6;
3be5262e 1747 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1748 break;
2c8ad2d5 1749 case CHIP_VEGA10:
2325ff30 1750 case CHIP_VEGA12:
1fe6bf2f 1751 case CHIP_VEGA20:
2c8ad2d5
AD		 1752 adev->mode_info.num_crtc = 6;
1753 adev->mode_info.num_hpd = 6;
1754 adev->mode_info.num_dig = 6;
3be5262e 1755 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1756 break;
dc37a9a0 1757#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
ff5ef992
AD		 1758 case CHIP_RAVEN:
1759 adev->mode_info.num_crtc = 4;
1760 adev->mode_info.num_hpd = 4;
1761 adev->mode_info.num_dig = 4;
3be5262e 1762 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1763 break;
1764#endif
4562236b 1765 default:
e63f8673 1766 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 1767 return -EINVAL;
1768 }
1769
c8dd5715
MD		 1770 amdgpu_dm_set_irq_funcs(adev);
1771
39cc5be2
AD		 1772 if (adev->mode_info.funcs == NULL)
1773 adev->mode_info.funcs = &dm_display_funcs;
1774
4562236b
HW		 1775 /* Note: Do NOT change adev->audio_endpt_rreg and
1776 * adev->audio_endpt_wreg because they are initialised in
1777 * amdgpu_device_init() */
1778#if defined(CONFIG_DEBUG_KERNEL_DC)
1779 device_create_file(
1780 adev->ddev->dev,
1781 &dev_attr_s3_debug);
1782#endif
1783
1784 return 0;
1785}
1786
9b690ef3 1787static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1788 struct dc_stream_state *new_stream,
1789 struct dc_stream_state *old_stream)
9b690ef3 1790{
e7b07cee
HW		 1791 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1792 return false;
1793
1794 if (!crtc_state->enable)
1795 return false;
1796
1797 return crtc_state->active;
1798}
1799
1800static bool modereset_required(struct drm_crtc_state *crtc_state)
1801{
1802 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1803 return false;
1804
1805 return !crtc_state->enable || !crtc_state->active;
1806}
1807
7578ecda 1808static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1809{
1810 drm_encoder_cleanup(encoder);
1811 kfree(encoder);
1812}
1813
1814static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1815 .destroy = amdgpu_dm_encoder_destroy,
1816};
1817
3ee6b26b
AD		 1818static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1819 struct dc_plane_state *plane_state)
e7b07cee 1820{
3be5262e
HW		 1821 plane_state->src_rect.x = state->src_x >> 16;
1822 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1823 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1824 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1825
3be5262e 1826 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1827 return false;
1828
3be5262e
HW		 1829 plane_state->src_rect.height = state->src_h >> 16;
1830 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1831 return false;
1832
3be5262e
HW		 1833 plane_state->dst_rect.x = state->crtc_x;
1834 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1835
1836 if (state->crtc_w == 0)
1837 return false;
1838
3be5262e 1839 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1840
1841 if (state->crtc_h == 0)
1842 return false;
1843
3be5262e 1844 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1845
3be5262e 1846 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1847
1848 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1849 case DRM_MODE_ROTATE_0:
3be5262e 1850 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1851 break;
1852 case DRM_MODE_ROTATE_90:
3be5262e 1853 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1854 break;
1855 case DRM_MODE_ROTATE_180:
3be5262e 1856 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1857 break;
1858 case DRM_MODE_ROTATE_270:
3be5262e 1859 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1860 break;
1861 default:
3be5262e 1862 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1863 break;
1864 }
1865
4562236b
HW		 1866 return true;
1867}
3ee6b26b 1868static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 1869 uint64_t *tiling_flags)
e7b07cee 1870{
e68d14dd 1871 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 1872 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1873
e7b07cee 1874 if (unlikely(r)) {
9bbc3031
JZ		 1875 // Don't show error msg. when return -ERESTARTSYS
1876 if (r != -ERESTARTSYS)
1877 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1878 return r;
1879 }
1880
e7b07cee
HW		 1881 if (tiling_flags)
1882 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1883
1884 amdgpu_bo_unreserve(rbo);
1885
1886 return r;
1887}
1888
3ee6b26b
AD		 1889static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1890 struct dc_plane_state *plane_state,
9817d5f5 1891 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 1892{
1893 uint64_t tiling_flags;
e7b07cee
HW		 1894 unsigned int awidth;
1895 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1896 int ret = 0;
1897 struct drm_format_name_buf format_name;
1898
1899 ret = get_fb_info(
1900 amdgpu_fb,
9817d5f5 1901 &tiling_flags);
e7b07cee
HW		 1902
1903 if (ret)
1904 return ret;
1905
1906 switch (fb->format->format) {
1907 case DRM_FORMAT_C8:
3be5262e 1908 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1909 break;
1910 case DRM_FORMAT_RGB565:
3be5262e 1911 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1912 break;
1913 case DRM_FORMAT_XRGB8888:
1914 case DRM_FORMAT_ARGB8888:
3be5262e 1915 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1916 break;
1917 case DRM_FORMAT_XRGB2101010:
1918 case DRM_FORMAT_ARGB2101010:
3be5262e 1919 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1920 break;
1921 case DRM_FORMAT_XBGR2101010:
1922 case DRM_FORMAT_ABGR2101010:
3be5262e 1923 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee 1924 break;
bcd47f60
MR		 1925 case DRM_FORMAT_XBGR8888:
1926 case DRM_FORMAT_ABGR8888:
1927 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
1928 break;
e7b07cee 1929 case DRM_FORMAT_NV21:
3be5262e 1930 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1931 break;
1932 case DRM_FORMAT_NV12:
3be5262e 1933 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1934 break;
1935 default:
1936 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1937 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1938 return -EINVAL;
1939 }
1940
3be5262e
HW		 1941 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1942 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 1943 plane_state->plane_size.grph.surface_size.x = 0;
1944 plane_state->plane_size.grph.surface_size.y = 0;
1945 plane_state->plane_size.grph.surface_size.width = fb->width;
1946 plane_state->plane_size.grph.surface_size.height = fb->height;
1947 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1948 fb->pitches[0] / fb->format->cpp[0];
1949 /* TODO: unhardcode */
3be5262e 1950 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1951
1952 } else {
1953 awidth = ALIGN(fb->width, 64);
3be5262e 1954 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 1955 plane_state->plane_size.video.luma_size.x = 0;
1956 plane_state->plane_size.video.luma_size.y = 0;
1957 plane_state->plane_size.video.luma_size.width = awidth;
1958 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1959 /* TODO: unhardcode */
3be5262e 1960 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1961
3be5262e
HW		 1962 plane_state->plane_size.video.chroma_size.x = 0;
1963 plane_state->plane_size.video.chroma_size.y = 0;
1964 plane_state->plane_size.video.chroma_size.width = awidth;
1965 plane_state->plane_size.video.chroma_size.height = fb->height;
1966 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1967
1968 /* TODO: unhardcode */
3be5262e 1969 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1970 }
1971
3be5262e 1972 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1973
b830ebc9
HW		 1974 /* Fill GFX8 params */
1975 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1976 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1977
1978 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1979 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1980 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1981 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1982 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1983
1984 /* XXX fix me for VI */
3be5262e
HW		 1985 plane_state->tiling_info.gfx8.num_banks = num_banks;
1986 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1987 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1988 plane_state->tiling_info.gfx8.tile_split = tile_split;
1989 plane_state->tiling_info.gfx8.bank_width = bankw;
1990 plane_state->tiling_info.gfx8.bank_height = bankh;
1991 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1992 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1993 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1994 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1995 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1996 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1997 }
1998
3be5262e 1999 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 2000 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2001
2002 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 2003 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 2004 adev->asic_type == CHIP_VEGA20 ||
e7b07cee
HW		 2005 adev->asic_type == CHIP_RAVEN) {
2006 /* Fill GFX9 params */
3be5262e 2007 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 2008 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 2009 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 2010 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 2011 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 2012 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 2013 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 2014 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 2015 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 2016 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 2017 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 2018 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 2019 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 2020 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 2021 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 2022 }
2023
3be5262e
HW		 2024 plane_state->visible = true;
2025 plane_state->scaling_quality.h_taps_c = 0;
2026 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 2027
3be5262e
HW		 2028 /* is this needed? is plane_state zeroed at allocation? */
2029 plane_state->scaling_quality.h_taps = 0;
2030 plane_state->scaling_quality.v_taps = 0;
2031 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 2032
2033 return ret;
2034
2035}
2036
3ee6b26b
AD		 2037static int fill_plane_attributes(struct amdgpu_device *adev,
2038 struct dc_plane_state *dc_plane_state,
2039 struct drm_plane_state *plane_state,
9817d5f5 2040 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2041{
2042 const struct amdgpu_framebuffer *amdgpu_fb =
2043 to_amdgpu_framebuffer(plane_state->fb);
2044 const struct drm_crtc *crtc = plane_state->crtc;
e7b07cee
HW		 2045 int ret = 0;
2046
3be5262e 2047 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 2048 return -EINVAL;
2049
2050 ret = fill_plane_attributes_from_fb(
2051 crtc->dev->dev_private,
3be5262e 2052 dc_plane_state,
9817d5f5 2053 amdgpu_fb);
e7b07cee
HW		 2054
2055 if (ret)
2056 return ret;
2057
e277adc5
LSL		 2058 /*
2059 * Always set input transfer function, since plane state is refreshed
2060 * every time.
2061 */
2062 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2063 if (ret) {
2064 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2065 dc_plane_state->in_transfer_func = NULL;
2066 }
e7b07cee
HW		 2067
2068 return ret;
2069}
2070
2071/*****************************************************************************/
2072
3ee6b26b
AD		 2073static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2074 const struct dm_connector_state *dm_state,
2075 struct dc_stream_state *stream)
e7b07cee
HW		 2076{
2077 enum amdgpu_rmx_type rmx_type;
2078
2079 struct rect src = { 0 }; /* viewport in composition space*/
2080 struct rect dst = { 0 }; /* stream addressable area */
2081
2082 /* no mode. nothing to be done */
2083 if (!mode)
2084 return;
2085
2086 /* Full screen scaling by default */
2087 src.width = mode->hdisplay;
2088 src.height = mode->vdisplay;
2089 dst.width = stream->timing.h_addressable;
2090 dst.height = stream->timing.v_addressable;
2091
f4791779
HW		 2092 if (dm_state) {
2093 rmx_type = dm_state->scaling;
2094 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2095 if (src.width * dst.height <
2096 src.height * dst.width) {
2097 /* height needs less upscaling/more downscaling */
2098 dst.width = src.width *
2099 dst.height / src.height;
2100 } else {
2101 /* width needs less upscaling/more downscaling */
2102 dst.height = src.height *
2103 dst.width / src.width;
2104 }
2105 } else if (rmx_type == RMX_CENTER) {
2106 dst = src;
e7b07cee 2107 }
e7b07cee 2108
f4791779
HW		 2109 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2110 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2111
f4791779
HW		 2112 if (dm_state->underscan_enable) {
2113 dst.x += dm_state->underscan_hborder / 2;
2114 dst.y += dm_state->underscan_vborder / 2;
2115 dst.width -= dm_state->underscan_hborder;
2116 dst.height -= dm_state->underscan_vborder;
2117 }
e7b07cee
HW		 2118 }
2119
2120 stream->src = src;
2121 stream->dst = dst;
2122
f1ad2f5e 2123 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2124 dst.x, dst.y, dst.width, dst.height);
2125
2126}
2127
3ee6b26b
AD		 2128static enum dc_color_depth
2129convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2130{
2131 uint32_t bpc = connector->display_info.bpc;
2132
e7b07cee
HW		 2133 switch (bpc) {
2134 case 0:
2135 /* Temporary Work around, DRM don't parse color depth for
2136 * EDID revision before 1.4
2137 * TODO: Fix edid parsing
2138 */
2139 return COLOR_DEPTH_888;
2140 case 6:
2141 return COLOR_DEPTH_666;
2142 case 8:
2143 return COLOR_DEPTH_888;
2144 case 10:
2145 return COLOR_DEPTH_101010;
2146 case 12:
2147 return COLOR_DEPTH_121212;
2148 case 14:
2149 return COLOR_DEPTH_141414;
2150 case 16:
2151 return COLOR_DEPTH_161616;
2152 default:
2153 return COLOR_DEPTH_UNDEFINED;
2154 }
2155}
2156
3ee6b26b
AD		 2157static enum dc_aspect_ratio
2158get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 2159{
e11d4147
LSL		 2160 /* 1-1 mapping, since both enums follow the HDMI spec. */
2161 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 2162}
2163
3ee6b26b
AD		 2164static enum dc_color_space
2165get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2166{
2167 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2168
2169 switch (dc_crtc_timing->pixel_encoding) {
2170 case PIXEL_ENCODING_YCBCR422:
2171 case PIXEL_ENCODING_YCBCR444:
2172 case PIXEL_ENCODING_YCBCR420:
2173 {
2174 /*
2175 * 27030khz is the separation point between HDTV and SDTV
2176 * according to HDMI spec, we use YCbCr709 and YCbCr601
2177 * respectively
2178 */
2179 if (dc_crtc_timing->pix_clk_khz > 27030) {
2180 if (dc_crtc_timing->flags.Y_ONLY)
2181 color_space =
2182 COLOR_SPACE_YCBCR709_LIMITED;
2183 else
2184 color_space = COLOR_SPACE_YCBCR709;
2185 } else {
2186 if (dc_crtc_timing->flags.Y_ONLY)
2187 color_space =
2188 COLOR_SPACE_YCBCR601_LIMITED;
2189 else
2190 color_space = COLOR_SPACE_YCBCR601;
2191 }
2192
2193 }
2194 break;
2195 case PIXEL_ENCODING_RGB:
2196 color_space = COLOR_SPACE_SRGB;
2197 break;
2198
2199 default:
2200 WARN_ON(1);
2201 break;
2202 }
2203
2204 return color_space;
2205}
2206
400443e8
ML		 2207static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2208{
2209 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2210 return;
2211
2212 timing_out->display_color_depth--;
2213}
2214
2215static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2216 const struct drm_display_info *info)
2217{
2218 int normalized_clk;
2219 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2220 return;
2221 do {
2222 normalized_clk = timing_out->pix_clk_khz;
2223 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2224 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2225 normalized_clk /= 2;
2226 /* Adjusting pix clock following on HDMI spec based on colour depth */
2227 switch (timing_out->display_color_depth) {
2228 case COLOR_DEPTH_101010:
2229 normalized_clk = (normalized_clk * 30) / 24;
2230 break;
2231 case COLOR_DEPTH_121212:
2232 normalized_clk = (normalized_clk * 36) / 24;
2233 break;
2234 case COLOR_DEPTH_161616:
2235 normalized_clk = (normalized_clk * 48) / 24;
2236 break;
2237 default:
2238 return;
2239 }
2240 if (normalized_clk <= info->max_tmds_clock)
2241 return;
2242 reduce_mode_colour_depth(timing_out);
2243
2244 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2245
2246}
e7b07cee
HW		 2247/*****************************************************************************/
2248
3ee6b26b
AD		 2249static void
2250fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2251 const struct drm_display_mode *mode_in,
2252 const struct drm_connector *connector)
e7b07cee
HW		 2253{
2254 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 2255 const struct drm_display_info *info = &connector->display_info;
b830ebc9 2256
e7b07cee
HW		 2257 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2258
2259 timing_out->h_border_left = 0;
2260 timing_out->h_border_right = 0;
2261 timing_out->v_border_top = 0;
2262 timing_out->v_border_bottom = 0;
2263 /* TODO: un-hardcode */
fe61a2f1
ML		 2264 if (drm_mode_is_420_only(info, mode_in)
2265 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2266 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2267 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
e7b07cee
HW		 2268 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2269 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2270 else
2271 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2272
2273 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2274 timing_out->display_color_depth = convert_color_depth_from_display_info(
2275 connector);
2276 timing_out->scan_type = SCANNING_TYPE_NODATA;
2277 timing_out->hdmi_vic = 0;
2278 timing_out->vic = drm_match_cea_mode(mode_in);
2279
2280 timing_out->h_addressable = mode_in->crtc_hdisplay;
2281 timing_out->h_total = mode_in->crtc_htotal;
2282 timing_out->h_sync_width =
2283 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2284 timing_out->h_front_porch =
2285 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2286 timing_out->v_total = mode_in->crtc_vtotal;
2287 timing_out->v_addressable = mode_in->crtc_vdisplay;
2288 timing_out->v_front_porch =
2289 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2290 timing_out->v_sync_width =
2291 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2292 timing_out->pix_clk_khz = mode_in->crtc_clock;
2293 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2294 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2295 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2296 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2297 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2298
2299 stream->output_color_space = get_output_color_space(timing_out);
2300
e43a432c
AK		 2301 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2302 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
400443e8
ML		 2303 if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2304 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 2305}
2306
3ee6b26b
AD		 2307static void fill_audio_info(struct audio_info *audio_info,
2308 const struct drm_connector *drm_connector,
2309 const struct dc_sink *dc_sink)
e7b07cee
HW		 2310{
2311 int i = 0;
2312 int cea_revision = 0;
2313 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2314
2315 audio_info->manufacture_id = edid_caps->manufacturer_id;
2316 audio_info->product_id = edid_caps->product_id;
2317
2318 cea_revision = drm_connector->display_info.cea_rev;
2319
d2b2562c
TSD		 2320 strncpy(audio_info->display_name,
2321 edid_caps->display_name,
2322 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2323
b830ebc9 2324 if (cea_revision >= 3) {
e7b07cee
HW		 2325 audio_info->mode_count = edid_caps->audio_mode_count;
2326
2327 for (i = 0; i < audio_info->mode_count; ++i) {
2328 audio_info->modes[i].format_code =
2329 (enum audio_format_code)
2330 (edid_caps->audio_modes[i].format_code);
2331 audio_info->modes[i].channel_count =
2332 edid_caps->audio_modes[i].channel_count;
2333 audio_info->modes[i].sample_rates.all =
2334 edid_caps->audio_modes[i].sample_rate;
2335 audio_info->modes[i].sample_size =
2336 edid_caps->audio_modes[i].sample_size;
2337 }
2338 }
2339
2340 audio_info->flags.all = edid_caps->speaker_flags;
2341
2342 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2343 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2344 audio_info->video_latency = drm_connector->video_latency[0];
2345 audio_info->audio_latency = drm_connector->audio_latency[0];
2346 }
2347
2348 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2349
2350}
2351
3ee6b26b
AD		 2352static void
2353copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2354 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2355{
2356 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2357 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2358 dst_mode->crtc_clock = src_mode->crtc_clock;
2359 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2360 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2361 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2362 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2363 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2364 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2365 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2366 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2367 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2368 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2369 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2370}
2371
3ee6b26b
AD		 2372static void
2373decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2374 const struct drm_display_mode *native_mode,
2375 bool scale_enabled)
e7b07cee
HW		 2376{
2377 if (scale_enabled) {
2378 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2379 } else if (native_mode->clock == drm_mode->clock &&
2380 native_mode->htotal == drm_mode->htotal &&
2381 native_mode->vtotal == drm_mode->vtotal) {
2382 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2383 } else {
2384 /* no scaling nor amdgpu inserted, no need to patch */
2385 }
2386}
2387
aed15309
ML		 2388static struct dc_sink *
2389create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 2390{
2e0ac3d6 2391 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 2392 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 2393 sink_init_data.link = aconnector->dc_link;
2394 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2395
2396 sink = dc_sink_create(&sink_init_data);
423788c7 2397 if (!sink) {
2e0ac3d6 2398 DRM_ERROR("Failed to create sink!\n");
aed15309 2399 return NULL;
423788c7 2400 }
2e0ac3d6 2401 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 2402
aed15309 2403 return sink;
2e0ac3d6
HW		 2404}
2405
fa2123db
ML		 2406static void set_multisync_trigger_params(
2407 struct dc_stream_state *stream)
2408{
2409 if (stream->triggered_crtc_reset.enabled) {
2410 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2411 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2412 }
2413}
2414
2415static void set_master_stream(struct dc_stream_state *stream_set[],
2416 int stream_count)
2417{
2418 int j, highest_rfr = 0, master_stream = 0;
2419
2420 for (j = 0; j < stream_count; j++) {
2421 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2422 int refresh_rate = 0;
2423
2424 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2425 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2426 if (refresh_rate > highest_rfr) {
2427 highest_rfr = refresh_rate;
2428 master_stream = j;
2429 }
2430 }
2431 }
2432 for (j = 0; j < stream_count; j++) {
03736f4c 2433 if (stream_set[j])
fa2123db
ML		 2434 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2435 }
2436}
2437
2438static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2439{
2440 int i = 0;
2441
2442 if (context->stream_count < 2)
2443 return;
2444 for (i = 0; i < context->stream_count ; i++) {
2445 if (!context->streams[i])
2446 continue;
2447 /* TODO: add a function to read AMD VSDB bits and will set
2448 * crtc_sync_master.multi_sync_enabled flag
2449 * For now its set to false
2450 */
2451 set_multisync_trigger_params(context->streams[i]);
2452 }
2453 set_master_stream(context->streams, context->stream_count);
2454}
2455
3ee6b26b
AD		 2456static struct dc_stream_state *
2457create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2458 const struct drm_display_mode *drm_mode,
2459 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2460{
2461 struct drm_display_mode *preferred_mode = NULL;
391ef035 2462 struct drm_connector *drm_connector;
0971c40e 2463 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2464 struct drm_display_mode mode = *drm_mode;
2465 bool native_mode_found = false;
aed15309 2466 struct dc_sink *sink = NULL;
b830ebc9 2467 if (aconnector == NULL) {
e7b07cee 2468 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2469 return stream;
e7b07cee
HW		 2470 }
2471
e7b07cee 2472 drm_connector = &aconnector->base;
2e0ac3d6 2473
f4ac176e
JZ		 2474 if (!aconnector->dc_sink) {
2475 /*
391ef035
JFZ		 2476 * Create dc_sink when necessary to MST
2477 * Don't apply fake_sink to MST
f4ac176e 2478 */
391ef035
JFZ		 2479 if (aconnector->mst_port) {
2480 dm_dp_mst_dc_sink_create(drm_connector);
64245fa7 2481 return stream;
391ef035 2482 }
f4ac176e 2483
aed15309
ML		 2484 sink = create_fake_sink(aconnector);
2485 if (!sink)
64245fa7 2486 return stream;
aed15309
ML		 2487 } else {
2488 sink = aconnector->dc_sink;
f4ac176e 2489 }
2e0ac3d6 2490
aed15309 2491 stream = dc_create_stream_for_sink(sink);
4562236b 2492
b830ebc9 2493 if (stream == NULL) {
e7b07cee 2494 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 2495 goto finish;
e7b07cee
HW		 2496 }
2497
2498 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2499 /* Search for preferred mode */
2500 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2501 native_mode_found = true;
2502 break;
2503 }
2504 }
2505 if (!native_mode_found)
2506 preferred_mode = list_first_entry_or_null(
2507 &aconnector->base.modes,
2508 struct drm_display_mode,
2509 head);
2510
b830ebc9 2511 if (preferred_mode == NULL) {
e7b07cee
HW		 2512 /* This may not be an error, the use case is when we we have no
2513 * usermode calls to reset and set mode upon hotplug. In this
2514 * case, we call set mode ourselves to restore the previous mode
2515 * and the modelist may not be filled in in time.
2516 */
f1ad2f5e 2517 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2518 } else {
2519 decide_crtc_timing_for_drm_display_mode(
2520 &mode, preferred_mode,
f4791779 2521 dm_state ? (dm_state->scaling != RMX_OFF) : false);
e7b07cee
HW		 2522 }
2523
f783577c
JFZ		 2524 if (!dm_state)
2525 drm_mode_set_crtcinfo(&mode, 0);
2526
e7b07cee
HW		 2527 fill_stream_properties_from_drm_display_mode(stream,
2528 &mode, &aconnector->base);
2529 update_stream_scaling_settings(&mode, dm_state, stream);
2530
2531 fill_audio_info(
2532 &stream->audio_info,
2533 drm_connector,
aed15309 2534 sink);
e7b07cee 2535
9182b4cb
HW		 2536 update_stream_signal(stream);
2537
9e3efe3e
HW		 2538 if (dm_state && dm_state->freesync_capable)
2539 stream->ignore_msa_timing_param = true;
aed15309
ML		 2540finish:
2541 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
2542 dc_sink_release(sink);
9e3efe3e 2543
e7b07cee
HW		 2544 return stream;
2545}
2546
7578ecda 2547static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2548{
2549 drm_crtc_cleanup(crtc);
2550 kfree(crtc);
2551}
2552
2553static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2554 struct drm_crtc_state *state)
e7b07cee
HW		 2555{
2556 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2557
2558 /* TODO Destroy dc_stream objects are stream object is flattened */
2559 if (cur->stream)
2560 dc_stream_release(cur->stream);
2561
2562
2563 __drm_atomic_helper_crtc_destroy_state(state);
2564
2565
2566 kfree(state);
2567}
2568
2569static void dm_crtc_reset_state(struct drm_crtc *crtc)
2570{
2571 struct dm_crtc_state *state;
2572
2573 if (crtc->state)
2574 dm_crtc_destroy_state(crtc, crtc->state);
2575
2576 state = kzalloc(sizeof(*state), GFP_KERNEL);
2577 if (WARN_ON(!state))
2578 return;
2579
2580 crtc->state = &state->base;
2581 crtc->state->crtc = crtc;
2582
2583}
2584
2585static struct drm_crtc_state *
2586dm_crtc_duplicate_state(struct drm_crtc *crtc)
2587{
2588 struct dm_crtc_state *state, *cur;
2589
2590 cur = to_dm_crtc_state(crtc->state);
2591
2592 if (WARN_ON(!crtc->state))
2593 return NULL;
2594
2004f45e 2595 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 2596 if (!state)
2597 return NULL;
e7b07cee
HW		 2598
2599 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2600
2601 if (cur->stream) {
2602 state->stream = cur->stream;
2603 dc_stream_retain(state->stream);
2604 }
2605
98e6436d
AK		 2606 state->adjust = cur->adjust;
2607 state->vrr_infopacket = cur->vrr_infopacket;
2608 state->freesync_enabled = cur->freesync_enabled;
2609
e7b07cee
HW		 2610 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2611
2612 return &state->base;
2613}
2614
589d2739
HW		 2615
2616static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2617{
2618 enum dc_irq_source irq_source;
2619 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2620 struct amdgpu_device *adev = crtc->dev->dev_private;
2621
2622 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 2623 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 2624}
2625
2626static int dm_enable_vblank(struct drm_crtc *crtc)
2627{
2628 return dm_set_vblank(crtc, true);
2629}
2630
2631static void dm_disable_vblank(struct drm_crtc *crtc)
2632{
2633 dm_set_vblank(crtc, false);
2634}
2635
e7b07cee
HW		 2636/* Implemented only the options currently availible for the driver */
2637static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2638 .reset = dm_crtc_reset_state,
2639 .destroy = amdgpu_dm_crtc_destroy,
2640 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2641 .set_config = drm_atomic_helper_set_config,
2642 .page_flip = drm_atomic_helper_page_flip,
2643 .atomic_duplicate_state = dm_crtc_duplicate_state,
2644 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 2645 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
589d2739
HW		 2646 .enable_vblank = dm_enable_vblank,
2647 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 2648};
2649
2650static enum drm_connector_status
2651amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2652{
2653 bool connected;
c84dec2f 2654 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2655
2656 /* Notes:
2657 * 1. This interface is NOT called in context of HPD irq.
2658 * 2. This interface *is called* in context of user-mode ioctl. Which
2659 * makes it a bad place for *any* MST-related activit. */
2660
8580d60b
HW		 2661 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2662 !aconnector->fake_enable)
e7b07cee
HW		 2663 connected = (aconnector->dc_sink != NULL);
2664 else
2665 connected = (aconnector->base.force == DRM_FORCE_ON);
2666
2667 return (connected ? connector_status_connected :
2668 connector_status_disconnected);
2669}
2670
3ee6b26b
AD		 2671int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2672 struct drm_connector_state *connector_state,
2673 struct drm_property *property,
2674 uint64_t val)
e7b07cee
HW		 2675{
2676 struct drm_device *dev = connector->dev;
2677 struct amdgpu_device *adev = dev->dev_private;
2678 struct dm_connector_state *dm_old_state =
2679 to_dm_connector_state(connector->state);
2680 struct dm_connector_state *dm_new_state =
2681 to_dm_connector_state(connector_state);
2682
2683 int ret = -EINVAL;
2684
2685 if (property == dev->mode_config.scaling_mode_property) {
2686 enum amdgpu_rmx_type rmx_type;
2687
2688 switch (val) {
2689 case DRM_MODE_SCALE_CENTER:
2690 rmx_type = RMX_CENTER;
2691 break;
2692 case DRM_MODE_SCALE_ASPECT:
2693 rmx_type = RMX_ASPECT;
2694 break;
2695 case DRM_MODE_SCALE_FULLSCREEN:
2696 rmx_type = RMX_FULL;
2697 break;
2698 case DRM_MODE_SCALE_NONE:
2699 default:
2700 rmx_type = RMX_OFF;
2701 break;
2702 }
2703
2704 if (dm_old_state->scaling == rmx_type)
2705 return 0;
2706
2707 dm_new_state->scaling = rmx_type;
2708 ret = 0;
2709 } else if (property == adev->mode_info.underscan_hborder_property) {
2710 dm_new_state->underscan_hborder = val;
2711 ret = 0;
2712 } else if (property == adev->mode_info.underscan_vborder_property) {
2713 dm_new_state->underscan_vborder = val;
2714 ret = 0;
2715 } else if (property == adev->mode_info.underscan_property) {
2716 dm_new_state->underscan_enable = val;
2717 ret = 0;
2718 }
2719
2720 return ret;
2721}
2722
3ee6b26b
AD		 2723int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2724 const struct drm_connector_state *state,
2725 struct drm_property *property,
2726 uint64_t *val)
e7b07cee
HW		 2727{
2728 struct drm_device *dev = connector->dev;
2729 struct amdgpu_device *adev = dev->dev_private;
2730 struct dm_connector_state *dm_state =
2731 to_dm_connector_state(state);
2732 int ret = -EINVAL;
2733
2734 if (property == dev->mode_config.scaling_mode_property) {
2735 switch (dm_state->scaling) {
2736 case RMX_CENTER:
2737 *val = DRM_MODE_SCALE_CENTER;
2738 break;
2739 case RMX_ASPECT:
2740 *val = DRM_MODE_SCALE_ASPECT;
2741 break;
2742 case RMX_FULL:
2743 *val = DRM_MODE_SCALE_FULLSCREEN;
2744 break;
2745 case RMX_OFF:
2746 default:
2747 *val = DRM_MODE_SCALE_NONE;
2748 break;
2749 }
2750 ret = 0;
2751 } else if (property == adev->mode_info.underscan_hborder_property) {
2752 *val = dm_state->underscan_hborder;
2753 ret = 0;
2754 } else if (property == adev->mode_info.underscan_vborder_property) {
2755 *val = dm_state->underscan_vborder;
2756 ret = 0;
2757 } else if (property == adev->mode_info.underscan_property) {
2758 *val = dm_state->underscan_enable;
2759 ret = 0;
2760 }
2761 return ret;
2762}
2763
7578ecda 2764static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2765{
c84dec2f 2766 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2767 const struct dc_link *link = aconnector->dc_link;
2768 struct amdgpu_device *adev = connector->dev->dev_private;
2769 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 2770
e7b07cee
HW		 2771#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2772 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2773
89fc8d4e 2774 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 2775 link->type != dc_connection_none &&
2776 dm->backlight_dev) {
2777 backlight_device_unregister(dm->backlight_dev);
2778 dm->backlight_dev = NULL;
e7b07cee
HW		 2779 }
2780#endif
2781 drm_connector_unregister(connector);
2782 drm_connector_cleanup(connector);
2783 kfree(connector);
2784}
2785
2786void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2787{
2788 struct dm_connector_state *state =
2789 to_dm_connector_state(connector->state);
2790
df099b9b
LSL		 2791 if (connector->state)
2792 __drm_atomic_helper_connector_destroy_state(connector->state);
2793
e7b07cee
HW		 2794 kfree(state);
2795
2796 state = kzalloc(sizeof(*state), GFP_KERNEL);
2797
2798 if (state) {
2799 state->scaling = RMX_OFF;
2800 state->underscan_enable = false;
2801 state->underscan_hborder = 0;
2802 state->underscan_vborder = 0;
2803
df099b9b 2804 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 2805 }
2806}
2807
3ee6b26b
AD		 2808struct drm_connector_state *
2809amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2810{
2811 struct dm_connector_state *state =
2812 to_dm_connector_state(connector->state);
2813
2814 struct dm_connector_state *new_state =
2815 kmemdup(state, sizeof(*state), GFP_KERNEL);
2816
98e6436d
AK		 2817 if (!new_state)
2818 return NULL;
e7b07cee 2819
98e6436d
AK		 2820 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
2821
2822 new_state->freesync_capable = state->freesync_capable;
2823 new_state->freesync_enable = state->freesync_enable;
2824
2825 return &new_state->base;
e7b07cee
HW		 2826}
2827
2828static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2829 .reset = amdgpu_dm_connector_funcs_reset,
2830 .detect = amdgpu_dm_connector_detect,
2831 .fill_modes = drm_helper_probe_single_connector_modes,
2832 .destroy = amdgpu_dm_connector_destroy,
2833 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2834 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2835 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2836 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2837};
2838
2839static struct drm_encoder *best_encoder(struct drm_connector *connector)
2840{
2841 int enc_id = connector->encoder_ids[0];
2842 struct drm_mode_object *obj;
2843 struct drm_encoder *encoder;
2844
f1ad2f5e 2845 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2846
2847 /* pick the encoder ids */
2848 if (enc_id) {
bd21a37d 2849 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2850 if (!obj) {
2851 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2852 return NULL;
2853 }
2854 encoder = obj_to_encoder(obj);
2855 return encoder;
2856 }
2857 DRM_ERROR("No encoder id\n");
2858 return NULL;
2859}
2860
2861static int get_modes(struct drm_connector *connector)
2862{
2863 return amdgpu_dm_connector_get_modes(connector);
2864}
2865
c84dec2f 2866static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2867{
2868 struct dc_sink_init_data init_params = {
2869 .link = aconnector->dc_link,
2870 .sink_signal = SIGNAL_TYPE_VIRTUAL
2871 };
70e8ffc5 2872 struct edid *edid;
e7b07cee 2873
a89ff457 2874 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 2875 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2876 aconnector->base.name);
2877
2878 aconnector->base.force = DRM_FORCE_OFF;
2879 aconnector->base.override_edid = false;
2880 return;
2881 }
2882
70e8ffc5
HW		 2883 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2884
e7b07cee
HW		 2885 aconnector->edid = edid;
2886
2887 aconnector->dc_em_sink = dc_link_add_remote_sink(
2888 aconnector->dc_link,
2889 (uint8_t *)edid,
2890 (edid->extensions + 1) * EDID_LENGTH,
2891 &init_params);
2892
a68d90e7 2893 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 2894 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2895 aconnector->dc_link->local_sink :
2896 aconnector->dc_em_sink;
2897}
2898
c84dec2f 2899static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2900{
2901 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2902
2903 /* In case of headless boot with force on for DP managed connector
2904 * Those settings have to be != 0 to get initial modeset
2905 */
2906 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2907 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2908 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2909 }
2910
2911
2912 aconnector->base.override_edid = true;
2913 create_eml_sink(aconnector);
2914}
2915
ba9ca088 2916enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 2917 struct drm_display_mode *mode)
e7b07cee
HW		 2918{
2919 int result = MODE_ERROR;
2920 struct dc_sink *dc_sink;
2921 struct amdgpu_device *adev = connector->dev->dev_private;
2922 /* TODO: Unhardcode stream count */
0971c40e 2923 struct dc_stream_state *stream;
c84dec2f 2924 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 2925 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 2926
2927 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2928 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2929 return result;
2930
2931 /* Only run this the first time mode_valid is called to initilialize
2932 * EDID mgmt
2933 */
2934 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2935 !aconnector->dc_em_sink)
2936 handle_edid_mgmt(aconnector);
2937
c84dec2f 2938 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2939
b830ebc9 2940 if (dc_sink == NULL) {
e7b07cee
HW		 2941 DRM_ERROR("dc_sink is NULL!\n");
2942 goto fail;
2943 }
2944
f4791779 2945 stream = create_stream_for_sink(aconnector, mode, NULL);
b830ebc9 2946 if (stream == NULL) {
e7b07cee
HW		 2947 DRM_ERROR("Failed to create stream for sink!\n");
2948 goto fail;
2949 }
2950
a39438f0
HW		 2951 dc_result = dc_validate_stream(adev->dm.dc, stream);
2952
2953 if (dc_result == DC_OK)
e7b07cee 2954 result = MODE_OK;
a39438f0 2955 else
9f921b14 2956 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 2957 mode->vdisplay,
2958 mode->hdisplay,
9f921b14
HW		 2959 mode->clock,
2960 dc_result);
e7b07cee
HW		 2961
2962 dc_stream_release(stream);
2963
2964fail:
2965 /* TODO: error handling*/
2966 return result;
2967}
2968
2969static const struct drm_connector_helper_funcs
2970amdgpu_dm_connector_helper_funcs = {
2971 /*
b830ebc9
HW		 2972 * If hotplug a second bigger display in FB Con mode, bigger resolution
2973 * modes will be filtered by drm_mode_validate_size(), and those modes
2974 * is missing after user start lightdm. So we need to renew modes list.
2975 * in get_modes call back, not just return the modes count
2976 */
e7b07cee
HW		 2977 .get_modes = get_modes,
2978 .mode_valid = amdgpu_dm_connector_mode_valid,
2979 .best_encoder = best_encoder
2980};
2981
2982static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2983{
2984}
2985
3ee6b26b
AD		 2986static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2987 struct drm_crtc_state *state)
e7b07cee
HW		 2988{
2989 struct amdgpu_device *adev = crtc->dev->dev_private;
2990 struct dc *dc = adev->dm.dc;
2991 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2992 int ret = -EINVAL;
2993
9b690ef3
BL		 2994 if (unlikely(!dm_crtc_state->stream &&
2995 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2996 WARN_ON(1);
2997 return ret;
2998 }
2999
3000 /* In some use cases, like reset, no stream is attached */
3001 if (!dm_crtc_state->stream)
3002 return 0;
3003
62c933f9 3004 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 3005 return 0;
3006
3007 return ret;
3008}
3009
3ee6b26b
AD		 3010static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3011 const struct drm_display_mode *mode,
3012 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 3013{
3014 return true;
3015}
3016
3017static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3018 .disable = dm_crtc_helper_disable,
3019 .atomic_check = dm_crtc_helper_atomic_check,
3020 .mode_fixup = dm_crtc_helper_mode_fixup
3021};
3022
3023static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3024{
3025
3026}
3027
3ee6b26b
AD		 3028static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3029 struct drm_crtc_state *crtc_state,
3030 struct drm_connector_state *conn_state)
e7b07cee
HW		 3031{
3032 return 0;
3033}
3034
3035const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3036 .disable = dm_encoder_helper_disable,
3037 .atomic_check = dm_encoder_helper_atomic_check
3038};
3039
3040static void dm_drm_plane_reset(struct drm_plane *plane)
3041{
3042 struct dm_plane_state *amdgpu_state = NULL;
3043
3044 if (plane->state)
3045 plane->funcs->atomic_destroy_state(plane, plane->state);
3046
3047 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d
TSD		 3048 WARN_ON(amdgpu_state == NULL);
3049
e7b07cee
HW		 3050 if (amdgpu_state) {
3051 plane->state = &amdgpu_state->base;
3052 plane->state->plane = plane;
3053 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 3054 }
e7b07cee
HW		 3055}
3056
3057static struct drm_plane_state *
3058dm_drm_plane_duplicate_state(struct drm_plane *plane)
3059{
3060 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3061
3062 old_dm_plane_state = to_dm_plane_state(plane->state);
3063 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3064 if (!dm_plane_state)
3065 return NULL;
3066
3067 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3068
3be5262e
HW		 3069 if (old_dm_plane_state->dc_state) {
3070 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3071 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 3072 }
3073
3074 return &dm_plane_state->base;
3075}
3076
3077void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 3078 struct drm_plane_state *state)
e7b07cee
HW		 3079{
3080 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3081
3be5262e
HW		 3082 if (dm_plane_state->dc_state)
3083 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 3084
0627bbd3 3085 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 3086}
3087
3088static const struct drm_plane_funcs dm_plane_funcs = {
3089 .update_plane = drm_atomic_helper_update_plane,
3090 .disable_plane = drm_atomic_helper_disable_plane,
3091 .destroy = drm_plane_cleanup,
3092 .reset = dm_drm_plane_reset,
3093 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3094 .atomic_destroy_state = dm_drm_plane_destroy_state,
3095};
3096
3ee6b26b
AD		 3097static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3098 struct drm_plane_state *new_state)
e7b07cee
HW		 3099{
3100 struct amdgpu_framebuffer *afb;
3101 struct drm_gem_object *obj;
5d43be0c 3102 struct amdgpu_device *adev;
e7b07cee 3103 struct amdgpu_bo *rbo;
56087b31 3104 uint64_t chroma_addr = 0;
e7b07cee
HW		 3105 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3106 unsigned int awidth;
5d43be0c
CK		 3107 uint32_t domain;
3108 int r;
e7b07cee
HW		 3109
3110 dm_plane_state_old = to_dm_plane_state(plane->state);
3111 dm_plane_state_new = to_dm_plane_state(new_state);
3112
3113 if (!new_state->fb) {
f1ad2f5e 3114 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3115 return 0;
3116 }
3117
3118 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 3119 obj = new_state->fb->obj[0];
e7b07cee 3120 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3121 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3122 r = amdgpu_bo_reserve(rbo, false);
3123 if (unlikely(r != 0))
3124 return r;
3125
5d43be0c 3126 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 3127 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 3128 else
3129 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3130
7b7c6c81 3131 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 3132 if (unlikely(r != 0)) {
30b7c614
HW		 3133 if (r != -ERESTARTSYS)
3134 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
bb812f1e 3135 amdgpu_bo_unreserve(rbo);
e7b07cee
HW		 3136 return r;
3137 }
3138
bb812f1e
JZ		 3139 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3140 if (unlikely(r != 0)) {
3141 amdgpu_bo_unpin(rbo);
3142 amdgpu_bo_unreserve(rbo);
3143 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 3144 return r;
3145 }
bb812f1e
JZ		 3146 amdgpu_bo_unreserve(rbo);
3147
7b7c6c81 3148 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 3149
3150 amdgpu_bo_ref(rbo);
3151
3be5262e
HW		 3152 if (dm_plane_state_new->dc_state &&
3153 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3154 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3155
3be5262e
HW		 3156 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3157 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3158 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 3159 } else {
3160 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3161 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3162 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3163 = lower_32_bits(afb->address);
56087b31
S		 3164 plane_state->address.video_progressive.luma_addr.high_part
3165 = upper_32_bits(afb->address);
35888630 3166 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3167 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3168 = lower_32_bits(chroma_addr);
3169 plane_state->address.video_progressive.chroma_addr.high_part
3170 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3171 }
3172 }
3173
e7b07cee
HW		 3174 return 0;
3175}
3176
3ee6b26b
AD		 3177static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3178 struct drm_plane_state *old_state)
e7b07cee
HW		 3179{
3180 struct amdgpu_bo *rbo;
e7b07cee
HW		 3181 int r;
3182
3183 if (!old_state->fb)
3184 return;
3185
e68d14dd 3186 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 3187 r = amdgpu_bo_reserve(rbo, false);
3188 if (unlikely(r)) {
3189 DRM_ERROR("failed to reserve rbo before unpin\n");
3190 return;
b830ebc9
HW		 3191 }
3192
3193 amdgpu_bo_unpin(rbo);
3194 amdgpu_bo_unreserve(rbo);
3195 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3196}
3197
7578ecda
AD		 3198static int dm_plane_atomic_check(struct drm_plane *plane,
3199 struct drm_plane_state *state)
cbd19488
AG		 3200{
3201 struct amdgpu_device *adev = plane->dev->dev_private;
3202 struct dc *dc = adev->dm.dc;
3203 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3204
3be5262e 3205 if (!dm_plane_state->dc_state)
9a3329b1 3206 return 0;
cbd19488 3207
a05bcff1
S		 3208 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3209 return -EINVAL;
3210
62c933f9 3211 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3212 return 0;
3213
3214 return -EINVAL;
3215}
3216
e7b07cee
HW		 3217static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3218 .prepare_fb = dm_plane_helper_prepare_fb,
3219 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3220 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3221};
3222
3223/*
3224 * TODO: these are currently initialized to rgb formats only.
3225 * For future use cases we should either initialize them dynamically based on
3226 * plane capabilities, or initialize this array to all formats, so internal drm
3227 * check will succeed, and let DC to implement proper check
3228 */
d90371b0 3229static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3230 DRM_FORMAT_RGB888,
3231 DRM_FORMAT_XRGB8888,
3232 DRM_FORMAT_ARGB8888,
3233 DRM_FORMAT_RGBA8888,
3234 DRM_FORMAT_XRGB2101010,
3235 DRM_FORMAT_XBGR2101010,
3236 DRM_FORMAT_ARGB2101010,
3237 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 3238 DRM_FORMAT_XBGR8888,
3239 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 3240};
3241
99d1abf8 3242static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3243 DRM_FORMAT_NV12,
3244 DRM_FORMAT_NV21,
3245};
3246
3247static const u32 cursor_formats[] = {
3248 DRM_FORMAT_ARGB8888
3249};
3250
7578ecda
AD		 3251static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3252 struct amdgpu_plane *aplane,
3253 unsigned long possible_crtcs)
e7b07cee
HW		 3254{
3255 int res = -EPERM;
3256
3257 switch (aplane->base.type) {
3258 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3259 res = drm_universal_plane_init(
3260 dm->adev->ddev,
3261 &aplane->base,
3262 possible_crtcs,
3263 &dm_plane_funcs,
3264 rgb_formats,
3265 ARRAY_SIZE(rgb_formats),
3266 NULL, aplane->base.type, NULL);
3267 break;
3268 case DRM_PLANE_TYPE_OVERLAY:
3269 res = drm_universal_plane_init(
3270 dm->adev->ddev,
3271 &aplane->base,
3272 possible_crtcs,
3273 &dm_plane_funcs,
3274 yuv_formats,
3275 ARRAY_SIZE(yuv_formats),
3276 NULL, aplane->base.type, NULL);
3277 break;
3278 case DRM_PLANE_TYPE_CURSOR:
3279 res = drm_universal_plane_init(
3280 dm->adev->ddev,
3281 &aplane->base,
3282 possible_crtcs,
3283 &dm_plane_funcs,
3284 cursor_formats,
3285 ARRAY_SIZE(cursor_formats),
3286 NULL, aplane->base.type, NULL);
3287 break;
3288 }
3289
3290 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3291
96719c54
HW		 3292 /* Create (reset) the plane state */
3293 if (aplane->base.funcs->reset)
3294 aplane->base.funcs->reset(&aplane->base);
3295
3296
e7b07cee
HW		 3297 return res;
3298}
3299
7578ecda
AD		 3300static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3301 struct drm_plane *plane,
3302 uint32_t crtc_index)
e7b07cee
HW		 3303{
3304 struct amdgpu_crtc *acrtc = NULL;
3305 struct amdgpu_plane *cursor_plane;
3306
3307 int res = -ENOMEM;
3308
3309 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3310 if (!cursor_plane)
3311 goto fail;
3312
3313 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3314 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3315
3316 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3317 if (!acrtc)
3318 goto fail;
3319
3320 res = drm_crtc_init_with_planes(
3321 dm->ddev,
3322 &acrtc->base,
3323 plane,
3324 &cursor_plane->base,
3325 &amdgpu_dm_crtc_funcs, NULL);
3326
3327 if (res)
3328 goto fail;
3329
3330 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3331
96719c54
HW		 3332 /* Create (reset) the plane state */
3333 if (acrtc->base.funcs->reset)
3334 acrtc->base.funcs->reset(&acrtc->base);
3335
e7b07cee
HW		 3336 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3337 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3338
3339 acrtc->crtc_id = crtc_index;
3340 acrtc->base.enabled = false;
3341
3342 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3343 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3344 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3345 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3346
3347 return 0;
3348
3349fail:
b830ebc9
HW		 3350 kfree(acrtc);
3351 kfree(cursor_plane);
e7b07cee
HW		 3352 return res;
3353}
3354
3355
3356static int to_drm_connector_type(enum signal_type st)
3357{
3358 switch (st) {
3359 case SIGNAL_TYPE_HDMI_TYPE_A:
3360 return DRM_MODE_CONNECTOR_HDMIA;
3361 case SIGNAL_TYPE_EDP:
3362 return DRM_MODE_CONNECTOR_eDP;
3363 case SIGNAL_TYPE_RGB:
3364 return DRM_MODE_CONNECTOR_VGA;
3365 case SIGNAL_TYPE_DISPLAY_PORT:
3366 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3367 return DRM_MODE_CONNECTOR_DisplayPort;
3368 case SIGNAL_TYPE_DVI_DUAL_LINK:
3369 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3370 return DRM_MODE_CONNECTOR_DVID;
3371 case SIGNAL_TYPE_VIRTUAL:
3372 return DRM_MODE_CONNECTOR_VIRTUAL;
3373
3374 default:
3375 return DRM_MODE_CONNECTOR_Unknown;
3376 }
3377}
3378
3379static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3380{
3381 const struct drm_connector_helper_funcs *helper =
3382 connector->helper_private;
3383 struct drm_encoder *encoder;
3384 struct amdgpu_encoder *amdgpu_encoder;
3385
3386 encoder = helper->best_encoder(connector);
3387
3388 if (encoder == NULL)
3389 return;
3390
3391 amdgpu_encoder = to_amdgpu_encoder(encoder);
3392
3393 amdgpu_encoder->native_mode.clock = 0;
3394
3395 if (!list_empty(&connector->probed_modes)) {
3396 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3397
e7b07cee 3398 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3399 &connector->probed_modes,
3400 head) {
3401 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3402 amdgpu_encoder->native_mode = *preferred_mode;
3403
e7b07cee
HW		 3404 break;
3405 }
3406
3407 }
3408}
3409
3ee6b26b
AD		 3410static struct drm_display_mode *
3411amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3412 char *name,
3413 int hdisplay, int vdisplay)
e7b07cee
HW		 3414{
3415 struct drm_device *dev = encoder->dev;
3416 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3417 struct drm_display_mode *mode = NULL;
3418 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3419
3420 mode = drm_mode_duplicate(dev, native_mode);
3421
b830ebc9 3422 if (mode == NULL)
e7b07cee
HW		 3423 return NULL;
3424
3425 mode->hdisplay = hdisplay;
3426 mode->vdisplay = vdisplay;
3427 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3428 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3429
3430 return mode;
3431
3432}
3433
3434static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3435 struct drm_connector *connector)
e7b07cee
HW		 3436{
3437 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3438 struct drm_display_mode *mode = NULL;
3439 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3440 struct amdgpu_dm_connector *amdgpu_dm_connector =
3441 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3442 int i;
3443 int n;
3444 struct mode_size {
3445 char name[DRM_DISPLAY_MODE_LEN];
3446 int w;
3447 int h;
b830ebc9 3448 } common_modes[] = {
e7b07cee
HW		 3449 { "640x480", 640, 480},
3450 { "800x600", 800, 600},
3451 { "1024x768", 1024, 768},
3452 { "1280x720", 1280, 720},
3453 { "1280x800", 1280, 800},
3454 {"1280x1024", 1280, 1024},
3455 { "1440x900", 1440, 900},
3456 {"1680x1050", 1680, 1050},
3457 {"1600x1200", 1600, 1200},
3458 {"1920x1080", 1920, 1080},
3459 {"1920x1200", 1920, 1200}
3460 };
3461
b830ebc9 3462 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3463
3464 for (i = 0; i < n; i++) {
3465 struct drm_display_mode *curmode = NULL;
3466 bool mode_existed = false;
3467
3468 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3469 common_modes[i].h > native_mode->vdisplay ||
3470 (common_modes[i].w == native_mode->hdisplay &&
3471 common_modes[i].h == native_mode->vdisplay))
3472 continue;
e7b07cee
HW		 3473
3474 list_for_each_entry(curmode, &connector->probed_modes, head) {
3475 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3476 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3477 mode_existed = true;
3478 break;
3479 }
3480 }
3481
3482 if (mode_existed)
3483 continue;
3484
3485 mode = amdgpu_dm_create_common_mode(encoder,
3486 common_modes[i].name, common_modes[i].w,
3487 common_modes[i].h);
3488 drm_mode_probed_add(connector, mode);
c84dec2f 3489 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3490 }
3491}
3492
3ee6b26b
AD		 3493static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3494 struct edid *edid)
e7b07cee 3495{
c84dec2f
HW		 3496 struct amdgpu_dm_connector *amdgpu_dm_connector =
3497 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3498
3499 if (edid) {
3500 /* empty probed_modes */
3501 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3502 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3503 drm_add_edid_modes(connector, edid);
3504
e7b07cee 3505 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3506 } else {
c84dec2f 3507 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3508 }
e7b07cee
HW		 3509}
3510
7578ecda 3511static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3512{
3513 const struct drm_connector_helper_funcs *helper =
3514 connector->helper_private;
c84dec2f
HW		 3515 struct amdgpu_dm_connector *amdgpu_dm_connector =
3516 to_amdgpu_dm_connector(connector);
e7b07cee 3517 struct drm_encoder *encoder;
c84dec2f 3518 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3519
3520 encoder = helper->best_encoder(connector);
3e332d3a 3521
85ee15d6 3522 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 3523 amdgpu_dm_connector->num_modes =
3524 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 3525 } else {
3526 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3527 amdgpu_dm_connector_add_common_modes(encoder, connector);
3528 }
3e332d3a 3529 amdgpu_dm_fbc_init(connector);
5099114b 3530
c84dec2f 3531 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3532}
3533
3ee6b26b
AD		 3534void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3535 struct amdgpu_dm_connector *aconnector,
3536 int connector_type,
3537 struct dc_link *link,
3538 int link_index)
e7b07cee
HW		 3539{
3540 struct amdgpu_device *adev = dm->ddev->dev_private;
3541
3542 aconnector->connector_id = link_index;
3543 aconnector->dc_link = link;
3544 aconnector->base.interlace_allowed = false;
3545 aconnector->base.doublescan_allowed = false;
3546 aconnector->base.stereo_allowed = false;
3547 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3548 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
e7b07cee
HW		 3549 mutex_init(&aconnector->hpd_lock);
3550
b830ebc9
HW		 3551 /* configure support HPD hot plug connector_>polled default value is 0
3552 * which means HPD hot plug not supported
3553 */
e7b07cee
HW		 3554 switch (connector_type) {
3555 case DRM_MODE_CONNECTOR_HDMIA:
3556 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c
JFZ		 3557 aconnector->base.ycbcr_420_allowed =
3558 link->link_enc->features.ycbcr420_supported ? true : false;
e7b07cee
HW		 3559 break;
3560 case DRM_MODE_CONNECTOR_DisplayPort:
3561 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c
JFZ		 3562 aconnector->base.ycbcr_420_allowed =
3563 link->link_enc->features.ycbcr420_supported ? true : false;
e7b07cee
HW		 3564 break;
3565 case DRM_MODE_CONNECTOR_DVID:
3566 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3567 break;
3568 default:
3569 break;
3570 }
3571
3572 drm_object_attach_property(&aconnector->base.base,
3573 dm->ddev->mode_config.scaling_mode_property,
3574 DRM_MODE_SCALE_NONE);
3575
3576 drm_object_attach_property(&aconnector->base.base,
3577 adev->mode_info.underscan_property,
3578 UNDERSCAN_OFF);
3579 drm_object_attach_property(&aconnector->base.base,
3580 adev->mode_info.underscan_hborder_property,
3581 0);
3582 drm_object_attach_property(&aconnector->base.base,
3583 adev->mode_info.underscan_vborder_property,
3584 0);
3585
3586}
3587
7578ecda
AD		 3588static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3589 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3590{
3591 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3592 struct ddc_service *ddc_service = i2c->ddc_service;
3593 struct i2c_command cmd;
3594 int i;
3595 int result = -EIO;
3596
b830ebc9 3597 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3598
3599 if (!cmd.payloads)
3600 return result;
3601
3602 cmd.number_of_payloads = num;
3603 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3604 cmd.speed = 100;
3605
3606 for (i = 0; i < num; i++) {
3607 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3608 cmd.payloads[i].address = msgs[i].addr;
3609 cmd.payloads[i].length = msgs[i].len;
3610 cmd.payloads[i].data = msgs[i].buf;
3611 }
3612
3613 if (dal_i2caux_submit_i2c_command(
3614 ddc_service->ctx->i2caux,
3615 ddc_service->ddc_pin,
3616 &cmd))
3617 result = num;
3618
3619 kfree(cmd.payloads);
3620 return result;
3621}
3622
7578ecda 3623static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3624{
3625 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3626}
3627
3628static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3629 .master_xfer = amdgpu_dm_i2c_xfer,
3630 .functionality = amdgpu_dm_i2c_func,
3631};
3632
3ee6b26b
AD		 3633static struct amdgpu_i2c_adapter *
3634create_i2c(struct ddc_service *ddc_service,
3635 int link_index,
3636 int *res)
e7b07cee
HW		 3637{
3638 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3639 struct amdgpu_i2c_adapter *i2c;
3640
b830ebc9 3641 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 3642 if (!i2c)
3643 return NULL;
e7b07cee
HW		 3644 i2c->base.owner = THIS_MODULE;
3645 i2c->base.class = I2C_CLASS_DDC;
3646 i2c->base.dev.parent = &adev->pdev->dev;
3647 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3648 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3649 i2c_set_adapdata(&i2c->base, i2c);
3650 i2c->ddc_service = ddc_service;
3651
3652 return i2c;
3653}
3654
89fc8d4e 3655
e7b07cee 3656/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3657 * dc_link which will be represented by this aconnector.
3658 */
7578ecda
AD		 3659static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3660 struct amdgpu_dm_connector *aconnector,
3661 uint32_t link_index,
3662 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3663{
3664 int res = 0;
3665 int connector_type;
3666 struct dc *dc = dm->dc;
3667 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3668 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 3669
3670 link->priv = aconnector;
e7b07cee 3671
f1ad2f5e 3672 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3673
3674 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 3675 if (!i2c) {
3676 DRM_ERROR("Failed to create i2c adapter data\n");
3677 return -ENOMEM;
3678 }
3679
e7b07cee
HW		 3680 aconnector->i2c = i2c;
3681 res = i2c_add_adapter(&i2c->base);
3682
3683 if (res) {
3684 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3685 goto out_free;
3686 }
3687
3688 connector_type = to_drm_connector_type(link->connector_signal);
3689
3690 res = drm_connector_init(
3691 dm->ddev,
3692 &aconnector->base,
3693 &amdgpu_dm_connector_funcs,
3694 connector_type);
3695
3696 if (res) {
3697 DRM_ERROR("connector_init failed\n");
3698 aconnector->connector_id = -1;
3699 goto out_free;
3700 }
3701
3702 drm_connector_helper_add(
3703 &aconnector->base,
3704 &amdgpu_dm_connector_helper_funcs);
3705
96719c54
HW		 3706 if (aconnector->base.funcs->reset)
3707 aconnector->base.funcs->reset(&aconnector->base);
3708
e7b07cee
HW		 3709 amdgpu_dm_connector_init_helper(
3710 dm,
3711 aconnector,
3712 connector_type,
3713 link,
3714 link_index);
3715
cde4c44d 3716 drm_connector_attach_encoder(
e7b07cee
HW		 3717 &aconnector->base, &aencoder->base);
3718
3719 drm_connector_register(&aconnector->base);
dc38fd9d
DF		 3720#if defined(CONFIG_DEBUG_FS)
3721 res = connector_debugfs_init(aconnector);
3722 if (res) {
3723 DRM_ERROR("Failed to create debugfs for connector");
3724 goto out_free;
3725 }
3726#endif
e7b07cee
HW		 3727
3728 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3729 || connector_type == DRM_MODE_CONNECTOR_eDP)
3730 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3731
e7b07cee
HW		 3732out_free:
3733 if (res) {
3734 kfree(i2c);
3735 aconnector->i2c = NULL;
3736 }
3737 return res;
3738}
3739
3740int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3741{
3742 switch (adev->mode_info.num_crtc) {
3743 case 1:
3744 return 0x1;
3745 case 2:
3746 return 0x3;
3747 case 3:
3748 return 0x7;
3749 case 4:
3750 return 0xf;
3751 case 5:
3752 return 0x1f;
3753 case 6:
3754 default:
3755 return 0x3f;
3756 }
3757}
3758
7578ecda
AD		 3759static int amdgpu_dm_encoder_init(struct drm_device *dev,
3760 struct amdgpu_encoder *aencoder,
3761 uint32_t link_index)
e7b07cee
HW		 3762{
3763 struct amdgpu_device *adev = dev->dev_private;
3764
3765 int res = drm_encoder_init(dev,
3766 &aencoder->base,
3767 &amdgpu_dm_encoder_funcs,
3768 DRM_MODE_ENCODER_TMDS,
3769 NULL);
3770
3771 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3772
3773 if (!res)
3774 aencoder->encoder_id = link_index;
3775 else
3776 aencoder->encoder_id = -1;
3777
3778 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3779
3780 return res;
3781}
3782
3ee6b26b
AD		 3783static void manage_dm_interrupts(struct amdgpu_device *adev,
3784 struct amdgpu_crtc *acrtc,
3785 bool enable)
e7b07cee
HW		 3786{
3787 /*
3788 * this is not correct translation but will work as soon as VBLANK
3789 * constant is the same as PFLIP
3790 */
3791 int irq_type =
734dd01d 3792 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 3793 adev,
3794 acrtc->crtc_id);
3795
3796 if (enable) {
3797 drm_crtc_vblank_on(&acrtc->base);
3798 amdgpu_irq_get(
3799 adev,
3800 &adev->pageflip_irq,
3801 irq_type);
3802 } else {
3803
3804 amdgpu_irq_put(
3805 adev,
3806 &adev->pageflip_irq,
3807 irq_type);
3808 drm_crtc_vblank_off(&acrtc->base);
3809 }
3810}
3811
3ee6b26b
AD		 3812static bool
3813is_scaling_state_different(const struct dm_connector_state *dm_state,
3814 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3815{
3816 if (dm_state->scaling != old_dm_state->scaling)
3817 return true;
3818 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3819 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3820 return true;
3821 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3822 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3823 return true;
b830ebc9
HW		 3824 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3825 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3826 return true;
e7b07cee
HW		 3827 return false;
3828}
3829
3ee6b26b
AD		 3830static void remove_stream(struct amdgpu_device *adev,
3831 struct amdgpu_crtc *acrtc,
3832 struct dc_stream_state *stream)
e7b07cee
HW		 3833{
3834 /* this is the update mode case */
e7b07cee
HW		 3835
3836 acrtc->otg_inst = -1;
3837 acrtc->enabled = false;
3838}
3839
7578ecda
AD		 3840static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3841 struct dc_cursor_position *position)
2a8f6ccb 3842{
f4c2cc43 3843 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 3844 int x, y;
3845 int xorigin = 0, yorigin = 0;
3846
3847 if (!crtc || !plane->state->fb) {
3848 position->enable = false;
3849 position->x = 0;
3850 position->y = 0;
3851 return 0;
3852 }
3853
3854 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3855 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3856 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3857 __func__,
3858 plane->state->crtc_w,
3859 plane->state->crtc_h);
3860 return -EINVAL;
3861 }
3862
3863 x = plane->state->crtc_x;
3864 y = plane->state->crtc_y;
3865 /* avivo cursor are offset into the total surface */
3866 x += crtc->primary->state->src_x >> 16;
3867 y += crtc->primary->state->src_y >> 16;
3868 if (x < 0) {
3869 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3870 x = 0;
3871 }
3872 if (y < 0) {
3873 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3874 y = 0;
3875 }
3876 position->enable = true;
3877 position->x = x;
3878 position->y = y;
3879 position->x_hotspot = xorigin;
3880 position->y_hotspot = yorigin;
3881
3882 return 0;
3883}
3884
3ee6b26b
AD		 3885static void handle_cursor_update(struct drm_plane *plane,
3886 struct drm_plane_state *old_plane_state)
e7b07cee 3887{
2a8f6ccb
HW		 3888 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3889 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3890 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3891 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3892 uint64_t address = afb ? afb->address : 0;
3893 struct dc_cursor_position position;
3894 struct dc_cursor_attributes attributes;
3895 int ret;
3896
e7b07cee
HW		 3897 if (!plane->state->fb && !old_plane_state->fb)
3898 return;
3899
f1ad2f5e 3900 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3901 __func__,
3902 amdgpu_crtc->crtc_id,
3903 plane->state->crtc_w,
3904 plane->state->crtc_h);
2a8f6ccb
HW		 3905
3906 ret = get_cursor_position(plane, crtc, &position);
3907 if (ret)
3908 return;
3909
3910 if (!position.enable) {
3911 /* turn off cursor */
3912 if (crtc_state && crtc_state->stream)
3913 dc_stream_set_cursor_position(crtc_state->stream,
3914 &position);
3915 return;
e7b07cee 3916 }
e7b07cee 3917
2a8f6ccb
HW		 3918 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3919 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3920
3921 attributes.address.high_part = upper_32_bits(address);
3922 attributes.address.low_part = lower_32_bits(address);
3923 attributes.width = plane->state->crtc_w;
3924 attributes.height = plane->state->crtc_h;
3925 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3926 attributes.rotation_angle = 0;
3927 attributes.attribute_flags.value = 0;
3928
3929 attributes.pitch = attributes.width;
3930
886daac9
JZ		 3931 if (crtc_state->stream) {
3932 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3933 &attributes))
3934 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3935
2a8f6ccb
HW		 3936 if (!dc_stream_set_cursor_position(crtc_state->stream,
3937 &position))
3938 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3939 }
2a8f6ccb 3940}
e7b07cee
HW		 3941
3942static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3943{
3944
3945 assert_spin_locked(&acrtc->base.dev->event_lock);
3946 WARN_ON(acrtc->event);
3947
3948 acrtc->event = acrtc->base.state->event;
3949
3950 /* Set the flip status */
3951 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3952
3953 /* Mark this event as consumed */
3954 acrtc->base.state->event = NULL;
3955
3956 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3957 acrtc->crtc_id);
3958}
3959
3960/*
3961 * Executes flip
3962 *
3963 * Waits on all BO's fences and for proper vblank count
3964 */
3ee6b26b
AD		 3965static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3966 struct drm_framebuffer *fb,
bc6828e0
BL		 3967 uint32_t target,
3968 struct dc_state *state)
e7b07cee
HW		 3969{
3970 unsigned long flags;
3971 uint32_t target_vblank;
3972 int r, vpos, hpos;
3973 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3974 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
e68d14dd 3975 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
e7b07cee 3976 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3977 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3978 struct dc_flip_addrs addr = { {0} };
3be5262e 3979 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3980 struct dc_surface_update surface_updates[1] = { {0} };
3981 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3982
3983
3984 /* Prepare wait for target vblank early - before the fence-waits */
23effc11 3985 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
e7b07cee
HW		 3986 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3987
b830ebc9 3988 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3989 * explicitly on fences instead
3990 * and in general should be called for
3991 * blocking commit to as per framework helpers
b830ebc9 3992 */
e7b07cee
HW		 3993 r = amdgpu_bo_reserve(abo, true);
3994 if (unlikely(r != 0)) {
3995 DRM_ERROR("failed to reserve buffer before flip\n");
3996 WARN_ON(1);
3997 }
3998
3999 /* Wait for all fences on this FB */
4000 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
4001 MAX_SCHEDULE_TIMEOUT) < 0);
4002
4003 amdgpu_bo_unreserve(abo);
4004
4005 /* Wait until we're out of the vertical blank period before the one
4006 * targeted by the flip
4007 */
4008 while ((acrtc->enabled &&
aa8e286a
SL		 4009 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
4010 0, &vpos, &hpos, NULL,
4011 NULL, &crtc->hwmode)
e7b07cee
HW		 4012 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4013 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4014 (int)(target_vblank -
4015 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
4016 usleep_range(1000, 1100);
4017 }
4018
4019 /* Flip */
4020 spin_lock_irqsave(&crtc->dev->event_lock, flags);
e7b07cee
HW		 4021
4022 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
4023 WARN_ON(!acrtc_state->stream);
4024
4025 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
4026 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
4027 addr.flip_immediate = async_flip;
4028
4029
4030 if (acrtc->base.state->event)
4031 prepare_flip_isr(acrtc);
4032
4de9f38b
S		 4033 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4034
3be5262e 4035 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 4036 surface_updates->flip_addr = &addr;
4037
bc6828e0
BL		 4038 dc_commit_updates_for_stream(adev->dm.dc,
4039 surface_updates,
4040 1,
4041 acrtc_state->stream,
4042 NULL,
4043 &surface_updates->surface,
4044 state);
e7b07cee
HW		 4045
4046 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
4047 __func__,
4048 addr.address.grph.addr.high_part,
4049 addr.address.grph.addr.low_part);
e7b07cee
HW		 4050}
4051
44d09c6a
HW		 4052/*
4053 * TODO this whole function needs to go
4054 *
4055 * dc_surface_update is needlessly complex. See if we can just replace this
4056 * with a dc_plane_state and follow the atomic model a bit more closely here.
4057 */
4058static bool commit_planes_to_stream(
4059 struct dc *dc,
4060 struct dc_plane_state **plane_states,
4061 uint8_t new_plane_count,
4062 struct dm_crtc_state *dm_new_crtc_state,
4063 struct dm_crtc_state *dm_old_crtc_state,
4064 struct dc_state *state)
4065{
4066 /* no need to dynamically allocate this. it's pretty small */
4067 struct dc_surface_update updates[MAX_SURFACES];
4068 struct dc_flip_addrs *flip_addr;
4069 struct dc_plane_info *plane_info;
4070 struct dc_scaling_info *scaling_info;
4071 int i;
4072 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
4073 struct dc_stream_update *stream_update =
4074 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
4075
4076 if (!stream_update) {
4077 BREAK_TO_DEBUGGER();
4078 return false;
4079 }
4080
4081 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
4082 GFP_KERNEL);
4083 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
4084 GFP_KERNEL);
4085 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
4086 GFP_KERNEL);
4087
4088 if (!flip_addr || !plane_info || !scaling_info) {
4089 kfree(flip_addr);
4090 kfree(plane_info);
4091 kfree(scaling_info);
4092 kfree(stream_update);
4093 return false;
4094 }
4095
4096 memset(updates, 0, sizeof(updates));
4097
4098 stream_update->src = dc_stream->src;
4099 stream_update->dst = dc_stream->dst;
4100 stream_update->out_transfer_func = dc_stream->out_transfer_func;
4101
98e6436d
AK		 4102 if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) {
4103 stream_update->vrr_infopacket = &dc_stream->vrr_infopacket;
4104 stream_update->adjust = &dc_stream->adjust;
4105 }
4106
44d09c6a
HW		 4107 for (i = 0; i < new_plane_count; i++) {
4108 updates[i].surface = plane_states[i];
4109 updates[i].gamma =
4110 (struct dc_gamma *)plane_states[i]->gamma_correction;
4111 updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4112 flip_addr[i].address = plane_states[i]->address;
4113 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4114 plane_info[i].color_space = plane_states[i]->color_space;
44d09c6a
HW		 4115 plane_info[i].format = plane_states[i]->format;
4116 plane_info[i].plane_size = plane_states[i]->plane_size;
4117 plane_info[i].rotation = plane_states[i]->rotation;
4118 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4119 plane_info[i].stereo_format = plane_states[i]->stereo_format;
4120 plane_info[i].tiling_info = plane_states[i]->tiling_info;
4121 plane_info[i].visible = plane_states[i]->visible;
4122 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4123 plane_info[i].dcc = plane_states[i]->dcc;
4124 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4125 scaling_info[i].src_rect = plane_states[i]->src_rect;
4126 scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4127 scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4128
4129 updates[i].flip_addr = &flip_addr[i];
4130 updates[i].plane_info = &plane_info[i];
4131 updates[i].scaling_info = &scaling_info[i];
4132 }
4133
4134 dc_commit_updates_for_stream(
4135 dc,
4136 updates,
4137 new_plane_count,
4138 dc_stream, stream_update, plane_states, state);
4139
4140 kfree(flip_addr);
4141 kfree(plane_info);
4142 kfree(scaling_info);
4143 kfree(stream_update);
4144 return true;
4145}
4146
3be5262e 4147static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 4148 struct drm_device *dev,
4149 struct amdgpu_display_manager *dm,
4150 struct drm_crtc *pcrtc,
4151 bool *wait_for_vblank)
e7b07cee
HW		 4152{
4153 uint32_t i;
4154 struct drm_plane *plane;
0bc9706d 4155 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 4156 struct dc_stream_state *dc_stream_attach;
3be5262e 4157 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 4158 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 4159 struct drm_crtc_state *new_pcrtc_state =
4160 drm_atomic_get_new_crtc_state(state, pcrtc);
4161 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 4162 struct dm_crtc_state *dm_old_crtc_state =
4163 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
bc6828e0 4164 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 4165 int planes_count = 0;
4166 unsigned long flags;
4167
4168 /* update planes when needed */
0bc9706d
LSL		 4169 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4170 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 4171 struct drm_crtc_state *new_crtc_state;
0bc9706d 4172 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 4173 bool pflip_needed;
54d76575 4174 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 4175
4176 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4177 handle_cursor_update(plane, old_plane_state);
4178 continue;
4179 }
4180
f5ba60fe
DD		 4181 if (!fb || !crtc || pcrtc != crtc)
4182 continue;
4183
4184 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4185 if (!new_crtc_state->active)
e7b07cee
HW		 4186 continue;
4187
4188 pflip_needed = !state->allow_modeset;
4189
4190 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4191 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 4192 DRM_ERROR("%s: acrtc %d, already busy\n",
4193 __func__,
4194 acrtc_attach->crtc_id);
b830ebc9 4195 /* In commit tail framework this cannot happen */
e7b07cee
HW		 4196 WARN_ON(1);
4197 }
4198 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4199
a2a330ad 4200 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
54d76575 4201 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 4202
54d76575 4203 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 4204
4205 dc_stream_attach = acrtc_state->stream;
4206 planes_count++;
4207
0bc9706d 4208 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 4209 /* Assume even ONE crtc with immediate flip means
4210 * entire can't wait for VBLANK
4211 * TODO Check if it's correct
4212 */
4213 *wait_for_vblank =
0bc9706d 4214 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 4215 false : true;
4216
4217 /* TODO: Needs rework for multiplane flip */
4218 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4219 drm_crtc_vblank_get(crtc);
4220
4221 amdgpu_dm_do_flip(
4222 crtc,
4223 fb,
23effc11 4224 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
bc6828e0 4225 dm_state->context);
e7b07cee
HW		 4226 }
4227
4228 }
4229
4230 if (planes_count) {
4231 unsigned long flags;
4232
0bc9706d 4233 if (new_pcrtc_state->event) {
e7b07cee
HW		 4234
4235 drm_crtc_vblank_get(pcrtc);
4236
4237 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4238 prepare_flip_isr(acrtc_attach);
4239 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4240 }
4241
98e6436d
AK		 4242 dc_stream_attach->adjust = acrtc_state->adjust;
4243 dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket;
44d09c6a
HW		 4244
4245 if (false == commit_planes_to_stream(dm->dc,
3be5262e
HW		 4246 plane_states_constructed,
4247 planes_count,
44d09c6a
HW		 4248 acrtc_state,
4249 dm_old_crtc_state,
bc6828e0 4250 dm_state->context))
3be5262e 4251 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4252 } else {
4253 /*TODO BUG Here should go disable planes on CRTC. */
4254 }
4255}
4256
27b3f4fc
LSL		 4257/**
4258 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4259 * @crtc_state: the DRM CRTC state
4260 * @stream_state: the DC stream state.
4261 *
4262 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4263 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4264 */
4265static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4266 struct dc_stream_state *stream_state)
4267{
4268 stream_state->mode_changed = crtc_state->mode_changed;
4269}
e7b07cee 4270
7578ecda
AD		 4271static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4272 struct drm_atomic_state *state,
4273 bool nonblock)
e7b07cee
HW		 4274{
4275 struct drm_crtc *crtc;
c2cea706 4276 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4277 struct amdgpu_device *adev = dev->dev_private;
4278 int i;
4279
4280 /*
4281 * We evade vblanks and pflips on crtc that
4282 * should be changed. We do it here to flush & disable
4283 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4284 * it will update crtc->dm_crtc_state->stream pointer which is used in
4285 * the ISRs.
4286 */
c2cea706 4287 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4288 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 4289 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4290
54d76575 4291 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 4292 manage_dm_interrupts(adev, acrtc, false);
4293 }
fc9e9920
S		 4294 /* Add check here for SoC's that support hardware cursor plane, to
4295 * unset legacy_cursor_update */
e7b07cee
HW		 4296
4297 return drm_atomic_helper_commit(dev, state, nonblock);
4298
4299 /*TODO Handle EINTR, reenable IRQ*/
4300}
4301
7578ecda 4302static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4303{
4304 struct drm_device *dev = state->dev;
4305 struct amdgpu_device *adev = dev->dev_private;
4306 struct amdgpu_display_manager *dm = &adev->dm;
4307 struct dm_atomic_state *dm_state;
4308 uint32_t i, j;
5cc6dcbd 4309 struct drm_crtc *crtc;
0bc9706d 4310 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4311 unsigned long flags;
4312 bool wait_for_vblank = true;
4313 struct drm_connector *connector;
c2cea706 4314 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4315 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 4316 int crtc_disable_count = 0;
e7b07cee
HW		 4317
4318 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4319
4320 dm_state = to_dm_atomic_state(state);
4321
4322 /* update changed items */
0bc9706d 4323 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4324 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4325
54d76575
LSL		 4326 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4327 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4328
f1ad2f5e 4329 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4330 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4331 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4332 "connectors_changed:%d\n",
4333 acrtc->crtc_id,
0bc9706d
LSL		 4334 new_crtc_state->enable,
4335 new_crtc_state->active,
4336 new_crtc_state->planes_changed,
4337 new_crtc_state->mode_changed,
4338 new_crtc_state->active_changed,
4339 new_crtc_state->connectors_changed);
e7b07cee 4340
27b3f4fc
LSL		 4341 /* Copy all transient state flags into dc state */
4342 if (dm_new_crtc_state->stream) {
4343 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4344 dm_new_crtc_state->stream);
4345 }
4346
e7b07cee
HW		 4347 /* handles headless hotplug case, updating new_state and
4348 * aconnector as needed
4349 */
4350
54d76575 4351 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4352
f1ad2f5e 4353 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4354
54d76575 4355 if (!dm_new_crtc_state->stream) {
e7b07cee 4356 /*
b830ebc9
HW		 4357 * this could happen because of issues with
4358 * userspace notifications delivery.
4359 * In this case userspace tries to set mode on
4360 * display which is disconnect in fact.
4361 * dc_sink in NULL in this case on aconnector.
4362 * We expect reset mode will come soon.
4363 *
4364 * This can also happen when unplug is done
4365 * during resume sequence ended
4366 *
4367 * In this case, we want to pretend we still
4368 * have a sink to keep the pipe running so that
4369 * hw state is consistent with the sw state
4370 */
f1ad2f5e 4371 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4372 __func__, acrtc->base.base.id);
4373 continue;
4374 }
4375
54d76575
LSL		 4376 if (dm_old_crtc_state->stream)
4377 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 4378
97028037
LP		 4379 pm_runtime_get_noresume(dev->dev);
4380
e7b07cee 4381 acrtc->enabled = true;
0bc9706d
LSL		 4382 acrtc->hw_mode = new_crtc_state->mode;
4383 crtc->hwmode = new_crtc_state->mode;
4384 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4385 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4386
4387 /* i.e. reset mode */
54d76575
LSL		 4388 if (dm_old_crtc_state->stream)
4389 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4390 }
4391 } /* for_each_crtc_in_state() */
4392
fa2123db
ML		 4393 if (dm_state->context) {
4394 dm_enable_per_frame_crtc_master_sync(dm_state->context);
608ac7bb 4395 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
fa2123db 4396 }
e7b07cee 4397
0bc9706d 4398 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4399 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4400
54d76575 4401 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4402
54d76575 4403 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4404 const struct dc_stream_status *status =
54d76575 4405 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4406
4407 if (!status)
54d76575 4408 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4409 else
4410 acrtc->otg_inst = status->primary_otg_inst;
4411 }
4412 }
4413
ebdd27e1 4414 /* Handle scaling and underscan changes*/
c2cea706 4415 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4416 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4417 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4418 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4419 struct dc_stream_status *status = NULL;
4420
44d09c6a 4421 if (acrtc) {
0bc9706d 4422 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 4423 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
4424 }
0bc9706d 4425
e7b07cee 4426 /* Skip any modesets/resets */
0bc9706d 4427 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4428 continue;
4429
4430 /* Skip any thing not scale or underscan changes */
54d76575 4431 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4432 continue;
4433
54d76575 4434 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4435
54d76575
LSL		 4436 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4437 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4438
70e8ffc5
HW		 4439 if (!dm_new_crtc_state->stream)
4440 continue;
4441
54d76575 4442 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4443 WARN_ON(!status);
3be5262e 4444 WARN_ON(!status->plane_count);
e7b07cee 4445
98e6436d
AK		 4446 dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust;
4447 dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket;
4448
e7b07cee 4449 /*TODO How it works with MPO ?*/
44d09c6a 4450 if (!commit_planes_to_stream(
e7b07cee 4451 dm->dc,
3be5262e
HW		 4452 status->plane_states,
4453 status->plane_count,
44d09c6a
HW		 4454 dm_new_crtc_state,
4455 to_dm_crtc_state(old_crtc_state),
bc6828e0 4456 dm_state->context))
e7b07cee
HW		 4457 dm_error("%s: Failed to update stream scaling!\n", __func__);
4458 }
4459
e1fc2dca
LSL		 4460 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4461 new_crtc_state, i) {
e7b07cee
HW		 4462 /*
4463 * loop to enable interrupts on newly arrived crtc
4464 */
e1fc2dca
LSL		 4465 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4466 bool modeset_needed;
b830ebc9 4467
fe2a1965
LP		 4468 if (old_crtc_state->active && !new_crtc_state->active)
4469 crtc_disable_count++;
4470
54d76575 4471 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 4472 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4473 modeset_needed = modeset_required(
4474 new_crtc_state,
4475 dm_new_crtc_state->stream,
4476 dm_old_crtc_state->stream);
4477
4478 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4479 continue;
e7b07cee 4480
e7b07cee
HW		 4481 manage_dm_interrupts(adev, acrtc, true);
4482 }
4483
4484 /* update planes when needed per crtc*/
5cc6dcbd 4485 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4486 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4487
54d76575 4488 if (dm_new_crtc_state->stream)
5cc6dcbd 4489 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4490 }
4491
4492
4493 /*
4494 * send vblank event on all events not handled in flip and
4495 * mark consumed event for drm_atomic_helper_commit_hw_done
4496 */
4497 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4498 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4499
0bc9706d
LSL		 4500 if (new_crtc_state->event)
4501 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4502
0bc9706d 4503 new_crtc_state->event = NULL;
e7b07cee
HW		 4504 }
4505 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4506
4507 /* Signal HW programming completion */
4508 drm_atomic_helper_commit_hw_done(state);
4509
4510 if (wait_for_vblank)
320a1274 4511 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 4512
4513 drm_atomic_helper_cleanup_planes(dev, state);
97028037
LP		 4514
4515 /* Finally, drop a runtime PM reference for each newly disabled CRTC,
4516 * so we can put the GPU into runtime suspend if we're not driving any
4517 * displays anymore
4518 */
fe2a1965
LP		 4519 for (i = 0; i < crtc_disable_count; i++)
4520 pm_runtime_put_autosuspend(dev->dev);
97028037 4521 pm_runtime_mark_last_busy(dev->dev);
e7b07cee
HW		 4522}
4523
4524
4525static int dm_force_atomic_commit(struct drm_connector *connector)
4526{
4527 int ret = 0;
4528 struct drm_device *ddev = connector->dev;
4529 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4530 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4531 struct drm_plane *plane = disconnected_acrtc->base.primary;
4532 struct drm_connector_state *conn_state;
4533 struct drm_crtc_state *crtc_state;
4534 struct drm_plane_state *plane_state;
4535
4536 if (!state)
4537 return -ENOMEM;
4538
4539 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4540
4541 /* Construct an atomic state to restore previous display setting */
4542
4543 /*
4544 * Attach connectors to drm_atomic_state
4545 */
4546 conn_state = drm_atomic_get_connector_state(state, connector);
4547
4548 ret = PTR_ERR_OR_ZERO(conn_state);
4549 if (ret)
4550 goto err;
4551
4552 /* Attach crtc to drm_atomic_state*/
4553 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4554
4555 ret = PTR_ERR_OR_ZERO(crtc_state);
4556 if (ret)
4557 goto err;
4558
4559 /* force a restore */
4560 crtc_state->mode_changed = true;
4561
4562 /* Attach plane to drm_atomic_state */
4563 plane_state = drm_atomic_get_plane_state(state, plane);
4564
4565 ret = PTR_ERR_OR_ZERO(plane_state);
4566 if (ret)
4567 goto err;
4568
4569
4570 /* Call commit internally with the state we just constructed */
4571 ret = drm_atomic_commit(state);
4572 if (!ret)
4573 return 0;
4574
4575err:
4576 DRM_ERROR("Restoring old state failed with %i\n", ret);
4577 drm_atomic_state_put(state);
4578
4579 return ret;
4580}
4581
4582/*
4583 * This functions handle all cases when set mode does not come upon hotplug.
4584 * This include when the same display is unplugged then plugged back into the
4585 * same port and when we are running without usermode desktop manager supprot
4586 */
3ee6b26b
AD		 4587void dm_restore_drm_connector_state(struct drm_device *dev,
4588 struct drm_connector *connector)
e7b07cee 4589{
c84dec2f 4590 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4591 struct amdgpu_crtc *disconnected_acrtc;
4592 struct dm_crtc_state *acrtc_state;
4593
4594 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4595 return;
4596
4597 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 4598 if (!disconnected_acrtc)
4599 return;
e7b07cee 4600
70e8ffc5
HW		 4601 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4602 if (!acrtc_state->stream)
e7b07cee
HW		 4603 return;
4604
4605 /*
4606 * If the previous sink is not released and different from the current,
4607 * we deduce we are in a state where we can not rely on usermode call
4608 * to turn on the display, so we do it here
4609 */
4610 if (acrtc_state->stream->sink != aconnector->dc_sink)
4611 dm_force_atomic_commit(&aconnector->base);
4612}
4613
e7b07cee
HW		 4614/*`
4615 * Grabs all modesetting locks to serialize against any blocking commits,
4616 * Waits for completion of all non blocking commits.
4617 */
3ee6b26b
AD		 4618static int do_aquire_global_lock(struct drm_device *dev,
4619 struct drm_atomic_state *state)
e7b07cee
HW		 4620{
4621 struct drm_crtc *crtc;
4622 struct drm_crtc_commit *commit;
4623 long ret;
4624
4625 /* Adding all modeset locks to aquire_ctx will
4626 * ensure that when the framework release it the
4627 * extra locks we are locking here will get released to
4628 */
4629 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4630 if (ret)
4631 return ret;
4632
4633 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4634 spin_lock(&crtc->commit_lock);
4635 commit = list_first_entry_or_null(&crtc->commit_list,
4636 struct drm_crtc_commit, commit_entry);
4637 if (commit)
4638 drm_crtc_commit_get(commit);
4639 spin_unlock(&crtc->commit_lock);
4640
4641 if (!commit)
4642 continue;
4643
4644 /* Make sure all pending HW programming completed and
4645 * page flips done
4646 */
4647 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4648
4649 if (ret > 0)
4650 ret = wait_for_completion_interruptible_timeout(
4651 &commit->flip_done, 10*HZ);
4652
4653 if (ret == 0)
4654 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4655 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4656
4657 drm_crtc_commit_put(commit);
4658 }
4659
4660 return ret < 0 ? ret : 0;
4661}
4662
98e6436d
AK		 4663void set_freesync_on_stream(struct amdgpu_display_manager *dm,
4664 struct dm_crtc_state *new_crtc_state,
4665 struct dm_connector_state *new_con_state,
4666 struct dc_stream_state *new_stream)
4667{
4668 struct mod_freesync_config config = {0};
4669 struct mod_vrr_params vrr = {0};
4670 struct dc_info_packet vrr_infopacket = {0};
4671 struct amdgpu_dm_connector *aconnector =
4672 to_amdgpu_dm_connector(new_con_state->base.connector);
4673
4674 if (new_con_state->freesync_capable &&
4675 new_con_state->freesync_enable) {
4676 config.state = new_crtc_state->freesync_enabled ?
4677 VRR_STATE_ACTIVE_VARIABLE :
4678 VRR_STATE_INACTIVE;
4679 config.min_refresh_in_uhz =
4680 aconnector->min_vfreq * 1000000;
4681 config.max_refresh_in_uhz =
4682 aconnector->max_vfreq * 1000000;
69ff8845 4683 config.vsif_supported = true;
98e6436d
AK		 4684 }
4685
4686 mod_freesync_build_vrr_params(dm->freesync_module,
4687 new_stream,
4688 &config, &vrr);
4689
4690 mod_freesync_build_vrr_infopacket(dm->freesync_module,
4691 new_stream,
4692 &vrr,
4693 &vrr_infopacket);
4694
4695 new_crtc_state->adjust = vrr.adjust;
4696 new_crtc_state->vrr_infopacket = vrr_infopacket;
4697}
4698
4699static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
3ee6b26b
AD		 4700 struct drm_atomic_state *state,
4701 bool enable,
4702 bool *lock_and_validation_needed)
e7b07cee 4703{
e7b07cee 4704 struct drm_crtc *crtc;
c2cea706 4705 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4706 int i;
54d76575 4707 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4708 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4709 struct dc_stream_state *new_stream;
62f55537 4710 int ret = 0;
d4d4a645 4711
62f55537
AG		 4712 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4713 /* update changed items */
c2cea706 4714 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4715 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4716 struct amdgpu_dm_connector *aconnector = NULL;
a9e8d275
DF		 4717 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
4718 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
f2877656 4719 struct drm_plane_state *new_plane_state = NULL;
e7b07cee 4720
9635b754
DS		 4721 new_stream = NULL;
4722
54d76575
LSL		 4723 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4724 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4725 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4726
f2877656
HW		 4727 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
4728
4729 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
4730 ret = -EINVAL;
4731 goto fail;
4732 }
4733
1daf8c63 4734 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4735
62f55537 4736 /* TODO This hack should go away */
f4ac176e
JZ		 4737 if (aconnector && enable) {
4738 // Make sure fake sink is created in plug-in scenario
a9e8d275 4739 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
c2cea706 4740 &aconnector->base);
a9e8d275
DF		 4741 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
4742 &aconnector->base);
19f89e23 4743
a9e8d275
DF		 4744 if (IS_ERR(drm_new_conn_state)) {
4745 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
62f55537
AG		 4746 break;
4747 }
19f89e23 4748
a9e8d275
DF		 4749 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
4750 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 4751
62f55537 4752 new_stream = create_stream_for_sink(aconnector,
c2cea706 4753 &new_crtc_state->mode,
a9e8d275 4754 dm_new_conn_state);
19f89e23 4755
62f55537
AG		 4756 /*
4757 * we can have no stream on ACTION_SET if a display
4758 * was disconnected during S3, in this case it not and
4759 * error, the OS will be updated after detection, and
4760 * do the right thing on next atomic commit
4761 */
19f89e23 4762
62f55537 4763 if (!new_stream) {
f1ad2f5e 4764 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4765 __func__, acrtc->base.base.id);
4766 break;
19f89e23 4767 }
e7b07cee 4768
98e6436d
AK		 4769 set_freesync_on_stream(dm, dm_new_crtc_state,
4770 dm_new_conn_state, new_stream);
4771
a97599a4
LSL		 4772 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4773 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4774 new_crtc_state->mode_changed = false;
4775 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4776 new_crtc_state->mode_changed);
4777 }
62f55537 4778 }
b830ebc9 4779
98e6436d
AK		 4780 if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled)
4781 new_crtc_state->mode_changed = true;
4782
c2cea706 4783 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4784 goto next_crtc;
e7b07cee 4785
f1ad2f5e 4786 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4787 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4788 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4789 "connectors_changed:%d\n",
4790 acrtc->crtc_id,
c2cea706
LSL		 4791 new_crtc_state->enable,
4792 new_crtc_state->active,
4793 new_crtc_state->planes_changed,
4794 new_crtc_state->mode_changed,
4795 new_crtc_state->active_changed,
4796 new_crtc_state->connectors_changed);
e7b07cee 4797
62f55537
AG		 4798 /* Remove stream for any changed/disabled CRTC */
4799 if (!enable) {
4800
54d76575 4801 if (!dm_old_crtc_state->stream)
9635b754 4802 goto next_crtc;
62f55537 4803
f1ad2f5e 4804 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4805 crtc->base.id);
e7b07cee 4806
1dc90497 4807 /* i.e. reset mode */
62c933f9 4808 if (dc_remove_stream_from_ctx(
98e6436d 4809 dm->dc,
62f55537 4810 dm_state->context,
62c933f9 4811 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4812 ret = -EINVAL;
9635b754 4813 goto fail;
62f55537
AG		 4814 }
4815
54d76575
LSL		 4816 dc_stream_release(dm_old_crtc_state->stream);
4817 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4818
4819 *lock_and_validation_needed = true;
4820
4821 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4822 /*
4823 * Quick fix to prevent NULL pointer on new_stream when
4824 * added MST connectors not found in existing crtc_state in the chained mode
4825 * TODO: need to dig out the root cause of that
4826 */
4827 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4828 goto next_crtc;
62f55537 4829
c2cea706 4830 if (modereset_required(new_crtc_state))
9635b754 4831 goto next_crtc;
62f55537 4832
c2cea706 4833 if (modeset_required(new_crtc_state, new_stream,
54d76575 4834 dm_old_crtc_state->stream)) {
62f55537 4835
54d76575 4836 WARN_ON(dm_new_crtc_state->stream);
62f55537 4837
54d76575 4838 dm_new_crtc_state->stream = new_stream;
27b3f4fc 4839
62f55537
AG		 4840 dc_stream_retain(new_stream);
4841
f1ad2f5e 4842 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4843 crtc->base.id);
1dc90497 4844
13ab1b44 4845 if (dc_add_stream_to_ctx(
98e6436d 4846 dm->dc,
1dc90497 4847 dm_state->context,
13ab1b44 4848 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4849 ret = -EINVAL;
9635b754 4850 goto fail;
1dc90497
AG		 4851 }
4852
62f55537 4853 *lock_and_validation_needed = true;
9b690ef3 4854 }
62f55537 4855 }
9b690ef3 4856
9635b754 4857next_crtc:
62f55537
AG		 4858 /* Release extra reference */
4859 if (new_stream)
4860 dc_stream_release(new_stream);
e277adc5
LSL		 4861
4862 /*
4863 * We want to do dc stream updates that do not require a
4864 * full modeset below.
4865 */
20fa2ff0
LSL		 4866 if (!(enable && aconnector && new_crtc_state->enable &&
4867 new_crtc_state->active))
e277adc5
LSL		 4868 continue;
4869 /*
4870 * Given above conditions, the dc state cannot be NULL because:
20fa2ff0
LSL		 4871 * 1. We're in the process of enabling CRTCs (just been added
4872 * to the dc context, or already is on the context)
4873 * 2. Has a valid connector attached, and
4874 * 3. Is currently active and enabled.
4875 * => The dc stream state currently exists.
e277adc5
LSL		 4876 */
4877 BUG_ON(dm_new_crtc_state->stream == NULL);
4878
a9e8d275
DF		 4879 /* Scaling or underscan settings */
4880 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
4881 update_stream_scaling_settings(
4882 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
4883
bc13f2f8
LSL		 4884 /*
4885 * Color management settings. We also update color properties
4886 * when a modeset is needed, to ensure it gets reprogrammed.
4887 */
4888 if (dm_new_crtc_state->base.color_mgmt_changed ||
4889 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
e277adc5
LSL		 4890 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
4891 if (ret)
4892 goto fail;
4893 amdgpu_dm_set_ctm(dm_new_crtc_state);
4894 }
98e6436d
AK		 4895
4896
62f55537 4897 }
e7b07cee 4898
62f55537 4899 return ret;
9635b754
DS		 4900
4901fail:
4902 if (new_stream)
4903 dc_stream_release(new_stream);
4904 return ret;
62f55537 4905}
9b690ef3 4906
3ee6b26b
AD		 4907static int dm_update_planes_state(struct dc *dc,
4908 struct drm_atomic_state *state,
4909 bool enable,
4910 bool *lock_and_validation_needed)
62f55537
AG		 4911{
4912 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4913 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4914 struct drm_plane *plane;
4915 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4916 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4917 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4918 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4919 int i ;
4920 /* TODO return page_flip_needed() function */
4921 bool pflip_needed = !state->allow_modeset;
4922 int ret = 0;
e7b07cee 4923
9b690ef3 4924
df534fff
S		 4925 /* Add new planes, in reverse order as DC expectation */
4926 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
62f55537
AG		 4927 new_plane_crtc = new_plane_state->crtc;
4928 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4929 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4930 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4931
4932 /*TODO Implement atomic check for cursor plane */
4933 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4934 continue;
9b690ef3 4935
62f55537
AG		 4936 /* Remove any changed/removed planes */
4937 if (!enable) {
a2a330ad
S		 4938 if (pflip_needed &&
4939 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 4940 continue;
a7b06724 4941
62f55537
AG		 4942 if (!old_plane_crtc)
4943 continue;
4944
0bc9706d
LSL		 4945 old_crtc_state = drm_atomic_get_old_crtc_state(
4946 state, old_plane_crtc);
54d76575 4947 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4948
54d76575 4949 if (!dm_old_crtc_state->stream)
62f55537
AG		 4950 continue;
4951
f2877656 4952 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4953 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4954
62f55537
AG		 4955 if (!dc_remove_plane_from_context(
4956 dc,
54d76575
LSL		 4957 dm_old_crtc_state->stream,
4958 dm_old_plane_state->dc_state,
62f55537
AG		 4959 dm_state->context)) {
4960
4961 ret = EINVAL;
4962 return ret;
e7b07cee
HW		 4963 }
4964
9b690ef3 4965
54d76575
LSL		 4966 dc_plane_state_release(dm_old_plane_state->dc_state);
4967 dm_new_plane_state->dc_state = NULL;
1dc90497 4968
62f55537 4969 *lock_and_validation_needed = true;
1dc90497 4970
62f55537 4971 } else { /* Add new planes */
8c45c5db 4972 struct dc_plane_state *dc_new_plane_state;
1dc90497 4973
62f55537
AG		 4974 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4975 continue;
e7b07cee 4976
62f55537
AG		 4977 if (!new_plane_crtc)
4978 continue;
e7b07cee 4979
62f55537 4980 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4981 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4982
54d76575 4983 if (!dm_new_crtc_state->stream)
62f55537
AG		 4984 continue;
4985
a2a330ad
S		 4986 if (pflip_needed &&
4987 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 4988 continue;
62f55537 4989
54d76575 4990 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4991
8c45c5db 4992 dc_new_plane_state = dc_create_plane_state(dc);
d5400aab
LSL		 4993 if (!dc_new_plane_state)
4994 return -ENOMEM;
62f55537 4995
8c45c5db
LSL		 4996 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4997 plane->base.id, new_plane_crtc->base.id);
4998
62f55537
AG		 4999 ret = fill_plane_attributes(
5000 new_plane_crtc->dev->dev_private,
8c45c5db 5001 dc_new_plane_state,
62f55537 5002 new_plane_state,
9817d5f5 5003 new_crtc_state);
8c45c5db
LSL		 5004 if (ret) {
5005 dc_plane_state_release(dc_new_plane_state);
62f55537 5006 return ret;
8c45c5db 5007 }
62f55537 5008
8c45c5db
LSL		 5009 /*
5010 * Any atomic check errors that occur after this will
5011 * not need a release. The plane state will be attached
5012 * to the stream, and therefore part of the atomic
5013 * state. It'll be released when the atomic state is
5014 * cleaned.
5015 */
62f55537
AG		 5016 if (!dc_add_plane_to_context(
5017 dc,
54d76575 5018 dm_new_crtc_state->stream,
8c45c5db 5019 dc_new_plane_state,
62f55537
AG		 5020 dm_state->context)) {
5021
8c45c5db 5022 dc_plane_state_release(dc_new_plane_state);
d5400aab 5023 return -EINVAL;
e7b07cee 5024 }
62f55537 5025
8c45c5db
LSL		 5026 dm_new_plane_state->dc_state = dc_new_plane_state;
5027
000b59ea
LSL		 5028 /* Tell DC to do a full surface update every time there
5029 * is a plane change. Inefficient, but works for now.
5030 */
5031 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5032
62f55537 5033 *lock_and_validation_needed = true;
e7b07cee 5034 }
62f55537 5035 }
e7b07cee
HW		 5036
5037
62f55537
AG		 5038 return ret;
5039}
5040
7578ecda
AD		 5041static int amdgpu_dm_atomic_check(struct drm_device *dev,
5042 struct drm_atomic_state *state)
62f55537 5043{
62f55537
AG		 5044 struct amdgpu_device *adev = dev->dev_private;
5045 struct dc *dc = adev->dm.dc;
5046 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
5047 struct drm_connector *connector;
c2cea706 5048 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 5049 struct drm_crtc *crtc;
fc9e9920 5050 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1e88ad0a 5051 int ret, i;
e7b07cee 5052
62f55537
AG		 5053 /*
5054 * This bool will be set for true for any modeset/reset
5055 * or plane update which implies non fast surface update.
5056 */
5057 bool lock_and_validation_needed = false;
5058
5059 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 5060 if (ret)
5061 goto fail;
62f55537 5062
1e88ad0a 5063 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
98e6436d
AK		 5064 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5065 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5066
1e88ad0a 5067 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d
AK		 5068 !new_crtc_state->color_mgmt_changed &&
5069 (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled))
1e88ad0a 5070 continue;
7bef1af3 5071
1e88ad0a
S		 5072 if (!new_crtc_state->enable)
5073 continue;
fc9e9920 5074
1e88ad0a
S		 5075 ret = drm_atomic_add_affected_connectors(state, crtc);
5076 if (ret)
5077 return ret;
fc9e9920 5078
1e88ad0a
S		 5079 ret = drm_atomic_add_affected_planes(state, crtc);
5080 if (ret)
5081 goto fail;
e7b07cee
HW		 5082 }
5083
62f55537
AG		 5084 dm_state->context = dc_create_state();
5085 ASSERT(dm_state->context);
f36cc577 5086 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 5087
5088 /* Remove exiting planes if they are modified */
5089 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
5090 if (ret) {
5091 goto fail;
5092 }
5093
5094 /* Disable all crtcs which require disable */
98e6436d 5095 ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed);
62f55537
AG		 5096 if (ret) {
5097 goto fail;
5098 }
5099
5100 /* Enable all crtcs which require enable */
98e6436d 5101 ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed);
62f55537
AG		 5102 if (ret) {
5103 goto fail;
5104 }
5105
5106 /* Add new/modified planes */
5107 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
5108 if (ret) {
5109 goto fail;
5110 }
5111
b349f76e
ES		 5112 /* Run this here since we want to validate the streams we created */
5113 ret = drm_atomic_helper_check_planes(dev, state);
5114 if (ret)
5115 goto fail;
62f55537 5116
ebdd27e1 5117 /* Check scaling and underscan changes*/
e7b07cee
HW		 5118 /*TODO Removed scaling changes validation due to inability to commit
5119 * new stream into context w\o causing full reset. Need to
5120 * decide how to handle.
5121 */
c2cea706 5122 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5123 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5124 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5125 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 5126
5127 /* Skip any modesets/resets */
0bc9706d
LSL		 5128 if (!acrtc || drm_atomic_crtc_needs_modeset(
5129 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 5130 continue;
5131
b830ebc9 5132 /* Skip any thing not scale or underscan changes */
54d76575 5133 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 5134 continue;
5135
5136 lock_and_validation_needed = true;
5137 }
5138
e7b07cee
HW		 5139 /*
5140 * For full updates case when
5141 * removing/adding/updating streams on once CRTC while flipping
5142 * on another CRTC,
5143 * acquiring global lock will guarantee that any such full
5144 * update commit
5145 * will wait for completion of any outstanding flip using DRMs
5146 * synchronization events.
5147 */
5148
5149 if (lock_and_validation_needed) {
5150
5151 ret = do_aquire_global_lock(dev, state);
5152 if (ret)
5153 goto fail;
1dc90497 5154
e750d56d 5155 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 5156 ret = -EINVAL;
5157 goto fail;
5158 }
5159 }
5160
5161 /* Must be success */
5162 WARN_ON(ret);
5163 return ret;
5164
5165fail:
5166 if (ret == -EDEADLK)
01e28f9c 5167 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 5168 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 5169 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 5170 else
01e28f9c 5171 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 5172
5173 return ret;
5174}
5175
3ee6b26b
AD		 5176static bool is_dp_capable_without_timing_msa(struct dc *dc,
5177 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 5178{
5179 uint8_t dpcd_data;
5180 bool capable = false;
5181
c84dec2f 5182 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 5183 dm_helpers_dp_read_dpcd(
5184 NULL,
c84dec2f 5185 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 5186 DP_DOWN_STREAM_PORT_COUNT,
5187 &dpcd_data,
5188 sizeof(dpcd_data))) {
5189 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
5190 }
5191
5192 return capable;
5193}
98e6436d
AK		 5194void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
5195 struct edid *edid)
e7b07cee
HW		 5196{
5197 int i;
e7b07cee
HW		 5198 bool edid_check_required;
5199 struct detailed_timing *timing;
5200 struct detailed_non_pixel *data;
5201 struct detailed_data_monitor_range *range;
c84dec2f
HW		 5202 struct amdgpu_dm_connector *amdgpu_dm_connector =
5203 to_amdgpu_dm_connector(connector);
8218d7f1 5204 struct dm_connector_state *dm_con_state;
e7b07cee
HW		 5205
5206 struct drm_device *dev = connector->dev;
5207 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 5208
8218d7f1
HW		 5209 if (!connector->state) {
5210 DRM_ERROR("%s - Connector has no state", __func__);
5211 return;
5212 }
5213
98e6436d
AK		 5214 if (!edid) {
5215 dm_con_state = to_dm_connector_state(connector->state);
5216
5217 amdgpu_dm_connector->min_vfreq = 0;
5218 amdgpu_dm_connector->max_vfreq = 0;
5219 amdgpu_dm_connector->pixel_clock_mhz = 0;
5220
5221 dm_con_state->freesync_capable = false;
5222 dm_con_state->freesync_enable = false;
5223 return;
5224 }
5225
8218d7f1
HW		 5226 dm_con_state = to_dm_connector_state(connector->state);
5227
e7b07cee 5228 edid_check_required = false;
c84dec2f 5229 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 5230 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
5231 return;
5232 }
5233 if (!adev->dm.freesync_module)
5234 return;
5235 /*
5236 * if edid non zero restrict freesync only for dp and edp
5237 */
5238 if (edid) {
c84dec2f
HW		 5239 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
5240 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 5241 edid_check_required = is_dp_capable_without_timing_msa(
5242 adev->dm.dc,
c84dec2f 5243 amdgpu_dm_connector);
e7b07cee
HW		 5244 }
5245 }
8218d7f1 5246 dm_con_state->freesync_capable = false;
e7b07cee
HW		 5247 if (edid_check_required == true && (edid->version > 1 ||
5248 (edid->version == 1 && edid->revision > 1))) {
5249 for (i = 0; i < 4; i++) {
5250
5251 timing = &edid->detailed_timings[i];
5252 data = &timing->data.other_data;
5253 range = &data->data.range;
5254 /*
5255 * Check if monitor has continuous frequency mode
5256 */
5257 if (data->type != EDID_DETAIL_MONITOR_RANGE)
5258 continue;
5259 /*
5260 * Check for flag range limits only. If flag == 1 then
5261 * no additional timing information provided.
5262 * Default GTF, GTF Secondary curve and CVT are not
5263 * supported
5264 */
5265 if (range->flags != 1)
5266 continue;
5267
c84dec2f
HW		 5268 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
5269 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
5270 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 5271 range->pixel_clock_mhz * 10;
5272 break;
5273 }
5274
c84dec2f 5275 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 5276 amdgpu_dm_connector->min_vfreq > 10) {
5277
8218d7f1 5278 dm_con_state->freesync_capable = true;
e7b07cee
HW		 5279 }
5280 }
e7b07cee
HW		 5281}
5282
Linux 6.x block layer and io_uring tree(s)