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drm/amd/display: Log which clocks are unsupported
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
ad941f7a
FX		 62#include "dcn/dcn_1_0_offset.h"
63#include "dcn/dcn_1_0_sh_mask.h"
fb960bd2 64#include "soc15ip.h"
ff5ef992
AD		 65
66#include "soc15_common.h"
67#endif
68
e7b07cee
HW		 69#include "modules/inc/mod_freesync.h"
70
71#include "i2caux_interface.h"
72
7578ecda
AD		 73/* basic init/fini API */
74static int amdgpu_dm_init(struct amdgpu_device *adev);
75static void amdgpu_dm_fini(struct amdgpu_device *adev);
76
77/* initializes drm_device display related structures, based on the information
78 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
79 * drm_encoder, drm_mode_config
80 *
81 * Returns 0 on success
82 */
83static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
84/* removes and deallocates the drm structures, created by the above function */
85static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
86
87static void
88amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
89
90static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
91 struct amdgpu_plane *aplane,
92 unsigned long possible_crtcs);
93static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
94 struct drm_plane *plane,
95 uint32_t link_index);
96static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
97 struct amdgpu_dm_connector *amdgpu_dm_connector,
98 uint32_t link_index,
99 struct amdgpu_encoder *amdgpu_encoder);
100static int amdgpu_dm_encoder_init(struct drm_device *dev,
101 struct amdgpu_encoder *aencoder,
102 uint32_t link_index);
103
104static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
105
106static int amdgpu_dm_atomic_commit(struct drm_device *dev,
107 struct drm_atomic_state *state,
108 bool nonblock);
109
110static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
111
112static int amdgpu_dm_atomic_check(struct drm_device *dev,
113 struct drm_atomic_state *state);
114
115
116
e7b07cee 117
e04a6123 118static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 119 DRM_PLANE_TYPE_PRIMARY,
120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125};
126
e04a6123 127static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 128 DRM_PLANE_TYPE_PRIMARY,
129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
132};
133
e04a6123 134static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 135 DRM_PLANE_TYPE_PRIMARY,
136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
138};
139
4562236b
HW		 140/*
141 * dm_vblank_get_counter
142 *
143 * @brief
144 * Get counter for number of vertical blanks
145 *
146 * @param
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
149 *
150 * @return
151 * Counter for vertical blanks
152 */
153static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
154{
155 if (crtc >= adev->mode_info.num_crtc)
156 return 0;
157 else {
158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
160 acrtc->base.state);
4562236b 161
da5c47f6
AG		 162
163 if (acrtc_state->stream == NULL) {
0971c40e
HW		 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
165 crtc);
4562236b
HW		 166 return 0;
167 }
168
da5c47f6 169 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 170 }
171}
172
173static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 174 u32 *vbl, u32 *position)
4562236b 175{
81c50963
ST		 176 uint32_t v_blank_start, v_blank_end, h_position, v_position;
177
4562236b
HW		 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
179 return -EINVAL;
180 else {
181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
183 acrtc->base.state);
4562236b 184
da5c47f6 185 if (acrtc_state->stream == NULL) {
0971c40e
HW		 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
187 crtc);
4562236b
HW		 188 return 0;
189 }
190
81c50963
ST		 191 /*
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
194 */
da5c47f6 195 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 196 &v_blank_start,
197 &v_blank_end,
198 &h_position,
199 &v_position);
200
e806208d
AG		 201 *position = v_position | (h_position << 16);
202 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 203 }
204
205 return 0;
206}
207
208static bool dm_is_idle(void *handle)
209{
210 /* XXX todo */
211 return true;
212}
213
214static int dm_wait_for_idle(void *handle)
215{
216 /* XXX todo */
217 return 0;
218}
219
220static bool dm_check_soft_reset(void *handle)
221{
222 return false;
223}
224
225static int dm_soft_reset(void *handle)
226{
227 /* XXX todo */
228 return 0;
229}
230
3ee6b26b
AD		 231static struct amdgpu_crtc *
232get_crtc_by_otg_inst(struct amdgpu_device *adev,
233 int otg_inst)
4562236b
HW		 234{
235 struct drm_device *dev = adev->ddev;
236 struct drm_crtc *crtc;
237 struct amdgpu_crtc *amdgpu_crtc;
238
239 /*
240 * following if is check inherited from both functions where this one is
241 * used now. Need to be checked why it could happen.
242 */
243 if (otg_inst == -1) {
244 WARN_ON(1);
245 return adev->mode_info.crtcs[0];
246 }
247
248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
249 amdgpu_crtc = to_amdgpu_crtc(crtc);
250
251 if (amdgpu_crtc->otg_inst == otg_inst)
252 return amdgpu_crtc;
253 }
254
255 return NULL;
256}
257
258static void dm_pflip_high_irq(void *interrupt_params)
259{
4562236b
HW		 260 struct amdgpu_crtc *amdgpu_crtc;
261 struct common_irq_params *irq_params = interrupt_params;
262 struct amdgpu_device *adev = irq_params->adev;
263 unsigned long flags;
264
265 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
266
267 /* IRQ could occur when in initial stage */
268 /*TODO work and BO cleanup */
269 if (amdgpu_crtc == NULL) {
270 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
271 return;
272 }
273
274 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 275
276 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
277 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
278 amdgpu_crtc->pflip_status,
279 AMDGPU_FLIP_SUBMITTED,
280 amdgpu_crtc->crtc_id,
281 amdgpu_crtc);
282 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
283 return;
284 }
285
4562236b
HW		 286
287 /* wakeup usersapce */
1159898a 288 if (amdgpu_crtc->event) {
753c66c9
MK		 289 /* Update to correct count/ts if racing with vblank irq */
290 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
291
54f5499a 292 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 293
54f5499a
AG		 294 /* page flip completed. clean up */
295 amdgpu_crtc->event = NULL;
1159898a 296
54f5499a
AG		 297 } else
298 WARN_ON(1);
4562236b 299
54f5499a 300 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 301 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
302
54f5499a
AG		 303 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
304 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 305
306 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 307}
308
309static void dm_crtc_high_irq(void *interrupt_params)
310{
311 struct common_irq_params *irq_params = interrupt_params;
312 struct amdgpu_device *adev = irq_params->adev;
313 uint8_t crtc_index = 0;
314 struct amdgpu_crtc *acrtc;
315
b57de80a 316 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 317
318 if (acrtc)
319 crtc_index = acrtc->crtc_id;
320
321 drm_handle_vblank(adev->ddev, crtc_index);
322}
323
324static int dm_set_clockgating_state(void *handle,
325 enum amd_clockgating_state state)
326{
327 return 0;
328}
329
330static int dm_set_powergating_state(void *handle,
331 enum amd_powergating_state state)
332{
333 return 0;
334}
335
336/* Prototypes of private functions */
337static int dm_early_init(void* handle);
338
339static void hotplug_notify_work_func(struct work_struct *work)
340{
341 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
342 struct drm_device *dev = dm->ddev;
343
344 drm_kms_helper_hotplug_event(dev);
345}
346
6ef39a62 347#if defined(CONFIG_DRM_AMD_DC_FBC)
a32e24b4 348/* Allocate memory for FBC compressed data */
42e67c3b 349static void amdgpu_dm_fbc_init(struct amdgpu_device *adev)
a32e24b4 350{
a32e24b4 351 struct dm_comressor_info *compressor = &adev->dm.compressor;
42e67c3b
RL		 352 struct drm_connector *conn;
353 struct drm_device *dev = adev->ddev;
354 unsigned long max_size = 0;
355
356 if (adev->dm.dc->fbc_compressor == NULL)
357 return;
a32e24b4 358
42e67c3b
RL		 359 if (compressor->bo_ptr)
360 return;
361
362 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
363
364 /* For eDP connector find a mode requiring max size */
365 list_for_each_entry(conn,
366 &dev->mode_config.connector_list, head) {
367 struct amdgpu_dm_connector *aconn;
368
369 aconn = to_amdgpu_dm_connector(conn);
370 if (aconn->dc_link->connector_signal == SIGNAL_TYPE_EDP) {
371 struct drm_display_mode *mode;
372
373 list_for_each_entry(mode, &conn->modes, head) {
374 if (max_size < mode->hdisplay * mode->vdisplay)
375 max_size = mode->htotal * mode->vtotal;
376 }
377 }
378 }
379
380 if (max_size) {
381 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
382 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
383 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 384
385 if (r)
42e67c3b
RL		 386 DRM_ERROR("DM: Failed to initialize FBC\n");
387 else {
388 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
389 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
390 }
391
a32e24b4
RL		 392 }
393
42e67c3b 394 drm_modeset_unlock(&dev->mode_config.connection_mutex);
a32e24b4
RL		 395}
396#endif
397
398
4562236b
HW		 399/* Init display KMS
400 *
401 * Returns 0 on success
402 */
7578ecda 403static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 404{
405 struct dc_init_data init_data;
406 adev->dm.ddev = adev->ddev;
407 adev->dm.adev = adev;
408
4562236b
HW		 409 /* Zero all the fields */
410 memset(&init_data, 0, sizeof(init_data));
411
412 /* initialize DAL's lock (for SYNC context use) */
413 spin_lock_init(&adev->dm.dal_lock);
414
415 /* initialize DAL's mutex */
416 mutex_init(&adev->dm.dal_mutex);
417
418 if(amdgpu_dm_irq_init(adev)) {
419 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
420 goto error;
421 }
422
423 init_data.asic_id.chip_family = adev->family;
424
425 init_data.asic_id.pci_revision_id = adev->rev_id;
426 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
427
428 init_data.asic_id.vram_width = adev->mc.vram_width;
429 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
430 init_data.asic_id.atombios_base_address =
431 adev->mode_info.atom_context->bios;
432
433 init_data.driver = adev;
434
435 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
436
437 if (!adev->dm.cgs_device) {
438 DRM_ERROR("amdgpu: failed to create cgs device.\n");
439 goto error;
440 }
441
442 init_data.cgs_device = adev->dm.cgs_device;
443
444 adev->dm.dal = NULL;
445
446 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
447
f1ad2f5e
HW		 448 if (amdgpu_dc_log)
449 init_data.log_mask = DC_DEFAULT_LOG_MASK;
450 else
451 init_data.log_mask = DC_MIN_LOG_MASK;
01a526f3 452
4562236b
HW		 453 /* Display Core create. */
454 adev->dm.dc = dc_create(&init_data);
455
423788c7 456 if (adev->dm.dc) {
76121231 457 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 458 } else {
76121231 459 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 460 goto error;
461 }
4562236b
HW		 462
463 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
464
465 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
466 if (!adev->dm.freesync_module) {
467 DRM_ERROR(
468 "amdgpu: failed to initialize freesync_module.\n");
469 } else
f1ad2f5e 470 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 471 adev->dm.freesync_module);
472
473 if (amdgpu_dm_initialize_drm_device(adev)) {
474 DRM_ERROR(
475 "amdgpu: failed to initialize sw for display support.\n");
476 goto error;
477 }
478
479 /* Update the actual used number of crtc */
480 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
481
482 /* TODO: Add_display_info? */
483
484 /* TODO use dynamic cursor width */
ce75805e
AG		 485 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
486 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 487
488 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
489 DRM_ERROR(
490 "amdgpu: failed to initialize sw for display support.\n");
491 goto error;
492 }
493
f1ad2f5e 494 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 495
496 return 0;
497error:
498 amdgpu_dm_fini(adev);
499
500 return -1;
501}
502
7578ecda 503static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 504{
505 amdgpu_dm_destroy_drm_device(&adev->dm);
506 /*
507 * TODO: pageflip, vlank interrupt
508 *
509 * amdgpu_dm_irq_fini(adev);
510 */
511
512 if (adev->dm.cgs_device) {
513 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
514 adev->dm.cgs_device = NULL;
515 }
516 if (adev->dm.freesync_module) {
517 mod_freesync_destroy(adev->dm.freesync_module);
518 adev->dm.freesync_module = NULL;
519 }
520 /* DC Destroy TODO: Replace destroy DAL */
21de3396 521 if (adev->dm.dc)
4562236b 522 dc_destroy(&adev->dm.dc);
4562236b
HW		 523 return;
524}
525
4562236b
HW		 526static int dm_sw_init(void *handle)
527{
528 return 0;
529}
530
531static int dm_sw_fini(void *handle)
532{
533 return 0;
534}
535
7abcf6b5 536static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 537{
c84dec2f 538 struct amdgpu_dm_connector *aconnector;
4562236b 539 struct drm_connector *connector;
7abcf6b5 540 int ret = 0;
4562236b
HW		 541
542 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
543
544 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 545 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 546 if (aconnector->dc_link->type == dc_connection_mst_branch &&
547 aconnector->mst_mgr.aux) {
f1ad2f5e 548 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 549 aconnector, aconnector->base.base.id);
550
551 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
552 if (ret < 0) {
553 DRM_ERROR("DM_MST: Failed to start MST\n");
554 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
555 return ret;
4562236b 556 }
7abcf6b5 557 }
4562236b
HW		 558 }
559
560 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 561 return ret;
562}
563
564static int dm_late_init(void *handle)
565{
42e67c3b 566 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 567
42e67c3b
RL		 568#if defined(CONFIG_DRM_AMD_DC_FBC)
569 amdgpu_dm_fbc_init(adev);
570#endif
571 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 572}
573
574static void s3_handle_mst(struct drm_device *dev, bool suspend)
575{
c84dec2f 576 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 577 struct drm_connector *connector;
578
579 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
580
581 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 582 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 583 if (aconnector->dc_link->type == dc_connection_mst_branch &&
584 !aconnector->mst_port) {
585
586 if (suspend)
587 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
588 else
589 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
590 }
591 }
592
593 drm_modeset_unlock(&dev->mode_config.connection_mutex);
594}
595
596static int dm_hw_init(void *handle)
597{
598 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
599 /* Create DAL display manager */
600 amdgpu_dm_init(adev);
4562236b
HW		 601 amdgpu_dm_hpd_init(adev);
602
4562236b
HW		 603 return 0;
604}
605
606static int dm_hw_fini(void *handle)
607{
608 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
609
610 amdgpu_dm_hpd_fini(adev);
611
612 amdgpu_dm_irq_fini(adev);
21de3396 613 amdgpu_dm_fini(adev);
4562236b
HW		 614 return 0;
615}
616
617static int dm_suspend(void *handle)
618{
619 struct amdgpu_device *adev = handle;
620 struct amdgpu_display_manager *dm = &adev->dm;
621 int ret = 0;
4562236b
HW		 622
623 s3_handle_mst(adev->ddev, true);
624
4562236b
HW		 625 amdgpu_dm_irq_suspend(adev);
626
0a214e2f 627 WARN_ON(adev->dm.cached_state);
a3621485
AG		 628 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
629
32f5062d 630 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 631
632 return ret;
633}
634
1daf8c63
AD		 635static struct amdgpu_dm_connector *
636amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
637 struct drm_crtc *crtc)
4562236b
HW		 638{
639 uint32_t i;
c2cea706 640 struct drm_connector_state *new_con_state;
4562236b
HW		 641 struct drm_connector *connector;
642 struct drm_crtc *crtc_from_state;
643
c2cea706
LSL		 644 for_each_new_connector_in_state(state, connector, new_con_state, i) {
645 crtc_from_state = new_con_state->crtc;
4562236b
HW		 646
647 if (crtc_from_state == crtc)
c84dec2f 648 return to_amdgpu_dm_connector(connector);
4562236b
HW		 649 }
650
651 return NULL;
652}
653
4562236b
HW		 654static int dm_resume(void *handle)
655{
656 struct amdgpu_device *adev = handle;
657 struct amdgpu_display_manager *dm = &adev->dm;
658
659 /* power on hardware */
1fb0c9cc 660 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
4562236b
HW		 661
662 return 0;
663}
664
1ecfc3da 665int amdgpu_dm_display_resume(struct amdgpu_device *adev)
4562236b
HW		 666{
667 struct drm_device *ddev = adev->ddev;
668 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 669 struct amdgpu_dm_connector *aconnector;
4562236b 670 struct drm_connector *connector;
4562236b 671 struct drm_crtc *crtc;
c2cea706 672 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 673 struct dm_crtc_state *dm_new_crtc_state;
674 struct drm_plane *plane;
675 struct drm_plane_state *new_plane_state;
676 struct dm_plane_state *dm_new_plane_state;
677
a3621485
AG		 678 int ret = 0;
679 int i;
4562236b
HW		 680
681 /* program HPD filter */
682 dc_resume(dm->dc);
683
684 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
685 s3_handle_mst(ddev, false);
686
687 /*
688 * early enable HPD Rx IRQ, should be done before set mode as short
689 * pulse interrupts are used for MST
690 */
691 amdgpu_dm_irq_resume_early(adev);
692
4562236b
HW		 693 /* Do detection*/
694 list_for_each_entry(connector,
695 &ddev->mode_config.connector_list, head) {
c84dec2f 696 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 697
698 /*
699 * this is the case when traversing through already created
700 * MST connectors, should be skipped
701 */
702 if (aconnector->mst_port)
703 continue;
704
03ea364c 705 mutex_lock(&aconnector->hpd_lock);
8f38b66c 706 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 707
708 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
709 aconnector->fake_enable = false;
710
4562236b
HW		 711 aconnector->dc_sink = NULL;
712 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 713 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 714 }
715
a3621485 716 /* Force mode set in atomic comit */
c2cea706
LSL		 717 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
718 new_crtc_state->active_changed = true;
4f346e65 719
fcb4019e
LSL		 720 /*
721 * atomic_check is expected to create the dc states. We need to release
722 * them here, since they were duplicated as part of the suspend
723 * procedure.
724 */
725 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
726 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
727 if (dm_new_crtc_state->stream) {
728 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
729 dc_stream_release(dm_new_crtc_state->stream);
730 dm_new_crtc_state->stream = NULL;
731 }
732 }
733
734 for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
735 dm_new_plane_state = to_dm_plane_state(new_plane_state);
736 if (dm_new_plane_state->dc_state) {
737 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
738 dc_plane_state_release(dm_new_plane_state->dc_state);
739 dm_new_plane_state->dc_state = NULL;
740 }
741 }
742
a3621485 743 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 744
0a214e2f
AG		 745 adev->dm.cached_state = NULL;
746
9faa4237 747 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 748
749 return ret;
750}
751
752static const struct amd_ip_funcs amdgpu_dm_funcs = {
753 .name = "dm",
754 .early_init = dm_early_init,
7abcf6b5 755 .late_init = dm_late_init,
4562236b
HW		 756 .sw_init = dm_sw_init,
757 .sw_fini = dm_sw_fini,
758 .hw_init = dm_hw_init,
759 .hw_fini = dm_hw_fini,
760 .suspend = dm_suspend,
761 .resume = dm_resume,
762 .is_idle = dm_is_idle,
763 .wait_for_idle = dm_wait_for_idle,
764 .check_soft_reset = dm_check_soft_reset,
765 .soft_reset = dm_soft_reset,
766 .set_clockgating_state = dm_set_clockgating_state,
767 .set_powergating_state = dm_set_powergating_state,
768};
769
770const struct amdgpu_ip_block_version dm_ip_block =
771{
772 .type = AMD_IP_BLOCK_TYPE_DCE,
773 .major = 1,
774 .minor = 0,
775 .rev = 0,
776 .funcs = &amdgpu_dm_funcs,
777};
778
ca3268c4 779
7578ecda 780static struct drm_atomic_state *
ca3268c4
HW		 781dm_atomic_state_alloc(struct drm_device *dev)
782{
783 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
784
1dc90497 785 if (!state)
ca3268c4 786 return NULL;
1dc90497
AG		 787
788 if (drm_atomic_state_init(dev, &state->base) < 0)
789 goto fail;
790
ca3268c4 791 return &state->base;
1dc90497
AG		 792
793fail:
794 kfree(state);
795 return NULL;
ca3268c4
HW		 796}
797
0a323b84
AG		 798static void
799dm_atomic_state_clear(struct drm_atomic_state *state)
800{
801 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
802
803 if (dm_state->context) {
608ac7bb 804 dc_release_state(dm_state->context);
0a323b84
AG		 805 dm_state->context = NULL;
806 }
807
808 drm_atomic_state_default_clear(state);
809}
810
811static void
812dm_atomic_state_alloc_free(struct drm_atomic_state *state)
813{
814 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
815 drm_atomic_state_default_release(state);
816 kfree(dm_state);
817}
818
b3663f70 819static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
a49dcb88 820 .fb_create = amdgpu_user_framebuffer_create,
366c1baa 821 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 822 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 823 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 824 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 825 .atomic_state_clear = dm_atomic_state_clear,
826 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 827};
828
829static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
830 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 831};
832
7578ecda 833static void
3ee6b26b 834amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 835{
836 struct drm_connector *connector = &aconnector->base;
837 struct drm_device *dev = connector->dev;
b73a22d3 838 struct dc_sink *sink;
4562236b
HW		 839
840 /* MST handled by drm_mst framework */
841 if (aconnector->mst_mgr.mst_state == true)
842 return;
843
844
845 sink = aconnector->dc_link->local_sink;
846
847 /* Edid mgmt connector gets first update only in mode_valid hook and then
848 * the connector sink is set to either fake or physical sink depends on link status.
849 * don't do it here if u are during boot
850 */
851 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
852 && aconnector->dc_em_sink) {
853
ab2541b6 854 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 855 * because on resume connecotr->sink is set ti NULL
856 */
857 mutex_lock(&dev->mode_config.mutex);
858
859 if (sink) {
922aa1e1 860 if (aconnector->dc_sink) {
4562236b
HW		 861 amdgpu_dm_remove_sink_from_freesync_module(
862 connector);
922aa1e1
AG		 863 /* retain and release bellow are used for
864 * bump up refcount for sink because the link don't point
865 * to it anymore after disconnect so on next crtc to connector
866 * reshuffle by UMD we will get into unwanted dc_sink release
867 */
868 if (aconnector->dc_sink != aconnector->dc_em_sink)
869 dc_sink_release(aconnector->dc_sink);
870 }
4562236b
HW		 871 aconnector->dc_sink = sink;
872 amdgpu_dm_add_sink_to_freesync_module(
873 connector, aconnector->edid);
874 } else {
875 amdgpu_dm_remove_sink_from_freesync_module(connector);
876 if (!aconnector->dc_sink)
877 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 878 else if (aconnector->dc_sink != aconnector->dc_em_sink)
879 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 880 }
881
882 mutex_unlock(&dev->mode_config.mutex);
883 return;
884 }
885
886 /*
887 * TODO: temporary guard to look for proper fix
888 * if this sink is MST sink, we should not do anything
889 */
890 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
891 return;
892
893 if (aconnector->dc_sink == sink) {
894 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
895 * Do nothing!! */
f1ad2f5e 896 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 897 aconnector->connector_id);
898 return;
899 }
900
f1ad2f5e 901 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 902 aconnector->connector_id, aconnector->dc_sink, sink);
903
904 mutex_lock(&dev->mode_config.mutex);
905
906 /* 1. Update status of the drm connector
907 * 2. Send an event and let userspace tell us what to do */
908 if (sink) {
909 /* TODO: check if we still need the S3 mode update workaround.
910 * If yes, put it here. */
911 if (aconnector->dc_sink)
912 amdgpu_dm_remove_sink_from_freesync_module(
913 connector);
914
915 aconnector->dc_sink = sink;
900b3cb1 916 if (sink->dc_edid.length == 0) {
4562236b 917 aconnector->edid = NULL;
900b3cb1 918 } else {
4562236b
HW		 919 aconnector->edid =
920 (struct edid *) sink->dc_edid.raw_edid;
921
922
923 drm_mode_connector_update_edid_property(connector,
924 aconnector->edid);
925 }
926 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
927
928 } else {
929 amdgpu_dm_remove_sink_from_freesync_module(connector);
930 drm_mode_connector_update_edid_property(connector, NULL);
931 aconnector->num_modes = 0;
932 aconnector->dc_sink = NULL;
933 }
934
935 mutex_unlock(&dev->mode_config.mutex);
936}
937
938static void handle_hpd_irq(void *param)
939{
c84dec2f 940 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 941 struct drm_connector *connector = &aconnector->base;
942 struct drm_device *dev = connector->dev;
943
944 /* In case of failure or MST no need to update connector status or notify the OS
945 * since (for MST case) MST does this in it's own context.
946 */
947 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 948
949 if (aconnector->fake_enable)
950 aconnector->fake_enable = false;
951
8f38b66c 952 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 953 amdgpu_dm_update_connector_after_detect(aconnector);
954
955
956 drm_modeset_lock_all(dev);
957 dm_restore_drm_connector_state(dev, connector);
958 drm_modeset_unlock_all(dev);
959
960 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
961 drm_kms_helper_hotplug_event(dev);
962 }
963 mutex_unlock(&aconnector->hpd_lock);
964
965}
966
c84dec2f 967static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 968{
969 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
970 uint8_t dret;
971 bool new_irq_handled = false;
972 int dpcd_addr;
973 int dpcd_bytes_to_read;
974
975 const int max_process_count = 30;
976 int process_count = 0;
977
978 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
979
980 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
981 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
982 /* DPCD 0x200 - 0x201 for downstream IRQ */
983 dpcd_addr = DP_SINK_COUNT;
984 } else {
985 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
986 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
987 dpcd_addr = DP_SINK_COUNT_ESI;
988 }
989
990 dret = drm_dp_dpcd_read(
991 &aconnector->dm_dp_aux.aux,
992 dpcd_addr,
993 esi,
994 dpcd_bytes_to_read);
995
996 while (dret == dpcd_bytes_to_read &&
997 process_count < max_process_count) {
998 uint8_t retry;
999 dret = 0;
1000
1001 process_count++;
1002
f1ad2f5e 1003 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1004 /* handle HPD short pulse irq */
1005 if (aconnector->mst_mgr.mst_state)
1006 drm_dp_mst_hpd_irq(
1007 &aconnector->mst_mgr,
1008 esi,
1009 &new_irq_handled);
4562236b
HW		 1010
1011 if (new_irq_handled) {
1012 /* ACK at DPCD to notify down stream */
1013 const int ack_dpcd_bytes_to_write =
1014 dpcd_bytes_to_read - 1;
1015
1016 for (retry = 0; retry < 3; retry++) {
1017 uint8_t wret;
1018
1019 wret = drm_dp_dpcd_write(
1020 &aconnector->dm_dp_aux.aux,
1021 dpcd_addr + 1,
1022 &esi[1],
1023 ack_dpcd_bytes_to_write);
1024 if (wret == ack_dpcd_bytes_to_write)
1025 break;
1026 }
1027
1028 /* check if there is new irq to be handle */
1029 dret = drm_dp_dpcd_read(
1030 &aconnector->dm_dp_aux.aux,
1031 dpcd_addr,
1032 esi,
1033 dpcd_bytes_to_read);
1034
1035 new_irq_handled = false;
d4a6e8a9 1036 } else {
4562236b 1037 break;
d4a6e8a9 1038 }
4562236b
HW		 1039 }
1040
1041 if (process_count == max_process_count)
f1ad2f5e 1042 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1043}
1044
1045static void handle_hpd_rx_irq(void *param)
1046{
c84dec2f 1047 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1048 struct drm_connector *connector = &aconnector->base;
1049 struct drm_device *dev = connector->dev;
53cbf65c 1050 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 1051 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1052
1053 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1054 * conflict, after implement i2c helper, this mutex should be
1055 * retired.
1056 */
53cbf65c 1057 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1058 mutex_lock(&aconnector->hpd_lock);
1059
53cbf65c 1060 if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
4562236b
HW		 1061 !is_mst_root_connector) {
1062 /* Downstream Port status changed. */
53cbf65c 1063 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
4562236b
HW		 1064 amdgpu_dm_update_connector_after_detect(aconnector);
1065
1066
1067 drm_modeset_lock_all(dev);
1068 dm_restore_drm_connector_state(dev, connector);
1069 drm_modeset_unlock_all(dev);
1070
1071 drm_kms_helper_hotplug_event(dev);
1072 }
1073 }
1074 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1075 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1076 dm_handle_hpd_rx_irq(aconnector);
1077
53cbf65c 1078 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1079 mutex_unlock(&aconnector->hpd_lock);
1080}
1081
1082static void register_hpd_handlers(struct amdgpu_device *adev)
1083{
1084 struct drm_device *dev = adev->ddev;
1085 struct drm_connector *connector;
c84dec2f 1086 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1087 const struct dc_link *dc_link;
1088 struct dc_interrupt_params int_params = {0};
1089
1090 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1091 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1092
1093 list_for_each_entry(connector,
1094 &dev->mode_config.connector_list, head) {
1095
c84dec2f 1096 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1097 dc_link = aconnector->dc_link;
1098
1099 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1100 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1101 int_params.irq_source = dc_link->irq_source_hpd;
1102
1103 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1104 handle_hpd_irq,
1105 (void *) aconnector);
1106 }
1107
1108 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1109
1110 /* Also register for DP short pulse (hpd_rx). */
1111 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1112 int_params.irq_source = dc_link->irq_source_hpd_rx;
1113
1114 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1115 handle_hpd_rx_irq,
1116 (void *) aconnector);
1117 }
1118 }
1119}
1120
1121/* Register IRQ sources and initialize IRQ callbacks */
1122static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1123{
1124 struct dc *dc = adev->dm.dc;
1125 struct common_irq_params *c_irq_params;
1126 struct dc_interrupt_params int_params = {0};
1127 int r;
1128 int i;
2c8ad2d5
AD		 1129 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1130
ff5ef992
AD		 1131 if (adev->asic_type == CHIP_VEGA10 ||
1132 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1133 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1134
1135 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1136 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1137
1138 /* Actions of amdgpu_irq_add_id():
1139 * 1. Register a set() function with base driver.
1140 * Base driver will call set() function to enable/disable an
1141 * interrupt in DC hardware.
1142 * 2. Register amdgpu_dm_irq_handler().
1143 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1144 * coming from DC hardware.
1145 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1146 * for acknowledging and handling. */
1147
b57de80a 1148 /* Use VBLANK interrupt */
e9029155 1149 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1150 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1151 if (r) {
1152 DRM_ERROR("Failed to add crtc irq id!\n");
1153 return r;
1154 }
1155
1156 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1157 int_params.irq_source =
3d761e79 1158 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1159
b57de80a 1160 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1161
1162 c_irq_params->adev = adev;
1163 c_irq_params->irq_src = int_params.irq_source;
1164
1165 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1166 dm_crtc_high_irq, c_irq_params);
1167 }
1168
3d761e79 1169 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1170 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1171 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1172 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1173 if (r) {
1174 DRM_ERROR("Failed to add page flip irq id!\n");
1175 return r;
1176 }
1177
1178 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1179 int_params.irq_source =
1180 dc_interrupt_to_irq_source(dc, i, 0);
1181
1182 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1183
1184 c_irq_params->adev = adev;
1185 c_irq_params->irq_src = int_params.irq_source;
1186
1187 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1188 dm_pflip_high_irq, c_irq_params);
1189
1190 }
1191
1192 /* HPD */
2c8ad2d5
AD		 1193 r = amdgpu_irq_add_id(adev, client_id,
1194 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1195 if (r) {
1196 DRM_ERROR("Failed to add hpd irq id!\n");
1197 return r;
1198 }
1199
1200 register_hpd_handlers(adev);
1201
1202 return 0;
1203}
1204
ff5ef992
AD		 1205#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1206/* Register IRQ sources and initialize IRQ callbacks */
1207static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1208{
1209 struct dc *dc = adev->dm.dc;
1210 struct common_irq_params *c_irq_params;
1211 struct dc_interrupt_params int_params = {0};
1212 int r;
1213 int i;
1214
1215 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1216 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1217
1218 /* Actions of amdgpu_irq_add_id():
1219 * 1. Register a set() function with base driver.
1220 * Base driver will call set() function to enable/disable an
1221 * interrupt in DC hardware.
1222 * 2. Register amdgpu_dm_irq_handler().
1223 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1224 * coming from DC hardware.
1225 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1226 * for acknowledging and handling.
1227 * */
1228
1229 /* Use VSTARTUP interrupt */
1230 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1231 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1232 i++) {
1233 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1234
1235 if (r) {
1236 DRM_ERROR("Failed to add crtc irq id!\n");
1237 return r;
1238 }
1239
1240 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1241 int_params.irq_source =
1242 dc_interrupt_to_irq_source(dc, i, 0);
1243
1244 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1245
1246 c_irq_params->adev = adev;
1247 c_irq_params->irq_src = int_params.irq_source;
1248
1249 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1250 dm_crtc_high_irq, c_irq_params);
1251 }
1252
1253 /* Use GRPH_PFLIP interrupt */
1254 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1255 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1256 i++) {
1257 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1258 if (r) {
1259 DRM_ERROR("Failed to add page flip irq id!\n");
1260 return r;
1261 }
1262
1263 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1264 int_params.irq_source =
1265 dc_interrupt_to_irq_source(dc, i, 0);
1266
1267 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1268
1269 c_irq_params->adev = adev;
1270 c_irq_params->irq_src = int_params.irq_source;
1271
1272 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1273 dm_pflip_high_irq, c_irq_params);
1274
1275 }
1276
1277 /* HPD */
1278 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1279 &adev->hpd_irq);
1280 if (r) {
1281 DRM_ERROR("Failed to add hpd irq id!\n");
1282 return r;
1283 }
1284
1285 register_hpd_handlers(adev);
1286
1287 return 0;
1288}
1289#endif
1290
4562236b
HW		 1291static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1292{
1293 int r;
1294
1295 adev->mode_info.mode_config_initialized = true;
1296
4562236b 1297 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1298 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1299
1300 adev->ddev->mode_config.max_width = 16384;
1301 adev->ddev->mode_config.max_height = 16384;
1302
1303 adev->ddev->mode_config.preferred_depth = 24;
1304 adev->ddev->mode_config.prefer_shadow = 1;
1305 /* indicate support of immediate flip */
1306 adev->ddev->mode_config.async_page_flip = true;
1307
1308 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1309
1310 r = amdgpu_modeset_create_props(adev);
1311 if (r)
1312 return r;
1313
1314 return 0;
1315}
1316
1317#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1318 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1319
1320static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1321{
1322 struct amdgpu_display_manager *dm = bl_get_data(bd);
1323
1324 if (dc_link_set_backlight_level(dm->backlight_link,
1325 bd->props.brightness, 0, 0))
1326 return 0;
1327 else
1328 return 1;
1329}
1330
1331static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1332{
1333 return bd->props.brightness;
1334}
1335
1336static const struct backlight_ops amdgpu_dm_backlight_ops = {
1337 .get_brightness = amdgpu_dm_backlight_get_brightness,
1338 .update_status = amdgpu_dm_backlight_update_status,
1339};
1340
7578ecda
AD		 1341static void
1342amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1343{
1344 char bl_name[16];
1345 struct backlight_properties props = { 0 };
1346
1347 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1348 props.type = BACKLIGHT_RAW;
1349
1350 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1351 dm->adev->ddev->primary->index);
1352
1353 dm->backlight_dev = backlight_device_register(bl_name,
1354 dm->adev->ddev->dev,
1355 dm,
1356 &amdgpu_dm_backlight_ops,
1357 &props);
1358
74baea42 1359 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1360 DRM_ERROR("DM: Backlight registration failed!\n");
1361 else
f1ad2f5e 1362 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1363}
1364
1365#endif
1366
1367/* In this architecture, the association
1368 * connector -> encoder -> crtc
1369 * id not really requried. The crtc and connector will hold the
1370 * display_index as an abstraction to use with DAL component
1371 *
1372 * Returns 0 on success
1373 */
7578ecda 1374static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1375{
1376 struct amdgpu_display_manager *dm = &adev->dm;
1377 uint32_t i;
c84dec2f 1378 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1379 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1380 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1381 uint32_t link_cnt;
92f3ac40 1382 unsigned long possible_crtcs;
4562236b
HW		 1383
1384 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1385 if (amdgpu_dm_mode_config_init(dm->adev)) {
1386 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1387 return -1;
4562236b
HW		 1388 }
1389
3be5262e 1390 for (i = 0; i < dm->dc->caps.max_planes; i++) {
efa6a8b7
HW		 1391 struct amdgpu_plane *plane;
1392
1393 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1394 mode_info->planes[i] = plane;
1395
1396 if (!plane) {
3be5262e 1397 DRM_ERROR("KMS: Failed to allocate plane\n");
cd8a2ae8 1398 goto fail;
d4e13b0d 1399 }
efa6a8b7 1400 plane->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1401
1402 /*
1403 * HACK: IGT tests expect that each plane can only have one
1404 * one possible CRTC. For now, set one CRTC for each
1405 * plane that is not an underlay, but still allow multiple
1406 * CRTCs for underlay planes.
1407 */
1408 possible_crtcs = 1 << i;
1409 if (i >= dm->dc->caps.max_streams)
1410 possible_crtcs = 0xff;
1411
1412 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d 1413 DRM_ERROR("KMS: Failed to initialize plane\n");
cd8a2ae8 1414 goto fail;
d4e13b0d
AD		 1415 }
1416 }
4562236b 1417
d4e13b0d
AD		 1418 for (i = 0; i < dm->dc->caps.max_streams; i++)
1419 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1420 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1421 goto fail;
4562236b 1422 }
4562236b 1423
ab2541b6 1424 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1425
1426 /* loops over all connectors on the board */
1427 for (i = 0; i < link_cnt; i++) {
1428
1429 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1430 DRM_ERROR(
1431 "KMS: Cannot support more than %d display indexes\n",
1432 AMDGPU_DM_MAX_DISPLAY_INDEX);
1433 continue;
1434 }
1435
1436 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1437 if (!aconnector)
cd8a2ae8 1438 goto fail;
4562236b
HW		 1439
1440 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1441 if (!aencoder)
cd8a2ae8 1442 goto fail;
4562236b
HW		 1443
1444 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1445 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1446 goto fail;
4562236b
HW		 1447 }
1448
1449 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1450 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1451 goto fail;
4562236b
HW		 1452 }
1453
8f38b66c
HW		 1454 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1455 DETECT_REASON_BOOT))
4562236b
HW		 1456 amdgpu_dm_update_connector_after_detect(aconnector);
1457 }
1458
1459 /* Software is initialized. Now we can register interrupt handlers. */
1460 switch (adev->asic_type) {
1461 case CHIP_BONAIRE:
1462 case CHIP_HAWAII:
cd4b356f
AD		 1463 case CHIP_KAVERI:
1464 case CHIP_KABINI:
1465 case CHIP_MULLINS:
4562236b
HW		 1466 case CHIP_TONGA:
1467 case CHIP_FIJI:
1468 case CHIP_CARRIZO:
1469 case CHIP_STONEY:
1470 case CHIP_POLARIS11:
1471 case CHIP_POLARIS10:
b264d345 1472 case CHIP_POLARIS12:
2c8ad2d5 1473 case CHIP_VEGA10:
4562236b
HW		 1474 if (dce110_register_irq_handlers(dm->adev)) {
1475 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1476 goto fail;
4562236b
HW		 1477 }
1478 break;
ff5ef992
AD		 1479#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1480 case CHIP_RAVEN:
1481 if (dcn10_register_irq_handlers(dm->adev)) {
1482 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1483 goto fail;
ff5ef992 1484 }
79c24086
BL		 1485 /*
1486 * Temporary disable until pplib/smu interaction is implemented
1487 */
1488 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1489 break;
1490#endif
4562236b
HW		 1491 default:
1492 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 1493 goto fail;
4562236b
HW		 1494 }
1495
4562236b 1496 return 0;
cd8a2ae8 1497fail:
4562236b 1498 kfree(aencoder);
4562236b 1499 kfree(aconnector);
3be5262e 1500 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1501 kfree(mode_info->planes[i]);
4562236b
HW		 1502 return -1;
1503}
1504
7578ecda 1505static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1506{
1507 drm_mode_config_cleanup(dm->ddev);
1508 return;
1509}
1510
1511/******************************************************************************
1512 * amdgpu_display_funcs functions
1513 *****************************************************************************/
1514
1515/**
1516 * dm_bandwidth_update - program display watermarks
1517 *
1518 * @adev: amdgpu_device pointer
1519 *
1520 * Calculate and program the display watermarks and line buffer allocation.
1521 */
1522static void dm_bandwidth_update(struct amdgpu_device *adev)
1523{
49c07a99 1524 /* TODO: implement later */
4562236b
HW		 1525}
1526
1527static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1528 u8 level)
1529{
1530 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1531}
1532
1533static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1534{
1535 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1536 return 0;
1537}
1538
4562236b
HW		 1539static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1540 struct drm_file *filp)
1541{
1542 struct mod_freesync_params freesync_params;
ab2541b6 1543 uint8_t num_streams;
4562236b 1544 uint8_t i;
4562236b
HW		 1545
1546 struct amdgpu_device *adev = dev->dev_private;
1547 int r = 0;
1548
1549 /* Get freesync enable flag from DRM */
1550
ab2541b6 1551 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1552
ab2541b6 1553 for (i = 0; i < num_streams; i++) {
0971c40e 1554 struct dc_stream_state *stream;
ab2541b6 1555 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1556
1557 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1558 &stream, 1, &freesync_params);
4562236b
HW		 1559 }
1560
1561 return r;
1562}
1563
39cc5be2 1564static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1565 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1566 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1567 .vblank_wait = NULL,
1568 .backlight_set_level =
1569 dm_set_backlight_level,/* called unconditionally */
1570 .backlight_get_level =
1571 dm_get_backlight_level,/* called unconditionally */
1572 .hpd_sense = NULL,/* called unconditionally */
1573 .hpd_set_polarity = NULL, /* called unconditionally */
1574 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1575 .page_flip_get_scanoutpos =
1576 dm_crtc_get_scanoutpos,/* called unconditionally */
1577 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1578 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1579 .notify_freesync = amdgpu_notify_freesync,
1580
1581};
1582
1583#if defined(CONFIG_DEBUG_KERNEL_DC)
1584
3ee6b26b
AD		 1585static ssize_t s3_debug_store(struct device *device,
1586 struct device_attribute *attr,
1587 const char *buf,
1588 size_t count)
4562236b
HW		 1589{
1590 int ret;
1591 int s3_state;
1592 struct pci_dev *pdev = to_pci_dev(device);
1593 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1594 struct amdgpu_device *adev = drm_dev->dev_private;
1595
1596 ret = kstrtoint(buf, 0, &s3_state);
1597
1598 if (ret == 0) {
1599 if (s3_state) {
1600 dm_resume(adev);
1601 amdgpu_dm_display_resume(adev);
1602 drm_kms_helper_hotplug_event(adev->ddev);
1603 } else
1604 dm_suspend(adev);
1605 }
1606
1607 return ret == 0 ? count : 0;
1608}
1609
1610DEVICE_ATTR_WO(s3_debug);
1611
1612#endif
1613
1614static int dm_early_init(void *handle)
1615{
1616 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1617
d7ec53d9 1618 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
4562236b
HW		 1619
1620 switch (adev->asic_type) {
1621 case CHIP_BONAIRE:
1622 case CHIP_HAWAII:
1623 adev->mode_info.num_crtc = 6;
1624 adev->mode_info.num_hpd = 6;
1625 adev->mode_info.num_dig = 6;
3be5262e 1626 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1627 break;
cd4b356f
AD		 1628 case CHIP_KAVERI:
1629 adev->mode_info.num_crtc = 4;
1630 adev->mode_info.num_hpd = 6;
1631 adev->mode_info.num_dig = 7;
1632 adev->mode_info.plane_type = dm_plane_type_default;
1633 break;
1634 case CHIP_KABINI:
1635 case CHIP_MULLINS:
1636 adev->mode_info.num_crtc = 2;
1637 adev->mode_info.num_hpd = 6;
1638 adev->mode_info.num_dig = 6;
1639 adev->mode_info.plane_type = dm_plane_type_default;
1640 break;
4562236b
HW		 1641 case CHIP_FIJI:
1642 case CHIP_TONGA:
1643 adev->mode_info.num_crtc = 6;
1644 adev->mode_info.num_hpd = 6;
1645 adev->mode_info.num_dig = 7;
3be5262e 1646 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1647 break;
1648 case CHIP_CARRIZO:
1649 adev->mode_info.num_crtc = 3;
1650 adev->mode_info.num_hpd = 6;
1651 adev->mode_info.num_dig = 9;
3be5262e 1652 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1653 break;
1654 case CHIP_STONEY:
1655 adev->mode_info.num_crtc = 2;
1656 adev->mode_info.num_hpd = 6;
1657 adev->mode_info.num_dig = 9;
3be5262e 1658 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1659 break;
1660 case CHIP_POLARIS11:
b264d345 1661 case CHIP_POLARIS12:
4562236b
HW		 1662 adev->mode_info.num_crtc = 5;
1663 adev->mode_info.num_hpd = 5;
1664 adev->mode_info.num_dig = 5;
3be5262e 1665 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1666 break;
1667 case CHIP_POLARIS10:
1668 adev->mode_info.num_crtc = 6;
1669 adev->mode_info.num_hpd = 6;
1670 adev->mode_info.num_dig = 6;
3be5262e 1671 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1672 break;
2c8ad2d5
AD		 1673 case CHIP_VEGA10:
1674 adev->mode_info.num_crtc = 6;
1675 adev->mode_info.num_hpd = 6;
1676 adev->mode_info.num_dig = 6;
3be5262e 1677 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1678 break;
ff5ef992
AD		 1679#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1680 case CHIP_RAVEN:
1681 adev->mode_info.num_crtc = 4;
1682 adev->mode_info.num_hpd = 4;
1683 adev->mode_info.num_dig = 4;
3be5262e 1684 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1685 break;
1686#endif
4562236b
HW		 1687 default:
1688 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1689 return -EINVAL;
1690 }
1691
c8dd5715
MD		 1692 amdgpu_dm_set_irq_funcs(adev);
1693
39cc5be2
AD		 1694 if (adev->mode_info.funcs == NULL)
1695 adev->mode_info.funcs = &dm_display_funcs;
1696
4562236b
HW		 1697 /* Note: Do NOT change adev->audio_endpt_rreg and
1698 * adev->audio_endpt_wreg because they are initialised in
1699 * amdgpu_device_init() */
1700#if defined(CONFIG_DEBUG_KERNEL_DC)
1701 device_create_file(
1702 adev->ddev->dev,
1703 &dev_attr_s3_debug);
1704#endif
1705
1706 return 0;
1707}
1708
9b690ef3 1709static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1710 struct dc_stream_state *new_stream,
1711 struct dc_stream_state *old_stream)
9b690ef3 1712{
e7b07cee
HW		 1713 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1714 return false;
1715
1716 if (!crtc_state->enable)
1717 return false;
1718
1719 return crtc_state->active;
1720}
1721
1722static bool modereset_required(struct drm_crtc_state *crtc_state)
1723{
1724 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1725 return false;
1726
1727 return !crtc_state->enable || !crtc_state->active;
1728}
1729
7578ecda 1730static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1731{
1732 drm_encoder_cleanup(encoder);
1733 kfree(encoder);
1734}
1735
1736static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1737 .destroy = amdgpu_dm_encoder_destroy,
1738};
1739
3ee6b26b
AD		 1740static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1741 struct dc_plane_state *plane_state)
e7b07cee 1742{
3be5262e
HW		 1743 plane_state->src_rect.x = state->src_x >> 16;
1744 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1745 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1746 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1747
3be5262e 1748 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1749 return false;
1750
3be5262e
HW		 1751 plane_state->src_rect.height = state->src_h >> 16;
1752 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1753 return false;
1754
3be5262e
HW		 1755 plane_state->dst_rect.x = state->crtc_x;
1756 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1757
1758 if (state->crtc_w == 0)
1759 return false;
1760
3be5262e 1761 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1762
1763 if (state->crtc_h == 0)
1764 return false;
1765
3be5262e 1766 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1767
3be5262e 1768 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1769
1770 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1771 case DRM_MODE_ROTATE_0:
3be5262e 1772 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1773 break;
1774 case DRM_MODE_ROTATE_90:
3be5262e 1775 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1776 break;
1777 case DRM_MODE_ROTATE_180:
3be5262e 1778 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1779 break;
1780 case DRM_MODE_ROTATE_270:
3be5262e 1781 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1782 break;
1783 default:
3be5262e 1784 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1785 break;
1786 }
1787
4562236b
HW		 1788 return true;
1789}
3ee6b26b 1790static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 1791 uint64_t *tiling_flags)
e7b07cee
HW		 1792{
1793 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1794 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1795
e7b07cee 1796 if (unlikely(r)) {
9bbc3031
JZ		 1797 // Don't show error msg. when return -ERESTARTSYS
1798 if (r != -ERESTARTSYS)
1799 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1800 return r;
1801 }
1802
e7b07cee
HW		 1803 if (tiling_flags)
1804 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1805
1806 amdgpu_bo_unreserve(rbo);
1807
1808 return r;
1809}
1810
3ee6b26b
AD		 1811static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1812 struct dc_plane_state *plane_state,
9817d5f5 1813 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 1814{
1815 uint64_t tiling_flags;
e7b07cee
HW		 1816 unsigned int awidth;
1817 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1818 int ret = 0;
1819 struct drm_format_name_buf format_name;
1820
1821 ret = get_fb_info(
1822 amdgpu_fb,
9817d5f5 1823 &tiling_flags);
e7b07cee
HW		 1824
1825 if (ret)
1826 return ret;
1827
1828 switch (fb->format->format) {
1829 case DRM_FORMAT_C8:
3be5262e 1830 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1831 break;
1832 case DRM_FORMAT_RGB565:
3be5262e 1833 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1834 break;
1835 case DRM_FORMAT_XRGB8888:
1836 case DRM_FORMAT_ARGB8888:
3be5262e 1837 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1838 break;
1839 case DRM_FORMAT_XRGB2101010:
1840 case DRM_FORMAT_ARGB2101010:
3be5262e 1841 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1842 break;
1843 case DRM_FORMAT_XBGR2101010:
1844 case DRM_FORMAT_ABGR2101010:
3be5262e 1845 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1846 break;
1847 case DRM_FORMAT_NV21:
3be5262e 1848 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1849 break;
1850 case DRM_FORMAT_NV12:
3be5262e 1851 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1852 break;
1853 default:
1854 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1855 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1856 return -EINVAL;
1857 }
1858
3be5262e
HW		 1859 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1860 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 1861 plane_state->plane_size.grph.surface_size.x = 0;
1862 plane_state->plane_size.grph.surface_size.y = 0;
1863 plane_state->plane_size.grph.surface_size.width = fb->width;
1864 plane_state->plane_size.grph.surface_size.height = fb->height;
1865 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1866 fb->pitches[0] / fb->format->cpp[0];
1867 /* TODO: unhardcode */
3be5262e 1868 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1869
1870 } else {
1871 awidth = ALIGN(fb->width, 64);
3be5262e 1872 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 1873 plane_state->plane_size.video.luma_size.x = 0;
1874 plane_state->plane_size.video.luma_size.y = 0;
1875 plane_state->plane_size.video.luma_size.width = awidth;
1876 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1877 /* TODO: unhardcode */
3be5262e 1878 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1879
3be5262e
HW		 1880 plane_state->plane_size.video.chroma_size.x = 0;
1881 plane_state->plane_size.video.chroma_size.y = 0;
1882 plane_state->plane_size.video.chroma_size.width = awidth;
1883 plane_state->plane_size.video.chroma_size.height = fb->height;
1884 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1885
1886 /* TODO: unhardcode */
3be5262e 1887 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1888 }
1889
3be5262e 1890 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1891
b830ebc9
HW		 1892 /* Fill GFX8 params */
1893 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1894 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1895
1896 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1897 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1898 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1899 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1900 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1901
1902 /* XXX fix me for VI */
3be5262e
HW		 1903 plane_state->tiling_info.gfx8.num_banks = num_banks;
1904 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1905 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1906 plane_state->tiling_info.gfx8.tile_split = tile_split;
1907 plane_state->tiling_info.gfx8.bank_width = bankw;
1908 plane_state->tiling_info.gfx8.bank_height = bankh;
1909 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1910 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1911 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1912 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1913 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1914 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1915 }
1916
3be5262e 1917 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1918 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1919
1920 if (adev->asic_type == CHIP_VEGA10 ||
1921 adev->asic_type == CHIP_RAVEN) {
1922 /* Fill GFX9 params */
3be5262e 1923 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1924 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1925 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1926 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1927 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1928 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1929 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1930 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1931 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1932 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1933 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1934 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1935 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1936 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1937 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1938 }
1939
3be5262e
HW		 1940 plane_state->visible = true;
1941 plane_state->scaling_quality.h_taps_c = 0;
1942 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1943
3be5262e
HW		 1944 /* is this needed? is plane_state zeroed at allocation? */
1945 plane_state->scaling_quality.h_taps = 0;
1946 plane_state->scaling_quality.v_taps = 0;
1947 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1948
1949 return ret;
1950
1951}
1952
3ee6b26b
AD		 1953static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state,
1954 struct dc_plane_state *plane_state)
e7b07cee
HW		 1955{
1956 int i;
1957 struct dc_gamma *gamma;
d66cf5f5
AK		 1958 struct drm_color_lut *lut =
1959 (struct drm_color_lut *) crtc_state->gamma_lut->data;
e7b07cee
HW		 1960
1961 gamma = dc_create_gamma();
1962
1963 if (gamma == NULL) {
1964 WARN_ON(1);
1965 return;
1966 }
1967
7483bed4
HW		 1968 gamma->type = GAMMA_RGB_256;
1969 gamma->num_entries = GAMMA_RGB_256_ENTRIES;
d66cf5f5
AK		 1970 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1971 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1972 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1973 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
e7b07cee
HW		 1974 }
1975
3be5262e 1976 plane_state->gamma_correction = gamma;
e7b07cee
HW		 1977}
1978
3ee6b26b
AD		 1979static int fill_plane_attributes(struct amdgpu_device *adev,
1980 struct dc_plane_state *dc_plane_state,
1981 struct drm_plane_state *plane_state,
9817d5f5 1982 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 1983{
1984 const struct amdgpu_framebuffer *amdgpu_fb =
1985 to_amdgpu_framebuffer(plane_state->fb);
1986 const struct drm_crtc *crtc = plane_state->crtc;
1987 struct dc_transfer_func *input_tf;
1988 int ret = 0;
1989
3be5262e 1990 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1991 return -EINVAL;
1992
1993 ret = fill_plane_attributes_from_fb(
1994 crtc->dev->dev_private,
3be5262e 1995 dc_plane_state,
9817d5f5 1996 amdgpu_fb);
e7b07cee
HW		 1997
1998 if (ret)
1999 return ret;
2000
2001 input_tf = dc_create_transfer_func();
2002
2003 if (input_tf == NULL)
2004 return -ENOMEM;
2005
2006 input_tf->type = TF_TYPE_PREDEFINED;
2007 input_tf->tf = TRANSFER_FUNCTION_SRGB;
2008
3be5262e 2009 dc_plane_state->in_transfer_func = input_tf;
e7b07cee
HW		 2010
2011 /* In case of gamma set, update gamma value */
2012 if (crtc_state->gamma_lut)
3be5262e 2013 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
e7b07cee
HW		 2014
2015 return ret;
2016}
2017
2018/*****************************************************************************/
2019
3ee6b26b
AD		 2020static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2021 const struct dm_connector_state *dm_state,
2022 struct dc_stream_state *stream)
e7b07cee
HW		 2023{
2024 enum amdgpu_rmx_type rmx_type;
2025
2026 struct rect src = { 0 }; /* viewport in composition space*/
2027 struct rect dst = { 0 }; /* stream addressable area */
2028
2029 /* no mode. nothing to be done */
2030 if (!mode)
2031 return;
2032
2033 /* Full screen scaling by default */
2034 src.width = mode->hdisplay;
2035 src.height = mode->vdisplay;
2036 dst.width = stream->timing.h_addressable;
2037 dst.height = stream->timing.v_addressable;
2038
2039 rmx_type = dm_state->scaling;
2040 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2041 if (src.width * dst.height <
2042 src.height * dst.width) {
2043 /* height needs less upscaling/more downscaling */
2044 dst.width = src.width *
2045 dst.height / src.height;
2046 } else {
2047 /* width needs less upscaling/more downscaling */
2048 dst.height = src.height *
2049 dst.width / src.width;
2050 }
2051 } else if (rmx_type == RMX_CENTER) {
2052 dst = src;
2053 }
2054
2055 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2056 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2057
2058 if (dm_state->underscan_enable) {
2059 dst.x += dm_state->underscan_hborder / 2;
2060 dst.y += dm_state->underscan_vborder / 2;
2061 dst.width -= dm_state->underscan_hborder;
2062 dst.height -= dm_state->underscan_vborder;
2063 }
2064
2065 stream->src = src;
2066 stream->dst = dst;
2067
f1ad2f5e 2068 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2069 dst.x, dst.y, dst.width, dst.height);
2070
2071}
2072
3ee6b26b
AD		 2073static enum dc_color_depth
2074convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2075{
2076 uint32_t bpc = connector->display_info.bpc;
2077
2078 /* Limited color depth to 8bit
b830ebc9
HW		 2079 * TODO: Still need to handle deep color
2080 */
e7b07cee
HW		 2081 if (bpc > 8)
2082 bpc = 8;
2083
2084 switch (bpc) {
2085 case 0:
2086 /* Temporary Work around, DRM don't parse color depth for
2087 * EDID revision before 1.4
2088 * TODO: Fix edid parsing
2089 */
2090 return COLOR_DEPTH_888;
2091 case 6:
2092 return COLOR_DEPTH_666;
2093 case 8:
2094 return COLOR_DEPTH_888;
2095 case 10:
2096 return COLOR_DEPTH_101010;
2097 case 12:
2098 return COLOR_DEPTH_121212;
2099 case 14:
2100 return COLOR_DEPTH_141414;
2101 case 16:
2102 return COLOR_DEPTH_161616;
2103 default:
2104 return COLOR_DEPTH_UNDEFINED;
2105 }
2106}
2107
3ee6b26b
AD		 2108static enum dc_aspect_ratio
2109get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2110{
2111 int32_t width = mode_in->crtc_hdisplay * 9;
2112 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2113
e7b07cee
HW		 2114 if ((width - height) < 10 && (width - height) > -10)
2115 return ASPECT_RATIO_16_9;
2116 else
2117 return ASPECT_RATIO_4_3;
2118}
2119
3ee6b26b
AD		 2120static enum dc_color_space
2121get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2122{
2123 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2124
2125 switch (dc_crtc_timing->pixel_encoding) {
2126 case PIXEL_ENCODING_YCBCR422:
2127 case PIXEL_ENCODING_YCBCR444:
2128 case PIXEL_ENCODING_YCBCR420:
2129 {
2130 /*
2131 * 27030khz is the separation point between HDTV and SDTV
2132 * according to HDMI spec, we use YCbCr709 and YCbCr601
2133 * respectively
2134 */
2135 if (dc_crtc_timing->pix_clk_khz > 27030) {
2136 if (dc_crtc_timing->flags.Y_ONLY)
2137 color_space =
2138 COLOR_SPACE_YCBCR709_LIMITED;
2139 else
2140 color_space = COLOR_SPACE_YCBCR709;
2141 } else {
2142 if (dc_crtc_timing->flags.Y_ONLY)
2143 color_space =
2144 COLOR_SPACE_YCBCR601_LIMITED;
2145 else
2146 color_space = COLOR_SPACE_YCBCR601;
2147 }
2148
2149 }
2150 break;
2151 case PIXEL_ENCODING_RGB:
2152 color_space = COLOR_SPACE_SRGB;
2153 break;
2154
2155 default:
2156 WARN_ON(1);
2157 break;
2158 }
2159
2160 return color_space;
2161}
2162
2163/*****************************************************************************/
2164
3ee6b26b
AD		 2165static void
2166fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2167 const struct drm_display_mode *mode_in,
2168 const struct drm_connector *connector)
e7b07cee
HW		 2169{
2170 struct dc_crtc_timing *timing_out = &stream->timing;
a6114e85 2171 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2172
e7b07cee
HW		 2173 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2174
2175 timing_out->h_border_left = 0;
2176 timing_out->h_border_right = 0;
2177 timing_out->v_border_top = 0;
2178 timing_out->v_border_bottom = 0;
2179 /* TODO: un-hardcode */
2180
2181 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2182 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2183 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2184 else
2185 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2186
2187 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2188 timing_out->display_color_depth = convert_color_depth_from_display_info(
2189 connector);
2190 timing_out->scan_type = SCANNING_TYPE_NODATA;
2191 timing_out->hdmi_vic = 0;
2192 timing_out->vic = drm_match_cea_mode(mode_in);
2193
2194 timing_out->h_addressable = mode_in->crtc_hdisplay;
2195 timing_out->h_total = mode_in->crtc_htotal;
2196 timing_out->h_sync_width =
2197 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2198 timing_out->h_front_porch =
2199 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2200 timing_out->v_total = mode_in->crtc_vtotal;
2201 timing_out->v_addressable = mode_in->crtc_vdisplay;
2202 timing_out->v_front_porch =
2203 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2204 timing_out->v_sync_width =
2205 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2206 timing_out->pix_clk_khz = mode_in->crtc_clock;
2207 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2208 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2209 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2210 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2211 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2212
2213 stream->output_color_space = get_output_color_space(timing_out);
2214
a6114e85
HW		 2215 tf->type = TF_TYPE_PREDEFINED;
2216 tf->tf = TRANSFER_FUNCTION_SRGB;
2217 stream->out_transfer_func = tf;
e7b07cee
HW		 2218}
2219
3ee6b26b
AD		 2220static void fill_audio_info(struct audio_info *audio_info,
2221 const struct drm_connector *drm_connector,
2222 const struct dc_sink *dc_sink)
e7b07cee
HW		 2223{
2224 int i = 0;
2225 int cea_revision = 0;
2226 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2227
2228 audio_info->manufacture_id = edid_caps->manufacturer_id;
2229 audio_info->product_id = edid_caps->product_id;
2230
2231 cea_revision = drm_connector->display_info.cea_rev;
2232
d2b2562c
TSD		 2233 strncpy(audio_info->display_name,
2234 edid_caps->display_name,
2235 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2236
b830ebc9 2237 if (cea_revision >= 3) {
e7b07cee
HW		 2238 audio_info->mode_count = edid_caps->audio_mode_count;
2239
2240 for (i = 0; i < audio_info->mode_count; ++i) {
2241 audio_info->modes[i].format_code =
2242 (enum audio_format_code)
2243 (edid_caps->audio_modes[i].format_code);
2244 audio_info->modes[i].channel_count =
2245 edid_caps->audio_modes[i].channel_count;
2246 audio_info->modes[i].sample_rates.all =
2247 edid_caps->audio_modes[i].sample_rate;
2248 audio_info->modes[i].sample_size =
2249 edid_caps->audio_modes[i].sample_size;
2250 }
2251 }
2252
2253 audio_info->flags.all = edid_caps->speaker_flags;
2254
2255 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2256 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2257 audio_info->video_latency = drm_connector->video_latency[0];
2258 audio_info->audio_latency = drm_connector->audio_latency[0];
2259 }
2260
2261 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2262
2263}
2264
3ee6b26b
AD		 2265static void
2266copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2267 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2268{
2269 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2270 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2271 dst_mode->crtc_clock = src_mode->crtc_clock;
2272 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2273 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2274 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2275 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2276 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2277 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2278 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2279 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2280 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2281 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2282 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2283}
2284
3ee6b26b
AD		 2285static void
2286decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2287 const struct drm_display_mode *native_mode,
2288 bool scale_enabled)
e7b07cee
HW		 2289{
2290 if (scale_enabled) {
2291 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2292 } else if (native_mode->clock == drm_mode->clock &&
2293 native_mode->htotal == drm_mode->htotal &&
2294 native_mode->vtotal == drm_mode->vtotal) {
2295 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2296 } else {
2297 /* no scaling nor amdgpu inserted, no need to patch */
2298 }
2299}
2300
423788c7 2301static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6
HW		 2302{
2303 struct dc_sink *sink = NULL;
2304 struct dc_sink_init_data sink_init_data = { 0 };
2305
2306 sink_init_data.link = aconnector->dc_link;
2307 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2308
2309 sink = dc_sink_create(&sink_init_data);
423788c7 2310 if (!sink) {
2e0ac3d6 2311 DRM_ERROR("Failed to create sink!\n");
423788c7
ES		 2312 return -ENOMEM;
2313 }
2e0ac3d6
HW		 2314
2315 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2316 aconnector->fake_enable = true;
2317
2318 aconnector->dc_sink = sink;
2319 aconnector->dc_link->local_sink = sink;
423788c7
ES		 2320
2321 return 0;
2e0ac3d6
HW		 2322}
2323
fa2123db
ML		 2324static void set_multisync_trigger_params(
2325 struct dc_stream_state *stream)
2326{
2327 if (stream->triggered_crtc_reset.enabled) {
2328 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2329 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2330 }
2331}
2332
2333static void set_master_stream(struct dc_stream_state *stream_set[],
2334 int stream_count)
2335{
2336 int j, highest_rfr = 0, master_stream = 0;
2337
2338 for (j = 0; j < stream_count; j++) {
2339 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2340 int refresh_rate = 0;
2341
2342 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2343 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2344 if (refresh_rate > highest_rfr) {
2345 highest_rfr = refresh_rate;
2346 master_stream = j;
2347 }
2348 }
2349 }
2350 for (j = 0; j < stream_count; j++) {
03736f4c 2351 if (stream_set[j])
fa2123db
ML		 2352 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2353 }
2354}
2355
2356static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2357{
2358 int i = 0;
2359
2360 if (context->stream_count < 2)
2361 return;
2362 for (i = 0; i < context->stream_count ; i++) {
2363 if (!context->streams[i])
2364 continue;
2365 /* TODO: add a function to read AMD VSDB bits and will set
2366 * crtc_sync_master.multi_sync_enabled flag
2367 * For now its set to false
2368 */
2369 set_multisync_trigger_params(context->streams[i]);
2370 }
2371 set_master_stream(context->streams, context->stream_count);
2372}
2373
3ee6b26b
AD		 2374static struct dc_stream_state *
2375create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2376 const struct drm_display_mode *drm_mode,
2377 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2378{
2379 struct drm_display_mode *preferred_mode = NULL;
391ef035 2380 struct drm_connector *drm_connector;
0971c40e 2381 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2382 struct drm_display_mode mode = *drm_mode;
2383 bool native_mode_found = false;
2384
b830ebc9 2385 if (aconnector == NULL) {
e7b07cee 2386 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2387 return stream;
e7b07cee
HW		 2388 }
2389
b830ebc9 2390 if (dm_state == NULL) {
e7b07cee 2391 DRM_ERROR("dm_state is NULL!\n");
64245fa7 2392 return stream;
e7b07cee 2393 }
4562236b 2394
e7b07cee 2395 drm_connector = &aconnector->base;
2e0ac3d6 2396
f4ac176e
JZ		 2397 if (!aconnector->dc_sink) {
2398 /*
391ef035
JFZ		 2399 * Create dc_sink when necessary to MST
2400 * Don't apply fake_sink to MST
f4ac176e 2401 */
391ef035
JFZ		 2402 if (aconnector->mst_port) {
2403 dm_dp_mst_dc_sink_create(drm_connector);
64245fa7 2404 return stream;
391ef035 2405 }
f4ac176e 2406
423788c7 2407 if (create_fake_sink(aconnector))
64245fa7 2408 return stream;
f4ac176e 2409 }
2e0ac3d6 2410
e7b07cee 2411 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2412
b830ebc9 2413 if (stream == NULL) {
e7b07cee 2414 DRM_ERROR("Failed to create stream for sink!\n");
64245fa7 2415 return stream;
e7b07cee
HW		 2416 }
2417
2418 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2419 /* Search for preferred mode */
2420 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2421 native_mode_found = true;
2422 break;
2423 }
2424 }
2425 if (!native_mode_found)
2426 preferred_mode = list_first_entry_or_null(
2427 &aconnector->base.modes,
2428 struct drm_display_mode,
2429 head);
2430
b830ebc9 2431 if (preferred_mode == NULL) {
e7b07cee
HW		 2432 /* This may not be an error, the use case is when we we have no
2433 * usermode calls to reset and set mode upon hotplug. In this
2434 * case, we call set mode ourselves to restore the previous mode
2435 * and the modelist may not be filled in in time.
2436 */
f1ad2f5e 2437 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2438 } else {
2439 decide_crtc_timing_for_drm_display_mode(
2440 &mode, preferred_mode,
2441 dm_state->scaling != RMX_OFF);
2442 }
2443
2444 fill_stream_properties_from_drm_display_mode(stream,
2445 &mode, &aconnector->base);
2446 update_stream_scaling_settings(&mode, dm_state, stream);
2447
2448 fill_audio_info(
2449 &stream->audio_info,
2450 drm_connector,
2451 aconnector->dc_sink);
2452
e7b07cee
HW		 2453 return stream;
2454}
2455
7578ecda 2456static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2457{
2458 drm_crtc_cleanup(crtc);
2459 kfree(crtc);
2460}
2461
2462static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2463 struct drm_crtc_state *state)
e7b07cee
HW		 2464{
2465 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2466
2467 /* TODO Destroy dc_stream objects are stream object is flattened */
2468 if (cur->stream)
2469 dc_stream_release(cur->stream);
2470
2471
2472 __drm_atomic_helper_crtc_destroy_state(state);
2473
2474
2475 kfree(state);
2476}
2477
2478static void dm_crtc_reset_state(struct drm_crtc *crtc)
2479{
2480 struct dm_crtc_state *state;
2481
2482 if (crtc->state)
2483 dm_crtc_destroy_state(crtc, crtc->state);
2484
2485 state = kzalloc(sizeof(*state), GFP_KERNEL);
2486 if (WARN_ON(!state))
2487 return;
2488
2489 crtc->state = &state->base;
2490 crtc->state->crtc = crtc;
2491
2492}
2493
2494static struct drm_crtc_state *
2495dm_crtc_duplicate_state(struct drm_crtc *crtc)
2496{
2497 struct dm_crtc_state *state, *cur;
2498
2499 cur = to_dm_crtc_state(crtc->state);
2500
2501 if (WARN_ON(!crtc->state))
2502 return NULL;
2503
2004f45e 2504 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 2505 if (!state)
2506 return NULL;
e7b07cee
HW		 2507
2508 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2509
2510 if (cur->stream) {
2511 state->stream = cur->stream;
2512 dc_stream_retain(state->stream);
2513 }
2514
2515 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2516
2517 return &state->base;
2518}
2519
2520/* Implemented only the options currently availible for the driver */
2521static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2522 .reset = dm_crtc_reset_state,
2523 .destroy = amdgpu_dm_crtc_destroy,
2524 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2525 .set_config = drm_atomic_helper_set_config,
2526 .page_flip = drm_atomic_helper_page_flip,
2527 .atomic_duplicate_state = dm_crtc_duplicate_state,
2528 .atomic_destroy_state = dm_crtc_destroy_state,
2529};
2530
2531static enum drm_connector_status
2532amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2533{
2534 bool connected;
c84dec2f 2535 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2536
2537 /* Notes:
2538 * 1. This interface is NOT called in context of HPD irq.
2539 * 2. This interface *is called* in context of user-mode ioctl. Which
2540 * makes it a bad place for *any* MST-related activit. */
2541
8580d60b
HW		 2542 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2543 !aconnector->fake_enable)
e7b07cee
HW		 2544 connected = (aconnector->dc_sink != NULL);
2545 else
2546 connected = (aconnector->base.force == DRM_FORCE_ON);
2547
2548 return (connected ? connector_status_connected :
2549 connector_status_disconnected);
2550}
2551
3ee6b26b
AD		 2552int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2553 struct drm_connector_state *connector_state,
2554 struct drm_property *property,
2555 uint64_t val)
e7b07cee
HW		 2556{
2557 struct drm_device *dev = connector->dev;
2558 struct amdgpu_device *adev = dev->dev_private;
2559 struct dm_connector_state *dm_old_state =
2560 to_dm_connector_state(connector->state);
2561 struct dm_connector_state *dm_new_state =
2562 to_dm_connector_state(connector_state);
2563
2564 int ret = -EINVAL;
2565
2566 if (property == dev->mode_config.scaling_mode_property) {
2567 enum amdgpu_rmx_type rmx_type;
2568
2569 switch (val) {
2570 case DRM_MODE_SCALE_CENTER:
2571 rmx_type = RMX_CENTER;
2572 break;
2573 case DRM_MODE_SCALE_ASPECT:
2574 rmx_type = RMX_ASPECT;
2575 break;
2576 case DRM_MODE_SCALE_FULLSCREEN:
2577 rmx_type = RMX_FULL;
2578 break;
2579 case DRM_MODE_SCALE_NONE:
2580 default:
2581 rmx_type = RMX_OFF;
2582 break;
2583 }
2584
2585 if (dm_old_state->scaling == rmx_type)
2586 return 0;
2587
2588 dm_new_state->scaling = rmx_type;
2589 ret = 0;
2590 } else if (property == adev->mode_info.underscan_hborder_property) {
2591 dm_new_state->underscan_hborder = val;
2592 ret = 0;
2593 } else if (property == adev->mode_info.underscan_vborder_property) {
2594 dm_new_state->underscan_vborder = val;
2595 ret = 0;
2596 } else if (property == adev->mode_info.underscan_property) {
2597 dm_new_state->underscan_enable = val;
2598 ret = 0;
2599 }
2600
2601 return ret;
2602}
2603
3ee6b26b
AD		 2604int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2605 const struct drm_connector_state *state,
2606 struct drm_property *property,
2607 uint64_t *val)
e7b07cee
HW		 2608{
2609 struct drm_device *dev = connector->dev;
2610 struct amdgpu_device *adev = dev->dev_private;
2611 struct dm_connector_state *dm_state =
2612 to_dm_connector_state(state);
2613 int ret = -EINVAL;
2614
2615 if (property == dev->mode_config.scaling_mode_property) {
2616 switch (dm_state->scaling) {
2617 case RMX_CENTER:
2618 *val = DRM_MODE_SCALE_CENTER;
2619 break;
2620 case RMX_ASPECT:
2621 *val = DRM_MODE_SCALE_ASPECT;
2622 break;
2623 case RMX_FULL:
2624 *val = DRM_MODE_SCALE_FULLSCREEN;
2625 break;
2626 case RMX_OFF:
2627 default:
2628 *val = DRM_MODE_SCALE_NONE;
2629 break;
2630 }
2631 ret = 0;
2632 } else if (property == adev->mode_info.underscan_hborder_property) {
2633 *val = dm_state->underscan_hborder;
2634 ret = 0;
2635 } else if (property == adev->mode_info.underscan_vborder_property) {
2636 *val = dm_state->underscan_vborder;
2637 ret = 0;
2638 } else if (property == adev->mode_info.underscan_property) {
2639 *val = dm_state->underscan_enable;
2640 ret = 0;
2641 }
2642 return ret;
2643}
2644
7578ecda 2645static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2646{
c84dec2f 2647 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2648 const struct dc_link *link = aconnector->dc_link;
2649 struct amdgpu_device *adev = connector->dev->dev_private;
2650 struct amdgpu_display_manager *dm = &adev->dm;
2651#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2652 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2653
2654 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2655 amdgpu_dm_register_backlight_device(dm);
2656
2657 if (dm->backlight_dev) {
2658 backlight_device_unregister(dm->backlight_dev);
2659 dm->backlight_dev = NULL;
2660 }
2661
2662 }
2663#endif
2664 drm_connector_unregister(connector);
2665 drm_connector_cleanup(connector);
2666 kfree(connector);
2667}
2668
2669void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2670{
2671 struct dm_connector_state *state =
2672 to_dm_connector_state(connector->state);
2673
2674 kfree(state);
2675
2676 state = kzalloc(sizeof(*state), GFP_KERNEL);
2677
2678 if (state) {
2679 state->scaling = RMX_OFF;
2680 state->underscan_enable = false;
2681 state->underscan_hborder = 0;
2682 state->underscan_vborder = 0;
2683
2684 connector->state = &state->base;
2685 connector->state->connector = connector;
2686 }
2687}
2688
3ee6b26b
AD		 2689struct drm_connector_state *
2690amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2691{
2692 struct dm_connector_state *state =
2693 to_dm_connector_state(connector->state);
2694
2695 struct dm_connector_state *new_state =
2696 kmemdup(state, sizeof(*state), GFP_KERNEL);
2697
2698 if (new_state) {
2699 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2700 &new_state->base);
e7b07cee
HW		 2701 return &new_state->base;
2702 }
2703
2704 return NULL;
2705}
2706
2707static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2708 .reset = amdgpu_dm_connector_funcs_reset,
2709 .detect = amdgpu_dm_connector_detect,
2710 .fill_modes = drm_helper_probe_single_connector_modes,
2711 .destroy = amdgpu_dm_connector_destroy,
2712 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2713 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2714 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2715 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2716};
2717
2718static struct drm_encoder *best_encoder(struct drm_connector *connector)
2719{
2720 int enc_id = connector->encoder_ids[0];
2721 struct drm_mode_object *obj;
2722 struct drm_encoder *encoder;
2723
f1ad2f5e 2724 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2725
2726 /* pick the encoder ids */
2727 if (enc_id) {
bd21a37d 2728 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2729 if (!obj) {
2730 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2731 return NULL;
2732 }
2733 encoder = obj_to_encoder(obj);
2734 return encoder;
2735 }
2736 DRM_ERROR("No encoder id\n");
2737 return NULL;
2738}
2739
2740static int get_modes(struct drm_connector *connector)
2741{
2742 return amdgpu_dm_connector_get_modes(connector);
2743}
2744
c84dec2f 2745static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2746{
2747 struct dc_sink_init_data init_params = {
2748 .link = aconnector->dc_link,
2749 .sink_signal = SIGNAL_TYPE_VIRTUAL
2750 };
70e8ffc5 2751 struct edid *edid;
e7b07cee 2752
a89ff457 2753 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 2754 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2755 aconnector->base.name);
2756
2757 aconnector->base.force = DRM_FORCE_OFF;
2758 aconnector->base.override_edid = false;
2759 return;
2760 }
2761
70e8ffc5
HW		 2762 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2763
e7b07cee
HW		 2764 aconnector->edid = edid;
2765
2766 aconnector->dc_em_sink = dc_link_add_remote_sink(
2767 aconnector->dc_link,
2768 (uint8_t *)edid,
2769 (edid->extensions + 1) * EDID_LENGTH,
2770 &init_params);
2771
a68d90e7 2772 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 2773 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2774 aconnector->dc_link->local_sink :
2775 aconnector->dc_em_sink;
2776}
2777
c84dec2f 2778static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2779{
2780 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2781
2782 /* In case of headless boot with force on for DP managed connector
2783 * Those settings have to be != 0 to get initial modeset
2784 */
2785 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2786 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2787 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2788 }
2789
2790
2791 aconnector->base.override_edid = true;
2792 create_eml_sink(aconnector);
2793}
2794
3ee6b26b
AD		 2795int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2796 struct drm_display_mode *mode)
e7b07cee
HW		 2797{
2798 int result = MODE_ERROR;
2799 struct dc_sink *dc_sink;
2800 struct amdgpu_device *adev = connector->dev->dev_private;
2801 /* TODO: Unhardcode stream count */
0971c40e 2802 struct dc_stream_state *stream;
c84dec2f 2803 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 2804 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 2805
2806 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2807 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2808 return result;
2809
2810 /* Only run this the first time mode_valid is called to initilialize
2811 * EDID mgmt
2812 */
2813 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2814 !aconnector->dc_em_sink)
2815 handle_edid_mgmt(aconnector);
2816
c84dec2f 2817 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2818
b830ebc9 2819 if (dc_sink == NULL) {
e7b07cee
HW		 2820 DRM_ERROR("dc_sink is NULL!\n");
2821 goto fail;
2822 }
2823
2824 stream = dc_create_stream_for_sink(dc_sink);
b830ebc9 2825 if (stream == NULL) {
e7b07cee
HW		 2826 DRM_ERROR("Failed to create stream for sink!\n");
2827 goto fail;
2828 }
2829
2830 drm_mode_set_crtcinfo(mode, 0);
2831 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2832
2833 stream->src.width = mode->hdisplay;
2834 stream->src.height = mode->vdisplay;
2835 stream->dst = stream->src;
2836
a39438f0
HW		 2837 dc_result = dc_validate_stream(adev->dm.dc, stream);
2838
2839 if (dc_result == DC_OK)
e7b07cee 2840 result = MODE_OK;
a39438f0 2841 else
9f921b14 2842 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 2843 mode->vdisplay,
2844 mode->hdisplay,
9f921b14
HW		 2845 mode->clock,
2846 dc_result);
e7b07cee
HW		 2847
2848 dc_stream_release(stream);
2849
2850fail:
2851 /* TODO: error handling*/
2852 return result;
2853}
2854
2855static const struct drm_connector_helper_funcs
2856amdgpu_dm_connector_helper_funcs = {
2857 /*
b830ebc9
HW		 2858 * If hotplug a second bigger display in FB Con mode, bigger resolution
2859 * modes will be filtered by drm_mode_validate_size(), and those modes
2860 * is missing after user start lightdm. So we need to renew modes list.
2861 * in get_modes call back, not just return the modes count
2862 */
e7b07cee
HW		 2863 .get_modes = get_modes,
2864 .mode_valid = amdgpu_dm_connector_mode_valid,
2865 .best_encoder = best_encoder
2866};
2867
2868static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2869{
2870}
2871
3ee6b26b
AD		 2872static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2873 struct drm_crtc_state *state)
e7b07cee
HW		 2874{
2875 struct amdgpu_device *adev = crtc->dev->dev_private;
2876 struct dc *dc = adev->dm.dc;
2877 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2878 int ret = -EINVAL;
2879
9b690ef3
BL		 2880 if (unlikely(!dm_crtc_state->stream &&
2881 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2882 WARN_ON(1);
2883 return ret;
2884 }
2885
2886 /* In some use cases, like reset, no stream is attached */
2887 if (!dm_crtc_state->stream)
2888 return 0;
2889
62c933f9 2890 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 2891 return 0;
2892
2893 return ret;
2894}
2895
3ee6b26b
AD		 2896static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2897 const struct drm_display_mode *mode,
2898 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2899{
2900 return true;
2901}
2902
2903static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2904 .disable = dm_crtc_helper_disable,
2905 .atomic_check = dm_crtc_helper_atomic_check,
2906 .mode_fixup = dm_crtc_helper_mode_fixup
2907};
2908
2909static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2910{
2911
2912}
2913
3ee6b26b
AD		 2914static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2915 struct drm_crtc_state *crtc_state,
2916 struct drm_connector_state *conn_state)
e7b07cee
HW		 2917{
2918 return 0;
2919}
2920
2921const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2922 .disable = dm_encoder_helper_disable,
2923 .atomic_check = dm_encoder_helper_atomic_check
2924};
2925
2926static void dm_drm_plane_reset(struct drm_plane *plane)
2927{
2928 struct dm_plane_state *amdgpu_state = NULL;
2929
2930 if (plane->state)
2931 plane->funcs->atomic_destroy_state(plane, plane->state);
2932
2933 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d
TSD		 2934 WARN_ON(amdgpu_state == NULL);
2935
e7b07cee
HW		 2936 if (amdgpu_state) {
2937 plane->state = &amdgpu_state->base;
2938 plane->state->plane = plane;
2939 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 2940 }
e7b07cee
HW		 2941}
2942
2943static struct drm_plane_state *
2944dm_drm_plane_duplicate_state(struct drm_plane *plane)
2945{
2946 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2947
2948 old_dm_plane_state = to_dm_plane_state(plane->state);
2949 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2950 if (!dm_plane_state)
2951 return NULL;
2952
2953 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2954
3be5262e
HW		 2955 if (old_dm_plane_state->dc_state) {
2956 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2957 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2958 }
2959
2960 return &dm_plane_state->base;
2961}
2962
2963void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2964 struct drm_plane_state *state)
e7b07cee
HW		 2965{
2966 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2967
3be5262e
HW		 2968 if (dm_plane_state->dc_state)
2969 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2970
0627bbd3 2971 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2972}
2973
2974static const struct drm_plane_funcs dm_plane_funcs = {
2975 .update_plane = drm_atomic_helper_update_plane,
2976 .disable_plane = drm_atomic_helper_disable_plane,
2977 .destroy = drm_plane_cleanup,
2978 .reset = dm_drm_plane_reset,
2979 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2980 .atomic_destroy_state = dm_drm_plane_destroy_state,
2981};
2982
3ee6b26b
AD		 2983static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2984 struct drm_plane_state *new_state)
e7b07cee
HW		 2985{
2986 struct amdgpu_framebuffer *afb;
2987 struct drm_gem_object *obj;
2988 struct amdgpu_bo *rbo;
56087b31 2989 uint64_t chroma_addr = 0;
e7b07cee
HW		 2990 int r;
2991 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2992 unsigned int awidth;
2993
2994 dm_plane_state_old = to_dm_plane_state(plane->state);
2995 dm_plane_state_new = to_dm_plane_state(new_state);
2996
2997 if (!new_state->fb) {
f1ad2f5e 2998 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 2999 return 0;
3000 }
3001
3002 afb = to_amdgpu_framebuffer(new_state->fb);
3003
3004 obj = afb->obj;
3005 rbo = gem_to_amdgpu_bo(obj);
3006 r = amdgpu_bo_reserve(rbo, false);
3007 if (unlikely(r != 0))
3008 return r;
3009
3010 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
3011
3012
3013 amdgpu_bo_unreserve(rbo);
3014
3015 if (unlikely(r != 0)) {
30b7c614
HW		 3016 if (r != -ERESTARTSYS)
3017 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
e7b07cee
HW		 3018 return r;
3019 }
3020
3021 amdgpu_bo_ref(rbo);
3022
3be5262e
HW		 3023 if (dm_plane_state_new->dc_state &&
3024 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3025 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3026
3be5262e
HW		 3027 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3028 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3029 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 3030 } else {
3031 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3032 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3033 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3034 = lower_32_bits(afb->address);
56087b31
S		 3035 plane_state->address.video_progressive.luma_addr.high_part
3036 = upper_32_bits(afb->address);
35888630 3037 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3038 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3039 = lower_32_bits(chroma_addr);
3040 plane_state->address.video_progressive.chroma_addr.high_part
3041 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3042 }
3043 }
3044
3045 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
3046 * prepare and cleanup in drm_atomic_helper_prepare_planes
3047 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
3048 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
3049 * code touching fram buffers should be avoided for DC.
3050 */
3051 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3052 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
3053
3054 acrtc->cursor_bo = obj;
3055 }
3056 return 0;
3057}
3058
3ee6b26b
AD		 3059static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3060 struct drm_plane_state *old_state)
e7b07cee
HW		 3061{
3062 struct amdgpu_bo *rbo;
3063 struct amdgpu_framebuffer *afb;
3064 int r;
3065
3066 if (!old_state->fb)
3067 return;
3068
3069 afb = to_amdgpu_framebuffer(old_state->fb);
3070 rbo = gem_to_amdgpu_bo(afb->obj);
3071 r = amdgpu_bo_reserve(rbo, false);
3072 if (unlikely(r)) {
3073 DRM_ERROR("failed to reserve rbo before unpin\n");
3074 return;
b830ebc9
HW		 3075 }
3076
3077 amdgpu_bo_unpin(rbo);
3078 amdgpu_bo_unreserve(rbo);
3079 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3080}
3081
7578ecda
AD		 3082static int dm_plane_atomic_check(struct drm_plane *plane,
3083 struct drm_plane_state *state)
cbd19488
AG		 3084{
3085 struct amdgpu_device *adev = plane->dev->dev_private;
3086 struct dc *dc = adev->dm.dc;
3087 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3088
3be5262e 3089 if (!dm_plane_state->dc_state)
9a3329b1 3090 return 0;
cbd19488 3091
62c933f9 3092 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3093 return 0;
3094
3095 return -EINVAL;
3096}
3097
e7b07cee
HW		 3098static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3099 .prepare_fb = dm_plane_helper_prepare_fb,
3100 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3101 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3102};
3103
3104/*
3105 * TODO: these are currently initialized to rgb formats only.
3106 * For future use cases we should either initialize them dynamically based on
3107 * plane capabilities, or initialize this array to all formats, so internal drm
3108 * check will succeed, and let DC to implement proper check
3109 */
d90371b0 3110static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3111 DRM_FORMAT_RGB888,
3112 DRM_FORMAT_XRGB8888,
3113 DRM_FORMAT_ARGB8888,
3114 DRM_FORMAT_RGBA8888,
3115 DRM_FORMAT_XRGB2101010,
3116 DRM_FORMAT_XBGR2101010,
3117 DRM_FORMAT_ARGB2101010,
3118 DRM_FORMAT_ABGR2101010,
3119};
3120
99d1abf8 3121static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3122 DRM_FORMAT_NV12,
3123 DRM_FORMAT_NV21,
3124};
3125
3126static const u32 cursor_formats[] = {
3127 DRM_FORMAT_ARGB8888
3128};
3129
7578ecda
AD		 3130static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3131 struct amdgpu_plane *aplane,
3132 unsigned long possible_crtcs)
e7b07cee
HW		 3133{
3134 int res = -EPERM;
3135
3136 switch (aplane->base.type) {
3137 case DRM_PLANE_TYPE_PRIMARY:
3138 aplane->base.format_default = true;
3139
3140 res = drm_universal_plane_init(
3141 dm->adev->ddev,
3142 &aplane->base,
3143 possible_crtcs,
3144 &dm_plane_funcs,
3145 rgb_formats,
3146 ARRAY_SIZE(rgb_formats),
3147 NULL, aplane->base.type, NULL);
3148 break;
3149 case DRM_PLANE_TYPE_OVERLAY:
3150 res = drm_universal_plane_init(
3151 dm->adev->ddev,
3152 &aplane->base,
3153 possible_crtcs,
3154 &dm_plane_funcs,
3155 yuv_formats,
3156 ARRAY_SIZE(yuv_formats),
3157 NULL, aplane->base.type, NULL);
3158 break;
3159 case DRM_PLANE_TYPE_CURSOR:
3160 res = drm_universal_plane_init(
3161 dm->adev->ddev,
3162 &aplane->base,
3163 possible_crtcs,
3164 &dm_plane_funcs,
3165 cursor_formats,
3166 ARRAY_SIZE(cursor_formats),
3167 NULL, aplane->base.type, NULL);
3168 break;
3169 }
3170
3171 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3172
96719c54
HW		 3173 /* Create (reset) the plane state */
3174 if (aplane->base.funcs->reset)
3175 aplane->base.funcs->reset(&aplane->base);
3176
3177
e7b07cee
HW		 3178 return res;
3179}
3180
7578ecda
AD		 3181static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3182 struct drm_plane *plane,
3183 uint32_t crtc_index)
e7b07cee
HW		 3184{
3185 struct amdgpu_crtc *acrtc = NULL;
3186 struct amdgpu_plane *cursor_plane;
3187
3188 int res = -ENOMEM;
3189
3190 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3191 if (!cursor_plane)
3192 goto fail;
3193
3194 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3195 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3196
3197 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3198 if (!acrtc)
3199 goto fail;
3200
3201 res = drm_crtc_init_with_planes(
3202 dm->ddev,
3203 &acrtc->base,
3204 plane,
3205 &cursor_plane->base,
3206 &amdgpu_dm_crtc_funcs, NULL);
3207
3208 if (res)
3209 goto fail;
3210
3211 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3212
96719c54
HW		 3213 /* Create (reset) the plane state */
3214 if (acrtc->base.funcs->reset)
3215 acrtc->base.funcs->reset(&acrtc->base);
3216
e7b07cee
HW		 3217 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3218 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3219
3220 acrtc->crtc_id = crtc_index;
3221 acrtc->base.enabled = false;
3222
3223 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3224 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3225
3226 return 0;
3227
3228fail:
b830ebc9
HW		 3229 kfree(acrtc);
3230 kfree(cursor_plane);
e7b07cee
HW		 3231 return res;
3232}
3233
3234
3235static int to_drm_connector_type(enum signal_type st)
3236{
3237 switch (st) {
3238 case SIGNAL_TYPE_HDMI_TYPE_A:
3239 return DRM_MODE_CONNECTOR_HDMIA;
3240 case SIGNAL_TYPE_EDP:
3241 return DRM_MODE_CONNECTOR_eDP;
3242 case SIGNAL_TYPE_RGB:
3243 return DRM_MODE_CONNECTOR_VGA;
3244 case SIGNAL_TYPE_DISPLAY_PORT:
3245 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3246 return DRM_MODE_CONNECTOR_DisplayPort;
3247 case SIGNAL_TYPE_DVI_DUAL_LINK:
3248 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3249 return DRM_MODE_CONNECTOR_DVID;
3250 case SIGNAL_TYPE_VIRTUAL:
3251 return DRM_MODE_CONNECTOR_VIRTUAL;
3252
3253 default:
3254 return DRM_MODE_CONNECTOR_Unknown;
3255 }
3256}
3257
3258static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3259{
3260 const struct drm_connector_helper_funcs *helper =
3261 connector->helper_private;
3262 struct drm_encoder *encoder;
3263 struct amdgpu_encoder *amdgpu_encoder;
3264
3265 encoder = helper->best_encoder(connector);
3266
3267 if (encoder == NULL)
3268 return;
3269
3270 amdgpu_encoder = to_amdgpu_encoder(encoder);
3271
3272 amdgpu_encoder->native_mode.clock = 0;
3273
3274 if (!list_empty(&connector->probed_modes)) {
3275 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3276
e7b07cee 3277 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3278 &connector->probed_modes,
3279 head) {
3280 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3281 amdgpu_encoder->native_mode = *preferred_mode;
3282
e7b07cee
HW		 3283 break;
3284 }
3285
3286 }
3287}
3288
3ee6b26b
AD		 3289static struct drm_display_mode *
3290amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3291 char *name,
3292 int hdisplay, int vdisplay)
e7b07cee
HW		 3293{
3294 struct drm_device *dev = encoder->dev;
3295 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3296 struct drm_display_mode *mode = NULL;
3297 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3298
3299 mode = drm_mode_duplicate(dev, native_mode);
3300
b830ebc9 3301 if (mode == NULL)
e7b07cee
HW		 3302 return NULL;
3303
3304 mode->hdisplay = hdisplay;
3305 mode->vdisplay = vdisplay;
3306 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3307 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3308
3309 return mode;
3310
3311}
3312
3313static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3314 struct drm_connector *connector)
e7b07cee
HW		 3315{
3316 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3317 struct drm_display_mode *mode = NULL;
3318 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3319 struct amdgpu_dm_connector *amdgpu_dm_connector =
3320 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3321 int i;
3322 int n;
3323 struct mode_size {
3324 char name[DRM_DISPLAY_MODE_LEN];
3325 int w;
3326 int h;
b830ebc9 3327 } common_modes[] = {
e7b07cee
HW		 3328 { "640x480", 640, 480},
3329 { "800x600", 800, 600},
3330 { "1024x768", 1024, 768},
3331 { "1280x720", 1280, 720},
3332 { "1280x800", 1280, 800},
3333 {"1280x1024", 1280, 1024},
3334 { "1440x900", 1440, 900},
3335 {"1680x1050", 1680, 1050},
3336 {"1600x1200", 1600, 1200},
3337 {"1920x1080", 1920, 1080},
3338 {"1920x1200", 1920, 1200}
3339 };
3340
b830ebc9 3341 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3342
3343 for (i = 0; i < n; i++) {
3344 struct drm_display_mode *curmode = NULL;
3345 bool mode_existed = false;
3346
3347 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3348 common_modes[i].h > native_mode->vdisplay ||
3349 (common_modes[i].w == native_mode->hdisplay &&
3350 common_modes[i].h == native_mode->vdisplay))
3351 continue;
e7b07cee
HW		 3352
3353 list_for_each_entry(curmode, &connector->probed_modes, head) {
3354 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3355 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3356 mode_existed = true;
3357 break;
3358 }
3359 }
3360
3361 if (mode_existed)
3362 continue;
3363
3364 mode = amdgpu_dm_create_common_mode(encoder,
3365 common_modes[i].name, common_modes[i].w,
3366 common_modes[i].h);
3367 drm_mode_probed_add(connector, mode);
c84dec2f 3368 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3369 }
3370}
3371
3ee6b26b
AD		 3372static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3373 struct edid *edid)
e7b07cee 3374{
c84dec2f
HW		 3375 struct amdgpu_dm_connector *amdgpu_dm_connector =
3376 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3377
3378 if (edid) {
3379 /* empty probed_modes */
3380 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3381 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3382 drm_add_edid_modes(connector, edid);
3383
e7b07cee 3384 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3385 } else {
c84dec2f 3386 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3387 }
e7b07cee
HW		 3388}
3389
7578ecda 3390static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3391{
3392 const struct drm_connector_helper_funcs *helper =
3393 connector->helper_private;
c84dec2f
HW		 3394 struct amdgpu_dm_connector *amdgpu_dm_connector =
3395 to_amdgpu_dm_connector(connector);
e7b07cee 3396 struct drm_encoder *encoder;
c84dec2f 3397 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3398
3399 encoder = helper->best_encoder(connector);
3400
3401 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3402 amdgpu_dm_connector_add_common_modes(encoder, connector);
c84dec2f 3403 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3404}
3405
3ee6b26b
AD		 3406void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3407 struct amdgpu_dm_connector *aconnector,
3408 int connector_type,
3409 struct dc_link *link,
3410 int link_index)
e7b07cee
HW		 3411{
3412 struct amdgpu_device *adev = dm->ddev->dev_private;
3413
3414 aconnector->connector_id = link_index;
3415 aconnector->dc_link = link;
3416 aconnector->base.interlace_allowed = false;
3417 aconnector->base.doublescan_allowed = false;
3418 aconnector->base.stereo_allowed = false;
3419 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3420 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3421
3422 mutex_init(&aconnector->hpd_lock);
3423
b830ebc9
HW		 3424 /* configure support HPD hot plug connector_>polled default value is 0
3425 * which means HPD hot plug not supported
3426 */
e7b07cee
HW		 3427 switch (connector_type) {
3428 case DRM_MODE_CONNECTOR_HDMIA:
3429 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3430 break;
3431 case DRM_MODE_CONNECTOR_DisplayPort:
3432 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3433 break;
3434 case DRM_MODE_CONNECTOR_DVID:
3435 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3436 break;
3437 default:
3438 break;
3439 }
3440
3441 drm_object_attach_property(&aconnector->base.base,
3442 dm->ddev->mode_config.scaling_mode_property,
3443 DRM_MODE_SCALE_NONE);
3444
3445 drm_object_attach_property(&aconnector->base.base,
3446 adev->mode_info.underscan_property,
3447 UNDERSCAN_OFF);
3448 drm_object_attach_property(&aconnector->base.base,
3449 adev->mode_info.underscan_hborder_property,
3450 0);
3451 drm_object_attach_property(&aconnector->base.base,
3452 adev->mode_info.underscan_vborder_property,
3453 0);
3454
3455}
3456
7578ecda
AD		 3457static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3458 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3459{
3460 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3461 struct ddc_service *ddc_service = i2c->ddc_service;
3462 struct i2c_command cmd;
3463 int i;
3464 int result = -EIO;
3465
b830ebc9 3466 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3467
3468 if (!cmd.payloads)
3469 return result;
3470
3471 cmd.number_of_payloads = num;
3472 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3473 cmd.speed = 100;
3474
3475 for (i = 0; i < num; i++) {
3476 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3477 cmd.payloads[i].address = msgs[i].addr;
3478 cmd.payloads[i].length = msgs[i].len;
3479 cmd.payloads[i].data = msgs[i].buf;
3480 }
3481
3482 if (dal_i2caux_submit_i2c_command(
3483 ddc_service->ctx->i2caux,
3484 ddc_service->ddc_pin,
3485 &cmd))
3486 result = num;
3487
3488 kfree(cmd.payloads);
3489 return result;
3490}
3491
7578ecda 3492static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3493{
3494 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3495}
3496
3497static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3498 .master_xfer = amdgpu_dm_i2c_xfer,
3499 .functionality = amdgpu_dm_i2c_func,
3500};
3501
3ee6b26b
AD		 3502static struct amdgpu_i2c_adapter *
3503create_i2c(struct ddc_service *ddc_service,
3504 int link_index,
3505 int *res)
e7b07cee
HW		 3506{
3507 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3508 struct amdgpu_i2c_adapter *i2c;
3509
b830ebc9 3510 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 3511 if (!i2c)
3512 return NULL;
e7b07cee
HW		 3513 i2c->base.owner = THIS_MODULE;
3514 i2c->base.class = I2C_CLASS_DDC;
3515 i2c->base.dev.parent = &adev->pdev->dev;
3516 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3517 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3518 i2c_set_adapdata(&i2c->base, i2c);
3519 i2c->ddc_service = ddc_service;
3520
3521 return i2c;
3522}
3523
3524/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3525 * dc_link which will be represented by this aconnector.
3526 */
7578ecda
AD		 3527static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3528 struct amdgpu_dm_connector *aconnector,
3529 uint32_t link_index,
3530 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3531{
3532 int res = 0;
3533 int connector_type;
3534 struct dc *dc = dm->dc;
3535 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3536 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 3537
3538 link->priv = aconnector;
e7b07cee 3539
f1ad2f5e 3540 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3541
3542 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 3543 if (!i2c) {
3544 DRM_ERROR("Failed to create i2c adapter data\n");
3545 return -ENOMEM;
3546 }
3547
e7b07cee
HW		 3548 aconnector->i2c = i2c;
3549 res = i2c_add_adapter(&i2c->base);
3550
3551 if (res) {
3552 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3553 goto out_free;
3554 }
3555
3556 connector_type = to_drm_connector_type(link->connector_signal);
3557
3558 res = drm_connector_init(
3559 dm->ddev,
3560 &aconnector->base,
3561 &amdgpu_dm_connector_funcs,
3562 connector_type);
3563
3564 if (res) {
3565 DRM_ERROR("connector_init failed\n");
3566 aconnector->connector_id = -1;
3567 goto out_free;
3568 }
3569
3570 drm_connector_helper_add(
3571 &aconnector->base,
3572 &amdgpu_dm_connector_helper_funcs);
3573
96719c54
HW		 3574 if (aconnector->base.funcs->reset)
3575 aconnector->base.funcs->reset(&aconnector->base);
3576
e7b07cee
HW		 3577 amdgpu_dm_connector_init_helper(
3578 dm,
3579 aconnector,
3580 connector_type,
3581 link,
3582 link_index);
3583
3584 drm_mode_connector_attach_encoder(
3585 &aconnector->base, &aencoder->base);
3586
3587 drm_connector_register(&aconnector->base);
3588
3589 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3590 || connector_type == DRM_MODE_CONNECTOR_eDP)
3591 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3592
3593#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3594 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3595
3596 /* NOTE: this currently will create backlight device even if a panel
3597 * is not connected to the eDP/LVDS connector.
3598 *
3599 * This is less than ideal but we don't have sink information at this
3600 * stage since detection happens after. We can't do detection earlier
3601 * since MST detection needs connectors to be created first.
3602 */
3603 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3604 /* Event if registration failed, we should continue with
3605 * DM initialization because not having a backlight control
b830ebc9
HW		 3606 * is better then a black screen.
3607 */
e7b07cee
HW		 3608 amdgpu_dm_register_backlight_device(dm);
3609
3610 if (dm->backlight_dev)
3611 dm->backlight_link = link;
3612 }
3613#endif
3614
3615out_free:
3616 if (res) {
3617 kfree(i2c);
3618 aconnector->i2c = NULL;
3619 }
3620 return res;
3621}
3622
3623int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3624{
3625 switch (adev->mode_info.num_crtc) {
3626 case 1:
3627 return 0x1;
3628 case 2:
3629 return 0x3;
3630 case 3:
3631 return 0x7;
3632 case 4:
3633 return 0xf;
3634 case 5:
3635 return 0x1f;
3636 case 6:
3637 default:
3638 return 0x3f;
3639 }
3640}
3641
7578ecda
AD		 3642static int amdgpu_dm_encoder_init(struct drm_device *dev,
3643 struct amdgpu_encoder *aencoder,
3644 uint32_t link_index)
e7b07cee
HW		 3645{
3646 struct amdgpu_device *adev = dev->dev_private;
3647
3648 int res = drm_encoder_init(dev,
3649 &aencoder->base,
3650 &amdgpu_dm_encoder_funcs,
3651 DRM_MODE_ENCODER_TMDS,
3652 NULL);
3653
3654 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3655
3656 if (!res)
3657 aencoder->encoder_id = link_index;
3658 else
3659 aencoder->encoder_id = -1;
3660
3661 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3662
3663 return res;
3664}
3665
3ee6b26b
AD		 3666static void manage_dm_interrupts(struct amdgpu_device *adev,
3667 struct amdgpu_crtc *acrtc,
3668 bool enable)
e7b07cee
HW		 3669{
3670 /*
3671 * this is not correct translation but will work as soon as VBLANK
3672 * constant is the same as PFLIP
3673 */
3674 int irq_type =
3675 amdgpu_crtc_idx_to_irq_type(
3676 adev,
3677 acrtc->crtc_id);
3678
3679 if (enable) {
3680 drm_crtc_vblank_on(&acrtc->base);
3681 amdgpu_irq_get(
3682 adev,
3683 &adev->pageflip_irq,
3684 irq_type);
3685 } else {
3686
3687 amdgpu_irq_put(
3688 adev,
3689 &adev->pageflip_irq,
3690 irq_type);
3691 drm_crtc_vblank_off(&acrtc->base);
3692 }
3693}
3694
3ee6b26b
AD		 3695static bool
3696is_scaling_state_different(const struct dm_connector_state *dm_state,
3697 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3698{
3699 if (dm_state->scaling != old_dm_state->scaling)
3700 return true;
3701 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3702 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3703 return true;
3704 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3705 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3706 return true;
b830ebc9
HW		 3707 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3708 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3709 return true;
e7b07cee
HW		 3710 return false;
3711}
3712
3ee6b26b
AD		 3713static void remove_stream(struct amdgpu_device *adev,
3714 struct amdgpu_crtc *acrtc,
3715 struct dc_stream_state *stream)
e7b07cee
HW		 3716{
3717 /* this is the update mode case */
3718 if (adev->dm.freesync_module)
3719 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3720
3721 acrtc->otg_inst = -1;
3722 acrtc->enabled = false;
3723}
3724
7578ecda
AD		 3725static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3726 struct dc_cursor_position *position)
2a8f6ccb
HW		 3727{
3728 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3729 int x, y;
3730 int xorigin = 0, yorigin = 0;
3731
3732 if (!crtc || !plane->state->fb) {
3733 position->enable = false;
3734 position->x = 0;
3735 position->y = 0;
3736 return 0;
3737 }
3738
3739 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3740 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3741 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3742 __func__,
3743 plane->state->crtc_w,
3744 plane->state->crtc_h);
3745 return -EINVAL;
3746 }
3747
3748 x = plane->state->crtc_x;
3749 y = plane->state->crtc_y;
3750 /* avivo cursor are offset into the total surface */
3751 x += crtc->primary->state->src_x >> 16;
3752 y += crtc->primary->state->src_y >> 16;
3753 if (x < 0) {
3754 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3755 x = 0;
3756 }
3757 if (y < 0) {
3758 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3759 y = 0;
3760 }
3761 position->enable = true;
3762 position->x = x;
3763 position->y = y;
3764 position->x_hotspot = xorigin;
3765 position->y_hotspot = yorigin;
3766
3767 return 0;
3768}
3769
3ee6b26b
AD		 3770static void handle_cursor_update(struct drm_plane *plane,
3771 struct drm_plane_state *old_plane_state)
e7b07cee 3772{
2a8f6ccb
HW		 3773 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3774 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3775 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3776 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3777 uint64_t address = afb ? afb->address : 0;
3778 struct dc_cursor_position position;
3779 struct dc_cursor_attributes attributes;
3780 int ret;
3781
e7b07cee
HW		 3782 if (!plane->state->fb && !old_plane_state->fb)
3783 return;
3784
f1ad2f5e 3785 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3786 __func__,
3787 amdgpu_crtc->crtc_id,
3788 plane->state->crtc_w,
3789 plane->state->crtc_h);
2a8f6ccb
HW		 3790
3791 ret = get_cursor_position(plane, crtc, &position);
3792 if (ret)
3793 return;
3794
3795 if (!position.enable) {
3796 /* turn off cursor */
3797 if (crtc_state && crtc_state->stream)
3798 dc_stream_set_cursor_position(crtc_state->stream,
3799 &position);
3800 return;
e7b07cee 3801 }
e7b07cee 3802
2a8f6ccb
HW		 3803 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3804 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3805
3806 attributes.address.high_part = upper_32_bits(address);
3807 attributes.address.low_part = lower_32_bits(address);
3808 attributes.width = plane->state->crtc_w;
3809 attributes.height = plane->state->crtc_h;
3810 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3811 attributes.rotation_angle = 0;
3812 attributes.attribute_flags.value = 0;
3813
3814 attributes.pitch = attributes.width;
3815
886daac9
JZ		 3816 if (crtc_state->stream) {
3817 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3818 &attributes))
3819 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3820
2a8f6ccb
HW		 3821 if (!dc_stream_set_cursor_position(crtc_state->stream,
3822 &position))
3823 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3824 }
2a8f6ccb 3825}
e7b07cee
HW		 3826
3827static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3828{
3829
3830 assert_spin_locked(&acrtc->base.dev->event_lock);
3831 WARN_ON(acrtc->event);
3832
3833 acrtc->event = acrtc->base.state->event;
3834
3835 /* Set the flip status */
3836 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3837
3838 /* Mark this event as consumed */
3839 acrtc->base.state->event = NULL;
3840
3841 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3842 acrtc->crtc_id);
3843}
3844
3845/*
3846 * Executes flip
3847 *
3848 * Waits on all BO's fences and for proper vblank count
3849 */
3ee6b26b
AD		 3850static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3851 struct drm_framebuffer *fb,
bc6828e0
BL		 3852 uint32_t target,
3853 struct dc_state *state)
e7b07cee
HW		 3854{
3855 unsigned long flags;
3856 uint32_t target_vblank;
3857 int r, vpos, hpos;
3858 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3859 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3860 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3861 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3862 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3863 struct dc_flip_addrs addr = { {0} };
3be5262e 3864 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3865 struct dc_surface_update surface_updates[1] = { {0} };
3866 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3867
3868
3869 /* Prepare wait for target vblank early - before the fence-waits */
3870 target_vblank = target - drm_crtc_vblank_count(crtc) +
3871 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3872
b830ebc9 3873 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3874 * explicitly on fences instead
3875 * and in general should be called for
3876 * blocking commit to as per framework helpers
b830ebc9 3877 */
e7b07cee
HW		 3878 r = amdgpu_bo_reserve(abo, true);
3879 if (unlikely(r != 0)) {
3880 DRM_ERROR("failed to reserve buffer before flip\n");
3881 WARN_ON(1);
3882 }
3883
3884 /* Wait for all fences on this FB */
3885 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3886 MAX_SCHEDULE_TIMEOUT) < 0);
3887
3888 amdgpu_bo_unreserve(abo);
3889
3890 /* Wait until we're out of the vertical blank period before the one
3891 * targeted by the flip
3892 */
3893 while ((acrtc->enabled &&
3894 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3895 &vpos, &hpos, NULL, NULL,
3896 &crtc->hwmode)
3897 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3898 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3899 (int)(target_vblank -
3900 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3901 usleep_range(1000, 1100);
3902 }
3903
3904 /* Flip */
3905 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3906 /* update crtc fb */
3907 crtc->primary->fb = fb;
3908
3909 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3910 WARN_ON(!acrtc_state->stream);
3911
3912 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3913 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3914 addr.flip_immediate = async_flip;
3915
3916
3917 if (acrtc->base.state->event)
3918 prepare_flip_isr(acrtc);
3919
3be5262e 3920 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3921 surface_updates->flip_addr = &addr;
3922
3923
bc6828e0
BL		 3924 dc_commit_updates_for_stream(adev->dm.dc,
3925 surface_updates,
3926 1,
3927 acrtc_state->stream,
3928 NULL,
3929 &surface_updates->surface,
3930 state);
e7b07cee
HW		 3931
3932 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3933 __func__,
3934 addr.address.grph.addr.high_part,
3935 addr.address.grph.addr.low_part);
3936
3937
3938 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3939}
3940
3be5262e 3941static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 3942 struct drm_device *dev,
3943 struct amdgpu_display_manager *dm,
3944 struct drm_crtc *pcrtc,
3945 bool *wait_for_vblank)
e7b07cee
HW		 3946{
3947 uint32_t i;
3948 struct drm_plane *plane;
0bc9706d 3949 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 3950 struct dc_stream_state *dc_stream_attach;
3be5262e 3951 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 3952 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 3953 struct drm_crtc_state *new_pcrtc_state =
3954 drm_atomic_get_new_crtc_state(state, pcrtc);
3955 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
bc6828e0 3956 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 3957 int planes_count = 0;
3958 unsigned long flags;
3959
3960 /* update planes when needed */
0bc9706d
LSL		 3961 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3962 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 3963 struct drm_crtc_state *new_crtc_state;
0bc9706d 3964 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 3965 bool pflip_needed;
54d76575 3966 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 3967
3968 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3969 handle_cursor_update(plane, old_plane_state);
3970 continue;
3971 }
3972
f5ba60fe
DD		 3973 if (!fb || !crtc || pcrtc != crtc)
3974 continue;
3975
3976 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
3977 if (!new_crtc_state->active)
e7b07cee
HW		 3978 continue;
3979
3980 pflip_needed = !state->allow_modeset;
3981
3982 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3983 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3984 DRM_ERROR("%s: acrtc %d, already busy\n",
3985 __func__,
3986 acrtc_attach->crtc_id);
b830ebc9 3987 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3988 WARN_ON(1);
3989 }
3990 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3991
3992 if (!pflip_needed) {
54d76575 3993 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 3994
54d76575 3995 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 3996
3997 dc_stream_attach = acrtc_state->stream;
3998 planes_count++;
3999
0bc9706d 4000 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 4001 /* Assume even ONE crtc with immediate flip means
4002 * entire can't wait for VBLANK
4003 * TODO Check if it's correct
4004 */
4005 *wait_for_vblank =
0bc9706d 4006 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 4007 false : true;
4008
4009 /* TODO: Needs rework for multiplane flip */
4010 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4011 drm_crtc_vblank_get(crtc);
4012
4013 amdgpu_dm_do_flip(
4014 crtc,
4015 fb,
bc6828e0
BL		 4016 drm_crtc_vblank_count(crtc) + *wait_for_vblank,
4017 dm_state->context);
e7b07cee
HW		 4018 }
4019
4020 }
4021
4022 if (planes_count) {
4023 unsigned long flags;
4024
0bc9706d 4025 if (new_pcrtc_state->event) {
e7b07cee
HW		 4026
4027 drm_crtc_vblank_get(pcrtc);
4028
4029 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4030 prepare_flip_isr(acrtc_attach);
4031 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4032 }
4033
3be5262e
HW		 4034 if (false == dc_commit_planes_to_stream(dm->dc,
4035 plane_states_constructed,
4036 planes_count,
bc6828e0
BL		 4037 dc_stream_attach,
4038 dm_state->context))
3be5262e 4039 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4040 } else {
4041 /*TODO BUG Here should go disable planes on CRTC. */
4042 }
4043}
4044
27b3f4fc
LSL		 4045/**
4046 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4047 * @crtc_state: the DRM CRTC state
4048 * @stream_state: the DC stream state.
4049 *
4050 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4051 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4052 */
4053static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4054 struct dc_stream_state *stream_state)
4055{
4056 stream_state->mode_changed = crtc_state->mode_changed;
4057}
e7b07cee 4058
7578ecda
AD		 4059static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4060 struct drm_atomic_state *state,
4061 bool nonblock)
e7b07cee
HW		 4062{
4063 struct drm_crtc *crtc;
c2cea706 4064 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4065 struct amdgpu_device *adev = dev->dev_private;
4066 int i;
4067
4068 /*
4069 * We evade vblanks and pflips on crtc that
4070 * should be changed. We do it here to flush & disable
4071 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4072 * it will update crtc->dm_crtc_state->stream pointer which is used in
4073 * the ISRs.
4074 */
c2cea706 4075 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4076 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 4077 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4078
54d76575 4079 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 4080 manage_dm_interrupts(adev, acrtc, false);
4081 }
fc9e9920
S		 4082 /* Add check here for SoC's that support hardware cursor plane, to
4083 * unset legacy_cursor_update */
e7b07cee
HW		 4084
4085 return drm_atomic_helper_commit(dev, state, nonblock);
4086
4087 /*TODO Handle EINTR, reenable IRQ*/
4088}
4089
7578ecda 4090static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4091{
4092 struct drm_device *dev = state->dev;
4093 struct amdgpu_device *adev = dev->dev_private;
4094 struct amdgpu_display_manager *dm = &adev->dm;
4095 struct dm_atomic_state *dm_state;
4096 uint32_t i, j;
5cc6dcbd 4097 struct drm_crtc *crtc;
0bc9706d 4098 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4099 unsigned long flags;
4100 bool wait_for_vblank = true;
4101 struct drm_connector *connector;
c2cea706 4102 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4103 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
e7b07cee
HW		 4104
4105 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4106
4107 dm_state = to_dm_atomic_state(state);
4108
4109 /* update changed items */
0bc9706d 4110 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4111 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4112
54d76575
LSL		 4113 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4114 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4115
f1ad2f5e 4116 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4117 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4118 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4119 "connectors_changed:%d\n",
4120 acrtc->crtc_id,
0bc9706d
LSL		 4121 new_crtc_state->enable,
4122 new_crtc_state->active,
4123 new_crtc_state->planes_changed,
4124 new_crtc_state->mode_changed,
4125 new_crtc_state->active_changed,
4126 new_crtc_state->connectors_changed);
e7b07cee 4127
27b3f4fc
LSL		 4128 /* Copy all transient state flags into dc state */
4129 if (dm_new_crtc_state->stream) {
4130 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4131 dm_new_crtc_state->stream);
4132 }
4133
e7b07cee
HW		 4134 /* handles headless hotplug case, updating new_state and
4135 * aconnector as needed
4136 */
4137
54d76575 4138 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4139
f1ad2f5e 4140 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4141
54d76575 4142 if (!dm_new_crtc_state->stream) {
e7b07cee 4143 /*
b830ebc9
HW		 4144 * this could happen because of issues with
4145 * userspace notifications delivery.
4146 * In this case userspace tries to set mode on
4147 * display which is disconnect in fact.
4148 * dc_sink in NULL in this case on aconnector.
4149 * We expect reset mode will come soon.
4150 *
4151 * This can also happen when unplug is done
4152 * during resume sequence ended
4153 *
4154 * In this case, we want to pretend we still
4155 * have a sink to keep the pipe running so that
4156 * hw state is consistent with the sw state
4157 */
f1ad2f5e 4158 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4159 __func__, acrtc->base.base.id);
4160 continue;
4161 }
4162
54d76575
LSL		 4163 if (dm_old_crtc_state->stream)
4164 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 4165
e7b07cee 4166 acrtc->enabled = true;
0bc9706d
LSL		 4167 acrtc->hw_mode = new_crtc_state->mode;
4168 crtc->hwmode = new_crtc_state->mode;
4169 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4170 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4171
4172 /* i.e. reset mode */
54d76575
LSL		 4173 if (dm_old_crtc_state->stream)
4174 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4175 }
4176 } /* for_each_crtc_in_state() */
4177
4178 /*
4179 * Add streams after required streams from new and replaced streams
4180 * are removed from freesync module
4181 */
4182 if (adev->dm.freesync_module) {
8b8f27f9
LSL		 4183 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4184 new_crtc_state, i) {
c84dec2f 4185 struct amdgpu_dm_connector *aconnector = NULL;
f01a2cf0
LSL		 4186 struct dm_connector_state *dm_new_con_state = NULL;
4187 struct amdgpu_crtc *acrtc = NULL;
1c77d4ee 4188 bool modeset_needed;
b830ebc9 4189
54d76575 4190 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1c77d4ee
LSL		 4191 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4192 modeset_needed = modeset_required(
4193 new_crtc_state,
4194 dm_new_crtc_state->stream,
4195 dm_old_crtc_state->stream);
4196 /* We add stream to freesync if:
4197 * 1. Said stream is not null, and
4198 * 2. A modeset is requested. This means that the
4199 * stream was removed previously, and needs to be
4200 * replaced.
4201 */
4202 if (dm_new_crtc_state->stream == NULL ||
4203 !modeset_needed)
4204 continue;
4205
f01a2cf0 4206 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4207
f01a2cf0
LSL		 4208 aconnector =
4209 amdgpu_dm_find_first_crtc_matching_connector(
4210 state, crtc);
e7b07cee 4211 if (!aconnector) {
8b8f27f9
LSL		 4212 DRM_DEBUG_DRIVER("Atomic commit: Failed to "
4213 "find connector for acrtc "
4214 "id:%d skipping freesync "
4215 "init\n",
4216 acrtc->crtc_id);
e7b07cee
HW		 4217 continue;
4218 }
4219
4220 mod_freesync_add_stream(adev->dm.freesync_module,
f01a2cf0
LSL		 4221 dm_new_crtc_state->stream,
4222 &aconnector->caps);
4223 new_con_state = drm_atomic_get_new_connector_state(
4224 state, &aconnector->base);
4225 dm_new_con_state = to_dm_connector_state(new_con_state);
4226
1c77d4ee
LSL		 4227 mod_freesync_set_user_enable(adev->dm.freesync_module,
4228 &dm_new_crtc_state->stream,
4229 1,
4230 &dm_new_con_state->user_enable);
bfe1708c 4231 }
e7b07cee
HW		 4232 }
4233
fa2123db
ML		 4234 if (dm_state->context) {
4235 dm_enable_per_frame_crtc_master_sync(dm_state->context);
608ac7bb 4236 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
fa2123db 4237 }
e7b07cee 4238
0bc9706d 4239 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4240 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4241
54d76575 4242 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4243
54d76575 4244 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4245 const struct dc_stream_status *status =
54d76575 4246 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4247
4248 if (!status)
54d76575 4249 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4250 else
4251 acrtc->otg_inst = status->primary_otg_inst;
4252 }
4253 }
4254
ebdd27e1 4255 /* Handle scaling and underscan changes*/
c2cea706 4256 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4257 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4258 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4259 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4260 struct dc_stream_status *status = NULL;
4261
0bc9706d
LSL		 4262 if (acrtc)
4263 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4264
e7b07cee 4265 /* Skip any modesets/resets */
0bc9706d 4266 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4267 continue;
4268
4269 /* Skip any thing not scale or underscan changes */
54d76575 4270 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4271 continue;
4272
54d76575 4273 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4274
54d76575
LSL		 4275 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4276 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4277
70e8ffc5
HW		 4278 if (!dm_new_crtc_state->stream)
4279 continue;
4280
54d76575 4281 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4282 WARN_ON(!status);
3be5262e 4283 WARN_ON(!status->plane_count);
e7b07cee 4284
e7b07cee 4285 /*TODO How it works with MPO ?*/
3be5262e 4286 if (!dc_commit_planes_to_stream(
e7b07cee 4287 dm->dc,
3be5262e
HW		 4288 status->plane_states,
4289 status->plane_count,
bc6828e0
BL		 4290 dm_new_crtc_state->stream,
4291 dm_state->context))
e7b07cee
HW		 4292 dm_error("%s: Failed to update stream scaling!\n", __func__);
4293 }
4294
e1fc2dca
LSL		 4295 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4296 new_crtc_state, i) {
e7b07cee
HW		 4297 /*
4298 * loop to enable interrupts on newly arrived crtc
4299 */
e1fc2dca
LSL		 4300 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4301 bool modeset_needed;
b830ebc9 4302
54d76575 4303 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 4304 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4305 modeset_needed = modeset_required(
4306 new_crtc_state,
4307 dm_new_crtc_state->stream,
4308 dm_old_crtc_state->stream);
4309
4310 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4311 continue;
e7b07cee
HW		 4312
4313 if (adev->dm.freesync_module)
4314 mod_freesync_notify_mode_change(
e1fc2dca
LSL		 4315 adev->dm.freesync_module,
4316 &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4317
4318 manage_dm_interrupts(adev, acrtc, true);
4319 }
4320
4321 /* update planes when needed per crtc*/
5cc6dcbd 4322 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4323 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4324
54d76575 4325 if (dm_new_crtc_state->stream)
5cc6dcbd 4326 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4327 }
4328
4329
4330 /*
4331 * send vblank event on all events not handled in flip and
4332 * mark consumed event for drm_atomic_helper_commit_hw_done
4333 */
4334 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4335 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4336
0bc9706d
LSL		 4337 if (new_crtc_state->event)
4338 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4339
0bc9706d 4340 new_crtc_state->event = NULL;
e7b07cee
HW		 4341 }
4342 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4343
4344 /* Signal HW programming completion */
4345 drm_atomic_helper_commit_hw_done(state);
4346
4347 if (wait_for_vblank)
320a1274 4348 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 4349
4350 drm_atomic_helper_cleanup_planes(dev, state);
4351}
4352
4353
4354static int dm_force_atomic_commit(struct drm_connector *connector)
4355{
4356 int ret = 0;
4357 struct drm_device *ddev = connector->dev;
4358 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4359 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4360 struct drm_plane *plane = disconnected_acrtc->base.primary;
4361 struct drm_connector_state *conn_state;
4362 struct drm_crtc_state *crtc_state;
4363 struct drm_plane_state *plane_state;
4364
4365 if (!state)
4366 return -ENOMEM;
4367
4368 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4369
4370 /* Construct an atomic state to restore previous display setting */
4371
4372 /*
4373 * Attach connectors to drm_atomic_state
4374 */
4375 conn_state = drm_atomic_get_connector_state(state, connector);
4376
4377 ret = PTR_ERR_OR_ZERO(conn_state);
4378 if (ret)
4379 goto err;
4380
4381 /* Attach crtc to drm_atomic_state*/
4382 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4383
4384 ret = PTR_ERR_OR_ZERO(crtc_state);
4385 if (ret)
4386 goto err;
4387
4388 /* force a restore */
4389 crtc_state->mode_changed = true;
4390
4391 /* Attach plane to drm_atomic_state */
4392 plane_state = drm_atomic_get_plane_state(state, plane);
4393
4394 ret = PTR_ERR_OR_ZERO(plane_state);
4395 if (ret)
4396 goto err;
4397
4398
4399 /* Call commit internally with the state we just constructed */
4400 ret = drm_atomic_commit(state);
4401 if (!ret)
4402 return 0;
4403
4404err:
4405 DRM_ERROR("Restoring old state failed with %i\n", ret);
4406 drm_atomic_state_put(state);
4407
4408 return ret;
4409}
4410
4411/*
4412 * This functions handle all cases when set mode does not come upon hotplug.
4413 * This include when the same display is unplugged then plugged back into the
4414 * same port and when we are running without usermode desktop manager supprot
4415 */
3ee6b26b
AD		 4416void dm_restore_drm_connector_state(struct drm_device *dev,
4417 struct drm_connector *connector)
e7b07cee 4418{
c84dec2f 4419 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4420 struct amdgpu_crtc *disconnected_acrtc;
4421 struct dm_crtc_state *acrtc_state;
4422
4423 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4424 return;
4425
4426 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 4427 if (!disconnected_acrtc)
4428 return;
e7b07cee 4429
70e8ffc5
HW		 4430 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4431 if (!acrtc_state->stream)
e7b07cee
HW		 4432 return;
4433
4434 /*
4435 * If the previous sink is not released and different from the current,
4436 * we deduce we are in a state where we can not rely on usermode call
4437 * to turn on the display, so we do it here
4438 */
4439 if (acrtc_state->stream->sink != aconnector->dc_sink)
4440 dm_force_atomic_commit(&aconnector->base);
4441}
4442
e7b07cee
HW		 4443/*`
4444 * Grabs all modesetting locks to serialize against any blocking commits,
4445 * Waits for completion of all non blocking commits.
4446 */
3ee6b26b
AD		 4447static int do_aquire_global_lock(struct drm_device *dev,
4448 struct drm_atomic_state *state)
e7b07cee
HW		 4449{
4450 struct drm_crtc *crtc;
4451 struct drm_crtc_commit *commit;
4452 long ret;
4453
4454 /* Adding all modeset locks to aquire_ctx will
4455 * ensure that when the framework release it the
4456 * extra locks we are locking here will get released to
4457 */
4458 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4459 if (ret)
4460 return ret;
4461
4462 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4463 spin_lock(&crtc->commit_lock);
4464 commit = list_first_entry_or_null(&crtc->commit_list,
4465 struct drm_crtc_commit, commit_entry);
4466 if (commit)
4467 drm_crtc_commit_get(commit);
4468 spin_unlock(&crtc->commit_lock);
4469
4470 if (!commit)
4471 continue;
4472
4473 /* Make sure all pending HW programming completed and
4474 * page flips done
4475 */
4476 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4477
4478 if (ret > 0)
4479 ret = wait_for_completion_interruptible_timeout(
4480 &commit->flip_done, 10*HZ);
4481
4482 if (ret == 0)
4483 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4484 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4485
4486 drm_crtc_commit_put(commit);
4487 }
4488
4489 return ret < 0 ? ret : 0;
4490}
4491
3ee6b26b
AD		 4492static int dm_update_crtcs_state(struct dc *dc,
4493 struct drm_atomic_state *state,
4494 bool enable,
4495 bool *lock_and_validation_needed)
e7b07cee 4496{
e7b07cee 4497 struct drm_crtc *crtc;
c2cea706 4498 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4499 int i;
54d76575 4500 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4501 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4502 struct dc_stream_state *new_stream;
62f55537 4503 int ret = 0;
d4d4a645 4504
62f55537
AG		 4505 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4506 /* update changed items */
c2cea706 4507 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4508 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4509 struct amdgpu_dm_connector *aconnector = NULL;
c2cea706 4510 struct drm_connector_state *new_con_state = NULL;
62f55537 4511 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4512
9635b754
DS		 4513 new_stream = NULL;
4514
54d76575
LSL		 4515 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4516 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4517 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4518
1daf8c63 4519 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4520
62f55537 4521 /* TODO This hack should go away */
f4ac176e
JZ		 4522 if (aconnector && enable) {
4523 // Make sure fake sink is created in plug-in scenario
c2cea706
LSL		 4524 new_con_state = drm_atomic_get_connector_state(state,
4525 &aconnector->base);
19f89e23 4526
c2cea706
LSL		 4527 if (IS_ERR(new_con_state)) {
4528 ret = PTR_ERR_OR_ZERO(new_con_state);
62f55537
AG		 4529 break;
4530 }
19f89e23 4531
c2cea706 4532 dm_conn_state = to_dm_connector_state(new_con_state);
19f89e23 4533
62f55537 4534 new_stream = create_stream_for_sink(aconnector,
c2cea706 4535 &new_crtc_state->mode,
62f55537 4536 dm_conn_state);
19f89e23 4537
62f55537
AG		 4538 /*
4539 * we can have no stream on ACTION_SET if a display
4540 * was disconnected during S3, in this case it not and
4541 * error, the OS will be updated after detection, and
4542 * do the right thing on next atomic commit
4543 */
19f89e23 4544
62f55537 4545 if (!new_stream) {
f1ad2f5e 4546 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4547 __func__, acrtc->base.base.id);
4548 break;
19f89e23 4549 }
e7b07cee 4550
a97599a4
LSL		 4551 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4552 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4553 new_crtc_state->mode_changed = false;
4554 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4555 new_crtc_state->mode_changed);
4556 }
62f55537 4557 }
b830ebc9 4558
c2cea706 4559 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4560 goto next_crtc;
e7b07cee 4561
f1ad2f5e 4562 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4563 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4564 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4565 "connectors_changed:%d\n",
4566 acrtc->crtc_id,
c2cea706
LSL		 4567 new_crtc_state->enable,
4568 new_crtc_state->active,
4569 new_crtc_state->planes_changed,
4570 new_crtc_state->mode_changed,
4571 new_crtc_state->active_changed,
4572 new_crtc_state->connectors_changed);
e7b07cee 4573
62f55537
AG		 4574 /* Remove stream for any changed/disabled CRTC */
4575 if (!enable) {
4576
54d76575 4577 if (!dm_old_crtc_state->stream)
9635b754 4578 goto next_crtc;
62f55537 4579
f1ad2f5e 4580 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4581 crtc->base.id);
e7b07cee 4582
1dc90497 4583 /* i.e. reset mode */
62c933f9 4584 if (dc_remove_stream_from_ctx(
62f55537
AG		 4585 dc,
4586 dm_state->context,
62c933f9 4587 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4588 ret = -EINVAL;
9635b754 4589 goto fail;
62f55537
AG		 4590 }
4591
54d76575
LSL		 4592 dc_stream_release(dm_old_crtc_state->stream);
4593 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4594
4595 *lock_and_validation_needed = true;
4596
4597 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4598 /*
4599 * Quick fix to prevent NULL pointer on new_stream when
4600 * added MST connectors not found in existing crtc_state in the chained mode
4601 * TODO: need to dig out the root cause of that
4602 */
4603 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4604 goto next_crtc;
62f55537 4605
c2cea706 4606 if (modereset_required(new_crtc_state))
9635b754 4607 goto next_crtc;
62f55537 4608
c2cea706 4609 if (modeset_required(new_crtc_state, new_stream,
54d76575 4610 dm_old_crtc_state->stream)) {
62f55537 4611
54d76575 4612 WARN_ON(dm_new_crtc_state->stream);
62f55537 4613
54d76575 4614 dm_new_crtc_state->stream = new_stream;
27b3f4fc 4615
62f55537
AG		 4616 dc_stream_retain(new_stream);
4617
f1ad2f5e 4618 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4619 crtc->base.id);
1dc90497 4620
13ab1b44 4621 if (dc_add_stream_to_ctx(
1dc90497
AG		 4622 dc,
4623 dm_state->context,
13ab1b44 4624 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4625 ret = -EINVAL;
9635b754 4626 goto fail;
1dc90497
AG		 4627 }
4628
62f55537 4629 *lock_and_validation_needed = true;
9b690ef3 4630 }
62f55537 4631 }
9b690ef3 4632
9635b754 4633next_crtc:
62f55537
AG		 4634 /* Release extra reference */
4635 if (new_stream)
4636 dc_stream_release(new_stream);
4637 }
e7b07cee 4638
62f55537 4639 return ret;
9635b754
DS		 4640
4641fail:
4642 if (new_stream)
4643 dc_stream_release(new_stream);
4644 return ret;
62f55537 4645}
9b690ef3 4646
3ee6b26b
AD		 4647static int dm_update_planes_state(struct dc *dc,
4648 struct drm_atomic_state *state,
4649 bool enable,
4650 bool *lock_and_validation_needed)
62f55537
AG		 4651{
4652 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4653 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4654 struct drm_plane *plane;
4655 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4656 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4657 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4658 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4659 int i ;
4660 /* TODO return page_flip_needed() function */
4661 bool pflip_needed = !state->allow_modeset;
4662 int ret = 0;
e7b07cee 4663
62f55537
AG		 4664 if (pflip_needed)
4665 return ret;
9b690ef3 4666
62f55537
AG		 4667 /* Add new planes */
4668 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4669 new_plane_crtc = new_plane_state->crtc;
4670 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4671 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4672 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4673
4674 /*TODO Implement atomic check for cursor plane */
4675 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4676 continue;
9b690ef3 4677
62f55537
AG		 4678 /* Remove any changed/removed planes */
4679 if (!enable) {
a7b06724 4680
62f55537
AG		 4681 if (!old_plane_crtc)
4682 continue;
4683
0bc9706d
LSL		 4684 old_crtc_state = drm_atomic_get_old_crtc_state(
4685 state, old_plane_crtc);
54d76575 4686 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4687
54d76575 4688 if (!dm_old_crtc_state->stream)
62f55537
AG		 4689 continue;
4690
f1ad2f5e 4691 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4692 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4693
62f55537
AG		 4694 if (!dc_remove_plane_from_context(
4695 dc,
54d76575
LSL		 4696 dm_old_crtc_state->stream,
4697 dm_old_plane_state->dc_state,
62f55537
AG		 4698 dm_state->context)) {
4699
4700 ret = EINVAL;
4701 return ret;
e7b07cee
HW		 4702 }
4703
9b690ef3 4704
54d76575
LSL		 4705 dc_plane_state_release(dm_old_plane_state->dc_state);
4706 dm_new_plane_state->dc_state = NULL;
1dc90497 4707
62f55537 4708 *lock_and_validation_needed = true;
1dc90497 4709
62f55537 4710 } else { /* Add new planes */
1dc90497 4711
62f55537
AG		 4712 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4713 continue;
e7b07cee 4714
62f55537
AG		 4715 if (!new_plane_crtc)
4716 continue;
e7b07cee 4717
62f55537 4718 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4719 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4720
54d76575 4721 if (!dm_new_crtc_state->stream)
62f55537
AG		 4722 continue;
4723
4724
54d76575 4725 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4726
54d76575 4727 dm_new_plane_state->dc_state = dc_create_plane_state(dc);
62f55537 4728
f1ad2f5e 4729 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
62f55537
AG		 4730 plane->base.id, new_plane_crtc->base.id);
4731
54d76575 4732 if (!dm_new_plane_state->dc_state) {
62f55537
AG		 4733 ret = -EINVAL;
4734 return ret;
4735 }
4736
4737 ret = fill_plane_attributes(
4738 new_plane_crtc->dev->dev_private,
54d76575 4739 dm_new_plane_state->dc_state,
62f55537 4740 new_plane_state,
9817d5f5 4741 new_crtc_state);
62f55537
AG		 4742 if (ret)
4743 return ret;
4744
4745
4746 if (!dc_add_plane_to_context(
4747 dc,
54d76575
LSL		 4748 dm_new_crtc_state->stream,
4749 dm_new_plane_state->dc_state,
62f55537
AG		 4750 dm_state->context)) {
4751
4752 ret = -EINVAL;
4753 return ret;
e7b07cee 4754 }
62f55537 4755
000b59ea
LSL		 4756 /* Tell DC to do a full surface update every time there
4757 * is a plane change. Inefficient, but works for now.
4758 */
4759 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
4760
62f55537 4761 *lock_and_validation_needed = true;
e7b07cee 4762 }
62f55537 4763 }
e7b07cee
HW		 4764
4765
62f55537
AG		 4766 return ret;
4767}
4768
7578ecda
AD		 4769static int amdgpu_dm_atomic_check(struct drm_device *dev,
4770 struct drm_atomic_state *state)
62f55537 4771{
62f55537
AG		 4772 struct amdgpu_device *adev = dev->dev_private;
4773 struct dc *dc = adev->dm.dc;
4774 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4775 struct drm_connector *connector;
c2cea706 4776 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4777 struct drm_crtc *crtc;
fc9e9920 4778 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1e88ad0a 4779 int ret, i;
e7b07cee 4780
62f55537
AG		 4781 /*
4782 * This bool will be set for true for any modeset/reset
4783 * or plane update which implies non fast surface update.
4784 */
4785 bool lock_and_validation_needed = false;
4786
4787 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 4788 if (ret)
4789 goto fail;
62f55537 4790
1e88ad0a
S		 4791 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4792 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
4793 !new_crtc_state->color_mgmt_changed)
4794 continue;
7bef1af3 4795
1e88ad0a
S		 4796 if (!new_crtc_state->enable)
4797 continue;
fc9e9920 4798
1e88ad0a
S		 4799 ret = drm_atomic_add_affected_connectors(state, crtc);
4800 if (ret)
4801 return ret;
fc9e9920 4802
1e88ad0a
S		 4803 ret = drm_atomic_add_affected_planes(state, crtc);
4804 if (ret)
4805 goto fail;
e7b07cee
HW		 4806 }
4807
62f55537
AG		 4808 dm_state->context = dc_create_state();
4809 ASSERT(dm_state->context);
f36cc577 4810 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4811
4812 /* Remove exiting planes if they are modified */
4813 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4814 if (ret) {
4815 goto fail;
4816 }
4817
4818 /* Disable all crtcs which require disable */
4819 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4820 if (ret) {
4821 goto fail;
4822 }
4823
4824 /* Enable all crtcs which require enable */
4825 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4826 if (ret) {
4827 goto fail;
4828 }
4829
4830 /* Add new/modified planes */
4831 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4832 if (ret) {
4833 goto fail;
4834 }
4835
b349f76e
ES		 4836 /* Run this here since we want to validate the streams we created */
4837 ret = drm_atomic_helper_check_planes(dev, state);
4838 if (ret)
4839 goto fail;
62f55537 4840
ebdd27e1 4841 /* Check scaling and underscan changes*/
e7b07cee
HW		 4842 /*TODO Removed scaling changes validation due to inability to commit
4843 * new stream into context w\o causing full reset. Need to
4844 * decide how to handle.
4845 */
c2cea706 4846 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4847 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4848 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4849 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4850
4851 /* Skip any modesets/resets */
0bc9706d
LSL		 4852 if (!acrtc || drm_atomic_crtc_needs_modeset(
4853 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 4854 continue;
4855
b830ebc9 4856 /* Skip any thing not scale or underscan changes */
54d76575 4857 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4858 continue;
4859
4860 lock_and_validation_needed = true;
4861 }
4862
e7b07cee
HW		 4863 /*
4864 * For full updates case when
4865 * removing/adding/updating streams on once CRTC while flipping
4866 * on another CRTC,
4867 * acquiring global lock will guarantee that any such full
4868 * update commit
4869 * will wait for completion of any outstanding flip using DRMs
4870 * synchronization events.
4871 */
4872
4873 if (lock_and_validation_needed) {
4874
4875 ret = do_aquire_global_lock(dev, state);
4876 if (ret)
4877 goto fail;
1dc90497 4878
e750d56d 4879 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 4880 ret = -EINVAL;
4881 goto fail;
4882 }
4883 }
4884
4885 /* Must be success */
4886 WARN_ON(ret);
4887 return ret;
4888
4889fail:
4890 if (ret == -EDEADLK)
01e28f9c 4891 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 4892 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 4893 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 4894 else
01e28f9c 4895 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 4896
4897 return ret;
4898}
4899
3ee6b26b
AD		 4900static bool is_dp_capable_without_timing_msa(struct dc *dc,
4901 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 4902{
4903 uint8_t dpcd_data;
4904 bool capable = false;
4905
c84dec2f 4906 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 4907 dm_helpers_dp_read_dpcd(
4908 NULL,
c84dec2f 4909 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 4910 DP_DOWN_STREAM_PORT_COUNT,
4911 &dpcd_data,
4912 sizeof(dpcd_data))) {
4913 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4914 }
4915
4916 return capable;
4917}
3ee6b26b
AD		 4918void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4919 struct edid *edid)
e7b07cee
HW		 4920{
4921 int i;
4922 uint64_t val_capable;
4923 bool edid_check_required;
4924 struct detailed_timing *timing;
4925 struct detailed_non_pixel *data;
4926 struct detailed_data_monitor_range *range;
c84dec2f
HW		 4927 struct amdgpu_dm_connector *amdgpu_dm_connector =
4928 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4929
4930 struct drm_device *dev = connector->dev;
4931 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4932
e7b07cee 4933 edid_check_required = false;
c84dec2f 4934 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 4935 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4936 return;
4937 }
4938 if (!adev->dm.freesync_module)
4939 return;
4940 /*
4941 * if edid non zero restrict freesync only for dp and edp
4942 */
4943 if (edid) {
c84dec2f
HW		 4944 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4945 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 4946 edid_check_required = is_dp_capable_without_timing_msa(
4947 adev->dm.dc,
c84dec2f 4948 amdgpu_dm_connector);
e7b07cee
HW		 4949 }
4950 }
4951 val_capable = 0;
4952 if (edid_check_required == true && (edid->version > 1 ||
4953 (edid->version == 1 && edid->revision > 1))) {
4954 for (i = 0; i < 4; i++) {
4955
4956 timing = &edid->detailed_timings[i];
4957 data = &timing->data.other_data;
4958 range = &data->data.range;
4959 /*
4960 * Check if monitor has continuous frequency mode
4961 */
4962 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4963 continue;
4964 /*
4965 * Check for flag range limits only. If flag == 1 then
4966 * no additional timing information provided.
4967 * Default GTF, GTF Secondary curve and CVT are not
4968 * supported
4969 */
4970 if (range->flags != 1)
4971 continue;
4972
c84dec2f
HW		 4973 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
4974 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
4975 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 4976 range->pixel_clock_mhz * 10;
4977 break;
4978 }
4979
c84dec2f
HW		 4980 if (amdgpu_dm_connector->max_vfreq -
4981 amdgpu_dm_connector->min_vfreq > 10) {
4982 amdgpu_dm_connector->caps.supported = true;
4983 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
4984 amdgpu_dm_connector->min_vfreq * 1000000;
4985 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
4986 amdgpu_dm_connector->max_vfreq * 1000000;
e7b07cee
HW		 4987 val_capable = 1;
4988 }
4989 }
4990
4991 /*
4992 * TODO figure out how to notify user-mode or DRM of freesync caps
4993 * once we figure out how to deal with freesync in an upstreamable
4994 * fashion
4995 */
4996
4997}
4998
3ee6b26b 4999void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 5000{
5001 /*
5002 * TODO fill in once we figure out how to deal with freesync in
5003 * an upstreamable fashion
5004 */
5005}
Linux 6.x block layer and io_uring tree(s)