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drm/amd/display: fix brightness level after resume from suspend
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
ad941f7a
FX		 62#include "dcn/dcn_1_0_offset.h"
63#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 64#include "soc15_hw_ip.h"
65#include "vega10_ip_offset.h"
ff5ef992
AD		 66
67#include "soc15_common.h"
68#endif
69
e7b07cee
HW		 70#include "modules/inc/mod_freesync.h"
71
72#include "i2caux_interface.h"
73
7578ecda
AD		 74/* basic init/fini API */
75static int amdgpu_dm_init(struct amdgpu_device *adev);
76static void amdgpu_dm_fini(struct amdgpu_device *adev);
77
78/* initializes drm_device display related structures, based on the information
79 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
80 * drm_encoder, drm_mode_config
81 *
82 * Returns 0 on success
83 */
84static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
85/* removes and deallocates the drm structures, created by the above function */
86static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
87
88static void
89amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
90
91static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
92 struct amdgpu_plane *aplane,
93 unsigned long possible_crtcs);
94static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
95 struct drm_plane *plane,
96 uint32_t link_index);
97static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
98 struct amdgpu_dm_connector *amdgpu_dm_connector,
99 uint32_t link_index,
100 struct amdgpu_encoder *amdgpu_encoder);
101static int amdgpu_dm_encoder_init(struct drm_device *dev,
102 struct amdgpu_encoder *aencoder,
103 uint32_t link_index);
104
105static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
106
107static int amdgpu_dm_atomic_commit(struct drm_device *dev,
108 struct drm_atomic_state *state,
109 bool nonblock);
110
111static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
112
113static int amdgpu_dm_atomic_check(struct drm_device *dev,
114 struct drm_atomic_state *state);
115
116
117
e7b07cee 118
e04a6123 119static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125 DRM_PLANE_TYPE_PRIMARY,
126};
127
e04a6123 128static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_PRIMARY,
132 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
133};
134
e04a6123 135static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_PRIMARY,
138 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
139};
140
4562236b
HW		 141/*
142 * dm_vblank_get_counter
143 *
144 * @brief
145 * Get counter for number of vertical blanks
146 *
147 * @param
148 * struct amdgpu_device *adev - [in] desired amdgpu device
149 * int disp_idx - [in] which CRTC to get the counter from
150 *
151 * @return
152 * Counter for vertical blanks
153 */
154static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
155{
156 if (crtc >= adev->mode_info.num_crtc)
157 return 0;
158 else {
159 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 160 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
161 acrtc->base.state);
4562236b 162
da5c47f6
AG		 163
164 if (acrtc_state->stream == NULL) {
0971c40e
HW		 165 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
166 crtc);
4562236b
HW		 167 return 0;
168 }
169
da5c47f6 170 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 171 }
172}
173
174static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 175 u32 *vbl, u32 *position)
4562236b 176{
81c50963
ST		 177 uint32_t v_blank_start, v_blank_end, h_position, v_position;
178
4562236b
HW		 179 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
180 return -EINVAL;
181 else {
182 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 183 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
184 acrtc->base.state);
4562236b 185
da5c47f6 186 if (acrtc_state->stream == NULL) {
0971c40e
HW		 187 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
188 crtc);
4562236b
HW		 189 return 0;
190 }
191
81c50963
ST		 192 /*
193 * TODO rework base driver to use values directly.
194 * for now parse it back into reg-format
195 */
da5c47f6 196 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 197 &v_blank_start,
198 &v_blank_end,
199 &h_position,
200 &v_position);
201
e806208d
AG		 202 *position = v_position | (h_position << 16);
203 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 204 }
205
206 return 0;
207}
208
209static bool dm_is_idle(void *handle)
210{
211 /* XXX todo */
212 return true;
213}
214
215static int dm_wait_for_idle(void *handle)
216{
217 /* XXX todo */
218 return 0;
219}
220
221static bool dm_check_soft_reset(void *handle)
222{
223 return false;
224}
225
226static int dm_soft_reset(void *handle)
227{
228 /* XXX todo */
229 return 0;
230}
231
3ee6b26b
AD		 232static struct amdgpu_crtc *
233get_crtc_by_otg_inst(struct amdgpu_device *adev,
234 int otg_inst)
4562236b
HW		 235{
236 struct drm_device *dev = adev->ddev;
237 struct drm_crtc *crtc;
238 struct amdgpu_crtc *amdgpu_crtc;
239
240 /*
241 * following if is check inherited from both functions where this one is
242 * used now. Need to be checked why it could happen.
243 */
244 if (otg_inst == -1) {
245 WARN_ON(1);
246 return adev->mode_info.crtcs[0];
247 }
248
249 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
250 amdgpu_crtc = to_amdgpu_crtc(crtc);
251
252 if (amdgpu_crtc->otg_inst == otg_inst)
253 return amdgpu_crtc;
254 }
255
256 return NULL;
257}
258
259static void dm_pflip_high_irq(void *interrupt_params)
260{
4562236b
HW		 261 struct amdgpu_crtc *amdgpu_crtc;
262 struct common_irq_params *irq_params = interrupt_params;
263 struct amdgpu_device *adev = irq_params->adev;
264 unsigned long flags;
265
266 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
267
268 /* IRQ could occur when in initial stage */
269 /*TODO work and BO cleanup */
270 if (amdgpu_crtc == NULL) {
271 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
272 return;
273 }
274
275 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 276
277 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
278 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
279 amdgpu_crtc->pflip_status,
280 AMDGPU_FLIP_SUBMITTED,
281 amdgpu_crtc->crtc_id,
282 amdgpu_crtc);
283 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
284 return;
285 }
286
4562236b
HW		 287
288 /* wakeup usersapce */
1159898a 289 if (amdgpu_crtc->event) {
753c66c9
MK		 290 /* Update to correct count/ts if racing with vblank irq */
291 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
292
54f5499a 293 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 294
54f5499a
AG		 295 /* page flip completed. clean up */
296 amdgpu_crtc->event = NULL;
1159898a 297
54f5499a
AG		 298 } else
299 WARN_ON(1);
4562236b 300
54f5499a 301 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 302 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
303
54f5499a
AG		 304 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
305 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 306
307 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 308}
309
310static void dm_crtc_high_irq(void *interrupt_params)
311{
312 struct common_irq_params *irq_params = interrupt_params;
313 struct amdgpu_device *adev = irq_params->adev;
314 uint8_t crtc_index = 0;
315 struct amdgpu_crtc *acrtc;
316
b57de80a 317 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 318
319 if (acrtc)
320 crtc_index = acrtc->crtc_id;
321
322 drm_handle_vblank(adev->ddev, crtc_index);
31aec354 323 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
4562236b
HW		 324}
325
326static int dm_set_clockgating_state(void *handle,
327 enum amd_clockgating_state state)
328{
329 return 0;
330}
331
332static int dm_set_powergating_state(void *handle,
333 enum amd_powergating_state state)
334{
335 return 0;
336}
337
338/* Prototypes of private functions */
339static int dm_early_init(void* handle);
340
341static void hotplug_notify_work_func(struct work_struct *work)
342{
343 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
344 struct drm_device *dev = dm->ddev;
345
346 drm_kms_helper_hotplug_event(dev);
347}
348
6ef39a62 349#if defined(CONFIG_DRM_AMD_DC_FBC)
a32e24b4 350/* Allocate memory for FBC compressed data */
3e332d3a 351static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 352{
3e332d3a
RL		 353 struct drm_device *dev = connector->dev;
354 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 355 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 356 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
357 struct drm_display_mode *mode;
42e67c3b
RL		 358 unsigned long max_size = 0;
359
360 if (adev->dm.dc->fbc_compressor == NULL)
361 return;
a32e24b4 362
3e332d3a 363 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 364 return;
365
3e332d3a
RL		 366 if (compressor->bo_ptr)
367 return;
42e67c3b 368
42e67c3b 369
3e332d3a
RL		 370 list_for_each_entry(mode, &connector->modes, head) {
371 if (max_size < mode->htotal * mode->vtotal)
372 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 373 }
374
375 if (max_size) {
376 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 377 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 378 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 379
380 if (r)
42e67c3b
RL		 381 DRM_ERROR("DM: Failed to initialize FBC\n");
382 else {
383 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
384 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
385 }
386
a32e24b4
RL		 387 }
388
389}
390#endif
391
392
4562236b
HW		 393/* Init display KMS
394 *
395 * Returns 0 on success
396 */
7578ecda 397static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 398{
399 struct dc_init_data init_data;
400 adev->dm.ddev = adev->ddev;
401 adev->dm.adev = adev;
402
4562236b
HW		 403 /* Zero all the fields */
404 memset(&init_data, 0, sizeof(init_data));
405
4562236b
HW		 406 if(amdgpu_dm_irq_init(adev)) {
407 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
408 goto error;
409 }
410
411 init_data.asic_id.chip_family = adev->family;
412
413 init_data.asic_id.pci_revision_id = adev->rev_id;
414 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
415
770d13b1 416 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 417 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
418 init_data.asic_id.atombios_base_address =
419 adev->mode_info.atom_context->bios;
420
421 init_data.driver = adev;
422
423 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
424
425 if (!adev->dm.cgs_device) {
426 DRM_ERROR("amdgpu: failed to create cgs device.\n");
427 goto error;
428 }
429
430 init_data.cgs_device = adev->dm.cgs_device;
431
432 adev->dm.dal = NULL;
433
434 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
435
f1ad2f5e
HW		 436 if (amdgpu_dc_log)
437 init_data.log_mask = DC_DEFAULT_LOG_MASK;
438 else
439 init_data.log_mask = DC_MIN_LOG_MASK;
01a526f3 440
6e227308
HW		 441 /*
442 * TODO debug why this doesn't work on Raven
443 */
444 if (adev->flags & AMD_IS_APU &&
445 adev->asic_type >= CHIP_CARRIZO &&
446 adev->asic_type < CHIP_RAVEN)
447 init_data.flags.gpu_vm_support = true;
448
4562236b
HW		 449 /* Display Core create. */
450 adev->dm.dc = dc_create(&init_data);
451
423788c7 452 if (adev->dm.dc) {
76121231 453 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 454 } else {
76121231 455 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 456 goto error;
457 }
4562236b
HW		 458
459 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
460
461 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
462 if (!adev->dm.freesync_module) {
463 DRM_ERROR(
464 "amdgpu: failed to initialize freesync_module.\n");
465 } else
f1ad2f5e 466 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 467 adev->dm.freesync_module);
468
e277adc5
LSL		 469 amdgpu_dm_init_color_mod();
470
4562236b
HW		 471 if (amdgpu_dm_initialize_drm_device(adev)) {
472 DRM_ERROR(
473 "amdgpu: failed to initialize sw for display support.\n");
474 goto error;
475 }
476
477 /* Update the actual used number of crtc */
478 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
479
480 /* TODO: Add_display_info? */
481
482 /* TODO use dynamic cursor width */
ce75805e
AG		 483 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
484 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 485
486 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
487 DRM_ERROR(
488 "amdgpu: failed to initialize sw for display support.\n");
489 goto error;
490 }
491
f1ad2f5e 492 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 493
494 return 0;
495error:
496 amdgpu_dm_fini(adev);
497
498 return -1;
499}
500
7578ecda 501static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 502{
503 amdgpu_dm_destroy_drm_device(&adev->dm);
504 /*
505 * TODO: pageflip, vlank interrupt
506 *
507 * amdgpu_dm_irq_fini(adev);
508 */
509
510 if (adev->dm.cgs_device) {
511 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
512 adev->dm.cgs_device = NULL;
513 }
514 if (adev->dm.freesync_module) {
515 mod_freesync_destroy(adev->dm.freesync_module);
516 adev->dm.freesync_module = NULL;
517 }
518 /* DC Destroy TODO: Replace destroy DAL */
21de3396 519 if (adev->dm.dc)
4562236b 520 dc_destroy(&adev->dm.dc);
4562236b
HW		 521 return;
522}
523
4562236b
HW		 524static int dm_sw_init(void *handle)
525{
526 return 0;
527}
528
529static int dm_sw_fini(void *handle)
530{
531 return 0;
532}
533
7abcf6b5 534static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 535{
c84dec2f 536 struct amdgpu_dm_connector *aconnector;
4562236b 537 struct drm_connector *connector;
7abcf6b5 538 int ret = 0;
4562236b
HW		 539
540 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
541
542 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 543 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 544 if (aconnector->dc_link->type == dc_connection_mst_branch &&
545 aconnector->mst_mgr.aux) {
f1ad2f5e 546 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 547 aconnector, aconnector->base.base.id);
548
549 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
550 if (ret < 0) {
551 DRM_ERROR("DM_MST: Failed to start MST\n");
552 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
553 return ret;
4562236b 554 }
7abcf6b5 555 }
4562236b
HW		 556 }
557
558 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 559 return ret;
560}
561
562static int dm_late_init(void *handle)
563{
42e67c3b 564 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 565
42e67c3b 566 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 567}
568
569static void s3_handle_mst(struct drm_device *dev, bool suspend)
570{
c84dec2f 571 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 572 struct drm_connector *connector;
573
574 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
575
576 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 577 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 578 if (aconnector->dc_link->type == dc_connection_mst_branch &&
579 !aconnector->mst_port) {
580
581 if (suspend)
582 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
583 else
584 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
585 }
586 }
587
588 drm_modeset_unlock(&dev->mode_config.connection_mutex);
589}
590
591static int dm_hw_init(void *handle)
592{
593 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
594 /* Create DAL display manager */
595 amdgpu_dm_init(adev);
4562236b
HW		 596 amdgpu_dm_hpd_init(adev);
597
4562236b
HW		 598 return 0;
599}
600
601static int dm_hw_fini(void *handle)
602{
603 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
604
605 amdgpu_dm_hpd_fini(adev);
606
607 amdgpu_dm_irq_fini(adev);
21de3396 608 amdgpu_dm_fini(adev);
4562236b
HW		 609 return 0;
610}
611
612static int dm_suspend(void *handle)
613{
614 struct amdgpu_device *adev = handle;
615 struct amdgpu_display_manager *dm = &adev->dm;
616 int ret = 0;
4562236b
HW		 617
618 s3_handle_mst(adev->ddev, true);
619
4562236b
HW		 620 amdgpu_dm_irq_suspend(adev);
621
0a214e2f 622 WARN_ON(adev->dm.cached_state);
a3621485
AG		 623 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
624
32f5062d 625 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 626
627 return ret;
628}
629
1daf8c63
AD		 630static struct amdgpu_dm_connector *
631amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
632 struct drm_crtc *crtc)
4562236b
HW		 633{
634 uint32_t i;
c2cea706 635 struct drm_connector_state *new_con_state;
4562236b
HW		 636 struct drm_connector *connector;
637 struct drm_crtc *crtc_from_state;
638
c2cea706
LSL		 639 for_each_new_connector_in_state(state, connector, new_con_state, i) {
640 crtc_from_state = new_con_state->crtc;
4562236b
HW		 641
642 if (crtc_from_state == crtc)
c84dec2f 643 return to_amdgpu_dm_connector(connector);
4562236b
HW		 644 }
645
646 return NULL;
647}
648
4562236b
HW		 649static int dm_resume(void *handle)
650{
651 struct amdgpu_device *adev = handle;
652 struct amdgpu_display_manager *dm = &adev->dm;
15b9bc9a 653 int ret = 0;
4562236b
HW		 654
655 /* power on hardware */
1fb0c9cc 656 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
4562236b 657
15b9bc9a
ML		 658 ret = amdgpu_dm_display_resume(adev);
659 return ret;
4562236b
HW		 660}
661
1ecfc3da 662int amdgpu_dm_display_resume(struct amdgpu_device *adev)
4562236b
HW		 663{
664 struct drm_device *ddev = adev->ddev;
665 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 666 struct amdgpu_dm_connector *aconnector;
4562236b 667 struct drm_connector *connector;
4562236b 668 struct drm_crtc *crtc;
c2cea706 669 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 670 struct dm_crtc_state *dm_new_crtc_state;
671 struct drm_plane *plane;
672 struct drm_plane_state *new_plane_state;
673 struct dm_plane_state *dm_new_plane_state;
674
a3621485
AG		 675 int ret = 0;
676 int i;
4562236b
HW		 677
678 /* program HPD filter */
679 dc_resume(dm->dc);
680
681 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
682 s3_handle_mst(ddev, false);
683
684 /*
685 * early enable HPD Rx IRQ, should be done before set mode as short
686 * pulse interrupts are used for MST
687 */
688 amdgpu_dm_irq_resume_early(adev);
689
4562236b
HW		 690 /* Do detection*/
691 list_for_each_entry(connector,
692 &ddev->mode_config.connector_list, head) {
c84dec2f 693 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 694
695 /*
696 * this is the case when traversing through already created
697 * MST connectors, should be skipped
698 */
699 if (aconnector->mst_port)
700 continue;
701
03ea364c 702 mutex_lock(&aconnector->hpd_lock);
8f38b66c 703 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 704
705 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
706 aconnector->fake_enable = false;
707
4562236b
HW		 708 aconnector->dc_sink = NULL;
709 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 710 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 711 }
712
a3621485 713 /* Force mode set in atomic comit */
c2cea706
LSL		 714 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
715 new_crtc_state->active_changed = true;
4f346e65 716
fcb4019e
LSL		 717 /*
718 * atomic_check is expected to create the dc states. We need to release
719 * them here, since they were duplicated as part of the suspend
720 * procedure.
721 */
722 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
723 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
724 if (dm_new_crtc_state->stream) {
725 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
726 dc_stream_release(dm_new_crtc_state->stream);
727 dm_new_crtc_state->stream = NULL;
728 }
729 }
730
731 for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
732 dm_new_plane_state = to_dm_plane_state(new_plane_state);
733 if (dm_new_plane_state->dc_state) {
734 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
735 dc_plane_state_release(dm_new_plane_state->dc_state);
736 dm_new_plane_state->dc_state = NULL;
737 }
738 }
739
a3621485 740 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 741
0a214e2f
AG		 742 adev->dm.cached_state = NULL;
743
9faa4237 744 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 745
746 return ret;
747}
748
749static const struct amd_ip_funcs amdgpu_dm_funcs = {
750 .name = "dm",
751 .early_init = dm_early_init,
7abcf6b5 752 .late_init = dm_late_init,
4562236b
HW		 753 .sw_init = dm_sw_init,
754 .sw_fini = dm_sw_fini,
755 .hw_init = dm_hw_init,
756 .hw_fini = dm_hw_fini,
757 .suspend = dm_suspend,
758 .resume = dm_resume,
759 .is_idle = dm_is_idle,
760 .wait_for_idle = dm_wait_for_idle,
761 .check_soft_reset = dm_check_soft_reset,
762 .soft_reset = dm_soft_reset,
763 .set_clockgating_state = dm_set_clockgating_state,
764 .set_powergating_state = dm_set_powergating_state,
765};
766
767const struct amdgpu_ip_block_version dm_ip_block =
768{
769 .type = AMD_IP_BLOCK_TYPE_DCE,
770 .major = 1,
771 .minor = 0,
772 .rev = 0,
773 .funcs = &amdgpu_dm_funcs,
774};
775
ca3268c4 776
7578ecda 777static struct drm_atomic_state *
ca3268c4
HW		 778dm_atomic_state_alloc(struct drm_device *dev)
779{
780 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
781
1dc90497 782 if (!state)
ca3268c4 783 return NULL;
1dc90497
AG		 784
785 if (drm_atomic_state_init(dev, &state->base) < 0)
786 goto fail;
787
ca3268c4 788 return &state->base;
1dc90497
AG		 789
790fail:
791 kfree(state);
792 return NULL;
ca3268c4
HW		 793}
794
0a323b84
AG		 795static void
796dm_atomic_state_clear(struct drm_atomic_state *state)
797{
798 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
799
800 if (dm_state->context) {
608ac7bb 801 dc_release_state(dm_state->context);
0a323b84
AG		 802 dm_state->context = NULL;
803 }
804
805 drm_atomic_state_default_clear(state);
806}
807
808static void
809dm_atomic_state_alloc_free(struct drm_atomic_state *state)
810{
811 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
812 drm_atomic_state_default_release(state);
813 kfree(dm_state);
814}
815
b3663f70 816static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 817 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 818 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 819 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 820 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 821 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 822 .atomic_state_clear = dm_atomic_state_clear,
823 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 824};
825
826static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
827 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 828};
829
7578ecda 830static void
3ee6b26b 831amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 832{
833 struct drm_connector *connector = &aconnector->base;
834 struct drm_device *dev = connector->dev;
b73a22d3 835 struct dc_sink *sink;
4562236b
HW		 836
837 /* MST handled by drm_mst framework */
838 if (aconnector->mst_mgr.mst_state == true)
839 return;
840
841
842 sink = aconnector->dc_link->local_sink;
843
844 /* Edid mgmt connector gets first update only in mode_valid hook and then
845 * the connector sink is set to either fake or physical sink depends on link status.
846 * don't do it here if u are during boot
847 */
848 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
849 && aconnector->dc_em_sink) {
850
ab2541b6 851 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 852 * because on resume connecotr->sink is set ti NULL
853 */
854 mutex_lock(&dev->mode_config.mutex);
855
856 if (sink) {
922aa1e1 857 if (aconnector->dc_sink) {
4562236b
HW		 858 amdgpu_dm_remove_sink_from_freesync_module(
859 connector);
922aa1e1
AG		 860 /* retain and release bellow are used for
861 * bump up refcount for sink because the link don't point
862 * to it anymore after disconnect so on next crtc to connector
863 * reshuffle by UMD we will get into unwanted dc_sink release
864 */
865 if (aconnector->dc_sink != aconnector->dc_em_sink)
866 dc_sink_release(aconnector->dc_sink);
867 }
4562236b
HW		 868 aconnector->dc_sink = sink;
869 amdgpu_dm_add_sink_to_freesync_module(
870 connector, aconnector->edid);
871 } else {
872 amdgpu_dm_remove_sink_from_freesync_module(connector);
873 if (!aconnector->dc_sink)
874 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 875 else if (aconnector->dc_sink != aconnector->dc_em_sink)
876 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 877 }
878
879 mutex_unlock(&dev->mode_config.mutex);
880 return;
881 }
882
883 /*
884 * TODO: temporary guard to look for proper fix
885 * if this sink is MST sink, we should not do anything
886 */
887 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
888 return;
889
890 if (aconnector->dc_sink == sink) {
891 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
892 * Do nothing!! */
f1ad2f5e 893 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 894 aconnector->connector_id);
895 return;
896 }
897
f1ad2f5e 898 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 899 aconnector->connector_id, aconnector->dc_sink, sink);
900
901 mutex_lock(&dev->mode_config.mutex);
902
903 /* 1. Update status of the drm connector
904 * 2. Send an event and let userspace tell us what to do */
905 if (sink) {
906 /* TODO: check if we still need the S3 mode update workaround.
907 * If yes, put it here. */
908 if (aconnector->dc_sink)
909 amdgpu_dm_remove_sink_from_freesync_module(
910 connector);
911
912 aconnector->dc_sink = sink;
900b3cb1 913 if (sink->dc_edid.length == 0) {
4562236b 914 aconnector->edid = NULL;
900b3cb1 915 } else {
4562236b
HW		 916 aconnector->edid =
917 (struct edid *) sink->dc_edid.raw_edid;
918
919
920 drm_mode_connector_update_edid_property(connector,
921 aconnector->edid);
922 }
923 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
924
925 } else {
926 amdgpu_dm_remove_sink_from_freesync_module(connector);
927 drm_mode_connector_update_edid_property(connector, NULL);
928 aconnector->num_modes = 0;
929 aconnector->dc_sink = NULL;
930 }
931
932 mutex_unlock(&dev->mode_config.mutex);
933}
934
935static void handle_hpd_irq(void *param)
936{
c84dec2f 937 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 938 struct drm_connector *connector = &aconnector->base;
939 struct drm_device *dev = connector->dev;
940
941 /* In case of failure or MST no need to update connector status or notify the OS
942 * since (for MST case) MST does this in it's own context.
943 */
944 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 945
946 if (aconnector->fake_enable)
947 aconnector->fake_enable = false;
948
8f38b66c 949 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 950 amdgpu_dm_update_connector_after_detect(aconnector);
951
952
953 drm_modeset_lock_all(dev);
954 dm_restore_drm_connector_state(dev, connector);
955 drm_modeset_unlock_all(dev);
956
957 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
958 drm_kms_helper_hotplug_event(dev);
959 }
960 mutex_unlock(&aconnector->hpd_lock);
961
962}
963
c84dec2f 964static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 965{
966 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
967 uint8_t dret;
968 bool new_irq_handled = false;
969 int dpcd_addr;
970 int dpcd_bytes_to_read;
971
972 const int max_process_count = 30;
973 int process_count = 0;
974
975 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
976
977 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
978 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
979 /* DPCD 0x200 - 0x201 for downstream IRQ */
980 dpcd_addr = DP_SINK_COUNT;
981 } else {
982 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
983 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
984 dpcd_addr = DP_SINK_COUNT_ESI;
985 }
986
987 dret = drm_dp_dpcd_read(
988 &aconnector->dm_dp_aux.aux,
989 dpcd_addr,
990 esi,
991 dpcd_bytes_to_read);
992
993 while (dret == dpcd_bytes_to_read &&
994 process_count < max_process_count) {
995 uint8_t retry;
996 dret = 0;
997
998 process_count++;
999
f1ad2f5e 1000 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1001 /* handle HPD short pulse irq */
1002 if (aconnector->mst_mgr.mst_state)
1003 drm_dp_mst_hpd_irq(
1004 &aconnector->mst_mgr,
1005 esi,
1006 &new_irq_handled);
4562236b
HW		 1007
1008 if (new_irq_handled) {
1009 /* ACK at DPCD to notify down stream */
1010 const int ack_dpcd_bytes_to_write =
1011 dpcd_bytes_to_read - 1;
1012
1013 for (retry = 0; retry < 3; retry++) {
1014 uint8_t wret;
1015
1016 wret = drm_dp_dpcd_write(
1017 &aconnector->dm_dp_aux.aux,
1018 dpcd_addr + 1,
1019 &esi[1],
1020 ack_dpcd_bytes_to_write);
1021 if (wret == ack_dpcd_bytes_to_write)
1022 break;
1023 }
1024
1025 /* check if there is new irq to be handle */
1026 dret = drm_dp_dpcd_read(
1027 &aconnector->dm_dp_aux.aux,
1028 dpcd_addr,
1029 esi,
1030 dpcd_bytes_to_read);
1031
1032 new_irq_handled = false;
d4a6e8a9 1033 } else {
4562236b 1034 break;
d4a6e8a9 1035 }
4562236b
HW		 1036 }
1037
1038 if (process_count == max_process_count)
f1ad2f5e 1039 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1040}
1041
1042static void handle_hpd_rx_irq(void *param)
1043{
c84dec2f 1044 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1045 struct drm_connector *connector = &aconnector->base;
1046 struct drm_device *dev = connector->dev;
53cbf65c 1047 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 1048 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1049
1050 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1051 * conflict, after implement i2c helper, this mutex should be
1052 * retired.
1053 */
53cbf65c 1054 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1055 mutex_lock(&aconnector->hpd_lock);
1056
53cbf65c 1057 if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
4562236b
HW		 1058 !is_mst_root_connector) {
1059 /* Downstream Port status changed. */
53cbf65c 1060 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1061
1062 if (aconnector->fake_enable)
1063 aconnector->fake_enable = false;
1064
4562236b
HW		 1065 amdgpu_dm_update_connector_after_detect(aconnector);
1066
1067
1068 drm_modeset_lock_all(dev);
1069 dm_restore_drm_connector_state(dev, connector);
1070 drm_modeset_unlock_all(dev);
1071
1072 drm_kms_helper_hotplug_event(dev);
1073 }
1074 }
1075 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1076 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1077 dm_handle_hpd_rx_irq(aconnector);
1078
53cbf65c 1079 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1080 mutex_unlock(&aconnector->hpd_lock);
1081}
1082
1083static void register_hpd_handlers(struct amdgpu_device *adev)
1084{
1085 struct drm_device *dev = adev->ddev;
1086 struct drm_connector *connector;
c84dec2f 1087 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1088 const struct dc_link *dc_link;
1089 struct dc_interrupt_params int_params = {0};
1090
1091 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1092 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1093
1094 list_for_each_entry(connector,
1095 &dev->mode_config.connector_list, head) {
1096
c84dec2f 1097 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1098 dc_link = aconnector->dc_link;
1099
1100 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1101 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1102 int_params.irq_source = dc_link->irq_source_hpd;
1103
1104 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1105 handle_hpd_irq,
1106 (void *) aconnector);
1107 }
1108
1109 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1110
1111 /* Also register for DP short pulse (hpd_rx). */
1112 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1113 int_params.irq_source = dc_link->irq_source_hpd_rx;
1114
1115 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1116 handle_hpd_rx_irq,
1117 (void *) aconnector);
1118 }
1119 }
1120}
1121
1122/* Register IRQ sources and initialize IRQ callbacks */
1123static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1124{
1125 struct dc *dc = adev->dm.dc;
1126 struct common_irq_params *c_irq_params;
1127 struct dc_interrupt_params int_params = {0};
1128 int r;
1129 int i;
2c8ad2d5
AD		 1130 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1131
ff5ef992 1132 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1133 adev->asic_type == CHIP_VEGA12 ||
ff5ef992 1134 adev->asic_type == CHIP_RAVEN)
3760f76c 1135 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1136
1137 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1138 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1139
1140 /* Actions of amdgpu_irq_add_id():
1141 * 1. Register a set() function with base driver.
1142 * Base driver will call set() function to enable/disable an
1143 * interrupt in DC hardware.
1144 * 2. Register amdgpu_dm_irq_handler().
1145 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1146 * coming from DC hardware.
1147 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1148 * for acknowledging and handling. */
1149
b57de80a 1150 /* Use VBLANK interrupt */
e9029155 1151 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1152 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1153 if (r) {
1154 DRM_ERROR("Failed to add crtc irq id!\n");
1155 return r;
1156 }
1157
1158 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1159 int_params.irq_source =
3d761e79 1160 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1161
b57de80a 1162 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1163
1164 c_irq_params->adev = adev;
1165 c_irq_params->irq_src = int_params.irq_source;
1166
1167 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1168 dm_crtc_high_irq, c_irq_params);
1169 }
1170
3d761e79 1171 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1172 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1173 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1174 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1175 if (r) {
1176 DRM_ERROR("Failed to add page flip irq id!\n");
1177 return r;
1178 }
1179
1180 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1181 int_params.irq_source =
1182 dc_interrupt_to_irq_source(dc, i, 0);
1183
1184 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1185
1186 c_irq_params->adev = adev;
1187 c_irq_params->irq_src = int_params.irq_source;
1188
1189 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1190 dm_pflip_high_irq, c_irq_params);
1191
1192 }
1193
1194 /* HPD */
2c8ad2d5
AD		 1195 r = amdgpu_irq_add_id(adev, client_id,
1196 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1197 if (r) {
1198 DRM_ERROR("Failed to add hpd irq id!\n");
1199 return r;
1200 }
1201
1202 register_hpd_handlers(adev);
1203
1204 return 0;
1205}
1206
ff5ef992
AD		 1207#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1208/* Register IRQ sources and initialize IRQ callbacks */
1209static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1210{
1211 struct dc *dc = adev->dm.dc;
1212 struct common_irq_params *c_irq_params;
1213 struct dc_interrupt_params int_params = {0};
1214 int r;
1215 int i;
1216
1217 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1218 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1219
1220 /* Actions of amdgpu_irq_add_id():
1221 * 1. Register a set() function with base driver.
1222 * Base driver will call set() function to enable/disable an
1223 * interrupt in DC hardware.
1224 * 2. Register amdgpu_dm_irq_handler().
1225 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1226 * coming from DC hardware.
1227 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1228 * for acknowledging and handling.
1229 * */
1230
1231 /* Use VSTARTUP interrupt */
1232 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1233 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1234 i++) {
3760f76c 1235 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1236
1237 if (r) {
1238 DRM_ERROR("Failed to add crtc irq id!\n");
1239 return r;
1240 }
1241
1242 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1243 int_params.irq_source =
1244 dc_interrupt_to_irq_source(dc, i, 0);
1245
1246 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1247
1248 c_irq_params->adev = adev;
1249 c_irq_params->irq_src = int_params.irq_source;
1250
1251 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1252 dm_crtc_high_irq, c_irq_params);
1253 }
1254
1255 /* Use GRPH_PFLIP interrupt */
1256 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1257 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1258 i++) {
3760f76c 1259 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1260 if (r) {
1261 DRM_ERROR("Failed to add page flip irq id!\n");
1262 return r;
1263 }
1264
1265 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1266 int_params.irq_source =
1267 dc_interrupt_to_irq_source(dc, i, 0);
1268
1269 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1270
1271 c_irq_params->adev = adev;
1272 c_irq_params->irq_src = int_params.irq_source;
1273
1274 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1275 dm_pflip_high_irq, c_irq_params);
1276
1277 }
1278
1279 /* HPD */
3760f76c 1280 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1281 &adev->hpd_irq);
1282 if (r) {
1283 DRM_ERROR("Failed to add hpd irq id!\n");
1284 return r;
1285 }
1286
1287 register_hpd_handlers(adev);
1288
1289 return 0;
1290}
1291#endif
1292
4562236b
HW		 1293static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1294{
1295 int r;
1296
1297 adev->mode_info.mode_config_initialized = true;
1298
4562236b 1299 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1300 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1301
1302 adev->ddev->mode_config.max_width = 16384;
1303 adev->ddev->mode_config.max_height = 16384;
1304
1305 adev->ddev->mode_config.preferred_depth = 24;
1306 adev->ddev->mode_config.prefer_shadow = 1;
1307 /* indicate support of immediate flip */
1308 adev->ddev->mode_config.async_page_flip = true;
1309
770d13b1 1310 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1311
3dc9b1ce 1312 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1313 if (r)
1314 return r;
1315
1316 return 0;
1317}
1318
1319#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1320 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1321
1322static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1323{
1324 struct amdgpu_display_manager *dm = bl_get_data(bd);
1325
1326 if (dc_link_set_backlight_level(dm->backlight_link,
1327 bd->props.brightness, 0, 0))
1328 return 0;
1329 else
1330 return 1;
1331}
1332
1333static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1334{
1335 return bd->props.brightness;
1336}
1337
1338static const struct backlight_ops amdgpu_dm_backlight_ops = {
1339 .get_brightness = amdgpu_dm_backlight_get_brightness,
1340 .update_status = amdgpu_dm_backlight_update_status,
1341};
1342
7578ecda
AD		 1343static void
1344amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1345{
1346 char bl_name[16];
1347 struct backlight_properties props = { 0 };
1348
1349 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1350 props.type = BACKLIGHT_RAW;
1351
1352 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1353 dm->adev->ddev->primary->index);
1354
1355 dm->backlight_dev = backlight_device_register(bl_name,
1356 dm->adev->ddev->dev,
1357 dm,
1358 &amdgpu_dm_backlight_ops,
1359 &props);
1360
74baea42 1361 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1362 DRM_ERROR("DM: Backlight registration failed!\n");
1363 else
f1ad2f5e 1364 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1365}
1366
1367#endif
1368
df534fff
S		 1369static int initialize_plane(struct amdgpu_display_manager *dm,
1370 struct amdgpu_mode_info *mode_info,
1371 int plane_id)
1372{
1373 struct amdgpu_plane *plane;
1374 unsigned long possible_crtcs;
1375 int ret = 0;
1376
1377 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1378 mode_info->planes[plane_id] = plane;
1379
1380 if (!plane) {
1381 DRM_ERROR("KMS: Failed to allocate plane\n");
1382 return -ENOMEM;
1383 }
1384 plane->base.type = mode_info->plane_type[plane_id];
1385
1386 /*
1387 * HACK: IGT tests expect that each plane can only have one
1388 * one possible CRTC. For now, set one CRTC for each
1389 * plane that is not an underlay, but still allow multiple
1390 * CRTCs for underlay planes.
1391 */
1392 possible_crtcs = 1 << plane_id;
1393 if (plane_id >= dm->dc->caps.max_streams)
1394 possible_crtcs = 0xff;
1395
1396 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1397
1398 if (ret) {
1399 DRM_ERROR("KMS: Failed to initialize plane\n");
1400 return ret;
1401 }
1402
1403 return ret;
1404}
1405
4562236b
HW		 1406/* In this architecture, the association
1407 * connector -> encoder -> crtc
1408 * id not really requried. The crtc and connector will hold the
1409 * display_index as an abstraction to use with DAL component
1410 *
1411 * Returns 0 on success
1412 */
7578ecda 1413static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1414{
1415 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 1416 int32_t i;
c84dec2f 1417 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1418 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1419 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1420 uint32_t link_cnt;
df534fff 1421 int32_t total_overlay_planes, total_primary_planes;
4562236b
HW		 1422
1423 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1424 if (amdgpu_dm_mode_config_init(dm->adev)) {
1425 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1426 return -1;
4562236b
HW		 1427 }
1428
df534fff
S		 1429 /* Identify the number of planes to be initialized */
1430 total_overlay_planes = dm->dc->caps.max_slave_planes;
1431 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
efa6a8b7 1432
df534fff
S		 1433 /* First initialize overlay planes, index starting after primary planes */
1434 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1435 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1436 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 1437 goto fail;
d4e13b0d 1438 }
df534fff 1439 }
92f3ac40 1440
df534fff
S		 1441 /* Initialize primary planes */
1442 for (i = (total_primary_planes - 1); i >= 0; i--) {
1443 if (initialize_plane(dm, mode_info, i)) {
1444 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 1445 goto fail;
d4e13b0d
AD		 1446 }
1447 }
4562236b 1448
d4e13b0d
AD		 1449 for (i = 0; i < dm->dc->caps.max_streams; i++)
1450 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1451 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1452 goto fail;
4562236b 1453 }
4562236b 1454
ab2541b6 1455 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1456
1457 /* loops over all connectors on the board */
1458 for (i = 0; i < link_cnt; i++) {
1459
1460 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1461 DRM_ERROR(
1462 "KMS: Cannot support more than %d display indexes\n",
1463 AMDGPU_DM_MAX_DISPLAY_INDEX);
1464 continue;
1465 }
1466
1467 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1468 if (!aconnector)
cd8a2ae8 1469 goto fail;
4562236b
HW		 1470
1471 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1472 if (!aencoder)
cd8a2ae8 1473 goto fail;
4562236b
HW		 1474
1475 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1476 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1477 goto fail;
4562236b
HW		 1478 }
1479
1480 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1481 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1482 goto fail;
4562236b
HW		 1483 }
1484
8f38b66c
HW		 1485 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1486 DETECT_REASON_BOOT))
4562236b
HW		 1487 amdgpu_dm_update_connector_after_detect(aconnector);
1488 }
1489
1490 /* Software is initialized. Now we can register interrupt handlers. */
1491 switch (adev->asic_type) {
1492 case CHIP_BONAIRE:
1493 case CHIP_HAWAII:
cd4b356f
AD		 1494 case CHIP_KAVERI:
1495 case CHIP_KABINI:
1496 case CHIP_MULLINS:
4562236b
HW		 1497 case CHIP_TONGA:
1498 case CHIP_FIJI:
1499 case CHIP_CARRIZO:
1500 case CHIP_STONEY:
1501 case CHIP_POLARIS11:
1502 case CHIP_POLARIS10:
b264d345 1503 case CHIP_POLARIS12:
2c8ad2d5 1504 case CHIP_VEGA10:
2325ff30 1505 case CHIP_VEGA12:
4562236b
HW		 1506 if (dce110_register_irq_handlers(dm->adev)) {
1507 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1508 goto fail;
4562236b
HW		 1509 }
1510 break;
ff5ef992
AD		 1511#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1512 case CHIP_RAVEN:
1513 if (dcn10_register_irq_handlers(dm->adev)) {
1514 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1515 goto fail;
ff5ef992 1516 }
79c24086
BL		 1517 /*
1518 * Temporary disable until pplib/smu interaction is implemented
1519 */
1520 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1521 break;
1522#endif
4562236b
HW		 1523 default:
1524 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 1525 goto fail;
4562236b
HW		 1526 }
1527
4562236b 1528 return 0;
cd8a2ae8 1529fail:
4562236b 1530 kfree(aencoder);
4562236b 1531 kfree(aconnector);
3be5262e 1532 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1533 kfree(mode_info->planes[i]);
4562236b
HW		 1534 return -1;
1535}
1536
7578ecda 1537static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1538{
1539 drm_mode_config_cleanup(dm->ddev);
1540 return;
1541}
1542
1543/******************************************************************************
1544 * amdgpu_display_funcs functions
1545 *****************************************************************************/
1546
1547/**
1548 * dm_bandwidth_update - program display watermarks
1549 *
1550 * @adev: amdgpu_device pointer
1551 *
1552 * Calculate and program the display watermarks and line buffer allocation.
1553 */
1554static void dm_bandwidth_update(struct amdgpu_device *adev)
1555{
49c07a99 1556 /* TODO: implement later */
4562236b
HW		 1557}
1558
1559static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1560 u8 level)
1561{
1562 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1563}
1564
1565static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1566{
1567 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1568 return 0;
1569}
1570
4562236b
HW		 1571static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1572 struct drm_file *filp)
1573{
1574 struct mod_freesync_params freesync_params;
ab2541b6 1575 uint8_t num_streams;
4562236b 1576 uint8_t i;
4562236b
HW		 1577
1578 struct amdgpu_device *adev = dev->dev_private;
1579 int r = 0;
1580
1581 /* Get freesync enable flag from DRM */
1582
ab2541b6 1583 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1584
ab2541b6 1585 for (i = 0; i < num_streams; i++) {
0971c40e 1586 struct dc_stream_state *stream;
ab2541b6 1587 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1588
1589 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1590 &stream, 1, &freesync_params);
4562236b
HW		 1591 }
1592
1593 return r;
1594}
1595
39cc5be2 1596static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1597 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1598 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4562236b
HW		 1599 .backlight_set_level =
1600 dm_set_backlight_level,/* called unconditionally */
1601 .backlight_get_level =
1602 dm_get_backlight_level,/* called unconditionally */
1603 .hpd_sense = NULL,/* called unconditionally */
1604 .hpd_set_polarity = NULL, /* called unconditionally */
1605 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1606 .page_flip_get_scanoutpos =
1607 dm_crtc_get_scanoutpos,/* called unconditionally */
1608 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1609 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1610 .notify_freesync = amdgpu_notify_freesync,
1611
1612};
1613
1614#if defined(CONFIG_DEBUG_KERNEL_DC)
1615
3ee6b26b
AD		 1616static ssize_t s3_debug_store(struct device *device,
1617 struct device_attribute *attr,
1618 const char *buf,
1619 size_t count)
4562236b
HW		 1620{
1621 int ret;
1622 int s3_state;
1623 struct pci_dev *pdev = to_pci_dev(device);
1624 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1625 struct amdgpu_device *adev = drm_dev->dev_private;
1626
1627 ret = kstrtoint(buf, 0, &s3_state);
1628
1629 if (ret == 0) {
1630 if (s3_state) {
1631 dm_resume(adev);
1632 amdgpu_dm_display_resume(adev);
1633 drm_kms_helper_hotplug_event(adev->ddev);
1634 } else
1635 dm_suspend(adev);
1636 }
1637
1638 return ret == 0 ? count : 0;
1639}
1640
1641DEVICE_ATTR_WO(s3_debug);
1642
1643#endif
1644
1645static int dm_early_init(void *handle)
1646{
1647 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1648
4562236b
HW		 1649 switch (adev->asic_type) {
1650 case CHIP_BONAIRE:
1651 case CHIP_HAWAII:
1652 adev->mode_info.num_crtc = 6;
1653 adev->mode_info.num_hpd = 6;
1654 adev->mode_info.num_dig = 6;
3be5262e 1655 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1656 break;
cd4b356f
AD		 1657 case CHIP_KAVERI:
1658 adev->mode_info.num_crtc = 4;
1659 adev->mode_info.num_hpd = 6;
1660 adev->mode_info.num_dig = 7;
1661 adev->mode_info.plane_type = dm_plane_type_default;
1662 break;
1663 case CHIP_KABINI:
1664 case CHIP_MULLINS:
1665 adev->mode_info.num_crtc = 2;
1666 adev->mode_info.num_hpd = 6;
1667 adev->mode_info.num_dig = 6;
1668 adev->mode_info.plane_type = dm_plane_type_default;
1669 break;
4562236b
HW		 1670 case CHIP_FIJI:
1671 case CHIP_TONGA:
1672 adev->mode_info.num_crtc = 6;
1673 adev->mode_info.num_hpd = 6;
1674 adev->mode_info.num_dig = 7;
3be5262e 1675 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1676 break;
1677 case CHIP_CARRIZO:
1678 adev->mode_info.num_crtc = 3;
1679 adev->mode_info.num_hpd = 6;
1680 adev->mode_info.num_dig = 9;
3be5262e 1681 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1682 break;
1683 case CHIP_STONEY:
1684 adev->mode_info.num_crtc = 2;
1685 adev->mode_info.num_hpd = 6;
1686 adev->mode_info.num_dig = 9;
3be5262e 1687 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1688 break;
1689 case CHIP_POLARIS11:
b264d345 1690 case CHIP_POLARIS12:
4562236b
HW		 1691 adev->mode_info.num_crtc = 5;
1692 adev->mode_info.num_hpd = 5;
1693 adev->mode_info.num_dig = 5;
3be5262e 1694 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1695 break;
1696 case CHIP_POLARIS10:
1697 adev->mode_info.num_crtc = 6;
1698 adev->mode_info.num_hpd = 6;
1699 adev->mode_info.num_dig = 6;
3be5262e 1700 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1701 break;
2c8ad2d5 1702 case CHIP_VEGA10:
2325ff30 1703 case CHIP_VEGA12:
2c8ad2d5
AD		 1704 adev->mode_info.num_crtc = 6;
1705 adev->mode_info.num_hpd = 6;
1706 adev->mode_info.num_dig = 6;
3be5262e 1707 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1708 break;
ff5ef992
AD		 1709#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1710 case CHIP_RAVEN:
1711 adev->mode_info.num_crtc = 4;
1712 adev->mode_info.num_hpd = 4;
1713 adev->mode_info.num_dig = 4;
3be5262e 1714 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1715 break;
1716#endif
4562236b
HW		 1717 default:
1718 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1719 return -EINVAL;
1720 }
1721
c8dd5715
MD		 1722 amdgpu_dm_set_irq_funcs(adev);
1723
39cc5be2
AD		 1724 if (adev->mode_info.funcs == NULL)
1725 adev->mode_info.funcs = &dm_display_funcs;
1726
4562236b
HW		 1727 /* Note: Do NOT change adev->audio_endpt_rreg and
1728 * adev->audio_endpt_wreg because they are initialised in
1729 * amdgpu_device_init() */
1730#if defined(CONFIG_DEBUG_KERNEL_DC)
1731 device_create_file(
1732 adev->ddev->dev,
1733 &dev_attr_s3_debug);
1734#endif
1735
1736 return 0;
1737}
1738
9b690ef3 1739static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1740 struct dc_stream_state *new_stream,
1741 struct dc_stream_state *old_stream)
9b690ef3 1742{
e7b07cee
HW		 1743 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1744 return false;
1745
1746 if (!crtc_state->enable)
1747 return false;
1748
1749 return crtc_state->active;
1750}
1751
1752static bool modereset_required(struct drm_crtc_state *crtc_state)
1753{
1754 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1755 return false;
1756
1757 return !crtc_state->enable || !crtc_state->active;
1758}
1759
7578ecda 1760static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1761{
1762 drm_encoder_cleanup(encoder);
1763 kfree(encoder);
1764}
1765
1766static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1767 .destroy = amdgpu_dm_encoder_destroy,
1768};
1769
3ee6b26b
AD		 1770static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1771 struct dc_plane_state *plane_state)
e7b07cee 1772{
3be5262e
HW		 1773 plane_state->src_rect.x = state->src_x >> 16;
1774 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1775 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1776 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1777
3be5262e 1778 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1779 return false;
1780
3be5262e
HW		 1781 plane_state->src_rect.height = state->src_h >> 16;
1782 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1783 return false;
1784
3be5262e
HW		 1785 plane_state->dst_rect.x = state->crtc_x;
1786 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1787
1788 if (state->crtc_w == 0)
1789 return false;
1790
3be5262e 1791 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1792
1793 if (state->crtc_h == 0)
1794 return false;
1795
3be5262e 1796 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1797
3be5262e 1798 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1799
1800 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1801 case DRM_MODE_ROTATE_0:
3be5262e 1802 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1803 break;
1804 case DRM_MODE_ROTATE_90:
3be5262e 1805 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1806 break;
1807 case DRM_MODE_ROTATE_180:
3be5262e 1808 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1809 break;
1810 case DRM_MODE_ROTATE_270:
3be5262e 1811 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1812 break;
1813 default:
3be5262e 1814 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1815 break;
1816 }
1817
4562236b
HW		 1818 return true;
1819}
3ee6b26b 1820static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 1821 uint64_t *tiling_flags)
e7b07cee
HW		 1822{
1823 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1824 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1825
e7b07cee 1826 if (unlikely(r)) {
9bbc3031
JZ		 1827 // Don't show error msg. when return -ERESTARTSYS
1828 if (r != -ERESTARTSYS)
1829 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1830 return r;
1831 }
1832
e7b07cee
HW		 1833 if (tiling_flags)
1834 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1835
1836 amdgpu_bo_unreserve(rbo);
1837
1838 return r;
1839}
1840
3ee6b26b
AD		 1841static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1842 struct dc_plane_state *plane_state,
9817d5f5 1843 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 1844{
1845 uint64_t tiling_flags;
e7b07cee
HW		 1846 unsigned int awidth;
1847 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1848 int ret = 0;
1849 struct drm_format_name_buf format_name;
1850
1851 ret = get_fb_info(
1852 amdgpu_fb,
9817d5f5 1853 &tiling_flags);
e7b07cee
HW		 1854
1855 if (ret)
1856 return ret;
1857
1858 switch (fb->format->format) {
1859 case DRM_FORMAT_C8:
3be5262e 1860 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1861 break;
1862 case DRM_FORMAT_RGB565:
3be5262e 1863 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1864 break;
1865 case DRM_FORMAT_XRGB8888:
1866 case DRM_FORMAT_ARGB8888:
3be5262e 1867 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1868 break;
1869 case DRM_FORMAT_XRGB2101010:
1870 case DRM_FORMAT_ARGB2101010:
3be5262e 1871 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1872 break;
1873 case DRM_FORMAT_XBGR2101010:
1874 case DRM_FORMAT_ABGR2101010:
3be5262e 1875 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1876 break;
1877 case DRM_FORMAT_NV21:
3be5262e 1878 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1879 break;
1880 case DRM_FORMAT_NV12:
3be5262e 1881 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1882 break;
1883 default:
1884 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1885 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1886 return -EINVAL;
1887 }
1888
3be5262e
HW		 1889 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1890 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 1891 plane_state->plane_size.grph.surface_size.x = 0;
1892 plane_state->plane_size.grph.surface_size.y = 0;
1893 plane_state->plane_size.grph.surface_size.width = fb->width;
1894 plane_state->plane_size.grph.surface_size.height = fb->height;
1895 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1896 fb->pitches[0] / fb->format->cpp[0];
1897 /* TODO: unhardcode */
3be5262e 1898 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1899
1900 } else {
1901 awidth = ALIGN(fb->width, 64);
3be5262e 1902 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 1903 plane_state->plane_size.video.luma_size.x = 0;
1904 plane_state->plane_size.video.luma_size.y = 0;
1905 plane_state->plane_size.video.luma_size.width = awidth;
1906 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1907 /* TODO: unhardcode */
3be5262e 1908 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1909
3be5262e
HW		 1910 plane_state->plane_size.video.chroma_size.x = 0;
1911 plane_state->plane_size.video.chroma_size.y = 0;
1912 plane_state->plane_size.video.chroma_size.width = awidth;
1913 plane_state->plane_size.video.chroma_size.height = fb->height;
1914 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1915
1916 /* TODO: unhardcode */
3be5262e 1917 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1918 }
1919
3be5262e 1920 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1921
b830ebc9
HW		 1922 /* Fill GFX8 params */
1923 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1924 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1925
1926 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1927 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1928 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1929 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1930 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1931
1932 /* XXX fix me for VI */
3be5262e
HW		 1933 plane_state->tiling_info.gfx8.num_banks = num_banks;
1934 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1935 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1936 plane_state->tiling_info.gfx8.tile_split = tile_split;
1937 plane_state->tiling_info.gfx8.bank_width = bankw;
1938 plane_state->tiling_info.gfx8.bank_height = bankh;
1939 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1940 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1941 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1942 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1943 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1944 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1945 }
1946
3be5262e 1947 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1948 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1949
1950 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1951 adev->asic_type == CHIP_VEGA12 ||
e7b07cee
HW		 1952 adev->asic_type == CHIP_RAVEN) {
1953 /* Fill GFX9 params */
3be5262e 1954 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1955 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1956 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1957 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1958 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1959 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1960 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1961 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1962 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1963 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1964 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1965 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1966 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1967 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1968 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1969 }
1970
3be5262e
HW		 1971 plane_state->visible = true;
1972 plane_state->scaling_quality.h_taps_c = 0;
1973 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1974
3be5262e
HW		 1975 /* is this needed? is plane_state zeroed at allocation? */
1976 plane_state->scaling_quality.h_taps = 0;
1977 plane_state->scaling_quality.v_taps = 0;
1978 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1979
1980 return ret;
1981
1982}
1983
3ee6b26b
AD		 1984static int fill_plane_attributes(struct amdgpu_device *adev,
1985 struct dc_plane_state *dc_plane_state,
1986 struct drm_plane_state *plane_state,
9817d5f5 1987 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 1988{
1989 const struct amdgpu_framebuffer *amdgpu_fb =
1990 to_amdgpu_framebuffer(plane_state->fb);
1991 const struct drm_crtc *crtc = plane_state->crtc;
1992 struct dc_transfer_func *input_tf;
1993 int ret = 0;
1994
3be5262e 1995 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1996 return -EINVAL;
1997
1998 ret = fill_plane_attributes_from_fb(
1999 crtc->dev->dev_private,
3be5262e 2000 dc_plane_state,
9817d5f5 2001 amdgpu_fb);
e7b07cee
HW		 2002
2003 if (ret)
2004 return ret;
2005
2006 input_tf = dc_create_transfer_func();
2007
2008 if (input_tf == NULL)
2009 return -ENOMEM;
2010
3be5262e 2011 dc_plane_state->in_transfer_func = input_tf;
e7b07cee 2012
e277adc5
LSL		 2013 /*
2014 * Always set input transfer function, since plane state is refreshed
2015 * every time.
2016 */
2017 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2018 if (ret) {
2019 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2020 dc_plane_state->in_transfer_func = NULL;
2021 }
e7b07cee
HW		 2022
2023 return ret;
2024}
2025
2026/*****************************************************************************/
2027
3ee6b26b
AD		 2028static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2029 const struct dm_connector_state *dm_state,
2030 struct dc_stream_state *stream)
e7b07cee
HW		 2031{
2032 enum amdgpu_rmx_type rmx_type;
2033
2034 struct rect src = { 0 }; /* viewport in composition space*/
2035 struct rect dst = { 0 }; /* stream addressable area */
2036
2037 /* no mode. nothing to be done */
2038 if (!mode)
2039 return;
2040
2041 /* Full screen scaling by default */
2042 src.width = mode->hdisplay;
2043 src.height = mode->vdisplay;
2044 dst.width = stream->timing.h_addressable;
2045 dst.height = stream->timing.v_addressable;
2046
f4791779
HW		 2047 if (dm_state) {
2048 rmx_type = dm_state->scaling;
2049 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2050 if (src.width * dst.height <
2051 src.height * dst.width) {
2052 /* height needs less upscaling/more downscaling */
2053 dst.width = src.width *
2054 dst.height / src.height;
2055 } else {
2056 /* width needs less upscaling/more downscaling */
2057 dst.height = src.height *
2058 dst.width / src.width;
2059 }
2060 } else if (rmx_type == RMX_CENTER) {
2061 dst = src;
e7b07cee 2062 }
e7b07cee 2063
f4791779
HW		 2064 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2065 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2066
f4791779
HW		 2067 if (dm_state->underscan_enable) {
2068 dst.x += dm_state->underscan_hborder / 2;
2069 dst.y += dm_state->underscan_vborder / 2;
2070 dst.width -= dm_state->underscan_hborder;
2071 dst.height -= dm_state->underscan_vborder;
2072 }
e7b07cee
HW		 2073 }
2074
2075 stream->src = src;
2076 stream->dst = dst;
2077
f1ad2f5e 2078 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2079 dst.x, dst.y, dst.width, dst.height);
2080
2081}
2082
3ee6b26b
AD		 2083static enum dc_color_depth
2084convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2085{
2086 uint32_t bpc = connector->display_info.bpc;
2087
2088 /* Limited color depth to 8bit
b830ebc9
HW		 2089 * TODO: Still need to handle deep color
2090 */
e7b07cee
HW		 2091 if (bpc > 8)
2092 bpc = 8;
2093
2094 switch (bpc) {
2095 case 0:
2096 /* Temporary Work around, DRM don't parse color depth for
2097 * EDID revision before 1.4
2098 * TODO: Fix edid parsing
2099 */
2100 return COLOR_DEPTH_888;
2101 case 6:
2102 return COLOR_DEPTH_666;
2103 case 8:
2104 return COLOR_DEPTH_888;
2105 case 10:
2106 return COLOR_DEPTH_101010;
2107 case 12:
2108 return COLOR_DEPTH_121212;
2109 case 14:
2110 return COLOR_DEPTH_141414;
2111 case 16:
2112 return COLOR_DEPTH_161616;
2113 default:
2114 return COLOR_DEPTH_UNDEFINED;
2115 }
2116}
2117
3ee6b26b
AD		 2118static enum dc_aspect_ratio
2119get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2120{
2121 int32_t width = mode_in->crtc_hdisplay * 9;
2122 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2123
e7b07cee
HW		 2124 if ((width - height) < 10 && (width - height) > -10)
2125 return ASPECT_RATIO_16_9;
2126 else
2127 return ASPECT_RATIO_4_3;
2128}
2129
3ee6b26b
AD		 2130static enum dc_color_space
2131get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2132{
2133 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2134
2135 switch (dc_crtc_timing->pixel_encoding) {
2136 case PIXEL_ENCODING_YCBCR422:
2137 case PIXEL_ENCODING_YCBCR444:
2138 case PIXEL_ENCODING_YCBCR420:
2139 {
2140 /*
2141 * 27030khz is the separation point between HDTV and SDTV
2142 * according to HDMI spec, we use YCbCr709 and YCbCr601
2143 * respectively
2144 */
2145 if (dc_crtc_timing->pix_clk_khz > 27030) {
2146 if (dc_crtc_timing->flags.Y_ONLY)
2147 color_space =
2148 COLOR_SPACE_YCBCR709_LIMITED;
2149 else
2150 color_space = COLOR_SPACE_YCBCR709;
2151 } else {
2152 if (dc_crtc_timing->flags.Y_ONLY)
2153 color_space =
2154 COLOR_SPACE_YCBCR601_LIMITED;
2155 else
2156 color_space = COLOR_SPACE_YCBCR601;
2157 }
2158
2159 }
2160 break;
2161 case PIXEL_ENCODING_RGB:
2162 color_space = COLOR_SPACE_SRGB;
2163 break;
2164
2165 default:
2166 WARN_ON(1);
2167 break;
2168 }
2169
2170 return color_space;
2171}
2172
2173/*****************************************************************************/
2174
3ee6b26b
AD		 2175static void
2176fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2177 const struct drm_display_mode *mode_in,
2178 const struct drm_connector *connector)
e7b07cee
HW		 2179{
2180 struct dc_crtc_timing *timing_out = &stream->timing;
a6114e85 2181 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2182
e7b07cee
HW		 2183 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2184
2185 timing_out->h_border_left = 0;
2186 timing_out->h_border_right = 0;
2187 timing_out->v_border_top = 0;
2188 timing_out->v_border_bottom = 0;
2189 /* TODO: un-hardcode */
2190
2191 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2192 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2193 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2194 else
2195 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2196
2197 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2198 timing_out->display_color_depth = convert_color_depth_from_display_info(
2199 connector);
2200 timing_out->scan_type = SCANNING_TYPE_NODATA;
2201 timing_out->hdmi_vic = 0;
2202 timing_out->vic = drm_match_cea_mode(mode_in);
2203
2204 timing_out->h_addressable = mode_in->crtc_hdisplay;
2205 timing_out->h_total = mode_in->crtc_htotal;
2206 timing_out->h_sync_width =
2207 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2208 timing_out->h_front_porch =
2209 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2210 timing_out->v_total = mode_in->crtc_vtotal;
2211 timing_out->v_addressable = mode_in->crtc_vdisplay;
2212 timing_out->v_front_porch =
2213 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2214 timing_out->v_sync_width =
2215 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2216 timing_out->pix_clk_khz = mode_in->crtc_clock;
2217 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2218 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2219 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2220 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2221 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2222
2223 stream->output_color_space = get_output_color_space(timing_out);
2224
a6114e85
HW		 2225 tf->type = TF_TYPE_PREDEFINED;
2226 tf->tf = TRANSFER_FUNCTION_SRGB;
2227 stream->out_transfer_func = tf;
e7b07cee
HW		 2228}
2229
3ee6b26b
AD		 2230static void fill_audio_info(struct audio_info *audio_info,
2231 const struct drm_connector *drm_connector,
2232 const struct dc_sink *dc_sink)
e7b07cee
HW		 2233{
2234 int i = 0;
2235 int cea_revision = 0;
2236 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2237
2238 audio_info->manufacture_id = edid_caps->manufacturer_id;
2239 audio_info->product_id = edid_caps->product_id;
2240
2241 cea_revision = drm_connector->display_info.cea_rev;
2242
d2b2562c
TSD		 2243 strncpy(audio_info->display_name,
2244 edid_caps->display_name,
2245 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2246
b830ebc9 2247 if (cea_revision >= 3) {
e7b07cee
HW		 2248 audio_info->mode_count = edid_caps->audio_mode_count;
2249
2250 for (i = 0; i < audio_info->mode_count; ++i) {
2251 audio_info->modes[i].format_code =
2252 (enum audio_format_code)
2253 (edid_caps->audio_modes[i].format_code);
2254 audio_info->modes[i].channel_count =
2255 edid_caps->audio_modes[i].channel_count;
2256 audio_info->modes[i].sample_rates.all =
2257 edid_caps->audio_modes[i].sample_rate;
2258 audio_info->modes[i].sample_size =
2259 edid_caps->audio_modes[i].sample_size;
2260 }
2261 }
2262
2263 audio_info->flags.all = edid_caps->speaker_flags;
2264
2265 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2266 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2267 audio_info->video_latency = drm_connector->video_latency[0];
2268 audio_info->audio_latency = drm_connector->audio_latency[0];
2269 }
2270
2271 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2272
2273}
2274
3ee6b26b
AD		 2275static void
2276copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2277 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2278{
2279 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2280 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2281 dst_mode->crtc_clock = src_mode->crtc_clock;
2282 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2283 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2284 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2285 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2286 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2287 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2288 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2289 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2290 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2291 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2292 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2293}
2294
3ee6b26b
AD		 2295static void
2296decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2297 const struct drm_display_mode *native_mode,
2298 bool scale_enabled)
e7b07cee
HW		 2299{
2300 if (scale_enabled) {
2301 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2302 } else if (native_mode->clock == drm_mode->clock &&
2303 native_mode->htotal == drm_mode->htotal &&
2304 native_mode->vtotal == drm_mode->vtotal) {
2305 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2306 } else {
2307 /* no scaling nor amdgpu inserted, no need to patch */
2308 }
2309}
2310
423788c7 2311static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6
HW		 2312{
2313 struct dc_sink *sink = NULL;
2314 struct dc_sink_init_data sink_init_data = { 0 };
2315
2316 sink_init_data.link = aconnector->dc_link;
2317 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2318
2319 sink = dc_sink_create(&sink_init_data);
423788c7 2320 if (!sink) {
2e0ac3d6 2321 DRM_ERROR("Failed to create sink!\n");
423788c7
ES		 2322 return -ENOMEM;
2323 }
2e0ac3d6
HW		 2324
2325 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2326 aconnector->fake_enable = true;
2327
2328 aconnector->dc_sink = sink;
2329 aconnector->dc_link->local_sink = sink;
423788c7
ES		 2330
2331 return 0;
2e0ac3d6
HW		 2332}
2333
fa2123db
ML		 2334static void set_multisync_trigger_params(
2335 struct dc_stream_state *stream)
2336{
2337 if (stream->triggered_crtc_reset.enabled) {
2338 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2339 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2340 }
2341}
2342
2343static void set_master_stream(struct dc_stream_state *stream_set[],
2344 int stream_count)
2345{
2346 int j, highest_rfr = 0, master_stream = 0;
2347
2348 for (j = 0; j < stream_count; j++) {
2349 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2350 int refresh_rate = 0;
2351
2352 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2353 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2354 if (refresh_rate > highest_rfr) {
2355 highest_rfr = refresh_rate;
2356 master_stream = j;
2357 }
2358 }
2359 }
2360 for (j = 0; j < stream_count; j++) {
03736f4c 2361 if (stream_set[j])
fa2123db
ML		 2362 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2363 }
2364}
2365
2366static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2367{
2368 int i = 0;
2369
2370 if (context->stream_count < 2)
2371 return;
2372 for (i = 0; i < context->stream_count ; i++) {
2373 if (!context->streams[i])
2374 continue;
2375 /* TODO: add a function to read AMD VSDB bits and will set
2376 * crtc_sync_master.multi_sync_enabled flag
2377 * For now its set to false
2378 */
2379 set_multisync_trigger_params(context->streams[i]);
2380 }
2381 set_master_stream(context->streams, context->stream_count);
2382}
2383
3ee6b26b
AD		 2384static struct dc_stream_state *
2385create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2386 const struct drm_display_mode *drm_mode,
2387 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2388{
2389 struct drm_display_mode *preferred_mode = NULL;
391ef035 2390 struct drm_connector *drm_connector;
0971c40e 2391 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2392 struct drm_display_mode mode = *drm_mode;
2393 bool native_mode_found = false;
2394
b830ebc9 2395 if (aconnector == NULL) {
e7b07cee 2396 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2397 return stream;
e7b07cee
HW		 2398 }
2399
e7b07cee 2400 drm_connector = &aconnector->base;
2e0ac3d6 2401
f4ac176e
JZ		 2402 if (!aconnector->dc_sink) {
2403 /*
391ef035
JFZ		 2404 * Create dc_sink when necessary to MST
2405 * Don't apply fake_sink to MST
f4ac176e 2406 */
391ef035
JFZ		 2407 if (aconnector->mst_port) {
2408 dm_dp_mst_dc_sink_create(drm_connector);
64245fa7 2409 return stream;
391ef035 2410 }
f4ac176e 2411
423788c7 2412 if (create_fake_sink(aconnector))
64245fa7 2413 return stream;
f4ac176e 2414 }
2e0ac3d6 2415
e7b07cee 2416 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2417
b830ebc9 2418 if (stream == NULL) {
e7b07cee 2419 DRM_ERROR("Failed to create stream for sink!\n");
64245fa7 2420 return stream;
e7b07cee
HW		 2421 }
2422
2423 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2424 /* Search for preferred mode */
2425 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2426 native_mode_found = true;
2427 break;
2428 }
2429 }
2430 if (!native_mode_found)
2431 preferred_mode = list_first_entry_or_null(
2432 &aconnector->base.modes,
2433 struct drm_display_mode,
2434 head);
2435
b830ebc9 2436 if (preferred_mode == NULL) {
e7b07cee
HW		 2437 /* This may not be an error, the use case is when we we have no
2438 * usermode calls to reset and set mode upon hotplug. In this
2439 * case, we call set mode ourselves to restore the previous mode
2440 * and the modelist may not be filled in in time.
2441 */
f1ad2f5e 2442 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2443 } else {
2444 decide_crtc_timing_for_drm_display_mode(
2445 &mode, preferred_mode,
f4791779 2446 dm_state ? (dm_state->scaling != RMX_OFF) : false);
e7b07cee
HW		 2447 }
2448
f783577c
JFZ		 2449 if (!dm_state)
2450 drm_mode_set_crtcinfo(&mode, 0);
2451
e7b07cee
HW		 2452 fill_stream_properties_from_drm_display_mode(stream,
2453 &mode, &aconnector->base);
2454 update_stream_scaling_settings(&mode, dm_state, stream);
2455
2456 fill_audio_info(
2457 &stream->audio_info,
2458 drm_connector,
2459 aconnector->dc_sink);
2460
9182b4cb
HW		 2461 update_stream_signal(stream);
2462
e7b07cee
HW		 2463 return stream;
2464}
2465
7578ecda 2466static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2467{
2468 drm_crtc_cleanup(crtc);
2469 kfree(crtc);
2470}
2471
2472static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2473 struct drm_crtc_state *state)
e7b07cee
HW		 2474{
2475 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2476
2477 /* TODO Destroy dc_stream objects are stream object is flattened */
2478 if (cur->stream)
2479 dc_stream_release(cur->stream);
2480
2481
2482 __drm_atomic_helper_crtc_destroy_state(state);
2483
2484
2485 kfree(state);
2486}
2487
2488static void dm_crtc_reset_state(struct drm_crtc *crtc)
2489{
2490 struct dm_crtc_state *state;
2491
2492 if (crtc->state)
2493 dm_crtc_destroy_state(crtc, crtc->state);
2494
2495 state = kzalloc(sizeof(*state), GFP_KERNEL);
2496 if (WARN_ON(!state))
2497 return;
2498
2499 crtc->state = &state->base;
2500 crtc->state->crtc = crtc;
2501
2502}
2503
2504static struct drm_crtc_state *
2505dm_crtc_duplicate_state(struct drm_crtc *crtc)
2506{
2507 struct dm_crtc_state *state, *cur;
2508
2509 cur = to_dm_crtc_state(crtc->state);
2510
2511 if (WARN_ON(!crtc->state))
2512 return NULL;
2513
2004f45e 2514 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 2515 if (!state)
2516 return NULL;
e7b07cee
HW		 2517
2518 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2519
2520 if (cur->stream) {
2521 state->stream = cur->stream;
2522 dc_stream_retain(state->stream);
2523 }
2524
2525 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2526
2527 return &state->base;
2528}
2529
589d2739
HW		 2530
2531static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2532{
2533 enum dc_irq_source irq_source;
2534 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2535 struct amdgpu_device *adev = crtc->dev->dev_private;
2536
2537 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 2538 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 2539}
2540
2541static int dm_enable_vblank(struct drm_crtc *crtc)
2542{
2543 return dm_set_vblank(crtc, true);
2544}
2545
2546static void dm_disable_vblank(struct drm_crtc *crtc)
2547{
2548 dm_set_vblank(crtc, false);
2549}
2550
e7b07cee
HW		 2551/* Implemented only the options currently availible for the driver */
2552static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2553 .reset = dm_crtc_reset_state,
2554 .destroy = amdgpu_dm_crtc_destroy,
2555 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2556 .set_config = drm_atomic_helper_set_config,
2557 .page_flip = drm_atomic_helper_page_flip,
2558 .atomic_duplicate_state = dm_crtc_duplicate_state,
2559 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 2560 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
589d2739
HW		 2561 .enable_vblank = dm_enable_vblank,
2562 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 2563};
2564
2565static enum drm_connector_status
2566amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2567{
2568 bool connected;
c84dec2f 2569 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2570
2571 /* Notes:
2572 * 1. This interface is NOT called in context of HPD irq.
2573 * 2. This interface *is called* in context of user-mode ioctl. Which
2574 * makes it a bad place for *any* MST-related activit. */
2575
8580d60b
HW		 2576 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2577 !aconnector->fake_enable)
e7b07cee
HW		 2578 connected = (aconnector->dc_sink != NULL);
2579 else
2580 connected = (aconnector->base.force == DRM_FORCE_ON);
2581
2582 return (connected ? connector_status_connected :
2583 connector_status_disconnected);
2584}
2585
3ee6b26b
AD		 2586int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2587 struct drm_connector_state *connector_state,
2588 struct drm_property *property,
2589 uint64_t val)
e7b07cee
HW		 2590{
2591 struct drm_device *dev = connector->dev;
2592 struct amdgpu_device *adev = dev->dev_private;
2593 struct dm_connector_state *dm_old_state =
2594 to_dm_connector_state(connector->state);
2595 struct dm_connector_state *dm_new_state =
2596 to_dm_connector_state(connector_state);
2597
2598 int ret = -EINVAL;
2599
2600 if (property == dev->mode_config.scaling_mode_property) {
2601 enum amdgpu_rmx_type rmx_type;
2602
2603 switch (val) {
2604 case DRM_MODE_SCALE_CENTER:
2605 rmx_type = RMX_CENTER;
2606 break;
2607 case DRM_MODE_SCALE_ASPECT:
2608 rmx_type = RMX_ASPECT;
2609 break;
2610 case DRM_MODE_SCALE_FULLSCREEN:
2611 rmx_type = RMX_FULL;
2612 break;
2613 case DRM_MODE_SCALE_NONE:
2614 default:
2615 rmx_type = RMX_OFF;
2616 break;
2617 }
2618
2619 if (dm_old_state->scaling == rmx_type)
2620 return 0;
2621
2622 dm_new_state->scaling = rmx_type;
2623 ret = 0;
2624 } else if (property == adev->mode_info.underscan_hborder_property) {
2625 dm_new_state->underscan_hborder = val;
2626 ret = 0;
2627 } else if (property == adev->mode_info.underscan_vborder_property) {
2628 dm_new_state->underscan_vborder = val;
2629 ret = 0;
2630 } else if (property == adev->mode_info.underscan_property) {
2631 dm_new_state->underscan_enable = val;
2632 ret = 0;
2633 }
2634
2635 return ret;
2636}
2637
3ee6b26b
AD		 2638int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2639 const struct drm_connector_state *state,
2640 struct drm_property *property,
2641 uint64_t *val)
e7b07cee
HW		 2642{
2643 struct drm_device *dev = connector->dev;
2644 struct amdgpu_device *adev = dev->dev_private;
2645 struct dm_connector_state *dm_state =
2646 to_dm_connector_state(state);
2647 int ret = -EINVAL;
2648
2649 if (property == dev->mode_config.scaling_mode_property) {
2650 switch (dm_state->scaling) {
2651 case RMX_CENTER:
2652 *val = DRM_MODE_SCALE_CENTER;
2653 break;
2654 case RMX_ASPECT:
2655 *val = DRM_MODE_SCALE_ASPECT;
2656 break;
2657 case RMX_FULL:
2658 *val = DRM_MODE_SCALE_FULLSCREEN;
2659 break;
2660 case RMX_OFF:
2661 default:
2662 *val = DRM_MODE_SCALE_NONE;
2663 break;
2664 }
2665 ret = 0;
2666 } else if (property == adev->mode_info.underscan_hborder_property) {
2667 *val = dm_state->underscan_hborder;
2668 ret = 0;
2669 } else if (property == adev->mode_info.underscan_vborder_property) {
2670 *val = dm_state->underscan_vborder;
2671 ret = 0;
2672 } else if (property == adev->mode_info.underscan_property) {
2673 *val = dm_state->underscan_enable;
2674 ret = 0;
2675 }
2676 return ret;
2677}
2678
7578ecda 2679static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2680{
c84dec2f 2681 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2682 const struct dc_link *link = aconnector->dc_link;
2683 struct amdgpu_device *adev = connector->dev->dev_private;
2684 struct amdgpu_display_manager *dm = &adev->dm;
2685#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2686 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2687
2688 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2689 amdgpu_dm_register_backlight_device(dm);
2690
2691 if (dm->backlight_dev) {
2692 backlight_device_unregister(dm->backlight_dev);
2693 dm->backlight_dev = NULL;
2694 }
2695
2696 }
2697#endif
2698 drm_connector_unregister(connector);
2699 drm_connector_cleanup(connector);
2700 kfree(connector);
2701}
2702
2703void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2704{
2705 struct dm_connector_state *state =
2706 to_dm_connector_state(connector->state);
2707
2708 kfree(state);
2709
2710 state = kzalloc(sizeof(*state), GFP_KERNEL);
2711
2712 if (state) {
2713 state->scaling = RMX_OFF;
2714 state->underscan_enable = false;
2715 state->underscan_hborder = 0;
2716 state->underscan_vborder = 0;
2717
2718 connector->state = &state->base;
2719 connector->state->connector = connector;
2720 }
2721}
2722
3ee6b26b
AD		 2723struct drm_connector_state *
2724amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2725{
2726 struct dm_connector_state *state =
2727 to_dm_connector_state(connector->state);
2728
2729 struct dm_connector_state *new_state =
2730 kmemdup(state, sizeof(*state), GFP_KERNEL);
2731
2732 if (new_state) {
2733 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2734 &new_state->base);
e7b07cee
HW		 2735 return &new_state->base;
2736 }
2737
2738 return NULL;
2739}
2740
2741static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2742 .reset = amdgpu_dm_connector_funcs_reset,
2743 .detect = amdgpu_dm_connector_detect,
2744 .fill_modes = drm_helper_probe_single_connector_modes,
2745 .destroy = amdgpu_dm_connector_destroy,
2746 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2747 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2748 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2749 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2750};
2751
2752static struct drm_encoder *best_encoder(struct drm_connector *connector)
2753{
2754 int enc_id = connector->encoder_ids[0];
2755 struct drm_mode_object *obj;
2756 struct drm_encoder *encoder;
2757
f1ad2f5e 2758 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2759
2760 /* pick the encoder ids */
2761 if (enc_id) {
bd21a37d 2762 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2763 if (!obj) {
2764 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2765 return NULL;
2766 }
2767 encoder = obj_to_encoder(obj);
2768 return encoder;
2769 }
2770 DRM_ERROR("No encoder id\n");
2771 return NULL;
2772}
2773
2774static int get_modes(struct drm_connector *connector)
2775{
2776 return amdgpu_dm_connector_get_modes(connector);
2777}
2778
c84dec2f 2779static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2780{
2781 struct dc_sink_init_data init_params = {
2782 .link = aconnector->dc_link,
2783 .sink_signal = SIGNAL_TYPE_VIRTUAL
2784 };
70e8ffc5 2785 struct edid *edid;
e7b07cee 2786
a89ff457 2787 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 2788 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2789 aconnector->base.name);
2790
2791 aconnector->base.force = DRM_FORCE_OFF;
2792 aconnector->base.override_edid = false;
2793 return;
2794 }
2795
70e8ffc5
HW		 2796 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2797
e7b07cee
HW		 2798 aconnector->edid = edid;
2799
2800 aconnector->dc_em_sink = dc_link_add_remote_sink(
2801 aconnector->dc_link,
2802 (uint8_t *)edid,
2803 (edid->extensions + 1) * EDID_LENGTH,
2804 &init_params);
2805
a68d90e7 2806 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 2807 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2808 aconnector->dc_link->local_sink :
2809 aconnector->dc_em_sink;
2810}
2811
c84dec2f 2812static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2813{
2814 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2815
2816 /* In case of headless boot with force on for DP managed connector
2817 * Those settings have to be != 0 to get initial modeset
2818 */
2819 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2820 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2821 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2822 }
2823
2824
2825 aconnector->base.override_edid = true;
2826 create_eml_sink(aconnector);
2827}
2828
3ee6b26b
AD		 2829int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2830 struct drm_display_mode *mode)
e7b07cee
HW		 2831{
2832 int result = MODE_ERROR;
2833 struct dc_sink *dc_sink;
2834 struct amdgpu_device *adev = connector->dev->dev_private;
2835 /* TODO: Unhardcode stream count */
0971c40e 2836 struct dc_stream_state *stream;
c84dec2f 2837 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 2838 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 2839
2840 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2841 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2842 return result;
2843
2844 /* Only run this the first time mode_valid is called to initilialize
2845 * EDID mgmt
2846 */
2847 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2848 !aconnector->dc_em_sink)
2849 handle_edid_mgmt(aconnector);
2850
c84dec2f 2851 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2852
b830ebc9 2853 if (dc_sink == NULL) {
e7b07cee
HW		 2854 DRM_ERROR("dc_sink is NULL!\n");
2855 goto fail;
2856 }
2857
f4791779 2858 stream = create_stream_for_sink(aconnector, mode, NULL);
b830ebc9 2859 if (stream == NULL) {
e7b07cee
HW		 2860 DRM_ERROR("Failed to create stream for sink!\n");
2861 goto fail;
2862 }
2863
a39438f0
HW		 2864 dc_result = dc_validate_stream(adev->dm.dc, stream);
2865
2866 if (dc_result == DC_OK)
e7b07cee 2867 result = MODE_OK;
a39438f0 2868 else
9f921b14 2869 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 2870 mode->vdisplay,
2871 mode->hdisplay,
9f921b14
HW		 2872 mode->clock,
2873 dc_result);
e7b07cee
HW		 2874
2875 dc_stream_release(stream);
2876
2877fail:
2878 /* TODO: error handling*/
2879 return result;
2880}
2881
2882static const struct drm_connector_helper_funcs
2883amdgpu_dm_connector_helper_funcs = {
2884 /*
b830ebc9
HW		 2885 * If hotplug a second bigger display in FB Con mode, bigger resolution
2886 * modes will be filtered by drm_mode_validate_size(), and those modes
2887 * is missing after user start lightdm. So we need to renew modes list.
2888 * in get_modes call back, not just return the modes count
2889 */
e7b07cee
HW		 2890 .get_modes = get_modes,
2891 .mode_valid = amdgpu_dm_connector_mode_valid,
2892 .best_encoder = best_encoder
2893};
2894
2895static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2896{
2897}
2898
3ee6b26b
AD		 2899static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2900 struct drm_crtc_state *state)
e7b07cee
HW		 2901{
2902 struct amdgpu_device *adev = crtc->dev->dev_private;
2903 struct dc *dc = adev->dm.dc;
2904 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2905 int ret = -EINVAL;
2906
9b690ef3
BL		 2907 if (unlikely(!dm_crtc_state->stream &&
2908 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2909 WARN_ON(1);
2910 return ret;
2911 }
2912
2913 /* In some use cases, like reset, no stream is attached */
2914 if (!dm_crtc_state->stream)
2915 return 0;
2916
62c933f9 2917 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 2918 return 0;
2919
2920 return ret;
2921}
2922
3ee6b26b
AD		 2923static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2924 const struct drm_display_mode *mode,
2925 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2926{
2927 return true;
2928}
2929
2930static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2931 .disable = dm_crtc_helper_disable,
2932 .atomic_check = dm_crtc_helper_atomic_check,
2933 .mode_fixup = dm_crtc_helper_mode_fixup
2934};
2935
2936static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2937{
2938
2939}
2940
3ee6b26b
AD		 2941static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2942 struct drm_crtc_state *crtc_state,
2943 struct drm_connector_state *conn_state)
e7b07cee
HW		 2944{
2945 return 0;
2946}
2947
2948const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2949 .disable = dm_encoder_helper_disable,
2950 .atomic_check = dm_encoder_helper_atomic_check
2951};
2952
2953static void dm_drm_plane_reset(struct drm_plane *plane)
2954{
2955 struct dm_plane_state *amdgpu_state = NULL;
2956
2957 if (plane->state)
2958 plane->funcs->atomic_destroy_state(plane, plane->state);
2959
2960 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d
TSD		 2961 WARN_ON(amdgpu_state == NULL);
2962
e7b07cee
HW		 2963 if (amdgpu_state) {
2964 plane->state = &amdgpu_state->base;
2965 plane->state->plane = plane;
2966 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 2967 }
e7b07cee
HW		 2968}
2969
2970static struct drm_plane_state *
2971dm_drm_plane_duplicate_state(struct drm_plane *plane)
2972{
2973 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2974
2975 old_dm_plane_state = to_dm_plane_state(plane->state);
2976 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2977 if (!dm_plane_state)
2978 return NULL;
2979
2980 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2981
3be5262e
HW		 2982 if (old_dm_plane_state->dc_state) {
2983 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2984 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2985 }
2986
2987 return &dm_plane_state->base;
2988}
2989
2990void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2991 struct drm_plane_state *state)
e7b07cee
HW		 2992{
2993 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2994
3be5262e
HW		 2995 if (dm_plane_state->dc_state)
2996 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2997
0627bbd3 2998 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2999}
3000
3001static const struct drm_plane_funcs dm_plane_funcs = {
3002 .update_plane = drm_atomic_helper_update_plane,
3003 .disable_plane = drm_atomic_helper_disable_plane,
3004 .destroy = drm_plane_cleanup,
3005 .reset = dm_drm_plane_reset,
3006 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3007 .atomic_destroy_state = dm_drm_plane_destroy_state,
3008};
3009
3ee6b26b
AD		 3010static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3011 struct drm_plane_state *new_state)
e7b07cee
HW		 3012{
3013 struct amdgpu_framebuffer *afb;
3014 struct drm_gem_object *obj;
5d43be0c 3015 struct amdgpu_device *adev;
e7b07cee 3016 struct amdgpu_bo *rbo;
56087b31 3017 uint64_t chroma_addr = 0;
e7b07cee
HW		 3018 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3019 unsigned int awidth;
5d43be0c
CK		 3020 uint32_t domain;
3021 int r;
e7b07cee
HW		 3022
3023 dm_plane_state_old = to_dm_plane_state(plane->state);
3024 dm_plane_state_new = to_dm_plane_state(new_state);
3025
3026 if (!new_state->fb) {
f1ad2f5e 3027 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3028 return 0;
3029 }
3030
3031 afb = to_amdgpu_framebuffer(new_state->fb);
3032
3033 obj = afb->obj;
3034 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3035 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3036 r = amdgpu_bo_reserve(rbo, false);
3037 if (unlikely(r != 0))
3038 return r;
3039
5d43be0c
CK		 3040 if (plane->type != DRM_PLANE_TYPE_CURSOR)
3041 domain = amdgpu_display_framebuffer_domains(adev);
3042 else
3043 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3044
5d43be0c 3045 r = amdgpu_bo_pin(rbo, domain, &afb->address);
e7b07cee
HW		 3046
3047 amdgpu_bo_unreserve(rbo);
3048
3049 if (unlikely(r != 0)) {
30b7c614
HW		 3050 if (r != -ERESTARTSYS)
3051 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
e7b07cee
HW		 3052 return r;
3053 }
3054
3055 amdgpu_bo_ref(rbo);
3056
3be5262e
HW		 3057 if (dm_plane_state_new->dc_state &&
3058 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3059 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3060
3be5262e
HW		 3061 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3062 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3063 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 3064 } else {
3065 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3066 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3067 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3068 = lower_32_bits(afb->address);
56087b31
S		 3069 plane_state->address.video_progressive.luma_addr.high_part
3070 = upper_32_bits(afb->address);
35888630 3071 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3072 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3073 = lower_32_bits(chroma_addr);
3074 plane_state->address.video_progressive.chroma_addr.high_part
3075 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3076 }
3077 }
3078
3079 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
3080 * prepare and cleanup in drm_atomic_helper_prepare_planes
3081 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
3082 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
3083 * code touching fram buffers should be avoided for DC.
3084 */
3085 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3086 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
3087
3088 acrtc->cursor_bo = obj;
3089 }
3090 return 0;
3091}
3092
3ee6b26b
AD		 3093static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3094 struct drm_plane_state *old_state)
e7b07cee
HW		 3095{
3096 struct amdgpu_bo *rbo;
3097 struct amdgpu_framebuffer *afb;
3098 int r;
3099
3100 if (!old_state->fb)
3101 return;
3102
3103 afb = to_amdgpu_framebuffer(old_state->fb);
3104 rbo = gem_to_amdgpu_bo(afb->obj);
3105 r = amdgpu_bo_reserve(rbo, false);
3106 if (unlikely(r)) {
3107 DRM_ERROR("failed to reserve rbo before unpin\n");
3108 return;
b830ebc9
HW		 3109 }
3110
3111 amdgpu_bo_unpin(rbo);
3112 amdgpu_bo_unreserve(rbo);
3113 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3114}
3115
7578ecda
AD		 3116static int dm_plane_atomic_check(struct drm_plane *plane,
3117 struct drm_plane_state *state)
cbd19488
AG		 3118{
3119 struct amdgpu_device *adev = plane->dev->dev_private;
3120 struct dc *dc = adev->dm.dc;
3121 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3122
3be5262e 3123 if (!dm_plane_state->dc_state)
9a3329b1 3124 return 0;
cbd19488 3125
a05bcff1
S		 3126 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3127 return -EINVAL;
3128
62c933f9 3129 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3130 return 0;
3131
3132 return -EINVAL;
3133}
3134
e7b07cee
HW		 3135static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3136 .prepare_fb = dm_plane_helper_prepare_fb,
3137 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3138 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3139};
3140
3141/*
3142 * TODO: these are currently initialized to rgb formats only.
3143 * For future use cases we should either initialize them dynamically based on
3144 * plane capabilities, or initialize this array to all formats, so internal drm
3145 * check will succeed, and let DC to implement proper check
3146 */
d90371b0 3147static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3148 DRM_FORMAT_RGB888,
3149 DRM_FORMAT_XRGB8888,
3150 DRM_FORMAT_ARGB8888,
3151 DRM_FORMAT_RGBA8888,
3152 DRM_FORMAT_XRGB2101010,
3153 DRM_FORMAT_XBGR2101010,
3154 DRM_FORMAT_ARGB2101010,
3155 DRM_FORMAT_ABGR2101010,
3156};
3157
99d1abf8 3158static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3159 DRM_FORMAT_NV12,
3160 DRM_FORMAT_NV21,
3161};
3162
3163static const u32 cursor_formats[] = {
3164 DRM_FORMAT_ARGB8888
3165};
3166
7578ecda
AD		 3167static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3168 struct amdgpu_plane *aplane,
3169 unsigned long possible_crtcs)
e7b07cee
HW		 3170{
3171 int res = -EPERM;
3172
3173 switch (aplane->base.type) {
3174 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3175 res = drm_universal_plane_init(
3176 dm->adev->ddev,
3177 &aplane->base,
3178 possible_crtcs,
3179 &dm_plane_funcs,
3180 rgb_formats,
3181 ARRAY_SIZE(rgb_formats),
3182 NULL, aplane->base.type, NULL);
3183 break;
3184 case DRM_PLANE_TYPE_OVERLAY:
3185 res = drm_universal_plane_init(
3186 dm->adev->ddev,
3187 &aplane->base,
3188 possible_crtcs,
3189 &dm_plane_funcs,
3190 yuv_formats,
3191 ARRAY_SIZE(yuv_formats),
3192 NULL, aplane->base.type, NULL);
3193 break;
3194 case DRM_PLANE_TYPE_CURSOR:
3195 res = drm_universal_plane_init(
3196 dm->adev->ddev,
3197 &aplane->base,
3198 possible_crtcs,
3199 &dm_plane_funcs,
3200 cursor_formats,
3201 ARRAY_SIZE(cursor_formats),
3202 NULL, aplane->base.type, NULL);
3203 break;
3204 }
3205
3206 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3207
96719c54
HW		 3208 /* Create (reset) the plane state */
3209 if (aplane->base.funcs->reset)
3210 aplane->base.funcs->reset(&aplane->base);
3211
3212
e7b07cee
HW		 3213 return res;
3214}
3215
7578ecda
AD		 3216static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3217 struct drm_plane *plane,
3218 uint32_t crtc_index)
e7b07cee
HW		 3219{
3220 struct amdgpu_crtc *acrtc = NULL;
3221 struct amdgpu_plane *cursor_plane;
3222
3223 int res = -ENOMEM;
3224
3225 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3226 if (!cursor_plane)
3227 goto fail;
3228
3229 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3230 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3231
3232 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3233 if (!acrtc)
3234 goto fail;
3235
3236 res = drm_crtc_init_with_planes(
3237 dm->ddev,
3238 &acrtc->base,
3239 plane,
3240 &cursor_plane->base,
3241 &amdgpu_dm_crtc_funcs, NULL);
3242
3243 if (res)
3244 goto fail;
3245
3246 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3247
96719c54
HW		 3248 /* Create (reset) the plane state */
3249 if (acrtc->base.funcs->reset)
3250 acrtc->base.funcs->reset(&acrtc->base);
3251
e7b07cee
HW		 3252 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3253 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3254
3255 acrtc->crtc_id = crtc_index;
3256 acrtc->base.enabled = false;
3257
3258 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3259 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3260 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3261 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3262
3263 return 0;
3264
3265fail:
b830ebc9
HW		 3266 kfree(acrtc);
3267 kfree(cursor_plane);
e7b07cee
HW		 3268 return res;
3269}
3270
3271
3272static int to_drm_connector_type(enum signal_type st)
3273{
3274 switch (st) {
3275 case SIGNAL_TYPE_HDMI_TYPE_A:
3276 return DRM_MODE_CONNECTOR_HDMIA;
3277 case SIGNAL_TYPE_EDP:
3278 return DRM_MODE_CONNECTOR_eDP;
3279 case SIGNAL_TYPE_RGB:
3280 return DRM_MODE_CONNECTOR_VGA;
3281 case SIGNAL_TYPE_DISPLAY_PORT:
3282 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3283 return DRM_MODE_CONNECTOR_DisplayPort;
3284 case SIGNAL_TYPE_DVI_DUAL_LINK:
3285 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3286 return DRM_MODE_CONNECTOR_DVID;
3287 case SIGNAL_TYPE_VIRTUAL:
3288 return DRM_MODE_CONNECTOR_VIRTUAL;
3289
3290 default:
3291 return DRM_MODE_CONNECTOR_Unknown;
3292 }
3293}
3294
3295static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3296{
3297 const struct drm_connector_helper_funcs *helper =
3298 connector->helper_private;
3299 struct drm_encoder *encoder;
3300 struct amdgpu_encoder *amdgpu_encoder;
3301
3302 encoder = helper->best_encoder(connector);
3303
3304 if (encoder == NULL)
3305 return;
3306
3307 amdgpu_encoder = to_amdgpu_encoder(encoder);
3308
3309 amdgpu_encoder->native_mode.clock = 0;
3310
3311 if (!list_empty(&connector->probed_modes)) {
3312 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3313
e7b07cee 3314 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3315 &connector->probed_modes,
3316 head) {
3317 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3318 amdgpu_encoder->native_mode = *preferred_mode;
3319
e7b07cee
HW		 3320 break;
3321 }
3322
3323 }
3324}
3325
3ee6b26b
AD		 3326static struct drm_display_mode *
3327amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3328 char *name,
3329 int hdisplay, int vdisplay)
e7b07cee
HW		 3330{
3331 struct drm_device *dev = encoder->dev;
3332 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3333 struct drm_display_mode *mode = NULL;
3334 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3335
3336 mode = drm_mode_duplicate(dev, native_mode);
3337
b830ebc9 3338 if (mode == NULL)
e7b07cee
HW		 3339 return NULL;
3340
3341 mode->hdisplay = hdisplay;
3342 mode->vdisplay = vdisplay;
3343 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3344 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3345
3346 return mode;
3347
3348}
3349
3350static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3351 struct drm_connector *connector)
e7b07cee
HW		 3352{
3353 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3354 struct drm_display_mode *mode = NULL;
3355 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3356 struct amdgpu_dm_connector *amdgpu_dm_connector =
3357 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3358 int i;
3359 int n;
3360 struct mode_size {
3361 char name[DRM_DISPLAY_MODE_LEN];
3362 int w;
3363 int h;
b830ebc9 3364 } common_modes[] = {
e7b07cee
HW		 3365 { "640x480", 640, 480},
3366 { "800x600", 800, 600},
3367 { "1024x768", 1024, 768},
3368 { "1280x720", 1280, 720},
3369 { "1280x800", 1280, 800},
3370 {"1280x1024", 1280, 1024},
3371 { "1440x900", 1440, 900},
3372 {"1680x1050", 1680, 1050},
3373 {"1600x1200", 1600, 1200},
3374 {"1920x1080", 1920, 1080},
3375 {"1920x1200", 1920, 1200}
3376 };
3377
b830ebc9 3378 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3379
3380 for (i = 0; i < n; i++) {
3381 struct drm_display_mode *curmode = NULL;
3382 bool mode_existed = false;
3383
3384 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3385 common_modes[i].h > native_mode->vdisplay ||
3386 (common_modes[i].w == native_mode->hdisplay &&
3387 common_modes[i].h == native_mode->vdisplay))
3388 continue;
e7b07cee
HW		 3389
3390 list_for_each_entry(curmode, &connector->probed_modes, head) {
3391 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3392 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3393 mode_existed = true;
3394 break;
3395 }
3396 }
3397
3398 if (mode_existed)
3399 continue;
3400
3401 mode = amdgpu_dm_create_common_mode(encoder,
3402 common_modes[i].name, common_modes[i].w,
3403 common_modes[i].h);
3404 drm_mode_probed_add(connector, mode);
c84dec2f 3405 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3406 }
3407}
3408
3ee6b26b
AD		 3409static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3410 struct edid *edid)
e7b07cee 3411{
c84dec2f
HW		 3412 struct amdgpu_dm_connector *amdgpu_dm_connector =
3413 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3414
3415 if (edid) {
3416 /* empty probed_modes */
3417 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3418 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3419 drm_add_edid_modes(connector, edid);
3420
e7b07cee 3421 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3422 } else {
c84dec2f 3423 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3424 }
e7b07cee
HW		 3425}
3426
7578ecda 3427static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3428{
3429 const struct drm_connector_helper_funcs *helper =
3430 connector->helper_private;
c84dec2f
HW		 3431 struct amdgpu_dm_connector *amdgpu_dm_connector =
3432 to_amdgpu_dm_connector(connector);
e7b07cee 3433 struct drm_encoder *encoder;
c84dec2f 3434 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3435
3436 encoder = helper->best_encoder(connector);
e7b07cee
HW		 3437 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3438 amdgpu_dm_connector_add_common_modes(encoder, connector);
3e332d3a
RL		 3439
3440#if defined(CONFIG_DRM_AMD_DC_FBC)
3441 amdgpu_dm_fbc_init(connector);
3442#endif
c84dec2f 3443 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3444}
3445
3ee6b26b
AD		 3446void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3447 struct amdgpu_dm_connector *aconnector,
3448 int connector_type,
3449 struct dc_link *link,
3450 int link_index)
e7b07cee
HW		 3451{
3452 struct amdgpu_device *adev = dm->ddev->dev_private;
3453
3454 aconnector->connector_id = link_index;
3455 aconnector->dc_link = link;
3456 aconnector->base.interlace_allowed = false;
3457 aconnector->base.doublescan_allowed = false;
3458 aconnector->base.stereo_allowed = false;
3459 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3460 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3461
3462 mutex_init(&aconnector->hpd_lock);
3463
b830ebc9
HW		 3464 /* configure support HPD hot plug connector_>polled default value is 0
3465 * which means HPD hot plug not supported
3466 */
e7b07cee
HW		 3467 switch (connector_type) {
3468 case DRM_MODE_CONNECTOR_HDMIA:
3469 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3470 break;
3471 case DRM_MODE_CONNECTOR_DisplayPort:
3472 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3473 break;
3474 case DRM_MODE_CONNECTOR_DVID:
3475 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3476 break;
3477 default:
3478 break;
3479 }
3480
3481 drm_object_attach_property(&aconnector->base.base,
3482 dm->ddev->mode_config.scaling_mode_property,
3483 DRM_MODE_SCALE_NONE);
3484
3485 drm_object_attach_property(&aconnector->base.base,
3486 adev->mode_info.underscan_property,
3487 UNDERSCAN_OFF);
3488 drm_object_attach_property(&aconnector->base.base,
3489 adev->mode_info.underscan_hborder_property,
3490 0);
3491 drm_object_attach_property(&aconnector->base.base,
3492 adev->mode_info.underscan_vborder_property,
3493 0);
3494
3495}
3496
7578ecda
AD		 3497static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3498 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3499{
3500 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3501 struct ddc_service *ddc_service = i2c->ddc_service;
3502 struct i2c_command cmd;
3503 int i;
3504 int result = -EIO;
3505
b830ebc9 3506 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3507
3508 if (!cmd.payloads)
3509 return result;
3510
3511 cmd.number_of_payloads = num;
3512 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3513 cmd.speed = 100;
3514
3515 for (i = 0; i < num; i++) {
3516 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3517 cmd.payloads[i].address = msgs[i].addr;
3518 cmd.payloads[i].length = msgs[i].len;
3519 cmd.payloads[i].data = msgs[i].buf;
3520 }
3521
3522 if (dal_i2caux_submit_i2c_command(
3523 ddc_service->ctx->i2caux,
3524 ddc_service->ddc_pin,
3525 &cmd))
3526 result = num;
3527
3528 kfree(cmd.payloads);
3529 return result;
3530}
3531
7578ecda 3532static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3533{
3534 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3535}
3536
3537static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3538 .master_xfer = amdgpu_dm_i2c_xfer,
3539 .functionality = amdgpu_dm_i2c_func,
3540};
3541
3ee6b26b
AD		 3542static struct amdgpu_i2c_adapter *
3543create_i2c(struct ddc_service *ddc_service,
3544 int link_index,
3545 int *res)
e7b07cee
HW		 3546{
3547 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3548 struct amdgpu_i2c_adapter *i2c;
3549
b830ebc9 3550 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 3551 if (!i2c)
3552 return NULL;
e7b07cee
HW		 3553 i2c->base.owner = THIS_MODULE;
3554 i2c->base.class = I2C_CLASS_DDC;
3555 i2c->base.dev.parent = &adev->pdev->dev;
3556 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3557 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3558 i2c_set_adapdata(&i2c->base, i2c);
3559 i2c->ddc_service = ddc_service;
3560
3561 return i2c;
3562}
3563
3564/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3565 * dc_link which will be represented by this aconnector.
3566 */
7578ecda
AD		 3567static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3568 struct amdgpu_dm_connector *aconnector,
3569 uint32_t link_index,
3570 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3571{
3572 int res = 0;
3573 int connector_type;
3574 struct dc *dc = dm->dc;
3575 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3576 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 3577
3578 link->priv = aconnector;
e7b07cee 3579
f1ad2f5e 3580 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3581
3582 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 3583 if (!i2c) {
3584 DRM_ERROR("Failed to create i2c adapter data\n");
3585 return -ENOMEM;
3586 }
3587
e7b07cee
HW		 3588 aconnector->i2c = i2c;
3589 res = i2c_add_adapter(&i2c->base);
3590
3591 if (res) {
3592 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3593 goto out_free;
3594 }
3595
3596 connector_type = to_drm_connector_type(link->connector_signal);
3597
3598 res = drm_connector_init(
3599 dm->ddev,
3600 &aconnector->base,
3601 &amdgpu_dm_connector_funcs,
3602 connector_type);
3603
3604 if (res) {
3605 DRM_ERROR("connector_init failed\n");
3606 aconnector->connector_id = -1;
3607 goto out_free;
3608 }
3609
3610 drm_connector_helper_add(
3611 &aconnector->base,
3612 &amdgpu_dm_connector_helper_funcs);
3613
96719c54
HW		 3614 if (aconnector->base.funcs->reset)
3615 aconnector->base.funcs->reset(&aconnector->base);
3616
e7b07cee
HW		 3617 amdgpu_dm_connector_init_helper(
3618 dm,
3619 aconnector,
3620 connector_type,
3621 link,
3622 link_index);
3623
3624 drm_mode_connector_attach_encoder(
3625 &aconnector->base, &aencoder->base);
3626
3627 drm_connector_register(&aconnector->base);
3628
3629 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3630 || connector_type == DRM_MODE_CONNECTOR_eDP)
3631 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3632
3633#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3634 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3635
3636 /* NOTE: this currently will create backlight device even if a panel
3637 * is not connected to the eDP/LVDS connector.
3638 *
3639 * This is less than ideal but we don't have sink information at this
3640 * stage since detection happens after. We can't do detection earlier
3641 * since MST detection needs connectors to be created first.
3642 */
3643 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3644 /* Event if registration failed, we should continue with
3645 * DM initialization because not having a backlight control
b830ebc9
HW		 3646 * is better then a black screen.
3647 */
e7b07cee
HW		 3648 amdgpu_dm_register_backlight_device(dm);
3649
3650 if (dm->backlight_dev)
3651 dm->backlight_link = link;
3652 }
3653#endif
3654
3655out_free:
3656 if (res) {
3657 kfree(i2c);
3658 aconnector->i2c = NULL;
3659 }
3660 return res;
3661}
3662
3663int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3664{
3665 switch (adev->mode_info.num_crtc) {
3666 case 1:
3667 return 0x1;
3668 case 2:
3669 return 0x3;
3670 case 3:
3671 return 0x7;
3672 case 4:
3673 return 0xf;
3674 case 5:
3675 return 0x1f;
3676 case 6:
3677 default:
3678 return 0x3f;
3679 }
3680}
3681
7578ecda
AD		 3682static int amdgpu_dm_encoder_init(struct drm_device *dev,
3683 struct amdgpu_encoder *aencoder,
3684 uint32_t link_index)
e7b07cee
HW		 3685{
3686 struct amdgpu_device *adev = dev->dev_private;
3687
3688 int res = drm_encoder_init(dev,
3689 &aencoder->base,
3690 &amdgpu_dm_encoder_funcs,
3691 DRM_MODE_ENCODER_TMDS,
3692 NULL);
3693
3694 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3695
3696 if (!res)
3697 aencoder->encoder_id = link_index;
3698 else
3699 aencoder->encoder_id = -1;
3700
3701 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3702
3703 return res;
3704}
3705
3ee6b26b
AD		 3706static void manage_dm_interrupts(struct amdgpu_device *adev,
3707 struct amdgpu_crtc *acrtc,
3708 bool enable)
e7b07cee
HW		 3709{
3710 /*
3711 * this is not correct translation but will work as soon as VBLANK
3712 * constant is the same as PFLIP
3713 */
3714 int irq_type =
734dd01d 3715 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 3716 adev,
3717 acrtc->crtc_id);
3718
3719 if (enable) {
3720 drm_crtc_vblank_on(&acrtc->base);
3721 amdgpu_irq_get(
3722 adev,
3723 &adev->pageflip_irq,
3724 irq_type);
3725 } else {
3726
3727 amdgpu_irq_put(
3728 adev,
3729 &adev->pageflip_irq,
3730 irq_type);
3731 drm_crtc_vblank_off(&acrtc->base);
3732 }
3733}
3734
3ee6b26b
AD		 3735static bool
3736is_scaling_state_different(const struct dm_connector_state *dm_state,
3737 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3738{
3739 if (dm_state->scaling != old_dm_state->scaling)
3740 return true;
3741 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3742 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3743 return true;
3744 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3745 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3746 return true;
b830ebc9
HW		 3747 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3748 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3749 return true;
e7b07cee
HW		 3750 return false;
3751}
3752
3ee6b26b
AD		 3753static void remove_stream(struct amdgpu_device *adev,
3754 struct amdgpu_crtc *acrtc,
3755 struct dc_stream_state *stream)
e7b07cee
HW		 3756{
3757 /* this is the update mode case */
3758 if (adev->dm.freesync_module)
3759 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3760
3761 acrtc->otg_inst = -1;
3762 acrtc->enabled = false;
3763}
3764
7578ecda
AD		 3765static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3766 struct dc_cursor_position *position)
2a8f6ccb
HW		 3767{
3768 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3769 int x, y;
3770 int xorigin = 0, yorigin = 0;
3771
3772 if (!crtc || !plane->state->fb) {
3773 position->enable = false;
3774 position->x = 0;
3775 position->y = 0;
3776 return 0;
3777 }
3778
3779 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3780 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3781 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3782 __func__,
3783 plane->state->crtc_w,
3784 plane->state->crtc_h);
3785 return -EINVAL;
3786 }
3787
3788 x = plane->state->crtc_x;
3789 y = plane->state->crtc_y;
3790 /* avivo cursor are offset into the total surface */
3791 x += crtc->primary->state->src_x >> 16;
3792 y += crtc->primary->state->src_y >> 16;
3793 if (x < 0) {
3794 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3795 x = 0;
3796 }
3797 if (y < 0) {
3798 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3799 y = 0;
3800 }
3801 position->enable = true;
3802 position->x = x;
3803 position->y = y;
3804 position->x_hotspot = xorigin;
3805 position->y_hotspot = yorigin;
3806
3807 return 0;
3808}
3809
3ee6b26b
AD		 3810static void handle_cursor_update(struct drm_plane *plane,
3811 struct drm_plane_state *old_plane_state)
e7b07cee 3812{
2a8f6ccb
HW		 3813 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3814 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3815 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3816 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3817 uint64_t address = afb ? afb->address : 0;
3818 struct dc_cursor_position position;
3819 struct dc_cursor_attributes attributes;
3820 int ret;
3821
e7b07cee
HW		 3822 if (!plane->state->fb && !old_plane_state->fb)
3823 return;
3824
f1ad2f5e 3825 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3826 __func__,
3827 amdgpu_crtc->crtc_id,
3828 plane->state->crtc_w,
3829 plane->state->crtc_h);
2a8f6ccb
HW		 3830
3831 ret = get_cursor_position(plane, crtc, &position);
3832 if (ret)
3833 return;
3834
3835 if (!position.enable) {
3836 /* turn off cursor */
3837 if (crtc_state && crtc_state->stream)
3838 dc_stream_set_cursor_position(crtc_state->stream,
3839 &position);
3840 return;
e7b07cee 3841 }
e7b07cee 3842
2a8f6ccb
HW		 3843 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3844 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3845
3846 attributes.address.high_part = upper_32_bits(address);
3847 attributes.address.low_part = lower_32_bits(address);
3848 attributes.width = plane->state->crtc_w;
3849 attributes.height = plane->state->crtc_h;
3850 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3851 attributes.rotation_angle = 0;
3852 attributes.attribute_flags.value = 0;
3853
3854 attributes.pitch = attributes.width;
3855
886daac9
JZ		 3856 if (crtc_state->stream) {
3857 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3858 &attributes))
3859 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3860
2a8f6ccb
HW		 3861 if (!dc_stream_set_cursor_position(crtc_state->stream,
3862 &position))
3863 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3864 }
2a8f6ccb 3865}
e7b07cee
HW		 3866
3867static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3868{
3869
3870 assert_spin_locked(&acrtc->base.dev->event_lock);
3871 WARN_ON(acrtc->event);
3872
3873 acrtc->event = acrtc->base.state->event;
3874
3875 /* Set the flip status */
3876 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3877
3878 /* Mark this event as consumed */
3879 acrtc->base.state->event = NULL;
3880
3881 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3882 acrtc->crtc_id);
3883}
3884
3885/*
3886 * Executes flip
3887 *
3888 * Waits on all BO's fences and for proper vblank count
3889 */
3ee6b26b
AD		 3890static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3891 struct drm_framebuffer *fb,
bc6828e0
BL		 3892 uint32_t target,
3893 struct dc_state *state)
e7b07cee
HW		 3894{
3895 unsigned long flags;
3896 uint32_t target_vblank;
3897 int r, vpos, hpos;
3898 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3899 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3900 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3901 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3902 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3903 struct dc_flip_addrs addr = { {0} };
3be5262e 3904 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3905 struct dc_surface_update surface_updates[1] = { {0} };
3906 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3907
3908
3909 /* Prepare wait for target vblank early - before the fence-waits */
23effc11 3910 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
e7b07cee
HW		 3911 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3912
b830ebc9 3913 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3914 * explicitly on fences instead
3915 * and in general should be called for
3916 * blocking commit to as per framework helpers
b830ebc9 3917 */
e7b07cee
HW		 3918 r = amdgpu_bo_reserve(abo, true);
3919 if (unlikely(r != 0)) {
3920 DRM_ERROR("failed to reserve buffer before flip\n");
3921 WARN_ON(1);
3922 }
3923
3924 /* Wait for all fences on this FB */
3925 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3926 MAX_SCHEDULE_TIMEOUT) < 0);
3927
3928 amdgpu_bo_unreserve(abo);
3929
3930 /* Wait until we're out of the vertical blank period before the one
3931 * targeted by the flip
3932 */
3933 while ((acrtc->enabled &&
aa8e286a
SL		 3934 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
3935 0, &vpos, &hpos, NULL,
3936 NULL, &crtc->hwmode)
e7b07cee
HW		 3937 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3938 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3939 (int)(target_vblank -
3940 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3941 usleep_range(1000, 1100);
3942 }
3943
3944 /* Flip */
3945 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3946 /* update crtc fb */
3947 crtc->primary->fb = fb;
3948
3949 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3950 WARN_ON(!acrtc_state->stream);
3951
3952 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3953 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3954 addr.flip_immediate = async_flip;
3955
3956
3957 if (acrtc->base.state->event)
3958 prepare_flip_isr(acrtc);
3959
3be5262e 3960 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3961 surface_updates->flip_addr = &addr;
3962
3963
bc6828e0
BL		 3964 dc_commit_updates_for_stream(adev->dm.dc,
3965 surface_updates,
3966 1,
3967 acrtc_state->stream,
3968 NULL,
3969 &surface_updates->surface,
3970 state);
e7b07cee
HW		 3971
3972 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3973 __func__,
3974 addr.address.grph.addr.high_part,
3975 addr.address.grph.addr.low_part);
3976
3977
3978 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3979}
3980
3be5262e 3981static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 3982 struct drm_device *dev,
3983 struct amdgpu_display_manager *dm,
3984 struct drm_crtc *pcrtc,
3985 bool *wait_for_vblank)
e7b07cee
HW		 3986{
3987 uint32_t i;
3988 struct drm_plane *plane;
0bc9706d 3989 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 3990 struct dc_stream_state *dc_stream_attach;
3be5262e 3991 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 3992 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 3993 struct drm_crtc_state *new_pcrtc_state =
3994 drm_atomic_get_new_crtc_state(state, pcrtc);
3995 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
bc6828e0 3996 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 3997 int planes_count = 0;
3998 unsigned long flags;
3999
4000 /* update planes when needed */
0bc9706d
LSL		 4001 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4002 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 4003 struct drm_crtc_state *new_crtc_state;
0bc9706d 4004 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 4005 bool pflip_needed;
54d76575 4006 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 4007
4008 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4009 handle_cursor_update(plane, old_plane_state);
4010 continue;
4011 }
4012
f5ba60fe
DD		 4013 if (!fb || !crtc || pcrtc != crtc)
4014 continue;
4015
4016 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4017 if (!new_crtc_state->active)
e7b07cee
HW		 4018 continue;
4019
4020 pflip_needed = !state->allow_modeset;
4021
4022 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4023 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 4024 DRM_ERROR("%s: acrtc %d, already busy\n",
4025 __func__,
4026 acrtc_attach->crtc_id);
b830ebc9 4027 /* In commit tail framework this cannot happen */
e7b07cee
HW		 4028 WARN_ON(1);
4029 }
4030 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4031
4032 if (!pflip_needed) {
54d76575 4033 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 4034
54d76575 4035 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 4036
4037 dc_stream_attach = acrtc_state->stream;
4038 planes_count++;
4039
0bc9706d 4040 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 4041 /* Assume even ONE crtc with immediate flip means
4042 * entire can't wait for VBLANK
4043 * TODO Check if it's correct
4044 */
4045 *wait_for_vblank =
0bc9706d 4046 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 4047 false : true;
4048
4049 /* TODO: Needs rework for multiplane flip */
4050 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4051 drm_crtc_vblank_get(crtc);
4052
4053 amdgpu_dm_do_flip(
4054 crtc,
4055 fb,
23effc11 4056 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
bc6828e0 4057 dm_state->context);
e7b07cee
HW		 4058 }
4059
4060 }
4061
4062 if (planes_count) {
4063 unsigned long flags;
4064
0bc9706d 4065 if (new_pcrtc_state->event) {
e7b07cee
HW		 4066
4067 drm_crtc_vblank_get(pcrtc);
4068
4069 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4070 prepare_flip_isr(acrtc_attach);
4071 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4072 }
4073
3be5262e
HW		 4074 if (false == dc_commit_planes_to_stream(dm->dc,
4075 plane_states_constructed,
4076 planes_count,
bc6828e0
BL		 4077 dc_stream_attach,
4078 dm_state->context))
3be5262e 4079 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4080 } else {
4081 /*TODO BUG Here should go disable planes on CRTC. */
4082 }
4083}
4084
27b3f4fc
LSL		 4085/**
4086 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4087 * @crtc_state: the DRM CRTC state
4088 * @stream_state: the DC stream state.
4089 *
4090 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4091 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4092 */
4093static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4094 struct dc_stream_state *stream_state)
4095{
4096 stream_state->mode_changed = crtc_state->mode_changed;
4097}
e7b07cee 4098
7578ecda
AD		 4099static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4100 struct drm_atomic_state *state,
4101 bool nonblock)
e7b07cee
HW		 4102{
4103 struct drm_crtc *crtc;
c2cea706 4104 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4105 struct amdgpu_device *adev = dev->dev_private;
4106 int i;
4107
4108 /*
4109 * We evade vblanks and pflips on crtc that
4110 * should be changed. We do it here to flush & disable
4111 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4112 * it will update crtc->dm_crtc_state->stream pointer which is used in
4113 * the ISRs.
4114 */
c2cea706 4115 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4116 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 4117 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4118
54d76575 4119 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 4120 manage_dm_interrupts(adev, acrtc, false);
4121 }
fc9e9920
S		 4122 /* Add check here for SoC's that support hardware cursor plane, to
4123 * unset legacy_cursor_update */
e7b07cee
HW		 4124
4125 return drm_atomic_helper_commit(dev, state, nonblock);
4126
4127 /*TODO Handle EINTR, reenable IRQ*/
4128}
4129
7578ecda 4130static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4131{
4132 struct drm_device *dev = state->dev;
4133 struct amdgpu_device *adev = dev->dev_private;
4134 struct amdgpu_display_manager *dm = &adev->dm;
4135 struct dm_atomic_state *dm_state;
4136 uint32_t i, j;
5cc6dcbd 4137 struct drm_crtc *crtc;
0bc9706d 4138 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4139 unsigned long flags;
4140 bool wait_for_vblank = true;
4141 struct drm_connector *connector;
c2cea706 4142 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4143 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
e7b07cee
HW		 4144
4145 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4146
4147 dm_state = to_dm_atomic_state(state);
4148
4149 /* update changed items */
0bc9706d 4150 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4151 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4152
54d76575
LSL		 4153 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4154 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4155
f1ad2f5e 4156 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4157 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4158 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4159 "connectors_changed:%d\n",
4160 acrtc->crtc_id,
0bc9706d
LSL		 4161 new_crtc_state->enable,
4162 new_crtc_state->active,
4163 new_crtc_state->planes_changed,
4164 new_crtc_state->mode_changed,
4165 new_crtc_state->active_changed,
4166 new_crtc_state->connectors_changed);
e7b07cee 4167
27b3f4fc
LSL		 4168 /* Copy all transient state flags into dc state */
4169 if (dm_new_crtc_state->stream) {
4170 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4171 dm_new_crtc_state->stream);
4172 }
4173
e7b07cee
HW		 4174 /* handles headless hotplug case, updating new_state and
4175 * aconnector as needed
4176 */
4177
54d76575 4178 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4179
f1ad2f5e 4180 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4181
54d76575 4182 if (!dm_new_crtc_state->stream) {
e7b07cee 4183 /*
b830ebc9
HW		 4184 * this could happen because of issues with
4185 * userspace notifications delivery.
4186 * In this case userspace tries to set mode on
4187 * display which is disconnect in fact.
4188 * dc_sink in NULL in this case on aconnector.
4189 * We expect reset mode will come soon.
4190 *
4191 * This can also happen when unplug is done
4192 * during resume sequence ended
4193 *
4194 * In this case, we want to pretend we still
4195 * have a sink to keep the pipe running so that
4196 * hw state is consistent with the sw state
4197 */
f1ad2f5e 4198 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4199 __func__, acrtc->base.base.id);
4200 continue;
4201 }
4202
54d76575
LSL		 4203 if (dm_old_crtc_state->stream)
4204 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 4205
e7b07cee 4206 acrtc->enabled = true;
0bc9706d
LSL		 4207 acrtc->hw_mode = new_crtc_state->mode;
4208 crtc->hwmode = new_crtc_state->mode;
4209 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4210 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4211
4212 /* i.e. reset mode */
54d76575
LSL		 4213 if (dm_old_crtc_state->stream)
4214 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4215 }
4216 } /* for_each_crtc_in_state() */
4217
4218 /*
4219 * Add streams after required streams from new and replaced streams
4220 * are removed from freesync module
4221 */
4222 if (adev->dm.freesync_module) {
8b8f27f9
LSL		 4223 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4224 new_crtc_state, i) {
c84dec2f 4225 struct amdgpu_dm_connector *aconnector = NULL;
f01a2cf0
LSL		 4226 struct dm_connector_state *dm_new_con_state = NULL;
4227 struct amdgpu_crtc *acrtc = NULL;
1c77d4ee 4228 bool modeset_needed;
b830ebc9 4229
54d76575 4230 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1c77d4ee
LSL		 4231 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4232 modeset_needed = modeset_required(
4233 new_crtc_state,
4234 dm_new_crtc_state->stream,
4235 dm_old_crtc_state->stream);
4236 /* We add stream to freesync if:
4237 * 1. Said stream is not null, and
4238 * 2. A modeset is requested. This means that the
4239 * stream was removed previously, and needs to be
4240 * replaced.
4241 */
4242 if (dm_new_crtc_state->stream == NULL ||
4243 !modeset_needed)
4244 continue;
4245
f01a2cf0 4246 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4247
f01a2cf0
LSL		 4248 aconnector =
4249 amdgpu_dm_find_first_crtc_matching_connector(
4250 state, crtc);
e7b07cee 4251 if (!aconnector) {
8b8f27f9
LSL		 4252 DRM_DEBUG_DRIVER("Atomic commit: Failed to "
4253 "find connector for acrtc "
4254 "id:%d skipping freesync "
4255 "init\n",
4256 acrtc->crtc_id);
e7b07cee
HW		 4257 continue;
4258 }
4259
4260 mod_freesync_add_stream(adev->dm.freesync_module,
f01a2cf0
LSL		 4261 dm_new_crtc_state->stream,
4262 &aconnector->caps);
4263 new_con_state = drm_atomic_get_new_connector_state(
4264 state, &aconnector->base);
4265 dm_new_con_state = to_dm_connector_state(new_con_state);
4266
1c77d4ee
LSL		 4267 mod_freesync_set_user_enable(adev->dm.freesync_module,
4268 &dm_new_crtc_state->stream,
4269 1,
4270 &dm_new_con_state->user_enable);
bfe1708c 4271 }
e7b07cee
HW		 4272 }
4273
fa2123db
ML		 4274 if (dm_state->context) {
4275 dm_enable_per_frame_crtc_master_sync(dm_state->context);
608ac7bb 4276 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
fa2123db 4277 }
e7b07cee 4278
0bc9706d 4279 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4280 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4281
54d76575 4282 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4283
54d76575 4284 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4285 const struct dc_stream_status *status =
54d76575 4286 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4287
4288 if (!status)
54d76575 4289 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4290 else
4291 acrtc->otg_inst = status->primary_otg_inst;
4292 }
4293 }
4294
ebdd27e1 4295 /* Handle scaling and underscan changes*/
c2cea706 4296 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4297 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4298 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4299 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4300 struct dc_stream_status *status = NULL;
4301
0bc9706d
LSL		 4302 if (acrtc)
4303 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4304
e7b07cee 4305 /* Skip any modesets/resets */
0bc9706d 4306 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4307 continue;
4308
4309 /* Skip any thing not scale or underscan changes */
54d76575 4310 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4311 continue;
4312
54d76575 4313 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4314
54d76575
LSL		 4315 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4316 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4317
70e8ffc5
HW		 4318 if (!dm_new_crtc_state->stream)
4319 continue;
4320
54d76575 4321 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4322 WARN_ON(!status);
3be5262e 4323 WARN_ON(!status->plane_count);
e7b07cee 4324
e7b07cee 4325 /*TODO How it works with MPO ?*/
3be5262e 4326 if (!dc_commit_planes_to_stream(
e7b07cee 4327 dm->dc,
3be5262e
HW		 4328 status->plane_states,
4329 status->plane_count,
bc6828e0
BL		 4330 dm_new_crtc_state->stream,
4331 dm_state->context))
e7b07cee
HW		 4332 dm_error("%s: Failed to update stream scaling!\n", __func__);
4333 }
4334
e1fc2dca
LSL		 4335 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4336 new_crtc_state, i) {
e7b07cee
HW		 4337 /*
4338 * loop to enable interrupts on newly arrived crtc
4339 */
e1fc2dca
LSL		 4340 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4341 bool modeset_needed;
b830ebc9 4342
54d76575 4343 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 4344 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4345 modeset_needed = modeset_required(
4346 new_crtc_state,
4347 dm_new_crtc_state->stream,
4348 dm_old_crtc_state->stream);
4349
4350 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4351 continue;
e7b07cee
HW		 4352
4353 if (adev->dm.freesync_module)
4354 mod_freesync_notify_mode_change(
e1fc2dca
LSL		 4355 adev->dm.freesync_module,
4356 &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4357
4358 manage_dm_interrupts(adev, acrtc, true);
4359 }
4360
4361 /* update planes when needed per crtc*/
5cc6dcbd 4362 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4363 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4364
54d76575 4365 if (dm_new_crtc_state->stream)
5cc6dcbd 4366 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4367 }
4368
4369
4370 /*
4371 * send vblank event on all events not handled in flip and
4372 * mark consumed event for drm_atomic_helper_commit_hw_done
4373 */
4374 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4375 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4376
0bc9706d
LSL		 4377 if (new_crtc_state->event)
4378 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4379
0bc9706d 4380 new_crtc_state->event = NULL;
e7b07cee
HW		 4381 }
4382 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4383
4384 /* Signal HW programming completion */
4385 drm_atomic_helper_commit_hw_done(state);
4386
4387 if (wait_for_vblank)
320a1274 4388 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 4389
4390 drm_atomic_helper_cleanup_planes(dev, state);
4391}
4392
4393
4394static int dm_force_atomic_commit(struct drm_connector *connector)
4395{
4396 int ret = 0;
4397 struct drm_device *ddev = connector->dev;
4398 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4399 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4400 struct drm_plane *plane = disconnected_acrtc->base.primary;
4401 struct drm_connector_state *conn_state;
4402 struct drm_crtc_state *crtc_state;
4403 struct drm_plane_state *plane_state;
4404
4405 if (!state)
4406 return -ENOMEM;
4407
4408 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4409
4410 /* Construct an atomic state to restore previous display setting */
4411
4412 /*
4413 * Attach connectors to drm_atomic_state
4414 */
4415 conn_state = drm_atomic_get_connector_state(state, connector);
4416
4417 ret = PTR_ERR_OR_ZERO(conn_state);
4418 if (ret)
4419 goto err;
4420
4421 /* Attach crtc to drm_atomic_state*/
4422 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4423
4424 ret = PTR_ERR_OR_ZERO(crtc_state);
4425 if (ret)
4426 goto err;
4427
4428 /* force a restore */
4429 crtc_state->mode_changed = true;
4430
4431 /* Attach plane to drm_atomic_state */
4432 plane_state = drm_atomic_get_plane_state(state, plane);
4433
4434 ret = PTR_ERR_OR_ZERO(plane_state);
4435 if (ret)
4436 goto err;
4437
4438
4439 /* Call commit internally with the state we just constructed */
4440 ret = drm_atomic_commit(state);
4441 if (!ret)
4442 return 0;
4443
4444err:
4445 DRM_ERROR("Restoring old state failed with %i\n", ret);
4446 drm_atomic_state_put(state);
4447
4448 return ret;
4449}
4450
4451/*
4452 * This functions handle all cases when set mode does not come upon hotplug.
4453 * This include when the same display is unplugged then plugged back into the
4454 * same port and when we are running without usermode desktop manager supprot
4455 */
3ee6b26b
AD		 4456void dm_restore_drm_connector_state(struct drm_device *dev,
4457 struct drm_connector *connector)
e7b07cee 4458{
c84dec2f 4459 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4460 struct amdgpu_crtc *disconnected_acrtc;
4461 struct dm_crtc_state *acrtc_state;
4462
4463 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4464 return;
4465
4466 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 4467 if (!disconnected_acrtc)
4468 return;
e7b07cee 4469
70e8ffc5
HW		 4470 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4471 if (!acrtc_state->stream)
e7b07cee
HW		 4472 return;
4473
4474 /*
4475 * If the previous sink is not released and different from the current,
4476 * we deduce we are in a state where we can not rely on usermode call
4477 * to turn on the display, so we do it here
4478 */
4479 if (acrtc_state->stream->sink != aconnector->dc_sink)
4480 dm_force_atomic_commit(&aconnector->base);
4481}
4482
e7b07cee
HW		 4483/*`
4484 * Grabs all modesetting locks to serialize against any blocking commits,
4485 * Waits for completion of all non blocking commits.
4486 */
3ee6b26b
AD		 4487static int do_aquire_global_lock(struct drm_device *dev,
4488 struct drm_atomic_state *state)
e7b07cee
HW		 4489{
4490 struct drm_crtc *crtc;
4491 struct drm_crtc_commit *commit;
4492 long ret;
4493
4494 /* Adding all modeset locks to aquire_ctx will
4495 * ensure that when the framework release it the
4496 * extra locks we are locking here will get released to
4497 */
4498 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4499 if (ret)
4500 return ret;
4501
4502 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4503 spin_lock(&crtc->commit_lock);
4504 commit = list_first_entry_or_null(&crtc->commit_list,
4505 struct drm_crtc_commit, commit_entry);
4506 if (commit)
4507 drm_crtc_commit_get(commit);
4508 spin_unlock(&crtc->commit_lock);
4509
4510 if (!commit)
4511 continue;
4512
4513 /* Make sure all pending HW programming completed and
4514 * page flips done
4515 */
4516 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4517
4518 if (ret > 0)
4519 ret = wait_for_completion_interruptible_timeout(
4520 &commit->flip_done, 10*HZ);
4521
4522 if (ret == 0)
4523 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4524 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4525
4526 drm_crtc_commit_put(commit);
4527 }
4528
4529 return ret < 0 ? ret : 0;
4530}
4531
3ee6b26b
AD		 4532static int dm_update_crtcs_state(struct dc *dc,
4533 struct drm_atomic_state *state,
4534 bool enable,
4535 bool *lock_and_validation_needed)
e7b07cee 4536{
e7b07cee 4537 struct drm_crtc *crtc;
c2cea706 4538 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4539 int i;
54d76575 4540 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4541 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4542 struct dc_stream_state *new_stream;
62f55537 4543 int ret = 0;
d4d4a645 4544
62f55537
AG		 4545 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4546 /* update changed items */
c2cea706 4547 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4548 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4549 struct amdgpu_dm_connector *aconnector = NULL;
c2cea706 4550 struct drm_connector_state *new_con_state = NULL;
62f55537 4551 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4552
9635b754
DS		 4553 new_stream = NULL;
4554
54d76575
LSL		 4555 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4556 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4557 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4558
1daf8c63 4559 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4560
62f55537 4561 /* TODO This hack should go away */
f4ac176e
JZ		 4562 if (aconnector && enable) {
4563 // Make sure fake sink is created in plug-in scenario
c2cea706
LSL		 4564 new_con_state = drm_atomic_get_connector_state(state,
4565 &aconnector->base);
19f89e23 4566
c2cea706
LSL		 4567 if (IS_ERR(new_con_state)) {
4568 ret = PTR_ERR_OR_ZERO(new_con_state);
62f55537
AG		 4569 break;
4570 }
19f89e23 4571
c2cea706 4572 dm_conn_state = to_dm_connector_state(new_con_state);
19f89e23 4573
62f55537 4574 new_stream = create_stream_for_sink(aconnector,
c2cea706 4575 &new_crtc_state->mode,
62f55537 4576 dm_conn_state);
19f89e23 4577
62f55537
AG		 4578 /*
4579 * we can have no stream on ACTION_SET if a display
4580 * was disconnected during S3, in this case it not and
4581 * error, the OS will be updated after detection, and
4582 * do the right thing on next atomic commit
4583 */
19f89e23 4584
62f55537 4585 if (!new_stream) {
f1ad2f5e 4586 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4587 __func__, acrtc->base.base.id);
4588 break;
19f89e23 4589 }
e7b07cee 4590
a97599a4
LSL		 4591 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4592 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4593 new_crtc_state->mode_changed = false;
4594 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4595 new_crtc_state->mode_changed);
4596 }
62f55537 4597 }
b830ebc9 4598
c2cea706 4599 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4600 goto next_crtc;
e7b07cee 4601
f1ad2f5e 4602 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4603 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4604 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4605 "connectors_changed:%d\n",
4606 acrtc->crtc_id,
c2cea706
LSL		 4607 new_crtc_state->enable,
4608 new_crtc_state->active,
4609 new_crtc_state->planes_changed,
4610 new_crtc_state->mode_changed,
4611 new_crtc_state->active_changed,
4612 new_crtc_state->connectors_changed);
e7b07cee 4613
62f55537
AG		 4614 /* Remove stream for any changed/disabled CRTC */
4615 if (!enable) {
4616
54d76575 4617 if (!dm_old_crtc_state->stream)
9635b754 4618 goto next_crtc;
62f55537 4619
f1ad2f5e 4620 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4621 crtc->base.id);
e7b07cee 4622
1dc90497 4623 /* i.e. reset mode */
62c933f9 4624 if (dc_remove_stream_from_ctx(
62f55537
AG		 4625 dc,
4626 dm_state->context,
62c933f9 4627 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4628 ret = -EINVAL;
9635b754 4629 goto fail;
62f55537
AG		 4630 }
4631
54d76575
LSL		 4632 dc_stream_release(dm_old_crtc_state->stream);
4633 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4634
4635 *lock_and_validation_needed = true;
4636
4637 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4638 /*
4639 * Quick fix to prevent NULL pointer on new_stream when
4640 * added MST connectors not found in existing crtc_state in the chained mode
4641 * TODO: need to dig out the root cause of that
4642 */
4643 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4644 goto next_crtc;
62f55537 4645
c2cea706 4646 if (modereset_required(new_crtc_state))
9635b754 4647 goto next_crtc;
62f55537 4648
c2cea706 4649 if (modeset_required(new_crtc_state, new_stream,
54d76575 4650 dm_old_crtc_state->stream)) {
62f55537 4651
54d76575 4652 WARN_ON(dm_new_crtc_state->stream);
62f55537 4653
54d76575 4654 dm_new_crtc_state->stream = new_stream;
27b3f4fc 4655
62f55537
AG		 4656 dc_stream_retain(new_stream);
4657
f1ad2f5e 4658 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4659 crtc->base.id);
1dc90497 4660
13ab1b44 4661 if (dc_add_stream_to_ctx(
1dc90497
AG		 4662 dc,
4663 dm_state->context,
13ab1b44 4664 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4665 ret = -EINVAL;
9635b754 4666 goto fail;
1dc90497
AG		 4667 }
4668
62f55537 4669 *lock_and_validation_needed = true;
9b690ef3 4670 }
62f55537 4671 }
9b690ef3 4672
9635b754 4673next_crtc:
62f55537
AG		 4674 /* Release extra reference */
4675 if (new_stream)
4676 dc_stream_release(new_stream);
e277adc5
LSL		 4677
4678 /*
4679 * We want to do dc stream updates that do not require a
4680 * full modeset below.
4681 */
4682 if (!enable || !aconnector || modereset_required(new_crtc_state))
4683 continue;
4684 /*
4685 * Given above conditions, the dc state cannot be NULL because:
4686 * 1. We're attempting to enable a CRTC. Which has a...
4687 * 2. Valid connector attached, and
4688 * 3. User does not want to reset it (disable or mark inactive,
4689 * which can happen on a CRTC that's already disabled).
4690 * => It currently exists.
4691 */
4692 BUG_ON(dm_new_crtc_state->stream == NULL);
4693
4694 /* Color managment settings */
4695 if (dm_new_crtc_state->base.color_mgmt_changed) {
4696 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
4697 if (ret)
4698 goto fail;
4699 amdgpu_dm_set_ctm(dm_new_crtc_state);
4700 }
62f55537 4701 }
e7b07cee 4702
62f55537 4703 return ret;
9635b754
DS		 4704
4705fail:
4706 if (new_stream)
4707 dc_stream_release(new_stream);
4708 return ret;
62f55537 4709}
9b690ef3 4710
3ee6b26b
AD		 4711static int dm_update_planes_state(struct dc *dc,
4712 struct drm_atomic_state *state,
4713 bool enable,
4714 bool *lock_and_validation_needed)
62f55537
AG		 4715{
4716 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4717 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4718 struct drm_plane *plane;
4719 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4720 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4721 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4722 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4723 int i ;
4724 /* TODO return page_flip_needed() function */
4725 bool pflip_needed = !state->allow_modeset;
4726 int ret = 0;
e7b07cee 4727
9b690ef3 4728
df534fff
S		 4729 /* Add new planes, in reverse order as DC expectation */
4730 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
62f55537
AG		 4731 new_plane_crtc = new_plane_state->crtc;
4732 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4733 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4734 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4735
4736 /*TODO Implement atomic check for cursor plane */
4737 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4738 continue;
9b690ef3 4739
62f55537
AG		 4740 /* Remove any changed/removed planes */
4741 if (!enable) {
c21b68c5
S		 4742 if (pflip_needed)
4743 continue;
a7b06724 4744
62f55537
AG		 4745 if (!old_plane_crtc)
4746 continue;
4747
0bc9706d
LSL		 4748 old_crtc_state = drm_atomic_get_old_crtc_state(
4749 state, old_plane_crtc);
54d76575 4750 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4751
54d76575 4752 if (!dm_old_crtc_state->stream)
62f55537
AG		 4753 continue;
4754
f1ad2f5e 4755 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4756 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4757
62f55537
AG		 4758 if (!dc_remove_plane_from_context(
4759 dc,
54d76575
LSL		 4760 dm_old_crtc_state->stream,
4761 dm_old_plane_state->dc_state,
62f55537
AG		 4762 dm_state->context)) {
4763
4764 ret = EINVAL;
4765 return ret;
e7b07cee
HW		 4766 }
4767
9b690ef3 4768
54d76575
LSL		 4769 dc_plane_state_release(dm_old_plane_state->dc_state);
4770 dm_new_plane_state->dc_state = NULL;
1dc90497 4771
62f55537 4772 *lock_and_validation_needed = true;
1dc90497 4773
62f55537 4774 } else { /* Add new planes */
8c45c5db 4775 struct dc_plane_state *dc_new_plane_state;
1dc90497 4776
62f55537
AG		 4777 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4778 continue;
e7b07cee 4779
62f55537
AG		 4780 if (!new_plane_crtc)
4781 continue;
e7b07cee 4782
62f55537 4783 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4784 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4785
54d76575 4786 if (!dm_new_crtc_state->stream)
62f55537
AG		 4787 continue;
4788
c21b68c5
S		 4789 if (pflip_needed)
4790 continue;
62f55537 4791
54d76575 4792 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4793
8c45c5db 4794 dc_new_plane_state = dc_create_plane_state(dc);
d5400aab
LSL		 4795 if (!dc_new_plane_state)
4796 return -ENOMEM;
62f55537 4797
8c45c5db
LSL		 4798 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4799 plane->base.id, new_plane_crtc->base.id);
4800
62f55537
AG		 4801 ret = fill_plane_attributes(
4802 new_plane_crtc->dev->dev_private,
8c45c5db 4803 dc_new_plane_state,
62f55537 4804 new_plane_state,
9817d5f5 4805 new_crtc_state);
8c45c5db
LSL		 4806 if (ret) {
4807 dc_plane_state_release(dc_new_plane_state);
62f55537 4808 return ret;
8c45c5db 4809 }
62f55537 4810
8c45c5db
LSL		 4811 /*
4812 * Any atomic check errors that occur after this will
4813 * not need a release. The plane state will be attached
4814 * to the stream, and therefore part of the atomic
4815 * state. It'll be released when the atomic state is
4816 * cleaned.
4817 */
62f55537
AG		 4818 if (!dc_add_plane_to_context(
4819 dc,
54d76575 4820 dm_new_crtc_state->stream,
8c45c5db 4821 dc_new_plane_state,
62f55537
AG		 4822 dm_state->context)) {
4823
8c45c5db 4824 dc_plane_state_release(dc_new_plane_state);
d5400aab 4825 return -EINVAL;
e7b07cee 4826 }
62f55537 4827
8c45c5db
LSL		 4828 dm_new_plane_state->dc_state = dc_new_plane_state;
4829
000b59ea
LSL		 4830 /* Tell DC to do a full surface update every time there
4831 * is a plane change. Inefficient, but works for now.
4832 */
4833 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
4834
62f55537 4835 *lock_and_validation_needed = true;
e7b07cee 4836 }
62f55537 4837 }
e7b07cee
HW		 4838
4839
62f55537
AG		 4840 return ret;
4841}
4842
b58f0c81
S		 4843static int dm_atomic_check_plane_state_fb(struct drm_atomic_state *state,
4844 struct drm_crtc *crtc)
4845{
4846 struct drm_plane *plane;
4847 struct drm_crtc_state *crtc_state;
4848
4849 WARN_ON(!drm_atomic_get_new_crtc_state(state, crtc));
4850
4851 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
4852 struct drm_plane_state *plane_state =
4853 drm_atomic_get_plane_state(state, plane);
4854
4855 if (IS_ERR(plane_state))
4856 return -EDEADLK;
4857
4858 crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc);
6f4969ef
S		 4859 if (IS_ERR(crtc_state))
4860 return PTR_ERR(crtc_state);
4861
b58f0c81
S		 4862 if (crtc->primary == plane && crtc_state->active) {
4863 if (!plane_state->fb)
4864 return -EINVAL;
4865 }
4866 }
4867 return 0;
4868}
4869
7578ecda
AD		 4870static int amdgpu_dm_atomic_check(struct drm_device *dev,
4871 struct drm_atomic_state *state)
62f55537 4872{
62f55537
AG		 4873 struct amdgpu_device *adev = dev->dev_private;
4874 struct dc *dc = adev->dm.dc;
4875 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4876 struct drm_connector *connector;
c2cea706 4877 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4878 struct drm_crtc *crtc;
fc9e9920 4879 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1e88ad0a 4880 int ret, i;
e7b07cee 4881
62f55537
AG		 4882 /*
4883 * This bool will be set for true for any modeset/reset
4884 * or plane update which implies non fast surface update.
4885 */
4886 bool lock_and_validation_needed = false;
4887
4888 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 4889 if (ret)
4890 goto fail;
62f55537 4891
1e88ad0a 4892 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
b58f0c81
S		 4893 ret = dm_atomic_check_plane_state_fb(state, crtc);
4894 if (ret)
4895 goto fail;
4896
1e88ad0a
S		 4897 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
4898 !new_crtc_state->color_mgmt_changed)
4899 continue;
7bef1af3 4900
1e88ad0a
S		 4901 if (!new_crtc_state->enable)
4902 continue;
fc9e9920 4903
1e88ad0a
S		 4904 ret = drm_atomic_add_affected_connectors(state, crtc);
4905 if (ret)
4906 return ret;
fc9e9920 4907
1e88ad0a
S		 4908 ret = drm_atomic_add_affected_planes(state, crtc);
4909 if (ret)
4910 goto fail;
e7b07cee
HW		 4911 }
4912
62f55537
AG		 4913 dm_state->context = dc_create_state();
4914 ASSERT(dm_state->context);
f36cc577 4915 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4916
4917 /* Remove exiting planes if they are modified */
4918 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4919 if (ret) {
4920 goto fail;
4921 }
4922
4923 /* Disable all crtcs which require disable */
4924 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4925 if (ret) {
4926 goto fail;
4927 }
4928
4929 /* Enable all crtcs which require enable */
4930 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4931 if (ret) {
4932 goto fail;
4933 }
4934
4935 /* Add new/modified planes */
4936 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4937 if (ret) {
4938 goto fail;
4939 }
4940
b349f76e
ES		 4941 /* Run this here since we want to validate the streams we created */
4942 ret = drm_atomic_helper_check_planes(dev, state);
4943 if (ret)
4944 goto fail;
62f55537 4945
ebdd27e1 4946 /* Check scaling and underscan changes*/
e7b07cee
HW		 4947 /*TODO Removed scaling changes validation due to inability to commit
4948 * new stream into context w\o causing full reset. Need to
4949 * decide how to handle.
4950 */
c2cea706 4951 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4952 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4953 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4954 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4955
4956 /* Skip any modesets/resets */
0bc9706d
LSL		 4957 if (!acrtc || drm_atomic_crtc_needs_modeset(
4958 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 4959 continue;
4960
b830ebc9 4961 /* Skip any thing not scale or underscan changes */
54d76575 4962 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4963 continue;
4964
4965 lock_and_validation_needed = true;
4966 }
4967
e7b07cee
HW		 4968 /*
4969 * For full updates case when
4970 * removing/adding/updating streams on once CRTC while flipping
4971 * on another CRTC,
4972 * acquiring global lock will guarantee that any such full
4973 * update commit
4974 * will wait for completion of any outstanding flip using DRMs
4975 * synchronization events.
4976 */
4977
4978 if (lock_and_validation_needed) {
4979
4980 ret = do_aquire_global_lock(dev, state);
4981 if (ret)
4982 goto fail;
1dc90497 4983
e750d56d 4984 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 4985 ret = -EINVAL;
4986 goto fail;
4987 }
4988 }
4989
4990 /* Must be success */
4991 WARN_ON(ret);
4992 return ret;
4993
4994fail:
4995 if (ret == -EDEADLK)
01e28f9c 4996 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 4997 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 4998 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 4999 else
01e28f9c 5000 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 5001
5002 return ret;
5003}
5004
3ee6b26b
AD		 5005static bool is_dp_capable_without_timing_msa(struct dc *dc,
5006 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 5007{
5008 uint8_t dpcd_data;
5009 bool capable = false;
5010
c84dec2f 5011 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 5012 dm_helpers_dp_read_dpcd(
5013 NULL,
c84dec2f 5014 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 5015 DP_DOWN_STREAM_PORT_COUNT,
5016 &dpcd_data,
5017 sizeof(dpcd_data))) {
5018 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
5019 }
5020
5021 return capable;
5022}
3ee6b26b
AD		 5023void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
5024 struct edid *edid)
e7b07cee
HW		 5025{
5026 int i;
5027 uint64_t val_capable;
5028 bool edid_check_required;
5029 struct detailed_timing *timing;
5030 struct detailed_non_pixel *data;
5031 struct detailed_data_monitor_range *range;
c84dec2f
HW		 5032 struct amdgpu_dm_connector *amdgpu_dm_connector =
5033 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5034
5035 struct drm_device *dev = connector->dev;
5036 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 5037
e7b07cee 5038 edid_check_required = false;
c84dec2f 5039 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 5040 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
5041 return;
5042 }
5043 if (!adev->dm.freesync_module)
5044 return;
5045 /*
5046 * if edid non zero restrict freesync only for dp and edp
5047 */
5048 if (edid) {
c84dec2f
HW		 5049 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
5050 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 5051 edid_check_required = is_dp_capable_without_timing_msa(
5052 adev->dm.dc,
c84dec2f 5053 amdgpu_dm_connector);
e7b07cee
HW		 5054 }
5055 }
5056 val_capable = 0;
5057 if (edid_check_required == true && (edid->version > 1 ||
5058 (edid->version == 1 && edid->revision > 1))) {
5059 for (i = 0; i < 4; i++) {
5060
5061 timing = &edid->detailed_timings[i];
5062 data = &timing->data.other_data;
5063 range = &data->data.range;
5064 /*
5065 * Check if monitor has continuous frequency mode
5066 */
5067 if (data->type != EDID_DETAIL_MONITOR_RANGE)
5068 continue;
5069 /*
5070 * Check for flag range limits only. If flag == 1 then
5071 * no additional timing information provided.
5072 * Default GTF, GTF Secondary curve and CVT are not
5073 * supported
5074 */
5075 if (range->flags != 1)
5076 continue;
5077
c84dec2f
HW		 5078 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
5079 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
5080 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 5081 range->pixel_clock_mhz * 10;
5082 break;
5083 }
5084
c84dec2f
HW		 5085 if (amdgpu_dm_connector->max_vfreq -
5086 amdgpu_dm_connector->min_vfreq > 10) {
5087 amdgpu_dm_connector->caps.supported = true;
5088 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
5089 amdgpu_dm_connector->min_vfreq * 1000000;
5090 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
5091 amdgpu_dm_connector->max_vfreq * 1000000;
e7b07cee
HW		 5092 val_capable = 1;
5093 }
5094 }
5095
5096 /*
5097 * TODO figure out how to notify user-mode or DRM of freesync caps
5098 * once we figure out how to deal with freesync in an upstreamable
5099 * fashion
5100 */
5101
5102}
5103
3ee6b26b 5104void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 5105{
5106 /*
5107 * TODO fill in once we figure out how to deal with freesync in
5108 * an upstreamable fashion
5109 */
5110}
Linux 6.x block layer and io_uring tree(s)