projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd: Use `amdgpu_ucode_*` helpers for GPU info bin
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
d2aa1356 31#include "dc_link_dp.h"
f6e03f80 32#include "link_enc_cfg.h"
1dc90497 33#include "dc/inc/core_types.h"
a7669aff 34#include "dal_asic_id.h"
cdca3f21 35#include "dmub/dmub_srv.h"
743b9786
NK		 36#include "dc/inc/hw/dmcu.h"
37#include "dc/inc/hw/abm.h"
9a71c7d3 38#include "dc/dc_dmub_srv.h"
f9b4f20c 39#include "dc/dc_edid_parser.h"
81927e28 40#include "dc/dc_stat.h"
9d83722d 41#include "amdgpu_dm_trace.h"
4562236b
HW		 42
43#include "vid.h"
44#include "amdgpu.h"
a49dcb88 45#include "amdgpu_display.h"
a94d5569 46#include "amdgpu_ucode.h"
4562236b
HW		 47#include "atom.h"
48#include "amdgpu_dm.h"
5d945cbc 49#include "amdgpu_dm_plane.h"
473683a0 50#include "amdgpu_dm_crtc.h"
52704fca
BL		 51#ifdef CONFIG_DRM_AMD_DC_HDCP
52#include "amdgpu_dm_hdcp.h"
6a99099f 53#include <drm/display/drm_hdcp_helper.h>
52704fca 54#endif
e7b07cee 55#include "amdgpu_pm.h"
1f579254 56#include "amdgpu_atombios.h"
4562236b
HW		 57
58#include "amd_shared.h"
59#include "amdgpu_dm_irq.h"
60#include "dm_helpers.h"
e7b07cee 61#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 62#if defined(CONFIG_DEBUG_FS)
63#include "amdgpu_dm_debugfs.h"
64#endif
f4594cd1 65#include "amdgpu_dm_psr.h"
4562236b
HW		 66
67#include "ivsrcid/ivsrcid_vislands30.h"
68
81927e28 69#include "i2caux_interface.h"
4562236b
HW		 70#include <linux/module.h>
71#include <linux/moduleparam.h>
e7b07cee 72#include <linux/types.h>
97028037 73#include <linux/pm_runtime.h>
09d21852 74#include <linux/pci.h>
a94d5569 75#include <linux/firmware.h>
6ce8f316 76#include <linux/component.h>
57b9f338 77#include <linux/dmi.h>
4562236b 78
da68386d 79#include <drm/display/drm_dp_mst_helper.h>
4fc8cb47 80#include <drm/display/drm_hdmi_helper.h>
4562236b 81#include <drm/drm_atomic.h>
674e78ac 82#include <drm/drm_atomic_uapi.h>
4562236b 83#include <drm/drm_atomic_helper.h>
90bb087f 84#include <drm/drm_blend.h>
09d21852 85#include <drm/drm_fourcc.h>
e7b07cee 86#include <drm/drm_edid.h>
09d21852 87#include <drm/drm_vblank.h>
6ce8f316 88#include <drm/drm_audio_component.h>
047de3f1 89#include <drm/drm_gem_atomic_helper.h>
30c63715 90#include <drm/drm_plane_helper.h>
4562236b 91
da11ef83
HG		 92#include <acpi/video.h>
93
5527cd06 94#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
ff5ef992 95
ad941f7a
FX		 96#include "dcn/dcn_1_0_offset.h"
97#include "dcn/dcn_1_0_sh_mask.h"
407e7517 98#include "soc15_hw_ip.h"
543036a2 99#include "soc15_common.h"
407e7517 100#include "vega10_ip_offset.h"
ff5ef992 101
543036a2
AP		 102#include "gc/gc_11_0_0_offset.h"
103#include "gc/gc_11_0_0_sh_mask.h"
104
e7b07cee 105#include "modules/inc/mod_freesync.h"
bbf854dc 106#include "modules/power/power_helpers.h"
ecd0136b 107#include "modules/inc/mod_info_packet.h"
e7b07cee 108
743b9786
NK		 109#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
110MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
79037324
BL		 111#define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
112MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
5ce868fc
BL		 113#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
114MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
71c0fd92
RL		 115#define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
116MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
469989ca
RL		 117#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
118MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
2a411205
BL		 119#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
120MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
656fe9b6
AP		 121#define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
122MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
1ebcaebd
NK		 123#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
124MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
e850f6b1
RL		 125#define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
126MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
b5b8ed44
QZ		 127#define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
128MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
de7cc1b4
PL		 129#define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
130MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
2200eb9e 131
577359ca
AP		 132#define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
133MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
134#define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
135MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
136
a94d5569
DF		 137#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
138MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 139
5ea23931
RL		 140#define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
141MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
142
8c7aea40
NK		 143/* Number of bytes in PSP header for firmware. */
144#define PSP_HEADER_BYTES 0x100
145
146/* Number of bytes in PSP footer for firmware. */
147#define PSP_FOOTER_BYTES 0x100
148
b8592b48
LL		 149/**
150 * DOC: overview
151 *
152 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
ec5c0ffa 153 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
b8592b48
LL		 154 * requests into DC requests, and DC responses into DRM responses.
155 *
156 * The root control structure is &struct amdgpu_display_manager.
157 */
158
7578ecda
AD		 159/* basic init/fini API */
160static int amdgpu_dm_init(struct amdgpu_device *adev);
161static void amdgpu_dm_fini(struct amdgpu_device *adev);
fe8858bb 162static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
7578ecda 163
0f877894
OV		 164static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
165{
166 switch (link->dpcd_caps.dongle_type) {
167 case DISPLAY_DONGLE_NONE:
168 return DRM_MODE_SUBCONNECTOR_Native;
169 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
170 return DRM_MODE_SUBCONNECTOR_VGA;
171 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
172 case DISPLAY_DONGLE_DP_DVI_DONGLE:
173 return DRM_MODE_SUBCONNECTOR_DVID;
174 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
175 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
176 return DRM_MODE_SUBCONNECTOR_HDMIA;
177 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
178 default:
179 return DRM_MODE_SUBCONNECTOR_Unknown;
180 }
181}
182
183static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
184{
185 struct dc_link *link = aconnector->dc_link;
186 struct drm_connector *connector = &aconnector->base;
187 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
188
189 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
190 return;
191
192 if (aconnector->dc_sink)
193 subconnector = get_subconnector_type(link);
194
195 drm_object_property_set_value(&connector->base,
196 connector->dev->mode_config.dp_subconnector_property,
197 subconnector);
198}
199
1f6010a9
DF		 200/*
201 * initializes drm_device display related structures, based on the information
7578ecda
AD		 202 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
203 * drm_encoder, drm_mode_config
204 *
205 * Returns 0 on success
206 */
207static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
208/* removes and deallocates the drm structures, created by the above function */
209static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
210
7578ecda
AD		 211static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
212 struct amdgpu_dm_connector *amdgpu_dm_connector,
ae67558b 213 u32 link_index,
7578ecda
AD		 214 struct amdgpu_encoder *amdgpu_encoder);
215static int amdgpu_dm_encoder_init(struct drm_device *dev,
216 struct amdgpu_encoder *aencoder,
217 uint32_t link_index);
218
219static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
220
7578ecda
AD		 221static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
222
223static int amdgpu_dm_atomic_check(struct drm_device *dev,
224 struct drm_atomic_state *state);
225
e27c41d5 226static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
c40a09e5 227static void handle_hpd_rx_irq(void *param);
e27c41d5 228
a85ba005
NC		 229static bool
230is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
231 struct drm_crtc_state *new_crtc_state);
4562236b
HW		 232/*
233 * dm_vblank_get_counter
234 *
235 * @brief
236 * Get counter for number of vertical blanks
237 *
238 * @param
239 * struct amdgpu_device *adev - [in] desired amdgpu device
240 * int disp_idx - [in] which CRTC to get the counter from
241 *
242 * @return
243 * Counter for vertical blanks
244 */
245static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
246{
247 if (crtc >= adev->mode_info.num_crtc)
248 return 0;
249 else {
250 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
251
585d450c 252 if (acrtc->dm_irq_params.stream == NULL) {
0971c40e
HW		 253 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
254 crtc);
4562236b
HW		 255 return 0;
256 }
257
585d450c 258 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
4562236b
HW		 259 }
260}
261
262static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 263 u32 *vbl, u32 *position)
4562236b 264{
ae67558b 265 u32 v_blank_start, v_blank_end, h_position, v_position;
81c50963 266
4562236b
HW		 267 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
268 return -EINVAL;
269 else {
270 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
271
585d450c 272 if (acrtc->dm_irq_params.stream == NULL) {
0971c40e
HW		 273 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
274 crtc);
4562236b
HW		 275 return 0;
276 }
277
81c50963
ST		 278 /*
279 * TODO rework base driver to use values directly.
280 * for now parse it back into reg-format
281 */
585d450c 282 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
81c50963
ST		 283 &v_blank_start,
284 &v_blank_end,
285 &h_position,
286 &v_position);
287
e806208d
AG		 288 *position = v_position | (h_position << 16);
289 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 290 }
291
292 return 0;
293}
294
295static bool dm_is_idle(void *handle)
296{
297 /* XXX todo */
298 return true;
299}
300
301static int dm_wait_for_idle(void *handle)
302{
303 /* XXX todo */
304 return 0;
305}
306
307static bool dm_check_soft_reset(void *handle)
308{
309 return false;
310}
311
312static int dm_soft_reset(void *handle)
313{
314 /* XXX todo */
315 return 0;
316}
317
3ee6b26b
AD		 318static struct amdgpu_crtc *
319get_crtc_by_otg_inst(struct amdgpu_device *adev,
320 int otg_inst)
4562236b 321{
4a580877 322 struct drm_device *dev = adev_to_drm(adev);
4562236b
HW		 323 struct drm_crtc *crtc;
324 struct amdgpu_crtc *amdgpu_crtc;
325
bcd74374 326 if (WARN_ON(otg_inst == -1))
4562236b 327 return adev->mode_info.crtcs[0];
4562236b
HW		 328
329 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
330 amdgpu_crtc = to_amdgpu_crtc(crtc);
331
332 if (amdgpu_crtc->otg_inst == otg_inst)
333 return amdgpu_crtc;
334 }
335
336 return NULL;
337}
338
a85ba005
NC		 339static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
340 struct dm_crtc_state *new_state)
341{
342 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
343 return true;
344 else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
345 return true;
346 else
347 return false;
348}
349
b8e8c934
HW		 350/**
351 * dm_pflip_high_irq() - Handle pageflip interrupt
352 * @interrupt_params: ignored
353 *
354 * Handles the pageflip interrupt by notifying all interested parties
355 * that the pageflip has been completed.
356 */
4562236b
HW		 357static void dm_pflip_high_irq(void *interrupt_params)
358{
4562236b
HW		 359 struct amdgpu_crtc *amdgpu_crtc;
360 struct common_irq_params *irq_params = interrupt_params;
361 struct amdgpu_device *adev = irq_params->adev;
362 unsigned long flags;
71bbe51a 363 struct drm_pending_vblank_event *e;
ae67558b 364 u32 vpos, hpos, v_blank_start, v_blank_end;
71bbe51a 365 bool vrr_active;
4562236b
HW		 366
367 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
368
369 /* IRQ could occur when in initial stage */
1f6010a9 370 /* TODO work and BO cleanup */
4562236b 371 if (amdgpu_crtc == NULL) {
cb2318b7 372 DC_LOG_PFLIP("CRTC is null, returning.\n");
4562236b
HW		 373 return;
374 }
375
4a580877 376 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
4562236b
HW		 377
378 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
cb2318b7 379 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
4562236b
HW		 380 amdgpu_crtc->pflip_status,
381 AMDGPU_FLIP_SUBMITTED,
382 amdgpu_crtc->crtc_id,
383 amdgpu_crtc);
4a580877 384 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
4562236b
HW		 385 return;
386 }
387
71bbe51a
MK		 388 /* page flip completed. */
389 e = amdgpu_crtc->event;
390 amdgpu_crtc->event = NULL;
4562236b 391
bcd74374 392 WARN_ON(!e);
1159898a 393
585d450c 394 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
71bbe51a
MK		 395
396 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
397 if (!vrr_active ||
585d450c 398 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
71bbe51a
MK		 399 &v_blank_end, &hpos, &vpos) ||
400 (vpos < v_blank_start)) {
401 /* Update to correct count and vblank timestamp if racing with
402 * vblank irq. This also updates to the correct vblank timestamp
403 * even in VRR mode, as scanout is past the front-porch atm.
404 */
405 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
1159898a 406
71bbe51a
MK		 407 /* Wake up userspace by sending the pageflip event with proper
408 * count and timestamp of vblank of flip completion.
409 */
410 if (e) {
411 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
412
413 /* Event sent, so done with vblank for this flip */
414 drm_crtc_vblank_put(&amdgpu_crtc->base);
415 }
416 } else if (e) {
417 /* VRR active and inside front-porch: vblank count and
418 * timestamp for pageflip event will only be up to date after
419 * drm_crtc_handle_vblank() has been executed from late vblank
420 * irq handler after start of back-porch (vline 0). We queue the
421 * pageflip event for send-out by drm_crtc_handle_vblank() with
422 * updated timestamp and count, once it runs after us.
423 *
424 * We need to open-code this instead of using the helper
425 * drm_crtc_arm_vblank_event(), as that helper would
426 * call drm_crtc_accurate_vblank_count(), which we must
427 * not call in VRR mode while we are in front-porch!
428 */
429
430 /* sequence will be replaced by real count during send-out. */
431 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
432 e->pipe = amdgpu_crtc->crtc_id;
433
4a580877 434 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
71bbe51a
MK		 435 e = NULL;
436 }
4562236b 437
fdd1fe57
MK		 438 /* Keep track of vblank of this flip for flip throttling. We use the
439 * cooked hw counter, as that one incremented at start of this vblank
440 * of pageflip completion, so last_flip_vblank is the forbidden count
441 * for queueing new pageflips if vsync + VRR is enabled.
442 */
5d1c59c4 443 amdgpu_crtc->dm_irq_params.last_flip_vblank =
e3eff4b5 444 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
fdd1fe57 445
54f5499a 446 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4a580877 447 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
4562236b 448
cb2318b7
VL		 449 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
450 amdgpu_crtc->crtc_id, amdgpu_crtc,
451 vrr_active, (int) !e);
4562236b
HW		 452}
453
d2574c33
MK		 454static void dm_vupdate_high_irq(void *interrupt_params)
455{
456 struct common_irq_params *irq_params = interrupt_params;
457 struct amdgpu_device *adev = irq_params->adev;
458 struct amdgpu_crtc *acrtc;
47588233
RS		 459 struct drm_device *drm_dev;
460 struct drm_vblank_crtc *vblank;
461 ktime_t frame_duration_ns, previous_timestamp;
09aef2c4 462 unsigned long flags;
585d450c 463 int vrr_active;
d2574c33
MK		 464
465 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
466
467 if (acrtc) {
585d450c 468 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
47588233
RS		 469 drm_dev = acrtc->base.dev;
470 vblank = &drm_dev->vblank[acrtc->base.index];
471 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
472 frame_duration_ns = vblank->time - previous_timestamp;
473
474 if (frame_duration_ns > 0) {
475 trace_amdgpu_refresh_rate_track(acrtc->base.index,
476 frame_duration_ns,
477 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
478 atomic64_set(&irq_params->previous_timestamp, vblank->time);
479 }
d2574c33 480
cb2318b7 481 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
7f2be468 482 acrtc->crtc_id,
585d450c 483 vrr_active);
d2574c33
MK		 484
485 /* Core vblank handling is done here after end of front-porch in
486 * vrr mode, as vblank timestamping will give valid results
487 * while now done after front-porch. This will also deliver
488 * page-flip completion events that have been queued to us
489 * if a pageflip happened inside front-porch.
490 */
585d450c 491 if (vrr_active) {
cc79950b 492 dm_crtc_handle_vblank(acrtc);
09aef2c4
MK		 493
494 /* BTR processing for pre-DCE12 ASICs */
585d450c 495 if (acrtc->dm_irq_params.stream &&
09aef2c4 496 adev->family < AMDGPU_FAMILY_AI) {
4a580877 497 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
09aef2c4
MK		 498 mod_freesync_handle_v_update(
499 adev->dm.freesync_module,
585d450c
AP		 500 acrtc->dm_irq_params.stream,
501 &acrtc->dm_irq_params.vrr_params);
09aef2c4
MK		 502
503 dc_stream_adjust_vmin_vmax(
504 adev->dm.dc,
585d450c
AP		 505 acrtc->dm_irq_params.stream,
506 &acrtc->dm_irq_params.vrr_params.adjust);
4a580877 507 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
09aef2c4
MK		 508 }
509 }
d2574c33
MK		 510 }
511}
512
b8e8c934
HW		 513/**
514 * dm_crtc_high_irq() - Handles CRTC interrupt
2346ef47 515 * @interrupt_params: used for determining the CRTC instance
b8e8c934
HW		 516 *
517 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
518 * event handler.
519 */
4562236b
HW		 520static void dm_crtc_high_irq(void *interrupt_params)
521{
522 struct common_irq_params *irq_params = interrupt_params;
523 struct amdgpu_device *adev = irq_params->adev;
4562236b 524 struct amdgpu_crtc *acrtc;
09aef2c4 525 unsigned long flags;
585d450c 526 int vrr_active;
4562236b 527
b57de80a 528 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
16f17eda
LL		 529 if (!acrtc)
530 return;
531
585d450c 532 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
16f17eda 533
cb2318b7 534 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
585d450c 535 vrr_active, acrtc->dm_irq_params.active_planes);
16f17eda 536
2346ef47
NK		 537 /**
538 * Core vblank handling at start of front-porch is only possible
539 * in non-vrr mode, as only there vblank timestamping will give
540 * valid results while done in front-porch. Otherwise defer it
541 * to dm_vupdate_high_irq after end of front-porch.
542 */
585d450c 543 if (!vrr_active)
cc79950b 544 dm_crtc_handle_vblank(acrtc);
2346ef47
NK		 545
546 /**
547 * Following stuff must happen at start of vblank, for crc
548 * computation and below-the-range btr support in vrr mode.
549 */
16f17eda 550 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
2346ef47
NK		 551
552 /* BTR updates need to happen before VUPDATE on Vega and above. */
553 if (adev->family < AMDGPU_FAMILY_AI)
554 return;
16f17eda 555
4a580877 556 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
16f17eda 557
585d450c
AP		 558 if (acrtc->dm_irq_params.stream &&
559 acrtc->dm_irq_params.vrr_params.supported &&
560 acrtc->dm_irq_params.freesync_config.state ==
561 VRR_STATE_ACTIVE_VARIABLE) {
2346ef47 562 mod_freesync_handle_v_update(adev->dm.freesync_module,
585d450c
AP		 563 acrtc->dm_irq_params.stream,
564 &acrtc->dm_irq_params.vrr_params);
16f17eda 565
585d450c
AP		 566 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
567 &acrtc->dm_irq_params.vrr_params.adjust);
16f17eda
LL		 568 }
569
2b5aed9a
MK		 570 /*
571 * If there aren't any active_planes then DCH HUBP may be clock-gated.
572 * In that case, pageflip completion interrupts won't fire and pageflip
573 * completion events won't get delivered. Prevent this by sending
574 * pending pageflip events from here if a flip is still pending.
575 *
576 * If any planes are enabled, use dm_pflip_high_irq() instead, to
577 * avoid race conditions between flip programming and completion,
578 * which could cause too early flip completion events.
579 */
2346ef47
NK		 580 if (adev->family >= AMDGPU_FAMILY_RV &&
581 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
585d450c 582 acrtc->dm_irq_params.active_planes == 0) {
16f17eda
LL		 583 if (acrtc->event) {
584 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
585 acrtc->event = NULL;
586 drm_crtc_vblank_put(&acrtc->base);
587 }
588 acrtc->pflip_status = AMDGPU_FLIP_NONE;
589 }
590
4a580877 591 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
16f17eda
LL		 592}
593
9e1178ef 594#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
86bc2219
WL		 595/**
596 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
597 * DCN generation ASICs
48e01bf4 598 * @interrupt_params: interrupt parameters
86bc2219
WL		 599 *
600 * Used to set crc window/read out crc value at vertical line 0 position
601 */
86bc2219
WL		 602static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
603{
604 struct common_irq_params *irq_params = interrupt_params;
605 struct amdgpu_device *adev = irq_params->adev;
606 struct amdgpu_crtc *acrtc;
607
608 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
609
610 if (!acrtc)
611 return;
612
613 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
614}
433e5dec 615#endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
86bc2219 616
e27c41d5 617/**
03f2abb0 618 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
e27c41d5
JS		 619 * @adev: amdgpu_device pointer
620 * @notify: dmub notification structure
621 *
622 * Dmub AUX or SET_CONFIG command completion processing callback
623 * Copies dmub notification to DM which is to be read by AUX command.
624 * issuing thread and also signals the event to wake up the thread.
625 */
240e6d25
IB		 626static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
627 struct dmub_notification *notify)
e27c41d5
JS		 628{
629 if (adev->dm.dmub_notify)
630 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
631 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
632 complete(&adev->dm.dmub_aux_transfer_done);
633}
634
635/**
636 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
637 * @adev: amdgpu_device pointer
638 * @notify: dmub notification structure
639 *
640 * Dmub Hpd interrupt processing callback. Gets displayindex through the
641 * ink index and calls helper to do the processing.
642 */
240e6d25
IB		 643static void dmub_hpd_callback(struct amdgpu_device *adev,
644 struct dmub_notification *notify)
e27c41d5
JS		 645{
646 struct amdgpu_dm_connector *aconnector;
f6e03f80 647 struct amdgpu_dm_connector *hpd_aconnector = NULL;
e27c41d5
JS		 648 struct drm_connector *connector;
649 struct drm_connector_list_iter iter;
650 struct dc_link *link;
ae67558b 651 u8 link_index = 0;
978ffac8 652 struct drm_device *dev;
e27c41d5
JS		 653
654 if (adev == NULL)
655 return;
656
657 if (notify == NULL) {
658 DRM_ERROR("DMUB HPD callback notification was NULL");
659 return;
660 }
661
662 if (notify->link_index > adev->dm.dc->link_count) {
663 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
664 return;
665 }
666
e27c41d5 667 link_index = notify->link_index;
e27c41d5 668 link = adev->dm.dc->links[link_index];
978ffac8 669 dev = adev->dm.ddev;
e27c41d5
JS		 670
671 drm_connector_list_iter_begin(dev, &iter);
672 drm_for_each_connector_iter(connector, &iter) {
673 aconnector = to_amdgpu_dm_connector(connector);
674 if (link && aconnector->dc_link == link) {
675 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
f6e03f80 676 hpd_aconnector = aconnector;
e27c41d5
JS		 677 break;
678 }
679 }
680 drm_connector_list_iter_end(&iter);
e27c41d5 681
c40a09e5
NK		 682 if (hpd_aconnector) {
683 if (notify->type == DMUB_NOTIFICATION_HPD)
684 handle_hpd_irq_helper(hpd_aconnector);
685 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
686 handle_hpd_rx_irq(hpd_aconnector);
687 }
e27c41d5
JS		 688}
689
690/**
691 * register_dmub_notify_callback - Sets callback for DMUB notify
692 * @adev: amdgpu_device pointer
693 * @type: Type of dmub notification
694 * @callback: Dmub interrupt callback function
695 * @dmub_int_thread_offload: offload indicator
696 *
697 * API to register a dmub callback handler for a dmub notification
698 * Also sets indicator whether callback processing to be offloaded.
699 * to dmub interrupt handling thread
700 * Return: true if successfully registered, false if there is existing registration
701 */
240e6d25
IB		 702static bool register_dmub_notify_callback(struct amdgpu_device *adev,
703 enum dmub_notification_type type,
704 dmub_notify_interrupt_callback_t callback,
705 bool dmub_int_thread_offload)
e27c41d5
JS		 706{
707 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
708 adev->dm.dmub_callback[type] = callback;
709 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
710 } else
711 return false;
712
713 return true;
714}
715
716static void dm_handle_hpd_work(struct work_struct *work)
717{
718 struct dmub_hpd_work *dmub_hpd_wrk;
719
720 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
721
722 if (!dmub_hpd_wrk->dmub_notify) {
723 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
724 return;
725 }
726
727 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
728 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
729 dmub_hpd_wrk->dmub_notify);
730 }
094b21c1
JS		 731
732 kfree(dmub_hpd_wrk->dmub_notify);
e27c41d5
JS		 733 kfree(dmub_hpd_wrk);
734
735}
736
e25515e2 737#define DMUB_TRACE_MAX_READ 64
81927e28
JS		 738/**
739 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
740 * @interrupt_params: used for determining the Outbox instance
741 *
742 * Handles the Outbox Interrupt
743 * event handler.
744 */
81927e28
JS		 745static void dm_dmub_outbox1_low_irq(void *interrupt_params)
746{
747 struct dmub_notification notify;
748 struct common_irq_params *irq_params = interrupt_params;
749 struct amdgpu_device *adev = irq_params->adev;
750 struct amdgpu_display_manager *dm = &adev->dm;
751 struct dmcub_trace_buf_entry entry = { 0 };
ae67558b 752 u32 count = 0;
e27c41d5 753 struct dmub_hpd_work *dmub_hpd_wrk;
f6e03f80 754 struct dc_link *plink = NULL;
81927e28 755
f6e03f80
JS		 756 if (dc_enable_dmub_notifications(adev->dm.dc) &&
757 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
e27c41d5 758
f6e03f80
JS		 759 do {
760 dc_stat_get_dmub_notification(adev->dm.dc, &notify);
a35faec3 761 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
f6e03f80
JS		 762 DRM_ERROR("DM: notify type %d invalid!", notify.type);
763 continue;
764 }
c40a09e5
NK		 765 if (!dm->dmub_callback[notify.type]) {
766 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
767 continue;
768 }
f6e03f80 769 if (dm->dmub_thread_offload[notify.type] == true) {
094b21c1
JS		 770 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
771 if (!dmub_hpd_wrk) {
772 DRM_ERROR("Failed to allocate dmub_hpd_wrk");
773 return;
774 }
775 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
776 if (!dmub_hpd_wrk->dmub_notify) {
777 kfree(dmub_hpd_wrk);
778 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
779 return;
780 }
781 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
782 if (dmub_hpd_wrk->dmub_notify)
783 memcpy(dmub_hpd_wrk->dmub_notify, &notify, sizeof(struct dmub_notification));
f6e03f80
JS		 784 dmub_hpd_wrk->adev = adev;
785 if (notify.type == DMUB_NOTIFICATION_HPD) {
786 plink = adev->dm.dc->links[notify.link_index];
787 if (plink) {
788 plink->hpd_status =
b97788e5 789 notify.hpd_status == DP_HPD_PLUG;
f6e03f80 790 }
e27c41d5 791 }
f6e03f80
JS		 792 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
793 } else {
794 dm->dmub_callback[notify.type](adev, &notify);
795 }
796 } while (notify.pending_notification);
81927e28
JS		 797 }
798
799
800 do {
801 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
802 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
803 entry.param0, entry.param1);
804
805 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
806 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
807 } else
808 break;
809
810 count++;
811
812 } while (count <= DMUB_TRACE_MAX_READ);
813
f6e03f80
JS		 814 if (count > DMUB_TRACE_MAX_READ)
815 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
81927e28 816}
86bc2219 817
4562236b
HW		 818static int dm_set_clockgating_state(void *handle,
819 enum amd_clockgating_state state)
820{
821 return 0;
822}
823
824static int dm_set_powergating_state(void *handle,
825 enum amd_powergating_state state)
826{
827 return 0;
828}
829
830/* Prototypes of private functions */
831static int dm_early_init(void* handle);
832
a32e24b4 833/* Allocate memory for FBC compressed data */
3e332d3a 834static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 835{
3e332d3a 836 struct drm_device *dev = connector->dev;
1348969a 837 struct amdgpu_device *adev = drm_to_adev(dev);
4d154b85 838 struct dm_compressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 839 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
840 struct drm_display_mode *mode;
42e67c3b
RL		 841 unsigned long max_size = 0;
842
843 if (adev->dm.dc->fbc_compressor == NULL)
844 return;
a32e24b4 845
3e332d3a 846 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 847 return;
848
3e332d3a
RL		 849 if (compressor->bo_ptr)
850 return;
42e67c3b 851
42e67c3b 852
3e332d3a
RL		 853 list_for_each_entry(mode, &connector->modes, head) {
854 if (max_size < mode->htotal * mode->vtotal)
855 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 856 }
857
858 if (max_size) {
859 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 860 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 861 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 862
863 if (r)
42e67c3b
RL		 864 DRM_ERROR("DM: Failed to initialize FBC\n");
865 else {
866 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
867 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
868 }
869
a32e24b4
RL		 870 }
871
872}
a32e24b4 873
6ce8f316
NK		 874static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
875 int pipe, bool *enabled,
876 unsigned char *buf, int max_bytes)
877{
878 struct drm_device *dev = dev_get_drvdata(kdev);
1348969a 879 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 880 struct drm_connector *connector;
881 struct drm_connector_list_iter conn_iter;
882 struct amdgpu_dm_connector *aconnector;
883 int ret = 0;
884
885 *enabled = false;
886
887 mutex_lock(&adev->dm.audio_lock);
888
889 drm_connector_list_iter_begin(dev, &conn_iter);
890 drm_for_each_connector_iter(connector, &conn_iter) {
891 aconnector = to_amdgpu_dm_connector(connector);
892 if (aconnector->audio_inst != port)
893 continue;
894
895 *enabled = true;
896 ret = drm_eld_size(connector->eld);
897 memcpy(buf, connector->eld, min(max_bytes, ret));
898
899 break;
900 }
901 drm_connector_list_iter_end(&conn_iter);
902
903 mutex_unlock(&adev->dm.audio_lock);
904
905 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
906
907 return ret;
908}
909
910static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
911 .get_eld = amdgpu_dm_audio_component_get_eld,
912};
913
914static int amdgpu_dm_audio_component_bind(struct device *kdev,
915 struct device *hda_kdev, void *data)
916{
917 struct drm_device *dev = dev_get_drvdata(kdev);
1348969a 918 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 919 struct drm_audio_component *acomp = data;
920
921 acomp->ops = &amdgpu_dm_audio_component_ops;
922 acomp->dev = kdev;
923 adev->dm.audio_component = acomp;
924
925 return 0;
926}
927
928static void amdgpu_dm_audio_component_unbind(struct device *kdev,
929 struct device *hda_kdev, void *data)
930{
931 struct drm_device *dev = dev_get_drvdata(kdev);
1348969a 932 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 933 struct drm_audio_component *acomp = data;
934
935 acomp->ops = NULL;
936 acomp->dev = NULL;
937 adev->dm.audio_component = NULL;
938}
939
940static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
941 .bind = amdgpu_dm_audio_component_bind,
942 .unbind = amdgpu_dm_audio_component_unbind,
943};
944
945static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
946{
947 int i, ret;
948
949 if (!amdgpu_audio)
950 return 0;
951
952 adev->mode_info.audio.enabled = true;
953
954 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
955
956 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
957 adev->mode_info.audio.pin[i].channels = -1;
958 adev->mode_info.audio.pin[i].rate = -1;
959 adev->mode_info.audio.pin[i].bits_per_sample = -1;
960 adev->mode_info.audio.pin[i].status_bits = 0;
961 adev->mode_info.audio.pin[i].category_code = 0;
962 adev->mode_info.audio.pin[i].connected = false;
963 adev->mode_info.audio.pin[i].id =
964 adev->dm.dc->res_pool->audios[i]->inst;
965 adev->mode_info.audio.pin[i].offset = 0;
966 }
967
968 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
969 if (ret < 0)
970 return ret;
971
972 adev->dm.audio_registered = true;
973
974 return 0;
975}
976
977static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
978{
979 if (!amdgpu_audio)
980 return;
981
982 if (!adev->mode_info.audio.enabled)
983 return;
984
985 if (adev->dm.audio_registered) {
986 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
987 adev->dm.audio_registered = false;
988 }
989
990 /* TODO: Disable audio? */
991
992 adev->mode_info.audio.enabled = false;
993}
994
dfd84d90 995static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
6ce8f316
NK		 996{
997 struct drm_audio_component *acomp = adev->dm.audio_component;
998
999 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1000 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1001
1002 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1003 pin, -1);
1004 }
1005}
1006
743b9786
NK		 1007static int dm_dmub_hw_init(struct amdgpu_device *adev)
1008{
743b9786
NK		 1009 const struct dmcub_firmware_header_v1_0 *hdr;
1010 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
8c7aea40 1011 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
743b9786
NK		 1012 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1013 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1014 struct abm *abm = adev->dm.dc->res_pool->abm;
743b9786
NK		 1015 struct dmub_srv_hw_params hw_params;
1016 enum dmub_status status;
1017 const unsigned char *fw_inst_const, *fw_bss_data;
ae67558b 1018 u32 i, fw_inst_const_size, fw_bss_data_size;
743b9786
NK		 1019 bool has_hw_support;
1020
1021 if (!dmub_srv)
1022 /* DMUB isn't supported on the ASIC. */
1023 return 0;
1024
8c7aea40
NK		 1025 if (!fb_info) {
1026 DRM_ERROR("No framebuffer info for DMUB service.\n");
1027 return -EINVAL;
1028 }
1029
743b9786
NK		 1030 if (!dmub_fw) {
1031 /* Firmware required for DMUB support. */
1032 DRM_ERROR("No firmware provided for DMUB.\n");
1033 return -EINVAL;
1034 }
1035
1036 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1037 if (status != DMUB_STATUS_OK) {
1038 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1039 return -EINVAL;
1040 }
1041
1042 if (!has_hw_support) {
1043 DRM_INFO("DMUB unsupported on ASIC\n");
1044 return 0;
1045 }
1046
47e62dbd
NK		 1047 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1048 status = dmub_srv_hw_reset(dmub_srv);
1049 if (status != DMUB_STATUS_OK)
1050 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1051
743b9786
NK		 1052 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1053
743b9786
NK		 1054 fw_inst_const = dmub_fw->data +
1055 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
8c7aea40 1056 PSP_HEADER_BYTES;
743b9786
NK		 1057
1058 fw_bss_data = dmub_fw->data +
1059 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1060 le32_to_cpu(hdr->inst_const_bytes);
1061
1062 /* Copy firmware and bios info into FB memory. */
8c7aea40
NK		 1063 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1064 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1065
1066 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1067
ddde28a5
HW		 1068 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1069 * amdgpu_ucode_init_single_fw will load dmub firmware
1070 * fw_inst_const part to cw0; otherwise, the firmware back door load
1071 * will be done by dm_dmub_hw_init
1072 */
1073 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1074 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1075 fw_inst_const_size);
1076 }
1077
a576b345
NK		 1078 if (fw_bss_data_size)
1079 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1080 fw_bss_data, fw_bss_data_size);
ddde28a5
HW		 1081
1082 /* Copy firmware bios info into FB memory. */
8c7aea40
NK		 1083 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1084 adev->bios_size);
1085
1086 /* Reset regions that need to be reset. */
1087 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1088 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1089
1090 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1091 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1092
1093 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1094 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
743b9786
NK		 1095
1096 /* Initialize hardware. */
1097 memset(&hw_params, 0, sizeof(hw_params));
1098 hw_params.fb_base = adev->gmc.fb_start;
949933b0 1099 hw_params.fb_offset = adev->vm_manager.vram_base_offset;
743b9786 1100
31a7f4bb
HW		 1101 /* backdoor load firmware and trigger dmub running */
1102 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1103 hw_params.load_inst_const = true;
1104
743b9786
NK		 1105 if (dmcu)
1106 hw_params.psp_version = dmcu->psp_version;
1107
8c7aea40
NK		 1108 for (i = 0; i < fb_info->num_fb; ++i)
1109 hw_params.fb[i] = &fb_info->fb[i];
743b9786 1110
3b36f50d 1111 switch (adev->ip_versions[DCE_HWIP][0]) {
f6aa84b8
RL		 1112 case IP_VERSION(3, 1, 3):
1113 case IP_VERSION(3, 1, 4):
3b36f50d 1114 hw_params.dpia_supported = true;
7367540b 1115 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
5b109397
JS		 1116 break;
1117 default:
1118 break;
1119 }
1120
743b9786
NK		 1121 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1122 if (status != DMUB_STATUS_OK) {
1123 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1124 return -EINVAL;
1125 }
1126
1127 /* Wait for firmware load to finish. */
1128 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1129 if (status != DMUB_STATUS_OK)
1130 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1131
1132 /* Init DMCU and ABM if available. */
1133 if (dmcu && abm) {
1134 dmcu->funcs->dmcu_init(dmcu);
1135 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1136 }
1137
051b7887
RL		 1138 if (!adev->dm.dc->ctx->dmub_srv)
1139 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
9a71c7d3
NK		 1140 if (!adev->dm.dc->ctx->dmub_srv) {
1141 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1142 return -ENOMEM;
1143 }
1144
743b9786
NK		 1145 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1146 adev->dm.dmcub_fw_version);
1147
1148 return 0;
1149}
1150
79d6b935
NK		 1151static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1152{
1153 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1154 enum dmub_status status;
1155 bool init;
1156
1157 if (!dmub_srv) {
1158 /* DMUB isn't supported on the ASIC. */
1159 return;
1160 }
1161
1162 status = dmub_srv_is_hw_init(dmub_srv, &init);
1163 if (status != DMUB_STATUS_OK)
1164 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1165
1166 if (status == DMUB_STATUS_OK && init) {
1167 /* Wait for firmware load to finish. */
1168 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1169 if (status != DMUB_STATUS_OK)
1170 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1171 } else {
1172 /* Perform the full hardware initialization. */
1173 dm_dmub_hw_init(adev);
1174 }
1175}
1176
c0fb85ae 1177static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
c44a22b3 1178{
ae67558b
SS		 1179 u64 pt_base;
1180 u32 logical_addr_low;
1181 u32 logical_addr_high;
1182 u32 agp_base, agp_bot, agp_top;
c0fb85ae 1183 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
c44a22b3 1184
a0f884f5
NK		 1185 memset(pa_config, 0, sizeof(*pa_config));
1186
c0fb85ae
YZ		 1187 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1188 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
c44a22b3 1189
c0fb85ae
YZ		 1190 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1191 /*
1192 * Raven2 has a HW issue that it is unable to use the vram which
1193 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1194 * workaround that increase system aperture high address (add 1)
1195 * to get rid of the VM fault and hardware hang.
1196 */
1197 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1198 else
1199 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
c44a22b3 1200
c0fb85ae
YZ		 1201 agp_base = 0;
1202 agp_bot = adev->gmc.agp_start >> 24;
1203 agp_top = adev->gmc.agp_end >> 24;
c44a22b3 1204
c44a22b3 1205
c0fb85ae
YZ		 1206 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1207 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1208 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1209 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1210 page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1211 page_table_base.low_part = lower_32_bits(pt_base);
c44a22b3 1212
c0fb85ae
YZ		 1213 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1214 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1215
1216 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1217 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1218 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1219
1220 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
949933b0 1221 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
c0fb85ae
YZ		 1222 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1223
1224 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1225 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1226 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1227
1228 pa_config->is_hvm_enabled = 0;
c44a22b3 1229
c44a22b3 1230}
cae5c1ab 1231
8e794421
WL		 1232static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1233{
1234 struct hpd_rx_irq_offload_work *offload_work;
1235 struct amdgpu_dm_connector *aconnector;
1236 struct dc_link *dc_link;
1237 struct amdgpu_device *adev;
1238 enum dc_connection_type new_connection_type = dc_connection_none;
1239 unsigned long flags;
1240
1241 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1242 aconnector = offload_work->offload_wq->aconnector;
1243
1244 if (!aconnector) {
1245 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1246 goto skip;
1247 }
1248
1249 adev = drm_to_adev(aconnector->base.dev);
1250 dc_link = aconnector->dc_link;
1251
1252 mutex_lock(&aconnector->hpd_lock);
1253 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1254 DRM_ERROR("KMS: Failed to detect connector\n");
1255 mutex_unlock(&aconnector->hpd_lock);
1256
1257 if (new_connection_type == dc_connection_none)
1258 goto skip;
1259
1260 if (amdgpu_in_reset(adev))
1261 goto skip;
1262
1263 mutex_lock(&adev->dm.dc_lock);
1264 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST)
1265 dc_link_dp_handle_automated_test(dc_link);
1266 else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1267 hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) &&
1268 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1269 dc_link_dp_handle_link_loss(dc_link);
1270 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1271 offload_work->offload_wq->is_handling_link_loss = false;
1272 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1273 }
1274 mutex_unlock(&adev->dm.dc_lock);
1275
1276skip:
1277 kfree(offload_work);
1278
1279}
1280
1281static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1282{
1283 int max_caps = dc->caps.max_links;
1284 int i = 0;
1285 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1286
1287 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1288
1289 if (!hpd_rx_offload_wq)
1290 return NULL;
1291
1292
1293 for (i = 0; i < max_caps; i++) {
1294 hpd_rx_offload_wq[i].wq =
1295 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1296
1297 if (hpd_rx_offload_wq[i].wq == NULL) {
1298 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
7136f956 1299 goto out_err;
8e794421
WL		 1300 }
1301
1302 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1303 }
1304
1305 return hpd_rx_offload_wq;
7136f956
RM		 1306
1307out_err:
1308 for (i = 0; i < max_caps; i++) {
1309 if (hpd_rx_offload_wq[i].wq)
1310 destroy_workqueue(hpd_rx_offload_wq[i].wq);
1311 }
1312 kfree(hpd_rx_offload_wq);
1313 return NULL;
8e794421
WL		 1314}
1315
3ce51649
AD		 1316struct amdgpu_stutter_quirk {
1317 u16 chip_vendor;
1318 u16 chip_device;
1319 u16 subsys_vendor;
1320 u16 subsys_device;
1321 u8 revision;
1322};
1323
1324static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1325 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1326 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1327 { 0, 0, 0, 0, 0 },
1328};
1329
1330static bool dm_should_disable_stutter(struct pci_dev *pdev)
1331{
1332 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1333
1334 while (p && p->chip_device != 0) {
1335 if (pdev->vendor == p->chip_vendor &&
1336 pdev->device == p->chip_device &&
1337 pdev->subsystem_vendor == p->subsys_vendor &&
1338 pdev->subsystem_device == p->subsys_device &&
1339 pdev->revision == p->revision) {
1340 return true;
1341 }
1342 ++p;
1343 }
1344 return false;
1345}
1346
57b9f338
FZ		 1347static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1348 {
1349 .matches = {
1350 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1351 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1352 },
1353 },
1354 {
1355 .matches = {
1356 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1357 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1358 },
1359 },
1360 {
1361 .matches = {
1362 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1363 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1364 },
1365 },
503dc81c
TL		 1366 {
1367 .matches = {
1368 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1369 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1370 },
1371 },
1372 {
1373 .matches = {
1374 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1375 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1376 },
1377 },
1378 {
1379 .matches = {
1380 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1381 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1382 },
1383 },
1384 {
1385 .matches = {
1386 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1387 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1388 },
1389 },
1390 {
1391 .matches = {
1392 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1393 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1394 },
1395 },
1396 {
1397 .matches = {
1398 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1399 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1400 },
1401 },
57b9f338 1402 {}
503dc81c 1403 /* TODO: refactor this from a fixed table to a dynamic option */
57b9f338
FZ		 1404};
1405
1406static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1407{
1408 const struct dmi_system_id *dmi_id;
1409
1410 dm->aux_hpd_discon_quirk = false;
1411
1412 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1413 if (dmi_id) {
1414 dm->aux_hpd_discon_quirk = true;
1415 DRM_INFO("aux_hpd_discon_quirk attached\n");
1416 }
1417}
1418
7578ecda 1419static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 1420{
1421 struct dc_init_data init_data;
52704fca
BL		 1422#ifdef CONFIG_DRM_AMD_DC_HDCP
1423 struct dc_callback_init init_params;
1424#endif
743b9786 1425 int r;
52704fca 1426
4a580877 1427 adev->dm.ddev = adev_to_drm(adev);
4562236b
HW		 1428 adev->dm.adev = adev;
1429
4562236b
HW		 1430 /* Zero all the fields */
1431 memset(&init_data, 0, sizeof(init_data));
52704fca
BL		 1432#ifdef CONFIG_DRM_AMD_DC_HDCP
1433 memset(&init_params, 0, sizeof(init_params));
1434#endif
4562236b 1435
ead08b95 1436 mutex_init(&adev->dm.dpia_aux_lock);
674e78ac 1437 mutex_init(&adev->dm.dc_lock);
6ce8f316 1438 mutex_init(&adev->dm.audio_lock);
674e78ac 1439
4562236b
HW		 1440 if(amdgpu_dm_irq_init(adev)) {
1441 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1442 goto error;
1443 }
1444
1445 init_data.asic_id.chip_family = adev->family;
1446
2dc31ca1 1447 init_data.asic_id.pci_revision_id = adev->pdev->revision;
4562236b 1448 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
dae66a04 1449 init_data.asic_id.chip_id = adev->pdev->device;
4562236b 1450
770d13b1 1451 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 1452 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1453 init_data.asic_id.atombios_base_address =
1454 adev->mode_info.atom_context->bios;
1455
1456 init_data.driver = adev;
1457
1458 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1459
1460 if (!adev->dm.cgs_device) {
1461 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1462 goto error;
1463 }
1464
1465 init_data.cgs_device = adev->dm.cgs_device;
1466
4562236b
HW		 1467 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1468
fd546bc5
AD		 1469 switch (adev->ip_versions[DCE_HWIP][0]) {
1470 case IP_VERSION(2, 1, 0):
1471 switch (adev->dm.dmcub_fw_version) {
1472 case 0: /* development */
1473 case 0x1: /* linux-firmware.git hash 6d9f399 */
1474 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1475 init_data.flags.disable_dmcu = false;
1476 break;
1477 default:
1478 init_data.flags.disable_dmcu = true;
1479 }
1480 break;
1481 case IP_VERSION(2, 0, 3):
1482 init_data.flags.disable_dmcu = true;
1483 break;
1484 default:
1485 break;
1486 }
1487
60fb100b
AD		 1488 switch (adev->asic_type) {
1489 case CHIP_CARRIZO:
1490 case CHIP_STONEY:
1ebcaebd
NK		 1491 init_data.flags.gpu_vm_support = true;
1492 break;
60fb100b 1493 default:
1d789535 1494 switch (adev->ip_versions[DCE_HWIP][0]) {
559f591d
AD		 1495 case IP_VERSION(1, 0, 0):
1496 case IP_VERSION(1, 0, 1):
a7f520bf
AD		 1497 /* enable S/G on PCO and RV2 */
1498 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1499 (adev->apu_flags & AMD_APU_IS_PICASSO))
1500 init_data.flags.gpu_vm_support = true;
1501 break;
fd546bc5 1502 case IP_VERSION(2, 1, 0):
c08182f2
AD		 1503 case IP_VERSION(3, 0, 1):
1504 case IP_VERSION(3, 1, 2):
1505 case IP_VERSION(3, 1, 3):
fe6872ad 1506 case IP_VERSION(3, 1, 4):
b5b8ed44 1507 case IP_VERSION(3, 1, 5):
0fe382fb 1508 case IP_VERSION(3, 1, 6):
c08182f2
AD		 1509 init_data.flags.gpu_vm_support = true;
1510 break;
c08182f2
AD		 1511 default:
1512 break;
1513 }
60fb100b
AD		 1514 break;
1515 }
6e227308 1516
a7f520bf
AD		 1517 if (init_data.flags.gpu_vm_support)
1518 adev->mode_info.gpu_vm_support = true;
1519
04b94af4
AD		 1520 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1521 init_data.flags.fbc_support = true;
1522
d99f38ae
AD		 1523 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1524 init_data.flags.multi_mon_pp_mclk_switch = true;
1525
eaf56410
LL		 1526 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1527 init_data.flags.disable_fractional_pwm = true;
a5148245
ZL		 1528
1529 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1530 init_data.flags.edp_no_power_sequencing = true;
eaf56410 1531
12320274
AP		 1532 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1533 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1534 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1535 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
12320274 1536
7aba117a 1537 init_data.flags.seamless_boot_edp_requested = false;
78ad75f8 1538
1edf5ae1 1539 if (check_seamless_boot_capability(adev)) {
7aba117a 1540 init_data.flags.seamless_boot_edp_requested = true;
1edf5ae1
ZL		 1541 init_data.flags.allow_seamless_boot_optimization = true;
1542 DRM_INFO("Seamless boot condition check passed\n");
1543 }
1544
a8201902
LM		 1545 init_data.flags.enable_mipi_converter_optimization = true;
1546
e5028e9f 1547 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
2a93292f 1548 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
e5028e9f 1549
0dd79532 1550 INIT_LIST_HEAD(&adev->dm.da_list);
57b9f338
FZ		 1551
1552 retrieve_dmi_info(&adev->dm);
1553
4562236b
HW		 1554 /* Display Core create. */
1555 adev->dm.dc = dc_create(&init_data);
1556
423788c7 1557 if (adev->dm.dc) {
76121231 1558 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 1559 } else {
76121231 1560 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 1561 goto error;
1562 }
4562236b 1563
8a791dab
HW		 1564 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1565 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1566 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1567 }
1568
f99d8762
HW		 1569 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1570 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
3ce51649
AD		 1571 if (dm_should_disable_stutter(adev->pdev))
1572 adev->dm.dc->debug.disable_stutter = true;
f99d8762 1573
8a791dab
HW		 1574 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1575 adev->dm.dc->debug.disable_stutter = true;
1576
2665f63a 1577 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
8a791dab 1578 adev->dm.dc->debug.disable_dsc = true;
2665f63a 1579 }
8a791dab
HW		 1580
1581 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1582 adev->dm.dc->debug.disable_clock_gate = true;
1583
cfb979f7
AP		 1584 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1585 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1586
792a0cdd
LL		 1587 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1588
d1bc26cb
FZ		 1589 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1590 adev->dm.dc->debug.ignore_cable_id = true;
1591
743b9786
NK		 1592 r = dm_dmub_hw_init(adev);
1593 if (r) {
1594 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1595 goto error;
1596 }
1597
bb6785c1
NK		 1598 dc_hardware_init(adev->dm.dc);
1599
8e794421
WL		 1600 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1601 if (!adev->dm.hpd_rx_offload_wq) {
1602 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1603 goto error;
1604 }
1605
3ca001af 1606 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
e6cd859d
AD		 1607 struct dc_phy_addr_space_config pa_config;
1608
0b08c54b 1609 mmhub_read_system_context(adev, &pa_config);
c0fb85ae 1610
0b08c54b
YZ		 1611 // Call the DC init_memory func
1612 dc_setup_system_context(adev->dm.dc, &pa_config);
1613 }
c0fb85ae 1614
4562236b
HW		 1615 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1616 if (!adev->dm.freesync_module) {
1617 DRM_ERROR(
1618 "amdgpu: failed to initialize freesync_module.\n");
1619 } else
f1ad2f5e 1620 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 1621 adev->dm.freesync_module);
1622
e277adc5
LSL		 1623 amdgpu_dm_init_color_mod();
1624
ea3b4242 1625 if (adev->dm.dc->caps.max_links > 0) {
09a5df6c
NK		 1626 adev->dm.vblank_control_workqueue =
1627 create_singlethread_workqueue("dm_vblank_control_workqueue");
1628 if (!adev->dm.vblank_control_workqueue)
ea3b4242 1629 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
ea3b4242 1630 }
ea3b4242 1631
52704fca 1632#ifdef CONFIG_DRM_AMD_DC_HDCP
c08182f2 1633 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
e50dc171 1634 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
52704fca 1635
96a3b32e
BL		 1636 if (!adev->dm.hdcp_workqueue)
1637 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1638 else
1639 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
52704fca 1640
96a3b32e
BL		 1641 dc_init_callbacks(adev->dm.dc, &init_params);
1642 }
9a65df19
WL		 1643#endif
1644#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
b8ff7e08 1645 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
cbd8f20b
AL		 1646 if (!adev->dm.secure_display_ctxs) {
1647 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1648 }
52704fca 1649#endif
11d526f1 1650 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
81927e28
JS		 1651 init_completion(&adev->dm.dmub_aux_transfer_done);
1652 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1653 if (!adev->dm.dmub_notify) {
1654 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1655 goto error;
1656 }
e27c41d5
JS		 1657
1658 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1659 if (!adev->dm.delayed_hpd_wq) {
1660 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1661 goto error;
1662 }
1663
81927e28 1664 amdgpu_dm_outbox_init(adev);
e27c41d5
JS		 1665 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1666 dmub_aux_setconfig_callback, false)) {
1667 DRM_ERROR("amdgpu: fail to register dmub aux callback");
1668 goto error;
1669 }
1670 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1671 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1672 goto error;
1673 }
c40a09e5
NK		 1674 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1675 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1676 goto error;
1677 }
81927e28
JS		 1678 }
1679
11d526f1
SW		 1680 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1681 * It is expected that DMUB will resend any pending notifications at this point, for
1682 * example HPD from DPIA.
1683 */
1684 if (dc_is_dmub_outbox_supported(adev->dm.dc))
1685 dc_enable_dmub_outbox(adev->dm.dc);
1686
1c43a48b
SW		 1687 if (amdgpu_dm_initialize_drm_device(adev)) {
1688 DRM_ERROR(
1689 "amdgpu: failed to initialize sw for display support.\n");
1690 goto error;
1691 }
1692
f74367e4
AD		 1693 /* create fake encoders for MST */
1694 dm_dp_create_fake_mst_encoders(adev);
1695
4562236b
HW		 1696 /* TODO: Add_display_info? */
1697
1698 /* TODO use dynamic cursor width */
4a580877
LT		 1699 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1700 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b 1701
4a580877 1702 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
4562236b
HW		 1703 DRM_ERROR(
1704 "amdgpu: failed to initialize sw for display support.\n");
1705 goto error;
1706 }
1707
c0fb85ae 1708
f1ad2f5e 1709 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 1710
1711 return 0;
1712error:
1713 amdgpu_dm_fini(adev);
1714
59d0f396 1715 return -EINVAL;
4562236b
HW		 1716}
1717
e9669fb7
AG		 1718static int amdgpu_dm_early_fini(void *handle)
1719{
1720 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1721
1722 amdgpu_dm_audio_fini(adev);
1723
1724 return 0;
1725}
1726
7578ecda 1727static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b 1728{
f74367e4
AD		 1729 int i;
1730
09a5df6c
NK		 1731 if (adev->dm.vblank_control_workqueue) {
1732 destroy_workqueue(adev->dm.vblank_control_workqueue);
1733 adev->dm.vblank_control_workqueue = NULL;
1734 }
09a5df6c 1735
f74367e4
AD		 1736 for (i = 0; i < adev->dm.display_indexes_num; i++) {
1737 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
1738 }
1739
4562236b 1740 amdgpu_dm_destroy_drm_device(&adev->dm);
c8bdf2b6 1741
9a65df19 1742#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1b11ff76
AL		 1743 if (adev->dm.secure_display_ctxs) {
1744 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1745 if (adev->dm.secure_display_ctxs[i].crtc) {
1746 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1747 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1748 }
1749 }
1750 kfree(adev->dm.secure_display_ctxs);
1751 adev->dm.secure_display_ctxs = NULL;
9a65df19
WL		 1752 }
1753#endif
52704fca
BL		 1754#ifdef CONFIG_DRM_AMD_DC_HDCP
1755 if (adev->dm.hdcp_workqueue) {
e96b1b29 1756 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
52704fca
BL		 1757 adev->dm.hdcp_workqueue = NULL;
1758 }
1759
1760 if (adev->dm.dc)
1761 dc_deinit_callbacks(adev->dm.dc);
1762#endif
51ba6912 1763
3beac533 1764 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
9a71c7d3 1765
81927e28
JS		 1766 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1767 kfree(adev->dm.dmub_notify);
1768 adev->dm.dmub_notify = NULL;
e27c41d5
JS		 1769 destroy_workqueue(adev->dm.delayed_hpd_wq);
1770 adev->dm.delayed_hpd_wq = NULL;
81927e28
JS		 1771 }
1772
743b9786
NK		 1773 if (adev->dm.dmub_bo)
1774 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1775 &adev->dm.dmub_bo_gpu_addr,
1776 &adev->dm.dmub_bo_cpu_addr);
52704fca 1777
006c26a0
AG		 1778 if (adev->dm.hpd_rx_offload_wq) {
1779 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1780 if (adev->dm.hpd_rx_offload_wq[i].wq) {
1781 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1782 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1783 }
1784 }
1785
1786 kfree(adev->dm.hpd_rx_offload_wq);
1787 adev->dm.hpd_rx_offload_wq = NULL;
1788 }
1789
c8bdf2b6
ED		 1790 /* DC Destroy TODO: Replace destroy DAL */
1791 if (adev->dm.dc)
1792 dc_destroy(&adev->dm.dc);
4562236b
HW		 1793 /*
1794 * TODO: pageflip, vlank interrupt
1795 *
1796 * amdgpu_dm_irq_fini(adev);
1797 */
1798
1799 if (adev->dm.cgs_device) {
1800 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1801 adev->dm.cgs_device = NULL;
1802 }
1803 if (adev->dm.freesync_module) {
1804 mod_freesync_destroy(adev->dm.freesync_module);
1805 adev->dm.freesync_module = NULL;
1806 }
674e78ac 1807
6ce8f316 1808 mutex_destroy(&adev->dm.audio_lock);
674e78ac 1809 mutex_destroy(&adev->dm.dc_lock);
ead08b95 1810 mutex_destroy(&adev->dm.dpia_aux_lock);
674e78ac 1811
4562236b
HW		 1812 return;
1813}
1814
a94d5569 1815static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 1816{
a7669aff 1817 const char *fw_name_dmcu = NULL;
a94d5569
DF		 1818 int r;
1819 const struct dmcu_firmware_header_v1_0 *hdr;
1820
1821 switch(adev->asic_type) {
55e56389
MR		 1822#if defined(CONFIG_DRM_AMD_DC_SI)
1823 case CHIP_TAHITI:
1824 case CHIP_PITCAIRN:
1825 case CHIP_VERDE:
1826 case CHIP_OLAND:
1827#endif
a94d5569
DF		 1828 case CHIP_BONAIRE:
1829 case CHIP_HAWAII:
1830 case CHIP_KAVERI:
1831 case CHIP_KABINI:
1832 case CHIP_MULLINS:
1833 case CHIP_TONGA:
1834 case CHIP_FIJI:
1835 case CHIP_CARRIZO:
1836 case CHIP_STONEY:
1837 case CHIP_POLARIS11:
1838 case CHIP_POLARIS10:
1839 case CHIP_POLARIS12:
1840 case CHIP_VEGAM:
1841 case CHIP_VEGA10:
1842 case CHIP_VEGA12:
1843 case CHIP_VEGA20:
1844 return 0;
5ea23931
RL		 1845 case CHIP_NAVI12:
1846 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1847 break;
a94d5569 1848 case CHIP_RAVEN:
a7669aff
HW		 1849 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1850 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1851 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1852 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1853 else
a7669aff 1854 return 0;
a94d5569
DF		 1855 break;
1856 default:
1d789535 1857 switch (adev->ip_versions[DCE_HWIP][0]) {
c08182f2
AD		 1858 case IP_VERSION(2, 0, 2):
1859 case IP_VERSION(2, 0, 3):
1860 case IP_VERSION(2, 0, 0):
1861 case IP_VERSION(2, 1, 0):
1862 case IP_VERSION(3, 0, 0):
1863 case IP_VERSION(3, 0, 2):
1864 case IP_VERSION(3, 0, 3):
1865 case IP_VERSION(3, 0, 1):
1866 case IP_VERSION(3, 1, 2):
1867 case IP_VERSION(3, 1, 3):
f3cd57e4 1868 case IP_VERSION(3, 1, 4):
b5b8ed44 1869 case IP_VERSION(3, 1, 5):
de7cc1b4 1870 case IP_VERSION(3, 1, 6):
577359ca
AP		 1871 case IP_VERSION(3, 2, 0):
1872 case IP_VERSION(3, 2, 1):
c08182f2
AD		 1873 return 0;
1874 default:
1875 break;
1876 }
a94d5569 1877 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 1878 return -EINVAL;
a94d5569
DF		 1879 }
1880
1881 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1882 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1883 return 0;
1884 }
1885
1886 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1887 if (r == -ENOENT) {
1888 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1889 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1890 adev->dm.fw_dmcu = NULL;
1891 return 0;
1892 }
1893 if (r) {
1894 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1895 fw_name_dmcu);
1896 return r;
1897 }
1898
1899 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1900 if (r) {
1901 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1902 fw_name_dmcu);
51526637 1903 amdgpu_ucode_release(&adev->dm.fw_dmcu);
a94d5569
DF		 1904 return r;
1905 }
1906
1907 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1908 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1909 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1910 adev->firmware.fw_size +=
1911 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1912
1913 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1914 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1915 adev->firmware.fw_size +=
1916 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1917
ee6e89c0
DF		 1918 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1919
a94d5569
DF		 1920 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1921
4562236b
HW		 1922 return 0;
1923}
1924
743b9786
NK		 1925static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1926{
1927 struct amdgpu_device *adev = ctx;
1928
1929 return dm_read_reg(adev->dm.dc->ctx, address);
1930}
1931
1932static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1933 uint32_t value)
1934{
1935 struct amdgpu_device *adev = ctx;
1936
1937 return dm_write_reg(adev->dm.dc->ctx, address, value);
1938}
1939
1940static int dm_dmub_sw_init(struct amdgpu_device *adev)
1941{
1942 struct dmub_srv_create_params create_params;
8c7aea40
NK		 1943 struct dmub_srv_region_params region_params;
1944 struct dmub_srv_region_info region_info;
1945 struct dmub_srv_fb_params fb_params;
1946 struct dmub_srv_fb_info *fb_info;
1947 struct dmub_srv *dmub_srv;
743b9786 1948 const struct dmcub_firmware_header_v1_0 *hdr;
743b9786
NK		 1949 enum dmub_asic dmub_asic;
1950 enum dmub_status status;
1951 int r;
1952
1d789535 1953 switch (adev->ip_versions[DCE_HWIP][0]) {
c08182f2 1954 case IP_VERSION(2, 1, 0):
743b9786 1955 dmub_asic = DMUB_ASIC_DCN21;
743b9786 1956 break;
c08182f2 1957 case IP_VERSION(3, 0, 0):
a7ab3451 1958 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
c08182f2 1959 dmub_asic = DMUB_ASIC_DCN30;
a7ab3451 1960 else
c08182f2 1961 dmub_asic = DMUB_ASIC_DCN30;
79037324 1962 break;
c08182f2 1963 case IP_VERSION(3, 0, 1):
469989ca 1964 dmub_asic = DMUB_ASIC_DCN301;
469989ca 1965 break;
c08182f2 1966 case IP_VERSION(3, 0, 2):
2a411205 1967 dmub_asic = DMUB_ASIC_DCN302;
2a411205 1968 break;
c08182f2 1969 case IP_VERSION(3, 0, 3):
656fe9b6 1970 dmub_asic = DMUB_ASIC_DCN303;
656fe9b6 1971 break;
c08182f2
AD		 1972 case IP_VERSION(3, 1, 2):
1973 case IP_VERSION(3, 1, 3):
3137f792 1974 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
1ebcaebd 1975 break;
e850f6b1
RL		 1976 case IP_VERSION(3, 1, 4):
1977 dmub_asic = DMUB_ASIC_DCN314;
e850f6b1 1978 break;
b5b8ed44
QZ		 1979 case IP_VERSION(3, 1, 5):
1980 dmub_asic = DMUB_ASIC_DCN315;
b5b8ed44 1981 break;
de7cc1b4 1982 case IP_VERSION(3, 1, 6):
868f4357 1983 dmub_asic = DMUB_ASIC_DCN316;
de7cc1b4 1984 break;
577359ca
AP		 1985 case IP_VERSION(3, 2, 0):
1986 dmub_asic = DMUB_ASIC_DCN32;
577359ca
AP		 1987 break;
1988 case IP_VERSION(3, 2, 1):
1989 dmub_asic = DMUB_ASIC_DCN321;
577359ca 1990 break;
743b9786
NK		 1991 default:
1992 /* ASIC doesn't support DMUB. */
1993 return 0;
1994 }
1995
743b9786 1996 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
72a74a18 1997 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
743b9786 1998
9a6ed547
NK		 1999 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2000 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2001 AMDGPU_UCODE_ID_DMCUB;
2002 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2003 adev->dm.dmub_fw;
2004 adev->firmware.fw_size +=
2005 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
743b9786 2006
9a6ed547
NK		 2007 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2008 adev->dm.dmcub_fw_version);
2009 }
2010
743b9786 2011
8c7aea40
NK		 2012 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2013 dmub_srv = adev->dm.dmub_srv;
2014
2015 if (!dmub_srv) {
2016 DRM_ERROR("Failed to allocate DMUB service!\n");
2017 return -ENOMEM;
2018 }
2019
2020 memset(&create_params, 0, sizeof(create_params));
2021 create_params.user_ctx = adev;
2022 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2023 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2024 create_params.asic = dmub_asic;
2025
2026 /* Create the DMUB service. */
2027 status = dmub_srv_create(dmub_srv, &create_params);
2028 if (status != DMUB_STATUS_OK) {
2029 DRM_ERROR("Error creating DMUB service: %d\n", status);
2030 return -EINVAL;
2031 }
2032
2033 /* Calculate the size of all the regions for the DMUB service. */
2034 memset(&region_params, 0, sizeof(region_params));
2035
2036 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2037 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2038 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2039 region_params.vbios_size = adev->bios_size;
0922b899 2040 region_params.fw_bss_data = region_params.bss_data_size ?
1f0674fd
NK		 2041 adev->dm.dmub_fw->data +
2042 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
0922b899 2043 le32_to_cpu(hdr->inst_const_bytes) : NULL;
a576b345
NK		 2044 region_params.fw_inst_const =
2045 adev->dm.dmub_fw->data +
2046 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2047 PSP_HEADER_BYTES;
8c7aea40
NK		 2048
2049 status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2050 &region_info);
2051
2052 if (status != DMUB_STATUS_OK) {
2053 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2054 return -EINVAL;
2055 }
2056
2057 /*
2058 * Allocate a framebuffer based on the total size of all the regions.
2059 * TODO: Move this into GART.
2060 */
2061 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
58ab2c08
CK		 2062 AMDGPU_GEM_DOMAIN_VRAM |
2063 AMDGPU_GEM_DOMAIN_GTT,
2064 &adev->dm.dmub_bo,
8c7aea40
NK		 2065 &adev->dm.dmub_bo_gpu_addr,
2066 &adev->dm.dmub_bo_cpu_addr);
2067 if (r)
2068 return r;
2069
2070 /* Rebase the regions on the framebuffer address. */
2071 memset(&fb_params, 0, sizeof(fb_params));
2072 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2073 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2074 fb_params.region_info = &region_info;
2075
2076 adev->dm.dmub_fb_info =
2077 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2078 fb_info = adev->dm.dmub_fb_info;
2079
2080 if (!fb_info) {
2081 DRM_ERROR(
2082 "Failed to allocate framebuffer info for DMUB service!\n");
2083 return -ENOMEM;
2084 }
2085
2086 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2087 if (status != DMUB_STATUS_OK) {
2088 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2089 return -EINVAL;
2090 }
2091
743b9786
NK		 2092 return 0;
2093}
2094
a94d5569
DF		 2095static int dm_sw_init(void *handle)
2096{
2097 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
743b9786
NK		 2098 int r;
2099
2100 r = dm_dmub_sw_init(adev);
2101 if (r)
2102 return r;
a94d5569
DF		 2103
2104 return load_dmcu_fw(adev);
2105}
2106
4562236b
HW		 2107static int dm_sw_fini(void *handle)
2108{
a94d5569
DF		 2109 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2110
8c7aea40
NK		 2111 kfree(adev->dm.dmub_fb_info);
2112 adev->dm.dmub_fb_info = NULL;
2113
743b9786
NK		 2114 if (adev->dm.dmub_srv) {
2115 dmub_srv_destroy(adev->dm.dmub_srv);
2116 adev->dm.dmub_srv = NULL;
2117 }
2118
51526637
ML		 2119 amdgpu_ucode_release(&adev->dm.dmub_fw);
2120 amdgpu_ucode_release(&adev->dm.fw_dmcu);
a94d5569 2121
4562236b
HW		 2122 return 0;
2123}
2124
7abcf6b5 2125static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 2126{
c84dec2f 2127 struct amdgpu_dm_connector *aconnector;
4562236b 2128 struct drm_connector *connector;
f8d2d39e 2129 struct drm_connector_list_iter iter;
7abcf6b5 2130 int ret = 0;
4562236b 2131
f8d2d39e
LP		 2132 drm_connector_list_iter_begin(dev, &iter);
2133 drm_for_each_connector_iter(connector, &iter) {
b349f76e 2134 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 2135 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2136 aconnector->mst_mgr.aux) {
f1ad2f5e 2137 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
f8d2d39e
LP		 2138 aconnector,
2139 aconnector->base.base.id);
7abcf6b5
AG		 2140
2141 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2142 if (ret < 0) {
2143 DRM_ERROR("DM_MST: Failed to start MST\n");
f8d2d39e
LP		 2144 aconnector->dc_link->type =
2145 dc_connection_single;
3f6752b4
RL		 2146 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2147 aconnector->dc_link);
f8d2d39e 2148 break;
7abcf6b5 2149 }
f8d2d39e 2150 }
4562236b 2151 }
f8d2d39e 2152 drm_connector_list_iter_end(&iter);
4562236b 2153
7abcf6b5
AG		 2154 return ret;
2155}
2156
2157static int dm_late_init(void *handle)
2158{
42e67c3b 2159 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 2160
bbf854dc
DF		 2161 struct dmcu_iram_parameters params;
2162 unsigned int linear_lut[16];
2163 int i;
17bdb4a8 2164 struct dmcu *dmcu = NULL;
bbf854dc 2165
17bdb4a8
JFZ		 2166 dmcu = adev->dm.dc->res_pool->dmcu;
2167
bbf854dc
DF		 2168 for (i = 0; i < 16; i++)
2169 linear_lut[i] = 0xFFFF * i / 15;
2170
2171 params.set = 0;
75068994 2172 params.backlight_ramping_override = false;
bbf854dc
DF		 2173 params.backlight_ramping_start = 0xCCCC;
2174 params.backlight_ramping_reduction = 0xCCCCCCCC;
2175 params.backlight_lut_array_size = 16;
2176 params.backlight_lut_array = linear_lut;
2177
2ad0cdf9
AK		 2178 /* Min backlight level after ABM reduction, Don't allow below 1%
2179 * 0xFFFF x 0.01 = 0x28F
2180 */
2181 params.min_abm_backlight = 0x28F;
5cb32419 2182 /* In the case where abm is implemented on dmcub,
6e568e43
JW		 2183 * dmcu object will be null.
2184 * ABM 2.4 and up are implemented on dmcub.
2185 */
2186 if (dmcu) {
2187 if (!dmcu_load_iram(dmcu, params))
2188 return -EINVAL;
2189 } else if (adev->dm.dc->ctx->dmub_srv) {
2190 struct dc_link *edp_links[MAX_NUM_EDP];
2191 int edp_num;
bbf854dc 2192
6e568e43
JW		 2193 get_edp_links(adev->dm.dc, edp_links, &edp_num);
2194 for (i = 0; i < edp_num; i++) {
2195 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2196 return -EINVAL;
2197 }
2198 }
bbf854dc 2199
4a580877 2200 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
4562236b
HW		 2201}
2202
2203static void s3_handle_mst(struct drm_device *dev, bool suspend)
2204{
c84dec2f 2205 struct amdgpu_dm_connector *aconnector;
4562236b 2206 struct drm_connector *connector;
f8d2d39e 2207 struct drm_connector_list_iter iter;
fe7553be
LP		 2208 struct drm_dp_mst_topology_mgr *mgr;
2209 int ret;
2210 bool need_hotplug = false;
4562236b 2211
f8d2d39e
LP		 2212 drm_connector_list_iter_begin(dev, &iter);
2213 drm_for_each_connector_iter(connector, &iter) {
fe7553be
LP		 2214 aconnector = to_amdgpu_dm_connector(connector);
2215 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2216 aconnector->mst_port)
2217 continue;
2218
2219 mgr = &aconnector->mst_mgr;
2220
2221 if (suspend) {
2222 drm_dp_mst_topology_mgr_suspend(mgr);
2223 } else {
6f85f738 2224 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
fe7553be 2225 if (ret < 0) {
84a8b390
WL		 2226 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2227 aconnector->dc_link);
fe7553be
LP		 2228 need_hotplug = true;
2229 }
2230 }
4562236b 2231 }
f8d2d39e 2232 drm_connector_list_iter_end(&iter);
fe7553be
LP		 2233
2234 if (need_hotplug)
2235 drm_kms_helper_hotplug_event(dev);
4562236b
HW		 2236}
2237
9340dfd3
HW		 2238static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2239{
9340dfd3
HW		 2240 int ret = 0;
2241
9340dfd3
HW		 2242 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2243 * on window driver dc implementation.
2244 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2245 * should be passed to smu during boot up and resume from s3.
2246 * boot up: dc calculate dcn watermark clock settings within dc_create,
2247 * dcn20_resource_construct
2248 * then call pplib functions below to pass the settings to smu:
2249 * smu_set_watermarks_for_clock_ranges
2250 * smu_set_watermarks_table
2251 * navi10_set_watermarks_table
2252 * smu_write_watermarks_table
2253 *
2254 * For Renoir, clock settings of dcn watermark are also fixed values.
2255 * dc has implemented different flow for window driver:
2256 * dc_hardware_init / dc_set_power_state
2257 * dcn10_init_hw
2258 * notify_wm_ranges
2259 * set_wm_ranges
2260 * -- Linux
2261 * smu_set_watermarks_for_clock_ranges
2262 * renoir_set_watermarks_table
2263 * smu_write_watermarks_table
2264 *
2265 * For Linux,
2266 * dc_hardware_init -> amdgpu_dm_init
2267 * dc_set_power_state --> dm_resume
2268 *
2269 * therefore, this function apply to navi10/12/14 but not Renoir
2270 * *
2271 */
1d789535 2272 switch (adev->ip_versions[DCE_HWIP][0]) {
c08182f2
AD		 2273 case IP_VERSION(2, 0, 2):
2274 case IP_VERSION(2, 0, 0):
9340dfd3
HW		 2275 break;
2276 default:
2277 return 0;
2278 }
2279
13f5dbd6 2280 ret = amdgpu_dpm_write_watermarks_table(adev);
e7a95eea
EQ		 2281 if (ret) {
2282 DRM_ERROR("Failed to update WMTABLE!\n");
2283 return ret;
9340dfd3
HW		 2284 }
2285
9340dfd3
HW		 2286 return 0;
2287}
2288
b8592b48
LL		 2289/**
2290 * dm_hw_init() - Initialize DC device
28d687ea 2291 * @handle: The base driver device containing the amdgpu_dm device.
b8592b48
LL		 2292 *
2293 * Initialize the &struct amdgpu_display_manager device. This involves calling
2294 * the initializers of each DM component, then populating the struct with them.
2295 *
2296 * Although the function implies hardware initialization, both hardware and
2297 * software are initialized here. Splitting them out to their relevant init
2298 * hooks is a future TODO item.
2299 *
2300 * Some notable things that are initialized here:
2301 *
2302 * - Display Core, both software and hardware
2303 * - DC modules that we need (freesync and color management)
2304 * - DRM software states
2305 * - Interrupt sources and handlers
2306 * - Vblank support
2307 * - Debug FS entries, if enabled
2308 */
4562236b
HW		 2309static int dm_hw_init(void *handle)
2310{
2311 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2312 /* Create DAL display manager */
2313 amdgpu_dm_init(adev);
4562236b
HW		 2314 amdgpu_dm_hpd_init(adev);
2315
4562236b
HW		 2316 return 0;
2317}
2318
b8592b48
LL		 2319/**
2320 * dm_hw_fini() - Teardown DC device
28d687ea 2321 * @handle: The base driver device containing the amdgpu_dm device.
b8592b48
LL		 2322 *
2323 * Teardown components within &struct amdgpu_display_manager that require
2324 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2325 * were loaded. Also flush IRQ workqueues and disable them.
2326 */
4562236b
HW		 2327static int dm_hw_fini(void *handle)
2328{
2329 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2330
2331 amdgpu_dm_hpd_fini(adev);
2332
2333 amdgpu_dm_irq_fini(adev);
21de3396 2334 amdgpu_dm_fini(adev);
4562236b
HW		 2335 return 0;
2336}
2337
cdaae837 2338
cdaae837
BL		 2339static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2340 struct dc_state *state, bool enable)
2341{
2342 enum dc_irq_source irq_source;
2343 struct amdgpu_crtc *acrtc;
2344 int rc = -EBUSY;
2345 int i = 0;
2346
2347 for (i = 0; i < state->stream_count; i++) {
2348 acrtc = get_crtc_by_otg_inst(
2349 adev, state->stream_status[i].primary_otg_inst);
2350
2351 if (acrtc && state->stream_status[i].plane_count != 0) {
2352 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2353 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
4711c033
LT		 2354 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2355 acrtc->crtc_id, enable ? "en" : "dis", rc);
cdaae837
BL		 2356 if (rc)
2357 DRM_WARN("Failed to %s pflip interrupts\n",
2358 enable ? "enable" : "disable");
2359
2360 if (enable) {
2361 rc = dm_enable_vblank(&acrtc->base);
2362 if (rc)
2363 DRM_WARN("Failed to enable vblank interrupts\n");
2364 } else {
2365 dm_disable_vblank(&acrtc->base);
2366 }
2367
2368 }
2369 }
2370
2371}
2372
dfd84d90 2373static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
cdaae837
BL		 2374{
2375 struct dc_state *context = NULL;
2376 enum dc_status res = DC_ERROR_UNEXPECTED;
2377 int i;
2378 struct dc_stream_state *del_streams[MAX_PIPES];
2379 int del_streams_count = 0;
2380
2381 memset(del_streams, 0, sizeof(del_streams));
2382
2383 context = dc_create_state(dc);
2384 if (context == NULL)
2385 goto context_alloc_fail;
2386
2387 dc_resource_state_copy_construct_current(dc, context);
2388
2389 /* First remove from context all streams */
2390 for (i = 0; i < context->stream_count; i++) {
2391 struct dc_stream_state *stream = context->streams[i];
2392
2393 del_streams[del_streams_count++] = stream;
2394 }
2395
2396 /* Remove all planes for removed streams and then remove the streams */
2397 for (i = 0; i < del_streams_count; i++) {
2398 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2399 res = DC_FAIL_DETACH_SURFACES;
2400 goto fail;
2401 }
2402
2403 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2404 if (res != DC_OK)
2405 goto fail;
2406 }
2407
cdaae837
BL		 2408 res = dc_commit_state(dc, context);
2409
2410fail:
2411 dc_release_state(context);
2412
2413context_alloc_fail:
2414 return res;
2415}
2416
8e794421
WL		 2417static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2418{
2419 int i;
2420
2421 if (dm->hpd_rx_offload_wq) {
2422 for (i = 0; i < dm->dc->caps.max_links; i++)
2423 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2424 }
2425}
2426
4562236b
HW		 2427static int dm_suspend(void *handle)
2428{
2429 struct amdgpu_device *adev = handle;
2430 struct amdgpu_display_manager *dm = &adev->dm;
2431 int ret = 0;
4562236b 2432
53b3f8f4 2433 if (amdgpu_in_reset(adev)) {
cdaae837 2434 mutex_lock(&dm->dc_lock);
98ab5f35 2435
98ab5f35 2436 dc_allow_idle_optimizations(adev->dm.dc, false);
98ab5f35 2437
cdaae837
BL		 2438 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2439
2440 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2441
2442 amdgpu_dm_commit_zero_streams(dm->dc);
2443
2444 amdgpu_dm_irq_suspend(adev);
2445
8e794421
WL		 2446 hpd_rx_irq_work_suspend(dm);
2447
cdaae837
BL		 2448 return ret;
2449 }
4562236b 2450
d2f0b53b 2451 WARN_ON(adev->dm.cached_state);
4a580877 2452 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
d2f0b53b 2453
4a580877 2454 s3_handle_mst(adev_to_drm(adev), true);
4562236b 2455
4562236b
HW		 2456 amdgpu_dm_irq_suspend(adev);
2457
8e794421
WL		 2458 hpd_rx_irq_work_suspend(dm);
2459
32f5062d 2460 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b 2461
1c2075d4 2462 return 0;
4562236b
HW		 2463}
2464
17ce8a69 2465struct amdgpu_dm_connector *
1daf8c63
AD		 2466amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2467 struct drm_crtc *crtc)
4562236b 2468{
ae67558b 2469 u32 i;
c2cea706 2470 struct drm_connector_state *new_con_state;
4562236b
HW		 2471 struct drm_connector *connector;
2472 struct drm_crtc *crtc_from_state;
2473
c2cea706
LSL		 2474 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2475 crtc_from_state = new_con_state->crtc;
4562236b
HW		 2476
2477 if (crtc_from_state == crtc)
c84dec2f 2478 return to_amdgpu_dm_connector(connector);
4562236b
HW		 2479 }
2480
2481 return NULL;
2482}
2483
fbbdadf2
BL		 2484static void emulated_link_detect(struct dc_link *link)
2485{
2486 struct dc_sink_init_data sink_init_data = { 0 };
2487 struct display_sink_capability sink_caps = { 0 };
2488 enum dc_edid_status edid_status;
2489 struct dc_context *dc_ctx = link->ctx;
2490 struct dc_sink *sink = NULL;
2491 struct dc_sink *prev_sink = NULL;
2492
2493 link->type = dc_connection_none;
2494 prev_sink = link->local_sink;
2495
30164a16
VL		 2496 if (prev_sink)
2497 dc_sink_release(prev_sink);
fbbdadf2
BL		 2498
2499 switch (link->connector_signal) {
2500 case SIGNAL_TYPE_HDMI_TYPE_A: {
2501 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2502 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2503 break;
2504 }
2505
2506 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2507 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2508 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2509 break;
2510 }
2511
2512 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2513 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2514 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2515 break;
2516 }
2517
2518 case SIGNAL_TYPE_LVDS: {
2519 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2520 sink_caps.signal = SIGNAL_TYPE_LVDS;
2521 break;
2522 }
2523
2524 case SIGNAL_TYPE_EDP: {
2525 sink_caps.transaction_type =
2526 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2527 sink_caps.signal = SIGNAL_TYPE_EDP;
2528 break;
2529 }
2530
2531 case SIGNAL_TYPE_DISPLAY_PORT: {
2532 sink_caps.transaction_type =
2533 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2534 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2535 break;
2536 }
2537
2538 default:
2539 DC_ERROR("Invalid connector type! signal:%d\n",
2540 link->connector_signal);
2541 return;
2542 }
2543
2544 sink_init_data.link = link;
2545 sink_init_data.sink_signal = sink_caps.signal;
2546
2547 sink = dc_sink_create(&sink_init_data);
2548 if (!sink) {
2549 DC_ERROR("Failed to create sink!\n");
2550 return;
2551 }
2552
dcd5fb82 2553 /* dc_sink_create returns a new reference */
fbbdadf2
BL		 2554 link->local_sink = sink;
2555
2556 edid_status = dm_helpers_read_local_edid(
2557 link->ctx,
2558 link,
2559 sink);
2560
2561 if (edid_status != EDID_OK)
2562 DC_ERROR("Failed to read EDID");
2563
2564}
2565
cdaae837
BL		 2566static void dm_gpureset_commit_state(struct dc_state *dc_state,
2567 struct amdgpu_display_manager *dm)
2568{
2569 struct {
2570 struct dc_surface_update surface_updates[MAX_SURFACES];
2571 struct dc_plane_info plane_infos[MAX_SURFACES];
2572 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2573 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2574 struct dc_stream_update stream_update;
2575 } * bundle;
2576 int k, m;
2577
2578 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2579
2580 if (!bundle) {
2581 dm_error("Failed to allocate update bundle\n");
2582 goto cleanup;
2583 }
2584
2585 for (k = 0; k < dc_state->stream_count; k++) {
2586 bundle->stream_update.stream = dc_state->streams[k];
2587
2588 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2589 bundle->surface_updates[m].surface =
2590 dc_state->stream_status->plane_states[m];
2591 bundle->surface_updates[m].surface->force_full_update =
2592 true;
2593 }
2594 dc_commit_updates_for_stream(
2595 dm->dc, bundle->surface_updates,
2596 dc_state->stream_status->plane_count,
efc8278e 2597 dc_state->streams[k], &bundle->stream_update, dc_state);
cdaae837
BL		 2598 }
2599
2600cleanup:
2601 kfree(bundle);
2602
2603 return;
2604}
2605
4562236b
HW		 2606static int dm_resume(void *handle)
2607{
2608 struct amdgpu_device *adev = handle;
4a580877 2609 struct drm_device *ddev = adev_to_drm(adev);
4562236b 2610 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 2611 struct amdgpu_dm_connector *aconnector;
4562236b 2612 struct drm_connector *connector;
f8d2d39e 2613 struct drm_connector_list_iter iter;
4562236b 2614 struct drm_crtc *crtc;
c2cea706 2615 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 2616 struct dm_crtc_state *dm_new_crtc_state;
2617 struct drm_plane *plane;
2618 struct drm_plane_state *new_plane_state;
2619 struct dm_plane_state *dm_new_plane_state;
113b7a01 2620 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
fbbdadf2 2621 enum dc_connection_type new_connection_type = dc_connection_none;
cdaae837
BL		 2622 struct dc_state *dc_state;
2623 int i, r, j;
4562236b 2624
53b3f8f4 2625 if (amdgpu_in_reset(adev)) {
cdaae837
BL		 2626 dc_state = dm->cached_dc_state;
2627
6d63fcc2
NK		 2628 /*
2629 * The dc->current_state is backed up into dm->cached_dc_state
2630 * before we commit 0 streams.
2631 *
2632 * DC will clear link encoder assignments on the real state
2633 * but the changes won't propagate over to the copy we made
2634 * before the 0 streams commit.
2635 *
2636 * DC expects that link encoder assignments are *not* valid
32685b32
NK		 2637 * when committing a state, so as a workaround we can copy
2638 * off of the current state.
2639 *
2640 * We lose the previous assignments, but we had already
2641 * commit 0 streams anyway.
6d63fcc2 2642 */
32685b32 2643 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
6d63fcc2 2644
cdaae837
BL		 2645 r = dm_dmub_hw_init(adev);
2646 if (r)
2647 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2648
2649 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2650 dc_resume(dm->dc);
2651
2652 amdgpu_dm_irq_resume_early(adev);
2653
2654 for (i = 0; i < dc_state->stream_count; i++) {
2655 dc_state->streams[i]->mode_changed = true;
6984fa41
NK		 2656 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2657 dc_state->stream_status[i].plane_states[j]->update_flags.raw
cdaae837
BL		 2658 = 0xffffffff;
2659 }
2660 }
2661
11d526f1
SW		 2662 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2663 amdgpu_dm_outbox_init(adev);
2664 dc_enable_dmub_outbox(adev->dm.dc);
2665 }
2666
cdaae837 2667 WARN_ON(!dc_commit_state(dm->dc, dc_state));
4562236b 2668
cdaae837
BL		 2669 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2670
2671 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2672
2673 dc_release_state(dm->cached_dc_state);
2674 dm->cached_dc_state = NULL;
2675
2676 amdgpu_dm_irq_resume_late(adev);
2677
2678 mutex_unlock(&dm->dc_lock);
2679
2680 return 0;
2681 }
113b7a01
LL		 2682 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2683 dc_release_state(dm_state->context);
2684 dm_state->context = dc_create_state(dm->dc);
2685 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2686 dc_resource_state_construct(dm->dc, dm_state->context);
2687
8c7aea40 2688 /* Before powering on DC we need to re-initialize DMUB. */
79d6b935 2689 dm_dmub_hw_resume(adev);
8c7aea40 2690
11d526f1
SW		 2691 /* Re-enable outbox interrupts for DPIA. */
2692 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2693 amdgpu_dm_outbox_init(adev);
2694 dc_enable_dmub_outbox(adev->dm.dc);
2695 }
2696
a80aa93d
ML		 2697 /* power on hardware */
2698 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2699
4562236b
HW		 2700 /* program HPD filter */
2701 dc_resume(dm->dc);
2702
4562236b
HW		 2703 /*
2704 * early enable HPD Rx IRQ, should be done before set mode as short
2705 * pulse interrupts are used for MST
2706 */
2707 amdgpu_dm_irq_resume_early(adev);
2708
d20ebea8 2709 /* On resume we need to rewrite the MSTM control bits to enable MST*/
684cd480
LP		 2710 s3_handle_mst(ddev, false);
2711
4562236b 2712 /* Do detection*/
f8d2d39e
LP		 2713 drm_connector_list_iter_begin(ddev, &iter);
2714 drm_for_each_connector_iter(connector, &iter) {
c84dec2f 2715 aconnector = to_amdgpu_dm_connector(connector);
4562236b 2716
7a7175a2
RL		 2717 if (!aconnector->dc_link)
2718 continue;
2719
4562236b
HW		 2720 /*
2721 * this is the case when traversing through already created
2722 * MST connectors, should be skipped
2723 */
7a7175a2 2724 if (aconnector->dc_link->type == dc_connection_mst_branch)
4562236b
HW		 2725 continue;
2726
03ea364c 2727 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 2728 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2729 DRM_ERROR("KMS: Failed to detect connector\n");
2730
15c735e7 2731 if (aconnector->base.force && new_connection_type == dc_connection_none) {
fbbdadf2 2732 emulated_link_detect(aconnector->dc_link);
15c735e7
WL		 2733 } else {
2734 mutex_lock(&dm->dc_lock);
fbbdadf2 2735 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
15c735e7
WL		 2736 mutex_unlock(&dm->dc_lock);
2737 }
3eb4eba4
RL		 2738
2739 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2740 aconnector->fake_enable = false;
2741
dcd5fb82
MF		 2742 if (aconnector->dc_sink)
2743 dc_sink_release(aconnector->dc_sink);
4562236b
HW		 2744 aconnector->dc_sink = NULL;
2745 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 2746 mutex_unlock(&aconnector->hpd_lock);
4562236b 2747 }
f8d2d39e 2748 drm_connector_list_iter_end(&iter);
4562236b 2749
1f6010a9 2750 /* Force mode set in atomic commit */
a80aa93d 2751 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 2752 new_crtc_state->active_changed = true;
4f346e65 2753
fcb4019e
LSL		 2754 /*
2755 * atomic_check is expected to create the dc states. We need to release
2756 * them here, since they were duplicated as part of the suspend
2757 * procedure.
2758 */
a80aa93d 2759 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 2760 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2761 if (dm_new_crtc_state->stream) {
2762 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2763 dc_stream_release(dm_new_crtc_state->stream);
2764 dm_new_crtc_state->stream = NULL;
2765 }
2766 }
2767
a80aa93d 2768 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 2769 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2770 if (dm_new_plane_state->dc_state) {
2771 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2772 dc_plane_state_release(dm_new_plane_state->dc_state);
2773 dm_new_plane_state->dc_state = NULL;
2774 }
2775 }
2776
2d1af6a1 2777 drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 2778
a80aa93d 2779 dm->cached_state = NULL;
0a214e2f 2780
9faa4237 2781 amdgpu_dm_irq_resume_late(adev);
4562236b 2782
9340dfd3
HW		 2783 amdgpu_dm_smu_write_watermarks_table(adev);
2784
2d1af6a1 2785 return 0;
4562236b
HW		 2786}
2787
b8592b48
LL		 2788/**
2789 * DOC: DM Lifecycle
2790 *
2791 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2792 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2793 * the base driver's device list to be initialized and torn down accordingly.
2794 *
2795 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2796 */
2797
4562236b
HW		 2798static const struct amd_ip_funcs amdgpu_dm_funcs = {
2799 .name = "dm",
2800 .early_init = dm_early_init,
7abcf6b5 2801 .late_init = dm_late_init,
4562236b
HW		 2802 .sw_init = dm_sw_init,
2803 .sw_fini = dm_sw_fini,
e9669fb7 2804 .early_fini = amdgpu_dm_early_fini,
4562236b
HW		 2805 .hw_init = dm_hw_init,
2806 .hw_fini = dm_hw_fini,
2807 .suspend = dm_suspend,
2808 .resume = dm_resume,
2809 .is_idle = dm_is_idle,
2810 .wait_for_idle = dm_wait_for_idle,
2811 .check_soft_reset = dm_check_soft_reset,
2812 .soft_reset = dm_soft_reset,
2813 .set_clockgating_state = dm_set_clockgating_state,
2814 .set_powergating_state = dm_set_powergating_state,
2815};
2816
2817const struct amdgpu_ip_block_version dm_ip_block =
2818{
2819 .type = AMD_IP_BLOCK_TYPE_DCE,
2820 .major = 1,
2821 .minor = 0,
2822 .rev = 0,
2823 .funcs = &amdgpu_dm_funcs,
2824};
2825
ca3268c4 2826
b8592b48
LL		 2827/**
2828 * DOC: atomic
2829 *
2830 * *WIP*
2831 */
0a323b84 2832
b3663f70 2833static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 2834 .fb_create = amdgpu_display_user_framebuffer_create,
dfbbfe3c 2835 .get_format_info = amd_get_format_info,
4562236b 2836 .atomic_check = amdgpu_dm_atomic_check,
0269764a 2837 .atomic_commit = drm_atomic_helper_commit,
54f5499a
AG		 2838};
2839
2840static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
a5c2c0d1
LP		 2841 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2842 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
4562236b
HW		 2843};
2844
94562810
RS		 2845static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2846{
94562810
RS		 2847 struct amdgpu_dm_backlight_caps *caps;
2848 struct amdgpu_display_manager *dm;
2849 struct drm_connector *conn_base;
2850 struct amdgpu_device *adev;
ec11fe37 2851 struct dc_link *link = NULL;
a61bb342 2852 struct drm_luminance_range_info *luminance_range;
7fd13bae 2853 int i;
94562810
RS		 2854
2855 if (!aconnector || !aconnector->dc_link)
2856 return;
2857
ec11fe37 2858 link = aconnector->dc_link;
2859 if (link->connector_signal != SIGNAL_TYPE_EDP)
2860 return;
2861
94562810 2862 conn_base = &aconnector->base;
1348969a 2863 adev = drm_to_adev(conn_base->dev);
94562810 2864 dm = &adev->dm;
7fd13bae
AD		 2865 for (i = 0; i < dm->num_of_edps; i++) {
2866 if (link == dm->backlight_link[i])
2867 break;
2868 }
2869 if (i >= dm->num_of_edps)
2870 return;
2871 caps = &dm->backlight_caps[i];
94562810
RS		 2872 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2873 caps->aux_support = false;
94562810 2874
d0ae0b64 2875 if (caps->ext_caps->bits.oled == 1 /*||
94562810 2876 caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
d0ae0b64 2877 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
94562810
RS		 2878 caps->aux_support = true;
2879
7a46f05e
TI		 2880 if (amdgpu_backlight == 0)
2881 caps->aux_support = false;
2882 else if (amdgpu_backlight == 1)
2883 caps->aux_support = true;
2884
a61bb342
JH		 2885 luminance_range = &conn_base->display_info.luminance_range;
2886 caps->aux_min_input_signal = luminance_range->min_luminance;
2887 caps->aux_max_input_signal = luminance_range->max_luminance;
94562810
RS		 2888}
2889
97e51c16
HW		 2890void amdgpu_dm_update_connector_after_detect(
2891 struct amdgpu_dm_connector *aconnector)
4562236b
HW		 2892{
2893 struct drm_connector *connector = &aconnector->base;
2894 struct drm_device *dev = connector->dev;
b73a22d3 2895 struct dc_sink *sink;
4562236b
HW		 2896
2897 /* MST handled by drm_mst framework */
2898 if (aconnector->mst_mgr.mst_state == true)
2899 return;
2900
4562236b 2901 sink = aconnector->dc_link->local_sink;
dcd5fb82
MF		 2902 if (sink)
2903 dc_sink_retain(sink);
4562236b 2904
1f6010a9
DF		 2905 /*
2906 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 2907 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 2908 * Skip if already done during boot.
4562236b
HW		 2909 */
2910 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2911 && aconnector->dc_em_sink) {
2912
1f6010a9
DF		 2913 /*
2914 * For S3 resume with headless use eml_sink to fake stream
2915 * because on resume connector->sink is set to NULL
4562236b
HW		 2916 */
2917 mutex_lock(&dev->mode_config.mutex);
2918
2919 if (sink) {
922aa1e1 2920 if (aconnector->dc_sink) {
98e6436d 2921 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 2922 /*
2923 * retain and release below are used to
2924 * bump up refcount for sink because the link doesn't point
2925 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 2926 * reshuffle by UMD we will get into unwanted dc_sink release
2927 */
dcd5fb82 2928 dc_sink_release(aconnector->dc_sink);
922aa1e1 2929 }
4562236b 2930 aconnector->dc_sink = sink;
dcd5fb82 2931 dc_sink_retain(aconnector->dc_sink);
98e6436d
AK		 2932 amdgpu_dm_update_freesync_caps(connector,
2933 aconnector->edid);
4562236b 2934 } else {
98e6436d 2935 amdgpu_dm_update_freesync_caps(connector, NULL);
dcd5fb82 2936 if (!aconnector->dc_sink) {
4562236b 2937 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1 2938 dc_sink_retain(aconnector->dc_sink);
dcd5fb82 2939 }
4562236b
HW		 2940 }
2941
2942 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 2943
2944 if (sink)
2945 dc_sink_release(sink);
4562236b
HW		 2946 return;
2947 }
2948
2949 /*
2950 * TODO: temporary guard to look for proper fix
2951 * if this sink is MST sink, we should not do anything
2952 */
dcd5fb82
MF		 2953 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2954 dc_sink_release(sink);
4562236b 2955 return;
dcd5fb82 2956 }
4562236b
HW		 2957
2958 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 2959 /*
2960 * We got a DP short pulse (Link Loss, DP CTS, etc...).
2961 * Do nothing!!
2962 */
f1ad2f5e 2963 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b 2964 aconnector->connector_id);
dcd5fb82
MF		 2965 if (sink)
2966 dc_sink_release(sink);
4562236b
HW		 2967 return;
2968 }
2969
f1ad2f5e 2970 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 2971 aconnector->connector_id, aconnector->dc_sink, sink);
2972
2973 mutex_lock(&dev->mode_config.mutex);
2974
1f6010a9
DF		 2975 /*
2976 * 1. Update status of the drm connector
2977 * 2. Send an event and let userspace tell us what to do
2978 */
4562236b 2979 if (sink) {
1f6010a9
DF		 2980 /*
2981 * TODO: check if we still need the S3 mode update workaround.
2982 * If yes, put it here.
2983 */
c64b0d6b 2984 if (aconnector->dc_sink) {
98e6436d 2985 amdgpu_dm_update_freesync_caps(connector, NULL);
c64b0d6b
VL		 2986 dc_sink_release(aconnector->dc_sink);
2987 }
4562236b
HW		 2988
2989 aconnector->dc_sink = sink;
dcd5fb82 2990 dc_sink_retain(aconnector->dc_sink);
900b3cb1 2991 if (sink->dc_edid.length == 0) {
4562236b 2992 aconnector->edid = NULL;
e6142dd5
AP		 2993 if (aconnector->dc_link->aux_mode) {
2994 drm_dp_cec_unset_edid(
2995 &aconnector->dm_dp_aux.aux);
2996 }
900b3cb1 2997 } else {
4562236b 2998 aconnector->edid =
e6142dd5 2999 (struct edid *)sink->dc_edid.raw_edid;
4562236b 3000
e6142dd5
AP		 3001 if (aconnector->dc_link->aux_mode)
3002 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3003 aconnector->edid);
4562236b 3004 }
e6142dd5 3005
20543be9 3006 drm_connector_update_edid_property(connector, aconnector->edid);
98e6436d 3007 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
94562810 3008 update_connector_ext_caps(aconnector);
4562236b 3009 } else {
e86e8947 3010 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 3011 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 3012 drm_connector_update_edid_property(connector, NULL);
4562236b 3013 aconnector->num_modes = 0;
dcd5fb82 3014 dc_sink_release(aconnector->dc_sink);
4562236b 3015 aconnector->dc_sink = NULL;
5326c452 3016 aconnector->edid = NULL;
0c8620d6
BL		 3017#ifdef CONFIG_DRM_AMD_DC_HDCP
3018 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3019 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3020 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3021#endif
4562236b
HW		 3022 }
3023
3024 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82 3025
0f877894
OV		 3026 update_subconnector_property(aconnector);
3027
dcd5fb82
MF		 3028 if (sink)
3029 dc_sink_release(sink);
4562236b
HW		 3030}
3031
e27c41d5 3032static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
4562236b 3033{
4562236b
HW		 3034 struct drm_connector *connector = &aconnector->base;
3035 struct drm_device *dev = connector->dev;
fbbdadf2 3036 enum dc_connection_type new_connection_type = dc_connection_none;
1348969a 3037 struct amdgpu_device *adev = drm_to_adev(dev);
10a36226 3038#ifdef CONFIG_DRM_AMD_DC_HDCP
97f6c917 3039 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
10a36226 3040#endif
15c735e7 3041 bool ret = false;
4562236b 3042
b972b4f9
HW		 3043 if (adev->dm.disable_hpd_irq)
3044 return;
3045
1f6010a9
DF		 3046 /*
3047 * In case of failure or MST no need to update connector status or notify the OS
3048 * since (for MST case) MST does this in its own context.
4562236b
HW		 3049 */
3050 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6 3051
0c8620d6 3052#ifdef CONFIG_DRM_AMD_DC_HDCP
97f6c917 3053 if (adev->dm.hdcp_workqueue) {
96a3b32e 3054 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
97f6c917
BL		 3055 dm_con_state->update_hdcp = true;
3056 }
0c8620d6 3057#endif
2e0ac3d6
HW		 3058 if (aconnector->fake_enable)
3059 aconnector->fake_enable = false;
3060
fbbdadf2
BL		 3061 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
3062 DRM_ERROR("KMS: Failed to detect connector\n");
3063
3064 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3065 emulated_link_detect(aconnector->dc_link);
3066
fbbdadf2
BL		 3067 drm_modeset_lock_all(dev);
3068 dm_restore_drm_connector_state(dev, connector);
3069 drm_modeset_unlock_all(dev);
3070
3071 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
fc320a6f 3072 drm_kms_helper_connector_hotplug_event(connector);
15c735e7
WL		 3073 } else {
3074 mutex_lock(&adev->dm.dc_lock);
3075 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3076 mutex_unlock(&adev->dm.dc_lock);
3077 if (ret) {
3078 amdgpu_dm_update_connector_after_detect(aconnector);
fbbdadf2 3079
15c735e7
WL		 3080 drm_modeset_lock_all(dev);
3081 dm_restore_drm_connector_state(dev, connector);
3082 drm_modeset_unlock_all(dev);
4562236b 3083
15c735e7
WL		 3084 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3085 drm_kms_helper_connector_hotplug_event(connector);
3086 }
4562236b
HW		 3087 }
3088 mutex_unlock(&aconnector->hpd_lock);
3089
3090}
3091
e27c41d5
JS		 3092static void handle_hpd_irq(void *param)
3093{
3094 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3095
3096 handle_hpd_irq_helper(aconnector);
3097
3098}
3099
8e794421 3100static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
4562236b 3101{
ae67558b
SS		 3102 u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3103 u8 dret;
4562236b
HW		 3104 bool new_irq_handled = false;
3105 int dpcd_addr;
3106 int dpcd_bytes_to_read;
3107
3108 const int max_process_count = 30;
3109 int process_count = 0;
3110
3111 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3112
3113 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3114 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3115 /* DPCD 0x200 - 0x201 for downstream IRQ */
3116 dpcd_addr = DP_SINK_COUNT;
3117 } else {
3118 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3119 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3120 dpcd_addr = DP_SINK_COUNT_ESI;
3121 }
3122
3123 dret = drm_dp_dpcd_read(
3124 &aconnector->dm_dp_aux.aux,
3125 dpcd_addr,
3126 esi,
3127 dpcd_bytes_to_read);
3128
3129 while (dret == dpcd_bytes_to_read &&
3130 process_count < max_process_count) {
ae67558b 3131 u8 retry;
4562236b
HW		 3132 dret = 0;
3133
3134 process_count++;
3135
f1ad2f5e 3136 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 3137 /* handle HPD short pulse irq */
3138 if (aconnector->mst_mgr.mst_state)
3139 drm_dp_mst_hpd_irq(
3140 &aconnector->mst_mgr,
3141 esi,
3142 &new_irq_handled);
4562236b
HW		 3143
3144 if (new_irq_handled) {
3145 /* ACK at DPCD to notify down stream */
3146 const int ack_dpcd_bytes_to_write =
3147 dpcd_bytes_to_read - 1;
3148
3149 for (retry = 0; retry < 3; retry++) {
ae67558b 3150 u8 wret;
4562236b
HW		 3151
3152 wret = drm_dp_dpcd_write(
3153 &aconnector->dm_dp_aux.aux,
3154 dpcd_addr + 1,
3155 &esi[1],
3156 ack_dpcd_bytes_to_write);
3157 if (wret == ack_dpcd_bytes_to_write)
3158 break;
3159 }
3160
1f6010a9 3161 /* check if there is new irq to be handled */
4562236b
HW		 3162 dret = drm_dp_dpcd_read(
3163 &aconnector->dm_dp_aux.aux,
3164 dpcd_addr,
3165 esi,
3166 dpcd_bytes_to_read);
3167
3168 new_irq_handled = false;
d4a6e8a9 3169 } else {
4562236b 3170 break;
d4a6e8a9 3171 }
4562236b
HW		 3172 }
3173
3174 if (process_count == max_process_count)
f1ad2f5e 3175 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 3176}
3177
8e794421
WL		 3178static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3179 union hpd_irq_data hpd_irq_data)
3180{
3181 struct hpd_rx_irq_offload_work *offload_work =
3182 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3183
3184 if (!offload_work) {
3185 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3186 return;
3187 }
3188
3189 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3190 offload_work->data = hpd_irq_data;
3191 offload_work->offload_wq = offload_wq;
3192
3193 queue_work(offload_wq->wq, &offload_work->work);
3194 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3195}
3196
4562236b
HW		 3197static void handle_hpd_rx_irq(void *param)
3198{
c84dec2f 3199 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 3200 struct drm_connector *connector = &aconnector->base;
3201 struct drm_device *dev = connector->dev;
53cbf65c 3202 struct dc_link *dc_link = aconnector->dc_link;
4562236b 3203 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
c8ea79a8 3204 bool result = false;
fbbdadf2 3205 enum dc_connection_type new_connection_type = dc_connection_none;
c8ea79a8 3206 struct amdgpu_device *adev = drm_to_adev(dev);
2a0f9270 3207 union hpd_irq_data hpd_irq_data;
8e794421
WL		 3208 bool link_loss = false;
3209 bool has_left_work = false;
3210 int idx = aconnector->base.index;
3211 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
2a0f9270
BL		 3212
3213 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
4562236b 3214
b972b4f9
HW		 3215 if (adev->dm.disable_hpd_irq)
3216 return;
3217
1f6010a9
DF		 3218 /*
3219 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 3220 * conflict, after implement i2c helper, this mutex should be
3221 * retired.
3222 */
b86e7eef 3223 mutex_lock(&aconnector->hpd_lock);
4562236b 3224
8e794421
WL		 3225 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3226 &link_loss, true, &has_left_work);
3083a984 3227
8e794421
WL		 3228 if (!has_left_work)
3229 goto out;
3230
3231 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3232 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3233 goto out;
3234 }
3235
3236 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3237 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3238 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3239 dm_handle_mst_sideband_msg(aconnector);
3083a984
QZ		 3240 goto out;
3241 }
3083a984 3242
8e794421
WL		 3243 if (link_loss) {
3244 bool skip = false;
d2aa1356 3245
8e794421
WL		 3246 spin_lock(&offload_wq->offload_lock);
3247 skip = offload_wq->is_handling_link_loss;
3248
3249 if (!skip)
3250 offload_wq->is_handling_link_loss = true;
3251
3252 spin_unlock(&offload_wq->offload_lock);
3253
3254 if (!skip)
3255 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3256
3257 goto out;
3258 }
3259 }
c8ea79a8 3260
3083a984 3261out:
c8ea79a8 3262 if (result && !is_mst_root_connector) {
4562236b 3263 /* Downstream Port status changed. */
fbbdadf2
BL		 3264 if (!dc_link_detect_sink(dc_link, &new_connection_type))
3265 DRM_ERROR("KMS: Failed to detect connector\n");
3266
3267 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3268 emulated_link_detect(dc_link);
3269
3270 if (aconnector->fake_enable)
3271 aconnector->fake_enable = false;
3272
3273 amdgpu_dm_update_connector_after_detect(aconnector);
3274
3275
3276 drm_modeset_lock_all(dev);
3277 dm_restore_drm_connector_state(dev, connector);
3278 drm_modeset_unlock_all(dev);
3279
fc320a6f 3280 drm_kms_helper_connector_hotplug_event(connector);
15c735e7
WL		 3281 } else {
3282 bool ret = false;
88ac3dda 3283
15c735e7
WL		 3284 mutex_lock(&adev->dm.dc_lock);
3285 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3286 mutex_unlock(&adev->dm.dc_lock);
88ac3dda 3287
15c735e7
WL		 3288 if (ret) {
3289 if (aconnector->fake_enable)
3290 aconnector->fake_enable = false;
4562236b 3291
15c735e7 3292 amdgpu_dm_update_connector_after_detect(aconnector);
4562236b 3293
15c735e7
WL		 3294 drm_modeset_lock_all(dev);
3295 dm_restore_drm_connector_state(dev, connector);
3296 drm_modeset_unlock_all(dev);
4562236b 3297
15c735e7
WL		 3298 drm_kms_helper_connector_hotplug_event(connector);
3299 }
4562236b
HW		 3300 }
3301 }
2a0f9270 3302#ifdef CONFIG_DRM_AMD_DC_HDCP
95f247e7
DC		 3303 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3304 if (adev->dm.hdcp_workqueue)
3305 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3306 }
2a0f9270 3307#endif
4562236b 3308
b86e7eef 3309 if (dc_link->type != dc_connection_mst_branch)
e86e8947 3310 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
b86e7eef
NC		 3311
3312 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 3313}
3314
3315static void register_hpd_handlers(struct amdgpu_device *adev)
3316{
4a580877 3317 struct drm_device *dev = adev_to_drm(adev);
4562236b 3318 struct drm_connector *connector;
c84dec2f 3319 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 3320 const struct dc_link *dc_link;
3321 struct dc_interrupt_params int_params = {0};
3322
3323 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3324 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3325
3326 list_for_each_entry(connector,
3327 &dev->mode_config.connector_list, head) {
3328
c84dec2f 3329 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 3330 dc_link = aconnector->dc_link;
3331
3332 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3333 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3334 int_params.irq_source = dc_link->irq_source_hpd;
3335
3336 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3337 handle_hpd_irq,
3338 (void *) aconnector);
3339 }
3340
3341 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3342
3343 /* Also register for DP short pulse (hpd_rx). */
3344 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3345 int_params.irq_source = dc_link->irq_source_hpd_rx;
3346
3347 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3348 handle_hpd_rx_irq,
3349 (void *) aconnector);
8e794421
WL		 3350
3351 if (adev->dm.hpd_rx_offload_wq)
3352 adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3353 aconnector;
4562236b
HW		 3354 }
3355 }
3356}
3357
55e56389
MR		 3358#if defined(CONFIG_DRM_AMD_DC_SI)
3359/* Register IRQ sources and initialize IRQ callbacks */
3360static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3361{
3362 struct dc *dc = adev->dm.dc;
3363 struct common_irq_params *c_irq_params;
3364 struct dc_interrupt_params int_params = {0};
3365 int r;
3366 int i;
3367 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3368
3369 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3370 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3371
3372 /*
3373 * Actions of amdgpu_irq_add_id():
3374 * 1. Register a set() function with base driver.
3375 * Base driver will call set() function to enable/disable an
3376 * interrupt in DC hardware.
3377 * 2. Register amdgpu_dm_irq_handler().
3378 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3379 * coming from DC hardware.
3380 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3381 * for acknowledging and handling. */
3382
3383 /* Use VBLANK interrupt */
3384 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3385 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3386 if (r) {
3387 DRM_ERROR("Failed to add crtc irq id!\n");
3388 return r;
3389 }
3390
3391 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3392 int_params.irq_source =
3393 dc_interrupt_to_irq_source(dc, i+1 , 0);
3394
3395 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3396
3397 c_irq_params->adev = adev;
3398 c_irq_params->irq_src = int_params.irq_source;
3399
3400 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3401 dm_crtc_high_irq, c_irq_params);
3402 }
3403
3404 /* Use GRPH_PFLIP interrupt */
3405 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3406 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3407 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3408 if (r) {
3409 DRM_ERROR("Failed to add page flip irq id!\n");
3410 return r;
3411 }
3412
3413 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3414 int_params.irq_source =
3415 dc_interrupt_to_irq_source(dc, i, 0);
3416
3417 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3418
3419 c_irq_params->adev = adev;
3420 c_irq_params->irq_src = int_params.irq_source;
3421
3422 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3423 dm_pflip_high_irq, c_irq_params);
3424
3425 }
3426
3427 /* HPD */
3428 r = amdgpu_irq_add_id(adev, client_id,
3429 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3430 if (r) {
3431 DRM_ERROR("Failed to add hpd irq id!\n");
3432 return r;
3433 }
3434
3435 register_hpd_handlers(adev);
3436
3437 return 0;
3438}
3439#endif
3440
4562236b
HW		 3441/* Register IRQ sources and initialize IRQ callbacks */
3442static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3443{
3444 struct dc *dc = adev->dm.dc;
3445 struct common_irq_params *c_irq_params;
3446 struct dc_interrupt_params int_params = {0};
3447 int r;
3448 int i;
1ffdeca6 3449 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 3450
c08182f2 3451 if (adev->family >= AMDGPU_FAMILY_AI)
3760f76c 3452 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 3453
3454 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3455 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3456
1f6010a9
DF		 3457 /*
3458 * Actions of amdgpu_irq_add_id():
4562236b
HW		 3459 * 1. Register a set() function with base driver.
3460 * Base driver will call set() function to enable/disable an
3461 * interrupt in DC hardware.
3462 * 2. Register amdgpu_dm_irq_handler().
3463 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3464 * coming from DC hardware.
3465 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3466 * for acknowledging and handling. */
3467
b57de80a 3468 /* Use VBLANK interrupt */
e9029155 3469 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 3470 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 3471 if (r) {
3472 DRM_ERROR("Failed to add crtc irq id!\n");
3473 return r;
3474 }
3475
3476 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3477 int_params.irq_source =
3d761e79 3478 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 3479
b57de80a 3480 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 3481
3482 c_irq_params->adev = adev;
3483 c_irq_params->irq_src = int_params.irq_source;
3484
3485 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3486 dm_crtc_high_irq, c_irq_params);
3487 }
3488
d2574c33
MK		 3489 /* Use VUPDATE interrupt */
3490 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3491 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3492 if (r) {
3493 DRM_ERROR("Failed to add vupdate irq id!\n");
3494 return r;
3495 }
3496
3497 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3498 int_params.irq_source =
3499 dc_interrupt_to_irq_source(dc, i, 0);
3500
3501 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3502
3503 c_irq_params->adev = adev;
3504 c_irq_params->irq_src = int_params.irq_source;
3505
3506 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3507 dm_vupdate_high_irq, c_irq_params);
3508 }
3509
3d761e79 3510 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 3511 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3512 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 3513 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 3514 if (r) {
3515 DRM_ERROR("Failed to add page flip irq id!\n");
3516 return r;
3517 }
3518
3519 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3520 int_params.irq_source =
3521 dc_interrupt_to_irq_source(dc, i, 0);
3522
3523 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3524
3525 c_irq_params->adev = adev;
3526 c_irq_params->irq_src = int_params.irq_source;
3527
3528 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3529 dm_pflip_high_irq, c_irq_params);
3530
3531 }
3532
3533 /* HPD */
2c8ad2d5
AD		 3534 r = amdgpu_irq_add_id(adev, client_id,
3535 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 3536 if (r) {
3537 DRM_ERROR("Failed to add hpd irq id!\n");
3538 return r;
3539 }
3540
3541 register_hpd_handlers(adev);
3542
3543 return 0;
3544}
3545
ff5ef992
AD		 3546/* Register IRQ sources and initialize IRQ callbacks */
3547static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3548{
3549 struct dc *dc = adev->dm.dc;
3550 struct common_irq_params *c_irq_params;
3551 struct dc_interrupt_params int_params = {0};
3552 int r;
3553 int i;
660d5406
WL		 3554#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3555 static const unsigned int vrtl_int_srcid[] = {
3556 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3557 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3558 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3559 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3560 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3561 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3562 };
3563#endif
ff5ef992
AD		 3564
3565 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3566 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3567
1f6010a9
DF		 3568 /*
3569 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 3570 * 1. Register a set() function with base driver.
3571 * Base driver will call set() function to enable/disable an
3572 * interrupt in DC hardware.
3573 * 2. Register amdgpu_dm_irq_handler().
3574 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3575 * coming from DC hardware.
3576 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3577 * for acknowledging and handling.
1f6010a9 3578 */
ff5ef992
AD		 3579
3580 /* Use VSTARTUP interrupt */
3581 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3582 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3583 i++) {
3760f76c 3584 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 3585
3586 if (r) {
3587 DRM_ERROR("Failed to add crtc irq id!\n");
3588 return r;
3589 }
3590
3591 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3592 int_params.irq_source =
3593 dc_interrupt_to_irq_source(dc, i, 0);
3594
3595 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3596
3597 c_irq_params->adev = adev;
3598 c_irq_params->irq_src = int_params.irq_source;
3599
2346ef47
NK		 3600 amdgpu_dm_irq_register_interrupt(
3601 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3602 }
3603
86bc2219
WL		 3604 /* Use otg vertical line interrupt */
3605#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
660d5406
WL		 3606 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3607 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3608 vrtl_int_srcid[i], &adev->vline0_irq);
86bc2219
WL		 3609
3610 if (r) {
3611 DRM_ERROR("Failed to add vline0 irq id!\n");
3612 return r;
3613 }
3614
3615 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3616 int_params.irq_source =
660d5406
WL		 3617 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3618
3619 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3620 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3621 break;
3622 }
86bc2219
WL		 3623
3624 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3625 - DC_IRQ_SOURCE_DC1_VLINE0];
3626
3627 c_irq_params->adev = adev;
3628 c_irq_params->irq_src = int_params.irq_source;
3629
3630 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3631 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3632 }
3633#endif
3634
2346ef47
NK		 3635 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3636 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3637 * to trigger at end of each vblank, regardless of state of the lock,
3638 * matching DCE behaviour.
3639 */
3640 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3641 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3642 i++) {
3643 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3644
3645 if (r) {
3646 DRM_ERROR("Failed to add vupdate irq id!\n");
3647 return r;
3648 }
3649
3650 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3651 int_params.irq_source =
3652 dc_interrupt_to_irq_source(dc, i, 0);
3653
3654 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3655
3656 c_irq_params->adev = adev;
3657 c_irq_params->irq_src = int_params.irq_source;
3658
ff5ef992 3659 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2346ef47 3660 dm_vupdate_high_irq, c_irq_params);
d2574c33
MK		 3661 }
3662
ff5ef992
AD		 3663 /* Use GRPH_PFLIP interrupt */
3664 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
de95753c 3665 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
ff5ef992 3666 i++) {
3760f76c 3667 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 3668 if (r) {
3669 DRM_ERROR("Failed to add page flip irq id!\n");
3670 return r;
3671 }
3672
3673 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3674 int_params.irq_source =
3675 dc_interrupt_to_irq_source(dc, i, 0);
3676
3677 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3678
3679 c_irq_params->adev = adev;
3680 c_irq_params->irq_src = int_params.irq_source;
3681
3682 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3683 dm_pflip_high_irq, c_irq_params);
3684
3685 }
3686
81927e28
JS		 3687 /* HPD */
3688 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3689 &adev->hpd_irq);
3690 if (r) {
3691 DRM_ERROR("Failed to add hpd irq id!\n");
3692 return r;
3693 }
a08f16cf 3694
81927e28 3695 register_hpd_handlers(adev);
a08f16cf 3696
81927e28
JS		 3697 return 0;
3698}
3699/* Register Outbox IRQ sources and initialize IRQ callbacks */
3700static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3701{
3702 struct dc *dc = adev->dm.dc;
3703 struct common_irq_params *c_irq_params;
3704 struct dc_interrupt_params int_params = {0};
3705 int r, i;
3706
3707 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3708 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3709
3710 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3711 &adev->dmub_outbox_irq);
3712 if (r) {
3713 DRM_ERROR("Failed to add outbox irq id!\n");
3714 return r;
3715 }
3716
3717 if (dc->ctx->dmub_srv) {
3718 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3719 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
a08f16cf 3720 int_params.irq_source =
81927e28 3721 dc_interrupt_to_irq_source(dc, i, 0);
a08f16cf 3722
81927e28 3723 c_irq_params = &adev->dm.dmub_outbox_params[0];
a08f16cf
LHM		 3724
3725 c_irq_params->adev = adev;
3726 c_irq_params->irq_src = int_params.irq_source;
3727
3728 amdgpu_dm_irq_register_interrupt(adev, &int_params,
81927e28 3729 dm_dmub_outbox1_low_irq, c_irq_params);
ff5ef992
AD		 3730 }
3731
ff5ef992
AD		 3732 return 0;
3733}
ff5ef992 3734
eb3dc897
NK		 3735/*
3736 * Acquires the lock for the atomic state object and returns
3737 * the new atomic state.
3738 *
3739 * This should only be called during atomic check.
3740 */
17ce8a69
RL		 3741int dm_atomic_get_state(struct drm_atomic_state *state,
3742 struct dm_atomic_state **dm_state)
eb3dc897
NK		 3743{
3744 struct drm_device *dev = state->dev;
1348969a 3745 struct amdgpu_device *adev = drm_to_adev(dev);
eb3dc897
NK		 3746 struct amdgpu_display_manager *dm = &adev->dm;
3747 struct drm_private_state *priv_state;
eb3dc897
NK		 3748
3749 if (*dm_state)
3750 return 0;
3751
eb3dc897
NK		 3752 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3753 if (IS_ERR(priv_state))
3754 return PTR_ERR(priv_state);
3755
3756 *dm_state = to_dm_atomic_state(priv_state);
3757
3758 return 0;
3759}
3760
dfd84d90 3761static struct dm_atomic_state *
eb3dc897
NK		 3762dm_atomic_get_new_state(struct drm_atomic_state *state)
3763{
3764 struct drm_device *dev = state->dev;
1348969a 3765 struct amdgpu_device *adev = drm_to_adev(dev);
eb3dc897
NK		 3766 struct amdgpu_display_manager *dm = &adev->dm;
3767 struct drm_private_obj *obj;
3768 struct drm_private_state *new_obj_state;
3769 int i;
3770
3771 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3772 if (obj->funcs == dm->atomic_obj.funcs)
3773 return to_dm_atomic_state(new_obj_state);
3774 }
3775
3776 return NULL;
3777}
3778
eb3dc897
NK		 3779static struct drm_private_state *
3780dm_atomic_duplicate_state(struct drm_private_obj *obj)
3781{
3782 struct dm_atomic_state *old_state, *new_state;
3783
3784 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3785 if (!new_state)
3786 return NULL;
3787
3788 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3789
813d20dc
AW		 3790 old_state = to_dm_atomic_state(obj->state);
3791
3792 if (old_state && old_state->context)
3793 new_state->context = dc_copy_state(old_state->context);
3794
eb3dc897
NK		 3795 if (!new_state->context) {
3796 kfree(new_state);
3797 return NULL;
3798 }
3799
eb3dc897
NK		 3800 return &new_state->base;
3801}
3802
3803static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3804 struct drm_private_state *state)
3805{
3806 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3807
3808 if (dm_state && dm_state->context)
3809 dc_release_state(dm_state->context);
3810
3811 kfree(dm_state);
3812}
3813
3814static struct drm_private_state_funcs dm_atomic_state_funcs = {
3815 .atomic_duplicate_state = dm_atomic_duplicate_state,
3816 .atomic_destroy_state = dm_atomic_destroy_state,
3817};
3818
4562236b
HW		 3819static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3820{
eb3dc897 3821 struct dm_atomic_state *state;
4562236b
HW		 3822 int r;
3823
3824 adev->mode_info.mode_config_initialized = true;
3825
4a580877
LT		 3826 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3827 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b 3828
4a580877
LT		 3829 adev_to_drm(adev)->mode_config.max_width = 16384;
3830 adev_to_drm(adev)->mode_config.max_height = 16384;
4562236b 3831
4a580877 3832 adev_to_drm(adev)->mode_config.preferred_depth = 24;
a6250bdb
AD		 3833 if (adev->asic_type == CHIP_HAWAII)
3834 /* disable prefer shadow for now due to hibernation issues */
3835 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3836 else
3837 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
1f6010a9 3838 /* indicates support for immediate flip */
4a580877 3839 adev_to_drm(adev)->mode_config.async_page_flip = true;
4562236b 3840
eb3dc897
NK		 3841 state = kzalloc(sizeof(*state), GFP_KERNEL);
3842 if (!state)
3843 return -ENOMEM;
3844
813d20dc 3845 state->context = dc_create_state(adev->dm.dc);
eb3dc897
NK		 3846 if (!state->context) {
3847 kfree(state);
3848 return -ENOMEM;
3849 }
3850
3851 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3852
4a580877 3853 drm_atomic_private_obj_init(adev_to_drm(adev),
8c1a765b 3854 &adev->dm.atomic_obj,
eb3dc897
NK		 3855 &state->base,
3856 &dm_atomic_state_funcs);
3857
3dc9b1ce 3858 r = amdgpu_display_modeset_create_props(adev);
b67a468a
DL		 3859 if (r) {
3860 dc_release_state(state->context);
3861 kfree(state);
4562236b 3862 return r;
b67a468a 3863 }
4562236b 3864
6ce8f316 3865 r = amdgpu_dm_audio_init(adev);
b67a468a
DL		 3866 if (r) {
3867 dc_release_state(state->context);
3868 kfree(state);
6ce8f316 3869 return r;
b67a468a 3870 }
6ce8f316 3871
4562236b
HW		 3872 return 0;
3873}
3874
206bbafe
DF		 3875#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3876#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
94562810 3877#define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
206bbafe 3878
7fd13bae
AD		 3879static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
3880 int bl_idx)
206bbafe
DF		 3881{
3882#if defined(CONFIG_ACPI)
3883 struct amdgpu_dm_backlight_caps caps;
3884
58965855
FS		 3885 memset(&caps, 0, sizeof(caps));
3886
7fd13bae 3887 if (dm->backlight_caps[bl_idx].caps_valid)
206bbafe
DF		 3888 return;
3889
f9b7f370 3890 amdgpu_acpi_get_backlight_caps(&caps);
206bbafe 3891 if (caps.caps_valid) {
7fd13bae 3892 dm->backlight_caps[bl_idx].caps_valid = true;
94562810
RS		 3893 if (caps.aux_support)
3894 return;
7fd13bae
AD		 3895 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
3896 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
206bbafe 3897 } else {
7fd13bae 3898 dm->backlight_caps[bl_idx].min_input_signal =
206bbafe 3899 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
7fd13bae 3900 dm->backlight_caps[bl_idx].max_input_signal =
206bbafe
DF		 3901 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3902 }
3903#else
7fd13bae 3904 if (dm->backlight_caps[bl_idx].aux_support)
94562810
RS		 3905 return;
3906
7fd13bae
AD		 3907 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3908 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 3909#endif
3910}
3911
69d9f427
AM		 3912static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3913 unsigned *min, unsigned *max)
94562810 3914{
94562810 3915 if (!caps)
69d9f427 3916 return 0;
94562810 3917
69d9f427
AM		 3918 if (caps->aux_support) {
3919 // Firmware limits are in nits, DC API wants millinits.
3920 *max = 1000 * caps->aux_max_input_signal;
3921 *min = 1000 * caps->aux_min_input_signal;
94562810 3922 } else {
69d9f427
AM		 3923 // Firmware limits are 8-bit, PWM control is 16-bit.
3924 *max = 0x101 * caps->max_input_signal;
3925 *min = 0x101 * caps->min_input_signal;
94562810 3926 }
69d9f427
AM		 3927 return 1;
3928}
94562810 3929
69d9f427
AM		 3930static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3931 uint32_t brightness)
3932{
3933 unsigned min, max;
94562810 3934
69d9f427
AM		 3935 if (!get_brightness_range(caps, &min, &max))
3936 return brightness;
3937
3938 // Rescale 0..255 to min..max
3939 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3940 AMDGPU_MAX_BL_LEVEL);
3941}
3942
3943static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3944 uint32_t brightness)
3945{
3946 unsigned min, max;
3947
3948 if (!get_brightness_range(caps, &min, &max))
3949 return brightness;
3950
3951 if (brightness < min)
3952 return 0;
3953 // Rescale min..max to 0..255
3954 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3955 max - min);
94562810
RS		 3956}
3957
4052287a 3958static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
7fd13bae 3959 int bl_idx,
3d6c9164 3960 u32 user_brightness)
4562236b 3961{
206bbafe 3962 struct amdgpu_dm_backlight_caps caps;
7fd13bae
AD		 3963 struct dc_link *link;
3964 u32 brightness;
94562810 3965 bool rc;
4562236b 3966
7fd13bae
AD		 3967 amdgpu_dm_update_backlight_caps(dm, bl_idx);
3968 caps = dm->backlight_caps[bl_idx];
94562810 3969
7fd13bae 3970 dm->brightness[bl_idx] = user_brightness;
1f579254
AD		 3971 /* update scratch register */
3972 if (bl_idx == 0)
3973 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
7fd13bae
AD		 3974 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
3975 link = (struct dc_link *)dm->backlight_link[bl_idx];
94562810 3976
3d6c9164 3977 /* Change brightness based on AUX property */
118b4627 3978 if (caps.aux_support) {
7fd13bae
AD		 3979 rc = dc_link_set_backlight_level_nits(link, true, brightness,
3980 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
3981 if (!rc)
3982 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
118b4627 3983 } else {
7fd13bae
AD		 3984 rc = dc_link_set_backlight_level(link, brightness, 0);
3985 if (!rc)
3986 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
118b4627 3987 }
94562810 3988
4052287a
S		 3989 if (rc)
3990 dm->actual_brightness[bl_idx] = user_brightness;
4562236b
HW		 3991}
3992
3d6c9164 3993static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4562236b 3994{
620a0d27 3995 struct amdgpu_display_manager *dm = bl_get_data(bd);
7fd13bae 3996 int i;
3d6c9164 3997
7fd13bae
AD		 3998 for (i = 0; i < dm->num_of_edps; i++) {
3999 if (bd == dm->backlight_dev[i])
4000 break;
4001 }
4002 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4003 i = 0;
4004 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
3d6c9164
AD		 4005
4006 return 0;
4007}
4008
7fd13bae
AD		 4009static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4010 int bl_idx)
3d6c9164 4011{
0ad3e64e 4012 struct amdgpu_dm_backlight_caps caps;
7fd13bae 4013 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
0ad3e64e 4014
7fd13bae
AD		 4015 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4016 caps = dm->backlight_caps[bl_idx];
620a0d27 4017
0ad3e64e 4018 if (caps.aux_support) {
0ad3e64e
AD		 4019 u32 avg, peak;
4020 bool rc;
4021
4022 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4023 if (!rc)
7fd13bae 4024 return dm->brightness[bl_idx];
0ad3e64e
AD		 4025 return convert_brightness_to_user(&caps, avg);
4026 } else {
7fd13bae 4027 int ret = dc_link_get_backlight_level(link);
0ad3e64e
AD		 4028
4029 if (ret == DC_ERROR_UNEXPECTED)
7fd13bae 4030 return dm->brightness[bl_idx];
0ad3e64e
AD		 4031 return convert_brightness_to_user(&caps, ret);
4032 }
4562236b
HW		 4033}
4034
3d6c9164
AD		 4035static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4036{
4037 struct amdgpu_display_manager *dm = bl_get_data(bd);
7fd13bae 4038 int i;
3d6c9164 4039
7fd13bae
AD		 4040 for (i = 0; i < dm->num_of_edps; i++) {
4041 if (bd == dm->backlight_dev[i])
4042 break;
4043 }
4044 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4045 i = 0;
4046 return amdgpu_dm_backlight_get_level(dm, i);
3d6c9164
AD		 4047}
4048
4562236b 4049static const struct backlight_ops amdgpu_dm_backlight_ops = {
bb264220 4050 .options = BL_CORE_SUSPENDRESUME,
4562236b
HW		 4051 .get_brightness = amdgpu_dm_backlight_get_brightness,
4052 .update_status = amdgpu_dm_backlight_update_status,
4053};
4054
7578ecda
AD		 4055static void
4056amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 4057{
4058 char bl_name[16];
4059 struct backlight_properties props = { 0 };
4060
7fd13bae
AD		 4061 amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4062 dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
206bbafe 4063
da11ef83
HG		 4064 if (!acpi_video_backlight_use_native()) {
4065 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
c0f50c5d
HG		 4066 /* Try registering an ACPI video backlight device instead. */
4067 acpi_video_register_backlight();
da11ef83
HG		 4068 return;
4069 }
4070
4562236b 4071 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 4072 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 4073 props.type = BACKLIGHT_RAW;
4074
4075 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
7fd13bae 4076 adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4562236b 4077
7fd13bae
AD		 4078 dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4079 adev_to_drm(dm->adev)->dev,
4080 dm,
4081 &amdgpu_dm_backlight_ops,
4082 &props);
4562236b 4083
7fd13bae 4084 if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4562236b
HW		 4085 DRM_ERROR("DM: Backlight registration failed!\n");
4086 else
f1ad2f5e 4087 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b 4088}
4562236b 4089
df534fff 4090static int initialize_plane(struct amdgpu_display_manager *dm,
b2fddb13 4091 struct amdgpu_mode_info *mode_info, int plane_id,
cc1fec57
NK		 4092 enum drm_plane_type plane_type,
4093 const struct dc_plane_cap *plane_cap)
df534fff 4094{
f180b4bc 4095 struct drm_plane *plane;
df534fff
S		 4096 unsigned long possible_crtcs;
4097 int ret = 0;
4098
f180b4bc 4099 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 4100 if (!plane) {
4101 DRM_ERROR("KMS: Failed to allocate plane\n");
4102 return -ENOMEM;
4103 }
b2fddb13 4104 plane->type = plane_type;
df534fff
S		 4105
4106 /*
b2fddb13
NK		 4107 * HACK: IGT tests expect that the primary plane for a CRTC
4108 * can only have one possible CRTC. Only expose support for
4109 * any CRTC if they're not going to be used as a primary plane
4110 * for a CRTC - like overlay or underlay planes.
df534fff
S		 4111 */
4112 possible_crtcs = 1 << plane_id;
4113 if (plane_id >= dm->dc->caps.max_streams)
4114 possible_crtcs = 0xff;
4115
cc1fec57 4116 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
df534fff
S		 4117
4118 if (ret) {
4119 DRM_ERROR("KMS: Failed to initialize plane\n");
54087768 4120 kfree(plane);
df534fff
S		 4121 return ret;
4122 }
4123
54087768
NK		 4124 if (mode_info)
4125 mode_info->planes[plane_id] = plane;
4126
df534fff
S		 4127 return ret;
4128}
4129
89fc8d4e
HW		 4130
4131static void register_backlight_device(struct amdgpu_display_manager *dm,
4132 struct dc_link *link)
4133{
89fc8d4e
HW		 4134 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4135 link->type != dc_connection_none) {
1f6010a9
DF		 4136 /*
4137 * Event if registration failed, we should continue with
89fc8d4e
HW		 4138 * DM initialization because not having a backlight control
4139 * is better then a black screen.
4140 */
7fd13bae 4141 if (!dm->backlight_dev[dm->num_of_edps])
118b4627 4142 amdgpu_dm_register_backlight_device(dm);
89fc8d4e 4143
7fd13bae 4144 if (dm->backlight_dev[dm->num_of_edps]) {
118b4627
ML		 4145 dm->backlight_link[dm->num_of_edps] = link;
4146 dm->num_of_edps++;
4147 }
89fc8d4e 4148 }
89fc8d4e
HW		 4149}
4150
acc96ae0 4151static void amdgpu_set_panel_orientation(struct drm_connector *connector);
89fc8d4e 4152
1f6010a9
DF		 4153/*
4154 * In this architecture, the association
4562236b
HW		 4155 * connector -> encoder -> crtc
4156 * id not really requried. The crtc and connector will hold the
4157 * display_index as an abstraction to use with DAL component
4158 *
4159 * Returns 0 on success
4160 */
7578ecda 4161static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 4162{
4163 struct amdgpu_display_manager *dm = &adev->dm;
ae67558b 4164 s32 i;
c84dec2f 4165 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 4166 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 4167 struct amdgpu_mode_info *mode_info = &adev->mode_info;
ae67558b
SS		 4168 u32 link_cnt;
4169 s32 primary_planes;
fbbdadf2 4170 enum dc_connection_type new_connection_type = dc_connection_none;
cc1fec57 4171 const struct dc_plane_cap *plane;
9470620e 4172 bool psr_feature_enabled = false;
4562236b 4173
d58159de
AD		 4174 dm->display_indexes_num = dm->dc->caps.max_streams;
4175 /* Update the actual used number of crtc */
4176 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4177
4562236b 4178 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 4179 if (amdgpu_dm_mode_config_init(dm->adev)) {
4180 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 4181 return -EINVAL;
4562236b
HW		 4182 }
4183
b2fddb13
NK		 4184 /* There is one primary plane per CRTC */
4185 primary_planes = dm->dc->caps.max_streams;
54087768 4186 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
efa6a8b7 4187
b2fddb13
NK		 4188 /*
4189 * Initialize primary planes, implicit planes for legacy IOCTLS.
4190 * Order is reversed to match iteration order in atomic check.
4191 */
4192 for (i = (primary_planes - 1); i >= 0; i--) {
cc1fec57
NK		 4193 plane = &dm->dc->caps.planes[i];
4194
b2fddb13 4195 if (initialize_plane(dm, mode_info, i,
cc1fec57 4196 DRM_PLANE_TYPE_PRIMARY, plane)) {
df534fff 4197 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 4198 goto fail;
d4e13b0d 4199 }
df534fff 4200 }
92f3ac40 4201
0d579c7e
NK		 4202 /*
4203 * Initialize overlay planes, index starting after primary planes.
4204 * These planes have a higher DRM index than the primary planes since
4205 * they should be considered as having a higher z-order.
4206 * Order is reversed to match iteration order in atomic check.
cc1fec57
NK		 4207 *
4208 * Only support DCN for now, and only expose one so we don't encourage
4209 * userspace to use up all the pipes.
0d579c7e 4210 */
cc1fec57
NK		 4211 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4212 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4213
8813381a
LL		 4214 /* Do not create overlay if MPO disabled */
4215 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4216 break;
4217
cc1fec57
NK		 4218 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4219 continue;
4220
4221 if (!plane->blends_with_above || !plane->blends_with_below)
4222 continue;
4223
ea36ad34 4224 if (!plane->pixel_format_support.argb8888)
cc1fec57
NK		 4225 continue;
4226
54087768 4227 if (initialize_plane(dm, NULL, primary_planes + i,
cc1fec57 4228 DRM_PLANE_TYPE_OVERLAY, plane)) {
0d579c7e 4229 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 4230 goto fail;
d4e13b0d 4231 }
cc1fec57
NK		 4232
4233 /* Only create one overlay plane. */
4234 break;
d4e13b0d 4235 }
4562236b 4236
d4e13b0d 4237 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 4238 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 4239 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 4240 goto fail;
4562236b 4241 }
4562236b 4242
81927e28 4243 /* Use Outbox interrupt */
1d789535 4244 switch (adev->ip_versions[DCE_HWIP][0]) {
c08182f2
AD		 4245 case IP_VERSION(3, 0, 0):
4246 case IP_VERSION(3, 1, 2):
4247 case IP_VERSION(3, 1, 3):
e850f6b1 4248 case IP_VERSION(3, 1, 4):
b5b8ed44 4249 case IP_VERSION(3, 1, 5):
de7cc1b4 4250 case IP_VERSION(3, 1, 6):
577359ca
AP		 4251 case IP_VERSION(3, 2, 0):
4252 case IP_VERSION(3, 2, 1):
c08182f2 4253 case IP_VERSION(2, 1, 0):
81927e28
JS		 4254 if (register_outbox_irq_handlers(dm->adev)) {
4255 DRM_ERROR("DM: Failed to initialize IRQ\n");
4256 goto fail;
4257 }
4258 break;
4259 default:
c08182f2 4260 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
1d789535 4261 adev->ip_versions[DCE_HWIP][0]);
81927e28 4262 }
9470620e
NK		 4263
4264 /* Determine whether to enable PSR support by default. */
4265 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4266 switch (adev->ip_versions[DCE_HWIP][0]) {
4267 case IP_VERSION(3, 1, 2):
4268 case IP_VERSION(3, 1, 3):
e850f6b1 4269 case IP_VERSION(3, 1, 4):
b5b8ed44 4270 case IP_VERSION(3, 1, 5):
de7cc1b4 4271 case IP_VERSION(3, 1, 6):
577359ca
AP		 4272 case IP_VERSION(3, 2, 0):
4273 case IP_VERSION(3, 2, 1):
9470620e
NK		 4274 psr_feature_enabled = true;
4275 break;
4276 default:
4277 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4278 break;
4279 }
4280 }
81927e28 4281
4562236b
HW		 4282 /* loops over all connectors on the board */
4283 for (i = 0; i < link_cnt; i++) {
89fc8d4e 4284 struct dc_link *link = NULL;
4562236b
HW		 4285
4286 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4287 DRM_ERROR(
4288 "KMS: Cannot support more than %d display indexes\n",
4289 AMDGPU_DM_MAX_DISPLAY_INDEX);
4290 continue;
4291 }
4292
4293 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4294 if (!aconnector)
cd8a2ae8 4295 goto fail;
4562236b
HW		 4296
4297 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 4298 if (!aencoder)
cd8a2ae8 4299 goto fail;
4562236b
HW		 4300
4301 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4302 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 4303 goto fail;
4562236b
HW		 4304 }
4305
4306 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4307 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 4308 goto fail;
4562236b
HW		 4309 }
4310
89fc8d4e
HW		 4311 link = dc_get_link_at_index(dm->dc, i);
4312
fbbdadf2
BL		 4313 if (!dc_link_detect_sink(link, &new_connection_type))
4314 DRM_ERROR("KMS: Failed to detect connector\n");
4315
4316 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4317 emulated_link_detect(link);
4318 amdgpu_dm_update_connector_after_detect(aconnector);
15c735e7
WL		 4319 } else {
4320 bool ret = false;
fbbdadf2 4321
15c735e7
WL		 4322 mutex_lock(&dm->dc_lock);
4323 ret = dc_link_detect(link, DETECT_REASON_BOOT);
4324 mutex_unlock(&dm->dc_lock);
4325
4326 if (ret) {
4327 amdgpu_dm_update_connector_after_detect(aconnector);
4328 register_backlight_device(dm, link);
89fc8d4e 4329
15c735e7
WL		 4330 if (dm->num_of_edps)
4331 update_connector_ext_caps(aconnector);
89fc8d4e 4332
15c735e7
WL		 4333 if (psr_feature_enabled)
4334 amdgpu_dm_set_psr_caps(link);
89fc8d4e 4335
15c735e7
WL		 4336 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4337 * PSR is also supported.
4338 */
4339 if (link->psr_settings.psr_feature_enabled)
4340 adev_to_drm(adev)->vblank_disable_immediate = false;
4341 }
4342 }
acc96ae0 4343 amdgpu_set_panel_orientation(&aconnector->base);
4562236b
HW		 4344 }
4345
4346 /* Software is initialized. Now we can register interrupt handlers. */
4347 switch (adev->asic_type) {
55e56389
MR		 4348#if defined(CONFIG_DRM_AMD_DC_SI)
4349 case CHIP_TAHITI:
4350 case CHIP_PITCAIRN:
4351 case CHIP_VERDE:
4352 case CHIP_OLAND:
4353 if (dce60_register_irq_handlers(dm->adev)) {
4354 DRM_ERROR("DM: Failed to initialize IRQ\n");
4355 goto fail;
4356 }
4357 break;
4358#endif
4562236b
HW		 4359 case CHIP_BONAIRE:
4360 case CHIP_HAWAII:
cd4b356f
AD		 4361 case CHIP_KAVERI:
4362 case CHIP_KABINI:
4363 case CHIP_MULLINS:
4562236b
HW		 4364 case CHIP_TONGA:
4365 case CHIP_FIJI:
4366 case CHIP_CARRIZO:
4367 case CHIP_STONEY:
4368 case CHIP_POLARIS11:
4369 case CHIP_POLARIS10:
b264d345 4370 case CHIP_POLARIS12:
7737de91 4371 case CHIP_VEGAM:
2c8ad2d5 4372 case CHIP_VEGA10:
2325ff30 4373 case CHIP_VEGA12:
1fe6bf2f 4374 case CHIP_VEGA20:
4562236b
HW		 4375 if (dce110_register_irq_handlers(dm->adev)) {
4376 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 4377 goto fail;
4562236b
HW		 4378 }
4379 break;
4380 default:
1d789535 4381 switch (adev->ip_versions[DCE_HWIP][0]) {
559f591d
AD		 4382 case IP_VERSION(1, 0, 0):
4383 case IP_VERSION(1, 0, 1):
c08182f2
AD		 4384 case IP_VERSION(2, 0, 2):
4385 case IP_VERSION(2, 0, 3):
4386 case IP_VERSION(2, 0, 0):
4387 case IP_VERSION(2, 1, 0):
4388 case IP_VERSION(3, 0, 0):
4389 case IP_VERSION(3, 0, 2):
4390 case IP_VERSION(3, 0, 3):
4391 case IP_VERSION(3, 0, 1):
4392 case IP_VERSION(3, 1, 2):
4393 case IP_VERSION(3, 1, 3):
e850f6b1 4394 case IP_VERSION(3, 1, 4):
b5b8ed44 4395 case IP_VERSION(3, 1, 5):
de7cc1b4 4396 case IP_VERSION(3, 1, 6):
577359ca
AP		 4397 case IP_VERSION(3, 2, 0):
4398 case IP_VERSION(3, 2, 1):
c08182f2
AD		 4399 if (dcn10_register_irq_handlers(dm->adev)) {
4400 DRM_ERROR("DM: Failed to initialize IRQ\n");
4401 goto fail;
4402 }
4403 break;
4404 default:
2cbc6f42 4405 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
1d789535 4406 adev->ip_versions[DCE_HWIP][0]);
2cbc6f42 4407 goto fail;
c08182f2 4408 }
2cbc6f42 4409 break;
4562236b
HW		 4410 }
4411
4562236b 4412 return 0;
cd8a2ae8 4413fail:
4562236b 4414 kfree(aencoder);
4562236b 4415 kfree(aconnector);
54087768 4416
59d0f396 4417 return -EINVAL;
4562236b
HW		 4418}
4419
7578ecda 4420static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b 4421{
eb3dc897 4422 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 4423 return;
4424}
4425
4426/******************************************************************************
4427 * amdgpu_display_funcs functions
4428 *****************************************************************************/
4429
1f6010a9 4430/*
4562236b
HW		 4431 * dm_bandwidth_update - program display watermarks
4432 *
4433 * @adev: amdgpu_device pointer
4434 *
4435 * Calculate and program the display watermarks and line buffer allocation.
4436 */
4437static void dm_bandwidth_update(struct amdgpu_device *adev)
4438{
49c07a99 4439 /* TODO: implement later */
4562236b
HW		 4440}
4441
39cc5be2 4442static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 4443 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4444 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 4445 .backlight_set_level = NULL, /* never called for DC */
4446 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 4447 .hpd_sense = NULL,/* called unconditionally */
4448 .hpd_set_polarity = NULL, /* called unconditionally */
4449 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 4450 .page_flip_get_scanoutpos =
4451 dm_crtc_get_scanoutpos,/* called unconditionally */
4452 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4453 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 4454};
4455
4456#if defined(CONFIG_DEBUG_KERNEL_DC)
4457
3ee6b26b
AD		 4458static ssize_t s3_debug_store(struct device *device,
4459 struct device_attribute *attr,
4460 const char *buf,
4461 size_t count)
4562236b
HW		 4462{
4463 int ret;
4464 int s3_state;
ef1de361 4465 struct drm_device *drm_dev = dev_get_drvdata(device);
1348969a 4466 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4562236b
HW		 4467
4468 ret = kstrtoint(buf, 0, &s3_state);
4469
4470 if (ret == 0) {
4471 if (s3_state) {
4472 dm_resume(adev);
4a580877 4473 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4562236b
HW		 4474 } else
4475 dm_suspend(adev);
4476 }
4477
4478 return ret == 0 ? count : 0;
4479}
4480
4481DEVICE_ATTR_WO(s3_debug);
4482
4483#endif
4484
a7ab3451
ML		 4485static int dm_init_microcode(struct amdgpu_device *adev)
4486{
4487 char *fw_name_dmub;
4488 int r;
4489
4490 switch (adev->ip_versions[DCE_HWIP][0]) {
4491 case IP_VERSION(2, 1, 0):
4492 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4493 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4494 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4495 break;
4496 case IP_VERSION(3, 0, 0):
4497 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4498 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4499 else
4500 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4501 break;
4502 case IP_VERSION(3, 0, 1):
4503 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4504 break;
4505 case IP_VERSION(3, 0, 2):
4506 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4507 break;
4508 case IP_VERSION(3, 0, 3):
4509 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4510 break;
4511 case IP_VERSION(3, 1, 2):
4512 case IP_VERSION(3, 1, 3):
4513 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4514 break;
4515 case IP_VERSION(3, 1, 4):
4516 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4517 break;
4518 case IP_VERSION(3, 1, 5):
4519 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4520 break;
4521 case IP_VERSION(3, 1, 6):
4522 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4523 break;
4524 case IP_VERSION(3, 2, 0):
4525 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4526 break;
4527 case IP_VERSION(3, 2, 1):
4528 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4529 break;
4530 default:
4531 /* ASIC doesn't support DMUB. */
4532 return 0;
4533 }
4534 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4535 if (r)
4536 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4537 return r;
4538}
4539
4562236b
HW		 4540static int dm_early_init(void *handle)
4541{
4542 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4543
4562236b 4544 switch (adev->asic_type) {
55e56389
MR		 4545#if defined(CONFIG_DRM_AMD_DC_SI)
4546 case CHIP_TAHITI:
4547 case CHIP_PITCAIRN:
4548 case CHIP_VERDE:
4549 adev->mode_info.num_crtc = 6;
4550 adev->mode_info.num_hpd = 6;
4551 adev->mode_info.num_dig = 6;
4552 break;
4553 case CHIP_OLAND:
4554 adev->mode_info.num_crtc = 2;
4555 adev->mode_info.num_hpd = 2;
4556 adev->mode_info.num_dig = 2;
4557 break;
4558#endif
4562236b
HW		 4559 case CHIP_BONAIRE:
4560 case CHIP_HAWAII:
4561 adev->mode_info.num_crtc = 6;
4562 adev->mode_info.num_hpd = 6;
4563 adev->mode_info.num_dig = 6;
4562236b 4564 break;
cd4b356f
AD		 4565 case CHIP_KAVERI:
4566 adev->mode_info.num_crtc = 4;
4567 adev->mode_info.num_hpd = 6;
4568 adev->mode_info.num_dig = 7;
cd4b356f
AD		 4569 break;
4570 case CHIP_KABINI:
4571 case CHIP_MULLINS:
4572 adev->mode_info.num_crtc = 2;
4573 adev->mode_info.num_hpd = 6;
4574 adev->mode_info.num_dig = 6;
cd4b356f 4575 break;
4562236b
HW		 4576 case CHIP_FIJI:
4577 case CHIP_TONGA:
4578 adev->mode_info.num_crtc = 6;
4579 adev->mode_info.num_hpd = 6;
4580 adev->mode_info.num_dig = 7;
4562236b
HW		 4581 break;
4582 case CHIP_CARRIZO:
4583 adev->mode_info.num_crtc = 3;
4584 adev->mode_info.num_hpd = 6;
4585 adev->mode_info.num_dig = 9;
4562236b
HW		 4586 break;
4587 case CHIP_STONEY:
4588 adev->mode_info.num_crtc = 2;
4589 adev->mode_info.num_hpd = 6;
4590 adev->mode_info.num_dig = 9;
4562236b
HW		 4591 break;
4592 case CHIP_POLARIS11:
b264d345 4593 case CHIP_POLARIS12:
4562236b
HW		 4594 adev->mode_info.num_crtc = 5;
4595 adev->mode_info.num_hpd = 5;
4596 adev->mode_info.num_dig = 5;
4562236b
HW		 4597 break;
4598 case CHIP_POLARIS10:
7737de91 4599 case CHIP_VEGAM:
4562236b
HW		 4600 adev->mode_info.num_crtc = 6;
4601 adev->mode_info.num_hpd = 6;
4602 adev->mode_info.num_dig = 6;
4562236b 4603 break;
2c8ad2d5 4604 case CHIP_VEGA10:
2325ff30 4605 case CHIP_VEGA12:
1fe6bf2f 4606 case CHIP_VEGA20:
2c8ad2d5
AD		 4607 adev->mode_info.num_crtc = 6;
4608 adev->mode_info.num_hpd = 6;
4609 adev->mode_info.num_dig = 6;
4610 break;
4562236b 4611 default:
cae5c1ab 4612
1d789535 4613 switch (adev->ip_versions[DCE_HWIP][0]) {
c08182f2
AD		 4614 case IP_VERSION(2, 0, 2):
4615 case IP_VERSION(3, 0, 0):
4616 adev->mode_info.num_crtc = 6;
4617 adev->mode_info.num_hpd = 6;
4618 adev->mode_info.num_dig = 6;
4619 break;
4620 case IP_VERSION(2, 0, 0):
4621 case IP_VERSION(3, 0, 2):
4622 adev->mode_info.num_crtc = 5;
4623 adev->mode_info.num_hpd = 5;
4624 adev->mode_info.num_dig = 5;
4625 break;
4626 case IP_VERSION(2, 0, 3):
4627 case IP_VERSION(3, 0, 3):
4628 adev->mode_info.num_crtc = 2;
4629 adev->mode_info.num_hpd = 2;
4630 adev->mode_info.num_dig = 2;
4631 break;
559f591d
AD		 4632 case IP_VERSION(1, 0, 0):
4633 case IP_VERSION(1, 0, 1):
c08182f2
AD		 4634 case IP_VERSION(3, 0, 1):
4635 case IP_VERSION(2, 1, 0):
4636 case IP_VERSION(3, 1, 2):
4637 case IP_VERSION(3, 1, 3):
e850f6b1 4638 case IP_VERSION(3, 1, 4):
b5b8ed44 4639 case IP_VERSION(3, 1, 5):
de7cc1b4 4640 case IP_VERSION(3, 1, 6):
577359ca
AP		 4641 case IP_VERSION(3, 2, 0):
4642 case IP_VERSION(3, 2, 1):
c08182f2
AD		 4643 adev->mode_info.num_crtc = 4;
4644 adev->mode_info.num_hpd = 4;
4645 adev->mode_info.num_dig = 4;
4646 break;
4647 default:
2cbc6f42 4648 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
1d789535 4649 adev->ip_versions[DCE_HWIP][0]);
2cbc6f42 4650 return -EINVAL;
c08182f2 4651 }
2cbc6f42 4652 break;
4562236b
HW		 4653 }
4654
c8dd5715
MD		 4655 amdgpu_dm_set_irq_funcs(adev);
4656
39cc5be2
AD		 4657 if (adev->mode_info.funcs == NULL)
4658 adev->mode_info.funcs = &dm_display_funcs;
4659
1f6010a9
DF		 4660 /*
4661 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 4662 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 4663 * amdgpu_device_init()
4664 */
4562236b
HW		 4665#if defined(CONFIG_DEBUG_KERNEL_DC)
4666 device_create_file(
4a580877 4667 adev_to_drm(adev)->dev,
4562236b
HW		 4668 &dev_attr_s3_debug);
4669#endif
d09ef243 4670 adev->dc_enabled = true;
4562236b 4671
a7ab3451 4672 return dm_init_microcode(adev);
4562236b
HW		 4673}
4674
e7b07cee
HW		 4675static bool modereset_required(struct drm_crtc_state *crtc_state)
4676{
2afda735 4677 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
e7b07cee
HW		 4678}
4679
7578ecda 4680static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 4681{
4682 drm_encoder_cleanup(encoder);
4683 kfree(encoder);
4684}
4685
4686static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4687 .destroy = amdgpu_dm_encoder_destroy,
4688};
4689
5d945cbc
RS		 4690static int
4691fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4692 const enum surface_pixel_format format,
4693 enum dc_color_space *color_space)
6300b3bd 4694{
5d945cbc 4695 bool full_range;
6300b3bd 4696
5d945cbc
RS		 4697 *color_space = COLOR_SPACE_SRGB;
4698
4699 /* DRM color properties only affect non-RGB formats. */
4700 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4701 return 0;
4702
4703 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4704
4705 switch (plane_state->color_encoding) {
4706 case DRM_COLOR_YCBCR_BT601:
4707 if (full_range)
4708 *color_space = COLOR_SPACE_YCBCR601;
4709 else
4710 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
6300b3bd
MK		 4711 break;
4712
5d945cbc
RS		 4713 case DRM_COLOR_YCBCR_BT709:
4714 if (full_range)
4715 *color_space = COLOR_SPACE_YCBCR709;
4716 else
4717 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
6300b3bd
MK		 4718 break;
4719
5d945cbc
RS		 4720 case DRM_COLOR_YCBCR_BT2020:
4721 if (full_range)
4722 *color_space = COLOR_SPACE_2020_YCBCR;
4723 else
4724 return -EINVAL;
6300b3bd 4725 break;
6300b3bd 4726
5d945cbc
RS		 4727 default:
4728 return -EINVAL;
4729 }
6300b3bd 4730
5d945cbc 4731 return 0;
6300b3bd
MK		 4732}
4733
5d945cbc
RS		 4734static int
4735fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4736 const struct drm_plane_state *plane_state,
ae67558b 4737 const u64 tiling_flags,
5d945cbc
RS		 4738 struct dc_plane_info *plane_info,
4739 struct dc_plane_address *address,
4740 bool tmz_surface,
4741 bool force_disable_dcc)
e7b07cee 4742{
5d945cbc
RS		 4743 const struct drm_framebuffer *fb = plane_state->fb;
4744 const struct amdgpu_framebuffer *afb =
4745 to_amdgpu_framebuffer(plane_state->fb);
4746 int ret;
e7b07cee 4747
5d945cbc 4748 memset(plane_info, 0, sizeof(*plane_info));
e7b07cee 4749
5d945cbc
RS		 4750 switch (fb->format->format) {
4751 case DRM_FORMAT_C8:
4752 plane_info->format =
4753 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4754 break;
4755 case DRM_FORMAT_RGB565:
4756 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4757 break;
4758 case DRM_FORMAT_XRGB8888:
4759 case DRM_FORMAT_ARGB8888:
4760 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4761 break;
4762 case DRM_FORMAT_XRGB2101010:
4763 case DRM_FORMAT_ARGB2101010:
4764 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4765 break;
4766 case DRM_FORMAT_XBGR2101010:
4767 case DRM_FORMAT_ABGR2101010:
4768 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4769 break;
4770 case DRM_FORMAT_XBGR8888:
4771 case DRM_FORMAT_ABGR8888:
4772 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4773 break;
4774 case DRM_FORMAT_NV21:
4775 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4776 break;
4777 case DRM_FORMAT_NV12:
4778 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4779 break;
4780 case DRM_FORMAT_P010:
4781 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4782 break;
4783 case DRM_FORMAT_XRGB16161616F:
4784 case DRM_FORMAT_ARGB16161616F:
4785 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4786 break;
4787 case DRM_FORMAT_XBGR16161616F:
4788 case DRM_FORMAT_ABGR16161616F:
4789 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4790 break;
4791 case DRM_FORMAT_XRGB16161616:
4792 case DRM_FORMAT_ARGB16161616:
4793 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4794 break;
4795 case DRM_FORMAT_XBGR16161616:
4796 case DRM_FORMAT_ABGR16161616:
4797 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4798 break;
4799 default:
4800 DRM_ERROR(
4801 "Unsupported screen format %p4cc\n",
4802 &fb->format->format);
d89f6048 4803 return -EINVAL;
5d945cbc 4804 }
d89f6048 4805
5d945cbc
RS		 4806 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4807 case DRM_MODE_ROTATE_0:
4808 plane_info->rotation = ROTATION_ANGLE_0;
4809 break;
4810 case DRM_MODE_ROTATE_90:
4811 plane_info->rotation = ROTATION_ANGLE_90;
4812 break;
4813 case DRM_MODE_ROTATE_180:
4814 plane_info->rotation = ROTATION_ANGLE_180;
4815 break;
4816 case DRM_MODE_ROTATE_270:
4817 plane_info->rotation = ROTATION_ANGLE_270;
4818 break;
4819 default:
4820 plane_info->rotation = ROTATION_ANGLE_0;
4821 break;
4822 }
695af5f9 4823
695af5f9 4824
5d945cbc
RS		 4825 plane_info->visible = true;
4826 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee 4827
22c42b0e 4828 plane_info->layer_index = plane_state->normalized_zpos;
e7b07cee 4829
5d945cbc
RS		 4830 ret = fill_plane_color_attributes(plane_state, plane_info->format,
4831 &plane_info->color_space);
4832 if (ret)
4833 return ret;
e7b07cee 4834
5d945cbc
RS		 4835 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4836 plane_info->rotation, tiling_flags,
4837 &plane_info->tiling_info,
4838 &plane_info->plane_size,
4839 &plane_info->dcc, address,
4840 tmz_surface, force_disable_dcc);
4841 if (ret)
4842 return ret;
e7b07cee 4843
5d945cbc
RS		 4844 fill_blending_from_plane_state(
4845 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4846 &plane_info->global_alpha, &plane_info->global_alpha_value);
e7b07cee 4847
5d945cbc
RS		 4848 return 0;
4849}
e7b07cee 4850
5d945cbc
RS		 4851static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4852 struct dc_plane_state *dc_plane_state,
4853 struct drm_plane_state *plane_state,
4854 struct drm_crtc_state *crtc_state)
4855{
4856 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4857 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4858 struct dc_scaling_info scaling_info;
4859 struct dc_plane_info plane_info;
4860 int ret;
4861 bool force_disable_dcc = false;
6300b3bd 4862
5d945cbc
RS		 4863 ret = fill_dc_scaling_info(adev, plane_state, &scaling_info);
4864 if (ret)
4865 return ret;
e7b07cee 4866
5d945cbc
RS		 4867 dc_plane_state->src_rect = scaling_info.src_rect;
4868 dc_plane_state->dst_rect = scaling_info.dst_rect;
4869 dc_plane_state->clip_rect = scaling_info.clip_rect;
4870 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
6491f0c0 4871
5d945cbc
RS		 4872 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4873 ret = fill_dc_plane_info_and_addr(adev, plane_state,
4874 afb->tiling_flags,
4875 &plane_info,
4876 &dc_plane_state->address,
4877 afb->tmz_surface,
4878 force_disable_dcc);
4879 if (ret)
4880 return ret;
6491f0c0 4881
5d945cbc
RS		 4882 dc_plane_state->format = plane_info.format;
4883 dc_plane_state->color_space = plane_info.color_space;
4884 dc_plane_state->format = plane_info.format;
4885 dc_plane_state->plane_size = plane_info.plane_size;
4886 dc_plane_state->rotation = plane_info.rotation;
4887 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4888 dc_plane_state->stereo_format = plane_info.stereo_format;
4889 dc_plane_state->tiling_info = plane_info.tiling_info;
4890 dc_plane_state->visible = plane_info.visible;
4891 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4892 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
4893 dc_plane_state->global_alpha = plane_info.global_alpha;
4894 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4895 dc_plane_state->dcc = plane_info.dcc;
22c42b0e 4896 dc_plane_state->layer_index = plane_info.layer_index;
5d945cbc 4897 dc_plane_state->flip_int_enabled = true;
6491f0c0 4898
695af5f9 4899 /*
5d945cbc
RS		 4900 * Always set input transfer function, since plane state is refreshed
4901 * every time.
695af5f9 4902 */
5d945cbc
RS		 4903 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4904 if (ret)
4905 return ret;
e7b07cee 4906
695af5f9 4907 return 0;
4562236b 4908}
695af5f9 4909
30ebe415
HM		 4910static inline void fill_dc_dirty_rect(struct drm_plane *plane,
4911 struct rect *dirty_rect, int32_t x,
ae67558b 4912 s32 y, s32 width, s32 height,
30ebe415
HM		 4913 int *i, bool ffu)
4914{
4915 if (*i > DC_MAX_DIRTY_RECTS)
4916 return;
4917
4918 if (*i == DC_MAX_DIRTY_RECTS)
4919 goto out;
4920
4921 dirty_rect->x = x;
4922 dirty_rect->y = y;
4923 dirty_rect->width = width;
4924 dirty_rect->height = height;
4925
4926 if (ffu)
4927 drm_dbg(plane->dev,
4928 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
4929 plane->base.id, width, height);
4930 else
4931 drm_dbg(plane->dev,
4932 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
4933 plane->base.id, x, y, width, height);
4934
4935out:
4936 (*i)++;
4937}
4938
5d945cbc
RS		 4939/**
4940 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
4941 *
4942 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
4943 * remote fb
4944 * @old_plane_state: Old state of @plane
4945 * @new_plane_state: New state of @plane
4946 * @crtc_state: New state of CRTC connected to the @plane
4947 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
4948 *
4949 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
4950 * (referred to as "damage clips" in DRM nomenclature) that require updating on
4951 * the eDP remote buffer. The responsibility of specifying the dirty regions is
4952 * amdgpu_dm's.
4953 *
4954 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
4955 * plane with regions that require flushing to the eDP remote buffer. In
4956 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
4957 * implicitly provide damage clips without any client support via the plane
4958 * bounds.
5d945cbc
RS		 4959 */
4960static void fill_dc_dirty_rects(struct drm_plane *plane,
4961 struct drm_plane_state *old_plane_state,
4962 struct drm_plane_state *new_plane_state,
4963 struct drm_crtc_state *crtc_state,
4964 struct dc_flip_addrs *flip_addrs)
4965{
4966 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4967 struct rect *dirty_rects = flip_addrs->dirty_rects;
ae67558b 4968 u32 num_clips;
30ebe415 4969 struct drm_mode_rect *clips;
5d945cbc
RS		 4970 bool bb_changed;
4971 bool fb_changed;
ae67558b 4972 u32 i = 0;
e7b07cee 4973
7cc191ee
LL		 4974 /*
4975 * Cursor plane has it's own dirty rect update interface. See
4976 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
4977 */
4978 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4979 return;
4980
30ebe415
HM		 4981 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
4982 clips = drm_plane_get_damage_clips(new_plane_state);
4983
7cc191ee 4984 if (!dm_crtc_state->mpo_requested) {
30ebe415
HM		 4985 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
4986 goto ffu;
4987
4988 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
4989 fill_dc_dirty_rect(new_plane_state->plane,
4990 &dirty_rects[i], clips->x1,
4991 clips->y1, clips->x2 - clips->x1,
4992 clips->y2 - clips->y1,
4993 &flip_addrs->dirty_rect_count,
4994 false);
7cc191ee
LL		 4995 return;
4996 }
4997
4998 /*
4999 * MPO is requested. Add entire plane bounding box to dirty rects if
5000 * flipped to or damaged.
5001 *
5002 * If plane is moved or resized, also add old bounding box to dirty
5003 * rects.
5004 */
7cc191ee
LL		 5005 fb_changed = old_plane_state->fb->base.id !=
5006 new_plane_state->fb->base.id;
5007 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5008 old_plane_state->crtc_y != new_plane_state->crtc_y ||
5009 old_plane_state->crtc_w != new_plane_state->crtc_w ||
5010 old_plane_state->crtc_h != new_plane_state->crtc_h);
5011
30ebe415
HM		 5012 drm_dbg(plane->dev,
5013 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5014 new_plane_state->plane->base.id,
5015 bb_changed, fb_changed, num_clips);
7cc191ee 5016
7cc191ee 5017 if (bb_changed) {
30ebe415
HM		 5018 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5019 new_plane_state->crtc_x,
5020 new_plane_state->crtc_y,
5021 new_plane_state->crtc_w,
5022 new_plane_state->crtc_h, &i, false);
5023
5024 /* Add old plane bounding-box if plane is moved or resized */
5025 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5026 old_plane_state->crtc_x,
5027 old_plane_state->crtc_y,
5028 old_plane_state->crtc_w,
5029 old_plane_state->crtc_h, &i, false);
5030 }
5031
5032 if (num_clips) {
5033 for (; i < num_clips; clips++)
5034 fill_dc_dirty_rect(new_plane_state->plane,
5035 &dirty_rects[i], clips->x1,
5036 clips->y1, clips->x2 - clips->x1,
5037 clips->y2 - clips->y1, &i, false);
5038 } else if (fb_changed && !bb_changed) {
5039 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5040 new_plane_state->crtc_x,
5041 new_plane_state->crtc_y,
5042 new_plane_state->crtc_w,
5043 new_plane_state->crtc_h, &i, false);
5044 }
5045
5046 if (i > DC_MAX_DIRTY_RECTS)
5047 goto ffu;
7cc191ee
LL		 5048
5049 flip_addrs->dirty_rect_count = i;
30ebe415
HM		 5050 return;
5051
5052ffu:
5053 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5054 dm_crtc_state->base.mode.crtc_hdisplay,
5055 dm_crtc_state->base.mode.crtc_vdisplay,
5056 &flip_addrs->dirty_rect_count, true);
7cc191ee
LL		 5057}
5058
3ee6b26b
AD		 5059static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5060 const struct dm_connector_state *dm_state,
5061 struct dc_stream_state *stream)
e7b07cee
HW		 5062{
5063 enum amdgpu_rmx_type rmx_type;
5064
5065 struct rect src = { 0 }; /* viewport in composition space*/
5066 struct rect dst = { 0 }; /* stream addressable area */
5067
5068 /* no mode. nothing to be done */
5069 if (!mode)
5070 return;
5071
5072 /* Full screen scaling by default */
5073 src.width = mode->hdisplay;
5074 src.height = mode->vdisplay;
5075 dst.width = stream->timing.h_addressable;
5076 dst.height = stream->timing.v_addressable;
5077
f4791779
HW		 5078 if (dm_state) {
5079 rmx_type = dm_state->scaling;
5080 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5081 if (src.width * dst.height <
5082 src.height * dst.width) {
5083 /* height needs less upscaling/more downscaling */
5084 dst.width = src.width *
5085 dst.height / src.height;
5086 } else {
5087 /* width needs less upscaling/more downscaling */
5088 dst.height = src.height *
5089 dst.width / src.width;
5090 }
5091 } else if (rmx_type == RMX_CENTER) {
5092 dst = src;
e7b07cee 5093 }
e7b07cee 5094
f4791779
HW		 5095 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5096 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 5097
f4791779
HW		 5098 if (dm_state->underscan_enable) {
5099 dst.x += dm_state->underscan_hborder / 2;
5100 dst.y += dm_state->underscan_vborder / 2;
5101 dst.width -= dm_state->underscan_hborder;
5102 dst.height -= dm_state->underscan_vborder;
5103 }
e7b07cee
HW		 5104 }
5105
5106 stream->src = src;
5107 stream->dst = dst;
5108
4711c033
LT		 5109 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
5110 dst.x, dst.y, dst.width, dst.height);
e7b07cee
HW		 5111
5112}
5113
3ee6b26b 5114static enum dc_color_depth
42ba01fc 5115convert_color_depth_from_display_info(const struct drm_connector *connector,
cbd14ae7 5116 bool is_y420, int requested_bpc)
e7b07cee 5117{
ae67558b 5118 u8 bpc;
01c22997 5119
1bc22f20
SW		 5120 if (is_y420) {
5121 bpc = 8;
5122
5123 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5124 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5125 bpc = 16;
5126 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5127 bpc = 12;
5128 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5129 bpc = 10;
5130 } else {
5131 bpc = (uint8_t)connector->display_info.bpc;
5132 /* Assume 8 bpc by default if no bpc is specified. */
5133 bpc = bpc ? bpc : 8;
5134 }
e7b07cee 5135
cbd14ae7 5136 if (requested_bpc > 0) {
01c22997
NK		 5137 /*
5138 * Cap display bpc based on the user requested value.
5139 *
5140 * The value for state->max_bpc may not correctly updated
5141 * depending on when the connector gets added to the state
5142 * or if this was called outside of atomic check, so it
5143 * can't be used directly.
5144 */
cbd14ae7 5145 bpc = min_t(u8, bpc, requested_bpc);
01c22997 5146
1825fd34
NK		 5147 /* Round down to the nearest even number. */
5148 bpc = bpc - (bpc & 1);
5149 }
07e3a1cf 5150
e7b07cee
HW		 5151 switch (bpc) {
5152 case 0:
1f6010a9
DF		 5153 /*
5154 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 5155 * EDID revision before 1.4
5156 * TODO: Fix edid parsing
5157 */
5158 return COLOR_DEPTH_888;
5159 case 6:
5160 return COLOR_DEPTH_666;
5161 case 8:
5162 return COLOR_DEPTH_888;
5163 case 10:
5164 return COLOR_DEPTH_101010;
5165 case 12:
5166 return COLOR_DEPTH_121212;
5167 case 14:
5168 return COLOR_DEPTH_141414;
5169 case 16:
5170 return COLOR_DEPTH_161616;
5171 default:
5172 return COLOR_DEPTH_UNDEFINED;
5173 }
5174}
5175
3ee6b26b
AD		 5176static enum dc_aspect_ratio
5177get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 5178{
e11d4147
LSL		 5179 /* 1-1 mapping, since both enums follow the HDMI spec. */
5180 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 5181}
5182
3ee6b26b
AD		 5183static enum dc_color_space
5184get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 5185{
5186 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5187
5188 switch (dc_crtc_timing->pixel_encoding) {
5189 case PIXEL_ENCODING_YCBCR422:
5190 case PIXEL_ENCODING_YCBCR444:
5191 case PIXEL_ENCODING_YCBCR420:
5192 {
5193 /*
5194 * 27030khz is the separation point between HDTV and SDTV
5195 * according to HDMI spec, we use YCbCr709 and YCbCr601
5196 * respectively
5197 */
380604e2 5198 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 5199 if (dc_crtc_timing->flags.Y_ONLY)
5200 color_space =
5201 COLOR_SPACE_YCBCR709_LIMITED;
5202 else
5203 color_space = COLOR_SPACE_YCBCR709;
5204 } else {
5205 if (dc_crtc_timing->flags.Y_ONLY)
5206 color_space =
5207 COLOR_SPACE_YCBCR601_LIMITED;
5208 else
5209 color_space = COLOR_SPACE_YCBCR601;
5210 }
5211
5212 }
5213 break;
5214 case PIXEL_ENCODING_RGB:
5215 color_space = COLOR_SPACE_SRGB;
5216 break;
5217
5218 default:
5219 WARN_ON(1);
5220 break;
5221 }
5222
5223 return color_space;
5224}
5225
ea117312
TA		 5226static bool adjust_colour_depth_from_display_info(
5227 struct dc_crtc_timing *timing_out,
5228 const struct drm_display_info *info)
400443e8 5229{
ea117312 5230 enum dc_color_depth depth = timing_out->display_color_depth;
400443e8 5231 int normalized_clk;
400443e8 5232 do {
380604e2 5233 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 5234 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5235 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5236 normalized_clk /= 2;
5237 /* Adjusting pix clock following on HDMI spec based on colour depth */
ea117312
TA		 5238 switch (depth) {
5239 case COLOR_DEPTH_888:
5240 break;
400443e8
ML		 5241 case COLOR_DEPTH_101010:
5242 normalized_clk = (normalized_clk * 30) / 24;
5243 break;
5244 case COLOR_DEPTH_121212:
5245 normalized_clk = (normalized_clk * 36) / 24;
5246 break;
5247 case COLOR_DEPTH_161616:
5248 normalized_clk = (normalized_clk * 48) / 24;
5249 break;
5250 default:
ea117312
TA		 5251 /* The above depths are the only ones valid for HDMI. */
5252 return false;
400443e8 5253 }
ea117312
TA		 5254 if (normalized_clk <= info->max_tmds_clock) {
5255 timing_out->display_color_depth = depth;
5256 return true;
5257 }
5258 } while (--depth > COLOR_DEPTH_666);
5259 return false;
400443e8 5260}
e7b07cee 5261
42ba01fc
NK		 5262static void fill_stream_properties_from_drm_display_mode(
5263 struct dc_stream_state *stream,
5264 const struct drm_display_mode *mode_in,
5265 const struct drm_connector *connector,
5266 const struct drm_connector_state *connector_state,
cbd14ae7
SW		 5267 const struct dc_stream_state *old_stream,
5268 int requested_bpc)
e7b07cee
HW		 5269{
5270 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 5271 const struct drm_display_info *info = &connector->display_info;
d4252eee 5272 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1cb1d477
WL		 5273 struct hdmi_vendor_infoframe hv_frame;
5274 struct hdmi_avi_infoframe avi_frame;
e7b07cee 5275
acf83f86
WL		 5276 memset(&hv_frame, 0, sizeof(hv_frame));
5277 memset(&avi_frame, 0, sizeof(avi_frame));
5278
e7b07cee
HW		 5279 timing_out->h_border_left = 0;
5280 timing_out->h_border_right = 0;
5281 timing_out->v_border_top = 0;
5282 timing_out->v_border_bottom = 0;
5283 /* TODO: un-hardcode */
fe61a2f1 5284 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 5285 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1 5286 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
d4252eee
SW		 5287 else if (drm_mode_is_420_also(info, mode_in)
5288 && aconnector->force_yuv420_output)
5289 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
c03d0b52 5290 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
ceb3dbb4 5291 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 5292 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5293 else
5294 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5295
5296 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5297 timing_out->display_color_depth = convert_color_depth_from_display_info(
cbd14ae7
SW		 5298 connector,
5299 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5300 requested_bpc);
e7b07cee
HW		 5301 timing_out->scan_type = SCANNING_TYPE_NODATA;
5302 timing_out->hdmi_vic = 0;
b333730d 5303
5d945cbc 5304 if (old_stream) {
b333730d
BL		 5305 timing_out->vic = old_stream->timing.vic;
5306 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5307 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5308 } else {
5309 timing_out->vic = drm_match_cea_mode(mode_in);
5310 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5311 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5312 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5313 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5314 }
e7b07cee 5315
1cb1d477
WL		 5316 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5317 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5318 timing_out->vic = avi_frame.video_code;
5319 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5320 timing_out->hdmi_vic = hv_frame.vic;
5321 }
5322
fe8858bb
NC		 5323 if (is_freesync_video_mode(mode_in, aconnector)) {
5324 timing_out->h_addressable = mode_in->hdisplay;
5325 timing_out->h_total = mode_in->htotal;
5326 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5327 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5328 timing_out->v_total = mode_in->vtotal;
5329 timing_out->v_addressable = mode_in->vdisplay;
5330 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5331 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5332 timing_out->pix_clk_100hz = mode_in->clock * 10;
5333 } else {
5334 timing_out->h_addressable = mode_in->crtc_hdisplay;
5335 timing_out->h_total = mode_in->crtc_htotal;
5336 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5337 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5338 timing_out->v_total = mode_in->crtc_vtotal;
5339 timing_out->v_addressable = mode_in->crtc_vdisplay;
5340 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5341 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5342 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5343 }
a85ba005 5344
e7b07cee 5345 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 5346
5347 stream->output_color_space = get_output_color_space(timing_out);
5348
e43a432c
AK		 5349 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5350 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ea117312
TA		 5351 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5352 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5353 drm_mode_is_420_also(info, mode_in) &&
5354 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5355 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5356 adjust_colour_depth_from_display_info(timing_out, info);
5357 }
5358 }
e7b07cee
HW		 5359}
5360
3ee6b26b
AD		 5361static void fill_audio_info(struct audio_info *audio_info,
5362 const struct drm_connector *drm_connector,
5363 const struct dc_sink *dc_sink)
e7b07cee
HW		 5364{
5365 int i = 0;
5366 int cea_revision = 0;
5367 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5368
5369 audio_info->manufacture_id = edid_caps->manufacturer_id;
5370 audio_info->product_id = edid_caps->product_id;
5371
5372 cea_revision = drm_connector->display_info.cea_rev;
5373
090afc1e 5374 strscpy(audio_info->display_name,
d2b2562c 5375 edid_caps->display_name,
090afc1e 5376 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 5377
b830ebc9 5378 if (cea_revision >= 3) {
e7b07cee
HW		 5379 audio_info->mode_count = edid_caps->audio_mode_count;
5380
5381 for (i = 0; i < audio_info->mode_count; ++i) {
5382 audio_info->modes[i].format_code =
5383 (enum audio_format_code)
5384 (edid_caps->audio_modes[i].format_code);
5385 audio_info->modes[i].channel_count =
5386 edid_caps->audio_modes[i].channel_count;
5387 audio_info->modes[i].sample_rates.all =
5388 edid_caps->audio_modes[i].sample_rate;
5389 audio_info->modes[i].sample_size =
5390 edid_caps->audio_modes[i].sample_size;
5391 }
5392 }
5393
5394 audio_info->flags.all = edid_caps->speaker_flags;
5395
5396 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 5397 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 5398 audio_info->video_latency = drm_connector->video_latency[0];
5399 audio_info->audio_latency = drm_connector->audio_latency[0];
5400 }
5401
5402 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5403
5404}
5405
3ee6b26b
AD		 5406static void
5407copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5408 struct drm_display_mode *dst_mode)
e7b07cee
HW		 5409{
5410 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5411 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5412 dst_mode->crtc_clock = src_mode->crtc_clock;
5413 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5414 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 5415 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 5416 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5417 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5418 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5419 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5420 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5421 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5422 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5423 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5424}
5425
3ee6b26b
AD		 5426static void
5427decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5428 const struct drm_display_mode *native_mode,
5429 bool scale_enabled)
e7b07cee
HW		 5430{
5431 if (scale_enabled) {
5432 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5433 } else if (native_mode->clock == drm_mode->clock &&
5434 native_mode->htotal == drm_mode->htotal &&
5435 native_mode->vtotal == drm_mode->vtotal) {
5436 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5437 } else {
5438 /* no scaling nor amdgpu inserted, no need to patch */
5439 }
5440}
5441
aed15309
ML		 5442static struct dc_sink *
5443create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 5444{
2e0ac3d6 5445 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 5446 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 5447 sink_init_data.link = aconnector->dc_link;
5448 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5449
5450 sink = dc_sink_create(&sink_init_data);
423788c7 5451 if (!sink) {
2e0ac3d6 5452 DRM_ERROR("Failed to create sink!\n");
aed15309 5453 return NULL;
423788c7 5454 }
2e0ac3d6 5455 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 5456
aed15309 5457 return sink;
2e0ac3d6
HW		 5458}
5459
fa2123db
ML		 5460static void set_multisync_trigger_params(
5461 struct dc_stream_state *stream)
5462{
ec372186
ML		 5463 struct dc_stream_state *master = NULL;
5464
fa2123db 5465 if (stream->triggered_crtc_reset.enabled) {
ec372186
ML		 5466 master = stream->triggered_crtc_reset.event_source;
5467 stream->triggered_crtc_reset.event =
5468 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5469 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5470 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
fa2123db
ML		 5471 }
5472}
5473
5474static void set_master_stream(struct dc_stream_state *stream_set[],
5475 int stream_count)
5476{
5477 int j, highest_rfr = 0, master_stream = 0;
5478
5479 for (j = 0; j < stream_count; j++) {
5480 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5481 int refresh_rate = 0;
5482
380604e2 5483 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 5484 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5485 if (refresh_rate > highest_rfr) {
5486 highest_rfr = refresh_rate;
5487 master_stream = j;
5488 }
5489 }
5490 }
5491 for (j = 0; j < stream_count; j++) {
03736f4c 5492 if (stream_set[j])
fa2123db
ML		 5493 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5494 }
5495}
5496
5497static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5498{
5499 int i = 0;
ec372186 5500 struct dc_stream_state *stream;
fa2123db
ML		 5501
5502 if (context->stream_count < 2)
5503 return;
5504 for (i = 0; i < context->stream_count ; i++) {
5505 if (!context->streams[i])
5506 continue;
1f6010a9
DF		 5507 /*
5508 * TODO: add a function to read AMD VSDB bits and set
fa2123db 5509 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 5510 * For now it's set to false
fa2123db 5511 */
fa2123db 5512 }
ec372186 5513
fa2123db 5514 set_master_stream(context->streams, context->stream_count);
ec372186
ML		 5515
5516 for (i = 0; i < context->stream_count ; i++) {
5517 stream = context->streams[i];
5518
5519 if (!stream)
5520 continue;
5521
5522 set_multisync_trigger_params(stream);
5523 }
fa2123db
ML		 5524}
5525
5d945cbc
RS		 5526/**
5527 * DOC: FreeSync Video
5528 *
5529 * When a userspace application wants to play a video, the content follows a
5530 * standard format definition that usually specifies the FPS for that format.
5531 * The below list illustrates some video format and the expected FPS,
5532 * respectively:
5533 *
5534 * - TV/NTSC (23.976 FPS)
5535 * - Cinema (24 FPS)
5536 * - TV/PAL (25 FPS)
5537 * - TV/NTSC (29.97 FPS)
5538 * - TV/NTSC (30 FPS)
5539 * - Cinema HFR (48 FPS)
5540 * - TV/PAL (50 FPS)
5541 * - Commonly used (60 FPS)
5542 * - Multiples of 24 (48,72,96 FPS)
5543 *
5544 * The list of standards video format is not huge and can be added to the
5545 * connector modeset list beforehand. With that, userspace can leverage
5546 * FreeSync to extends the front porch in order to attain the target refresh
5547 * rate. Such a switch will happen seamlessly, without screen blanking or
5548 * reprogramming of the output in any other way. If the userspace requests a
5549 * modesetting change compatible with FreeSync modes that only differ in the
5550 * refresh rate, DC will skip the full update and avoid blink during the
5551 * transition. For example, the video player can change the modesetting from
5552 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5553 * causing any display blink. This same concept can be applied to a mode
5554 * setting change.
5555 */
5556static struct drm_display_mode *
5557get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5558 bool use_probed_modes)
5559{
5560 struct drm_display_mode *m, *m_pref = NULL;
5561 u16 current_refresh, highest_refresh;
5562 struct list_head *list_head = use_probed_modes ?
5563 &aconnector->base.probed_modes :
5564 &aconnector->base.modes;
5565
5566 if (aconnector->freesync_vid_base.clock != 0)
5567 return &aconnector->freesync_vid_base;
5568
5569 /* Find the preferred mode */
5570 list_for_each_entry (m, list_head, head) {
5571 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5572 m_pref = m;
5573 break;
5574 }
5575 }
5576
5577 if (!m_pref) {
5578 /* Probably an EDID with no preferred mode. Fallback to first entry */
5579 m_pref = list_first_entry_or_null(
5580 &aconnector->base.modes, struct drm_display_mode, head);
5581 if (!m_pref) {
5582 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5583 return NULL;
5584 }
5585 }
5586
5587 highest_refresh = drm_mode_vrefresh(m_pref);
5588
5589 /*
5590 * Find the mode with highest refresh rate with same resolution.
5591 * For some monitors, preferred mode is not the mode with highest
5592 * supported refresh rate.
5593 */
5594 list_for_each_entry (m, list_head, head) {
5595 current_refresh = drm_mode_vrefresh(m);
5596
5597 if (m->hdisplay == m_pref->hdisplay &&
5598 m->vdisplay == m_pref->vdisplay &&
5599 highest_refresh < current_refresh) {
5600 highest_refresh = current_refresh;
5601 m_pref = m;
5602 }
5603 }
5604
5605 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5606 return m_pref;
5607}
5608
5609static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5610 struct amdgpu_dm_connector *aconnector)
5611{
5612 struct drm_display_mode *high_mode;
5613 int timing_diff;
5614
5615 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5616 if (!high_mode || !mode)
5617 return false;
5618
5619 timing_diff = high_mode->vtotal - mode->vtotal;
5620
5621 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5622 high_mode->hdisplay != mode->hdisplay ||
5623 high_mode->vdisplay != mode->vdisplay ||
5624 high_mode->hsync_start != mode->hsync_start ||
5625 high_mode->hsync_end != mode->hsync_end ||
5626 high_mode->htotal != mode->htotal ||
5627 high_mode->hskew != mode->hskew ||
5628 high_mode->vscan != mode->vscan ||
5629 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5630 high_mode->vsync_end - mode->vsync_end != timing_diff)
5631 return false;
5632 else
5633 return true;
5634}
5635
ea2be5c0 5636#if defined(CONFIG_DRM_AMD_DC_DCN)
998b7ad2 5637static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5d945cbc
RS		 5638 struct dc_sink *sink, struct dc_stream_state *stream,
5639 struct dsc_dec_dpcd_caps *dsc_caps)
998b7ad2
FZ		 5640{
5641 stream->timing.flags.DSC = 0;
63ad5371 5642 dsc_caps->is_dsc_supported = false;
998b7ad2 5643
2665f63a 5644 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5d945cbc 5645 sink->sink_signal == SIGNAL_TYPE_EDP)) {
50b1f44e
FZ		 5646 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5647 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5648 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5649 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5650 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5651 dsc_caps);
998b7ad2
FZ		 5652 }
5653}
5654
5d945cbc 5655
2665f63a
ML		 5656static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5657 struct dc_sink *sink, struct dc_stream_state *stream,
5658 struct dsc_dec_dpcd_caps *dsc_caps,
5659 uint32_t max_dsc_target_bpp_limit_override)
5660{
5661 const struct dc_link_settings *verified_link_cap = NULL;
ae67558b
SS		 5662 u32 link_bw_in_kbps;
5663 u32 edp_min_bpp_x16, edp_max_bpp_x16;
2665f63a
ML		 5664 struct dc *dc = sink->ctx->dc;
5665 struct dc_dsc_bw_range bw_range = {0};
5666 struct dc_dsc_config dsc_cfg = {0};
5667
5668 verified_link_cap = dc_link_get_link_cap(stream->link);
5669 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5670 edp_min_bpp_x16 = 8 * 16;
5671 edp_max_bpp_x16 = 8 * 16;
5672
5673 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5674 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5675
5676 if (edp_max_bpp_x16 < edp_min_bpp_x16)
5677 edp_min_bpp_x16 = edp_max_bpp_x16;
5678
5679 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5680 dc->debug.dsc_min_slice_height_override,
5681 edp_min_bpp_x16, edp_max_bpp_x16,
5682 dsc_caps,
5683 &stream->timing,
5684 &bw_range)) {
5685
5686 if (bw_range.max_kbps < link_bw_in_kbps) {
5687 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5688 dsc_caps,
5689 dc->debug.dsc_min_slice_height_override,
5690 max_dsc_target_bpp_limit_override,
5691 0,
5692 &stream->timing,
5693 &dsc_cfg)) {
5694 stream->timing.dsc_cfg = dsc_cfg;
5695 stream->timing.flags.DSC = 1;
5696 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5697 }
5698 return;
5699 }
5700 }
5701
5702 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5703 dsc_caps,
5704 dc->debug.dsc_min_slice_height_override,
5705 max_dsc_target_bpp_limit_override,
5706 link_bw_in_kbps,
5707 &stream->timing,
5708 &dsc_cfg)) {
5709 stream->timing.dsc_cfg = dsc_cfg;
5710 stream->timing.flags.DSC = 1;
5711 }
5712}
5713
5d945cbc 5714
998b7ad2 5715static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5d945cbc
RS		 5716 struct dc_sink *sink, struct dc_stream_state *stream,
5717 struct dsc_dec_dpcd_caps *dsc_caps)
998b7ad2
FZ		 5718{
5719 struct drm_connector *drm_connector = &aconnector->base;
ae67558b 5720 u32 link_bandwidth_kbps;
2665f63a 5721 struct dc *dc = sink->ctx->dc;
ae67558b
SS		 5722 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5723 u32 dsc_max_supported_bw_in_kbps;
5724 u32 max_dsc_target_bpp_limit_override =
6e5abe94 5725 drm_connector->display_info.max_dsc_bpp;
998b7ad2
FZ		 5726
5727 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5728 dc_link_get_link_cap(aconnector->dc_link));
de7cc1b4 5729
998b7ad2
FZ		 5730 /* Set DSC policy according to dsc_clock_en */
5731 dc_dsc_policy_set_enable_dsc_when_not_needed(
5732 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5733
c17a34e0
IC		 5734 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5735 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
2665f63a
ML		 5736 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5737
5738 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5739
5740 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
50b1f44e
FZ		 5741 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5742 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
998b7ad2
FZ		 5743 dsc_caps,
5744 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
f1c1a982 5745 max_dsc_target_bpp_limit_override,
998b7ad2
FZ		 5746 link_bandwidth_kbps,
5747 &stream->timing,
5748 &stream->timing.dsc_cfg)) {
50b1f44e 5749 stream->timing.flags.DSC = 1;
5d945cbc 5750 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
50b1f44e
FZ		 5751 }
5752 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5753 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5754 max_supported_bw_in_kbps = link_bandwidth_kbps;
5755 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5756
5757 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5758 max_supported_bw_in_kbps > 0 &&
5759 dsc_max_supported_bw_in_kbps > 0)
5760 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5761 dsc_caps,
5762 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5763 max_dsc_target_bpp_limit_override,
5764 dsc_max_supported_bw_in_kbps,
5765 &stream->timing,
5766 &stream->timing.dsc_cfg)) {
5767 stream->timing.flags.DSC = 1;
5768 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5769 __func__, drm_connector->name);
5770 }
998b7ad2
FZ		 5771 }
5772 }
5773
5774 /* Overwrite the stream flag if DSC is enabled through debugfs */
5775 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5776 stream->timing.flags.DSC = 1;
5777
5d945cbc
RS		 5778 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5779 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
a85ba005 5780
5d945cbc
RS		 5781 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5782 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
a85ba005 5783
5d945cbc
RS		 5784 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5785 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
a85ba005 5786}
5d945cbc 5787#endif /* CONFIG_DRM_AMD_DC_DCN */
a85ba005 5788
f11d9373 5789static struct dc_stream_state *
3ee6b26b
AD		 5790create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5791 const struct drm_display_mode *drm_mode,
b333730d 5792 const struct dm_connector_state *dm_state,
cbd14ae7
SW		 5793 const struct dc_stream_state *old_stream,
5794 int requested_bpc)
e7b07cee
HW		 5795{
5796 struct drm_display_mode *preferred_mode = NULL;
391ef035 5797 struct drm_connector *drm_connector;
42ba01fc
NK		 5798 const struct drm_connector_state *con_state =
5799 dm_state ? &dm_state->base : NULL;
0971c40e 5800 struct dc_stream_state *stream = NULL;
0a204ce0 5801 struct drm_display_mode mode;
a85ba005
NC		 5802 struct drm_display_mode saved_mode;
5803 struct drm_display_mode *freesync_mode = NULL;
e7b07cee 5804 bool native_mode_found = false;
b0781603
NK		 5805 bool recalculate_timing = false;
5806 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
b333730d 5807 int mode_refresh;
58124bf8 5808 int preferred_refresh = 0;
b1a98cf8 5809 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
defeb878 5810#if defined(CONFIG_DRM_AMD_DC_DCN)
df2f1015 5811 struct dsc_dec_dpcd_caps dsc_caps;
7c431455 5812#endif
5d945cbc 5813
aed15309 5814 struct dc_sink *sink = NULL;
a85ba005 5815
0a204ce0 5816 drm_mode_init(&mode, drm_mode);
a85ba005
NC		 5817 memset(&saved_mode, 0, sizeof(saved_mode));
5818
b830ebc9 5819 if (aconnector == NULL) {
e7b07cee 5820 DRM_ERROR("aconnector is NULL!\n");
64245fa7 5821 return stream;
e7b07cee
HW		 5822 }
5823
e7b07cee 5824 drm_connector = &aconnector->base;
2e0ac3d6 5825
f4ac176e 5826 if (!aconnector->dc_sink) {
e3fa5c4c
JFZ		 5827 sink = create_fake_sink(aconnector);
5828 if (!sink)
5829 return stream;
aed15309
ML		 5830 } else {
5831 sink = aconnector->dc_sink;
dcd5fb82 5832 dc_sink_retain(sink);
f4ac176e 5833 }
2e0ac3d6 5834
aed15309 5835 stream = dc_create_stream_for_sink(sink);
4562236b 5836
b830ebc9 5837 if (stream == NULL) {
e7b07cee 5838 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 5839 goto finish;
e7b07cee
HW		 5840 }
5841
ceb3dbb4
JL		 5842 stream->dm_stream_context = aconnector;
5843
4a36fcba
WL		 5844 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5845 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5846
e7b07cee
HW		 5847 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5848 /* Search for preferred mode */
5849 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5850 native_mode_found = true;
5851 break;
5852 }
5853 }
5854 if (!native_mode_found)
5855 preferred_mode = list_first_entry_or_null(
5856 &aconnector->base.modes,
5857 struct drm_display_mode,
5858 head);
5859
b333730d
BL		 5860 mode_refresh = drm_mode_vrefresh(&mode);
5861
b830ebc9 5862 if (preferred_mode == NULL) {
1f6010a9
DF		 5863 /*
5864 * This may not be an error, the use case is when we have no
e7b07cee
HW		 5865 * usermode calls to reset and set mode upon hotplug. In this
5866 * case, we call set mode ourselves to restore the previous mode
5867 * and the modelist may not be filled in in time.
5868 */
f1ad2f5e 5869 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee 5870 } else {
4243c84a
MD		 5871 recalculate_timing = amdgpu_freesync_vid_mode &&
5872 is_freesync_video_mode(&mode, aconnector);
a85ba005
NC		 5873 if (recalculate_timing) {
5874 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
426c89aa
VS		 5875 drm_mode_copy(&saved_mode, &mode);
5876 drm_mode_copy(&mode, freesync_mode);
a85ba005
NC		 5877 } else {
5878 decide_crtc_timing_for_drm_display_mode(
5d945cbc 5879 &mode, preferred_mode, scale);
a85ba005 5880
b0781603
NK		 5881 preferred_refresh = drm_mode_vrefresh(preferred_mode);
5882 }
e7b07cee
HW		 5883 }
5884
a85ba005
NC		 5885 if (recalculate_timing)
5886 drm_mode_set_crtcinfo(&saved_mode, 0);
fe8858bb 5887 else if (!dm_state)
f783577c
JFZ		 5888 drm_mode_set_crtcinfo(&mode, 0);
5889
5d945cbc 5890 /*
b333730d
BL		 5891 * If scaling is enabled and refresh rate didn't change
5892 * we copy the vic and polarities of the old timings
5893 */
b0781603 5894 if (!scale || mode_refresh != preferred_refresh)
a85ba005
NC		 5895 fill_stream_properties_from_drm_display_mode(
5896 stream, &mode, &aconnector->base, con_state, NULL,
5897 requested_bpc);
b333730d 5898 else
a85ba005
NC		 5899 fill_stream_properties_from_drm_display_mode(
5900 stream, &mode, &aconnector->base, con_state, old_stream,
5901 requested_bpc);
b333730d 5902
defeb878 5903#if defined(CONFIG_DRM_AMD_DC_DCN)
998b7ad2
FZ		 5904 /* SST DSC determination policy */
5905 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
5906 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
5907 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
39a4eb85
WL		 5908#endif
5909
e7b07cee
HW		 5910 update_stream_scaling_settings(&mode, dm_state, stream);
5911
5912 fill_audio_info(
5913 &stream->audio_info,
5914 drm_connector,
aed15309 5915 sink);
e7b07cee 5916
ceb3dbb4 5917 update_stream_signal(stream, sink);
9182b4cb 5918
d832fc3b 5919 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
75f77aaf
WL		 5920 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5921
8a488f5d
RL		 5922 if (stream->link->psr_settings.psr_feature_enabled) {
5923 //
5924 // should decide stream support vsc sdp colorimetry capability
5925 // before building vsc info packet
5926 //
5927 stream->use_vsc_sdp_for_colorimetry = false;
5928 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5929 stream->use_vsc_sdp_for_colorimetry =
5930 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5931 } else {
5932 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5933 stream->use_vsc_sdp_for_colorimetry = true;
8c322309 5934 }
b1a98cf8
MH		 5935 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
5936 tf = TRANSFER_FUNC_GAMMA_22;
5937 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
1a365683
RL		 5938 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
5939
8c322309 5940 }
aed15309 5941finish:
dcd5fb82 5942 dc_sink_release(sink);
9e3efe3e 5943
e7b07cee
HW		 5944 return stream;
5945}
5946
e7b07cee
HW		 5947static enum drm_connector_status
5948amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5949{
5950 bool connected;
c84dec2f 5951 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 5952
1f6010a9
DF		 5953 /*
5954 * Notes:
e7b07cee
HW		 5955 * 1. This interface is NOT called in context of HPD irq.
5956 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 5957 * makes it a bad place for *any* MST-related activity.
5958 */
e7b07cee 5959
8580d60b
HW		 5960 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
5961 !aconnector->fake_enable)
e7b07cee
HW		 5962 connected = (aconnector->dc_sink != NULL);
5963 else
5d945cbc
RS		 5964 connected = (aconnector->base.force == DRM_FORCE_ON ||
5965 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
e7b07cee 5966
0f877894
OV		 5967 update_subconnector_property(aconnector);
5968
e7b07cee
HW		 5969 return (connected ? connector_status_connected :
5970 connector_status_disconnected);
5971}
5972
3ee6b26b
AD		 5973int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
5974 struct drm_connector_state *connector_state,
5975 struct drm_property *property,
5976 uint64_t val)
e7b07cee
HW		 5977{
5978 struct drm_device *dev = connector->dev;
1348969a 5979 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 5980 struct dm_connector_state *dm_old_state =
5981 to_dm_connector_state(connector->state);
5982 struct dm_connector_state *dm_new_state =
5983 to_dm_connector_state(connector_state);
5984
5985 int ret = -EINVAL;
5986
5987 if (property == dev->mode_config.scaling_mode_property) {
5988 enum amdgpu_rmx_type rmx_type;
5989
5990 switch (val) {
5991 case DRM_MODE_SCALE_CENTER:
5992 rmx_type = RMX_CENTER;
5993 break;
5994 case DRM_MODE_SCALE_ASPECT:
5995 rmx_type = RMX_ASPECT;
5996 break;
5997 case DRM_MODE_SCALE_FULLSCREEN:
5998 rmx_type = RMX_FULL;
5999 break;
6000 case DRM_MODE_SCALE_NONE:
6001 default:
6002 rmx_type = RMX_OFF;
6003 break;
6004 }
6005
6006 if (dm_old_state->scaling == rmx_type)
6007 return 0;
6008
6009 dm_new_state->scaling = rmx_type;
6010 ret = 0;
6011 } else if (property == adev->mode_info.underscan_hborder_property) {
6012 dm_new_state->underscan_hborder = val;
6013 ret = 0;
6014 } else if (property == adev->mode_info.underscan_vborder_property) {
6015 dm_new_state->underscan_vborder = val;
6016 ret = 0;
6017 } else if (property == adev->mode_info.underscan_property) {
6018 dm_new_state->underscan_enable = val;
6019 ret = 0;
c1ee92f9
DF		 6020 } else if (property == adev->mode_info.abm_level_property) {
6021 dm_new_state->abm_level = val;
6022 ret = 0;
e7b07cee
HW		 6023 }
6024
6025 return ret;
6026}
6027
3ee6b26b
AD		 6028int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6029 const struct drm_connector_state *state,
6030 struct drm_property *property,
6031 uint64_t *val)
e7b07cee
HW		 6032{
6033 struct drm_device *dev = connector->dev;
1348969a 6034 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 6035 struct dm_connector_state *dm_state =
6036 to_dm_connector_state(state);
6037 int ret = -EINVAL;
6038
6039 if (property == dev->mode_config.scaling_mode_property) {
6040 switch (dm_state->scaling) {
6041 case RMX_CENTER:
6042 *val = DRM_MODE_SCALE_CENTER;
6043 break;
6044 case RMX_ASPECT:
6045 *val = DRM_MODE_SCALE_ASPECT;
6046 break;
6047 case RMX_FULL:
6048 *val = DRM_MODE_SCALE_FULLSCREEN;
6049 break;
6050 case RMX_OFF:
6051 default:
6052 *val = DRM_MODE_SCALE_NONE;
6053 break;
6054 }
6055 ret = 0;
6056 } else if (property == adev->mode_info.underscan_hborder_property) {
6057 *val = dm_state->underscan_hborder;
6058 ret = 0;
6059 } else if (property == adev->mode_info.underscan_vborder_property) {
6060 *val = dm_state->underscan_vborder;
6061 ret = 0;
6062 } else if (property == adev->mode_info.underscan_property) {
6063 *val = dm_state->underscan_enable;
6064 ret = 0;
c1ee92f9
DF		 6065 } else if (property == adev->mode_info.abm_level_property) {
6066 *val = dm_state->abm_level;
6067 ret = 0;
e7b07cee 6068 }
c1ee92f9 6069
e7b07cee
HW		 6070 return ret;
6071}
6072
526c654a
ED		 6073static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6074{
6075 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6076
6077 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6078}
6079
7578ecda 6080static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 6081{
c84dec2f 6082 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 6083 const struct dc_link *link = aconnector->dc_link;
1348969a 6084 struct amdgpu_device *adev = drm_to_adev(connector->dev);
e7b07cee 6085 struct amdgpu_display_manager *dm = &adev->dm;
7fd13bae 6086 int i;
ada8ce15 6087
5dff80bd 6088 /*
5d945cbc 6089 * Call only if mst_mgr was initialized before since it's not done
5dff80bd
AG		 6090 * for all connector types.
6091 */
6092 if (aconnector->mst_mgr.dev)
6093 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6094
5d945cbc
RS		 6095#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
6096 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
7fd13bae
AD		 6097 for (i = 0; i < dm->num_of_edps; i++) {
6098 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
6099 backlight_device_unregister(dm->backlight_dev[i]);
6100 dm->backlight_dev[i] = NULL;
6101 }
e7b07cee 6102 }
5d945cbc 6103#endif
dcd5fb82
MF		 6104
6105 if (aconnector->dc_em_sink)
6106 dc_sink_release(aconnector->dc_em_sink);
6107 aconnector->dc_em_sink = NULL;
6108 if (aconnector->dc_sink)
6109 dc_sink_release(aconnector->dc_sink);
6110 aconnector->dc_sink = NULL;
6111
e86e8947 6112 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 6113 drm_connector_unregister(connector);
6114 drm_connector_cleanup(connector);
526c654a
ED		 6115 if (aconnector->i2c) {
6116 i2c_del_adapter(&aconnector->i2c->base);
6117 kfree(aconnector->i2c);
6118 }
7daec99f 6119 kfree(aconnector->dm_dp_aux.aux.name);
526c654a 6120
e7b07cee
HW		 6121 kfree(connector);
6122}
6123
6124void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6125{
6126 struct dm_connector_state *state =
6127 to_dm_connector_state(connector->state);
6128
df099b9b
LSL		 6129 if (connector->state)
6130 __drm_atomic_helper_connector_destroy_state(connector->state);
6131
e7b07cee
HW		 6132 kfree(state);
6133
6134 state = kzalloc(sizeof(*state), GFP_KERNEL);
6135
6136 if (state) {
6137 state->scaling = RMX_OFF;
6138 state->underscan_enable = false;
6139 state->underscan_hborder = 0;
6140 state->underscan_vborder = 0;
01933ba4 6141 state->base.max_requested_bpc = 8;
3261e013
ML		 6142 state->vcpi_slots = 0;
6143 state->pbn = 0;
5d945cbc 6144
c3e50f89
NK		 6145 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6146 state->abm_level = amdgpu_dm_abm_level;
6147
df099b9b 6148 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 6149 }
6150}
6151
3ee6b26b
AD		 6152struct drm_connector_state *
6153amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 6154{
6155 struct dm_connector_state *state =
6156 to_dm_connector_state(connector->state);
6157
6158 struct dm_connector_state *new_state =
6159 kmemdup(state, sizeof(*state), GFP_KERNEL);
6160
98e6436d
AK		 6161 if (!new_state)
6162 return NULL;
e7b07cee 6163
98e6436d
AK		 6164 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6165
6166 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 6167 new_state->abm_level = state->abm_level;
922454c2
NK		 6168 new_state->scaling = state->scaling;
6169 new_state->underscan_enable = state->underscan_enable;
6170 new_state->underscan_hborder = state->underscan_hborder;
6171 new_state->underscan_vborder = state->underscan_vborder;
3261e013
ML		 6172 new_state->vcpi_slots = state->vcpi_slots;
6173 new_state->pbn = state->pbn;
98e6436d 6174 return &new_state->base;
e7b07cee
HW		 6175}
6176
14f04fa4
AD		 6177static int
6178amdgpu_dm_connector_late_register(struct drm_connector *connector)
6179{
6180 struct amdgpu_dm_connector *amdgpu_dm_connector =
6181 to_amdgpu_dm_connector(connector);
00a8037e 6182 int r;
14f04fa4 6183
00a8037e
AD		 6184 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6185 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6186 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6187 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6188 if (r)
6189 return r;
6190 }
6191
6192#if defined(CONFIG_DEBUG_FS)
14f04fa4
AD		 6193 connector_debugfs_init(amdgpu_dm_connector);
6194#endif
6195
6196 return 0;
6197}
6198
e7b07cee
HW		 6199static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6200 .reset = amdgpu_dm_connector_funcs_reset,
6201 .detect = amdgpu_dm_connector_detect,
6202 .fill_modes = drm_helper_probe_single_connector_modes,
6203 .destroy = amdgpu_dm_connector_destroy,
6204 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6205 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6206 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
526c654a 6207 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
14f04fa4 6208 .late_register = amdgpu_dm_connector_late_register,
526c654a 6209 .early_unregister = amdgpu_dm_connector_unregister
e7b07cee
HW		 6210};
6211
e7b07cee
HW		 6212static int get_modes(struct drm_connector *connector)
6213{
6214 return amdgpu_dm_connector_get_modes(connector);
6215}
6216
c84dec2f 6217static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 6218{
6219 struct dc_sink_init_data init_params = {
6220 .link = aconnector->dc_link,
6221 .sink_signal = SIGNAL_TYPE_VIRTUAL
6222 };
70e8ffc5 6223 struct edid *edid;
e7b07cee 6224
a89ff457 6225 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 6226 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6227 aconnector->base.name);
6228
6229 aconnector->base.force = DRM_FORCE_OFF;
e7b07cee
HW		 6230 return;
6231 }
6232
70e8ffc5
HW		 6233 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6234
e7b07cee
HW		 6235 aconnector->edid = edid;
6236
6237 aconnector->dc_em_sink = dc_link_add_remote_sink(
6238 aconnector->dc_link,
6239 (uint8_t *)edid,
6240 (edid->extensions + 1) * EDID_LENGTH,
6241 &init_params);
6242
dcd5fb82 6243 if (aconnector->base.force == DRM_FORCE_ON) {
e7b07cee
HW		 6244 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6245 aconnector->dc_link->local_sink :
6246 aconnector->dc_em_sink;
dcd5fb82
MF		 6247 dc_sink_retain(aconnector->dc_sink);
6248 }
e7b07cee
HW		 6249}
6250
c84dec2f 6251static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 6252{
6253 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6254
1f6010a9
DF		 6255 /*
6256 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 6257 * Those settings have to be != 0 to get initial modeset
6258 */
6259 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6260 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6261 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6262 }
6263
e7b07cee
HW		 6264 create_eml_sink(aconnector);
6265}
6266
5468c36d
FZ		 6267static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6268 struct dc_stream_state *stream)
6269{
6270 enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6271 struct dc_plane_state *dc_plane_state = NULL;
6272 struct dc_state *dc_state = NULL;
6273
6274 if (!stream)
6275 goto cleanup;
6276
6277 dc_plane_state = dc_create_plane_state(dc);
6278 if (!dc_plane_state)
6279 goto cleanup;
6280
6281 dc_state = dc_create_state(dc);
6282 if (!dc_state)
6283 goto cleanup;
6284
6285 /* populate stream to plane */
6286 dc_plane_state->src_rect.height = stream->src.height;
6287 dc_plane_state->src_rect.width = stream->src.width;
6288 dc_plane_state->dst_rect.height = stream->src.height;
6289 dc_plane_state->dst_rect.width = stream->src.width;
6290 dc_plane_state->clip_rect.height = stream->src.height;
6291 dc_plane_state->clip_rect.width = stream->src.width;
6292 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6293 dc_plane_state->plane_size.surface_size.height = stream->src.height;
6294 dc_plane_state->plane_size.surface_size.width = stream->src.width;
6295 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
6296 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
6297 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6298 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6299 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6300 dc_plane_state->rotation = ROTATION_ANGLE_0;
6301 dc_plane_state->is_tiling_rotated = false;
6302 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6303
6304 dc_result = dc_validate_stream(dc, stream);
6305 if (dc_result == DC_OK)
6306 dc_result = dc_validate_plane(dc, dc_plane_state);
6307
6308 if (dc_result == DC_OK)
6309 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6310
6311 if (dc_result == DC_OK && !dc_add_plane_to_context(
6312 dc,
6313 stream,
6314 dc_plane_state,
6315 dc_state))
6316 dc_result = DC_FAIL_ATTACH_SURFACES;
6317
6318 if (dc_result == DC_OK)
6319 dc_result = dc_validate_global_state(dc, dc_state, true);
6320
6321cleanup:
6322 if (dc_state)
6323 dc_release_state(dc_state);
6324
6325 if (dc_plane_state)
6326 dc_plane_state_release(dc_plane_state);
6327
6328 return dc_result;
6329}
6330
17ce8a69 6331struct dc_stream_state *
cbd14ae7
SW		 6332create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6333 const struct drm_display_mode *drm_mode,
6334 const struct dm_connector_state *dm_state,
6335 const struct dc_stream_state *old_stream)
6336{
6337 struct drm_connector *connector = &aconnector->base;
1348969a 6338 struct amdgpu_device *adev = drm_to_adev(connector->dev);
cbd14ae7 6339 struct dc_stream_state *stream;
4b7da34b
SW		 6340 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6341 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
cbd14ae7
SW		 6342 enum dc_status dc_result = DC_OK;
6343
6344 do {
6345 stream = create_stream_for_sink(aconnector, drm_mode,
6346 dm_state, old_stream,
6347 requested_bpc);
6348 if (stream == NULL) {
6349 DRM_ERROR("Failed to create stream for sink!\n");
6350 break;
6351 }
6352
e9a7d236
RS		 6353 dc_result = dc_validate_stream(adev->dm.dc, stream);
6354 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
f04d275d 6355 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6356
5468c36d
FZ		 6357 if (dc_result == DC_OK)
6358 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6359
cbd14ae7 6360 if (dc_result != DC_OK) {
74a16675 6361 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
cbd14ae7
SW		 6362 drm_mode->hdisplay,
6363 drm_mode->vdisplay,
6364 drm_mode->clock,
74a16675
RS		 6365 dc_result,
6366 dc_status_to_str(dc_result));
cbd14ae7
SW		 6367
6368 dc_stream_release(stream);
6369 stream = NULL;
6370 requested_bpc -= 2; /* lower bpc to retry validation */
6371 }
6372
6373 } while (stream == NULL && requested_bpc >= 6);
6374
68eb3ae3
WS		 6375 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6376 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6377
6378 aconnector->force_yuv420_output = true;
6379 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6380 dm_state, old_stream);
6381 aconnector->force_yuv420_output = false;
6382 }
6383
cbd14ae7
SW		 6384 return stream;
6385}
6386
ba9ca088 6387enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 6388 struct drm_display_mode *mode)
e7b07cee
HW		 6389{
6390 int result = MODE_ERROR;
6391 struct dc_sink *dc_sink;
e7b07cee 6392 /* TODO: Unhardcode stream count */
0971c40e 6393 struct dc_stream_state *stream;
c84dec2f 6394 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 6395
6396 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6397 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6398 return result;
6399
1f6010a9
DF		 6400 /*
6401 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 6402 * EDID mgmt
6403 */
6404 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6405 !aconnector->dc_em_sink)
6406 handle_edid_mgmt(aconnector);
6407
c84dec2f 6408 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 6409
ad975f44
VL		 6410 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6411 aconnector->base.force != DRM_FORCE_ON) {
e7b07cee
HW		 6412 DRM_ERROR("dc_sink is NULL!\n");
6413 goto fail;
6414 }
6415
cbd14ae7
SW		 6416 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6417 if (stream) {
6418 dc_stream_release(stream);
e7b07cee 6419 result = MODE_OK;
cbd14ae7 6420 }
e7b07cee
HW		 6421
6422fail:
6423 /* TODO: error handling*/
6424 return result;
6425}
6426
88694af9
NK		 6427static int fill_hdr_info_packet(const struct drm_connector_state *state,
6428 struct dc_info_packet *out)
6429{
6430 struct hdmi_drm_infoframe frame;
6431 unsigned char buf[30]; /* 26 + 4 */
6432 ssize_t len;
6433 int ret, i;
6434
6435 memset(out, 0, sizeof(*out));
6436
6437 if (!state->hdr_output_metadata)
6438 return 0;
6439
6440 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6441 if (ret)
6442 return ret;
6443
6444 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6445 if (len < 0)
6446 return (int)len;
6447
6448 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6449 if (len != 30)
6450 return -EINVAL;
6451
6452 /* Prepare the infopacket for DC. */
6453 switch (state->connector->connector_type) {
6454 case DRM_MODE_CONNECTOR_HDMIA:
6455 out->hb0 = 0x87; /* type */
6456 out->hb1 = 0x01; /* version */
6457 out->hb2 = 0x1A; /* length */
6458 out->sb[0] = buf[3]; /* checksum */
6459 i = 1;
6460 break;
6461
6462 case DRM_MODE_CONNECTOR_DisplayPort:
6463 case DRM_MODE_CONNECTOR_eDP:
6464 out->hb0 = 0x00; /* sdp id, zero */
6465 out->hb1 = 0x87; /* type */
6466 out->hb2 = 0x1D; /* payload len - 1 */
6467 out->hb3 = (0x13 << 2); /* sdp version */
6468 out->sb[0] = 0x01; /* version */
6469 out->sb[1] = 0x1A; /* length */
6470 i = 2;
6471 break;
6472
6473 default:
6474 return -EINVAL;
6475 }
6476
6477 memcpy(&out->sb[i], &buf[4], 26);
6478 out->valid = true;
6479
6480 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6481 sizeof(out->sb), false);
6482
6483 return 0;
6484}
6485
88694af9
NK		 6486static int
6487amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
51e857af 6488 struct drm_atomic_state *state)
88694af9 6489{
51e857af
SP		 6490 struct drm_connector_state *new_con_state =
6491 drm_atomic_get_new_connector_state(state, conn);
88694af9
NK		 6492 struct drm_connector_state *old_con_state =
6493 drm_atomic_get_old_connector_state(state, conn);
6494 struct drm_crtc *crtc = new_con_state->crtc;
6495 struct drm_crtc_state *new_crtc_state;
a76eb429 6496 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
88694af9
NK		 6497 int ret;
6498
e8a98235
RS		 6499 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6500
a76eb429
LP		 6501 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6502 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6503 if (ret < 0)
6504 return ret;
6505 }
6506
88694af9
NK		 6507 if (!crtc)
6508 return 0;
6509
72921cdf 6510 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
88694af9
NK		 6511 struct dc_info_packet hdr_infopacket;
6512
6513 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6514 if (ret)
6515 return ret;
6516
6517 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6518 if (IS_ERR(new_crtc_state))
6519 return PTR_ERR(new_crtc_state);
6520
6521 /*
6522 * DC considers the stream backends changed if the
6523 * static metadata changes. Forcing the modeset also
6524 * gives a simple way for userspace to switch from
b232d4ed
NK		 6525 * 8bpc to 10bpc when setting the metadata to enter
6526 * or exit HDR.
6527 *
6528 * Changing the static metadata after it's been
6529 * set is permissible, however. So only force a
6530 * modeset if we're entering or exiting HDR.
88694af9 6531 */
b232d4ed
NK		 6532 new_crtc_state->mode_changed =
6533 !old_con_state->hdr_output_metadata ||
6534 !new_con_state->hdr_output_metadata;
88694af9
NK		 6535 }
6536
6537 return 0;
6538}
6539
e7b07cee
HW		 6540static const struct drm_connector_helper_funcs
6541amdgpu_dm_connector_helper_funcs = {
6542 /*
1f6010a9 6543 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 6544 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 6545 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 6546 * in get_modes call back, not just return the modes count
6547 */
e7b07cee
HW		 6548 .get_modes = get_modes,
6549 .mode_valid = amdgpu_dm_connector_mode_valid,
88694af9 6550 .atomic_check = amdgpu_dm_connector_atomic_check,
e7b07cee
HW		 6551};
6552
e7b07cee
HW		 6553static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6554{
6555
6556}
6557
f04d275d 6558int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
3261e013
ML		 6559{
6560 switch (display_color_depth) {
5d945cbc
RS		 6561 case COLOR_DEPTH_666:
6562 return 6;
6563 case COLOR_DEPTH_888:
6564 return 8;
6565 case COLOR_DEPTH_101010:
6566 return 10;
6567 case COLOR_DEPTH_121212:
6568 return 12;
6569 case COLOR_DEPTH_141414:
6570 return 14;
6571 case COLOR_DEPTH_161616:
6572 return 16;
6573 default:
6574 break;
6575 }
3261e013
ML		 6576 return 0;
6577}
6578
3ee6b26b
AD		 6579static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6580 struct drm_crtc_state *crtc_state,
6581 struct drm_connector_state *conn_state)
e7b07cee 6582{
3261e013
ML		 6583 struct drm_atomic_state *state = crtc_state->state;
6584 struct drm_connector *connector = conn_state->connector;
6585 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6586 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6587 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6588 struct drm_dp_mst_topology_mgr *mst_mgr;
6589 struct drm_dp_mst_port *mst_port;
4d07b0bc 6590 struct drm_dp_mst_topology_state *mst_state;
3261e013
ML		 6591 enum dc_color_depth color_depth;
6592 int clock, bpp = 0;
1bc22f20 6593 bool is_y420 = false;
3261e013
ML		 6594
6595 if (!aconnector->port || !aconnector->dc_sink)
6596 return 0;
6597
6598 mst_port = aconnector->port;
6599 mst_mgr = &aconnector->mst_port->mst_mgr;
6600
6601 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6602 return 0;
6603
4d07b0bc
LP		 6604 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6605 if (IS_ERR(mst_state))
6606 return PTR_ERR(mst_state);
6607
6608 if (!mst_state->pbn_div)
6609 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_port->dc_link);
6610
3261e013 6611 if (!state->duplicated) {
cbd14ae7 6612 int max_bpc = conn_state->max_requested_bpc;
1bc22f20 6613 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
5d945cbc 6614 aconnector->force_yuv420_output;
cbd14ae7
SW		 6615 color_depth = convert_color_depth_from_display_info(connector,
6616 is_y420,
6617 max_bpc);
3261e013
ML		 6618 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6619 clock = adjusted_mode->clock;
dc48529f 6620 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
3261e013 6621 }
4d07b0bc
LP		 6622
6623 dm_new_connector_state->vcpi_slots =
6624 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6625 dm_new_connector_state->pbn);
3261e013
ML		 6626 if (dm_new_connector_state->vcpi_slots < 0) {
6627 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6628 return dm_new_connector_state->vcpi_slots;
6629 }
e7b07cee
HW		 6630 return 0;
6631}
6632
6633const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6634 .disable = dm_encoder_helper_disable,
6635 .atomic_check = dm_encoder_helper_atomic_check
6636};
6637
d9fe1a4c 6638#if defined(CONFIG_DRM_AMD_DC_DCN)
29b9ba74 6639static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6513104b
HW		 6640 struct dc_state *dc_state,
6641 struct dsc_mst_fairness_vars *vars)
29b9ba74
ML		 6642{
6643 struct dc_stream_state *stream = NULL;
6644 struct drm_connector *connector;
5760dcb9 6645 struct drm_connector_state *new_con_state;
29b9ba74
ML		 6646 struct amdgpu_dm_connector *aconnector;
6647 struct dm_connector_state *dm_conn_state;
7cce4cd6 6648 int i, j, ret;
a550bb16 6649 int vcpi, pbn_div, pbn, slot_num = 0;
29b9ba74 6650
5760dcb9 6651 for_each_new_connector_in_state(state, connector, new_con_state, i) {
29b9ba74
ML		 6652
6653 aconnector = to_amdgpu_dm_connector(connector);
6654
6655 if (!aconnector->port)
6656 continue;
6657
6658 if (!new_con_state || !new_con_state->crtc)
6659 continue;
6660
6661 dm_conn_state = to_dm_connector_state(new_con_state);
6662
6663 for (j = 0; j < dc_state->stream_count; j++) {
6664 stream = dc_state->streams[j];
6665 if (!stream)
6666 continue;
6667
5d945cbc 6668 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
29b9ba74
ML		 6669 break;
6670
6671 stream = NULL;
6672 }
6673
6674 if (!stream)
6675 continue;
6676
29b9ba74 6677 pbn_div = dm_mst_get_pbn_divider(stream->link);
6513104b
HW		 6678 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6679 for (j = 0; j < dc_state->stream_count; j++) {
6680 if (vars[j].aconnector == aconnector) {
6681 pbn = vars[j].pbn;
6682 break;
6683 }
6684 }
6685
a550bb16
HW		 6686 if (j == dc_state->stream_count)
6687 continue;
6688
6689 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6690
6691 if (stream->timing.flags.DSC != 1) {
6692 dm_conn_state->pbn = pbn;
6693 dm_conn_state->vcpi_slots = slot_num;
6694
7cce4cd6
LP		 6695 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->port,
6696 dm_conn_state->pbn, false);
6697 if (ret < 0)
6698 return ret;
6699
a550bb16
HW		 6700 continue;
6701 }
6702
4d07b0bc 6703 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, pbn, true);
29b9ba74
ML		 6704 if (vcpi < 0)
6705 return vcpi;
6706
6707 dm_conn_state->pbn = pbn;
6708 dm_conn_state->vcpi_slots = vcpi;
6709 }
6710 return 0;
6711}
d9fe1a4c 6712#endif
29b9ba74 6713
e7b07cee
HW		 6714static int to_drm_connector_type(enum signal_type st)
6715{
6716 switch (st) {
6717 case SIGNAL_TYPE_HDMI_TYPE_A:
6718 return DRM_MODE_CONNECTOR_HDMIA;
6719 case SIGNAL_TYPE_EDP:
6720 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 6721 case SIGNAL_TYPE_LVDS:
6722 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 6723 case SIGNAL_TYPE_RGB:
6724 return DRM_MODE_CONNECTOR_VGA;
6725 case SIGNAL_TYPE_DISPLAY_PORT:
6726 case SIGNAL_TYPE_DISPLAY_PORT_MST:
6727 return DRM_MODE_CONNECTOR_DisplayPort;
6728 case SIGNAL_TYPE_DVI_DUAL_LINK:
6729 case SIGNAL_TYPE_DVI_SINGLE_LINK:
6730 return DRM_MODE_CONNECTOR_DVID;
6731 case SIGNAL_TYPE_VIRTUAL:
6732 return DRM_MODE_CONNECTOR_VIRTUAL;
6733
6734 default:
6735 return DRM_MODE_CONNECTOR_Unknown;
6736 }
6737}
6738
2b4c1c05
DV		 6739static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6740{
62afb4ad
JRS		 6741 struct drm_encoder *encoder;
6742
6743 /* There is only one encoder per connector */
6744 drm_connector_for_each_possible_encoder(connector, encoder)
6745 return encoder;
6746
6747 return NULL;
2b4c1c05
DV		 6748}
6749
e7b07cee
HW		 6750static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6751{
e7b07cee
HW		 6752 struct drm_encoder *encoder;
6753 struct amdgpu_encoder *amdgpu_encoder;
6754
2b4c1c05 6755 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 6756
6757 if (encoder == NULL)
6758 return;
6759
6760 amdgpu_encoder = to_amdgpu_encoder(encoder);
6761
6762 amdgpu_encoder->native_mode.clock = 0;
6763
6764 if (!list_empty(&connector->probed_modes)) {
6765 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 6766
e7b07cee 6767 list_for_each_entry(preferred_mode,
b830ebc9
HW		 6768 &connector->probed_modes,
6769 head) {
6770 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6771 amdgpu_encoder->native_mode = *preferred_mode;
6772
e7b07cee
HW		 6773 break;
6774 }
6775
6776 }
6777}
6778
3ee6b26b
AD		 6779static struct drm_display_mode *
6780amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6781 char *name,
6782 int hdisplay, int vdisplay)
e7b07cee
HW		 6783{
6784 struct drm_device *dev = encoder->dev;
6785 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6786 struct drm_display_mode *mode = NULL;
6787 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6788
6789 mode = drm_mode_duplicate(dev, native_mode);
6790
b830ebc9 6791 if (mode == NULL)
e7b07cee
HW		 6792 return NULL;
6793
6794 mode->hdisplay = hdisplay;
6795 mode->vdisplay = vdisplay;
6796 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 6797 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 6798
6799 return mode;
6800
6801}
6802
6803static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 6804 struct drm_connector *connector)
e7b07cee
HW		 6805{
6806 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6807 struct drm_display_mode *mode = NULL;
6808 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 6809 struct amdgpu_dm_connector *amdgpu_dm_connector =
6810 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 6811 int i;
6812 int n;
6813 struct mode_size {
6814 char name[DRM_DISPLAY_MODE_LEN];
6815 int w;
6816 int h;
b830ebc9 6817 } common_modes[] = {
e7b07cee
HW		 6818 { "640x480", 640, 480},
6819 { "800x600", 800, 600},
6820 { "1024x768", 1024, 768},
6821 { "1280x720", 1280, 720},
6822 { "1280x800", 1280, 800},
6823 {"1280x1024", 1280, 1024},
6824 { "1440x900", 1440, 900},
6825 {"1680x1050", 1680, 1050},
6826 {"1600x1200", 1600, 1200},
6827 {"1920x1080", 1920, 1080},
6828 {"1920x1200", 1920, 1200}
6829 };
6830
b830ebc9 6831 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 6832
6833 for (i = 0; i < n; i++) {
6834 struct drm_display_mode *curmode = NULL;
6835 bool mode_existed = false;
6836
6837 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 6838 common_modes[i].h > native_mode->vdisplay ||
6839 (common_modes[i].w == native_mode->hdisplay &&
6840 common_modes[i].h == native_mode->vdisplay))
6841 continue;
e7b07cee
HW		 6842
6843 list_for_each_entry(curmode, &connector->probed_modes, head) {
6844 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 6845 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 6846 mode_existed = true;
6847 break;
6848 }
6849 }
6850
6851 if (mode_existed)
6852 continue;
6853
6854 mode = amdgpu_dm_create_common_mode(encoder,
6855 common_modes[i].name, common_modes[i].w,
6856 common_modes[i].h);
588a7017
ZQ		 6857 if (!mode)
6858 continue;
6859
e7b07cee 6860 drm_mode_probed_add(connector, mode);
c84dec2f 6861 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 6862 }
6863}
6864
d77de788
SS		 6865static void amdgpu_set_panel_orientation(struct drm_connector *connector)
6866{
6867 struct drm_encoder *encoder;
6868 struct amdgpu_encoder *amdgpu_encoder;
6869 const struct drm_display_mode *native_mode;
6870
6871 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
6872 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
6873 return;
6874
acc96ae0
MW		 6875 mutex_lock(&connector->dev->mode_config.mutex);
6876 amdgpu_dm_connector_get_modes(connector);
6877 mutex_unlock(&connector->dev->mode_config.mutex);
6878
d77de788
SS		 6879 encoder = amdgpu_dm_connector_to_encoder(connector);
6880 if (!encoder)
6881 return;
6882
6883 amdgpu_encoder = to_amdgpu_encoder(encoder);
6884
6885 native_mode = &amdgpu_encoder->native_mode;
6886 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
6887 return;
6888
6889 drm_connector_set_panel_orientation_with_quirk(connector,
6890 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
6891 native_mode->hdisplay,
6892 native_mode->vdisplay);
6893}
6894
3ee6b26b
AD		 6895static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
6896 struct edid *edid)
e7b07cee 6897{
c84dec2f
HW		 6898 struct amdgpu_dm_connector *amdgpu_dm_connector =
6899 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 6900
6901 if (edid) {
6902 /* empty probed_modes */
6903 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 6904 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 6905 drm_add_edid_modes(connector, edid);
6906
f1e5e913
YMM		 6907 /* sorting the probed modes before calling function
6908 * amdgpu_dm_get_native_mode() since EDID can have
6909 * more than one preferred mode. The modes that are
6910 * later in the probed mode list could be of higher
6911 * and preferred resolution. For example, 3840x2160
6912 * resolution in base EDID preferred timing and 4096x2160
6913 * preferred resolution in DID extension block later.
6914 */
6915 drm_mode_sort(&connector->probed_modes);
e7b07cee 6916 amdgpu_dm_get_native_mode(connector);
f9b4f20c
SW		 6917
6918 /* Freesync capabilities are reset by calling
6919 * drm_add_edid_modes() and need to be
6920 * restored here.
6921 */
6922 amdgpu_dm_update_freesync_caps(connector, edid);
a8d8d3dc 6923 } else {
c84dec2f 6924 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 6925 }
e7b07cee
HW		 6926}
6927
a85ba005
NC		 6928static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
6929 struct drm_display_mode *mode)
6930{
6931 struct drm_display_mode *m;
6932
6933 list_for_each_entry (m, &aconnector->base.probed_modes, head) {
6934 if (drm_mode_equal(m, mode))
6935 return true;
6936 }
6937
6938 return false;
6939}
6940
6941static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
6942{
6943 const struct drm_display_mode *m;
6944 struct drm_display_mode *new_mode;
6945 uint i;
ae67558b 6946 u32 new_modes_count = 0;
a85ba005
NC		 6947
6948 /* Standard FPS values
6949 *
12cdff6b
SC		 6950 * 23.976 - TV/NTSC
6951 * 24 - Cinema
6952 * 25 - TV/PAL
6953 * 29.97 - TV/NTSC
6954 * 30 - TV/NTSC
6955 * 48 - Cinema HFR
6956 * 50 - TV/PAL
6957 * 60 - Commonly used
6958 * 48,72,96,120 - Multiples of 24
a85ba005 6959 */
ae67558b 6960 static const u32 common_rates[] = {
9ce5ed6e 6961 23976, 24000, 25000, 29970, 30000,
12cdff6b 6962 48000, 50000, 60000, 72000, 96000, 120000
9ce5ed6e 6963 };
a85ba005
NC		 6964
6965 /*
6966 * Find mode with highest refresh rate with the same resolution
6967 * as the preferred mode. Some monitors report a preferred mode
6968 * with lower resolution than the highest refresh rate supported.
6969 */
6970
6971 m = get_highest_refresh_rate_mode(aconnector, true);
6972 if (!m)
6973 return 0;
6974
6975 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
ae67558b
SS		 6976 u64 target_vtotal, target_vtotal_diff;
6977 u64 num, den;
a85ba005
NC		 6978
6979 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
6980 continue;
6981
6982 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
6983 common_rates[i] > aconnector->max_vfreq * 1000)
6984 continue;
6985
6986 num = (unsigned long long)m->clock * 1000 * 1000;
6987 den = common_rates[i] * (unsigned long long)m->htotal;
6988 target_vtotal = div_u64(num, den);
6989 target_vtotal_diff = target_vtotal - m->vtotal;
6990
6991 /* Check for illegal modes */
6992 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
6993 m->vsync_end + target_vtotal_diff < m->vsync_start ||
6994 m->vtotal + target_vtotal_diff < m->vsync_end)
6995 continue;
6996
6997 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
6998 if (!new_mode)
6999 goto out;
7000
7001 new_mode->vtotal += (u16)target_vtotal_diff;
7002 new_mode->vsync_start += (u16)target_vtotal_diff;
7003 new_mode->vsync_end += (u16)target_vtotal_diff;
7004 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7005 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7006
7007 if (!is_duplicate_mode(aconnector, new_mode)) {
7008 drm_mode_probed_add(&aconnector->base, new_mode);
7009 new_modes_count += 1;
7010 } else
7011 drm_mode_destroy(aconnector->base.dev, new_mode);
7012 }
7013 out:
7014 return new_modes_count;
7015}
7016
7017static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7018 struct edid *edid)
7019{
7020 struct amdgpu_dm_connector *amdgpu_dm_connector =
7021 to_amdgpu_dm_connector(connector);
7022
4243c84a 7023 if (!(amdgpu_freesync_vid_mode && edid))
a85ba005 7024 return;
fe8858bb 7025
a85ba005
NC		 7026 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7027 amdgpu_dm_connector->num_modes +=
7028 add_fs_modes(amdgpu_dm_connector);
7029}
7030
7578ecda 7031static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 7032{
c84dec2f
HW		 7033 struct amdgpu_dm_connector *amdgpu_dm_connector =
7034 to_amdgpu_dm_connector(connector);
e7b07cee 7035 struct drm_encoder *encoder;
c84dec2f 7036 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 7037
2b4c1c05 7038 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 7039
5c0e6840 7040 if (!drm_edid_is_valid(edid)) {
1b369d3c
ML		 7041 amdgpu_dm_connector->num_modes =
7042 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 7043 } else {
7044 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7045 amdgpu_dm_connector_add_common_modes(encoder, connector);
a85ba005 7046 amdgpu_dm_connector_add_freesync_modes(connector, edid);
85ee15d6 7047 }
3e332d3a 7048 amdgpu_dm_fbc_init(connector);
5099114b 7049
c84dec2f 7050 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 7051}
7052
3ee6b26b
AD		 7053void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7054 struct amdgpu_dm_connector *aconnector,
7055 int connector_type,
7056 struct dc_link *link,
7057 int link_index)
e7b07cee 7058{
1348969a 7059 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
e7b07cee 7060
f04bee34
NK		 7061 /*
7062 * Some of the properties below require access to state, like bpc.
7063 * Allocate some default initial connector state with our reset helper.
7064 */
7065 if (aconnector->base.funcs->reset)
7066 aconnector->base.funcs->reset(&aconnector->base);
7067
e7b07cee
HW		 7068 aconnector->connector_id = link_index;
7069 aconnector->dc_link = link;
7070 aconnector->base.interlace_allowed = false;
7071 aconnector->base.doublescan_allowed = false;
7072 aconnector->base.stereo_allowed = false;
7073 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7074 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
6ce8f316 7075 aconnector->audio_inst = -1;
e7b07cee
HW		 7076 mutex_init(&aconnector->hpd_lock);
7077
1f6010a9
DF		 7078 /*
7079 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 7080 * which means HPD hot plug not supported
7081 */
e7b07cee
HW		 7082 switch (connector_type) {
7083 case DRM_MODE_CONNECTOR_HDMIA:
7084 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 7085 aconnector->base.ycbcr_420_allowed =
9ea59d5a 7086 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 7087 break;
7088 case DRM_MODE_CONNECTOR_DisplayPort:
7089 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
d715c9a2 7090 link->link_enc = link_enc_cfg_get_link_enc(link);
7b201d53 7091 ASSERT(link->link_enc);
f6e03f80
JS		 7092 if (link->link_enc)
7093 aconnector->base.ycbcr_420_allowed =
9ea59d5a 7094 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 7095 break;
7096 case DRM_MODE_CONNECTOR_DVID:
7097 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7098 break;
7099 default:
7100 break;
7101 }
7102
7103 drm_object_attach_property(&aconnector->base.base,
7104 dm->ddev->mode_config.scaling_mode_property,
7105 DRM_MODE_SCALE_NONE);
7106
7107 drm_object_attach_property(&aconnector->base.base,
7108 adev->mode_info.underscan_property,
7109 UNDERSCAN_OFF);
7110 drm_object_attach_property(&aconnector->base.base,
7111 adev->mode_info.underscan_hborder_property,
7112 0);
7113 drm_object_attach_property(&aconnector->base.base,
7114 adev->mode_info.underscan_vborder_property,
7115 0);
1825fd34 7116
8c61b31e
JFZ		 7117 if (!aconnector->mst_port)
7118 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
1825fd34 7119
4a8ca46b
RL		 7120 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7121 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
7122 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
e7b07cee 7123
c1ee92f9 7124 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5cb32419 7125 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
c1ee92f9
DF		 7126 drm_object_attach_property(&aconnector->base.base,
7127 adev->mode_info.abm_level_property, 0);
7128 }
bb47de73
NK		 7129
7130 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7fad8da1
NK		 7131 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7132 connector_type == DRM_MODE_CONNECTOR_eDP) {
e057b52c 7133 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
88694af9 7134
8c61b31e
JFZ		 7135 if (!aconnector->mst_port)
7136 drm_connector_attach_vrr_capable_property(&aconnector->base);
7137
0c8620d6 7138#ifdef CONFIG_DRM_AMD_DC_HDCP
e22bb562 7139 if (adev->dm.hdcp_workqueue)
53e108aa 7140 drm_connector_attach_content_protection_property(&aconnector->base, true);
0c8620d6 7141#endif
bb47de73 7142 }
e7b07cee
HW		 7143}
7144
7578ecda
AD		 7145static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7146 struct i2c_msg *msgs, int num)
e7b07cee
HW		 7147{
7148 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7149 struct ddc_service *ddc_service = i2c->ddc_service;
7150 struct i2c_command cmd;
7151 int i;
7152 int result = -EIO;
7153
b830ebc9 7154 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 7155
7156 if (!cmd.payloads)
7157 return result;
7158
7159 cmd.number_of_payloads = num;
7160 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7161 cmd.speed = 100;
7162
7163 for (i = 0; i < num; i++) {
7164 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7165 cmd.payloads[i].address = msgs[i].addr;
7166 cmd.payloads[i].length = msgs[i].len;
7167 cmd.payloads[i].data = msgs[i].buf;
7168 }
7169
c85e6e54
DF		 7170 if (dc_submit_i2c(
7171 ddc_service->ctx->dc,
22676bc5 7172 ddc_service->link->link_index,
e7b07cee
HW		 7173 &cmd))
7174 result = num;
7175
7176 kfree(cmd.payloads);
7177 return result;
7178}
7179
7578ecda 7180static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 7181{
7182 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7183}
7184
7185static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7186 .master_xfer = amdgpu_dm_i2c_xfer,
7187 .functionality = amdgpu_dm_i2c_func,
7188};
7189
3ee6b26b
AD		 7190static struct amdgpu_i2c_adapter *
7191create_i2c(struct ddc_service *ddc_service,
7192 int link_index,
7193 int *res)
e7b07cee
HW		 7194{
7195 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7196 struct amdgpu_i2c_adapter *i2c;
7197
b830ebc9 7198 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 7199 if (!i2c)
7200 return NULL;
e7b07cee
HW		 7201 i2c->base.owner = THIS_MODULE;
7202 i2c->base.class = I2C_CLASS_DDC;
7203 i2c->base.dev.parent = &adev->pdev->dev;
7204 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 7205 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 7206 i2c_set_adapdata(&i2c->base, i2c);
7207 i2c->ddc_service = ddc_service;
7208
7209 return i2c;
7210}
7211
89fc8d4e 7212
1f6010a9
DF		 7213/*
7214 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 7215 * dc_link which will be represented by this aconnector.
7216 */
7578ecda
AD		 7217static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7218 struct amdgpu_dm_connector *aconnector,
ae67558b 7219 u32 link_index,
7578ecda 7220 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 7221{
7222 int res = 0;
7223 int connector_type;
7224 struct dc *dc = dm->dc;
7225 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7226 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 7227
7228 link->priv = aconnector;
e7b07cee 7229
f1ad2f5e 7230 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 7231
7232 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 7233 if (!i2c) {
7234 DRM_ERROR("Failed to create i2c adapter data\n");
7235 return -ENOMEM;
7236 }
7237
e7b07cee
HW		 7238 aconnector->i2c = i2c;
7239 res = i2c_add_adapter(&i2c->base);
7240
7241 if (res) {
7242 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7243 goto out_free;
7244 }
7245
7246 connector_type = to_drm_connector_type(link->connector_signal);
7247
17165de2 7248 res = drm_connector_init_with_ddc(
e7b07cee
HW		 7249 dm->ddev,
7250 &aconnector->base,
7251 &amdgpu_dm_connector_funcs,
17165de2
AP		 7252 connector_type,
7253 &i2c->base);
e7b07cee
HW		 7254
7255 if (res) {
7256 DRM_ERROR("connector_init failed\n");
7257 aconnector->connector_id = -1;
7258 goto out_free;
7259 }
7260
7261 drm_connector_helper_add(
7262 &aconnector->base,
7263 &amdgpu_dm_connector_helper_funcs);
7264
7265 amdgpu_dm_connector_init_helper(
7266 dm,
7267 aconnector,
7268 connector_type,
7269 link,
7270 link_index);
7271
cde4c44d 7272 drm_connector_attach_encoder(
e7b07cee
HW		 7273 &aconnector->base, &aencoder->base);
7274
e7b07cee
HW		 7275 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7276 || connector_type == DRM_MODE_CONNECTOR_eDP)
7daec99f 7277 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
e7b07cee 7278
e7b07cee
HW		 7279out_free:
7280 if (res) {
7281 kfree(i2c);
7282 aconnector->i2c = NULL;
7283 }
7284 return res;
7285}
7286
7287int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7288{
7289 switch (adev->mode_info.num_crtc) {
7290 case 1:
7291 return 0x1;
7292 case 2:
7293 return 0x3;
7294 case 3:
7295 return 0x7;
7296 case 4:
7297 return 0xf;
7298 case 5:
7299 return 0x1f;
7300 case 6:
7301 default:
7302 return 0x3f;
7303 }
7304}
7305
7578ecda
AD		 7306static int amdgpu_dm_encoder_init(struct drm_device *dev,
7307 struct amdgpu_encoder *aencoder,
7308 uint32_t link_index)
e7b07cee 7309{
1348969a 7310 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 7311
7312 int res = drm_encoder_init(dev,
7313 &aencoder->base,
7314 &amdgpu_dm_encoder_funcs,
7315 DRM_MODE_ENCODER_TMDS,
7316 NULL);
7317
7318 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7319
7320 if (!res)
7321 aencoder->encoder_id = link_index;
7322 else
7323 aencoder->encoder_id = -1;
7324
7325 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7326
7327 return res;
7328}
7329
3ee6b26b
AD		 7330static void manage_dm_interrupts(struct amdgpu_device *adev,
7331 struct amdgpu_crtc *acrtc,
7332 bool enable)
e7b07cee
HW		 7333{
7334 /*
8fe684e9
NK		 7335 * We have no guarantee that the frontend index maps to the same
7336 * backend index - some even map to more than one.
7337 *
7338 * TODO: Use a different interrupt or check DC itself for the mapping.
e7b07cee
HW		 7339 */
7340 int irq_type =
734dd01d 7341 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 7342 adev,
7343 acrtc->crtc_id);
7344
7345 if (enable) {
7346 drm_crtc_vblank_on(&acrtc->base);
7347 amdgpu_irq_get(
7348 adev,
7349 &adev->pageflip_irq,
7350 irq_type);
86bc2219
WL		 7351#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7352 amdgpu_irq_get(
7353 adev,
7354 &adev->vline0_irq,
7355 irq_type);
7356#endif
e7b07cee 7357 } else {
86bc2219
WL		 7358#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7359 amdgpu_irq_put(
7360 adev,
7361 &adev->vline0_irq,
7362 irq_type);
7363#endif
e7b07cee
HW		 7364 amdgpu_irq_put(
7365 adev,
7366 &adev->pageflip_irq,
7367 irq_type);
7368 drm_crtc_vblank_off(&acrtc->base);
7369 }
7370}
7371
8fe684e9
NK		 7372static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7373 struct amdgpu_crtc *acrtc)
7374{
7375 int irq_type =
7376 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7377
7378 /**
7379 * This reads the current state for the IRQ and force reapplies
7380 * the setting to hardware.
7381 */
7382 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7383}
7384
3ee6b26b
AD		 7385static bool
7386is_scaling_state_different(const struct dm_connector_state *dm_state,
7387 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 7388{
7389 if (dm_state->scaling != old_dm_state->scaling)
7390 return true;
7391 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7392 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7393 return true;
7394 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7395 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7396 return true;
b830ebc9
HW		 7397 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7398 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7399 return true;
e7b07cee
HW		 7400 return false;
7401}
7402
0c8620d6 7403#ifdef CONFIG_DRM_AMD_DC_HDCP
e8fd3eeb 7404static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7405 struct drm_crtc_state *old_crtc_state,
7406 struct drm_connector_state *new_conn_state,
7407 struct drm_connector_state *old_conn_state,
7408 const struct drm_connector *connector,
7409 struct hdcp_workqueue *hdcp_w)
0c8620d6
BL		 7410{
7411 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
97f6c917 7412 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
0c8620d6 7413
e8fd3eeb 7414 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7415 connector->index, connector->status, connector->dpms);
7416 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7417 old_conn_state->content_protection, new_conn_state->content_protection);
7418
7419 if (old_crtc_state)
7420 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7421 old_crtc_state->enable,
7422 old_crtc_state->active,
7423 old_crtc_state->mode_changed,
7424 old_crtc_state->active_changed,
7425 old_crtc_state->connectors_changed);
7426
7427 if (new_crtc_state)
7428 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7429 new_crtc_state->enable,
7430 new_crtc_state->active,
7431 new_crtc_state->mode_changed,
7432 new_crtc_state->active_changed,
7433 new_crtc_state->connectors_changed);
7434
7435 /* hdcp content type change */
7436 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7437 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7438 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7439 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
53e108aa
BL		 7440 return true;
7441 }
7442
e8fd3eeb 7443 /* CP is being re enabled, ignore this */
7444 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7445 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7446 if (new_crtc_state && new_crtc_state->mode_changed) {
7447 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7448 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7449 return true;
0b8f42ab 7450 }
e8fd3eeb 7451 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7452 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
0c8620d6
BL		 7453 return false;
7454 }
7455
31c0ed90
BL		 7456 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7457 *
7458 * Handles: UNDESIRED -> ENABLED
7459 */
e8fd3eeb 7460 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7461 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7462 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
0c8620d6 7463
0d9a947b
QZ		 7464 /* Stream removed and re-enabled
7465 *
7466 * Can sometimes overlap with the HPD case,
7467 * thus set update_hdcp to false to avoid
7468 * setting HDCP multiple times.
7469 *
7470 * Handles: DESIRED -> DESIRED (Special case)
7471 */
e8fd3eeb 7472 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7473 new_conn_state->crtc && new_conn_state->crtc->enabled &&
0d9a947b
QZ		 7474 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7475 dm_con_state->update_hdcp = false;
e8fd3eeb 7476 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7477 __func__);
0d9a947b
QZ		 7478 return true;
7479 }
7480
7481 /* Hot-plug, headless s3, dpms
7482 *
7483 * Only start HDCP if the display is connected/enabled.
7484 * update_hdcp flag will be set to false until the next
7485 * HPD comes in.
31c0ed90
BL		 7486 *
7487 * Handles: DESIRED -> DESIRED (Special case)
0c8620d6 7488 */
e8fd3eeb 7489 if (dm_con_state->update_hdcp &&
7490 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7491 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
97f6c917 7492 dm_con_state->update_hdcp = false;
e8fd3eeb 7493 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7494 __func__);
0c8620d6 7495 return true;
97f6c917 7496 }
0c8620d6 7497
e8fd3eeb 7498 if (old_conn_state->content_protection == new_conn_state->content_protection) {
7499 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7500 if (new_crtc_state && new_crtc_state->mode_changed) {
7501 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7502 __func__);
7503 return true;
0b8f42ab 7504 }
e8fd3eeb 7505 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7506 __func__);
7507 return false;
0b8f42ab 7508 }
e8fd3eeb 7509
7510 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
0c8620d6 7511 return false;
e8fd3eeb 7512 }
0c8620d6 7513
e8fd3eeb 7514 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7515 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7516 __func__);
0c8620d6 7517 return true;
e8fd3eeb 7518 }
0c8620d6 7519
e8fd3eeb 7520 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
0c8620d6
BL		 7521 return false;
7522}
0c8620d6 7523#endif
e8fd3eeb 7524
3ee6b26b
AD		 7525static void remove_stream(struct amdgpu_device *adev,
7526 struct amdgpu_crtc *acrtc,
7527 struct dc_stream_state *stream)
e7b07cee
HW		 7528{
7529 /* this is the update mode case */
e7b07cee
HW		 7530
7531 acrtc->otg_inst = -1;
7532 acrtc->enabled = false;
7533}
7534
e7b07cee
HW		 7535static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7536{
7537
7538 assert_spin_locked(&acrtc->base.dev->event_lock);
7539 WARN_ON(acrtc->event);
7540
7541 acrtc->event = acrtc->base.state->event;
7542
7543 /* Set the flip status */
7544 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7545
7546 /* Mark this event as consumed */
7547 acrtc->base.state->event = NULL;
7548
cb2318b7
VL		 7549 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7550 acrtc->crtc_id);
e7b07cee
HW		 7551}
7552
bb47de73
NK		 7553static void update_freesync_state_on_stream(
7554 struct amdgpu_display_manager *dm,
7555 struct dm_crtc_state *new_crtc_state,
180db303
NK		 7556 struct dc_stream_state *new_stream,
7557 struct dc_plane_state *surface,
7558 u32 flip_timestamp_in_us)
bb47de73 7559{
09aef2c4 7560 struct mod_vrr_params vrr_params;
bb47de73 7561 struct dc_info_packet vrr_infopacket = {0};
09aef2c4 7562 struct amdgpu_device *adev = dm->adev;
585d450c 7563 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
09aef2c4 7564 unsigned long flags;
4cda3243 7565 bool pack_sdp_v1_3 = false;
bb47de73
NK		 7566
7567 if (!new_stream)
7568 return;
7569
7570 /*
7571 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7572 * For now it's sufficient to just guard against these conditions.
7573 */
7574
7575 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7576 return;
7577
4a580877 7578 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
585d450c 7579 vrr_params = acrtc->dm_irq_params.vrr_params;
09aef2c4 7580
180db303
NK		 7581 if (surface) {
7582 mod_freesync_handle_preflip(
7583 dm->freesync_module,
7584 surface,
7585 new_stream,
7586 flip_timestamp_in_us,
7587 &vrr_params);
09aef2c4
MK		 7588
7589 if (adev->family < AMDGPU_FAMILY_AI &&
7590 amdgpu_dm_vrr_active(new_crtc_state)) {
7591 mod_freesync_handle_v_update(dm->freesync_module,
7592 new_stream, &vrr_params);
e63e2491
EB		 7593
7594 /* Need to call this before the frame ends. */
7595 dc_stream_adjust_vmin_vmax(dm->dc,
7596 new_crtc_state->stream,
7597 &vrr_params.adjust);
09aef2c4 7598 }
180db303 7599 }
bb47de73
NK		 7600
7601 mod_freesync_build_vrr_infopacket(
7602 dm->freesync_module,
7603 new_stream,
180db303 7604 &vrr_params,
ecd0136b
HT		 7605 PACKET_TYPE_VRR,
7606 TRANSFER_FUNC_UNKNOWN,
4cda3243
MT		 7607 &vrr_infopacket,
7608 pack_sdp_v1_3);
bb47de73 7609
8a48b44c 7610 new_crtc_state->freesync_vrr_info_changed |=
bb47de73
NK		 7611 (memcmp(&new_crtc_state->vrr_infopacket,
7612 &vrr_infopacket,
7613 sizeof(vrr_infopacket)) != 0);
7614
585d450c 7615 acrtc->dm_irq_params.vrr_params = vrr_params;
bb47de73
NK		 7616 new_crtc_state->vrr_infopacket = vrr_infopacket;
7617
bb47de73
NK		 7618 new_stream->vrr_infopacket = vrr_infopacket;
7619
7620 if (new_crtc_state->freesync_vrr_info_changed)
7621 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7622 new_crtc_state->base.crtc->base.id,
7623 (int)new_crtc_state->base.vrr_enabled,
180db303 7624 (int)vrr_params.state);
09aef2c4 7625
4a580877 7626 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
bb47de73
NK		 7627}
7628
585d450c 7629static void update_stream_irq_parameters(
e854194c
MK		 7630 struct amdgpu_display_manager *dm,
7631 struct dm_crtc_state *new_crtc_state)
7632{
7633 struct dc_stream_state *new_stream = new_crtc_state->stream;
09aef2c4 7634 struct mod_vrr_params vrr_params;
e854194c 7635 struct mod_freesync_config config = new_crtc_state->freesync_config;
09aef2c4 7636 struct amdgpu_device *adev = dm->adev;
585d450c 7637 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
09aef2c4 7638 unsigned long flags;
e854194c
MK		 7639
7640 if (!new_stream)
7641 return;
7642
7643 /*
7644 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7645 * For now it's sufficient to just guard against these conditions.
7646 */
7647 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7648 return;
7649
4a580877 7650 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
585d450c 7651 vrr_params = acrtc->dm_irq_params.vrr_params;
09aef2c4 7652
e854194c
MK		 7653 if (new_crtc_state->vrr_supported &&
7654 config.min_refresh_in_uhz &&
7655 config.max_refresh_in_uhz) {
a85ba005
NC		 7656 /*
7657 * if freesync compatible mode was set, config.state will be set
7658 * in atomic check
7659 */
7660 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7661 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7662 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7663 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7664 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7665 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7666 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7667 } else {
7668 config.state = new_crtc_state->base.vrr_enabled ?
7669 VRR_STATE_ACTIVE_VARIABLE :
7670 VRR_STATE_INACTIVE;
7671 }
e854194c
MK		 7672 } else {
7673 config.state = VRR_STATE_UNSUPPORTED;
7674 }
7675
7676 mod_freesync_build_vrr_params(dm->freesync_module,
7677 new_stream,
7678 &config, &vrr_params);
7679
585d450c
AP		 7680 new_crtc_state->freesync_config = config;
7681 /* Copy state for access from DM IRQ handler */
7682 acrtc->dm_irq_params.freesync_config = config;
7683 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7684 acrtc->dm_irq_params.vrr_params = vrr_params;
4a580877 7685 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
e854194c
MK		 7686}
7687
66b0c973
MK		 7688static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7689 struct dm_crtc_state *new_state)
7690{
7691 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
7692 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
7693
7694 if (!old_vrr_active && new_vrr_active) {
7695 /* Transition VRR inactive -> active:
7696 * While VRR is active, we must not disable vblank irq, as a
7697 * reenable after disable would compute bogus vblank/pflip
7698 * timestamps if it likely happened inside display front-porch.
d2574c33
MK		 7699 *
7700 * We also need vupdate irq for the actual core vblank handling
7701 * at end of vblank.
66b0c973 7702 */
8799c0be
YL		 7703 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0);
7704 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
66b0c973
MK		 7705 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7706 __func__, new_state->base.crtc->base.id);
7707 } else if (old_vrr_active && !new_vrr_active) {
7708 /* Transition VRR active -> inactive:
7709 * Allow vblank irq disable again for fixed refresh rate.
7710 */
8799c0be 7711 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0);
66b0c973
MK		 7712 drm_crtc_vblank_put(new_state->base.crtc);
7713 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7714 __func__, new_state->base.crtc->base.id);
7715 }
7716}
7717
8ad27806
NK		 7718static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7719{
7720 struct drm_plane *plane;
5760dcb9 7721 struct drm_plane_state *old_plane_state;
8ad27806
NK		 7722 int i;
7723
7724 /*
7725 * TODO: Make this per-stream so we don't issue redundant updates for
7726 * commits with multiple streams.
7727 */
5760dcb9 7728 for_each_old_plane_in_state(state, plane, old_plane_state, i)
8ad27806
NK		 7729 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7730 handle_cursor_update(plane, old_plane_state);
7731}
7732
3be5262e 7733static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 7734 struct dc_state *dc_state,
3ee6b26b
AD		 7735 struct drm_device *dev,
7736 struct amdgpu_display_manager *dm,
7737 struct drm_crtc *pcrtc,
420cd472 7738 bool wait_for_vblank)
e7b07cee 7739{
ae67558b
SS		 7740 u32 i;
7741 u64 timestamp_ns;
e7b07cee 7742 struct drm_plane *plane;
0bc9706d 7743 struct drm_plane_state *old_plane_state, *new_plane_state;
e7b07cee 7744 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 7745 struct drm_crtc_state *new_pcrtc_state =
7746 drm_atomic_get_new_crtc_state(state, pcrtc);
7747 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 7748 struct dm_crtc_state *dm_old_crtc_state =
7749 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
74aa7bd4 7750 int planes_count = 0, vpos, hpos;
e7b07cee 7751 unsigned long flags;
ae67558b 7752 u32 target_vblank, last_flip_vblank;
fdd1fe57 7753 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
cc79950b 7754 bool cursor_update = false;
74aa7bd4 7755 bool pflip_present = false;
bc7f670e
DF		 7756 struct {
7757 struct dc_surface_update surface_updates[MAX_SURFACES];
7758 struct dc_plane_info plane_infos[MAX_SURFACES];
7759 struct dc_scaling_info scaling_infos[MAX_SURFACES];
74aa7bd4 7760 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
bc7f670e 7761 struct dc_stream_update stream_update;
74aa7bd4 7762 } *bundle;
bc7f670e 7763
74aa7bd4 7764 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8a48b44c 7765
74aa7bd4
DF		 7766 if (!bundle) {
7767 dm_error("Failed to allocate update bundle\n");
4b510503
NK		 7768 goto cleanup;
7769 }
e7b07cee 7770
8ad27806
NK		 7771 /*
7772 * Disable the cursor first if we're disabling all the planes.
7773 * It'll remain on the screen after the planes are re-enabled
7774 * if we don't.
7775 */
7776 if (acrtc_state->active_planes == 0)
7777 amdgpu_dm_commit_cursors(state);
7778
e7b07cee 7779 /* update planes when needed */
efc8278e 7780 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
0bc9706d 7781 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 7782 struct drm_crtc_state *new_crtc_state;
0bc9706d 7783 struct drm_framebuffer *fb = new_plane_state->fb;
6eed95b0 7784 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
34bafd27 7785 bool plane_needs_flip;
c7af5f77 7786 struct dc_plane_state *dc_plane;
54d76575 7787 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee 7788
80c218d5 7789 /* Cursor plane is handled after stream updates */
cc79950b
MD		 7790 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7791 if ((fb && crtc == pcrtc) ||
7792 (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7793 cursor_update = true;
7794
e7b07cee 7795 continue;
cc79950b 7796 }
e7b07cee 7797
f5ba60fe
DD		 7798 if (!fb || !crtc || pcrtc != crtc)
7799 continue;
7800
7801 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7802 if (!new_crtc_state->active)
e7b07cee
HW		 7803 continue;
7804
bc7f670e 7805 dc_plane = dm_new_plane_state->dc_state;
e7b07cee 7806
74aa7bd4 7807 bundle->surface_updates[planes_count].surface = dc_plane;
bc7f670e 7808 if (new_pcrtc_state->color_mgmt_changed) {
74aa7bd4
DF		 7809 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7810 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
44efb784 7811 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
bc7f670e 7812 }
8a48b44c 7813
4375d625 7814 fill_dc_scaling_info(dm->adev, new_plane_state,
695af5f9 7815 &bundle->scaling_infos[planes_count]);
8a48b44c 7816
695af5f9
NK		 7817 bundle->surface_updates[planes_count].scaling_info =
7818 &bundle->scaling_infos[planes_count];
8a48b44c 7819
f5031000 7820 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8a48b44c 7821
f5031000 7822 pflip_present = pflip_present || plane_needs_flip;
8a48b44c 7823
f5031000
DF		 7824 if (!plane_needs_flip) {
7825 planes_count += 1;
7826 continue;
7827 }
8a48b44c 7828
695af5f9 7829 fill_dc_plane_info_and_addr(
8ce5d842 7830 dm->adev, new_plane_state,
6eed95b0 7831 afb->tiling_flags,
695af5f9 7832 &bundle->plane_infos[planes_count],
87b7ebc2 7833 &bundle->flip_addrs[planes_count].address,
6eed95b0 7834 afb->tmz_surface, false);
87b7ebc2 7835
9f07550b 7836 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
87b7ebc2
RS		 7837 new_plane_state->plane->index,
7838 bundle->plane_infos[planes_count].dcc.enable);
695af5f9
NK		 7839
7840 bundle->surface_updates[planes_count].plane_info =
7841 &bundle->plane_infos[planes_count];
8a48b44c 7842
d852871c
HM		 7843 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled)
7844 fill_dc_dirty_rects(plane, old_plane_state,
7845 new_plane_state, new_crtc_state,
7846 &bundle->flip_addrs[planes_count]);
7cc191ee 7847
caff0e66
NK		 7848 /*
7849 * Only allow immediate flips for fast updates that don't
7850 * change FB pitch, DCC state, rotation or mirroing.
7851 */
f5031000 7852 bundle->flip_addrs[planes_count].flip_immediate =
4d85f45c 7853 crtc->state->async_flip &&
caff0e66 7854 acrtc_state->update_type == UPDATE_TYPE_FAST;
8a48b44c 7855
f5031000
DF		 7856 timestamp_ns = ktime_get_ns();
7857 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
7858 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
7859 bundle->surface_updates[planes_count].surface = dc_plane;
8a48b44c 7860
f5031000
DF		 7861 if (!bundle->surface_updates[planes_count].surface) {
7862 DRM_ERROR("No surface for CRTC: id=%d\n",
7863 acrtc_attach->crtc_id);
7864 continue;
bc7f670e
DF		 7865 }
7866
f5031000
DF		 7867 if (plane == pcrtc->primary)
7868 update_freesync_state_on_stream(
7869 dm,
7870 acrtc_state,
7871 acrtc_state->stream,
7872 dc_plane,
7873 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
bc7f670e 7874
9f07550b 7875 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
f5031000
DF		 7876 __func__,
7877 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
7878 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
bc7f670e
DF		 7879
7880 planes_count += 1;
7881
8a48b44c
DF		 7882 }
7883
74aa7bd4 7884 if (pflip_present) {
634092b1
MK		 7885 if (!vrr_active) {
7886 /* Use old throttling in non-vrr fixed refresh rate mode
7887 * to keep flip scheduling based on target vblank counts
7888 * working in a backwards compatible way, e.g., for
7889 * clients using the GLX_OML_sync_control extension or
7890 * DRI3/Present extension with defined target_msc.
7891 */
e3eff4b5 7892 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
634092b1
MK		 7893 }
7894 else {
7895 /* For variable refresh rate mode only:
7896 * Get vblank of last completed flip to avoid > 1 vrr
7897 * flips per video frame by use of throttling, but allow
7898 * flip programming anywhere in the possibly large
7899 * variable vrr vblank interval for fine-grained flip
7900 * timing control and more opportunity to avoid stutter
7901 * on late submission of flips.
7902 */
7903 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5d1c59c4 7904 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
634092b1
MK		 7905 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7906 }
7907
fdd1fe57 7908 target_vblank = last_flip_vblank + wait_for_vblank;
8a48b44c
DF		 7909
7910 /*
7911 * Wait until we're out of the vertical blank period before the one
7912 * targeted by the flip
7913 */
7914 while ((acrtc_attach->enabled &&
7915 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
7916 0, &vpos, &hpos, NULL,
7917 NULL, &pcrtc->hwmode)
7918 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
7919 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
7920 (int)(target_vblank -
e3eff4b5 7921 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8a48b44c
DF		 7922 usleep_range(1000, 1100);
7923 }
7924
8fe684e9
NK		 7925 /**
7926 * Prepare the flip event for the pageflip interrupt to handle.
7927 *
7928 * This only works in the case where we've already turned on the
7929 * appropriate hardware blocks (eg. HUBP) so in the transition case
7930 * from 0 -> n planes we have to skip a hardware generated event
7931 * and rely on sending it from software.
7932 */
7933 if (acrtc_attach->base.state->event &&
10a36226 7934 acrtc_state->active_planes > 0) {
8a48b44c
DF		 7935 drm_crtc_vblank_get(pcrtc);
7936
7937 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7938
7939 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
7940 prepare_flip_isr(acrtc_attach);
7941
7942 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7943 }
7944
7945 if (acrtc_state->stream) {
8a48b44c 7946 if (acrtc_state->freesync_vrr_info_changed)
74aa7bd4 7947 bundle->stream_update.vrr_infopacket =
8a48b44c 7948 &acrtc_state->stream->vrr_infopacket;
e7b07cee 7949 }
cc79950b
MD		 7950 } else if (cursor_update && acrtc_state->active_planes > 0 &&
7951 acrtc_attach->base.state->event) {
7952 drm_crtc_vblank_get(pcrtc);
7953
7954 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7955
7956 acrtc_attach->event = acrtc_attach->base.state->event;
7957 acrtc_attach->base.state->event = NULL;
7958
7959 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
e7b07cee
HW		 7960 }
7961
bc92c065 7962 /* Update the planes if changed or disable if we don't have any. */
ed9656fb
ES		 7963 if ((planes_count || acrtc_state->active_planes == 0) &&
7964 acrtc_state->stream) {
58aa1c50
NK		 7965 /*
7966 * If PSR or idle optimizations are enabled then flush out
7967 * any pending work before hardware programming.
7968 */
06dd1888
NK		 7969 if (dm->vblank_control_workqueue)
7970 flush_workqueue(dm->vblank_control_workqueue);
58aa1c50 7971
b6e881c9 7972 bundle->stream_update.stream = acrtc_state->stream;
bc7f670e 7973 if (new_pcrtc_state->mode_changed) {
74aa7bd4
DF		 7974 bundle->stream_update.src = acrtc_state->stream->src;
7975 bundle->stream_update.dst = acrtc_state->stream->dst;
e7b07cee
HW		 7976 }
7977
cf020d49
NK		 7978 if (new_pcrtc_state->color_mgmt_changed) {
7979 /*
7980 * TODO: This isn't fully correct since we've actually
7981 * already modified the stream in place.
7982 */
7983 bundle->stream_update.gamut_remap =
7984 &acrtc_state->stream->gamut_remap_matrix;
7985 bundle->stream_update.output_csc_transform =
7986 &acrtc_state->stream->csc_color_matrix;
7987 bundle->stream_update.out_transfer_func =
7988 acrtc_state->stream->out_transfer_func;
7989 }
bc7f670e 7990
8a48b44c 7991 acrtc_state->stream->abm_level = acrtc_state->abm_level;
bc7f670e 7992 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
74aa7bd4 7993 bundle->stream_update.abm_level = &acrtc_state->abm_level;
44d09c6a 7994
e63e2491
EB		 7995 /*
7996 * If FreeSync state on the stream has changed then we need to
7997 * re-adjust the min/max bounds now that DC doesn't handle this
7998 * as part of commit.
7999 */
a85ba005 8000 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
e63e2491
EB		 8001 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8002 dc_stream_adjust_vmin_vmax(
8003 dm->dc, acrtc_state->stream,
585d450c 8004 &acrtc_attach->dm_irq_params.vrr_params.adjust);
e63e2491
EB		 8005 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8006 }
bc7f670e 8007 mutex_lock(&dm->dc_lock);
8c322309 8008 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
d1ebfdd8 8009 acrtc_state->stream->link->psr_settings.psr_allow_active)
8c322309
RL		 8010 amdgpu_dm_psr_disable(acrtc_state->stream);
8011
bc7f670e 8012 dc_commit_updates_for_stream(dm->dc,
74aa7bd4 8013 bundle->surface_updates,
bc7f670e
DF		 8014 planes_count,
8015 acrtc_state->stream,
efc8278e
AJ		 8016 &bundle->stream_update,
8017 dc_state);
8c322309 8018
8fe684e9
NK		 8019 /**
8020 * Enable or disable the interrupts on the backend.
8021 *
8022 * Most pipes are put into power gating when unused.
8023 *
8024 * When power gating is enabled on a pipe we lose the
8025 * interrupt enablement state when power gating is disabled.
8026 *
8027 * So we need to update the IRQ control state in hardware
8028 * whenever the pipe turns on (since it could be previously
8029 * power gated) or off (since some pipes can't be power gated
8030 * on some ASICs).
8031 */
8032 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
1348969a
LT		 8033 dm_update_pflip_irq_state(drm_to_adev(dev),
8034 acrtc_attach);
8fe684e9 8035
8c322309 8036 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
1cfbbdde 8037 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
d1ebfdd8 8038 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8c322309 8039 amdgpu_dm_link_setup_psr(acrtc_state->stream);
58aa1c50
NK		 8040
8041 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8042 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8043 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8044 struct amdgpu_dm_connector *aconn =
8045 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
1a365683
RL		 8046
8047 if (aconn->psr_skip_count > 0)
8048 aconn->psr_skip_count--;
58aa1c50
NK		 8049
8050 /* Allow PSR when skip count is 0. */
8051 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
7cc191ee
LL		 8052
8053 /*
8054 * If sink supports PSR SU, there is no need to rely on
8055 * a vblank event disable request to enable PSR. PSR SU
8056 * can be enabled immediately once OS demonstrates an
8057 * adequate number of fast atomic commits to notify KMD
8058 * of update events. See `vblank_control_worker()`.
8059 */
8060 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8061 acrtc_attach->dm_irq_params.allow_psr_entry &&
c0459bdd
AL		 8062#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8063 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8064#endif
7cc191ee
LL		 8065 !acrtc_state->stream->link->psr_settings.psr_allow_active)
8066 amdgpu_dm_psr_enable(acrtc_state->stream);
58aa1c50
NK		 8067 } else {
8068 acrtc_attach->dm_irq_params.allow_psr_entry = false;
8c322309
RL		 8069 }
8070
bc7f670e 8071 mutex_unlock(&dm->dc_lock);
e7b07cee 8072 }
4b510503 8073
8ad27806
NK		 8074 /*
8075 * Update cursor state *after* programming all the planes.
8076 * This avoids redundant programming in the case where we're going
8077 * to be disabling a single plane - those pipes are being disabled.
8078 */
8079 if (acrtc_state->active_planes)
8080 amdgpu_dm_commit_cursors(state);
80c218d5 8081
4b510503 8082cleanup:
74aa7bd4 8083 kfree(bundle);
e7b07cee
HW		 8084}
8085
6ce8f316
NK		 8086static void amdgpu_dm_commit_audio(struct drm_device *dev,
8087 struct drm_atomic_state *state)
8088{
1348969a 8089 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 8090 struct amdgpu_dm_connector *aconnector;
8091 struct drm_connector *connector;
8092 struct drm_connector_state *old_con_state, *new_con_state;
8093 struct drm_crtc_state *new_crtc_state;
8094 struct dm_crtc_state *new_dm_crtc_state;
8095 const struct dc_stream_status *status;
8096 int i, inst;
8097
8098 /* Notify device removals. */
8099 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8100 if (old_con_state->crtc != new_con_state->crtc) {
8101 /* CRTC changes require notification. */
8102 goto notify;
8103 }
8104
8105 if (!new_con_state->crtc)
8106 continue;
8107
8108 new_crtc_state = drm_atomic_get_new_crtc_state(
8109 state, new_con_state->crtc);
8110
8111 if (!new_crtc_state)
8112 continue;
8113
8114 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8115 continue;
8116
8117 notify:
8118 aconnector = to_amdgpu_dm_connector(connector);
8119
8120 mutex_lock(&adev->dm.audio_lock);
8121 inst = aconnector->audio_inst;
8122 aconnector->audio_inst = -1;
8123 mutex_unlock(&adev->dm.audio_lock);
8124
8125 amdgpu_dm_audio_eld_notify(adev, inst);
8126 }
8127
8128 /* Notify audio device additions. */
8129 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8130 if (!new_con_state->crtc)
8131 continue;
8132
8133 new_crtc_state = drm_atomic_get_new_crtc_state(
8134 state, new_con_state->crtc);
8135
8136 if (!new_crtc_state)
8137 continue;
8138
8139 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8140 continue;
8141
8142 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8143 if (!new_dm_crtc_state->stream)
8144 continue;
8145
8146 status = dc_stream_get_status(new_dm_crtc_state->stream);
8147 if (!status)
8148 continue;
8149
8150 aconnector = to_amdgpu_dm_connector(connector);
8151
8152 mutex_lock(&adev->dm.audio_lock);
8153 inst = status->audio_inst;
8154 aconnector->audio_inst = inst;
8155 mutex_unlock(&adev->dm.audio_lock);
8156
8157 amdgpu_dm_audio_eld_notify(adev, inst);
8158 }
8159}
8160
1f6010a9 8161/*
27b3f4fc
LSL		 8162 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8163 * @crtc_state: the DRM CRTC state
8164 * @stream_state: the DC stream state.
8165 *
8166 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8167 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8168 */
8169static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8170 struct dc_stream_state *stream_state)
8171{
b9952f93 8172 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
27b3f4fc 8173}
e7b07cee 8174
b8592b48
LL		 8175/**
8176 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8177 * @state: The atomic state to commit
8178 *
8179 * This will tell DC to commit the constructed DC state from atomic_check,
8180 * programming the hardware. Any failures here implies a hardware failure, since
8181 * atomic check should have filtered anything non-kosher.
8182 */
7578ecda 8183static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 8184{
8185 struct drm_device *dev = state->dev;
1348969a 8186 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 8187 struct amdgpu_display_manager *dm = &adev->dm;
8188 struct dm_atomic_state *dm_state;
eb3dc897 8189 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
ae67558b 8190 u32 i, j;
5cc6dcbd 8191 struct drm_crtc *crtc;
0bc9706d 8192 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 8193 unsigned long flags;
8194 bool wait_for_vblank = true;
8195 struct drm_connector *connector;
c2cea706 8196 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 8197 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 8198 int crtc_disable_count = 0;
6ee90e88 8199 bool mode_set_reset_required = false;
047de3f1 8200 int r;
e7b07cee 8201
e8a98235
RS		 8202 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8203
047de3f1
CK		 8204 r = drm_atomic_helper_wait_for_fences(dev, state, false);
8205 if (unlikely(r))
8206 DRM_ERROR("Waiting for fences timed out!");
8207
e7b07cee 8208 drm_atomic_helper_update_legacy_modeset_state(dev, state);
a5c2c0d1 8209 drm_dp_mst_atomic_wait_for_dependencies(state);
e7b07cee 8210
eb3dc897
NK		 8211 dm_state = dm_atomic_get_new_state(state);
8212 if (dm_state && dm_state->context) {
8213 dc_state = dm_state->context;
8214 } else {
8215 /* No state changes, retain current state. */
813d20dc 8216 dc_state_temp = dc_create_state(dm->dc);
eb3dc897
NK		 8217 ASSERT(dc_state_temp);
8218 dc_state = dc_state_temp;
8219 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8220 }
e7b07cee 8221
6d90a208
AP		 8222 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8223 new_crtc_state, i) {
8224 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8225
8226 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8227
8228 if (old_crtc_state->active &&
8229 (!new_crtc_state->active ||
8230 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8231 manage_dm_interrupts(adev, acrtc, false);
8232 dc_stream_release(dm_old_crtc_state->stream);
8233 }
8234 }
8235
8976f73b
RS		 8236 drm_atomic_helper_calc_timestamping_constants(state);
8237
e7b07cee 8238 /* update changed items */
0bc9706d 8239 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 8240 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 8241
54d76575
LSL		 8242 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8243 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 8244
9f07550b 8245 drm_dbg_state(state->dev,
e7b07cee
HW		 8246 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8247 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8248 "connectors_changed:%d\n",
8249 acrtc->crtc_id,
0bc9706d
LSL		 8250 new_crtc_state->enable,
8251 new_crtc_state->active,
8252 new_crtc_state->planes_changed,
8253 new_crtc_state->mode_changed,
8254 new_crtc_state->active_changed,
8255 new_crtc_state->connectors_changed);
e7b07cee 8256
5c68c652
VL		 8257 /* Disable cursor if disabling crtc */
8258 if (old_crtc_state->active && !new_crtc_state->active) {
8259 struct dc_cursor_position position;
8260
8261 memset(&position, 0, sizeof(position));
8262 mutex_lock(&dm->dc_lock);
8263 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8264 mutex_unlock(&dm->dc_lock);
8265 }
8266
27b3f4fc
LSL		 8267 /* Copy all transient state flags into dc state */
8268 if (dm_new_crtc_state->stream) {
8269 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8270 dm_new_crtc_state->stream);
8271 }
8272
e7b07cee
HW		 8273 /* handles headless hotplug case, updating new_state and
8274 * aconnector as needed
8275 */
8276
54d76575 8277 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 8278
4711c033 8279 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 8280
54d76575 8281 if (!dm_new_crtc_state->stream) {
e7b07cee 8282 /*
b830ebc9
HW		 8283 * this could happen because of issues with
8284 * userspace notifications delivery.
8285 * In this case userspace tries to set mode on
1f6010a9
DF		 8286 * display which is disconnected in fact.
8287 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 8288 * We expect reset mode will come soon.
8289 *
8290 * This can also happen when unplug is done
8291 * during resume sequence ended
8292 *
8293 * In this case, we want to pretend we still
8294 * have a sink to keep the pipe running so that
8295 * hw state is consistent with the sw state
8296 */
f1ad2f5e 8297 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 8298 __func__, acrtc->base.base.id);
8299 continue;
8300 }
8301
54d76575
LSL		 8302 if (dm_old_crtc_state->stream)
8303 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 8304
97028037
LP		 8305 pm_runtime_get_noresume(dev->dev);
8306
e7b07cee 8307 acrtc->enabled = true;
0bc9706d
LSL		 8308 acrtc->hw_mode = new_crtc_state->mode;
8309 crtc->hwmode = new_crtc_state->mode;
6ee90e88 8310 mode_set_reset_required = true;
0bc9706d 8311 } else if (modereset_required(new_crtc_state)) {
4711c033 8312 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 8313 /* i.e. reset mode */
6ee90e88 8314 if (dm_old_crtc_state->stream)
54d76575 8315 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
a85ba005 8316
6ee90e88 8317 mode_set_reset_required = true;
e7b07cee
HW		 8318 }
8319 } /* for_each_crtc_in_state() */
8320
eb3dc897 8321 if (dc_state) {
6ee90e88 8322 /* if there mode set or reset, disable eDP PSR */
58aa1c50 8323 if (mode_set_reset_required) {
06dd1888
NK		 8324 if (dm->vblank_control_workqueue)
8325 flush_workqueue(dm->vblank_control_workqueue);
cae5c1ab 8326
6ee90e88 8327 amdgpu_dm_psr_disable_all(dm);
58aa1c50 8328 }
6ee90e88 8329
eb3dc897 8330 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 8331 mutex_lock(&dm->dc_lock);
eb3dc897 8332 WARN_ON(!dc_commit_state(dm->dc, dc_state));
f3106c94
JC		 8333
8334 /* Allow idle optimization when vblank count is 0 for display off */
8335 if (dm->active_vblank_irq_count == 0)
8336 dc_allow_idle_optimizations(dm->dc, true);
674e78ac 8337 mutex_unlock(&dm->dc_lock);
fa2123db 8338 }
fe8858bb 8339
0bc9706d 8340 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 8341 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 8342
54d76575 8343 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 8344
54d76575 8345 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 8346 const struct dc_stream_status *status =
54d76575 8347 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 8348
eb3dc897 8349 if (!status)
09f609c3
LL		 8350 status = dc_stream_get_status_from_state(dc_state,
8351 dm_new_crtc_state->stream);
e7b07cee 8352 if (!status)
54d76575 8353 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 8354 else
8355 acrtc->otg_inst = status->primary_otg_inst;
8356 }
8357 }
0c8620d6
BL		 8358#ifdef CONFIG_DRM_AMD_DC_HDCP
8359 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8360 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8361 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8362 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8363
e8fd3eeb 8364 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8365
8366 if (!connector)
8367 continue;
8368
8369 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8370 connector->index, connector->status, connector->dpms);
8371 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8372 old_con_state->content_protection, new_con_state->content_protection);
8373
8374 if (aconnector->dc_sink) {
8375 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8376 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8377 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8378 aconnector->dc_sink->edid_caps.display_name);
8379 }
8380 }
8381
0c8620d6 8382 new_crtc_state = NULL;
e8fd3eeb 8383 old_crtc_state = NULL;
0c8620d6 8384
e8fd3eeb 8385 if (acrtc) {
0c8620d6 8386 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
e8fd3eeb 8387 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8388 }
8389
8390 if (old_crtc_state)
8391 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8392 old_crtc_state->enable,
8393 old_crtc_state->active,
8394 old_crtc_state->mode_changed,
8395 old_crtc_state->active_changed,
8396 old_crtc_state->connectors_changed);
8397
8398 if (new_crtc_state)
8399 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8400 new_crtc_state->enable,
8401 new_crtc_state->active,
8402 new_crtc_state->mode_changed,
8403 new_crtc_state->active_changed,
8404 new_crtc_state->connectors_changed);
8405 }
8406
8407 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8408 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8409 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8410 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8411
8412 new_crtc_state = NULL;
8413 old_crtc_state = NULL;
8414
8415 if (acrtc) {
8416 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8417 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8418 }
0c8620d6
BL		 8419
8420 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8421
8422 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8423 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8424 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8425 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
97f6c917 8426 dm_new_con_state->update_hdcp = true;
0c8620d6
BL		 8427 continue;
8428 }
8429
e8fd3eeb 8430 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8431 old_con_state, connector, adev->dm.hdcp_workqueue)) {
82986fd6 8432 /* when display is unplugged from mst hub, connctor will
8433 * be destroyed within dm_dp_mst_connector_destroy. connector
8434 * hdcp perperties, like type, undesired, desired, enabled,
8435 * will be lost. So, save hdcp properties into hdcp_work within
8436 * amdgpu_dm_atomic_commit_tail. if the same display is
8437 * plugged back with same display index, its hdcp properties
8438 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8439 */
8440
e8fd3eeb 8441 bool enable_encryption = false;
8442
8443 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8444 enable_encryption = true;
8445
82986fd6 8446 if (aconnector->dc_link && aconnector->dc_sink &&
8447 aconnector->dc_link->type == dc_connection_mst_branch) {
8448 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8449 struct hdcp_workqueue *hdcp_w =
8450 &hdcp_work[aconnector->dc_link->link_index];
8451
8452 hdcp_w->hdcp_content_type[connector->index] =
8453 new_con_state->hdcp_content_type;
8454 hdcp_w->content_protection[connector->index] =
8455 new_con_state->content_protection;
8456 }
8457
e8fd3eeb 8458 if (new_crtc_state && new_crtc_state->mode_changed &&
8459 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8460 enable_encryption = true;
8461
8462 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8463
b1abe558
BL		 8464 hdcp_update_display(
8465 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
e8fd3eeb 8466 new_con_state->hdcp_content_type, enable_encryption);
8467 }
0c8620d6
BL		 8468 }
8469#endif
e7b07cee 8470
02d6a6fc 8471 /* Handle connector state changes */
c2cea706 8472 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 8473 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8474 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8475 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
efc8278e 8476 struct dc_surface_update dummy_updates[MAX_SURFACES];
19afd799 8477 struct dc_stream_update stream_update;
b232d4ed 8478 struct dc_info_packet hdr_packet;
e7b07cee 8479 struct dc_stream_status *status = NULL;
b232d4ed 8480 bool abm_changed, hdr_changed, scaling_changed;
e7b07cee 8481
efc8278e 8482 memset(&dummy_updates, 0, sizeof(dummy_updates));
19afd799
NC		 8483 memset(&stream_update, 0, sizeof(stream_update));
8484
44d09c6a 8485 if (acrtc) {
0bc9706d 8486 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 8487 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8488 }
0bc9706d 8489
e7b07cee 8490 /* Skip any modesets/resets */
0bc9706d 8491 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 8492 continue;
8493
54d76575 8494 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 8495 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8496
b232d4ed
NK		 8497 scaling_changed = is_scaling_state_different(dm_new_con_state,
8498 dm_old_con_state);
8499
8500 abm_changed = dm_new_crtc_state->abm_level !=
8501 dm_old_crtc_state->abm_level;
8502
8503 hdr_changed =
72921cdf 8504 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
b232d4ed
NK		 8505
8506 if (!scaling_changed && !abm_changed && !hdr_changed)
c1ee92f9 8507 continue;
e7b07cee 8508
b6e881c9 8509 stream_update.stream = dm_new_crtc_state->stream;
b232d4ed 8510 if (scaling_changed) {
02d6a6fc 8511 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
b6e881c9 8512 dm_new_con_state, dm_new_crtc_state->stream);
e7b07cee 8513
02d6a6fc
DF		 8514 stream_update.src = dm_new_crtc_state->stream->src;
8515 stream_update.dst = dm_new_crtc_state->stream->dst;
8516 }
8517
b232d4ed 8518 if (abm_changed) {
02d6a6fc
DF		 8519 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8520
8521 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8522 }
70e8ffc5 8523
b232d4ed
NK		 8524 if (hdr_changed) {
8525 fill_hdr_info_packet(new_con_state, &hdr_packet);
8526 stream_update.hdr_static_metadata = &hdr_packet;
8527 }
8528
54d76575 8529 status = dc_stream_get_status(dm_new_crtc_state->stream);
57738ae4
ND		 8530
8531 if (WARN_ON(!status))
8532 continue;
8533
3be5262e 8534 WARN_ON(!status->plane_count);
e7b07cee 8535
02d6a6fc
DF		 8536 /*
8537 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8538 * Here we create an empty update on each plane.
8539 * To fix this, DC should permit updating only stream properties.
8540 */
8541 for (j = 0; j < status->plane_count; j++)
efc8278e 8542 dummy_updates[j].surface = status->plane_states[0];
02d6a6fc
DF		 8543
8544
8545 mutex_lock(&dm->dc_lock);
8546 dc_commit_updates_for_stream(dm->dc,
efc8278e 8547 dummy_updates,
02d6a6fc
DF		 8548 status->plane_count,
8549 dm_new_crtc_state->stream,
efc8278e
AJ		 8550 &stream_update,
8551 dc_state);
02d6a6fc 8552 mutex_unlock(&dm->dc_lock);
e7b07cee
HW		 8553 }
8554
8fe684e9
NK		 8555 /**
8556 * Enable interrupts for CRTCs that are newly enabled or went through
8557 * a modeset. It was intentionally deferred until after the front end
8558 * state was modified to wait until the OTG was on and so the IRQ
8559 * handlers didn't access stale or invalid state.
8560 */
8561 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8562 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8e7b6fee
WL		 8563#ifdef CONFIG_DEBUG_FS
8564 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8799c0be
YL		 8565#endif
8566 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8567 if (old_crtc_state->active && !new_crtc_state->active)
8568 crtc_disable_count++;
8569
8570 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8571 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8572
8573 /* For freesync config update on crtc state and params for irq */
8574 update_stream_irq_parameters(dm, dm_new_crtc_state);
8575
8576#ifdef CONFIG_DEBUG_FS
d98af272
WL		 8577 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8578 cur_crc_src = acrtc->dm_irq_params.crc_src;
8579 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8e7b6fee 8580#endif
585d450c 8581
8fe684e9
NK		 8582 if (new_crtc_state->active &&
8583 (!old_crtc_state->active ||
8584 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
585d450c
AP		 8585 dc_stream_retain(dm_new_crtc_state->stream);
8586 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8fe684e9 8587 manage_dm_interrupts(adev, acrtc, true);
8799c0be
YL		 8588 }
8589 /* Handle vrr on->off / off->on transitions */
8590 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
e2881d6d 8591
24eb9374 8592#ifdef CONFIG_DEBUG_FS
8799c0be
YL		 8593 if (new_crtc_state->active &&
8594 (!old_crtc_state->active ||
8595 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8fe684e9
NK		 8596 /**
8597 * Frontend may have changed so reapply the CRC capture
8598 * settings for the stream.
8599 */
8e7b6fee 8600 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
86bc2219 8601#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
d98af272
WL		 8602 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8603 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
c0459bdd 8604 acrtc->dm_irq_params.window_param.update_win = true;
1b11ff76
AL		 8605
8606 /**
8607 * It takes 2 frames for HW to stably generate CRC when
8608 * resuming from suspend, so we set skip_frame_cnt 2.
8609 */
c0459bdd 8610 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
d98af272
WL		 8611 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8612 }
86bc2219 8613#endif
bbc49fc0
WL		 8614 if (amdgpu_dm_crtc_configure_crc_source(
8615 crtc, dm_new_crtc_state, cur_crc_src))
8616 DRM_DEBUG_DRIVER("Failed to configure crc source");
8799c0be 8617 }
8fe684e9 8618 }
2130b87b 8619#endif
8fe684e9 8620 }
e7b07cee 8621
420cd472 8622 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
4d85f45c 8623 if (new_crtc_state->async_flip)
420cd472
DF		 8624 wait_for_vblank = false;
8625
e7b07cee 8626 /* update planes when needed per crtc*/
5cc6dcbd 8627 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 8628 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 8629
54d76575 8630 if (dm_new_crtc_state->stream)
eb3dc897 8631 amdgpu_dm_commit_planes(state, dc_state, dev,
420cd472 8632 dm, crtc, wait_for_vblank);
e7b07cee
HW		 8633 }
8634
6ce8f316
NK		 8635 /* Update audio instances for each connector. */
8636 amdgpu_dm_commit_audio(dev, state);
8637
7230362c 8638 /* restore the backlight level */
7fd13bae
AD		 8639 for (i = 0; i < dm->num_of_edps; i++) {
8640 if (dm->backlight_dev[i] &&
4052287a 8641 (dm->actual_brightness[i] != dm->brightness[i]))
7fd13bae
AD		 8642 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8643 }
83a3439d 8644
e7b07cee
HW		 8645 /*
8646 * send vblank event on all events not handled in flip and
8647 * mark consumed event for drm_atomic_helper_commit_hw_done
8648 */
4a580877 8649 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
0bc9706d 8650 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 8651
0bc9706d
LSL		 8652 if (new_crtc_state->event)
8653 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 8654
0bc9706d 8655 new_crtc_state->event = NULL;
e7b07cee 8656 }
4a580877 8657 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
e7b07cee 8658
29c8f234
LL		 8659 /* Signal HW programming completion */
8660 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 8661
8662 if (wait_for_vblank)
320a1274 8663 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 8664
8665 drm_atomic_helper_cleanup_planes(dev, state);
97028037 8666
5f6fab24
AD		 8667 /* return the stolen vga memory back to VRAM */
8668 if (!adev->mman.keep_stolen_vga_memory)
8669 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8670 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8671
1f6010a9
DF		 8672 /*
8673 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 8674 * so we can put the GPU into runtime suspend if we're not driving any
8675 * displays anymore
8676 */
fe2a1965
LP		 8677 for (i = 0; i < crtc_disable_count; i++)
8678 pm_runtime_put_autosuspend(dev->dev);
97028037 8679 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 8680
8681 if (dc_state_temp)
8682 dc_release_state(dc_state_temp);
e7b07cee
HW		 8683}
8684
e7b07cee
HW		 8685static int dm_force_atomic_commit(struct drm_connector *connector)
8686{
8687 int ret = 0;
8688 struct drm_device *ddev = connector->dev;
8689 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8690 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8691 struct drm_plane *plane = disconnected_acrtc->base.primary;
8692 struct drm_connector_state *conn_state;
8693 struct drm_crtc_state *crtc_state;
8694 struct drm_plane_state *plane_state;
8695
8696 if (!state)
8697 return -ENOMEM;
8698
8699 state->acquire_ctx = ddev->mode_config.acquire_ctx;
8700
8701 /* Construct an atomic state to restore previous display setting */
8702
8703 /*
8704 * Attach connectors to drm_atomic_state
8705 */
8706 conn_state = drm_atomic_get_connector_state(state, connector);
8707
8708 ret = PTR_ERR_OR_ZERO(conn_state);
8709 if (ret)
2dc39051 8710 goto out;
e7b07cee
HW		 8711
8712 /* Attach crtc to drm_atomic_state*/
8713 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8714
8715 ret = PTR_ERR_OR_ZERO(crtc_state);
8716 if (ret)
2dc39051 8717 goto out;
e7b07cee
HW		 8718
8719 /* force a restore */
8720 crtc_state->mode_changed = true;
8721
8722 /* Attach plane to drm_atomic_state */
8723 plane_state = drm_atomic_get_plane_state(state, plane);
8724
8725 ret = PTR_ERR_OR_ZERO(plane_state);
8726 if (ret)
2dc39051 8727 goto out;
e7b07cee
HW		 8728
8729 /* Call commit internally with the state we just constructed */
8730 ret = drm_atomic_commit(state);
e7b07cee 8731
2dc39051 8732out:
e7b07cee 8733 drm_atomic_state_put(state);
2dc39051
VL		 8734 if (ret)
8735 DRM_ERROR("Restoring old state failed with %i\n", ret);
e7b07cee
HW		 8736
8737 return ret;
8738}
8739
8740/*
1f6010a9
DF		 8741 * This function handles all cases when set mode does not come upon hotplug.
8742 * This includes when a display is unplugged then plugged back into the
8743 * same port and when running without usermode desktop manager supprot
e7b07cee 8744 */
3ee6b26b
AD		 8745void dm_restore_drm_connector_state(struct drm_device *dev,
8746 struct drm_connector *connector)
e7b07cee 8747{
c84dec2f 8748 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 8749 struct amdgpu_crtc *disconnected_acrtc;
8750 struct dm_crtc_state *acrtc_state;
8751
8752 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8753 return;
8754
8755 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 8756 if (!disconnected_acrtc)
8757 return;
e7b07cee 8758
70e8ffc5
HW		 8759 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8760 if (!acrtc_state->stream)
e7b07cee
HW		 8761 return;
8762
8763 /*
8764 * If the previous sink is not released and different from the current,
8765 * we deduce we are in a state where we can not rely on usermode call
8766 * to turn on the display, so we do it here
8767 */
8768 if (acrtc_state->stream->sink != aconnector->dc_sink)
8769 dm_force_atomic_commit(&aconnector->base);
8770}
8771
1f6010a9 8772/*
e7b07cee
HW		 8773 * Grabs all modesetting locks to serialize against any blocking commits,
8774 * Waits for completion of all non blocking commits.
8775 */
3ee6b26b
AD		 8776static int do_aquire_global_lock(struct drm_device *dev,
8777 struct drm_atomic_state *state)
e7b07cee
HW		 8778{
8779 struct drm_crtc *crtc;
8780 struct drm_crtc_commit *commit;
8781 long ret;
8782
1f6010a9
DF		 8783 /*
8784 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 8785 * ensure that when the framework release it the
8786 * extra locks we are locking here will get released to
8787 */
8788 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8789 if (ret)
8790 return ret;
8791
8792 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8793 spin_lock(&crtc->commit_lock);
8794 commit = list_first_entry_or_null(&crtc->commit_list,
8795 struct drm_crtc_commit, commit_entry);
8796 if (commit)
8797 drm_crtc_commit_get(commit);
8798 spin_unlock(&crtc->commit_lock);
8799
8800 if (!commit)
8801 continue;
8802
1f6010a9
DF		 8803 /*
8804 * Make sure all pending HW programming completed and
e7b07cee
HW		 8805 * page flips done
8806 */
8807 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8808
8809 if (ret > 0)
8810 ret = wait_for_completion_interruptible_timeout(
8811 &commit->flip_done, 10*HZ);
8812
8813 if (ret == 0)
8814 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 8815 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 8816
8817 drm_crtc_commit_put(commit);
8818 }
8819
8820 return ret < 0 ? ret : 0;
8821}
8822
bb47de73
NK		 8823static void get_freesync_config_for_crtc(
8824 struct dm_crtc_state *new_crtc_state,
8825 struct dm_connector_state *new_con_state)
98e6436d
AK		 8826{
8827 struct mod_freesync_config config = {0};
98e6436d
AK		 8828 struct amdgpu_dm_connector *aconnector =
8829 to_amdgpu_dm_connector(new_con_state->base.connector);
a057ec46 8830 struct drm_display_mode *mode = &new_crtc_state->base.mode;
0ab925d3 8831 int vrefresh = drm_mode_vrefresh(mode);
a85ba005 8832 bool fs_vid_mode = false;
6ffa6799 8833 bool drr_active = false;
98e6436d 8834
a057ec46 8835 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
0ab925d3
NK		 8836 vrefresh >= aconnector->min_vfreq &&
8837 vrefresh <= aconnector->max_vfreq;
bb47de73 8838
6ffa6799
AP		 8839 drr_active = new_crtc_state->vrr_supported &&
8840 new_crtc_state->freesync_config.state != VRR_STATE_DISABLED &&
8841 new_crtc_state->freesync_config.state != VRR_STATE_INACTIVE &&
8842 new_crtc_state->freesync_config.state != VRR_STATE_UNSUPPORTED;
8843
8844 if (drr_active)
a057ec46 8845 new_crtc_state->stream->ignore_msa_timing_param = true;
a85ba005 8846
6ffa6799
AP		 8847 if (new_crtc_state->vrr_supported) {
8848 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
a85ba005
NC		 8849 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
8850 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
69ff8845 8851 config.vsif_supported = true;
180db303 8852 config.btr = true;
98e6436d 8853
a85ba005
NC		 8854 if (fs_vid_mode) {
8855 config.state = VRR_STATE_ACTIVE_FIXED;
8856 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
8857 goto out;
8858 } else if (new_crtc_state->base.vrr_enabled) {
8859 config.state = VRR_STATE_ACTIVE_VARIABLE;
8860 } else {
8861 config.state = VRR_STATE_INACTIVE;
8862 }
8863 }
8864out:
bb47de73
NK		 8865 new_crtc_state->freesync_config = config;
8866}
98e6436d 8867
bb47de73
NK		 8868static void reset_freesync_config_for_crtc(
8869 struct dm_crtc_state *new_crtc_state)
8870{
8871 new_crtc_state->vrr_supported = false;
98e6436d 8872
bb47de73
NK		 8873 memset(&new_crtc_state->vrr_infopacket, 0,
8874 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 8875}
8876
a85ba005
NC		 8877static bool
8878is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
8879 struct drm_crtc_state *new_crtc_state)
8880{
1cbd7887 8881 const struct drm_display_mode *old_mode, *new_mode;
a85ba005
NC		 8882
8883 if (!old_crtc_state || !new_crtc_state)
8884 return false;
8885
1cbd7887
VS		 8886 old_mode = &old_crtc_state->mode;
8887 new_mode = &new_crtc_state->mode;
8888
8889 if (old_mode->clock == new_mode->clock &&
8890 old_mode->hdisplay == new_mode->hdisplay &&
8891 old_mode->vdisplay == new_mode->vdisplay &&
8892 old_mode->htotal == new_mode->htotal &&
8893 old_mode->vtotal != new_mode->vtotal &&
8894 old_mode->hsync_start == new_mode->hsync_start &&
8895 old_mode->vsync_start != new_mode->vsync_start &&
8896 old_mode->hsync_end == new_mode->hsync_end &&
8897 old_mode->vsync_end != new_mode->vsync_end &&
8898 old_mode->hskew == new_mode->hskew &&
8899 old_mode->vscan == new_mode->vscan &&
8900 (old_mode->vsync_end - old_mode->vsync_start) ==
8901 (new_mode->vsync_end - new_mode->vsync_start))
a85ba005
NC		 8902 return true;
8903
8904 return false;
8905}
8906
8907static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
ae67558b 8908 u64 num, den, res;
a85ba005
NC		 8909 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
8910
8911 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
8912
8913 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
8914 den = (unsigned long long)new_crtc_state->mode.htotal *
8915 (unsigned long long)new_crtc_state->mode.vtotal;
8916
8917 res = div_u64(num, den);
8918 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
8919}
8920
f11d9373 8921static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
17ce8a69
RL		 8922 struct drm_atomic_state *state,
8923 struct drm_crtc *crtc,
8924 struct drm_crtc_state *old_crtc_state,
8925 struct drm_crtc_state *new_crtc_state,
8926 bool enable,
8927 bool *lock_and_validation_needed)
e7b07cee 8928{
eb3dc897 8929 struct dm_atomic_state *dm_state = NULL;
54d76575 8930 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 8931 struct dc_stream_state *new_stream;
62f55537 8932 int ret = 0;
d4d4a645 8933
1f6010a9
DF		 8934 /*
8935 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
8936 * update changed items
8937 */
4b9674e5
LL		 8938 struct amdgpu_crtc *acrtc = NULL;
8939 struct amdgpu_dm_connector *aconnector = NULL;
8940 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
8941 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
e7b07cee 8942
4b9674e5 8943 new_stream = NULL;
9635b754 8944
4b9674e5
LL		 8945 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8946 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8947 acrtc = to_amdgpu_crtc(crtc);
4b9674e5 8948 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 8949
4b9674e5
LL		 8950 /* TODO This hack should go away */
8951 if (aconnector && enable) {
8952 /* Make sure fake sink is created in plug-in scenario */
8953 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
8954 &aconnector->base);
8955 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
8956 &aconnector->base);
19f89e23 8957
4b9674e5
LL		 8958 if (IS_ERR(drm_new_conn_state)) {
8959 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
8960 goto fail;
8961 }
19f89e23 8962
4b9674e5
LL		 8963 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
8964 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 8965
02d35a67
JFZ		 8966 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8967 goto skip_modeset;
8968
cbd14ae7
SW		 8969 new_stream = create_validate_stream_for_sink(aconnector,
8970 &new_crtc_state->mode,
8971 dm_new_conn_state,
8972 dm_old_crtc_state->stream);
19f89e23 8973
4b9674e5
LL		 8974 /*
8975 * we can have no stream on ACTION_SET if a display
8976 * was disconnected during S3, in this case it is not an
8977 * error, the OS will be updated after detection, and
8978 * will do the right thing on next atomic commit
8979 */
19f89e23 8980
4b9674e5
LL		 8981 if (!new_stream) {
8982 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8983 __func__, acrtc->base.base.id);
8984 ret = -ENOMEM;
8985 goto fail;
8986 }
e7b07cee 8987
3d4e52d0
VL		 8988 /*
8989 * TODO: Check VSDB bits to decide whether this should
8990 * be enabled or not.
8991 */
8992 new_stream->triggered_crtc_reset.enabled =
8993 dm->force_timing_sync;
8994
4b9674e5 8995 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 8996
88694af9
NK		 8997 ret = fill_hdr_info_packet(drm_new_conn_state,
8998 &new_stream->hdr_static_metadata);
8999 if (ret)
9000 goto fail;
9001
7e930949
NK		 9002 /*
9003 * If we already removed the old stream from the context
9004 * (and set the new stream to NULL) then we can't reuse
9005 * the old stream even if the stream and scaling are unchanged.
9006 * We'll hit the BUG_ON and black screen.
9007 *
9008 * TODO: Refactor this function to allow this check to work
9009 * in all conditions.
9010 */
4243c84a
MD		 9011 if (amdgpu_freesync_vid_mode &&
9012 dm_new_crtc_state->stream &&
a85ba005
NC		 9013 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9014 goto skip_modeset;
9015
7e930949
NK		 9016 if (dm_new_crtc_state->stream &&
9017 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4b9674e5
LL		 9018 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9019 new_crtc_state->mode_changed = false;
9020 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9021 new_crtc_state->mode_changed);
62f55537 9022 }
4b9674e5 9023 }
b830ebc9 9024
02d35a67 9025 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 9026 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9027 goto skip_modeset;
e7b07cee 9028
9f07550b 9029 drm_dbg_state(state->dev,
4b9674e5
LL		 9030 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9031 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9032 "connectors_changed:%d\n",
9033 acrtc->crtc_id,
9034 new_crtc_state->enable,
9035 new_crtc_state->active,
9036 new_crtc_state->planes_changed,
9037 new_crtc_state->mode_changed,
9038 new_crtc_state->active_changed,
9039 new_crtc_state->connectors_changed);
62f55537 9040
4b9674e5
LL		 9041 /* Remove stream for any changed/disabled CRTC */
9042 if (!enable) {
62f55537 9043
4b9674e5
LL		 9044 if (!dm_old_crtc_state->stream)
9045 goto skip_modeset;
eb3dc897 9046
4243c84a 9047 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
a85ba005
NC		 9048 is_timing_unchanged_for_freesync(new_crtc_state,
9049 old_crtc_state)) {
9050 new_crtc_state->mode_changed = false;
9051 DRM_DEBUG_DRIVER(
9052 "Mode change not required for front porch change, "
9053 "setting mode_changed to %d",
9054 new_crtc_state->mode_changed);
9055
9056 set_freesync_fixed_config(dm_new_crtc_state);
9057
9058 goto skip_modeset;
4243c84a 9059 } else if (amdgpu_freesync_vid_mode && aconnector &&
a85ba005
NC		 9060 is_freesync_video_mode(&new_crtc_state->mode,
9061 aconnector)) {
e88ebd83
SC		 9062 struct drm_display_mode *high_mode;
9063
9064 high_mode = get_highest_refresh_rate_mode(aconnector, false);
9065 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9066 set_freesync_fixed_config(dm_new_crtc_state);
9067 }
a85ba005
NC		 9068 }
9069
4b9674e5
LL		 9070 ret = dm_atomic_get_state(state, &dm_state);
9071 if (ret)
9072 goto fail;
e7b07cee 9073
4b9674e5
LL		 9074 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9075 crtc->base.id);
62f55537 9076
4b9674e5
LL		 9077 /* i.e. reset mode */
9078 if (dc_remove_stream_from_ctx(
9079 dm->dc,
9080 dm_state->context,
9081 dm_old_crtc_state->stream) != DC_OK) {
9082 ret = -EINVAL;
9083 goto fail;
9084 }
62f55537 9085
4b9674e5
LL		 9086 dc_stream_release(dm_old_crtc_state->stream);
9087 dm_new_crtc_state->stream = NULL;
bb47de73 9088
4b9674e5 9089 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 9090
4b9674e5 9091 *lock_and_validation_needed = true;
62f55537 9092
4b9674e5
LL		 9093 } else {/* Add stream for any updated/enabled CRTC */
9094 /*
9095 * Quick fix to prevent NULL pointer on new_stream when
9096 * added MST connectors not found in existing crtc_state in the chained mode
9097 * TODO: need to dig out the root cause of that
9098 */
84a8b390 9099 if (!aconnector)
4b9674e5 9100 goto skip_modeset;
62f55537 9101
4b9674e5
LL		 9102 if (modereset_required(new_crtc_state))
9103 goto skip_modeset;
62f55537 9104
4b9674e5
LL		 9105 if (modeset_required(new_crtc_state, new_stream,
9106 dm_old_crtc_state->stream)) {
62f55537 9107
4b9674e5 9108 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 9109
4b9674e5
LL		 9110 ret = dm_atomic_get_state(state, &dm_state);
9111 if (ret)
9112 goto fail;
27b3f4fc 9113
4b9674e5 9114 dm_new_crtc_state->stream = new_stream;
62f55537 9115
4b9674e5 9116 dc_stream_retain(new_stream);
1dc90497 9117
4711c033
LT		 9118 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9119 crtc->base.id);
1dc90497 9120
4b9674e5
LL		 9121 if (dc_add_stream_to_ctx(
9122 dm->dc,
9123 dm_state->context,
9124 dm_new_crtc_state->stream) != DC_OK) {
9125 ret = -EINVAL;
9126 goto fail;
9b690ef3
BL		 9127 }
9128
4b9674e5
LL		 9129 *lock_and_validation_needed = true;
9130 }
9131 }
e277adc5 9132
4b9674e5
LL		 9133skip_modeset:
9134 /* Release extra reference */
9135 if (new_stream)
9136 dc_stream_release(new_stream);
e277adc5 9137
4b9674e5
LL		 9138 /*
9139 * We want to do dc stream updates that do not require a
9140 * full modeset below.
9141 */
2afda735 9142 if (!(enable && aconnector && new_crtc_state->active))
4b9674e5
LL		 9143 return 0;
9144 /*
9145 * Given above conditions, the dc state cannot be NULL because:
9146 * 1. We're in the process of enabling CRTCs (just been added
9147 * to the dc context, or already is on the context)
9148 * 2. Has a valid connector attached, and
9149 * 3. Is currently active and enabled.
9150 * => The dc stream state currently exists.
9151 */
9152 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 9153
4b9674e5 9154 /* Scaling or underscan settings */
c521fc31
RL		 9155 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9156 drm_atomic_crtc_needs_modeset(new_crtc_state))
4b9674e5
LL		 9157 update_stream_scaling_settings(
9158 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 9159
b05e2c5e
DF		 9160 /* ABM settings */
9161 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9162
4b9674e5
LL		 9163 /*
9164 * Color management settings. We also update color properties
9165 * when a modeset is needed, to ensure it gets reprogrammed.
9166 */
9167 if (dm_new_crtc_state->base.color_mgmt_changed ||
9168 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
cf020d49 9169 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
4b9674e5
LL		 9170 if (ret)
9171 goto fail;
62f55537 9172 }
e7b07cee 9173
4b9674e5
LL		 9174 /* Update Freesync settings. */
9175 get_freesync_config_for_crtc(dm_new_crtc_state,
9176 dm_new_conn_state);
9177
62f55537 9178 return ret;
9635b754
DS		 9179
9180fail:
9181 if (new_stream)
9182 dc_stream_release(new_stream);
9183 return ret;
62f55537 9184}
9b690ef3 9185
f6ff2a08
NK		 9186static bool should_reset_plane(struct drm_atomic_state *state,
9187 struct drm_plane *plane,
9188 struct drm_plane_state *old_plane_state,
9189 struct drm_plane_state *new_plane_state)
9190{
9191 struct drm_plane *other;
9192 struct drm_plane_state *old_other_state, *new_other_state;
9193 struct drm_crtc_state *new_crtc_state;
9194 int i;
9195
70a1efac
NK		 9196 /*
9197 * TODO: Remove this hack once the checks below are sufficient
9198 * enough to determine when we need to reset all the planes on
9199 * the stream.
9200 */
9201 if (state->allow_modeset)
9202 return true;
9203
f6ff2a08
NK		 9204 /* Exit early if we know that we're adding or removing the plane. */
9205 if (old_plane_state->crtc != new_plane_state->crtc)
9206 return true;
9207
9208 /* old crtc == new_crtc == NULL, plane not in context. */
9209 if (!new_plane_state->crtc)
9210 return false;
9211
9212 new_crtc_state =
9213 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9214
9215 if (!new_crtc_state)
9216 return true;
9217
7316c4ad
NK		 9218 /* CRTC Degamma changes currently require us to recreate planes. */
9219 if (new_crtc_state->color_mgmt_changed)
9220 return true;
9221
f6ff2a08
NK		 9222 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9223 return true;
9224
9225 /*
9226 * If there are any new primary or overlay planes being added or
9227 * removed then the z-order can potentially change. To ensure
9228 * correct z-order and pipe acquisition the current DC architecture
9229 * requires us to remove and recreate all existing planes.
9230 *
9231 * TODO: Come up with a more elegant solution for this.
9232 */
9233 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
6eed95b0 9234 struct amdgpu_framebuffer *old_afb, *new_afb;
f6ff2a08
NK		 9235 if (other->type == DRM_PLANE_TYPE_CURSOR)
9236 continue;
9237
9238 if (old_other_state->crtc != new_plane_state->crtc &&
9239 new_other_state->crtc != new_plane_state->crtc)
9240 continue;
9241
9242 if (old_other_state->crtc != new_other_state->crtc)
9243 return true;
9244
dc4cb30d
NK		 9245 /* Src/dst size and scaling updates. */
9246 if (old_other_state->src_w != new_other_state->src_w ||
9247 old_other_state->src_h != new_other_state->src_h ||
9248 old_other_state->crtc_w != new_other_state->crtc_w ||
9249 old_other_state->crtc_h != new_other_state->crtc_h)
9250 return true;
9251
9252 /* Rotation / mirroring updates. */
9253 if (old_other_state->rotation != new_other_state->rotation)
9254 return true;
9255
9256 /* Blending updates. */
9257 if (old_other_state->pixel_blend_mode !=
9258 new_other_state->pixel_blend_mode)
9259 return true;
9260
9261 /* Alpha updates. */
9262 if (old_other_state->alpha != new_other_state->alpha)
9263 return true;
9264
9265 /* Colorspace changes. */
9266 if (old_other_state->color_range != new_other_state->color_range ||
9267 old_other_state->color_encoding != new_other_state->color_encoding)
9268 return true;
9269
9a81cc60
NK		 9270 /* Framebuffer checks fall at the end. */
9271 if (!old_other_state->fb || !new_other_state->fb)
9272 continue;
9273
9274 /* Pixel format changes can require bandwidth updates. */
9275 if (old_other_state->fb->format != new_other_state->fb->format)
9276 return true;
9277
6eed95b0
BN		 9278 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9279 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9a81cc60
NK		 9280
9281 /* Tiling and DCC changes also require bandwidth updates. */
37384b3f
BN		 9282 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9283 old_afb->base.modifier != new_afb->base.modifier)
f6ff2a08
NK		 9284 return true;
9285 }
9286
9287 return false;
9288}
9289
b0455fda
SS		 9290static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9291 struct drm_plane_state *new_plane_state,
9292 struct drm_framebuffer *fb)
9293{
e72868c4
SS		 9294 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9295 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
b0455fda 9296 unsigned int pitch;
e72868c4 9297 bool linear;
b0455fda
SS		 9298
9299 if (fb->width > new_acrtc->max_cursor_width ||
9300 fb->height > new_acrtc->max_cursor_height) {
9301 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9302 new_plane_state->fb->width,
9303 new_plane_state->fb->height);
9304 return -EINVAL;
9305 }
9306 if (new_plane_state->src_w != fb->width << 16 ||
9307 new_plane_state->src_h != fb->height << 16) {
9308 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9309 return -EINVAL;
9310 }
9311
9312 /* Pitch in pixels */
9313 pitch = fb->pitches[0] / fb->format->cpp[0];
9314
9315 if (fb->width != pitch) {
9316 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9317 fb->width, pitch);
9318 return -EINVAL;
9319 }
9320
9321 switch (pitch) {
9322 case 64:
9323 case 128:
9324 case 256:
9325 /* FB pitch is supported by cursor plane */
9326 break;
9327 default:
9328 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9329 return -EINVAL;
9330 }
9331
e72868c4
SS		 9332 /* Core DRM takes care of checking FB modifiers, so we only need to
9333 * check tiling flags when the FB doesn't have a modifier. */
9334 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9335 if (adev->family < AMDGPU_FAMILY_AI) {
9336 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9337 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9338 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9339 } else {
9340 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9341 }
9342 if (!linear) {
9343 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9344 return -EINVAL;
9345 }
9346 }
9347
b0455fda
SS		 9348 return 0;
9349}
9350
9e869063
LL		 9351static int dm_update_plane_state(struct dc *dc,
9352 struct drm_atomic_state *state,
9353 struct drm_plane *plane,
9354 struct drm_plane_state *old_plane_state,
9355 struct drm_plane_state *new_plane_state,
9356 bool enable,
9357 bool *lock_and_validation_needed)
62f55537 9358{
eb3dc897
NK		 9359
9360 struct dm_atomic_state *dm_state = NULL;
62f55537 9361 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 9362 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 9363 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 9364 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
626bf90f 9365 struct amdgpu_crtc *new_acrtc;
f6ff2a08 9366 bool needs_reset;
62f55537 9367 int ret = 0;
e7b07cee 9368
9b690ef3 9369
9e869063
LL		 9370 new_plane_crtc = new_plane_state->crtc;
9371 old_plane_crtc = old_plane_state->crtc;
9372 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9373 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 9374
626bf90f
SS		 9375 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9376 if (!enable || !new_plane_crtc ||
9377 drm_atomic_plane_disabling(plane->state, new_plane_state))
9378 return 0;
9379
9380 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9381
5f581248
SS		 9382 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9383 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9384 return -EINVAL;
9385 }
9386
24f99d2b 9387 if (new_plane_state->fb) {
b0455fda
SS		 9388 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9389 new_plane_state->fb);
9390 if (ret)
9391 return ret;
24f99d2b
SS		 9392 }
9393
9e869063 9394 return 0;
626bf90f 9395 }
9b690ef3 9396
f6ff2a08
NK		 9397 needs_reset = should_reset_plane(state, plane, old_plane_state,
9398 new_plane_state);
9399
9e869063
LL		 9400 /* Remove any changed/removed planes */
9401 if (!enable) {
f6ff2a08 9402 if (!needs_reset)
9e869063 9403 return 0;
a7b06724 9404
9e869063
LL		 9405 if (!old_plane_crtc)
9406 return 0;
62f55537 9407
9e869063
LL		 9408 old_crtc_state = drm_atomic_get_old_crtc_state(
9409 state, old_plane_crtc);
9410 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 9411
9e869063
LL		 9412 if (!dm_old_crtc_state->stream)
9413 return 0;
62f55537 9414
9e869063
LL		 9415 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9416 plane->base.id, old_plane_crtc->base.id);
9b690ef3 9417
9e869063
LL		 9418 ret = dm_atomic_get_state(state, &dm_state);
9419 if (ret)
9420 return ret;
eb3dc897 9421
9e869063
LL		 9422 if (!dc_remove_plane_from_context(
9423 dc,
9424 dm_old_crtc_state->stream,
9425 dm_old_plane_state->dc_state,
9426 dm_state->context)) {
62f55537 9427
c3537613 9428 return -EINVAL;
9e869063 9429 }
e7b07cee 9430
9b690ef3 9431
9e869063
LL		 9432 dc_plane_state_release(dm_old_plane_state->dc_state);
9433 dm_new_plane_state->dc_state = NULL;
1dc90497 9434
9e869063 9435 *lock_and_validation_needed = true;
1dc90497 9436
9e869063
LL		 9437 } else { /* Add new planes */
9438 struct dc_plane_state *dc_new_plane_state;
1dc90497 9439
9e869063
LL		 9440 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9441 return 0;
e7b07cee 9442
9e869063
LL		 9443 if (!new_plane_crtc)
9444 return 0;
e7b07cee 9445
9e869063
LL		 9446 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9447 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 9448
9e869063
LL		 9449 if (!dm_new_crtc_state->stream)
9450 return 0;
62f55537 9451
f6ff2a08 9452 if (!needs_reset)
9e869063 9453 return 0;
62f55537 9454
8c44515b
AP		 9455 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9456 if (ret)
9457 return ret;
9458
9e869063 9459 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 9460
9e869063
LL		 9461 dc_new_plane_state = dc_create_plane_state(dc);
9462 if (!dc_new_plane_state)
9463 return -ENOMEM;
62f55537 9464
4711c033
LT		 9465 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9466 plane->base.id, new_plane_crtc->base.id);
8c45c5db 9467
695af5f9 9468 ret = fill_dc_plane_attributes(
1348969a 9469 drm_to_adev(new_plane_crtc->dev),
9e869063
LL		 9470 dc_new_plane_state,
9471 new_plane_state,
9472 new_crtc_state);
9473 if (ret) {
9474 dc_plane_state_release(dc_new_plane_state);
9475 return ret;
9476 }
62f55537 9477
9e869063
LL		 9478 ret = dm_atomic_get_state(state, &dm_state);
9479 if (ret) {
9480 dc_plane_state_release(dc_new_plane_state);
9481 return ret;
9482 }
eb3dc897 9483
9e869063
LL		 9484 /*
9485 * Any atomic check errors that occur after this will
9486 * not need a release. The plane state will be attached
9487 * to the stream, and therefore part of the atomic
9488 * state. It'll be released when the atomic state is
9489 * cleaned.
9490 */
9491 if (!dc_add_plane_to_context(
9492 dc,
9493 dm_new_crtc_state->stream,
9494 dc_new_plane_state,
9495 dm_state->context)) {
62f55537 9496
9e869063
LL		 9497 dc_plane_state_release(dc_new_plane_state);
9498 return -EINVAL;
9499 }
8c45c5db 9500
9e869063 9501 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 9502
214993e1
ML		 9503 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9504
9e869063
LL		 9505 /* Tell DC to do a full surface update every time there
9506 * is a plane change. Inefficient, but works for now.
9507 */
9508 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9509
9510 *lock_and_validation_needed = true;
62f55537 9511 }
e7b07cee
HW		 9512
9513
62f55537
AG		 9514 return ret;
9515}
a87fa993 9516
69cb5629
VZ		 9517static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9518 int *src_w, int *src_h)
9519{
9520 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9521 case DRM_MODE_ROTATE_90:
9522 case DRM_MODE_ROTATE_270:
9523 *src_w = plane_state->src_h >> 16;
9524 *src_h = plane_state->src_w >> 16;
9525 break;
9526 case DRM_MODE_ROTATE_0:
9527 case DRM_MODE_ROTATE_180:
9528 default:
9529 *src_w = plane_state->src_w >> 16;
9530 *src_h = plane_state->src_h >> 16;
9531 break;
9532 }
9533}
9534
12f4849a
SS		 9535static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9536 struct drm_crtc *crtc,
9537 struct drm_crtc_state *new_crtc_state)
9538{
d1bfbe8a
SS		 9539 struct drm_plane *cursor = crtc->cursor, *underlying;
9540 struct drm_plane_state *new_cursor_state, *new_underlying_state;
9541 int i;
9542 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
69cb5629
VZ		 9543 int cursor_src_w, cursor_src_h;
9544 int underlying_src_w, underlying_src_h;
12f4849a
SS		 9545
9546 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9547 * cursor per pipe but it's going to inherit the scaling and
9548 * positioning from the underlying pipe. Check the cursor plane's
d1bfbe8a 9549 * blending properties match the underlying planes'. */
12f4849a 9550
d1bfbe8a
SS		 9551 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9552 if (!new_cursor_state || !new_cursor_state->fb) {
12f4849a
SS		 9553 return 0;
9554 }
9555
69cb5629
VZ		 9556 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9557 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9558 cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
12f4849a 9559
d1bfbe8a
SS		 9560 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9561 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9562 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9563 continue;
12f4849a 9564
d1bfbe8a
SS		 9565 /* Ignore disabled planes */
9566 if (!new_underlying_state->fb)
9567 continue;
9568
69cb5629
VZ		 9569 dm_get_oriented_plane_size(new_underlying_state,
9570 &underlying_src_w, &underlying_src_h);
9571 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9572 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
d1bfbe8a
SS		 9573
9574 if (cursor_scale_w != underlying_scale_w ||
9575 cursor_scale_h != underlying_scale_h) {
9576 drm_dbg_atomic(crtc->dev,
9577 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9578 cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9579 return -EINVAL;
9580 }
9581
9582 /* If this plane covers the whole CRTC, no need to check planes underneath */
9583 if (new_underlying_state->crtc_x <= 0 &&
9584 new_underlying_state->crtc_y <= 0 &&
9585 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9586 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9587 break;
12f4849a
SS		 9588 }
9589
9590 return 0;
9591}
9592
e10517b3 9593#if defined(CONFIG_DRM_AMD_DC_DCN)
44be939f
ML		 9594static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9595{
9596 struct drm_connector *connector;
128f8ed5 9597 struct drm_connector_state *conn_state, *old_conn_state;
44be939f
ML		 9598 struct amdgpu_dm_connector *aconnector = NULL;
9599 int i;
128f8ed5
RL		 9600 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9601 if (!conn_state->crtc)
9602 conn_state = old_conn_state;
9603
44be939f
ML		 9604 if (conn_state->crtc != crtc)
9605 continue;
9606
9607 aconnector = to_amdgpu_dm_connector(connector);
9608 if (!aconnector->port || !aconnector->mst_port)
9609 aconnector = NULL;
9610 else
9611 break;
9612 }
9613
9614 if (!aconnector)
9615 return 0;
9616
9617 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9618}
e10517b3 9619#endif
44be939f 9620
b8592b48
LL		 9621/**
9622 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
c620e79b 9623 *
b8592b48
LL		 9624 * @dev: The DRM device
9625 * @state: The atomic state to commit
9626 *
9627 * Validate that the given atomic state is programmable by DC into hardware.
9628 * This involves constructing a &struct dc_state reflecting the new hardware
9629 * state we wish to commit, then querying DC to see if it is programmable. It's
9630 * important not to modify the existing DC state. Otherwise, atomic_check
9631 * may unexpectedly commit hardware changes.
9632 *
9633 * When validating the DC state, it's important that the right locks are
9634 * acquired. For full updates case which removes/adds/updates streams on one
9635 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9636 * that any such full update commit will wait for completion of any outstanding
f6d7c7fa 9637 * flip using DRMs synchronization events.
b8592b48
LL		 9638 *
9639 * Note that DM adds the affected connectors for all CRTCs in state, when that
9640 * might not seem necessary. This is because DC stream creation requires the
9641 * DC sink, which is tied to the DRM connector state. Cleaning this up should
9642 * be possible but non-trivial - a possible TODO item.
9643 *
9644 * Return: -Error code if validation failed.
9645 */
7578ecda
AD		 9646static int amdgpu_dm_atomic_check(struct drm_device *dev,
9647 struct drm_atomic_state *state)
62f55537 9648{
1348969a 9649 struct amdgpu_device *adev = drm_to_adev(dev);
eb3dc897 9650 struct dm_atomic_state *dm_state = NULL;
62f55537 9651 struct dc *dc = adev->dm.dc;
62f55537 9652 struct drm_connector *connector;
c2cea706 9653 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 9654 struct drm_crtc *crtc;
fc9e9920 9655 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 9656 struct drm_plane *plane;
9657 struct drm_plane_state *old_plane_state, *new_plane_state;
74a16675 9658 enum dc_status status;
1e88ad0a 9659 int ret, i;
62f55537 9660 bool lock_and_validation_needed = false;
214993e1 9661 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6513104b
HW		 9662#if defined(CONFIG_DRM_AMD_DC_DCN)
9663 struct dsc_mst_fairness_vars vars[MAX_PIPES];
9664#endif
62f55537 9665
e8a98235 9666 trace_amdgpu_dm_atomic_check_begin(state);
c44a22b3 9667
62f55537 9668 ret = drm_atomic_helper_check_modeset(dev, state);
68ca1c3e
S		 9669 if (ret) {
9670 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
01e28f9c 9671 goto fail;
68ca1c3e 9672 }
62f55537 9673
c5892a10
SW		 9674 /* Check connector changes */
9675 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9676 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9677 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9678
9679 /* Skip connectors that are disabled or part of modeset already. */
c5892a10
SW		 9680 if (!new_con_state->crtc)
9681 continue;
9682
9683 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9684 if (IS_ERR(new_crtc_state)) {
68ca1c3e 9685 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
c5892a10
SW		 9686 ret = PTR_ERR(new_crtc_state);
9687 goto fail;
9688 }
9689
9690 if (dm_old_con_state->abm_level !=
9691 dm_new_con_state->abm_level)
9692 new_crtc_state->connectors_changed = true;
9693 }
9694
e10517b3 9695#if defined(CONFIG_DRM_AMD_DC_DCN)
349a19b2 9696 if (dc_resource_is_dsc_encoding_supported(dc)) {
44be939f
ML		 9697 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9698 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9699 ret = add_affected_mst_dsc_crtcs(state, crtc);
68ca1c3e
S		 9700 if (ret) {
9701 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
44be939f 9702 goto fail;
68ca1c3e 9703 }
44be939f
ML		 9704 }
9705 }
9706 }
e10517b3 9707#endif
1e88ad0a 9708 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
886876ec
EB		 9709 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9710
1e88ad0a 9711 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 9712 !new_crtc_state->color_mgmt_changed &&
886876ec
EB		 9713 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9714 dm_old_crtc_state->dsc_force_changed == false)
1e88ad0a 9715 continue;
7bef1af3 9716
03fc4cf4 9717 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
68ca1c3e
S		 9718 if (ret) {
9719 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
03fc4cf4 9720 goto fail;
68ca1c3e 9721 }
03fc4cf4 9722
1e88ad0a
S		 9723 if (!new_crtc_state->enable)
9724 continue;
fc9e9920 9725
1e88ad0a 9726 ret = drm_atomic_add_affected_connectors(state, crtc);
68ca1c3e
S		 9727 if (ret) {
9728 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
706bc8c5 9729 goto fail;
68ca1c3e 9730 }
fc9e9920 9731
1e88ad0a 9732 ret = drm_atomic_add_affected_planes(state, crtc);
68ca1c3e
S		 9733 if (ret) {
9734 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
1e88ad0a 9735 goto fail;
68ca1c3e 9736 }
115a385c 9737
cbac53f7 9738 if (dm_old_crtc_state->dsc_force_changed)
115a385c 9739 new_crtc_state->mode_changed = true;
e7b07cee
HW		 9740 }
9741
2d9e6431
NK		 9742 /*
9743 * Add all primary and overlay planes on the CRTC to the state
9744 * whenever a plane is enabled to maintain correct z-ordering
9745 * and to enable fast surface updates.
9746 */
9747 drm_for_each_crtc(crtc, dev) {
9748 bool modified = false;
9749
9750 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9751 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9752 continue;
9753
9754 if (new_plane_state->crtc == crtc ||
9755 old_plane_state->crtc == crtc) {
9756 modified = true;
9757 break;
9758 }
9759 }
9760
9761 if (!modified)
9762 continue;
9763
9764 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9765 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9766 continue;
9767
9768 new_plane_state =
9769 drm_atomic_get_plane_state(state, plane);
9770
9771 if (IS_ERR(new_plane_state)) {
9772 ret = PTR_ERR(new_plane_state);
68ca1c3e 9773 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
2d9e6431
NK		 9774 goto fail;
9775 }
9776 }
9777 }
9778
22c42b0e
LL		 9779 /*
9780 * DC consults the zpos (layer_index in DC terminology) to determine the
9781 * hw plane on which to enable the hw cursor (see
9782 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9783 * atomic state, so call drm helper to normalize zpos.
9784 */
9785 drm_atomic_normalize_zpos(dev, state);
9786
62f55537 9787 /* Remove exiting planes if they are modified */
9e869063
LL		 9788 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9789 ret = dm_update_plane_state(dc, state, plane,
9790 old_plane_state,
9791 new_plane_state,
9792 false,
9793 &lock_and_validation_needed);
68ca1c3e
S		 9794 if (ret) {
9795 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9e869063 9796 goto fail;
68ca1c3e 9797 }
62f55537
AG		 9798 }
9799
9800 /* Disable all crtcs which require disable */
4b9674e5
LL		 9801 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9802 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9803 old_crtc_state,
9804 new_crtc_state,
9805 false,
9806 &lock_and_validation_needed);
68ca1c3e
S		 9807 if (ret) {
9808 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
4b9674e5 9809 goto fail;
68ca1c3e 9810 }
62f55537
AG		 9811 }
9812
9813 /* Enable all crtcs which require enable */
4b9674e5
LL		 9814 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9815 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9816 old_crtc_state,
9817 new_crtc_state,
9818 true,
9819 &lock_and_validation_needed);
68ca1c3e
S		 9820 if (ret) {
9821 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
4b9674e5 9822 goto fail;
68ca1c3e 9823 }
62f55537
AG		 9824 }
9825
9826 /* Add new/modified planes */
9e869063
LL		 9827 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9828 ret = dm_update_plane_state(dc, state, plane,
9829 old_plane_state,
9830 new_plane_state,
9831 true,
9832 &lock_and_validation_needed);
68ca1c3e
S		 9833 if (ret) {
9834 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9e869063 9835 goto fail;
68ca1c3e 9836 }
62f55537
AG		 9837 }
9838
876fcc42
FZ		 9839#if defined(CONFIG_DRM_AMD_DC_DCN)
9840 if (dc_resource_is_dsc_encoding_supported(dc)) {
7cce4cd6
LP		 9841 ret = pre_validate_dsc(state, &dm_state, vars);
9842 if (ret != 0)
876fcc42 9843 goto fail;
876fcc42
FZ		 9844 }
9845#endif
9846
b349f76e
ES		 9847 /* Run this here since we want to validate the streams we created */
9848 ret = drm_atomic_helper_check_planes(dev, state);
68ca1c3e
S		 9849 if (ret) {
9850 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
b349f76e 9851 goto fail;
68ca1c3e 9852 }
62f55537 9853
214993e1
ML		 9854 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9855 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9856 if (dm_new_crtc_state->mpo_requested)
9857 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
9858 }
9859
12f4849a
SS		 9860 /* Check cursor planes scaling */
9861 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9862 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
68ca1c3e
S		 9863 if (ret) {
9864 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
12f4849a 9865 goto fail;
68ca1c3e 9866 }
12f4849a
SS		 9867 }
9868
43d10d30
NK		 9869 if (state->legacy_cursor_update) {
9870 /*
9871 * This is a fast cursor update coming from the plane update
9872 * helper, check if it can be done asynchronously for better
9873 * performance.
9874 */
9875 state->async_update =
9876 !drm_atomic_helper_async_check(dev, state);
9877
9878 /*
9879 * Skip the remaining global validation if this is an async
9880 * update. Cursor updates can be done without affecting
9881 * state or bandwidth calcs and this avoids the performance
9882 * penalty of locking the private state object and
9883 * allocating a new dc_state.
9884 */
9885 if (state->async_update)
9886 return 0;
9887 }
9888
ebdd27e1 9889 /* Check scaling and underscan changes*/
1f6010a9 9890 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 9891 * new stream into context w\o causing full reset. Need to
9892 * decide how to handle.
9893 */
c2cea706 9894 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 9895 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9896 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9897 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 9898
9899 /* Skip any modesets/resets */
0bc9706d
LSL		 9900 if (!acrtc || drm_atomic_crtc_needs_modeset(
9901 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 9902 continue;
9903
b830ebc9 9904 /* Skip any thing not scale or underscan changes */
54d76575 9905 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 9906 continue;
9907
9908 lock_and_validation_needed = true;
9909 }
9910
f6d7c7fa
NK		 9911 /**
9912 * Streams and planes are reset when there are changes that affect
9913 * bandwidth. Anything that affects bandwidth needs to go through
9914 * DC global validation to ensure that the configuration can be applied
9915 * to hardware.
9916 *
9917 * We have to currently stall out here in atomic_check for outstanding
9918 * commits to finish in this case because our IRQ handlers reference
9919 * DRM state directly - we can end up disabling interrupts too early
9920 * if we don't.
9921 *
9922 * TODO: Remove this stall and drop DM state private objects.
a87fa993 9923 */
f6d7c7fa 9924 if (lock_and_validation_needed) {
eb3dc897 9925 ret = dm_atomic_get_state(state, &dm_state);
68ca1c3e
S		 9926 if (ret) {
9927 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
eb3dc897 9928 goto fail;
68ca1c3e 9929 }
e7b07cee
HW		 9930
9931 ret = do_aquire_global_lock(dev, state);
68ca1c3e
S		 9932 if (ret) {
9933 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
e7b07cee 9934 goto fail;
68ca1c3e 9935 }
1dc90497 9936
d9fe1a4c 9937#if defined(CONFIG_DRM_AMD_DC_DCN)
7cce4cd6
LP		 9938 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
9939 if (ret) {
68ca1c3e 9940 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
8c20a1ed 9941 goto fail;
68ca1c3e 9942 }
8c20a1ed 9943
6513104b 9944 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
68ca1c3e
S		 9945 if (ret) {
9946 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
29b9ba74 9947 goto fail;
68ca1c3e 9948 }
d9fe1a4c 9949#endif
29b9ba74 9950
ded58c7b
ZL		 9951 /*
9952 * Perform validation of MST topology in the state:
9953 * We need to perform MST atomic check before calling
9954 * dc_validate_global_state(), or there is a chance
9955 * to get stuck in an infinite loop and hang eventually.
9956 */
9957 ret = drm_dp_mst_atomic_check(state);
68ca1c3e
S		 9958 if (ret) {
9959 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
ded58c7b 9960 goto fail;
68ca1c3e 9961 }
85fb8bb9 9962 status = dc_validate_global_state(dc, dm_state->context, true);
74a16675 9963 if (status != DC_OK) {
68ca1c3e 9964 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
74a16675 9965 dc_status_to_str(status), status);
e7b07cee
HW		 9966 ret = -EINVAL;
9967 goto fail;
9968 }
bd200d19 9969 } else {
674e78ac 9970 /*
bd200d19
NK		 9971 * The commit is a fast update. Fast updates shouldn't change
9972 * the DC context, affect global validation, and can have their
9973 * commit work done in parallel with other commits not touching
9974 * the same resource. If we have a new DC context as part of
9975 * the DM atomic state from validation we need to free it and
9976 * retain the existing one instead.
fde9f39a
MR		 9977 *
9978 * Furthermore, since the DM atomic state only contains the DC
9979 * context and can safely be annulled, we can free the state
9980 * and clear the associated private object now to free
9981 * some memory and avoid a possible use-after-free later.
674e78ac 9982 */
bd200d19 9983
fde9f39a
MR		 9984 for (i = 0; i < state->num_private_objs; i++) {
9985 struct drm_private_obj *obj = state->private_objs[i].ptr;
bd200d19 9986
fde9f39a
MR		 9987 if (obj->funcs == adev->dm.atomic_obj.funcs) {
9988 int j = state->num_private_objs-1;
bd200d19 9989
fde9f39a
MR		 9990 dm_atomic_destroy_state(obj,
9991 state->private_objs[i].state);
9992
9993 /* If i is not at the end of the array then the
9994 * last element needs to be moved to where i was
9995 * before the array can safely be truncated.
9996 */
9997 if (i != j)
9998 state->private_objs[i] =
9999 state->private_objs[j];
bd200d19 10000
fde9f39a
MR		 10001 state->private_objs[j].ptr = NULL;
10002 state->private_objs[j].state = NULL;
10003 state->private_objs[j].old_state = NULL;
10004 state->private_objs[j].new_state = NULL;
10005
10006 state->num_private_objs = j;
10007 break;
10008 }
bd200d19 10009 }
e7b07cee
HW		 10010 }
10011
caff0e66
NK		 10012 /* Store the overall update type for use later in atomic check. */
10013 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10014 struct dm_crtc_state *dm_new_crtc_state =
10015 to_dm_crtc_state(new_crtc_state);
10016
f6d7c7fa
NK		 10017 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10018 UPDATE_TYPE_FULL :
10019 UPDATE_TYPE_FAST;
e7b07cee
HW		 10020 }
10021
10022 /* Must be success */
10023 WARN_ON(ret);
e8a98235
RS		 10024
10025 trace_amdgpu_dm_atomic_check_finish(state, ret);
10026
e7b07cee
HW		 10027 return ret;
10028
10029fail:
10030 if (ret == -EDEADLK)
01e28f9c 10031 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 10032 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 10033 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 10034 else
01e28f9c 10035 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee 10036
e8a98235
RS		 10037 trace_amdgpu_dm_atomic_check_finish(state, ret);
10038
e7b07cee
HW		 10039 return ret;
10040}
10041
3ee6b26b
AD		 10042static bool is_dp_capable_without_timing_msa(struct dc *dc,
10043 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee 10044{
ae67558b 10045 u8 dpcd_data;
e7b07cee
HW		 10046 bool capable = false;
10047
c84dec2f 10048 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 10049 dm_helpers_dp_read_dpcd(
10050 NULL,
c84dec2f 10051 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 10052 DP_DOWN_STREAM_PORT_COUNT,
10053 &dpcd_data,
10054 sizeof(dpcd_data))) {
10055 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10056 }
10057
10058 return capable;
10059}
f9b4f20c 10060
46db138d
SW		 10061static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10062 unsigned int offset,
10063 unsigned int total_length,
ae67558b 10064 u8 *data,
46db138d
SW		 10065 unsigned int length,
10066 struct amdgpu_hdmi_vsdb_info *vsdb)
10067{
10068 bool res;
10069 union dmub_rb_cmd cmd;
10070 struct dmub_cmd_send_edid_cea *input;
10071 struct dmub_cmd_edid_cea_output *output;
10072
10073 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10074 return false;
10075
10076 memset(&cmd, 0, sizeof(cmd));
10077
10078 input = &cmd.edid_cea.data.input;
10079
10080 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10081 cmd.edid_cea.header.sub_type = 0;
10082 cmd.edid_cea.header.payload_bytes =
10083 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10084 input->offset = offset;
10085 input->length = length;
eb9e59eb 10086 input->cea_total_length = total_length;
46db138d
SW		 10087 memcpy(input->payload, data, length);
10088
10089 res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10090 if (!res) {
10091 DRM_ERROR("EDID CEA parser failed\n");
10092 return false;
10093 }
10094
10095 output = &cmd.edid_cea.data.output;
10096
10097 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10098 if (!output->ack.success) {
10099 DRM_ERROR("EDID CEA ack failed at offset %d\n",
10100 output->ack.offset);
10101 }
10102 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10103 if (!output->amd_vsdb.vsdb_found)
10104 return false;
10105
10106 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10107 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10108 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10109 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10110 } else {
b76a8062 10111 DRM_WARN("Unknown EDID CEA parser results\n");
46db138d
SW		 10112 return false;
10113 }
10114
10115 return true;
10116}
10117
10118static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
ae67558b 10119 u8 *edid_ext, int len,
f9b4f20c
SW		 10120 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10121{
10122 int i;
f9b4f20c
SW		 10123
10124 /* send extension block to DMCU for parsing */
10125 for (i = 0; i < len; i += 8) {
10126 bool res;
10127 int offset;
10128
10129 /* send 8 bytes a time */
46db138d 10130 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
f9b4f20c
SW		 10131 return false;
10132
10133 if (i+8 == len) {
10134 /* EDID block sent completed, expect result */
10135 int version, min_rate, max_rate;
10136
46db138d 10137 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
f9b4f20c
SW		 10138 if (res) {
10139 /* amd vsdb found */
10140 vsdb_info->freesync_supported = 1;
10141 vsdb_info->amd_vsdb_version = version;
10142 vsdb_info->min_refresh_rate_hz = min_rate;
10143 vsdb_info->max_refresh_rate_hz = max_rate;
10144 return true;
10145 }
10146 /* not amd vsdb */
10147 return false;
10148 }
10149
10150 /* check for ack*/
46db138d 10151 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
f9b4f20c
SW		 10152 if (!res)
10153 return false;
10154 }
10155
10156 return false;
10157}
10158
46db138d 10159static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
ae67558b 10160 u8 *edid_ext, int len,
46db138d
SW		 10161 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10162{
10163 int i;
10164
10165 /* send extension block to DMCU for parsing */
10166 for (i = 0; i < len; i += 8) {
10167 /* send 8 bytes a time */
10168 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10169 return false;
10170 }
10171
10172 return vsdb_info->freesync_supported;
10173}
10174
10175static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
ae67558b 10176 u8 *edid_ext, int len,
46db138d
SW		 10177 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10178{
10179 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10180
10181 if (adev->dm.dmub_srv)
10182 return parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10183 else
10184 return parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10185}
10186
7c7dd774 10187static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
f9b4f20c
SW		 10188 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10189{
ae67558b 10190 u8 *edid_ext = NULL;
f9b4f20c
SW		 10191 int i;
10192 bool valid_vsdb_found = false;
10193
10194 /*----- drm_find_cea_extension() -----*/
10195 /* No EDID or EDID extensions */
10196 if (edid == NULL || edid->extensions == 0)
7c7dd774 10197 return -ENODEV;
f9b4f20c
SW		 10198
10199 /* Find CEA extension */
10200 for (i = 0; i < edid->extensions; i++) {
10201 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10202 if (edid_ext[0] == CEA_EXT)
10203 break;
10204 }
10205
10206 if (i == edid->extensions)
7c7dd774 10207 return -ENODEV;
f9b4f20c
SW		 10208
10209 /*----- cea_db_offsets() -----*/
10210 if (edid_ext[0] != CEA_EXT)
7c7dd774 10211 return -ENODEV;
f9b4f20c
SW		 10212
10213 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
7c7dd774
AB		 10214
10215 return valid_vsdb_found ? i : -ENODEV;
f9b4f20c
SW		 10216}
10217
c620e79b
RS		 10218/**
10219 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10220 *
41ee1f18
AD		 10221 * @connector: Connector to query.
10222 * @edid: EDID from monitor
c620e79b
RS		 10223 *
10224 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10225 * track of some of the display information in the internal data struct used by
10226 * amdgpu_dm. This function checks which type of connector we need to set the
10227 * FreeSync parameters.
10228 */
98e6436d 10229void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
c620e79b 10230 struct edid *edid)
e7b07cee 10231{
eb0709ba 10232 int i = 0;
e7b07cee
HW		 10233 struct detailed_timing *timing;
10234 struct detailed_non_pixel *data;
10235 struct detailed_data_monitor_range *range;
c84dec2f
HW		 10236 struct amdgpu_dm_connector *amdgpu_dm_connector =
10237 to_amdgpu_dm_connector(connector);
bb47de73 10238 struct dm_connector_state *dm_con_state = NULL;
9ad54467 10239 struct dc_sink *sink;
e7b07cee
HW		 10240
10241 struct drm_device *dev = connector->dev;
1348969a 10242 struct amdgpu_device *adev = drm_to_adev(dev);
f9b4f20c 10243 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
c620e79b 10244 bool freesync_capable = false;
b830ebc9 10245
8218d7f1
HW		 10246 if (!connector->state) {
10247 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 10248 goto update;
8218d7f1
HW		 10249 }
10250
9b2fdc33
AP		 10251 sink = amdgpu_dm_connector->dc_sink ?
10252 amdgpu_dm_connector->dc_sink :
10253 amdgpu_dm_connector->dc_em_sink;
10254
10255 if (!edid || !sink) {
98e6436d
AK		 10256 dm_con_state = to_dm_connector_state(connector->state);
10257
10258 amdgpu_dm_connector->min_vfreq = 0;
10259 amdgpu_dm_connector->max_vfreq = 0;
10260 amdgpu_dm_connector->pixel_clock_mhz = 0;
9b2fdc33
AP		 10261 connector->display_info.monitor_range.min_vfreq = 0;
10262 connector->display_info.monitor_range.max_vfreq = 0;
10263 freesync_capable = false;
98e6436d 10264
bb47de73 10265 goto update;
98e6436d
AK		 10266 }
10267
8218d7f1
HW		 10268 dm_con_state = to_dm_connector_state(connector->state);
10269
e7b07cee 10270 if (!adev->dm.freesync_module)
bb47de73 10271 goto update;
f9b4f20c 10272
9b2fdc33
AP		 10273 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10274 || sink->sink_signal == SIGNAL_TYPE_EDP) {
f9b4f20c
SW		 10275 bool edid_check_required = false;
10276
10277 if (edid) {
e7b07cee
HW		 10278 edid_check_required = is_dp_capable_without_timing_msa(
10279 adev->dm.dc,
c84dec2f 10280 amdgpu_dm_connector);
e7b07cee 10281 }
e7b07cee 10282
f9b4f20c
SW		 10283 if (edid_check_required == true && (edid->version > 1 ||
10284 (edid->version == 1 && edid->revision > 1))) {
10285 for (i = 0; i < 4; i++) {
e7b07cee 10286
f9b4f20c
SW		 10287 timing = &edid->detailed_timings[i];
10288 data = &timing->data.other_data;
10289 range = &data->data.range;
10290 /*
10291 * Check if monitor has continuous frequency mode
10292 */
10293 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10294 continue;
10295 /*
10296 * Check for flag range limits only. If flag == 1 then
10297 * no additional timing information provided.
10298 * Default GTF, GTF Secondary curve and CVT are not
10299 * supported
10300 */
10301 if (range->flags != 1)
10302 continue;
a0ffc3fd 10303
f9b4f20c
SW		 10304 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10305 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10306 amdgpu_dm_connector->pixel_clock_mhz =
10307 range->pixel_clock_mhz * 10;
a0ffc3fd 10308
f9b4f20c
SW		 10309 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10310 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
e7b07cee 10311
f9b4f20c
SW		 10312 break;
10313 }
98e6436d 10314
f9b4f20c
SW		 10315 if (amdgpu_dm_connector->max_vfreq -
10316 amdgpu_dm_connector->min_vfreq > 10) {
98e6436d 10317
f9b4f20c
SW		 10318 freesync_capable = true;
10319 }
10320 }
9b2fdc33 10321 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
7c7dd774
AB		 10322 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10323 if (i >= 0 && vsdb_info.freesync_supported) {
f9b4f20c
SW		 10324 timing = &edid->detailed_timings[i];
10325 data = &timing->data.other_data;
10326
10327 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10328 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10329 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10330 freesync_capable = true;
10331
10332 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10333 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
e7b07cee
HW		 10334 }
10335 }
bb47de73
NK		 10336
10337update:
10338 if (dm_con_state)
10339 dm_con_state->freesync_capable = freesync_capable;
10340
10341 if (connector->vrr_capable_property)
10342 drm_connector_set_vrr_capable_property(connector,
10343 freesync_capable);
e7b07cee
HW		 10344}
10345
3d4e52d0
VL		 10346void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10347{
1348969a 10348 struct amdgpu_device *adev = drm_to_adev(dev);
3d4e52d0
VL		 10349 struct dc *dc = adev->dm.dc;
10350 int i;
10351
10352 mutex_lock(&adev->dm.dc_lock);
10353 if (dc->current_state) {
10354 for (i = 0; i < dc->current_state->stream_count; ++i)
10355 dc->current_state->streams[i]
10356 ->triggered_crtc_reset.enabled =
10357 adev->dm.force_timing_sync;
10358
10359 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10360 dc_trigger_sync(dc, dc->current_state);
10361 }
10362 mutex_unlock(&adev->dm.dc_lock);
10363}
9d83722d
RS		 10364
10365void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
ae67558b 10366 u32 value, const char *func_name)
9d83722d
RS		 10367{
10368#ifdef DM_CHECK_ADDR_0
10369 if (address == 0) {
10370 DC_ERR("invalid register write. address = 0");
10371 return;
10372 }
10373#endif
10374 cgs_write_register(ctx->cgs_device, address, value);
10375 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10376}
10377
10378uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10379 const char *func_name)
10380{
ae67558b 10381 u32 value;
9d83722d
RS		 10382#ifdef DM_CHECK_ADDR_0
10383 if (address == 0) {
10384 DC_ERR("invalid register read; address = 0\n");
10385 return 0;
10386 }
10387#endif
10388
10389 if (ctx->dmub_srv &&
10390 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10391 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10392 ASSERT(false);
10393 return 0;
10394 }
10395
10396 value = cgs_read_register(ctx->cgs_device, address);
10397
10398 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10399
10400 return value;
10401}
81927e28 10402
ead08b95
SW		 10403int amdgpu_dm_process_dmub_aux_transfer_sync(
10404 struct dc_context *ctx,
10405 unsigned int link_index,
10406 struct aux_payload *payload,
10407 enum aux_return_code_type *operation_result)
88f52b1f
JS		 10408{
10409 struct amdgpu_device *adev = ctx->driver_context;
88f52b1f 10410 struct dmub_notification *p_notify = adev->dm.dmub_notify;
ead08b95 10411 int ret = -1;
88f52b1f 10412
ead08b95
SW		 10413 mutex_lock(&adev->dm.dpia_aux_lock);
10414 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10415 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10416 goto out;
10417 }
10418
10419 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10420 DRM_ERROR("wait_for_completion_timeout timeout!");
10421 *operation_result = AUX_RET_ERROR_TIMEOUT;
10422 goto out;
10423 }
10424
10425 if (p_notify->result != AUX_RET_SUCCESS) {
10426 /*
10427 * Transient states before tunneling is enabled could
10428 * lead to this error. We can ignore this for now.
10429 */
10430 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10431 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10432 payload->address, payload->length,
10433 p_notify->result);
88f52b1f 10434 }
ead08b95
SW		 10435 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10436 goto out;
10437 }
10438
10439
10440 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10441 if (!payload->write && p_notify->aux_reply.length &&
10442 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10443
10444 if (payload->length != p_notify->aux_reply.length) {
10445 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10446 p_notify->aux_reply.length,
10447 payload->address, payload->length);
10448 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10449 goto out;
88f52b1f 10450 }
ead08b95
SW		 10451
10452 memcpy(payload->data, p_notify->aux_reply.data,
10453 p_notify->aux_reply.length);
88f52b1f
JS		 10454 }
10455
ead08b95
SW		 10456 /* success */
10457 ret = p_notify->aux_reply.length;
10458 *operation_result = p_notify->result;
10459out:
10460 mutex_unlock(&adev->dm.dpia_aux_lock);
10461 return ret;
88f52b1f
JS		 10462}
10463
ead08b95
SW		 10464int amdgpu_dm_process_dmub_set_config_sync(
10465 struct dc_context *ctx,
10466 unsigned int link_index,
10467 struct set_config_cmd_payload *payload,
10468 enum set_config_status *operation_result)
81927e28
JS		 10469{
10470 struct amdgpu_device *adev = ctx->driver_context;
ead08b95
SW		 10471 bool is_cmd_complete;
10472 int ret;
81927e28 10473
ead08b95
SW		 10474 mutex_lock(&adev->dm.dpia_aux_lock);
10475 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10476 link_index, payload, adev->dm.dmub_notify);
88f52b1f 10477
ead08b95
SW		 10478 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10479 ret = 0;
10480 *operation_result = adev->dm.dmub_notify->sc_status;
10481 } else {
9e3a50d2 10482 DRM_ERROR("wait_for_completion_timeout timeout!");
ead08b95
SW		 10483 ret = -1;
10484 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
81927e28
JS		 10485 }
10486
ead08b95
SW		 10487 mutex_unlock(&adev->dm.dpia_aux_lock);
10488 return ret;
81927e28 10489}
1edf5ae1
ZL		 10490
10491/*
10492 * Check whether seamless boot is supported.
10493 *
10494 * So far we only support seamless boot on CHIP_VANGOGH.
10495 * If everything goes well, we may consider expanding
10496 * seamless boot to other ASICs.
10497 */
10498bool check_seamless_boot_capability(struct amdgpu_device *adev)
10499{
20875141
PY		 10500 switch (adev->ip_versions[DCE_HWIP][0]) {
10501 case IP_VERSION(3, 0, 1):
1edf5ae1
ZL		 10502 if (!adev->mman.keep_stolen_vga_memory)
10503 return true;
10504 break;
10505 default:
10506 break;
10507 }
10508
10509 return false;
10510}
Linux 6.x block layer and io_uring tree(s)