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drm/amd/display: Detach backlight from stream
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
1dc90497 31#include "dc/inc/core_types.h"
4562236b
HW		 32
33#include "vid.h"
34#include "amdgpu.h"
a49dcb88 35#include "amdgpu_display.h"
a94d5569 36#include "amdgpu_ucode.h"
4562236b
HW		 37#include "atom.h"
38#include "amdgpu_dm.h"
e7b07cee 39#include "amdgpu_pm.h"
4562236b
HW		 40
41#include "amd_shared.h"
42#include "amdgpu_dm_irq.h"
43#include "dm_helpers.h"
e7b07cee 44#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 45#if defined(CONFIG_DEBUG_FS)
46#include "amdgpu_dm_debugfs.h"
47#endif
4562236b
HW		 48
49#include "ivsrcid/ivsrcid_vislands30.h"
50
51#include <linux/module.h>
52#include <linux/moduleparam.h>
53#include <linux/version.h>
e7b07cee 54#include <linux/types.h>
97028037 55#include <linux/pm_runtime.h>
a94d5569 56#include <linux/firmware.h>
4562236b 57
e7b07cee 58#include <drm/drmP.h>
4562236b 59#include <drm/drm_atomic.h>
674e78ac 60#include <drm/drm_atomic_uapi.h>
4562236b
HW		 61#include <drm/drm_atomic_helper.h>
62#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 63#include <drm/drm_fb_helper.h>
64#include <drm/drm_edid.h>
4562236b 65
ff5ef992
AD		 66#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
67#include "ivsrcid/irqsrcs_dcn_1_0.h"
68
ad941f7a
FX		 69#include "dcn/dcn_1_0_offset.h"
70#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 71#include "soc15_hw_ip.h"
72#include "vega10_ip_offset.h"
ff5ef992
AD		 73
74#include "soc15_common.h"
75#endif
76
e7b07cee 77#include "modules/inc/mod_freesync.h"
bbf854dc 78#include "modules/power/power_helpers.h"
ecd0136b 79#include "modules/inc/mod_info_packet.h"
e7b07cee 80
a94d5569
DF		 81#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
82MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 83
b8592b48
LL		 84/**
85 * DOC: overview
86 *
87 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
88 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
89 * requests into DC requests, and DC responses into DRM responses.
90 *
91 * The root control structure is &struct amdgpu_display_manager.
92 */
93
7578ecda
AD		 94/* basic init/fini API */
95static int amdgpu_dm_init(struct amdgpu_device *adev);
96static void amdgpu_dm_fini(struct amdgpu_device *adev);
97
1f6010a9
DF		 98/*
99 * initializes drm_device display related structures, based on the information
7578ecda
AD		 100 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
101 * drm_encoder, drm_mode_config
102 *
103 * Returns 0 on success
104 */
105static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
106/* removes and deallocates the drm structures, created by the above function */
107static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
108
109static void
110amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
111
112static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 113 struct drm_plane *plane,
7578ecda
AD		 114 unsigned long possible_crtcs);
115static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
116 struct drm_plane *plane,
117 uint32_t link_index);
118static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
119 struct amdgpu_dm_connector *amdgpu_dm_connector,
120 uint32_t link_index,
121 struct amdgpu_encoder *amdgpu_encoder);
122static int amdgpu_dm_encoder_init(struct drm_device *dev,
123 struct amdgpu_encoder *aencoder,
124 uint32_t link_index);
125
126static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
127
128static int amdgpu_dm_atomic_commit(struct drm_device *dev,
129 struct drm_atomic_state *state,
130 bool nonblock);
131
132static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
133
134static int amdgpu_dm_atomic_check(struct drm_device *dev,
135 struct drm_atomic_state *state);
136
674e78ac
NK		 137static void handle_cursor_update(struct drm_plane *plane,
138 struct drm_plane_state *old_plane_state);
7578ecda
AD		 139
140
e7b07cee 141
e04a6123 142static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 143 DRM_PLANE_TYPE_PRIMARY,
144 DRM_PLANE_TYPE_PRIMARY,
145 DRM_PLANE_TYPE_PRIMARY,
146 DRM_PLANE_TYPE_PRIMARY,
147 DRM_PLANE_TYPE_PRIMARY,
148 DRM_PLANE_TYPE_PRIMARY,
149};
150
e04a6123 151static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 152 DRM_PLANE_TYPE_PRIMARY,
153 DRM_PLANE_TYPE_PRIMARY,
154 DRM_PLANE_TYPE_PRIMARY,
155 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
156};
157
e04a6123 158static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 159 DRM_PLANE_TYPE_PRIMARY,
160 DRM_PLANE_TYPE_PRIMARY,
161 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
162};
163
4562236b
HW		 164/*
165 * dm_vblank_get_counter
166 *
167 * @brief
168 * Get counter for number of vertical blanks
169 *
170 * @param
171 * struct amdgpu_device *adev - [in] desired amdgpu device
172 * int disp_idx - [in] which CRTC to get the counter from
173 *
174 * @return
175 * Counter for vertical blanks
176 */
177static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
178{
179 if (crtc >= adev->mode_info.num_crtc)
180 return 0;
181 else {
182 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 183 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
184 acrtc->base.state);
4562236b 185
da5c47f6
AG		 186
187 if (acrtc_state->stream == NULL) {
0971c40e
HW		 188 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
189 crtc);
4562236b
HW		 190 return 0;
191 }
192
da5c47f6 193 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 194 }
195}
196
197static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 198 u32 *vbl, u32 *position)
4562236b 199{
81c50963
ST		 200 uint32_t v_blank_start, v_blank_end, h_position, v_position;
201
4562236b
HW		 202 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
203 return -EINVAL;
204 else {
205 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 206 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
207 acrtc->base.state);
4562236b 208
da5c47f6 209 if (acrtc_state->stream == NULL) {
0971c40e
HW		 210 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
211 crtc);
4562236b
HW		 212 return 0;
213 }
214
81c50963
ST		 215 /*
216 * TODO rework base driver to use values directly.
217 * for now parse it back into reg-format
218 */
da5c47f6 219 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 220 &v_blank_start,
221 &v_blank_end,
222 &h_position,
223 &v_position);
224
e806208d
AG		 225 *position = v_position | (h_position << 16);
226 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 227 }
228
229 return 0;
230}
231
232static bool dm_is_idle(void *handle)
233{
234 /* XXX todo */
235 return true;
236}
237
238static int dm_wait_for_idle(void *handle)
239{
240 /* XXX todo */
241 return 0;
242}
243
244static bool dm_check_soft_reset(void *handle)
245{
246 return false;
247}
248
249static int dm_soft_reset(void *handle)
250{
251 /* XXX todo */
252 return 0;
253}
254
3ee6b26b
AD		 255static struct amdgpu_crtc *
256get_crtc_by_otg_inst(struct amdgpu_device *adev,
257 int otg_inst)
4562236b
HW		 258{
259 struct drm_device *dev = adev->ddev;
260 struct drm_crtc *crtc;
261 struct amdgpu_crtc *amdgpu_crtc;
262
4562236b
HW		 263 if (otg_inst == -1) {
264 WARN_ON(1);
265 return adev->mode_info.crtcs[0];
266 }
267
268 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
269 amdgpu_crtc = to_amdgpu_crtc(crtc);
270
271 if (amdgpu_crtc->otg_inst == otg_inst)
272 return amdgpu_crtc;
273 }
274
275 return NULL;
276}
277
278static void dm_pflip_high_irq(void *interrupt_params)
279{
4562236b
HW		 280 struct amdgpu_crtc *amdgpu_crtc;
281 struct common_irq_params *irq_params = interrupt_params;
282 struct amdgpu_device *adev = irq_params->adev;
283 unsigned long flags;
284
285 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
286
287 /* IRQ could occur when in initial stage */
1f6010a9 288 /* TODO work and BO cleanup */
4562236b
HW		 289 if (amdgpu_crtc == NULL) {
290 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
291 return;
292 }
293
294 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 295
296 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
297 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
298 amdgpu_crtc->pflip_status,
299 AMDGPU_FLIP_SUBMITTED,
300 amdgpu_crtc->crtc_id,
301 amdgpu_crtc);
302 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
303 return;
304 }
305
4562236b 306
1f6010a9 307 /* wake up userspace */
1159898a 308 if (amdgpu_crtc->event) {
1f6010a9 309 /* Update to correct count(s) if racing with vblank irq */
753c66c9
MK		 310 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
311
54f5499a 312 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 313
54f5499a
AG		 314 /* page flip completed. clean up */
315 amdgpu_crtc->event = NULL;
1159898a 316
54f5499a
AG		 317 } else
318 WARN_ON(1);
4562236b 319
54f5499a 320 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 321 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
322
54f5499a
AG		 323 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
324 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 325
326 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 327}
328
329static void dm_crtc_high_irq(void *interrupt_params)
330{
331 struct common_irq_params *irq_params = interrupt_params;
332 struct amdgpu_device *adev = irq_params->adev;
4562236b 333 struct amdgpu_crtc *acrtc;
180db303 334 struct dm_crtc_state *acrtc_state;
4562236b 335
b57de80a 336 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 337
e5d0170e
LSL		 338 if (acrtc) {
339 drm_crtc_handle_vblank(&acrtc->base);
340 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
180db303
NK		 341
342 acrtc_state = to_dm_crtc_state(acrtc->base.state);
343
344 if (acrtc_state->stream &&
345 acrtc_state->vrr_params.supported &&
346 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
347 mod_freesync_handle_v_update(
348 adev->dm.freesync_module,
349 acrtc_state->stream,
350 &acrtc_state->vrr_params);
351
352 dc_stream_adjust_vmin_vmax(
353 adev->dm.dc,
354 acrtc_state->stream,
355 &acrtc_state->vrr_params.adjust);
356 }
e5d0170e 357 }
4562236b
HW		 358}
359
360static int dm_set_clockgating_state(void *handle,
361 enum amd_clockgating_state state)
362{
363 return 0;
364}
365
366static int dm_set_powergating_state(void *handle,
367 enum amd_powergating_state state)
368{
369 return 0;
370}
371
372/* Prototypes of private functions */
373static int dm_early_init(void* handle);
374
a32e24b4 375/* Allocate memory for FBC compressed data */
3e332d3a 376static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 377{
3e332d3a
RL		 378 struct drm_device *dev = connector->dev;
379 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 380 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 381 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
382 struct drm_display_mode *mode;
42e67c3b
RL		 383 unsigned long max_size = 0;
384
385 if (adev->dm.dc->fbc_compressor == NULL)
386 return;
a32e24b4 387
3e332d3a 388 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 389 return;
390
3e332d3a
RL		 391 if (compressor->bo_ptr)
392 return;
42e67c3b 393
42e67c3b 394
3e332d3a
RL		 395 list_for_each_entry(mode, &connector->modes, head) {
396 if (max_size < mode->htotal * mode->vtotal)
397 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 398 }
399
400 if (max_size) {
401 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 402 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 403 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 404
405 if (r)
42e67c3b
RL		 406 DRM_ERROR("DM: Failed to initialize FBC\n");
407 else {
408 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
409 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
410 }
411
a32e24b4
RL		 412 }
413
414}
a32e24b4 415
7578ecda 416static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 417{
418 struct dc_init_data init_data;
419 adev->dm.ddev = adev->ddev;
420 adev->dm.adev = adev;
421
4562236b
HW		 422 /* Zero all the fields */
423 memset(&init_data, 0, sizeof(init_data));
424
674e78ac
NK		 425 mutex_init(&adev->dm.dc_lock);
426
4562236b
HW		 427 if(amdgpu_dm_irq_init(adev)) {
428 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
429 goto error;
430 }
431
432 init_data.asic_id.chip_family = adev->family;
433
434 init_data.asic_id.pci_revision_id = adev->rev_id;
435 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
436
770d13b1 437 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 438 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
439 init_data.asic_id.atombios_base_address =
440 adev->mode_info.atom_context->bios;
441
442 init_data.driver = adev;
443
444 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
445
446 if (!adev->dm.cgs_device) {
447 DRM_ERROR("amdgpu: failed to create cgs device.\n");
448 goto error;
449 }
450
451 init_data.cgs_device = adev->dm.cgs_device;
452
4562236b
HW		 453 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
454
6e227308
HW		 455 /*
456 * TODO debug why this doesn't work on Raven
457 */
458 if (adev->flags & AMD_IS_APU &&
459 adev->asic_type >= CHIP_CARRIZO &&
460 adev->asic_type < CHIP_RAVEN)
461 init_data.flags.gpu_vm_support = true;
462
04b94af4
AD		 463 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
464 init_data.flags.fbc_support = true;
465
4562236b
HW		 466 /* Display Core create. */
467 adev->dm.dc = dc_create(&init_data);
468
423788c7 469 if (adev->dm.dc) {
76121231 470 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 471 } else {
76121231 472 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 473 goto error;
474 }
4562236b 475
4562236b
HW		 476 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
477 if (!adev->dm.freesync_module) {
478 DRM_ERROR(
479 "amdgpu: failed to initialize freesync_module.\n");
480 } else
f1ad2f5e 481 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 482 adev->dm.freesync_module);
483
e277adc5
LSL		 484 amdgpu_dm_init_color_mod();
485
4562236b
HW		 486 if (amdgpu_dm_initialize_drm_device(adev)) {
487 DRM_ERROR(
488 "amdgpu: failed to initialize sw for display support.\n");
489 goto error;
490 }
491
492 /* Update the actual used number of crtc */
493 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
494
495 /* TODO: Add_display_info? */
496
497 /* TODO use dynamic cursor width */
ce75805e
AG		 498 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
499 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 500
501 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
502 DRM_ERROR(
503 "amdgpu: failed to initialize sw for display support.\n");
504 goto error;
505 }
506
e498eb71
NK		 507#if defined(CONFIG_DEBUG_FS)
508 if (dtn_debugfs_init(adev))
509 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
510#endif
511
f1ad2f5e 512 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 513
514 return 0;
515error:
516 amdgpu_dm_fini(adev);
517
59d0f396 518 return -EINVAL;
4562236b
HW		 519}
520
7578ecda 521static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 522{
523 amdgpu_dm_destroy_drm_device(&adev->dm);
524 /*
525 * TODO: pageflip, vlank interrupt
526 *
527 * amdgpu_dm_irq_fini(adev);
528 */
529
530 if (adev->dm.cgs_device) {
531 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
532 adev->dm.cgs_device = NULL;
533 }
534 if (adev->dm.freesync_module) {
535 mod_freesync_destroy(adev->dm.freesync_module);
536 adev->dm.freesync_module = NULL;
537 }
538 /* DC Destroy TODO: Replace destroy DAL */
21de3396 539 if (adev->dm.dc)
4562236b 540 dc_destroy(&adev->dm.dc);
674e78ac
NK		 541
542 mutex_destroy(&adev->dm.dc_lock);
543
4562236b
HW		 544 return;
545}
546
a94d5569 547static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 548{
a94d5569
DF		 549 const char *fw_name_dmcu;
550 int r;
551 const struct dmcu_firmware_header_v1_0 *hdr;
552
553 switch(adev->asic_type) {
554 case CHIP_BONAIRE:
555 case CHIP_HAWAII:
556 case CHIP_KAVERI:
557 case CHIP_KABINI:
558 case CHIP_MULLINS:
559 case CHIP_TONGA:
560 case CHIP_FIJI:
561 case CHIP_CARRIZO:
562 case CHIP_STONEY:
563 case CHIP_POLARIS11:
564 case CHIP_POLARIS10:
565 case CHIP_POLARIS12:
566 case CHIP_VEGAM:
567 case CHIP_VEGA10:
568 case CHIP_VEGA12:
569 case CHIP_VEGA20:
570 return 0;
571 case CHIP_RAVEN:
572 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
573 break;
574 default:
575 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 576 return -EINVAL;
a94d5569
DF		 577 }
578
579 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
580 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
581 return 0;
582 }
583
584 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
585 if (r == -ENOENT) {
586 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
587 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
588 adev->dm.fw_dmcu = NULL;
589 return 0;
590 }
591 if (r) {
592 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
593 fw_name_dmcu);
594 return r;
595 }
596
597 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
598 if (r) {
599 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
600 fw_name_dmcu);
601 release_firmware(adev->dm.fw_dmcu);
602 adev->dm.fw_dmcu = NULL;
603 return r;
604 }
605
606 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
607 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
608 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
609 adev->firmware.fw_size +=
610 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
611
612 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
613 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
614 adev->firmware.fw_size +=
615 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
616
ee6e89c0
DF		 617 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
618
a94d5569
DF		 619 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
620
4562236b
HW		 621 return 0;
622}
623
a94d5569
DF		 624static int dm_sw_init(void *handle)
625{
626 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
627
628 return load_dmcu_fw(adev);
629}
630
4562236b
HW		 631static int dm_sw_fini(void *handle)
632{
a94d5569
DF		 633 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
634
635 if(adev->dm.fw_dmcu) {
636 release_firmware(adev->dm.fw_dmcu);
637 adev->dm.fw_dmcu = NULL;
638 }
639
4562236b
HW		 640 return 0;
641}
642
7abcf6b5 643static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 644{
c84dec2f 645 struct amdgpu_dm_connector *aconnector;
4562236b 646 struct drm_connector *connector;
7abcf6b5 647 int ret = 0;
4562236b
HW		 648
649 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
650
651 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 652 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 653 if (aconnector->dc_link->type == dc_connection_mst_branch &&
654 aconnector->mst_mgr.aux) {
f1ad2f5e 655 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 656 aconnector, aconnector->base.base.id);
657
658 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
659 if (ret < 0) {
660 DRM_ERROR("DM_MST: Failed to start MST\n");
661 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
662 return ret;
4562236b 663 }
7abcf6b5 664 }
4562236b
HW		 665 }
666
667 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 668 return ret;
669}
670
671static int dm_late_init(void *handle)
672{
42e67c3b 673 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 674
bbf854dc
DF		 675 struct dmcu_iram_parameters params;
676 unsigned int linear_lut[16];
677 int i;
678 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
679 bool ret;
680
681 for (i = 0; i < 16; i++)
682 linear_lut[i] = 0xFFFF * i / 15;
683
684 params.set = 0;
685 params.backlight_ramping_start = 0xCCCC;
686 params.backlight_ramping_reduction = 0xCCCCCCCC;
687 params.backlight_lut_array_size = 16;
688 params.backlight_lut_array = linear_lut;
689
690 ret = dmcu_load_iram(dmcu, params);
691
692 if (!ret)
693 return -EINVAL;
694
42e67c3b 695 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 696}
697
698static void s3_handle_mst(struct drm_device *dev, bool suspend)
699{
c84dec2f 700 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 701 struct drm_connector *connector;
702
703 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
704
705 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 706 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 707 if (aconnector->dc_link->type == dc_connection_mst_branch &&
708 !aconnector->mst_port) {
709
710 if (suspend)
711 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
712 else
713 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
714 }
715 }
716
717 drm_modeset_unlock(&dev->mode_config.connection_mutex);
718}
719
b8592b48
LL		 720/**
721 * dm_hw_init() - Initialize DC device
722 * @handle: The base driver device containing the amdpgu_dm device.
723 *
724 * Initialize the &struct amdgpu_display_manager device. This involves calling
725 * the initializers of each DM component, then populating the struct with them.
726 *
727 * Although the function implies hardware initialization, both hardware and
728 * software are initialized here. Splitting them out to their relevant init
729 * hooks is a future TODO item.
730 *
731 * Some notable things that are initialized here:
732 *
733 * - Display Core, both software and hardware
734 * - DC modules that we need (freesync and color management)
735 * - DRM software states
736 * - Interrupt sources and handlers
737 * - Vblank support
738 * - Debug FS entries, if enabled
739 */
4562236b
HW		 740static int dm_hw_init(void *handle)
741{
742 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
743 /* Create DAL display manager */
744 amdgpu_dm_init(adev);
4562236b
HW		 745 amdgpu_dm_hpd_init(adev);
746
4562236b
HW		 747 return 0;
748}
749
b8592b48
LL		 750/**
751 * dm_hw_fini() - Teardown DC device
752 * @handle: The base driver device containing the amdpgu_dm device.
753 *
754 * Teardown components within &struct amdgpu_display_manager that require
755 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
756 * were loaded. Also flush IRQ workqueues and disable them.
757 */
4562236b
HW		 758static int dm_hw_fini(void *handle)
759{
760 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
761
762 amdgpu_dm_hpd_fini(adev);
763
764 amdgpu_dm_irq_fini(adev);
21de3396 765 amdgpu_dm_fini(adev);
4562236b
HW		 766 return 0;
767}
768
769static int dm_suspend(void *handle)
770{
771 struct amdgpu_device *adev = handle;
772 struct amdgpu_display_manager *dm = &adev->dm;
773 int ret = 0;
4562236b
HW		 774
775 s3_handle_mst(adev->ddev, true);
776
4562236b
HW		 777 amdgpu_dm_irq_suspend(adev);
778
0a214e2f 779 WARN_ON(adev->dm.cached_state);
a3621485
AG		 780 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
781
32f5062d 782 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 783
784 return ret;
785}
786
1daf8c63
AD		 787static struct amdgpu_dm_connector *
788amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
789 struct drm_crtc *crtc)
4562236b
HW		 790{
791 uint32_t i;
c2cea706 792 struct drm_connector_state *new_con_state;
4562236b
HW		 793 struct drm_connector *connector;
794 struct drm_crtc *crtc_from_state;
795
c2cea706
LSL		 796 for_each_new_connector_in_state(state, connector, new_con_state, i) {
797 crtc_from_state = new_con_state->crtc;
4562236b
HW		 798
799 if (crtc_from_state == crtc)
c84dec2f 800 return to_amdgpu_dm_connector(connector);
4562236b
HW		 801 }
802
803 return NULL;
804}
805
fbbdadf2
BL		 806static void emulated_link_detect(struct dc_link *link)
807{
808 struct dc_sink_init_data sink_init_data = { 0 };
809 struct display_sink_capability sink_caps = { 0 };
810 enum dc_edid_status edid_status;
811 struct dc_context *dc_ctx = link->ctx;
812 struct dc_sink *sink = NULL;
813 struct dc_sink *prev_sink = NULL;
814
815 link->type = dc_connection_none;
816 prev_sink = link->local_sink;
817
818 if (prev_sink != NULL)
819 dc_sink_retain(prev_sink);
820
821 switch (link->connector_signal) {
822 case SIGNAL_TYPE_HDMI_TYPE_A: {
823 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
824 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
825 break;
826 }
827
828 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
829 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
830 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
831 break;
832 }
833
834 case SIGNAL_TYPE_DVI_DUAL_LINK: {
835 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
836 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
837 break;
838 }
839
840 case SIGNAL_TYPE_LVDS: {
841 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
842 sink_caps.signal = SIGNAL_TYPE_LVDS;
843 break;
844 }
845
846 case SIGNAL_TYPE_EDP: {
847 sink_caps.transaction_type =
848 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
849 sink_caps.signal = SIGNAL_TYPE_EDP;
850 break;
851 }
852
853 case SIGNAL_TYPE_DISPLAY_PORT: {
854 sink_caps.transaction_type =
855 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
856 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
857 break;
858 }
859
860 default:
861 DC_ERROR("Invalid connector type! signal:%d\n",
862 link->connector_signal);
863 return;
864 }
865
866 sink_init_data.link = link;
867 sink_init_data.sink_signal = sink_caps.signal;
868
869 sink = dc_sink_create(&sink_init_data);
870 if (!sink) {
871 DC_ERROR("Failed to create sink!\n");
872 return;
873 }
874
875 link->local_sink = sink;
876
877 edid_status = dm_helpers_read_local_edid(
878 link->ctx,
879 link,
880 sink);
881
882 if (edid_status != EDID_OK)
883 DC_ERROR("Failed to read EDID");
884
885}
886
4562236b
HW		 887static int dm_resume(void *handle)
888{
889 struct amdgpu_device *adev = handle;
4562236b
HW		 890 struct drm_device *ddev = adev->ddev;
891 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 892 struct amdgpu_dm_connector *aconnector;
4562236b 893 struct drm_connector *connector;
4562236b 894 struct drm_crtc *crtc;
c2cea706 895 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 896 struct dm_crtc_state *dm_new_crtc_state;
897 struct drm_plane *plane;
898 struct drm_plane_state *new_plane_state;
899 struct dm_plane_state *dm_new_plane_state;
fbbdadf2 900 enum dc_connection_type new_connection_type = dc_connection_none;
a80aa93d 901 int ret;
a3621485 902 int i;
4562236b 903
a80aa93d
ML		 904 /* power on hardware */
905 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
906
4562236b
HW		 907 /* program HPD filter */
908 dc_resume(dm->dc);
909
910 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
911 s3_handle_mst(ddev, false);
912
913 /*
914 * early enable HPD Rx IRQ, should be done before set mode as short
915 * pulse interrupts are used for MST
916 */
917 amdgpu_dm_irq_resume_early(adev);
918
4562236b 919 /* Do detection*/
a80aa93d 920 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 921 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 922
923 /*
924 * this is the case when traversing through already created
925 * MST connectors, should be skipped
926 */
927 if (aconnector->mst_port)
928 continue;
929
03ea364c 930 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 931 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
932 DRM_ERROR("KMS: Failed to detect connector\n");
933
934 if (aconnector->base.force && new_connection_type == dc_connection_none)
935 emulated_link_detect(aconnector->dc_link);
936 else
937 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 938
939 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
940 aconnector->fake_enable = false;
941
4562236b
HW		 942 aconnector->dc_sink = NULL;
943 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 944 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 945 }
946
1f6010a9 947 /* Force mode set in atomic commit */
a80aa93d 948 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 949 new_crtc_state->active_changed = true;
4f346e65 950
fcb4019e
LSL		 951 /*
952 * atomic_check is expected to create the dc states. We need to release
953 * them here, since they were duplicated as part of the suspend
954 * procedure.
955 */
a80aa93d 956 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 957 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
958 if (dm_new_crtc_state->stream) {
959 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
960 dc_stream_release(dm_new_crtc_state->stream);
961 dm_new_crtc_state->stream = NULL;
962 }
963 }
964
a80aa93d 965 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 966 dm_new_plane_state = to_dm_plane_state(new_plane_state);
967 if (dm_new_plane_state->dc_state) {
968 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
969 dc_plane_state_release(dm_new_plane_state->dc_state);
970 dm_new_plane_state->dc_state = NULL;
971 }
972 }
973
a80aa93d 974 ret = drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 975
a80aa93d 976 dm->cached_state = NULL;
0a214e2f 977
9faa4237 978 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 979
980 return ret;
981}
982
b8592b48
LL		 983/**
984 * DOC: DM Lifecycle
985 *
986 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
987 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
988 * the base driver's device list to be initialized and torn down accordingly.
989 *
990 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
991 */
992
4562236b
HW		 993static const struct amd_ip_funcs amdgpu_dm_funcs = {
994 .name = "dm",
995 .early_init = dm_early_init,
7abcf6b5 996 .late_init = dm_late_init,
4562236b
HW		 997 .sw_init = dm_sw_init,
998 .sw_fini = dm_sw_fini,
999 .hw_init = dm_hw_init,
1000 .hw_fini = dm_hw_fini,
1001 .suspend = dm_suspend,
1002 .resume = dm_resume,
1003 .is_idle = dm_is_idle,
1004 .wait_for_idle = dm_wait_for_idle,
1005 .check_soft_reset = dm_check_soft_reset,
1006 .soft_reset = dm_soft_reset,
1007 .set_clockgating_state = dm_set_clockgating_state,
1008 .set_powergating_state = dm_set_powergating_state,
1009};
1010
1011const struct amdgpu_ip_block_version dm_ip_block =
1012{
1013 .type = AMD_IP_BLOCK_TYPE_DCE,
1014 .major = 1,
1015 .minor = 0,
1016 .rev = 0,
1017 .funcs = &amdgpu_dm_funcs,
1018};
1019
ca3268c4 1020
b8592b48
LL		 1021/**
1022 * DOC: atomic
1023 *
1024 * *WIP*
1025 */
0a323b84 1026
b3663f70 1027static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 1028 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 1029 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 1030 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 1031 .atomic_commit = amdgpu_dm_atomic_commit,
54f5499a
AG		 1032};
1033
1034static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1035 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 1036};
1037
7578ecda 1038static void
3ee6b26b 1039amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1040{
1041 struct drm_connector *connector = &aconnector->base;
1042 struct drm_device *dev = connector->dev;
b73a22d3 1043 struct dc_sink *sink;
4562236b
HW		 1044
1045 /* MST handled by drm_mst framework */
1046 if (aconnector->mst_mgr.mst_state == true)
1047 return;
1048
1049
1050 sink = aconnector->dc_link->local_sink;
1051
1f6010a9
DF		 1052 /*
1053 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 1054 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 1055 * Skip if already done during boot.
4562236b
HW		 1056 */
1057 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1058 && aconnector->dc_em_sink) {
1059
1f6010a9
DF		 1060 /*
1061 * For S3 resume with headless use eml_sink to fake stream
1062 * because on resume connector->sink is set to NULL
4562236b
HW		 1063 */
1064 mutex_lock(&dev->mode_config.mutex);
1065
1066 if (sink) {
922aa1e1 1067 if (aconnector->dc_sink) {
98e6436d 1068 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 1069 /*
1070 * retain and release below are used to
1071 * bump up refcount for sink because the link doesn't point
1072 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 1073 * reshuffle by UMD we will get into unwanted dc_sink release
1074 */
1075 if (aconnector->dc_sink != aconnector->dc_em_sink)
1076 dc_sink_release(aconnector->dc_sink);
1077 }
4562236b 1078 aconnector->dc_sink = sink;
98e6436d
AK		 1079 amdgpu_dm_update_freesync_caps(connector,
1080 aconnector->edid);
4562236b 1081 } else {
98e6436d 1082 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1083 if (!aconnector->dc_sink)
1084 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 1085 else if (aconnector->dc_sink != aconnector->dc_em_sink)
1086 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 1087 }
1088
1089 mutex_unlock(&dev->mode_config.mutex);
1090 return;
1091 }
1092
1093 /*
1094 * TODO: temporary guard to look for proper fix
1095 * if this sink is MST sink, we should not do anything
1096 */
1097 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
1098 return;
1099
1100 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 1101 /*
1102 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1103 * Do nothing!!
1104 */
f1ad2f5e 1105 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 1106 aconnector->connector_id);
1107 return;
1108 }
1109
f1ad2f5e 1110 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 1111 aconnector->connector_id, aconnector->dc_sink, sink);
1112
1113 mutex_lock(&dev->mode_config.mutex);
1114
1f6010a9
DF		 1115 /*
1116 * 1. Update status of the drm connector
1117 * 2. Send an event and let userspace tell us what to do
1118 */
4562236b 1119 if (sink) {
1f6010a9
DF		 1120 /*
1121 * TODO: check if we still need the S3 mode update workaround.
1122 * If yes, put it here.
1123 */
4562236b 1124 if (aconnector->dc_sink)
98e6436d 1125 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1126
1127 aconnector->dc_sink = sink;
900b3cb1 1128 if (sink->dc_edid.length == 0) {
4562236b 1129 aconnector->edid = NULL;
e86e8947 1130 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 1131 } else {
4562236b
HW		 1132 aconnector->edid =
1133 (struct edid *) sink->dc_edid.raw_edid;
1134
1135
c555f023 1136 drm_connector_update_edid_property(connector,
4562236b 1137 aconnector->edid);
e86e8947
HV		 1138 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1139 aconnector->edid);
4562236b 1140 }
98e6436d 1141 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 1142
1143 } else {
e86e8947 1144 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 1145 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 1146 drm_connector_update_edid_property(connector, NULL);
4562236b
HW		 1147 aconnector->num_modes = 0;
1148 aconnector->dc_sink = NULL;
5326c452 1149 aconnector->edid = NULL;
4562236b
HW		 1150 }
1151
1152 mutex_unlock(&dev->mode_config.mutex);
1153}
1154
1155static void handle_hpd_irq(void *param)
1156{
c84dec2f 1157 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1158 struct drm_connector *connector = &aconnector->base;
1159 struct drm_device *dev = connector->dev;
fbbdadf2 1160 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1161
1f6010a9
DF		 1162 /*
1163 * In case of failure or MST no need to update connector status or notify the OS
1164 * since (for MST case) MST does this in its own context.
4562236b
HW		 1165 */
1166 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 1167
1168 if (aconnector->fake_enable)
1169 aconnector->fake_enable = false;
1170
fbbdadf2
BL		 1171 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1172 DRM_ERROR("KMS: Failed to detect connector\n");
1173
1174 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1175 emulated_link_detect(aconnector->dc_link);
1176
1177
1178 drm_modeset_lock_all(dev);
1179 dm_restore_drm_connector_state(dev, connector);
1180 drm_modeset_unlock_all(dev);
1181
1182 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1183 drm_kms_helper_hotplug_event(dev);
1184
1185 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1186 amdgpu_dm_update_connector_after_detect(aconnector);
1187
1188
1189 drm_modeset_lock_all(dev);
1190 dm_restore_drm_connector_state(dev, connector);
1191 drm_modeset_unlock_all(dev);
1192
1193 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1194 drm_kms_helper_hotplug_event(dev);
1195 }
1196 mutex_unlock(&aconnector->hpd_lock);
1197
1198}
1199
c84dec2f 1200static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1201{
1202 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1203 uint8_t dret;
1204 bool new_irq_handled = false;
1205 int dpcd_addr;
1206 int dpcd_bytes_to_read;
1207
1208 const int max_process_count = 30;
1209 int process_count = 0;
1210
1211 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1212
1213 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1214 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1215 /* DPCD 0x200 - 0x201 for downstream IRQ */
1216 dpcd_addr = DP_SINK_COUNT;
1217 } else {
1218 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1219 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1220 dpcd_addr = DP_SINK_COUNT_ESI;
1221 }
1222
1223 dret = drm_dp_dpcd_read(
1224 &aconnector->dm_dp_aux.aux,
1225 dpcd_addr,
1226 esi,
1227 dpcd_bytes_to_read);
1228
1229 while (dret == dpcd_bytes_to_read &&
1230 process_count < max_process_count) {
1231 uint8_t retry;
1232 dret = 0;
1233
1234 process_count++;
1235
f1ad2f5e 1236 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1237 /* handle HPD short pulse irq */
1238 if (aconnector->mst_mgr.mst_state)
1239 drm_dp_mst_hpd_irq(
1240 &aconnector->mst_mgr,
1241 esi,
1242 &new_irq_handled);
4562236b
HW		 1243
1244 if (new_irq_handled) {
1245 /* ACK at DPCD to notify down stream */
1246 const int ack_dpcd_bytes_to_write =
1247 dpcd_bytes_to_read - 1;
1248
1249 for (retry = 0; retry < 3; retry++) {
1250 uint8_t wret;
1251
1252 wret = drm_dp_dpcd_write(
1253 &aconnector->dm_dp_aux.aux,
1254 dpcd_addr + 1,
1255 &esi[1],
1256 ack_dpcd_bytes_to_write);
1257 if (wret == ack_dpcd_bytes_to_write)
1258 break;
1259 }
1260
1f6010a9 1261 /* check if there is new irq to be handled */
4562236b
HW		 1262 dret = drm_dp_dpcd_read(
1263 &aconnector->dm_dp_aux.aux,
1264 dpcd_addr,
1265 esi,
1266 dpcd_bytes_to_read);
1267
1268 new_irq_handled = false;
d4a6e8a9 1269 } else {
4562236b 1270 break;
d4a6e8a9 1271 }
4562236b
HW		 1272 }
1273
1274 if (process_count == max_process_count)
f1ad2f5e 1275 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1276}
1277
1278static void handle_hpd_rx_irq(void *param)
1279{
c84dec2f 1280 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1281 struct drm_connector *connector = &aconnector->base;
1282 struct drm_device *dev = connector->dev;
53cbf65c 1283 struct dc_link *dc_link = aconnector->dc_link;
4562236b 1284 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
fbbdadf2 1285 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1286
1f6010a9
DF		 1287 /*
1288 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 1289 * conflict, after implement i2c helper, this mutex should be
1290 * retired.
1291 */
53cbf65c 1292 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1293 mutex_lock(&aconnector->hpd_lock);
1294
4e18814e 1295 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1296 !is_mst_root_connector) {
1297 /* Downstream Port status changed. */
fbbdadf2
BL		 1298 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1299 DRM_ERROR("KMS: Failed to detect connector\n");
1300
1301 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1302 emulated_link_detect(dc_link);
1303
1304 if (aconnector->fake_enable)
1305 aconnector->fake_enable = false;
1306
1307 amdgpu_dm_update_connector_after_detect(aconnector);
1308
1309
1310 drm_modeset_lock_all(dev);
1311 dm_restore_drm_connector_state(dev, connector);
1312 drm_modeset_unlock_all(dev);
1313
1314 drm_kms_helper_hotplug_event(dev);
1315 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1316
1317 if (aconnector->fake_enable)
1318 aconnector->fake_enable = false;
1319
4562236b
HW		 1320 amdgpu_dm_update_connector_after_detect(aconnector);
1321
1322
1323 drm_modeset_lock_all(dev);
1324 dm_restore_drm_connector_state(dev, connector);
1325 drm_modeset_unlock_all(dev);
1326
1327 drm_kms_helper_hotplug_event(dev);
1328 }
1329 }
1330 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1331 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1332 dm_handle_hpd_rx_irq(aconnector);
1333
e86e8947
HV		 1334 if (dc_link->type != dc_connection_mst_branch) {
1335 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 1336 mutex_unlock(&aconnector->hpd_lock);
e86e8947 1337 }
4562236b
HW		 1338}
1339
1340static void register_hpd_handlers(struct amdgpu_device *adev)
1341{
1342 struct drm_device *dev = adev->ddev;
1343 struct drm_connector *connector;
c84dec2f 1344 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1345 const struct dc_link *dc_link;
1346 struct dc_interrupt_params int_params = {0};
1347
1348 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1349 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1350
1351 list_for_each_entry(connector,
1352 &dev->mode_config.connector_list, head) {
1353
c84dec2f 1354 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1355 dc_link = aconnector->dc_link;
1356
1357 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1358 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1359 int_params.irq_source = dc_link->irq_source_hpd;
1360
1361 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1362 handle_hpd_irq,
1363 (void *) aconnector);
1364 }
1365
1366 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1367
1368 /* Also register for DP short pulse (hpd_rx). */
1369 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1370 int_params.irq_source = dc_link->irq_source_hpd_rx;
1371
1372 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1373 handle_hpd_rx_irq,
1374 (void *) aconnector);
1375 }
1376 }
1377}
1378
1379/* Register IRQ sources and initialize IRQ callbacks */
1380static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1381{
1382 struct dc *dc = adev->dm.dc;
1383 struct common_irq_params *c_irq_params;
1384 struct dc_interrupt_params int_params = {0};
1385 int r;
1386 int i;
1ffdeca6 1387 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 1388
ff5ef992 1389 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1390 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1391 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1392 adev->asic_type == CHIP_RAVEN)
3760f76c 1393 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1394
1395 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1396 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1397
1f6010a9
DF		 1398 /*
1399 * Actions of amdgpu_irq_add_id():
4562236b
HW		 1400 * 1. Register a set() function with base driver.
1401 * Base driver will call set() function to enable/disable an
1402 * interrupt in DC hardware.
1403 * 2. Register amdgpu_dm_irq_handler().
1404 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1405 * coming from DC hardware.
1406 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1407 * for acknowledging and handling. */
1408
b57de80a 1409 /* Use VBLANK interrupt */
e9029155 1410 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1411 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1412 if (r) {
1413 DRM_ERROR("Failed to add crtc irq id!\n");
1414 return r;
1415 }
1416
1417 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1418 int_params.irq_source =
3d761e79 1419 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1420
b57de80a 1421 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1422
1423 c_irq_params->adev = adev;
1424 c_irq_params->irq_src = int_params.irq_source;
1425
1426 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1427 dm_crtc_high_irq, c_irq_params);
1428 }
1429
3d761e79 1430 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1431 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1432 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1433 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1434 if (r) {
1435 DRM_ERROR("Failed to add page flip irq id!\n");
1436 return r;
1437 }
1438
1439 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1440 int_params.irq_source =
1441 dc_interrupt_to_irq_source(dc, i, 0);
1442
1443 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1444
1445 c_irq_params->adev = adev;
1446 c_irq_params->irq_src = int_params.irq_source;
1447
1448 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1449 dm_pflip_high_irq, c_irq_params);
1450
1451 }
1452
1453 /* HPD */
2c8ad2d5
AD		 1454 r = amdgpu_irq_add_id(adev, client_id,
1455 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1456 if (r) {
1457 DRM_ERROR("Failed to add hpd irq id!\n");
1458 return r;
1459 }
1460
1461 register_hpd_handlers(adev);
1462
1463 return 0;
1464}
1465
ff5ef992
AD		 1466#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1467/* Register IRQ sources and initialize IRQ callbacks */
1468static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1469{
1470 struct dc *dc = adev->dm.dc;
1471 struct common_irq_params *c_irq_params;
1472 struct dc_interrupt_params int_params = {0};
1473 int r;
1474 int i;
1475
1476 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1477 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1478
1f6010a9
DF		 1479 /*
1480 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 1481 * 1. Register a set() function with base driver.
1482 * Base driver will call set() function to enable/disable an
1483 * interrupt in DC hardware.
1484 * 2. Register amdgpu_dm_irq_handler().
1485 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1486 * coming from DC hardware.
1487 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1488 * for acknowledging and handling.
1f6010a9 1489 */
ff5ef992
AD		 1490
1491 /* Use VSTARTUP interrupt */
1492 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1493 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1494 i++) {
3760f76c 1495 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1496
1497 if (r) {
1498 DRM_ERROR("Failed to add crtc irq id!\n");
1499 return r;
1500 }
1501
1502 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1503 int_params.irq_source =
1504 dc_interrupt_to_irq_source(dc, i, 0);
1505
1506 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1507
1508 c_irq_params->adev = adev;
1509 c_irq_params->irq_src = int_params.irq_source;
1510
1511 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1512 dm_crtc_high_irq, c_irq_params);
1513 }
1514
1515 /* Use GRPH_PFLIP interrupt */
1516 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1517 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1518 i++) {
3760f76c 1519 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1520 if (r) {
1521 DRM_ERROR("Failed to add page flip irq id!\n");
1522 return r;
1523 }
1524
1525 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1526 int_params.irq_source =
1527 dc_interrupt_to_irq_source(dc, i, 0);
1528
1529 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1530
1531 c_irq_params->adev = adev;
1532 c_irq_params->irq_src = int_params.irq_source;
1533
1534 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1535 dm_pflip_high_irq, c_irq_params);
1536
1537 }
1538
1539 /* HPD */
3760f76c 1540 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1541 &adev->hpd_irq);
1542 if (r) {
1543 DRM_ERROR("Failed to add hpd irq id!\n");
1544 return r;
1545 }
1546
1547 register_hpd_handlers(adev);
1548
1549 return 0;
1550}
1551#endif
1552
eb3dc897
NK		 1553/*
1554 * Acquires the lock for the atomic state object and returns
1555 * the new atomic state.
1556 *
1557 * This should only be called during atomic check.
1558 */
1559static int dm_atomic_get_state(struct drm_atomic_state *state,
1560 struct dm_atomic_state **dm_state)
1561{
1562 struct drm_device *dev = state->dev;
1563 struct amdgpu_device *adev = dev->dev_private;
1564 struct amdgpu_display_manager *dm = &adev->dm;
1565 struct drm_private_state *priv_state;
1566 int ret;
1567
1568 if (*dm_state)
1569 return 0;
1570
1571 ret = drm_modeset_lock(&dm->atomic_obj_lock, state->acquire_ctx);
1572 if (ret)
1573 return ret;
1574
1575 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1576 if (IS_ERR(priv_state))
1577 return PTR_ERR(priv_state);
1578
1579 *dm_state = to_dm_atomic_state(priv_state);
1580
1581 return 0;
1582}
1583
1584struct dm_atomic_state *
1585dm_atomic_get_new_state(struct drm_atomic_state *state)
1586{
1587 struct drm_device *dev = state->dev;
1588 struct amdgpu_device *adev = dev->dev_private;
1589 struct amdgpu_display_manager *dm = &adev->dm;
1590 struct drm_private_obj *obj;
1591 struct drm_private_state *new_obj_state;
1592 int i;
1593
1594 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1595 if (obj->funcs == dm->atomic_obj.funcs)
1596 return to_dm_atomic_state(new_obj_state);
1597 }
1598
1599 return NULL;
1600}
1601
1602struct dm_atomic_state *
1603dm_atomic_get_old_state(struct drm_atomic_state *state)
1604{
1605 struct drm_device *dev = state->dev;
1606 struct amdgpu_device *adev = dev->dev_private;
1607 struct amdgpu_display_manager *dm = &adev->dm;
1608 struct drm_private_obj *obj;
1609 struct drm_private_state *old_obj_state;
1610 int i;
1611
1612 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1613 if (obj->funcs == dm->atomic_obj.funcs)
1614 return to_dm_atomic_state(old_obj_state);
1615 }
1616
1617 return NULL;
1618}
1619
1620static struct drm_private_state *
1621dm_atomic_duplicate_state(struct drm_private_obj *obj)
1622{
1623 struct dm_atomic_state *old_state, *new_state;
1624
1625 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1626 if (!new_state)
1627 return NULL;
1628
1629 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1630
1631 new_state->context = dc_create_state();
1632 if (!new_state->context) {
1633 kfree(new_state);
1634 return NULL;
1635 }
1636
1637 old_state = to_dm_atomic_state(obj->state);
1638 if (old_state && old_state->context)
1639 dc_resource_state_copy_construct(old_state->context,
1640 new_state->context);
1641
1642 return &new_state->base;
1643}
1644
1645static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1646 struct drm_private_state *state)
1647{
1648 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1649
1650 if (dm_state && dm_state->context)
1651 dc_release_state(dm_state->context);
1652
1653 kfree(dm_state);
1654}
1655
1656static struct drm_private_state_funcs dm_atomic_state_funcs = {
1657 .atomic_duplicate_state = dm_atomic_duplicate_state,
1658 .atomic_destroy_state = dm_atomic_destroy_state,
1659};
1660
4562236b
HW		 1661static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1662{
eb3dc897 1663 struct dm_atomic_state *state;
4562236b
HW		 1664 int r;
1665
1666 adev->mode_info.mode_config_initialized = true;
1667
4562236b 1668 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1669 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1670
1671 adev->ddev->mode_config.max_width = 16384;
1672 adev->ddev->mode_config.max_height = 16384;
1673
1674 adev->ddev->mode_config.preferred_depth = 24;
1675 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 1676 /* indicates support for immediate flip */
4562236b
HW		 1677 adev->ddev->mode_config.async_page_flip = true;
1678
770d13b1 1679 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1680
eb3dc897
NK		 1681 drm_modeset_lock_init(&adev->dm.atomic_obj_lock);
1682
1683 state = kzalloc(sizeof(*state), GFP_KERNEL);
1684 if (!state)
1685 return -ENOMEM;
1686
1687 state->context = dc_create_state();
1688 if (!state->context) {
1689 kfree(state);
1690 return -ENOMEM;
1691 }
1692
1693 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1694
8c1a765b
DA		 1695 drm_atomic_private_obj_init(adev->ddev,
1696 &adev->dm.atomic_obj,
eb3dc897
NK		 1697 &state->base,
1698 &dm_atomic_state_funcs);
1699
3dc9b1ce 1700 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1701 if (r)
1702 return r;
1703
1704 return 0;
1705}
1706
206bbafe
DF		 1707#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1708#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1709
4562236b
HW		 1710#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1711 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1712
206bbafe
DF		 1713static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1714{
1715#if defined(CONFIG_ACPI)
1716 struct amdgpu_dm_backlight_caps caps;
1717
1718 if (dm->backlight_caps.caps_valid)
1719 return;
1720
1721 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1722 if (caps.caps_valid) {
1723 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1724 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1725 dm->backlight_caps.caps_valid = true;
1726 } else {
1727 dm->backlight_caps.min_input_signal =
1728 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1729 dm->backlight_caps.max_input_signal =
1730 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1731 }
1732#else
8bcbc9ef
DF		 1733 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1734 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 1735#endif
1736}
1737
4562236b
HW		 1738static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1739{
1740 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe
DF		 1741 struct amdgpu_dm_backlight_caps caps;
1742 uint32_t brightness = bd->props.brightness;
4562236b 1743
206bbafe
DF		 1744 amdgpu_dm_update_backlight_caps(dm);
1745 caps = dm->backlight_caps;
0cafc82f 1746 /*
206bbafe
DF		 1747 * The brightness input is in the range 0-255
1748 * It needs to be rescaled to be between the
1749 * requested min and max input signal
1750 *
1751 * It also needs to be scaled up by 0x101 to
1752 * match the DC interface which has a range of
1753 * 0 to 0xffff
0cafc82f 1754 */
206bbafe
DF		 1755 brightness =
1756 brightness
1757 * 0x101
1758 * (caps.max_input_signal - caps.min_input_signal)
1759 / AMDGPU_MAX_BL_LEVEL
1760 + caps.min_input_signal * 0x101;
4562236b
HW		 1761
1762 if (dc_link_set_backlight_level(dm->backlight_link,
923fe495 1763 brightness, 0))
4562236b
HW		 1764 return 0;
1765 else
1766 return 1;
1767}
1768
1769static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1770{
620a0d27
DF		 1771 struct amdgpu_display_manager *dm = bl_get_data(bd);
1772 int ret = dc_link_get_backlight_level(dm->backlight_link);
1773
1774 if (ret == DC_ERROR_UNEXPECTED)
1775 return bd->props.brightness;
1776 return ret;
4562236b
HW		 1777}
1778
1779static const struct backlight_ops amdgpu_dm_backlight_ops = {
1780 .get_brightness = amdgpu_dm_backlight_get_brightness,
1781 .update_status = amdgpu_dm_backlight_update_status,
1782};
1783
7578ecda
AD		 1784static void
1785amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1786{
1787 char bl_name[16];
1788 struct backlight_properties props = { 0 };
1789
206bbafe
DF		 1790 amdgpu_dm_update_backlight_caps(dm);
1791
4562236b 1792 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 1793 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 1794 props.type = BACKLIGHT_RAW;
1795
1796 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1797 dm->adev->ddev->primary->index);
1798
1799 dm->backlight_dev = backlight_device_register(bl_name,
1800 dm->adev->ddev->dev,
1801 dm,
1802 &amdgpu_dm_backlight_ops,
1803 &props);
1804
74baea42 1805 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1806 DRM_ERROR("DM: Backlight registration failed!\n");
1807 else
f1ad2f5e 1808 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1809}
1810
1811#endif
1812
df534fff
S		 1813static int initialize_plane(struct amdgpu_display_manager *dm,
1814 struct amdgpu_mode_info *mode_info,
1815 int plane_id)
1816{
f180b4bc 1817 struct drm_plane *plane;
df534fff
S		 1818 unsigned long possible_crtcs;
1819 int ret = 0;
1820
f180b4bc 1821 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 1822 mode_info->planes[plane_id] = plane;
1823
1824 if (!plane) {
1825 DRM_ERROR("KMS: Failed to allocate plane\n");
1826 return -ENOMEM;
1827 }
f180b4bc 1828 plane->type = mode_info->plane_type[plane_id];
df534fff
S		 1829
1830 /*
1f6010a9 1831 * HACK: IGT tests expect that each plane can only have
df534fff
S		 1832 * one possible CRTC. For now, set one CRTC for each
1833 * plane that is not an underlay, but still allow multiple
1834 * CRTCs for underlay planes.
1835 */
1836 possible_crtcs = 1 << plane_id;
1837 if (plane_id >= dm->dc->caps.max_streams)
1838 possible_crtcs = 0xff;
1839
1840 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1841
1842 if (ret) {
1843 DRM_ERROR("KMS: Failed to initialize plane\n");
1844 return ret;
1845 }
1846
1847 return ret;
1848}
1849
89fc8d4e
HW		 1850
1851static void register_backlight_device(struct amdgpu_display_manager *dm,
1852 struct dc_link *link)
1853{
1854#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1855 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1856
1857 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1858 link->type != dc_connection_none) {
1f6010a9
DF		 1859 /*
1860 * Event if registration failed, we should continue with
89fc8d4e
HW		 1861 * DM initialization because not having a backlight control
1862 * is better then a black screen.
1863 */
1864 amdgpu_dm_register_backlight_device(dm);
1865
1866 if (dm->backlight_dev)
1867 dm->backlight_link = link;
1868 }
1869#endif
1870}
1871
1872
1f6010a9
DF		 1873/*
1874 * In this architecture, the association
4562236b
HW		 1875 * connector -> encoder -> crtc
1876 * id not really requried. The crtc and connector will hold the
1877 * display_index as an abstraction to use with DAL component
1878 *
1879 * Returns 0 on success
1880 */
7578ecda 1881static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1882{
1883 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 1884 int32_t i;
c84dec2f 1885 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1886 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1887 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1888 uint32_t link_cnt;
df534fff 1889 int32_t total_overlay_planes, total_primary_planes;
fbbdadf2 1890 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b
HW		 1891
1892 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1893 if (amdgpu_dm_mode_config_init(dm->adev)) {
1894 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 1895 return -EINVAL;
4562236b
HW		 1896 }
1897
df534fff
S		 1898 /* Identify the number of planes to be initialized */
1899 total_overlay_planes = dm->dc->caps.max_slave_planes;
1900 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
efa6a8b7 1901
df534fff
S		 1902 /* First initialize overlay planes, index starting after primary planes */
1903 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1904 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1905 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 1906 goto fail;
d4e13b0d 1907 }
df534fff 1908 }
92f3ac40 1909
df534fff
S		 1910 /* Initialize primary planes */
1911 for (i = (total_primary_planes - 1); i >= 0; i--) {
1912 if (initialize_plane(dm, mode_info, i)) {
1913 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 1914 goto fail;
d4e13b0d
AD		 1915 }
1916 }
4562236b 1917
d4e13b0d 1918 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 1919 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 1920 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1921 goto fail;
4562236b 1922 }
4562236b 1923
ab2541b6 1924 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1925
1926 /* loops over all connectors on the board */
1927 for (i = 0; i < link_cnt; i++) {
89fc8d4e 1928 struct dc_link *link = NULL;
4562236b
HW		 1929
1930 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1931 DRM_ERROR(
1932 "KMS: Cannot support more than %d display indexes\n",
1933 AMDGPU_DM_MAX_DISPLAY_INDEX);
1934 continue;
1935 }
1936
1937 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1938 if (!aconnector)
cd8a2ae8 1939 goto fail;
4562236b
HW		 1940
1941 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1942 if (!aencoder)
cd8a2ae8 1943 goto fail;
4562236b
HW		 1944
1945 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1946 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1947 goto fail;
4562236b
HW		 1948 }
1949
1950 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1951 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1952 goto fail;
4562236b
HW		 1953 }
1954
89fc8d4e
HW		 1955 link = dc_get_link_at_index(dm->dc, i);
1956
fbbdadf2
BL		 1957 if (!dc_link_detect_sink(link, &new_connection_type))
1958 DRM_ERROR("KMS: Failed to detect connector\n");
1959
1960 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1961 emulated_link_detect(link);
1962 amdgpu_dm_update_connector_after_detect(aconnector);
1963
1964 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 1965 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 1966 register_backlight_device(dm, link);
1967 }
1968
1969
4562236b
HW		 1970 }
1971
1972 /* Software is initialized. Now we can register interrupt handlers. */
1973 switch (adev->asic_type) {
1974 case CHIP_BONAIRE:
1975 case CHIP_HAWAII:
cd4b356f
AD		 1976 case CHIP_KAVERI:
1977 case CHIP_KABINI:
1978 case CHIP_MULLINS:
4562236b
HW		 1979 case CHIP_TONGA:
1980 case CHIP_FIJI:
1981 case CHIP_CARRIZO:
1982 case CHIP_STONEY:
1983 case CHIP_POLARIS11:
1984 case CHIP_POLARIS10:
b264d345 1985 case CHIP_POLARIS12:
7737de91 1986 case CHIP_VEGAM:
2c8ad2d5 1987 case CHIP_VEGA10:
2325ff30 1988 case CHIP_VEGA12:
1fe6bf2f 1989 case CHIP_VEGA20:
4562236b
HW		 1990 if (dce110_register_irq_handlers(dm->adev)) {
1991 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1992 goto fail;
4562236b
HW		 1993 }
1994 break;
ff5ef992
AD		 1995#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1996 case CHIP_RAVEN:
1997 if (dcn10_register_irq_handlers(dm->adev)) {
1998 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1999 goto fail;
ff5ef992
AD		 2000 }
2001 break;
2002#endif
4562236b 2003 default:
e63f8673 2004 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 2005 goto fail;
4562236b
HW		 2006 }
2007
1bc460a4
HW		 2008 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2009 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2010
4562236b 2011 return 0;
cd8a2ae8 2012fail:
4562236b 2013 kfree(aencoder);
4562236b 2014 kfree(aconnector);
3be5262e 2015 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 2016 kfree(mode_info->planes[i]);
59d0f396 2017 return -EINVAL;
4562236b
HW		 2018}
2019
7578ecda 2020static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2021{
2022 drm_mode_config_cleanup(dm->ddev);
eb3dc897 2023 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 2024 return;
2025}
2026
2027/******************************************************************************
2028 * amdgpu_display_funcs functions
2029 *****************************************************************************/
2030
1f6010a9 2031/*
4562236b
HW		 2032 * dm_bandwidth_update - program display watermarks
2033 *
2034 * @adev: amdgpu_device pointer
2035 *
2036 * Calculate and program the display watermarks and line buffer allocation.
2037 */
2038static void dm_bandwidth_update(struct amdgpu_device *adev)
2039{
49c07a99 2040 /* TODO: implement later */
4562236b
HW		 2041}
2042
39cc5be2 2043static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 2044 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2045 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 2046 .backlight_set_level = NULL, /* never called for DC */
2047 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 2048 .hpd_sense = NULL,/* called unconditionally */
2049 .hpd_set_polarity = NULL, /* called unconditionally */
2050 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2051 .page_flip_get_scanoutpos =
2052 dm_crtc_get_scanoutpos,/* called unconditionally */
2053 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2054 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2055};
2056
2057#if defined(CONFIG_DEBUG_KERNEL_DC)
2058
3ee6b26b
AD		 2059static ssize_t s3_debug_store(struct device *device,
2060 struct device_attribute *attr,
2061 const char *buf,
2062 size_t count)
4562236b
HW		 2063{
2064 int ret;
2065 int s3_state;
2066 struct pci_dev *pdev = to_pci_dev(device);
2067 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2068 struct amdgpu_device *adev = drm_dev->dev_private;
2069
2070 ret = kstrtoint(buf, 0, &s3_state);
2071
2072 if (ret == 0) {
2073 if (s3_state) {
2074 dm_resume(adev);
4562236b
HW		 2075 drm_kms_helper_hotplug_event(adev->ddev);
2076 } else
2077 dm_suspend(adev);
2078 }
2079
2080 return ret == 0 ? count : 0;
2081}
2082
2083DEVICE_ATTR_WO(s3_debug);
2084
2085#endif
2086
2087static int dm_early_init(void *handle)
2088{
2089 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2090
4562236b
HW		 2091 switch (adev->asic_type) {
2092 case CHIP_BONAIRE:
2093 case CHIP_HAWAII:
2094 adev->mode_info.num_crtc = 6;
2095 adev->mode_info.num_hpd = 6;
2096 adev->mode_info.num_dig = 6;
3be5262e 2097 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 2098 break;
cd4b356f
AD		 2099 case CHIP_KAVERI:
2100 adev->mode_info.num_crtc = 4;
2101 adev->mode_info.num_hpd = 6;
2102 adev->mode_info.num_dig = 7;
2103 adev->mode_info.plane_type = dm_plane_type_default;
2104 break;
2105 case CHIP_KABINI:
2106 case CHIP_MULLINS:
2107 adev->mode_info.num_crtc = 2;
2108 adev->mode_info.num_hpd = 6;
2109 adev->mode_info.num_dig = 6;
2110 adev->mode_info.plane_type = dm_plane_type_default;
2111 break;
4562236b
HW		 2112 case CHIP_FIJI:
2113 case CHIP_TONGA:
2114 adev->mode_info.num_crtc = 6;
2115 adev->mode_info.num_hpd = 6;
2116 adev->mode_info.num_dig = 7;
3be5262e 2117 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 2118 break;
2119 case CHIP_CARRIZO:
2120 adev->mode_info.num_crtc = 3;
2121 adev->mode_info.num_hpd = 6;
2122 adev->mode_info.num_dig = 9;
3be5262e 2123 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 2124 break;
2125 case CHIP_STONEY:
2126 adev->mode_info.num_crtc = 2;
2127 adev->mode_info.num_hpd = 6;
2128 adev->mode_info.num_dig = 9;
3be5262e 2129 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 2130 break;
2131 case CHIP_POLARIS11:
b264d345 2132 case CHIP_POLARIS12:
4562236b
HW		 2133 adev->mode_info.num_crtc = 5;
2134 adev->mode_info.num_hpd = 5;
2135 adev->mode_info.num_dig = 5;
3be5262e 2136 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 2137 break;
2138 case CHIP_POLARIS10:
7737de91 2139 case CHIP_VEGAM:
4562236b
HW		 2140 adev->mode_info.num_crtc = 6;
2141 adev->mode_info.num_hpd = 6;
2142 adev->mode_info.num_dig = 6;
3be5262e 2143 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 2144 break;
2c8ad2d5 2145 case CHIP_VEGA10:
2325ff30 2146 case CHIP_VEGA12:
1fe6bf2f 2147 case CHIP_VEGA20:
2c8ad2d5
AD		 2148 adev->mode_info.num_crtc = 6;
2149 adev->mode_info.num_hpd = 6;
2150 adev->mode_info.num_dig = 6;
3be5262e 2151 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 2152 break;
ff5ef992
AD		 2153#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2154 case CHIP_RAVEN:
2155 adev->mode_info.num_crtc = 4;
2156 adev->mode_info.num_hpd = 4;
2157 adev->mode_info.num_dig = 4;
3be5262e 2158 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 2159 break;
2160#endif
4562236b 2161 default:
e63f8673 2162 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 2163 return -EINVAL;
2164 }
2165
c8dd5715
MD		 2166 amdgpu_dm_set_irq_funcs(adev);
2167
39cc5be2
AD		 2168 if (adev->mode_info.funcs == NULL)
2169 adev->mode_info.funcs = &dm_display_funcs;
2170
1f6010a9
DF		 2171 /*
2172 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 2173 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 2174 * amdgpu_device_init()
2175 */
4562236b
HW		 2176#if defined(CONFIG_DEBUG_KERNEL_DC)
2177 device_create_file(
2178 adev->ddev->dev,
2179 &dev_attr_s3_debug);
2180#endif
2181
2182 return 0;
2183}
2184
9b690ef3 2185static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 2186 struct dc_stream_state *new_stream,
2187 struct dc_stream_state *old_stream)
9b690ef3 2188{
e7b07cee
HW		 2189 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2190 return false;
2191
2192 if (!crtc_state->enable)
2193 return false;
2194
2195 return crtc_state->active;
2196}
2197
2198static bool modereset_required(struct drm_crtc_state *crtc_state)
2199{
2200 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2201 return false;
2202
2203 return !crtc_state->enable || !crtc_state->active;
2204}
2205
7578ecda 2206static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 2207{
2208 drm_encoder_cleanup(encoder);
2209 kfree(encoder);
2210}
2211
2212static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2213 .destroy = amdgpu_dm_encoder_destroy,
2214};
2215
3ee6b26b
AD		 2216static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
2217 struct dc_plane_state *plane_state)
e7b07cee 2218{
3be5262e
HW		 2219 plane_state->src_rect.x = state->src_x >> 16;
2220 plane_state->src_rect.y = state->src_y >> 16;
1f6010a9 2221 /* we ignore the mantissa for now and do not deal with floating pixels :( */
3be5262e 2222 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 2223
3be5262e 2224 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 2225 return false;
2226
3be5262e
HW		 2227 plane_state->src_rect.height = state->src_h >> 16;
2228 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 2229 return false;
2230
3be5262e
HW		 2231 plane_state->dst_rect.x = state->crtc_x;
2232 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 2233
2234 if (state->crtc_w == 0)
2235 return false;
2236
3be5262e 2237 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 2238
2239 if (state->crtc_h == 0)
2240 return false;
2241
3be5262e 2242 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 2243
3be5262e 2244 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 2245
2246 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
2247 case DRM_MODE_ROTATE_0:
3be5262e 2248 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2249 break;
2250 case DRM_MODE_ROTATE_90:
3be5262e 2251 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 2252 break;
2253 case DRM_MODE_ROTATE_180:
3be5262e 2254 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 2255 break;
2256 case DRM_MODE_ROTATE_270:
3be5262e 2257 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 2258 break;
2259 default:
3be5262e 2260 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2261 break;
2262 }
2263
4562236b
HW		 2264 return true;
2265}
3ee6b26b 2266static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 2267 uint64_t *tiling_flags)
e7b07cee 2268{
e68d14dd 2269 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 2270 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 2271
e7b07cee 2272 if (unlikely(r)) {
1f6010a9 2273 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 2274 if (r != -ERESTARTSYS)
2275 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 2276 return r;
2277 }
2278
e7b07cee
HW		 2279 if (tiling_flags)
2280 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2281
2282 amdgpu_bo_unreserve(rbo);
2283
2284 return r;
2285}
2286
3ee6b26b
AD		 2287static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
2288 struct dc_plane_state *plane_state,
9817d5f5 2289 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 2290{
2291 uint64_t tiling_flags;
e7b07cee
HW		 2292 unsigned int awidth;
2293 const struct drm_framebuffer *fb = &amdgpu_fb->base;
2294 int ret = 0;
2295 struct drm_format_name_buf format_name;
2296
2297 ret = get_fb_info(
2298 amdgpu_fb,
9817d5f5 2299 &tiling_flags);
e7b07cee
HW		 2300
2301 if (ret)
2302 return ret;
2303
2304 switch (fb->format->format) {
2305 case DRM_FORMAT_C8:
3be5262e 2306 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 2307 break;
2308 case DRM_FORMAT_RGB565:
3be5262e 2309 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 2310 break;
2311 case DRM_FORMAT_XRGB8888:
2312 case DRM_FORMAT_ARGB8888:
3be5262e 2313 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 2314 break;
2315 case DRM_FORMAT_XRGB2101010:
2316 case DRM_FORMAT_ARGB2101010:
3be5262e 2317 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 2318 break;
2319 case DRM_FORMAT_XBGR2101010:
2320 case DRM_FORMAT_ABGR2101010:
3be5262e 2321 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee 2322 break;
bcd47f60
MR		 2323 case DRM_FORMAT_XBGR8888:
2324 case DRM_FORMAT_ABGR8888:
2325 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2326 break;
e7b07cee 2327 case DRM_FORMAT_NV21:
3be5262e 2328 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 2329 break;
2330 case DRM_FORMAT_NV12:
3be5262e 2331 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 2332 break;
2333 default:
2334 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 2335 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 2336 return -EINVAL;
2337 }
2338
3be5262e
HW		 2339 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2340 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 2341 plane_state->plane_size.grph.surface_size.x = 0;
2342 plane_state->plane_size.grph.surface_size.y = 0;
2343 plane_state->plane_size.grph.surface_size.width = fb->width;
2344 plane_state->plane_size.grph.surface_size.height = fb->height;
2345 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 2346 fb->pitches[0] / fb->format->cpp[0];
2347 /* TODO: unhardcode */
3be5262e 2348 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 2349
2350 } else {
2351 awidth = ALIGN(fb->width, 64);
3be5262e 2352 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 2353 plane_state->plane_size.video.luma_size.x = 0;
2354 plane_state->plane_size.video.luma_size.y = 0;
2355 plane_state->plane_size.video.luma_size.width = awidth;
2356 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 2357 /* TODO: unhardcode */
3be5262e 2358 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 2359
3be5262e
HW		 2360 plane_state->plane_size.video.chroma_size.x = 0;
2361 plane_state->plane_size.video.chroma_size.y = 0;
2362 plane_state->plane_size.video.chroma_size.width = awidth;
2363 plane_state->plane_size.video.chroma_size.height = fb->height;
2364 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 2365
2366 /* TODO: unhardcode */
3be5262e 2367 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 2368 }
2369
3be5262e 2370 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 2371
b830ebc9
HW		 2372 /* Fill GFX8 params */
2373 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2374 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 2375
2376 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2377 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2378 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2379 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2380 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2381
2382 /* XXX fix me for VI */
3be5262e
HW		 2383 plane_state->tiling_info.gfx8.num_banks = num_banks;
2384 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 2385 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 2386 plane_state->tiling_info.gfx8.tile_split = tile_split;
2387 plane_state->tiling_info.gfx8.bank_width = bankw;
2388 plane_state->tiling_info.gfx8.bank_height = bankh;
2389 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2390 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 2391 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2392 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2393 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 2394 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 2395 }
2396
3be5262e 2397 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 2398 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2399
2400 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 2401 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 2402 adev->asic_type == CHIP_VEGA20 ||
e7b07cee
HW		 2403 adev->asic_type == CHIP_RAVEN) {
2404 /* Fill GFX9 params */
3be5262e 2405 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 2406 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 2407 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 2408 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 2409 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 2410 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 2411 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 2412 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 2413 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 2414 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 2415 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 2416 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 2417 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 2418 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 2419 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 2420 }
2421
3be5262e
HW		 2422 plane_state->visible = true;
2423 plane_state->scaling_quality.h_taps_c = 0;
2424 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 2425
3be5262e
HW		 2426 /* is this needed? is plane_state zeroed at allocation? */
2427 plane_state->scaling_quality.h_taps = 0;
2428 plane_state->scaling_quality.v_taps = 0;
2429 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 2430
2431 return ret;
2432
2433}
2434
3ee6b26b
AD		 2435static int fill_plane_attributes(struct amdgpu_device *adev,
2436 struct dc_plane_state *dc_plane_state,
2437 struct drm_plane_state *plane_state,
9817d5f5 2438 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2439{
2440 const struct amdgpu_framebuffer *amdgpu_fb =
2441 to_amdgpu_framebuffer(plane_state->fb);
2442 const struct drm_crtc *crtc = plane_state->crtc;
e7b07cee
HW		 2443 int ret = 0;
2444
3be5262e 2445 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 2446 return -EINVAL;
2447
2448 ret = fill_plane_attributes_from_fb(
2449 crtc->dev->dev_private,
3be5262e 2450 dc_plane_state,
9817d5f5 2451 amdgpu_fb);
e7b07cee
HW		 2452
2453 if (ret)
2454 return ret;
2455
e277adc5
LSL		 2456 /*
2457 * Always set input transfer function, since plane state is refreshed
2458 * every time.
2459 */
2460 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2461 if (ret) {
2462 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2463 dc_plane_state->in_transfer_func = NULL;
2464 }
e7b07cee
HW		 2465
2466 return ret;
2467}
2468
3ee6b26b
AD		 2469static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2470 const struct dm_connector_state *dm_state,
2471 struct dc_stream_state *stream)
e7b07cee
HW		 2472{
2473 enum amdgpu_rmx_type rmx_type;
2474
2475 struct rect src = { 0 }; /* viewport in composition space*/
2476 struct rect dst = { 0 }; /* stream addressable area */
2477
2478 /* no mode. nothing to be done */
2479 if (!mode)
2480 return;
2481
2482 /* Full screen scaling by default */
2483 src.width = mode->hdisplay;
2484 src.height = mode->vdisplay;
2485 dst.width = stream->timing.h_addressable;
2486 dst.height = stream->timing.v_addressable;
2487
f4791779
HW		 2488 if (dm_state) {
2489 rmx_type = dm_state->scaling;
2490 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2491 if (src.width * dst.height <
2492 src.height * dst.width) {
2493 /* height needs less upscaling/more downscaling */
2494 dst.width = src.width *
2495 dst.height / src.height;
2496 } else {
2497 /* width needs less upscaling/more downscaling */
2498 dst.height = src.height *
2499 dst.width / src.width;
2500 }
2501 } else if (rmx_type == RMX_CENTER) {
2502 dst = src;
e7b07cee 2503 }
e7b07cee 2504
f4791779
HW		 2505 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2506 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2507
f4791779
HW		 2508 if (dm_state->underscan_enable) {
2509 dst.x += dm_state->underscan_hborder / 2;
2510 dst.y += dm_state->underscan_vborder / 2;
2511 dst.width -= dm_state->underscan_hborder;
2512 dst.height -= dm_state->underscan_vborder;
2513 }
e7b07cee
HW		 2514 }
2515
2516 stream->src = src;
2517 stream->dst = dst;
2518
f1ad2f5e 2519 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2520 dst.x, dst.y, dst.width, dst.height);
2521
2522}
2523
3ee6b26b
AD		 2524static enum dc_color_depth
2525convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee 2526{
07e3a1cf
NK		 2527 struct dm_connector_state *dm_conn_state =
2528 to_dm_connector_state(connector->state);
e7b07cee
HW		 2529 uint32_t bpc = connector->display_info.bpc;
2530
07e3a1cf
NK		 2531 /* TODO: Remove this when there's support for max_bpc in drm */
2532 if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2533 /* Round down to nearest even number. */
2534 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2535
e7b07cee
HW		 2536 switch (bpc) {
2537 case 0:
1f6010a9
DF		 2538 /*
2539 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 2540 * EDID revision before 1.4
2541 * TODO: Fix edid parsing
2542 */
2543 return COLOR_DEPTH_888;
2544 case 6:
2545 return COLOR_DEPTH_666;
2546 case 8:
2547 return COLOR_DEPTH_888;
2548 case 10:
2549 return COLOR_DEPTH_101010;
2550 case 12:
2551 return COLOR_DEPTH_121212;
2552 case 14:
2553 return COLOR_DEPTH_141414;
2554 case 16:
2555 return COLOR_DEPTH_161616;
2556 default:
2557 return COLOR_DEPTH_UNDEFINED;
2558 }
2559}
2560
3ee6b26b
AD		 2561static enum dc_aspect_ratio
2562get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 2563{
e11d4147
LSL		 2564 /* 1-1 mapping, since both enums follow the HDMI spec. */
2565 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 2566}
2567
3ee6b26b
AD		 2568static enum dc_color_space
2569get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2570{
2571 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2572
2573 switch (dc_crtc_timing->pixel_encoding) {
2574 case PIXEL_ENCODING_YCBCR422:
2575 case PIXEL_ENCODING_YCBCR444:
2576 case PIXEL_ENCODING_YCBCR420:
2577 {
2578 /*
2579 * 27030khz is the separation point between HDTV and SDTV
2580 * according to HDMI spec, we use YCbCr709 and YCbCr601
2581 * respectively
2582 */
2583 if (dc_crtc_timing->pix_clk_khz > 27030) {
2584 if (dc_crtc_timing->flags.Y_ONLY)
2585 color_space =
2586 COLOR_SPACE_YCBCR709_LIMITED;
2587 else
2588 color_space = COLOR_SPACE_YCBCR709;
2589 } else {
2590 if (dc_crtc_timing->flags.Y_ONLY)
2591 color_space =
2592 COLOR_SPACE_YCBCR601_LIMITED;
2593 else
2594 color_space = COLOR_SPACE_YCBCR601;
2595 }
2596
2597 }
2598 break;
2599 case PIXEL_ENCODING_RGB:
2600 color_space = COLOR_SPACE_SRGB;
2601 break;
2602
2603 default:
2604 WARN_ON(1);
2605 break;
2606 }
2607
2608 return color_space;
2609}
2610
400443e8
ML		 2611static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2612{
2613 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2614 return;
2615
2616 timing_out->display_color_depth--;
2617}
2618
2619static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2620 const struct drm_display_info *info)
2621{
2622 int normalized_clk;
2623 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2624 return;
2625 do {
2626 normalized_clk = timing_out->pix_clk_khz;
2627 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2628 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2629 normalized_clk /= 2;
2630 /* Adjusting pix clock following on HDMI spec based on colour depth */
2631 switch (timing_out->display_color_depth) {
2632 case COLOR_DEPTH_101010:
2633 normalized_clk = (normalized_clk * 30) / 24;
2634 break;
2635 case COLOR_DEPTH_121212:
2636 normalized_clk = (normalized_clk * 36) / 24;
2637 break;
2638 case COLOR_DEPTH_161616:
2639 normalized_clk = (normalized_clk * 48) / 24;
2640 break;
2641 default:
2642 return;
2643 }
2644 if (normalized_clk <= info->max_tmds_clock)
2645 return;
2646 reduce_mode_colour_depth(timing_out);
2647
2648 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2649
2650}
e7b07cee 2651
3ee6b26b
AD		 2652static void
2653fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2654 const struct drm_display_mode *mode_in,
b333730d
BL		 2655 const struct drm_connector *connector,
2656 const struct dc_stream_state *old_stream)
e7b07cee
HW		 2657{
2658 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 2659 const struct drm_display_info *info = &connector->display_info;
b830ebc9 2660
e7b07cee
HW		 2661 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2662
2663 timing_out->h_border_left = 0;
2664 timing_out->h_border_right = 0;
2665 timing_out->v_border_top = 0;
2666 timing_out->v_border_bottom = 0;
2667 /* TODO: un-hardcode */
fe61a2f1 2668 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 2669 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1
ML		 2670 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2671 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
ceb3dbb4 2672 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 2673 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2674 else
2675 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2676
2677 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2678 timing_out->display_color_depth = convert_color_depth_from_display_info(
2679 connector);
2680 timing_out->scan_type = SCANNING_TYPE_NODATA;
2681 timing_out->hdmi_vic = 0;
b333730d
BL		 2682
2683 if(old_stream) {
2684 timing_out->vic = old_stream->timing.vic;
2685 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
2686 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
2687 } else {
2688 timing_out->vic = drm_match_cea_mode(mode_in);
2689 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2690 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2691 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2692 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2693 }
e7b07cee
HW		 2694
2695 timing_out->h_addressable = mode_in->crtc_hdisplay;
2696 timing_out->h_total = mode_in->crtc_htotal;
2697 timing_out->h_sync_width =
2698 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2699 timing_out->h_front_porch =
2700 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2701 timing_out->v_total = mode_in->crtc_vtotal;
2702 timing_out->v_addressable = mode_in->crtc_vdisplay;
2703 timing_out->v_front_porch =
2704 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2705 timing_out->v_sync_width =
2706 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2707 timing_out->pix_clk_khz = mode_in->crtc_clock;
2708 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 2709
2710 stream->output_color_space = get_output_color_space(timing_out);
2711
e43a432c
AK		 2712 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2713 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ceb3dbb4 2714 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
400443e8 2715 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 2716}
2717
3ee6b26b
AD		 2718static void fill_audio_info(struct audio_info *audio_info,
2719 const struct drm_connector *drm_connector,
2720 const struct dc_sink *dc_sink)
e7b07cee
HW		 2721{
2722 int i = 0;
2723 int cea_revision = 0;
2724 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2725
2726 audio_info->manufacture_id = edid_caps->manufacturer_id;
2727 audio_info->product_id = edid_caps->product_id;
2728
2729 cea_revision = drm_connector->display_info.cea_rev;
2730
090afc1e 2731 strscpy(audio_info->display_name,
d2b2562c 2732 edid_caps->display_name,
090afc1e 2733 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 2734
b830ebc9 2735 if (cea_revision >= 3) {
e7b07cee
HW		 2736 audio_info->mode_count = edid_caps->audio_mode_count;
2737
2738 for (i = 0; i < audio_info->mode_count; ++i) {
2739 audio_info->modes[i].format_code =
2740 (enum audio_format_code)
2741 (edid_caps->audio_modes[i].format_code);
2742 audio_info->modes[i].channel_count =
2743 edid_caps->audio_modes[i].channel_count;
2744 audio_info->modes[i].sample_rates.all =
2745 edid_caps->audio_modes[i].sample_rate;
2746 audio_info->modes[i].sample_size =
2747 edid_caps->audio_modes[i].sample_size;
2748 }
2749 }
2750
2751 audio_info->flags.all = edid_caps->speaker_flags;
2752
2753 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2754 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2755 audio_info->video_latency = drm_connector->video_latency[0];
2756 audio_info->audio_latency = drm_connector->audio_latency[0];
2757 }
2758
2759 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2760
2761}
2762
3ee6b26b
AD		 2763static void
2764copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2765 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2766{
2767 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2768 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2769 dst_mode->crtc_clock = src_mode->crtc_clock;
2770 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2771 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2772 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2773 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2774 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2775 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2776 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2777 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2778 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2779 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2780 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2781}
2782
3ee6b26b
AD		 2783static void
2784decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2785 const struct drm_display_mode *native_mode,
2786 bool scale_enabled)
e7b07cee
HW		 2787{
2788 if (scale_enabled) {
2789 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2790 } else if (native_mode->clock == drm_mode->clock &&
2791 native_mode->htotal == drm_mode->htotal &&
2792 native_mode->vtotal == drm_mode->vtotal) {
2793 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2794 } else {
2795 /* no scaling nor amdgpu inserted, no need to patch */
2796 }
2797}
2798
aed15309
ML		 2799static struct dc_sink *
2800create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 2801{
2e0ac3d6 2802 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 2803 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 2804 sink_init_data.link = aconnector->dc_link;
2805 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2806
2807 sink = dc_sink_create(&sink_init_data);
423788c7 2808 if (!sink) {
2e0ac3d6 2809 DRM_ERROR("Failed to create sink!\n");
aed15309 2810 return NULL;
423788c7 2811 }
2e0ac3d6 2812 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 2813
aed15309 2814 return sink;
2e0ac3d6
HW		 2815}
2816
fa2123db
ML		 2817static void set_multisync_trigger_params(
2818 struct dc_stream_state *stream)
2819{
2820 if (stream->triggered_crtc_reset.enabled) {
2821 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2822 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2823 }
2824}
2825
2826static void set_master_stream(struct dc_stream_state *stream_set[],
2827 int stream_count)
2828{
2829 int j, highest_rfr = 0, master_stream = 0;
2830
2831 for (j = 0; j < stream_count; j++) {
2832 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2833 int refresh_rate = 0;
2834
2835 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2836 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2837 if (refresh_rate > highest_rfr) {
2838 highest_rfr = refresh_rate;
2839 master_stream = j;
2840 }
2841 }
2842 }
2843 for (j = 0; j < stream_count; j++) {
03736f4c 2844 if (stream_set[j])
fa2123db
ML		 2845 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2846 }
2847}
2848
2849static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2850{
2851 int i = 0;
2852
2853 if (context->stream_count < 2)
2854 return;
2855 for (i = 0; i < context->stream_count ; i++) {
2856 if (!context->streams[i])
2857 continue;
1f6010a9
DF		 2858 /*
2859 * TODO: add a function to read AMD VSDB bits and set
fa2123db 2860 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 2861 * For now it's set to false
fa2123db
ML		 2862 */
2863 set_multisync_trigger_params(context->streams[i]);
2864 }
2865 set_master_stream(context->streams, context->stream_count);
2866}
2867
3ee6b26b
AD		 2868static struct dc_stream_state *
2869create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2870 const struct drm_display_mode *drm_mode,
b333730d
BL		 2871 const struct dm_connector_state *dm_state,
2872 const struct dc_stream_state *old_stream)
e7b07cee
HW		 2873{
2874 struct drm_display_mode *preferred_mode = NULL;
391ef035 2875 struct drm_connector *drm_connector;
0971c40e 2876 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2877 struct drm_display_mode mode = *drm_mode;
2878 bool native_mode_found = false;
b333730d
BL		 2879 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
2880 int mode_refresh;
58124bf8 2881 int preferred_refresh = 0;
b333730d 2882
aed15309 2883 struct dc_sink *sink = NULL;
b830ebc9 2884 if (aconnector == NULL) {
e7b07cee 2885 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2886 return stream;
e7b07cee
HW		 2887 }
2888
e7b07cee 2889 drm_connector = &aconnector->base;
2e0ac3d6 2890
f4ac176e 2891 if (!aconnector->dc_sink) {
8be17ac9
JFZ		 2892 if (!aconnector->mst_port) {
2893 sink = create_fake_sink(aconnector);
2894 if (!sink)
2895 return stream;
391ef035 2896 }
aed15309
ML		 2897 } else {
2898 sink = aconnector->dc_sink;
f4ac176e 2899 }
2e0ac3d6 2900
aed15309 2901 stream = dc_create_stream_for_sink(sink);
4562236b 2902
b830ebc9 2903 if (stream == NULL) {
e7b07cee 2904 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 2905 goto finish;
e7b07cee
HW		 2906 }
2907
ceb3dbb4
JL		 2908 stream->dm_stream_context = aconnector;
2909
e7b07cee
HW		 2910 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2911 /* Search for preferred mode */
2912 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2913 native_mode_found = true;
2914 break;
2915 }
2916 }
2917 if (!native_mode_found)
2918 preferred_mode = list_first_entry_or_null(
2919 &aconnector->base.modes,
2920 struct drm_display_mode,
2921 head);
2922
b333730d
BL		 2923 mode_refresh = drm_mode_vrefresh(&mode);
2924
b830ebc9 2925 if (preferred_mode == NULL) {
1f6010a9
DF		 2926 /*
2927 * This may not be an error, the use case is when we have no
e7b07cee
HW		 2928 * usermode calls to reset and set mode upon hotplug. In this
2929 * case, we call set mode ourselves to restore the previous mode
2930 * and the modelist may not be filled in in time.
2931 */
f1ad2f5e 2932 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2933 } else {
2934 decide_crtc_timing_for_drm_display_mode(
2935 &mode, preferred_mode,
f4791779 2936 dm_state ? (dm_state->scaling != RMX_OFF) : false);
58124bf8 2937 preferred_refresh = drm_mode_vrefresh(preferred_mode);
e7b07cee
HW		 2938 }
2939
f783577c
JFZ		 2940 if (!dm_state)
2941 drm_mode_set_crtcinfo(&mode, 0);
2942
b333730d
BL		 2943 /*
2944 * If scaling is enabled and refresh rate didn't change
2945 * we copy the vic and polarities of the old timings
2946 */
2947 if (!scale || mode_refresh != preferred_refresh)
2948 fill_stream_properties_from_drm_display_mode(stream,
2949 &mode, &aconnector->base, NULL);
2950 else
2951 fill_stream_properties_from_drm_display_mode(stream,
2952 &mode, &aconnector->base, old_stream);
2953
e7b07cee
HW		 2954 update_stream_scaling_settings(&mode, dm_state, stream);
2955
2956 fill_audio_info(
2957 &stream->audio_info,
2958 drm_connector,
aed15309 2959 sink);
e7b07cee 2960
ceb3dbb4 2961 update_stream_signal(stream, sink);
9182b4cb 2962
9e3efe3e
HW		 2963 if (dm_state && dm_state->freesync_capable)
2964 stream->ignore_msa_timing_param = true;
ecd0136b 2965
aed15309 2966finish:
fbbdadf2 2967 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON)
aed15309 2968 dc_sink_release(sink);
9e3efe3e 2969
e7b07cee
HW		 2970 return stream;
2971}
2972
7578ecda 2973static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2974{
2975 drm_crtc_cleanup(crtc);
2976 kfree(crtc);
2977}
2978
2979static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2980 struct drm_crtc_state *state)
e7b07cee
HW		 2981{
2982 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2983
2984 /* TODO Destroy dc_stream objects are stream object is flattened */
2985 if (cur->stream)
2986 dc_stream_release(cur->stream);
2987
2988
2989 __drm_atomic_helper_crtc_destroy_state(state);
2990
2991
2992 kfree(state);
2993}
2994
2995static void dm_crtc_reset_state(struct drm_crtc *crtc)
2996{
2997 struct dm_crtc_state *state;
2998
2999 if (crtc->state)
3000 dm_crtc_destroy_state(crtc, crtc->state);
3001
3002 state = kzalloc(sizeof(*state), GFP_KERNEL);
3003 if (WARN_ON(!state))
3004 return;
3005
3006 crtc->state = &state->base;
3007 crtc->state->crtc = crtc;
3008
3009}
3010
3011static struct drm_crtc_state *
3012dm_crtc_duplicate_state(struct drm_crtc *crtc)
3013{
3014 struct dm_crtc_state *state, *cur;
3015
3016 cur = to_dm_crtc_state(crtc->state);
3017
3018 if (WARN_ON(!crtc->state))
3019 return NULL;
3020
2004f45e 3021 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 3022 if (!state)
3023 return NULL;
e7b07cee
HW		 3024
3025 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3026
3027 if (cur->stream) {
3028 state->stream = cur->stream;
3029 dc_stream_retain(state->stream);
3030 }
3031
180db303 3032 state->vrr_params = cur->vrr_params;
98e6436d 3033 state->vrr_infopacket = cur->vrr_infopacket;
c1ee92f9 3034 state->abm_level = cur->abm_level;
bb47de73
NK		 3035 state->vrr_supported = cur->vrr_supported;
3036 state->freesync_config = cur->freesync_config;
ed20dc0d 3037 state->crc_enabled = cur->crc_enabled;
98e6436d 3038
e7b07cee
HW		 3039 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3040
3041 return &state->base;
3042}
3043
589d2739
HW		 3044
3045static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3046{
3047 enum dc_irq_source irq_source;
3048 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3049 struct amdgpu_device *adev = crtc->dev->dev_private;
3050
3051 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 3052 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 3053}
3054
3055static int dm_enable_vblank(struct drm_crtc *crtc)
3056{
3057 return dm_set_vblank(crtc, true);
3058}
3059
3060static void dm_disable_vblank(struct drm_crtc *crtc)
3061{
3062 dm_set_vblank(crtc, false);
3063}
3064
e7b07cee
HW		 3065/* Implemented only the options currently availible for the driver */
3066static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3067 .reset = dm_crtc_reset_state,
3068 .destroy = amdgpu_dm_crtc_destroy,
3069 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3070 .set_config = drm_atomic_helper_set_config,
3071 .page_flip = drm_atomic_helper_page_flip,
3072 .atomic_duplicate_state = dm_crtc_duplicate_state,
3073 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 3074 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 3075 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
589d2739
HW		 3076 .enable_vblank = dm_enable_vblank,
3077 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 3078};
3079
3080static enum drm_connector_status
3081amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3082{
3083 bool connected;
c84dec2f 3084 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 3085
1f6010a9
DF		 3086 /*
3087 * Notes:
e7b07cee
HW		 3088 * 1. This interface is NOT called in context of HPD irq.
3089 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 3090 * makes it a bad place for *any* MST-related activity.
3091 */
e7b07cee 3092
8580d60b
HW		 3093 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3094 !aconnector->fake_enable)
e7b07cee
HW		 3095 connected = (aconnector->dc_sink != NULL);
3096 else
3097 connected = (aconnector->base.force == DRM_FORCE_ON);
3098
3099 return (connected ? connector_status_connected :
3100 connector_status_disconnected);
3101}
3102
3ee6b26b
AD		 3103int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3104 struct drm_connector_state *connector_state,
3105 struct drm_property *property,
3106 uint64_t val)
e7b07cee
HW		 3107{
3108 struct drm_device *dev = connector->dev;
3109 struct amdgpu_device *adev = dev->dev_private;
3110 struct dm_connector_state *dm_old_state =
3111 to_dm_connector_state(connector->state);
3112 struct dm_connector_state *dm_new_state =
3113 to_dm_connector_state(connector_state);
3114
3115 int ret = -EINVAL;
3116
3117 if (property == dev->mode_config.scaling_mode_property) {
3118 enum amdgpu_rmx_type rmx_type;
3119
3120 switch (val) {
3121 case DRM_MODE_SCALE_CENTER:
3122 rmx_type = RMX_CENTER;
3123 break;
3124 case DRM_MODE_SCALE_ASPECT:
3125 rmx_type = RMX_ASPECT;
3126 break;
3127 case DRM_MODE_SCALE_FULLSCREEN:
3128 rmx_type = RMX_FULL;
3129 break;
3130 case DRM_MODE_SCALE_NONE:
3131 default:
3132 rmx_type = RMX_OFF;
3133 break;
3134 }
3135
3136 if (dm_old_state->scaling == rmx_type)
3137 return 0;
3138
3139 dm_new_state->scaling = rmx_type;
3140 ret = 0;
3141 } else if (property == adev->mode_info.underscan_hborder_property) {
3142 dm_new_state->underscan_hborder = val;
3143 ret = 0;
3144 } else if (property == adev->mode_info.underscan_vborder_property) {
3145 dm_new_state->underscan_vborder = val;
3146 ret = 0;
3147 } else if (property == adev->mode_info.underscan_property) {
3148 dm_new_state->underscan_enable = val;
3149 ret = 0;
07e3a1cf
NK		 3150 } else if (property == adev->mode_info.max_bpc_property) {
3151 dm_new_state->max_bpc = val;
3152 ret = 0;
c1ee92f9
DF		 3153 } else if (property == adev->mode_info.abm_level_property) {
3154 dm_new_state->abm_level = val;
3155 ret = 0;
e7b07cee
HW		 3156 }
3157
3158 return ret;
3159}
3160
3ee6b26b
AD		 3161int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3162 const struct drm_connector_state *state,
3163 struct drm_property *property,
3164 uint64_t *val)
e7b07cee
HW		 3165{
3166 struct drm_device *dev = connector->dev;
3167 struct amdgpu_device *adev = dev->dev_private;
3168 struct dm_connector_state *dm_state =
3169 to_dm_connector_state(state);
3170 int ret = -EINVAL;
3171
3172 if (property == dev->mode_config.scaling_mode_property) {
3173 switch (dm_state->scaling) {
3174 case RMX_CENTER:
3175 *val = DRM_MODE_SCALE_CENTER;
3176 break;
3177 case RMX_ASPECT:
3178 *val = DRM_MODE_SCALE_ASPECT;
3179 break;
3180 case RMX_FULL:
3181 *val = DRM_MODE_SCALE_FULLSCREEN;
3182 break;
3183 case RMX_OFF:
3184 default:
3185 *val = DRM_MODE_SCALE_NONE;
3186 break;
3187 }
3188 ret = 0;
3189 } else if (property == adev->mode_info.underscan_hborder_property) {
3190 *val = dm_state->underscan_hborder;
3191 ret = 0;
3192 } else if (property == adev->mode_info.underscan_vborder_property) {
3193 *val = dm_state->underscan_vborder;
3194 ret = 0;
3195 } else if (property == adev->mode_info.underscan_property) {
3196 *val = dm_state->underscan_enable;
3197 ret = 0;
07e3a1cf
NK		 3198 } else if (property == adev->mode_info.max_bpc_property) {
3199 *val = dm_state->max_bpc;
3200 ret = 0;
c1ee92f9
DF		 3201 } else if (property == adev->mode_info.abm_level_property) {
3202 *val = dm_state->abm_level;
3203 ret = 0;
e7b07cee 3204 }
c1ee92f9 3205
e7b07cee
HW		 3206 return ret;
3207}
3208
7578ecda 3209static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 3210{
c84dec2f 3211 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3212 const struct dc_link *link = aconnector->dc_link;
3213 struct amdgpu_device *adev = connector->dev->dev_private;
3214 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 3215
e7b07cee
HW		 3216#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3217 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3218
89fc8d4e 3219 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 3220 link->type != dc_connection_none &&
3221 dm->backlight_dev) {
3222 backlight_device_unregister(dm->backlight_dev);
3223 dm->backlight_dev = NULL;
e7b07cee
HW		 3224 }
3225#endif
e86e8947 3226 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 3227 drm_connector_unregister(connector);
3228 drm_connector_cleanup(connector);
3229 kfree(connector);
3230}
3231
3232void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3233{
3234 struct dm_connector_state *state =
3235 to_dm_connector_state(connector->state);
3236
df099b9b
LSL		 3237 if (connector->state)
3238 __drm_atomic_helper_connector_destroy_state(connector->state);
3239
e7b07cee
HW		 3240 kfree(state);
3241
3242 state = kzalloc(sizeof(*state), GFP_KERNEL);
3243
3244 if (state) {
3245 state->scaling = RMX_OFF;
3246 state->underscan_enable = false;
3247 state->underscan_hborder = 0;
3248 state->underscan_vborder = 0;
49f1c44b 3249 state->max_bpc = 8;
e7b07cee 3250
df099b9b 3251 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 3252 }
3253}
3254
3ee6b26b
AD		 3255struct drm_connector_state *
3256amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 3257{
3258 struct dm_connector_state *state =
3259 to_dm_connector_state(connector->state);
3260
3261 struct dm_connector_state *new_state =
3262 kmemdup(state, sizeof(*state), GFP_KERNEL);
3263
98e6436d
AK		 3264 if (!new_state)
3265 return NULL;
e7b07cee 3266
98e6436d
AK		 3267 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3268
3269 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 3270 new_state->abm_level = state->abm_level;
922454c2
NK		 3271 new_state->scaling = state->scaling;
3272 new_state->underscan_enable = state->underscan_enable;
3273 new_state->underscan_hborder = state->underscan_hborder;
3274 new_state->underscan_vborder = state->underscan_vborder;
49f1c44b 3275 new_state->max_bpc = state->max_bpc;
98e6436d
AK		 3276
3277 return &new_state->base;
e7b07cee
HW		 3278}
3279
3280static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3281 .reset = amdgpu_dm_connector_funcs_reset,
3282 .detect = amdgpu_dm_connector_detect,
3283 .fill_modes = drm_helper_probe_single_connector_modes,
3284 .destroy = amdgpu_dm_connector_destroy,
3285 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3286 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3287 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3288 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3289};
3290
e7b07cee
HW		 3291static int get_modes(struct drm_connector *connector)
3292{
3293 return amdgpu_dm_connector_get_modes(connector);
3294}
3295
c84dec2f 3296static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3297{
3298 struct dc_sink_init_data init_params = {
3299 .link = aconnector->dc_link,
3300 .sink_signal = SIGNAL_TYPE_VIRTUAL
3301 };
70e8ffc5 3302 struct edid *edid;
e7b07cee 3303
a89ff457 3304 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 3305 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3306 aconnector->base.name);
3307
3308 aconnector->base.force = DRM_FORCE_OFF;
3309 aconnector->base.override_edid = false;
3310 return;
3311 }
3312
70e8ffc5
HW		 3313 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3314
e7b07cee
HW		 3315 aconnector->edid = edid;
3316
3317 aconnector->dc_em_sink = dc_link_add_remote_sink(
3318 aconnector->dc_link,
3319 (uint8_t *)edid,
3320 (edid->extensions + 1) * EDID_LENGTH,
3321 &init_params);
3322
a68d90e7 3323 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 3324 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3325 aconnector->dc_link->local_sink :
3326 aconnector->dc_em_sink;
3327}
3328
c84dec2f 3329static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3330{
3331 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3332
1f6010a9
DF		 3333 /*
3334 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 3335 * Those settings have to be != 0 to get initial modeset
3336 */
3337 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3338 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3339 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3340 }
3341
3342
3343 aconnector->base.override_edid = true;
3344 create_eml_sink(aconnector);
3345}
3346
ba9ca088 3347enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 3348 struct drm_display_mode *mode)
e7b07cee
HW		 3349{
3350 int result = MODE_ERROR;
3351 struct dc_sink *dc_sink;
3352 struct amdgpu_device *adev = connector->dev->dev_private;
3353 /* TODO: Unhardcode stream count */
0971c40e 3354 struct dc_stream_state *stream;
c84dec2f 3355 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 3356 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 3357
3358 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3359 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3360 return result;
3361
1f6010a9
DF		 3362 /*
3363 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 3364 * EDID mgmt
3365 */
3366 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3367 !aconnector->dc_em_sink)
3368 handle_edid_mgmt(aconnector);
3369
c84dec2f 3370 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 3371
b830ebc9 3372 if (dc_sink == NULL) {
e7b07cee
HW		 3373 DRM_ERROR("dc_sink is NULL!\n");
3374 goto fail;
3375 }
3376
b333730d 3377 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
b830ebc9 3378 if (stream == NULL) {
e7b07cee
HW		 3379 DRM_ERROR("Failed to create stream for sink!\n");
3380 goto fail;
3381 }
3382
a39438f0
HW		 3383 dc_result = dc_validate_stream(adev->dm.dc, stream);
3384
3385 if (dc_result == DC_OK)
e7b07cee 3386 result = MODE_OK;
a39438f0 3387 else
9f921b14 3388 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 3389 mode->vdisplay,
3390 mode->hdisplay,
9f921b14
HW		 3391 mode->clock,
3392 dc_result);
e7b07cee
HW		 3393
3394 dc_stream_release(stream);
3395
3396fail:
3397 /* TODO: error handling*/
3398 return result;
3399}
3400
3401static const struct drm_connector_helper_funcs
3402amdgpu_dm_connector_helper_funcs = {
3403 /*
1f6010a9 3404 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 3405 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 3406 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 3407 * in get_modes call back, not just return the modes count
3408 */
e7b07cee
HW		 3409 .get_modes = get_modes,
3410 .mode_valid = amdgpu_dm_connector_mode_valid,
e7b07cee
HW		 3411};
3412
3413static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3414{
3415}
3416
3ee6b26b
AD		 3417static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3418 struct drm_crtc_state *state)
e7b07cee
HW		 3419{
3420 struct amdgpu_device *adev = crtc->dev->dev_private;
3421 struct dc *dc = adev->dm.dc;
3422 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3423 int ret = -EINVAL;
3424
9b690ef3
BL		 3425 if (unlikely(!dm_crtc_state->stream &&
3426 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 3427 WARN_ON(1);
3428 return ret;
3429 }
3430
1f6010a9 3431 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 3432 if (!dm_crtc_state->stream)
3433 return 0;
3434
62c933f9 3435 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 3436 return 0;
3437
3438 return ret;
3439}
3440
3ee6b26b
AD		 3441static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3442 const struct drm_display_mode *mode,
3443 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 3444{
3445 return true;
3446}
3447
3448static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3449 .disable = dm_crtc_helper_disable,
3450 .atomic_check = dm_crtc_helper_atomic_check,
3451 .mode_fixup = dm_crtc_helper_mode_fixup
3452};
3453
3454static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3455{
3456
3457}
3458
3ee6b26b
AD		 3459static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3460 struct drm_crtc_state *crtc_state,
3461 struct drm_connector_state *conn_state)
e7b07cee
HW		 3462{
3463 return 0;
3464}
3465
3466const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3467 .disable = dm_encoder_helper_disable,
3468 .atomic_check = dm_encoder_helper_atomic_check
3469};
3470
3471static void dm_drm_plane_reset(struct drm_plane *plane)
3472{
3473 struct dm_plane_state *amdgpu_state = NULL;
3474
3475 if (plane->state)
3476 plane->funcs->atomic_destroy_state(plane, plane->state);
3477
3478 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 3479 WARN_ON(amdgpu_state == NULL);
1f6010a9 3480
e7b07cee
HW		 3481 if (amdgpu_state) {
3482 plane->state = &amdgpu_state->base;
3483 plane->state->plane = plane;
3484 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 3485 }
e7b07cee
HW		 3486}
3487
3488static struct drm_plane_state *
3489dm_drm_plane_duplicate_state(struct drm_plane *plane)
3490{
3491 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3492
3493 old_dm_plane_state = to_dm_plane_state(plane->state);
3494 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3495 if (!dm_plane_state)
3496 return NULL;
3497
3498 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3499
3be5262e
HW		 3500 if (old_dm_plane_state->dc_state) {
3501 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3502 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 3503 }
3504
3505 return &dm_plane_state->base;
3506}
3507
3508void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 3509 struct drm_plane_state *state)
e7b07cee
HW		 3510{
3511 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3512
3be5262e
HW		 3513 if (dm_plane_state->dc_state)
3514 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 3515
0627bbd3 3516 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 3517}
3518
3519static const struct drm_plane_funcs dm_plane_funcs = {
3520 .update_plane = drm_atomic_helper_update_plane,
3521 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 3522 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 3523 .reset = dm_drm_plane_reset,
3524 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3525 .atomic_destroy_state = dm_drm_plane_destroy_state,
3526};
3527
3ee6b26b
AD		 3528static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3529 struct drm_plane_state *new_state)
e7b07cee
HW		 3530{
3531 struct amdgpu_framebuffer *afb;
3532 struct drm_gem_object *obj;
5d43be0c 3533 struct amdgpu_device *adev;
e7b07cee 3534 struct amdgpu_bo *rbo;
56087b31 3535 uint64_t chroma_addr = 0;
e7b07cee
HW		 3536 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3537 unsigned int awidth;
5d43be0c
CK		 3538 uint32_t domain;
3539 int r;
e7b07cee
HW		 3540
3541 dm_plane_state_old = to_dm_plane_state(plane->state);
3542 dm_plane_state_new = to_dm_plane_state(new_state);
3543
3544 if (!new_state->fb) {
f1ad2f5e 3545 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3546 return 0;
3547 }
3548
3549 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 3550 obj = new_state->fb->obj[0];
e7b07cee 3551 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3552 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3553 r = amdgpu_bo_reserve(rbo, false);
3554 if (unlikely(r != 0))
3555 return r;
3556
5d43be0c 3557 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 3558 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 3559 else
3560 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3561
7b7c6c81 3562 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 3563 if (unlikely(r != 0)) {
30b7c614
HW		 3564 if (r != -ERESTARTSYS)
3565 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
bb812f1e 3566 amdgpu_bo_unreserve(rbo);
e7b07cee
HW		 3567 return r;
3568 }
3569
bb812f1e
JZ		 3570 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3571 if (unlikely(r != 0)) {
3572 amdgpu_bo_unpin(rbo);
3573 amdgpu_bo_unreserve(rbo);
3574 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 3575 return r;
3576 }
bb812f1e
JZ		 3577 amdgpu_bo_unreserve(rbo);
3578
7b7c6c81 3579 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 3580
3581 amdgpu_bo_ref(rbo);
3582
3be5262e
HW		 3583 if (dm_plane_state_new->dc_state &&
3584 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3585 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3586
3be5262e
HW		 3587 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3588 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3589 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 3590 } else {
3591 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3592 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3593 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3594 = lower_32_bits(afb->address);
56087b31
S		 3595 plane_state->address.video_progressive.luma_addr.high_part
3596 = upper_32_bits(afb->address);
35888630 3597 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3598 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3599 = lower_32_bits(chroma_addr);
3600 plane_state->address.video_progressive.chroma_addr.high_part
3601 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3602 }
3603 }
3604
e7b07cee
HW		 3605 return 0;
3606}
3607
3ee6b26b
AD		 3608static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3609 struct drm_plane_state *old_state)
e7b07cee
HW		 3610{
3611 struct amdgpu_bo *rbo;
e7b07cee
HW		 3612 int r;
3613
3614 if (!old_state->fb)
3615 return;
3616
e68d14dd 3617 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 3618 r = amdgpu_bo_reserve(rbo, false);
3619 if (unlikely(r)) {
3620 DRM_ERROR("failed to reserve rbo before unpin\n");
3621 return;
b830ebc9
HW		 3622 }
3623
3624 amdgpu_bo_unpin(rbo);
3625 amdgpu_bo_unreserve(rbo);
3626 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3627}
3628
7578ecda
AD		 3629static int dm_plane_atomic_check(struct drm_plane *plane,
3630 struct drm_plane_state *state)
cbd19488
AG		 3631{
3632 struct amdgpu_device *adev = plane->dev->dev_private;
3633 struct dc *dc = adev->dm.dc;
3634 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3635
3be5262e 3636 if (!dm_plane_state->dc_state)
9a3329b1 3637 return 0;
cbd19488 3638
a05bcff1
S		 3639 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3640 return -EINVAL;
3641
62c933f9 3642 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3643 return 0;
3644
3645 return -EINVAL;
3646}
3647
674e78ac
NK		 3648static int dm_plane_atomic_async_check(struct drm_plane *plane,
3649 struct drm_plane_state *new_plane_state)
3650{
77acd1cd
NK		 3651 struct drm_plane_state *old_plane_state =
3652 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
3653
674e78ac
NK		 3654 /* Only support async updates on cursor planes. */
3655 if (plane->type != DRM_PLANE_TYPE_CURSOR)
3656 return -EINVAL;
3657
77acd1cd
NK		 3658 /*
3659 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
3660 * async commits so don't allow fb changes.
3661 */
3662 if (old_plane_state->fb != new_plane_state->fb)
3663 return -EINVAL;
3664
674e78ac
NK		 3665 return 0;
3666}
3667
3668static void dm_plane_atomic_async_update(struct drm_plane *plane,
3669 struct drm_plane_state *new_state)
3670{
3671 struct drm_plane_state *old_state =
3672 drm_atomic_get_old_plane_state(new_state->state, plane);
3673
3674 if (plane->state->fb != new_state->fb)
3675 drm_atomic_set_fb_for_plane(plane->state, new_state->fb);
3676
3677 plane->state->src_x = new_state->src_x;
3678 plane->state->src_y = new_state->src_y;
3679 plane->state->src_w = new_state->src_w;
3680 plane->state->src_h = new_state->src_h;
3681 plane->state->crtc_x = new_state->crtc_x;
3682 plane->state->crtc_y = new_state->crtc_y;
3683 plane->state->crtc_w = new_state->crtc_w;
3684 plane->state->crtc_h = new_state->crtc_h;
3685
3686 handle_cursor_update(plane, old_state);
3687}
3688
e7b07cee
HW		 3689static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3690 .prepare_fb = dm_plane_helper_prepare_fb,
3691 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3692 .atomic_check = dm_plane_atomic_check,
674e78ac
NK		 3693 .atomic_async_check = dm_plane_atomic_async_check,
3694 .atomic_async_update = dm_plane_atomic_async_update
e7b07cee
HW		 3695};
3696
3697/*
3698 * TODO: these are currently initialized to rgb formats only.
3699 * For future use cases we should either initialize them dynamically based on
3700 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 3701 * check will succeed, and let DC implement proper check
e7b07cee 3702 */
d90371b0 3703static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3704 DRM_FORMAT_RGB888,
3705 DRM_FORMAT_XRGB8888,
3706 DRM_FORMAT_ARGB8888,
3707 DRM_FORMAT_RGBA8888,
3708 DRM_FORMAT_XRGB2101010,
3709 DRM_FORMAT_XBGR2101010,
3710 DRM_FORMAT_ARGB2101010,
3711 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 3712 DRM_FORMAT_XBGR8888,
3713 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 3714};
3715
99d1abf8 3716static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3717 DRM_FORMAT_NV12,
3718 DRM_FORMAT_NV21,
3719};
3720
3721static const u32 cursor_formats[] = {
3722 DRM_FORMAT_ARGB8888
3723};
3724
7578ecda 3725static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 3726 struct drm_plane *plane,
7578ecda 3727 unsigned long possible_crtcs)
e7b07cee
HW		 3728{
3729 int res = -EPERM;
3730
f180b4bc 3731 switch (plane->type) {
e7b07cee 3732 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3733 res = drm_universal_plane_init(
3734 dm->adev->ddev,
f180b4bc 3735 plane,
e7b07cee
HW		 3736 possible_crtcs,
3737 &dm_plane_funcs,
3738 rgb_formats,
3739 ARRAY_SIZE(rgb_formats),
f180b4bc 3740 NULL, plane->type, NULL);
e7b07cee
HW		 3741 break;
3742 case DRM_PLANE_TYPE_OVERLAY:
3743 res = drm_universal_plane_init(
3744 dm->adev->ddev,
f180b4bc 3745 plane,
e7b07cee
HW		 3746 possible_crtcs,
3747 &dm_plane_funcs,
3748 yuv_formats,
3749 ARRAY_SIZE(yuv_formats),
f180b4bc 3750 NULL, plane->type, NULL);
e7b07cee
HW		 3751 break;
3752 case DRM_PLANE_TYPE_CURSOR:
3753 res = drm_universal_plane_init(
3754 dm->adev->ddev,
f180b4bc 3755 plane,
e7b07cee
HW		 3756 possible_crtcs,
3757 &dm_plane_funcs,
3758 cursor_formats,
3759 ARRAY_SIZE(cursor_formats),
f180b4bc 3760 NULL, plane->type, NULL);
e7b07cee
HW		 3761 break;
3762 }
3763
f180b4bc 3764 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 3765
96719c54 3766 /* Create (reset) the plane state */
f180b4bc
HW		 3767 if (plane->funcs->reset)
3768 plane->funcs->reset(plane);
96719c54
HW		 3769
3770
e7b07cee
HW		 3771 return res;
3772}
3773
7578ecda
AD		 3774static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3775 struct drm_plane *plane,
3776 uint32_t crtc_index)
e7b07cee
HW		 3777{
3778 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 3779 struct drm_plane *cursor_plane;
e7b07cee
HW		 3780
3781 int res = -ENOMEM;
3782
3783 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3784 if (!cursor_plane)
3785 goto fail;
3786
f180b4bc 3787 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
e7b07cee
HW		 3788 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3789
3790 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3791 if (!acrtc)
3792 goto fail;
3793
3794 res = drm_crtc_init_with_planes(
3795 dm->ddev,
3796 &acrtc->base,
3797 plane,
f180b4bc 3798 cursor_plane,
e7b07cee
HW		 3799 &amdgpu_dm_crtc_funcs, NULL);
3800
3801 if (res)
3802 goto fail;
3803
3804 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3805
96719c54
HW		 3806 /* Create (reset) the plane state */
3807 if (acrtc->base.funcs->reset)
3808 acrtc->base.funcs->reset(&acrtc->base);
3809
e7b07cee
HW		 3810 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3811 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3812
3813 acrtc->crtc_id = crtc_index;
3814 acrtc->base.enabled = false;
c37e2d29 3815 acrtc->otg_inst = -1;
e7b07cee
HW		 3816
3817 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3818 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3819 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3820 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3821
3822 return 0;
3823
3824fail:
b830ebc9
HW		 3825 kfree(acrtc);
3826 kfree(cursor_plane);
e7b07cee
HW		 3827 return res;
3828}
3829
3830
3831static int to_drm_connector_type(enum signal_type st)
3832{
3833 switch (st) {
3834 case SIGNAL_TYPE_HDMI_TYPE_A:
3835 return DRM_MODE_CONNECTOR_HDMIA;
3836 case SIGNAL_TYPE_EDP:
3837 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 3838 case SIGNAL_TYPE_LVDS:
3839 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 3840 case SIGNAL_TYPE_RGB:
3841 return DRM_MODE_CONNECTOR_VGA;
3842 case SIGNAL_TYPE_DISPLAY_PORT:
3843 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3844 return DRM_MODE_CONNECTOR_DisplayPort;
3845 case SIGNAL_TYPE_DVI_DUAL_LINK:
3846 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3847 return DRM_MODE_CONNECTOR_DVID;
3848 case SIGNAL_TYPE_VIRTUAL:
3849 return DRM_MODE_CONNECTOR_VIRTUAL;
3850
3851 default:
3852 return DRM_MODE_CONNECTOR_Unknown;
3853 }
3854}
3855
2b4c1c05
DV		 3856static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
3857{
3858 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
3859}
3860
e7b07cee
HW		 3861static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3862{
e7b07cee
HW		 3863 struct drm_encoder *encoder;
3864 struct amdgpu_encoder *amdgpu_encoder;
3865
2b4c1c05 3866 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 3867
3868 if (encoder == NULL)
3869 return;
3870
3871 amdgpu_encoder = to_amdgpu_encoder(encoder);
3872
3873 amdgpu_encoder->native_mode.clock = 0;
3874
3875 if (!list_empty(&connector->probed_modes)) {
3876 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3877
e7b07cee 3878 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3879 &connector->probed_modes,
3880 head) {
3881 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3882 amdgpu_encoder->native_mode = *preferred_mode;
3883
e7b07cee
HW		 3884 break;
3885 }
3886
3887 }
3888}
3889
3ee6b26b
AD		 3890static struct drm_display_mode *
3891amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3892 char *name,
3893 int hdisplay, int vdisplay)
e7b07cee
HW		 3894{
3895 struct drm_device *dev = encoder->dev;
3896 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3897 struct drm_display_mode *mode = NULL;
3898 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3899
3900 mode = drm_mode_duplicate(dev, native_mode);
3901
b830ebc9 3902 if (mode == NULL)
e7b07cee
HW		 3903 return NULL;
3904
3905 mode->hdisplay = hdisplay;
3906 mode->vdisplay = vdisplay;
3907 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 3908 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 3909
3910 return mode;
3911
3912}
3913
3914static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3915 struct drm_connector *connector)
e7b07cee
HW		 3916{
3917 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3918 struct drm_display_mode *mode = NULL;
3919 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3920 struct amdgpu_dm_connector *amdgpu_dm_connector =
3921 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3922 int i;
3923 int n;
3924 struct mode_size {
3925 char name[DRM_DISPLAY_MODE_LEN];
3926 int w;
3927 int h;
b830ebc9 3928 } common_modes[] = {
e7b07cee
HW		 3929 { "640x480", 640, 480},
3930 { "800x600", 800, 600},
3931 { "1024x768", 1024, 768},
3932 { "1280x720", 1280, 720},
3933 { "1280x800", 1280, 800},
3934 {"1280x1024", 1280, 1024},
3935 { "1440x900", 1440, 900},
3936 {"1680x1050", 1680, 1050},
3937 {"1600x1200", 1600, 1200},
3938 {"1920x1080", 1920, 1080},
3939 {"1920x1200", 1920, 1200}
3940 };
3941
b830ebc9 3942 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3943
3944 for (i = 0; i < n; i++) {
3945 struct drm_display_mode *curmode = NULL;
3946 bool mode_existed = false;
3947
3948 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3949 common_modes[i].h > native_mode->vdisplay ||
3950 (common_modes[i].w == native_mode->hdisplay &&
3951 common_modes[i].h == native_mode->vdisplay))
3952 continue;
e7b07cee
HW		 3953
3954 list_for_each_entry(curmode, &connector->probed_modes, head) {
3955 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3956 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3957 mode_existed = true;
3958 break;
3959 }
3960 }
3961
3962 if (mode_existed)
3963 continue;
3964
3965 mode = amdgpu_dm_create_common_mode(encoder,
3966 common_modes[i].name, common_modes[i].w,
3967 common_modes[i].h);
3968 drm_mode_probed_add(connector, mode);
c84dec2f 3969 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3970 }
3971}
3972
3ee6b26b
AD		 3973static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3974 struct edid *edid)
e7b07cee 3975{
c84dec2f
HW		 3976 struct amdgpu_dm_connector *amdgpu_dm_connector =
3977 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3978
3979 if (edid) {
3980 /* empty probed_modes */
3981 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3982 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3983 drm_add_edid_modes(connector, edid);
3984
e7b07cee 3985 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3986 } else {
c84dec2f 3987 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3988 }
e7b07cee
HW		 3989}
3990
7578ecda 3991static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 3992{
c84dec2f
HW		 3993 struct amdgpu_dm_connector *amdgpu_dm_connector =
3994 to_amdgpu_dm_connector(connector);
e7b07cee 3995 struct drm_encoder *encoder;
c84dec2f 3996 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 3997
2b4c1c05 3998 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 3999
85ee15d6 4000 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 4001 amdgpu_dm_connector->num_modes =
4002 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 4003 } else {
4004 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4005 amdgpu_dm_connector_add_common_modes(encoder, connector);
4006 }
3e332d3a 4007 amdgpu_dm_fbc_init(connector);
5099114b 4008
c84dec2f 4009 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 4010}
4011
3ee6b26b
AD		 4012void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4013 struct amdgpu_dm_connector *aconnector,
4014 int connector_type,
4015 struct dc_link *link,
4016 int link_index)
e7b07cee
HW		 4017{
4018 struct amdgpu_device *adev = dm->ddev->dev_private;
4019
4020 aconnector->connector_id = link_index;
4021 aconnector->dc_link = link;
4022 aconnector->base.interlace_allowed = false;
4023 aconnector->base.doublescan_allowed = false;
4024 aconnector->base.stereo_allowed = false;
4025 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4026 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
e7b07cee
HW		 4027 mutex_init(&aconnector->hpd_lock);
4028
1f6010a9
DF		 4029 /*
4030 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 4031 * which means HPD hot plug not supported
4032 */
e7b07cee
HW		 4033 switch (connector_type) {
4034 case DRM_MODE_CONNECTOR_HDMIA:
4035 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4036 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4037 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 4038 break;
4039 case DRM_MODE_CONNECTOR_DisplayPort:
4040 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4041 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4042 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 4043 break;
4044 case DRM_MODE_CONNECTOR_DVID:
4045 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4046 break;
4047 default:
4048 break;
4049 }
4050
4051 drm_object_attach_property(&aconnector->base.base,
4052 dm->ddev->mode_config.scaling_mode_property,
4053 DRM_MODE_SCALE_NONE);
4054
4055 drm_object_attach_property(&aconnector->base.base,
4056 adev->mode_info.underscan_property,
4057 UNDERSCAN_OFF);
4058 drm_object_attach_property(&aconnector->base.base,
4059 adev->mode_info.underscan_hborder_property,
4060 0);
4061 drm_object_attach_property(&aconnector->base.base,
4062 adev->mode_info.underscan_vborder_property,
4063 0);
07e3a1cf
NK		 4064 drm_object_attach_property(&aconnector->base.base,
4065 adev->mode_info.max_bpc_property,
4066 0);
e7b07cee 4067
c1ee92f9
DF		 4068 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4069 dc_is_dmcu_initialized(adev->dm.dc)) {
4070 drm_object_attach_property(&aconnector->base.base,
4071 adev->mode_info.abm_level_property, 0);
4072 }
bb47de73
NK		 4073
4074 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
4075 connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
4076 drm_connector_attach_vrr_capable_property(
4077 &aconnector->base);
4078 }
e7b07cee
HW		 4079}
4080
7578ecda
AD		 4081static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4082 struct i2c_msg *msgs, int num)
e7b07cee
HW		 4083{
4084 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4085 struct ddc_service *ddc_service = i2c->ddc_service;
4086 struct i2c_command cmd;
4087 int i;
4088 int result = -EIO;
4089
b830ebc9 4090 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 4091
4092 if (!cmd.payloads)
4093 return result;
4094
4095 cmd.number_of_payloads = num;
4096 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4097 cmd.speed = 100;
4098
4099 for (i = 0; i < num; i++) {
4100 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4101 cmd.payloads[i].address = msgs[i].addr;
4102 cmd.payloads[i].length = msgs[i].len;
4103 cmd.payloads[i].data = msgs[i].buf;
4104 }
4105
c85e6e54
DF		 4106 if (dc_submit_i2c(
4107 ddc_service->ctx->dc,
4108 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 4109 &cmd))
4110 result = num;
4111
4112 kfree(cmd.payloads);
4113 return result;
4114}
4115
7578ecda 4116static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 4117{
4118 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4119}
4120
4121static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4122 .master_xfer = amdgpu_dm_i2c_xfer,
4123 .functionality = amdgpu_dm_i2c_func,
4124};
4125
3ee6b26b
AD		 4126static struct amdgpu_i2c_adapter *
4127create_i2c(struct ddc_service *ddc_service,
4128 int link_index,
4129 int *res)
e7b07cee
HW		 4130{
4131 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4132 struct amdgpu_i2c_adapter *i2c;
4133
b830ebc9 4134 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 4135 if (!i2c)
4136 return NULL;
e7b07cee
HW		 4137 i2c->base.owner = THIS_MODULE;
4138 i2c->base.class = I2C_CLASS_DDC;
4139 i2c->base.dev.parent = &adev->pdev->dev;
4140 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 4141 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 4142 i2c_set_adapdata(&i2c->base, i2c);
4143 i2c->ddc_service = ddc_service;
c85e6e54 4144 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 4145
4146 return i2c;
4147}
4148
89fc8d4e 4149
1f6010a9
DF		 4150/*
4151 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 4152 * dc_link which will be represented by this aconnector.
4153 */
7578ecda
AD		 4154static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4155 struct amdgpu_dm_connector *aconnector,
4156 uint32_t link_index,
4157 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 4158{
4159 int res = 0;
4160 int connector_type;
4161 struct dc *dc = dm->dc;
4162 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4163 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 4164
4165 link->priv = aconnector;
e7b07cee 4166
f1ad2f5e 4167 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 4168
4169 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 4170 if (!i2c) {
4171 DRM_ERROR("Failed to create i2c adapter data\n");
4172 return -ENOMEM;
4173 }
4174
e7b07cee
HW		 4175 aconnector->i2c = i2c;
4176 res = i2c_add_adapter(&i2c->base);
4177
4178 if (res) {
4179 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4180 goto out_free;
4181 }
4182
4183 connector_type = to_drm_connector_type(link->connector_signal);
4184
4185 res = drm_connector_init(
4186 dm->ddev,
4187 &aconnector->base,
4188 &amdgpu_dm_connector_funcs,
4189 connector_type);
4190
4191 if (res) {
4192 DRM_ERROR("connector_init failed\n");
4193 aconnector->connector_id = -1;
4194 goto out_free;
4195 }
4196
4197 drm_connector_helper_add(
4198 &aconnector->base,
4199 &amdgpu_dm_connector_helper_funcs);
4200
96719c54
HW		 4201 if (aconnector->base.funcs->reset)
4202 aconnector->base.funcs->reset(&aconnector->base);
4203
e7b07cee
HW		 4204 amdgpu_dm_connector_init_helper(
4205 dm,
4206 aconnector,
4207 connector_type,
4208 link,
4209 link_index);
4210
cde4c44d 4211 drm_connector_attach_encoder(
e7b07cee
HW		 4212 &aconnector->base, &aencoder->base);
4213
4214 drm_connector_register(&aconnector->base);
dc38fd9d
DF		 4215#if defined(CONFIG_DEBUG_FS)
4216 res = connector_debugfs_init(aconnector);
4217 if (res) {
4218 DRM_ERROR("Failed to create debugfs for connector");
4219 goto out_free;
4220 }
4221#endif
e7b07cee
HW		 4222
4223 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4224 || connector_type == DRM_MODE_CONNECTOR_eDP)
4225 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4226
e7b07cee
HW		 4227out_free:
4228 if (res) {
4229 kfree(i2c);
4230 aconnector->i2c = NULL;
4231 }
4232 return res;
4233}
4234
4235int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4236{
4237 switch (adev->mode_info.num_crtc) {
4238 case 1:
4239 return 0x1;
4240 case 2:
4241 return 0x3;
4242 case 3:
4243 return 0x7;
4244 case 4:
4245 return 0xf;
4246 case 5:
4247 return 0x1f;
4248 case 6:
4249 default:
4250 return 0x3f;
4251 }
4252}
4253
7578ecda
AD		 4254static int amdgpu_dm_encoder_init(struct drm_device *dev,
4255 struct amdgpu_encoder *aencoder,
4256 uint32_t link_index)
e7b07cee
HW		 4257{
4258 struct amdgpu_device *adev = dev->dev_private;
4259
4260 int res = drm_encoder_init(dev,
4261 &aencoder->base,
4262 &amdgpu_dm_encoder_funcs,
4263 DRM_MODE_ENCODER_TMDS,
4264 NULL);
4265
4266 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4267
4268 if (!res)
4269 aencoder->encoder_id = link_index;
4270 else
4271 aencoder->encoder_id = -1;
4272
4273 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4274
4275 return res;
4276}
4277
3ee6b26b
AD		 4278static void manage_dm_interrupts(struct amdgpu_device *adev,
4279 struct amdgpu_crtc *acrtc,
4280 bool enable)
e7b07cee
HW		 4281{
4282 /*
4283 * this is not correct translation but will work as soon as VBLANK
4284 * constant is the same as PFLIP
4285 */
4286 int irq_type =
734dd01d 4287 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 4288 adev,
4289 acrtc->crtc_id);
4290
4291 if (enable) {
4292 drm_crtc_vblank_on(&acrtc->base);
4293 amdgpu_irq_get(
4294 adev,
4295 &adev->pageflip_irq,
4296 irq_type);
4297 } else {
4298
4299 amdgpu_irq_put(
4300 adev,
4301 &adev->pageflip_irq,
4302 irq_type);
4303 drm_crtc_vblank_off(&acrtc->base);
4304 }
4305}
4306
3ee6b26b
AD		 4307static bool
4308is_scaling_state_different(const struct dm_connector_state *dm_state,
4309 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 4310{
4311 if (dm_state->scaling != old_dm_state->scaling)
4312 return true;
4313 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4314 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4315 return true;
4316 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4317 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4318 return true;
b830ebc9
HW		 4319 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4320 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4321 return true;
e7b07cee
HW		 4322 return false;
4323}
4324
3ee6b26b
AD		 4325static void remove_stream(struct amdgpu_device *adev,
4326 struct amdgpu_crtc *acrtc,
4327 struct dc_stream_state *stream)
e7b07cee
HW		 4328{
4329 /* this is the update mode case */
e7b07cee
HW		 4330
4331 acrtc->otg_inst = -1;
4332 acrtc->enabled = false;
4333}
4334
7578ecda
AD		 4335static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4336 struct dc_cursor_position *position)
2a8f6ccb 4337{
f4c2cc43 4338 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 4339 int x, y;
4340 int xorigin = 0, yorigin = 0;
4341
4342 if (!crtc || !plane->state->fb) {
4343 position->enable = false;
4344 position->x = 0;
4345 position->y = 0;
4346 return 0;
4347 }
4348
4349 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4350 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4351 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4352 __func__,
4353 plane->state->crtc_w,
4354 plane->state->crtc_h);
4355 return -EINVAL;
4356 }
4357
4358 x = plane->state->crtc_x;
4359 y = plane->state->crtc_y;
4360 /* avivo cursor are offset into the total surface */
4361 x += crtc->primary->state->src_x >> 16;
4362 y += crtc->primary->state->src_y >> 16;
4363 if (x < 0) {
4364 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4365 x = 0;
4366 }
4367 if (y < 0) {
4368 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4369 y = 0;
4370 }
4371 position->enable = true;
4372 position->x = x;
4373 position->y = y;
4374 position->x_hotspot = xorigin;
4375 position->y_hotspot = yorigin;
4376
4377 return 0;
4378}
4379
3ee6b26b
AD		 4380static void handle_cursor_update(struct drm_plane *plane,
4381 struct drm_plane_state *old_plane_state)
e7b07cee 4382{
674e78ac 4383 struct amdgpu_device *adev = plane->dev->dev_private;
2a8f6ccb
HW		 4384 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4385 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4386 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4387 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4388 uint64_t address = afb ? afb->address : 0;
4389 struct dc_cursor_position position;
4390 struct dc_cursor_attributes attributes;
4391 int ret;
4392
e7b07cee
HW		 4393 if (!plane->state->fb && !old_plane_state->fb)
4394 return;
4395
f1ad2f5e 4396 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 4397 __func__,
4398 amdgpu_crtc->crtc_id,
4399 plane->state->crtc_w,
4400 plane->state->crtc_h);
2a8f6ccb
HW		 4401
4402 ret = get_cursor_position(plane, crtc, &position);
4403 if (ret)
4404 return;
4405
4406 if (!position.enable) {
4407 /* turn off cursor */
674e78ac
NK		 4408 if (crtc_state && crtc_state->stream) {
4409 mutex_lock(&adev->dm.dc_lock);
2a8f6ccb
HW		 4410 dc_stream_set_cursor_position(crtc_state->stream,
4411 &position);
674e78ac
NK		 4412 mutex_unlock(&adev->dm.dc_lock);
4413 }
2a8f6ccb 4414 return;
e7b07cee 4415 }
e7b07cee 4416
2a8f6ccb
HW		 4417 amdgpu_crtc->cursor_width = plane->state->crtc_w;
4418 amdgpu_crtc->cursor_height = plane->state->crtc_h;
4419
4420 attributes.address.high_part = upper_32_bits(address);
4421 attributes.address.low_part = lower_32_bits(address);
4422 attributes.width = plane->state->crtc_w;
4423 attributes.height = plane->state->crtc_h;
4424 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4425 attributes.rotation_angle = 0;
4426 attributes.attribute_flags.value = 0;
4427
4428 attributes.pitch = attributes.width;
4429
886daac9 4430 if (crtc_state->stream) {
674e78ac 4431 mutex_lock(&adev->dm.dc_lock);
886daac9
JZ		 4432 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4433 &attributes))
4434 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 4435
2a8f6ccb
HW		 4436 if (!dc_stream_set_cursor_position(crtc_state->stream,
4437 &position))
4438 DRM_ERROR("DC failed to set cursor position\n");
674e78ac 4439 mutex_unlock(&adev->dm.dc_lock);
886daac9 4440 }
2a8f6ccb 4441}
e7b07cee
HW		 4442
4443static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4444{
4445
4446 assert_spin_locked(&acrtc->base.dev->event_lock);
4447 WARN_ON(acrtc->event);
4448
4449 acrtc->event = acrtc->base.state->event;
4450
4451 /* Set the flip status */
4452 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4453
4454 /* Mark this event as consumed */
4455 acrtc->base.state->event = NULL;
4456
4457 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4458 acrtc->crtc_id);
4459}
4460
eb3dc897
NK		 4461struct dc_stream_status *dc_state_get_stream_status(
4462 struct dc_state *state,
4463 struct dc_stream_state *stream)
4464{
4465 uint8_t i;
4466
4467 for (i = 0; i < state->stream_count; i++) {
4468 if (stream == state->streams[i])
4469 return &state->stream_status[i];
4470 }
4471
4472 return NULL;
4473}
4474
bb47de73
NK		 4475static void update_freesync_state_on_stream(
4476 struct amdgpu_display_manager *dm,
4477 struct dm_crtc_state *new_crtc_state,
180db303
NK		 4478 struct dc_stream_state *new_stream,
4479 struct dc_plane_state *surface,
4480 u32 flip_timestamp_in_us)
bb47de73 4481{
180db303 4482 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params;
bb47de73
NK		 4483 struct dc_info_packet vrr_infopacket = {0};
4484 struct mod_freesync_config config = new_crtc_state->freesync_config;
4485
4486 if (!new_stream)
4487 return;
4488
4489 /*
4490 * TODO: Determine why min/max totals and vrefresh can be 0 here.
4491 * For now it's sufficient to just guard against these conditions.
4492 */
4493
4494 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
4495 return;
4496
4497 if (new_crtc_state->vrr_supported &&
4498 config.min_refresh_in_uhz &&
4499 config.max_refresh_in_uhz) {
4500 config.state = new_crtc_state->base.vrr_enabled ?
4501 VRR_STATE_ACTIVE_VARIABLE :
4502 VRR_STATE_INACTIVE;
4503 } else {
4504 config.state = VRR_STATE_UNSUPPORTED;
4505 }
4506
4507 mod_freesync_build_vrr_params(dm->freesync_module,
4508 new_stream,
180db303
NK		 4509 &config, &vrr_params);
4510
4511 if (surface) {
4512 mod_freesync_handle_preflip(
4513 dm->freesync_module,
4514 surface,
4515 new_stream,
4516 flip_timestamp_in_us,
4517 &vrr_params);
4518 }
bb47de73
NK		 4519
4520 mod_freesync_build_vrr_infopacket(
4521 dm->freesync_module,
4522 new_stream,
180db303 4523 &vrr_params,
ecd0136b
HT		 4524 PACKET_TYPE_VRR,
4525 TRANSFER_FUNC_UNKNOWN,
bb47de73
NK		 4526 &vrr_infopacket);
4527
4528 new_crtc_state->freesync_timing_changed =
180db303
NK		 4529 (memcmp(&new_crtc_state->vrr_params.adjust,
4530 &vrr_params.adjust,
4531 sizeof(vrr_params.adjust)) != 0);
bb47de73
NK		 4532
4533 new_crtc_state->freesync_vrr_info_changed =
4534 (memcmp(&new_crtc_state->vrr_infopacket,
4535 &vrr_infopacket,
4536 sizeof(vrr_infopacket)) != 0);
4537
180db303 4538 new_crtc_state->vrr_params = vrr_params;
bb47de73
NK		 4539 new_crtc_state->vrr_infopacket = vrr_infopacket;
4540
180db303 4541 new_stream->adjust = new_crtc_state->vrr_params.adjust;
bb47de73
NK		 4542 new_stream->vrr_infopacket = vrr_infopacket;
4543
4544 if (new_crtc_state->freesync_vrr_info_changed)
4545 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
4546 new_crtc_state->base.crtc->base.id,
4547 (int)new_crtc_state->base.vrr_enabled,
180db303 4548 (int)vrr_params.state);
bb47de73
NK		 4549
4550 if (new_crtc_state->freesync_timing_changed)
4551 DRM_DEBUG_KMS("VRR timing update: crtc=%u min=%u max=%u\n",
4552 new_crtc_state->base.crtc->base.id,
180db303
NK		 4553 vrr_params.adjust.v_total_min,
4554 vrr_params.adjust.v_total_max);
bb47de73
NK		 4555}
4556
e7b07cee
HW		 4557/*
4558 * Executes flip
4559 *
4560 * Waits on all BO's fences and for proper vblank count
4561 */
3ee6b26b
AD		 4562static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
4563 struct drm_framebuffer *fb,
bc6828e0
BL		 4564 uint32_t target,
4565 struct dc_state *state)
e7b07cee
HW		 4566{
4567 unsigned long flags;
9136e81e 4568 uint64_t timestamp_ns;
e7b07cee
HW		 4569 uint32_t target_vblank;
4570 int r, vpos, hpos;
4571 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4572 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
e68d14dd 4573 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
e7b07cee 4574 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 4575 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 4576 struct dc_flip_addrs addr = { {0} };
3be5262e 4577 /* TODO eliminate or rename surface_update */
e7b07cee 4578 struct dc_surface_update surface_updates[1] = { {0} };
bb47de73 4579 struct dc_stream_update stream_update = {0};
e7b07cee 4580 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
d999853e 4581 struct dc_stream_status *stream_status;
180db303 4582 struct dc_plane_state *surface;
e7b07cee
HW		 4583
4584
4585 /* Prepare wait for target vblank early - before the fence-waits */
23effc11 4586 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
e7b07cee
HW		 4587 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
4588
1f6010a9
DF		 4589 /*
4590 * TODO This might fail and hence better not used, wait
e7b07cee
HW		 4591 * explicitly on fences instead
4592 * and in general should be called for
4593 * blocking commit to as per framework helpers
b830ebc9 4594 */
e7b07cee
HW		 4595 r = amdgpu_bo_reserve(abo, true);
4596 if (unlikely(r != 0)) {
4597 DRM_ERROR("failed to reserve buffer before flip\n");
4598 WARN_ON(1);
4599 }
4600
4601 /* Wait for all fences on this FB */
4602 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
4603 MAX_SCHEDULE_TIMEOUT) < 0);
4604
4605 amdgpu_bo_unreserve(abo);
4606
1f6010a9
DF		 4607 /*
4608 * Wait until we're out of the vertical blank period before the one
e7b07cee
HW		 4609 * targeted by the flip
4610 */
4611 while ((acrtc->enabled &&
aa8e286a
SL		 4612 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
4613 0, &vpos, &hpos, NULL,
4614 NULL, &crtc->hwmode)
e7b07cee
HW		 4615 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4616 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4617 (int)(target_vblank -
4618 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
4619 usleep_range(1000, 1100);
4620 }
4621
4622 /* Flip */
4623 spin_lock_irqsave(&crtc->dev->event_lock, flags);
e7b07cee
HW		 4624
4625 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
4626 WARN_ON(!acrtc_state->stream);
4627
4628 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
4629 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
4630 addr.flip_immediate = async_flip;
4631
9136e81e
NK		 4632 timestamp_ns = ktime_get_ns();
4633 addr.flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
e7b07cee
HW		 4634
4635
4636 if (acrtc->base.state->event)
4637 prepare_flip_isr(acrtc);
4638
4de9f38b
S		 4639 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4640
d999853e
NK		 4641 stream_status = dc_stream_get_status(acrtc_state->stream);
4642 if (!stream_status) {
4643 DRM_ERROR("No stream status for CRTC: id=%d\n",
4644 acrtc->crtc_id);
4645 return;
4646 }
4647
180db303
NK		 4648 surface = stream_status->plane_states[0];
4649 surface_updates->surface = surface;
4650
4651 if (!surface) {
d999853e
NK		 4652 DRM_ERROR("No surface for CRTC: id=%d\n",
4653 acrtc->crtc_id);
4654 return;
4655 }
e7b07cee
HW		 4656 surface_updates->flip_addr = &addr;
4657
bb47de73
NK		 4658 if (acrtc_state->stream) {
4659 update_freesync_state_on_stream(
4660 &adev->dm,
4661 acrtc_state,
180db303
NK		 4662 acrtc_state->stream,
4663 surface,
4664 addr.flip_timestamp_in_us);
bb47de73
NK		 4665
4666 if (acrtc_state->freesync_timing_changed)
4667 stream_update.adjust =
4668 &acrtc_state->stream->adjust;
4669
4670 if (acrtc_state->freesync_vrr_info_changed)
4671 stream_update.vrr_infopacket =
4672 &acrtc_state->stream->vrr_infopacket;
4673 }
4674
180db303
NK		 4675 /* Update surface timing information. */
4676 surface->time.time_elapsed_in_us[surface->time.index] =
4677 addr.flip_timestamp_in_us - surface->time.prev_update_time_in_us;
4678 surface->time.prev_update_time_in_us = addr.flip_timestamp_in_us;
4679 surface->time.index++;
4680 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
4681 surface->time.index = 0;
4682
674e78ac 4683 mutex_lock(&adev->dm.dc_lock);
180db303 4684
bc6828e0
BL		 4685 dc_commit_updates_for_stream(adev->dm.dc,
4686 surface_updates,
4687 1,
4688 acrtc_state->stream,
bb47de73 4689 &stream_update,
bc6828e0
BL		 4690 &surface_updates->surface,
4691 state);
674e78ac 4692 mutex_unlock(&adev->dm.dc_lock);
e7b07cee
HW		 4693
4694 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
4695 __func__,
4696 addr.address.grph.addr.high_part,
4697 addr.address.grph.addr.low_part);
e7b07cee
HW		 4698}
4699
44d09c6a
HW		 4700/*
4701 * TODO this whole function needs to go
4702 *
4703 * dc_surface_update is needlessly complex. See if we can just replace this
4704 * with a dc_plane_state and follow the atomic model a bit more closely here.
4705 */
4706static bool commit_planes_to_stream(
674e78ac 4707 struct amdgpu_display_manager *dm,
44d09c6a
HW		 4708 struct dc *dc,
4709 struct dc_plane_state **plane_states,
4710 uint8_t new_plane_count,
4711 struct dm_crtc_state *dm_new_crtc_state,
4712 struct dm_crtc_state *dm_old_crtc_state,
4713 struct dc_state *state)
4714{
4715 /* no need to dynamically allocate this. it's pretty small */
4716 struct dc_surface_update updates[MAX_SURFACES];
4717 struct dc_flip_addrs *flip_addr;
4718 struct dc_plane_info *plane_info;
4719 struct dc_scaling_info *scaling_info;
4720 int i;
4721 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
4722 struct dc_stream_update *stream_update =
4723 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
c1ee92f9 4724 unsigned int abm_level;
44d09c6a
HW		 4725
4726 if (!stream_update) {
4727 BREAK_TO_DEBUGGER();
4728 return false;
4729 }
4730
4731 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
4732 GFP_KERNEL);
4733 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
4734 GFP_KERNEL);
4735 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
4736 GFP_KERNEL);
4737
4738 if (!flip_addr || !plane_info || !scaling_info) {
4739 kfree(flip_addr);
4740 kfree(plane_info);
4741 kfree(scaling_info);
4742 kfree(stream_update);
4743 return false;
4744 }
4745
4746 memset(updates, 0, sizeof(updates));
4747
4748 stream_update->src = dc_stream->src;
4749 stream_update->dst = dc_stream->dst;
4750 stream_update->out_transfer_func = dc_stream->out_transfer_func;
4751
c1ee92f9
DF		 4752 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
4753 abm_level = dm_new_crtc_state->abm_level;
4754 stream_update->abm_level = &abm_level;
98e6436d
AK		 4755 }
4756
44d09c6a
HW		 4757 for (i = 0; i < new_plane_count; i++) {
4758 updates[i].surface = plane_states[i];
4759 updates[i].gamma =
4760 (struct dc_gamma *)plane_states[i]->gamma_correction;
4761 updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4762 flip_addr[i].address = plane_states[i]->address;
4763 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4764 plane_info[i].color_space = plane_states[i]->color_space;
44d09c6a
HW		 4765 plane_info[i].format = plane_states[i]->format;
4766 plane_info[i].plane_size = plane_states[i]->plane_size;
4767 plane_info[i].rotation = plane_states[i]->rotation;
4768 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4769 plane_info[i].stereo_format = plane_states[i]->stereo_format;
4770 plane_info[i].tiling_info = plane_states[i]->tiling_info;
4771 plane_info[i].visible = plane_states[i]->visible;
4772 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4773 plane_info[i].dcc = plane_states[i]->dcc;
4774 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4775 scaling_info[i].src_rect = plane_states[i]->src_rect;
4776 scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4777 scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4778
4779 updates[i].flip_addr = &flip_addr[i];
4780 updates[i].plane_info = &plane_info[i];
4781 updates[i].scaling_info = &scaling_info[i];
4782 }
4783
674e78ac 4784 mutex_lock(&dm->dc_lock);
44d09c6a
HW		 4785 dc_commit_updates_for_stream(
4786 dc,
4787 updates,
4788 new_plane_count,
4789 dc_stream, stream_update, plane_states, state);
674e78ac 4790 mutex_unlock(&dm->dc_lock);
44d09c6a
HW		 4791
4792 kfree(flip_addr);
4793 kfree(plane_info);
4794 kfree(scaling_info);
4795 kfree(stream_update);
4796 return true;
4797}
4798
3be5262e 4799static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 4800 struct dc_state *dc_state,
3ee6b26b
AD		 4801 struct drm_device *dev,
4802 struct amdgpu_display_manager *dm,
4803 struct drm_crtc *pcrtc,
4804 bool *wait_for_vblank)
e7b07cee
HW		 4805{
4806 uint32_t i;
4807 struct drm_plane *plane;
0bc9706d 4808 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 4809 struct dc_stream_state *dc_stream_attach;
3be5262e 4810 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 4811 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 4812 struct drm_crtc_state *new_pcrtc_state =
4813 drm_atomic_get_new_crtc_state(state, pcrtc);
4814 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 4815 struct dm_crtc_state *dm_old_crtc_state =
4816 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
e7b07cee
HW		 4817 int planes_count = 0;
4818 unsigned long flags;
4819
4820 /* update planes when needed */
0bc9706d
LSL		 4821 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4822 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 4823 struct drm_crtc_state *new_crtc_state;
0bc9706d 4824 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 4825 bool pflip_needed;
54d76575 4826 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 4827
4828 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4829 handle_cursor_update(plane, old_plane_state);
4830 continue;
4831 }
4832
f5ba60fe
DD		 4833 if (!fb || !crtc || pcrtc != crtc)
4834 continue;
4835
4836 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4837 if (!new_crtc_state->active)
e7b07cee
HW		 4838 continue;
4839
4840 pflip_needed = !state->allow_modeset;
4841
4842 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4843 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 4844 DRM_ERROR("%s: acrtc %d, already busy\n",
4845 __func__,
4846 acrtc_attach->crtc_id);
b830ebc9 4847 /* In commit tail framework this cannot happen */
e7b07cee
HW		 4848 WARN_ON(1);
4849 }
4850 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4851
a2a330ad 4852 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
54d76575 4853 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 4854
54d76575 4855 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 4856
4857 dc_stream_attach = acrtc_state->stream;
4858 planes_count++;
4859
0bc9706d 4860 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 4861 /* Assume even ONE crtc with immediate flip means
4862 * entire can't wait for VBLANK
4863 * TODO Check if it's correct
4864 */
4865 *wait_for_vblank =
0bc9706d 4866 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 4867 false : true;
4868
4869 /* TODO: Needs rework for multiplane flip */
4870 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4871 drm_crtc_vblank_get(crtc);
4872
4873 amdgpu_dm_do_flip(
4874 crtc,
4875 fb,
23effc11 4876 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
eb3dc897 4877 dc_state);
e7b07cee
HW		 4878 }
4879
4880 }
4881
4882 if (planes_count) {
4883 unsigned long flags;
4884
0bc9706d 4885 if (new_pcrtc_state->event) {
e7b07cee
HW		 4886
4887 drm_crtc_vblank_get(pcrtc);
4888
4889 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4890 prepare_flip_isr(acrtc_attach);
4891 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4892 }
4893
c1ee92f9 4894 dc_stream_attach->abm_level = acrtc_state->abm_level;
44d09c6a 4895
674e78ac
NK		 4896 if (false == commit_planes_to_stream(dm,
4897 dm->dc,
3be5262e
HW		 4898 plane_states_constructed,
4899 planes_count,
44d09c6a
HW		 4900 acrtc_state,
4901 dm_old_crtc_state,
eb3dc897 4902 dc_state))
3be5262e 4903 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4904 } else {
4905 /*TODO BUG Here should go disable planes on CRTC. */
4906 }
4907}
4908
1f6010a9 4909/*
27b3f4fc
LSL		 4910 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4911 * @crtc_state: the DRM CRTC state
4912 * @stream_state: the DC stream state.
4913 *
4914 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4915 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4916 */
4917static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4918 struct dc_stream_state *stream_state)
4919{
4920 stream_state->mode_changed = crtc_state->mode_changed;
4921}
e7b07cee 4922
7578ecda
AD		 4923static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4924 struct drm_atomic_state *state,
4925 bool nonblock)
e7b07cee
HW		 4926{
4927 struct drm_crtc *crtc;
c2cea706 4928 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4929 struct amdgpu_device *adev = dev->dev_private;
4930 int i;
4931
4932 /*
4933 * We evade vblanks and pflips on crtc that
4934 * should be changed. We do it here to flush & disable
4935 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4936 * it will update crtc->dm_crtc_state->stream pointer which is used in
4937 * the ISRs.
4938 */
c2cea706 4939 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4940 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 4941 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4942
54d76575 4943 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 4944 manage_dm_interrupts(adev, acrtc, false);
4945 }
1f6010a9
DF		 4946 /*
4947 * Add check here for SoC's that support hardware cursor plane, to
4948 * unset legacy_cursor_update
4949 */
e7b07cee
HW		 4950
4951 return drm_atomic_helper_commit(dev, state, nonblock);
4952
4953 /*TODO Handle EINTR, reenable IRQ*/
4954}
4955
b8592b48
LL		 4956/**
4957 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
4958 * @state: The atomic state to commit
4959 *
4960 * This will tell DC to commit the constructed DC state from atomic_check,
4961 * programming the hardware. Any failures here implies a hardware failure, since
4962 * atomic check should have filtered anything non-kosher.
4963 */
7578ecda 4964static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4965{
4966 struct drm_device *dev = state->dev;
4967 struct amdgpu_device *adev = dev->dev_private;
4968 struct amdgpu_display_manager *dm = &adev->dm;
4969 struct dm_atomic_state *dm_state;
eb3dc897 4970 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 4971 uint32_t i, j;
5cc6dcbd 4972 struct drm_crtc *crtc;
0bc9706d 4973 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4974 unsigned long flags;
4975 bool wait_for_vblank = true;
4976 struct drm_connector *connector;
c2cea706 4977 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4978 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 4979 int crtc_disable_count = 0;
e7b07cee
HW		 4980
4981 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4982
eb3dc897
NK		 4983 dm_state = dm_atomic_get_new_state(state);
4984 if (dm_state && dm_state->context) {
4985 dc_state = dm_state->context;
4986 } else {
4987 /* No state changes, retain current state. */
4988 dc_state_temp = dc_create_state();
4989 ASSERT(dc_state_temp);
4990 dc_state = dc_state_temp;
4991 dc_resource_state_copy_construct_current(dm->dc, dc_state);
4992 }
e7b07cee
HW		 4993
4994 /* update changed items */
0bc9706d 4995 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4996 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4997
54d76575
LSL		 4998 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4999 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 5000
f1ad2f5e 5001 DRM_DEBUG_DRIVER(
e7b07cee
HW		 5002 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5003 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5004 "connectors_changed:%d\n",
5005 acrtc->crtc_id,
0bc9706d
LSL		 5006 new_crtc_state->enable,
5007 new_crtc_state->active,
5008 new_crtc_state->planes_changed,
5009 new_crtc_state->mode_changed,
5010 new_crtc_state->active_changed,
5011 new_crtc_state->connectors_changed);
e7b07cee 5012
27b3f4fc
LSL		 5013 /* Copy all transient state flags into dc state */
5014 if (dm_new_crtc_state->stream) {
5015 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5016 dm_new_crtc_state->stream);
5017 }
5018
e7b07cee
HW		 5019 /* handles headless hotplug case, updating new_state and
5020 * aconnector as needed
5021 */
5022
54d76575 5023 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 5024
f1ad2f5e 5025 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 5026
54d76575 5027 if (!dm_new_crtc_state->stream) {
e7b07cee 5028 /*
b830ebc9
HW		 5029 * this could happen because of issues with
5030 * userspace notifications delivery.
5031 * In this case userspace tries to set mode on
1f6010a9
DF		 5032 * display which is disconnected in fact.
5033 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 5034 * We expect reset mode will come soon.
5035 *
5036 * This can also happen when unplug is done
5037 * during resume sequence ended
5038 *
5039 * In this case, we want to pretend we still
5040 * have a sink to keep the pipe running so that
5041 * hw state is consistent with the sw state
5042 */
f1ad2f5e 5043 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 5044 __func__, acrtc->base.base.id);
5045 continue;
5046 }
5047
54d76575
LSL		 5048 if (dm_old_crtc_state->stream)
5049 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 5050
97028037
LP		 5051 pm_runtime_get_noresume(dev->dev);
5052
e7b07cee 5053 acrtc->enabled = true;
0bc9706d
LSL		 5054 acrtc->hw_mode = new_crtc_state->mode;
5055 crtc->hwmode = new_crtc_state->mode;
5056 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 5057 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 5058
5059 /* i.e. reset mode */
54d76575
LSL		 5060 if (dm_old_crtc_state->stream)
5061 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 5062 }
5063 } /* for_each_crtc_in_state() */
5064
eb3dc897
NK		 5065 if (dc_state) {
5066 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 5067 mutex_lock(&dm->dc_lock);
eb3dc897 5068 WARN_ON(!dc_commit_state(dm->dc, dc_state));
674e78ac 5069 mutex_unlock(&dm->dc_lock);
fa2123db 5070 }
e7b07cee 5071
0bc9706d 5072 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5073 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5074
54d76575 5075 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5076
54d76575 5077 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 5078 const struct dc_stream_status *status =
54d76575 5079 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5080
eb3dc897
NK		 5081 if (!status)
5082 status = dc_state_get_stream_status(dc_state,
5083 dm_new_crtc_state->stream);
5084
e7b07cee 5085 if (!status)
54d76575 5086 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 5087 else
5088 acrtc->otg_inst = status->primary_otg_inst;
5089 }
5090 }
5091
c1ee92f9 5092 /* Handle scaling, underscan, and abm changes*/
c2cea706 5093 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5094 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5095 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5096 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 5097 struct dc_stream_status *status = NULL;
5098
44d09c6a 5099 if (acrtc) {
0bc9706d 5100 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 5101 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5102 }
0bc9706d 5103
e7b07cee 5104 /* Skip any modesets/resets */
0bc9706d 5105 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 5106 continue;
5107
e7b07cee 5108
54d76575 5109 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 5110 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5111
5112 /* Skip anything that is not scaling or underscan changes */
5113 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5114 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5115 continue;
e7b07cee 5116
54d76575
LSL		 5117 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5118 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 5119
70e8ffc5
HW		 5120 if (!dm_new_crtc_state->stream)
5121 continue;
5122
54d76575 5123 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5124 WARN_ON(!status);
3be5262e 5125 WARN_ON(!status->plane_count);
e7b07cee 5126
c1ee92f9 5127 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
98e6436d 5128
e7b07cee 5129 /*TODO How it works with MPO ?*/
44d09c6a 5130 if (!commit_planes_to_stream(
674e78ac 5131 dm,
e7b07cee 5132 dm->dc,
3be5262e
HW		 5133 status->plane_states,
5134 status->plane_count,
44d09c6a
HW		 5135 dm_new_crtc_state,
5136 to_dm_crtc_state(old_crtc_state),
fb6e4709 5137 dc_state))
e7b07cee
HW		 5138 dm_error("%s: Failed to update stream scaling!\n", __func__);
5139 }
5140
e1fc2dca
LSL		 5141 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5142 new_crtc_state, i) {
e7b07cee
HW		 5143 /*
5144 * loop to enable interrupts on newly arrived crtc
5145 */
e1fc2dca
LSL		 5146 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5147 bool modeset_needed;
b830ebc9 5148
fe2a1965
LP		 5149 if (old_crtc_state->active && !new_crtc_state->active)
5150 crtc_disable_count++;
5151
54d76575 5152 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 5153 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5154 modeset_needed = modeset_required(
5155 new_crtc_state,
5156 dm_new_crtc_state->stream,
5157 dm_old_crtc_state->stream);
5158
5159 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
5160 continue;
e7b07cee 5161
e7b07cee
HW		 5162 manage_dm_interrupts(adev, acrtc, true);
5163 }
5164
5165 /* update planes when needed per crtc*/
5cc6dcbd 5166 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 5167 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5168
54d76575 5169 if (dm_new_crtc_state->stream)
eb3dc897
NK		 5170 amdgpu_dm_commit_planes(state, dc_state, dev,
5171 dm, crtc, &wait_for_vblank);
e7b07cee
HW		 5172 }
5173
5174
5175 /*
5176 * send vblank event on all events not handled in flip and
5177 * mark consumed event for drm_atomic_helper_commit_hw_done
5178 */
5179 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 5180 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5181
0bc9706d
LSL		 5182 if (new_crtc_state->event)
5183 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 5184
0bc9706d 5185 new_crtc_state->event = NULL;
e7b07cee
HW		 5186 }
5187 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5188
e7b07cee
HW		 5189
5190 if (wait_for_vblank)
320a1274 5191 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee 5192
717276b9
S		 5193 /*
5194 * FIXME:
5195 * Delay hw_done() until flip_done() is signaled. This is to block
5196 * another commit from freeing the CRTC state while we're still
5197 * waiting on flip_done.
5198 */
5199 drm_atomic_helper_commit_hw_done(state);
5200
e7b07cee 5201 drm_atomic_helper_cleanup_planes(dev, state);
97028037 5202
1f6010a9
DF		 5203 /*
5204 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 5205 * so we can put the GPU into runtime suspend if we're not driving any
5206 * displays anymore
5207 */
fe2a1965
LP		 5208 for (i = 0; i < crtc_disable_count; i++)
5209 pm_runtime_put_autosuspend(dev->dev);
97028037 5210 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 5211
5212 if (dc_state_temp)
5213 dc_release_state(dc_state_temp);
e7b07cee
HW		 5214}
5215
5216
5217static int dm_force_atomic_commit(struct drm_connector *connector)
5218{
5219 int ret = 0;
5220 struct drm_device *ddev = connector->dev;
5221 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5222 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5223 struct drm_plane *plane = disconnected_acrtc->base.primary;
5224 struct drm_connector_state *conn_state;
5225 struct drm_crtc_state *crtc_state;
5226 struct drm_plane_state *plane_state;
5227
5228 if (!state)
5229 return -ENOMEM;
5230
5231 state->acquire_ctx = ddev->mode_config.acquire_ctx;
5232
5233 /* Construct an atomic state to restore previous display setting */
5234
5235 /*
5236 * Attach connectors to drm_atomic_state
5237 */
5238 conn_state = drm_atomic_get_connector_state(state, connector);
5239
5240 ret = PTR_ERR_OR_ZERO(conn_state);
5241 if (ret)
5242 goto err;
5243
5244 /* Attach crtc to drm_atomic_state*/
5245 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5246
5247 ret = PTR_ERR_OR_ZERO(crtc_state);
5248 if (ret)
5249 goto err;
5250
5251 /* force a restore */
5252 crtc_state->mode_changed = true;
5253
5254 /* Attach plane to drm_atomic_state */
5255 plane_state = drm_atomic_get_plane_state(state, plane);
5256
5257 ret = PTR_ERR_OR_ZERO(plane_state);
5258 if (ret)
5259 goto err;
5260
5261
5262 /* Call commit internally with the state we just constructed */
5263 ret = drm_atomic_commit(state);
5264 if (!ret)
5265 return 0;
5266
5267err:
5268 DRM_ERROR("Restoring old state failed with %i\n", ret);
5269 drm_atomic_state_put(state);
5270
5271 return ret;
5272}
5273
5274/*
1f6010a9
DF		 5275 * This function handles all cases when set mode does not come upon hotplug.
5276 * This includes when a display is unplugged then plugged back into the
5277 * same port and when running without usermode desktop manager supprot
e7b07cee 5278 */
3ee6b26b
AD		 5279void dm_restore_drm_connector_state(struct drm_device *dev,
5280 struct drm_connector *connector)
e7b07cee 5281{
c84dec2f 5282 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5283 struct amdgpu_crtc *disconnected_acrtc;
5284 struct dm_crtc_state *acrtc_state;
5285
5286 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5287 return;
5288
5289 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 5290 if (!disconnected_acrtc)
5291 return;
e7b07cee 5292
70e8ffc5
HW		 5293 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5294 if (!acrtc_state->stream)
e7b07cee
HW		 5295 return;
5296
5297 /*
5298 * If the previous sink is not released and different from the current,
5299 * we deduce we are in a state where we can not rely on usermode call
5300 * to turn on the display, so we do it here
5301 */
5302 if (acrtc_state->stream->sink != aconnector->dc_sink)
5303 dm_force_atomic_commit(&aconnector->base);
5304}
5305
1f6010a9 5306/*
e7b07cee
HW		 5307 * Grabs all modesetting locks to serialize against any blocking commits,
5308 * Waits for completion of all non blocking commits.
5309 */
3ee6b26b
AD		 5310static int do_aquire_global_lock(struct drm_device *dev,
5311 struct drm_atomic_state *state)
e7b07cee
HW		 5312{
5313 struct drm_crtc *crtc;
5314 struct drm_crtc_commit *commit;
5315 long ret;
5316
1f6010a9
DF		 5317 /*
5318 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 5319 * ensure that when the framework release it the
5320 * extra locks we are locking here will get released to
5321 */
5322 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
5323 if (ret)
5324 return ret;
5325
5326 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5327 spin_lock(&crtc->commit_lock);
5328 commit = list_first_entry_or_null(&crtc->commit_list,
5329 struct drm_crtc_commit, commit_entry);
5330 if (commit)
5331 drm_crtc_commit_get(commit);
5332 spin_unlock(&crtc->commit_lock);
5333
5334 if (!commit)
5335 continue;
5336
1f6010a9
DF		 5337 /*
5338 * Make sure all pending HW programming completed and
e7b07cee
HW		 5339 * page flips done
5340 */
5341 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
5342
5343 if (ret > 0)
5344 ret = wait_for_completion_interruptible_timeout(
5345 &commit->flip_done, 10*HZ);
5346
5347 if (ret == 0)
5348 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 5349 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 5350
5351 drm_crtc_commit_put(commit);
5352 }
5353
5354 return ret < 0 ? ret : 0;
5355}
5356
bb47de73
NK		 5357static void get_freesync_config_for_crtc(
5358 struct dm_crtc_state *new_crtc_state,
5359 struct dm_connector_state *new_con_state)
98e6436d
AK		 5360{
5361 struct mod_freesync_config config = {0};
98e6436d
AK		 5362 struct amdgpu_dm_connector *aconnector =
5363 to_amdgpu_dm_connector(new_con_state->base.connector);
5364
bb47de73
NK		 5365 new_crtc_state->vrr_supported = new_con_state->freesync_capable;
5366
5367 if (new_con_state->freesync_capable) {
5368 config.state = new_crtc_state->base.vrr_enabled ?
98e6436d
AK		 5369 VRR_STATE_ACTIVE_VARIABLE :
5370 VRR_STATE_INACTIVE;
5371 config.min_refresh_in_uhz =
5372 aconnector->min_vfreq * 1000000;
5373 config.max_refresh_in_uhz =
5374 aconnector->max_vfreq * 1000000;
69ff8845 5375 config.vsif_supported = true;
180db303 5376 config.btr = true;
98e6436d
AK		 5377 }
5378
bb47de73
NK		 5379 new_crtc_state->freesync_config = config;
5380}
98e6436d 5381
bb47de73
NK		 5382static void reset_freesync_config_for_crtc(
5383 struct dm_crtc_state *new_crtc_state)
5384{
5385 new_crtc_state->vrr_supported = false;
98e6436d 5386
180db303
NK		 5387 memset(&new_crtc_state->vrr_params, 0,
5388 sizeof(new_crtc_state->vrr_params));
bb47de73
NK		 5389 memset(&new_crtc_state->vrr_infopacket, 0,
5390 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 5391}
5392
5393static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
3ee6b26b
AD		 5394 struct drm_atomic_state *state,
5395 bool enable,
5396 bool *lock_and_validation_needed)
e7b07cee 5397{
eb3dc897 5398 struct dm_atomic_state *dm_state = NULL;
e7b07cee 5399 struct drm_crtc *crtc;
c2cea706 5400 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 5401 int i;
54d76575 5402 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 5403 struct dc_stream_state *new_stream;
62f55537 5404 int ret = 0;
d4d4a645 5405
1f6010a9
DF		 5406 /*
5407 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
5408 * update changed items
5409 */
c2cea706 5410 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 5411 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 5412 struct amdgpu_dm_connector *aconnector = NULL;
a9e8d275
DF		 5413 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
5414 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
f2877656 5415 struct drm_plane_state *new_plane_state = NULL;
e7b07cee 5416
9635b754
DS		 5417 new_stream = NULL;
5418
54d76575
LSL		 5419 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5420 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 5421 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 5422
f2877656
HW		 5423 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
5424
5425 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
5426 ret = -EINVAL;
5427 goto fail;
5428 }
5429
1daf8c63 5430 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 5431
62f55537 5432 /* TODO This hack should go away */
f4ac176e 5433 if (aconnector && enable) {
1f6010a9 5434 /* Make sure fake sink is created in plug-in scenario */
a9e8d275 5435 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
c2cea706 5436 &aconnector->base);
a9e8d275
DF		 5437 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
5438 &aconnector->base);
19f89e23 5439
a9e8d275
DF		 5440 if (IS_ERR(drm_new_conn_state)) {
5441 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
62f55537
AG		 5442 break;
5443 }
19f89e23 5444
a9e8d275
DF		 5445 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
5446 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 5447
62f55537 5448 new_stream = create_stream_for_sink(aconnector,
c2cea706 5449 &new_crtc_state->mode,
b333730d
BL		 5450 dm_new_conn_state,
5451 dm_old_crtc_state->stream);
19f89e23 5452
62f55537
AG		 5453 /*
5454 * we can have no stream on ACTION_SET if a display
1f6010a9 5455 * was disconnected during S3, in this case it is not an
62f55537 5456 * error, the OS will be updated after detection, and
1f6010a9 5457 * will do the right thing on next atomic commit
62f55537 5458 */
19f89e23 5459
62f55537 5460 if (!new_stream) {
f1ad2f5e 5461 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 5462 __func__, acrtc->base.base.id);
5463 break;
19f89e23 5464 }
e7b07cee 5465
c1ee92f9 5466 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 5467
a97599a4
LSL		 5468 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
5469 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
5470 new_crtc_state->mode_changed = false;
5471 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
5472 new_crtc_state->mode_changed);
5473 }
62f55537 5474 }
b830ebc9 5475
c2cea706 5476 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 5477 goto next_crtc;
e7b07cee 5478
f1ad2f5e 5479 DRM_DEBUG_DRIVER(
e7b07cee
HW		 5480 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5481 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5482 "connectors_changed:%d\n",
5483 acrtc->crtc_id,
c2cea706
LSL		 5484 new_crtc_state->enable,
5485 new_crtc_state->active,
5486 new_crtc_state->planes_changed,
5487 new_crtc_state->mode_changed,
5488 new_crtc_state->active_changed,
5489 new_crtc_state->connectors_changed);
e7b07cee 5490
62f55537
AG		 5491 /* Remove stream for any changed/disabled CRTC */
5492 if (!enable) {
5493
54d76575 5494 if (!dm_old_crtc_state->stream)
9635b754 5495 goto next_crtc;
62f55537 5496
eb3dc897
NK		 5497 ret = dm_atomic_get_state(state, &dm_state);
5498 if (ret)
5499 goto fail;
5500
f1ad2f5e 5501 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 5502 crtc->base.id);
e7b07cee 5503
1dc90497 5504 /* i.e. reset mode */
62c933f9 5505 if (dc_remove_stream_from_ctx(
98e6436d 5506 dm->dc,
62f55537 5507 dm_state->context,
62c933f9 5508 dm_old_crtc_state->stream) != DC_OK) {
62f55537 5509 ret = -EINVAL;
9635b754 5510 goto fail;
62f55537
AG		 5511 }
5512
54d76575
LSL		 5513 dc_stream_release(dm_old_crtc_state->stream);
5514 dm_new_crtc_state->stream = NULL;
62f55537 5515
bb47de73
NK		 5516 reset_freesync_config_for_crtc(dm_new_crtc_state);
5517
62f55537
AG		 5518 *lock_and_validation_needed = true;
5519
5520 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 5521 /*
5522 * Quick fix to prevent NULL pointer on new_stream when
5523 * added MST connectors not found in existing crtc_state in the chained mode
5524 * TODO: need to dig out the root cause of that
5525 */
5526 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 5527 goto next_crtc;
62f55537 5528
c2cea706 5529 if (modereset_required(new_crtc_state))
9635b754 5530 goto next_crtc;
62f55537 5531
c2cea706 5532 if (modeset_required(new_crtc_state, new_stream,
54d76575 5533 dm_old_crtc_state->stream)) {
62f55537 5534
54d76575 5535 WARN_ON(dm_new_crtc_state->stream);
62f55537 5536
eb3dc897
NK		 5537 ret = dm_atomic_get_state(state, &dm_state);
5538 if (ret)
5539 goto fail;
5540
54d76575 5541 dm_new_crtc_state->stream = new_stream;
27b3f4fc 5542
62f55537
AG		 5543 dc_stream_retain(new_stream);
5544
f1ad2f5e 5545 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 5546 crtc->base.id);
1dc90497 5547
13ab1b44 5548 if (dc_add_stream_to_ctx(
98e6436d 5549 dm->dc,
1dc90497 5550 dm_state->context,
13ab1b44 5551 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 5552 ret = -EINVAL;
9635b754 5553 goto fail;
1dc90497
AG		 5554 }
5555
62f55537 5556 *lock_and_validation_needed = true;
9b690ef3 5557 }
62f55537 5558 }
9b690ef3 5559
9635b754 5560next_crtc:
62f55537
AG		 5561 /* Release extra reference */
5562 if (new_stream)
5563 dc_stream_release(new_stream);
e277adc5
LSL		 5564
5565 /*
5566 * We want to do dc stream updates that do not require a
5567 * full modeset below.
5568 */
20fa2ff0
LSL		 5569 if (!(enable && aconnector && new_crtc_state->enable &&
5570 new_crtc_state->active))
e277adc5
LSL		 5571 continue;
5572 /*
5573 * Given above conditions, the dc state cannot be NULL because:
20fa2ff0
LSL		 5574 * 1. We're in the process of enabling CRTCs (just been added
5575 * to the dc context, or already is on the context)
5576 * 2. Has a valid connector attached, and
5577 * 3. Is currently active and enabled.
5578 * => The dc stream state currently exists.
e277adc5
LSL		 5579 */
5580 BUG_ON(dm_new_crtc_state->stream == NULL);
5581
a9e8d275
DF		 5582 /* Scaling or underscan settings */
5583 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
5584 update_stream_scaling_settings(
5585 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
5586
bc13f2f8
LSL		 5587 /*
5588 * Color management settings. We also update color properties
5589 * when a modeset is needed, to ensure it gets reprogrammed.
5590 */
5591 if (dm_new_crtc_state->base.color_mgmt_changed ||
5592 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
e277adc5
LSL		 5593 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
5594 if (ret)
5595 goto fail;
5596 amdgpu_dm_set_ctm(dm_new_crtc_state);
5597 }
98e6436d 5598
bb47de73
NK		 5599 /* Update Freesync settings. */
5600 get_freesync_config_for_crtc(dm_new_crtc_state,
5601 dm_new_conn_state);
62f55537 5602 }
e7b07cee 5603
62f55537 5604 return ret;
9635b754
DS		 5605
5606fail:
5607 if (new_stream)
5608 dc_stream_release(new_stream);
5609 return ret;
62f55537 5610}
9b690ef3 5611
3ee6b26b
AD		 5612static int dm_update_planes_state(struct dc *dc,
5613 struct drm_atomic_state *state,
5614 bool enable,
5615 bool *lock_and_validation_needed)
62f55537 5616{
eb3dc897
NK		 5617
5618 struct dm_atomic_state *dm_state = NULL;
62f55537 5619 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 5620 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 5621 struct drm_plane *plane;
5622 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 5623 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 5624 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 5625 int i ;
5626 /* TODO return page_flip_needed() function */
5627 bool pflip_needed = !state->allow_modeset;
5628 int ret = 0;
e7b07cee 5629
9b690ef3 5630
df534fff
S		 5631 /* Add new planes, in reverse order as DC expectation */
5632 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
62f55537
AG		 5633 new_plane_crtc = new_plane_state->crtc;
5634 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 5635 dm_new_plane_state = to_dm_plane_state(new_plane_state);
5636 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 5637
5638 /*TODO Implement atomic check for cursor plane */
5639 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5640 continue;
9b690ef3 5641
62f55537
AG		 5642 /* Remove any changed/removed planes */
5643 if (!enable) {
a2a330ad
S		 5644 if (pflip_needed &&
5645 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 5646 continue;
a7b06724 5647
62f55537
AG		 5648 if (!old_plane_crtc)
5649 continue;
5650
0bc9706d
LSL		 5651 old_crtc_state = drm_atomic_get_old_crtc_state(
5652 state, old_plane_crtc);
54d76575 5653 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 5654
54d76575 5655 if (!dm_old_crtc_state->stream)
62f55537
AG		 5656 continue;
5657
f2877656 5658 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 5659 plane->base.id, old_plane_crtc->base.id);
9b690ef3 5660
eb3dc897
NK		 5661 ret = dm_atomic_get_state(state, &dm_state);
5662 if (ret)
5663 return ret;
5664
62f55537
AG		 5665 if (!dc_remove_plane_from_context(
5666 dc,
54d76575
LSL		 5667 dm_old_crtc_state->stream,
5668 dm_old_plane_state->dc_state,
62f55537
AG		 5669 dm_state->context)) {
5670
5671 ret = EINVAL;
5672 return ret;
e7b07cee
HW		 5673 }
5674
9b690ef3 5675
54d76575
LSL		 5676 dc_plane_state_release(dm_old_plane_state->dc_state);
5677 dm_new_plane_state->dc_state = NULL;
1dc90497 5678
62f55537 5679 *lock_and_validation_needed = true;
1dc90497 5680
62f55537 5681 } else { /* Add new planes */
8c45c5db 5682 struct dc_plane_state *dc_new_plane_state;
1dc90497 5683
62f55537
AG		 5684 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
5685 continue;
e7b07cee 5686
62f55537
AG		 5687 if (!new_plane_crtc)
5688 continue;
e7b07cee 5689
62f55537 5690 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 5691 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 5692
54d76575 5693 if (!dm_new_crtc_state->stream)
62f55537
AG		 5694 continue;
5695
a2a330ad
S		 5696 if (pflip_needed &&
5697 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 5698 continue;
62f55537 5699
54d76575 5700 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 5701
8c45c5db 5702 dc_new_plane_state = dc_create_plane_state(dc);
d5400aab
LSL		 5703 if (!dc_new_plane_state)
5704 return -ENOMEM;
62f55537 5705
8c45c5db
LSL		 5706 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5707 plane->base.id, new_plane_crtc->base.id);
5708
62f55537
AG		 5709 ret = fill_plane_attributes(
5710 new_plane_crtc->dev->dev_private,
8c45c5db 5711 dc_new_plane_state,
62f55537 5712 new_plane_state,
9817d5f5 5713 new_crtc_state);
8c45c5db
LSL		 5714 if (ret) {
5715 dc_plane_state_release(dc_new_plane_state);
62f55537 5716 return ret;
8c45c5db 5717 }
62f55537 5718
eb3dc897
NK		 5719 ret = dm_atomic_get_state(state, &dm_state);
5720 if (ret) {
5721 dc_plane_state_release(dc_new_plane_state);
5722 return ret;
5723 }
5724
8c45c5db
LSL		 5725 /*
5726 * Any atomic check errors that occur after this will
5727 * not need a release. The plane state will be attached
5728 * to the stream, and therefore part of the atomic
5729 * state. It'll be released when the atomic state is
5730 * cleaned.
5731 */
62f55537
AG		 5732 if (!dc_add_plane_to_context(
5733 dc,
54d76575 5734 dm_new_crtc_state->stream,
8c45c5db 5735 dc_new_plane_state,
62f55537
AG		 5736 dm_state->context)) {
5737
8c45c5db 5738 dc_plane_state_release(dc_new_plane_state);
d5400aab 5739 return -EINVAL;
e7b07cee 5740 }
62f55537 5741
8c45c5db
LSL		 5742 dm_new_plane_state->dc_state = dc_new_plane_state;
5743
000b59ea
LSL		 5744 /* Tell DC to do a full surface update every time there
5745 * is a plane change. Inefficient, but works for now.
5746 */
5747 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5748
62f55537 5749 *lock_and_validation_needed = true;
e7b07cee 5750 }
62f55537 5751 }
e7b07cee
HW		 5752
5753
62f55537
AG		 5754 return ret;
5755}
a87fa993 5756
eb3dc897
NK		 5757static int
5758dm_determine_update_type_for_commit(struct dc *dc,
5759 struct drm_atomic_state *state,
5760 enum surface_update_type *out_type)
5761{
5762 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
5763 int i, j, num_plane, ret = 0;
a87fa993
BL		 5764 struct drm_plane_state *old_plane_state, *new_plane_state;
5765 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
5766 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5767 struct drm_plane *plane;
5768
5769 struct drm_crtc *crtc;
5770 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
5771 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
5772 struct dc_stream_status *status = NULL;
5773
5774 struct dc_surface_update *updates = kzalloc(MAX_SURFACES * sizeof(struct dc_surface_update), GFP_KERNEL);
5775 struct dc_plane_state *surface = kzalloc(MAX_SURFACES * sizeof(struct dc_plane_state), GFP_KERNEL);
5776 struct dc_stream_update stream_update;
5777 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5778
4f712911
BL		 5779 if (!updates || !surface) {
5780 DRM_ERROR("Plane or surface update failed to allocate");
5781 /* Set type to FULL to avoid crashing in DC*/
5782 update_type = UPDATE_TYPE_FULL;
eb3dc897 5783 goto cleanup;
4f712911 5784 }
a87fa993
BL		 5785
5786 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5787 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5788 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
5789 num_plane = 0;
5790
5791 if (new_dm_crtc_state->stream) {
5792
5793 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5794 new_plane_crtc = new_plane_state->crtc;
5795 old_plane_crtc = old_plane_state->crtc;
5796 new_dm_plane_state = to_dm_plane_state(new_plane_state);
5797 old_dm_plane_state = to_dm_plane_state(old_plane_state);
5798
5799 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5800 continue;
5801
5802 if (!state->allow_modeset)
5803 continue;
5804
5805 if (crtc == new_plane_crtc) {
5806 updates[num_plane].surface = &surface[num_plane];
5807
5808 if (new_crtc_state->mode_changed) {
5809 updates[num_plane].surface->src_rect =
5810 new_dm_plane_state->dc_state->src_rect;
5811 updates[num_plane].surface->dst_rect =
5812 new_dm_plane_state->dc_state->dst_rect;
5813 updates[num_plane].surface->rotation =
5814 new_dm_plane_state->dc_state->rotation;
5815 updates[num_plane].surface->in_transfer_func =
5816 new_dm_plane_state->dc_state->in_transfer_func;
5817 stream_update.dst = new_dm_crtc_state->stream->dst;
5818 stream_update.src = new_dm_crtc_state->stream->src;
5819 }
5820
5821 if (new_crtc_state->color_mgmt_changed) {
5822 updates[num_plane].gamma =
5823 new_dm_plane_state->dc_state->gamma_correction;
5824 updates[num_plane].in_transfer_func =
5825 new_dm_plane_state->dc_state->in_transfer_func;
5826 stream_update.gamut_remap =
5827 &new_dm_crtc_state->stream->gamut_remap_matrix;
5828 stream_update.out_transfer_func =
5829 new_dm_crtc_state->stream->out_transfer_func;
5830 }
5831
5832 num_plane++;
5833 }
5834 }
5835
5836 if (num_plane > 0) {
eb3dc897
NK		 5837 ret = dm_atomic_get_state(state, &dm_state);
5838 if (ret)
5839 goto cleanup;
5840
5841 old_dm_state = dm_atomic_get_old_state(state);
5842 if (!old_dm_state) {
5843 ret = -EINVAL;
5844 goto cleanup;
5845 }
5846
5847 status = dc_state_get_stream_status(old_dm_state->context,
5848 new_dm_crtc_state->stream);
5849
a87fa993
BL		 5850 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5851 &stream_update, status);
5852
5853 if (update_type > UPDATE_TYPE_MED) {
5854 update_type = UPDATE_TYPE_FULL;
eb3dc897 5855 goto cleanup;
a87fa993
BL		 5856 }
5857 }
5858
5859 } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) {
5860 update_type = UPDATE_TYPE_FULL;
eb3dc897 5861 goto cleanup;
a87fa993
BL		 5862 }
5863 }
5864
eb3dc897 5865cleanup:
a87fa993
BL		 5866 kfree(updates);
5867 kfree(surface);
5868
eb3dc897
NK		 5869 *out_type = update_type;
5870 return ret;
a87fa993 5871}
62f55537 5872
b8592b48
LL		 5873/**
5874 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
5875 * @dev: The DRM device
5876 * @state: The atomic state to commit
5877 *
5878 * Validate that the given atomic state is programmable by DC into hardware.
5879 * This involves constructing a &struct dc_state reflecting the new hardware
5880 * state we wish to commit, then querying DC to see if it is programmable. It's
5881 * important not to modify the existing DC state. Otherwise, atomic_check
5882 * may unexpectedly commit hardware changes.
5883 *
5884 * When validating the DC state, it's important that the right locks are
5885 * acquired. For full updates case which removes/adds/updates streams on one
5886 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
5887 * that any such full update commit will wait for completion of any outstanding
5888 * flip using DRMs synchronization events. See
5889 * dm_determine_update_type_for_commit()
5890 *
5891 * Note that DM adds the affected connectors for all CRTCs in state, when that
5892 * might not seem necessary. This is because DC stream creation requires the
5893 * DC sink, which is tied to the DRM connector state. Cleaning this up should
5894 * be possible but non-trivial - a possible TODO item.
5895 *
5896 * Return: -Error code if validation failed.
5897 */
7578ecda
AD		 5898static int amdgpu_dm_atomic_check(struct drm_device *dev,
5899 struct drm_atomic_state *state)
62f55537 5900{
62f55537 5901 struct amdgpu_device *adev = dev->dev_private;
eb3dc897 5902 struct dm_atomic_state *dm_state = NULL;
62f55537 5903 struct dc *dc = adev->dm.dc;
62f55537 5904 struct drm_connector *connector;
c2cea706 5905 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 5906 struct drm_crtc *crtc;
fc9e9920 5907 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
a87fa993
BL		 5908 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5909 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
5910
1e88ad0a 5911 int ret, i;
e7b07cee 5912
62f55537
AG		 5913 /*
5914 * This bool will be set for true for any modeset/reset
5915 * or plane update which implies non fast surface update.
5916 */
5917 bool lock_and_validation_needed = false;
5918
5919 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 5920 if (ret)
5921 goto fail;
62f55537 5922
1e88ad0a
S		 5923 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5924 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 5925 !new_crtc_state->color_mgmt_changed &&
bb47de73 5926 !new_crtc_state->vrr_enabled)
1e88ad0a 5927 continue;
7bef1af3 5928
1e88ad0a
S		 5929 if (!new_crtc_state->enable)
5930 continue;
fc9e9920 5931
1e88ad0a
S		 5932 ret = drm_atomic_add_affected_connectors(state, crtc);
5933 if (ret)
5934 return ret;
fc9e9920 5935
1e88ad0a
S		 5936 ret = drm_atomic_add_affected_planes(state, crtc);
5937 if (ret)
5938 goto fail;
e7b07cee
HW		 5939 }
5940
62f55537
AG		 5941 /* Remove exiting planes if they are modified */
5942 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
5943 if (ret) {
5944 goto fail;
5945 }
5946
5947 /* Disable all crtcs which require disable */
98e6436d 5948 ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed);
62f55537
AG		 5949 if (ret) {
5950 goto fail;
5951 }
5952
5953 /* Enable all crtcs which require enable */
98e6436d 5954 ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed);
62f55537
AG		 5955 if (ret) {
5956 goto fail;
5957 }
5958
5959 /* Add new/modified planes */
5960 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
5961 if (ret) {
5962 goto fail;
5963 }
5964
b349f76e
ES		 5965 /* Run this here since we want to validate the streams we created */
5966 ret = drm_atomic_helper_check_planes(dev, state);
5967 if (ret)
5968 goto fail;
62f55537 5969
ebdd27e1 5970 /* Check scaling and underscan changes*/
1f6010a9 5971 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 5972 * new stream into context w\o causing full reset. Need to
5973 * decide how to handle.
5974 */
c2cea706 5975 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5976 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5977 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5978 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 5979
5980 /* Skip any modesets/resets */
0bc9706d
LSL		 5981 if (!acrtc || drm_atomic_crtc_needs_modeset(
5982 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 5983 continue;
5984
b830ebc9 5985 /* Skip any thing not scale or underscan changes */
54d76575 5986 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 5987 continue;
5988
a87fa993 5989 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 5990 lock_and_validation_needed = true;
5991 }
5992
eb3dc897
NK		 5993 ret = dm_determine_update_type_for_commit(dc, state, &update_type);
5994 if (ret)
5995 goto fail;
a87fa993
BL		 5996
5997 if (overall_update_type < update_type)
5998 overall_update_type = update_type;
5999
6000 /*
6001 * lock_and_validation_needed was an old way to determine if we need to set
6002 * the global lock. Leaving it in to check if we broke any corner cases
6003 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
6004 * lock_and_validation_needed false = UPDATE_TYPE_FAST
6005 */
6006 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
6007 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
6008 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
6009 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
e7b07cee 6010
e7b07cee 6011
a87fa993 6012 if (overall_update_type > UPDATE_TYPE_FAST) {
eb3dc897
NK		 6013 ret = dm_atomic_get_state(state, &dm_state);
6014 if (ret)
6015 goto fail;
e7b07cee
HW		 6016
6017 ret = do_aquire_global_lock(dev, state);
6018 if (ret)
6019 goto fail;
1dc90497 6020
e750d56d 6021 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 6022 ret = -EINVAL;
6023 goto fail;
6024 }
674e78ac
NK		 6025 } else if (state->legacy_cursor_update) {
6026 /*
6027 * This is a fast cursor update coming from the plane update
6028 * helper, check if it can be done asynchronously for better
6029 * performance.
6030 */
6031 state->async_update = !drm_atomic_helper_async_check(dev, state);
e7b07cee
HW		 6032 }
6033
6034 /* Must be success */
6035 WARN_ON(ret);
6036 return ret;
6037
6038fail:
6039 if (ret == -EDEADLK)
01e28f9c 6040 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 6041 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 6042 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 6043 else
01e28f9c 6044 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 6045
6046 return ret;
6047}
6048
3ee6b26b
AD		 6049static bool is_dp_capable_without_timing_msa(struct dc *dc,
6050 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 6051{
6052 uint8_t dpcd_data;
6053 bool capable = false;
6054
c84dec2f 6055 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 6056 dm_helpers_dp_read_dpcd(
6057 NULL,
c84dec2f 6058 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 6059 DP_DOWN_STREAM_PORT_COUNT,
6060 &dpcd_data,
6061 sizeof(dpcd_data))) {
6062 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
6063 }
6064
6065 return capable;
6066}
98e6436d
AK		 6067void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
6068 struct edid *edid)
e7b07cee
HW		 6069{
6070 int i;
e7b07cee
HW		 6071 bool edid_check_required;
6072 struct detailed_timing *timing;
6073 struct detailed_non_pixel *data;
6074 struct detailed_data_monitor_range *range;
c84dec2f
HW		 6075 struct amdgpu_dm_connector *amdgpu_dm_connector =
6076 to_amdgpu_dm_connector(connector);
bb47de73 6077 struct dm_connector_state *dm_con_state = NULL;
e7b07cee
HW		 6078
6079 struct drm_device *dev = connector->dev;
6080 struct amdgpu_device *adev = dev->dev_private;
bb47de73 6081 bool freesync_capable = false;
b830ebc9 6082
8218d7f1
HW		 6083 if (!connector->state) {
6084 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 6085 goto update;
8218d7f1
HW		 6086 }
6087
98e6436d
AK		 6088 if (!edid) {
6089 dm_con_state = to_dm_connector_state(connector->state);
6090
6091 amdgpu_dm_connector->min_vfreq = 0;
6092 amdgpu_dm_connector->max_vfreq = 0;
6093 amdgpu_dm_connector->pixel_clock_mhz = 0;
6094
bb47de73 6095 goto update;
98e6436d
AK		 6096 }
6097
8218d7f1
HW		 6098 dm_con_state = to_dm_connector_state(connector->state);
6099
e7b07cee 6100 edid_check_required = false;
c84dec2f 6101 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee 6102 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
bb47de73 6103 goto update;
e7b07cee
HW		 6104 }
6105 if (!adev->dm.freesync_module)
bb47de73 6106 goto update;
e7b07cee
HW		 6107 /*
6108 * if edid non zero restrict freesync only for dp and edp
6109 */
6110 if (edid) {
c84dec2f
HW		 6111 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
6112 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 6113 edid_check_required = is_dp_capable_without_timing_msa(
6114 adev->dm.dc,
c84dec2f 6115 amdgpu_dm_connector);
e7b07cee
HW		 6116 }
6117 }
e7b07cee
HW		 6118 if (edid_check_required == true && (edid->version > 1 ||
6119 (edid->version == 1 && edid->revision > 1))) {
6120 for (i = 0; i < 4; i++) {
6121
6122 timing = &edid->detailed_timings[i];
6123 data = &timing->data.other_data;
6124 range = &data->data.range;
6125 /*
6126 * Check if monitor has continuous frequency mode
6127 */
6128 if (data->type != EDID_DETAIL_MONITOR_RANGE)
6129 continue;
6130 /*
6131 * Check for flag range limits only. If flag == 1 then
6132 * no additional timing information provided.
6133 * Default GTF, GTF Secondary curve and CVT are not
6134 * supported
6135 */
6136 if (range->flags != 1)
6137 continue;
6138
c84dec2f
HW		 6139 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6140 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6141 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 6142 range->pixel_clock_mhz * 10;
6143 break;
6144 }
6145
c84dec2f 6146 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 6147 amdgpu_dm_connector->min_vfreq > 10) {
6148
bb47de73 6149 freesync_capable = true;
e7b07cee
HW		 6150 }
6151 }
bb47de73
NK		 6152
6153update:
6154 if (dm_con_state)
6155 dm_con_state->freesync_capable = freesync_capable;
6156
6157 if (connector->vrr_capable_property)
6158 drm_connector_set_vrr_capable_property(connector,
6159 freesync_capable);
e7b07cee
HW		 6160}
6161
Linux 6.x block layer and io_uring tree(s)