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drm/amd/display: Fix brace style in amdgpu_dm_initialize_drm_device()
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
62#include "raven1/DCN/dcn_1_0_offset.h"
63#include "raven1/DCN/dcn_1_0_sh_mask.h"
64#include "vega10/soc15ip.h"
65
66#include "soc15_common.h"
67#endif
68
e7b07cee
HW		 69#include "modules/inc/mod_freesync.h"
70
71#include "i2caux_interface.h"
72
7578ecda
AD		 73/* basic init/fini API */
74static int amdgpu_dm_init(struct amdgpu_device *adev);
75static void amdgpu_dm_fini(struct amdgpu_device *adev);
76
77/* initializes drm_device display related structures, based on the information
78 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
79 * drm_encoder, drm_mode_config
80 *
81 * Returns 0 on success
82 */
83static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
84/* removes and deallocates the drm structures, created by the above function */
85static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
86
87static void
88amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
89
90static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
91 struct amdgpu_plane *aplane,
92 unsigned long possible_crtcs);
93static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
94 struct drm_plane *plane,
95 uint32_t link_index);
96static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
97 struct amdgpu_dm_connector *amdgpu_dm_connector,
98 uint32_t link_index,
99 struct amdgpu_encoder *amdgpu_encoder);
100static int amdgpu_dm_encoder_init(struct drm_device *dev,
101 struct amdgpu_encoder *aencoder,
102 uint32_t link_index);
103
104static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
105
106static int amdgpu_dm_atomic_commit(struct drm_device *dev,
107 struct drm_atomic_state *state,
108 bool nonblock);
109
110static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
111
112static int amdgpu_dm_atomic_check(struct drm_device *dev,
113 struct drm_atomic_state *state);
114
115
116
e7b07cee 117
e04a6123 118static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 119 DRM_PLANE_TYPE_PRIMARY,
120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125};
126
e04a6123 127static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 128 DRM_PLANE_TYPE_PRIMARY,
129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
132};
133
e04a6123 134static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 135 DRM_PLANE_TYPE_PRIMARY,
136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
138};
139
4562236b
HW		 140/*
141 * dm_vblank_get_counter
142 *
143 * @brief
144 * Get counter for number of vertical blanks
145 *
146 * @param
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
149 *
150 * @return
151 * Counter for vertical blanks
152 */
153static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
154{
155 if (crtc >= adev->mode_info.num_crtc)
156 return 0;
157 else {
158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
160 acrtc->base.state);
4562236b 161
da5c47f6
AG		 162
163 if (acrtc_state->stream == NULL) {
0971c40e
HW		 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
165 crtc);
4562236b
HW		 166 return 0;
167 }
168
da5c47f6 169 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 170 }
171}
172
173static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 174 u32 *vbl, u32 *position)
4562236b 175{
81c50963
ST		 176 uint32_t v_blank_start, v_blank_end, h_position, v_position;
177
4562236b
HW		 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
179 return -EINVAL;
180 else {
181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
183 acrtc->base.state);
4562236b 184
da5c47f6 185 if (acrtc_state->stream == NULL) {
0971c40e
HW		 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
187 crtc);
4562236b
HW		 188 return 0;
189 }
190
81c50963
ST		 191 /*
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
194 */
da5c47f6 195 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 196 &v_blank_start,
197 &v_blank_end,
198 &h_position,
199 &v_position);
200
e806208d
AG		 201 *position = v_position | (h_position << 16);
202 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 203 }
204
205 return 0;
206}
207
208static bool dm_is_idle(void *handle)
209{
210 /* XXX todo */
211 return true;
212}
213
214static int dm_wait_for_idle(void *handle)
215{
216 /* XXX todo */
217 return 0;
218}
219
220static bool dm_check_soft_reset(void *handle)
221{
222 return false;
223}
224
225static int dm_soft_reset(void *handle)
226{
227 /* XXX todo */
228 return 0;
229}
230
3ee6b26b
AD		 231static struct amdgpu_crtc *
232get_crtc_by_otg_inst(struct amdgpu_device *adev,
233 int otg_inst)
4562236b
HW		 234{
235 struct drm_device *dev = adev->ddev;
236 struct drm_crtc *crtc;
237 struct amdgpu_crtc *amdgpu_crtc;
238
239 /*
240 * following if is check inherited from both functions where this one is
241 * used now. Need to be checked why it could happen.
242 */
243 if (otg_inst == -1) {
244 WARN_ON(1);
245 return adev->mode_info.crtcs[0];
246 }
247
248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
249 amdgpu_crtc = to_amdgpu_crtc(crtc);
250
251 if (amdgpu_crtc->otg_inst == otg_inst)
252 return amdgpu_crtc;
253 }
254
255 return NULL;
256}
257
258static void dm_pflip_high_irq(void *interrupt_params)
259{
4562236b
HW		 260 struct amdgpu_crtc *amdgpu_crtc;
261 struct common_irq_params *irq_params = interrupt_params;
262 struct amdgpu_device *adev = irq_params->adev;
263 unsigned long flags;
264
265 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
266
267 /* IRQ could occur when in initial stage */
268 /*TODO work and BO cleanup */
269 if (amdgpu_crtc == NULL) {
270 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
271 return;
272 }
273
274 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 275
276 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
277 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
278 amdgpu_crtc->pflip_status,
279 AMDGPU_FLIP_SUBMITTED,
280 amdgpu_crtc->crtc_id,
281 amdgpu_crtc);
282 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
283 return;
284 }
285
4562236b
HW		 286
287 /* wakeup usersapce */
1159898a 288 if (amdgpu_crtc->event) {
753c66c9
MK		 289 /* Update to correct count/ts if racing with vblank irq */
290 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
291
54f5499a 292 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 293
54f5499a
AG		 294 /* page flip completed. clean up */
295 amdgpu_crtc->event = NULL;
1159898a 296
54f5499a
AG		 297 } else
298 WARN_ON(1);
4562236b 299
54f5499a 300 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 301 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
302
54f5499a
AG		 303 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
304 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 305
306 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 307}
308
309static void dm_crtc_high_irq(void *interrupt_params)
310{
311 struct common_irq_params *irq_params = interrupt_params;
312 struct amdgpu_device *adev = irq_params->adev;
313 uint8_t crtc_index = 0;
314 struct amdgpu_crtc *acrtc;
315
b57de80a 316 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 317
318 if (acrtc)
319 crtc_index = acrtc->crtc_id;
320
321 drm_handle_vblank(adev->ddev, crtc_index);
322}
323
324static int dm_set_clockgating_state(void *handle,
325 enum amd_clockgating_state state)
326{
327 return 0;
328}
329
330static int dm_set_powergating_state(void *handle,
331 enum amd_powergating_state state)
332{
333 return 0;
334}
335
336/* Prototypes of private functions */
337static int dm_early_init(void* handle);
338
339static void hotplug_notify_work_func(struct work_struct *work)
340{
341 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
342 struct drm_device *dev = dm->ddev;
343
344 drm_kms_helper_hotplug_event(dev);
345}
346
a32e24b4
RL		 347#ifdef ENABLE_FBC
348#include "dal_asic_id.h"
349/* Allocate memory for FBC compressed data */
350/* TODO: Dynamic allocation */
351#define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
352
7578ecda 353static void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
a32e24b4
RL		 354{
355 int r;
356 struct dm_comressor_info *compressor = &adev->dm.compressor;
357
358 if (!compressor->bo_ptr) {
359 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
360 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
361 &compressor->gpu_addr, &compressor->cpu_addr);
362
363 if (r)
364 DRM_ERROR("DM: Failed to initialize fbc\n");
365 }
366
367}
368#endif
369
370
4562236b
HW		 371/* Init display KMS
372 *
373 * Returns 0 on success
374 */
7578ecda 375static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 376{
377 struct dc_init_data init_data;
378 adev->dm.ddev = adev->ddev;
379 adev->dm.adev = adev;
380
4562236b
HW		 381 /* Zero all the fields */
382 memset(&init_data, 0, sizeof(init_data));
383
384 /* initialize DAL's lock (for SYNC context use) */
385 spin_lock_init(&adev->dm.dal_lock);
386
387 /* initialize DAL's mutex */
388 mutex_init(&adev->dm.dal_mutex);
389
390 if(amdgpu_dm_irq_init(adev)) {
391 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
392 goto error;
393 }
394
395 init_data.asic_id.chip_family = adev->family;
396
397 init_data.asic_id.pci_revision_id = adev->rev_id;
398 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
399
400 init_data.asic_id.vram_width = adev->mc.vram_width;
401 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
402 init_data.asic_id.atombios_base_address =
403 adev->mode_info.atom_context->bios;
404
405 init_data.driver = adev;
406
407 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
408
409 if (!adev->dm.cgs_device) {
410 DRM_ERROR("amdgpu: failed to create cgs device.\n");
411 goto error;
412 }
413
414 init_data.cgs_device = adev->dm.cgs_device;
415
416 adev->dm.dal = NULL;
417
418 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
419
f1ad2f5e
HW		 420 if (amdgpu_dc_log)
421 init_data.log_mask = DC_DEFAULT_LOG_MASK;
422 else
423 init_data.log_mask = DC_MIN_LOG_MASK;
01a526f3 424
a32e24b4
RL		 425#ifdef ENABLE_FBC
426 if (adev->family == FAMILY_CZ)
427 amdgpu_dm_initialize_fbc(adev);
428 init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
429#endif
4562236b
HW		 430 /* Display Core create. */
431 adev->dm.dc = dc_create(&init_data);
432
f1ad2f5e
HW		 433 if (adev->dm.dc)
434 DRM_INFO("Display Core initialized!\n");
435 else
4562236b
HW		 436 DRM_INFO("Display Core failed to initialize!\n");
437
438 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
439
440 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
441 if (!adev->dm.freesync_module) {
442 DRM_ERROR(
443 "amdgpu: failed to initialize freesync_module.\n");
444 } else
f1ad2f5e 445 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 446 adev->dm.freesync_module);
447
448 if (amdgpu_dm_initialize_drm_device(adev)) {
449 DRM_ERROR(
450 "amdgpu: failed to initialize sw for display support.\n");
451 goto error;
452 }
453
454 /* Update the actual used number of crtc */
455 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
456
457 /* TODO: Add_display_info? */
458
459 /* TODO use dynamic cursor width */
ce75805e
AG		 460 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
461 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 462
463 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
464 DRM_ERROR(
465 "amdgpu: failed to initialize sw for display support.\n");
466 goto error;
467 }
468
f1ad2f5e 469 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 470
471 return 0;
472error:
473 amdgpu_dm_fini(adev);
474
475 return -1;
476}
477
7578ecda 478static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 479{
480 amdgpu_dm_destroy_drm_device(&adev->dm);
481 /*
482 * TODO: pageflip, vlank interrupt
483 *
484 * amdgpu_dm_irq_fini(adev);
485 */
486
487 if (adev->dm.cgs_device) {
488 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
489 adev->dm.cgs_device = NULL;
490 }
491 if (adev->dm.freesync_module) {
492 mod_freesync_destroy(adev->dm.freesync_module);
493 adev->dm.freesync_module = NULL;
494 }
495 /* DC Destroy TODO: Replace destroy DAL */
21de3396 496 if (adev->dm.dc)
4562236b 497 dc_destroy(&adev->dm.dc);
4562236b
HW		 498 return;
499}
500
4562236b
HW		 501static int dm_sw_init(void *handle)
502{
503 return 0;
504}
505
506static int dm_sw_fini(void *handle)
507{
508 return 0;
509}
510
7abcf6b5 511static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 512{
c84dec2f 513 struct amdgpu_dm_connector *aconnector;
4562236b 514 struct drm_connector *connector;
7abcf6b5 515 int ret = 0;
4562236b
HW		 516
517 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
518
519 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 520 aconnector = to_amdgpu_dm_connector(connector);
7abcf6b5 521 if (aconnector->dc_link->type == dc_connection_mst_branch) {
f1ad2f5e 522 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 523 aconnector, aconnector->base.base.id);
524
525 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
526 if (ret < 0) {
527 DRM_ERROR("DM_MST: Failed to start MST\n");
528 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
529 return ret;
4562236b 530 }
7abcf6b5 531 }
4562236b
HW		 532 }
533
534 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 535 return ret;
536}
537
538static int dm_late_init(void *handle)
539{
540 struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
7abcf6b5 541
33be2785 542 return detect_mst_link_for_all_connectors(dev);
4562236b
HW		 543}
544
545static void s3_handle_mst(struct drm_device *dev, bool suspend)
546{
c84dec2f 547 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 548 struct drm_connector *connector;
549
550 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
551
552 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 553 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 554 if (aconnector->dc_link->type == dc_connection_mst_branch &&
555 !aconnector->mst_port) {
556
557 if (suspend)
558 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
559 else
560 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
561 }
562 }
563
564 drm_modeset_unlock(&dev->mode_config.connection_mutex);
565}
566
567static int dm_hw_init(void *handle)
568{
569 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
570 /* Create DAL display manager */
571 amdgpu_dm_init(adev);
4562236b
HW		 572 amdgpu_dm_hpd_init(adev);
573
4562236b
HW		 574 return 0;
575}
576
577static int dm_hw_fini(void *handle)
578{
579 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
580
581 amdgpu_dm_hpd_fini(adev);
582
583 amdgpu_dm_irq_fini(adev);
21de3396 584 amdgpu_dm_fini(adev);
4562236b
HW		 585 return 0;
586}
587
588static int dm_suspend(void *handle)
589{
590 struct amdgpu_device *adev = handle;
591 struct amdgpu_display_manager *dm = &adev->dm;
592 int ret = 0;
4562236b
HW		 593
594 s3_handle_mst(adev->ddev, true);
595
4562236b
HW		 596 amdgpu_dm_irq_suspend(adev);
597
0a214e2f 598 WARN_ON(adev->dm.cached_state);
a3621485
AG		 599 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
600
32f5062d 601 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 602
603 return ret;
604}
605
1daf8c63
AD		 606static struct amdgpu_dm_connector *
607amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
608 struct drm_crtc *crtc)
4562236b
HW		 609{
610 uint32_t i;
c2cea706 611 struct drm_connector_state *new_con_state;
4562236b
HW		 612 struct drm_connector *connector;
613 struct drm_crtc *crtc_from_state;
614
c2cea706
LSL		 615 for_each_new_connector_in_state(state, connector, new_con_state, i) {
616 crtc_from_state = new_con_state->crtc;
4562236b
HW		 617
618 if (crtc_from_state == crtc)
c84dec2f 619 return to_amdgpu_dm_connector(connector);
4562236b
HW		 620 }
621
622 return NULL;
623}
624
4562236b
HW		 625static int dm_resume(void *handle)
626{
627 struct amdgpu_device *adev = handle;
628 struct amdgpu_display_manager *dm = &adev->dm;
629
630 /* power on hardware */
1fb0c9cc 631 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
4562236b
HW		 632
633 return 0;
634}
635
1ecfc3da 636int amdgpu_dm_display_resume(struct amdgpu_device *adev)
4562236b
HW		 637{
638 struct drm_device *ddev = adev->ddev;
639 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 640 struct amdgpu_dm_connector *aconnector;
4562236b 641 struct drm_connector *connector;
4562236b 642 struct drm_crtc *crtc;
c2cea706 643 struct drm_crtc_state *new_crtc_state;
4f346e65
LSL		 644 struct dm_crtc_state *dm_crtc_state;
645 struct drm_plane *plane;
646 struct drm_plane_state *plane_state;
647 struct dm_plane_state *dm_plane_state;
648 struct dm_atomic_state *cached_state;
a3621485
AG		 649 int ret = 0;
650 int i;
4562236b
HW		 651
652 /* program HPD filter */
653 dc_resume(dm->dc);
654
655 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
656 s3_handle_mst(ddev, false);
657
658 /*
659 * early enable HPD Rx IRQ, should be done before set mode as short
660 * pulse interrupts are used for MST
661 */
662 amdgpu_dm_irq_resume_early(adev);
663
4562236b
HW		 664 /* Do detection*/
665 list_for_each_entry(connector,
666 &ddev->mode_config.connector_list, head) {
c84dec2f 667 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 668
669 /*
670 * this is the case when traversing through already created
671 * MST connectors, should be skipped
672 */
673 if (aconnector->mst_port)
674 continue;
675
03ea364c 676 mutex_lock(&aconnector->hpd_lock);
8f38b66c 677 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
4562236b
HW		 678 aconnector->dc_sink = NULL;
679 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 680 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 681 }
682
a3621485 683 /* Force mode set in atomic comit */
c2cea706
LSL		 684 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
685 new_crtc_state->active_changed = true;
a3621485 686
4f346e65
LSL		 687 cached_state = to_dm_atomic_state(adev->dm.cached_state);
688
689 /*
690 * During suspend, the cached state is saved before all streams are
691 * disabled. Refresh cached state to match actual current state before
692 * restoring it.
693 */
694 WARN_ON(kref_read(&cached_state->context->refcount) > 1);
695 dc_release_state(cached_state->context);
696
697 cached_state->context = dc_create_state();
5771ec8f 698 ASSERT(cached_state->context);
4f346e65
LSL		 699 dc_resource_state_copy_construct_current(adev->dm.dc, cached_state->context);
700
701 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
702 dm_crtc_state = to_dm_crtc_state(new_crtc_state);
703 if (dm_crtc_state->stream) {
704 WARN_ON(kref_read(&dm_crtc_state->stream->refcount) > 1);
705 dc_stream_release(dm_crtc_state->stream);
706 dm_crtc_state->stream = NULL;
707 }
708 }
709
710 for_each_new_plane_in_state(adev->dm.cached_state, plane, plane_state, i) {
711 dm_plane_state = to_dm_plane_state(plane_state);
712 if (dm_plane_state->dc_state) {
713 WARN_ON(kref_read(&dm_plane_state->dc_state->refcount) > 1);
714 dc_plane_state_release(dm_plane_state->dc_state);
715 dm_plane_state->dc_state = NULL;
716 }
717 }
718
a3621485 719 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 720
0a214e2f
AG		 721 drm_atomic_state_put(adev->dm.cached_state);
722 adev->dm.cached_state = NULL;
723
9faa4237 724 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 725
726 return ret;
727}
728
729static const struct amd_ip_funcs amdgpu_dm_funcs = {
730 .name = "dm",
731 .early_init = dm_early_init,
7abcf6b5 732 .late_init = dm_late_init,
4562236b
HW		 733 .sw_init = dm_sw_init,
734 .sw_fini = dm_sw_fini,
735 .hw_init = dm_hw_init,
736 .hw_fini = dm_hw_fini,
737 .suspend = dm_suspend,
738 .resume = dm_resume,
739 .is_idle = dm_is_idle,
740 .wait_for_idle = dm_wait_for_idle,
741 .check_soft_reset = dm_check_soft_reset,
742 .soft_reset = dm_soft_reset,
743 .set_clockgating_state = dm_set_clockgating_state,
744 .set_powergating_state = dm_set_powergating_state,
745};
746
747const struct amdgpu_ip_block_version dm_ip_block =
748{
749 .type = AMD_IP_BLOCK_TYPE_DCE,
750 .major = 1,
751 .minor = 0,
752 .rev = 0,
753 .funcs = &amdgpu_dm_funcs,
754};
755
ca3268c4 756
7578ecda 757static struct drm_atomic_state *
ca3268c4
HW		 758dm_atomic_state_alloc(struct drm_device *dev)
759{
760 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
761
1dc90497 762 if (!state)
ca3268c4 763 return NULL;
1dc90497
AG		 764
765 if (drm_atomic_state_init(dev, &state->base) < 0)
766 goto fail;
767
ca3268c4 768 return &state->base;
1dc90497
AG		 769
770fail:
771 kfree(state);
772 return NULL;
ca3268c4
HW		 773}
774
0a323b84
AG		 775static void
776dm_atomic_state_clear(struct drm_atomic_state *state)
777{
778 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
779
780 if (dm_state->context) {
608ac7bb 781 dc_release_state(dm_state->context);
0a323b84
AG		 782 dm_state->context = NULL;
783 }
784
785 drm_atomic_state_default_clear(state);
786}
787
788static void
789dm_atomic_state_alloc_free(struct drm_atomic_state *state)
790{
791 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
792 drm_atomic_state_default_release(state);
793 kfree(dm_state);
794}
795
b3663f70 796static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
a49dcb88
HW		 797 .fb_create = amdgpu_user_framebuffer_create,
798 .output_poll_changed = amdgpu_output_poll_changed,
4562236b 799 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 800 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 801 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 802 .atomic_state_clear = dm_atomic_state_clear,
803 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 804};
805
806static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
807 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 808};
809
7578ecda 810static void
3ee6b26b 811amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 812{
813 struct drm_connector *connector = &aconnector->base;
814 struct drm_device *dev = connector->dev;
b73a22d3 815 struct dc_sink *sink;
4562236b
HW		 816
817 /* MST handled by drm_mst framework */
818 if (aconnector->mst_mgr.mst_state == true)
819 return;
820
821
822 sink = aconnector->dc_link->local_sink;
823
824 /* Edid mgmt connector gets first update only in mode_valid hook and then
825 * the connector sink is set to either fake or physical sink depends on link status.
826 * don't do it here if u are during boot
827 */
828 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
829 && aconnector->dc_em_sink) {
830
ab2541b6 831 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 832 * because on resume connecotr->sink is set ti NULL
833 */
834 mutex_lock(&dev->mode_config.mutex);
835
836 if (sink) {
922aa1e1 837 if (aconnector->dc_sink) {
4562236b
HW		 838 amdgpu_dm_remove_sink_from_freesync_module(
839 connector);
922aa1e1
AG		 840 /* retain and release bellow are used for
841 * bump up refcount for sink because the link don't point
842 * to it anymore after disconnect so on next crtc to connector
843 * reshuffle by UMD we will get into unwanted dc_sink release
844 */
845 if (aconnector->dc_sink != aconnector->dc_em_sink)
846 dc_sink_release(aconnector->dc_sink);
847 }
4562236b
HW		 848 aconnector->dc_sink = sink;
849 amdgpu_dm_add_sink_to_freesync_module(
850 connector, aconnector->edid);
851 } else {
852 amdgpu_dm_remove_sink_from_freesync_module(connector);
853 if (!aconnector->dc_sink)
854 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 855 else if (aconnector->dc_sink != aconnector->dc_em_sink)
856 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 857 }
858
859 mutex_unlock(&dev->mode_config.mutex);
860 return;
861 }
862
863 /*
864 * TODO: temporary guard to look for proper fix
865 * if this sink is MST sink, we should not do anything
866 */
867 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
868 return;
869
870 if (aconnector->dc_sink == sink) {
871 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
872 * Do nothing!! */
f1ad2f5e 873 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 874 aconnector->connector_id);
875 return;
876 }
877
f1ad2f5e 878 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 879 aconnector->connector_id, aconnector->dc_sink, sink);
880
881 mutex_lock(&dev->mode_config.mutex);
882
883 /* 1. Update status of the drm connector
884 * 2. Send an event and let userspace tell us what to do */
885 if (sink) {
886 /* TODO: check if we still need the S3 mode update workaround.
887 * If yes, put it here. */
888 if (aconnector->dc_sink)
889 amdgpu_dm_remove_sink_from_freesync_module(
890 connector);
891
892 aconnector->dc_sink = sink;
900b3cb1 893 if (sink->dc_edid.length == 0) {
4562236b 894 aconnector->edid = NULL;
900b3cb1 895 } else {
4562236b
HW		 896 aconnector->edid =
897 (struct edid *) sink->dc_edid.raw_edid;
898
899
900 drm_mode_connector_update_edid_property(connector,
901 aconnector->edid);
902 }
903 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
904
905 } else {
906 amdgpu_dm_remove_sink_from_freesync_module(connector);
907 drm_mode_connector_update_edid_property(connector, NULL);
908 aconnector->num_modes = 0;
909 aconnector->dc_sink = NULL;
910 }
911
912 mutex_unlock(&dev->mode_config.mutex);
913}
914
915static void handle_hpd_irq(void *param)
916{
c84dec2f 917 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 918 struct drm_connector *connector = &aconnector->base;
919 struct drm_device *dev = connector->dev;
920
921 /* In case of failure or MST no need to update connector status or notify the OS
922 * since (for MST case) MST does this in it's own context.
923 */
924 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 925
926 if (aconnector->fake_enable)
927 aconnector->fake_enable = false;
928
8f38b66c 929 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 930 amdgpu_dm_update_connector_after_detect(aconnector);
931
932
933 drm_modeset_lock_all(dev);
934 dm_restore_drm_connector_state(dev, connector);
935 drm_modeset_unlock_all(dev);
936
937 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
938 drm_kms_helper_hotplug_event(dev);
939 }
940 mutex_unlock(&aconnector->hpd_lock);
941
942}
943
c84dec2f 944static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 945{
946 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
947 uint8_t dret;
948 bool new_irq_handled = false;
949 int dpcd_addr;
950 int dpcd_bytes_to_read;
951
952 const int max_process_count = 30;
953 int process_count = 0;
954
955 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
956
957 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
958 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
959 /* DPCD 0x200 - 0x201 for downstream IRQ */
960 dpcd_addr = DP_SINK_COUNT;
961 } else {
962 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
963 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
964 dpcd_addr = DP_SINK_COUNT_ESI;
965 }
966
967 dret = drm_dp_dpcd_read(
968 &aconnector->dm_dp_aux.aux,
969 dpcd_addr,
970 esi,
971 dpcd_bytes_to_read);
972
973 while (dret == dpcd_bytes_to_read &&
974 process_count < max_process_count) {
975 uint8_t retry;
976 dret = 0;
977
978 process_count++;
979
f1ad2f5e 980 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 981 /* handle HPD short pulse irq */
982 if (aconnector->mst_mgr.mst_state)
983 drm_dp_mst_hpd_irq(
984 &aconnector->mst_mgr,
985 esi,
986 &new_irq_handled);
4562236b
HW		 987
988 if (new_irq_handled) {
989 /* ACK at DPCD to notify down stream */
990 const int ack_dpcd_bytes_to_write =
991 dpcd_bytes_to_read - 1;
992
993 for (retry = 0; retry < 3; retry++) {
994 uint8_t wret;
995
996 wret = drm_dp_dpcd_write(
997 &aconnector->dm_dp_aux.aux,
998 dpcd_addr + 1,
999 &esi[1],
1000 ack_dpcd_bytes_to_write);
1001 if (wret == ack_dpcd_bytes_to_write)
1002 break;
1003 }
1004
1005 /* check if there is new irq to be handle */
1006 dret = drm_dp_dpcd_read(
1007 &aconnector->dm_dp_aux.aux,
1008 dpcd_addr,
1009 esi,
1010 dpcd_bytes_to_read);
1011
1012 new_irq_handled = false;
d4a6e8a9 1013 } else {
4562236b 1014 break;
d4a6e8a9 1015 }
4562236b
HW		 1016 }
1017
1018 if (process_count == max_process_count)
f1ad2f5e 1019 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1020}
1021
1022static void handle_hpd_rx_irq(void *param)
1023{
c84dec2f 1024 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1025 struct drm_connector *connector = &aconnector->base;
1026 struct drm_device *dev = connector->dev;
53cbf65c 1027 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 1028 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1029
1030 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1031 * conflict, after implement i2c helper, this mutex should be
1032 * retired.
1033 */
53cbf65c 1034 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1035 mutex_lock(&aconnector->hpd_lock);
1036
53cbf65c 1037 if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
4562236b
HW		 1038 !is_mst_root_connector) {
1039 /* Downstream Port status changed. */
53cbf65c 1040 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
4562236b
HW		 1041 amdgpu_dm_update_connector_after_detect(aconnector);
1042
1043
1044 drm_modeset_lock_all(dev);
1045 dm_restore_drm_connector_state(dev, connector);
1046 drm_modeset_unlock_all(dev);
1047
1048 drm_kms_helper_hotplug_event(dev);
1049 }
1050 }
1051 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1052 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1053 dm_handle_hpd_rx_irq(aconnector);
1054
53cbf65c 1055 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1056 mutex_unlock(&aconnector->hpd_lock);
1057}
1058
1059static void register_hpd_handlers(struct amdgpu_device *adev)
1060{
1061 struct drm_device *dev = adev->ddev;
1062 struct drm_connector *connector;
c84dec2f 1063 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1064 const struct dc_link *dc_link;
1065 struct dc_interrupt_params int_params = {0};
1066
1067 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1068 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1069
1070 list_for_each_entry(connector,
1071 &dev->mode_config.connector_list, head) {
1072
c84dec2f 1073 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1074 dc_link = aconnector->dc_link;
1075
1076 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1077 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1078 int_params.irq_source = dc_link->irq_source_hpd;
1079
1080 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1081 handle_hpd_irq,
1082 (void *) aconnector);
1083 }
1084
1085 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1086
1087 /* Also register for DP short pulse (hpd_rx). */
1088 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1089 int_params.irq_source = dc_link->irq_source_hpd_rx;
1090
1091 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1092 handle_hpd_rx_irq,
1093 (void *) aconnector);
1094 }
1095 }
1096}
1097
1098/* Register IRQ sources and initialize IRQ callbacks */
1099static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1100{
1101 struct dc *dc = adev->dm.dc;
1102 struct common_irq_params *c_irq_params;
1103 struct dc_interrupt_params int_params = {0};
1104 int r;
1105 int i;
2c8ad2d5
AD		 1106 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1107
ff5ef992
AD		 1108 if (adev->asic_type == CHIP_VEGA10 ||
1109 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1110 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1111
1112 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1113 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1114
1115 /* Actions of amdgpu_irq_add_id():
1116 * 1. Register a set() function with base driver.
1117 * Base driver will call set() function to enable/disable an
1118 * interrupt in DC hardware.
1119 * 2. Register amdgpu_dm_irq_handler().
1120 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1121 * coming from DC hardware.
1122 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1123 * for acknowledging and handling. */
1124
b57de80a 1125 /* Use VBLANK interrupt */
e9029155 1126 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1127 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1128 if (r) {
1129 DRM_ERROR("Failed to add crtc irq id!\n");
1130 return r;
1131 }
1132
1133 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1134 int_params.irq_source =
3d761e79 1135 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1136
b57de80a 1137 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1138
1139 c_irq_params->adev = adev;
1140 c_irq_params->irq_src = int_params.irq_source;
1141
1142 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1143 dm_crtc_high_irq, c_irq_params);
1144 }
1145
3d761e79 1146 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1147 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1148 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1149 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1150 if (r) {
1151 DRM_ERROR("Failed to add page flip irq id!\n");
1152 return r;
1153 }
1154
1155 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1156 int_params.irq_source =
1157 dc_interrupt_to_irq_source(dc, i, 0);
1158
1159 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1160
1161 c_irq_params->adev = adev;
1162 c_irq_params->irq_src = int_params.irq_source;
1163
1164 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1165 dm_pflip_high_irq, c_irq_params);
1166
1167 }
1168
1169 /* HPD */
2c8ad2d5
AD		 1170 r = amdgpu_irq_add_id(adev, client_id,
1171 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1172 if (r) {
1173 DRM_ERROR("Failed to add hpd irq id!\n");
1174 return r;
1175 }
1176
1177 register_hpd_handlers(adev);
1178
1179 return 0;
1180}
1181
ff5ef992
AD		 1182#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1183/* Register IRQ sources and initialize IRQ callbacks */
1184static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1185{
1186 struct dc *dc = adev->dm.dc;
1187 struct common_irq_params *c_irq_params;
1188 struct dc_interrupt_params int_params = {0};
1189 int r;
1190 int i;
1191
1192 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1193 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1194
1195 /* Actions of amdgpu_irq_add_id():
1196 * 1. Register a set() function with base driver.
1197 * Base driver will call set() function to enable/disable an
1198 * interrupt in DC hardware.
1199 * 2. Register amdgpu_dm_irq_handler().
1200 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1201 * coming from DC hardware.
1202 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1203 * for acknowledging and handling.
1204 * */
1205
1206 /* Use VSTARTUP interrupt */
1207 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1208 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1209 i++) {
1210 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1211
1212 if (r) {
1213 DRM_ERROR("Failed to add crtc irq id!\n");
1214 return r;
1215 }
1216
1217 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1218 int_params.irq_source =
1219 dc_interrupt_to_irq_source(dc, i, 0);
1220
1221 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1222
1223 c_irq_params->adev = adev;
1224 c_irq_params->irq_src = int_params.irq_source;
1225
1226 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1227 dm_crtc_high_irq, c_irq_params);
1228 }
1229
1230 /* Use GRPH_PFLIP interrupt */
1231 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1232 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1233 i++) {
1234 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1235 if (r) {
1236 DRM_ERROR("Failed to add page flip irq id!\n");
1237 return r;
1238 }
1239
1240 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1241 int_params.irq_source =
1242 dc_interrupt_to_irq_source(dc, i, 0);
1243
1244 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1245
1246 c_irq_params->adev = adev;
1247 c_irq_params->irq_src = int_params.irq_source;
1248
1249 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1250 dm_pflip_high_irq, c_irq_params);
1251
1252 }
1253
1254 /* HPD */
1255 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1256 &adev->hpd_irq);
1257 if (r) {
1258 DRM_ERROR("Failed to add hpd irq id!\n");
1259 return r;
1260 }
1261
1262 register_hpd_handlers(adev);
1263
1264 return 0;
1265}
1266#endif
1267
4562236b
HW		 1268static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1269{
1270 int r;
1271
1272 adev->mode_info.mode_config_initialized = true;
1273
4562236b 1274 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1275 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1276
1277 adev->ddev->mode_config.max_width = 16384;
1278 adev->ddev->mode_config.max_height = 16384;
1279
1280 adev->ddev->mode_config.preferred_depth = 24;
1281 adev->ddev->mode_config.prefer_shadow = 1;
1282 /* indicate support of immediate flip */
1283 adev->ddev->mode_config.async_page_flip = true;
1284
1285 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1286
1287 r = amdgpu_modeset_create_props(adev);
1288 if (r)
1289 return r;
1290
1291 return 0;
1292}
1293
1294#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1295 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1296
1297static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1298{
1299 struct amdgpu_display_manager *dm = bl_get_data(bd);
1300
1301 if (dc_link_set_backlight_level(dm->backlight_link,
1302 bd->props.brightness, 0, 0))
1303 return 0;
1304 else
1305 return 1;
1306}
1307
1308static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1309{
1310 return bd->props.brightness;
1311}
1312
1313static const struct backlight_ops amdgpu_dm_backlight_ops = {
1314 .get_brightness = amdgpu_dm_backlight_get_brightness,
1315 .update_status = amdgpu_dm_backlight_update_status,
1316};
1317
7578ecda
AD		 1318static void
1319amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1320{
1321 char bl_name[16];
1322 struct backlight_properties props = { 0 };
1323
1324 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1325 props.type = BACKLIGHT_RAW;
1326
1327 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1328 dm->adev->ddev->primary->index);
1329
1330 dm->backlight_dev = backlight_device_register(bl_name,
1331 dm->adev->ddev->dev,
1332 dm,
1333 &amdgpu_dm_backlight_ops,
1334 &props);
1335
1336 if (NULL == dm->backlight_dev)
1337 DRM_ERROR("DM: Backlight registration failed!\n");
1338 else
f1ad2f5e 1339 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1340}
1341
1342#endif
1343
1344/* In this architecture, the association
1345 * connector -> encoder -> crtc
1346 * id not really requried. The crtc and connector will hold the
1347 * display_index as an abstraction to use with DAL component
1348 *
1349 * Returns 0 on success
1350 */
7578ecda 1351static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1352{
1353 struct amdgpu_display_manager *dm = &adev->dm;
1354 uint32_t i;
c84dec2f 1355 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1356 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1357 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1358 uint32_t link_cnt;
92f3ac40 1359 unsigned long possible_crtcs;
4562236b
HW		 1360
1361 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1362 if (amdgpu_dm_mode_config_init(dm->adev)) {
1363 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1364 return -1;
4562236b
HW		 1365 }
1366
3be5262e 1367 for (i = 0; i < dm->dc->caps.max_planes; i++) {
d4e13b0d
AD		 1368 mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),
1369 GFP_KERNEL);
1370 if (!mode_info->planes[i]) {
3be5262e 1371 DRM_ERROR("KMS: Failed to allocate plane\n");
d4e13b0d
AD		 1372 goto fail_free_planes;
1373 }
1605b3be 1374 mode_info->planes[i]->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1375
1376 /*
1377 * HACK: IGT tests expect that each plane can only have one
1378 * one possible CRTC. For now, set one CRTC for each
1379 * plane that is not an underlay, but still allow multiple
1380 * CRTCs for underlay planes.
1381 */
1382 possible_crtcs = 1 << i;
1383 if (i >= dm->dc->caps.max_streams)
1384 possible_crtcs = 0xff;
1385
1386 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d
AD		 1387 DRM_ERROR("KMS: Failed to initialize plane\n");
1388 goto fail_free_planes;
1389 }
1390 }
4562236b 1391
d4e13b0d
AD		 1392 for (i = 0; i < dm->dc->caps.max_streams; i++)
1393 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1394 DRM_ERROR("KMS: Failed to initialize crtc\n");
d4e13b0d 1395 goto fail_free_planes;
4562236b 1396 }
4562236b 1397
ab2541b6 1398 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1399
1400 /* loops over all connectors on the board */
1401 for (i = 0; i < link_cnt; i++) {
1402
1403 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1404 DRM_ERROR(
1405 "KMS: Cannot support more than %d display indexes\n",
1406 AMDGPU_DM_MAX_DISPLAY_INDEX);
1407 continue;
1408 }
1409
1410 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1411 if (!aconnector)
f2a0f5e6 1412 goto fail_free_planes;
4562236b
HW		 1413
1414 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1415 if (!aencoder)
4562236b 1416 goto fail_free_connector;
4562236b
HW		 1417
1418 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1419 DRM_ERROR("KMS: Failed to initialize encoder\n");
1420 goto fail_free_encoder;
1421 }
1422
1423 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1424 DRM_ERROR("KMS: Failed to initialize connector\n");
f2a0f5e6 1425 goto fail_free_encoder;
4562236b
HW		 1426 }
1427
8f38b66c
HW		 1428 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1429 DETECT_REASON_BOOT))
4562236b
HW		 1430 amdgpu_dm_update_connector_after_detect(aconnector);
1431 }
1432
1433 /* Software is initialized. Now we can register interrupt handlers. */
1434 switch (adev->asic_type) {
1435 case CHIP_BONAIRE:
1436 case CHIP_HAWAII:
cd4b356f
AD		 1437 case CHIP_KAVERI:
1438 case CHIP_KABINI:
1439 case CHIP_MULLINS:
4562236b
HW		 1440 case CHIP_TONGA:
1441 case CHIP_FIJI:
1442 case CHIP_CARRIZO:
1443 case CHIP_STONEY:
1444 case CHIP_POLARIS11:
1445 case CHIP_POLARIS10:
b264d345 1446 case CHIP_POLARIS12:
2c8ad2d5 1447 case CHIP_VEGA10:
4562236b
HW		 1448 if (dce110_register_irq_handlers(dm->adev)) {
1449 DRM_ERROR("DM: Failed to initialize IRQ\n");
d4e13b0d 1450 goto fail_free_encoder;
4562236b
HW		 1451 }
1452 break;
ff5ef992
AD		 1453#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1454 case CHIP_RAVEN:
1455 if (dcn10_register_irq_handlers(dm->adev)) {
1456 DRM_ERROR("DM: Failed to initialize IRQ\n");
1457 goto fail_free_encoder;
1458 }
79c24086
BL		 1459 /*
1460 * Temporary disable until pplib/smu interaction is implemented
1461 */
1462 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1463 break;
1464#endif
4562236b
HW		 1465 default:
1466 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
d4e13b0d 1467 goto fail_free_encoder;
4562236b
HW		 1468 }
1469
1470 drm_mode_config_reset(dm->ddev);
1471
1472 return 0;
1473fail_free_encoder:
1474 kfree(aencoder);
1475fail_free_connector:
1476 kfree(aconnector);
d4e13b0d 1477fail_free_planes:
3be5262e 1478 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1479 kfree(mode_info->planes[i]);
4562236b
HW		 1480 return -1;
1481}
1482
7578ecda 1483static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1484{
1485 drm_mode_config_cleanup(dm->ddev);
1486 return;
1487}
1488
1489/******************************************************************************
1490 * amdgpu_display_funcs functions
1491 *****************************************************************************/
1492
1493/**
1494 * dm_bandwidth_update - program display watermarks
1495 *
1496 * @adev: amdgpu_device pointer
1497 *
1498 * Calculate and program the display watermarks and line buffer allocation.
1499 */
1500static void dm_bandwidth_update(struct amdgpu_device *adev)
1501{
49c07a99 1502 /* TODO: implement later */
4562236b
HW		 1503}
1504
1505static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1506 u8 level)
1507{
1508 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1509}
1510
1511static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1512{
1513 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1514 return 0;
1515}
1516
4562236b
HW		 1517static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1518 struct drm_file *filp)
1519{
1520 struct mod_freesync_params freesync_params;
ab2541b6 1521 uint8_t num_streams;
4562236b 1522 uint8_t i;
4562236b
HW		 1523
1524 struct amdgpu_device *adev = dev->dev_private;
1525 int r = 0;
1526
1527 /* Get freesync enable flag from DRM */
1528
ab2541b6 1529 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1530
ab2541b6 1531 for (i = 0; i < num_streams; i++) {
0971c40e 1532 struct dc_stream_state *stream;
ab2541b6 1533 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1534
1535 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1536 &stream, 1, &freesync_params);
4562236b
HW		 1537 }
1538
1539 return r;
1540}
1541
39cc5be2 1542static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1543 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1544 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1545 .vblank_wait = NULL,
1546 .backlight_set_level =
1547 dm_set_backlight_level,/* called unconditionally */
1548 .backlight_get_level =
1549 dm_get_backlight_level,/* called unconditionally */
1550 .hpd_sense = NULL,/* called unconditionally */
1551 .hpd_set_polarity = NULL, /* called unconditionally */
1552 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1553 .page_flip_get_scanoutpos =
1554 dm_crtc_get_scanoutpos,/* called unconditionally */
1555 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1556 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1557 .notify_freesync = amdgpu_notify_freesync,
1558
1559};
1560
1561#if defined(CONFIG_DEBUG_KERNEL_DC)
1562
3ee6b26b
AD		 1563static ssize_t s3_debug_store(struct device *device,
1564 struct device_attribute *attr,
1565 const char *buf,
1566 size_t count)
4562236b
HW		 1567{
1568 int ret;
1569 int s3_state;
1570 struct pci_dev *pdev = to_pci_dev(device);
1571 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1572 struct amdgpu_device *adev = drm_dev->dev_private;
1573
1574 ret = kstrtoint(buf, 0, &s3_state);
1575
1576 if (ret == 0) {
1577 if (s3_state) {
1578 dm_resume(adev);
1579 amdgpu_dm_display_resume(adev);
1580 drm_kms_helper_hotplug_event(adev->ddev);
1581 } else
1582 dm_suspend(adev);
1583 }
1584
1585 return ret == 0 ? count : 0;
1586}
1587
1588DEVICE_ATTR_WO(s3_debug);
1589
1590#endif
1591
1592static int dm_early_init(void *handle)
1593{
1594 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1595
d7ec53d9 1596 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
4562236b
HW		 1597 amdgpu_dm_set_irq_funcs(adev);
1598
1599 switch (adev->asic_type) {
1600 case CHIP_BONAIRE:
1601 case CHIP_HAWAII:
1602 adev->mode_info.num_crtc = 6;
1603 adev->mode_info.num_hpd = 6;
1604 adev->mode_info.num_dig = 6;
3be5262e 1605 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1606 break;
cd4b356f
AD		 1607 case CHIP_KAVERI:
1608 adev->mode_info.num_crtc = 4;
1609 adev->mode_info.num_hpd = 6;
1610 adev->mode_info.num_dig = 7;
1611 adev->mode_info.plane_type = dm_plane_type_default;
1612 break;
1613 case CHIP_KABINI:
1614 case CHIP_MULLINS:
1615 adev->mode_info.num_crtc = 2;
1616 adev->mode_info.num_hpd = 6;
1617 adev->mode_info.num_dig = 6;
1618 adev->mode_info.plane_type = dm_plane_type_default;
1619 break;
4562236b
HW		 1620 case CHIP_FIJI:
1621 case CHIP_TONGA:
1622 adev->mode_info.num_crtc = 6;
1623 adev->mode_info.num_hpd = 6;
1624 adev->mode_info.num_dig = 7;
3be5262e 1625 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1626 break;
1627 case CHIP_CARRIZO:
1628 adev->mode_info.num_crtc = 3;
1629 adev->mode_info.num_hpd = 6;
1630 adev->mode_info.num_dig = 9;
3be5262e 1631 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1632 break;
1633 case CHIP_STONEY:
1634 adev->mode_info.num_crtc = 2;
1635 adev->mode_info.num_hpd = 6;
1636 adev->mode_info.num_dig = 9;
3be5262e 1637 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1638 break;
1639 case CHIP_POLARIS11:
b264d345 1640 case CHIP_POLARIS12:
4562236b
HW		 1641 adev->mode_info.num_crtc = 5;
1642 adev->mode_info.num_hpd = 5;
1643 adev->mode_info.num_dig = 5;
3be5262e 1644 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1645 break;
1646 case CHIP_POLARIS10:
1647 adev->mode_info.num_crtc = 6;
1648 adev->mode_info.num_hpd = 6;
1649 adev->mode_info.num_dig = 6;
3be5262e 1650 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1651 break;
2c8ad2d5
AD		 1652 case CHIP_VEGA10:
1653 adev->mode_info.num_crtc = 6;
1654 adev->mode_info.num_hpd = 6;
1655 adev->mode_info.num_dig = 6;
3be5262e 1656 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1657 break;
ff5ef992
AD		 1658#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1659 case CHIP_RAVEN:
1660 adev->mode_info.num_crtc = 4;
1661 adev->mode_info.num_hpd = 4;
1662 adev->mode_info.num_dig = 4;
3be5262e 1663 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1664 break;
1665#endif
4562236b
HW		 1666 default:
1667 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1668 return -EINVAL;
1669 }
1670
39cc5be2
AD		 1671 if (adev->mode_info.funcs == NULL)
1672 adev->mode_info.funcs = &dm_display_funcs;
1673
4562236b
HW		 1674 /* Note: Do NOT change adev->audio_endpt_rreg and
1675 * adev->audio_endpt_wreg because they are initialised in
1676 * amdgpu_device_init() */
1677#if defined(CONFIG_DEBUG_KERNEL_DC)
1678 device_create_file(
1679 adev->ddev->dev,
1680 &dev_attr_s3_debug);
1681#endif
1682
1683 return 0;
1684}
1685
e7b07cee
HW		 1686struct dm_connector_state {
1687 struct drm_connector_state base;
1688
1689 enum amdgpu_rmx_type scaling;
1690 uint8_t underscan_vborder;
1691 uint8_t underscan_hborder;
1692 bool underscan_enable;
1693};
1694
1695#define to_dm_connector_state(x)\
1696 container_of((x), struct dm_connector_state, base)
1697
9b690ef3 1698static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1699 struct dc_stream_state *new_stream,
1700 struct dc_stream_state *old_stream)
9b690ef3 1701{
e7b07cee
HW		 1702 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1703 return false;
1704
1705 if (!crtc_state->enable)
1706 return false;
1707
1708 return crtc_state->active;
1709}
1710
1711static bool modereset_required(struct drm_crtc_state *crtc_state)
1712{
1713 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1714 return false;
1715
1716 return !crtc_state->enable || !crtc_state->active;
1717}
1718
7578ecda 1719static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1720{
1721 drm_encoder_cleanup(encoder);
1722 kfree(encoder);
1723}
1724
1725static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1726 .destroy = amdgpu_dm_encoder_destroy,
1727};
1728
3ee6b26b
AD		 1729static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1730 struct dc_plane_state *plane_state)
e7b07cee 1731{
3be5262e
HW		 1732 plane_state->src_rect.x = state->src_x >> 16;
1733 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1734 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1735 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1736
3be5262e 1737 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1738 return false;
1739
3be5262e
HW		 1740 plane_state->src_rect.height = state->src_h >> 16;
1741 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1742 return false;
1743
3be5262e
HW		 1744 plane_state->dst_rect.x = state->crtc_x;
1745 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1746
1747 if (state->crtc_w == 0)
1748 return false;
1749
3be5262e 1750 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1751
1752 if (state->crtc_h == 0)
1753 return false;
1754
3be5262e 1755 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1756
3be5262e 1757 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1758
1759 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1760 case DRM_MODE_ROTATE_0:
3be5262e 1761 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1762 break;
1763 case DRM_MODE_ROTATE_90:
3be5262e 1764 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1765 break;
1766 case DRM_MODE_ROTATE_180:
3be5262e 1767 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1768 break;
1769 case DRM_MODE_ROTATE_270:
3be5262e 1770 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1771 break;
1772 default:
3be5262e 1773 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1774 break;
1775 }
1776
4562236b
HW		 1777 return true;
1778}
3ee6b26b
AD		 1779static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1780 uint64_t *tiling_flags,
1781 uint64_t *fb_location)
e7b07cee
HW		 1782{
1783 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1784 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1785
e7b07cee 1786 if (unlikely(r)) {
9bbc3031
JZ		 1787 // Don't show error msg. when return -ERESTARTSYS
1788 if (r != -ERESTARTSYS)
1789 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1790 return r;
1791 }
1792
1793 if (fb_location)
1794 *fb_location = amdgpu_bo_gpu_offset(rbo);
1795
1796 if (tiling_flags)
1797 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1798
1799 amdgpu_bo_unreserve(rbo);
1800
1801 return r;
1802}
1803
3ee6b26b
AD		 1804static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1805 struct dc_plane_state *plane_state,
1806 const struct amdgpu_framebuffer *amdgpu_fb,
1807 bool addReq)
e7b07cee
HW		 1808{
1809 uint64_t tiling_flags;
1810 uint64_t fb_location = 0;
1811 unsigned int awidth;
1812 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1813 int ret = 0;
1814 struct drm_format_name_buf format_name;
1815
1816 ret = get_fb_info(
1817 amdgpu_fb,
1818 &tiling_flags,
1819 addReq == true ? &fb_location:NULL);
1820
1821 if (ret)
1822 return ret;
1823
1824 switch (fb->format->format) {
1825 case DRM_FORMAT_C8:
3be5262e 1826 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1827 break;
1828 case DRM_FORMAT_RGB565:
3be5262e 1829 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1830 break;
1831 case DRM_FORMAT_XRGB8888:
1832 case DRM_FORMAT_ARGB8888:
3be5262e 1833 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1834 break;
1835 case DRM_FORMAT_XRGB2101010:
1836 case DRM_FORMAT_ARGB2101010:
3be5262e 1837 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1838 break;
1839 case DRM_FORMAT_XBGR2101010:
1840 case DRM_FORMAT_ABGR2101010:
3be5262e 1841 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1842 break;
1843 case DRM_FORMAT_NV21:
3be5262e 1844 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1845 break;
1846 case DRM_FORMAT_NV12:
3be5262e 1847 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1848 break;
1849 default:
1850 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1851 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1852 return -EINVAL;
1853 }
1854
3be5262e
HW		 1855 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1856 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1857 plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
1858 plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
1859 plane_state->plane_size.grph.surface_size.x = 0;
1860 plane_state->plane_size.grph.surface_size.y = 0;
1861 plane_state->plane_size.grph.surface_size.width = fb->width;
1862 plane_state->plane_size.grph.surface_size.height = fb->height;
1863 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1864 fb->pitches[0] / fb->format->cpp[0];
1865 /* TODO: unhardcode */
3be5262e 1866 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1867
1868 } else {
1869 awidth = ALIGN(fb->width, 64);
3be5262e
HW		 1870 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1871 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 1872 = lower_32_bits(fb_location);
3be5262e 1873 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 1874 = lower_32_bits(fb_location) +
1875 (awidth * fb->height);
3be5262e
HW		 1876 plane_state->plane_size.video.luma_size.x = 0;
1877 plane_state->plane_size.video.luma_size.y = 0;
1878 plane_state->plane_size.video.luma_size.width = awidth;
1879 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1880 /* TODO: unhardcode */
3be5262e 1881 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1882
3be5262e
HW		 1883 plane_state->plane_size.video.chroma_size.x = 0;
1884 plane_state->plane_size.video.chroma_size.y = 0;
1885 plane_state->plane_size.video.chroma_size.width = awidth;
1886 plane_state->plane_size.video.chroma_size.height = fb->height;
1887 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1888
1889 /* TODO: unhardcode */
3be5262e 1890 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1891 }
1892
3be5262e 1893 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1894
b830ebc9
HW		 1895 /* Fill GFX8 params */
1896 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1897 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1898
1899 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1900 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1901 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1902 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1903 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1904
1905 /* XXX fix me for VI */
3be5262e
HW		 1906 plane_state->tiling_info.gfx8.num_banks = num_banks;
1907 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1908 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1909 plane_state->tiling_info.gfx8.tile_split = tile_split;
1910 plane_state->tiling_info.gfx8.bank_width = bankw;
1911 plane_state->tiling_info.gfx8.bank_height = bankh;
1912 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1913 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1914 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1915 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1916 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1917 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1918 }
1919
3be5262e 1920 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1921 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1922
1923 if (adev->asic_type == CHIP_VEGA10 ||
1924 adev->asic_type == CHIP_RAVEN) {
1925 /* Fill GFX9 params */
3be5262e 1926 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1927 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1928 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1929 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1930 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1931 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1932 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1933 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1934 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1935 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1936 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1937 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1938 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1939 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1940 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1941 }
1942
3be5262e
HW		 1943 plane_state->visible = true;
1944 plane_state->scaling_quality.h_taps_c = 0;
1945 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1946
3be5262e
HW		 1947 /* is this needed? is plane_state zeroed at allocation? */
1948 plane_state->scaling_quality.h_taps = 0;
1949 plane_state->scaling_quality.v_taps = 0;
1950 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1951
1952 return ret;
1953
1954}
1955
3ee6b26b
AD		 1956static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state,
1957 struct dc_plane_state *plane_state)
e7b07cee
HW		 1958{
1959 int i;
1960 struct dc_gamma *gamma;
d66cf5f5
AK		 1961 struct drm_color_lut *lut =
1962 (struct drm_color_lut *) crtc_state->gamma_lut->data;
e7b07cee
HW		 1963
1964 gamma = dc_create_gamma();
1965
1966 if (gamma == NULL) {
1967 WARN_ON(1);
1968 return;
1969 }
1970
7483bed4
HW		 1971 gamma->type = GAMMA_RGB_256;
1972 gamma->num_entries = GAMMA_RGB_256_ENTRIES;
d66cf5f5
AK		 1973 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1974 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1975 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1976 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
e7b07cee
HW		 1977 }
1978
3be5262e 1979 plane_state->gamma_correction = gamma;
e7b07cee
HW		 1980}
1981
3ee6b26b
AD		 1982static int fill_plane_attributes(struct amdgpu_device *adev,
1983 struct dc_plane_state *dc_plane_state,
1984 struct drm_plane_state *plane_state,
1985 struct drm_crtc_state *crtc_state,
1986 bool addrReq)
e7b07cee
HW		 1987{
1988 const struct amdgpu_framebuffer *amdgpu_fb =
1989 to_amdgpu_framebuffer(plane_state->fb);
1990 const struct drm_crtc *crtc = plane_state->crtc;
1991 struct dc_transfer_func *input_tf;
1992 int ret = 0;
1993
3be5262e 1994 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1995 return -EINVAL;
1996
1997 ret = fill_plane_attributes_from_fb(
1998 crtc->dev->dev_private,
3be5262e 1999 dc_plane_state,
e7b07cee
HW		 2000 amdgpu_fb,
2001 addrReq);
2002
2003 if (ret)
2004 return ret;
2005
2006 input_tf = dc_create_transfer_func();
2007
2008 if (input_tf == NULL)
2009 return -ENOMEM;
2010
2011 input_tf->type = TF_TYPE_PREDEFINED;
2012 input_tf->tf = TRANSFER_FUNCTION_SRGB;
2013
3be5262e 2014 dc_plane_state->in_transfer_func = input_tf;
e7b07cee
HW		 2015
2016 /* In case of gamma set, update gamma value */
2017 if (crtc_state->gamma_lut)
3be5262e 2018 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
e7b07cee
HW		 2019
2020 return ret;
2021}
2022
2023/*****************************************************************************/
2024
3ee6b26b
AD		 2025static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2026 const struct dm_connector_state *dm_state,
2027 struct dc_stream_state *stream)
e7b07cee
HW		 2028{
2029 enum amdgpu_rmx_type rmx_type;
2030
2031 struct rect src = { 0 }; /* viewport in composition space*/
2032 struct rect dst = { 0 }; /* stream addressable area */
2033
2034 /* no mode. nothing to be done */
2035 if (!mode)
2036 return;
2037
2038 /* Full screen scaling by default */
2039 src.width = mode->hdisplay;
2040 src.height = mode->vdisplay;
2041 dst.width = stream->timing.h_addressable;
2042 dst.height = stream->timing.v_addressable;
2043
2044 rmx_type = dm_state->scaling;
2045 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2046 if (src.width * dst.height <
2047 src.height * dst.width) {
2048 /* height needs less upscaling/more downscaling */
2049 dst.width = src.width *
2050 dst.height / src.height;
2051 } else {
2052 /* width needs less upscaling/more downscaling */
2053 dst.height = src.height *
2054 dst.width / src.width;
2055 }
2056 } else if (rmx_type == RMX_CENTER) {
2057 dst = src;
2058 }
2059
2060 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2061 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2062
2063 if (dm_state->underscan_enable) {
2064 dst.x += dm_state->underscan_hborder / 2;
2065 dst.y += dm_state->underscan_vborder / 2;
2066 dst.width -= dm_state->underscan_hborder;
2067 dst.height -= dm_state->underscan_vborder;
2068 }
2069
2070 stream->src = src;
2071 stream->dst = dst;
2072
f1ad2f5e 2073 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2074 dst.x, dst.y, dst.width, dst.height);
2075
2076}
2077
3ee6b26b
AD		 2078static enum dc_color_depth
2079convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2080{
2081 uint32_t bpc = connector->display_info.bpc;
2082
2083 /* Limited color depth to 8bit
b830ebc9
HW		 2084 * TODO: Still need to handle deep color
2085 */
e7b07cee
HW		 2086 if (bpc > 8)
2087 bpc = 8;
2088
2089 switch (bpc) {
2090 case 0:
2091 /* Temporary Work around, DRM don't parse color depth for
2092 * EDID revision before 1.4
2093 * TODO: Fix edid parsing
2094 */
2095 return COLOR_DEPTH_888;
2096 case 6:
2097 return COLOR_DEPTH_666;
2098 case 8:
2099 return COLOR_DEPTH_888;
2100 case 10:
2101 return COLOR_DEPTH_101010;
2102 case 12:
2103 return COLOR_DEPTH_121212;
2104 case 14:
2105 return COLOR_DEPTH_141414;
2106 case 16:
2107 return COLOR_DEPTH_161616;
2108 default:
2109 return COLOR_DEPTH_UNDEFINED;
2110 }
2111}
2112
3ee6b26b
AD		 2113static enum dc_aspect_ratio
2114get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2115{
2116 int32_t width = mode_in->crtc_hdisplay * 9;
2117 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2118
e7b07cee
HW		 2119 if ((width - height) < 10 && (width - height) > -10)
2120 return ASPECT_RATIO_16_9;
2121 else
2122 return ASPECT_RATIO_4_3;
2123}
2124
3ee6b26b
AD		 2125static enum dc_color_space
2126get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2127{
2128 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2129
2130 switch (dc_crtc_timing->pixel_encoding) {
2131 case PIXEL_ENCODING_YCBCR422:
2132 case PIXEL_ENCODING_YCBCR444:
2133 case PIXEL_ENCODING_YCBCR420:
2134 {
2135 /*
2136 * 27030khz is the separation point between HDTV and SDTV
2137 * according to HDMI spec, we use YCbCr709 and YCbCr601
2138 * respectively
2139 */
2140 if (dc_crtc_timing->pix_clk_khz > 27030) {
2141 if (dc_crtc_timing->flags.Y_ONLY)
2142 color_space =
2143 COLOR_SPACE_YCBCR709_LIMITED;
2144 else
2145 color_space = COLOR_SPACE_YCBCR709;
2146 } else {
2147 if (dc_crtc_timing->flags.Y_ONLY)
2148 color_space =
2149 COLOR_SPACE_YCBCR601_LIMITED;
2150 else
2151 color_space = COLOR_SPACE_YCBCR601;
2152 }
2153
2154 }
2155 break;
2156 case PIXEL_ENCODING_RGB:
2157 color_space = COLOR_SPACE_SRGB;
2158 break;
2159
2160 default:
2161 WARN_ON(1);
2162 break;
2163 }
2164
2165 return color_space;
2166}
2167
2168/*****************************************************************************/
2169
3ee6b26b
AD		 2170static void
2171fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2172 const struct drm_display_mode *mode_in,
2173 const struct drm_connector *connector)
e7b07cee
HW		 2174{
2175 struct dc_crtc_timing *timing_out = &stream->timing;
b830ebc9 2176
e7b07cee
HW		 2177 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2178
2179 timing_out->h_border_left = 0;
2180 timing_out->h_border_right = 0;
2181 timing_out->v_border_top = 0;
2182 timing_out->v_border_bottom = 0;
2183 /* TODO: un-hardcode */
2184
2185 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2186 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2187 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2188 else
2189 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2190
2191 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2192 timing_out->display_color_depth = convert_color_depth_from_display_info(
2193 connector);
2194 timing_out->scan_type = SCANNING_TYPE_NODATA;
2195 timing_out->hdmi_vic = 0;
2196 timing_out->vic = drm_match_cea_mode(mode_in);
2197
2198 timing_out->h_addressable = mode_in->crtc_hdisplay;
2199 timing_out->h_total = mode_in->crtc_htotal;
2200 timing_out->h_sync_width =
2201 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2202 timing_out->h_front_porch =
2203 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2204 timing_out->v_total = mode_in->crtc_vtotal;
2205 timing_out->v_addressable = mode_in->crtc_vdisplay;
2206 timing_out->v_front_porch =
2207 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2208 timing_out->v_sync_width =
2209 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2210 timing_out->pix_clk_khz = mode_in->crtc_clock;
2211 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2212 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2213 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2214 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2215 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2216
2217 stream->output_color_space = get_output_color_space(timing_out);
2218
2219 {
2220 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2221
e7b07cee
HW		 2222 tf->type = TF_TYPE_PREDEFINED;
2223 tf->tf = TRANSFER_FUNCTION_SRGB;
2224 stream->out_transfer_func = tf;
2225 }
2226}
2227
3ee6b26b
AD		 2228static void fill_audio_info(struct audio_info *audio_info,
2229 const struct drm_connector *drm_connector,
2230 const struct dc_sink *dc_sink)
e7b07cee
HW		 2231{
2232 int i = 0;
2233 int cea_revision = 0;
2234 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2235
2236 audio_info->manufacture_id = edid_caps->manufacturer_id;
2237 audio_info->product_id = edid_caps->product_id;
2238
2239 cea_revision = drm_connector->display_info.cea_rev;
2240
2241 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
2242 edid_caps->display_name[i]) {
2243 audio_info->display_name[i] = edid_caps->display_name[i];
2244 i++;
2245 }
2246
b830ebc9 2247 if (cea_revision >= 3) {
e7b07cee
HW		 2248 audio_info->mode_count = edid_caps->audio_mode_count;
2249
2250 for (i = 0; i < audio_info->mode_count; ++i) {
2251 audio_info->modes[i].format_code =
2252 (enum audio_format_code)
2253 (edid_caps->audio_modes[i].format_code);
2254 audio_info->modes[i].channel_count =
2255 edid_caps->audio_modes[i].channel_count;
2256 audio_info->modes[i].sample_rates.all =
2257 edid_caps->audio_modes[i].sample_rate;
2258 audio_info->modes[i].sample_size =
2259 edid_caps->audio_modes[i].sample_size;
2260 }
2261 }
2262
2263 audio_info->flags.all = edid_caps->speaker_flags;
2264
2265 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2266 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2267 audio_info->video_latency = drm_connector->video_latency[0];
2268 audio_info->audio_latency = drm_connector->audio_latency[0];
2269 }
2270
2271 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2272
2273}
2274
3ee6b26b
AD		 2275static void
2276copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2277 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2278{
2279 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2280 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2281 dst_mode->crtc_clock = src_mode->crtc_clock;
2282 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2283 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2284 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2285 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2286 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2287 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2288 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2289 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2290 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2291 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2292 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2293}
2294
3ee6b26b
AD		 2295static void
2296decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2297 const struct drm_display_mode *native_mode,
2298 bool scale_enabled)
e7b07cee
HW		 2299{
2300 if (scale_enabled) {
2301 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2302 } else if (native_mode->clock == drm_mode->clock &&
2303 native_mode->htotal == drm_mode->htotal &&
2304 native_mode->vtotal == drm_mode->vtotal) {
2305 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2306 } else {
2307 /* no scaling nor amdgpu inserted, no need to patch */
2308 }
2309}
2310
2e0ac3d6
HW		 2311static void create_fake_sink(struct amdgpu_dm_connector *aconnector)
2312{
2313 struct dc_sink *sink = NULL;
2314 struct dc_sink_init_data sink_init_data = { 0 };
2315
2316 sink_init_data.link = aconnector->dc_link;
2317 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2318
2319 sink = dc_sink_create(&sink_init_data);
2320 if (!sink)
2321 DRM_ERROR("Failed to create sink!\n");
2322
2323 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2324 aconnector->fake_enable = true;
2325
2326 aconnector->dc_sink = sink;
2327 aconnector->dc_link->local_sink = sink;
2328}
2329
3ee6b26b
AD		 2330static struct dc_stream_state *
2331create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2332 const struct drm_display_mode *drm_mode,
2333 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2334{
2335 struct drm_display_mode *preferred_mode = NULL;
2336 const struct drm_connector *drm_connector;
0971c40e 2337 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2338 struct drm_display_mode mode = *drm_mode;
2339 bool native_mode_found = false;
2340
b830ebc9 2341 if (aconnector == NULL) {
e7b07cee
HW		 2342 DRM_ERROR("aconnector is NULL!\n");
2343 goto drm_connector_null;
2344 }
2345
b830ebc9 2346 if (dm_state == NULL) {
e7b07cee
HW		 2347 DRM_ERROR("dm_state is NULL!\n");
2348 goto dm_state_null;
2349 }
4562236b 2350
e7b07cee 2351 drm_connector = &aconnector->base;
2e0ac3d6 2352
f4ac176e
JZ		 2353 if (!aconnector->dc_sink) {
2354 /*
2355 * Exclude MST from creating fake_sink
2356 * TODO: need to enable MST into fake_sink feature
2357 */
2358 if (aconnector->mst_port)
2359 goto stream_create_fail;
2360
2e0ac3d6 2361 create_fake_sink(aconnector);
f4ac176e 2362 }
2e0ac3d6 2363
e7b07cee 2364 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2365
b830ebc9 2366 if (stream == NULL) {
e7b07cee
HW		 2367 DRM_ERROR("Failed to create stream for sink!\n");
2368 goto stream_create_fail;
2369 }
2370
2371 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2372 /* Search for preferred mode */
2373 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2374 native_mode_found = true;
2375 break;
2376 }
2377 }
2378 if (!native_mode_found)
2379 preferred_mode = list_first_entry_or_null(
2380 &aconnector->base.modes,
2381 struct drm_display_mode,
2382 head);
2383
b830ebc9 2384 if (preferred_mode == NULL) {
e7b07cee
HW		 2385 /* This may not be an error, the use case is when we we have no
2386 * usermode calls to reset and set mode upon hotplug. In this
2387 * case, we call set mode ourselves to restore the previous mode
2388 * and the modelist may not be filled in in time.
2389 */
f1ad2f5e 2390 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2391 } else {
2392 decide_crtc_timing_for_drm_display_mode(
2393 &mode, preferred_mode,
2394 dm_state->scaling != RMX_OFF);
2395 }
2396
2397 fill_stream_properties_from_drm_display_mode(stream,
2398 &mode, &aconnector->base);
2399 update_stream_scaling_settings(&mode, dm_state, stream);
2400
2401 fill_audio_info(
2402 &stream->audio_info,
2403 drm_connector,
2404 aconnector->dc_sink);
2405
2406stream_create_fail:
2407dm_state_null:
2408drm_connector_null:
2409 return stream;
2410}
2411
7578ecda 2412static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2413{
2414 drm_crtc_cleanup(crtc);
2415 kfree(crtc);
2416}
2417
2418static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2419 struct drm_crtc_state *state)
e7b07cee
HW		 2420{
2421 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2422
2423 /* TODO Destroy dc_stream objects are stream object is flattened */
2424 if (cur->stream)
2425 dc_stream_release(cur->stream);
2426
2427
2428 __drm_atomic_helper_crtc_destroy_state(state);
2429
2430
2431 kfree(state);
2432}
2433
2434static void dm_crtc_reset_state(struct drm_crtc *crtc)
2435{
2436 struct dm_crtc_state *state;
2437
2438 if (crtc->state)
2439 dm_crtc_destroy_state(crtc, crtc->state);
2440
2441 state = kzalloc(sizeof(*state), GFP_KERNEL);
2442 if (WARN_ON(!state))
2443 return;
2444
2445 crtc->state = &state->base;
2446 crtc->state->crtc = crtc;
2447
2448}
2449
2450static struct drm_crtc_state *
2451dm_crtc_duplicate_state(struct drm_crtc *crtc)
2452{
2453 struct dm_crtc_state *state, *cur;
2454
2455 cur = to_dm_crtc_state(crtc->state);
2456
2457 if (WARN_ON(!crtc->state))
2458 return NULL;
2459
2004f45e 2460 state = kzalloc(sizeof(*state), GFP_KERNEL);
e7b07cee
HW		 2461
2462 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2463
2464 if (cur->stream) {
2465 state->stream = cur->stream;
2466 dc_stream_retain(state->stream);
2467 }
2468
2469 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2470
2471 return &state->base;
2472}
2473
2474/* Implemented only the options currently availible for the driver */
2475static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2476 .reset = dm_crtc_reset_state,
2477 .destroy = amdgpu_dm_crtc_destroy,
2478 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2479 .set_config = drm_atomic_helper_set_config,
2480 .page_flip = drm_atomic_helper_page_flip,
2481 .atomic_duplicate_state = dm_crtc_duplicate_state,
2482 .atomic_destroy_state = dm_crtc_destroy_state,
2483};
2484
2485static enum drm_connector_status
2486amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2487{
2488 bool connected;
c84dec2f 2489 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2490
2491 /* Notes:
2492 * 1. This interface is NOT called in context of HPD irq.
2493 * 2. This interface *is called* in context of user-mode ioctl. Which
2494 * makes it a bad place for *any* MST-related activit. */
2495
8580d60b
HW		 2496 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2497 !aconnector->fake_enable)
e7b07cee
HW		 2498 connected = (aconnector->dc_sink != NULL);
2499 else
2500 connected = (aconnector->base.force == DRM_FORCE_ON);
2501
2502 return (connected ? connector_status_connected :
2503 connector_status_disconnected);
2504}
2505
3ee6b26b
AD		 2506int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2507 struct drm_connector_state *connector_state,
2508 struct drm_property *property,
2509 uint64_t val)
e7b07cee
HW		 2510{
2511 struct drm_device *dev = connector->dev;
2512 struct amdgpu_device *adev = dev->dev_private;
2513 struct dm_connector_state *dm_old_state =
2514 to_dm_connector_state(connector->state);
2515 struct dm_connector_state *dm_new_state =
2516 to_dm_connector_state(connector_state);
2517
2518 int ret = -EINVAL;
2519
2520 if (property == dev->mode_config.scaling_mode_property) {
2521 enum amdgpu_rmx_type rmx_type;
2522
2523 switch (val) {
2524 case DRM_MODE_SCALE_CENTER:
2525 rmx_type = RMX_CENTER;
2526 break;
2527 case DRM_MODE_SCALE_ASPECT:
2528 rmx_type = RMX_ASPECT;
2529 break;
2530 case DRM_MODE_SCALE_FULLSCREEN:
2531 rmx_type = RMX_FULL;
2532 break;
2533 case DRM_MODE_SCALE_NONE:
2534 default:
2535 rmx_type = RMX_OFF;
2536 break;
2537 }
2538
2539 if (dm_old_state->scaling == rmx_type)
2540 return 0;
2541
2542 dm_new_state->scaling = rmx_type;
2543 ret = 0;
2544 } else if (property == adev->mode_info.underscan_hborder_property) {
2545 dm_new_state->underscan_hborder = val;
2546 ret = 0;
2547 } else if (property == adev->mode_info.underscan_vborder_property) {
2548 dm_new_state->underscan_vborder = val;
2549 ret = 0;
2550 } else if (property == adev->mode_info.underscan_property) {
2551 dm_new_state->underscan_enable = val;
2552 ret = 0;
2553 }
2554
2555 return ret;
2556}
2557
3ee6b26b
AD		 2558int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2559 const struct drm_connector_state *state,
2560 struct drm_property *property,
2561 uint64_t *val)
e7b07cee
HW		 2562{
2563 struct drm_device *dev = connector->dev;
2564 struct amdgpu_device *adev = dev->dev_private;
2565 struct dm_connector_state *dm_state =
2566 to_dm_connector_state(state);
2567 int ret = -EINVAL;
2568
2569 if (property == dev->mode_config.scaling_mode_property) {
2570 switch (dm_state->scaling) {
2571 case RMX_CENTER:
2572 *val = DRM_MODE_SCALE_CENTER;
2573 break;
2574 case RMX_ASPECT:
2575 *val = DRM_MODE_SCALE_ASPECT;
2576 break;
2577 case RMX_FULL:
2578 *val = DRM_MODE_SCALE_FULLSCREEN;
2579 break;
2580 case RMX_OFF:
2581 default:
2582 *val = DRM_MODE_SCALE_NONE;
2583 break;
2584 }
2585 ret = 0;
2586 } else if (property == adev->mode_info.underscan_hborder_property) {
2587 *val = dm_state->underscan_hborder;
2588 ret = 0;
2589 } else if (property == adev->mode_info.underscan_vborder_property) {
2590 *val = dm_state->underscan_vborder;
2591 ret = 0;
2592 } else if (property == adev->mode_info.underscan_property) {
2593 *val = dm_state->underscan_enable;
2594 ret = 0;
2595 }
2596 return ret;
2597}
2598
7578ecda 2599static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2600{
c84dec2f 2601 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2602 const struct dc_link *link = aconnector->dc_link;
2603 struct amdgpu_device *adev = connector->dev->dev_private;
2604 struct amdgpu_display_manager *dm = &adev->dm;
2605#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2606 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2607
2608 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2609 amdgpu_dm_register_backlight_device(dm);
2610
2611 if (dm->backlight_dev) {
2612 backlight_device_unregister(dm->backlight_dev);
2613 dm->backlight_dev = NULL;
2614 }
2615
2616 }
2617#endif
2618 drm_connector_unregister(connector);
2619 drm_connector_cleanup(connector);
2620 kfree(connector);
2621}
2622
2623void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2624{
2625 struct dm_connector_state *state =
2626 to_dm_connector_state(connector->state);
2627
2628 kfree(state);
2629
2630 state = kzalloc(sizeof(*state), GFP_KERNEL);
2631
2632 if (state) {
2633 state->scaling = RMX_OFF;
2634 state->underscan_enable = false;
2635 state->underscan_hborder = 0;
2636 state->underscan_vborder = 0;
2637
2638 connector->state = &state->base;
2639 connector->state->connector = connector;
2640 }
2641}
2642
3ee6b26b
AD		 2643struct drm_connector_state *
2644amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2645{
2646 struct dm_connector_state *state =
2647 to_dm_connector_state(connector->state);
2648
2649 struct dm_connector_state *new_state =
2650 kmemdup(state, sizeof(*state), GFP_KERNEL);
2651
2652 if (new_state) {
2653 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2654 &new_state->base);
e7b07cee
HW		 2655 return &new_state->base;
2656 }
2657
2658 return NULL;
2659}
2660
2661static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2662 .reset = amdgpu_dm_connector_funcs_reset,
2663 .detect = amdgpu_dm_connector_detect,
2664 .fill_modes = drm_helper_probe_single_connector_modes,
2665 .destroy = amdgpu_dm_connector_destroy,
2666 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2667 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2668 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2669 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2670};
2671
2672static struct drm_encoder *best_encoder(struct drm_connector *connector)
2673{
2674 int enc_id = connector->encoder_ids[0];
2675 struct drm_mode_object *obj;
2676 struct drm_encoder *encoder;
2677
f1ad2f5e 2678 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2679
2680 /* pick the encoder ids */
2681 if (enc_id) {
bd21a37d 2682 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2683 if (!obj) {
2684 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2685 return NULL;
2686 }
2687 encoder = obj_to_encoder(obj);
2688 return encoder;
2689 }
2690 DRM_ERROR("No encoder id\n");
2691 return NULL;
2692}
2693
2694static int get_modes(struct drm_connector *connector)
2695{
2696 return amdgpu_dm_connector_get_modes(connector);
2697}
2698
c84dec2f 2699static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2700{
2701 struct dc_sink_init_data init_params = {
2702 .link = aconnector->dc_link,
2703 .sink_signal = SIGNAL_TYPE_VIRTUAL
2704 };
2705 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2706
2707 if (!aconnector->base.edid_blob_ptr ||
2708 !aconnector->base.edid_blob_ptr->data) {
2709 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2710 aconnector->base.name);
2711
2712 aconnector->base.force = DRM_FORCE_OFF;
2713 aconnector->base.override_edid = false;
2714 return;
2715 }
2716
2717 aconnector->edid = edid;
2718
2719 aconnector->dc_em_sink = dc_link_add_remote_sink(
2720 aconnector->dc_link,
2721 (uint8_t *)edid,
2722 (edid->extensions + 1) * EDID_LENGTH,
2723 &init_params);
2724
2725 if (aconnector->base.force
2726 == DRM_FORCE_ON)
2727 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2728 aconnector->dc_link->local_sink :
2729 aconnector->dc_em_sink;
2730}
2731
c84dec2f 2732static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2733{
2734 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2735
2736 /* In case of headless boot with force on for DP managed connector
2737 * Those settings have to be != 0 to get initial modeset
2738 */
2739 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2740 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2741 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2742 }
2743
2744
2745 aconnector->base.override_edid = true;
2746 create_eml_sink(aconnector);
2747}
2748
3ee6b26b
AD		 2749int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2750 struct drm_display_mode *mode)
e7b07cee
HW		 2751{
2752 int result = MODE_ERROR;
2753 struct dc_sink *dc_sink;
2754 struct amdgpu_device *adev = connector->dev->dev_private;
2755 /* TODO: Unhardcode stream count */
0971c40e 2756 struct dc_stream_state *stream;
c84dec2f 2757 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2758
2759 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2760 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2761 return result;
2762
2763 /* Only run this the first time mode_valid is called to initilialize
2764 * EDID mgmt
2765 */
2766 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2767 !aconnector->dc_em_sink)
2768 handle_edid_mgmt(aconnector);
2769
c84dec2f 2770 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2771
b830ebc9 2772 if (dc_sink == NULL) {
e7b07cee
HW		 2773 DRM_ERROR("dc_sink is NULL!\n");
2774 goto fail;
2775 }
2776
2777 stream = dc_create_stream_for_sink(dc_sink);
b830ebc9 2778 if (stream == NULL) {
e7b07cee
HW		 2779 DRM_ERROR("Failed to create stream for sink!\n");
2780 goto fail;
2781 }
2782
2783 drm_mode_set_crtcinfo(mode, 0);
2784 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2785
2786 stream->src.width = mode->hdisplay;
2787 stream->src.height = mode->vdisplay;
2788 stream->dst = stream->src;
2789
62c933f9 2790 if (dc_validate_stream(adev->dm.dc, stream) == DC_OK)
e7b07cee
HW		 2791 result = MODE_OK;
2792
2793 dc_stream_release(stream);
2794
2795fail:
2796 /* TODO: error handling*/
2797 return result;
2798}
2799
2800static const struct drm_connector_helper_funcs
2801amdgpu_dm_connector_helper_funcs = {
2802 /*
b830ebc9
HW		 2803 * If hotplug a second bigger display in FB Con mode, bigger resolution
2804 * modes will be filtered by drm_mode_validate_size(), and those modes
2805 * is missing after user start lightdm. So we need to renew modes list.
2806 * in get_modes call back, not just return the modes count
2807 */
e7b07cee
HW		 2808 .get_modes = get_modes,
2809 .mode_valid = amdgpu_dm_connector_mode_valid,
2810 .best_encoder = best_encoder
2811};
2812
2813static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2814{
2815}
2816
3ee6b26b
AD		 2817static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2818 struct drm_crtc_state *state)
e7b07cee
HW		 2819{
2820 struct amdgpu_device *adev = crtc->dev->dev_private;
2821 struct dc *dc = adev->dm.dc;
2822 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2823 int ret = -EINVAL;
2824
9b690ef3
BL		 2825 if (unlikely(!dm_crtc_state->stream &&
2826 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2827 WARN_ON(1);
2828 return ret;
2829 }
2830
2831 /* In some use cases, like reset, no stream is attached */
2832 if (!dm_crtc_state->stream)
2833 return 0;
2834
62c933f9 2835 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 2836 return 0;
2837
2838 return ret;
2839}
2840
3ee6b26b
AD		 2841static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2842 const struct drm_display_mode *mode,
2843 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2844{
2845 return true;
2846}
2847
2848static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2849 .disable = dm_crtc_helper_disable,
2850 .atomic_check = dm_crtc_helper_atomic_check,
2851 .mode_fixup = dm_crtc_helper_mode_fixup
2852};
2853
2854static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2855{
2856
2857}
2858
3ee6b26b
AD		 2859static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2860 struct drm_crtc_state *crtc_state,
2861 struct drm_connector_state *conn_state)
e7b07cee
HW		 2862{
2863 return 0;
2864}
2865
2866const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2867 .disable = dm_encoder_helper_disable,
2868 .atomic_check = dm_encoder_helper_atomic_check
2869};
2870
2871static void dm_drm_plane_reset(struct drm_plane *plane)
2872{
2873 struct dm_plane_state *amdgpu_state = NULL;
2874
2875 if (plane->state)
2876 plane->funcs->atomic_destroy_state(plane, plane->state);
2877
2878 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2879
2880 if (amdgpu_state) {
2881 plane->state = &amdgpu_state->base;
2882 plane->state->plane = plane;
2883 plane->state->rotation = DRM_MODE_ROTATE_0;
2884 } else
2885 WARN_ON(1);
2886}
2887
2888static struct drm_plane_state *
2889dm_drm_plane_duplicate_state(struct drm_plane *plane)
2890{
2891 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2892
2893 old_dm_plane_state = to_dm_plane_state(plane->state);
2894 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2895 if (!dm_plane_state)
2896 return NULL;
2897
2898 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2899
3be5262e
HW		 2900 if (old_dm_plane_state->dc_state) {
2901 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2902 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2903 }
2904
2905 return &dm_plane_state->base;
2906}
2907
2908void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2909 struct drm_plane_state *state)
e7b07cee
HW		 2910{
2911 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2912
3be5262e
HW		 2913 if (dm_plane_state->dc_state)
2914 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2915
0627bbd3 2916 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2917}
2918
2919static const struct drm_plane_funcs dm_plane_funcs = {
2920 .update_plane = drm_atomic_helper_update_plane,
2921 .disable_plane = drm_atomic_helper_disable_plane,
2922 .destroy = drm_plane_cleanup,
2923 .reset = dm_drm_plane_reset,
2924 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2925 .atomic_destroy_state = dm_drm_plane_destroy_state,
2926};
2927
3ee6b26b
AD		 2928static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2929 struct drm_plane_state *new_state)
e7b07cee
HW		 2930{
2931 struct amdgpu_framebuffer *afb;
2932 struct drm_gem_object *obj;
2933 struct amdgpu_bo *rbo;
2934 int r;
2935 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2936 unsigned int awidth;
2937
2938 dm_plane_state_old = to_dm_plane_state(plane->state);
2939 dm_plane_state_new = to_dm_plane_state(new_state);
2940
2941 if (!new_state->fb) {
f1ad2f5e 2942 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 2943 return 0;
2944 }
2945
2946 afb = to_amdgpu_framebuffer(new_state->fb);
2947
2948 obj = afb->obj;
2949 rbo = gem_to_amdgpu_bo(obj);
2950 r = amdgpu_bo_reserve(rbo, false);
2951 if (unlikely(r != 0))
2952 return r;
2953
2954 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
2955
2956
2957 amdgpu_bo_unreserve(rbo);
2958
2959 if (unlikely(r != 0)) {
2960 DRM_ERROR("Failed to pin framebuffer\n");
2961 return r;
2962 }
2963
2964 amdgpu_bo_ref(rbo);
2965
3be5262e
HW		 2966 if (dm_plane_state_new->dc_state &&
2967 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2968 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 2969
3be5262e
HW		 2970 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2971 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
2972 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 2973 } else {
2974 awidth = ALIGN(new_state->fb->width, 64);
3be5262e 2975 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 2976 = lower_32_bits(afb->address);
3be5262e 2977 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 2978 = lower_32_bits(afb->address) +
2979 (awidth * new_state->fb->height);
2980 }
2981 }
2982
2983 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
2984 * prepare and cleanup in drm_atomic_helper_prepare_planes
2985 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
2986 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
2987 * code touching fram buffers should be avoided for DC.
2988 */
2989 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2990 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
2991
2992 acrtc->cursor_bo = obj;
2993 }
2994 return 0;
2995}
2996
3ee6b26b
AD		 2997static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
2998 struct drm_plane_state *old_state)
e7b07cee
HW		 2999{
3000 struct amdgpu_bo *rbo;
3001 struct amdgpu_framebuffer *afb;
3002 int r;
3003
3004 if (!old_state->fb)
3005 return;
3006
3007 afb = to_amdgpu_framebuffer(old_state->fb);
3008 rbo = gem_to_amdgpu_bo(afb->obj);
3009 r = amdgpu_bo_reserve(rbo, false);
3010 if (unlikely(r)) {
3011 DRM_ERROR("failed to reserve rbo before unpin\n");
3012 return;
b830ebc9
HW		 3013 }
3014
3015 amdgpu_bo_unpin(rbo);
3016 amdgpu_bo_unreserve(rbo);
3017 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3018}
3019
7578ecda
AD		 3020static int dm_plane_atomic_check(struct drm_plane *plane,
3021 struct drm_plane_state *state)
cbd19488
AG		 3022{
3023 struct amdgpu_device *adev = plane->dev->dev_private;
3024 struct dc *dc = adev->dm.dc;
3025 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3026
3be5262e 3027 if (!dm_plane_state->dc_state)
9a3329b1 3028 return 0;
cbd19488 3029
62c933f9 3030 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3031 return 0;
3032
3033 return -EINVAL;
3034}
3035
e7b07cee
HW		 3036static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3037 .prepare_fb = dm_plane_helper_prepare_fb,
3038 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3039 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3040};
3041
3042/*
3043 * TODO: these are currently initialized to rgb formats only.
3044 * For future use cases we should either initialize them dynamically based on
3045 * plane capabilities, or initialize this array to all formats, so internal drm
3046 * check will succeed, and let DC to implement proper check
3047 */
d90371b0 3048static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3049 DRM_FORMAT_RGB888,
3050 DRM_FORMAT_XRGB8888,
3051 DRM_FORMAT_ARGB8888,
3052 DRM_FORMAT_RGBA8888,
3053 DRM_FORMAT_XRGB2101010,
3054 DRM_FORMAT_XBGR2101010,
3055 DRM_FORMAT_ARGB2101010,
3056 DRM_FORMAT_ABGR2101010,
3057};
3058
99d1abf8 3059static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3060 DRM_FORMAT_NV12,
3061 DRM_FORMAT_NV21,
3062};
3063
3064static const u32 cursor_formats[] = {
3065 DRM_FORMAT_ARGB8888
3066};
3067
7578ecda
AD		 3068static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3069 struct amdgpu_plane *aplane,
3070 unsigned long possible_crtcs)
e7b07cee
HW		 3071{
3072 int res = -EPERM;
3073
3074 switch (aplane->base.type) {
3075 case DRM_PLANE_TYPE_PRIMARY:
3076 aplane->base.format_default = true;
3077
3078 res = drm_universal_plane_init(
3079 dm->adev->ddev,
3080 &aplane->base,
3081 possible_crtcs,
3082 &dm_plane_funcs,
3083 rgb_formats,
3084 ARRAY_SIZE(rgb_formats),
3085 NULL, aplane->base.type, NULL);
3086 break;
3087 case DRM_PLANE_TYPE_OVERLAY:
3088 res = drm_universal_plane_init(
3089 dm->adev->ddev,
3090 &aplane->base,
3091 possible_crtcs,
3092 &dm_plane_funcs,
3093 yuv_formats,
3094 ARRAY_SIZE(yuv_formats),
3095 NULL, aplane->base.type, NULL);
3096 break;
3097 case DRM_PLANE_TYPE_CURSOR:
3098 res = drm_universal_plane_init(
3099 dm->adev->ddev,
3100 &aplane->base,
3101 possible_crtcs,
3102 &dm_plane_funcs,
3103 cursor_formats,
3104 ARRAY_SIZE(cursor_formats),
3105 NULL, aplane->base.type, NULL);
3106 break;
3107 }
3108
3109 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3110
3111 return res;
3112}
3113
7578ecda
AD		 3114static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3115 struct drm_plane *plane,
3116 uint32_t crtc_index)
e7b07cee
HW		 3117{
3118 struct amdgpu_crtc *acrtc = NULL;
3119 struct amdgpu_plane *cursor_plane;
3120
3121 int res = -ENOMEM;
3122
3123 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3124 if (!cursor_plane)
3125 goto fail;
3126
3127 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3128 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3129
3130 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3131 if (!acrtc)
3132 goto fail;
3133
3134 res = drm_crtc_init_with_planes(
3135 dm->ddev,
3136 &acrtc->base,
3137 plane,
3138 &cursor_plane->base,
3139 &amdgpu_dm_crtc_funcs, NULL);
3140
3141 if (res)
3142 goto fail;
3143
3144 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3145
3146 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3147 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3148
3149 acrtc->crtc_id = crtc_index;
3150 acrtc->base.enabled = false;
3151
3152 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3153 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3154
3155 return 0;
3156
3157fail:
b830ebc9
HW		 3158 kfree(acrtc);
3159 kfree(cursor_plane);
e7b07cee
HW		 3160 return res;
3161}
3162
3163
3164static int to_drm_connector_type(enum signal_type st)
3165{
3166 switch (st) {
3167 case SIGNAL_TYPE_HDMI_TYPE_A:
3168 return DRM_MODE_CONNECTOR_HDMIA;
3169 case SIGNAL_TYPE_EDP:
3170 return DRM_MODE_CONNECTOR_eDP;
3171 case SIGNAL_TYPE_RGB:
3172 return DRM_MODE_CONNECTOR_VGA;
3173 case SIGNAL_TYPE_DISPLAY_PORT:
3174 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3175 return DRM_MODE_CONNECTOR_DisplayPort;
3176 case SIGNAL_TYPE_DVI_DUAL_LINK:
3177 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3178 return DRM_MODE_CONNECTOR_DVID;
3179 case SIGNAL_TYPE_VIRTUAL:
3180 return DRM_MODE_CONNECTOR_VIRTUAL;
3181
3182 default:
3183 return DRM_MODE_CONNECTOR_Unknown;
3184 }
3185}
3186
3187static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3188{
3189 const struct drm_connector_helper_funcs *helper =
3190 connector->helper_private;
3191 struct drm_encoder *encoder;
3192 struct amdgpu_encoder *amdgpu_encoder;
3193
3194 encoder = helper->best_encoder(connector);
3195
3196 if (encoder == NULL)
3197 return;
3198
3199 amdgpu_encoder = to_amdgpu_encoder(encoder);
3200
3201 amdgpu_encoder->native_mode.clock = 0;
3202
3203 if (!list_empty(&connector->probed_modes)) {
3204 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3205
e7b07cee 3206 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3207 &connector->probed_modes,
3208 head) {
3209 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3210 amdgpu_encoder->native_mode = *preferred_mode;
3211
e7b07cee
HW		 3212 break;
3213 }
3214
3215 }
3216}
3217
3ee6b26b
AD		 3218static struct drm_display_mode *
3219amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3220 char *name,
3221 int hdisplay, int vdisplay)
e7b07cee
HW		 3222{
3223 struct drm_device *dev = encoder->dev;
3224 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3225 struct drm_display_mode *mode = NULL;
3226 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3227
3228 mode = drm_mode_duplicate(dev, native_mode);
3229
b830ebc9 3230 if (mode == NULL)
e7b07cee
HW		 3231 return NULL;
3232
3233 mode->hdisplay = hdisplay;
3234 mode->vdisplay = vdisplay;
3235 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3236 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3237
3238 return mode;
3239
3240}
3241
3242static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3243 struct drm_connector *connector)
e7b07cee
HW		 3244{
3245 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3246 struct drm_display_mode *mode = NULL;
3247 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3248 struct amdgpu_dm_connector *amdgpu_dm_connector =
3249 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3250 int i;
3251 int n;
3252 struct mode_size {
3253 char name[DRM_DISPLAY_MODE_LEN];
3254 int w;
3255 int h;
b830ebc9 3256 } common_modes[] = {
e7b07cee
HW		 3257 { "640x480", 640, 480},
3258 { "800x600", 800, 600},
3259 { "1024x768", 1024, 768},
3260 { "1280x720", 1280, 720},
3261 { "1280x800", 1280, 800},
3262 {"1280x1024", 1280, 1024},
3263 { "1440x900", 1440, 900},
3264 {"1680x1050", 1680, 1050},
3265 {"1600x1200", 1600, 1200},
3266 {"1920x1080", 1920, 1080},
3267 {"1920x1200", 1920, 1200}
3268 };
3269
b830ebc9 3270 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3271
3272 for (i = 0; i < n; i++) {
3273 struct drm_display_mode *curmode = NULL;
3274 bool mode_existed = false;
3275
3276 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3277 common_modes[i].h > native_mode->vdisplay ||
3278 (common_modes[i].w == native_mode->hdisplay &&
3279 common_modes[i].h == native_mode->vdisplay))
3280 continue;
e7b07cee
HW		 3281
3282 list_for_each_entry(curmode, &connector->probed_modes, head) {
3283 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3284 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3285 mode_existed = true;
3286 break;
3287 }
3288 }
3289
3290 if (mode_existed)
3291 continue;
3292
3293 mode = amdgpu_dm_create_common_mode(encoder,
3294 common_modes[i].name, common_modes[i].w,
3295 common_modes[i].h);
3296 drm_mode_probed_add(connector, mode);
c84dec2f 3297 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3298 }
3299}
3300
3ee6b26b
AD		 3301static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3302 struct edid *edid)
e7b07cee 3303{
c84dec2f
HW		 3304 struct amdgpu_dm_connector *amdgpu_dm_connector =
3305 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3306
3307 if (edid) {
3308 /* empty probed_modes */
3309 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3310 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3311 drm_add_edid_modes(connector, edid);
3312
3313 drm_edid_to_eld(connector, edid);
3314
3315 amdgpu_dm_get_native_mode(connector);
3316 } else
c84dec2f 3317 amdgpu_dm_connector->num_modes = 0;
e7b07cee
HW		 3318}
3319
7578ecda 3320static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3321{
3322 const struct drm_connector_helper_funcs *helper =
3323 connector->helper_private;
c84dec2f
HW		 3324 struct amdgpu_dm_connector *amdgpu_dm_connector =
3325 to_amdgpu_dm_connector(connector);
e7b07cee 3326 struct drm_encoder *encoder;
c84dec2f 3327 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3328
3329 encoder = helper->best_encoder(connector);
3330
3331 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3332 amdgpu_dm_connector_add_common_modes(encoder, connector);
c84dec2f 3333 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3334}
3335
3ee6b26b
AD		 3336void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3337 struct amdgpu_dm_connector *aconnector,
3338 int connector_type,
3339 struct dc_link *link,
3340 int link_index)
e7b07cee
HW		 3341{
3342 struct amdgpu_device *adev = dm->ddev->dev_private;
3343
3344 aconnector->connector_id = link_index;
3345 aconnector->dc_link = link;
3346 aconnector->base.interlace_allowed = false;
3347 aconnector->base.doublescan_allowed = false;
3348 aconnector->base.stereo_allowed = false;
3349 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3350 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3351
3352 mutex_init(&aconnector->hpd_lock);
3353
b830ebc9
HW		 3354 /* configure support HPD hot plug connector_>polled default value is 0
3355 * which means HPD hot plug not supported
3356 */
e7b07cee
HW		 3357 switch (connector_type) {
3358 case DRM_MODE_CONNECTOR_HDMIA:
3359 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3360 break;
3361 case DRM_MODE_CONNECTOR_DisplayPort:
3362 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3363 break;
3364 case DRM_MODE_CONNECTOR_DVID:
3365 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3366 break;
3367 default:
3368 break;
3369 }
3370
3371 drm_object_attach_property(&aconnector->base.base,
3372 dm->ddev->mode_config.scaling_mode_property,
3373 DRM_MODE_SCALE_NONE);
3374
3375 drm_object_attach_property(&aconnector->base.base,
3376 adev->mode_info.underscan_property,
3377 UNDERSCAN_OFF);
3378 drm_object_attach_property(&aconnector->base.base,
3379 adev->mode_info.underscan_hborder_property,
3380 0);
3381 drm_object_attach_property(&aconnector->base.base,
3382 adev->mode_info.underscan_vborder_property,
3383 0);
3384
3385}
3386
7578ecda
AD		 3387static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3388 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3389{
3390 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3391 struct ddc_service *ddc_service = i2c->ddc_service;
3392 struct i2c_command cmd;
3393 int i;
3394 int result = -EIO;
3395
b830ebc9 3396 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3397
3398 if (!cmd.payloads)
3399 return result;
3400
3401 cmd.number_of_payloads = num;
3402 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3403 cmd.speed = 100;
3404
3405 for (i = 0; i < num; i++) {
3406 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3407 cmd.payloads[i].address = msgs[i].addr;
3408 cmd.payloads[i].length = msgs[i].len;
3409 cmd.payloads[i].data = msgs[i].buf;
3410 }
3411
3412 if (dal_i2caux_submit_i2c_command(
3413 ddc_service->ctx->i2caux,
3414 ddc_service->ddc_pin,
3415 &cmd))
3416 result = num;
3417
3418 kfree(cmd.payloads);
3419 return result;
3420}
3421
7578ecda 3422static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3423{
3424 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3425}
3426
3427static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3428 .master_xfer = amdgpu_dm_i2c_xfer,
3429 .functionality = amdgpu_dm_i2c_func,
3430};
3431
3ee6b26b
AD		 3432static struct amdgpu_i2c_adapter *
3433create_i2c(struct ddc_service *ddc_service,
3434 int link_index,
3435 int *res)
e7b07cee
HW		 3436{
3437 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3438 struct amdgpu_i2c_adapter *i2c;
3439
b830ebc9 3440 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
e7b07cee
HW		 3441 i2c->base.owner = THIS_MODULE;
3442 i2c->base.class = I2C_CLASS_DDC;
3443 i2c->base.dev.parent = &adev->pdev->dev;
3444 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3445 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3446 i2c_set_adapdata(&i2c->base, i2c);
3447 i2c->ddc_service = ddc_service;
3448
3449 return i2c;
3450}
3451
3452/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3453 * dc_link which will be represented by this aconnector.
3454 */
7578ecda
AD		 3455static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3456 struct amdgpu_dm_connector *aconnector,
3457 uint32_t link_index,
3458 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3459{
3460 int res = 0;
3461 int connector_type;
3462 struct dc *dc = dm->dc;
3463 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3464 struct amdgpu_i2c_adapter *i2c;
3465 ((struct dc_link *)link)->priv = aconnector;
3466
f1ad2f5e 3467 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3468
3469 i2c = create_i2c(link->ddc, link->link_index, &res);
3470 aconnector->i2c = i2c;
3471 res = i2c_add_adapter(&i2c->base);
3472
3473 if (res) {
3474 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3475 goto out_free;
3476 }
3477
3478 connector_type = to_drm_connector_type(link->connector_signal);
3479
3480 res = drm_connector_init(
3481 dm->ddev,
3482 &aconnector->base,
3483 &amdgpu_dm_connector_funcs,
3484 connector_type);
3485
3486 if (res) {
3487 DRM_ERROR("connector_init failed\n");
3488 aconnector->connector_id = -1;
3489 goto out_free;
3490 }
3491
3492 drm_connector_helper_add(
3493 &aconnector->base,
3494 &amdgpu_dm_connector_helper_funcs);
3495
3496 amdgpu_dm_connector_init_helper(
3497 dm,
3498 aconnector,
3499 connector_type,
3500 link,
3501 link_index);
3502
3503 drm_mode_connector_attach_encoder(
3504 &aconnector->base, &aencoder->base);
3505
3506 drm_connector_register(&aconnector->base);
3507
3508 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3509 || connector_type == DRM_MODE_CONNECTOR_eDP)
3510 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3511
3512#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3513 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3514
3515 /* NOTE: this currently will create backlight device even if a panel
3516 * is not connected to the eDP/LVDS connector.
3517 *
3518 * This is less than ideal but we don't have sink information at this
3519 * stage since detection happens after. We can't do detection earlier
3520 * since MST detection needs connectors to be created first.
3521 */
3522 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3523 /* Event if registration failed, we should continue with
3524 * DM initialization because not having a backlight control
b830ebc9
HW		 3525 * is better then a black screen.
3526 */
e7b07cee
HW		 3527 amdgpu_dm_register_backlight_device(dm);
3528
3529 if (dm->backlight_dev)
3530 dm->backlight_link = link;
3531 }
3532#endif
3533
3534out_free:
3535 if (res) {
3536 kfree(i2c);
3537 aconnector->i2c = NULL;
3538 }
3539 return res;
3540}
3541
3542int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3543{
3544 switch (adev->mode_info.num_crtc) {
3545 case 1:
3546 return 0x1;
3547 case 2:
3548 return 0x3;
3549 case 3:
3550 return 0x7;
3551 case 4:
3552 return 0xf;
3553 case 5:
3554 return 0x1f;
3555 case 6:
3556 default:
3557 return 0x3f;
3558 }
3559}
3560
7578ecda
AD		 3561static int amdgpu_dm_encoder_init(struct drm_device *dev,
3562 struct amdgpu_encoder *aencoder,
3563 uint32_t link_index)
e7b07cee
HW		 3564{
3565 struct amdgpu_device *adev = dev->dev_private;
3566
3567 int res = drm_encoder_init(dev,
3568 &aencoder->base,
3569 &amdgpu_dm_encoder_funcs,
3570 DRM_MODE_ENCODER_TMDS,
3571 NULL);
3572
3573 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3574
3575 if (!res)
3576 aencoder->encoder_id = link_index;
3577 else
3578 aencoder->encoder_id = -1;
3579
3580 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3581
3582 return res;
3583}
3584
3ee6b26b
AD		 3585static void manage_dm_interrupts(struct amdgpu_device *adev,
3586 struct amdgpu_crtc *acrtc,
3587 bool enable)
e7b07cee
HW		 3588{
3589 /*
3590 * this is not correct translation but will work as soon as VBLANK
3591 * constant is the same as PFLIP
3592 */
3593 int irq_type =
3594 amdgpu_crtc_idx_to_irq_type(
3595 adev,
3596 acrtc->crtc_id);
3597
3598 if (enable) {
3599 drm_crtc_vblank_on(&acrtc->base);
3600 amdgpu_irq_get(
3601 adev,
3602 &adev->pageflip_irq,
3603 irq_type);
3604 } else {
3605
3606 amdgpu_irq_put(
3607 adev,
3608 &adev->pageflip_irq,
3609 irq_type);
3610 drm_crtc_vblank_off(&acrtc->base);
3611 }
3612}
3613
3ee6b26b
AD		 3614static bool
3615is_scaling_state_different(const struct dm_connector_state *dm_state,
3616 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3617{
3618 if (dm_state->scaling != old_dm_state->scaling)
3619 return true;
3620 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3621 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3622 return true;
3623 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3624 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3625 return true;
b830ebc9
HW		 3626 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3627 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3628 return true;
e7b07cee
HW		 3629 return false;
3630}
3631
3ee6b26b
AD		 3632static void remove_stream(struct amdgpu_device *adev,
3633 struct amdgpu_crtc *acrtc,
3634 struct dc_stream_state *stream)
e7b07cee
HW		 3635{
3636 /* this is the update mode case */
3637 if (adev->dm.freesync_module)
3638 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3639
3640 acrtc->otg_inst = -1;
3641 acrtc->enabled = false;
3642}
3643
7578ecda
AD		 3644static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3645 struct dc_cursor_position *position)
2a8f6ccb
HW		 3646{
3647 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3648 int x, y;
3649 int xorigin = 0, yorigin = 0;
3650
3651 if (!crtc || !plane->state->fb) {
3652 position->enable = false;
3653 position->x = 0;
3654 position->y = 0;
3655 return 0;
3656 }
3657
3658 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3659 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3660 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3661 __func__,
3662 plane->state->crtc_w,
3663 plane->state->crtc_h);
3664 return -EINVAL;
3665 }
3666
3667 x = plane->state->crtc_x;
3668 y = plane->state->crtc_y;
3669 /* avivo cursor are offset into the total surface */
3670 x += crtc->primary->state->src_x >> 16;
3671 y += crtc->primary->state->src_y >> 16;
3672 if (x < 0) {
3673 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3674 x = 0;
3675 }
3676 if (y < 0) {
3677 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3678 y = 0;
3679 }
3680 position->enable = true;
3681 position->x = x;
3682 position->y = y;
3683 position->x_hotspot = xorigin;
3684 position->y_hotspot = yorigin;
3685
3686 return 0;
3687}
3688
3ee6b26b
AD		 3689static void handle_cursor_update(struct drm_plane *plane,
3690 struct drm_plane_state *old_plane_state)
e7b07cee 3691{
2a8f6ccb
HW		 3692 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3693 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3694 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3695 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3696 uint64_t address = afb ? afb->address : 0;
3697 struct dc_cursor_position position;
3698 struct dc_cursor_attributes attributes;
3699 int ret;
3700
e7b07cee
HW		 3701 if (!plane->state->fb && !old_plane_state->fb)
3702 return;
3703
f1ad2f5e 3704 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3705 __func__,
3706 amdgpu_crtc->crtc_id,
3707 plane->state->crtc_w,
3708 plane->state->crtc_h);
2a8f6ccb
HW		 3709
3710 ret = get_cursor_position(plane, crtc, &position);
3711 if (ret)
3712 return;
3713
3714 if (!position.enable) {
3715 /* turn off cursor */
3716 if (crtc_state && crtc_state->stream)
3717 dc_stream_set_cursor_position(crtc_state->stream,
3718 &position);
3719 return;
e7b07cee 3720 }
e7b07cee 3721
2a8f6ccb
HW		 3722 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3723 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3724
3725 attributes.address.high_part = upper_32_bits(address);
3726 attributes.address.low_part = lower_32_bits(address);
3727 attributes.width = plane->state->crtc_w;
3728 attributes.height = plane->state->crtc_h;
3729 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3730 attributes.rotation_angle = 0;
3731 attributes.attribute_flags.value = 0;
3732
3733 attributes.pitch = attributes.width;
3734
886daac9
JZ		 3735 if (crtc_state->stream) {
3736 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3737 &attributes))
3738 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3739
2a8f6ccb
HW		 3740 if (!dc_stream_set_cursor_position(crtc_state->stream,
3741 &position))
3742 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3743 }
2a8f6ccb 3744}
e7b07cee
HW		 3745
3746static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3747{
3748
3749 assert_spin_locked(&acrtc->base.dev->event_lock);
3750 WARN_ON(acrtc->event);
3751
3752 acrtc->event = acrtc->base.state->event;
3753
3754 /* Set the flip status */
3755 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3756
3757 /* Mark this event as consumed */
3758 acrtc->base.state->event = NULL;
3759
3760 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3761 acrtc->crtc_id);
3762}
3763
3764/*
3765 * Executes flip
3766 *
3767 * Waits on all BO's fences and for proper vblank count
3768 */
3ee6b26b
AD		 3769static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3770 struct drm_framebuffer *fb,
bc6828e0
BL		 3771 uint32_t target,
3772 struct dc_state *state)
e7b07cee
HW		 3773{
3774 unsigned long flags;
3775 uint32_t target_vblank;
3776 int r, vpos, hpos;
3777 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3778 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3779 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3780 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3781 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3782 struct dc_flip_addrs addr = { {0} };
3be5262e 3783 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3784 struct dc_surface_update surface_updates[1] = { {0} };
3785 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3786
3787
3788 /* Prepare wait for target vblank early - before the fence-waits */
3789 target_vblank = target - drm_crtc_vblank_count(crtc) +
3790 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3791
b830ebc9 3792 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3793 * explicitly on fences instead
3794 * and in general should be called for
3795 * blocking commit to as per framework helpers
b830ebc9 3796 */
e7b07cee
HW		 3797 r = amdgpu_bo_reserve(abo, true);
3798 if (unlikely(r != 0)) {
3799 DRM_ERROR("failed to reserve buffer before flip\n");
3800 WARN_ON(1);
3801 }
3802
3803 /* Wait for all fences on this FB */
3804 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3805 MAX_SCHEDULE_TIMEOUT) < 0);
3806
3807 amdgpu_bo_unreserve(abo);
3808
3809 /* Wait until we're out of the vertical blank period before the one
3810 * targeted by the flip
3811 */
3812 while ((acrtc->enabled &&
3813 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3814 &vpos, &hpos, NULL, NULL,
3815 &crtc->hwmode)
3816 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3817 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3818 (int)(target_vblank -
3819 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3820 usleep_range(1000, 1100);
3821 }
3822
3823 /* Flip */
3824 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3825 /* update crtc fb */
3826 crtc->primary->fb = fb;
3827
3828 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3829 WARN_ON(!acrtc_state->stream);
3830
3831 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3832 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3833 addr.flip_immediate = async_flip;
3834
3835
3836 if (acrtc->base.state->event)
3837 prepare_flip_isr(acrtc);
3838
3be5262e 3839 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3840 surface_updates->flip_addr = &addr;
3841
3842
bc6828e0
BL		 3843 dc_commit_updates_for_stream(adev->dm.dc,
3844 surface_updates,
3845 1,
3846 acrtc_state->stream,
3847 NULL,
3848 &surface_updates->surface,
3849 state);
e7b07cee
HW		 3850
3851 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3852 __func__,
3853 addr.address.grph.addr.high_part,
3854 addr.address.grph.addr.low_part);
3855
3856
3857 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3858}
3859
3be5262e 3860static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 3861 struct drm_device *dev,
3862 struct amdgpu_display_manager *dm,
3863 struct drm_crtc *pcrtc,
3864 bool *wait_for_vblank)
e7b07cee
HW		 3865{
3866 uint32_t i;
3867 struct drm_plane *plane;
0bc9706d 3868 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 3869 struct dc_stream_state *dc_stream_attach;
3be5262e 3870 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 3871 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 3872 struct drm_crtc_state *new_pcrtc_state =
3873 drm_atomic_get_new_crtc_state(state, pcrtc);
3874 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
bc6828e0 3875 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 3876 int planes_count = 0;
3877 unsigned long flags;
3878
3879 /* update planes when needed */
0bc9706d
LSL		 3880 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3881 struct drm_crtc *crtc = new_plane_state->crtc;
3882 struct drm_crtc_state *new_crtc_state =
3883 drm_atomic_get_new_crtc_state(state, crtc);
3884 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 3885 bool pflip_needed;
54d76575 3886 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 3887
3888 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3889 handle_cursor_update(plane, old_plane_state);
3890 continue;
3891 }
3892
0bc9706d 3893 if (!fb || !crtc || pcrtc != crtc || !new_crtc_state->active)
e7b07cee
HW		 3894 continue;
3895
3896 pflip_needed = !state->allow_modeset;
3897
3898 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3899 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3900 DRM_ERROR("%s: acrtc %d, already busy\n",
3901 __func__,
3902 acrtc_attach->crtc_id);
e7b07cee 3903 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
b830ebc9 3904 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3905 WARN_ON(1);
3906 }
3907 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3908
3909 if (!pflip_needed) {
54d76575 3910 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 3911
54d76575 3912 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 3913
3914 dc_stream_attach = acrtc_state->stream;
3915 planes_count++;
3916
0bc9706d 3917 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 3918 /* Assume even ONE crtc with immediate flip means
3919 * entire can't wait for VBLANK
3920 * TODO Check if it's correct
3921 */
3922 *wait_for_vblank =
0bc9706d 3923 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 3924 false : true;
3925
3926 /* TODO: Needs rework for multiplane flip */
3927 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3928 drm_crtc_vblank_get(crtc);
3929
3930 amdgpu_dm_do_flip(
3931 crtc,
3932 fb,
bc6828e0
BL		 3933 drm_crtc_vblank_count(crtc) + *wait_for_vblank,
3934 dm_state->context);
e7b07cee
HW		 3935 }
3936
3937 }
3938
3939 if (planes_count) {
3940 unsigned long flags;
3941
0bc9706d 3942 if (new_pcrtc_state->event) {
e7b07cee
HW		 3943
3944 drm_crtc_vblank_get(pcrtc);
3945
3946 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
3947 prepare_flip_isr(acrtc_attach);
3948 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
3949 }
3950
3be5262e
HW		 3951 if (false == dc_commit_planes_to_stream(dm->dc,
3952 plane_states_constructed,
3953 planes_count,
bc6828e0
BL		 3954 dc_stream_attach,
3955 dm_state->context))
3be5262e 3956 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 3957 } else {
3958 /*TODO BUG Here should go disable planes on CRTC. */
3959 }
3960}
3961
3962
7578ecda
AD		 3963static int amdgpu_dm_atomic_commit(struct drm_device *dev,
3964 struct drm_atomic_state *state,
3965 bool nonblock)
e7b07cee
HW		 3966{
3967 struct drm_crtc *crtc;
c2cea706 3968 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 3969 struct amdgpu_device *adev = dev->dev_private;
3970 int i;
3971
3972 /*
3973 * We evade vblanks and pflips on crtc that
3974 * should be changed. We do it here to flush & disable
3975 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
3976 * it will update crtc->dm_crtc_state->stream pointer which is used in
3977 * the ISRs.
3978 */
c2cea706 3979 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 3980 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 3981 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3982
54d76575 3983 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 3984 manage_dm_interrupts(adev, acrtc, false);
3985 }
3986
3987 return drm_atomic_helper_commit(dev, state, nonblock);
3988
3989 /*TODO Handle EINTR, reenable IRQ*/
3990}
3991
7578ecda 3992static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 3993{
3994 struct drm_device *dev = state->dev;
3995 struct amdgpu_device *adev = dev->dev_private;
3996 struct amdgpu_display_manager *dm = &adev->dm;
3997 struct dm_atomic_state *dm_state;
3998 uint32_t i, j;
3999 uint32_t new_crtcs_count = 0;
5cc6dcbd 4000 struct drm_crtc *crtc;
0bc9706d 4001 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee 4002 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
0971c40e 4003 struct dc_stream_state *new_stream = NULL;
e7b07cee
HW		 4004 unsigned long flags;
4005 bool wait_for_vblank = true;
4006 struct drm_connector *connector;
c2cea706 4007 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4008 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
e7b07cee
HW		 4009
4010 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4011
4012 dm_state = to_dm_atomic_state(state);
4013
4014 /* update changed items */
0bc9706d 4015 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4016 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4017
54d76575
LSL		 4018 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4019 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4020
f1ad2f5e 4021 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4022 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4023 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4024 "connectors_changed:%d\n",
4025 acrtc->crtc_id,
0bc9706d
LSL		 4026 new_crtc_state->enable,
4027 new_crtc_state->active,
4028 new_crtc_state->planes_changed,
4029 new_crtc_state->mode_changed,
4030 new_crtc_state->active_changed,
4031 new_crtc_state->connectors_changed);
e7b07cee
HW		 4032
4033 /* handles headless hotplug case, updating new_state and
4034 * aconnector as needed
4035 */
4036
54d76575 4037 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4038
f1ad2f5e 4039 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4040
54d76575 4041 if (!dm_new_crtc_state->stream) {
e7b07cee 4042 /*
b830ebc9
HW		 4043 * this could happen because of issues with
4044 * userspace notifications delivery.
4045 * In this case userspace tries to set mode on
4046 * display which is disconnect in fact.
4047 * dc_sink in NULL in this case on aconnector.
4048 * We expect reset mode will come soon.
4049 *
4050 * This can also happen when unplug is done
4051 * during resume sequence ended
4052 *
4053 * In this case, we want to pretend we still
4054 * have a sink to keep the pipe running so that
4055 * hw state is consistent with the sw state
4056 */
f1ad2f5e 4057 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4058 __func__, acrtc->base.base.id);
4059 continue;
4060 }
4061
4062
54d76575
LSL		 4063 if (dm_old_crtc_state->stream)
4064 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4065
4066
4067 /*
4068 * this loop saves set mode crtcs
4069 * we needed to enable vblanks once all
4070 * resources acquired in dc after dc_commit_streams
4071 */
4072
4073 /*TODO move all this into dm_crtc_state, get rid of
4074 * new_crtcs array and use old and new atomic states
4075 * instead
4076 */
4077 new_crtcs[new_crtcs_count] = acrtc;
4078 new_crtcs_count++;
4079
0bc9706d 4080 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
e7b07cee 4081 acrtc->enabled = true;
0bc9706d
LSL		 4082 acrtc->hw_mode = new_crtc_state->mode;
4083 crtc->hwmode = new_crtc_state->mode;
4084 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4085 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4086
4087 /* i.e. reset mode */
54d76575
LSL		 4088 if (dm_old_crtc_state->stream)
4089 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4090 }
4091 } /* for_each_crtc_in_state() */
4092
4093 /*
4094 * Add streams after required streams from new and replaced streams
4095 * are removed from freesync module
4096 */
4097 if (adev->dm.freesync_module) {
4098 for (i = 0; i < new_crtcs_count; i++) {
c84dec2f 4099 struct amdgpu_dm_connector *aconnector = NULL;
b830ebc9 4100
0bc9706d
LSL		 4101 new_crtc_state = drm_atomic_get_new_crtc_state(state,
4102 &new_crtcs[i]->base);
54d76575 4103 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4104
54d76575 4105 new_stream = dm_new_crtc_state->stream;
1daf8c63 4106 aconnector = amdgpu_dm_find_first_crtc_matching_connector(
e7b07cee 4107 state,
9ba29fcb 4108 &new_crtcs[i]->base);
e7b07cee 4109 if (!aconnector) {
f1ad2f5e 4110 DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d "
b830ebc9
HW		 4111 "skipping freesync init\n",
4112 new_crtcs[i]->crtc_id);
e7b07cee
HW		 4113 continue;
4114 }
4115
4116 mod_freesync_add_stream(adev->dm.freesync_module,
4117 new_stream, &aconnector->caps);
4118 }
4119 }
4120
4121 if (dm_state->context)
608ac7bb 4122 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
e7b07cee 4123
0bc9706d 4124 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4125 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4126
54d76575 4127 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4128
54d76575 4129 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4130 const struct dc_stream_status *status =
54d76575 4131 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4132
4133 if (!status)
54d76575 4134 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4135 else
4136 acrtc->otg_inst = status->primary_otg_inst;
4137 }
4138 }
4139
ebdd27e1 4140 /* Handle scaling and underscan changes*/
c2cea706 4141 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4142 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4143 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4144 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4145 struct dc_stream_status *status = NULL;
4146
0bc9706d
LSL		 4147 if (acrtc)
4148 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4149
e7b07cee 4150 /* Skip any modesets/resets */
0bc9706d 4151 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4152 continue;
4153
4154 /* Skip any thing not scale or underscan changes */
54d76575 4155 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4156 continue;
4157
54d76575 4158 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4159
54d76575
LSL		 4160 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4161 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4162
54d76575 4163 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4164 WARN_ON(!status);
3be5262e 4165 WARN_ON(!status->plane_count);
e7b07cee 4166
54d76575 4167 if (!dm_new_crtc_state->stream)
e7b07cee
HW		 4168 continue;
4169
4170 /*TODO How it works with MPO ?*/
3be5262e 4171 if (!dc_commit_planes_to_stream(
e7b07cee 4172 dm->dc,
3be5262e
HW		 4173 status->plane_states,
4174 status->plane_count,
bc6828e0
BL		 4175 dm_new_crtc_state->stream,
4176 dm_state->context))
e7b07cee
HW		 4177 dm_error("%s: Failed to update stream scaling!\n", __func__);
4178 }
4179
4180 for (i = 0; i < new_crtcs_count; i++) {
4181 /*
4182 * loop to enable interrupts on newly arrived crtc
4183 */
4184 struct amdgpu_crtc *acrtc = new_crtcs[i];
b830ebc9 4185
0bc9706d 4186 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
54d76575 4187 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 4188
4189 if (adev->dm.freesync_module)
4190 mod_freesync_notify_mode_change(
54d76575 4191 adev->dm.freesync_module, &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4192
4193 manage_dm_interrupts(adev, acrtc, true);
4194 }
4195
4196 /* update planes when needed per crtc*/
5cc6dcbd 4197 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4198 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4199
54d76575 4200 if (dm_new_crtc_state->stream)
5cc6dcbd 4201 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4202 }
4203
4204
4205 /*
4206 * send vblank event on all events not handled in flip and
4207 * mark consumed event for drm_atomic_helper_commit_hw_done
4208 */
4209 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4210 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4211
0bc9706d
LSL		 4212 if (new_crtc_state->event)
4213 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4214
0bc9706d 4215 new_crtc_state->event = NULL;
e7b07cee
HW		 4216 }
4217 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4218
4219 /* Signal HW programming completion */
4220 drm_atomic_helper_commit_hw_done(state);
4221
4222 if (wait_for_vblank)
4223 drm_atomic_helper_wait_for_vblanks(dev, state);
4224
4225 drm_atomic_helper_cleanup_planes(dev, state);
4226}
4227
4228
4229static int dm_force_atomic_commit(struct drm_connector *connector)
4230{
4231 int ret = 0;
4232 struct drm_device *ddev = connector->dev;
4233 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4234 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4235 struct drm_plane *plane = disconnected_acrtc->base.primary;
4236 struct drm_connector_state *conn_state;
4237 struct drm_crtc_state *crtc_state;
4238 struct drm_plane_state *plane_state;
4239
4240 if (!state)
4241 return -ENOMEM;
4242
4243 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4244
4245 /* Construct an atomic state to restore previous display setting */
4246
4247 /*
4248 * Attach connectors to drm_atomic_state
4249 */
4250 conn_state = drm_atomic_get_connector_state(state, connector);
4251
4252 ret = PTR_ERR_OR_ZERO(conn_state);
4253 if (ret)
4254 goto err;
4255
4256 /* Attach crtc to drm_atomic_state*/
4257 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4258
4259 ret = PTR_ERR_OR_ZERO(crtc_state);
4260 if (ret)
4261 goto err;
4262
4263 /* force a restore */
4264 crtc_state->mode_changed = true;
4265
4266 /* Attach plane to drm_atomic_state */
4267 plane_state = drm_atomic_get_plane_state(state, plane);
4268
4269 ret = PTR_ERR_OR_ZERO(plane_state);
4270 if (ret)
4271 goto err;
4272
4273
4274 /* Call commit internally with the state we just constructed */
4275 ret = drm_atomic_commit(state);
4276 if (!ret)
4277 return 0;
4278
4279err:
4280 DRM_ERROR("Restoring old state failed with %i\n", ret);
4281 drm_atomic_state_put(state);
4282
4283 return ret;
4284}
4285
4286/*
4287 * This functions handle all cases when set mode does not come upon hotplug.
4288 * This include when the same display is unplugged then plugged back into the
4289 * same port and when we are running without usermode desktop manager supprot
4290 */
3ee6b26b
AD		 4291void dm_restore_drm_connector_state(struct drm_device *dev,
4292 struct drm_connector *connector)
e7b07cee 4293{
c84dec2f 4294 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4295 struct amdgpu_crtc *disconnected_acrtc;
4296 struct dm_crtc_state *acrtc_state;
4297
4298 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4299 return;
4300
4301 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4302 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4303
4304 if (!disconnected_acrtc || !acrtc_state->stream)
4305 return;
4306
4307 /*
4308 * If the previous sink is not released and different from the current,
4309 * we deduce we are in a state where we can not rely on usermode call
4310 * to turn on the display, so we do it here
4311 */
4312 if (acrtc_state->stream->sink != aconnector->dc_sink)
4313 dm_force_atomic_commit(&aconnector->base);
4314}
4315
e7b07cee
HW		 4316/*`
4317 * Grabs all modesetting locks to serialize against any blocking commits,
4318 * Waits for completion of all non blocking commits.
4319 */
3ee6b26b
AD		 4320static int do_aquire_global_lock(struct drm_device *dev,
4321 struct drm_atomic_state *state)
e7b07cee
HW		 4322{
4323 struct drm_crtc *crtc;
4324 struct drm_crtc_commit *commit;
4325 long ret;
4326
4327 /* Adding all modeset locks to aquire_ctx will
4328 * ensure that when the framework release it the
4329 * extra locks we are locking here will get released to
4330 */
4331 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4332 if (ret)
4333 return ret;
4334
4335 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4336 spin_lock(&crtc->commit_lock);
4337 commit = list_first_entry_or_null(&crtc->commit_list,
4338 struct drm_crtc_commit, commit_entry);
4339 if (commit)
4340 drm_crtc_commit_get(commit);
4341 spin_unlock(&crtc->commit_lock);
4342
4343 if (!commit)
4344 continue;
4345
4346 /* Make sure all pending HW programming completed and
4347 * page flips done
4348 */
4349 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4350
4351 if (ret > 0)
4352 ret = wait_for_completion_interruptible_timeout(
4353 &commit->flip_done, 10*HZ);
4354
4355 if (ret == 0)
4356 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4357 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4358
4359 drm_crtc_commit_put(commit);
4360 }
4361
4362 return ret < 0 ? ret : 0;
4363}
4364
3ee6b26b
AD		 4365static int dm_update_crtcs_state(struct dc *dc,
4366 struct drm_atomic_state *state,
4367 bool enable,
4368 bool *lock_and_validation_needed)
e7b07cee 4369{
e7b07cee 4370 struct drm_crtc *crtc;
c2cea706 4371 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4372 int i;
54d76575 4373 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4374 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4375 struct dc_stream_state *new_stream;
62f55537 4376 int ret = 0;
d4d4a645 4377
62f55537
AG		 4378 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4379 /* update changed items */
c2cea706 4380 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4381 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4382 struct amdgpu_dm_connector *aconnector = NULL;
c2cea706 4383 struct drm_connector_state *new_con_state = NULL;
62f55537 4384 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4385
9635b754
DS		 4386 new_stream = NULL;
4387
54d76575
LSL		 4388 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4389 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4390 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4391
1daf8c63 4392 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4393
62f55537 4394 /* TODO This hack should go away */
f4ac176e
JZ		 4395 if (aconnector && enable) {
4396 // Make sure fake sink is created in plug-in scenario
c2cea706
LSL		 4397 new_con_state = drm_atomic_get_connector_state(state,
4398 &aconnector->base);
19f89e23 4399
c2cea706
LSL		 4400 if (IS_ERR(new_con_state)) {
4401 ret = PTR_ERR_OR_ZERO(new_con_state);
62f55537
AG		 4402 break;
4403 }
19f89e23 4404
c2cea706 4405 dm_conn_state = to_dm_connector_state(new_con_state);
19f89e23 4406
62f55537 4407 new_stream = create_stream_for_sink(aconnector,
c2cea706 4408 &new_crtc_state->mode,
62f55537 4409 dm_conn_state);
19f89e23 4410
62f55537
AG		 4411 /*
4412 * we can have no stream on ACTION_SET if a display
4413 * was disconnected during S3, in this case it not and
4414 * error, the OS will be updated after detection, and
4415 * do the right thing on next atomic commit
4416 */
19f89e23 4417
62f55537 4418 if (!new_stream) {
f1ad2f5e 4419 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4420 __func__, acrtc->base.base.id);
4421 break;
19f89e23 4422 }
62f55537 4423 }
19f89e23 4424
9a5d9c48
LSL		 4425 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4426 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
19f89e23 4427
c2cea706 4428 new_crtc_state->mode_changed = false;
e7b07cee 4429
c2cea706 4430 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9a5d9c48 4431 new_crtc_state->mode_changed);
62f55537 4432 }
b830ebc9 4433
e7b07cee 4434
c2cea706 4435 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4436 goto next_crtc;
e7b07cee 4437
f1ad2f5e 4438 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4439 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4440 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4441 "connectors_changed:%d\n",
4442 acrtc->crtc_id,
c2cea706
LSL		 4443 new_crtc_state->enable,
4444 new_crtc_state->active,
4445 new_crtc_state->planes_changed,
4446 new_crtc_state->mode_changed,
4447 new_crtc_state->active_changed,
4448 new_crtc_state->connectors_changed);
e7b07cee 4449
62f55537
AG		 4450 /* Remove stream for any changed/disabled CRTC */
4451 if (!enable) {
4452
54d76575 4453 if (!dm_old_crtc_state->stream)
9635b754 4454 goto next_crtc;
62f55537 4455
f1ad2f5e 4456 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4457 crtc->base.id);
e7b07cee 4458
1dc90497 4459 /* i.e. reset mode */
62c933f9 4460 if (dc_remove_stream_from_ctx(
62f55537
AG		 4461 dc,
4462 dm_state->context,
62c933f9 4463 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4464 ret = -EINVAL;
9635b754 4465 goto fail;
62f55537
AG		 4466 }
4467
54d76575
LSL		 4468 dc_stream_release(dm_old_crtc_state->stream);
4469 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4470
4471 *lock_and_validation_needed = true;
4472
4473 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4474 /*
4475 * Quick fix to prevent NULL pointer on new_stream when
4476 * added MST connectors not found in existing crtc_state in the chained mode
4477 * TODO: need to dig out the root cause of that
4478 */
4479 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4480 goto next_crtc;
62f55537 4481
c2cea706 4482 if (modereset_required(new_crtc_state))
9635b754 4483 goto next_crtc;
62f55537 4484
c2cea706 4485 if (modeset_required(new_crtc_state, new_stream,
54d76575 4486 dm_old_crtc_state->stream)) {
62f55537 4487
54d76575 4488 WARN_ON(dm_new_crtc_state->stream);
62f55537 4489
54d76575 4490 dm_new_crtc_state->stream = new_stream;
62f55537
AG		 4491 dc_stream_retain(new_stream);
4492
f1ad2f5e 4493 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4494 crtc->base.id);
1dc90497 4495
13ab1b44 4496 if (dc_add_stream_to_ctx(
1dc90497
AG		 4497 dc,
4498 dm_state->context,
13ab1b44 4499 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4500 ret = -EINVAL;
9635b754 4501 goto fail;
1dc90497
AG		 4502 }
4503
62f55537 4504 *lock_and_validation_needed = true;
9b690ef3 4505 }
62f55537 4506 }
9b690ef3 4507
9635b754 4508next_crtc:
62f55537
AG		 4509 /* Release extra reference */
4510 if (new_stream)
4511 dc_stream_release(new_stream);
4512 }
e7b07cee 4513
62f55537 4514 return ret;
9635b754
DS		 4515
4516fail:
4517 if (new_stream)
4518 dc_stream_release(new_stream);
4519 return ret;
62f55537 4520}
9b690ef3 4521
3ee6b26b
AD		 4522static int dm_update_planes_state(struct dc *dc,
4523 struct drm_atomic_state *state,
4524 bool enable,
4525 bool *lock_and_validation_needed)
62f55537
AG		 4526{
4527 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4528 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4529 struct drm_plane *plane;
4530 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4531 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4532 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4533 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4534 int i ;
4535 /* TODO return page_flip_needed() function */
4536 bool pflip_needed = !state->allow_modeset;
4537 int ret = 0;
e7b07cee 4538
62f55537
AG		 4539 if (pflip_needed)
4540 return ret;
9b690ef3 4541
62f55537
AG		 4542 /* Add new planes */
4543 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4544 new_plane_crtc = new_plane_state->crtc;
4545 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4546 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4547 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4548
4549 /*TODO Implement atomic check for cursor plane */
4550 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4551 continue;
9b690ef3 4552
62f55537
AG		 4553 /* Remove any changed/removed planes */
4554 if (!enable) {
a7b06724 4555
62f55537
AG		 4556 if (!old_plane_crtc)
4557 continue;
4558
0bc9706d
LSL		 4559 old_crtc_state = drm_atomic_get_old_crtc_state(
4560 state, old_plane_crtc);
54d76575 4561 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4562
54d76575 4563 if (!dm_old_crtc_state->stream)
62f55537
AG		 4564 continue;
4565
f1ad2f5e 4566 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4567 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4568
62f55537
AG		 4569 if (!dc_remove_plane_from_context(
4570 dc,
54d76575
LSL		 4571 dm_old_crtc_state->stream,
4572 dm_old_plane_state->dc_state,
62f55537
AG		 4573 dm_state->context)) {
4574
4575 ret = EINVAL;
4576 return ret;
e7b07cee
HW		 4577 }
4578
9b690ef3 4579
54d76575
LSL		 4580 dc_plane_state_release(dm_old_plane_state->dc_state);
4581 dm_new_plane_state->dc_state = NULL;
1dc90497 4582
62f55537 4583 *lock_and_validation_needed = true;
1dc90497 4584
62f55537 4585 } else { /* Add new planes */
1dc90497 4586
62f55537
AG		 4587 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4588 continue;
e7b07cee 4589
62f55537
AG		 4590 if (!new_plane_crtc)
4591 continue;
e7b07cee 4592
62f55537 4593 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4594 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4595
54d76575 4596 if (!dm_new_crtc_state->stream)
62f55537
AG		 4597 continue;
4598
4599
54d76575 4600 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4601
54d76575 4602 dm_new_plane_state->dc_state = dc_create_plane_state(dc);
62f55537 4603
f1ad2f5e 4604 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
62f55537
AG		 4605 plane->base.id, new_plane_crtc->base.id);
4606
54d76575 4607 if (!dm_new_plane_state->dc_state) {
62f55537
AG		 4608 ret = -EINVAL;
4609 return ret;
4610 }
4611
4612 ret = fill_plane_attributes(
4613 new_plane_crtc->dev->dev_private,
54d76575 4614 dm_new_plane_state->dc_state,
62f55537
AG		 4615 new_plane_state,
4616 new_crtc_state,
4617 false);
4618 if (ret)
4619 return ret;
4620
4621
4622 if (!dc_add_plane_to_context(
4623 dc,
54d76575
LSL		 4624 dm_new_crtc_state->stream,
4625 dm_new_plane_state->dc_state,
62f55537
AG		 4626 dm_state->context)) {
4627
4628 ret = -EINVAL;
4629 return ret;
e7b07cee 4630 }
62f55537
AG		 4631
4632 *lock_and_validation_needed = true;
e7b07cee 4633 }
62f55537 4634 }
e7b07cee
HW		 4635
4636
62f55537
AG		 4637 return ret;
4638}
4639
7578ecda
AD		 4640static int amdgpu_dm_atomic_check(struct drm_device *dev,
4641 struct drm_atomic_state *state)
62f55537
AG		 4642{
4643 int i;
4644 int ret;
4645 struct amdgpu_device *adev = dev->dev_private;
4646 struct dc *dc = adev->dm.dc;
4647 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4648 struct drm_connector *connector;
c2cea706 4649 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4650 struct drm_crtc *crtc;
c2cea706 4651 struct drm_crtc_state *new_crtc_state;
e7b07cee 4652
62f55537
AG		 4653 /*
4654 * This bool will be set for true for any modeset/reset
4655 * or plane update which implies non fast surface update.
4656 */
4657 bool lock_and_validation_needed = false;
4658
4659 ret = drm_atomic_helper_check_modeset(dev, state);
4660
4661 if (ret) {
4662 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret);
4663 return ret;
4664 }
4665
4666 /*
4667 * Hack: Commit needs planes right now, specifically for gamma
4668 * TODO rework commit to check CRTC for gamma change
4669 */
c2cea706
LSL		 4670 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4671 if (new_crtc_state->color_mgmt_changed) {
e7b07cee
HW		 4672 ret = drm_atomic_add_affected_planes(state, crtc);
4673 if (ret)
4674 goto fail;
4675 }
4676 }
4677
62f55537
AG		 4678 dm_state->context = dc_create_state();
4679 ASSERT(dm_state->context);
f36cc577 4680 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4681
4682 /* Remove exiting planes if they are modified */
4683 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4684 if (ret) {
4685 goto fail;
4686 }
4687
4688 /* Disable all crtcs which require disable */
4689 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4690 if (ret) {
4691 goto fail;
4692 }
4693
4694 /* Enable all crtcs which require enable */
4695 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4696 if (ret) {
4697 goto fail;
4698 }
4699
4700 /* Add new/modified planes */
4701 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4702 if (ret) {
4703 goto fail;
4704 }
4705
4706 /* Run this here since we want to validate the streams we created */
4707 ret = drm_atomic_helper_check_planes(dev, state);
4708 if (ret)
4709 goto fail;
4710
ebdd27e1 4711 /* Check scaling and underscan changes*/
e7b07cee
HW		 4712 /*TODO Removed scaling changes validation due to inability to commit
4713 * new stream into context w\o causing full reset. Need to
4714 * decide how to handle.
4715 */
c2cea706 4716 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4717 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4718 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4719 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4720
4721 /* Skip any modesets/resets */
0bc9706d
LSL		 4722 if (!acrtc || drm_atomic_crtc_needs_modeset(
4723 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 4724 continue;
4725
b830ebc9 4726 /* Skip any thing not scale or underscan changes */
54d76575 4727 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4728 continue;
4729
4730 lock_and_validation_needed = true;
4731 }
4732
e7b07cee
HW		 4733 /*
4734 * For full updates case when
4735 * removing/adding/updating streams on once CRTC while flipping
4736 * on another CRTC,
4737 * acquiring global lock will guarantee that any such full
4738 * update commit
4739 * will wait for completion of any outstanding flip using DRMs
4740 * synchronization events.
4741 */
4742
4743 if (lock_and_validation_needed) {
4744
4745 ret = do_aquire_global_lock(dev, state);
4746 if (ret)
4747 goto fail;
1dc90497 4748
e750d56d 4749 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 4750 ret = -EINVAL;
4751 goto fail;
4752 }
4753 }
4754
4755 /* Must be success */
4756 WARN_ON(ret);
4757 return ret;
4758
4759fail:
4760 if (ret == -EDEADLK)
f1ad2f5e 4761 DRM_DEBUG_DRIVER("Atomic check stopped due to to deadlock.\n");
e7b07cee 4762 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
f1ad2f5e 4763 DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n");
e7b07cee 4764 else
62f55537 4765 DRM_ERROR("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 4766
4767 return ret;
4768}
4769
3ee6b26b
AD		 4770static bool is_dp_capable_without_timing_msa(struct dc *dc,
4771 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 4772{
4773 uint8_t dpcd_data;
4774 bool capable = false;
4775
c84dec2f 4776 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 4777 dm_helpers_dp_read_dpcd(
4778 NULL,
c84dec2f 4779 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 4780 DP_DOWN_STREAM_PORT_COUNT,
4781 &dpcd_data,
4782 sizeof(dpcd_data))) {
4783 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4784 }
4785
4786 return capable;
4787}
3ee6b26b
AD		 4788void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4789 struct edid *edid)
e7b07cee
HW		 4790{
4791 int i;
4792 uint64_t val_capable;
4793 bool edid_check_required;
4794 struct detailed_timing *timing;
4795 struct detailed_non_pixel *data;
4796 struct detailed_data_monitor_range *range;
c84dec2f
HW		 4797 struct amdgpu_dm_connector *amdgpu_dm_connector =
4798 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4799
4800 struct drm_device *dev = connector->dev;
4801 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4802
e7b07cee 4803 edid_check_required = false;
c84dec2f 4804 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 4805 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4806 return;
4807 }
4808 if (!adev->dm.freesync_module)
4809 return;
4810 /*
4811 * if edid non zero restrict freesync only for dp and edp
4812 */
4813 if (edid) {
c84dec2f
HW		 4814 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4815 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 4816 edid_check_required = is_dp_capable_without_timing_msa(
4817 adev->dm.dc,
c84dec2f 4818 amdgpu_dm_connector);
e7b07cee
HW		 4819 }
4820 }
4821 val_capable = 0;
4822 if (edid_check_required == true && (edid->version > 1 ||
4823 (edid->version == 1 && edid->revision > 1))) {
4824 for (i = 0; i < 4; i++) {
4825
4826 timing = &edid->detailed_timings[i];
4827 data = &timing->data.other_data;
4828 range = &data->data.range;
4829 /*
4830 * Check if monitor has continuous frequency mode
4831 */
4832 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4833 continue;
4834 /*
4835 * Check for flag range limits only. If flag == 1 then
4836 * no additional timing information provided.
4837 * Default GTF, GTF Secondary curve and CVT are not
4838 * supported
4839 */
4840 if (range->flags != 1)
4841 continue;
4842
c84dec2f
HW		 4843 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
4844 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
4845 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 4846 range->pixel_clock_mhz * 10;
4847 break;
4848 }
4849
c84dec2f
HW		 4850 if (amdgpu_dm_connector->max_vfreq -
4851 amdgpu_dm_connector->min_vfreq > 10) {
4852 amdgpu_dm_connector->caps.supported = true;
4853 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
4854 amdgpu_dm_connector->min_vfreq * 1000000;
4855 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
4856 amdgpu_dm_connector->max_vfreq * 1000000;
e7b07cee
HW		 4857 val_capable = 1;
4858 }
4859 }
4860
4861 /*
4862 * TODO figure out how to notify user-mode or DRM of freesync caps
4863 * once we figure out how to deal with freesync in an upstreamable
4864 * fashion
4865 */
4866
4867}
4868
3ee6b26b 4869void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 4870{
4871 /*
4872 * TODO fill in once we figure out how to deal with freesync in
4873 * an upstreamable fashion
4874 */
4875}
Linux 6.x block layer and io_uring tree(s)