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drm/amd/display: Add a backlight module option
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
1dc90497 31#include "dc/inc/core_types.h"
a7669aff 32#include "dal_asic_id.h"
cdca3f21 33#include "dmub/dmub_srv.h"
743b9786
NK		 34#include "dc/inc/hw/dmcu.h"
35#include "dc/inc/hw/abm.h"
9a71c7d3 36#include "dc/dc_dmub_srv.h"
f9b4f20c 37#include "dc/dc_edid_parser.h"
9d83722d 38#include "amdgpu_dm_trace.h"
4562236b
HW		 39
40#include "vid.h"
41#include "amdgpu.h"
a49dcb88 42#include "amdgpu_display.h"
a94d5569 43#include "amdgpu_ucode.h"
4562236b
HW		 44#include "atom.h"
45#include "amdgpu_dm.h"
52704fca
BL		 46#ifdef CONFIG_DRM_AMD_DC_HDCP
47#include "amdgpu_dm_hdcp.h"
53e108aa 48#include <drm/drm_hdcp.h>
52704fca 49#endif
e7b07cee 50#include "amdgpu_pm.h"
4562236b
HW		 51
52#include "amd_shared.h"
53#include "amdgpu_dm_irq.h"
54#include "dm_helpers.h"
e7b07cee 55#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 56#if defined(CONFIG_DEBUG_FS)
57#include "amdgpu_dm_debugfs.h"
58#endif
4562236b
HW		 59
60#include "ivsrcid/ivsrcid_vislands30.h"
61
62#include <linux/module.h>
63#include <linux/moduleparam.h>
e7b07cee 64#include <linux/types.h>
97028037 65#include <linux/pm_runtime.h>
09d21852 66#include <linux/pci.h>
a94d5569 67#include <linux/firmware.h>
6ce8f316 68#include <linux/component.h>
4562236b
HW		 69
70#include <drm/drm_atomic.h>
674e78ac 71#include <drm/drm_atomic_uapi.h>
4562236b
HW		 72#include <drm/drm_atomic_helper.h>
73#include <drm/drm_dp_mst_helper.h>
e7b07cee 74#include <drm/drm_fb_helper.h>
09d21852 75#include <drm/drm_fourcc.h>
e7b07cee 76#include <drm/drm_edid.h>
09d21852 77#include <drm/drm_vblank.h>
6ce8f316 78#include <drm/drm_audio_component.h>
0c8620d6 79#include <drm/drm_hdcp.h>
4562236b 80
b86a1aa3 81#if defined(CONFIG_DRM_AMD_DC_DCN)
5527cd06 82#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
ff5ef992 83
ad941f7a
FX		 84#include "dcn/dcn_1_0_offset.h"
85#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 86#include "soc15_hw_ip.h"
87#include "vega10_ip_offset.h"
ff5ef992
AD		 88
89#include "soc15_common.h"
90#endif
91
e7b07cee 92#include "modules/inc/mod_freesync.h"
bbf854dc 93#include "modules/power/power_helpers.h"
ecd0136b 94#include "modules/inc/mod_info_packet.h"
e7b07cee 95
743b9786
NK		 96#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
97MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
79037324
BL		 98#define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
99MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
5ce868fc
BL		 100#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
101MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
71c0fd92
RL		 102#define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
103MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
469989ca
RL		 104#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
105MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
2a411205
BL		 106#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
107MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
2200eb9e 108
a94d5569
DF		 109#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
110MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 111
5ea23931
RL		 112#define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
113MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
114
8c7aea40
NK		 115/* Number of bytes in PSP header for firmware. */
116#define PSP_HEADER_BYTES 0x100
117
118/* Number of bytes in PSP footer for firmware. */
119#define PSP_FOOTER_BYTES 0x100
120
b8592b48
LL		 121/**
122 * DOC: overview
123 *
124 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
125 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
126 * requests into DC requests, and DC responses into DRM responses.
127 *
128 * The root control structure is &struct amdgpu_display_manager.
129 */
130
7578ecda
AD		 131/* basic init/fini API */
132static int amdgpu_dm_init(struct amdgpu_device *adev);
133static void amdgpu_dm_fini(struct amdgpu_device *adev);
134
0f877894
OV		 135static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
136{
137 switch (link->dpcd_caps.dongle_type) {
138 case DISPLAY_DONGLE_NONE:
139 return DRM_MODE_SUBCONNECTOR_Native;
140 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
141 return DRM_MODE_SUBCONNECTOR_VGA;
142 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
143 case DISPLAY_DONGLE_DP_DVI_DONGLE:
144 return DRM_MODE_SUBCONNECTOR_DVID;
145 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
146 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
147 return DRM_MODE_SUBCONNECTOR_HDMIA;
148 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
149 default:
150 return DRM_MODE_SUBCONNECTOR_Unknown;
151 }
152}
153
154static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
155{
156 struct dc_link *link = aconnector->dc_link;
157 struct drm_connector *connector = &aconnector->base;
158 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
159
160 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
161 return;
162
163 if (aconnector->dc_sink)
164 subconnector = get_subconnector_type(link);
165
166 drm_object_property_set_value(&connector->base,
167 connector->dev->mode_config.dp_subconnector_property,
168 subconnector);
169}
170
1f6010a9
DF		 171/*
172 * initializes drm_device display related structures, based on the information
7578ecda
AD		 173 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
174 * drm_encoder, drm_mode_config
175 *
176 * Returns 0 on success
177 */
178static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
179/* removes and deallocates the drm structures, created by the above function */
180static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
181
7578ecda 182static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 183 struct drm_plane *plane,
cc1fec57
NK		 184 unsigned long possible_crtcs,
185 const struct dc_plane_cap *plane_cap);
7578ecda
AD		 186static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
187 struct drm_plane *plane,
188 uint32_t link_index);
189static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
190 struct amdgpu_dm_connector *amdgpu_dm_connector,
191 uint32_t link_index,
192 struct amdgpu_encoder *amdgpu_encoder);
193static int amdgpu_dm_encoder_init(struct drm_device *dev,
194 struct amdgpu_encoder *aencoder,
195 uint32_t link_index);
196
197static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
198
7578ecda
AD		 199static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
200
201static int amdgpu_dm_atomic_check(struct drm_device *dev,
202 struct drm_atomic_state *state);
203
674e78ac
NK		 204static void handle_cursor_update(struct drm_plane *plane,
205 struct drm_plane_state *old_plane_state);
7578ecda 206
8c322309
RL		 207static void amdgpu_dm_set_psr_caps(struct dc_link *link);
208static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
209static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
210static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
6ee90e88 211static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
8c322309 212
dfbbfe3c
BN		 213static const struct drm_format_info *
214amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
215
6f59f229
AP		 216static bool
217is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
218 struct drm_crtc_state *new_crtc_state);
4562236b
HW		 219/*
220 * dm_vblank_get_counter
221 *
222 * @brief
223 * Get counter for number of vertical blanks
224 *
225 * @param
226 * struct amdgpu_device *adev - [in] desired amdgpu device
227 * int disp_idx - [in] which CRTC to get the counter from
228 *
229 * @return
230 * Counter for vertical blanks
231 */
232static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
233{
234 if (crtc >= adev->mode_info.num_crtc)
235 return 0;
236 else {
237 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
238
585d450c 239 if (acrtc->dm_irq_params.stream == NULL) {
0971c40e
HW		 240 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
241 crtc);
4562236b
HW		 242 return 0;
243 }
244
585d450c 245 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
4562236b
HW		 246 }
247}
248
249static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 250 u32 *vbl, u32 *position)
4562236b 251{
81c50963
ST		 252 uint32_t v_blank_start, v_blank_end, h_position, v_position;
253
4562236b
HW		 254 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
255 return -EINVAL;
256 else {
257 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
258
585d450c 259 if (acrtc->dm_irq_params.stream == NULL) {
0971c40e
HW		 260 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
261 crtc);
4562236b
HW		 262 return 0;
263 }
264
81c50963
ST		 265 /*
266 * TODO rework base driver to use values directly.
267 * for now parse it back into reg-format
268 */
585d450c 269 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
81c50963
ST		 270 &v_blank_start,
271 &v_blank_end,
272 &h_position,
273 &v_position);
274
e806208d
AG		 275 *position = v_position | (h_position << 16);
276 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 277 }
278
279 return 0;
280}
281
282static bool dm_is_idle(void *handle)
283{
284 /* XXX todo */
285 return true;
286}
287
288static int dm_wait_for_idle(void *handle)
289{
290 /* XXX todo */
291 return 0;
292}
293
294static bool dm_check_soft_reset(void *handle)
295{
296 return false;
297}
298
299static int dm_soft_reset(void *handle)
300{
301 /* XXX todo */
302 return 0;
303}
304
3ee6b26b
AD		 305static struct amdgpu_crtc *
306get_crtc_by_otg_inst(struct amdgpu_device *adev,
307 int otg_inst)
4562236b 308{
4a580877 309 struct drm_device *dev = adev_to_drm(adev);
4562236b
HW		 310 struct drm_crtc *crtc;
311 struct amdgpu_crtc *amdgpu_crtc;
312
4562236b
HW		 313 if (otg_inst == -1) {
314 WARN_ON(1);
315 return adev->mode_info.crtcs[0];
316 }
317
318 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
319 amdgpu_crtc = to_amdgpu_crtc(crtc);
320
321 if (amdgpu_crtc->otg_inst == otg_inst)
322 return amdgpu_crtc;
323 }
324
325 return NULL;
326}
327
585d450c
AP		 328static inline bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc)
329{
330 return acrtc->dm_irq_params.freesync_config.state ==
331 VRR_STATE_ACTIVE_VARIABLE ||
332 acrtc->dm_irq_params.freesync_config.state ==
333 VRR_STATE_ACTIVE_FIXED;
334}
335
66b0c973
MK		 336static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
337{
338 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
339 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
340}
341
6f59f229
AP		 342static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
343 struct dm_crtc_state *new_state)
344{
345 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
346 return true;
347 else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
348 return true;
349 else
350 return false;
351}
352
b8e8c934
HW		 353/**
354 * dm_pflip_high_irq() - Handle pageflip interrupt
355 * @interrupt_params: ignored
356 *
357 * Handles the pageflip interrupt by notifying all interested parties
358 * that the pageflip has been completed.
359 */
4562236b
HW		 360static void dm_pflip_high_irq(void *interrupt_params)
361{
4562236b
HW		 362 struct amdgpu_crtc *amdgpu_crtc;
363 struct common_irq_params *irq_params = interrupt_params;
364 struct amdgpu_device *adev = irq_params->adev;
365 unsigned long flags;
71bbe51a 366 struct drm_pending_vblank_event *e;
71bbe51a
MK		 367 uint32_t vpos, hpos, v_blank_start, v_blank_end;
368 bool vrr_active;
4562236b
HW		 369
370 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
371
372 /* IRQ could occur when in initial stage */
1f6010a9 373 /* TODO work and BO cleanup */
4562236b
HW		 374 if (amdgpu_crtc == NULL) {
375 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
376 return;
377 }
378
4a580877 379 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
4562236b
HW		 380
381 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
382 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
383 amdgpu_crtc->pflip_status,
384 AMDGPU_FLIP_SUBMITTED,
385 amdgpu_crtc->crtc_id,
386 amdgpu_crtc);
4a580877 387 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
4562236b
HW		 388 return;
389 }
390
71bbe51a
MK		 391 /* page flip completed. */
392 e = amdgpu_crtc->event;
393 amdgpu_crtc->event = NULL;
4562236b 394
71bbe51a
MK		 395 if (!e)
396 WARN_ON(1);
1159898a 397
585d450c 398 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
71bbe51a
MK		 399
400 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
401 if (!vrr_active ||
585d450c 402 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
71bbe51a
MK		 403 &v_blank_end, &hpos, &vpos) ||
404 (vpos < v_blank_start)) {
405 /* Update to correct count and vblank timestamp if racing with
406 * vblank irq. This also updates to the correct vblank timestamp
407 * even in VRR mode, as scanout is past the front-porch atm.
408 */
409 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
1159898a 410
71bbe51a
MK		 411 /* Wake up userspace by sending the pageflip event with proper
412 * count and timestamp of vblank of flip completion.
413 */
414 if (e) {
415 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
416
417 /* Event sent, so done with vblank for this flip */
418 drm_crtc_vblank_put(&amdgpu_crtc->base);
419 }
420 } else if (e) {
421 /* VRR active and inside front-porch: vblank count and
422 * timestamp for pageflip event will only be up to date after
423 * drm_crtc_handle_vblank() has been executed from late vblank
424 * irq handler after start of back-porch (vline 0). We queue the
425 * pageflip event for send-out by drm_crtc_handle_vblank() with
426 * updated timestamp and count, once it runs after us.
427 *
428 * We need to open-code this instead of using the helper
429 * drm_crtc_arm_vblank_event(), as that helper would
430 * call drm_crtc_accurate_vblank_count(), which we must
431 * not call in VRR mode while we are in front-porch!
432 */
433
434 /* sequence will be replaced by real count during send-out. */
435 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
436 e->pipe = amdgpu_crtc->crtc_id;
437
4a580877 438 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
71bbe51a
MK		 439 e = NULL;
440 }
4562236b 441
fdd1fe57
MK		 442 /* Keep track of vblank of this flip for flip throttling. We use the
443 * cooked hw counter, as that one incremented at start of this vblank
444 * of pageflip completion, so last_flip_vblank is the forbidden count
445 * for queueing new pageflips if vsync + VRR is enabled.
446 */
5d1c59c4 447 amdgpu_crtc->dm_irq_params.last_flip_vblank =
e3eff4b5 448 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
fdd1fe57 449
54f5499a 450 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4a580877 451 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
4562236b 452
71bbe51a
MK		 453 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
454 amdgpu_crtc->crtc_id, amdgpu_crtc,
455 vrr_active, (int) !e);
4562236b
HW		 456}
457
d2574c33
MK		 458static void dm_vupdate_high_irq(void *interrupt_params)
459{
460 struct common_irq_params *irq_params = interrupt_params;
461 struct amdgpu_device *adev = irq_params->adev;
462 struct amdgpu_crtc *acrtc;
09aef2c4 463 unsigned long flags;
585d450c 464 int vrr_active;
d2574c33
MK		 465
466 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
467
468 if (acrtc) {
585d450c 469 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
d2574c33 470
7f2be468
LP		 471 DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d\n",
472 acrtc->crtc_id,
585d450c 473 vrr_active);
d2574c33
MK		 474
475 /* Core vblank handling is done here after end of front-porch in
476 * vrr mode, as vblank timestamping will give valid results
477 * while now done after front-porch. This will also deliver
478 * page-flip completion events that have been queued to us
479 * if a pageflip happened inside front-porch.
480 */
585d450c 481 if (vrr_active) {
d2574c33 482 drm_crtc_handle_vblank(&acrtc->base);
09aef2c4
MK		 483
484 /* BTR processing for pre-DCE12 ASICs */
585d450c 485 if (acrtc->dm_irq_params.stream &&
09aef2c4 486 adev->family < AMDGPU_FAMILY_AI) {
4a580877 487 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
09aef2c4
MK		 488 mod_freesync_handle_v_update(
489 adev->dm.freesync_module,
585d450c
AP		 490 acrtc->dm_irq_params.stream,
491 &acrtc->dm_irq_params.vrr_params);
09aef2c4
MK		 492
493 dc_stream_adjust_vmin_vmax(
494 adev->dm.dc,
585d450c
AP		 495 acrtc->dm_irq_params.stream,
496 &acrtc->dm_irq_params.vrr_params.adjust);
4a580877 497 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
09aef2c4
MK		 498 }
499 }
d2574c33
MK		 500 }
501}
502
b8e8c934
HW		 503/**
504 * dm_crtc_high_irq() - Handles CRTC interrupt
2346ef47 505 * @interrupt_params: used for determining the CRTC instance
b8e8c934
HW		 506 *
507 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
508 * event handler.
509 */
4562236b
HW		 510static void dm_crtc_high_irq(void *interrupt_params)
511{
512 struct common_irq_params *irq_params = interrupt_params;
513 struct amdgpu_device *adev = irq_params->adev;
4562236b 514 struct amdgpu_crtc *acrtc;
09aef2c4 515 unsigned long flags;
585d450c 516 int vrr_active;
4562236b 517
b57de80a 518 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
16f17eda
LL		 519 if (!acrtc)
520 return;
521
585d450c 522 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
16f17eda 523
2b5aed9a 524 DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
585d450c 525 vrr_active, acrtc->dm_irq_params.active_planes);
16f17eda 526
2346ef47
NK		 527 /**
528 * Core vblank handling at start of front-porch is only possible
529 * in non-vrr mode, as only there vblank timestamping will give
530 * valid results while done in front-porch. Otherwise defer it
531 * to dm_vupdate_high_irq after end of front-porch.
532 */
585d450c 533 if (!vrr_active)
2346ef47
NK		 534 drm_crtc_handle_vblank(&acrtc->base);
535
536 /**
537 * Following stuff must happen at start of vblank, for crc
538 * computation and below-the-range btr support in vrr mode.
539 */
16f17eda 540 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
2346ef47
NK		 541
542 /* BTR updates need to happen before VUPDATE on Vega and above. */
543 if (adev->family < AMDGPU_FAMILY_AI)
544 return;
16f17eda 545
4a580877 546 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
16f17eda 547
585d450c
AP		 548 if (acrtc->dm_irq_params.stream &&
549 acrtc->dm_irq_params.vrr_params.supported &&
550 acrtc->dm_irq_params.freesync_config.state ==
551 VRR_STATE_ACTIVE_VARIABLE) {
2346ef47 552 mod_freesync_handle_v_update(adev->dm.freesync_module,
585d450c
AP		 553 acrtc->dm_irq_params.stream,
554 &acrtc->dm_irq_params.vrr_params);
16f17eda 555
585d450c
AP		 556 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
557 &acrtc->dm_irq_params.vrr_params.adjust);
16f17eda
LL		 558 }
559
2b5aed9a
MK		 560 /*
561 * If there aren't any active_planes then DCH HUBP may be clock-gated.
562 * In that case, pageflip completion interrupts won't fire and pageflip
563 * completion events won't get delivered. Prevent this by sending
564 * pending pageflip events from here if a flip is still pending.
565 *
566 * If any planes are enabled, use dm_pflip_high_irq() instead, to
567 * avoid race conditions between flip programming and completion,
568 * which could cause too early flip completion events.
569 */
2346ef47
NK		 570 if (adev->family >= AMDGPU_FAMILY_RV &&
571 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
585d450c 572 acrtc->dm_irq_params.active_planes == 0) {
16f17eda
LL		 573 if (acrtc->event) {
574 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
575 acrtc->event = NULL;
576 drm_crtc_vblank_put(&acrtc->base);
577 }
578 acrtc->pflip_status = AMDGPU_FLIP_NONE;
579 }
580
4a580877 581 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
16f17eda
LL		 582}
583
86bc2219
WL		 584#if defined(CONFIG_DRM_AMD_DC_DCN)
585/**
586 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
587 * DCN generation ASICs
588 * @interrupt params - interrupt parameters
589 *
590 * Used to set crc window/read out crc value at vertical line 0 position
591 */
592#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
593static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
594{
595 struct common_irq_params *irq_params = interrupt_params;
596 struct amdgpu_device *adev = irq_params->adev;
597 struct amdgpu_crtc *acrtc;
598
599 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
600
601 if (!acrtc)
602 return;
603
604 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
605}
606#endif
607#endif
608
4562236b
HW		 609static int dm_set_clockgating_state(void *handle,
610 enum amd_clockgating_state state)
611{
612 return 0;
613}
614
615static int dm_set_powergating_state(void *handle,
616 enum amd_powergating_state state)
617{
618 return 0;
619}
620
621/* Prototypes of private functions */
622static int dm_early_init(void* handle);
623
a32e24b4 624/* Allocate memory for FBC compressed data */
3e332d3a 625static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 626{
3e332d3a 627 struct drm_device *dev = connector->dev;
1348969a 628 struct amdgpu_device *adev = drm_to_adev(dev);
4d154b85 629 struct dm_compressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 630 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
631 struct drm_display_mode *mode;
42e67c3b
RL		 632 unsigned long max_size = 0;
633
634 if (adev->dm.dc->fbc_compressor == NULL)
635 return;
a32e24b4 636
3e332d3a 637 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 638 return;
639
3e332d3a
RL		 640 if (compressor->bo_ptr)
641 return;
42e67c3b 642
42e67c3b 643
3e332d3a
RL		 644 list_for_each_entry(mode, &connector->modes, head) {
645 if (max_size < mode->htotal * mode->vtotal)
646 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 647 }
648
649 if (max_size) {
650 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 651 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 652 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 653
654 if (r)
42e67c3b
RL		 655 DRM_ERROR("DM: Failed to initialize FBC\n");
656 else {
657 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
658 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
659 }
660
a32e24b4
RL		 661 }
662
663}
a32e24b4 664
6ce8f316
NK		 665static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
666 int pipe, bool *enabled,
667 unsigned char *buf, int max_bytes)
668{
669 struct drm_device *dev = dev_get_drvdata(kdev);
1348969a 670 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 671 struct drm_connector *connector;
672 struct drm_connector_list_iter conn_iter;
673 struct amdgpu_dm_connector *aconnector;
674 int ret = 0;
675
676 *enabled = false;
677
678 mutex_lock(&adev->dm.audio_lock);
679
680 drm_connector_list_iter_begin(dev, &conn_iter);
681 drm_for_each_connector_iter(connector, &conn_iter) {
682 aconnector = to_amdgpu_dm_connector(connector);
683 if (aconnector->audio_inst != port)
684 continue;
685
686 *enabled = true;
687 ret = drm_eld_size(connector->eld);
688 memcpy(buf, connector->eld, min(max_bytes, ret));
689
690 break;
691 }
692 drm_connector_list_iter_end(&conn_iter);
693
694 mutex_unlock(&adev->dm.audio_lock);
695
696 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
697
698 return ret;
699}
700
701static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
702 .get_eld = amdgpu_dm_audio_component_get_eld,
703};
704
705static int amdgpu_dm_audio_component_bind(struct device *kdev,
706 struct device *hda_kdev, void *data)
707{
708 struct drm_device *dev = dev_get_drvdata(kdev);
1348969a 709 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 710 struct drm_audio_component *acomp = data;
711
712 acomp->ops = &amdgpu_dm_audio_component_ops;
713 acomp->dev = kdev;
714 adev->dm.audio_component = acomp;
715
716 return 0;
717}
718
719static void amdgpu_dm_audio_component_unbind(struct device *kdev,
720 struct device *hda_kdev, void *data)
721{
722 struct drm_device *dev = dev_get_drvdata(kdev);
1348969a 723 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 724 struct drm_audio_component *acomp = data;
725
726 acomp->ops = NULL;
727 acomp->dev = NULL;
728 adev->dm.audio_component = NULL;
729}
730
731static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
732 .bind = amdgpu_dm_audio_component_bind,
733 .unbind = amdgpu_dm_audio_component_unbind,
734};
735
736static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
737{
738 int i, ret;
739
740 if (!amdgpu_audio)
741 return 0;
742
743 adev->mode_info.audio.enabled = true;
744
745 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
746
747 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
748 adev->mode_info.audio.pin[i].channels = -1;
749 adev->mode_info.audio.pin[i].rate = -1;
750 adev->mode_info.audio.pin[i].bits_per_sample = -1;
751 adev->mode_info.audio.pin[i].status_bits = 0;
752 adev->mode_info.audio.pin[i].category_code = 0;
753 adev->mode_info.audio.pin[i].connected = false;
754 adev->mode_info.audio.pin[i].id =
755 adev->dm.dc->res_pool->audios[i]->inst;
756 adev->mode_info.audio.pin[i].offset = 0;
757 }
758
759 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
760 if (ret < 0)
761 return ret;
762
763 adev->dm.audio_registered = true;
764
765 return 0;
766}
767
768static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
769{
770 if (!amdgpu_audio)
771 return;
772
773 if (!adev->mode_info.audio.enabled)
774 return;
775
776 if (adev->dm.audio_registered) {
777 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
778 adev->dm.audio_registered = false;
779 }
780
781 /* TODO: Disable audio? */
782
783 adev->mode_info.audio.enabled = false;
784}
785
dfd84d90 786static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
6ce8f316
NK		 787{
788 struct drm_audio_component *acomp = adev->dm.audio_component;
789
790 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
791 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
792
793 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
794 pin, -1);
795 }
796}
797
743b9786
NK		 798static int dm_dmub_hw_init(struct amdgpu_device *adev)
799{
743b9786
NK		 800 const struct dmcub_firmware_header_v1_0 *hdr;
801 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
8c7aea40 802 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
743b9786
NK		 803 const struct firmware *dmub_fw = adev->dm.dmub_fw;
804 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
805 struct abm *abm = adev->dm.dc->res_pool->abm;
743b9786
NK		 806 struct dmub_srv_hw_params hw_params;
807 enum dmub_status status;
808 const unsigned char *fw_inst_const, *fw_bss_data;
8c7aea40 809 uint32_t i, fw_inst_const_size, fw_bss_data_size;
743b9786
NK		 810 bool has_hw_support;
811
812 if (!dmub_srv)
813 /* DMUB isn't supported on the ASIC. */
814 return 0;
815
8c7aea40
NK		 816 if (!fb_info) {
817 DRM_ERROR("No framebuffer info for DMUB service.\n");
818 return -EINVAL;
819 }
820
743b9786
NK		 821 if (!dmub_fw) {
822 /* Firmware required for DMUB support. */
823 DRM_ERROR("No firmware provided for DMUB.\n");
824 return -EINVAL;
825 }
826
827 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
828 if (status != DMUB_STATUS_OK) {
829 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
830 return -EINVAL;
831 }
832
833 if (!has_hw_support) {
834 DRM_INFO("DMUB unsupported on ASIC\n");
835 return 0;
836 }
837
838 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
839
743b9786
NK		 840 fw_inst_const = dmub_fw->data +
841 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
8c7aea40 842 PSP_HEADER_BYTES;
743b9786
NK		 843
844 fw_bss_data = dmub_fw->data +
845 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
846 le32_to_cpu(hdr->inst_const_bytes);
847
848 /* Copy firmware and bios info into FB memory. */
8c7aea40
NK		 849 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
850 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
851
852 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
853
ddde28a5
HW		 854 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
855 * amdgpu_ucode_init_single_fw will load dmub firmware
856 * fw_inst_const part to cw0; otherwise, the firmware back door load
857 * will be done by dm_dmub_hw_init
858 */
859 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
860 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
861 fw_inst_const_size);
862 }
863
a576b345
NK		 864 if (fw_bss_data_size)
865 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
866 fw_bss_data, fw_bss_data_size);
ddde28a5
HW		 867
868 /* Copy firmware bios info into FB memory. */
8c7aea40
NK		 869 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
870 adev->bios_size);
871
872 /* Reset regions that need to be reset. */
873 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
874 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
875
876 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
877 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
878
879 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
880 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
743b9786
NK		 881
882 /* Initialize hardware. */
883 memset(&hw_params, 0, sizeof(hw_params));
884 hw_params.fb_base = adev->gmc.fb_start;
885 hw_params.fb_offset = adev->gmc.aper_base;
886
31a7f4bb
HW		 887 /* backdoor load firmware and trigger dmub running */
888 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
889 hw_params.load_inst_const = true;
890
743b9786
NK		 891 if (dmcu)
892 hw_params.psp_version = dmcu->psp_version;
893
8c7aea40
NK		 894 for (i = 0; i < fb_info->num_fb; ++i)
895 hw_params.fb[i] = &fb_info->fb[i];
743b9786
NK		 896
897 status = dmub_srv_hw_init(dmub_srv, &hw_params);
898 if (status != DMUB_STATUS_OK) {
899 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
900 return -EINVAL;
901 }
902
903 /* Wait for firmware load to finish. */
904 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
905 if (status != DMUB_STATUS_OK)
906 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
907
908 /* Init DMCU and ABM if available. */
909 if (dmcu && abm) {
910 dmcu->funcs->dmcu_init(dmcu);
911 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
912 }
913
9a71c7d3
NK		 914 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
915 if (!adev->dm.dc->ctx->dmub_srv) {
916 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
917 return -ENOMEM;
918 }
919
743b9786
NK		 920 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
921 adev->dm.dmcub_fw_version);
922
923 return 0;
924}
925
e6cd859d 926#if defined(CONFIG_DRM_AMD_DC_DCN)
c0fb85ae 927static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
c44a22b3 928{
c0fb85ae
YZ		 929 uint64_t pt_base;
930 uint32_t logical_addr_low;
931 uint32_t logical_addr_high;
932 uint32_t agp_base, agp_bot, agp_top;
933 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
c44a22b3 934
c0fb85ae
YZ		 935 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
936 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
c44a22b3 937
c0fb85ae
YZ		 938 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
939 /*
940 * Raven2 has a HW issue that it is unable to use the vram which
941 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
942 * workaround that increase system aperture high address (add 1)
943 * to get rid of the VM fault and hardware hang.
944 */
945 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
946 else
947 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
c44a22b3 948
c0fb85ae
YZ		 949 agp_base = 0;
950 agp_bot = adev->gmc.agp_start >> 24;
951 agp_top = adev->gmc.agp_end >> 24;
c44a22b3 952
c44a22b3 953
c0fb85ae
YZ		 954 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
955 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
956 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
957 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
958 page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
959 page_table_base.low_part = lower_32_bits(pt_base);
c44a22b3 960
c0fb85ae
YZ		 961 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
962 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
963
964 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
965 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
966 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
967
968 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
969 pa_config->system_aperture.fb_offset = adev->gmc.aper_base;
970 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
971
972 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
973 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
974 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
975
976 pa_config->is_hvm_enabled = 0;
c44a22b3 977
c44a22b3 978}
e6cd859d 979#endif
d7faf6f5
QZ		 980#if defined(CONFIG_DRM_AMD_DC_DCN)
981static void event_mall_stutter(struct work_struct *work)
982{
983
984 struct vblank_workqueue *vblank_work = container_of(work, struct vblank_workqueue, mall_work);
985 struct amdgpu_display_manager *dm = vblank_work->dm;
986
987 mutex_lock(&dm->dc_lock);
988
989 if (vblank_work->enable)
990 dm->active_vblank_irq_count++;
991 else
992 dm->active_vblank_irq_count--;
993
994
995 dc_allow_idle_optimizations(
996 dm->dc, dm->active_vblank_irq_count == 0 ? true : false);
997
998 DRM_DEBUG_DRIVER("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
999
1000
1001 mutex_unlock(&dm->dc_lock);
1002}
1003
1004static struct vblank_workqueue *vblank_create_workqueue(struct amdgpu_device *adev, struct dc *dc)
1005{
1006
1007 int max_caps = dc->caps.max_links;
1008 struct vblank_workqueue *vblank_work;
1009 int i = 0;
1010
1011 vblank_work = kcalloc(max_caps, sizeof(*vblank_work), GFP_KERNEL);
1012 if (ZERO_OR_NULL_PTR(vblank_work)) {
1013 kfree(vblank_work);
1014 return NULL;
1015 }
c44a22b3 1016
d7faf6f5
QZ		 1017 for (i = 0; i < max_caps; i++)
1018 INIT_WORK(&vblank_work[i].mall_work, event_mall_stutter);
1019
1020 return vblank_work;
1021}
1022#endif
7578ecda 1023static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 1024{
1025 struct dc_init_data init_data;
52704fca
BL		 1026#ifdef CONFIG_DRM_AMD_DC_HDCP
1027 struct dc_callback_init init_params;
1028#endif
743b9786 1029 int r;
52704fca 1030
4a580877 1031 adev->dm.ddev = adev_to_drm(adev);
4562236b
HW		 1032 adev->dm.adev = adev;
1033
4562236b
HW		 1034 /* Zero all the fields */
1035 memset(&init_data, 0, sizeof(init_data));
52704fca
BL		 1036#ifdef CONFIG_DRM_AMD_DC_HDCP
1037 memset(&init_params, 0, sizeof(init_params));
1038#endif
4562236b 1039
674e78ac 1040 mutex_init(&adev->dm.dc_lock);
6ce8f316 1041 mutex_init(&adev->dm.audio_lock);
d7faf6f5
QZ		 1042#if defined(CONFIG_DRM_AMD_DC_DCN)
1043 spin_lock_init(&adev->dm.vblank_lock);
1044#endif
674e78ac 1045
4562236b
HW		 1046 if(amdgpu_dm_irq_init(adev)) {
1047 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1048 goto error;
1049 }
1050
1051 init_data.asic_id.chip_family = adev->family;
1052
2dc31ca1 1053 init_data.asic_id.pci_revision_id = adev->pdev->revision;
4562236b
HW		 1054 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1055
770d13b1 1056 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 1057 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1058 init_data.asic_id.atombios_base_address =
1059 adev->mode_info.atom_context->bios;
1060
1061 init_data.driver = adev;
1062
1063 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1064
1065 if (!adev->dm.cgs_device) {
1066 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1067 goto error;
1068 }
1069
1070 init_data.cgs_device = adev->dm.cgs_device;
1071
4562236b
HW		 1072 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1073
60fb100b
AD		 1074 switch (adev->asic_type) {
1075 case CHIP_CARRIZO:
1076 case CHIP_STONEY:
1077 case CHIP_RAVEN:
fe3db437 1078 case CHIP_RENOIR:
6e227308 1079 init_data.flags.gpu_vm_support = true;
71c0fd92
RL		 1080 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1081 init_data.flags.disable_dmcu = true;
60fb100b 1082 break;
6df9218a
CL		 1083#if defined(CONFIG_DRM_AMD_DC_DCN)
1084 case CHIP_VANGOGH:
1085 init_data.flags.gpu_vm_support = true;
1086 break;
1087#endif
60fb100b
AD		 1088 default:
1089 break;
1090 }
6e227308 1091
04b94af4
AD		 1092 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1093 init_data.flags.fbc_support = true;
1094
d99f38ae
AD		 1095 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1096 init_data.flags.multi_mon_pp_mclk_switch = true;
1097
eaf56410
LL		 1098 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1099 init_data.flags.disable_fractional_pwm = true;
1100
27eaa492 1101 init_data.flags.power_down_display_on_boot = true;
78ad75f8 1102
4562236b
HW		 1103 /* Display Core create. */
1104 adev->dm.dc = dc_create(&init_data);
1105
423788c7 1106 if (adev->dm.dc) {
76121231 1107 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 1108 } else {
76121231 1109 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 1110 goto error;
1111 }
4562236b 1112
8a791dab
HW		 1113 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1114 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1115 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1116 }
1117
f99d8762
HW		 1118 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1119 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1120
8a791dab
HW		 1121 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1122 adev->dm.dc->debug.disable_stutter = true;
1123
1124 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1125 adev->dm.dc->debug.disable_dsc = true;
1126
1127 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1128 adev->dm.dc->debug.disable_clock_gate = true;
1129
743b9786
NK		 1130 r = dm_dmub_hw_init(adev);
1131 if (r) {
1132 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1133 goto error;
1134 }
1135
bb6785c1
NK		 1136 dc_hardware_init(adev->dm.dc);
1137
0b08c54b 1138#if defined(CONFIG_DRM_AMD_DC_DCN)
13524856 1139 if (adev->apu_flags) {
e6cd859d
AD		 1140 struct dc_phy_addr_space_config pa_config;
1141
0b08c54b 1142 mmhub_read_system_context(adev, &pa_config);
c0fb85ae 1143
0b08c54b
YZ		 1144 // Call the DC init_memory func
1145 dc_setup_system_context(adev->dm.dc, &pa_config);
1146 }
1147#endif
c0fb85ae 1148
4562236b
HW		 1149 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1150 if (!adev->dm.freesync_module) {
1151 DRM_ERROR(
1152 "amdgpu: failed to initialize freesync_module.\n");
1153 } else
f1ad2f5e 1154 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 1155 adev->dm.freesync_module);
1156
e277adc5
LSL		 1157 amdgpu_dm_init_color_mod();
1158
d7faf6f5
QZ		 1159#if defined(CONFIG_DRM_AMD_DC_DCN)
1160 if (adev->dm.dc->caps.max_links > 0) {
1161 adev->dm.vblank_workqueue = vblank_create_workqueue(adev, adev->dm.dc);
1162
1163 if (!adev->dm.vblank_workqueue)
1164 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1165 else
1166 DRM_DEBUG_DRIVER("amdgpu: vblank_workqueue init done %p.\n", adev->dm.vblank_workqueue);
1167 }
1168#endif
1169
52704fca 1170#ifdef CONFIG_DRM_AMD_DC_HDCP
af5bbf93 1171 if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
e50dc171 1172 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
52704fca 1173
96a3b32e
BL		 1174 if (!adev->dm.hdcp_workqueue)
1175 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1176 else
1177 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
52704fca 1178
96a3b32e
BL		 1179 dc_init_callbacks(adev->dm.dc, &init_params);
1180 }
9a65df19
WL		 1181#endif
1182#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1183 adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
52704fca 1184#endif
4562236b
HW		 1185 if (amdgpu_dm_initialize_drm_device(adev)) {
1186 DRM_ERROR(
1187 "amdgpu: failed to initialize sw for display support.\n");
1188 goto error;
1189 }
1190
f74367e4
AD		 1191 /* create fake encoders for MST */
1192 dm_dp_create_fake_mst_encoders(adev);
1193
4562236b
HW		 1194 /* TODO: Add_display_info? */
1195
1196 /* TODO use dynamic cursor width */
4a580877
LT		 1197 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1198 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b 1199
4a580877 1200 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
4562236b
HW		 1201 DRM_ERROR(
1202 "amdgpu: failed to initialize sw for display support.\n");
1203 goto error;
1204 }
1205
c0fb85ae 1206
f1ad2f5e 1207 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 1208
1209 return 0;
1210error:
1211 amdgpu_dm_fini(adev);
1212
59d0f396 1213 return -EINVAL;
4562236b
HW		 1214}
1215
7578ecda 1216static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b 1217{
f74367e4
AD		 1218 int i;
1219
1220 for (i = 0; i < adev->dm.display_indexes_num; i++) {
1221 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
1222 }
1223
6ce8f316
NK		 1224 amdgpu_dm_audio_fini(adev);
1225
4562236b 1226 amdgpu_dm_destroy_drm_device(&adev->dm);
c8bdf2b6 1227
9a65df19
WL		 1228#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1229 if (adev->dm.crc_rd_wrk) {
1230 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
1231 kfree(adev->dm.crc_rd_wrk);
1232 adev->dm.crc_rd_wrk = NULL;
1233 }
1234#endif
52704fca
BL		 1235#ifdef CONFIG_DRM_AMD_DC_HDCP
1236 if (adev->dm.hdcp_workqueue) {
e96b1b29 1237 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
52704fca
BL		 1238 adev->dm.hdcp_workqueue = NULL;
1239 }
1240
1241 if (adev->dm.dc)
1242 dc_deinit_callbacks(adev->dm.dc);
1243#endif
9a71c7d3
NK		 1244 if (adev->dm.dc->ctx->dmub_srv) {
1245 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1246 adev->dm.dc->ctx->dmub_srv = NULL;
1247 }
1248
743b9786
NK		 1249 if (adev->dm.dmub_bo)
1250 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1251 &adev->dm.dmub_bo_gpu_addr,
1252 &adev->dm.dmub_bo_cpu_addr);
52704fca 1253
c8bdf2b6
ED		 1254 /* DC Destroy TODO: Replace destroy DAL */
1255 if (adev->dm.dc)
1256 dc_destroy(&adev->dm.dc);
4562236b
HW		 1257 /*
1258 * TODO: pageflip, vlank interrupt
1259 *
1260 * amdgpu_dm_irq_fini(adev);
1261 */
1262
1263 if (adev->dm.cgs_device) {
1264 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1265 adev->dm.cgs_device = NULL;
1266 }
1267 if (adev->dm.freesync_module) {
1268 mod_freesync_destroy(adev->dm.freesync_module);
1269 adev->dm.freesync_module = NULL;
1270 }
674e78ac 1271
6ce8f316 1272 mutex_destroy(&adev->dm.audio_lock);
674e78ac
NK		 1273 mutex_destroy(&adev->dm.dc_lock);
1274
4562236b
HW		 1275 return;
1276}
1277
a94d5569 1278static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 1279{
a7669aff 1280 const char *fw_name_dmcu = NULL;
a94d5569
DF		 1281 int r;
1282 const struct dmcu_firmware_header_v1_0 *hdr;
1283
1284 switch(adev->asic_type) {
55e56389
MR		 1285#if defined(CONFIG_DRM_AMD_DC_SI)
1286 case CHIP_TAHITI:
1287 case CHIP_PITCAIRN:
1288 case CHIP_VERDE:
1289 case CHIP_OLAND:
1290#endif
a94d5569
DF		 1291 case CHIP_BONAIRE:
1292 case CHIP_HAWAII:
1293 case CHIP_KAVERI:
1294 case CHIP_KABINI:
1295 case CHIP_MULLINS:
1296 case CHIP_TONGA:
1297 case CHIP_FIJI:
1298 case CHIP_CARRIZO:
1299 case CHIP_STONEY:
1300 case CHIP_POLARIS11:
1301 case CHIP_POLARIS10:
1302 case CHIP_POLARIS12:
1303 case CHIP_VEGAM:
1304 case CHIP_VEGA10:
1305 case CHIP_VEGA12:
1306 case CHIP_VEGA20:
476e955d 1307 case CHIP_NAVI10:
baebcf2e 1308 case CHIP_NAVI14:
30221ad8 1309 case CHIP_RENOIR:
79037324 1310 case CHIP_SIENNA_CICHLID:
a6c5308f 1311 case CHIP_NAVY_FLOUNDER:
2a411205 1312 case CHIP_DIMGREY_CAVEFISH:
469989ca 1313 case CHIP_VANGOGH:
a94d5569 1314 return 0;
5ea23931
RL		 1315 case CHIP_NAVI12:
1316 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1317 break;
a94d5569 1318 case CHIP_RAVEN:
a7669aff
HW		 1319 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1320 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1321 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1322 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1323 else
a7669aff 1324 return 0;
a94d5569
DF		 1325 break;
1326 default:
1327 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 1328 return -EINVAL;
a94d5569
DF		 1329 }
1330
1331 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1332 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1333 return 0;
1334 }
1335
1336 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1337 if (r == -ENOENT) {
1338 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1339 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1340 adev->dm.fw_dmcu = NULL;
1341 return 0;
1342 }
1343 if (r) {
1344 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1345 fw_name_dmcu);
1346 return r;
1347 }
1348
1349 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1350 if (r) {
1351 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1352 fw_name_dmcu);
1353 release_firmware(adev->dm.fw_dmcu);
1354 adev->dm.fw_dmcu = NULL;
1355 return r;
1356 }
1357
1358 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1359 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1360 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1361 adev->firmware.fw_size +=
1362 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1363
1364 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1365 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1366 adev->firmware.fw_size +=
1367 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1368
ee6e89c0
DF		 1369 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1370
a94d5569
DF		 1371 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1372
4562236b
HW		 1373 return 0;
1374}
1375
743b9786
NK		 1376static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1377{
1378 struct amdgpu_device *adev = ctx;
1379
1380 return dm_read_reg(adev->dm.dc->ctx, address);
1381}
1382
1383static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1384 uint32_t value)
1385{
1386 struct amdgpu_device *adev = ctx;
1387
1388 return dm_write_reg(adev->dm.dc->ctx, address, value);
1389}
1390
1391static int dm_dmub_sw_init(struct amdgpu_device *adev)
1392{
1393 struct dmub_srv_create_params create_params;
8c7aea40
NK		 1394 struct dmub_srv_region_params region_params;
1395 struct dmub_srv_region_info region_info;
1396 struct dmub_srv_fb_params fb_params;
1397 struct dmub_srv_fb_info *fb_info;
1398 struct dmub_srv *dmub_srv;
743b9786
NK		 1399 const struct dmcub_firmware_header_v1_0 *hdr;
1400 const char *fw_name_dmub;
1401 enum dmub_asic dmub_asic;
1402 enum dmub_status status;
1403 int r;
1404
1405 switch (adev->asic_type) {
1406 case CHIP_RENOIR:
1407 dmub_asic = DMUB_ASIC_DCN21;
1408 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
71c0fd92
RL		 1409 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1410 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
743b9786 1411 break;
79037324
BL		 1412 case CHIP_SIENNA_CICHLID:
1413 dmub_asic = DMUB_ASIC_DCN30;
1414 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
1415 break;
5ce868fc
BL		 1416 case CHIP_NAVY_FLOUNDER:
1417 dmub_asic = DMUB_ASIC_DCN30;
1418 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
79037324 1419 break;
469989ca
RL		 1420 case CHIP_VANGOGH:
1421 dmub_asic = DMUB_ASIC_DCN301;
1422 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
1423 break;
2a411205
BL		 1424 case CHIP_DIMGREY_CAVEFISH:
1425 dmub_asic = DMUB_ASIC_DCN302;
1426 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
1427 break;
743b9786
NK		 1428
1429 default:
1430 /* ASIC doesn't support DMUB. */
1431 return 0;
1432 }
1433
743b9786
NK		 1434 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
1435 if (r) {
1436 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
1437 return 0;
1438 }
1439
1440 r = amdgpu_ucode_validate(adev->dm.dmub_fw);
1441 if (r) {
1442 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
1443 return 0;
1444 }
1445
743b9786 1446 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
743b9786 1447
9a6ed547
NK		 1448 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1449 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
1450 AMDGPU_UCODE_ID_DMCUB;
1451 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
1452 adev->dm.dmub_fw;
1453 adev->firmware.fw_size +=
1454 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
743b9786 1455
9a6ed547
NK		 1456 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1457 adev->dm.dmcub_fw_version);
1458 }
1459
1460 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
743b9786 1461
8c7aea40
NK		 1462 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
1463 dmub_srv = adev->dm.dmub_srv;
1464
1465 if (!dmub_srv) {
1466 DRM_ERROR("Failed to allocate DMUB service!\n");
1467 return -ENOMEM;
1468 }
1469
1470 memset(&create_params, 0, sizeof(create_params));
1471 create_params.user_ctx = adev;
1472 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
1473 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
1474 create_params.asic = dmub_asic;
1475
1476 /* Create the DMUB service. */
1477 status = dmub_srv_create(dmub_srv, &create_params);
1478 if (status != DMUB_STATUS_OK) {
1479 DRM_ERROR("Error creating DMUB service: %d\n", status);
1480 return -EINVAL;
1481 }
1482
1483 /* Calculate the size of all the regions for the DMUB service. */
1484 memset(&region_params, 0, sizeof(region_params));
1485
1486 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1487 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1488 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1489 region_params.vbios_size = adev->bios_size;
0922b899 1490 region_params.fw_bss_data = region_params.bss_data_size ?
1f0674fd
NK		 1491 adev->dm.dmub_fw->data +
1492 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
0922b899 1493 le32_to_cpu(hdr->inst_const_bytes) : NULL;
a576b345
NK		 1494 region_params.fw_inst_const =
1495 adev->dm.dmub_fw->data +
1496 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1497 PSP_HEADER_BYTES;
8c7aea40
NK		 1498
1499 status = dmub_srv_calc_region_info(dmub_srv, &region_params,
1500 &region_info);
1501
1502 if (status != DMUB_STATUS_OK) {
1503 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
1504 return -EINVAL;
1505 }
1506
1507 /*
1508 * Allocate a framebuffer based on the total size of all the regions.
1509 * TODO: Move this into GART.
1510 */
1511 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
1512 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
1513 &adev->dm.dmub_bo_gpu_addr,
1514 &adev->dm.dmub_bo_cpu_addr);
1515 if (r)
1516 return r;
1517
1518 /* Rebase the regions on the framebuffer address. */
1519 memset(&fb_params, 0, sizeof(fb_params));
1520 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
1521 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
1522 fb_params.region_info = &region_info;
1523
1524 adev->dm.dmub_fb_info =
1525 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
1526 fb_info = adev->dm.dmub_fb_info;
1527
1528 if (!fb_info) {
1529 DRM_ERROR(
1530 "Failed to allocate framebuffer info for DMUB service!\n");
1531 return -ENOMEM;
1532 }
1533
1534 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
1535 if (status != DMUB_STATUS_OK) {
1536 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
1537 return -EINVAL;
1538 }
1539
743b9786
NK		 1540 return 0;
1541}
1542
a94d5569
DF		 1543static int dm_sw_init(void *handle)
1544{
1545 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
743b9786
NK		 1546 int r;
1547
1548 r = dm_dmub_sw_init(adev);
1549 if (r)
1550 return r;
a94d5569
DF		 1551
1552 return load_dmcu_fw(adev);
1553}
1554
4562236b
HW		 1555static int dm_sw_fini(void *handle)
1556{
a94d5569
DF		 1557 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1558
8c7aea40
NK		 1559 kfree(adev->dm.dmub_fb_info);
1560 adev->dm.dmub_fb_info = NULL;
1561
743b9786
NK		 1562 if (adev->dm.dmub_srv) {
1563 dmub_srv_destroy(adev->dm.dmub_srv);
1564 adev->dm.dmub_srv = NULL;
1565 }
1566
75e1658e
ND		 1567 release_firmware(adev->dm.dmub_fw);
1568 adev->dm.dmub_fw = NULL;
743b9786 1569
75e1658e
ND		 1570 release_firmware(adev->dm.fw_dmcu);
1571 adev->dm.fw_dmcu = NULL;
a94d5569 1572
4562236b
HW		 1573 return 0;
1574}
1575
7abcf6b5 1576static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 1577{
c84dec2f 1578 struct amdgpu_dm_connector *aconnector;
4562236b 1579 struct drm_connector *connector;
f8d2d39e 1580 struct drm_connector_list_iter iter;
7abcf6b5 1581 int ret = 0;
4562236b 1582
f8d2d39e
LP		 1583 drm_connector_list_iter_begin(dev, &iter);
1584 drm_for_each_connector_iter(connector, &iter) {
b349f76e 1585 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 1586 if (aconnector->dc_link->type == dc_connection_mst_branch &&
1587 aconnector->mst_mgr.aux) {
f1ad2f5e 1588 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
f8d2d39e
LP		 1589 aconnector,
1590 aconnector->base.base.id);
7abcf6b5
AG		 1591
1592 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
1593 if (ret < 0) {
1594 DRM_ERROR("DM_MST: Failed to start MST\n");
f8d2d39e
LP		 1595 aconnector->dc_link->type =
1596 dc_connection_single;
1597 break;
7abcf6b5 1598 }
f8d2d39e 1599 }
4562236b 1600 }
f8d2d39e 1601 drm_connector_list_iter_end(&iter);
4562236b 1602
7abcf6b5
AG		 1603 return ret;
1604}
1605
1606static int dm_late_init(void *handle)
1607{
42e67c3b 1608 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 1609
bbf854dc
DF		 1610 struct dmcu_iram_parameters params;
1611 unsigned int linear_lut[16];
1612 int i;
17bdb4a8 1613 struct dmcu *dmcu = NULL;
5cb32419 1614 bool ret = true;
bbf854dc 1615
17bdb4a8
JFZ		 1616 dmcu = adev->dm.dc->res_pool->dmcu;
1617
bbf854dc
DF		 1618 for (i = 0; i < 16; i++)
1619 linear_lut[i] = 0xFFFF * i / 15;
1620
1621 params.set = 0;
1622 params.backlight_ramping_start = 0xCCCC;
1623 params.backlight_ramping_reduction = 0xCCCCCCCC;
1624 params.backlight_lut_array_size = 16;
1625 params.backlight_lut_array = linear_lut;
1626
2ad0cdf9
AK		 1627 /* Min backlight level after ABM reduction, Don't allow below 1%
1628 * 0xFFFF x 0.01 = 0x28F
1629 */
1630 params.min_abm_backlight = 0x28F;
1631
5cb32419
RL		 1632 /* In the case where abm is implemented on dmcub,
1633 * dmcu object will be null.
1634 * ABM 2.4 and up are implemented on dmcub.
1635 */
1636 if (dmcu)
1637 ret = dmcu_load_iram(dmcu, params);
1638 else if (adev->dm.dc->ctx->dmub_srv)
ecfe7569 1639 ret = dmub_init_abm_config(adev->dm.dc->res_pool, params);
bbf854dc 1640
14ed1c90
HW		 1641 if (!ret)
1642 return -EINVAL;
bbf854dc 1643
4a580877 1644 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
4562236b
HW		 1645}
1646
1647static void s3_handle_mst(struct drm_device *dev, bool suspend)
1648{
c84dec2f 1649 struct amdgpu_dm_connector *aconnector;
4562236b 1650 struct drm_connector *connector;
f8d2d39e 1651 struct drm_connector_list_iter iter;
fe7553be
LP		 1652 struct drm_dp_mst_topology_mgr *mgr;
1653 int ret;
1654 bool need_hotplug = false;
4562236b 1655
f8d2d39e
LP		 1656 drm_connector_list_iter_begin(dev, &iter);
1657 drm_for_each_connector_iter(connector, &iter) {
fe7553be
LP		 1658 aconnector = to_amdgpu_dm_connector(connector);
1659 if (aconnector->dc_link->type != dc_connection_mst_branch ||
1660 aconnector->mst_port)
1661 continue;
1662
1663 mgr = &aconnector->mst_mgr;
1664
1665 if (suspend) {
1666 drm_dp_mst_topology_mgr_suspend(mgr);
1667 } else {
6f85f738 1668 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
fe7553be
LP		 1669 if (ret < 0) {
1670 drm_dp_mst_topology_mgr_set_mst(mgr, false);
1671 need_hotplug = true;
1672 }
1673 }
4562236b 1674 }
f8d2d39e 1675 drm_connector_list_iter_end(&iter);
fe7553be
LP		 1676
1677 if (need_hotplug)
1678 drm_kms_helper_hotplug_event(dev);
4562236b
HW		 1679}
1680
9340dfd3
HW		 1681static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
1682{
1683 struct smu_context *smu = &adev->smu;
1684 int ret = 0;
1685
1686 if (!is_support_sw_smu(adev))
1687 return 0;
1688
1689 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
1690 * on window driver dc implementation.
1691 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
1692 * should be passed to smu during boot up and resume from s3.
1693 * boot up: dc calculate dcn watermark clock settings within dc_create,
1694 * dcn20_resource_construct
1695 * then call pplib functions below to pass the settings to smu:
1696 * smu_set_watermarks_for_clock_ranges
1697 * smu_set_watermarks_table
1698 * navi10_set_watermarks_table
1699 * smu_write_watermarks_table
1700 *
1701 * For Renoir, clock settings of dcn watermark are also fixed values.
1702 * dc has implemented different flow for window driver:
1703 * dc_hardware_init / dc_set_power_state
1704 * dcn10_init_hw
1705 * notify_wm_ranges
1706 * set_wm_ranges
1707 * -- Linux
1708 * smu_set_watermarks_for_clock_ranges
1709 * renoir_set_watermarks_table
1710 * smu_write_watermarks_table
1711 *
1712 * For Linux,
1713 * dc_hardware_init -> amdgpu_dm_init
1714 * dc_set_power_state --> dm_resume
1715 *
1716 * therefore, this function apply to navi10/12/14 but not Renoir
1717 * *
1718 */
1719 switch(adev->asic_type) {
1720 case CHIP_NAVI10:
1721 case CHIP_NAVI14:
1722 case CHIP_NAVI12:
1723 break;
1724 default:
1725 return 0;
1726 }
1727
e7a95eea
EQ		 1728 ret = smu_write_watermarks_table(smu);
1729 if (ret) {
1730 DRM_ERROR("Failed to update WMTABLE!\n");
1731 return ret;
9340dfd3
HW		 1732 }
1733
9340dfd3
HW		 1734 return 0;
1735}
1736
b8592b48
LL		 1737/**
1738 * dm_hw_init() - Initialize DC device
28d687ea 1739 * @handle: The base driver device containing the amdgpu_dm device.
b8592b48
LL		 1740 *
1741 * Initialize the &struct amdgpu_display_manager device. This involves calling
1742 * the initializers of each DM component, then populating the struct with them.
1743 *
1744 * Although the function implies hardware initialization, both hardware and
1745 * software are initialized here. Splitting them out to their relevant init
1746 * hooks is a future TODO item.
1747 *
1748 * Some notable things that are initialized here:
1749 *
1750 * - Display Core, both software and hardware
1751 * - DC modules that we need (freesync and color management)
1752 * - DRM software states
1753 * - Interrupt sources and handlers
1754 * - Vblank support
1755 * - Debug FS entries, if enabled
1756 */
4562236b
HW		 1757static int dm_hw_init(void *handle)
1758{
1759 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1760 /* Create DAL display manager */
1761 amdgpu_dm_init(adev);
4562236b
HW		 1762 amdgpu_dm_hpd_init(adev);
1763
4562236b
HW		 1764 return 0;
1765}
1766
b8592b48
LL		 1767/**
1768 * dm_hw_fini() - Teardown DC device
28d687ea 1769 * @handle: The base driver device containing the amdgpu_dm device.
b8592b48
LL		 1770 *
1771 * Teardown components within &struct amdgpu_display_manager that require
1772 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1773 * were loaded. Also flush IRQ workqueues and disable them.
1774 */
4562236b
HW		 1775static int dm_hw_fini(void *handle)
1776{
1777 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1778
1779 amdgpu_dm_hpd_fini(adev);
1780
1781 amdgpu_dm_irq_fini(adev);
21de3396 1782 amdgpu_dm_fini(adev);
4562236b
HW		 1783 return 0;
1784}
1785
cdaae837
BL		 1786
1787static int dm_enable_vblank(struct drm_crtc *crtc);
1788static void dm_disable_vblank(struct drm_crtc *crtc);
1789
1790static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
1791 struct dc_state *state, bool enable)
1792{
1793 enum dc_irq_source irq_source;
1794 struct amdgpu_crtc *acrtc;
1795 int rc = -EBUSY;
1796 int i = 0;
1797
1798 for (i = 0; i < state->stream_count; i++) {
1799 acrtc = get_crtc_by_otg_inst(
1800 adev, state->stream_status[i].primary_otg_inst);
1801
1802 if (acrtc && state->stream_status[i].plane_count != 0) {
1803 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
1804 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
1805 DRM_DEBUG("crtc %d - vupdate irq %sabling: r=%d\n",
1806 acrtc->crtc_id, enable ? "en" : "dis", rc);
1807 if (rc)
1808 DRM_WARN("Failed to %s pflip interrupts\n",
1809 enable ? "enable" : "disable");
1810
1811 if (enable) {
1812 rc = dm_enable_vblank(&acrtc->base);
1813 if (rc)
1814 DRM_WARN("Failed to enable vblank interrupts\n");
1815 } else {
1816 dm_disable_vblank(&acrtc->base);
1817 }
1818
1819 }
1820 }
1821
1822}
1823
dfd84d90 1824static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
cdaae837
BL		 1825{
1826 struct dc_state *context = NULL;
1827 enum dc_status res = DC_ERROR_UNEXPECTED;
1828 int i;
1829 struct dc_stream_state *del_streams[MAX_PIPES];
1830 int del_streams_count = 0;
1831
1832 memset(del_streams, 0, sizeof(del_streams));
1833
1834 context = dc_create_state(dc);
1835 if (context == NULL)
1836 goto context_alloc_fail;
1837
1838 dc_resource_state_copy_construct_current(dc, context);
1839
1840 /* First remove from context all streams */
1841 for (i = 0; i < context->stream_count; i++) {
1842 struct dc_stream_state *stream = context->streams[i];
1843
1844 del_streams[del_streams_count++] = stream;
1845 }
1846
1847 /* Remove all planes for removed streams and then remove the streams */
1848 for (i = 0; i < del_streams_count; i++) {
1849 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
1850 res = DC_FAIL_DETACH_SURFACES;
1851 goto fail;
1852 }
1853
1854 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
1855 if (res != DC_OK)
1856 goto fail;
1857 }
1858
1859
1860 res = dc_validate_global_state(dc, context, false);
1861
1862 if (res != DC_OK) {
1863 DRM_ERROR("%s:resource validation failed, dc_status:%d\n", __func__, res);
1864 goto fail;
1865 }
1866
1867 res = dc_commit_state(dc, context);
1868
1869fail:
1870 dc_release_state(context);
1871
1872context_alloc_fail:
1873 return res;
1874}
1875
4562236b
HW		 1876static int dm_suspend(void *handle)
1877{
1878 struct amdgpu_device *adev = handle;
1879 struct amdgpu_display_manager *dm = &adev->dm;
1880 int ret = 0;
4562236b 1881
53b3f8f4 1882 if (amdgpu_in_reset(adev)) {
cdaae837 1883 mutex_lock(&dm->dc_lock);
98ab5f35
BL		 1884
1885#if defined(CONFIG_DRM_AMD_DC_DCN)
1886 dc_allow_idle_optimizations(adev->dm.dc, false);
1887#endif
1888
cdaae837
BL		 1889 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
1890
1891 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
1892
1893 amdgpu_dm_commit_zero_streams(dm->dc);
1894
1895 amdgpu_dm_irq_suspend(adev);
1896
1897 return ret;
1898 }
4562236b 1899
9a65df19
WL		 1900#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
1901 amdgpu_dm_crtc_secure_display_suspend(adev);
1902#endif
d2f0b53b 1903 WARN_ON(adev->dm.cached_state);
4a580877 1904 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
d2f0b53b 1905
4a580877 1906 s3_handle_mst(adev_to_drm(adev), true);
4562236b 1907
4562236b
HW		 1908 amdgpu_dm_irq_suspend(adev);
1909
a3621485 1910
32f5062d 1911 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b 1912
1c2075d4 1913 return 0;
4562236b
HW		 1914}
1915
1daf8c63
AD		 1916static struct amdgpu_dm_connector *
1917amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1918 struct drm_crtc *crtc)
4562236b
HW		 1919{
1920 uint32_t i;
c2cea706 1921 struct drm_connector_state *new_con_state;
4562236b
HW		 1922 struct drm_connector *connector;
1923 struct drm_crtc *crtc_from_state;
1924
c2cea706
LSL		 1925 for_each_new_connector_in_state(state, connector, new_con_state, i) {
1926 crtc_from_state = new_con_state->crtc;
4562236b
HW		 1927
1928 if (crtc_from_state == crtc)
c84dec2f 1929 return to_amdgpu_dm_connector(connector);
4562236b
HW		 1930 }
1931
1932 return NULL;
1933}
1934
fbbdadf2
BL		 1935static void emulated_link_detect(struct dc_link *link)
1936{
1937 struct dc_sink_init_data sink_init_data = { 0 };
1938 struct display_sink_capability sink_caps = { 0 };
1939 enum dc_edid_status edid_status;
1940 struct dc_context *dc_ctx = link->ctx;
1941 struct dc_sink *sink = NULL;
1942 struct dc_sink *prev_sink = NULL;
1943
1944 link->type = dc_connection_none;
1945 prev_sink = link->local_sink;
1946
30164a16
VL		 1947 if (prev_sink)
1948 dc_sink_release(prev_sink);
fbbdadf2
BL		 1949
1950 switch (link->connector_signal) {
1951 case SIGNAL_TYPE_HDMI_TYPE_A: {
1952 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1953 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1954 break;
1955 }
1956
1957 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1958 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1959 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1960 break;
1961 }
1962
1963 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1964 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1965 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1966 break;
1967 }
1968
1969 case SIGNAL_TYPE_LVDS: {
1970 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1971 sink_caps.signal = SIGNAL_TYPE_LVDS;
1972 break;
1973 }
1974
1975 case SIGNAL_TYPE_EDP: {
1976 sink_caps.transaction_type =
1977 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1978 sink_caps.signal = SIGNAL_TYPE_EDP;
1979 break;
1980 }
1981
1982 case SIGNAL_TYPE_DISPLAY_PORT: {
1983 sink_caps.transaction_type =
1984 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1985 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1986 break;
1987 }
1988
1989 default:
1990 DC_ERROR("Invalid connector type! signal:%d\n",
1991 link->connector_signal);
1992 return;
1993 }
1994
1995 sink_init_data.link = link;
1996 sink_init_data.sink_signal = sink_caps.signal;
1997
1998 sink = dc_sink_create(&sink_init_data);
1999 if (!sink) {
2000 DC_ERROR("Failed to create sink!\n");
2001 return;
2002 }
2003
dcd5fb82 2004 /* dc_sink_create returns a new reference */
fbbdadf2
BL		 2005 link->local_sink = sink;
2006
2007 edid_status = dm_helpers_read_local_edid(
2008 link->ctx,
2009 link,
2010 sink);
2011
2012 if (edid_status != EDID_OK)
2013 DC_ERROR("Failed to read EDID");
2014
2015}
2016
cdaae837
BL		 2017static void dm_gpureset_commit_state(struct dc_state *dc_state,
2018 struct amdgpu_display_manager *dm)
2019{
2020 struct {
2021 struct dc_surface_update surface_updates[MAX_SURFACES];
2022 struct dc_plane_info plane_infos[MAX_SURFACES];
2023 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2024 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2025 struct dc_stream_update stream_update;
2026 } * bundle;
2027 int k, m;
2028
2029 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2030
2031 if (!bundle) {
2032 dm_error("Failed to allocate update bundle\n");
2033 goto cleanup;
2034 }
2035
2036 for (k = 0; k < dc_state->stream_count; k++) {
2037 bundle->stream_update.stream = dc_state->streams[k];
2038
2039 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2040 bundle->surface_updates[m].surface =
2041 dc_state->stream_status->plane_states[m];
2042 bundle->surface_updates[m].surface->force_full_update =
2043 true;
2044 }
2045 dc_commit_updates_for_stream(
2046 dm->dc, bundle->surface_updates,
2047 dc_state->stream_status->plane_count,
263a4feb 2048 dc_state->streams[k], &bundle->stream_update, dc_state);
cdaae837
BL		 2049 }
2050
2051cleanup:
2052 kfree(bundle);
2053
2054 return;
2055}
2056
3c4d55c9
AP		 2057static void dm_set_dpms_off(struct dc_link *link)
2058{
2059 struct dc_stream_state *stream_state;
2060 struct amdgpu_dm_connector *aconnector = link->priv;
2061 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
2062 struct dc_stream_update stream_update;
2063 bool dpms_off = true;
2064
2065 memset(&stream_update, 0, sizeof(stream_update));
2066 stream_update.dpms_off = &dpms_off;
2067
2068 mutex_lock(&adev->dm.dc_lock);
2069 stream_state = dc_stream_find_from_link(link);
2070
2071 if (stream_state == NULL) {
2072 DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n");
2073 mutex_unlock(&adev->dm.dc_lock);
2074 return;
2075 }
2076
2077 stream_update.stream = stream_state;
2078 dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0,
263a4feb
AJ		 2079 stream_state, &stream_update,
2080 stream_state->ctx->dc->current_state);
3c4d55c9
AP		 2081 mutex_unlock(&adev->dm.dc_lock);
2082}
2083
4562236b
HW		 2084static int dm_resume(void *handle)
2085{
2086 struct amdgpu_device *adev = handle;
4a580877 2087 struct drm_device *ddev = adev_to_drm(adev);
4562236b 2088 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 2089 struct amdgpu_dm_connector *aconnector;
4562236b 2090 struct drm_connector *connector;
f8d2d39e 2091 struct drm_connector_list_iter iter;
4562236b 2092 struct drm_crtc *crtc;
c2cea706 2093 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 2094 struct dm_crtc_state *dm_new_crtc_state;
2095 struct drm_plane *plane;
2096 struct drm_plane_state *new_plane_state;
2097 struct dm_plane_state *dm_new_plane_state;
113b7a01 2098 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
fbbdadf2 2099 enum dc_connection_type new_connection_type = dc_connection_none;
cdaae837
BL		 2100 struct dc_state *dc_state;
2101 int i, r, j;
4562236b 2102
53b3f8f4 2103 if (amdgpu_in_reset(adev)) {
cdaae837
BL		 2104 dc_state = dm->cached_dc_state;
2105
2106 r = dm_dmub_hw_init(adev);
2107 if (r)
2108 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2109
2110 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2111 dc_resume(dm->dc);
2112
2113 amdgpu_dm_irq_resume_early(adev);
2114
2115 for (i = 0; i < dc_state->stream_count; i++) {
2116 dc_state->streams[i]->mode_changed = true;
2117 for (j = 0; j < dc_state->stream_status->plane_count; j++) {
2118 dc_state->stream_status->plane_states[j]->update_flags.raw
2119 = 0xffffffff;
2120 }
2121 }
2122
2123 WARN_ON(!dc_commit_state(dm->dc, dc_state));
4562236b 2124
cdaae837
BL		 2125 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2126
2127 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2128
2129 dc_release_state(dm->cached_dc_state);
2130 dm->cached_dc_state = NULL;
2131
2132 amdgpu_dm_irq_resume_late(adev);
2133
2134 mutex_unlock(&dm->dc_lock);
2135
2136 return 0;
2137 }
113b7a01
LL		 2138 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2139 dc_release_state(dm_state->context);
2140 dm_state->context = dc_create_state(dm->dc);
2141 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2142 dc_resource_state_construct(dm->dc, dm_state->context);
2143
8c7aea40
NK		 2144 /* Before powering on DC we need to re-initialize DMUB. */
2145 r = dm_dmub_hw_init(adev);
2146 if (r)
2147 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2148
a80aa93d
ML		 2149 /* power on hardware */
2150 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2151
4562236b
HW		 2152 /* program HPD filter */
2153 dc_resume(dm->dc);
2154
4562236b
HW		 2155 /*
2156 * early enable HPD Rx IRQ, should be done before set mode as short
2157 * pulse interrupts are used for MST
2158 */
2159 amdgpu_dm_irq_resume_early(adev);
2160
d20ebea8 2161 /* On resume we need to rewrite the MSTM control bits to enable MST*/
684cd480
LP		 2162 s3_handle_mst(ddev, false);
2163
4562236b 2164 /* Do detection*/
f8d2d39e
LP		 2165 drm_connector_list_iter_begin(ddev, &iter);
2166 drm_for_each_connector_iter(connector, &iter) {
c84dec2f 2167 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 2168
2169 /*
2170 * this is the case when traversing through already created
2171 * MST connectors, should be skipped
2172 */
2173 if (aconnector->mst_port)
2174 continue;
2175
03ea364c 2176 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 2177 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2178 DRM_ERROR("KMS: Failed to detect connector\n");
2179
2180 if (aconnector->base.force && new_connection_type == dc_connection_none)
2181 emulated_link_detect(aconnector->dc_link);
2182 else
2183 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 2184
2185 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2186 aconnector->fake_enable = false;
2187
dcd5fb82
MF		 2188 if (aconnector->dc_sink)
2189 dc_sink_release(aconnector->dc_sink);
4562236b
HW		 2190 aconnector->dc_sink = NULL;
2191 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 2192 mutex_unlock(&aconnector->hpd_lock);
4562236b 2193 }
f8d2d39e 2194 drm_connector_list_iter_end(&iter);
4562236b 2195
1f6010a9 2196 /* Force mode set in atomic commit */
a80aa93d 2197 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 2198 new_crtc_state->active_changed = true;
4f346e65 2199
fcb4019e
LSL		 2200 /*
2201 * atomic_check is expected to create the dc states. We need to release
2202 * them here, since they were duplicated as part of the suspend
2203 * procedure.
2204 */
a80aa93d 2205 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 2206 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2207 if (dm_new_crtc_state->stream) {
2208 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2209 dc_stream_release(dm_new_crtc_state->stream);
2210 dm_new_crtc_state->stream = NULL;
2211 }
2212 }
2213
a80aa93d 2214 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 2215 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2216 if (dm_new_plane_state->dc_state) {
2217 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2218 dc_plane_state_release(dm_new_plane_state->dc_state);
2219 dm_new_plane_state->dc_state = NULL;
2220 }
2221 }
2222
2d1af6a1 2223 drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 2224
a80aa93d 2225 dm->cached_state = NULL;
0a214e2f 2226
9a65df19
WL		 2227#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
2228 amdgpu_dm_crtc_secure_display_resume(adev);
2229#endif
2230
9faa4237 2231 amdgpu_dm_irq_resume_late(adev);
4562236b 2232
9340dfd3
HW		 2233 amdgpu_dm_smu_write_watermarks_table(adev);
2234
2d1af6a1 2235 return 0;
4562236b
HW		 2236}
2237
b8592b48
LL		 2238/**
2239 * DOC: DM Lifecycle
2240 *
2241 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2242 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2243 * the base driver's device list to be initialized and torn down accordingly.
2244 *
2245 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2246 */
2247
4562236b
HW		 2248static const struct amd_ip_funcs amdgpu_dm_funcs = {
2249 .name = "dm",
2250 .early_init = dm_early_init,
7abcf6b5 2251 .late_init = dm_late_init,
4562236b
HW		 2252 .sw_init = dm_sw_init,
2253 .sw_fini = dm_sw_fini,
2254 .hw_init = dm_hw_init,
2255 .hw_fini = dm_hw_fini,
2256 .suspend = dm_suspend,
2257 .resume = dm_resume,
2258 .is_idle = dm_is_idle,
2259 .wait_for_idle = dm_wait_for_idle,
2260 .check_soft_reset = dm_check_soft_reset,
2261 .soft_reset = dm_soft_reset,
2262 .set_clockgating_state = dm_set_clockgating_state,
2263 .set_powergating_state = dm_set_powergating_state,
2264};
2265
2266const struct amdgpu_ip_block_version dm_ip_block =
2267{
2268 .type = AMD_IP_BLOCK_TYPE_DCE,
2269 .major = 1,
2270 .minor = 0,
2271 .rev = 0,
2272 .funcs = &amdgpu_dm_funcs,
2273};
2274
ca3268c4 2275
b8592b48
LL		 2276/**
2277 * DOC: atomic
2278 *
2279 * *WIP*
2280 */
0a323b84 2281
b3663f70 2282static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 2283 .fb_create = amdgpu_display_user_framebuffer_create,
dfbbfe3c 2284 .get_format_info = amd_get_format_info,
366c1baa 2285 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 2286 .atomic_check = amdgpu_dm_atomic_check,
0269764a 2287 .atomic_commit = drm_atomic_helper_commit,
54f5499a
AG		 2288};
2289
2290static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2291 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 2292};
2293
94562810
RS		 2294static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2295{
2296 u32 max_cll, min_cll, max, min, q, r;
2297 struct amdgpu_dm_backlight_caps *caps;
2298 struct amdgpu_display_manager *dm;
2299 struct drm_connector *conn_base;
2300 struct amdgpu_device *adev;
ec11fe37 2301 struct dc_link *link = NULL;
94562810
RS		 2302 static const u8 pre_computed_values[] = {
2303 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
2304 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};
2305
2306 if (!aconnector || !aconnector->dc_link)
2307 return;
2308
ec11fe37 2309 link = aconnector->dc_link;
2310 if (link->connector_signal != SIGNAL_TYPE_EDP)
2311 return;
2312
94562810 2313 conn_base = &aconnector->base;
1348969a 2314 adev = drm_to_adev(conn_base->dev);
94562810
RS		 2315 dm = &adev->dm;
2316 caps = &dm->backlight_caps;
2317 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2318 caps->aux_support = false;
2319 max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
2320 min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
2321
2322 if (caps->ext_caps->bits.oled == 1 ||
2323 caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2324 caps->ext_caps->bits.hdr_aux_backlight_control == 1)
2325 caps->aux_support = true;
2326
7c209847
TI		 2327 if (amdgpu_backlight == 0)
2328 caps->aux_support = false;
2329 else if (amdgpu_backlight == 1)
2330 caps->aux_support = true;
2331
94562810
RS		 2332 /* From the specification (CTA-861-G), for calculating the maximum
2333 * luminance we need to use:
2334 * Luminance = 50*2**(CV/32)
2335 * Where CV is a one-byte value.
2336 * For calculating this expression we may need float point precision;
2337 * to avoid this complexity level, we take advantage that CV is divided
2338 * by a constant. From the Euclids division algorithm, we know that CV
2339 * can be written as: CV = 32*q + r. Next, we replace CV in the
2340 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
2341 * need to pre-compute the value of r/32. For pre-computing the values
2342 * We just used the following Ruby line:
2343 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
2344 * The results of the above expressions can be verified at
2345 * pre_computed_values.
2346 */
2347 q = max_cll >> 5;
2348 r = max_cll % 32;
2349 max = (1 << q) * pre_computed_values[r];
2350
2351 // min luminance: maxLum * (CV/255)^2 / 100
2352 q = DIV_ROUND_CLOSEST(min_cll, 255);
2353 min = max * DIV_ROUND_CLOSEST((q * q), 100);
2354
2355 caps->aux_max_input_signal = max;
2356 caps->aux_min_input_signal = min;
2357}
2358
97e51c16
HW		 2359void amdgpu_dm_update_connector_after_detect(
2360 struct amdgpu_dm_connector *aconnector)
4562236b
HW		 2361{
2362 struct drm_connector *connector = &aconnector->base;
2363 struct drm_device *dev = connector->dev;
b73a22d3 2364 struct dc_sink *sink;
4562236b
HW		 2365
2366 /* MST handled by drm_mst framework */
2367 if (aconnector->mst_mgr.mst_state == true)
2368 return;
2369
4562236b 2370 sink = aconnector->dc_link->local_sink;
dcd5fb82
MF		 2371 if (sink)
2372 dc_sink_retain(sink);
4562236b 2373
1f6010a9
DF		 2374 /*
2375 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 2376 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 2377 * Skip if already done during boot.
4562236b
HW		 2378 */
2379 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2380 && aconnector->dc_em_sink) {
2381
1f6010a9
DF		 2382 /*
2383 * For S3 resume with headless use eml_sink to fake stream
2384 * because on resume connector->sink is set to NULL
4562236b
HW		 2385 */
2386 mutex_lock(&dev->mode_config.mutex);
2387
2388 if (sink) {
922aa1e1 2389 if (aconnector->dc_sink) {
98e6436d 2390 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 2391 /*
2392 * retain and release below are used to
2393 * bump up refcount for sink because the link doesn't point
2394 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 2395 * reshuffle by UMD we will get into unwanted dc_sink release
2396 */
dcd5fb82 2397 dc_sink_release(aconnector->dc_sink);
922aa1e1 2398 }
4562236b 2399 aconnector->dc_sink = sink;
dcd5fb82 2400 dc_sink_retain(aconnector->dc_sink);
98e6436d
AK		 2401 amdgpu_dm_update_freesync_caps(connector,
2402 aconnector->edid);
4562236b 2403 } else {
98e6436d 2404 amdgpu_dm_update_freesync_caps(connector, NULL);
dcd5fb82 2405 if (!aconnector->dc_sink) {
4562236b 2406 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1 2407 dc_sink_retain(aconnector->dc_sink);
dcd5fb82 2408 }
4562236b
HW		 2409 }
2410
2411 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 2412
2413 if (sink)
2414 dc_sink_release(sink);
4562236b
HW		 2415 return;
2416 }
2417
2418 /*
2419 * TODO: temporary guard to look for proper fix
2420 * if this sink is MST sink, we should not do anything
2421 */
dcd5fb82
MF		 2422 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2423 dc_sink_release(sink);
4562236b 2424 return;
dcd5fb82 2425 }
4562236b
HW		 2426
2427 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 2428 /*
2429 * We got a DP short pulse (Link Loss, DP CTS, etc...).
2430 * Do nothing!!
2431 */
f1ad2f5e 2432 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b 2433 aconnector->connector_id);
dcd5fb82
MF		 2434 if (sink)
2435 dc_sink_release(sink);
4562236b
HW		 2436 return;
2437 }
2438
f1ad2f5e 2439 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 2440 aconnector->connector_id, aconnector->dc_sink, sink);
2441
2442 mutex_lock(&dev->mode_config.mutex);
2443
1f6010a9
DF		 2444 /*
2445 * 1. Update status of the drm connector
2446 * 2. Send an event and let userspace tell us what to do
2447 */
4562236b 2448 if (sink) {
1f6010a9
DF		 2449 /*
2450 * TODO: check if we still need the S3 mode update workaround.
2451 * If yes, put it here.
2452 */
c64b0d6b 2453 if (aconnector->dc_sink) {
98e6436d 2454 amdgpu_dm_update_freesync_caps(connector, NULL);
c64b0d6b
VL		 2455 dc_sink_release(aconnector->dc_sink);
2456 }
4562236b
HW		 2457
2458 aconnector->dc_sink = sink;
dcd5fb82 2459 dc_sink_retain(aconnector->dc_sink);
900b3cb1 2460 if (sink->dc_edid.length == 0) {
4562236b 2461 aconnector->edid = NULL;
e6142dd5
AP		 2462 if (aconnector->dc_link->aux_mode) {
2463 drm_dp_cec_unset_edid(
2464 &aconnector->dm_dp_aux.aux);
2465 }
900b3cb1 2466 } else {
4562236b 2467 aconnector->edid =
e6142dd5 2468 (struct edid *)sink->dc_edid.raw_edid;
4562236b 2469
c555f023 2470 drm_connector_update_edid_property(connector,
e6142dd5 2471 aconnector->edid);
e6142dd5
AP		 2472 if (aconnector->dc_link->aux_mode)
2473 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
2474 aconnector->edid);
4562236b 2475 }
e6142dd5 2476
98e6436d 2477 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
94562810 2478 update_connector_ext_caps(aconnector);
4562236b 2479 } else {
e86e8947 2480 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 2481 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 2482 drm_connector_update_edid_property(connector, NULL);
4562236b 2483 aconnector->num_modes = 0;
dcd5fb82 2484 dc_sink_release(aconnector->dc_sink);
4562236b 2485 aconnector->dc_sink = NULL;
5326c452 2486 aconnector->edid = NULL;
0c8620d6
BL		 2487#ifdef CONFIG_DRM_AMD_DC_HDCP
2488 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
2489 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
2490 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
2491#endif
4562236b
HW		 2492 }
2493
2494 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82 2495
0f877894
OV		 2496 update_subconnector_property(aconnector);
2497
dcd5fb82
MF		 2498 if (sink)
2499 dc_sink_release(sink);
4562236b
HW		 2500}
2501
2502static void handle_hpd_irq(void *param)
2503{
c84dec2f 2504 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 2505 struct drm_connector *connector = &aconnector->base;
2506 struct drm_device *dev = connector->dev;
fbbdadf2 2507 enum dc_connection_type new_connection_type = dc_connection_none;
0c8620d6 2508#ifdef CONFIG_DRM_AMD_DC_HDCP
1348969a 2509 struct amdgpu_device *adev = drm_to_adev(dev);
97f6c917 2510 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
0c8620d6 2511#endif
4562236b 2512
1f6010a9
DF		 2513 /*
2514 * In case of failure or MST no need to update connector status or notify the OS
2515 * since (for MST case) MST does this in its own context.
4562236b
HW		 2516 */
2517 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6 2518
0c8620d6 2519#ifdef CONFIG_DRM_AMD_DC_HDCP
97f6c917 2520 if (adev->dm.hdcp_workqueue) {
96a3b32e 2521 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
97f6c917
BL		 2522 dm_con_state->update_hdcp = true;
2523 }
0c8620d6 2524#endif
2e0ac3d6
HW		 2525 if (aconnector->fake_enable)
2526 aconnector->fake_enable = false;
2527
fbbdadf2
BL		 2528 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2529 DRM_ERROR("KMS: Failed to detect connector\n");
2530
2531 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2532 emulated_link_detect(aconnector->dc_link);
2533
2534
2535 drm_modeset_lock_all(dev);
2536 dm_restore_drm_connector_state(dev, connector);
2537 drm_modeset_unlock_all(dev);
2538
2539 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2540 drm_kms_helper_hotplug_event(dev);
2541
2542 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
3c4d55c9
AP		 2543 if (new_connection_type == dc_connection_none &&
2544 aconnector->dc_link->type == dc_connection_none)
2545 dm_set_dpms_off(aconnector->dc_link);
4562236b 2546
3c4d55c9 2547 amdgpu_dm_update_connector_after_detect(aconnector);
4562236b
HW		 2548
2549 drm_modeset_lock_all(dev);
2550 dm_restore_drm_connector_state(dev, connector);
2551 drm_modeset_unlock_all(dev);
2552
2553 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2554 drm_kms_helper_hotplug_event(dev);
2555 }
2556 mutex_unlock(&aconnector->hpd_lock);
2557
2558}
2559
c84dec2f 2560static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 2561{
2562 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
2563 uint8_t dret;
2564 bool new_irq_handled = false;
2565 int dpcd_addr;
2566 int dpcd_bytes_to_read;
2567
2568 const int max_process_count = 30;
2569 int process_count = 0;
2570
2571 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
2572
2573 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
2574 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
2575 /* DPCD 0x200 - 0x201 for downstream IRQ */
2576 dpcd_addr = DP_SINK_COUNT;
2577 } else {
2578 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
2579 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
2580 dpcd_addr = DP_SINK_COUNT_ESI;
2581 }
2582
2583 dret = drm_dp_dpcd_read(
2584 &aconnector->dm_dp_aux.aux,
2585 dpcd_addr,
2586 esi,
2587 dpcd_bytes_to_read);
2588
2589 while (dret == dpcd_bytes_to_read &&
2590 process_count < max_process_count) {
2591 uint8_t retry;
2592 dret = 0;
2593
2594 process_count++;
2595
f1ad2f5e 2596 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 2597 /* handle HPD short pulse irq */
2598 if (aconnector->mst_mgr.mst_state)
2599 drm_dp_mst_hpd_irq(
2600 &aconnector->mst_mgr,
2601 esi,
2602 &new_irq_handled);
4562236b
HW		 2603
2604 if (new_irq_handled) {
2605 /* ACK at DPCD to notify down stream */
2606 const int ack_dpcd_bytes_to_write =
2607 dpcd_bytes_to_read - 1;
2608
2609 for (retry = 0; retry < 3; retry++) {
2610 uint8_t wret;
2611
2612 wret = drm_dp_dpcd_write(
2613 &aconnector->dm_dp_aux.aux,
2614 dpcd_addr + 1,
2615 &esi[1],
2616 ack_dpcd_bytes_to_write);
2617 if (wret == ack_dpcd_bytes_to_write)
2618 break;
2619 }
2620
1f6010a9 2621 /* check if there is new irq to be handled */
4562236b
HW		 2622 dret = drm_dp_dpcd_read(
2623 &aconnector->dm_dp_aux.aux,
2624 dpcd_addr,
2625 esi,
2626 dpcd_bytes_to_read);
2627
2628 new_irq_handled = false;
d4a6e8a9 2629 } else {
4562236b 2630 break;
d4a6e8a9 2631 }
4562236b
HW		 2632 }
2633
2634 if (process_count == max_process_count)
f1ad2f5e 2635 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 2636}
2637
2638static void handle_hpd_rx_irq(void *param)
2639{
c84dec2f 2640 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 2641 struct drm_connector *connector = &aconnector->base;
2642 struct drm_device *dev = connector->dev;
53cbf65c 2643 struct dc_link *dc_link = aconnector->dc_link;
4562236b 2644 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
c8ea79a8 2645 bool result = false;
fbbdadf2 2646 enum dc_connection_type new_connection_type = dc_connection_none;
c8ea79a8 2647 struct amdgpu_device *adev = drm_to_adev(dev);
2a0f9270 2648 union hpd_irq_data hpd_irq_data;
2a0f9270
BL		 2649
2650 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
4562236b 2651
1f6010a9
DF		 2652 /*
2653 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 2654 * conflict, after implement i2c helper, this mutex should be
2655 * retired.
2656 */
53cbf65c 2657 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 2658 mutex_lock(&aconnector->hpd_lock);
2659
3083a984
QZ		 2660 read_hpd_rx_irq_data(dc_link, &hpd_irq_data);
2661
2662 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2663 (dc_link->type == dc_connection_mst_branch)) {
2664 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY) {
2665 result = true;
2666 dm_handle_hpd_rx_irq(aconnector);
2667 goto out;
2668 } else if (hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
2669 result = false;
2670 dm_handle_hpd_rx_irq(aconnector);
2671 goto out;
2672 }
2673 }
2674
c8ea79a8 2675 mutex_lock(&adev->dm.dc_lock);
2a0f9270 2676#ifdef CONFIG_DRM_AMD_DC_HDCP
c8ea79a8 2677 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL);
2a0f9270 2678#else
c8ea79a8 2679 result = dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL);
2a0f9270 2680#endif
c8ea79a8
QZ		 2681 mutex_unlock(&adev->dm.dc_lock);
2682
3083a984 2683out:
c8ea79a8 2684 if (result && !is_mst_root_connector) {
4562236b 2685 /* Downstream Port status changed. */
fbbdadf2
BL		 2686 if (!dc_link_detect_sink(dc_link, &new_connection_type))
2687 DRM_ERROR("KMS: Failed to detect connector\n");
2688
2689 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2690 emulated_link_detect(dc_link);
2691
2692 if (aconnector->fake_enable)
2693 aconnector->fake_enable = false;
2694
2695 amdgpu_dm_update_connector_after_detect(aconnector);
2696
2697
2698 drm_modeset_lock_all(dev);
2699 dm_restore_drm_connector_state(dev, connector);
2700 drm_modeset_unlock_all(dev);
2701
2702 drm_kms_helper_hotplug_event(dev);
2703 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 2704
2705 if (aconnector->fake_enable)
2706 aconnector->fake_enable = false;
2707
4562236b
HW		 2708 amdgpu_dm_update_connector_after_detect(aconnector);
2709
2710
2711 drm_modeset_lock_all(dev);
2712 dm_restore_drm_connector_state(dev, connector);
2713 drm_modeset_unlock_all(dev);
2714
2715 drm_kms_helper_hotplug_event(dev);
2716 }
2717 }
2a0f9270 2718#ifdef CONFIG_DRM_AMD_DC_HDCP
95f247e7
DC		 2719 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
2720 if (adev->dm.hdcp_workqueue)
2721 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
2722 }
2a0f9270 2723#endif
4562236b 2724
e86e8947
HV		 2725 if (dc_link->type != dc_connection_mst_branch) {
2726 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 2727 mutex_unlock(&aconnector->hpd_lock);
e86e8947 2728 }
4562236b
HW		 2729}
2730
2731static void register_hpd_handlers(struct amdgpu_device *adev)
2732{
4a580877 2733 struct drm_device *dev = adev_to_drm(adev);
4562236b 2734 struct drm_connector *connector;
c84dec2f 2735 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 2736 const struct dc_link *dc_link;
2737 struct dc_interrupt_params int_params = {0};
2738
2739 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2740 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2741
2742 list_for_each_entry(connector,
2743 &dev->mode_config.connector_list, head) {
2744
c84dec2f 2745 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 2746 dc_link = aconnector->dc_link;
2747
2748 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
2749 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2750 int_params.irq_source = dc_link->irq_source_hpd;
2751
2752 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2753 handle_hpd_irq,
2754 (void *) aconnector);
2755 }
2756
2757 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
2758
2759 /* Also register for DP short pulse (hpd_rx). */
2760 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2761 int_params.irq_source = dc_link->irq_source_hpd_rx;
2762
2763 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2764 handle_hpd_rx_irq,
2765 (void *) aconnector);
2766 }
2767 }
2768}
2769
55e56389
MR		 2770#if defined(CONFIG_DRM_AMD_DC_SI)
2771/* Register IRQ sources and initialize IRQ callbacks */
2772static int dce60_register_irq_handlers(struct amdgpu_device *adev)
2773{
2774 struct dc *dc = adev->dm.dc;
2775 struct common_irq_params *c_irq_params;
2776 struct dc_interrupt_params int_params = {0};
2777 int r;
2778 int i;
2779 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2780
2781 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2782 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2783
2784 /*
2785 * Actions of amdgpu_irq_add_id():
2786 * 1. Register a set() function with base driver.
2787 * Base driver will call set() function to enable/disable an
2788 * interrupt in DC hardware.
2789 * 2. Register amdgpu_dm_irq_handler().
2790 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2791 * coming from DC hardware.
2792 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2793 * for acknowledging and handling. */
2794
2795 /* Use VBLANK interrupt */
2796 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2797 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
2798 if (r) {
2799 DRM_ERROR("Failed to add crtc irq id!\n");
2800 return r;
2801 }
2802
2803 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2804 int_params.irq_source =
2805 dc_interrupt_to_irq_source(dc, i+1 , 0);
2806
2807 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2808
2809 c_irq_params->adev = adev;
2810 c_irq_params->irq_src = int_params.irq_source;
2811
2812 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2813 dm_crtc_high_irq, c_irq_params);
2814 }
2815
2816 /* Use GRPH_PFLIP interrupt */
2817 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2818 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2819 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
2820 if (r) {
2821 DRM_ERROR("Failed to add page flip irq id!\n");
2822 return r;
2823 }
2824
2825 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2826 int_params.irq_source =
2827 dc_interrupt_to_irq_source(dc, i, 0);
2828
2829 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2830
2831 c_irq_params->adev = adev;
2832 c_irq_params->irq_src = int_params.irq_source;
2833
2834 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2835 dm_pflip_high_irq, c_irq_params);
2836
2837 }
2838
2839 /* HPD */
2840 r = amdgpu_irq_add_id(adev, client_id,
2841 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2842 if (r) {
2843 DRM_ERROR("Failed to add hpd irq id!\n");
2844 return r;
2845 }
2846
2847 register_hpd_handlers(adev);
2848
2849 return 0;
2850}
2851#endif
2852
4562236b
HW		 2853/* Register IRQ sources and initialize IRQ callbacks */
2854static int dce110_register_irq_handlers(struct amdgpu_device *adev)
2855{
2856 struct dc *dc = adev->dm.dc;
2857 struct common_irq_params *c_irq_params;
2858 struct dc_interrupt_params int_params = {0};
2859 int r;
2860 int i;
1ffdeca6 2861 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 2862
84374725 2863 if (adev->asic_type >= CHIP_VEGA10)
3760f76c 2864 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 2865
2866 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2867 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2868
1f6010a9
DF		 2869 /*
2870 * Actions of amdgpu_irq_add_id():
4562236b
HW		 2871 * 1. Register a set() function with base driver.
2872 * Base driver will call set() function to enable/disable an
2873 * interrupt in DC hardware.
2874 * 2. Register amdgpu_dm_irq_handler().
2875 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2876 * coming from DC hardware.
2877 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2878 * for acknowledging and handling. */
2879
b57de80a 2880 /* Use VBLANK interrupt */
e9029155 2881 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 2882 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 2883 if (r) {
2884 DRM_ERROR("Failed to add crtc irq id!\n");
2885 return r;
2886 }
2887
2888 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2889 int_params.irq_source =
3d761e79 2890 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 2891
b57de80a 2892 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 2893
2894 c_irq_params->adev = adev;
2895 c_irq_params->irq_src = int_params.irq_source;
2896
2897 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2898 dm_crtc_high_irq, c_irq_params);
2899 }
2900
d2574c33
MK		 2901 /* Use VUPDATE interrupt */
2902 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
2903 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
2904 if (r) {
2905 DRM_ERROR("Failed to add vupdate irq id!\n");
2906 return r;
2907 }
2908
2909 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2910 int_params.irq_source =
2911 dc_interrupt_to_irq_source(dc, i, 0);
2912
2913 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
2914
2915 c_irq_params->adev = adev;
2916 c_irq_params->irq_src = int_params.irq_source;
2917
2918 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2919 dm_vupdate_high_irq, c_irq_params);
2920 }
2921
3d761e79 2922 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 2923 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2924 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 2925 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 2926 if (r) {
2927 DRM_ERROR("Failed to add page flip irq id!\n");
2928 return r;
2929 }
2930
2931 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2932 int_params.irq_source =
2933 dc_interrupt_to_irq_source(dc, i, 0);
2934
2935 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2936
2937 c_irq_params->adev = adev;
2938 c_irq_params->irq_src = int_params.irq_source;
2939
2940 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2941 dm_pflip_high_irq, c_irq_params);
2942
2943 }
2944
2945 /* HPD */
2c8ad2d5
AD		 2946 r = amdgpu_irq_add_id(adev, client_id,
2947 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 2948 if (r) {
2949 DRM_ERROR("Failed to add hpd irq id!\n");
2950 return r;
2951 }
2952
2953 register_hpd_handlers(adev);
2954
2955 return 0;
2956}
2957
b86a1aa3 2958#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD		 2959/* Register IRQ sources and initialize IRQ callbacks */
2960static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
2961{
2962 struct dc *dc = adev->dm.dc;
2963 struct common_irq_params *c_irq_params;
2964 struct dc_interrupt_params int_params = {0};
2965 int r;
2966 int i;
2967
2968 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2969 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2970
1f6010a9
DF		 2971 /*
2972 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 2973 * 1. Register a set() function with base driver.
2974 * Base driver will call set() function to enable/disable an
2975 * interrupt in DC hardware.
2976 * 2. Register amdgpu_dm_irq_handler().
2977 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2978 * coming from DC hardware.
2979 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2980 * for acknowledging and handling.
1f6010a9 2981 */
ff5ef992
AD		 2982
2983 /* Use VSTARTUP interrupt */
2984 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
2985 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
2986 i++) {
3760f76c 2987 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 2988
2989 if (r) {
2990 DRM_ERROR("Failed to add crtc irq id!\n");
2991 return r;
2992 }
2993
2994 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2995 int_params.irq_source =
2996 dc_interrupt_to_irq_source(dc, i, 0);
2997
2998 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2999
3000 c_irq_params->adev = adev;
3001 c_irq_params->irq_src = int_params.irq_source;
3002
2346ef47
NK		 3003 amdgpu_dm_irq_register_interrupt(
3004 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3005 }
3006
86bc2219
WL		 3007 /* Use otg vertical line interrupt */
3008#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3009 for (i = DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL;
3010 i <= DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL
3011 + adev->mode_info.num_crtc - 1;
3012 i++) {
3013 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vline0_irq);
3014
3015 if (r) {
3016 DRM_ERROR("Failed to add vline0 irq id!\n");
3017 return r;
3018 }
3019
3020 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3021 int_params.irq_source =
3022 dc_interrupt_to_irq_source(dc, i, 0);
3023
3024 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3025 - DC_IRQ_SOURCE_DC1_VLINE0];
3026
3027 c_irq_params->adev = adev;
3028 c_irq_params->irq_src = int_params.irq_source;
3029
3030 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3031 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3032 }
3033#endif
3034
2346ef47
NK		 3035 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3036 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3037 * to trigger at end of each vblank, regardless of state of the lock,
3038 * matching DCE behaviour.
3039 */
3040 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3041 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3042 i++) {
3043 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3044
3045 if (r) {
3046 DRM_ERROR("Failed to add vupdate irq id!\n");
3047 return r;
3048 }
3049
3050 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3051 int_params.irq_source =
3052 dc_interrupt_to_irq_source(dc, i, 0);
3053
3054 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3055
3056 c_irq_params->adev = adev;
3057 c_irq_params->irq_src = int_params.irq_source;
3058
ff5ef992 3059 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2346ef47 3060 dm_vupdate_high_irq, c_irq_params);
d2574c33
MK		 3061 }
3062
ff5ef992
AD		 3063 /* Use GRPH_PFLIP interrupt */
3064 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3065 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
3066 i++) {
3760f76c 3067 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 3068 if (r) {
3069 DRM_ERROR("Failed to add page flip irq id!\n");
3070 return r;
3071 }
3072
3073 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3074 int_params.irq_source =
3075 dc_interrupt_to_irq_source(dc, i, 0);
3076
3077 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3078
3079 c_irq_params->adev = adev;
3080 c_irq_params->irq_src = int_params.irq_source;
3081
3082 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3083 dm_pflip_high_irq, c_irq_params);
3084
3085 }
3086
3087 /* HPD */
3760f76c 3088 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 3089 &adev->hpd_irq);
3090 if (r) {
3091 DRM_ERROR("Failed to add hpd irq id!\n");
3092 return r;
3093 }
3094
3095 register_hpd_handlers(adev);
3096
3097 return 0;
3098}
3099#endif
3100
eb3dc897
NK		 3101/*
3102 * Acquires the lock for the atomic state object and returns
3103 * the new atomic state.
3104 *
3105 * This should only be called during atomic check.
3106 */
3107static int dm_atomic_get_state(struct drm_atomic_state *state,
3108 struct dm_atomic_state **dm_state)
3109{
3110 struct drm_device *dev = state->dev;
1348969a 3111 struct amdgpu_device *adev = drm_to_adev(dev);
eb3dc897
NK		 3112 struct amdgpu_display_manager *dm = &adev->dm;
3113 struct drm_private_state *priv_state;
eb3dc897
NK		 3114
3115 if (*dm_state)
3116 return 0;
3117
eb3dc897
NK		 3118 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3119 if (IS_ERR(priv_state))
3120 return PTR_ERR(priv_state);
3121
3122 *dm_state = to_dm_atomic_state(priv_state);
3123
3124 return 0;
3125}
3126
dfd84d90 3127static struct dm_atomic_state *
eb3dc897
NK		 3128dm_atomic_get_new_state(struct drm_atomic_state *state)
3129{
3130 struct drm_device *dev = state->dev;
1348969a 3131 struct amdgpu_device *adev = drm_to_adev(dev);
eb3dc897
NK		 3132 struct amdgpu_display_manager *dm = &adev->dm;
3133 struct drm_private_obj *obj;
3134 struct drm_private_state *new_obj_state;
3135 int i;
3136
3137 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3138 if (obj->funcs == dm->atomic_obj.funcs)
3139 return to_dm_atomic_state(new_obj_state);
3140 }
3141
3142 return NULL;
3143}
3144
eb3dc897
NK		 3145static struct drm_private_state *
3146dm_atomic_duplicate_state(struct drm_private_obj *obj)
3147{
3148 struct dm_atomic_state *old_state, *new_state;
3149
3150 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3151 if (!new_state)
3152 return NULL;
3153
3154 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3155
813d20dc
AW		 3156 old_state = to_dm_atomic_state(obj->state);
3157
3158 if (old_state && old_state->context)
3159 new_state->context = dc_copy_state(old_state->context);
3160
eb3dc897
NK		 3161 if (!new_state->context) {
3162 kfree(new_state);
3163 return NULL;
3164 }
3165
eb3dc897
NK		 3166 return &new_state->base;
3167}
3168
3169static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3170 struct drm_private_state *state)
3171{
3172 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3173
3174 if (dm_state && dm_state->context)
3175 dc_release_state(dm_state->context);
3176
3177 kfree(dm_state);
3178}
3179
3180static struct drm_private_state_funcs dm_atomic_state_funcs = {
3181 .atomic_duplicate_state = dm_atomic_duplicate_state,
3182 .atomic_destroy_state = dm_atomic_destroy_state,
3183};
3184
4562236b
HW		 3185static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3186{
eb3dc897 3187 struct dm_atomic_state *state;
4562236b
HW		 3188 int r;
3189
3190 adev->mode_info.mode_config_initialized = true;
3191
4a580877
LT		 3192 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3193 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b 3194
4a580877
LT		 3195 adev_to_drm(adev)->mode_config.max_width = 16384;
3196 adev_to_drm(adev)->mode_config.max_height = 16384;
4562236b 3197
4a580877
LT		 3198 adev_to_drm(adev)->mode_config.preferred_depth = 24;
3199 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
1f6010a9 3200 /* indicates support for immediate flip */
4a580877 3201 adev_to_drm(adev)->mode_config.async_page_flip = true;
4562236b 3202
4a580877 3203 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
4562236b 3204
eb3dc897
NK		 3205 state = kzalloc(sizeof(*state), GFP_KERNEL);
3206 if (!state)
3207 return -ENOMEM;
3208
813d20dc 3209 state->context = dc_create_state(adev->dm.dc);
eb3dc897
NK		 3210 if (!state->context) {
3211 kfree(state);
3212 return -ENOMEM;
3213 }
3214
3215 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3216
4a580877 3217 drm_atomic_private_obj_init(adev_to_drm(adev),
8c1a765b 3218 &adev->dm.atomic_obj,
eb3dc897
NK		 3219 &state->base,
3220 &dm_atomic_state_funcs);
3221
3dc9b1ce 3222 r = amdgpu_display_modeset_create_props(adev);
b67a468a
DL		 3223 if (r) {
3224 dc_release_state(state->context);
3225 kfree(state);
4562236b 3226 return r;
b67a468a 3227 }
4562236b 3228
6ce8f316 3229 r = amdgpu_dm_audio_init(adev);
b67a468a
DL		 3230 if (r) {
3231 dc_release_state(state->context);
3232 kfree(state);
6ce8f316 3233 return r;
b67a468a 3234 }
6ce8f316 3235
4562236b
HW		 3236 return 0;
3237}
3238
206bbafe
DF		 3239#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3240#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
94562810 3241#define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
206bbafe 3242
4562236b
HW		 3243#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3244 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3245
206bbafe
DF		 3246static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
3247{
3248#if defined(CONFIG_ACPI)
3249 struct amdgpu_dm_backlight_caps caps;
3250
58965855
FS		 3251 memset(&caps, 0, sizeof(caps));
3252
206bbafe
DF		 3253 if (dm->backlight_caps.caps_valid)
3254 return;
3255
3256 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
3257 if (caps.caps_valid) {
94562810
RS		 3258 dm->backlight_caps.caps_valid = true;
3259 if (caps.aux_support)
3260 return;
206bbafe
DF		 3261 dm->backlight_caps.min_input_signal = caps.min_input_signal;
3262 dm->backlight_caps.max_input_signal = caps.max_input_signal;
206bbafe
DF		 3263 } else {
3264 dm->backlight_caps.min_input_signal =
3265 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3266 dm->backlight_caps.max_input_signal =
3267 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3268 }
3269#else
94562810
RS		 3270 if (dm->backlight_caps.aux_support)
3271 return;
3272
8bcbc9ef
DF		 3273 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3274 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 3275#endif
3276}
3277
69d9f427
AM		 3278static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3279 unsigned *min, unsigned *max)
94562810 3280{
94562810 3281 if (!caps)
69d9f427 3282 return 0;
94562810 3283
69d9f427
AM		 3284 if (caps->aux_support) {
3285 // Firmware limits are in nits, DC API wants millinits.
3286 *max = 1000 * caps->aux_max_input_signal;
3287 *min = 1000 * caps->aux_min_input_signal;
94562810 3288 } else {
69d9f427
AM		 3289 // Firmware limits are 8-bit, PWM control is 16-bit.
3290 *max = 0x101 * caps->max_input_signal;
3291 *min = 0x101 * caps->min_input_signal;
94562810 3292 }
69d9f427
AM		 3293 return 1;
3294}
94562810 3295
69d9f427
AM		 3296static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3297 uint32_t brightness)
3298{
3299 unsigned min, max;
94562810 3300
69d9f427
AM		 3301 if (!get_brightness_range(caps, &min, &max))
3302 return brightness;
3303
3304 // Rescale 0..255 to min..max
3305 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3306 AMDGPU_MAX_BL_LEVEL);
3307}
3308
3309static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3310 uint32_t brightness)
3311{
3312 unsigned min, max;
3313
3314 if (!get_brightness_range(caps, &min, &max))
3315 return brightness;
3316
3317 if (brightness < min)
3318 return 0;
3319 // Rescale min..max to 0..255
3320 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3321 max - min);
94562810
RS		 3322}
3323
4562236b
HW		 3324static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
3325{
3326 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe 3327 struct amdgpu_dm_backlight_caps caps;
94562810
RS		 3328 struct dc_link *link = NULL;
3329 u32 brightness;
3330 bool rc;
4562236b 3331
206bbafe
DF		 3332 amdgpu_dm_update_backlight_caps(dm);
3333 caps = dm->backlight_caps;
94562810
RS		 3334
3335 link = (struct dc_link *)dm->backlight_link;
3336
69d9f427 3337 brightness = convert_brightness_from_user(&caps, bd->props.brightness);
94562810
RS		 3338 // Change brightness based on AUX property
3339 if (caps.aux_support)
3c8e99cc
AD		 3340 rc = dc_link_set_backlight_level_nits(link, true, brightness,
3341 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
3342 else
3343 rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0);
94562810
RS		 3344
3345 return rc ? 0 : 1;
4562236b
HW		 3346}
3347
3348static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
3349{
620a0d27 3350 struct amdgpu_display_manager *dm = bl_get_data(bd);
f275e875
AD		 3351 struct amdgpu_dm_backlight_caps caps;
3352
3353 amdgpu_dm_update_backlight_caps(dm);
3354 caps = dm->backlight_caps;
620a0d27 3355
f275e875
AD		 3356 if (caps.aux_support) {
3357 struct dc_link *link = (struct dc_link *)dm->backlight_link;
3358 u32 avg, peak;
3359 bool rc;
3360
3361 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
3362 if (!rc)
3363 return bd->props.brightness;
3364 return convert_brightness_to_user(&caps, avg);
3365 } else {
3366 int ret = dc_link_get_backlight_level(dm->backlight_link);
3367
3368 if (ret == DC_ERROR_UNEXPECTED)
3369 return bd->props.brightness;
3370 return convert_brightness_to_user(&caps, ret);
3371 }
4562236b
HW		 3372}
3373
3374static const struct backlight_ops amdgpu_dm_backlight_ops = {
bb264220 3375 .options = BL_CORE_SUSPENDRESUME,
4562236b
HW		 3376 .get_brightness = amdgpu_dm_backlight_get_brightness,
3377 .update_status = amdgpu_dm_backlight_update_status,
3378};
3379
7578ecda
AD		 3380static void
3381amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 3382{
3383 char bl_name[16];
3384 struct backlight_properties props = { 0 };
3385
206bbafe
DF		 3386 amdgpu_dm_update_backlight_caps(dm);
3387
4562236b 3388 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 3389 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 3390 props.type = BACKLIGHT_RAW;
3391
3392 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4a580877 3393 adev_to_drm(dm->adev)->primary->index);
4562236b
HW		 3394
3395 dm->backlight_dev = backlight_device_register(bl_name,
4a580877
LT		 3396 adev_to_drm(dm->adev)->dev,
3397 dm,
3398 &amdgpu_dm_backlight_ops,
3399 &props);
4562236b 3400
74baea42 3401 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 3402 DRM_ERROR("DM: Backlight registration failed!\n");
3403 else
f1ad2f5e 3404 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 3405}
3406
3407#endif
3408
df534fff 3409static int initialize_plane(struct amdgpu_display_manager *dm,
b2fddb13 3410 struct amdgpu_mode_info *mode_info, int plane_id,
cc1fec57
NK		 3411 enum drm_plane_type plane_type,
3412 const struct dc_plane_cap *plane_cap)
df534fff 3413{
f180b4bc 3414 struct drm_plane *plane;
df534fff
S		 3415 unsigned long possible_crtcs;
3416 int ret = 0;
3417
f180b4bc 3418 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 3419 if (!plane) {
3420 DRM_ERROR("KMS: Failed to allocate plane\n");
3421 return -ENOMEM;
3422 }
b2fddb13 3423 plane->type = plane_type;
df534fff
S		 3424
3425 /*
b2fddb13
NK		 3426 * HACK: IGT tests expect that the primary plane for a CRTC
3427 * can only have one possible CRTC. Only expose support for
3428 * any CRTC if they're not going to be used as a primary plane
3429 * for a CRTC - like overlay or underlay planes.
df534fff
S		 3430 */
3431 possible_crtcs = 1 << plane_id;
3432 if (plane_id >= dm->dc->caps.max_streams)
3433 possible_crtcs = 0xff;
3434
cc1fec57 3435 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
df534fff
S		 3436
3437 if (ret) {
3438 DRM_ERROR("KMS: Failed to initialize plane\n");
54087768 3439 kfree(plane);
df534fff
S		 3440 return ret;
3441 }
3442
54087768
NK		 3443 if (mode_info)
3444 mode_info->planes[plane_id] = plane;
3445
df534fff
S		 3446 return ret;
3447}
3448
89fc8d4e
HW		 3449
3450static void register_backlight_device(struct amdgpu_display_manager *dm,
3451 struct dc_link *link)
3452{
3453#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3454 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3455
3456 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3457 link->type != dc_connection_none) {
1f6010a9
DF		 3458 /*
3459 * Event if registration failed, we should continue with
89fc8d4e
HW		 3460 * DM initialization because not having a backlight control
3461 * is better then a black screen.
3462 */
3463 amdgpu_dm_register_backlight_device(dm);
3464
3465 if (dm->backlight_dev)
3466 dm->backlight_link = link;
3467 }
3468#endif
3469}
3470
3471
1f6010a9
DF		 3472/*
3473 * In this architecture, the association
4562236b
HW		 3474 * connector -> encoder -> crtc
3475 * id not really requried. The crtc and connector will hold the
3476 * display_index as an abstraction to use with DAL component
3477 *
3478 * Returns 0 on success
3479 */
7578ecda 3480static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 3481{
3482 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 3483 int32_t i;
c84dec2f 3484 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 3485 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 3486 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 3487 uint32_t link_cnt;
cc1fec57 3488 int32_t primary_planes;
fbbdadf2 3489 enum dc_connection_type new_connection_type = dc_connection_none;
cc1fec57 3490 const struct dc_plane_cap *plane;
4562236b 3491
d58159de
AD		 3492 dm->display_indexes_num = dm->dc->caps.max_streams;
3493 /* Update the actual used number of crtc */
3494 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
3495
4562236b 3496 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 3497 if (amdgpu_dm_mode_config_init(dm->adev)) {
3498 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 3499 return -EINVAL;
4562236b
HW		 3500 }
3501
b2fddb13
NK		 3502 /* There is one primary plane per CRTC */
3503 primary_planes = dm->dc->caps.max_streams;
54087768 3504 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
efa6a8b7 3505
b2fddb13
NK		 3506 /*
3507 * Initialize primary planes, implicit planes for legacy IOCTLS.
3508 * Order is reversed to match iteration order in atomic check.
3509 */
3510 for (i = (primary_planes - 1); i >= 0; i--) {
cc1fec57
NK		 3511 plane = &dm->dc->caps.planes[i];
3512
b2fddb13 3513 if (initialize_plane(dm, mode_info, i,
cc1fec57 3514 DRM_PLANE_TYPE_PRIMARY, plane)) {
df534fff 3515 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 3516 goto fail;
d4e13b0d 3517 }
df534fff 3518 }
92f3ac40 3519
0d579c7e
NK		 3520 /*
3521 * Initialize overlay planes, index starting after primary planes.
3522 * These planes have a higher DRM index than the primary planes since
3523 * they should be considered as having a higher z-order.
3524 * Order is reversed to match iteration order in atomic check.
cc1fec57
NK		 3525 *
3526 * Only support DCN for now, and only expose one so we don't encourage
3527 * userspace to use up all the pipes.
0d579c7e 3528 */
cc1fec57
NK		 3529 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
3530 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
3531
3532 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
3533 continue;
3534
3535 if (!plane->blends_with_above || !plane->blends_with_below)
3536 continue;
3537
ea36ad34 3538 if (!plane->pixel_format_support.argb8888)
cc1fec57
NK		 3539 continue;
3540
54087768 3541 if (initialize_plane(dm, NULL, primary_planes + i,
cc1fec57 3542 DRM_PLANE_TYPE_OVERLAY, plane)) {
0d579c7e 3543 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 3544 goto fail;
d4e13b0d 3545 }
cc1fec57
NK		 3546
3547 /* Only create one overlay plane. */
3548 break;
d4e13b0d 3549 }
4562236b 3550
d4e13b0d 3551 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 3552 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 3553 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 3554 goto fail;
4562236b 3555 }
4562236b 3556
4562236b
HW		 3557 /* loops over all connectors on the board */
3558 for (i = 0; i < link_cnt; i++) {
89fc8d4e 3559 struct dc_link *link = NULL;
4562236b
HW		 3560
3561 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
3562 DRM_ERROR(
3563 "KMS: Cannot support more than %d display indexes\n",
3564 AMDGPU_DM_MAX_DISPLAY_INDEX);
3565 continue;
3566 }
3567
3568 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
3569 if (!aconnector)
cd8a2ae8 3570 goto fail;
4562236b
HW		 3571
3572 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 3573 if (!aencoder)
cd8a2ae8 3574 goto fail;
4562236b
HW		 3575
3576 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
3577 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 3578 goto fail;
4562236b
HW		 3579 }
3580
3581 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
3582 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 3583 goto fail;
4562236b
HW		 3584 }
3585
89fc8d4e
HW		 3586 link = dc_get_link_at_index(dm->dc, i);
3587
fbbdadf2
BL		 3588 if (!dc_link_detect_sink(link, &new_connection_type))
3589 DRM_ERROR("KMS: Failed to detect connector\n");
3590
3591 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3592 emulated_link_detect(link);
3593 amdgpu_dm_update_connector_after_detect(aconnector);
3594
3595 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 3596 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e 3597 register_backlight_device(dm, link);
397a9bc5
RL		 3598 if (amdgpu_dc_feature_mask & DC_PSR_MASK)
3599 amdgpu_dm_set_psr_caps(link);
89fc8d4e
HW		 3600 }
3601
3602
4562236b
HW		 3603 }
3604
3605 /* Software is initialized. Now we can register interrupt handlers. */
3606 switch (adev->asic_type) {
55e56389
MR		 3607#if defined(CONFIG_DRM_AMD_DC_SI)
3608 case CHIP_TAHITI:
3609 case CHIP_PITCAIRN:
3610 case CHIP_VERDE:
3611 case CHIP_OLAND:
3612 if (dce60_register_irq_handlers(dm->adev)) {
3613 DRM_ERROR("DM: Failed to initialize IRQ\n");
3614 goto fail;
3615 }
3616 break;
3617#endif
4562236b
HW		 3618 case CHIP_BONAIRE:
3619 case CHIP_HAWAII:
cd4b356f
AD		 3620 case CHIP_KAVERI:
3621 case CHIP_KABINI:
3622 case CHIP_MULLINS:
4562236b
HW		 3623 case CHIP_TONGA:
3624 case CHIP_FIJI:
3625 case CHIP_CARRIZO:
3626 case CHIP_STONEY:
3627 case CHIP_POLARIS11:
3628 case CHIP_POLARIS10:
b264d345 3629 case CHIP_POLARIS12:
7737de91 3630 case CHIP_VEGAM:
2c8ad2d5 3631 case CHIP_VEGA10:
2325ff30 3632 case CHIP_VEGA12:
1fe6bf2f 3633 case CHIP_VEGA20:
4562236b
HW		 3634 if (dce110_register_irq_handlers(dm->adev)) {
3635 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 3636 goto fail;
4562236b
HW		 3637 }
3638 break;
b86a1aa3 3639#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 3640 case CHIP_RAVEN:
fbd2afe5 3641 case CHIP_NAVI12:
476e955d 3642 case CHIP_NAVI10:
fce651e3 3643 case CHIP_NAVI14:
30221ad8 3644 case CHIP_RENOIR:
79037324 3645 case CHIP_SIENNA_CICHLID:
a6c5308f 3646 case CHIP_NAVY_FLOUNDER:
2a411205 3647 case CHIP_DIMGREY_CAVEFISH:
469989ca 3648 case CHIP_VANGOGH:
ff5ef992
AD		 3649 if (dcn10_register_irq_handlers(dm->adev)) {
3650 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 3651 goto fail;
ff5ef992
AD		 3652 }
3653 break;
3654#endif
4562236b 3655 default:
e63f8673 3656 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 3657 goto fail;
4562236b
HW		 3658 }
3659
4562236b 3660 return 0;
cd8a2ae8 3661fail:
4562236b 3662 kfree(aencoder);
4562236b 3663 kfree(aconnector);
54087768 3664
59d0f396 3665 return -EINVAL;
4562236b
HW		 3666}
3667
7578ecda 3668static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 3669{
3670 drm_mode_config_cleanup(dm->ddev);
eb3dc897 3671 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 3672 return;
3673}
3674
3675/******************************************************************************
3676 * amdgpu_display_funcs functions
3677 *****************************************************************************/
3678
1f6010a9 3679/*
4562236b
HW		 3680 * dm_bandwidth_update - program display watermarks
3681 *
3682 * @adev: amdgpu_device pointer
3683 *
3684 * Calculate and program the display watermarks and line buffer allocation.
3685 */
3686static void dm_bandwidth_update(struct amdgpu_device *adev)
3687{
49c07a99 3688 /* TODO: implement later */
4562236b
HW		 3689}
3690
39cc5be2 3691static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 3692 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
3693 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 3694 .backlight_set_level = NULL, /* never called for DC */
3695 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 3696 .hpd_sense = NULL,/* called unconditionally */
3697 .hpd_set_polarity = NULL, /* called unconditionally */
3698 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 3699 .page_flip_get_scanoutpos =
3700 dm_crtc_get_scanoutpos,/* called unconditionally */
3701 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
3702 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 3703};
3704
3705#if defined(CONFIG_DEBUG_KERNEL_DC)
3706
3ee6b26b
AD		 3707static ssize_t s3_debug_store(struct device *device,
3708 struct device_attribute *attr,
3709 const char *buf,
3710 size_t count)
4562236b
HW		 3711{
3712 int ret;
3713 int s3_state;
ef1de361 3714 struct drm_device *drm_dev = dev_get_drvdata(device);
1348969a 3715 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4562236b
HW		 3716
3717 ret = kstrtoint(buf, 0, &s3_state);
3718
3719 if (ret == 0) {
3720 if (s3_state) {
3721 dm_resume(adev);
4a580877 3722 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4562236b
HW		 3723 } else
3724 dm_suspend(adev);
3725 }
3726
3727 return ret == 0 ? count : 0;
3728}
3729
3730DEVICE_ATTR_WO(s3_debug);
3731
3732#endif
3733
3734static int dm_early_init(void *handle)
3735{
3736 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3737
4562236b 3738 switch (adev->asic_type) {
55e56389
MR		 3739#if defined(CONFIG_DRM_AMD_DC_SI)
3740 case CHIP_TAHITI:
3741 case CHIP_PITCAIRN:
3742 case CHIP_VERDE:
3743 adev->mode_info.num_crtc = 6;
3744 adev->mode_info.num_hpd = 6;
3745 adev->mode_info.num_dig = 6;
3746 break;
3747 case CHIP_OLAND:
3748 adev->mode_info.num_crtc = 2;
3749 adev->mode_info.num_hpd = 2;
3750 adev->mode_info.num_dig = 2;
3751 break;
3752#endif
4562236b
HW		 3753 case CHIP_BONAIRE:
3754 case CHIP_HAWAII:
3755 adev->mode_info.num_crtc = 6;
3756 adev->mode_info.num_hpd = 6;
3757 adev->mode_info.num_dig = 6;
4562236b 3758 break;
cd4b356f
AD		 3759 case CHIP_KAVERI:
3760 adev->mode_info.num_crtc = 4;
3761 adev->mode_info.num_hpd = 6;
3762 adev->mode_info.num_dig = 7;
cd4b356f
AD		 3763 break;
3764 case CHIP_KABINI:
3765 case CHIP_MULLINS:
3766 adev->mode_info.num_crtc = 2;
3767 adev->mode_info.num_hpd = 6;
3768 adev->mode_info.num_dig = 6;
cd4b356f 3769 break;
4562236b
HW		 3770 case CHIP_FIJI:
3771 case CHIP_TONGA:
3772 adev->mode_info.num_crtc = 6;
3773 adev->mode_info.num_hpd = 6;
3774 adev->mode_info.num_dig = 7;
4562236b
HW		 3775 break;
3776 case CHIP_CARRIZO:
3777 adev->mode_info.num_crtc = 3;
3778 adev->mode_info.num_hpd = 6;
3779 adev->mode_info.num_dig = 9;
4562236b
HW		 3780 break;
3781 case CHIP_STONEY:
3782 adev->mode_info.num_crtc = 2;
3783 adev->mode_info.num_hpd = 6;
3784 adev->mode_info.num_dig = 9;
4562236b
HW		 3785 break;
3786 case CHIP_POLARIS11:
b264d345 3787 case CHIP_POLARIS12:
4562236b
HW		 3788 adev->mode_info.num_crtc = 5;
3789 adev->mode_info.num_hpd = 5;
3790 adev->mode_info.num_dig = 5;
4562236b
HW		 3791 break;
3792 case CHIP_POLARIS10:
7737de91 3793 case CHIP_VEGAM:
4562236b
HW		 3794 adev->mode_info.num_crtc = 6;
3795 adev->mode_info.num_hpd = 6;
3796 adev->mode_info.num_dig = 6;
4562236b 3797 break;
2c8ad2d5 3798 case CHIP_VEGA10:
2325ff30 3799 case CHIP_VEGA12:
1fe6bf2f 3800 case CHIP_VEGA20:
2c8ad2d5
AD		 3801 adev->mode_info.num_crtc = 6;
3802 adev->mode_info.num_hpd = 6;
3803 adev->mode_info.num_dig = 6;
3804 break;
b86a1aa3 3805#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 3806 case CHIP_RAVEN:
20f2ffe5
AD		 3807 case CHIP_RENOIR:
3808 case CHIP_VANGOGH:
ff5ef992
AD		 3809 adev->mode_info.num_crtc = 4;
3810 adev->mode_info.num_hpd = 4;
3811 adev->mode_info.num_dig = 4;
ff5ef992 3812 break;
476e955d 3813 case CHIP_NAVI10:
fbd2afe5 3814 case CHIP_NAVI12:
79037324 3815 case CHIP_SIENNA_CICHLID:
a6c5308f 3816 case CHIP_NAVY_FLOUNDER:
476e955d
HW		 3817 adev->mode_info.num_crtc = 6;
3818 adev->mode_info.num_hpd = 6;
3819 adev->mode_info.num_dig = 6;
3820 break;
fce651e3 3821 case CHIP_NAVI14:
2a411205 3822 case CHIP_DIMGREY_CAVEFISH:
fce651e3
BL		 3823 adev->mode_info.num_crtc = 5;
3824 adev->mode_info.num_hpd = 5;
3825 adev->mode_info.num_dig = 5;
3826 break;
20f2ffe5 3827#endif
4562236b 3828 default:
e63f8673 3829 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 3830 return -EINVAL;
3831 }
3832
c8dd5715
MD		 3833 amdgpu_dm_set_irq_funcs(adev);
3834
39cc5be2
AD		 3835 if (adev->mode_info.funcs == NULL)
3836 adev->mode_info.funcs = &dm_display_funcs;
3837
1f6010a9
DF		 3838 /*
3839 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 3840 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 3841 * amdgpu_device_init()
3842 */
4562236b
HW		 3843#if defined(CONFIG_DEBUG_KERNEL_DC)
3844 device_create_file(
4a580877 3845 adev_to_drm(adev)->dev,
4562236b
HW		 3846 &dev_attr_s3_debug);
3847#endif
3848
3849 return 0;
3850}
3851
9b690ef3 3852static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 3853 struct dc_stream_state *new_stream,
3854 struct dc_stream_state *old_stream)
9b690ef3 3855{
2afda735 3856 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
e7b07cee
HW		 3857}
3858
3859static bool modereset_required(struct drm_crtc_state *crtc_state)
3860{
2afda735 3861 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
e7b07cee
HW		 3862}
3863
7578ecda 3864static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 3865{
3866 drm_encoder_cleanup(encoder);
3867 kfree(encoder);
3868}
3869
3870static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
3871 .destroy = amdgpu_dm_encoder_destroy,
3872};
3873
e7b07cee 3874
6300b3bd
MK		 3875static void get_min_max_dc_plane_scaling(struct drm_device *dev,
3876 struct drm_framebuffer *fb,
3877 int *min_downscale, int *max_upscale)
3878{
3879 struct amdgpu_device *adev = drm_to_adev(dev);
3880 struct dc *dc = adev->dm.dc;
3881 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */
3882 struct dc_plane_cap *plane_cap = &dc->caps.planes[0];
3883
3884 switch (fb->format->format) {
3885 case DRM_FORMAT_P010:
3886 case DRM_FORMAT_NV12:
3887 case DRM_FORMAT_NV21:
3888 *max_upscale = plane_cap->max_upscale_factor.nv12;
3889 *min_downscale = plane_cap->max_downscale_factor.nv12;
3890 break;
3891
3892 case DRM_FORMAT_XRGB16161616F:
3893 case DRM_FORMAT_ARGB16161616F:
3894 case DRM_FORMAT_XBGR16161616F:
3895 case DRM_FORMAT_ABGR16161616F:
3896 *max_upscale = plane_cap->max_upscale_factor.fp16;
3897 *min_downscale = plane_cap->max_downscale_factor.fp16;
3898 break;
3899
3900 default:
3901 *max_upscale = plane_cap->max_upscale_factor.argb8888;
3902 *min_downscale = plane_cap->max_downscale_factor.argb8888;
3903 break;
3904 }
3905
3906 /*
3907 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a
3908 * scaling factor of 1.0 == 1000 units.
3909 */
3910 if (*max_upscale == 1)
3911 *max_upscale = 1000;
3912
3913 if (*min_downscale == 1)
3914 *min_downscale = 1000;
3915}
3916
3917
695af5f9
NK		 3918static int fill_dc_scaling_info(const struct drm_plane_state *state,
3919 struct dc_scaling_info *scaling_info)
e7b07cee 3920{
6300b3bd 3921 int scale_w, scale_h, min_downscale, max_upscale;
e7b07cee 3922
695af5f9 3923 memset(scaling_info, 0, sizeof(*scaling_info));
e7b07cee 3924
695af5f9
NK		 3925 /* Source is fixed 16.16 but we ignore mantissa for now... */
3926 scaling_info->src_rect.x = state->src_x >> 16;
3927 scaling_info->src_rect.y = state->src_y >> 16;
e7b07cee 3928
695af5f9
NK		 3929 scaling_info->src_rect.width = state->src_w >> 16;
3930 if (scaling_info->src_rect.width == 0)
3931 return -EINVAL;
3932
3933 scaling_info->src_rect.height = state->src_h >> 16;
3934 if (scaling_info->src_rect.height == 0)
3935 return -EINVAL;
3936
3937 scaling_info->dst_rect.x = state->crtc_x;
3938 scaling_info->dst_rect.y = state->crtc_y;
e7b07cee
HW		 3939
3940 if (state->crtc_w == 0)
695af5f9 3941 return -EINVAL;
e7b07cee 3942
695af5f9 3943 scaling_info->dst_rect.width = state->crtc_w;
e7b07cee
HW		 3944
3945 if (state->crtc_h == 0)
695af5f9 3946 return -EINVAL;
e7b07cee 3947
695af5f9 3948 scaling_info->dst_rect.height = state->crtc_h;
e7b07cee 3949
695af5f9
NK		 3950 /* DRM doesn't specify clipping on destination output. */
3951 scaling_info->clip_rect = scaling_info->dst_rect;
e7b07cee 3952
6300b3bd
MK		 3953 /* Validate scaling per-format with DC plane caps */
3954 if (state->plane && state->plane->dev && state->fb) {
3955 get_min_max_dc_plane_scaling(state->plane->dev, state->fb,
3956 &min_downscale, &max_upscale);
3957 } else {
3958 min_downscale = 250;
3959 max_upscale = 16000;
3960 }
3961
6491f0c0
NK		 3962 scale_w = scaling_info->dst_rect.width * 1000 /
3963 scaling_info->src_rect.width;
e7b07cee 3964
6300b3bd 3965 if (scale_w < min_downscale || scale_w > max_upscale)
6491f0c0
NK		 3966 return -EINVAL;
3967
3968 scale_h = scaling_info->dst_rect.height * 1000 /
3969 scaling_info->src_rect.height;
3970
6300b3bd 3971 if (scale_h < min_downscale || scale_h > max_upscale)
6491f0c0
NK		 3972 return -EINVAL;
3973
695af5f9
NK		 3974 /*
3975 * The "scaling_quality" can be ignored for now, quality = 0 has DC
3976 * assume reasonable defaults based on the format.
3977 */
e7b07cee 3978
695af5f9 3979 return 0;
4562236b 3980}
695af5f9 3981
a3241991
BN		 3982static void
3983fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
3984 uint64_t tiling_flags)
e7b07cee 3985{
a3241991
BN		 3986 /* Fill GFX8 params */
3987 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
3988 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
707477b0 3989
a3241991
BN		 3990 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
3991 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
3992 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
3993 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
3994 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
b830ebc9 3995
a3241991
BN		 3996 /* XXX fix me for VI */
3997 tiling_info->gfx8.num_banks = num_banks;
3998 tiling_info->gfx8.array_mode =
3999 DC_ARRAY_2D_TILED_THIN1;
4000 tiling_info->gfx8.tile_split = tile_split;
4001 tiling_info->gfx8.bank_width = bankw;
4002 tiling_info->gfx8.bank_height = bankh;
4003 tiling_info->gfx8.tile_aspect = mtaspect;
4004 tiling_info->gfx8.tile_mode =
4005 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
4006 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
4007 == DC_ARRAY_1D_TILED_THIN1) {
4008 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 4009 }
4010
a3241991
BN		 4011 tiling_info->gfx8.pipe_config =
4012 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
e7b07cee
HW		 4013}
4014
a3241991
BN		 4015static void
4016fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
4017 union dc_tiling_info *tiling_info)
4018{
4019 tiling_info->gfx9.num_pipes =
4020 adev->gfx.config.gb_addr_config_fields.num_pipes;
4021 tiling_info->gfx9.num_banks =
4022 adev->gfx.config.gb_addr_config_fields.num_banks;
4023 tiling_info->gfx9.pipe_interleave =
4024 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
4025 tiling_info->gfx9.num_shader_engines =
4026 adev->gfx.config.gb_addr_config_fields.num_se;
4027 tiling_info->gfx9.max_compressed_frags =
4028 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
4029 tiling_info->gfx9.num_rb_per_se =
4030 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
4031 tiling_info->gfx9.shaderEnable = 1;
a3241991
BN		 4032 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4033 adev->asic_type == CHIP_NAVY_FLOUNDER ||
4034 adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
4035 adev->asic_type == CHIP_VANGOGH)
4036 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
7df7e505
NK		 4037}
4038
695af5f9 4039static int
a3241991
BN		 4040validate_dcc(struct amdgpu_device *adev,
4041 const enum surface_pixel_format format,
4042 const enum dc_rotation_angle rotation,
4043 const union dc_tiling_info *tiling_info,
4044 const struct dc_plane_dcc_param *dcc,
4045 const struct dc_plane_address *address,
4046 const struct plane_size *plane_size)
7df7e505
NK		 4047{
4048 struct dc *dc = adev->dm.dc;
8daa1218
NC		 4049 struct dc_dcc_surface_param input;
4050 struct dc_surface_dcc_cap output;
7df7e505 4051
8daa1218
NC		 4052 memset(&input, 0, sizeof(input));
4053 memset(&output, 0, sizeof(output));
4054
a3241991 4055 if (!dcc->enable)
87b7ebc2
RS		 4056 return 0;
4057
a3241991
BN		 4058 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN ||
4059 !dc->cap_funcs.get_dcc_compression_cap)
09e5665a 4060 return -EINVAL;
7df7e505 4061
695af5f9 4062 input.format = format;
12e2b2d4
DL		 4063 input.surface_size.width = plane_size->surface_size.width;
4064 input.surface_size.height = plane_size->surface_size.height;
695af5f9 4065 input.swizzle_mode = tiling_info->gfx9.swizzle;
7df7e505 4066
695af5f9 4067 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
7df7e505 4068 input.scan = SCAN_DIRECTION_HORIZONTAL;
695af5f9 4069 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
7df7e505
NK		 4070 input.scan = SCAN_DIRECTION_VERTICAL;
4071
4072 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
09e5665a 4073 return -EINVAL;
7df7e505
NK		 4074
4075 if (!output.capable)
09e5665a 4076 return -EINVAL;
7df7e505 4077
a3241991
BN		 4078 if (dcc->independent_64b_blks == 0 &&
4079 output.grph.rgb.independent_64b_blks != 0)
09e5665a 4080 return -EINVAL;
7df7e505 4081
a3241991
BN		 4082 return 0;
4083}
4084
37384b3f
BN		 4085static bool
4086modifier_has_dcc(uint64_t modifier)
4087{
4088 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
4089}
4090
4091static unsigned
4092modifier_gfx9_swizzle_mode(uint64_t modifier)
4093{
4094 if (modifier == DRM_FORMAT_MOD_LINEAR)
4095 return 0;
4096
4097 return AMD_FMT_MOD_GET(TILE, modifier);
4098}
4099
dfbbfe3c
BN		 4100static const struct drm_format_info *
4101amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
4102{
816853f9 4103 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]);
dfbbfe3c
BN		 4104}
4105
37384b3f
BN		 4106static void
4107fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
4108 union dc_tiling_info *tiling_info,
4109 uint64_t modifier)
4110{
4111 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
4112 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
4113 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
4114 unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
4115
4116 fill_gfx9_tiling_info_from_device(adev, tiling_info);
4117
4118 if (!IS_AMD_FMT_MOD(modifier))
4119 return;
4120
4121 tiling_info->gfx9.num_pipes = 1u << pipes_log2;
4122 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2);
4123
4124 if (adev->family >= AMDGPU_FAMILY_NV) {
4125 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
4126 } else {
4127 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
4128
4129 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
4130 }
4131}
4132
faa37f54
BN		 4133enum dm_micro_swizzle {
4134 MICRO_SWIZZLE_Z = 0,
4135 MICRO_SWIZZLE_S = 1,
4136 MICRO_SWIZZLE_D = 2,
4137 MICRO_SWIZZLE_R = 3
4138};
4139
4140static bool dm_plane_format_mod_supported(struct drm_plane *plane,
4141 uint32_t format,
4142 uint64_t modifier)
4143{
4144 struct amdgpu_device *adev = drm_to_adev(plane->dev);
4145 const struct drm_format_info *info = drm_format_info(format);
4146
4147 enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
4148
4149 if (!info)
4150 return false;
4151
4152 /*
4153 * We always have to allow this modifier, because core DRM still
4154 * checks LINEAR support if userspace does not provide modifers.
4155 */
4156 if (modifier == DRM_FORMAT_MOD_LINEAR)
4157 return true;
4158
4159 /*
4160 * The arbitrary tiling support for multiplane formats has not been hooked
4161 * up.
4162 */
4163 if (info->num_planes > 1)
4164 return false;
4165
4166 /*
4167 * For D swizzle the canonical modifier depends on the bpp, so check
4168 * it here.
4169 */
4170 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 &&
4171 adev->family >= AMDGPU_FAMILY_NV) {
4172 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4)
4173 return false;
4174 }
4175
4176 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D &&
4177 info->cpp[0] < 8)
4178 return false;
4179
4180 if (modifier_has_dcc(modifier)) {
4181 /* Per radeonsi comments 16/64 bpp are more complicated. */
4182 if (info->cpp[0] != 4)
4183 return false;
4184 }
4185
4186 return true;
4187}
4188
4189static void
4190add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod)
4191{
4192 if (!*mods)
4193 return;
4194
4195 if (*cap - *size < 1) {
4196 uint64_t new_cap = *cap * 2;
4197 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL);
4198
4199 if (!new_mods) {
4200 kfree(*mods);
4201 *mods = NULL;
4202 return;
4203 }
4204
4205 memcpy(new_mods, *mods, sizeof(uint64_t) * *size);
4206 kfree(*mods);
4207 *mods = new_mods;
4208 *cap = new_cap;
4209 }
4210
4211 (*mods)[*size] = mod;
4212 *size += 1;
4213}
4214
4215static void
4216add_gfx9_modifiers(const struct amdgpu_device *adev,
4217 uint64_t **mods, uint64_t *size, uint64_t *capacity)
4218{
4219 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4220 int pipe_xor_bits = min(8, pipes +
4221 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
4222 int bank_xor_bits = min(8 - pipe_xor_bits,
4223 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
4224 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
4225 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
4226
4227
4228 if (adev->family == AMDGPU_FAMILY_RV) {
4229 /* Raven2 and later */
4230 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81;
4231
4232 /*
4233 * No _D DCC swizzles yet because we only allow 32bpp, which
4234 * doesn't support _D on DCN
4235 */
4236
4237 if (has_constant_encode) {
4238 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4239 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4240 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4241 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4242 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4243 AMD_FMT_MOD_SET(DCC, 1) |
4244 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4245 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4246 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1));
4247 }
4248
4249 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4250 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4251 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4252 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4253 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4254 AMD_FMT_MOD_SET(DCC, 1) |
4255 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4256 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4257 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0));
4258
4259 if (has_constant_encode) {
4260 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4261 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4262 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4263 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4264 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4265 AMD_FMT_MOD_SET(DCC, 1) |
4266 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4267 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4268 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4269
4270 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4271 AMD_FMT_MOD_SET(RB, rb) |
4272 AMD_FMT_MOD_SET(PIPE, pipes));
4273 }
4274
4275 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4276 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4277 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4278 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4279 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4280 AMD_FMT_MOD_SET(DCC, 1) |
4281 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4282 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4283 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4284 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) |
4285 AMD_FMT_MOD_SET(RB, rb) |
4286 AMD_FMT_MOD_SET(PIPE, pipes));
4287 }
4288
4289 /*
4290 * Only supported for 64bpp on Raven, will be filtered on format in
4291 * dm_plane_format_mod_supported.
4292 */
4293 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4294 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) |
4295 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4296 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4297 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
4298
4299 if (adev->family == AMDGPU_FAMILY_RV) {
4300 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4301 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4302 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4303 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4304 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
4305 }
4306
4307 /*
4308 * Only supported for 64bpp on Raven, will be filtered on format in
4309 * dm_plane_format_mod_supported.
4310 */
4311 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4312 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4313 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4314
4315 if (adev->family == AMDGPU_FAMILY_RV) {
4316 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4317 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4318 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4319 }
4320}
4321
4322static void
4323add_gfx10_1_modifiers(const struct amdgpu_device *adev,
4324 uint64_t **mods, uint64_t *size, uint64_t *capacity)
4325{
4326 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4327
4328 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4329 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4330 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4331 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4332 AMD_FMT_MOD_SET(DCC, 1) |
4333 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4334 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4335 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4336
4337 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4338 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4339 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4340 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4341 AMD_FMT_MOD_SET(DCC, 1) |
4342 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4343 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4344 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4345 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4346
4347 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4348 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4349 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4350 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
4351
4352 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4353 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4354 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4355 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
4356
4357
4358 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
4359 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4360 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4361 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4362
4363 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4364 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4365 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4366}
4367
4368static void
4369add_gfx10_3_modifiers(const struct amdgpu_device *adev,
4370 uint64_t **mods, uint64_t *size, uint64_t *capacity)
4371{
4372 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4373 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
4374
4375 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4376 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4377 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4378 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4379 AMD_FMT_MOD_SET(PACKERS, pkrs) |
4380 AMD_FMT_MOD_SET(DCC, 1) |
4381 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4382 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4383 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
4384 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
4385
4386 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4387 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4388 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4389 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4390 AMD_FMT_MOD_SET(PACKERS, pkrs) |
4391 AMD_FMT_MOD_SET(DCC, 1) |
4392 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4393 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4394 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4395 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
4396 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
4397
4398 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4399 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4400 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4401 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4402 AMD_FMT_MOD_SET(PACKERS, pkrs));
4403
4404 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4405 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4406 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4407 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4408 AMD_FMT_MOD_SET(PACKERS, pkrs));
4409
4410 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
4411 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4412 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4413 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4414
4415 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4416 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4417 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4418}
4419
4420static int
4421get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
4422{
4423 uint64_t size = 0, capacity = 128;
4424 *mods = NULL;
4425
4426 /* We have not hooked up any pre-GFX9 modifiers. */
4427 if (adev->family < AMDGPU_FAMILY_AI)
4428 return 0;
4429
4430 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL);
4431
4432 if (plane_type == DRM_PLANE_TYPE_CURSOR) {
4433 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
4434 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
4435 return *mods ? 0 : -ENOMEM;
4436 }
4437
4438 switch (adev->family) {
4439 case AMDGPU_FAMILY_AI:
4440 case AMDGPU_FAMILY_RV:
4441 add_gfx9_modifiers(adev, mods, &size, &capacity);
4442 break;
4443 case AMDGPU_FAMILY_NV:
4444 case AMDGPU_FAMILY_VGH:
4445 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4446 add_gfx10_3_modifiers(adev, mods, &size, &capacity);
4447 else
4448 add_gfx10_1_modifiers(adev, mods, &size, &capacity);
4449 break;
4450 }
4451
4452 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
4453
4454 /* INVALID marks the end of the list. */
4455 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
4456
4457 if (!*mods)
4458 return -ENOMEM;
4459
4460 return 0;
4461}
4462
37384b3f
BN		 4463static int
4464fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
4465 const struct amdgpu_framebuffer *afb,
4466 const enum surface_pixel_format format,
4467 const enum dc_rotation_angle rotation,
4468 const struct plane_size *plane_size,
4469 union dc_tiling_info *tiling_info,
4470 struct dc_plane_dcc_param *dcc,
4471 struct dc_plane_address *address,
4472 const bool force_disable_dcc)
4473{
4474 const uint64_t modifier = afb->base.modifier;
4475 int ret;
4476
4477 fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
4478 tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
4479
4480 if (modifier_has_dcc(modifier) && !force_disable_dcc) {
4481 uint64_t dcc_address = afb->address + afb->base.offsets[1];
4482
4483 dcc->enable = 1;
4484 dcc->meta_pitch = afb->base.pitches[1];
4485 dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
4486
4487 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
4488 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
4489 }
4490
4491 ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
4492 if (ret)
4493 return ret;
7df7e505 4494
09e5665a
NK		 4495 return 0;
4496}
4497
4498static int
320932bf 4499fill_plane_buffer_attributes(struct amdgpu_device *adev,
09e5665a 4500 const struct amdgpu_framebuffer *afb,
695af5f9
NK		 4501 const enum surface_pixel_format format,
4502 const enum dc_rotation_angle rotation,
4503 const uint64_t tiling_flags,
09e5665a 4504 union dc_tiling_info *tiling_info,
12e2b2d4 4505 struct plane_size *plane_size,
09e5665a 4506 struct dc_plane_dcc_param *dcc,
87b7ebc2 4507 struct dc_plane_address *address,
5888f07a 4508 bool tmz_surface,
87b7ebc2 4509 bool force_disable_dcc)
09e5665a 4510{
320932bf 4511 const struct drm_framebuffer *fb = &afb->base;
09e5665a
NK		 4512 int ret;
4513
4514 memset(tiling_info, 0, sizeof(*tiling_info));
320932bf 4515 memset(plane_size, 0, sizeof(*plane_size));
09e5665a 4516 memset(dcc, 0, sizeof(*dcc));
e0634e8d
NK		 4517 memset(address, 0, sizeof(*address));
4518
5888f07a
HW		 4519 address->tmz_surface = tmz_surface;
4520
695af5f9 4521 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
be7b9b32
BN		 4522 uint64_t addr = afb->address + fb->offsets[0];
4523
12e2b2d4
DL		 4524 plane_size->surface_size.x = 0;
4525 plane_size->surface_size.y = 0;
4526 plane_size->surface_size.width = fb->width;
4527 plane_size->surface_size.height = fb->height;
4528 plane_size->surface_pitch =
320932bf
NK		 4529 fb->pitches[0] / fb->format->cpp[0];
4530
e0634e8d 4531 address->type = PLN_ADDR_TYPE_GRAPHICS;
be7b9b32
BN		 4532 address->grph.addr.low_part = lower_32_bits(addr);
4533 address->grph.addr.high_part = upper_32_bits(addr);
1894478a 4534 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
be7b9b32 4535 uint64_t luma_addr = afb->address + fb->offsets[0];
1791e54f 4536 uint64_t chroma_addr = afb->address + fb->offsets[1];
e0634e8d 4537
12e2b2d4
DL		 4538 plane_size->surface_size.x = 0;
4539 plane_size->surface_size.y = 0;
4540 plane_size->surface_size.width = fb->width;
4541 plane_size->surface_size.height = fb->height;
4542 plane_size->surface_pitch =
320932bf
NK		 4543 fb->pitches[0] / fb->format->cpp[0];
4544
12e2b2d4
DL		 4545 plane_size->chroma_size.x = 0;
4546 plane_size->chroma_size.y = 0;
320932bf 4547 /* TODO: set these based on surface format */
12e2b2d4
DL		 4548 plane_size->chroma_size.width = fb->width / 2;
4549 plane_size->chroma_size.height = fb->height / 2;
320932bf 4550
12e2b2d4 4551 plane_size->chroma_pitch =
320932bf
NK		 4552 fb->pitches[1] / fb->format->cpp[1];
4553
e0634e8d
NK		 4554 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
4555 address->video_progressive.luma_addr.low_part =
be7b9b32 4556 lower_32_bits(luma_addr);
e0634e8d 4557 address->video_progressive.luma_addr.high_part =
be7b9b32 4558 upper_32_bits(luma_addr);
e0634e8d
NK		 4559 address->video_progressive.chroma_addr.low_part =
4560 lower_32_bits(chroma_addr);
4561 address->video_progressive.chroma_addr.high_part =
4562 upper_32_bits(chroma_addr);
4563 }
09e5665a 4564
a3241991 4565 if (adev->family >= AMDGPU_FAMILY_AI) {
9a33e881
BN		 4566 ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
4567 rotation, plane_size,
4568 tiling_info, dcc,
4569 address,
4570 force_disable_dcc);
09e5665a
NK		 4571 if (ret)
4572 return ret;
a3241991
BN		 4573 } else {
4574 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
09e5665a
NK		 4575 }
4576
4577 return 0;
7df7e505
NK		 4578}
4579
d74004b6 4580static void
695af5f9 4581fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
d74004b6
NK		 4582 bool *per_pixel_alpha, bool *global_alpha,
4583 int *global_alpha_value)
4584{
4585 *per_pixel_alpha = false;
4586 *global_alpha = false;
4587 *global_alpha_value = 0xff;
4588
4589 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
4590 return;
4591
4592 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
4593 static const uint32_t alpha_formats[] = {
4594 DRM_FORMAT_ARGB8888,
4595 DRM_FORMAT_RGBA8888,
4596 DRM_FORMAT_ABGR8888,
4597 };
4598 uint32_t format = plane_state->fb->format->format;
4599 unsigned int i;
4600
4601 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
4602 if (format == alpha_formats[i]) {
4603 *per_pixel_alpha = true;
4604 break;
4605 }
4606 }
4607 }
4608
4609 if (plane_state->alpha < 0xffff) {
4610 *global_alpha = true;
4611 *global_alpha_value = plane_state->alpha >> 8;
4612 }
4613}
4614
004fefa3
NK		 4615static int
4616fill_plane_color_attributes(const struct drm_plane_state *plane_state,
695af5f9 4617 const enum surface_pixel_format format,
004fefa3
NK		 4618 enum dc_color_space *color_space)
4619{
4620 bool full_range;
4621
4622 *color_space = COLOR_SPACE_SRGB;
4623
4624 /* DRM color properties only affect non-RGB formats. */
695af5f9 4625 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
004fefa3
NK		 4626 return 0;
4627
4628 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4629
4630 switch (plane_state->color_encoding) {
4631 case DRM_COLOR_YCBCR_BT601:
4632 if (full_range)
4633 *color_space = COLOR_SPACE_YCBCR601;
4634 else
4635 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4636 break;
4637
4638 case DRM_COLOR_YCBCR_BT709:
4639 if (full_range)
4640 *color_space = COLOR_SPACE_YCBCR709;
4641 else
4642 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4643 break;
4644
4645 case DRM_COLOR_YCBCR_BT2020:
4646 if (full_range)
4647 *color_space = COLOR_SPACE_2020_YCBCR;
4648 else
4649 return -EINVAL;
4650 break;
4651
4652 default:
4653 return -EINVAL;
4654 }
4655
4656 return 0;
4657}
4658
695af5f9
NK		 4659static int
4660fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4661 const struct drm_plane_state *plane_state,
4662 const uint64_t tiling_flags,
4663 struct dc_plane_info *plane_info,
87b7ebc2 4664 struct dc_plane_address *address,
5888f07a 4665 bool tmz_surface,
87b7ebc2 4666 bool force_disable_dcc)
695af5f9
NK		 4667{
4668 const struct drm_framebuffer *fb = plane_state->fb;
4669 const struct amdgpu_framebuffer *afb =
4670 to_amdgpu_framebuffer(plane_state->fb);
4671 struct drm_format_name_buf format_name;
4672 int ret;
4673
4674 memset(plane_info, 0, sizeof(*plane_info));
4675
4676 switch (fb->format->format) {
4677 case DRM_FORMAT_C8:
4678 plane_info->format =
4679 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4680 break;
4681 case DRM_FORMAT_RGB565:
4682 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4683 break;
4684 case DRM_FORMAT_XRGB8888:
4685 case DRM_FORMAT_ARGB8888:
4686 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4687 break;
4688 case DRM_FORMAT_XRGB2101010:
4689 case DRM_FORMAT_ARGB2101010:
4690 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4691 break;
4692 case DRM_FORMAT_XBGR2101010:
4693 case DRM_FORMAT_ABGR2101010:
4694 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4695 break;
4696 case DRM_FORMAT_XBGR8888:
4697 case DRM_FORMAT_ABGR8888:
4698 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4699 break;
4700 case DRM_FORMAT_NV21:
4701 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4702 break;
4703 case DRM_FORMAT_NV12:
4704 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4705 break;
cbec6477
SW		 4706 case DRM_FORMAT_P010:
4707 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4708 break;
492548dc
SW		 4709 case DRM_FORMAT_XRGB16161616F:
4710 case DRM_FORMAT_ARGB16161616F:
4711 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4712 break;
2a5195dc
MK		 4713 case DRM_FORMAT_XBGR16161616F:
4714 case DRM_FORMAT_ABGR16161616F:
4715 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4716 break;
695af5f9
NK		 4717 default:
4718 DRM_ERROR(
4719 "Unsupported screen format %s\n",
4720 drm_get_format_name(fb->format->format, &format_name));
4721 return -EINVAL;
4722 }
4723
4724 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4725 case DRM_MODE_ROTATE_0:
4726 plane_info->rotation = ROTATION_ANGLE_0;
4727 break;
4728 case DRM_MODE_ROTATE_90:
4729 plane_info->rotation = ROTATION_ANGLE_90;
4730 break;
4731 case DRM_MODE_ROTATE_180:
4732 plane_info->rotation = ROTATION_ANGLE_180;
4733 break;
4734 case DRM_MODE_ROTATE_270:
4735 plane_info->rotation = ROTATION_ANGLE_270;
4736 break;
4737 default:
4738 plane_info->rotation = ROTATION_ANGLE_0;
4739 break;
4740 }
4741
4742 plane_info->visible = true;
4743 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4744
6d83a32d
MS		 4745 plane_info->layer_index = 0;
4746
695af5f9
NK		 4747 ret = fill_plane_color_attributes(plane_state, plane_info->format,
4748 &plane_info->color_space);
4749 if (ret)
4750 return ret;
4751
4752 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4753 plane_info->rotation, tiling_flags,
4754 &plane_info->tiling_info,
4755 &plane_info->plane_size,
5888f07a 4756 &plane_info->dcc, address, tmz_surface,
87b7ebc2 4757 force_disable_dcc);
695af5f9
NK		 4758 if (ret)
4759 return ret;
4760
4761 fill_blending_from_plane_state(
4762 plane_state, &plane_info->per_pixel_alpha,
4763 &plane_info->global_alpha, &plane_info->global_alpha_value);
4764
4765 return 0;
4766}
4767
4768static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4769 struct dc_plane_state *dc_plane_state,
4770 struct drm_plane_state *plane_state,
4771 struct drm_crtc_state *crtc_state)
e7b07cee 4772{
cf020d49 4773 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
6eed95b0 4774 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
695af5f9
NK		 4775 struct dc_scaling_info scaling_info;
4776 struct dc_plane_info plane_info;
695af5f9 4777 int ret;
87b7ebc2 4778 bool force_disable_dcc = false;
e7b07cee 4779
695af5f9
NK		 4780 ret = fill_dc_scaling_info(plane_state, &scaling_info);
4781 if (ret)
4782 return ret;
e7b07cee 4783
695af5f9
NK		 4784 dc_plane_state->src_rect = scaling_info.src_rect;
4785 dc_plane_state->dst_rect = scaling_info.dst_rect;
4786 dc_plane_state->clip_rect = scaling_info.clip_rect;
4787 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
e7b07cee 4788
87b7ebc2 4789 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
707477b0 4790 ret = fill_dc_plane_info_and_addr(adev, plane_state,
6eed95b0 4791 afb->tiling_flags,
695af5f9 4792 &plane_info,
87b7ebc2 4793 &dc_plane_state->address,
6eed95b0 4794 afb->tmz_surface,
87b7ebc2 4795 force_disable_dcc);
004fefa3
NK		 4796 if (ret)
4797 return ret;
4798
695af5f9
NK		 4799 dc_plane_state->format = plane_info.format;
4800 dc_plane_state->color_space = plane_info.color_space;
4801 dc_plane_state->format = plane_info.format;
4802 dc_plane_state->plane_size = plane_info.plane_size;
4803 dc_plane_state->rotation = plane_info.rotation;
4804 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4805 dc_plane_state->stereo_format = plane_info.stereo_format;
4806 dc_plane_state->tiling_info = plane_info.tiling_info;
4807 dc_plane_state->visible = plane_info.visible;
4808 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4809 dc_plane_state->global_alpha = plane_info.global_alpha;
4810 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4811 dc_plane_state->dcc = plane_info.dcc;
6d83a32d 4812 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
695af5f9 4813
e277adc5
LSL		 4814 /*
4815 * Always set input transfer function, since plane state is refreshed
4816 * every time.
4817 */
cf020d49
NK		 4818 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4819 if (ret)
4820 return ret;
e7b07cee 4821
cf020d49 4822 return 0;
e7b07cee
HW		 4823}
4824
3ee6b26b
AD		 4825static void update_stream_scaling_settings(const struct drm_display_mode *mode,
4826 const struct dm_connector_state *dm_state,
4827 struct dc_stream_state *stream)
e7b07cee
HW		 4828{
4829 enum amdgpu_rmx_type rmx_type;
4830
4831 struct rect src = { 0 }; /* viewport in composition space*/
4832 struct rect dst = { 0 }; /* stream addressable area */
4833
4834 /* no mode. nothing to be done */
4835 if (!mode)
4836 return;
4837
4838 /* Full screen scaling by default */
4839 src.width = mode->hdisplay;
4840 src.height = mode->vdisplay;
4841 dst.width = stream->timing.h_addressable;
4842 dst.height = stream->timing.v_addressable;
4843
f4791779
HW		 4844 if (dm_state) {
4845 rmx_type = dm_state->scaling;
4846 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
4847 if (src.width * dst.height <
4848 src.height * dst.width) {
4849 /* height needs less upscaling/more downscaling */
4850 dst.width = src.width *
4851 dst.height / src.height;
4852 } else {
4853 /* width needs less upscaling/more downscaling */
4854 dst.height = src.height *
4855 dst.width / src.width;
4856 }
4857 } else if (rmx_type == RMX_CENTER) {
4858 dst = src;
e7b07cee 4859 }
e7b07cee 4860
f4791779
HW		 4861 dst.x = (stream->timing.h_addressable - dst.width) / 2;
4862 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 4863
f4791779
HW		 4864 if (dm_state->underscan_enable) {
4865 dst.x += dm_state->underscan_hborder / 2;
4866 dst.y += dm_state->underscan_vborder / 2;
4867 dst.width -= dm_state->underscan_hborder;
4868 dst.height -= dm_state->underscan_vborder;
4869 }
e7b07cee
HW		 4870 }
4871
4872 stream->src = src;
4873 stream->dst = dst;
4874
f1ad2f5e 4875 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 4876 dst.x, dst.y, dst.width, dst.height);
4877
4878}
4879
3ee6b26b 4880static enum dc_color_depth
42ba01fc 4881convert_color_depth_from_display_info(const struct drm_connector *connector,
cbd14ae7 4882 bool is_y420, int requested_bpc)
e7b07cee 4883{
1bc22f20 4884 uint8_t bpc;
01c22997 4885
1bc22f20
SW		 4886 if (is_y420) {
4887 bpc = 8;
4888
4889 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
4890 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
4891 bpc = 16;
4892 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
4893 bpc = 12;
4894 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
4895 bpc = 10;
4896 } else {
4897 bpc = (uint8_t)connector->display_info.bpc;
4898 /* Assume 8 bpc by default if no bpc is specified. */
4899 bpc = bpc ? bpc : 8;
4900 }
e7b07cee 4901
cbd14ae7 4902 if (requested_bpc > 0) {
01c22997
NK		 4903 /*
4904 * Cap display bpc based on the user requested value.
4905 *
4906 * The value for state->max_bpc may not correctly updated
4907 * depending on when the connector gets added to the state
4908 * or if this was called outside of atomic check, so it
4909 * can't be used directly.
4910 */
cbd14ae7 4911 bpc = min_t(u8, bpc, requested_bpc);
01c22997 4912
1825fd34
NK		 4913 /* Round down to the nearest even number. */
4914 bpc = bpc - (bpc & 1);
4915 }
07e3a1cf 4916
e7b07cee
HW		 4917 switch (bpc) {
4918 case 0:
1f6010a9
DF		 4919 /*
4920 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 4921 * EDID revision before 1.4
4922 * TODO: Fix edid parsing
4923 */
4924 return COLOR_DEPTH_888;
4925 case 6:
4926 return COLOR_DEPTH_666;
4927 case 8:
4928 return COLOR_DEPTH_888;
4929 case 10:
4930 return COLOR_DEPTH_101010;
4931 case 12:
4932 return COLOR_DEPTH_121212;
4933 case 14:
4934 return COLOR_DEPTH_141414;
4935 case 16:
4936 return COLOR_DEPTH_161616;
4937 default:
4938 return COLOR_DEPTH_UNDEFINED;
4939 }
4940}
4941
3ee6b26b
AD		 4942static enum dc_aspect_ratio
4943get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 4944{
e11d4147
LSL		 4945 /* 1-1 mapping, since both enums follow the HDMI spec. */
4946 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 4947}
4948
3ee6b26b
AD		 4949static enum dc_color_space
4950get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 4951{
4952 enum dc_color_space color_space = COLOR_SPACE_SRGB;
4953
4954 switch (dc_crtc_timing->pixel_encoding) {
4955 case PIXEL_ENCODING_YCBCR422:
4956 case PIXEL_ENCODING_YCBCR444:
4957 case PIXEL_ENCODING_YCBCR420:
4958 {
4959 /*
4960 * 27030khz is the separation point between HDTV and SDTV
4961 * according to HDMI spec, we use YCbCr709 and YCbCr601
4962 * respectively
4963 */
380604e2 4964 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 4965 if (dc_crtc_timing->flags.Y_ONLY)
4966 color_space =
4967 COLOR_SPACE_YCBCR709_LIMITED;
4968 else
4969 color_space = COLOR_SPACE_YCBCR709;
4970 } else {
4971 if (dc_crtc_timing->flags.Y_ONLY)
4972 color_space =
4973 COLOR_SPACE_YCBCR601_LIMITED;
4974 else
4975 color_space = COLOR_SPACE_YCBCR601;
4976 }
4977
4978 }
4979 break;
4980 case PIXEL_ENCODING_RGB:
4981 color_space = COLOR_SPACE_SRGB;
4982 break;
4983
4984 default:
4985 WARN_ON(1);
4986 break;
4987 }
4988
4989 return color_space;
4990}
4991
ea117312
TA		 4992static bool adjust_colour_depth_from_display_info(
4993 struct dc_crtc_timing *timing_out,
4994 const struct drm_display_info *info)
400443e8 4995{
ea117312 4996 enum dc_color_depth depth = timing_out->display_color_depth;
400443e8 4997 int normalized_clk;
400443e8 4998 do {
380604e2 4999 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 5000 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5001 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5002 normalized_clk /= 2;
5003 /* Adjusting pix clock following on HDMI spec based on colour depth */
ea117312
TA		 5004 switch (depth) {
5005 case COLOR_DEPTH_888:
5006 break;
400443e8
ML		 5007 case COLOR_DEPTH_101010:
5008 normalized_clk = (normalized_clk * 30) / 24;
5009 break;
5010 case COLOR_DEPTH_121212:
5011 normalized_clk = (normalized_clk * 36) / 24;
5012 break;
5013 case COLOR_DEPTH_161616:
5014 normalized_clk = (normalized_clk * 48) / 24;
5015 break;
5016 default:
ea117312
TA		 5017 /* The above depths are the only ones valid for HDMI. */
5018 return false;
400443e8 5019 }
ea117312
TA		 5020 if (normalized_clk <= info->max_tmds_clock) {
5021 timing_out->display_color_depth = depth;
5022 return true;
5023 }
5024 } while (--depth > COLOR_DEPTH_666);
5025 return false;
400443e8 5026}
e7b07cee 5027
42ba01fc
NK		 5028static void fill_stream_properties_from_drm_display_mode(
5029 struct dc_stream_state *stream,
5030 const struct drm_display_mode *mode_in,
5031 const struct drm_connector *connector,
5032 const struct drm_connector_state *connector_state,
cbd14ae7
SW		 5033 const struct dc_stream_state *old_stream,
5034 int requested_bpc)
e7b07cee
HW		 5035{
5036 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 5037 const struct drm_display_info *info = &connector->display_info;
d4252eee 5038 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1cb1d477
WL		 5039 struct hdmi_vendor_infoframe hv_frame;
5040 struct hdmi_avi_infoframe avi_frame;
e7b07cee 5041
acf83f86
WL		 5042 memset(&hv_frame, 0, sizeof(hv_frame));
5043 memset(&avi_frame, 0, sizeof(avi_frame));
5044
e7b07cee
HW		 5045 timing_out->h_border_left = 0;
5046 timing_out->h_border_right = 0;
5047 timing_out->v_border_top = 0;
5048 timing_out->v_border_bottom = 0;
5049 /* TODO: un-hardcode */
fe61a2f1 5050 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 5051 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1 5052 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
d4252eee
SW		 5053 else if (drm_mode_is_420_also(info, mode_in)
5054 && aconnector->force_yuv420_output)
5055 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
fe61a2f1 5056 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
ceb3dbb4 5057 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 5058 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5059 else
5060 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5061
5062 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5063 timing_out->display_color_depth = convert_color_depth_from_display_info(
cbd14ae7
SW		 5064 connector,
5065 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5066 requested_bpc);
e7b07cee
HW		 5067 timing_out->scan_type = SCANNING_TYPE_NODATA;
5068 timing_out->hdmi_vic = 0;
b333730d
BL		 5069
5070 if(old_stream) {
5071 timing_out->vic = old_stream->timing.vic;
5072 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5073 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5074 } else {
5075 timing_out->vic = drm_match_cea_mode(mode_in);
5076 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5077 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5078 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5079 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5080 }
e7b07cee 5081
1cb1d477
WL		 5082 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5083 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5084 timing_out->vic = avi_frame.video_code;
5085 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5086 timing_out->hdmi_vic = hv_frame.vic;
5087 }
5088
6f59f229
AP		 5089 timing_out->h_addressable = mode_in->hdisplay;
5090 timing_out->h_total = mode_in->htotal;
5091 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5092 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5093 timing_out->v_total = mode_in->vtotal;
5094 timing_out->v_addressable = mode_in->vdisplay;
5095 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5096 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5097 timing_out->pix_clk_100hz = mode_in->clock * 10;
5098
e7b07cee 5099 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 5100
5101 stream->output_color_space = get_output_color_space(timing_out);
5102
e43a432c
AK		 5103 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5104 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ea117312
TA		 5105 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5106 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5107 drm_mode_is_420_also(info, mode_in) &&
5108 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5109 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5110 adjust_colour_depth_from_display_info(timing_out, info);
5111 }
5112 }
e7b07cee
HW		 5113}
5114
3ee6b26b
AD		 5115static void fill_audio_info(struct audio_info *audio_info,
5116 const struct drm_connector *drm_connector,
5117 const struct dc_sink *dc_sink)
e7b07cee
HW		 5118{
5119 int i = 0;
5120 int cea_revision = 0;
5121 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5122
5123 audio_info->manufacture_id = edid_caps->manufacturer_id;
5124 audio_info->product_id = edid_caps->product_id;
5125
5126 cea_revision = drm_connector->display_info.cea_rev;
5127
090afc1e 5128 strscpy(audio_info->display_name,
d2b2562c 5129 edid_caps->display_name,
090afc1e 5130 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 5131
b830ebc9 5132 if (cea_revision >= 3) {
e7b07cee
HW		 5133 audio_info->mode_count = edid_caps->audio_mode_count;
5134
5135 for (i = 0; i < audio_info->mode_count; ++i) {
5136 audio_info->modes[i].format_code =
5137 (enum audio_format_code)
5138 (edid_caps->audio_modes[i].format_code);
5139 audio_info->modes[i].channel_count =
5140 edid_caps->audio_modes[i].channel_count;
5141 audio_info->modes[i].sample_rates.all =
5142 edid_caps->audio_modes[i].sample_rate;
5143 audio_info->modes[i].sample_size =
5144 edid_caps->audio_modes[i].sample_size;
5145 }
5146 }
5147
5148 audio_info->flags.all = edid_caps->speaker_flags;
5149
5150 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 5151 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 5152 audio_info->video_latency = drm_connector->video_latency[0];
5153 audio_info->audio_latency = drm_connector->audio_latency[0];
5154 }
5155
5156 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5157
5158}
5159
3ee6b26b
AD		 5160static void
5161copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5162 struct drm_display_mode *dst_mode)
e7b07cee
HW		 5163{
5164 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5165 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5166 dst_mode->crtc_clock = src_mode->crtc_clock;
5167 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5168 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 5169 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 5170 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5171 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5172 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5173 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5174 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5175 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5176 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5177 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5178}
5179
3ee6b26b
AD		 5180static void
5181decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5182 const struct drm_display_mode *native_mode,
5183 bool scale_enabled)
e7b07cee
HW		 5184{
5185 if (scale_enabled) {
5186 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5187 } else if (native_mode->clock == drm_mode->clock &&
5188 native_mode->htotal == drm_mode->htotal &&
5189 native_mode->vtotal == drm_mode->vtotal) {
5190 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5191 } else {
5192 /* no scaling nor amdgpu inserted, no need to patch */
5193 }
5194}
5195
aed15309
ML		 5196static struct dc_sink *
5197create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 5198{
2e0ac3d6 5199 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 5200 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 5201 sink_init_data.link = aconnector->dc_link;
5202 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5203
5204 sink = dc_sink_create(&sink_init_data);
423788c7 5205 if (!sink) {
2e0ac3d6 5206 DRM_ERROR("Failed to create sink!\n");
aed15309 5207 return NULL;
423788c7 5208 }
2e0ac3d6 5209 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 5210
aed15309 5211 return sink;
2e0ac3d6
HW		 5212}
5213
fa2123db
ML		 5214static void set_multisync_trigger_params(
5215 struct dc_stream_state *stream)
5216{
5217 if (stream->triggered_crtc_reset.enabled) {
5218 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
5219 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
5220 }
5221}
5222
5223static void set_master_stream(struct dc_stream_state *stream_set[],
5224 int stream_count)
5225{
5226 int j, highest_rfr = 0, master_stream = 0;
5227
5228 for (j = 0; j < stream_count; j++) {
5229 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5230 int refresh_rate = 0;
5231
380604e2 5232 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 5233 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5234 if (refresh_rate > highest_rfr) {
5235 highest_rfr = refresh_rate;
5236 master_stream = j;
5237 }
5238 }
5239 }
5240 for (j = 0; j < stream_count; j++) {
03736f4c 5241 if (stream_set[j])
fa2123db
ML		 5242 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5243 }
5244}
5245
5246static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5247{
5248 int i = 0;
5249
5250 if (context->stream_count < 2)
5251 return;
5252 for (i = 0; i < context->stream_count ; i++) {
5253 if (!context->streams[i])
5254 continue;
1f6010a9
DF		 5255 /*
5256 * TODO: add a function to read AMD VSDB bits and set
fa2123db 5257 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 5258 * For now it's set to false
fa2123db
ML		 5259 */
5260 set_multisync_trigger_params(context->streams[i]);
5261 }
5262 set_master_stream(context->streams, context->stream_count);
5263}
5264
d10cd527
AP		 5265static struct drm_display_mode *
5266get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5267 bool use_probed_modes)
5268{
5269 struct drm_display_mode *m, *m_pref = NULL;
5270 u16 current_refresh, highest_refresh;
5271 struct list_head *list_head = use_probed_modes ?
5272 &aconnector->base.probed_modes :
5273 &aconnector->base.modes;
5274
5275 if (aconnector->freesync_vid_base.clock != 0)
5276 return &aconnector->freesync_vid_base;
5277
5278 /* Find the preferred mode */
5279 list_for_each_entry (m, list_head, head) {
5280 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5281 m_pref = m;
5282 break;
5283 }
5284 }
5285
5286 if (!m_pref) {
5287 /* Probably an EDID with no preferred mode. Fallback to first entry */
5288 m_pref = list_first_entry_or_null(
5289 &aconnector->base.modes, struct drm_display_mode, head);
5290 if (!m_pref) {
5291 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5292 return NULL;
5293 }
5294 }
5295
5296 highest_refresh = drm_mode_vrefresh(m_pref);
5297
5298 /*
5299 * Find the mode with highest refresh rate with same resolution.
5300 * For some monitors, preferred mode is not the mode with highest
5301 * supported refresh rate.
5302 */
5303 list_for_each_entry (m, list_head, head) {
5304 current_refresh = drm_mode_vrefresh(m);
5305
5306 if (m->hdisplay == m_pref->hdisplay &&
5307 m->vdisplay == m_pref->vdisplay &&
5308 highest_refresh < current_refresh) {
5309 highest_refresh = current_refresh;
5310 m_pref = m;
5311 }
5312 }
5313
5314 aconnector->freesync_vid_base = *m_pref;
5315 return m_pref;
5316}
5317
6f59f229
AP		 5318static bool is_freesync_video_mode(struct drm_display_mode *mode,
5319 struct amdgpu_dm_connector *aconnector)
5320{
5321 struct drm_display_mode *high_mode;
5322 int timing_diff;
5323
5324 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5325 if (!high_mode || !mode)
5326 return false;
5327
5328 timing_diff = high_mode->vtotal - mode->vtotal;
5329
5330 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5331 high_mode->hdisplay != mode->hdisplay ||
5332 high_mode->vdisplay != mode->vdisplay ||
5333 high_mode->hsync_start != mode->hsync_start ||
5334 high_mode->hsync_end != mode->hsync_end ||
5335 high_mode->htotal != mode->htotal ||
5336 high_mode->hskew != mode->hskew ||
5337 high_mode->vscan != mode->vscan ||
5338 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5339 high_mode->vsync_end - mode->vsync_end != timing_diff)
5340 return false;
5341 else
5342 return true;
5343}
5344
3ee6b26b
AD		 5345static struct dc_stream_state *
5346create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5347 const struct drm_display_mode *drm_mode,
b333730d 5348 const struct dm_connector_state *dm_state,
cbd14ae7
SW		 5349 const struct dc_stream_state *old_stream,
5350 int requested_bpc)
e7b07cee
HW		 5351{
5352 struct drm_display_mode *preferred_mode = NULL;
391ef035 5353 struct drm_connector *drm_connector;
42ba01fc
NK		 5354 const struct drm_connector_state *con_state =
5355 dm_state ? &dm_state->base : NULL;
0971c40e 5356 struct dc_stream_state *stream = NULL;
e7b07cee 5357 struct drm_display_mode mode = *drm_mode;
6f59f229
AP		 5358 struct drm_display_mode saved_mode;
5359 struct drm_display_mode *freesync_mode = NULL;
e7b07cee 5360 bool native_mode_found = false;
6f59f229 5361 bool recalculate_timing = dm_state ? (dm_state->scaling != RMX_OFF) : false;
b333730d 5362 int mode_refresh;
58124bf8 5363 int preferred_refresh = 0;
defeb878 5364#if defined(CONFIG_DRM_AMD_DC_DCN)
df2f1015
DF		 5365 struct dsc_dec_dpcd_caps dsc_caps;
5366 uint32_t link_bandwidth_kbps;
7c431455 5367#endif
aed15309 5368 struct dc_sink *sink = NULL;
6f59f229
AP		 5369
5370 memset(&saved_mode, 0, sizeof(saved_mode));
5371
b830ebc9 5372 if (aconnector == NULL) {
e7b07cee 5373 DRM_ERROR("aconnector is NULL!\n");
64245fa7 5374 return stream;
e7b07cee
HW		 5375 }
5376
e7b07cee 5377 drm_connector = &aconnector->base;
2e0ac3d6 5378
f4ac176e 5379 if (!aconnector->dc_sink) {
e3fa5c4c
JFZ		 5380 sink = create_fake_sink(aconnector);
5381 if (!sink)
5382 return stream;
aed15309
ML		 5383 } else {
5384 sink = aconnector->dc_sink;
dcd5fb82 5385 dc_sink_retain(sink);
f4ac176e 5386 }
2e0ac3d6 5387
aed15309 5388 stream = dc_create_stream_for_sink(sink);
4562236b 5389
b830ebc9 5390 if (stream == NULL) {
e7b07cee 5391 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 5392 goto finish;
e7b07cee
HW		 5393 }
5394
ceb3dbb4
JL		 5395 stream->dm_stream_context = aconnector;
5396
4a36fcba
WL		 5397 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5398 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5399
e7b07cee
HW		 5400 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5401 /* Search for preferred mode */
5402 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5403 native_mode_found = true;
5404 break;
5405 }
5406 }
5407 if (!native_mode_found)
5408 preferred_mode = list_first_entry_or_null(
5409 &aconnector->base.modes,
5410 struct drm_display_mode,
5411 head);
5412
b333730d
BL		 5413 mode_refresh = drm_mode_vrefresh(&mode);
5414
b830ebc9 5415 if (preferred_mode == NULL) {
1f6010a9
DF		 5416 /*
5417 * This may not be an error, the use case is when we have no
e7b07cee
HW		 5418 * usermode calls to reset and set mode upon hotplug. In this
5419 * case, we call set mode ourselves to restore the previous mode
5420 * and the modelist may not be filled in in time.
5421 */
f1ad2f5e 5422 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee 5423 } else {
6f59f229
AP		 5424 recalculate_timing |= amdgpu_freesync_vid_mode &&
5425 is_freesync_video_mode(&mode, aconnector);
5426 if (recalculate_timing) {
5427 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
5428 saved_mode = mode;
5429 mode = *freesync_mode;
5430 } else {
5431 decide_crtc_timing_for_drm_display_mode(
e7b07cee 5432 &mode, preferred_mode,
f4791779 5433 dm_state ? (dm_state->scaling != RMX_OFF) : false);
6f59f229
AP		 5434 }
5435
58124bf8 5436 preferred_refresh = drm_mode_vrefresh(preferred_mode);
e7b07cee
HW		 5437 }
5438
6f59f229
AP		 5439 if (recalculate_timing)
5440 drm_mode_set_crtcinfo(&saved_mode, 0);
5441 else
f783577c
JFZ		 5442 drm_mode_set_crtcinfo(&mode, 0);
5443
6f59f229 5444 /*
b333730d
BL		 5445 * If scaling is enabled and refresh rate didn't change
5446 * we copy the vic and polarities of the old timings
5447 */
6f59f229
AP		 5448 if (!recalculate_timing || mode_refresh != preferred_refresh)
5449 fill_stream_properties_from_drm_display_mode(
5450 stream, &mode, &aconnector->base, con_state, NULL,
5451 requested_bpc);
b333730d 5452 else
6f59f229
AP		 5453 fill_stream_properties_from_drm_display_mode(
5454 stream, &mode, &aconnector->base, con_state, old_stream,
5455 requested_bpc);
b333730d 5456
df2f1015
DF		 5457 stream->timing.flags.DSC = 0;
5458
5459 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
defeb878 5460#if defined(CONFIG_DRM_AMD_DC_DCN)
2af0f378
NC		 5461 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5462 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
6d824ed5 5463 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
df2f1015
DF		 5464 &dsc_caps);
5465 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5466 dc_link_get_link_cap(aconnector->dc_link));
5467
0749ddeb 5468 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) {
bcc6aa61 5469 /* Set DSC policy according to dsc_clock_en */
0749ddeb
EB		 5470 dc_dsc_policy_set_enable_dsc_when_not_needed(
5471 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
bcc6aa61 5472
0417df16 5473 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
df2f1015 5474 &dsc_caps,
0417df16 5475 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
9abdf392 5476 0,
df2f1015
DF		 5477 link_bandwidth_kbps,
5478 &stream->timing,
5479 &stream->timing.dsc_cfg))
5480 stream->timing.flags.DSC = 1;
27e84dd7 5481 /* Overwrite the stream flag if DSC is enabled through debugfs */
0749ddeb 5482 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
097e6d98 5483 stream->timing.flags.DSC = 1;
734e4c97 5484
28b2f656
EB		 5485 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5486 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
734e4c97 5487
28b2f656
EB		 5488 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5489 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5268bf13
EB		 5490
5491 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5492 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
097e6d98 5493 }
39a4eb85 5494#endif
df2f1015 5495 }
39a4eb85 5496
e7b07cee
HW		 5497 update_stream_scaling_settings(&mode, dm_state, stream);
5498
5499 fill_audio_info(
5500 &stream->audio_info,
5501 drm_connector,
aed15309 5502 sink);
e7b07cee 5503
ceb3dbb4 5504 update_stream_signal(stream, sink);
9182b4cb 5505
d832fc3b 5506 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
75f77aaf
WL		 5507 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5508
8a488f5d
RL		 5509 if (stream->link->psr_settings.psr_feature_enabled) {
5510 //
5511 // should decide stream support vsc sdp colorimetry capability
5512 // before building vsc info packet
5513 //
5514 stream->use_vsc_sdp_for_colorimetry = false;
5515 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5516 stream->use_vsc_sdp_for_colorimetry =
5517 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5518 } else {
5519 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5520 stream->use_vsc_sdp_for_colorimetry = true;
8c322309 5521 }
8a488f5d 5522 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
8c322309 5523 }
aed15309 5524finish:
dcd5fb82 5525 dc_sink_release(sink);
9e3efe3e 5526
e7b07cee
HW		 5527 return stream;
5528}
5529
7578ecda 5530static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 5531{
5532 drm_crtc_cleanup(crtc);
5533 kfree(crtc);
5534}
5535
5536static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 5537 struct drm_crtc_state *state)
e7b07cee
HW		 5538{
5539 struct dm_crtc_state *cur = to_dm_crtc_state(state);
5540
5541 /* TODO Destroy dc_stream objects are stream object is flattened */
5542 if (cur->stream)
5543 dc_stream_release(cur->stream);
5544
5545
5546 __drm_atomic_helper_crtc_destroy_state(state);
5547
5548
5549 kfree(state);
5550}
5551
5552static void dm_crtc_reset_state(struct drm_crtc *crtc)
5553{
5554 struct dm_crtc_state *state;
5555
5556 if (crtc->state)
5557 dm_crtc_destroy_state(crtc, crtc->state);
5558
5559 state = kzalloc(sizeof(*state), GFP_KERNEL);
5560 if (WARN_ON(!state))
5561 return;
5562
1f8a52ec 5563 __drm_atomic_helper_crtc_reset(crtc, &state->base);
e7b07cee
HW		 5564}
5565
5566static struct drm_crtc_state *
5567dm_crtc_duplicate_state(struct drm_crtc *crtc)
5568{
5569 struct dm_crtc_state *state, *cur;
5570
5571 cur = to_dm_crtc_state(crtc->state);
5572
5573 if (WARN_ON(!crtc->state))
5574 return NULL;
5575
2004f45e 5576 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 5577 if (!state)
5578 return NULL;
e7b07cee
HW		 5579
5580 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
5581
5582 if (cur->stream) {
5583 state->stream = cur->stream;
5584 dc_stream_retain(state->stream);
5585 }
5586
d6ef9b41 5587 state->active_planes = cur->active_planes;
98e6436d 5588 state->vrr_infopacket = cur->vrr_infopacket;
c1ee92f9 5589 state->abm_level = cur->abm_level;
bb47de73
NK		 5590 state->vrr_supported = cur->vrr_supported;
5591 state->freesync_config = cur->freesync_config;
cf020d49
NK		 5592 state->cm_has_degamma = cur->cm_has_degamma;
5593 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
e7b07cee
HW		 5594 /* TODO Duplicate dc_stream after objects are stream object is flattened */
5595
5596 return &state->base;
5597}
5598
86bc2219
WL		 5599#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
5600int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
5601{
5602 crtc_debugfs_init(crtc);
5603
5604 return 0;
5605}
5606#endif
5607
d2574c33
MK		 5608static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
5609{
5610 enum dc_irq_source irq_source;
5611 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
1348969a 5612 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
d2574c33
MK		 5613 int rc;
5614
5615 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
5616
5617 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
5618
5619 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
5620 acrtc->crtc_id, enable ? "en" : "dis", rc);
5621 return rc;
5622}
589d2739
HW		 5623
5624static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
5625{
5626 enum dc_irq_source irq_source;
5627 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
1348969a 5628 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
d2574c33 5629 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
d7faf6f5 5630#if defined(CONFIG_DRM_AMD_DC_DCN)
71338cb4 5631 struct amdgpu_display_manager *dm = &adev->dm;
d7faf6f5
QZ		 5632 unsigned long flags;
5633#endif
d2574c33
MK		 5634 int rc = 0;
5635
5636 if (enable) {
5637 /* vblank irq on -> Only need vupdate irq in vrr mode */
5638 if (amdgpu_dm_vrr_active(acrtc_state))
5639 rc = dm_set_vupdate_irq(crtc, true);
5640 } else {
5641 /* vblank irq off -> vupdate irq off */
5642 rc = dm_set_vupdate_irq(crtc, false);
5643 }
5644
5645 if (rc)
5646 return rc;
589d2739
HW		 5647
5648 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
71338cb4
BL		 5649
5650 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
5651 return -EBUSY;
5652
98ab5f35
BL		 5653 if (amdgpu_in_reset(adev))
5654 return 0;
5655
4928b480 5656#if defined(CONFIG_DRM_AMD_DC_DCN)
d7faf6f5
QZ		 5657 spin_lock_irqsave(&dm->vblank_lock, flags);
5658 dm->vblank_workqueue->dm = dm;
5659 dm->vblank_workqueue->otg_inst = acrtc->otg_inst;
5660 dm->vblank_workqueue->enable = enable;
5661 spin_unlock_irqrestore(&dm->vblank_lock, flags);
5662 schedule_work(&dm->vblank_workqueue->mall_work);
4928b480 5663#endif
71338cb4 5664
71338cb4 5665 return 0;
589d2739
HW		 5666}
5667
5668static int dm_enable_vblank(struct drm_crtc *crtc)
5669{
5670 return dm_set_vblank(crtc, true);
5671}
5672
5673static void dm_disable_vblank(struct drm_crtc *crtc)
5674{
5675 dm_set_vblank(crtc, false);
5676}
5677
e7b07cee
HW		 5678/* Implemented only the options currently availible for the driver */
5679static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
5680 .reset = dm_crtc_reset_state,
5681 .destroy = amdgpu_dm_crtc_destroy,
e7b07cee
HW		 5682 .set_config = drm_atomic_helper_set_config,
5683 .page_flip = drm_atomic_helper_page_flip,
5684 .atomic_duplicate_state = dm_crtc_duplicate_state,
5685 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 5686 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 5687 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
8fb843d1 5688 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
e3eff4b5 5689 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
589d2739
HW		 5690 .enable_vblank = dm_enable_vblank,
5691 .disable_vblank = dm_disable_vblank,
e3eff4b5 5692 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
86bc2219
WL		 5693#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
5694 .late_register = amdgpu_dm_crtc_late_register,
5695#endif
e7b07cee
HW		 5696};
5697
5698static enum drm_connector_status
5699amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5700{
5701 bool connected;
c84dec2f 5702 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 5703
1f6010a9
DF		 5704 /*
5705 * Notes:
e7b07cee
HW		 5706 * 1. This interface is NOT called in context of HPD irq.
5707 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 5708 * makes it a bad place for *any* MST-related activity.
5709 */
e7b07cee 5710
8580d60b
HW		 5711 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
5712 !aconnector->fake_enable)
e7b07cee
HW		 5713 connected = (aconnector->dc_sink != NULL);
5714 else
5715 connected = (aconnector->base.force == DRM_FORCE_ON);
5716
0f877894
OV		 5717 update_subconnector_property(aconnector);
5718
e7b07cee
HW		 5719 return (connected ? connector_status_connected :
5720 connector_status_disconnected);
5721}
5722
3ee6b26b
AD		 5723int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
5724 struct drm_connector_state *connector_state,
5725 struct drm_property *property,
5726 uint64_t val)
e7b07cee
HW		 5727{
5728 struct drm_device *dev = connector->dev;
1348969a 5729 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 5730 struct dm_connector_state *dm_old_state =
5731 to_dm_connector_state(connector->state);
5732 struct dm_connector_state *dm_new_state =
5733 to_dm_connector_state(connector_state);
5734
5735 int ret = -EINVAL;
5736
5737 if (property == dev->mode_config.scaling_mode_property) {
5738 enum amdgpu_rmx_type rmx_type;
5739
5740 switch (val) {
5741 case DRM_MODE_SCALE_CENTER:
5742 rmx_type = RMX_CENTER;
5743 break;
5744 case DRM_MODE_SCALE_ASPECT:
5745 rmx_type = RMX_ASPECT;
5746 break;
5747 case DRM_MODE_SCALE_FULLSCREEN:
5748 rmx_type = RMX_FULL;
5749 break;
5750 case DRM_MODE_SCALE_NONE:
5751 default:
5752 rmx_type = RMX_OFF;
5753 break;
5754 }
5755
5756 if (dm_old_state->scaling == rmx_type)
5757 return 0;
5758
5759 dm_new_state->scaling = rmx_type;
5760 ret = 0;
5761 } else if (property == adev->mode_info.underscan_hborder_property) {
5762 dm_new_state->underscan_hborder = val;
5763 ret = 0;
5764 } else if (property == adev->mode_info.underscan_vborder_property) {
5765 dm_new_state->underscan_vborder = val;
5766 ret = 0;
5767 } else if (property == adev->mode_info.underscan_property) {
5768 dm_new_state->underscan_enable = val;
5769 ret = 0;
c1ee92f9
DF		 5770 } else if (property == adev->mode_info.abm_level_property) {
5771 dm_new_state->abm_level = val;
5772 ret = 0;
e7b07cee
HW		 5773 }
5774
5775 return ret;
5776}
5777
3ee6b26b
AD		 5778int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
5779 const struct drm_connector_state *state,
5780 struct drm_property *property,
5781 uint64_t *val)
e7b07cee
HW		 5782{
5783 struct drm_device *dev = connector->dev;
1348969a 5784 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 5785 struct dm_connector_state *dm_state =
5786 to_dm_connector_state(state);
5787 int ret = -EINVAL;
5788
5789 if (property == dev->mode_config.scaling_mode_property) {
5790 switch (dm_state->scaling) {
5791 case RMX_CENTER:
5792 *val = DRM_MODE_SCALE_CENTER;
5793 break;
5794 case RMX_ASPECT:
5795 *val = DRM_MODE_SCALE_ASPECT;
5796 break;
5797 case RMX_FULL:
5798 *val = DRM_MODE_SCALE_FULLSCREEN;
5799 break;
5800 case RMX_OFF:
5801 default:
5802 *val = DRM_MODE_SCALE_NONE;
5803 break;
5804 }
5805 ret = 0;
5806 } else if (property == adev->mode_info.underscan_hborder_property) {
5807 *val = dm_state->underscan_hborder;
5808 ret = 0;
5809 } else if (property == adev->mode_info.underscan_vborder_property) {
5810 *val = dm_state->underscan_vborder;
5811 ret = 0;
5812 } else if (property == adev->mode_info.underscan_property) {
5813 *val = dm_state->underscan_enable;
5814 ret = 0;
c1ee92f9
DF		 5815 } else if (property == adev->mode_info.abm_level_property) {
5816 *val = dm_state->abm_level;
5817 ret = 0;
e7b07cee 5818 }
c1ee92f9 5819
e7b07cee
HW		 5820 return ret;
5821}
5822
526c654a
ED		 5823static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
5824{
5825 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
5826
5827 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
5828}
5829
7578ecda 5830static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 5831{
c84dec2f 5832 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 5833 const struct dc_link *link = aconnector->dc_link;
1348969a 5834 struct amdgpu_device *adev = drm_to_adev(connector->dev);
e7b07cee 5835 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 5836
5dff80bd
AG		 5837 /*
5838 * Call only if mst_mgr was iniitalized before since it's not done
5839 * for all connector types.
5840 */
5841 if (aconnector->mst_mgr.dev)
5842 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
5843
e7b07cee
HW		 5844#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
5845 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
5846
89fc8d4e 5847 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 5848 link->type != dc_connection_none &&
5849 dm->backlight_dev) {
5850 backlight_device_unregister(dm->backlight_dev);
5851 dm->backlight_dev = NULL;
e7b07cee
HW		 5852 }
5853#endif
dcd5fb82
MF		 5854
5855 if (aconnector->dc_em_sink)
5856 dc_sink_release(aconnector->dc_em_sink);
5857 aconnector->dc_em_sink = NULL;
5858 if (aconnector->dc_sink)
5859 dc_sink_release(aconnector->dc_sink);
5860 aconnector->dc_sink = NULL;
5861
e86e8947 5862 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 5863 drm_connector_unregister(connector);
5864 drm_connector_cleanup(connector);
526c654a
ED		 5865 if (aconnector->i2c) {
5866 i2c_del_adapter(&aconnector->i2c->base);
5867 kfree(aconnector->i2c);
5868 }
7daec99f 5869 kfree(aconnector->dm_dp_aux.aux.name);
526c654a 5870
e7b07cee
HW		 5871 kfree(connector);
5872}
5873
5874void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
5875{
5876 struct dm_connector_state *state =
5877 to_dm_connector_state(connector->state);
5878
df099b9b
LSL		 5879 if (connector->state)
5880 __drm_atomic_helper_connector_destroy_state(connector->state);
5881
e7b07cee
HW		 5882 kfree(state);
5883
5884 state = kzalloc(sizeof(*state), GFP_KERNEL);
5885
5886 if (state) {
5887 state->scaling = RMX_OFF;
5888 state->underscan_enable = false;
5889 state->underscan_hborder = 0;
5890 state->underscan_vborder = 0;
01933ba4 5891 state->base.max_requested_bpc = 8;
3261e013
ML		 5892 state->vcpi_slots = 0;
5893 state->pbn = 0;
c3e50f89
NK		 5894 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5895 state->abm_level = amdgpu_dm_abm_level;
5896
df099b9b 5897 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 5898 }
5899}
5900
3ee6b26b
AD		 5901struct drm_connector_state *
5902amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 5903{
5904 struct dm_connector_state *state =
5905 to_dm_connector_state(connector->state);
5906
5907 struct dm_connector_state *new_state =
5908 kmemdup(state, sizeof(*state), GFP_KERNEL);
5909
98e6436d
AK		 5910 if (!new_state)
5911 return NULL;
e7b07cee 5912
98e6436d
AK		 5913 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
5914
5915 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 5916 new_state->abm_level = state->abm_level;
922454c2
NK		 5917 new_state->scaling = state->scaling;
5918 new_state->underscan_enable = state->underscan_enable;
5919 new_state->underscan_hborder = state->underscan_hborder;
5920 new_state->underscan_vborder = state->underscan_vborder;
3261e013
ML		 5921 new_state->vcpi_slots = state->vcpi_slots;
5922 new_state->pbn = state->pbn;
98e6436d 5923 return &new_state->base;
e7b07cee
HW		 5924}
5925
14f04fa4
AD		 5926static int
5927amdgpu_dm_connector_late_register(struct drm_connector *connector)
5928{
5929 struct amdgpu_dm_connector *amdgpu_dm_connector =
5930 to_amdgpu_dm_connector(connector);
00a8037e 5931 int r;
14f04fa4 5932
00a8037e
AD		 5933 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
5934 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
5935 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
5936 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
5937 if (r)
5938 return r;
5939 }
5940
5941#if defined(CONFIG_DEBUG_FS)
14f04fa4
AD		 5942 connector_debugfs_init(amdgpu_dm_connector);
5943#endif
5944
5945 return 0;
5946}
5947
e7b07cee
HW		 5948static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
5949 .reset = amdgpu_dm_connector_funcs_reset,
5950 .detect = amdgpu_dm_connector_detect,
5951 .fill_modes = drm_helper_probe_single_connector_modes,
5952 .destroy = amdgpu_dm_connector_destroy,
5953 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
5954 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5955 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
526c654a 5956 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
14f04fa4 5957 .late_register = amdgpu_dm_connector_late_register,
526c654a 5958 .early_unregister = amdgpu_dm_connector_unregister
e7b07cee
HW		 5959};
5960
e7b07cee
HW		 5961static int get_modes(struct drm_connector *connector)
5962{
5963 return amdgpu_dm_connector_get_modes(connector);
5964}
5965
c84dec2f 5966static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 5967{
5968 struct dc_sink_init_data init_params = {
5969 .link = aconnector->dc_link,
5970 .sink_signal = SIGNAL_TYPE_VIRTUAL
5971 };
70e8ffc5 5972 struct edid *edid;
e7b07cee 5973
a89ff457 5974 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 5975 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
5976 aconnector->base.name);
5977
5978 aconnector->base.force = DRM_FORCE_OFF;
5979 aconnector->base.override_edid = false;
5980 return;
5981 }
5982
70e8ffc5
HW		 5983 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
5984
e7b07cee
HW		 5985 aconnector->edid = edid;
5986
5987 aconnector->dc_em_sink = dc_link_add_remote_sink(
5988 aconnector->dc_link,
5989 (uint8_t *)edid,
5990 (edid->extensions + 1) * EDID_LENGTH,
5991 &init_params);
5992
dcd5fb82 5993 if (aconnector->base.force == DRM_FORCE_ON) {
e7b07cee
HW		 5994 aconnector->dc_sink = aconnector->dc_link->local_sink ?
5995 aconnector->dc_link->local_sink :
5996 aconnector->dc_em_sink;
dcd5fb82
MF		 5997 dc_sink_retain(aconnector->dc_sink);
5998 }
e7b07cee
HW		 5999}
6000
c84dec2f 6001static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 6002{
6003 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6004
1f6010a9
DF		 6005 /*
6006 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 6007 * Those settings have to be != 0 to get initial modeset
6008 */
6009 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6010 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6011 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6012 }
6013
6014
6015 aconnector->base.override_edid = true;
6016 create_eml_sink(aconnector);
6017}
6018
cbd14ae7
SW		 6019static struct dc_stream_state *
6020create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6021 const struct drm_display_mode *drm_mode,
6022 const struct dm_connector_state *dm_state,
6023 const struct dc_stream_state *old_stream)
6024{
6025 struct drm_connector *connector = &aconnector->base;
1348969a 6026 struct amdgpu_device *adev = drm_to_adev(connector->dev);
cbd14ae7 6027 struct dc_stream_state *stream;
4b7da34b
SW		 6028 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6029 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
cbd14ae7
SW		 6030 enum dc_status dc_result = DC_OK;
6031
6032 do {
6033 stream = create_stream_for_sink(aconnector, drm_mode,
6034 dm_state, old_stream,
6035 requested_bpc);
6036 if (stream == NULL) {
6037 DRM_ERROR("Failed to create stream for sink!\n");
6038 break;
6039 }
6040
6041 dc_result = dc_validate_stream(adev->dm.dc, stream);
6042
6043 if (dc_result != DC_OK) {
74a16675 6044 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
cbd14ae7
SW		 6045 drm_mode->hdisplay,
6046 drm_mode->vdisplay,
6047 drm_mode->clock,
74a16675
RS		 6048 dc_result,
6049 dc_status_to_str(dc_result));
cbd14ae7
SW		 6050
6051 dc_stream_release(stream);
6052 stream = NULL;
6053 requested_bpc -= 2; /* lower bpc to retry validation */
6054 }
6055
6056 } while (stream == NULL && requested_bpc >= 6);
6057
6058 return stream;
6059}
6060
ba9ca088 6061enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 6062 struct drm_display_mode *mode)
e7b07cee
HW		 6063{
6064 int result = MODE_ERROR;
6065 struct dc_sink *dc_sink;
e7b07cee 6066 /* TODO: Unhardcode stream count */
0971c40e 6067 struct dc_stream_state *stream;
c84dec2f 6068 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 6069
6070 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6071 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6072 return result;
6073
1f6010a9
DF		 6074 /*
6075 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 6076 * EDID mgmt
6077 */
6078 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6079 !aconnector->dc_em_sink)
6080 handle_edid_mgmt(aconnector);
6081
c84dec2f 6082 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 6083
ad975f44
VL		 6084 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6085 aconnector->base.force != DRM_FORCE_ON) {
e7b07cee
HW		 6086 DRM_ERROR("dc_sink is NULL!\n");
6087 goto fail;
6088 }
6089
cbd14ae7
SW		 6090 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6091 if (stream) {
6092 dc_stream_release(stream);
e7b07cee 6093 result = MODE_OK;
cbd14ae7 6094 }
e7b07cee
HW		 6095
6096fail:
6097 /* TODO: error handling*/
6098 return result;
6099}
6100
88694af9
NK		 6101static int fill_hdr_info_packet(const struct drm_connector_state *state,
6102 struct dc_info_packet *out)
6103{
6104 struct hdmi_drm_infoframe frame;
6105 unsigned char buf[30]; /* 26 + 4 */
6106 ssize_t len;
6107 int ret, i;
6108
6109 memset(out, 0, sizeof(*out));
6110
6111 if (!state->hdr_output_metadata)
6112 return 0;
6113
6114 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6115 if (ret)
6116 return ret;
6117
6118 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6119 if (len < 0)
6120 return (int)len;
6121
6122 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6123 if (len != 30)
6124 return -EINVAL;
6125
6126 /* Prepare the infopacket for DC. */
6127 switch (state->connector->connector_type) {
6128 case DRM_MODE_CONNECTOR_HDMIA:
6129 out->hb0 = 0x87; /* type */
6130 out->hb1 = 0x01; /* version */
6131 out->hb2 = 0x1A; /* length */
6132 out->sb[0] = buf[3]; /* checksum */
6133 i = 1;
6134 break;
6135
6136 case DRM_MODE_CONNECTOR_DisplayPort:
6137 case DRM_MODE_CONNECTOR_eDP:
6138 out->hb0 = 0x00; /* sdp id, zero */
6139 out->hb1 = 0x87; /* type */
6140 out->hb2 = 0x1D; /* payload len - 1 */
6141 out->hb3 = (0x13 << 2); /* sdp version */
6142 out->sb[0] = 0x01; /* version */
6143 out->sb[1] = 0x1A; /* length */
6144 i = 2;
6145 break;
6146
6147 default:
6148 return -EINVAL;
6149 }
6150
6151 memcpy(&out->sb[i], &buf[4], 26);
6152 out->valid = true;
6153
6154 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6155 sizeof(out->sb), false);
6156
6157 return 0;
6158}
6159
6160static bool
6161is_hdr_metadata_different(const struct drm_connector_state *old_state,
6162 const struct drm_connector_state *new_state)
6163{
6164 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
6165 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
6166
6167 if (old_blob != new_blob) {
6168 if (old_blob && new_blob &&
6169 old_blob->length == new_blob->length)
6170 return memcmp(old_blob->data, new_blob->data,
6171 old_blob->length);
6172
6173 return true;
6174 }
6175
6176 return false;
6177}
6178
6179static int
6180amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
51e857af 6181 struct drm_atomic_state *state)
88694af9 6182{
51e857af
SP		 6183 struct drm_connector_state *new_con_state =
6184 drm_atomic_get_new_connector_state(state, conn);
88694af9
NK		 6185 struct drm_connector_state *old_con_state =
6186 drm_atomic_get_old_connector_state(state, conn);
6187 struct drm_crtc *crtc = new_con_state->crtc;
6188 struct drm_crtc_state *new_crtc_state;
6189 int ret;
6190
e8a98235
RS		 6191 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6192
88694af9
NK		 6193 if (!crtc)
6194 return 0;
6195
6196 if (is_hdr_metadata_different(old_con_state, new_con_state)) {
6197 struct dc_info_packet hdr_infopacket;
6198
6199 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6200 if (ret)
6201 return ret;
6202
6203 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6204 if (IS_ERR(new_crtc_state))
6205 return PTR_ERR(new_crtc_state);
6206
6207 /*
6208 * DC considers the stream backends changed if the
6209 * static metadata changes. Forcing the modeset also
6210 * gives a simple way for userspace to switch from
b232d4ed
NK		 6211 * 8bpc to 10bpc when setting the metadata to enter
6212 * or exit HDR.
6213 *
6214 * Changing the static metadata after it's been
6215 * set is permissible, however. So only force a
6216 * modeset if we're entering or exiting HDR.
88694af9 6217 */
b232d4ed
NK		 6218 new_crtc_state->mode_changed =
6219 !old_con_state->hdr_output_metadata ||
6220 !new_con_state->hdr_output_metadata;
88694af9
NK		 6221 }
6222
6223 return 0;
6224}
6225
e7b07cee
HW		 6226static const struct drm_connector_helper_funcs
6227amdgpu_dm_connector_helper_funcs = {
6228 /*
1f6010a9 6229 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 6230 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 6231 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 6232 * in get_modes call back, not just return the modes count
6233 */
e7b07cee
HW		 6234 .get_modes = get_modes,
6235 .mode_valid = amdgpu_dm_connector_mode_valid,
88694af9 6236 .atomic_check = amdgpu_dm_connector_atomic_check,
e7b07cee
HW		 6237};
6238
6239static void dm_crtc_helper_disable(struct drm_crtc *crtc)
6240{
6241}
6242
d6ef9b41 6243static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
c14a005c
NK		 6244{
6245 struct drm_atomic_state *state = new_crtc_state->state;
6246 struct drm_plane *plane;
6247 int num_active = 0;
6248
6249 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
6250 struct drm_plane_state *new_plane_state;
6251
6252 /* Cursor planes are "fake". */
6253 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6254 continue;
6255
6256 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
6257
6258 if (!new_plane_state) {
6259 /*
6260 * The plane is enable on the CRTC and hasn't changed
6261 * state. This means that it previously passed
6262 * validation and is therefore enabled.
6263 */
6264 num_active += 1;
6265 continue;
6266 }
6267
6268 /* We need a framebuffer to be considered enabled. */
6269 num_active += (new_plane_state->fb != NULL);
6270 }
6271
d6ef9b41
NK		 6272 return num_active;
6273}
6274
8fe684e9
NK		 6275static void dm_update_crtc_active_planes(struct drm_crtc *crtc,
6276 struct drm_crtc_state *new_crtc_state)
d6ef9b41
NK		 6277{
6278 struct dm_crtc_state *dm_new_crtc_state =
6279 to_dm_crtc_state(new_crtc_state);
6280
6281 dm_new_crtc_state->active_planes = 0;
d6ef9b41
NK		 6282
6283 if (!dm_new_crtc_state->stream)
6284 return;
6285
6286 dm_new_crtc_state->active_planes =
6287 count_crtc_active_planes(new_crtc_state);
c14a005c
NK		 6288}
6289
3ee6b26b 6290static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
29b77ad7 6291 struct drm_atomic_state *state)
e7b07cee 6292{
29b77ad7
MR		 6293 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
6294 crtc);
1348969a 6295 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
e7b07cee 6296 struct dc *dc = adev->dm.dc;
29b77ad7 6297 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
e7b07cee
HW		 6298 int ret = -EINVAL;
6299
5b8c5969 6300 trace_amdgpu_dm_crtc_atomic_check(crtc_state);
e8a98235 6301
29b77ad7 6302 dm_update_crtc_active_planes(crtc, crtc_state);
d6ef9b41 6303
9b690ef3 6304 if (unlikely(!dm_crtc_state->stream &&
29b77ad7 6305 modeset_required(crtc_state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 6306 WARN_ON(1);
6307 return ret;
6308 }
6309
bc92c065 6310 /*
b836a274
MD		 6311 * We require the primary plane to be enabled whenever the CRTC is, otherwise
6312 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
6313 * planes are disabled, which is not supported by the hardware. And there is legacy
6314 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
bc92c065 6315 */
29b77ad7 6316 if (crtc_state->enable &&
ea9522f5
SS		 6317 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
6318 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
c14a005c 6319 return -EINVAL;
ea9522f5 6320 }
c14a005c 6321
b836a274
MD		 6322 /* In some use cases, like reset, no stream is attached */
6323 if (!dm_crtc_state->stream)
6324 return 0;
6325
62c933f9 6326 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 6327 return 0;
6328
ea9522f5 6329 DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
e7b07cee
HW		 6330 return ret;
6331}
6332
3ee6b26b
AD		 6333static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
6334 const struct drm_display_mode *mode,
6335 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 6336{
6337 return true;
6338}
6339
6340static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
6341 .disable = dm_crtc_helper_disable,
6342 .atomic_check = dm_crtc_helper_atomic_check,
ea702333
TZ		 6343 .mode_fixup = dm_crtc_helper_mode_fixup,
6344 .get_scanout_position = amdgpu_crtc_get_scanout_position,
e7b07cee
HW		 6345};
6346
6347static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6348{
6349
6350}
6351
3261e013
ML		 6352static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
6353{
6354 switch (display_color_depth) {
6355 case COLOR_DEPTH_666:
6356 return 6;
6357 case COLOR_DEPTH_888:
6358 return 8;
6359 case COLOR_DEPTH_101010:
6360 return 10;
6361 case COLOR_DEPTH_121212:
6362 return 12;
6363 case COLOR_DEPTH_141414:
6364 return 14;
6365 case COLOR_DEPTH_161616:
6366 return 16;
6367 default:
6368 break;
6369 }
6370 return 0;
6371}
6372
3ee6b26b
AD		 6373static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6374 struct drm_crtc_state *crtc_state,
6375 struct drm_connector_state *conn_state)
e7b07cee 6376{
3261e013
ML		 6377 struct drm_atomic_state *state = crtc_state->state;
6378 struct drm_connector *connector = conn_state->connector;
6379 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6380 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6381 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6382 struct drm_dp_mst_topology_mgr *mst_mgr;
6383 struct drm_dp_mst_port *mst_port;
6384 enum dc_color_depth color_depth;
6385 int clock, bpp = 0;
1bc22f20 6386 bool is_y420 = false;
3261e013
ML		 6387
6388 if (!aconnector->port || !aconnector->dc_sink)
6389 return 0;
6390
6391 mst_port = aconnector->port;
6392 mst_mgr = &aconnector->mst_port->mst_mgr;
6393
6394 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6395 return 0;
6396
6397 if (!state->duplicated) {
cbd14ae7 6398 int max_bpc = conn_state->max_requested_bpc;
1bc22f20
SW		 6399 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6400 aconnector->force_yuv420_output;
cbd14ae7
SW		 6401 color_depth = convert_color_depth_from_display_info(connector,
6402 is_y420,
6403 max_bpc);
3261e013
ML		 6404 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6405 clock = adjusted_mode->clock;
dc48529f 6406 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
3261e013
ML		 6407 }
6408 dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
6409 mst_mgr,
6410 mst_port,
1c6c1cb5 6411 dm_new_connector_state->pbn,
03ca9600 6412 dm_mst_get_pbn_divider(aconnector->dc_link));
3261e013
ML		 6413 if (dm_new_connector_state->vcpi_slots < 0) {
6414 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6415 return dm_new_connector_state->vcpi_slots;
6416 }
e7b07cee
HW		 6417 return 0;
6418}
6419
6420const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6421 .disable = dm_encoder_helper_disable,
6422 .atomic_check = dm_encoder_helper_atomic_check
6423};
6424
d9fe1a4c 6425#if defined(CONFIG_DRM_AMD_DC_DCN)
29b9ba74
ML		 6426static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6427 struct dc_state *dc_state)
6428{
6429 struct dc_stream_state *stream = NULL;
6430 struct drm_connector *connector;
6431 struct drm_connector_state *new_con_state, *old_con_state;
6432 struct amdgpu_dm_connector *aconnector;
6433 struct dm_connector_state *dm_conn_state;
6434 int i, j, clock, bpp;
6435 int vcpi, pbn_div, pbn = 0;
6436
6437 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6438
6439 aconnector = to_amdgpu_dm_connector(connector);
6440
6441 if (!aconnector->port)
6442 continue;
6443
6444 if (!new_con_state || !new_con_state->crtc)
6445 continue;
6446
6447 dm_conn_state = to_dm_connector_state(new_con_state);
6448
6449 for (j = 0; j < dc_state->stream_count; j++) {
6450 stream = dc_state->streams[j];
6451 if (!stream)
6452 continue;
6453
6454 if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector)
6455 break;
6456
6457 stream = NULL;
6458 }
6459
6460 if (!stream)
6461 continue;
6462
6463 if (stream->timing.flags.DSC != 1) {
6464 drm_dp_mst_atomic_enable_dsc(state,
6465 aconnector->port,
6466 dm_conn_state->pbn,
6467 0,
6468 false);
6469 continue;
6470 }
6471
6472 pbn_div = dm_mst_get_pbn_divider(stream->link);
6473 bpp = stream->timing.dsc_cfg.bits_per_pixel;
6474 clock = stream->timing.pix_clk_100hz / 10;
6475 pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
6476 vcpi = drm_dp_mst_atomic_enable_dsc(state,
6477 aconnector->port,
6478 pbn, pbn_div,
6479 true);
6480 if (vcpi < 0)
6481 return vcpi;
6482
6483 dm_conn_state->pbn = pbn;
6484 dm_conn_state->vcpi_slots = vcpi;
6485 }
6486 return 0;
6487}
d9fe1a4c 6488#endif
29b9ba74 6489
e7b07cee
HW		 6490static void dm_drm_plane_reset(struct drm_plane *plane)
6491{
6492 struct dm_plane_state *amdgpu_state = NULL;
6493
6494 if (plane->state)
6495 plane->funcs->atomic_destroy_state(plane, plane->state);
6496
6497 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 6498 WARN_ON(amdgpu_state == NULL);
1f6010a9 6499
7ddaef96
NK		 6500 if (amdgpu_state)
6501 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
e7b07cee
HW		 6502}
6503
6504static struct drm_plane_state *
6505dm_drm_plane_duplicate_state(struct drm_plane *plane)
6506{
6507 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
6508
6509 old_dm_plane_state = to_dm_plane_state(plane->state);
6510 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
6511 if (!dm_plane_state)
6512 return NULL;
6513
6514 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
6515
3be5262e
HW		 6516 if (old_dm_plane_state->dc_state) {
6517 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
6518 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 6519 }
6520
6521 return &dm_plane_state->base;
6522}
6523
dfd84d90 6524static void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 6525 struct drm_plane_state *state)
e7b07cee
HW		 6526{
6527 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
6528
3be5262e
HW		 6529 if (dm_plane_state->dc_state)
6530 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 6531
0627bbd3 6532 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 6533}
6534
6535static const struct drm_plane_funcs dm_plane_funcs = {
6536 .update_plane = drm_atomic_helper_update_plane,
6537 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 6538 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 6539 .reset = dm_drm_plane_reset,
6540 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
6541 .atomic_destroy_state = dm_drm_plane_destroy_state,
faa37f54 6542 .format_mod_supported = dm_plane_format_mod_supported,
e7b07cee
HW		 6543};
6544
3ee6b26b
AD		 6545static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
6546 struct drm_plane_state *new_state)
e7b07cee
HW		 6547{
6548 struct amdgpu_framebuffer *afb;
6549 struct drm_gem_object *obj;
5d43be0c 6550 struct amdgpu_device *adev;
e7b07cee 6551 struct amdgpu_bo *rbo;
e7b07cee 6552 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
0f257b09
CZ		 6553 struct list_head list;
6554 struct ttm_validate_buffer tv;
6555 struct ww_acquire_ctx ticket;
5d43be0c
CK		 6556 uint32_t domain;
6557 int r;
e7b07cee
HW		 6558
6559 if (!new_state->fb) {
f1ad2f5e 6560 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 6561 return 0;
6562 }
6563
6564 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 6565 obj = new_state->fb->obj[0];
e7b07cee 6566 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 6567 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
0f257b09
CZ		 6568 INIT_LIST_HEAD(&list);
6569
6570 tv.bo = &rbo->tbo;
6571 tv.num_shared = 1;
6572 list_add(&tv.head, &list);
6573
9165fb87 6574 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
0f257b09
CZ		 6575 if (r) {
6576 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
e7b07cee 6577 return r;
0f257b09 6578 }
e7b07cee 6579
5d43be0c 6580 if (plane->type != DRM_PLANE_TYPE_CURSOR)
f2bd8a0e 6581 domain = amdgpu_display_supported_domains(adev, rbo->flags);
5d43be0c
CK		 6582 else
6583 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 6584
7b7c6c81 6585 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 6586 if (unlikely(r != 0)) {
30b7c614
HW		 6587 if (r != -ERESTARTSYS)
6588 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
0f257b09 6589 ttm_eu_backoff_reservation(&ticket, &list);
e7b07cee
HW		 6590 return r;
6591 }
6592
bb812f1e
JZ		 6593 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
6594 if (unlikely(r != 0)) {
6595 amdgpu_bo_unpin(rbo);
0f257b09 6596 ttm_eu_backoff_reservation(&ticket, &list);
bb812f1e 6597 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 6598 return r;
6599 }
7df7e505 6600
0f257b09 6601 ttm_eu_backoff_reservation(&ticket, &list);
bb812f1e 6602
7b7c6c81 6603 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 6604
6605 amdgpu_bo_ref(rbo);
6606
cf322b49
NK		 6607 /**
6608 * We don't do surface updates on planes that have been newly created,
6609 * but we also don't have the afb->address during atomic check.
6610 *
6611 * Fill in buffer attributes depending on the address here, but only on
6612 * newly created planes since they're not being used by DC yet and this
6613 * won't modify global state.
6614 */
6615 dm_plane_state_old = to_dm_plane_state(plane->state);
6616 dm_plane_state_new = to_dm_plane_state(new_state);
6617
3be5262e 6618 if (dm_plane_state_new->dc_state &&
cf322b49
NK		 6619 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
6620 struct dc_plane_state *plane_state =
6621 dm_plane_state_new->dc_state;
6622 bool force_disable_dcc = !plane_state->dcc.enable;
e7b07cee 6623
320932bf 6624 fill_plane_buffer_attributes(
695af5f9 6625 adev, afb, plane_state->format, plane_state->rotation,
6eed95b0 6626 afb->tiling_flags,
cf322b49
NK		 6627 &plane_state->tiling_info, &plane_state->plane_size,
6628 &plane_state->dcc, &plane_state->address,
6eed95b0 6629 afb->tmz_surface, force_disable_dcc);
e7b07cee
HW		 6630 }
6631
e7b07cee
HW		 6632 return 0;
6633}
6634
3ee6b26b
AD		 6635static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
6636 struct drm_plane_state *old_state)
e7b07cee
HW		 6637{
6638 struct amdgpu_bo *rbo;
e7b07cee
HW		 6639 int r;
6640
6641 if (!old_state->fb)
6642 return;
6643
e68d14dd 6644 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 6645 r = amdgpu_bo_reserve(rbo, false);
6646 if (unlikely(r)) {
6647 DRM_ERROR("failed to reserve rbo before unpin\n");
6648 return;
b830ebc9
HW		 6649 }
6650
6651 amdgpu_bo_unpin(rbo);
6652 amdgpu_bo_unreserve(rbo);
6653 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 6654}
6655
8c44515b
AP		 6656static int dm_plane_helper_check_state(struct drm_plane_state *state,
6657 struct drm_crtc_state *new_crtc_state)
6658{
6300b3bd
MK		 6659 struct drm_framebuffer *fb = state->fb;
6660 int min_downscale, max_upscale;
6661 int min_scale = 0;
6662 int max_scale = INT_MAX;
6663
40d916a2 6664 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */
6300b3bd 6665 if (fb && state->crtc) {
40d916a2
NC		 6666 /* Validate viewport to cover the case when only the position changes */
6667 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) {
6668 int viewport_width = state->crtc_w;
6669 int viewport_height = state->crtc_h;
6670
6671 if (state->crtc_x < 0)
6672 viewport_width += state->crtc_x;
6673 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay)
6674 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x;
6675
6676 if (state->crtc_y < 0)
6677 viewport_height += state->crtc_y;
6678 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay)
6679 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y;
6680
6681 /* If completely outside of screen, viewport_width and/or viewport_height will be negative,
6682 * which is still OK to satisfy the condition below, thereby also covering these cases
6683 * (when plane is completely outside of screen).
6684 * x2 for width is because of pipe-split.
6685 */
6686 if (viewport_width < MIN_VIEWPORT_SIZE*2 || viewport_height < MIN_VIEWPORT_SIZE)
6687 return -EINVAL;
6688 }
6689
6690 /* Get min/max allowed scaling factors from plane caps. */
6300b3bd
MK		 6691 get_min_max_dc_plane_scaling(state->crtc->dev, fb,
6692 &min_downscale, &max_upscale);
6693 /*
6694 * Convert to drm convention: 16.16 fixed point, instead of dc's
6695 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's
6696 * dst/src, so min_scale = 1.0 / max_upscale, etc.
6697 */
6698 min_scale = (1000 << 16) / max_upscale;
6699 max_scale = (1000 << 16) / min_downscale;
6700 }
8c44515b 6701
8c44515b 6702 return drm_atomic_helper_check_plane_state(
6300b3bd 6703 state, new_crtc_state, min_scale, max_scale, true, true);
8c44515b
AP		 6704}
6705
7578ecda
AD		 6706static int dm_plane_atomic_check(struct drm_plane *plane,
6707 struct drm_plane_state *state)
cbd19488 6708{
1348969a 6709 struct amdgpu_device *adev = drm_to_adev(plane->dev);
cbd19488 6710 struct dc *dc = adev->dm.dc;
78171832 6711 struct dm_plane_state *dm_plane_state;
695af5f9 6712 struct dc_scaling_info scaling_info;
8c44515b 6713 struct drm_crtc_state *new_crtc_state;
695af5f9 6714 int ret;
78171832 6715
e8a98235
RS		 6716 trace_amdgpu_dm_plane_atomic_check(state);
6717
78171832 6718 dm_plane_state = to_dm_plane_state(state);
cbd19488 6719
3be5262e 6720 if (!dm_plane_state->dc_state)
9a3329b1 6721 return 0;
cbd19488 6722
8c44515b
AP		 6723 new_crtc_state =
6724 drm_atomic_get_new_crtc_state(state->state, state->crtc);
6725 if (!new_crtc_state)
6726 return -EINVAL;
6727
6728 ret = dm_plane_helper_check_state(state, new_crtc_state);
6729 if (ret)
6730 return ret;
6731
695af5f9
NK		 6732 ret = fill_dc_scaling_info(state, &scaling_info);
6733 if (ret)
6734 return ret;
a05bcff1 6735
62c933f9 6736 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 6737 return 0;
6738
6739 return -EINVAL;
6740}
6741
674e78ac
NK		 6742static int dm_plane_atomic_async_check(struct drm_plane *plane,
6743 struct drm_plane_state *new_plane_state)
6744{
6745 /* Only support async updates on cursor planes. */
6746 if (plane->type != DRM_PLANE_TYPE_CURSOR)
6747 return -EINVAL;
6748
6749 return 0;
6750}
6751
6752static void dm_plane_atomic_async_update(struct drm_plane *plane,
6753 struct drm_plane_state *new_state)
6754{
6755 struct drm_plane_state *old_state =
6756 drm_atomic_get_old_plane_state(new_state->state, plane);
6757
e8a98235
RS		 6758 trace_amdgpu_dm_atomic_update_cursor(new_state);
6759
332af874 6760 swap(plane->state->fb, new_state->fb);
674e78ac
NK		 6761
6762 plane->state->src_x = new_state->src_x;
6763 plane->state->src_y = new_state->src_y;
6764 plane->state->src_w = new_state->src_w;
6765 plane->state->src_h = new_state->src_h;
6766 plane->state->crtc_x = new_state->crtc_x;
6767 plane->state->crtc_y = new_state->crtc_y;
6768 plane->state->crtc_w = new_state->crtc_w;
6769 plane->state->crtc_h = new_state->crtc_h;
6770
6771 handle_cursor_update(plane, old_state);
6772}
6773
e7b07cee
HW		 6774static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
6775 .prepare_fb = dm_plane_helper_prepare_fb,
6776 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 6777 .atomic_check = dm_plane_atomic_check,
674e78ac
NK		 6778 .atomic_async_check = dm_plane_atomic_async_check,
6779 .atomic_async_update = dm_plane_atomic_async_update
e7b07cee
HW		 6780};
6781
6782/*
6783 * TODO: these are currently initialized to rgb formats only.
6784 * For future use cases we should either initialize them dynamically based on
6785 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 6786 * check will succeed, and let DC implement proper check
e7b07cee 6787 */
d90371b0 6788static const uint32_t rgb_formats[] = {
e7b07cee
HW		 6789 DRM_FORMAT_XRGB8888,
6790 DRM_FORMAT_ARGB8888,
6791 DRM_FORMAT_RGBA8888,
6792 DRM_FORMAT_XRGB2101010,
6793 DRM_FORMAT_XBGR2101010,
6794 DRM_FORMAT_ARGB2101010,
6795 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 6796 DRM_FORMAT_XBGR8888,
6797 DRM_FORMAT_ABGR8888,
46dd9ff7 6798 DRM_FORMAT_RGB565,
e7b07cee
HW		 6799};
6800
0d579c7e
NK		 6801static const uint32_t overlay_formats[] = {
6802 DRM_FORMAT_XRGB8888,
6803 DRM_FORMAT_ARGB8888,
6804 DRM_FORMAT_RGBA8888,
6805 DRM_FORMAT_XBGR8888,
6806 DRM_FORMAT_ABGR8888,
7267a1a9 6807 DRM_FORMAT_RGB565
e7b07cee
HW		 6808};
6809
6810static const u32 cursor_formats[] = {
6811 DRM_FORMAT_ARGB8888
6812};
6813
37c6a93b
NK		 6814static int get_plane_formats(const struct drm_plane *plane,
6815 const struct dc_plane_cap *plane_cap,
6816 uint32_t *formats, int max_formats)
e7b07cee 6817{
37c6a93b
NK		 6818 int i, num_formats = 0;
6819
6820 /*
6821 * TODO: Query support for each group of formats directly from
6822 * DC plane caps. This will require adding more formats to the
6823 * caps list.
6824 */
e7b07cee 6825
f180b4bc 6826 switch (plane->type) {
e7b07cee 6827 case DRM_PLANE_TYPE_PRIMARY:
37c6a93b
NK		 6828 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
6829 if (num_formats >= max_formats)
6830 break;
6831
6832 formats[num_formats++] = rgb_formats[i];
6833 }
6834
ea36ad34 6835 if (plane_cap && plane_cap->pixel_format_support.nv12)
37c6a93b 6836 formats[num_formats++] = DRM_FORMAT_NV12;
cbec6477
SW		 6837 if (plane_cap && plane_cap->pixel_format_support.p010)
6838 formats[num_formats++] = DRM_FORMAT_P010;
492548dc
SW		 6839 if (plane_cap && plane_cap->pixel_format_support.fp16) {
6840 formats[num_formats++] = DRM_FORMAT_XRGB16161616F;
6841 formats[num_formats++] = DRM_FORMAT_ARGB16161616F;
2a5195dc
MK		 6842 formats[num_formats++] = DRM_FORMAT_XBGR16161616F;
6843 formats[num_formats++] = DRM_FORMAT_ABGR16161616F;
492548dc 6844 }
e7b07cee 6845 break;
37c6a93b 6846
e7b07cee 6847 case DRM_PLANE_TYPE_OVERLAY:
37c6a93b
NK		 6848 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
6849 if (num_formats >= max_formats)
6850 break;
6851
6852 formats[num_formats++] = overlay_formats[i];
6853 }
e7b07cee 6854 break;
37c6a93b 6855
e7b07cee 6856 case DRM_PLANE_TYPE_CURSOR:
37c6a93b
NK		 6857 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
6858 if (num_formats >= max_formats)
6859 break;
6860
6861 formats[num_formats++] = cursor_formats[i];
6862 }
e7b07cee
HW		 6863 break;
6864 }
6865
37c6a93b
NK		 6866 return num_formats;
6867}
6868
6869static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
6870 struct drm_plane *plane,
6871 unsigned long possible_crtcs,
6872 const struct dc_plane_cap *plane_cap)
6873{
6874 uint32_t formats[32];
6875 int num_formats;
6876 int res = -EPERM;
ecc874a6 6877 unsigned int supported_rotations;
faa37f54 6878 uint64_t *modifiers = NULL;
37c6a93b
NK		 6879
6880 num_formats = get_plane_formats(plane, plane_cap, formats,
6881 ARRAY_SIZE(formats));
6882
faa37f54
BN		 6883 res = get_plane_modifiers(dm->adev, plane->type, &modifiers);
6884 if (res)
6885 return res;
6886
4a580877 6887 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs,
37c6a93b 6888 &dm_plane_funcs, formats, num_formats,
faa37f54
BN		 6889 modifiers, plane->type, NULL);
6890 kfree(modifiers);
37c6a93b
NK		 6891 if (res)
6892 return res;
6893
cc1fec57
NK		 6894 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
6895 plane_cap && plane_cap->per_pixel_alpha) {
d74004b6
NK		 6896 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
6897 BIT(DRM_MODE_BLEND_PREMULTI);
6898
6899 drm_plane_create_alpha_property(plane);
6900 drm_plane_create_blend_mode_property(plane, blend_caps);
6901 }
6902
fc8e5230 6903 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
00755bb7
SW		 6904 plane_cap &&
6905 (plane_cap->pixel_format_support.nv12 ||
6906 plane_cap->pixel_format_support.p010)) {
fc8e5230
NK		 6907 /* This only affects YUV formats. */
6908 drm_plane_create_color_properties(
6909 plane,
6910 BIT(DRM_COLOR_YCBCR_BT601) |
00755bb7
SW		 6911 BIT(DRM_COLOR_YCBCR_BT709) |
6912 BIT(DRM_COLOR_YCBCR_BT2020),
fc8e5230
NK		 6913 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
6914 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
6915 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
6916 }
6917
ecc874a6
PLG		 6918 supported_rotations =
6919 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
6920 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
6921
1347385f
SS		 6922 if (dm->adev->asic_type >= CHIP_BONAIRE &&
6923 plane->type != DRM_PLANE_TYPE_CURSOR)
f784112f
MR		 6924 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
6925 supported_rotations);
ecc874a6 6926
f180b4bc 6927 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 6928
96719c54 6929 /* Create (reset) the plane state */
f180b4bc
HW		 6930 if (plane->funcs->reset)
6931 plane->funcs->reset(plane);
96719c54 6932
37c6a93b 6933 return 0;
e7b07cee
HW		 6934}
6935
7578ecda
AD		 6936static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
6937 struct drm_plane *plane,
6938 uint32_t crtc_index)
e7b07cee
HW		 6939{
6940 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 6941 struct drm_plane *cursor_plane;
e7b07cee
HW		 6942
6943 int res = -ENOMEM;
6944
6945 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
6946 if (!cursor_plane)
6947 goto fail;
6948
f180b4bc 6949 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
cc1fec57 6950 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
e7b07cee
HW		 6951
6952 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
6953 if (!acrtc)
6954 goto fail;
6955
6956 res = drm_crtc_init_with_planes(
6957 dm->ddev,
6958 &acrtc->base,
6959 plane,
f180b4bc 6960 cursor_plane,
e7b07cee
HW		 6961 &amdgpu_dm_crtc_funcs, NULL);
6962
6963 if (res)
6964 goto fail;
6965
6966 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
6967
96719c54
HW		 6968 /* Create (reset) the plane state */
6969 if (acrtc->base.funcs->reset)
6970 acrtc->base.funcs->reset(&acrtc->base);
6971
e7b07cee
HW		 6972 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
6973 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
6974
6975 acrtc->crtc_id = crtc_index;
6976 acrtc->base.enabled = false;
c37e2d29 6977 acrtc->otg_inst = -1;
e7b07cee
HW		 6978
6979 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 6980 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
6981 true, MAX_COLOR_LUT_ENTRIES);
086247a4 6982 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e2881d6d 6983
e7b07cee
HW		 6984 return 0;
6985
6986fail:
b830ebc9
HW		 6987 kfree(acrtc);
6988 kfree(cursor_plane);
e7b07cee
HW		 6989 return res;
6990}
6991
6992
6993static int to_drm_connector_type(enum signal_type st)
6994{
6995 switch (st) {
6996 case SIGNAL_TYPE_HDMI_TYPE_A:
6997 return DRM_MODE_CONNECTOR_HDMIA;
6998 case SIGNAL_TYPE_EDP:
6999 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 7000 case SIGNAL_TYPE_LVDS:
7001 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 7002 case SIGNAL_TYPE_RGB:
7003 return DRM_MODE_CONNECTOR_VGA;
7004 case SIGNAL_TYPE_DISPLAY_PORT:
7005 case SIGNAL_TYPE_DISPLAY_PORT_MST:
7006 return DRM_MODE_CONNECTOR_DisplayPort;
7007 case SIGNAL_TYPE_DVI_DUAL_LINK:
7008 case SIGNAL_TYPE_DVI_SINGLE_LINK:
7009 return DRM_MODE_CONNECTOR_DVID;
7010 case SIGNAL_TYPE_VIRTUAL:
7011 return DRM_MODE_CONNECTOR_VIRTUAL;
7012
7013 default:
7014 return DRM_MODE_CONNECTOR_Unknown;
7015 }
7016}
7017
2b4c1c05
DV		 7018static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7019{
62afb4ad
JRS		 7020 struct drm_encoder *encoder;
7021
7022 /* There is only one encoder per connector */
7023 drm_connector_for_each_possible_encoder(connector, encoder)
7024 return encoder;
7025
7026 return NULL;
2b4c1c05
DV		 7027}
7028
e7b07cee
HW		 7029static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7030{
e7b07cee
HW		 7031 struct drm_encoder *encoder;
7032 struct amdgpu_encoder *amdgpu_encoder;
7033
2b4c1c05 7034 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 7035
7036 if (encoder == NULL)
7037 return;
7038
7039 amdgpu_encoder = to_amdgpu_encoder(encoder);
7040
7041 amdgpu_encoder->native_mode.clock = 0;
7042
7043 if (!list_empty(&connector->probed_modes)) {
7044 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 7045
e7b07cee 7046 list_for_each_entry(preferred_mode,
b830ebc9
HW		 7047 &connector->probed_modes,
7048 head) {
7049 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7050 amdgpu_encoder->native_mode = *preferred_mode;
7051
e7b07cee
HW		 7052 break;
7053 }
7054
7055 }
7056}
7057
3ee6b26b
AD		 7058static struct drm_display_mode *
7059amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7060 char *name,
7061 int hdisplay, int vdisplay)
e7b07cee
HW		 7062{
7063 struct drm_device *dev = encoder->dev;
7064 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7065 struct drm_display_mode *mode = NULL;
7066 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7067
7068 mode = drm_mode_duplicate(dev, native_mode);
7069
b830ebc9 7070 if (mode == NULL)
e7b07cee
HW		 7071 return NULL;
7072
7073 mode->hdisplay = hdisplay;
7074 mode->vdisplay = vdisplay;
7075 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 7076 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 7077
7078 return mode;
7079
7080}
7081
7082static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 7083 struct drm_connector *connector)
e7b07cee
HW		 7084{
7085 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7086 struct drm_display_mode *mode = NULL;
7087 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 7088 struct amdgpu_dm_connector *amdgpu_dm_connector =
7089 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 7090 int i;
7091 int n;
7092 struct mode_size {
7093 char name[DRM_DISPLAY_MODE_LEN];
7094 int w;
7095 int h;
b830ebc9 7096 } common_modes[] = {
e7b07cee
HW		 7097 { "640x480", 640, 480},
7098 { "800x600", 800, 600},
7099 { "1024x768", 1024, 768},
7100 { "1280x720", 1280, 720},
7101 { "1280x800", 1280, 800},
7102 {"1280x1024", 1280, 1024},
7103 { "1440x900", 1440, 900},
7104 {"1680x1050", 1680, 1050},
7105 {"1600x1200", 1600, 1200},
7106 {"1920x1080", 1920, 1080},
7107 {"1920x1200", 1920, 1200}
7108 };
7109
b830ebc9 7110 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 7111
7112 for (i = 0; i < n; i++) {
7113 struct drm_display_mode *curmode = NULL;
7114 bool mode_existed = false;
7115
7116 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 7117 common_modes[i].h > native_mode->vdisplay ||
7118 (common_modes[i].w == native_mode->hdisplay &&
7119 common_modes[i].h == native_mode->vdisplay))
7120 continue;
e7b07cee
HW		 7121
7122 list_for_each_entry(curmode, &connector->probed_modes, head) {
7123 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 7124 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 7125 mode_existed = true;
7126 break;
7127 }
7128 }
7129
7130 if (mode_existed)
7131 continue;
7132
7133 mode = amdgpu_dm_create_common_mode(encoder,
7134 common_modes[i].name, common_modes[i].w,
7135 common_modes[i].h);
7136 drm_mode_probed_add(connector, mode);
c84dec2f 7137 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 7138 }
7139}
7140
3ee6b26b
AD		 7141static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7142 struct edid *edid)
e7b07cee 7143{
c84dec2f
HW		 7144 struct amdgpu_dm_connector *amdgpu_dm_connector =
7145 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 7146
7147 if (edid) {
7148 /* empty probed_modes */
7149 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 7150 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 7151 drm_add_edid_modes(connector, edid);
7152
f1e5e913
YMM		 7153 /* sorting the probed modes before calling function
7154 * amdgpu_dm_get_native_mode() since EDID can have
7155 * more than one preferred mode. The modes that are
7156 * later in the probed mode list could be of higher
7157 * and preferred resolution. For example, 3840x2160
7158 * resolution in base EDID preferred timing and 4096x2160
7159 * preferred resolution in DID extension block later.
7160 */
7161 drm_mode_sort(&connector->probed_modes);
e7b07cee 7162 amdgpu_dm_get_native_mode(connector);
f9b4f20c
SW		 7163
7164 /* Freesync capabilities are reset by calling
7165 * drm_add_edid_modes() and need to be
7166 * restored here.
7167 */
7168 amdgpu_dm_update_freesync_caps(connector, edid);
a8d8d3dc 7169 } else {
c84dec2f 7170 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 7171 }
e7b07cee
HW		 7172}
7173
d10cd527
AP		 7174static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7175 struct drm_display_mode *mode)
7176{
7177 struct drm_display_mode *m;
7178
7179 list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7180 if (drm_mode_equal(m, mode))
7181 return true;
7182 }
7183
7184 return false;
7185}
7186
7187static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7188{
7189 const struct drm_display_mode *m;
7190 struct drm_display_mode *new_mode;
7191 uint i;
7192 uint32_t new_modes_count = 0;
7193
7194 /* Standard FPS values
7195 *
7196 * 23.976 - TV/NTSC
7197 * 24 - Cinema
7198 * 25 - TV/PAL
7199 * 29.97 - TV/NTSC
7200 * 30 - TV/NTSC
7201 * 48 - Cinema HFR
7202 * 50 - TV/PAL
7203 * 60 - Commonly used
7204 * 48,72,96 - Multiples of 24
7205 */
7206 const uint32_t common_rates[] = { 23976, 24000, 25000, 29970, 30000,
7207 48000, 50000, 60000, 72000, 96000 };
7208
7209 /*
7210 * Find mode with highest refresh rate with the same resolution
7211 * as the preferred mode. Some monitors report a preferred mode
7212 * with lower resolution than the highest refresh rate supported.
7213 */
7214
7215 m = get_highest_refresh_rate_mode(aconnector, true);
7216 if (!m)
7217 return 0;
7218
7219 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7220 uint64_t target_vtotal, target_vtotal_diff;
7221 uint64_t num, den;
7222
7223 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7224 continue;
7225
7226 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7227 common_rates[i] > aconnector->max_vfreq * 1000)
7228 continue;
7229
7230 num = (unsigned long long)m->clock * 1000 * 1000;
7231 den = common_rates[i] * (unsigned long long)m->htotal;
7232 target_vtotal = div_u64(num, den);
7233 target_vtotal_diff = target_vtotal - m->vtotal;
7234
7235 /* Check for illegal modes */
7236 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7237 m->vsync_end + target_vtotal_diff < m->vsync_start ||
7238 m->vtotal + target_vtotal_diff < m->vsync_end)
7239 continue;
7240
7241 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7242 if (!new_mode)
7243 goto out;
7244
7245 new_mode->vtotal += (u16)target_vtotal_diff;
7246 new_mode->vsync_start += (u16)target_vtotal_diff;
7247 new_mode->vsync_end += (u16)target_vtotal_diff;
7248 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7249 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7250
7251 if (!is_duplicate_mode(aconnector, new_mode)) {
7252 drm_mode_probed_add(&aconnector->base, new_mode);
7253 new_modes_count += 1;
7254 } else
7255 drm_mode_destroy(aconnector->base.dev, new_mode);
7256 }
7257 out:
7258 return new_modes_count;
7259}
7260
7261static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7262 struct edid *edid)
7263{
7264 struct amdgpu_dm_connector *amdgpu_dm_connector =
7265 to_amdgpu_dm_connector(connector);
7266
7267 if (!(amdgpu_freesync_vid_mode && edid))
7268 return;
7269
7270 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7271 amdgpu_dm_connector->num_modes +=
7272 add_fs_modes(amdgpu_dm_connector);
7273}
7274
7578ecda 7275static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 7276{
c84dec2f
HW		 7277 struct amdgpu_dm_connector *amdgpu_dm_connector =
7278 to_amdgpu_dm_connector(connector);
e7b07cee 7279 struct drm_encoder *encoder;
c84dec2f 7280 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 7281
2b4c1c05 7282 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 7283
5c0e6840 7284 if (!drm_edid_is_valid(edid)) {
1b369d3c
ML		 7285 amdgpu_dm_connector->num_modes =
7286 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 7287 } else {
7288 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7289 amdgpu_dm_connector_add_common_modes(encoder, connector);
d10cd527 7290 amdgpu_dm_connector_add_freesync_modes(connector, edid);
85ee15d6 7291 }
3e332d3a 7292 amdgpu_dm_fbc_init(connector);
5099114b 7293
c84dec2f 7294 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 7295}
7296
3ee6b26b
AD		 7297void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7298 struct amdgpu_dm_connector *aconnector,
7299 int connector_type,
7300 struct dc_link *link,
7301 int link_index)
e7b07cee 7302{
1348969a 7303 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
e7b07cee 7304
f04bee34
NK		 7305 /*
7306 * Some of the properties below require access to state, like bpc.
7307 * Allocate some default initial connector state with our reset helper.
7308 */
7309 if (aconnector->base.funcs->reset)
7310 aconnector->base.funcs->reset(&aconnector->base);
7311
e7b07cee
HW		 7312 aconnector->connector_id = link_index;
7313 aconnector->dc_link = link;
7314 aconnector->base.interlace_allowed = false;
7315 aconnector->base.doublescan_allowed = false;
7316 aconnector->base.stereo_allowed = false;
7317 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7318 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
6ce8f316 7319 aconnector->audio_inst = -1;
e7b07cee
HW		 7320 mutex_init(&aconnector->hpd_lock);
7321
1f6010a9
DF		 7322 /*
7323 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 7324 * which means HPD hot plug not supported
7325 */
e7b07cee
HW		 7326 switch (connector_type) {
7327 case DRM_MODE_CONNECTOR_HDMIA:
7328 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 7329 aconnector->base.ycbcr_420_allowed =
9ea59d5a 7330 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 7331 break;
7332 case DRM_MODE_CONNECTOR_DisplayPort:
7333 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 7334 aconnector->base.ycbcr_420_allowed =
9ea59d5a 7335 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 7336 break;
7337 case DRM_MODE_CONNECTOR_DVID:
7338 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7339 break;
7340 default:
7341 break;
7342 }
7343
7344 drm_object_attach_property(&aconnector->base.base,
7345 dm->ddev->mode_config.scaling_mode_property,
7346 DRM_MODE_SCALE_NONE);
7347
7348 drm_object_attach_property(&aconnector->base.base,
7349 adev->mode_info.underscan_property,
7350 UNDERSCAN_OFF);
7351 drm_object_attach_property(&aconnector->base.base,
7352 adev->mode_info.underscan_hborder_property,
7353 0);
7354 drm_object_attach_property(&aconnector->base.base,
7355 adev->mode_info.underscan_vborder_property,
7356 0);
1825fd34 7357
8c61b31e
JFZ		 7358 if (!aconnector->mst_port)
7359 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
1825fd34 7360
4a8ca46b
RL		 7361 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7362 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
7363 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
e7b07cee 7364
c1ee92f9 7365 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5cb32419 7366 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
c1ee92f9
DF		 7367 drm_object_attach_property(&aconnector->base.base,
7368 adev->mode_info.abm_level_property, 0);
7369 }
bb47de73
NK		 7370
7371 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7fad8da1
NK		 7372 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7373 connector_type == DRM_MODE_CONNECTOR_eDP) {
88694af9
NK		 7374 drm_object_attach_property(
7375 &aconnector->base.base,
7376 dm->ddev->mode_config.hdr_output_metadata_property, 0);
7377
8c61b31e
JFZ		 7378 if (!aconnector->mst_port)
7379 drm_connector_attach_vrr_capable_property(&aconnector->base);
7380
0c8620d6 7381#ifdef CONFIG_DRM_AMD_DC_HDCP
e22bb562 7382 if (adev->dm.hdcp_workqueue)
53e108aa 7383 drm_connector_attach_content_protection_property(&aconnector->base, true);
0c8620d6 7384#endif
bb47de73 7385 }
e7b07cee
HW		 7386}
7387
7578ecda
AD		 7388static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7389 struct i2c_msg *msgs, int num)
e7b07cee
HW		 7390{
7391 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7392 struct ddc_service *ddc_service = i2c->ddc_service;
7393 struct i2c_command cmd;
7394 int i;
7395 int result = -EIO;
7396
b830ebc9 7397 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 7398
7399 if (!cmd.payloads)
7400 return result;
7401
7402 cmd.number_of_payloads = num;
7403 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7404 cmd.speed = 100;
7405
7406 for (i = 0; i < num; i++) {
7407 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7408 cmd.payloads[i].address = msgs[i].addr;
7409 cmd.payloads[i].length = msgs[i].len;
7410 cmd.payloads[i].data = msgs[i].buf;
7411 }
7412
c85e6e54
DF		 7413 if (dc_submit_i2c(
7414 ddc_service->ctx->dc,
7415 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 7416 &cmd))
7417 result = num;
7418
7419 kfree(cmd.payloads);
7420 return result;
7421}
7422
7578ecda 7423static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 7424{
7425 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7426}
7427
7428static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7429 .master_xfer = amdgpu_dm_i2c_xfer,
7430 .functionality = amdgpu_dm_i2c_func,
7431};
7432
3ee6b26b
AD		 7433static struct amdgpu_i2c_adapter *
7434create_i2c(struct ddc_service *ddc_service,
7435 int link_index,
7436 int *res)
e7b07cee
HW		 7437{
7438 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7439 struct amdgpu_i2c_adapter *i2c;
7440
b830ebc9 7441 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 7442 if (!i2c)
7443 return NULL;
e7b07cee
HW		 7444 i2c->base.owner = THIS_MODULE;
7445 i2c->base.class = I2C_CLASS_DDC;
7446 i2c->base.dev.parent = &adev->pdev->dev;
7447 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 7448 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 7449 i2c_set_adapdata(&i2c->base, i2c);
7450 i2c->ddc_service = ddc_service;
c85e6e54 7451 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 7452
7453 return i2c;
7454}
7455
89fc8d4e 7456
1f6010a9
DF		 7457/*
7458 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 7459 * dc_link which will be represented by this aconnector.
7460 */
7578ecda
AD		 7461static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7462 struct amdgpu_dm_connector *aconnector,
7463 uint32_t link_index,
7464 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 7465{
7466 int res = 0;
7467 int connector_type;
7468 struct dc *dc = dm->dc;
7469 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7470 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 7471
7472 link->priv = aconnector;
e7b07cee 7473
f1ad2f5e 7474 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 7475
7476 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 7477 if (!i2c) {
7478 DRM_ERROR("Failed to create i2c adapter data\n");
7479 return -ENOMEM;
7480 }
7481
e7b07cee
HW		 7482 aconnector->i2c = i2c;
7483 res = i2c_add_adapter(&i2c->base);
7484
7485 if (res) {
7486 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7487 goto out_free;
7488 }
7489
7490 connector_type = to_drm_connector_type(link->connector_signal);
7491
17165de2 7492 res = drm_connector_init_with_ddc(
e7b07cee
HW		 7493 dm->ddev,
7494 &aconnector->base,
7495 &amdgpu_dm_connector_funcs,
17165de2
AP		 7496 connector_type,
7497 &i2c->base);
e7b07cee
HW		 7498
7499 if (res) {
7500 DRM_ERROR("connector_init failed\n");
7501 aconnector->connector_id = -1;
7502 goto out_free;
7503 }
7504
7505 drm_connector_helper_add(
7506 &aconnector->base,
7507 &amdgpu_dm_connector_helper_funcs);
7508
7509 amdgpu_dm_connector_init_helper(
7510 dm,
7511 aconnector,
7512 connector_type,
7513 link,
7514 link_index);
7515
cde4c44d 7516 drm_connector_attach_encoder(
e7b07cee
HW		 7517 &aconnector->base, &aencoder->base);
7518
e7b07cee
HW		 7519 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7520 || connector_type == DRM_MODE_CONNECTOR_eDP)
7daec99f 7521 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
e7b07cee 7522
e7b07cee
HW		 7523out_free:
7524 if (res) {
7525 kfree(i2c);
7526 aconnector->i2c = NULL;
7527 }
7528 return res;
7529}
7530
7531int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7532{
7533 switch (adev->mode_info.num_crtc) {
7534 case 1:
7535 return 0x1;
7536 case 2:
7537 return 0x3;
7538 case 3:
7539 return 0x7;
7540 case 4:
7541 return 0xf;
7542 case 5:
7543 return 0x1f;
7544 case 6:
7545 default:
7546 return 0x3f;
7547 }
7548}
7549
7578ecda
AD		 7550static int amdgpu_dm_encoder_init(struct drm_device *dev,
7551 struct amdgpu_encoder *aencoder,
7552 uint32_t link_index)
e7b07cee 7553{
1348969a 7554 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 7555
7556 int res = drm_encoder_init(dev,
7557 &aencoder->base,
7558 &amdgpu_dm_encoder_funcs,
7559 DRM_MODE_ENCODER_TMDS,
7560 NULL);
7561
7562 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7563
7564 if (!res)
7565 aencoder->encoder_id = link_index;
7566 else
7567 aencoder->encoder_id = -1;
7568
7569 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7570
7571 return res;
7572}
7573
3ee6b26b
AD		 7574static void manage_dm_interrupts(struct amdgpu_device *adev,
7575 struct amdgpu_crtc *acrtc,
7576 bool enable)
e7b07cee
HW		 7577{
7578 /*
8fe684e9
NK		 7579 * We have no guarantee that the frontend index maps to the same
7580 * backend index - some even map to more than one.
7581 *
7582 * TODO: Use a different interrupt or check DC itself for the mapping.
e7b07cee
HW		 7583 */
7584 int irq_type =
734dd01d 7585 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 7586 adev,
7587 acrtc->crtc_id);
7588
7589 if (enable) {
7590 drm_crtc_vblank_on(&acrtc->base);
7591 amdgpu_irq_get(
7592 adev,
7593 &adev->pageflip_irq,
7594 irq_type);
86bc2219
WL		 7595#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7596 amdgpu_irq_get(
7597 adev,
7598 &adev->vline0_irq,
7599 irq_type);
7600#endif
e7b07cee 7601 } else {
86bc2219
WL		 7602#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7603 amdgpu_irq_put(
7604 adev,
7605 &adev->vline0_irq,
7606 irq_type);
7607#endif
e7b07cee
HW		 7608 amdgpu_irq_put(
7609 adev,
7610 &adev->pageflip_irq,
7611 irq_type);
7612 drm_crtc_vblank_off(&acrtc->base);
7613 }
7614}
7615
8fe684e9
NK		 7616static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7617 struct amdgpu_crtc *acrtc)
7618{
7619 int irq_type =
7620 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7621
7622 /**
7623 * This reads the current state for the IRQ and force reapplies
7624 * the setting to hardware.
7625 */
7626 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7627}
7628
3ee6b26b
AD		 7629static bool
7630is_scaling_state_different(const struct dm_connector_state *dm_state,
7631 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 7632{
7633 if (dm_state->scaling != old_dm_state->scaling)
7634 return true;
7635 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7636 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7637 return true;
7638 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7639 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7640 return true;
b830ebc9
HW		 7641 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7642 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7643 return true;
e7b07cee
HW		 7644 return false;
7645}
7646
0c8620d6
BL		 7647#ifdef CONFIG_DRM_AMD_DC_HDCP
7648static bool is_content_protection_different(struct drm_connector_state *state,
7649 const struct drm_connector_state *old_state,
7650 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
7651{
7652 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
97f6c917 7653 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
0c8620d6 7654
31c0ed90 7655 /* Handle: Type0/1 change */
53e108aa
BL		 7656 if (old_state->hdcp_content_type != state->hdcp_content_type &&
7657 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7658 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7659 return true;
7660 }
7661
31c0ed90
BL		 7662 /* CP is being re enabled, ignore this
7663 *
7664 * Handles: ENABLED -> DESIRED
7665 */
0c8620d6
BL		 7666 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7667 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7668 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7669 return false;
7670 }
7671
31c0ed90
BL		 7672 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7673 *
7674 * Handles: UNDESIRED -> ENABLED
7675 */
0c8620d6
BL		 7676 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7677 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7678 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7679
7680 /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
7681 * hot-plug, headless s3, dpms
31c0ed90
BL		 7682 *
7683 * Handles: DESIRED -> DESIRED (Special case)
0c8620d6 7684 */
97f6c917
BL		 7685 if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7686 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7687 dm_con_state->update_hdcp = false;
0c8620d6 7688 return true;
97f6c917 7689 }
0c8620d6 7690
31c0ed90
BL		 7691 /*
7692 * Handles: UNDESIRED -> UNDESIRED
7693 * DESIRED -> DESIRED
7694 * ENABLED -> ENABLED
7695 */
0c8620d6
BL		 7696 if (old_state->content_protection == state->content_protection)
7697 return false;
7698
31c0ed90
BL		 7699 /*
7700 * Handles: UNDESIRED -> DESIRED
7701 * DESIRED -> UNDESIRED
7702 * ENABLED -> UNDESIRED
7703 */
97f6c917 7704 if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
0c8620d6
BL		 7705 return true;
7706
31c0ed90
BL		 7707 /*
7708 * Handles: DESIRED -> ENABLED
7709 */
0c8620d6
BL		 7710 return false;
7711}
7712
0c8620d6 7713#endif
3ee6b26b
AD		 7714static void remove_stream(struct amdgpu_device *adev,
7715 struct amdgpu_crtc *acrtc,
7716 struct dc_stream_state *stream)
e7b07cee
HW		 7717{
7718 /* this is the update mode case */
e7b07cee
HW		 7719
7720 acrtc->otg_inst = -1;
7721 acrtc->enabled = false;
7722}
7723
7578ecda
AD		 7724static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
7725 struct dc_cursor_position *position)
2a8f6ccb 7726{
f4c2cc43 7727 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 7728 int x, y;
7729 int xorigin = 0, yorigin = 0;
7730
e371e19c
NK		 7731 position->enable = false;
7732 position->x = 0;
7733 position->y = 0;
7734
7735 if (!crtc || !plane->state->fb)
2a8f6ccb 7736 return 0;
2a8f6ccb
HW		 7737
7738 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
7739 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
7740 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
7741 __func__,
7742 plane->state->crtc_w,
7743 plane->state->crtc_h);
7744 return -EINVAL;
7745 }
7746
7747 x = plane->state->crtc_x;
7748 y = plane->state->crtc_y;
c14a005c 7749
e371e19c
NK		 7750 if (x <= -amdgpu_crtc->max_cursor_width ||
7751 y <= -amdgpu_crtc->max_cursor_height)
7752 return 0;
7753
2a8f6ccb
HW		 7754 if (x < 0) {
7755 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
7756 x = 0;
7757 }
7758 if (y < 0) {
7759 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
7760 y = 0;
7761 }
7762 position->enable = true;
d243b6ff 7763 position->translate_by_source = true;
2a8f6ccb
HW		 7764 position->x = x;
7765 position->y = y;
7766 position->x_hotspot = xorigin;
7767 position->y_hotspot = yorigin;
7768
7769 return 0;
7770}
7771
3ee6b26b
AD		 7772static void handle_cursor_update(struct drm_plane *plane,
7773 struct drm_plane_state *old_plane_state)
e7b07cee 7774{
1348969a 7775 struct amdgpu_device *adev = drm_to_adev(plane->dev);
2a8f6ccb
HW		 7776 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
7777 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
7778 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
7779 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7780 uint64_t address = afb ? afb->address : 0;
7781 struct dc_cursor_position position;
7782 struct dc_cursor_attributes attributes;
7783 int ret;
7784
e7b07cee
HW		 7785 if (!plane->state->fb && !old_plane_state->fb)
7786 return;
7787
f1ad2f5e 7788 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 7789 __func__,
7790 amdgpu_crtc->crtc_id,
7791 plane->state->crtc_w,
7792 plane->state->crtc_h);
2a8f6ccb
HW		 7793
7794 ret = get_cursor_position(plane, crtc, &position);
7795 if (ret)
7796 return;
7797
7798 if (!position.enable) {
7799 /* turn off cursor */
674e78ac
NK		 7800 if (crtc_state && crtc_state->stream) {
7801 mutex_lock(&adev->dm.dc_lock);
2a8f6ccb
HW		 7802 dc_stream_set_cursor_position(crtc_state->stream,
7803 &position);
674e78ac
NK		 7804 mutex_unlock(&adev->dm.dc_lock);
7805 }
2a8f6ccb 7806 return;
e7b07cee 7807 }
e7b07cee 7808
2a8f6ccb
HW		 7809 amdgpu_crtc->cursor_width = plane->state->crtc_w;
7810 amdgpu_crtc->cursor_height = plane->state->crtc_h;
7811
c1cefe11 7812 memset(&attributes, 0, sizeof(attributes));
2a8f6ccb
HW		 7813 attributes.address.high_part = upper_32_bits(address);
7814 attributes.address.low_part = lower_32_bits(address);
7815 attributes.width = plane->state->crtc_w;
7816 attributes.height = plane->state->crtc_h;
7817 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
7818 attributes.rotation_angle = 0;
7819 attributes.attribute_flags.value = 0;
7820
03a66367 7821 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0];
2a8f6ccb 7822
886daac9 7823 if (crtc_state->stream) {
674e78ac 7824 mutex_lock(&adev->dm.dc_lock);
886daac9
JZ		 7825 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
7826 &attributes))
7827 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 7828
2a8f6ccb
HW		 7829 if (!dc_stream_set_cursor_position(crtc_state->stream,
7830 &position))
7831 DRM_ERROR("DC failed to set cursor position\n");
674e78ac 7832 mutex_unlock(&adev->dm.dc_lock);
886daac9 7833 }
2a8f6ccb 7834}
e7b07cee
HW		 7835
7836static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7837{
7838
7839 assert_spin_locked(&acrtc->base.dev->event_lock);
7840 WARN_ON(acrtc->event);
7841
7842 acrtc->event = acrtc->base.state->event;
7843
7844 /* Set the flip status */
7845 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7846
7847 /* Mark this event as consumed */
7848 acrtc->base.state->event = NULL;
7849
7850 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7851 acrtc->crtc_id);
7852}
7853
bb47de73
NK		 7854static void update_freesync_state_on_stream(
7855 struct amdgpu_display_manager *dm,
7856 struct dm_crtc_state *new_crtc_state,
180db303
NK		 7857 struct dc_stream_state *new_stream,
7858 struct dc_plane_state *surface,
7859 u32 flip_timestamp_in_us)
bb47de73 7860{
09aef2c4 7861 struct mod_vrr_params vrr_params;
bb47de73 7862 struct dc_info_packet vrr_infopacket = {0};
09aef2c4 7863 struct amdgpu_device *adev = dm->adev;
585d450c 7864 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
09aef2c4 7865 unsigned long flags;
4cda3243 7866 bool pack_sdp_v1_3 = false;
bb47de73
NK		 7867
7868 if (!new_stream)
7869 return;
7870
7871 /*
7872 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7873 * For now it's sufficient to just guard against these conditions.
7874 */
7875
7876 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7877 return;
7878
4a580877 7879 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
585d450c 7880 vrr_params = acrtc->dm_irq_params.vrr_params;
09aef2c4 7881
180db303
NK		 7882 if (surface) {
7883 mod_freesync_handle_preflip(
7884 dm->freesync_module,
7885 surface,
7886 new_stream,
7887 flip_timestamp_in_us,
7888 &vrr_params);
09aef2c4
MK		 7889
7890 if (adev->family < AMDGPU_FAMILY_AI &&
7891 amdgpu_dm_vrr_active(new_crtc_state)) {
7892 mod_freesync_handle_v_update(dm->freesync_module,
7893 new_stream, &vrr_params);
e63e2491
EB		 7894
7895 /* Need to call this before the frame ends. */
7896 dc_stream_adjust_vmin_vmax(dm->dc,
7897 new_crtc_state->stream,
7898 &vrr_params.adjust);
09aef2c4 7899 }
180db303 7900 }
bb47de73
NK		 7901
7902 mod_freesync_build_vrr_infopacket(
7903 dm->freesync_module,
7904 new_stream,
180db303 7905 &vrr_params,
ecd0136b
HT		 7906 PACKET_TYPE_VRR,
7907 TRANSFER_FUNC_UNKNOWN,
4cda3243
MT		 7908 &vrr_infopacket,
7909 pack_sdp_v1_3);
bb47de73 7910
8a48b44c 7911 new_crtc_state->freesync_timing_changed |=
585d450c 7912 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
180db303
NK		 7913 &vrr_params.adjust,
7914 sizeof(vrr_params.adjust)) != 0);
bb47de73 7915
8a48b44c 7916 new_crtc_state->freesync_vrr_info_changed |=
bb47de73
NK		 7917 (memcmp(&new_crtc_state->vrr_infopacket,
7918 &vrr_infopacket,
7919 sizeof(vrr_infopacket)) != 0);
7920
585d450c 7921 acrtc->dm_irq_params.vrr_params = vrr_params;
bb47de73
NK		 7922 new_crtc_state->vrr_infopacket = vrr_infopacket;
7923
585d450c 7924 new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust;
bb47de73
NK		 7925 new_stream->vrr_infopacket = vrr_infopacket;
7926
7927 if (new_crtc_state->freesync_vrr_info_changed)
7928 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7929 new_crtc_state->base.crtc->base.id,
7930 (int)new_crtc_state->base.vrr_enabled,
180db303 7931 (int)vrr_params.state);
09aef2c4 7932
4a580877 7933 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
bb47de73
NK		 7934}
7935
585d450c 7936static void update_stream_irq_parameters(
e854194c
MK		 7937 struct amdgpu_display_manager *dm,
7938 struct dm_crtc_state *new_crtc_state)
7939{
7940 struct dc_stream_state *new_stream = new_crtc_state->stream;
09aef2c4 7941 struct mod_vrr_params vrr_params;
e854194c 7942 struct mod_freesync_config config = new_crtc_state->freesync_config;
09aef2c4 7943 struct amdgpu_device *adev = dm->adev;
585d450c 7944 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
09aef2c4 7945 unsigned long flags;
e854194c
MK		 7946
7947 if (!new_stream)
7948 return;
7949
7950 /*
7951 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7952 * For now it's sufficient to just guard against these conditions.
7953 */
7954 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7955 return;
7956
4a580877 7957 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
585d450c 7958 vrr_params = acrtc->dm_irq_params.vrr_params;
09aef2c4 7959
e854194c
MK		 7960 if (new_crtc_state->vrr_supported &&
7961 config.min_refresh_in_uhz &&
7962 config.max_refresh_in_uhz) {
6f59f229
AP		 7963 /*
7964 * if freesync compatible mode was set, config.state will be set
7965 * in atomic check
7966 */
7967 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7968 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7969 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7970 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7971 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7972 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7973 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7974 } else {
7975 config.state = new_crtc_state->base.vrr_enabled ?
7976 VRR_STATE_ACTIVE_VARIABLE :
7977 VRR_STATE_INACTIVE;
7978 }
e854194c
MK		 7979 } else {
7980 config.state = VRR_STATE_UNSUPPORTED;
7981 }
7982
7983 mod_freesync_build_vrr_params(dm->freesync_module,
7984 new_stream,
7985 &config, &vrr_params);
7986
7987 new_crtc_state->freesync_timing_changed |=
585d450c
AP		 7988 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
7989 &vrr_params.adjust, sizeof(vrr_params.adjust)) != 0);
e854194c 7990
585d450c
AP		 7991 new_crtc_state->freesync_config = config;
7992 /* Copy state for access from DM IRQ handler */
7993 acrtc->dm_irq_params.freesync_config = config;
7994 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7995 acrtc->dm_irq_params.vrr_params = vrr_params;
4a580877 7996 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
e854194c
MK		 7997}
7998
66b0c973
MK		 7999static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8000 struct dm_crtc_state *new_state)
8001{
8002 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
8003 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
8004
8005 if (!old_vrr_active && new_vrr_active) {
8006 /* Transition VRR inactive -> active:
8007 * While VRR is active, we must not disable vblank irq, as a
8008 * reenable after disable would compute bogus vblank/pflip
8009 * timestamps if it likely happened inside display front-porch.
d2574c33
MK		 8010 *
8011 * We also need vupdate irq for the actual core vblank handling
8012 * at end of vblank.
66b0c973 8013 */
d2574c33 8014 dm_set_vupdate_irq(new_state->base.crtc, true);
66b0c973
MK		 8015 drm_crtc_vblank_get(new_state->base.crtc);
8016 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8017 __func__, new_state->base.crtc->base.id);
8018 } else if (old_vrr_active && !new_vrr_active) {
8019 /* Transition VRR active -> inactive:
8020 * Allow vblank irq disable again for fixed refresh rate.
8021 */
d2574c33 8022 dm_set_vupdate_irq(new_state->base.crtc, false);
66b0c973
MK		 8023 drm_crtc_vblank_put(new_state->base.crtc);
8024 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8025 __func__, new_state->base.crtc->base.id);
8026 }
8027}
8028
8ad27806
NK		 8029static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8030{
8031 struct drm_plane *plane;
8032 struct drm_plane_state *old_plane_state, *new_plane_state;
8033 int i;
8034
8035 /*
8036 * TODO: Make this per-stream so we don't issue redundant updates for
8037 * commits with multiple streams.
8038 */
8039 for_each_oldnew_plane_in_state(state, plane, old_plane_state,
8040 new_plane_state, i)
8041 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8042 handle_cursor_update(plane, old_plane_state);
8043}
8044
3be5262e 8045static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 8046 struct dc_state *dc_state,
3ee6b26b
AD		 8047 struct drm_device *dev,
8048 struct amdgpu_display_manager *dm,
8049 struct drm_crtc *pcrtc,
420cd472 8050 bool wait_for_vblank)
e7b07cee 8051{
263a4feb 8052 uint32_t i;
8a48b44c 8053 uint64_t timestamp_ns;
e7b07cee 8054 struct drm_plane *plane;
0bc9706d 8055 struct drm_plane_state *old_plane_state, *new_plane_state;
e7b07cee 8056 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 8057 struct drm_crtc_state *new_pcrtc_state =
8058 drm_atomic_get_new_crtc_state(state, pcrtc);
8059 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 8060 struct dm_crtc_state *dm_old_crtc_state =
8061 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
74aa7bd4 8062 int planes_count = 0, vpos, hpos;
570c91d5 8063 long r;
e7b07cee 8064 unsigned long flags;
8a48b44c 8065 struct amdgpu_bo *abo;
fdd1fe57
MK		 8066 uint32_t target_vblank, last_flip_vblank;
8067 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
74aa7bd4 8068 bool pflip_present = false;
bc7f670e
DF		 8069 struct {
8070 struct dc_surface_update surface_updates[MAX_SURFACES];
8071 struct dc_plane_info plane_infos[MAX_SURFACES];
8072 struct dc_scaling_info scaling_infos[MAX_SURFACES];
74aa7bd4 8073 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
bc7f670e 8074 struct dc_stream_update stream_update;
74aa7bd4 8075 } *bundle;
bc7f670e 8076
74aa7bd4 8077 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8a48b44c 8078
74aa7bd4
DF		 8079 if (!bundle) {
8080 dm_error("Failed to allocate update bundle\n");
4b510503
NK		 8081 goto cleanup;
8082 }
e7b07cee 8083
8ad27806
NK		 8084 /*
8085 * Disable the cursor first if we're disabling all the planes.
8086 * It'll remain on the screen after the planes are re-enabled
8087 * if we don't.
8088 */
8089 if (acrtc_state->active_planes == 0)
8090 amdgpu_dm_commit_cursors(state);
8091
e7b07cee 8092 /* update planes when needed */
263a4feb 8093 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
0bc9706d 8094 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 8095 struct drm_crtc_state *new_crtc_state;
0bc9706d 8096 struct drm_framebuffer *fb = new_plane_state->fb;
6eed95b0 8097 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
34bafd27 8098 bool plane_needs_flip;
c7af5f77 8099 struct dc_plane_state *dc_plane;
54d76575 8100 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee 8101
80c218d5
NK		 8102 /* Cursor plane is handled after stream updates */
8103 if (plane->type == DRM_PLANE_TYPE_CURSOR)
e7b07cee 8104 continue;
e7b07cee 8105
f5ba60fe
DD		 8106 if (!fb || !crtc || pcrtc != crtc)
8107 continue;
8108
8109 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8110 if (!new_crtc_state->active)
e7b07cee
HW		 8111 continue;
8112
bc7f670e 8113 dc_plane = dm_new_plane_state->dc_state;
e7b07cee 8114
74aa7bd4 8115 bundle->surface_updates[planes_count].surface = dc_plane;
bc7f670e 8116 if (new_pcrtc_state->color_mgmt_changed) {
74aa7bd4
DF		 8117 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8118 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
44efb784 8119 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
bc7f670e 8120 }
8a48b44c 8121
695af5f9
NK		 8122 fill_dc_scaling_info(new_plane_state,
8123 &bundle->scaling_infos[planes_count]);
8a48b44c 8124
695af5f9
NK		 8125 bundle->surface_updates[planes_count].scaling_info =
8126 &bundle->scaling_infos[planes_count];
8a48b44c 8127
f5031000 8128 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8a48b44c 8129
f5031000 8130 pflip_present = pflip_present || plane_needs_flip;
8a48b44c 8131
f5031000
DF		 8132 if (!plane_needs_flip) {
8133 planes_count += 1;
8134 continue;
8135 }
8a48b44c 8136
2fac0f53
CK		 8137 abo = gem_to_amdgpu_bo(fb->obj[0]);
8138
f8308898
AG		 8139 /*
8140 * Wait for all fences on this FB. Do limited wait to avoid
8141 * deadlock during GPU reset when this fence will not signal
8142 * but we hold reservation lock for the BO.
8143 */
52791eee 8144 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
2fac0f53 8145 false,
f8308898
AG		 8146 msecs_to_jiffies(5000));
8147 if (unlikely(r <= 0))
ed8a5fb2 8148 DRM_ERROR("Waiting for fences timed out!");
2fac0f53 8149
695af5f9 8150 fill_dc_plane_info_and_addr(
8ce5d842 8151 dm->adev, new_plane_state,
6eed95b0 8152 afb->tiling_flags,
695af5f9 8153 &bundle->plane_infos[planes_count],
87b7ebc2 8154 &bundle->flip_addrs[planes_count].address,
6eed95b0 8155 afb->tmz_surface, false);
87b7ebc2
RS		 8156
8157 DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",
8158 new_plane_state->plane->index,
8159 bundle->plane_infos[planes_count].dcc.enable);
695af5f9
NK		 8160
8161 bundle->surface_updates[planes_count].plane_info =
8162 &bundle->plane_infos[planes_count];
8a48b44c 8163
caff0e66
NK		 8164 /*
8165 * Only allow immediate flips for fast updates that don't
8166 * change FB pitch, DCC state, rotation or mirroing.
8167 */
f5031000 8168 bundle->flip_addrs[planes_count].flip_immediate =
4d85f45c 8169 crtc->state->async_flip &&
caff0e66 8170 acrtc_state->update_type == UPDATE_TYPE_FAST;
8a48b44c 8171
f5031000
DF		 8172 timestamp_ns = ktime_get_ns();
8173 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8174 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8175 bundle->surface_updates[planes_count].surface = dc_plane;
8a48b44c 8176
f5031000
DF		 8177 if (!bundle->surface_updates[planes_count].surface) {
8178 DRM_ERROR("No surface for CRTC: id=%d\n",
8179 acrtc_attach->crtc_id);
8180 continue;
bc7f670e
DF		 8181 }
8182
f5031000
DF		 8183 if (plane == pcrtc->primary)
8184 update_freesync_state_on_stream(
8185 dm,
8186 acrtc_state,
8187 acrtc_state->stream,
8188 dc_plane,
8189 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
bc7f670e 8190
f5031000
DF		 8191 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
8192 __func__,
8193 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8194 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
bc7f670e
DF		 8195
8196 planes_count += 1;
8197
8a48b44c
DF		 8198 }
8199
74aa7bd4 8200 if (pflip_present) {
634092b1
MK		 8201 if (!vrr_active) {
8202 /* Use old throttling in non-vrr fixed refresh rate mode
8203 * to keep flip scheduling based on target vblank counts
8204 * working in a backwards compatible way, e.g., for
8205 * clients using the GLX_OML_sync_control extension or
8206 * DRI3/Present extension with defined target_msc.
8207 */
e3eff4b5 8208 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
634092b1
MK		 8209 }
8210 else {
8211 /* For variable refresh rate mode only:
8212 * Get vblank of last completed flip to avoid > 1 vrr
8213 * flips per video frame by use of throttling, but allow
8214 * flip programming anywhere in the possibly large
8215 * variable vrr vblank interval for fine-grained flip
8216 * timing control and more opportunity to avoid stutter
8217 * on late submission of flips.
8218 */
8219 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5d1c59c4 8220 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
634092b1
MK		 8221 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8222 }
8223
fdd1fe57 8224 target_vblank = last_flip_vblank + wait_for_vblank;
8a48b44c
DF		 8225
8226 /*
8227 * Wait until we're out of the vertical blank period before the one
8228 * targeted by the flip
8229 */
8230 while ((acrtc_attach->enabled &&
8231 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8232 0, &vpos, &hpos, NULL,
8233 NULL, &pcrtc->hwmode)
8234 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8235 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8236 (int)(target_vblank -
e3eff4b5 8237 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8a48b44c
DF		 8238 usleep_range(1000, 1100);
8239 }
8240
8fe684e9
NK		 8241 /**
8242 * Prepare the flip event for the pageflip interrupt to handle.
8243 *
8244 * This only works in the case where we've already turned on the
8245 * appropriate hardware blocks (eg. HUBP) so in the transition case
8246 * from 0 -> n planes we have to skip a hardware generated event
8247 * and rely on sending it from software.
8248 */
8249 if (acrtc_attach->base.state->event &&
8250 acrtc_state->active_planes > 0) {
8a48b44c
DF		 8251 drm_crtc_vblank_get(pcrtc);
8252
8253 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8254
8255 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8256 prepare_flip_isr(acrtc_attach);
8257
8258 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8259 }
8260
8261 if (acrtc_state->stream) {
8a48b44c 8262 if (acrtc_state->freesync_vrr_info_changed)
74aa7bd4 8263 bundle->stream_update.vrr_infopacket =
8a48b44c 8264 &acrtc_state->stream->vrr_infopacket;
e7b07cee 8265 }
e7b07cee
HW		 8266 }
8267
bc92c065 8268 /* Update the planes if changed or disable if we don't have any. */
ed9656fb
ES		 8269 if ((planes_count || acrtc_state->active_planes == 0) &&
8270 acrtc_state->stream) {
b6e881c9 8271 bundle->stream_update.stream = acrtc_state->stream;
bc7f670e 8272 if (new_pcrtc_state->mode_changed) {
74aa7bd4
DF		 8273 bundle->stream_update.src = acrtc_state->stream->src;
8274 bundle->stream_update.dst = acrtc_state->stream->dst;
e7b07cee
HW		 8275 }
8276
cf020d49
NK		 8277 if (new_pcrtc_state->color_mgmt_changed) {
8278 /*
8279 * TODO: This isn't fully correct since we've actually
8280 * already modified the stream in place.
8281 */
8282 bundle->stream_update.gamut_remap =
8283 &acrtc_state->stream->gamut_remap_matrix;
8284 bundle->stream_update.output_csc_transform =
8285 &acrtc_state->stream->csc_color_matrix;
8286 bundle->stream_update.out_transfer_func =
8287 acrtc_state->stream->out_transfer_func;
8288 }
bc7f670e 8289
8a48b44c 8290 acrtc_state->stream->abm_level = acrtc_state->abm_level;
bc7f670e 8291 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
74aa7bd4 8292 bundle->stream_update.abm_level = &acrtc_state->abm_level;
44d09c6a 8293
e63e2491
EB		 8294 /*
8295 * If FreeSync state on the stream has changed then we need to
8296 * re-adjust the min/max bounds now that DC doesn't handle this
8297 * as part of commit.
8298 */
6f59f229 8299 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
e63e2491
EB		 8300 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8301 dc_stream_adjust_vmin_vmax(
8302 dm->dc, acrtc_state->stream,
585d450c 8303 &acrtc_attach->dm_irq_params.vrr_params.adjust);
e63e2491
EB		 8304 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8305 }
bc7f670e 8306 mutex_lock(&dm->dc_lock);
8c322309 8307 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
d1ebfdd8 8308 acrtc_state->stream->link->psr_settings.psr_allow_active)
8c322309
RL		 8309 amdgpu_dm_psr_disable(acrtc_state->stream);
8310
bc7f670e 8311 dc_commit_updates_for_stream(dm->dc,
74aa7bd4 8312 bundle->surface_updates,
bc7f670e
DF		 8313 planes_count,
8314 acrtc_state->stream,
263a4feb
AJ		 8315 &bundle->stream_update,
8316 dc_state);
8c322309 8317
8fe684e9
NK		 8318 /**
8319 * Enable or disable the interrupts on the backend.
8320 *
8321 * Most pipes are put into power gating when unused.
8322 *
8323 * When power gating is enabled on a pipe we lose the
8324 * interrupt enablement state when power gating is disabled.
8325 *
8326 * So we need to update the IRQ control state in hardware
8327 * whenever the pipe turns on (since it could be previously
8328 * power gated) or off (since some pipes can't be power gated
8329 * on some ASICs).
8330 */
8331 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
1348969a
LT		 8332 dm_update_pflip_irq_state(drm_to_adev(dev),
8333 acrtc_attach);
8fe684e9 8334
8c322309 8335 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
1cfbbdde 8336 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
d1ebfdd8 8337 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8c322309
RL		 8338 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8339 else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
d1ebfdd8
WW		 8340 acrtc_state->stream->link->psr_settings.psr_feature_enabled &&
8341 !acrtc_state->stream->link->psr_settings.psr_allow_active) {
8c322309
RL		 8342 amdgpu_dm_psr_enable(acrtc_state->stream);
8343 }
8344
bc7f670e 8345 mutex_unlock(&dm->dc_lock);
e7b07cee 8346 }
4b510503 8347
8ad27806
NK		 8348 /*
8349 * Update cursor state *after* programming all the planes.
8350 * This avoids redundant programming in the case where we're going
8351 * to be disabling a single plane - those pipes are being disabled.
8352 */
8353 if (acrtc_state->active_planes)
8354 amdgpu_dm_commit_cursors(state);
80c218d5 8355
4b510503 8356cleanup:
74aa7bd4 8357 kfree(bundle);
e7b07cee
HW		 8358}
8359
6ce8f316
NK		 8360static void amdgpu_dm_commit_audio(struct drm_device *dev,
8361 struct drm_atomic_state *state)
8362{
1348969a 8363 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 8364 struct amdgpu_dm_connector *aconnector;
8365 struct drm_connector *connector;
8366 struct drm_connector_state *old_con_state, *new_con_state;
8367 struct drm_crtc_state *new_crtc_state;
8368 struct dm_crtc_state *new_dm_crtc_state;
8369 const struct dc_stream_status *status;
8370 int i, inst;
8371
8372 /* Notify device removals. */
8373 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8374 if (old_con_state->crtc != new_con_state->crtc) {
8375 /* CRTC changes require notification. */
8376 goto notify;
8377 }
8378
8379 if (!new_con_state->crtc)
8380 continue;
8381
8382 new_crtc_state = drm_atomic_get_new_crtc_state(
8383 state, new_con_state->crtc);
8384
8385 if (!new_crtc_state)
8386 continue;
8387
8388 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8389 continue;
8390
8391 notify:
8392 aconnector = to_amdgpu_dm_connector(connector);
8393
8394 mutex_lock(&adev->dm.audio_lock);
8395 inst = aconnector->audio_inst;
8396 aconnector->audio_inst = -1;
8397 mutex_unlock(&adev->dm.audio_lock);
8398
8399 amdgpu_dm_audio_eld_notify(adev, inst);
8400 }
8401
8402 /* Notify audio device additions. */
8403 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8404 if (!new_con_state->crtc)
8405 continue;
8406
8407 new_crtc_state = drm_atomic_get_new_crtc_state(
8408 state, new_con_state->crtc);
8409
8410 if (!new_crtc_state)
8411 continue;
8412
8413 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8414 continue;
8415
8416 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8417 if (!new_dm_crtc_state->stream)
8418 continue;
8419
8420 status = dc_stream_get_status(new_dm_crtc_state->stream);
8421 if (!status)
8422 continue;
8423
8424 aconnector = to_amdgpu_dm_connector(connector);
8425
8426 mutex_lock(&adev->dm.audio_lock);
8427 inst = status->audio_inst;
8428 aconnector->audio_inst = inst;
8429 mutex_unlock(&adev->dm.audio_lock);
8430
8431 amdgpu_dm_audio_eld_notify(adev, inst);
8432 }
8433}
8434
1f6010a9 8435/*
27b3f4fc
LSL		 8436 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8437 * @crtc_state: the DRM CRTC state
8438 * @stream_state: the DC stream state.
8439 *
8440 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8441 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8442 */
8443static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8444 struct dc_stream_state *stream_state)
8445{
b9952f93 8446 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
27b3f4fc 8447}
e7b07cee 8448
b8592b48
LL		 8449/**
8450 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8451 * @state: The atomic state to commit
8452 *
8453 * This will tell DC to commit the constructed DC state from atomic_check,
8454 * programming the hardware. Any failures here implies a hardware failure, since
8455 * atomic check should have filtered anything non-kosher.
8456 */
7578ecda 8457static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 8458{
8459 struct drm_device *dev = state->dev;
1348969a 8460 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 8461 struct amdgpu_display_manager *dm = &adev->dm;
8462 struct dm_atomic_state *dm_state;
eb3dc897 8463 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 8464 uint32_t i, j;
5cc6dcbd 8465 struct drm_crtc *crtc;
0bc9706d 8466 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 8467 unsigned long flags;
8468 bool wait_for_vblank = true;
8469 struct drm_connector *connector;
c2cea706 8470 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 8471 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 8472 int crtc_disable_count = 0;
6ee90e88 8473 bool mode_set_reset_required = false;
e7b07cee 8474
e8a98235
RS		 8475 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8476
e7b07cee
HW		 8477 drm_atomic_helper_update_legacy_modeset_state(dev, state);
8478
eb3dc897
NK		 8479 dm_state = dm_atomic_get_new_state(state);
8480 if (dm_state && dm_state->context) {
8481 dc_state = dm_state->context;
8482 } else {
8483 /* No state changes, retain current state. */
813d20dc 8484 dc_state_temp = dc_create_state(dm->dc);
eb3dc897
NK		 8485 ASSERT(dc_state_temp);
8486 dc_state = dc_state_temp;
8487 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8488 }
e7b07cee 8489
6d90a208
AP		 8490 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8491 new_crtc_state, i) {
8492 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8493
8494 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8495
8496 if (old_crtc_state->active &&
8497 (!new_crtc_state->active ||
8498 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8499 manage_dm_interrupts(adev, acrtc, false);
8500 dc_stream_release(dm_old_crtc_state->stream);
8501 }
8502 }
8503
8976f73b
RS		 8504 drm_atomic_helper_calc_timestamping_constants(state);
8505
e7b07cee 8506 /* update changed items */
0bc9706d 8507 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 8508 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 8509
54d76575
LSL		 8510 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8511 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 8512
f1ad2f5e 8513 DRM_DEBUG_DRIVER(
e7b07cee
HW		 8514 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8515 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8516 "connectors_changed:%d\n",
8517 acrtc->crtc_id,
0bc9706d
LSL		 8518 new_crtc_state->enable,
8519 new_crtc_state->active,
8520 new_crtc_state->planes_changed,
8521 new_crtc_state->mode_changed,
8522 new_crtc_state->active_changed,
8523 new_crtc_state->connectors_changed);
e7b07cee 8524
5c68c652
VL		 8525 /* Disable cursor if disabling crtc */
8526 if (old_crtc_state->active && !new_crtc_state->active) {
8527 struct dc_cursor_position position;
8528
8529 memset(&position, 0, sizeof(position));
8530 mutex_lock(&dm->dc_lock);
8531 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8532 mutex_unlock(&dm->dc_lock);
8533 }
8534
27b3f4fc
LSL		 8535 /* Copy all transient state flags into dc state */
8536 if (dm_new_crtc_state->stream) {
8537 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8538 dm_new_crtc_state->stream);
8539 }
8540
e7b07cee
HW		 8541 /* handles headless hotplug case, updating new_state and
8542 * aconnector as needed
8543 */
8544
54d76575 8545 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 8546
f1ad2f5e 8547 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 8548
54d76575 8549 if (!dm_new_crtc_state->stream) {
e7b07cee 8550 /*
b830ebc9
HW		 8551 * this could happen because of issues with
8552 * userspace notifications delivery.
8553 * In this case userspace tries to set mode on
1f6010a9
DF		 8554 * display which is disconnected in fact.
8555 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 8556 * We expect reset mode will come soon.
8557 *
8558 * This can also happen when unplug is done
8559 * during resume sequence ended
8560 *
8561 * In this case, we want to pretend we still
8562 * have a sink to keep the pipe running so that
8563 * hw state is consistent with the sw state
8564 */
f1ad2f5e 8565 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 8566 __func__, acrtc->base.base.id);
8567 continue;
8568 }
8569
54d76575
LSL		 8570 if (dm_old_crtc_state->stream)
8571 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 8572
97028037
LP		 8573 pm_runtime_get_noresume(dev->dev);
8574
e7b07cee 8575 acrtc->enabled = true;
0bc9706d
LSL		 8576 acrtc->hw_mode = new_crtc_state->mode;
8577 crtc->hwmode = new_crtc_state->mode;
6ee90e88 8578 mode_set_reset_required = true;
0bc9706d 8579 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 8580 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 8581 /* i.e. reset mode */
6ee90e88 8582 if (dm_old_crtc_state->stream)
54d76575 8583 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6f59f229 8584
6ee90e88 8585 mode_set_reset_required = true;
e7b07cee
HW		 8586 }
8587 } /* for_each_crtc_in_state() */
8588
eb3dc897 8589 if (dc_state) {
6ee90e88 8590 /* if there mode set or reset, disable eDP PSR */
8591 if (mode_set_reset_required)
8592 amdgpu_dm_psr_disable_all(dm);
8593
eb3dc897 8594 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 8595 mutex_lock(&dm->dc_lock);
eb3dc897 8596 WARN_ON(!dc_commit_state(dm->dc, dc_state));
674e78ac 8597 mutex_unlock(&dm->dc_lock);
fa2123db 8598 }
e7b07cee 8599
0bc9706d 8600 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 8601 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 8602
54d76575 8603 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 8604
54d76575 8605 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 8606 const struct dc_stream_status *status =
54d76575 8607 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 8608
eb3dc897 8609 if (!status)
09f609c3
LL		 8610 status = dc_stream_get_status_from_state(dc_state,
8611 dm_new_crtc_state->stream);
e7b07cee 8612 if (!status)
54d76575 8613 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 8614 else
8615 acrtc->otg_inst = status->primary_otg_inst;
8616 }
8617 }
0c8620d6
BL		 8618#ifdef CONFIG_DRM_AMD_DC_HDCP
8619 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8620 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8621 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8622 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8623
8624 new_crtc_state = NULL;
8625
8626 if (acrtc)
8627 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8628
8629 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8630
8631 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8632 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8633 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8634 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
97f6c917 8635 dm_new_con_state->update_hdcp = true;
0c8620d6
BL		 8636 continue;
8637 }
8638
8639 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
b1abe558
BL		 8640 hdcp_update_display(
8641 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
23eb4191 8642 new_con_state->hdcp_content_type,
0e86d3d4 8643 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
0c8620d6
BL		 8644 }
8645#endif
e7b07cee 8646
02d6a6fc 8647 /* Handle connector state changes */
c2cea706 8648 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 8649 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8650 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8651 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
263a4feb 8652 struct dc_surface_update dummy_updates[MAX_SURFACES];
19afd799 8653 struct dc_stream_update stream_update;
b232d4ed 8654 struct dc_info_packet hdr_packet;
e7b07cee 8655 struct dc_stream_status *status = NULL;
b232d4ed 8656 bool abm_changed, hdr_changed, scaling_changed;
e7b07cee 8657
263a4feb 8658 memset(&dummy_updates, 0, sizeof(dummy_updates));
19afd799
NC		 8659 memset(&stream_update, 0, sizeof(stream_update));
8660
44d09c6a 8661 if (acrtc) {
0bc9706d 8662 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 8663 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8664 }
0bc9706d 8665
e7b07cee 8666 /* Skip any modesets/resets */
0bc9706d 8667 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 8668 continue;
8669
54d76575 8670 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 8671 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8672
b232d4ed
NK		 8673 scaling_changed = is_scaling_state_different(dm_new_con_state,
8674 dm_old_con_state);
8675
8676 abm_changed = dm_new_crtc_state->abm_level !=
8677 dm_old_crtc_state->abm_level;
8678
8679 hdr_changed =
8680 is_hdr_metadata_different(old_con_state, new_con_state);
8681
8682 if (!scaling_changed && !abm_changed && !hdr_changed)
c1ee92f9 8683 continue;
e7b07cee 8684
b6e881c9 8685 stream_update.stream = dm_new_crtc_state->stream;
b232d4ed 8686 if (scaling_changed) {
02d6a6fc 8687 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
b6e881c9 8688 dm_new_con_state, dm_new_crtc_state->stream);
e7b07cee 8689
02d6a6fc
DF		 8690 stream_update.src = dm_new_crtc_state->stream->src;
8691 stream_update.dst = dm_new_crtc_state->stream->dst;
8692 }
8693
b232d4ed 8694 if (abm_changed) {
02d6a6fc
DF		 8695 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8696
8697 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8698 }
70e8ffc5 8699
b232d4ed
NK		 8700 if (hdr_changed) {
8701 fill_hdr_info_packet(new_con_state, &hdr_packet);
8702 stream_update.hdr_static_metadata = &hdr_packet;
8703 }
8704
54d76575 8705 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 8706 WARN_ON(!status);
3be5262e 8707 WARN_ON(!status->plane_count);
e7b07cee 8708
02d6a6fc
DF		 8709 /*
8710 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8711 * Here we create an empty update on each plane.
8712 * To fix this, DC should permit updating only stream properties.
8713 */
8714 for (j = 0; j < status->plane_count; j++)
263a4feb 8715 dummy_updates[j].surface = status->plane_states[0];
02d6a6fc
DF		 8716
8717
8718 mutex_lock(&dm->dc_lock);
8719 dc_commit_updates_for_stream(dm->dc,
263a4feb 8720 dummy_updates,
02d6a6fc
DF		 8721 status->plane_count,
8722 dm_new_crtc_state->stream,
263a4feb
AJ		 8723 &stream_update,
8724 dc_state);
02d6a6fc 8725 mutex_unlock(&dm->dc_lock);
e7b07cee
HW		 8726 }
8727
b5e83f6f 8728 /* Count number of newly disabled CRTCs for dropping PM refs later. */
e1fc2dca 8729 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
057be086 8730 new_crtc_state, i) {
fe2a1965
LP		 8731 if (old_crtc_state->active && !new_crtc_state->active)
8732 crtc_disable_count++;
8733
54d76575 8734 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca 8735 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
66b0c973 8736
585d450c
AP		 8737 /* For freesync config update on crtc state and params for irq */
8738 update_stream_irq_parameters(dm, dm_new_crtc_state);
057be086 8739
66b0c973
MK		 8740 /* Handle vrr on->off / off->on transitions */
8741 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
8742 dm_new_crtc_state);
e7b07cee
HW		 8743 }
8744
8fe684e9
NK		 8745 /**
8746 * Enable interrupts for CRTCs that are newly enabled or went through
8747 * a modeset. It was intentionally deferred until after the front end
8748 * state was modified to wait until the OTG was on and so the IRQ
8749 * handlers didn't access stale or invalid state.
8750 */
8751 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8752 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8e7b6fee 8753#ifdef CONFIG_DEBUG_FS
86bc2219 8754 bool configure_crc = false;
8e7b6fee
WL		 8755 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8756#endif
585d450c
AP		 8757 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8758
8fe684e9
NK		 8759 if (new_crtc_state->active &&
8760 (!old_crtc_state->active ||
8761 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
585d450c
AP		 8762 dc_stream_retain(dm_new_crtc_state->stream);
8763 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8fe684e9 8764 manage_dm_interrupts(adev, acrtc, true);
e2881d6d 8765
24eb9374 8766#ifdef CONFIG_DEBUG_FS
8fe684e9
NK		 8767 /**
8768 * Frontend may have changed so reapply the CRC capture
8769 * settings for the stream.
8770 */
8771 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8e7b6fee
WL		 8772 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8773 cur_crc_src = acrtc->dm_irq_params.crc_src;
8774 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
c920888c 8775
8e7b6fee 8776 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
86bc2219
WL		 8777 configure_crc = true;
8778#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8779 if (amdgpu_dm_crc_window_is_activated(crtc))
8780 configure_crc = false;
8781#endif
e2881d6d 8782 }
86bc2219
WL		 8783
8784 if (configure_crc)
8785 amdgpu_dm_crtc_configure_crc_source(
8786 crtc, dm_new_crtc_state, cur_crc_src);
24eb9374 8787#endif
8fe684e9
NK		 8788 }
8789 }
e7b07cee 8790
420cd472 8791 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
4d85f45c 8792 if (new_crtc_state->async_flip)
420cd472
DF		 8793 wait_for_vblank = false;
8794
e7b07cee 8795 /* update planes when needed per crtc*/
5cc6dcbd 8796 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 8797 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 8798
54d76575 8799 if (dm_new_crtc_state->stream)
eb3dc897 8800 amdgpu_dm_commit_planes(state, dc_state, dev,
420cd472 8801 dm, crtc, wait_for_vblank);
e7b07cee
HW		 8802 }
8803
6ce8f316
NK		 8804 /* Update audio instances for each connector. */
8805 amdgpu_dm_commit_audio(dev, state);
8806
e7b07cee
HW		 8807 /*
8808 * send vblank event on all events not handled in flip and
8809 * mark consumed event for drm_atomic_helper_commit_hw_done
8810 */
4a580877 8811 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
0bc9706d 8812 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 8813
0bc9706d
LSL		 8814 if (new_crtc_state->event)
8815 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 8816
0bc9706d 8817 new_crtc_state->event = NULL;
e7b07cee 8818 }
4a580877 8819 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
e7b07cee 8820
29c8f234
LL		 8821 /* Signal HW programming completion */
8822 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 8823
8824 if (wait_for_vblank)
320a1274 8825 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 8826
8827 drm_atomic_helper_cleanup_planes(dev, state);
97028037 8828
5f6fab24
AD		 8829 /* return the stolen vga memory back to VRAM */
8830 if (!adev->mman.keep_stolen_vga_memory)
8831 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8832 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8833
1f6010a9
DF		 8834 /*
8835 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 8836 * so we can put the GPU into runtime suspend if we're not driving any
8837 * displays anymore
8838 */
fe2a1965
LP		 8839 for (i = 0; i < crtc_disable_count; i++)
8840 pm_runtime_put_autosuspend(dev->dev);
97028037 8841 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 8842
8843 if (dc_state_temp)
8844 dc_release_state(dc_state_temp);
e7b07cee
HW		 8845}
8846
8847
8848static int dm_force_atomic_commit(struct drm_connector *connector)
8849{
8850 int ret = 0;
8851 struct drm_device *ddev = connector->dev;
8852 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8853 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8854 struct drm_plane *plane = disconnected_acrtc->base.primary;
8855 struct drm_connector_state *conn_state;
8856 struct drm_crtc_state *crtc_state;
8857 struct drm_plane_state *plane_state;
8858
8859 if (!state)
8860 return -ENOMEM;
8861
8862 state->acquire_ctx = ddev->mode_config.acquire_ctx;
8863
8864 /* Construct an atomic state to restore previous display setting */
8865
8866 /*
8867 * Attach connectors to drm_atomic_state
8868 */
8869 conn_state = drm_atomic_get_connector_state(state, connector);
8870
8871 ret = PTR_ERR_OR_ZERO(conn_state);
8872 if (ret)
2dc39051 8873 goto out;
e7b07cee
HW		 8874
8875 /* Attach crtc to drm_atomic_state*/
8876 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8877
8878 ret = PTR_ERR_OR_ZERO(crtc_state);
8879 if (ret)
2dc39051 8880 goto out;
e7b07cee
HW		 8881
8882 /* force a restore */
8883 crtc_state->mode_changed = true;
8884
8885 /* Attach plane to drm_atomic_state */
8886 plane_state = drm_atomic_get_plane_state(state, plane);
8887
8888 ret = PTR_ERR_OR_ZERO(plane_state);
8889 if (ret)
2dc39051 8890 goto out;
e7b07cee
HW		 8891
8892 /* Call commit internally with the state we just constructed */
8893 ret = drm_atomic_commit(state);
e7b07cee 8894
2dc39051 8895out:
e7b07cee 8896 drm_atomic_state_put(state);
2dc39051
VL		 8897 if (ret)
8898 DRM_ERROR("Restoring old state failed with %i\n", ret);
e7b07cee
HW		 8899
8900 return ret;
8901}
8902
8903/*
1f6010a9
DF		 8904 * This function handles all cases when set mode does not come upon hotplug.
8905 * This includes when a display is unplugged then plugged back into the
8906 * same port and when running without usermode desktop manager supprot
e7b07cee 8907 */
3ee6b26b
AD		 8908void dm_restore_drm_connector_state(struct drm_device *dev,
8909 struct drm_connector *connector)
e7b07cee 8910{
c84dec2f 8911 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 8912 struct amdgpu_crtc *disconnected_acrtc;
8913 struct dm_crtc_state *acrtc_state;
8914
8915 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8916 return;
8917
8918 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 8919 if (!disconnected_acrtc)
8920 return;
e7b07cee 8921
70e8ffc5
HW		 8922 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8923 if (!acrtc_state->stream)
e7b07cee
HW		 8924 return;
8925
8926 /*
8927 * If the previous sink is not released and different from the current,
8928 * we deduce we are in a state where we can not rely on usermode call
8929 * to turn on the display, so we do it here
8930 */
8931 if (acrtc_state->stream->sink != aconnector->dc_sink)
8932 dm_force_atomic_commit(&aconnector->base);
8933}
8934
1f6010a9 8935/*
e7b07cee
HW		 8936 * Grabs all modesetting locks to serialize against any blocking commits,
8937 * Waits for completion of all non blocking commits.
8938 */
3ee6b26b
AD		 8939static int do_aquire_global_lock(struct drm_device *dev,
8940 struct drm_atomic_state *state)
e7b07cee
HW		 8941{
8942 struct drm_crtc *crtc;
8943 struct drm_crtc_commit *commit;
8944 long ret;
8945
1f6010a9
DF		 8946 /*
8947 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 8948 * ensure that when the framework release it the
8949 * extra locks we are locking here will get released to
8950 */
8951 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8952 if (ret)
8953 return ret;
8954
8955 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8956 spin_lock(&crtc->commit_lock);
8957 commit = list_first_entry_or_null(&crtc->commit_list,
8958 struct drm_crtc_commit, commit_entry);
8959 if (commit)
8960 drm_crtc_commit_get(commit);
8961 spin_unlock(&crtc->commit_lock);
8962
8963 if (!commit)
8964 continue;
8965
1f6010a9
DF		 8966 /*
8967 * Make sure all pending HW programming completed and
e7b07cee
HW		 8968 * page flips done
8969 */
8970 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8971
8972 if (ret > 0)
8973 ret = wait_for_completion_interruptible_timeout(
8974 &commit->flip_done, 10*HZ);
8975
8976 if (ret == 0)
8977 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 8978 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 8979
8980 drm_crtc_commit_put(commit);
8981 }
8982
8983 return ret < 0 ? ret : 0;
8984}
8985
bb47de73
NK		 8986static void get_freesync_config_for_crtc(
8987 struct dm_crtc_state *new_crtc_state,
8988 struct dm_connector_state *new_con_state)
98e6436d
AK		 8989{
8990 struct mod_freesync_config config = {0};
98e6436d
AK		 8991 struct amdgpu_dm_connector *aconnector =
8992 to_amdgpu_dm_connector(new_con_state->base.connector);
a057ec46 8993 struct drm_display_mode *mode = &new_crtc_state->base.mode;
0ab925d3 8994 int vrefresh = drm_mode_vrefresh(mode);
6f59f229 8995 bool fs_vid_mode = false;
98e6436d 8996
a057ec46 8997 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
0ab925d3
NK		 8998 vrefresh >= aconnector->min_vfreq &&
8999 vrefresh <= aconnector->max_vfreq;
bb47de73 9000
a057ec46
IB		 9001 if (new_crtc_state->vrr_supported) {
9002 new_crtc_state->stream->ignore_msa_timing_param = true;
6f59f229
AP		 9003 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9004
9005 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9006 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
69ff8845 9007 config.vsif_supported = true;
180db303 9008 config.btr = true;
98e6436d 9009
6f59f229
AP		 9010 if (fs_vid_mode) {
9011 config.state = VRR_STATE_ACTIVE_FIXED;
9012 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9013 goto out;
9014 } else if (new_crtc_state->base.vrr_enabled) {
9015 config.state = VRR_STATE_ACTIVE_VARIABLE;
9016 } else {
9017 config.state = VRR_STATE_INACTIVE;
9018 }
9019 }
9020out:
bb47de73
NK		 9021 new_crtc_state->freesync_config = config;
9022}
98e6436d 9023
bb47de73
NK		 9024static void reset_freesync_config_for_crtc(
9025 struct dm_crtc_state *new_crtc_state)
9026{
9027 new_crtc_state->vrr_supported = false;
98e6436d 9028
bb47de73
NK		 9029 memset(&new_crtc_state->vrr_infopacket, 0,
9030 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 9031}
9032
6f59f229
AP		 9033static bool
9034is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9035 struct drm_crtc_state *new_crtc_state)
9036{
9037 struct drm_display_mode old_mode, new_mode;
9038
9039 if (!old_crtc_state || !new_crtc_state)
9040 return false;
9041
9042 old_mode = old_crtc_state->mode;
9043 new_mode = new_crtc_state->mode;
9044
9045 if (old_mode.clock == new_mode.clock &&
9046 old_mode.hdisplay == new_mode.hdisplay &&
9047 old_mode.vdisplay == new_mode.vdisplay &&
9048 old_mode.htotal == new_mode.htotal &&
9049 old_mode.vtotal != new_mode.vtotal &&
9050 old_mode.hsync_start == new_mode.hsync_start &&
9051 old_mode.vsync_start != new_mode.vsync_start &&
9052 old_mode.hsync_end == new_mode.hsync_end &&
9053 old_mode.vsync_end != new_mode.vsync_end &&
9054 old_mode.hskew == new_mode.hskew &&
9055 old_mode.vscan == new_mode.vscan &&
9056 (old_mode.vsync_end - old_mode.vsync_start) ==
9057 (new_mode.vsync_end - new_mode.vsync_start))
9058 return true;
9059
9060 return false;
9061}
9062
9063static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9064 uint64_t num, den, res;
9065 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9066
9067 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9068
9069 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9070 den = (unsigned long long)new_crtc_state->mode.htotal *
9071 (unsigned long long)new_crtc_state->mode.vtotal;
9072
9073 res = div_u64(num, den);
9074 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9075}
9076
4b9674e5
LL		 9077static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9078 struct drm_atomic_state *state,
9079 struct drm_crtc *crtc,
9080 struct drm_crtc_state *old_crtc_state,
9081 struct drm_crtc_state *new_crtc_state,
9082 bool enable,
9083 bool *lock_and_validation_needed)
e7b07cee 9084{
eb3dc897 9085 struct dm_atomic_state *dm_state = NULL;
54d76575 9086 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 9087 struct dc_stream_state *new_stream;
62f55537 9088 int ret = 0;
d4d4a645 9089
1f6010a9
DF		 9090 /*
9091 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9092 * update changed items
9093 */
4b9674e5
LL		 9094 struct amdgpu_crtc *acrtc = NULL;
9095 struct amdgpu_dm_connector *aconnector = NULL;
9096 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9097 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
e7b07cee 9098
4b9674e5 9099 new_stream = NULL;
9635b754 9100
4b9674e5
LL		 9101 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9102 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9103 acrtc = to_amdgpu_crtc(crtc);
4b9674e5 9104 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 9105
4b9674e5
LL		 9106 /* TODO This hack should go away */
9107 if (aconnector && enable) {
9108 /* Make sure fake sink is created in plug-in scenario */
9109 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9110 &aconnector->base);
9111 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9112 &aconnector->base);
19f89e23 9113
4b9674e5
LL		 9114 if (IS_ERR(drm_new_conn_state)) {
9115 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9116 goto fail;
9117 }
19f89e23 9118
4b9674e5
LL		 9119 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9120 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 9121
02d35a67
JFZ		 9122 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9123 goto skip_modeset;
9124
cbd14ae7
SW		 9125 new_stream = create_validate_stream_for_sink(aconnector,
9126 &new_crtc_state->mode,
9127 dm_new_conn_state,
9128 dm_old_crtc_state->stream);
19f89e23 9129
4b9674e5
LL		 9130 /*
9131 * we can have no stream on ACTION_SET if a display
9132 * was disconnected during S3, in this case it is not an
9133 * error, the OS will be updated after detection, and
9134 * will do the right thing on next atomic commit
9135 */
19f89e23 9136
4b9674e5
LL		 9137 if (!new_stream) {
9138 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9139 __func__, acrtc->base.base.id);
9140 ret = -ENOMEM;
9141 goto fail;
9142 }
e7b07cee 9143
3d4e52d0
VL		 9144 /*
9145 * TODO: Check VSDB bits to decide whether this should
9146 * be enabled or not.
9147 */
9148 new_stream->triggered_crtc_reset.enabled =
9149 dm->force_timing_sync;
9150
4b9674e5 9151 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 9152
88694af9
NK		 9153 ret = fill_hdr_info_packet(drm_new_conn_state,
9154 &new_stream->hdr_static_metadata);
9155 if (ret)
9156 goto fail;
9157
7e930949
NK		 9158 /*
9159 * If we already removed the old stream from the context
9160 * (and set the new stream to NULL) then we can't reuse
9161 * the old stream even if the stream and scaling are unchanged.
9162 * We'll hit the BUG_ON and black screen.
9163 *
9164 * TODO: Refactor this function to allow this check to work
9165 * in all conditions.
9166 */
6f59f229
AP		 9167 if (amdgpu_freesync_vid_mode &&
9168 dm_new_crtc_state->stream &&
9169 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9170 goto skip_modeset;
9171
7e930949
NK		 9172 if (dm_new_crtc_state->stream &&
9173 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4b9674e5
LL		 9174 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9175 new_crtc_state->mode_changed = false;
9176 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9177 new_crtc_state->mode_changed);
62f55537 9178 }
4b9674e5 9179 }
b830ebc9 9180
02d35a67 9181 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 9182 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9183 goto skip_modeset;
e7b07cee 9184
4b9674e5
LL		 9185 DRM_DEBUG_DRIVER(
9186 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9187 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9188 "connectors_changed:%d\n",
9189 acrtc->crtc_id,
9190 new_crtc_state->enable,
9191 new_crtc_state->active,
9192 new_crtc_state->planes_changed,
9193 new_crtc_state->mode_changed,
9194 new_crtc_state->active_changed,
9195 new_crtc_state->connectors_changed);
62f55537 9196
4b9674e5
LL		 9197 /* Remove stream for any changed/disabled CRTC */
9198 if (!enable) {
62f55537 9199
4b9674e5
LL		 9200 if (!dm_old_crtc_state->stream)
9201 goto skip_modeset;
eb3dc897 9202
6f59f229
AP		 9203 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9204 is_timing_unchanged_for_freesync(new_crtc_state,
9205 old_crtc_state)) {
9206 new_crtc_state->mode_changed = false;
9207 DRM_DEBUG_DRIVER(
9208 "Mode change not required for front porch change, "
9209 "setting mode_changed to %d",
9210 new_crtc_state->mode_changed);
9211
9212 set_freesync_fixed_config(dm_new_crtc_state);
9213
9214 goto skip_modeset;
9215 } else if (amdgpu_freesync_vid_mode && aconnector &&
9216 is_freesync_video_mode(&new_crtc_state->mode,
9217 aconnector)) {
9218 set_freesync_fixed_config(dm_new_crtc_state);
9219 }
9220
4b9674e5
LL		 9221 ret = dm_atomic_get_state(state, &dm_state);
9222 if (ret)
9223 goto fail;
e7b07cee 9224
4b9674e5
LL		 9225 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9226 crtc->base.id);
62f55537 9227
4b9674e5
LL		 9228 /* i.e. reset mode */
9229 if (dc_remove_stream_from_ctx(
9230 dm->dc,
9231 dm_state->context,
9232 dm_old_crtc_state->stream) != DC_OK) {
9233 ret = -EINVAL;
9234 goto fail;
9235 }
62f55537 9236
4b9674e5
LL		 9237 dc_stream_release(dm_old_crtc_state->stream);
9238 dm_new_crtc_state->stream = NULL;
bb47de73 9239
4b9674e5 9240 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 9241
4b9674e5 9242 *lock_and_validation_needed = true;
62f55537 9243
4b9674e5
LL		 9244 } else {/* Add stream for any updated/enabled CRTC */
9245 /*
9246 * Quick fix to prevent NULL pointer on new_stream when
9247 * added MST connectors not found in existing crtc_state in the chained mode
9248 * TODO: need to dig out the root cause of that
9249 */
9250 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
9251 goto skip_modeset;
62f55537 9252
4b9674e5
LL		 9253 if (modereset_required(new_crtc_state))
9254 goto skip_modeset;
62f55537 9255
4b9674e5
LL		 9256 if (modeset_required(new_crtc_state, new_stream,
9257 dm_old_crtc_state->stream)) {
62f55537 9258
4b9674e5 9259 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 9260
4b9674e5
LL		 9261 ret = dm_atomic_get_state(state, &dm_state);
9262 if (ret)
9263 goto fail;
27b3f4fc 9264
4b9674e5 9265 dm_new_crtc_state->stream = new_stream;
62f55537 9266
4b9674e5 9267 dc_stream_retain(new_stream);
1dc90497 9268
4b9674e5
LL		 9269 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
9270 crtc->base.id);
1dc90497 9271
4b9674e5
LL		 9272 if (dc_add_stream_to_ctx(
9273 dm->dc,
9274 dm_state->context,
9275 dm_new_crtc_state->stream) != DC_OK) {
9276 ret = -EINVAL;
9277 goto fail;
9b690ef3
BL		 9278 }
9279
4b9674e5
LL		 9280 *lock_and_validation_needed = true;
9281 }
9282 }
e277adc5 9283
4b9674e5
LL		 9284skip_modeset:
9285 /* Release extra reference */
9286 if (new_stream)
9287 dc_stream_release(new_stream);
e277adc5 9288
4b9674e5
LL		 9289 /*
9290 * We want to do dc stream updates that do not require a
9291 * full modeset below.
9292 */
2afda735 9293 if (!(enable && aconnector && new_crtc_state->active))
4b9674e5
LL		 9294 return 0;
9295 /*
9296 * Given above conditions, the dc state cannot be NULL because:
9297 * 1. We're in the process of enabling CRTCs (just been added
9298 * to the dc context, or already is on the context)
9299 * 2. Has a valid connector attached, and
9300 * 3. Is currently active and enabled.
9301 * => The dc stream state currently exists.
9302 */
9303 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 9304
4b9674e5
LL		 9305 /* Scaling or underscan settings */
9306 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
9307 update_stream_scaling_settings(
9308 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 9309
b05e2c5e
DF		 9310 /* ABM settings */
9311 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9312
4b9674e5
LL		 9313 /*
9314 * Color management settings. We also update color properties
9315 * when a modeset is needed, to ensure it gets reprogrammed.
9316 */
9317 if (dm_new_crtc_state->base.color_mgmt_changed ||
9318 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
cf020d49 9319 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
4b9674e5
LL		 9320 if (ret)
9321 goto fail;
62f55537 9322 }
e7b07cee 9323
4b9674e5
LL		 9324 /* Update Freesync settings. */
9325 get_freesync_config_for_crtc(dm_new_crtc_state,
9326 dm_new_conn_state);
9327
62f55537 9328 return ret;
9635b754
DS		 9329
9330fail:
9331 if (new_stream)
9332 dc_stream_release(new_stream);
9333 return ret;
62f55537 9334}
9b690ef3 9335
f6ff2a08
NK		 9336static bool should_reset_plane(struct drm_atomic_state *state,
9337 struct drm_plane *plane,
9338 struct drm_plane_state *old_plane_state,
9339 struct drm_plane_state *new_plane_state)
9340{
9341 struct drm_plane *other;
9342 struct drm_plane_state *old_other_state, *new_other_state;
9343 struct drm_crtc_state *new_crtc_state;
9344 int i;
9345
70a1efac
NK		 9346 /*
9347 * TODO: Remove this hack once the checks below are sufficient
9348 * enough to determine when we need to reset all the planes on
9349 * the stream.
9350 */
9351 if (state->allow_modeset)
9352 return true;
9353
f6ff2a08
NK		 9354 /* Exit early if we know that we're adding or removing the plane. */
9355 if (old_plane_state->crtc != new_plane_state->crtc)
9356 return true;
9357
9358 /* old crtc == new_crtc == NULL, plane not in context. */
9359 if (!new_plane_state->crtc)
9360 return false;
9361
9362 new_crtc_state =
9363 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9364
9365 if (!new_crtc_state)
9366 return true;
9367
7316c4ad
NK		 9368 /* CRTC Degamma changes currently require us to recreate planes. */
9369 if (new_crtc_state->color_mgmt_changed)
9370 return true;
9371
f6ff2a08
NK		 9372 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9373 return true;
9374
9375 /*
9376 * If there are any new primary or overlay planes being added or
9377 * removed then the z-order can potentially change. To ensure
9378 * correct z-order and pipe acquisition the current DC architecture
9379 * requires us to remove and recreate all existing planes.
9380 *
9381 * TODO: Come up with a more elegant solution for this.
9382 */
9383 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
6eed95b0 9384 struct amdgpu_framebuffer *old_afb, *new_afb;
f6ff2a08
NK		 9385 if (other->type == DRM_PLANE_TYPE_CURSOR)
9386 continue;
9387
9388 if (old_other_state->crtc != new_plane_state->crtc &&
9389 new_other_state->crtc != new_plane_state->crtc)
9390 continue;
9391
9392 if (old_other_state->crtc != new_other_state->crtc)
9393 return true;
9394
dc4cb30d
NK		 9395 /* Src/dst size and scaling updates. */
9396 if (old_other_state->src_w != new_other_state->src_w ||
9397 old_other_state->src_h != new_other_state->src_h ||
9398 old_other_state->crtc_w != new_other_state->crtc_w ||
9399 old_other_state->crtc_h != new_other_state->crtc_h)
9400 return true;
9401
9402 /* Rotation / mirroring updates. */
9403 if (old_other_state->rotation != new_other_state->rotation)
9404 return true;
9405
9406 /* Blending updates. */
9407 if (old_other_state->pixel_blend_mode !=
9408 new_other_state->pixel_blend_mode)
9409 return true;
9410
9411 /* Alpha updates. */
9412 if (old_other_state->alpha != new_other_state->alpha)
9413 return true;
9414
9415 /* Colorspace changes. */
9416 if (old_other_state->color_range != new_other_state->color_range ||
9417 old_other_state->color_encoding != new_other_state->color_encoding)
9418 return true;
9419
9a81cc60
NK		 9420 /* Framebuffer checks fall at the end. */
9421 if (!old_other_state->fb || !new_other_state->fb)
9422 continue;
9423
9424 /* Pixel format changes can require bandwidth updates. */
9425 if (old_other_state->fb->format != new_other_state->fb->format)
9426 return true;
9427
6eed95b0
BN		 9428 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9429 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9a81cc60
NK		 9430
9431 /* Tiling and DCC changes also require bandwidth updates. */
37384b3f
BN		 9432 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9433 old_afb->base.modifier != new_afb->base.modifier)
f6ff2a08
NK		 9434 return true;
9435 }
9436
9437 return false;
9438}
9439
b0455fda
SS		 9440static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9441 struct drm_plane_state *new_plane_state,
9442 struct drm_framebuffer *fb)
9443{
e72868c4
SS		 9444 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9445 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
b0455fda 9446 unsigned int pitch;
e72868c4 9447 bool linear;
b0455fda
SS		 9448
9449 if (fb->width > new_acrtc->max_cursor_width ||
9450 fb->height > new_acrtc->max_cursor_height) {
9451 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9452 new_plane_state->fb->width,
9453 new_plane_state->fb->height);
9454 return -EINVAL;
9455 }
9456 if (new_plane_state->src_w != fb->width << 16 ||
9457 new_plane_state->src_h != fb->height << 16) {
9458 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9459 return -EINVAL;
9460 }
9461
9462 /* Pitch in pixels */
9463 pitch = fb->pitches[0] / fb->format->cpp[0];
9464
9465 if (fb->width != pitch) {
9466 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9467 fb->width, pitch);
9468 return -EINVAL;
9469 }
9470
9471 switch (pitch) {
9472 case 64:
9473 case 128:
9474 case 256:
9475 /* FB pitch is supported by cursor plane */
9476 break;
9477 default:
9478 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9479 return -EINVAL;
9480 }
9481
e72868c4
SS		 9482 /* Core DRM takes care of checking FB modifiers, so we only need to
9483 * check tiling flags when the FB doesn't have a modifier. */
9484 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9485 if (adev->family < AMDGPU_FAMILY_AI) {
9486 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9487 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9488 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9489 } else {
9490 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9491 }
9492 if (!linear) {
9493 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9494 return -EINVAL;
9495 }
9496 }
9497
b0455fda
SS		 9498 return 0;
9499}
9500
9e869063
LL		 9501static int dm_update_plane_state(struct dc *dc,
9502 struct drm_atomic_state *state,
9503 struct drm_plane *plane,
9504 struct drm_plane_state *old_plane_state,
9505 struct drm_plane_state *new_plane_state,
9506 bool enable,
9507 bool *lock_and_validation_needed)
62f55537 9508{
eb3dc897
NK		 9509
9510 struct dm_atomic_state *dm_state = NULL;
62f55537 9511 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 9512 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 9513 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 9514 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
626bf90f 9515 struct amdgpu_crtc *new_acrtc;
f6ff2a08 9516 bool needs_reset;
62f55537 9517 int ret = 0;
e7b07cee 9518
9b690ef3 9519
9e869063
LL		 9520 new_plane_crtc = new_plane_state->crtc;
9521 old_plane_crtc = old_plane_state->crtc;
9522 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9523 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 9524
626bf90f
SS		 9525 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9526 if (!enable || !new_plane_crtc ||
9527 drm_atomic_plane_disabling(plane->state, new_plane_state))
9528 return 0;
9529
9530 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9531
5f581248
SS		 9532 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9533 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9534 return -EINVAL;
9535 }
9536
24f99d2b 9537 if (new_plane_state->fb) {
b0455fda
SS		 9538 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9539 new_plane_state->fb);
9540 if (ret)
9541 return ret;
24f99d2b
SS		 9542 }
9543
9e869063 9544 return 0;
626bf90f 9545 }
9b690ef3 9546
f6ff2a08
NK		 9547 needs_reset = should_reset_plane(state, plane, old_plane_state,
9548 new_plane_state);
9549
9e869063
LL		 9550 /* Remove any changed/removed planes */
9551 if (!enable) {
f6ff2a08 9552 if (!needs_reset)
9e869063 9553 return 0;
a7b06724 9554
9e869063
LL		 9555 if (!old_plane_crtc)
9556 return 0;
62f55537 9557
9e869063
LL		 9558 old_crtc_state = drm_atomic_get_old_crtc_state(
9559 state, old_plane_crtc);
9560 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 9561
9e869063
LL		 9562 if (!dm_old_crtc_state->stream)
9563 return 0;
62f55537 9564
9e869063
LL		 9565 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9566 plane->base.id, old_plane_crtc->base.id);
9b690ef3 9567
9e869063
LL		 9568 ret = dm_atomic_get_state(state, &dm_state);
9569 if (ret)
9570 return ret;
eb3dc897 9571
9e869063
LL		 9572 if (!dc_remove_plane_from_context(
9573 dc,
9574 dm_old_crtc_state->stream,
9575 dm_old_plane_state->dc_state,
9576 dm_state->context)) {
62f55537 9577
c3537613 9578 return -EINVAL;
9e869063 9579 }
e7b07cee 9580
9b690ef3 9581
9e869063
LL		 9582 dc_plane_state_release(dm_old_plane_state->dc_state);
9583 dm_new_plane_state->dc_state = NULL;
1dc90497 9584
9e869063 9585 *lock_and_validation_needed = true;
1dc90497 9586
9e869063
LL		 9587 } else { /* Add new planes */
9588 struct dc_plane_state *dc_new_plane_state;
1dc90497 9589
9e869063
LL		 9590 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9591 return 0;
e7b07cee 9592
9e869063
LL		 9593 if (!new_plane_crtc)
9594 return 0;
e7b07cee 9595
9e869063
LL		 9596 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9597 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 9598
9e869063
LL		 9599 if (!dm_new_crtc_state->stream)
9600 return 0;
62f55537 9601
f6ff2a08 9602 if (!needs_reset)
9e869063 9603 return 0;
62f55537 9604
8c44515b
AP		 9605 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9606 if (ret)
9607 return ret;
9608
9e869063 9609 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 9610
9e869063
LL		 9611 dc_new_plane_state = dc_create_plane_state(dc);
9612 if (!dc_new_plane_state)
9613 return -ENOMEM;
62f55537 9614
9e869063
LL		 9615 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
9616 plane->base.id, new_plane_crtc->base.id);
8c45c5db 9617
695af5f9 9618 ret = fill_dc_plane_attributes(
1348969a 9619 drm_to_adev(new_plane_crtc->dev),
9e869063
LL		 9620 dc_new_plane_state,
9621 new_plane_state,
9622 new_crtc_state);
9623 if (ret) {
9624 dc_plane_state_release(dc_new_plane_state);
9625 return ret;
9626 }
62f55537 9627
9e869063
LL		 9628 ret = dm_atomic_get_state(state, &dm_state);
9629 if (ret) {
9630 dc_plane_state_release(dc_new_plane_state);
9631 return ret;
9632 }
eb3dc897 9633
9e869063
LL		 9634 /*
9635 * Any atomic check errors that occur after this will
9636 * not need a release. The plane state will be attached
9637 * to the stream, and therefore part of the atomic
9638 * state. It'll be released when the atomic state is
9639 * cleaned.
9640 */
9641 if (!dc_add_plane_to_context(
9642 dc,
9643 dm_new_crtc_state->stream,
9644 dc_new_plane_state,
9645 dm_state->context)) {
62f55537 9646
9e869063
LL		 9647 dc_plane_state_release(dc_new_plane_state);
9648 return -EINVAL;
9649 }
8c45c5db 9650
9e869063 9651 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 9652
9e869063
LL		 9653 /* Tell DC to do a full surface update every time there
9654 * is a plane change. Inefficient, but works for now.
9655 */
9656 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9657
9658 *lock_and_validation_needed = true;
62f55537 9659 }
e7b07cee
HW		 9660
9661
62f55537
AG		 9662 return ret;
9663}
a87fa993 9664
12f4849a
SS		 9665static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9666 struct drm_crtc *crtc,
9667 struct drm_crtc_state *new_crtc_state)
9668{
9669 struct drm_plane_state *new_cursor_state, *new_primary_state;
9670 int cursor_scale_w, cursor_scale_h, primary_scale_w, primary_scale_h;
9671
9672 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9673 * cursor per pipe but it's going to inherit the scaling and
9674 * positioning from the underlying pipe. Check the cursor plane's
9675 * blending properties match the primary plane's. */
9676
9677 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor);
9678 new_primary_state = drm_atomic_get_new_plane_state(state, crtc->primary);
9679 if (!new_cursor_state || !new_primary_state || !new_cursor_state->fb) {
9680 return 0;
9681 }
9682
9683 cursor_scale_w = new_cursor_state->crtc_w * 1000 /
9684 (new_cursor_state->src_w >> 16);
9685 cursor_scale_h = new_cursor_state->crtc_h * 1000 /
9686 (new_cursor_state->src_h >> 16);
9687
9688 primary_scale_w = new_primary_state->crtc_w * 1000 /
9689 (new_primary_state->src_w >> 16);
9690 primary_scale_h = new_primary_state->crtc_h * 1000 /
9691 (new_primary_state->src_h >> 16);
9692
9693 if (cursor_scale_w != primary_scale_w ||
9694 cursor_scale_h != primary_scale_h) {
9695 DRM_DEBUG_ATOMIC("Cursor plane scaling doesn't match primary plane\n");
9696 return -EINVAL;
9697 }
9698
9699 return 0;
9700}
9701
e10517b3 9702#if defined(CONFIG_DRM_AMD_DC_DCN)
44be939f
ML		 9703static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9704{
9705 struct drm_connector *connector;
9706 struct drm_connector_state *conn_state;
9707 struct amdgpu_dm_connector *aconnector = NULL;
9708 int i;
9709 for_each_new_connector_in_state(state, connector, conn_state, i) {
9710 if (conn_state->crtc != crtc)
9711 continue;
9712
9713 aconnector = to_amdgpu_dm_connector(connector);
9714 if (!aconnector->port || !aconnector->mst_port)
9715 aconnector = NULL;
9716 else
9717 break;
9718 }
9719
9720 if (!aconnector)
9721 return 0;
9722
9723 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9724}
e10517b3 9725#endif
44be939f 9726
b8592b48
LL		 9727/**
9728 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9729 * @dev: The DRM device
9730 * @state: The atomic state to commit
9731 *
9732 * Validate that the given atomic state is programmable by DC into hardware.
9733 * This involves constructing a &struct dc_state reflecting the new hardware
9734 * state we wish to commit, then querying DC to see if it is programmable. It's
9735 * important not to modify the existing DC state. Otherwise, atomic_check
9736 * may unexpectedly commit hardware changes.
9737 *
9738 * When validating the DC state, it's important that the right locks are
9739 * acquired. For full updates case which removes/adds/updates streams on one
9740 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9741 * that any such full update commit will wait for completion of any outstanding
f6d7c7fa 9742 * flip using DRMs synchronization events.
b8592b48
LL		 9743 *
9744 * Note that DM adds the affected connectors for all CRTCs in state, when that
9745 * might not seem necessary. This is because DC stream creation requires the
9746 * DC sink, which is tied to the DRM connector state. Cleaning this up should
9747 * be possible but non-trivial - a possible TODO item.
9748 *
9749 * Return: -Error code if validation failed.
9750 */
7578ecda
AD		 9751static int amdgpu_dm_atomic_check(struct drm_device *dev,
9752 struct drm_atomic_state *state)
62f55537 9753{
1348969a 9754 struct amdgpu_device *adev = drm_to_adev(dev);
eb3dc897 9755 struct dm_atomic_state *dm_state = NULL;
62f55537 9756 struct dc *dc = adev->dm.dc;
62f55537 9757 struct drm_connector *connector;
c2cea706 9758 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 9759 struct drm_crtc *crtc;
fc9e9920 9760 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 9761 struct drm_plane *plane;
9762 struct drm_plane_state *old_plane_state, *new_plane_state;
74a16675 9763 enum dc_status status;
1e88ad0a 9764 int ret, i;
62f55537 9765 bool lock_and_validation_needed = false;
886876ec 9766 struct dm_crtc_state *dm_old_crtc_state;
62f55537 9767
e8a98235 9768 trace_amdgpu_dm_atomic_check_begin(state);
c44a22b3 9769
62f55537 9770 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 9771 if (ret)
9772 goto fail;
62f55537 9773
c5892a10
SW		 9774 /* Check connector changes */
9775 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9776 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9777 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9778
9779 /* Skip connectors that are disabled or part of modeset already. */
9780 if (!old_con_state->crtc && !new_con_state->crtc)
9781 continue;
9782
9783 if (!new_con_state->crtc)
9784 continue;
9785
9786 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9787 if (IS_ERR(new_crtc_state)) {
9788 ret = PTR_ERR(new_crtc_state);
9789 goto fail;
9790 }
9791
9792 if (dm_old_con_state->abm_level !=
9793 dm_new_con_state->abm_level)
9794 new_crtc_state->connectors_changed = true;
9795 }
9796
e10517b3 9797#if defined(CONFIG_DRM_AMD_DC_DCN)
349a19b2 9798 if (dc_resource_is_dsc_encoding_supported(dc)) {
44be939f
ML		 9799 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9800 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9801 ret = add_affected_mst_dsc_crtcs(state, crtc);
9802 if (ret)
9803 goto fail;
9804 }
9805 }
9806 }
e10517b3 9807#endif
1e88ad0a 9808 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
886876ec
EB		 9809 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9810
1e88ad0a 9811 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 9812 !new_crtc_state->color_mgmt_changed &&
886876ec
EB		 9813 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9814 dm_old_crtc_state->dsc_force_changed == false)
1e88ad0a 9815 continue;
7bef1af3 9816
1e88ad0a
S		 9817 if (!new_crtc_state->enable)
9818 continue;
fc9e9920 9819
1e88ad0a
S		 9820 ret = drm_atomic_add_affected_connectors(state, crtc);
9821 if (ret)
9822 return ret;
fc9e9920 9823
1e88ad0a
S		 9824 ret = drm_atomic_add_affected_planes(state, crtc);
9825 if (ret)
9826 goto fail;
115a385c 9827
cbac53f7 9828 if (dm_old_crtc_state->dsc_force_changed)
115a385c 9829 new_crtc_state->mode_changed = true;
e7b07cee
HW		 9830 }
9831
2d9e6431
NK		 9832 /*
9833 * Add all primary and overlay planes on the CRTC to the state
9834 * whenever a plane is enabled to maintain correct z-ordering
9835 * and to enable fast surface updates.
9836 */
9837 drm_for_each_crtc(crtc, dev) {
9838 bool modified = false;
9839
9840 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9841 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9842 continue;
9843
9844 if (new_plane_state->crtc == crtc ||
9845 old_plane_state->crtc == crtc) {
9846 modified = true;
9847 break;
9848 }
9849 }
9850
9851 if (!modified)
9852 continue;
9853
9854 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9855 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9856 continue;
9857
9858 new_plane_state =
9859 drm_atomic_get_plane_state(state, plane);
9860
9861 if (IS_ERR(new_plane_state)) {
9862 ret = PTR_ERR(new_plane_state);
9863 goto fail;
9864 }
9865 }
9866 }
9867
62f55537 9868 /* Remove exiting planes if they are modified */
9e869063
LL		 9869 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9870 ret = dm_update_plane_state(dc, state, plane,
9871 old_plane_state,
9872 new_plane_state,
9873 false,
9874 &lock_and_validation_needed);
9875 if (ret)
9876 goto fail;
62f55537
AG		 9877 }
9878
9879 /* Disable all crtcs which require disable */
4b9674e5
LL		 9880 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9881 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9882 old_crtc_state,
9883 new_crtc_state,
9884 false,
9885 &lock_and_validation_needed);
9886 if (ret)
9887 goto fail;
62f55537
AG		 9888 }
9889
9890 /* Enable all crtcs which require enable */
4b9674e5
LL		 9891 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9892 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9893 old_crtc_state,
9894 new_crtc_state,
9895 true,
9896 &lock_and_validation_needed);
9897 if (ret)
9898 goto fail;
62f55537
AG		 9899 }
9900
9901 /* Add new/modified planes */
9e869063
LL		 9902 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9903 ret = dm_update_plane_state(dc, state, plane,
9904 old_plane_state,
9905 new_plane_state,
9906 true,
9907 &lock_and_validation_needed);
9908 if (ret)
9909 goto fail;
62f55537
AG		 9910 }
9911
b349f76e
ES		 9912 /* Run this here since we want to validate the streams we created */
9913 ret = drm_atomic_helper_check_planes(dev, state);
9914 if (ret)
9915 goto fail;
62f55537 9916
12f4849a
SS		 9917 /* Check cursor planes scaling */
9918 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9919 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
9920 if (ret)
9921 goto fail;
9922 }
9923
43d10d30
NK		 9924 if (state->legacy_cursor_update) {
9925 /*
9926 * This is a fast cursor update coming from the plane update
9927 * helper, check if it can be done asynchronously for better
9928 * performance.
9929 */
9930 state->async_update =
9931 !drm_atomic_helper_async_check(dev, state);
9932
9933 /*
9934 * Skip the remaining global validation if this is an async
9935 * update. Cursor updates can be done without affecting
9936 * state or bandwidth calcs and this avoids the performance
9937 * penalty of locking the private state object and
9938 * allocating a new dc_state.
9939 */
9940 if (state->async_update)
9941 return 0;
9942 }
9943
ebdd27e1 9944 /* Check scaling and underscan changes*/
1f6010a9 9945 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 9946 * new stream into context w\o causing full reset. Need to
9947 * decide how to handle.
9948 */
c2cea706 9949 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 9950 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9951 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9952 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 9953
9954 /* Skip any modesets/resets */
0bc9706d
LSL		 9955 if (!acrtc || drm_atomic_crtc_needs_modeset(
9956 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 9957 continue;
9958
b830ebc9 9959 /* Skip any thing not scale or underscan changes */
54d76575 9960 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 9961 continue;
9962
9963 lock_and_validation_needed = true;
9964 }
9965
f6d7c7fa
NK		 9966 /**
9967 * Streams and planes are reset when there are changes that affect
9968 * bandwidth. Anything that affects bandwidth needs to go through
9969 * DC global validation to ensure that the configuration can be applied
9970 * to hardware.
9971 *
9972 * We have to currently stall out here in atomic_check for outstanding
9973 * commits to finish in this case because our IRQ handlers reference
9974 * DRM state directly - we can end up disabling interrupts too early
9975 * if we don't.
9976 *
9977 * TODO: Remove this stall and drop DM state private objects.
a87fa993 9978 */
f6d7c7fa 9979 if (lock_and_validation_needed) {
eb3dc897
NK		 9980 ret = dm_atomic_get_state(state, &dm_state);
9981 if (ret)
9982 goto fail;
e7b07cee
HW		 9983
9984 ret = do_aquire_global_lock(dev, state);
9985 if (ret)
9986 goto fail;
1dc90497 9987
d9fe1a4c 9988#if defined(CONFIG_DRM_AMD_DC_DCN)
8c20a1ed
DF		 9989 if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
9990 goto fail;
9991
29b9ba74
ML		 9992 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);
9993 if (ret)
9994 goto fail;
d9fe1a4c 9995#endif
29b9ba74 9996
ded58c7b
ZL		 9997 /*
9998 * Perform validation of MST topology in the state:
9999 * We need to perform MST atomic check before calling
10000 * dc_validate_global_state(), or there is a chance
10001 * to get stuck in an infinite loop and hang eventually.
10002 */
10003 ret = drm_dp_mst_atomic_check(state);
10004 if (ret)
10005 goto fail;
74a16675
RS		 10006 status = dc_validate_global_state(dc, dm_state->context, false);
10007 if (status != DC_OK) {
10008 DC_LOG_WARNING("DC global validation failure: %s (%d)",
10009 dc_status_to_str(status), status);
e7b07cee
HW		 10010 ret = -EINVAL;
10011 goto fail;
10012 }
bd200d19 10013 } else {
674e78ac 10014 /*
bd200d19
NK		 10015 * The commit is a fast update. Fast updates shouldn't change
10016 * the DC context, affect global validation, and can have their
10017 * commit work done in parallel with other commits not touching
10018 * the same resource. If we have a new DC context as part of
10019 * the DM atomic state from validation we need to free it and
10020 * retain the existing one instead.
fde9f39a
MR		 10021 *
10022 * Furthermore, since the DM atomic state only contains the DC
10023 * context and can safely be annulled, we can free the state
10024 * and clear the associated private object now to free
10025 * some memory and avoid a possible use-after-free later.
674e78ac 10026 */
bd200d19 10027
fde9f39a
MR		 10028 for (i = 0; i < state->num_private_objs; i++) {
10029 struct drm_private_obj *obj = state->private_objs[i].ptr;
bd200d19 10030
fde9f39a
MR		 10031 if (obj->funcs == adev->dm.atomic_obj.funcs) {
10032 int j = state->num_private_objs-1;
bd200d19 10033
fde9f39a
MR		 10034 dm_atomic_destroy_state(obj,
10035 state->private_objs[i].state);
10036
10037 /* If i is not at the end of the array then the
10038 * last element needs to be moved to where i was
10039 * before the array can safely be truncated.
10040 */
10041 if (i != j)
10042 state->private_objs[i] =
10043 state->private_objs[j];
bd200d19 10044
fde9f39a
MR		 10045 state->private_objs[j].ptr = NULL;
10046 state->private_objs[j].state = NULL;
10047 state->private_objs[j].old_state = NULL;
10048 state->private_objs[j].new_state = NULL;
10049
10050 state->num_private_objs = j;
10051 break;
10052 }
bd200d19 10053 }
e7b07cee
HW		 10054 }
10055
caff0e66
NK		 10056 /* Store the overall update type for use later in atomic check. */
10057 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10058 struct dm_crtc_state *dm_new_crtc_state =
10059 to_dm_crtc_state(new_crtc_state);
10060
f6d7c7fa
NK		 10061 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10062 UPDATE_TYPE_FULL :
10063 UPDATE_TYPE_FAST;
e7b07cee
HW		 10064 }
10065
10066 /* Must be success */
10067 WARN_ON(ret);
e8a98235
RS		 10068
10069 trace_amdgpu_dm_atomic_check_finish(state, ret);
10070
e7b07cee
HW		 10071 return ret;
10072
10073fail:
10074 if (ret == -EDEADLK)
01e28f9c 10075 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 10076 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 10077 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 10078 else
01e28f9c 10079 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee 10080
e8a98235
RS		 10081 trace_amdgpu_dm_atomic_check_finish(state, ret);
10082
e7b07cee
HW		 10083 return ret;
10084}
10085
3ee6b26b
AD		 10086static bool is_dp_capable_without_timing_msa(struct dc *dc,
10087 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 10088{
10089 uint8_t dpcd_data;
10090 bool capable = false;
10091
c84dec2f 10092 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 10093 dm_helpers_dp_read_dpcd(
10094 NULL,
c84dec2f 10095 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 10096 DP_DOWN_STREAM_PORT_COUNT,
10097 &dpcd_data,
10098 sizeof(dpcd_data))) {
10099 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10100 }
10101
10102 return capable;
10103}
f9b4f20c
SW		 10104
10105static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10106 uint8_t *edid_ext, int len,
10107 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10108{
10109 int i;
10110 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10111 struct dc *dc = adev->dm.dc;
10112
10113 /* send extension block to DMCU for parsing */
10114 for (i = 0; i < len; i += 8) {
10115 bool res;
10116 int offset;
10117
10118 /* send 8 bytes a time */
10119 if (!dc_edid_parser_send_cea(dc, i, len, &edid_ext[i], 8))
10120 return false;
10121
10122 if (i+8 == len) {
10123 /* EDID block sent completed, expect result */
10124 int version, min_rate, max_rate;
10125
10126 res = dc_edid_parser_recv_amd_vsdb(dc, &version, &min_rate, &max_rate);
10127 if (res) {
10128 /* amd vsdb found */
10129 vsdb_info->freesync_supported = 1;
10130 vsdb_info->amd_vsdb_version = version;
10131 vsdb_info->min_refresh_rate_hz = min_rate;
10132 vsdb_info->max_refresh_rate_hz = max_rate;
10133 return true;
10134 }
10135 /* not amd vsdb */
10136 return false;
10137 }
10138
10139 /* check for ack*/
10140 res = dc_edid_parser_recv_cea_ack(dc, &offset);
10141 if (!res)
10142 return false;
10143 }
10144
10145 return false;
10146}
10147
7c7dd774 10148static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
f9b4f20c
SW		 10149 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10150{
10151 uint8_t *edid_ext = NULL;
10152 int i;
10153 bool valid_vsdb_found = false;
10154
10155 /*----- drm_find_cea_extension() -----*/
10156 /* No EDID or EDID extensions */
10157 if (edid == NULL || edid->extensions == 0)
7c7dd774 10158 return -ENODEV;
f9b4f20c
SW		 10159
10160 /* Find CEA extension */
10161 for (i = 0; i < edid->extensions; i++) {
10162 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10163 if (edid_ext[0] == CEA_EXT)
10164 break;
10165 }
10166
10167 if (i == edid->extensions)
7c7dd774 10168 return -ENODEV;
f9b4f20c
SW		 10169
10170 /*----- cea_db_offsets() -----*/
10171 if (edid_ext[0] != CEA_EXT)
7c7dd774 10172 return -ENODEV;
f9b4f20c
SW		 10173
10174 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
7c7dd774
AB		 10175
10176 return valid_vsdb_found ? i : -ENODEV;
f9b4f20c
SW		 10177}
10178
98e6436d
AK		 10179void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10180 struct edid *edid)
e7b07cee 10181{
eb0709ba 10182 int i = 0;
e7b07cee
HW		 10183 struct detailed_timing *timing;
10184 struct detailed_non_pixel *data;
10185 struct detailed_data_monitor_range *range;
c84dec2f
HW		 10186 struct amdgpu_dm_connector *amdgpu_dm_connector =
10187 to_amdgpu_dm_connector(connector);
bb47de73 10188 struct dm_connector_state *dm_con_state = NULL;
e7b07cee
HW		 10189
10190 struct drm_device *dev = connector->dev;
1348969a 10191 struct amdgpu_device *adev = drm_to_adev(dev);
bb47de73 10192 bool freesync_capable = false;
f9b4f20c 10193 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
b830ebc9 10194
8218d7f1
HW		 10195 if (!connector->state) {
10196 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 10197 goto update;
8218d7f1
HW		 10198 }
10199
98e6436d
AK		 10200 if (!edid) {
10201 dm_con_state = to_dm_connector_state(connector->state);
10202
10203 amdgpu_dm_connector->min_vfreq = 0;
10204 amdgpu_dm_connector->max_vfreq = 0;
10205 amdgpu_dm_connector->pixel_clock_mhz = 0;
10206
bb47de73 10207 goto update;
98e6436d
AK		 10208 }
10209
8218d7f1
HW		 10210 dm_con_state = to_dm_connector_state(connector->state);
10211
c84dec2f 10212 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee 10213 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
bb47de73 10214 goto update;
e7b07cee
HW		 10215 }
10216 if (!adev->dm.freesync_module)
bb47de73 10217 goto update;
f9b4f20c
SW		 10218
10219
10220 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10221 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
10222 bool edid_check_required = false;
10223
10224 if (edid) {
e7b07cee
HW		 10225 edid_check_required = is_dp_capable_without_timing_msa(
10226 adev->dm.dc,
c84dec2f 10227 amdgpu_dm_connector);
e7b07cee 10228 }
e7b07cee 10229
f9b4f20c
SW		 10230 if (edid_check_required == true && (edid->version > 1 ||
10231 (edid->version == 1 && edid->revision > 1))) {
10232 for (i = 0; i < 4; i++) {
10233
10234 timing = &edid->detailed_timings[i];
10235 data = &timing->data.other_data;
10236 range = &data->data.range;
10237 /*
10238 * Check if monitor has continuous frequency mode
10239 */
10240 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10241 continue;
10242 /*
10243 * Check for flag range limits only. If flag == 1 then
10244 * no additional timing information provided.
10245 * Default GTF, GTF Secondary curve and CVT are not
10246 * supported
10247 */
10248 if (range->flags != 1)
10249 continue;
e7b07cee 10250
f9b4f20c
SW		 10251 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10252 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10253 amdgpu_dm_connector->pixel_clock_mhz =
10254 range->pixel_clock_mhz * 10;
a0ffc3fd 10255
f9b4f20c
SW		 10256 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10257 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
a0ffc3fd 10258
f9b4f20c
SW		 10259 break;
10260 }
e7b07cee 10261
f9b4f20c
SW		 10262 if (amdgpu_dm_connector->max_vfreq -
10263 amdgpu_dm_connector->min_vfreq > 10) {
98e6436d 10264
f9b4f20c
SW		 10265 freesync_capable = true;
10266 }
10267 }
10268 } else if (edid && amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
7c7dd774
AB		 10269 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10270 if (i >= 0 && vsdb_info.freesync_supported) {
f9b4f20c
SW		 10271 timing = &edid->detailed_timings[i];
10272 data = &timing->data.other_data;
10273
10274 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10275 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10276 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10277 freesync_capable = true;
10278
10279 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10280 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
e7b07cee
HW		 10281 }
10282 }
bb47de73
NK		 10283
10284update:
10285 if (dm_con_state)
10286 dm_con_state->freesync_capable = freesync_capable;
10287
10288 if (connector->vrr_capable_property)
10289 drm_connector_set_vrr_capable_property(connector,
10290 freesync_capable);
e7b07cee
HW		 10291}
10292
8c322309
RL		 10293static void amdgpu_dm_set_psr_caps(struct dc_link *link)
10294{
10295 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
10296
10297 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
10298 return;
10299 if (link->type == dc_connection_none)
10300 return;
10301 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
10302 dpcd_data, sizeof(dpcd_data))) {
d1ebfdd8
WW		 10303 link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];
10304
10305 if (dpcd_data[0] == 0) {
1cfbbdde 10306 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
d1ebfdd8
WW		 10307 link->psr_settings.psr_feature_enabled = false;
10308 } else {
1cfbbdde 10309 link->psr_settings.psr_version = DC_PSR_VERSION_1;
d1ebfdd8
WW		 10310 link->psr_settings.psr_feature_enabled = true;
10311 }
10312
10313 DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
8c322309
RL		 10314 }
10315}
10316
10317/*
10318 * amdgpu_dm_link_setup_psr() - configure psr link
10319 * @stream: stream state
10320 *
10321 * Return: true if success
10322 */
10323static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
10324{
10325 struct dc_link *link = NULL;
10326 struct psr_config psr_config = {0};
10327 struct psr_context psr_context = {0};
8c322309
RL		 10328 bool ret = false;
10329
10330 if (stream == NULL)
10331 return false;
10332
10333 link = stream->link;
8c322309 10334
d1ebfdd8 10335 psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
8c322309
RL		 10336
10337 if (psr_config.psr_version > 0) {
10338 psr_config.psr_exit_link_training_required = 0x1;
10339 psr_config.psr_frame_capture_indication_req = 0;
10340 psr_config.psr_rfb_setup_time = 0x37;
10341 psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
10342 psr_config.allow_smu_optimizations = 0x0;
10343
10344 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
10345
10346 }
d1ebfdd8 10347 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled);
8c322309
RL		 10348
10349 return ret;
10350}
10351
10352/*
10353 * amdgpu_dm_psr_enable() - enable psr f/w
10354 * @stream: stream state
10355 *
10356 * Return: true if success
10357 */
10358bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
10359{
10360 struct dc_link *link = stream->link;
5b5abe95
AK		 10361 unsigned int vsync_rate_hz = 0;
10362 struct dc_static_screen_params params = {0};
10363 /* Calculate number of static frames before generating interrupt to
10364 * enter PSR.
10365 */
5b5abe95
AK		 10366 // Init fail safe of 2 frames static
10367 unsigned int num_frames_static = 2;
8c322309
RL		 10368
10369 DRM_DEBUG_DRIVER("Enabling psr...\n");
10370
5b5abe95
AK		 10371 vsync_rate_hz = div64_u64(div64_u64((
10372 stream->timing.pix_clk_100hz * 100),
10373 stream->timing.v_total),
10374 stream->timing.h_total);
10375
10376 /* Round up
10377 * Calculate number of frames such that at least 30 ms of time has
10378 * passed.
10379 */
7aa62404
RL		 10380 if (vsync_rate_hz != 0) {
10381 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
5b5abe95 10382 num_frames_static = (30000 / frame_time_microsec) + 1;
7aa62404 10383 }
5b5abe95
AK		 10384
10385 params.triggers.cursor_update = true;
10386 params.triggers.overlay_update = true;
10387 params.triggers.surface_update = true;
10388 params.num_frames = num_frames_static;
8c322309 10389
5b5abe95 10390 dc_stream_set_static_screen_params(link->ctx->dc,
8c322309 10391 &stream, 1,
5b5abe95 10392 &params);
8c322309 10393
1d496907 10394 return dc_link_set_psr_allow_active(link, true, false, false);
8c322309
RL		 10395}
10396
10397/*
10398 * amdgpu_dm_psr_disable() - disable psr f/w
10399 * @stream: stream state
10400 *
10401 * Return: true if success
10402 */
10403static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
10404{
10405
10406 DRM_DEBUG_DRIVER("Disabling psr...\n");
10407
1d496907 10408 return dc_link_set_psr_allow_active(stream->link, false, true, false);
8c322309 10409}
3d4e52d0 10410
6ee90e88 10411/*
10412 * amdgpu_dm_psr_disable() - disable psr f/w
10413 * if psr is enabled on any stream
10414 *
10415 * Return: true if success
10416 */
10417static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
10418{
10419 DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
10420 return dc_set_psr_allow_active(dm->dc, false);
10421}
10422
3d4e52d0
VL		 10423void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10424{
1348969a 10425 struct amdgpu_device *adev = drm_to_adev(dev);
3d4e52d0
VL		 10426 struct dc *dc = adev->dm.dc;
10427 int i;
10428
10429 mutex_lock(&adev->dm.dc_lock);
10430 if (dc->current_state) {
10431 for (i = 0; i < dc->current_state->stream_count; ++i)
10432 dc->current_state->streams[i]
10433 ->triggered_crtc_reset.enabled =
10434 adev->dm.force_timing_sync;
10435
10436 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10437 dc_trigger_sync(dc, dc->current_state);
10438 }
10439 mutex_unlock(&adev->dm.dc_lock);
10440}
9d83722d
RS		 10441
10442void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10443 uint32_t value, const char *func_name)
10444{
10445#ifdef DM_CHECK_ADDR_0
10446 if (address == 0) {
10447 DC_ERR("invalid register write. address = 0");
10448 return;
10449 }
10450#endif
10451 cgs_write_register(ctx->cgs_device, address, value);
10452 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10453}
10454
10455uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10456 const char *func_name)
10457{
10458 uint32_t value;
10459#ifdef DM_CHECK_ADDR_0
10460 if (address == 0) {
10461 DC_ERR("invalid register read; address = 0\n");
10462 return 0;
10463 }
10464#endif
10465
10466 if (ctx->dmub_srv &&
10467 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10468 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10469 ASSERT(false);
10470 return 0;
10471 }
10472
10473 value = cgs_read_register(ctx->cgs_device, address);
10474
10475 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10476
10477 return value;
10478}
Linux 6.x block layer and io_uring tree(s)