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drm/amd/display: Update plane scaling parameters for fast updates
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
1dc90497 31#include "dc/inc/core_types.h"
4562236b
HW		 32
33#include "vid.h"
34#include "amdgpu.h"
a49dcb88 35#include "amdgpu_display.h"
a94d5569 36#include "amdgpu_ucode.h"
4562236b
HW		 37#include "atom.h"
38#include "amdgpu_dm.h"
e7b07cee 39#include "amdgpu_pm.h"
4562236b
HW		 40
41#include "amd_shared.h"
42#include "amdgpu_dm_irq.h"
43#include "dm_helpers.h"
e7b07cee 44#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 45#if defined(CONFIG_DEBUG_FS)
46#include "amdgpu_dm_debugfs.h"
47#endif
4562236b
HW		 48
49#include "ivsrcid/ivsrcid_vislands30.h"
50
51#include <linux/module.h>
52#include <linux/moduleparam.h>
53#include <linux/version.h>
e7b07cee 54#include <linux/types.h>
97028037 55#include <linux/pm_runtime.h>
a94d5569 56#include <linux/firmware.h>
4562236b 57
e7b07cee 58#include <drm/drmP.h>
4562236b 59#include <drm/drm_atomic.h>
674e78ac 60#include <drm/drm_atomic_uapi.h>
4562236b
HW		 61#include <drm/drm_atomic_helper.h>
62#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 63#include <drm/drm_fb_helper.h>
64#include <drm/drm_edid.h>
4562236b 65
ff5ef992
AD		 66#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
67#include "ivsrcid/irqsrcs_dcn_1_0.h"
68
ad941f7a
FX		 69#include "dcn/dcn_1_0_offset.h"
70#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 71#include "soc15_hw_ip.h"
72#include "vega10_ip_offset.h"
ff5ef992
AD		 73
74#include "soc15_common.h"
75#endif
76
e7b07cee 77#include "modules/inc/mod_freesync.h"
bbf854dc 78#include "modules/power/power_helpers.h"
ecd0136b 79#include "modules/inc/mod_info_packet.h"
e7b07cee 80
a94d5569
DF		 81#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
82MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 83
b8592b48
LL		 84/**
85 * DOC: overview
86 *
87 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
88 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
89 * requests into DC requests, and DC responses into DRM responses.
90 *
91 * The root control structure is &struct amdgpu_display_manager.
92 */
93
7578ecda
AD		 94/* basic init/fini API */
95static int amdgpu_dm_init(struct amdgpu_device *adev);
96static void amdgpu_dm_fini(struct amdgpu_device *adev);
97
1f6010a9
DF		 98/*
99 * initializes drm_device display related structures, based on the information
7578ecda
AD		 100 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
101 * drm_encoder, drm_mode_config
102 *
103 * Returns 0 on success
104 */
105static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
106/* removes and deallocates the drm structures, created by the above function */
107static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
108
109static void
110amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
111
112static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 113 struct drm_plane *plane,
cc1fec57
NK		 114 unsigned long possible_crtcs,
115 const struct dc_plane_cap *plane_cap);
7578ecda
AD		 116static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
117 struct drm_plane *plane,
118 uint32_t link_index);
119static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
120 struct amdgpu_dm_connector *amdgpu_dm_connector,
121 uint32_t link_index,
122 struct amdgpu_encoder *amdgpu_encoder);
123static int amdgpu_dm_encoder_init(struct drm_device *dev,
124 struct amdgpu_encoder *aencoder,
125 uint32_t link_index);
126
127static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
128
129static int amdgpu_dm_atomic_commit(struct drm_device *dev,
130 struct drm_atomic_state *state,
131 bool nonblock);
132
133static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
134
135static int amdgpu_dm_atomic_check(struct drm_device *dev,
136 struct drm_atomic_state *state);
137
674e78ac
NK		 138static void handle_cursor_update(struct drm_plane *plane,
139 struct drm_plane_state *old_plane_state);
7578ecda 140
4562236b
HW		 141/*
142 * dm_vblank_get_counter
143 *
144 * @brief
145 * Get counter for number of vertical blanks
146 *
147 * @param
148 * struct amdgpu_device *adev - [in] desired amdgpu device
149 * int disp_idx - [in] which CRTC to get the counter from
150 *
151 * @return
152 * Counter for vertical blanks
153 */
154static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
155{
156 if (crtc >= adev->mode_info.num_crtc)
157 return 0;
158 else {
159 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 160 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
161 acrtc->base.state);
4562236b 162
da5c47f6
AG		 163
164 if (acrtc_state->stream == NULL) {
0971c40e
HW		 165 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
166 crtc);
4562236b
HW		 167 return 0;
168 }
169
da5c47f6 170 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 171 }
172}
173
174static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 175 u32 *vbl, u32 *position)
4562236b 176{
81c50963
ST		 177 uint32_t v_blank_start, v_blank_end, h_position, v_position;
178
4562236b
HW		 179 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
180 return -EINVAL;
181 else {
182 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 183 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
184 acrtc->base.state);
4562236b 185
da5c47f6 186 if (acrtc_state->stream == NULL) {
0971c40e
HW		 187 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
188 crtc);
4562236b
HW		 189 return 0;
190 }
191
81c50963
ST		 192 /*
193 * TODO rework base driver to use values directly.
194 * for now parse it back into reg-format
195 */
da5c47f6 196 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 197 &v_blank_start,
198 &v_blank_end,
199 &h_position,
200 &v_position);
201
e806208d
AG		 202 *position = v_position | (h_position << 16);
203 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 204 }
205
206 return 0;
207}
208
209static bool dm_is_idle(void *handle)
210{
211 /* XXX todo */
212 return true;
213}
214
215static int dm_wait_for_idle(void *handle)
216{
217 /* XXX todo */
218 return 0;
219}
220
221static bool dm_check_soft_reset(void *handle)
222{
223 return false;
224}
225
226static int dm_soft_reset(void *handle)
227{
228 /* XXX todo */
229 return 0;
230}
231
3ee6b26b
AD		 232static struct amdgpu_crtc *
233get_crtc_by_otg_inst(struct amdgpu_device *adev,
234 int otg_inst)
4562236b
HW		 235{
236 struct drm_device *dev = adev->ddev;
237 struct drm_crtc *crtc;
238 struct amdgpu_crtc *amdgpu_crtc;
239
4562236b
HW		 240 if (otg_inst == -1) {
241 WARN_ON(1);
242 return adev->mode_info.crtcs[0];
243 }
244
245 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
246 amdgpu_crtc = to_amdgpu_crtc(crtc);
247
248 if (amdgpu_crtc->otg_inst == otg_inst)
249 return amdgpu_crtc;
250 }
251
252 return NULL;
253}
254
66b0c973
MK		 255static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
256{
257 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
258 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
259}
260
4562236b
HW		 261static void dm_pflip_high_irq(void *interrupt_params)
262{
4562236b
HW		 263 struct amdgpu_crtc *amdgpu_crtc;
264 struct common_irq_params *irq_params = interrupt_params;
265 struct amdgpu_device *adev = irq_params->adev;
266 unsigned long flags;
71bbe51a
MK		 267 struct drm_pending_vblank_event *e;
268 struct dm_crtc_state *acrtc_state;
269 uint32_t vpos, hpos, v_blank_start, v_blank_end;
270 bool vrr_active;
4562236b
HW		 271
272 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
273
274 /* IRQ could occur when in initial stage */
1f6010a9 275 /* TODO work and BO cleanup */
4562236b
HW		 276 if (amdgpu_crtc == NULL) {
277 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
278 return;
279 }
280
281 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 282
283 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
284 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
285 amdgpu_crtc->pflip_status,
286 AMDGPU_FLIP_SUBMITTED,
287 amdgpu_crtc->crtc_id,
288 amdgpu_crtc);
289 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
290 return;
291 }
292
71bbe51a
MK		 293 /* page flip completed. */
294 e = amdgpu_crtc->event;
295 amdgpu_crtc->event = NULL;
4562236b 296
71bbe51a
MK		 297 if (!e)
298 WARN_ON(1);
1159898a 299
71bbe51a
MK		 300 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
301 vrr_active = amdgpu_dm_vrr_active(acrtc_state);
302
303 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
304 if (!vrr_active ||
305 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
306 &v_blank_end, &hpos, &vpos) ||
307 (vpos < v_blank_start)) {
308 /* Update to correct count and vblank timestamp if racing with
309 * vblank irq. This also updates to the correct vblank timestamp
310 * even in VRR mode, as scanout is past the front-porch atm.
311 */
312 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
1159898a 313
71bbe51a
MK		 314 /* Wake up userspace by sending the pageflip event with proper
315 * count and timestamp of vblank of flip completion.
316 */
317 if (e) {
318 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
319
320 /* Event sent, so done with vblank for this flip */
321 drm_crtc_vblank_put(&amdgpu_crtc->base);
322 }
323 } else if (e) {
324 /* VRR active and inside front-porch: vblank count and
325 * timestamp for pageflip event will only be up to date after
326 * drm_crtc_handle_vblank() has been executed from late vblank
327 * irq handler after start of back-porch (vline 0). We queue the
328 * pageflip event for send-out by drm_crtc_handle_vblank() with
329 * updated timestamp and count, once it runs after us.
330 *
331 * We need to open-code this instead of using the helper
332 * drm_crtc_arm_vblank_event(), as that helper would
333 * call drm_crtc_accurate_vblank_count(), which we must
334 * not call in VRR mode while we are in front-porch!
335 */
336
337 /* sequence will be replaced by real count during send-out. */
338 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
339 e->pipe = amdgpu_crtc->crtc_id;
340
341 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
342 e = NULL;
343 }
4562236b 344
fdd1fe57
MK		 345 /* Keep track of vblank of this flip for flip throttling. We use the
346 * cooked hw counter, as that one incremented at start of this vblank
347 * of pageflip completion, so last_flip_vblank is the forbidden count
348 * for queueing new pageflips if vsync + VRR is enabled.
349 */
350 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
351 amdgpu_crtc->crtc_id);
352
54f5499a 353 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 354 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
355
71bbe51a
MK		 356 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
357 amdgpu_crtc->crtc_id, amdgpu_crtc,
358 vrr_active, (int) !e);
4562236b
HW		 359}
360
d2574c33
MK		 361static void dm_vupdate_high_irq(void *interrupt_params)
362{
363 struct common_irq_params *irq_params = interrupt_params;
364 struct amdgpu_device *adev = irq_params->adev;
365 struct amdgpu_crtc *acrtc;
366 struct dm_crtc_state *acrtc_state;
367
368 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
369
370 if (acrtc) {
371 acrtc_state = to_dm_crtc_state(acrtc->base.state);
372
373 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
374 amdgpu_dm_vrr_active(acrtc_state));
375
376 /* Core vblank handling is done here after end of front-porch in
377 * vrr mode, as vblank timestamping will give valid results
378 * while now done after front-porch. This will also deliver
379 * page-flip completion events that have been queued to us
380 * if a pageflip happened inside front-porch.
381 */
382 if (amdgpu_dm_vrr_active(acrtc_state))
383 drm_crtc_handle_vblank(&acrtc->base);
384 }
385}
386
4562236b
HW		 387static void dm_crtc_high_irq(void *interrupt_params)
388{
389 struct common_irq_params *irq_params = interrupt_params;
390 struct amdgpu_device *adev = irq_params->adev;
4562236b 391 struct amdgpu_crtc *acrtc;
180db303 392 struct dm_crtc_state *acrtc_state;
4562236b 393
b57de80a 394 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 395
e5d0170e 396 if (acrtc) {
180db303
NK		 397 acrtc_state = to_dm_crtc_state(acrtc->base.state);
398
d2574c33
MK		 399 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
400 amdgpu_dm_vrr_active(acrtc_state));
401
402 /* Core vblank handling at start of front-porch is only possible
403 * in non-vrr mode, as only there vblank timestamping will give
404 * valid results while done in front-porch. Otherwise defer it
405 * to dm_vupdate_high_irq after end of front-porch.
406 */
407 if (!amdgpu_dm_vrr_active(acrtc_state))
408 drm_crtc_handle_vblank(&acrtc->base);
409
410 /* Following stuff must happen at start of vblank, for crc
411 * computation and below-the-range btr support in vrr mode.
412 */
413 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
414
180db303
NK		 415 if (acrtc_state->stream &&
416 acrtc_state->vrr_params.supported &&
417 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
418 mod_freesync_handle_v_update(
419 adev->dm.freesync_module,
420 acrtc_state->stream,
421 &acrtc_state->vrr_params);
422
423 dc_stream_adjust_vmin_vmax(
424 adev->dm.dc,
425 acrtc_state->stream,
426 &acrtc_state->vrr_params.adjust);
427 }
e5d0170e 428 }
4562236b
HW		 429}
430
431static int dm_set_clockgating_state(void *handle,
432 enum amd_clockgating_state state)
433{
434 return 0;
435}
436
437static int dm_set_powergating_state(void *handle,
438 enum amd_powergating_state state)
439{
440 return 0;
441}
442
443/* Prototypes of private functions */
444static int dm_early_init(void* handle);
445
a32e24b4 446/* Allocate memory for FBC compressed data */
3e332d3a 447static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 448{
3e332d3a
RL		 449 struct drm_device *dev = connector->dev;
450 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 451 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 452 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
453 struct drm_display_mode *mode;
42e67c3b
RL		 454 unsigned long max_size = 0;
455
456 if (adev->dm.dc->fbc_compressor == NULL)
457 return;
a32e24b4 458
3e332d3a 459 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 460 return;
461
3e332d3a
RL		 462 if (compressor->bo_ptr)
463 return;
42e67c3b 464
42e67c3b 465
3e332d3a
RL		 466 list_for_each_entry(mode, &connector->modes, head) {
467 if (max_size < mode->htotal * mode->vtotal)
468 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 469 }
470
471 if (max_size) {
472 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 473 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 474 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 475
476 if (r)
42e67c3b
RL		 477 DRM_ERROR("DM: Failed to initialize FBC\n");
478 else {
479 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
480 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
481 }
482
a32e24b4
RL		 483 }
484
485}
a32e24b4 486
7578ecda 487static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 488{
489 struct dc_init_data init_data;
490 adev->dm.ddev = adev->ddev;
491 adev->dm.adev = adev;
492
4562236b
HW		 493 /* Zero all the fields */
494 memset(&init_data, 0, sizeof(init_data));
495
674e78ac
NK		 496 mutex_init(&adev->dm.dc_lock);
497
4562236b
HW		 498 if(amdgpu_dm_irq_init(adev)) {
499 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
500 goto error;
501 }
502
503 init_data.asic_id.chip_family = adev->family;
504
505 init_data.asic_id.pci_revision_id = adev->rev_id;
506 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
507
770d13b1 508 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 509 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
510 init_data.asic_id.atombios_base_address =
511 adev->mode_info.atom_context->bios;
512
513 init_data.driver = adev;
514
515 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
516
517 if (!adev->dm.cgs_device) {
518 DRM_ERROR("amdgpu: failed to create cgs device.\n");
519 goto error;
520 }
521
522 init_data.cgs_device = adev->dm.cgs_device;
523
4562236b
HW		 524 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
525
6e227308
HW		 526 /*
527 * TODO debug why this doesn't work on Raven
528 */
529 if (adev->flags & AMD_IS_APU &&
530 adev->asic_type >= CHIP_CARRIZO &&
531 adev->asic_type < CHIP_RAVEN)
532 init_data.flags.gpu_vm_support = true;
533
04b94af4
AD		 534 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
535 init_data.flags.fbc_support = true;
536
4562236b
HW		 537 /* Display Core create. */
538 adev->dm.dc = dc_create(&init_data);
539
423788c7 540 if (adev->dm.dc) {
76121231 541 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 542 } else {
76121231 543 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 544 goto error;
545 }
4562236b 546
4562236b
HW		 547 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
548 if (!adev->dm.freesync_module) {
549 DRM_ERROR(
550 "amdgpu: failed to initialize freesync_module.\n");
551 } else
f1ad2f5e 552 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 553 adev->dm.freesync_module);
554
e277adc5
LSL		 555 amdgpu_dm_init_color_mod();
556
4562236b
HW		 557 if (amdgpu_dm_initialize_drm_device(adev)) {
558 DRM_ERROR(
559 "amdgpu: failed to initialize sw for display support.\n");
560 goto error;
561 }
562
563 /* Update the actual used number of crtc */
564 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
565
566 /* TODO: Add_display_info? */
567
568 /* TODO use dynamic cursor width */
ce75805e
AG		 569 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
570 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 571
572 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
573 DRM_ERROR(
574 "amdgpu: failed to initialize sw for display support.\n");
575 goto error;
576 }
577
e498eb71
NK		 578#if defined(CONFIG_DEBUG_FS)
579 if (dtn_debugfs_init(adev))
580 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
581#endif
582
f1ad2f5e 583 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 584
585 return 0;
586error:
587 amdgpu_dm_fini(adev);
588
59d0f396 589 return -EINVAL;
4562236b
HW		 590}
591
7578ecda 592static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 593{
594 amdgpu_dm_destroy_drm_device(&adev->dm);
595 /*
596 * TODO: pageflip, vlank interrupt
597 *
598 * amdgpu_dm_irq_fini(adev);
599 */
600
601 if (adev->dm.cgs_device) {
602 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
603 adev->dm.cgs_device = NULL;
604 }
605 if (adev->dm.freesync_module) {
606 mod_freesync_destroy(adev->dm.freesync_module);
607 adev->dm.freesync_module = NULL;
608 }
609 /* DC Destroy TODO: Replace destroy DAL */
21de3396 610 if (adev->dm.dc)
4562236b 611 dc_destroy(&adev->dm.dc);
674e78ac
NK		 612
613 mutex_destroy(&adev->dm.dc_lock);
614
4562236b
HW		 615 return;
616}
617
a94d5569 618static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 619{
a94d5569
DF		 620 const char *fw_name_dmcu;
621 int r;
622 const struct dmcu_firmware_header_v1_0 *hdr;
623
624 switch(adev->asic_type) {
625 case CHIP_BONAIRE:
626 case CHIP_HAWAII:
627 case CHIP_KAVERI:
628 case CHIP_KABINI:
629 case CHIP_MULLINS:
630 case CHIP_TONGA:
631 case CHIP_FIJI:
632 case CHIP_CARRIZO:
633 case CHIP_STONEY:
634 case CHIP_POLARIS11:
635 case CHIP_POLARIS10:
636 case CHIP_POLARIS12:
637 case CHIP_VEGAM:
638 case CHIP_VEGA10:
639 case CHIP_VEGA12:
640 case CHIP_VEGA20:
641 return 0;
642 case CHIP_RAVEN:
643 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
644 break;
645 default:
646 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 647 return -EINVAL;
a94d5569
DF		 648 }
649
650 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
651 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
652 return 0;
653 }
654
655 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
656 if (r == -ENOENT) {
657 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
658 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
659 adev->dm.fw_dmcu = NULL;
660 return 0;
661 }
662 if (r) {
663 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
664 fw_name_dmcu);
665 return r;
666 }
667
668 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
669 if (r) {
670 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
671 fw_name_dmcu);
672 release_firmware(adev->dm.fw_dmcu);
673 adev->dm.fw_dmcu = NULL;
674 return r;
675 }
676
677 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
678 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
679 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
680 adev->firmware.fw_size +=
681 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
682
683 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
684 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
685 adev->firmware.fw_size +=
686 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
687
ee6e89c0
DF		 688 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
689
a94d5569
DF		 690 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
691
4562236b
HW		 692 return 0;
693}
694
a94d5569
DF		 695static int dm_sw_init(void *handle)
696{
697 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
698
699 return load_dmcu_fw(adev);
700}
701
4562236b
HW		 702static int dm_sw_fini(void *handle)
703{
a94d5569
DF		 704 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
705
706 if(adev->dm.fw_dmcu) {
707 release_firmware(adev->dm.fw_dmcu);
708 adev->dm.fw_dmcu = NULL;
709 }
710
4562236b
HW		 711 return 0;
712}
713
7abcf6b5 714static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 715{
c84dec2f 716 struct amdgpu_dm_connector *aconnector;
4562236b 717 struct drm_connector *connector;
7abcf6b5 718 int ret = 0;
4562236b
HW		 719
720 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
721
722 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 723 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 724 if (aconnector->dc_link->type == dc_connection_mst_branch &&
725 aconnector->mst_mgr.aux) {
f1ad2f5e 726 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 727 aconnector, aconnector->base.base.id);
728
729 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
730 if (ret < 0) {
731 DRM_ERROR("DM_MST: Failed to start MST\n");
732 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
733 return ret;
4562236b 734 }
7abcf6b5 735 }
4562236b
HW		 736 }
737
738 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 739 return ret;
740}
741
742static int dm_late_init(void *handle)
743{
42e67c3b 744 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 745
bbf854dc
DF		 746 struct dmcu_iram_parameters params;
747 unsigned int linear_lut[16];
748 int i;
749 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
750 bool ret;
751
752 for (i = 0; i < 16; i++)
753 linear_lut[i] = 0xFFFF * i / 15;
754
755 params.set = 0;
756 params.backlight_ramping_start = 0xCCCC;
757 params.backlight_ramping_reduction = 0xCCCCCCCC;
758 params.backlight_lut_array_size = 16;
759 params.backlight_lut_array = linear_lut;
760
761 ret = dmcu_load_iram(dmcu, params);
762
763 if (!ret)
764 return -EINVAL;
765
42e67c3b 766 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 767}
768
769static void s3_handle_mst(struct drm_device *dev, bool suspend)
770{
c84dec2f 771 struct amdgpu_dm_connector *aconnector;
4562236b 772 struct drm_connector *connector;
fe7553be
LP		 773 struct drm_dp_mst_topology_mgr *mgr;
774 int ret;
775 bool need_hotplug = false;
4562236b
HW		 776
777 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
778
fe7553be
LP		 779 list_for_each_entry(connector, &dev->mode_config.connector_list,
780 head) {
781 aconnector = to_amdgpu_dm_connector(connector);
782 if (aconnector->dc_link->type != dc_connection_mst_branch ||
783 aconnector->mst_port)
784 continue;
785
786 mgr = &aconnector->mst_mgr;
787
788 if (suspend) {
789 drm_dp_mst_topology_mgr_suspend(mgr);
790 } else {
791 ret = drm_dp_mst_topology_mgr_resume(mgr);
792 if (ret < 0) {
793 drm_dp_mst_topology_mgr_set_mst(mgr, false);
794 need_hotplug = true;
795 }
796 }
4562236b
HW		 797 }
798
799 drm_modeset_unlock(&dev->mode_config.connection_mutex);
fe7553be
LP		 800
801 if (need_hotplug)
802 drm_kms_helper_hotplug_event(dev);
4562236b
HW		 803}
804
b8592b48
LL		 805/**
806 * dm_hw_init() - Initialize DC device
807 * @handle: The base driver device containing the amdpgu_dm device.
808 *
809 * Initialize the &struct amdgpu_display_manager device. This involves calling
810 * the initializers of each DM component, then populating the struct with them.
811 *
812 * Although the function implies hardware initialization, both hardware and
813 * software are initialized here. Splitting them out to their relevant init
814 * hooks is a future TODO item.
815 *
816 * Some notable things that are initialized here:
817 *
818 * - Display Core, both software and hardware
819 * - DC modules that we need (freesync and color management)
820 * - DRM software states
821 * - Interrupt sources and handlers
822 * - Vblank support
823 * - Debug FS entries, if enabled
824 */
4562236b
HW		 825static int dm_hw_init(void *handle)
826{
827 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
828 /* Create DAL display manager */
829 amdgpu_dm_init(adev);
4562236b
HW		 830 amdgpu_dm_hpd_init(adev);
831
4562236b
HW		 832 return 0;
833}
834
b8592b48
LL		 835/**
836 * dm_hw_fini() - Teardown DC device
837 * @handle: The base driver device containing the amdpgu_dm device.
838 *
839 * Teardown components within &struct amdgpu_display_manager that require
840 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
841 * were loaded. Also flush IRQ workqueues and disable them.
842 */
4562236b
HW		 843static int dm_hw_fini(void *handle)
844{
845 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
846
847 amdgpu_dm_hpd_fini(adev);
848
849 amdgpu_dm_irq_fini(adev);
21de3396 850 amdgpu_dm_fini(adev);
4562236b
HW		 851 return 0;
852}
853
854static int dm_suspend(void *handle)
855{
856 struct amdgpu_device *adev = handle;
857 struct amdgpu_display_manager *dm = &adev->dm;
858 int ret = 0;
4562236b 859
d2f0b53b
LHM		 860 WARN_ON(adev->dm.cached_state);
861 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
862
4562236b
HW		 863 s3_handle_mst(adev->ddev, true);
864
4562236b
HW		 865 amdgpu_dm_irq_suspend(adev);
866
a3621485 867
32f5062d 868 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 869
870 return ret;
871}
872
1daf8c63
AD		 873static struct amdgpu_dm_connector *
874amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
875 struct drm_crtc *crtc)
4562236b
HW		 876{
877 uint32_t i;
c2cea706 878 struct drm_connector_state *new_con_state;
4562236b
HW		 879 struct drm_connector *connector;
880 struct drm_crtc *crtc_from_state;
881
c2cea706
LSL		 882 for_each_new_connector_in_state(state, connector, new_con_state, i) {
883 crtc_from_state = new_con_state->crtc;
4562236b
HW		 884
885 if (crtc_from_state == crtc)
c84dec2f 886 return to_amdgpu_dm_connector(connector);
4562236b
HW		 887 }
888
889 return NULL;
890}
891
fbbdadf2
BL		 892static void emulated_link_detect(struct dc_link *link)
893{
894 struct dc_sink_init_data sink_init_data = { 0 };
895 struct display_sink_capability sink_caps = { 0 };
896 enum dc_edid_status edid_status;
897 struct dc_context *dc_ctx = link->ctx;
898 struct dc_sink *sink = NULL;
899 struct dc_sink *prev_sink = NULL;
900
901 link->type = dc_connection_none;
902 prev_sink = link->local_sink;
903
904 if (prev_sink != NULL)
905 dc_sink_retain(prev_sink);
906
907 switch (link->connector_signal) {
908 case SIGNAL_TYPE_HDMI_TYPE_A: {
909 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
910 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
911 break;
912 }
913
914 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
915 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
916 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
917 break;
918 }
919
920 case SIGNAL_TYPE_DVI_DUAL_LINK: {
921 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
922 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
923 break;
924 }
925
926 case SIGNAL_TYPE_LVDS: {
927 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
928 sink_caps.signal = SIGNAL_TYPE_LVDS;
929 break;
930 }
931
932 case SIGNAL_TYPE_EDP: {
933 sink_caps.transaction_type =
934 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
935 sink_caps.signal = SIGNAL_TYPE_EDP;
936 break;
937 }
938
939 case SIGNAL_TYPE_DISPLAY_PORT: {
940 sink_caps.transaction_type =
941 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
942 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
943 break;
944 }
945
946 default:
947 DC_ERROR("Invalid connector type! signal:%d\n",
948 link->connector_signal);
949 return;
950 }
951
952 sink_init_data.link = link;
953 sink_init_data.sink_signal = sink_caps.signal;
954
955 sink = dc_sink_create(&sink_init_data);
956 if (!sink) {
957 DC_ERROR("Failed to create sink!\n");
958 return;
959 }
960
dcd5fb82 961 /* dc_sink_create returns a new reference */
fbbdadf2
BL		 962 link->local_sink = sink;
963
964 edid_status = dm_helpers_read_local_edid(
965 link->ctx,
966 link,
967 sink);
968
969 if (edid_status != EDID_OK)
970 DC_ERROR("Failed to read EDID");
971
972}
973
4562236b
HW		 974static int dm_resume(void *handle)
975{
976 struct amdgpu_device *adev = handle;
4562236b
HW		 977 struct drm_device *ddev = adev->ddev;
978 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 979 struct amdgpu_dm_connector *aconnector;
4562236b 980 struct drm_connector *connector;
4562236b 981 struct drm_crtc *crtc;
c2cea706 982 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 983 struct dm_crtc_state *dm_new_crtc_state;
984 struct drm_plane *plane;
985 struct drm_plane_state *new_plane_state;
986 struct dm_plane_state *dm_new_plane_state;
113b7a01 987 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
fbbdadf2 988 enum dc_connection_type new_connection_type = dc_connection_none;
a3621485 989 int i;
4562236b 990
113b7a01
LL		 991 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
992 dc_release_state(dm_state->context);
993 dm_state->context = dc_create_state(dm->dc);
994 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
995 dc_resource_state_construct(dm->dc, dm_state->context);
996
a80aa93d
ML		 997 /* power on hardware */
998 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
999
4562236b
HW		 1000 /* program HPD filter */
1001 dc_resume(dm->dc);
1002
1003 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
1004 s3_handle_mst(ddev, false);
1005
1006 /*
1007 * early enable HPD Rx IRQ, should be done before set mode as short
1008 * pulse interrupts are used for MST
1009 */
1010 amdgpu_dm_irq_resume_early(adev);
1011
4562236b 1012 /* Do detection*/
a80aa93d 1013 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 1014 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1015
1016 /*
1017 * this is the case when traversing through already created
1018 * MST connectors, should be skipped
1019 */
1020 if (aconnector->mst_port)
1021 continue;
1022
03ea364c 1023 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 1024 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1025 DRM_ERROR("KMS: Failed to detect connector\n");
1026
1027 if (aconnector->base.force && new_connection_type == dc_connection_none)
1028 emulated_link_detect(aconnector->dc_link);
1029 else
1030 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 1031
1032 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1033 aconnector->fake_enable = false;
1034
dcd5fb82
MF		 1035 if (aconnector->dc_sink)
1036 dc_sink_release(aconnector->dc_sink);
4562236b
HW		 1037 aconnector->dc_sink = NULL;
1038 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 1039 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 1040 }
1041
1f6010a9 1042 /* Force mode set in atomic commit */
a80aa93d 1043 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 1044 new_crtc_state->active_changed = true;
4f346e65 1045
fcb4019e
LSL		 1046 /*
1047 * atomic_check is expected to create the dc states. We need to release
1048 * them here, since they were duplicated as part of the suspend
1049 * procedure.
1050 */
a80aa93d 1051 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 1052 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1053 if (dm_new_crtc_state->stream) {
1054 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1055 dc_stream_release(dm_new_crtc_state->stream);
1056 dm_new_crtc_state->stream = NULL;
1057 }
1058 }
1059
a80aa93d 1060 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 1061 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1062 if (dm_new_plane_state->dc_state) {
1063 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1064 dc_plane_state_release(dm_new_plane_state->dc_state);
1065 dm_new_plane_state->dc_state = NULL;
1066 }
1067 }
1068
2d1af6a1 1069 drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 1070
a80aa93d 1071 dm->cached_state = NULL;
0a214e2f 1072
9faa4237 1073 amdgpu_dm_irq_resume_late(adev);
4562236b 1074
2d1af6a1 1075 return 0;
4562236b
HW		 1076}
1077
b8592b48
LL		 1078/**
1079 * DOC: DM Lifecycle
1080 *
1081 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1082 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1083 * the base driver's device list to be initialized and torn down accordingly.
1084 *
1085 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1086 */
1087
4562236b
HW		 1088static const struct amd_ip_funcs amdgpu_dm_funcs = {
1089 .name = "dm",
1090 .early_init = dm_early_init,
7abcf6b5 1091 .late_init = dm_late_init,
4562236b
HW		 1092 .sw_init = dm_sw_init,
1093 .sw_fini = dm_sw_fini,
1094 .hw_init = dm_hw_init,
1095 .hw_fini = dm_hw_fini,
1096 .suspend = dm_suspend,
1097 .resume = dm_resume,
1098 .is_idle = dm_is_idle,
1099 .wait_for_idle = dm_wait_for_idle,
1100 .check_soft_reset = dm_check_soft_reset,
1101 .soft_reset = dm_soft_reset,
1102 .set_clockgating_state = dm_set_clockgating_state,
1103 .set_powergating_state = dm_set_powergating_state,
1104};
1105
1106const struct amdgpu_ip_block_version dm_ip_block =
1107{
1108 .type = AMD_IP_BLOCK_TYPE_DCE,
1109 .major = 1,
1110 .minor = 0,
1111 .rev = 0,
1112 .funcs = &amdgpu_dm_funcs,
1113};
1114
ca3268c4 1115
b8592b48
LL		 1116/**
1117 * DOC: atomic
1118 *
1119 * *WIP*
1120 */
0a323b84 1121
b3663f70 1122static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 1123 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 1124 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 1125 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 1126 .atomic_commit = amdgpu_dm_atomic_commit,
54f5499a
AG		 1127};
1128
1129static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1130 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 1131};
1132
7578ecda 1133static void
3ee6b26b 1134amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1135{
1136 struct drm_connector *connector = &aconnector->base;
1137 struct drm_device *dev = connector->dev;
b73a22d3 1138 struct dc_sink *sink;
4562236b
HW		 1139
1140 /* MST handled by drm_mst framework */
1141 if (aconnector->mst_mgr.mst_state == true)
1142 return;
1143
1144
1145 sink = aconnector->dc_link->local_sink;
dcd5fb82
MF		 1146 if (sink)
1147 dc_sink_retain(sink);
4562236b 1148
1f6010a9
DF		 1149 /*
1150 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 1151 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 1152 * Skip if already done during boot.
4562236b
HW		 1153 */
1154 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1155 && aconnector->dc_em_sink) {
1156
1f6010a9
DF		 1157 /*
1158 * For S3 resume with headless use eml_sink to fake stream
1159 * because on resume connector->sink is set to NULL
4562236b
HW		 1160 */
1161 mutex_lock(&dev->mode_config.mutex);
1162
1163 if (sink) {
922aa1e1 1164 if (aconnector->dc_sink) {
98e6436d 1165 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 1166 /*
1167 * retain and release below are used to
1168 * bump up refcount for sink because the link doesn't point
1169 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 1170 * reshuffle by UMD we will get into unwanted dc_sink release
1171 */
dcd5fb82 1172 dc_sink_release(aconnector->dc_sink);
922aa1e1 1173 }
4562236b 1174 aconnector->dc_sink = sink;
dcd5fb82 1175 dc_sink_retain(aconnector->dc_sink);
98e6436d
AK		 1176 amdgpu_dm_update_freesync_caps(connector,
1177 aconnector->edid);
4562236b 1178 } else {
98e6436d 1179 amdgpu_dm_update_freesync_caps(connector, NULL);
dcd5fb82 1180 if (!aconnector->dc_sink) {
4562236b 1181 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1 1182 dc_sink_retain(aconnector->dc_sink);
dcd5fb82 1183 }
4562236b
HW		 1184 }
1185
1186 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1187
1188 if (sink)
1189 dc_sink_release(sink);
4562236b
HW		 1190 return;
1191 }
1192
1193 /*
1194 * TODO: temporary guard to look for proper fix
1195 * if this sink is MST sink, we should not do anything
1196 */
dcd5fb82
MF		 1197 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1198 dc_sink_release(sink);
4562236b 1199 return;
dcd5fb82 1200 }
4562236b
HW		 1201
1202 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 1203 /*
1204 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1205 * Do nothing!!
1206 */
f1ad2f5e 1207 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b 1208 aconnector->connector_id);
dcd5fb82
MF		 1209 if (sink)
1210 dc_sink_release(sink);
4562236b
HW		 1211 return;
1212 }
1213
f1ad2f5e 1214 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 1215 aconnector->connector_id, aconnector->dc_sink, sink);
1216
1217 mutex_lock(&dev->mode_config.mutex);
1218
1f6010a9
DF		 1219 /*
1220 * 1. Update status of the drm connector
1221 * 2. Send an event and let userspace tell us what to do
1222 */
4562236b 1223 if (sink) {
1f6010a9
DF		 1224 /*
1225 * TODO: check if we still need the S3 mode update workaround.
1226 * If yes, put it here.
1227 */
4562236b 1228 if (aconnector->dc_sink)
98e6436d 1229 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1230
1231 aconnector->dc_sink = sink;
dcd5fb82 1232 dc_sink_retain(aconnector->dc_sink);
900b3cb1 1233 if (sink->dc_edid.length == 0) {
4562236b 1234 aconnector->edid = NULL;
e86e8947 1235 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 1236 } else {
4562236b
HW		 1237 aconnector->edid =
1238 (struct edid *) sink->dc_edid.raw_edid;
1239
1240
c555f023 1241 drm_connector_update_edid_property(connector,
4562236b 1242 aconnector->edid);
e86e8947
HV		 1243 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1244 aconnector->edid);
4562236b 1245 }
98e6436d 1246 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 1247
1248 } else {
e86e8947 1249 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 1250 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 1251 drm_connector_update_edid_property(connector, NULL);
4562236b 1252 aconnector->num_modes = 0;
dcd5fb82 1253 dc_sink_release(aconnector->dc_sink);
4562236b 1254 aconnector->dc_sink = NULL;
5326c452 1255 aconnector->edid = NULL;
4562236b
HW		 1256 }
1257
1258 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1259
1260 if (sink)
1261 dc_sink_release(sink);
4562236b
HW		 1262}
1263
1264static void handle_hpd_irq(void *param)
1265{
c84dec2f 1266 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1267 struct drm_connector *connector = &aconnector->base;
1268 struct drm_device *dev = connector->dev;
fbbdadf2 1269 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1270
1f6010a9
DF		 1271 /*
1272 * In case of failure or MST no need to update connector status or notify the OS
1273 * since (for MST case) MST does this in its own context.
4562236b
HW		 1274 */
1275 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 1276
1277 if (aconnector->fake_enable)
1278 aconnector->fake_enable = false;
1279
fbbdadf2
BL		 1280 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1281 DRM_ERROR("KMS: Failed to detect connector\n");
1282
1283 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1284 emulated_link_detect(aconnector->dc_link);
1285
1286
1287 drm_modeset_lock_all(dev);
1288 dm_restore_drm_connector_state(dev, connector);
1289 drm_modeset_unlock_all(dev);
1290
1291 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1292 drm_kms_helper_hotplug_event(dev);
1293
1294 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1295 amdgpu_dm_update_connector_after_detect(aconnector);
1296
1297
1298 drm_modeset_lock_all(dev);
1299 dm_restore_drm_connector_state(dev, connector);
1300 drm_modeset_unlock_all(dev);
1301
1302 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1303 drm_kms_helper_hotplug_event(dev);
1304 }
1305 mutex_unlock(&aconnector->hpd_lock);
1306
1307}
1308
c84dec2f 1309static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1310{
1311 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1312 uint8_t dret;
1313 bool new_irq_handled = false;
1314 int dpcd_addr;
1315 int dpcd_bytes_to_read;
1316
1317 const int max_process_count = 30;
1318 int process_count = 0;
1319
1320 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1321
1322 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1323 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1324 /* DPCD 0x200 - 0x201 for downstream IRQ */
1325 dpcd_addr = DP_SINK_COUNT;
1326 } else {
1327 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1328 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1329 dpcd_addr = DP_SINK_COUNT_ESI;
1330 }
1331
1332 dret = drm_dp_dpcd_read(
1333 &aconnector->dm_dp_aux.aux,
1334 dpcd_addr,
1335 esi,
1336 dpcd_bytes_to_read);
1337
1338 while (dret == dpcd_bytes_to_read &&
1339 process_count < max_process_count) {
1340 uint8_t retry;
1341 dret = 0;
1342
1343 process_count++;
1344
f1ad2f5e 1345 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1346 /* handle HPD short pulse irq */
1347 if (aconnector->mst_mgr.mst_state)
1348 drm_dp_mst_hpd_irq(
1349 &aconnector->mst_mgr,
1350 esi,
1351 &new_irq_handled);
4562236b
HW		 1352
1353 if (new_irq_handled) {
1354 /* ACK at DPCD to notify down stream */
1355 const int ack_dpcd_bytes_to_write =
1356 dpcd_bytes_to_read - 1;
1357
1358 for (retry = 0; retry < 3; retry++) {
1359 uint8_t wret;
1360
1361 wret = drm_dp_dpcd_write(
1362 &aconnector->dm_dp_aux.aux,
1363 dpcd_addr + 1,
1364 &esi[1],
1365 ack_dpcd_bytes_to_write);
1366 if (wret == ack_dpcd_bytes_to_write)
1367 break;
1368 }
1369
1f6010a9 1370 /* check if there is new irq to be handled */
4562236b
HW		 1371 dret = drm_dp_dpcd_read(
1372 &aconnector->dm_dp_aux.aux,
1373 dpcd_addr,
1374 esi,
1375 dpcd_bytes_to_read);
1376
1377 new_irq_handled = false;
d4a6e8a9 1378 } else {
4562236b 1379 break;
d4a6e8a9 1380 }
4562236b
HW		 1381 }
1382
1383 if (process_count == max_process_count)
f1ad2f5e 1384 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1385}
1386
1387static void handle_hpd_rx_irq(void *param)
1388{
c84dec2f 1389 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1390 struct drm_connector *connector = &aconnector->base;
1391 struct drm_device *dev = connector->dev;
53cbf65c 1392 struct dc_link *dc_link = aconnector->dc_link;
4562236b 1393 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
fbbdadf2 1394 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1395
1f6010a9
DF		 1396 /*
1397 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 1398 * conflict, after implement i2c helper, this mutex should be
1399 * retired.
1400 */
53cbf65c 1401 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1402 mutex_lock(&aconnector->hpd_lock);
1403
4e18814e 1404 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1405 !is_mst_root_connector) {
1406 /* Downstream Port status changed. */
fbbdadf2
BL		 1407 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1408 DRM_ERROR("KMS: Failed to detect connector\n");
1409
1410 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1411 emulated_link_detect(dc_link);
1412
1413 if (aconnector->fake_enable)
1414 aconnector->fake_enable = false;
1415
1416 amdgpu_dm_update_connector_after_detect(aconnector);
1417
1418
1419 drm_modeset_lock_all(dev);
1420 dm_restore_drm_connector_state(dev, connector);
1421 drm_modeset_unlock_all(dev);
1422
1423 drm_kms_helper_hotplug_event(dev);
1424 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1425
1426 if (aconnector->fake_enable)
1427 aconnector->fake_enable = false;
1428
4562236b
HW		 1429 amdgpu_dm_update_connector_after_detect(aconnector);
1430
1431
1432 drm_modeset_lock_all(dev);
1433 dm_restore_drm_connector_state(dev, connector);
1434 drm_modeset_unlock_all(dev);
1435
1436 drm_kms_helper_hotplug_event(dev);
1437 }
1438 }
1439 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1440 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1441 dm_handle_hpd_rx_irq(aconnector);
1442
e86e8947
HV		 1443 if (dc_link->type != dc_connection_mst_branch) {
1444 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 1445 mutex_unlock(&aconnector->hpd_lock);
e86e8947 1446 }
4562236b
HW		 1447}
1448
1449static void register_hpd_handlers(struct amdgpu_device *adev)
1450{
1451 struct drm_device *dev = adev->ddev;
1452 struct drm_connector *connector;
c84dec2f 1453 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1454 const struct dc_link *dc_link;
1455 struct dc_interrupt_params int_params = {0};
1456
1457 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1458 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1459
1460 list_for_each_entry(connector,
1461 &dev->mode_config.connector_list, head) {
1462
c84dec2f 1463 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1464 dc_link = aconnector->dc_link;
1465
1466 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1467 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1468 int_params.irq_source = dc_link->irq_source_hpd;
1469
1470 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1471 handle_hpd_irq,
1472 (void *) aconnector);
1473 }
1474
1475 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1476
1477 /* Also register for DP short pulse (hpd_rx). */
1478 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1479 int_params.irq_source = dc_link->irq_source_hpd_rx;
1480
1481 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1482 handle_hpd_rx_irq,
1483 (void *) aconnector);
1484 }
1485 }
1486}
1487
1488/* Register IRQ sources and initialize IRQ callbacks */
1489static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1490{
1491 struct dc *dc = adev->dm.dc;
1492 struct common_irq_params *c_irq_params;
1493 struct dc_interrupt_params int_params = {0};
1494 int r;
1495 int i;
1ffdeca6 1496 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 1497
ff5ef992 1498 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1499 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1500 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1501 adev->asic_type == CHIP_RAVEN)
3760f76c 1502 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1503
1504 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1505 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1506
1f6010a9
DF		 1507 /*
1508 * Actions of amdgpu_irq_add_id():
4562236b
HW		 1509 * 1. Register a set() function with base driver.
1510 * Base driver will call set() function to enable/disable an
1511 * interrupt in DC hardware.
1512 * 2. Register amdgpu_dm_irq_handler().
1513 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1514 * coming from DC hardware.
1515 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1516 * for acknowledging and handling. */
1517
b57de80a 1518 /* Use VBLANK interrupt */
e9029155 1519 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1520 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1521 if (r) {
1522 DRM_ERROR("Failed to add crtc irq id!\n");
1523 return r;
1524 }
1525
1526 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1527 int_params.irq_source =
3d761e79 1528 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1529
b57de80a 1530 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1531
1532 c_irq_params->adev = adev;
1533 c_irq_params->irq_src = int_params.irq_source;
1534
1535 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1536 dm_crtc_high_irq, c_irq_params);
1537 }
1538
d2574c33
MK		 1539 /* Use VUPDATE interrupt */
1540 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
1541 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
1542 if (r) {
1543 DRM_ERROR("Failed to add vupdate irq id!\n");
1544 return r;
1545 }
1546
1547 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1548 int_params.irq_source =
1549 dc_interrupt_to_irq_source(dc, i, 0);
1550
1551 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1552
1553 c_irq_params->adev = adev;
1554 c_irq_params->irq_src = int_params.irq_source;
1555
1556 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1557 dm_vupdate_high_irq, c_irq_params);
1558 }
1559
3d761e79 1560 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1561 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1562 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1563 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1564 if (r) {
1565 DRM_ERROR("Failed to add page flip irq id!\n");
1566 return r;
1567 }
1568
1569 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1570 int_params.irq_source =
1571 dc_interrupt_to_irq_source(dc, i, 0);
1572
1573 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1574
1575 c_irq_params->adev = adev;
1576 c_irq_params->irq_src = int_params.irq_source;
1577
1578 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1579 dm_pflip_high_irq, c_irq_params);
1580
1581 }
1582
1583 /* HPD */
2c8ad2d5
AD		 1584 r = amdgpu_irq_add_id(adev, client_id,
1585 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1586 if (r) {
1587 DRM_ERROR("Failed to add hpd irq id!\n");
1588 return r;
1589 }
1590
1591 register_hpd_handlers(adev);
1592
1593 return 0;
1594}
1595
ff5ef992
AD		 1596#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1597/* Register IRQ sources and initialize IRQ callbacks */
1598static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1599{
1600 struct dc *dc = adev->dm.dc;
1601 struct common_irq_params *c_irq_params;
1602 struct dc_interrupt_params int_params = {0};
1603 int r;
1604 int i;
1605
1606 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1607 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1608
1f6010a9
DF		 1609 /*
1610 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 1611 * 1. Register a set() function with base driver.
1612 * Base driver will call set() function to enable/disable an
1613 * interrupt in DC hardware.
1614 * 2. Register amdgpu_dm_irq_handler().
1615 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1616 * coming from DC hardware.
1617 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1618 * for acknowledging and handling.
1f6010a9 1619 */
ff5ef992
AD		 1620
1621 /* Use VSTARTUP interrupt */
1622 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1623 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1624 i++) {
3760f76c 1625 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1626
1627 if (r) {
1628 DRM_ERROR("Failed to add crtc irq id!\n");
1629 return r;
1630 }
1631
1632 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1633 int_params.irq_source =
1634 dc_interrupt_to_irq_source(dc, i, 0);
1635
1636 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1637
1638 c_irq_params->adev = adev;
1639 c_irq_params->irq_src = int_params.irq_source;
1640
1641 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1642 dm_crtc_high_irq, c_irq_params);
1643 }
1644
d2574c33
MK		 1645 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
1646 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
1647 * to trigger at end of each vblank, regardless of state of the lock,
1648 * matching DCE behaviour.
1649 */
1650 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
1651 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
1652 i++) {
1653 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
1654
1655 if (r) {
1656 DRM_ERROR("Failed to add vupdate irq id!\n");
1657 return r;
1658 }
1659
1660 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1661 int_params.irq_source =
1662 dc_interrupt_to_irq_source(dc, i, 0);
1663
1664 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1665
1666 c_irq_params->adev = adev;
1667 c_irq_params->irq_src = int_params.irq_source;
1668
1669 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1670 dm_vupdate_high_irq, c_irq_params);
1671 }
1672
ff5ef992
AD		 1673 /* Use GRPH_PFLIP interrupt */
1674 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1675 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1676 i++) {
3760f76c 1677 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1678 if (r) {
1679 DRM_ERROR("Failed to add page flip irq id!\n");
1680 return r;
1681 }
1682
1683 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1684 int_params.irq_source =
1685 dc_interrupt_to_irq_source(dc, i, 0);
1686
1687 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1688
1689 c_irq_params->adev = adev;
1690 c_irq_params->irq_src = int_params.irq_source;
1691
1692 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1693 dm_pflip_high_irq, c_irq_params);
1694
1695 }
1696
1697 /* HPD */
3760f76c 1698 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1699 &adev->hpd_irq);
1700 if (r) {
1701 DRM_ERROR("Failed to add hpd irq id!\n");
1702 return r;
1703 }
1704
1705 register_hpd_handlers(adev);
1706
1707 return 0;
1708}
1709#endif
1710
eb3dc897
NK		 1711/*
1712 * Acquires the lock for the atomic state object and returns
1713 * the new atomic state.
1714 *
1715 * This should only be called during atomic check.
1716 */
1717static int dm_atomic_get_state(struct drm_atomic_state *state,
1718 struct dm_atomic_state **dm_state)
1719{
1720 struct drm_device *dev = state->dev;
1721 struct amdgpu_device *adev = dev->dev_private;
1722 struct amdgpu_display_manager *dm = &adev->dm;
1723 struct drm_private_state *priv_state;
eb3dc897
NK		 1724
1725 if (*dm_state)
1726 return 0;
1727
eb3dc897
NK		 1728 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1729 if (IS_ERR(priv_state))
1730 return PTR_ERR(priv_state);
1731
1732 *dm_state = to_dm_atomic_state(priv_state);
1733
1734 return 0;
1735}
1736
1737struct dm_atomic_state *
1738dm_atomic_get_new_state(struct drm_atomic_state *state)
1739{
1740 struct drm_device *dev = state->dev;
1741 struct amdgpu_device *adev = dev->dev_private;
1742 struct amdgpu_display_manager *dm = &adev->dm;
1743 struct drm_private_obj *obj;
1744 struct drm_private_state *new_obj_state;
1745 int i;
1746
1747 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1748 if (obj->funcs == dm->atomic_obj.funcs)
1749 return to_dm_atomic_state(new_obj_state);
1750 }
1751
1752 return NULL;
1753}
1754
1755struct dm_atomic_state *
1756dm_atomic_get_old_state(struct drm_atomic_state *state)
1757{
1758 struct drm_device *dev = state->dev;
1759 struct amdgpu_device *adev = dev->dev_private;
1760 struct amdgpu_display_manager *dm = &adev->dm;
1761 struct drm_private_obj *obj;
1762 struct drm_private_state *old_obj_state;
1763 int i;
1764
1765 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1766 if (obj->funcs == dm->atomic_obj.funcs)
1767 return to_dm_atomic_state(old_obj_state);
1768 }
1769
1770 return NULL;
1771}
1772
1773static struct drm_private_state *
1774dm_atomic_duplicate_state(struct drm_private_obj *obj)
1775{
1776 struct dm_atomic_state *old_state, *new_state;
1777
1778 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1779 if (!new_state)
1780 return NULL;
1781
1782 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1783
813d20dc
AW		 1784 old_state = to_dm_atomic_state(obj->state);
1785
1786 if (old_state && old_state->context)
1787 new_state->context = dc_copy_state(old_state->context);
1788
eb3dc897
NK		 1789 if (!new_state->context) {
1790 kfree(new_state);
1791 return NULL;
1792 }
1793
eb3dc897
NK		 1794 return &new_state->base;
1795}
1796
1797static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1798 struct drm_private_state *state)
1799{
1800 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1801
1802 if (dm_state && dm_state->context)
1803 dc_release_state(dm_state->context);
1804
1805 kfree(dm_state);
1806}
1807
1808static struct drm_private_state_funcs dm_atomic_state_funcs = {
1809 .atomic_duplicate_state = dm_atomic_duplicate_state,
1810 .atomic_destroy_state = dm_atomic_destroy_state,
1811};
1812
4562236b
HW		 1813static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1814{
eb3dc897 1815 struct dm_atomic_state *state;
4562236b
HW		 1816 int r;
1817
1818 adev->mode_info.mode_config_initialized = true;
1819
4562236b 1820 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1821 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1822
1823 adev->ddev->mode_config.max_width = 16384;
1824 adev->ddev->mode_config.max_height = 16384;
1825
1826 adev->ddev->mode_config.preferred_depth = 24;
1827 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 1828 /* indicates support for immediate flip */
4562236b
HW		 1829 adev->ddev->mode_config.async_page_flip = true;
1830
770d13b1 1831 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1832
eb3dc897
NK		 1833 state = kzalloc(sizeof(*state), GFP_KERNEL);
1834 if (!state)
1835 return -ENOMEM;
1836
813d20dc 1837 state->context = dc_create_state(adev->dm.dc);
eb3dc897
NK		 1838 if (!state->context) {
1839 kfree(state);
1840 return -ENOMEM;
1841 }
1842
1843 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1844
8c1a765b
DA		 1845 drm_atomic_private_obj_init(adev->ddev,
1846 &adev->dm.atomic_obj,
eb3dc897
NK		 1847 &state->base,
1848 &dm_atomic_state_funcs);
1849
3dc9b1ce 1850 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1851 if (r)
1852 return r;
1853
1854 return 0;
1855}
1856
206bbafe
DF		 1857#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1858#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1859
4562236b
HW		 1860#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1861 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1862
206bbafe
DF		 1863static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1864{
1865#if defined(CONFIG_ACPI)
1866 struct amdgpu_dm_backlight_caps caps;
1867
1868 if (dm->backlight_caps.caps_valid)
1869 return;
1870
1871 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1872 if (caps.caps_valid) {
1873 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1874 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1875 dm->backlight_caps.caps_valid = true;
1876 } else {
1877 dm->backlight_caps.min_input_signal =
1878 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1879 dm->backlight_caps.max_input_signal =
1880 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1881 }
1882#else
8bcbc9ef
DF		 1883 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1884 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 1885#endif
1886}
1887
4562236b
HW		 1888static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1889{
1890 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe
DF		 1891 struct amdgpu_dm_backlight_caps caps;
1892 uint32_t brightness = bd->props.brightness;
4562236b 1893
206bbafe
DF		 1894 amdgpu_dm_update_backlight_caps(dm);
1895 caps = dm->backlight_caps;
0cafc82f 1896 /*
206bbafe
DF		 1897 * The brightness input is in the range 0-255
1898 * It needs to be rescaled to be between the
1899 * requested min and max input signal
1900 *
1901 * It also needs to be scaled up by 0x101 to
1902 * match the DC interface which has a range of
1903 * 0 to 0xffff
0cafc82f 1904 */
206bbafe
DF		 1905 brightness =
1906 brightness
1907 * 0x101
1908 * (caps.max_input_signal - caps.min_input_signal)
1909 / AMDGPU_MAX_BL_LEVEL
1910 + caps.min_input_signal * 0x101;
4562236b
HW		 1911
1912 if (dc_link_set_backlight_level(dm->backlight_link,
923fe495 1913 brightness, 0))
4562236b
HW		 1914 return 0;
1915 else
1916 return 1;
1917}
1918
1919static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1920{
620a0d27
DF		 1921 struct amdgpu_display_manager *dm = bl_get_data(bd);
1922 int ret = dc_link_get_backlight_level(dm->backlight_link);
1923
1924 if (ret == DC_ERROR_UNEXPECTED)
1925 return bd->props.brightness;
1926 return ret;
4562236b
HW		 1927}
1928
1929static const struct backlight_ops amdgpu_dm_backlight_ops = {
1930 .get_brightness = amdgpu_dm_backlight_get_brightness,
1931 .update_status = amdgpu_dm_backlight_update_status,
1932};
1933
7578ecda
AD		 1934static void
1935amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1936{
1937 char bl_name[16];
1938 struct backlight_properties props = { 0 };
1939
206bbafe
DF		 1940 amdgpu_dm_update_backlight_caps(dm);
1941
4562236b 1942 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 1943 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 1944 props.type = BACKLIGHT_RAW;
1945
1946 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1947 dm->adev->ddev->primary->index);
1948
1949 dm->backlight_dev = backlight_device_register(bl_name,
1950 dm->adev->ddev->dev,
1951 dm,
1952 &amdgpu_dm_backlight_ops,
1953 &props);
1954
74baea42 1955 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1956 DRM_ERROR("DM: Backlight registration failed!\n");
1957 else
f1ad2f5e 1958 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1959}
1960
1961#endif
1962
df534fff 1963static int initialize_plane(struct amdgpu_display_manager *dm,
b2fddb13 1964 struct amdgpu_mode_info *mode_info, int plane_id,
cc1fec57
NK		 1965 enum drm_plane_type plane_type,
1966 const struct dc_plane_cap *plane_cap)
df534fff 1967{
f180b4bc 1968 struct drm_plane *plane;
df534fff
S		 1969 unsigned long possible_crtcs;
1970 int ret = 0;
1971
f180b4bc 1972 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 1973 if (!plane) {
1974 DRM_ERROR("KMS: Failed to allocate plane\n");
1975 return -ENOMEM;
1976 }
b2fddb13 1977 plane->type = plane_type;
df534fff
S		 1978
1979 /*
b2fddb13
NK		 1980 * HACK: IGT tests expect that the primary plane for a CRTC
1981 * can only have one possible CRTC. Only expose support for
1982 * any CRTC if they're not going to be used as a primary plane
1983 * for a CRTC - like overlay or underlay planes.
df534fff
S		 1984 */
1985 possible_crtcs = 1 << plane_id;
1986 if (plane_id >= dm->dc->caps.max_streams)
1987 possible_crtcs = 0xff;
1988
cc1fec57 1989 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
df534fff
S		 1990
1991 if (ret) {
1992 DRM_ERROR("KMS: Failed to initialize plane\n");
54087768 1993 kfree(plane);
df534fff
S		 1994 return ret;
1995 }
1996
54087768
NK		 1997 if (mode_info)
1998 mode_info->planes[plane_id] = plane;
1999
df534fff
S		 2000 return ret;
2001}
2002
89fc8d4e
HW		 2003
2004static void register_backlight_device(struct amdgpu_display_manager *dm,
2005 struct dc_link *link)
2006{
2007#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2008 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2009
2010 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2011 link->type != dc_connection_none) {
1f6010a9
DF		 2012 /*
2013 * Event if registration failed, we should continue with
89fc8d4e
HW		 2014 * DM initialization because not having a backlight control
2015 * is better then a black screen.
2016 */
2017 amdgpu_dm_register_backlight_device(dm);
2018
2019 if (dm->backlight_dev)
2020 dm->backlight_link = link;
2021 }
2022#endif
2023}
2024
2025
1f6010a9
DF		 2026/*
2027 * In this architecture, the association
4562236b
HW		 2028 * connector -> encoder -> crtc
2029 * id not really requried. The crtc and connector will hold the
2030 * display_index as an abstraction to use with DAL component
2031 *
2032 * Returns 0 on success
2033 */
7578ecda 2034static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 2035{
2036 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 2037 int32_t i;
c84dec2f 2038 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 2039 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 2040 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 2041 uint32_t link_cnt;
cc1fec57 2042 int32_t primary_planes;
fbbdadf2 2043 enum dc_connection_type new_connection_type = dc_connection_none;
cc1fec57 2044 const struct dc_plane_cap *plane;
4562236b
HW		 2045
2046 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 2047 if (amdgpu_dm_mode_config_init(dm->adev)) {
2048 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 2049 return -EINVAL;
4562236b
HW		 2050 }
2051
b2fddb13
NK		 2052 /* There is one primary plane per CRTC */
2053 primary_planes = dm->dc->caps.max_streams;
54087768 2054 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
efa6a8b7 2055
b2fddb13
NK		 2056 /*
2057 * Initialize primary planes, implicit planes for legacy IOCTLS.
2058 * Order is reversed to match iteration order in atomic check.
2059 */
2060 for (i = (primary_planes - 1); i >= 0; i--) {
cc1fec57
NK		 2061 plane = &dm->dc->caps.planes[i];
2062
b2fddb13 2063 if (initialize_plane(dm, mode_info, i,
cc1fec57 2064 DRM_PLANE_TYPE_PRIMARY, plane)) {
df534fff 2065 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 2066 goto fail;
d4e13b0d 2067 }
df534fff 2068 }
92f3ac40 2069
0d579c7e
NK		 2070 /*
2071 * Initialize overlay planes, index starting after primary planes.
2072 * These planes have a higher DRM index than the primary planes since
2073 * they should be considered as having a higher z-order.
2074 * Order is reversed to match iteration order in atomic check.
cc1fec57
NK		 2075 *
2076 * Only support DCN for now, and only expose one so we don't encourage
2077 * userspace to use up all the pipes.
0d579c7e 2078 */
cc1fec57
NK		 2079 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2080 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2081
2082 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2083 continue;
2084
2085 if (!plane->blends_with_above || !plane->blends_with_below)
2086 continue;
2087
ea36ad34 2088 if (!plane->pixel_format_support.argb8888)
cc1fec57
NK		 2089 continue;
2090
54087768 2091 if (initialize_plane(dm, NULL, primary_planes + i,
cc1fec57 2092 DRM_PLANE_TYPE_OVERLAY, plane)) {
0d579c7e 2093 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 2094 goto fail;
d4e13b0d 2095 }
cc1fec57
NK		 2096
2097 /* Only create one overlay plane. */
2098 break;
d4e13b0d 2099 }
4562236b 2100
d4e13b0d 2101 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 2102 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 2103 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 2104 goto fail;
4562236b 2105 }
4562236b 2106
ab2541b6 2107 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 2108
2109 /* loops over all connectors on the board */
2110 for (i = 0; i < link_cnt; i++) {
89fc8d4e 2111 struct dc_link *link = NULL;
4562236b
HW		 2112
2113 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2114 DRM_ERROR(
2115 "KMS: Cannot support more than %d display indexes\n",
2116 AMDGPU_DM_MAX_DISPLAY_INDEX);
2117 continue;
2118 }
2119
2120 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2121 if (!aconnector)
cd8a2ae8 2122 goto fail;
4562236b
HW		 2123
2124 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 2125 if (!aencoder)
cd8a2ae8 2126 goto fail;
4562236b
HW		 2127
2128 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2129 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 2130 goto fail;
4562236b
HW		 2131 }
2132
2133 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2134 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 2135 goto fail;
4562236b
HW		 2136 }
2137
89fc8d4e
HW		 2138 link = dc_get_link_at_index(dm->dc, i);
2139
fbbdadf2
BL		 2140 if (!dc_link_detect_sink(link, &new_connection_type))
2141 DRM_ERROR("KMS: Failed to detect connector\n");
2142
2143 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2144 emulated_link_detect(link);
2145 amdgpu_dm_update_connector_after_detect(aconnector);
2146
2147 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 2148 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 2149 register_backlight_device(dm, link);
2150 }
2151
2152
4562236b
HW		 2153 }
2154
2155 /* Software is initialized. Now we can register interrupt handlers. */
2156 switch (adev->asic_type) {
2157 case CHIP_BONAIRE:
2158 case CHIP_HAWAII:
cd4b356f
AD		 2159 case CHIP_KAVERI:
2160 case CHIP_KABINI:
2161 case CHIP_MULLINS:
4562236b
HW		 2162 case CHIP_TONGA:
2163 case CHIP_FIJI:
2164 case CHIP_CARRIZO:
2165 case CHIP_STONEY:
2166 case CHIP_POLARIS11:
2167 case CHIP_POLARIS10:
b264d345 2168 case CHIP_POLARIS12:
7737de91 2169 case CHIP_VEGAM:
2c8ad2d5 2170 case CHIP_VEGA10:
2325ff30 2171 case CHIP_VEGA12:
1fe6bf2f 2172 case CHIP_VEGA20:
4562236b
HW		 2173 if (dce110_register_irq_handlers(dm->adev)) {
2174 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2175 goto fail;
4562236b
HW		 2176 }
2177 break;
ff5ef992
AD		 2178#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2179 case CHIP_RAVEN:
2180 if (dcn10_register_irq_handlers(dm->adev)) {
2181 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2182 goto fail;
ff5ef992
AD		 2183 }
2184 break;
2185#endif
4562236b 2186 default:
e63f8673 2187 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 2188 goto fail;
4562236b
HW		 2189 }
2190
1bc460a4
HW		 2191 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2192 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2193
4562236b 2194 return 0;
cd8a2ae8 2195fail:
4562236b 2196 kfree(aencoder);
4562236b 2197 kfree(aconnector);
54087768 2198
59d0f396 2199 return -EINVAL;
4562236b
HW		 2200}
2201
7578ecda 2202static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2203{
2204 drm_mode_config_cleanup(dm->ddev);
eb3dc897 2205 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 2206 return;
2207}
2208
2209/******************************************************************************
2210 * amdgpu_display_funcs functions
2211 *****************************************************************************/
2212
1f6010a9 2213/*
4562236b
HW		 2214 * dm_bandwidth_update - program display watermarks
2215 *
2216 * @adev: amdgpu_device pointer
2217 *
2218 * Calculate and program the display watermarks and line buffer allocation.
2219 */
2220static void dm_bandwidth_update(struct amdgpu_device *adev)
2221{
49c07a99 2222 /* TODO: implement later */
4562236b
HW		 2223}
2224
39cc5be2 2225static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 2226 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2227 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 2228 .backlight_set_level = NULL, /* never called for DC */
2229 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 2230 .hpd_sense = NULL,/* called unconditionally */
2231 .hpd_set_polarity = NULL, /* called unconditionally */
2232 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2233 .page_flip_get_scanoutpos =
2234 dm_crtc_get_scanoutpos,/* called unconditionally */
2235 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2236 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2237};
2238
2239#if defined(CONFIG_DEBUG_KERNEL_DC)
2240
3ee6b26b
AD		 2241static ssize_t s3_debug_store(struct device *device,
2242 struct device_attribute *attr,
2243 const char *buf,
2244 size_t count)
4562236b
HW		 2245{
2246 int ret;
2247 int s3_state;
2248 struct pci_dev *pdev = to_pci_dev(device);
2249 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2250 struct amdgpu_device *adev = drm_dev->dev_private;
2251
2252 ret = kstrtoint(buf, 0, &s3_state);
2253
2254 if (ret == 0) {
2255 if (s3_state) {
2256 dm_resume(adev);
4562236b
HW		 2257 drm_kms_helper_hotplug_event(adev->ddev);
2258 } else
2259 dm_suspend(adev);
2260 }
2261
2262 return ret == 0 ? count : 0;
2263}
2264
2265DEVICE_ATTR_WO(s3_debug);
2266
2267#endif
2268
2269static int dm_early_init(void *handle)
2270{
2271 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2272
4562236b
HW		 2273 switch (adev->asic_type) {
2274 case CHIP_BONAIRE:
2275 case CHIP_HAWAII:
2276 adev->mode_info.num_crtc = 6;
2277 adev->mode_info.num_hpd = 6;
2278 adev->mode_info.num_dig = 6;
4562236b 2279 break;
cd4b356f
AD		 2280 case CHIP_KAVERI:
2281 adev->mode_info.num_crtc = 4;
2282 adev->mode_info.num_hpd = 6;
2283 adev->mode_info.num_dig = 7;
cd4b356f
AD		 2284 break;
2285 case CHIP_KABINI:
2286 case CHIP_MULLINS:
2287 adev->mode_info.num_crtc = 2;
2288 adev->mode_info.num_hpd = 6;
2289 adev->mode_info.num_dig = 6;
cd4b356f 2290 break;
4562236b
HW		 2291 case CHIP_FIJI:
2292 case CHIP_TONGA:
2293 adev->mode_info.num_crtc = 6;
2294 adev->mode_info.num_hpd = 6;
2295 adev->mode_info.num_dig = 7;
4562236b
HW		 2296 break;
2297 case CHIP_CARRIZO:
2298 adev->mode_info.num_crtc = 3;
2299 adev->mode_info.num_hpd = 6;
2300 adev->mode_info.num_dig = 9;
4562236b
HW		 2301 break;
2302 case CHIP_STONEY:
2303 adev->mode_info.num_crtc = 2;
2304 adev->mode_info.num_hpd = 6;
2305 adev->mode_info.num_dig = 9;
4562236b
HW		 2306 break;
2307 case CHIP_POLARIS11:
b264d345 2308 case CHIP_POLARIS12:
4562236b
HW		 2309 adev->mode_info.num_crtc = 5;
2310 adev->mode_info.num_hpd = 5;
2311 adev->mode_info.num_dig = 5;
4562236b
HW		 2312 break;
2313 case CHIP_POLARIS10:
7737de91 2314 case CHIP_VEGAM:
4562236b
HW		 2315 adev->mode_info.num_crtc = 6;
2316 adev->mode_info.num_hpd = 6;
2317 adev->mode_info.num_dig = 6;
4562236b 2318 break;
2c8ad2d5 2319 case CHIP_VEGA10:
2325ff30 2320 case CHIP_VEGA12:
1fe6bf2f 2321 case CHIP_VEGA20:
2c8ad2d5
AD		 2322 adev->mode_info.num_crtc = 6;
2323 adev->mode_info.num_hpd = 6;
2324 adev->mode_info.num_dig = 6;
2325 break;
ff5ef992
AD		 2326#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2327 case CHIP_RAVEN:
2328 adev->mode_info.num_crtc = 4;
2329 adev->mode_info.num_hpd = 4;
2330 adev->mode_info.num_dig = 4;
ff5ef992
AD		 2331 break;
2332#endif
4562236b 2333 default:
e63f8673 2334 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 2335 return -EINVAL;
2336 }
2337
c8dd5715
MD		 2338 amdgpu_dm_set_irq_funcs(adev);
2339
39cc5be2
AD		 2340 if (adev->mode_info.funcs == NULL)
2341 adev->mode_info.funcs = &dm_display_funcs;
2342
1f6010a9
DF		 2343 /*
2344 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 2345 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 2346 * amdgpu_device_init()
2347 */
4562236b
HW		 2348#if defined(CONFIG_DEBUG_KERNEL_DC)
2349 device_create_file(
2350 adev->ddev->dev,
2351 &dev_attr_s3_debug);
2352#endif
2353
2354 return 0;
2355}
2356
9b690ef3 2357static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 2358 struct dc_stream_state *new_stream,
2359 struct dc_stream_state *old_stream)
9b690ef3 2360{
e7b07cee
HW		 2361 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2362 return false;
2363
2364 if (!crtc_state->enable)
2365 return false;
2366
2367 return crtc_state->active;
2368}
2369
2370static bool modereset_required(struct drm_crtc_state *crtc_state)
2371{
2372 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2373 return false;
2374
2375 return !crtc_state->enable || !crtc_state->active;
2376}
2377
7578ecda 2378static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 2379{
2380 drm_encoder_cleanup(encoder);
2381 kfree(encoder);
2382}
2383
2384static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2385 .destroy = amdgpu_dm_encoder_destroy,
2386};
2387
3ee6b26b 2388static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
78171832
NK		 2389 struct rect *src_rect,
2390 struct rect *dst_rect,
2391 struct rect *clip_rect,
2392 enum dc_rotation_angle *rotation)
e7b07cee 2393{
78171832
NK		 2394 src_rect->x = state->src_x >> 16;
2395 src_rect->y = state->src_y >> 16;
1f6010a9 2396 /* we ignore the mantissa for now and do not deal with floating pixels :( */
78171832 2397 src_rect->width = state->src_w >> 16;
e7b07cee 2398
78171832 2399 if (src_rect->width == 0)
e7b07cee
HW		 2400 return false;
2401
78171832
NK		 2402 src_rect->height = state->src_h >> 16;
2403 if (src_rect->height == 0)
e7b07cee
HW		 2404 return false;
2405
78171832
NK		 2406 dst_rect->x = state->crtc_x;
2407 dst_rect->y = state->crtc_y;
e7b07cee
HW		 2408
2409 if (state->crtc_w == 0)
2410 return false;
2411
78171832 2412 dst_rect->width = state->crtc_w;
e7b07cee
HW		 2413
2414 if (state->crtc_h == 0)
2415 return false;
2416
78171832 2417 dst_rect->height = state->crtc_h;
e7b07cee 2418
78171832 2419 *clip_rect = *dst_rect;
e7b07cee
HW		 2420
2421 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
2422 case DRM_MODE_ROTATE_0:
78171832 2423 *rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2424 break;
2425 case DRM_MODE_ROTATE_90:
78171832 2426 *rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 2427 break;
2428 case DRM_MODE_ROTATE_180:
78171832 2429 *rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 2430 break;
2431 case DRM_MODE_ROTATE_270:
78171832 2432 *rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 2433 break;
2434 default:
78171832 2435 *rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2436 break;
2437 }
2438
4562236b
HW		 2439 return true;
2440}
3ee6b26b 2441static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 2442 uint64_t *tiling_flags)
e7b07cee 2443{
e68d14dd 2444 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 2445 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 2446
e7b07cee 2447 if (unlikely(r)) {
1f6010a9 2448 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 2449 if (r != -ERESTARTSYS)
2450 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 2451 return r;
2452 }
2453
e7b07cee
HW		 2454 if (tiling_flags)
2455 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2456
2457 amdgpu_bo_unreserve(rbo);
2458
2459 return r;
2460}
2461
7df7e505
NK		 2462static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2463{
2464 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2465
2466 return offset ? (address + offset * 256) : 0;
2467}
2468
09e5665a 2469static int fill_plane_dcc_attributes(struct amdgpu_device *adev,
7df7e505 2470 const struct amdgpu_framebuffer *afb,
09e5665a
NK		 2471 const struct dc_plane_state *plane_state,
2472 struct dc_plane_dcc_param *dcc,
2473 struct dc_plane_address *address,
7df7e505
NK		 2474 uint64_t info)
2475{
2476 struct dc *dc = adev->dm.dc;
8daa1218
NC		 2477 struct dc_dcc_surface_param input;
2478 struct dc_surface_dcc_cap output;
7df7e505
NK		 2479 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2480 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2481 uint64_t dcc_address;
2482
8daa1218
NC		 2483 memset(&input, 0, sizeof(input));
2484 memset(&output, 0, sizeof(output));
2485
7df7e505 2486 if (!offset)
09e5665a
NK		 2487 return 0;
2488
2489 if (plane_state->address.type != PLN_ADDR_TYPE_GRAPHICS)
2490 return 0;
7df7e505
NK		 2491
2492 if (!dc->cap_funcs.get_dcc_compression_cap)
09e5665a 2493 return -EINVAL;
7df7e505
NK		 2494
2495 input.format = plane_state->format;
2496 input.surface_size.width =
2497 plane_state->plane_size.grph.surface_size.width;
2498 input.surface_size.height =
2499 plane_state->plane_size.grph.surface_size.height;
2500 input.swizzle_mode = plane_state->tiling_info.gfx9.swizzle;
2501
2502 if (plane_state->rotation == ROTATION_ANGLE_0 ||
2503 plane_state->rotation == ROTATION_ANGLE_180)
2504 input.scan = SCAN_DIRECTION_HORIZONTAL;
2505 else if (plane_state->rotation == ROTATION_ANGLE_90 ||
2506 plane_state->rotation == ROTATION_ANGLE_270)
2507 input.scan = SCAN_DIRECTION_VERTICAL;
2508
2509 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
09e5665a 2510 return -EINVAL;
7df7e505
NK		 2511
2512 if (!output.capable)
09e5665a 2513 return -EINVAL;
7df7e505
NK		 2514
2515 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
09e5665a 2516 return -EINVAL;
7df7e505 2517
09e5665a
NK		 2518 dcc->enable = 1;
2519 dcc->grph.meta_pitch =
7df7e505 2520 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
09e5665a 2521 dcc->grph.independent_64b_blks = i64b;
7df7e505
NK		 2522
2523 dcc_address = get_dcc_address(afb->address, info);
09e5665a
NK		 2524 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
2525 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
7df7e505 2526
09e5665a
NK		 2527 return 0;
2528}
2529
2530static int
2531fill_plane_tiling_attributes(struct amdgpu_device *adev,
2532 const struct amdgpu_framebuffer *afb,
2533 const struct dc_plane_state *plane_state,
2534 union dc_tiling_info *tiling_info,
2535 struct dc_plane_dcc_param *dcc,
2536 struct dc_plane_address *address,
2537 uint64_t tiling_flags)
2538{
2539 int ret;
2540
2541 memset(tiling_info, 0, sizeof(*tiling_info));
2542 memset(dcc, 0, sizeof(*dcc));
e0634e8d
NK		 2543 memset(address, 0, sizeof(*address));
2544
2545 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2546 address->type = PLN_ADDR_TYPE_GRAPHICS;
2547 address->grph.addr.low_part = lower_32_bits(afb->address);
2548 address->grph.addr.high_part = upper_32_bits(afb->address);
2549 } else {
2550 const struct drm_framebuffer *fb = &afb->base;
1791e54f 2551 uint64_t chroma_addr = afb->address + fb->offsets[1];
e0634e8d
NK		 2552
2553 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2554 address->video_progressive.luma_addr.low_part =
2555 lower_32_bits(afb->address);
2556 address->video_progressive.luma_addr.high_part =
2557 upper_32_bits(afb->address);
2558 address->video_progressive.chroma_addr.low_part =
2559 lower_32_bits(chroma_addr);
2560 address->video_progressive.chroma_addr.high_part =
2561 upper_32_bits(chroma_addr);
2562 }
09e5665a
NK		 2563
2564 /* Fill GFX8 params */
2565 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2566 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2567
2568 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2569 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2570 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2571 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2572 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2573
2574 /* XXX fix me for VI */
2575 tiling_info->gfx8.num_banks = num_banks;
2576 tiling_info->gfx8.array_mode =
2577 DC_ARRAY_2D_TILED_THIN1;
2578 tiling_info->gfx8.tile_split = tile_split;
2579 tiling_info->gfx8.bank_width = bankw;
2580 tiling_info->gfx8.bank_height = bankh;
2581 tiling_info->gfx8.tile_aspect = mtaspect;
2582 tiling_info->gfx8.tile_mode =
2583 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2584 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2585 == DC_ARRAY_1D_TILED_THIN1) {
2586 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2587 }
2588
2589 tiling_info->gfx8.pipe_config =
2590 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2591
2592 if (adev->asic_type == CHIP_VEGA10 ||
2593 adev->asic_type == CHIP_VEGA12 ||
2594 adev->asic_type == CHIP_VEGA20 ||
2595 adev->asic_type == CHIP_RAVEN) {
2596 /* Fill GFX9 params */
2597 tiling_info->gfx9.num_pipes =
2598 adev->gfx.config.gb_addr_config_fields.num_pipes;
2599 tiling_info->gfx9.num_banks =
2600 adev->gfx.config.gb_addr_config_fields.num_banks;
2601 tiling_info->gfx9.pipe_interleave =
2602 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2603 tiling_info->gfx9.num_shader_engines =
2604 adev->gfx.config.gb_addr_config_fields.num_se;
2605 tiling_info->gfx9.max_compressed_frags =
2606 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2607 tiling_info->gfx9.num_rb_per_se =
2608 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2609 tiling_info->gfx9.swizzle =
2610 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2611 tiling_info->gfx9.shaderEnable = 1;
2612
2613 ret = fill_plane_dcc_attributes(adev, afb, plane_state, dcc,
2614 address, tiling_flags);
2615 if (ret)
2616 return ret;
2617 }
2618
2619 return 0;
7df7e505
NK		 2620}
2621
3ee6b26b
AD		 2622static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
2623 struct dc_plane_state *plane_state,
9817d5f5 2624 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 2625{
2626 uint64_t tiling_flags;
e7b07cee
HW		 2627 const struct drm_framebuffer *fb = &amdgpu_fb->base;
2628 int ret = 0;
2629 struct drm_format_name_buf format_name;
2630
2631 ret = get_fb_info(
2632 amdgpu_fb,
9817d5f5 2633 &tiling_flags);
e7b07cee
HW		 2634
2635 if (ret)
2636 return ret;
2637
2638 switch (fb->format->format) {
2639 case DRM_FORMAT_C8:
3be5262e 2640 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 2641 break;
2642 case DRM_FORMAT_RGB565:
3be5262e 2643 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 2644 break;
2645 case DRM_FORMAT_XRGB8888:
2646 case DRM_FORMAT_ARGB8888:
3be5262e 2647 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 2648 break;
2649 case DRM_FORMAT_XRGB2101010:
2650 case DRM_FORMAT_ARGB2101010:
3be5262e 2651 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 2652 break;
2653 case DRM_FORMAT_XBGR2101010:
2654 case DRM_FORMAT_ABGR2101010:
3be5262e 2655 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee 2656 break;
bcd47f60
MR		 2657 case DRM_FORMAT_XBGR8888:
2658 case DRM_FORMAT_ABGR8888:
2659 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2660 break;
e7b07cee 2661 case DRM_FORMAT_NV21:
3be5262e 2662 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 2663 break;
2664 case DRM_FORMAT_NV12:
3be5262e 2665 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 2666 break;
2667 default:
2668 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 2669 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 2670 return -EINVAL;
2671 }
2672
7df7e505 2673 memset(&plane_state->address, 0, sizeof(plane_state->address));
7df7e505 2674
3be5262e 2675 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3be5262e
HW		 2676 plane_state->plane_size.grph.surface_size.x = 0;
2677 plane_state->plane_size.grph.surface_size.y = 0;
2678 plane_state->plane_size.grph.surface_size.width = fb->width;
2679 plane_state->plane_size.grph.surface_size.height = fb->height;
2680 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 2681 fb->pitches[0] / fb->format->cpp[0];
2682 /* TODO: unhardcode */
3be5262e 2683 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 2684
2685 } else {
3be5262e
HW		 2686 plane_state->plane_size.video.luma_size.x = 0;
2687 plane_state->plane_size.video.luma_size.y = 0;
1791e54f 2688 plane_state->plane_size.video.luma_size.width = fb->width;
3be5262e 2689 plane_state->plane_size.video.luma_size.height = fb->height;
1791e54f
NK		 2690 plane_state->plane_size.video.luma_pitch =
2691 fb->pitches[0] / fb->format->cpp[0];
e7b07cee 2692
3be5262e
HW		 2693 plane_state->plane_size.video.chroma_size.x = 0;
2694 plane_state->plane_size.video.chroma_size.y = 0;
1791e54f
NK		 2695 /* TODO: set these based on surface format */
2696 plane_state->plane_size.video.chroma_size.width = fb->width / 2;
2697 plane_state->plane_size.video.chroma_size.height = fb->height / 2;
2698
2699 plane_state->plane_size.video.chroma_pitch =
2700 fb->pitches[1] / fb->format->cpp[1];
e7b07cee
HW		 2701
2702 /* TODO: unhardcode */
3be5262e 2703 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 2704 }
2705
09e5665a
NK		 2706 fill_plane_tiling_attributes(adev, amdgpu_fb, plane_state,
2707 &plane_state->tiling_info,
2708 &plane_state->dcc,
2709 &plane_state->address,
2710 tiling_flags);
e7b07cee 2711
3be5262e
HW		 2712 plane_state->visible = true;
2713 plane_state->scaling_quality.h_taps_c = 0;
2714 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 2715
3be5262e
HW		 2716 /* is this needed? is plane_state zeroed at allocation? */
2717 plane_state->scaling_quality.h_taps = 0;
2718 plane_state->scaling_quality.v_taps = 0;
2719 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 2720
2721 return ret;
2722
2723}
2724
d74004b6
NK		 2725static void
2726fill_blending_from_plane_state(struct drm_plane_state *plane_state,
2727 const struct dc_plane_state *dc_plane_state,
2728 bool *per_pixel_alpha, bool *global_alpha,
2729 int *global_alpha_value)
2730{
2731 *per_pixel_alpha = false;
2732 *global_alpha = false;
2733 *global_alpha_value = 0xff;
2734
2735 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
2736 return;
2737
2738 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
2739 static const uint32_t alpha_formats[] = {
2740 DRM_FORMAT_ARGB8888,
2741 DRM_FORMAT_RGBA8888,
2742 DRM_FORMAT_ABGR8888,
2743 };
2744 uint32_t format = plane_state->fb->format->format;
2745 unsigned int i;
2746
2747 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
2748 if (format == alpha_formats[i]) {
2749 *per_pixel_alpha = true;
2750 break;
2751 }
2752 }
2753 }
2754
2755 if (plane_state->alpha < 0xffff) {
2756 *global_alpha = true;
2757 *global_alpha_value = plane_state->alpha >> 8;
2758 }
2759}
2760
004fefa3
NK		 2761static int
2762fill_plane_color_attributes(const struct drm_plane_state *plane_state,
2763 const struct dc_plane_state *dc_plane_state,
2764 enum dc_color_space *color_space)
2765{
2766 bool full_range;
2767
2768 *color_space = COLOR_SPACE_SRGB;
2769
2770 /* DRM color properties only affect non-RGB formats. */
2771 if (dc_plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2772 return 0;
2773
2774 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
2775
2776 switch (plane_state->color_encoding) {
2777 case DRM_COLOR_YCBCR_BT601:
2778 if (full_range)
2779 *color_space = COLOR_SPACE_YCBCR601;
2780 else
2781 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
2782 break;
2783
2784 case DRM_COLOR_YCBCR_BT709:
2785 if (full_range)
2786 *color_space = COLOR_SPACE_YCBCR709;
2787 else
2788 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
2789 break;
2790
2791 case DRM_COLOR_YCBCR_BT2020:
2792 if (full_range)
2793 *color_space = COLOR_SPACE_2020_YCBCR;
2794 else
2795 return -EINVAL;
2796 break;
2797
2798 default:
2799 return -EINVAL;
2800 }
2801
2802 return 0;
2803}
2804
3ee6b26b
AD		 2805static int fill_plane_attributes(struct amdgpu_device *adev,
2806 struct dc_plane_state *dc_plane_state,
2807 struct drm_plane_state *plane_state,
9817d5f5 2808 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2809{
2810 const struct amdgpu_framebuffer *amdgpu_fb =
2811 to_amdgpu_framebuffer(plane_state->fb);
2812 const struct drm_crtc *crtc = plane_state->crtc;
e7b07cee
HW		 2813 int ret = 0;
2814
78171832
NK		 2815 if (!fill_rects_from_plane_state(plane_state,
2816 &dc_plane_state->src_rect,
2817 &dc_plane_state->dst_rect,
2818 &dc_plane_state->clip_rect,
2819 &dc_plane_state->rotation))
e7b07cee
HW		 2820 return -EINVAL;
2821
2822 ret = fill_plane_attributes_from_fb(
2823 crtc->dev->dev_private,
3be5262e 2824 dc_plane_state,
9817d5f5 2825 amdgpu_fb);
e7b07cee
HW		 2826
2827 if (ret)
2828 return ret;
2829
004fefa3
NK		 2830 ret = fill_plane_color_attributes(plane_state, dc_plane_state,
2831 &dc_plane_state->color_space);
2832 if (ret)
2833 return ret;
2834
e277adc5
LSL		 2835 /*
2836 * Always set input transfer function, since plane state is refreshed
2837 * every time.
2838 */
2839 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2840 if (ret) {
2841 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2842 dc_plane_state->in_transfer_func = NULL;
2843 }
e7b07cee 2844
d74004b6
NK		 2845 fill_blending_from_plane_state(plane_state, dc_plane_state,
2846 &dc_plane_state->per_pixel_alpha,
2847 &dc_plane_state->global_alpha,
2848 &dc_plane_state->global_alpha_value);
2849
e7b07cee
HW		 2850 return ret;
2851}
2852
3ee6b26b
AD		 2853static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2854 const struct dm_connector_state *dm_state,
2855 struct dc_stream_state *stream)
e7b07cee
HW		 2856{
2857 enum amdgpu_rmx_type rmx_type;
2858
2859 struct rect src = { 0 }; /* viewport in composition space*/
2860 struct rect dst = { 0 }; /* stream addressable area */
2861
2862 /* no mode. nothing to be done */
2863 if (!mode)
2864 return;
2865
2866 /* Full screen scaling by default */
2867 src.width = mode->hdisplay;
2868 src.height = mode->vdisplay;
2869 dst.width = stream->timing.h_addressable;
2870 dst.height = stream->timing.v_addressable;
2871
f4791779
HW		 2872 if (dm_state) {
2873 rmx_type = dm_state->scaling;
2874 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2875 if (src.width * dst.height <
2876 src.height * dst.width) {
2877 /* height needs less upscaling/more downscaling */
2878 dst.width = src.width *
2879 dst.height / src.height;
2880 } else {
2881 /* width needs less upscaling/more downscaling */
2882 dst.height = src.height *
2883 dst.width / src.width;
2884 }
2885 } else if (rmx_type == RMX_CENTER) {
2886 dst = src;
e7b07cee 2887 }
e7b07cee 2888
f4791779
HW		 2889 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2890 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2891
f4791779
HW		 2892 if (dm_state->underscan_enable) {
2893 dst.x += dm_state->underscan_hborder / 2;
2894 dst.y += dm_state->underscan_vborder / 2;
2895 dst.width -= dm_state->underscan_hborder;
2896 dst.height -= dm_state->underscan_vborder;
2897 }
e7b07cee
HW		 2898 }
2899
2900 stream->src = src;
2901 stream->dst = dst;
2902
f1ad2f5e 2903 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2904 dst.x, dst.y, dst.width, dst.height);
2905
2906}
2907
3ee6b26b
AD		 2908static enum dc_color_depth
2909convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee 2910{
07e3a1cf
NK		 2911 struct dm_connector_state *dm_conn_state =
2912 to_dm_connector_state(connector->state);
e7b07cee
HW		 2913 uint32_t bpc = connector->display_info.bpc;
2914
07e3a1cf
NK		 2915 /* TODO: Remove this when there's support for max_bpc in drm */
2916 if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2917 /* Round down to nearest even number. */
2918 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2919
e7b07cee
HW		 2920 switch (bpc) {
2921 case 0:
1f6010a9
DF		 2922 /*
2923 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 2924 * EDID revision before 1.4
2925 * TODO: Fix edid parsing
2926 */
2927 return COLOR_DEPTH_888;
2928 case 6:
2929 return COLOR_DEPTH_666;
2930 case 8:
2931 return COLOR_DEPTH_888;
2932 case 10:
2933 return COLOR_DEPTH_101010;
2934 case 12:
2935 return COLOR_DEPTH_121212;
2936 case 14:
2937 return COLOR_DEPTH_141414;
2938 case 16:
2939 return COLOR_DEPTH_161616;
2940 default:
2941 return COLOR_DEPTH_UNDEFINED;
2942 }
2943}
2944
3ee6b26b
AD		 2945static enum dc_aspect_ratio
2946get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 2947{
e11d4147
LSL		 2948 /* 1-1 mapping, since both enums follow the HDMI spec. */
2949 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 2950}
2951
3ee6b26b
AD		 2952static enum dc_color_space
2953get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2954{
2955 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2956
2957 switch (dc_crtc_timing->pixel_encoding) {
2958 case PIXEL_ENCODING_YCBCR422:
2959 case PIXEL_ENCODING_YCBCR444:
2960 case PIXEL_ENCODING_YCBCR420:
2961 {
2962 /*
2963 * 27030khz is the separation point between HDTV and SDTV
2964 * according to HDMI spec, we use YCbCr709 and YCbCr601
2965 * respectively
2966 */
380604e2 2967 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 2968 if (dc_crtc_timing->flags.Y_ONLY)
2969 color_space =
2970 COLOR_SPACE_YCBCR709_LIMITED;
2971 else
2972 color_space = COLOR_SPACE_YCBCR709;
2973 } else {
2974 if (dc_crtc_timing->flags.Y_ONLY)
2975 color_space =
2976 COLOR_SPACE_YCBCR601_LIMITED;
2977 else
2978 color_space = COLOR_SPACE_YCBCR601;
2979 }
2980
2981 }
2982 break;
2983 case PIXEL_ENCODING_RGB:
2984 color_space = COLOR_SPACE_SRGB;
2985 break;
2986
2987 default:
2988 WARN_ON(1);
2989 break;
2990 }
2991
2992 return color_space;
2993}
2994
400443e8
ML		 2995static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2996{
2997 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2998 return;
2999
3000 timing_out->display_color_depth--;
3001}
3002
3003static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
3004 const struct drm_display_info *info)
3005{
3006 int normalized_clk;
3007 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3008 return;
3009 do {
380604e2 3010 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 3011 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3012 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3013 normalized_clk /= 2;
3014 /* Adjusting pix clock following on HDMI spec based on colour depth */
3015 switch (timing_out->display_color_depth) {
3016 case COLOR_DEPTH_101010:
3017 normalized_clk = (normalized_clk * 30) / 24;
3018 break;
3019 case COLOR_DEPTH_121212:
3020 normalized_clk = (normalized_clk * 36) / 24;
3021 break;
3022 case COLOR_DEPTH_161616:
3023 normalized_clk = (normalized_clk * 48) / 24;
3024 break;
3025 default:
3026 return;
3027 }
3028 if (normalized_clk <= info->max_tmds_clock)
3029 return;
3030 reduce_mode_colour_depth(timing_out);
3031
3032 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
3033
3034}
e7b07cee 3035
3ee6b26b
AD		 3036static void
3037fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
3038 const struct drm_display_mode *mode_in,
b333730d
BL		 3039 const struct drm_connector *connector,
3040 const struct dc_stream_state *old_stream)
e7b07cee
HW		 3041{
3042 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 3043 const struct drm_display_info *info = &connector->display_info;
b830ebc9 3044
e7b07cee
HW		 3045 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
3046
3047 timing_out->h_border_left = 0;
3048 timing_out->h_border_right = 0;
3049 timing_out->v_border_top = 0;
3050 timing_out->v_border_bottom = 0;
3051 /* TODO: un-hardcode */
fe61a2f1 3052 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 3053 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1
ML		 3054 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3055 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
ceb3dbb4 3056 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 3057 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3058 else
3059 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3060
3061 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3062 timing_out->display_color_depth = convert_color_depth_from_display_info(
3063 connector);
3064 timing_out->scan_type = SCANNING_TYPE_NODATA;
3065 timing_out->hdmi_vic = 0;
b333730d
BL		 3066
3067 if(old_stream) {
3068 timing_out->vic = old_stream->timing.vic;
3069 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3070 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3071 } else {
3072 timing_out->vic = drm_match_cea_mode(mode_in);
3073 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3074 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3075 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3076 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3077 }
e7b07cee
HW		 3078
3079 timing_out->h_addressable = mode_in->crtc_hdisplay;
3080 timing_out->h_total = mode_in->crtc_htotal;
3081 timing_out->h_sync_width =
3082 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3083 timing_out->h_front_porch =
3084 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3085 timing_out->v_total = mode_in->crtc_vtotal;
3086 timing_out->v_addressable = mode_in->crtc_vdisplay;
3087 timing_out->v_front_porch =
3088 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3089 timing_out->v_sync_width =
3090 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
380604e2 3091 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
e7b07cee 3092 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 3093
3094 stream->output_color_space = get_output_color_space(timing_out);
3095
e43a432c
AK		 3096 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3097 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ceb3dbb4 3098 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
400443e8 3099 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 3100}
3101
3ee6b26b
AD		 3102static void fill_audio_info(struct audio_info *audio_info,
3103 const struct drm_connector *drm_connector,
3104 const struct dc_sink *dc_sink)
e7b07cee
HW		 3105{
3106 int i = 0;
3107 int cea_revision = 0;
3108 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3109
3110 audio_info->manufacture_id = edid_caps->manufacturer_id;
3111 audio_info->product_id = edid_caps->product_id;
3112
3113 cea_revision = drm_connector->display_info.cea_rev;
3114
090afc1e 3115 strscpy(audio_info->display_name,
d2b2562c 3116 edid_caps->display_name,
090afc1e 3117 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 3118
b830ebc9 3119 if (cea_revision >= 3) {
e7b07cee
HW		 3120 audio_info->mode_count = edid_caps->audio_mode_count;
3121
3122 for (i = 0; i < audio_info->mode_count; ++i) {
3123 audio_info->modes[i].format_code =
3124 (enum audio_format_code)
3125 (edid_caps->audio_modes[i].format_code);
3126 audio_info->modes[i].channel_count =
3127 edid_caps->audio_modes[i].channel_count;
3128 audio_info->modes[i].sample_rates.all =
3129 edid_caps->audio_modes[i].sample_rate;
3130 audio_info->modes[i].sample_size =
3131 edid_caps->audio_modes[i].sample_size;
3132 }
3133 }
3134
3135 audio_info->flags.all = edid_caps->speaker_flags;
3136
3137 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 3138 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 3139 audio_info->video_latency = drm_connector->video_latency[0];
3140 audio_info->audio_latency = drm_connector->audio_latency[0];
3141 }
3142
3143 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3144
3145}
3146
3ee6b26b
AD		 3147static void
3148copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3149 struct drm_display_mode *dst_mode)
e7b07cee
HW		 3150{
3151 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3152 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3153 dst_mode->crtc_clock = src_mode->crtc_clock;
3154 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3155 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 3156 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 3157 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3158 dst_mode->crtc_htotal = src_mode->crtc_htotal;
3159 dst_mode->crtc_hskew = src_mode->crtc_hskew;
3160 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3161 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3162 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3163 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3164 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3165}
3166
3ee6b26b
AD		 3167static void
3168decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3169 const struct drm_display_mode *native_mode,
3170 bool scale_enabled)
e7b07cee
HW		 3171{
3172 if (scale_enabled) {
3173 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3174 } else if (native_mode->clock == drm_mode->clock &&
3175 native_mode->htotal == drm_mode->htotal &&
3176 native_mode->vtotal == drm_mode->vtotal) {
3177 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3178 } else {
3179 /* no scaling nor amdgpu inserted, no need to patch */
3180 }
3181}
3182
aed15309
ML		 3183static struct dc_sink *
3184create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 3185{
2e0ac3d6 3186 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 3187 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 3188 sink_init_data.link = aconnector->dc_link;
3189 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3190
3191 sink = dc_sink_create(&sink_init_data);
423788c7 3192 if (!sink) {
2e0ac3d6 3193 DRM_ERROR("Failed to create sink!\n");
aed15309 3194 return NULL;
423788c7 3195 }
2e0ac3d6 3196 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 3197
aed15309 3198 return sink;
2e0ac3d6
HW		 3199}
3200
fa2123db
ML		 3201static void set_multisync_trigger_params(
3202 struct dc_stream_state *stream)
3203{
3204 if (stream->triggered_crtc_reset.enabled) {
3205 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3206 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3207 }
3208}
3209
3210static void set_master_stream(struct dc_stream_state *stream_set[],
3211 int stream_count)
3212{
3213 int j, highest_rfr = 0, master_stream = 0;
3214
3215 for (j = 0; j < stream_count; j++) {
3216 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3217 int refresh_rate = 0;
3218
380604e2 3219 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 3220 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3221 if (refresh_rate > highest_rfr) {
3222 highest_rfr = refresh_rate;
3223 master_stream = j;
3224 }
3225 }
3226 }
3227 for (j = 0; j < stream_count; j++) {
03736f4c 3228 if (stream_set[j])
fa2123db
ML		 3229 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3230 }
3231}
3232
3233static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3234{
3235 int i = 0;
3236
3237 if (context->stream_count < 2)
3238 return;
3239 for (i = 0; i < context->stream_count ; i++) {
3240 if (!context->streams[i])
3241 continue;
1f6010a9
DF		 3242 /*
3243 * TODO: add a function to read AMD VSDB bits and set
fa2123db 3244 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 3245 * For now it's set to false
fa2123db
ML		 3246 */
3247 set_multisync_trigger_params(context->streams[i]);
3248 }
3249 set_master_stream(context->streams, context->stream_count);
3250}
3251
3ee6b26b
AD		 3252static struct dc_stream_state *
3253create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3254 const struct drm_display_mode *drm_mode,
b333730d
BL		 3255 const struct dm_connector_state *dm_state,
3256 const struct dc_stream_state *old_stream)
e7b07cee
HW		 3257{
3258 struct drm_display_mode *preferred_mode = NULL;
391ef035 3259 struct drm_connector *drm_connector;
0971c40e 3260 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 3261 struct drm_display_mode mode = *drm_mode;
3262 bool native_mode_found = false;
b333730d
BL		 3263 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3264 int mode_refresh;
58124bf8 3265 int preferred_refresh = 0;
b333730d 3266
aed15309 3267 struct dc_sink *sink = NULL;
b830ebc9 3268 if (aconnector == NULL) {
e7b07cee 3269 DRM_ERROR("aconnector is NULL!\n");
64245fa7 3270 return stream;
e7b07cee
HW		 3271 }
3272
e7b07cee 3273 drm_connector = &aconnector->base;
2e0ac3d6 3274
f4ac176e 3275 if (!aconnector->dc_sink) {
e3fa5c4c
JFZ		 3276 sink = create_fake_sink(aconnector);
3277 if (!sink)
3278 return stream;
aed15309
ML		 3279 } else {
3280 sink = aconnector->dc_sink;
dcd5fb82 3281 dc_sink_retain(sink);
f4ac176e 3282 }
2e0ac3d6 3283
aed15309 3284 stream = dc_create_stream_for_sink(sink);
4562236b 3285
b830ebc9 3286 if (stream == NULL) {
e7b07cee 3287 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 3288 goto finish;
e7b07cee
HW		 3289 }
3290
ceb3dbb4
JL		 3291 stream->dm_stream_context = aconnector;
3292
e7b07cee
HW		 3293 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3294 /* Search for preferred mode */
3295 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3296 native_mode_found = true;
3297 break;
3298 }
3299 }
3300 if (!native_mode_found)
3301 preferred_mode = list_first_entry_or_null(
3302 &aconnector->base.modes,
3303 struct drm_display_mode,
3304 head);
3305
b333730d
BL		 3306 mode_refresh = drm_mode_vrefresh(&mode);
3307
b830ebc9 3308 if (preferred_mode == NULL) {
1f6010a9
DF		 3309 /*
3310 * This may not be an error, the use case is when we have no
e7b07cee
HW		 3311 * usermode calls to reset and set mode upon hotplug. In this
3312 * case, we call set mode ourselves to restore the previous mode
3313 * and the modelist may not be filled in in time.
3314 */
f1ad2f5e 3315 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 3316 } else {
3317 decide_crtc_timing_for_drm_display_mode(
3318 &mode, preferred_mode,
f4791779 3319 dm_state ? (dm_state->scaling != RMX_OFF) : false);
58124bf8 3320 preferred_refresh = drm_mode_vrefresh(preferred_mode);
e7b07cee
HW		 3321 }
3322
f783577c
JFZ		 3323 if (!dm_state)
3324 drm_mode_set_crtcinfo(&mode, 0);
3325
b333730d
BL		 3326 /*
3327 * If scaling is enabled and refresh rate didn't change
3328 * we copy the vic and polarities of the old timings
3329 */
3330 if (!scale || mode_refresh != preferred_refresh)
3331 fill_stream_properties_from_drm_display_mode(stream,
3332 &mode, &aconnector->base, NULL);
3333 else
3334 fill_stream_properties_from_drm_display_mode(stream,
3335 &mode, &aconnector->base, old_stream);
3336
e7b07cee
HW		 3337 update_stream_scaling_settings(&mode, dm_state, stream);
3338
3339 fill_audio_info(
3340 &stream->audio_info,
3341 drm_connector,
aed15309 3342 sink);
e7b07cee 3343
ceb3dbb4 3344 update_stream_signal(stream, sink);
9182b4cb 3345
aed15309 3346finish:
dcd5fb82 3347 dc_sink_release(sink);
9e3efe3e 3348
e7b07cee
HW		 3349 return stream;
3350}
3351
7578ecda 3352static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 3353{
3354 drm_crtc_cleanup(crtc);
3355 kfree(crtc);
3356}
3357
3358static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 3359 struct drm_crtc_state *state)
e7b07cee
HW		 3360{
3361 struct dm_crtc_state *cur = to_dm_crtc_state(state);
3362
3363 /* TODO Destroy dc_stream objects are stream object is flattened */
3364 if (cur->stream)
3365 dc_stream_release(cur->stream);
3366
3367
3368 __drm_atomic_helper_crtc_destroy_state(state);
3369
3370
3371 kfree(state);
3372}
3373
3374static void dm_crtc_reset_state(struct drm_crtc *crtc)
3375{
3376 struct dm_crtc_state *state;
3377
3378 if (crtc->state)
3379 dm_crtc_destroy_state(crtc, crtc->state);
3380
3381 state = kzalloc(sizeof(*state), GFP_KERNEL);
3382 if (WARN_ON(!state))
3383 return;
3384
3385 crtc->state = &state->base;
3386 crtc->state->crtc = crtc;
3387
3388}
3389
3390static struct drm_crtc_state *
3391dm_crtc_duplicate_state(struct drm_crtc *crtc)
3392{
3393 struct dm_crtc_state *state, *cur;
3394
3395 cur = to_dm_crtc_state(crtc->state);
3396
3397 if (WARN_ON(!crtc->state))
3398 return NULL;
3399
2004f45e 3400 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 3401 if (!state)
3402 return NULL;
e7b07cee
HW		 3403
3404 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3405
3406 if (cur->stream) {
3407 state->stream = cur->stream;
3408 dc_stream_retain(state->stream);
3409 }
3410
180db303 3411 state->vrr_params = cur->vrr_params;
98e6436d 3412 state->vrr_infopacket = cur->vrr_infopacket;
c1ee92f9 3413 state->abm_level = cur->abm_level;
bb47de73
NK		 3414 state->vrr_supported = cur->vrr_supported;
3415 state->freesync_config = cur->freesync_config;
ed20dc0d 3416 state->crc_enabled = cur->crc_enabled;
98e6436d 3417
e7b07cee
HW		 3418 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3419
3420 return &state->base;
3421}
3422
d2574c33
MK		 3423static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
3424{
3425 enum dc_irq_source irq_source;
3426 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3427 struct amdgpu_device *adev = crtc->dev->dev_private;
3428 int rc;
3429
3430 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
3431
3432 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3433
3434 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
3435 acrtc->crtc_id, enable ? "en" : "dis", rc);
3436 return rc;
3437}
589d2739
HW		 3438
3439static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3440{
3441 enum dc_irq_source irq_source;
3442 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3443 struct amdgpu_device *adev = crtc->dev->dev_private;
d2574c33
MK		 3444 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3445 int rc = 0;
3446
3447 if (enable) {
3448 /* vblank irq on -> Only need vupdate irq in vrr mode */
3449 if (amdgpu_dm_vrr_active(acrtc_state))
3450 rc = dm_set_vupdate_irq(crtc, true);
3451 } else {
3452 /* vblank irq off -> vupdate irq off */
3453 rc = dm_set_vupdate_irq(crtc, false);
3454 }
3455
3456 if (rc)
3457 return rc;
589d2739
HW		 3458
3459 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 3460 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 3461}
3462
3463static int dm_enable_vblank(struct drm_crtc *crtc)
3464{
3465 return dm_set_vblank(crtc, true);
3466}
3467
3468static void dm_disable_vblank(struct drm_crtc *crtc)
3469{
3470 dm_set_vblank(crtc, false);
3471}
3472
e7b07cee
HW		 3473/* Implemented only the options currently availible for the driver */
3474static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3475 .reset = dm_crtc_reset_state,
3476 .destroy = amdgpu_dm_crtc_destroy,
3477 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3478 .set_config = drm_atomic_helper_set_config,
3479 .page_flip = drm_atomic_helper_page_flip,
3480 .atomic_duplicate_state = dm_crtc_duplicate_state,
3481 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 3482 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 3483 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
589d2739
HW		 3484 .enable_vblank = dm_enable_vblank,
3485 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 3486};
3487
3488static enum drm_connector_status
3489amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3490{
3491 bool connected;
c84dec2f 3492 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 3493
1f6010a9
DF		 3494 /*
3495 * Notes:
e7b07cee
HW		 3496 * 1. This interface is NOT called in context of HPD irq.
3497 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 3498 * makes it a bad place for *any* MST-related activity.
3499 */
e7b07cee 3500
8580d60b
HW		 3501 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3502 !aconnector->fake_enable)
e7b07cee
HW		 3503 connected = (aconnector->dc_sink != NULL);
3504 else
3505 connected = (aconnector->base.force == DRM_FORCE_ON);
3506
3507 return (connected ? connector_status_connected :
3508 connector_status_disconnected);
3509}
3510
3ee6b26b
AD		 3511int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3512 struct drm_connector_state *connector_state,
3513 struct drm_property *property,
3514 uint64_t val)
e7b07cee
HW		 3515{
3516 struct drm_device *dev = connector->dev;
3517 struct amdgpu_device *adev = dev->dev_private;
3518 struct dm_connector_state *dm_old_state =
3519 to_dm_connector_state(connector->state);
3520 struct dm_connector_state *dm_new_state =
3521 to_dm_connector_state(connector_state);
3522
3523 int ret = -EINVAL;
3524
3525 if (property == dev->mode_config.scaling_mode_property) {
3526 enum amdgpu_rmx_type rmx_type;
3527
3528 switch (val) {
3529 case DRM_MODE_SCALE_CENTER:
3530 rmx_type = RMX_CENTER;
3531 break;
3532 case DRM_MODE_SCALE_ASPECT:
3533 rmx_type = RMX_ASPECT;
3534 break;
3535 case DRM_MODE_SCALE_FULLSCREEN:
3536 rmx_type = RMX_FULL;
3537 break;
3538 case DRM_MODE_SCALE_NONE:
3539 default:
3540 rmx_type = RMX_OFF;
3541 break;
3542 }
3543
3544 if (dm_old_state->scaling == rmx_type)
3545 return 0;
3546
3547 dm_new_state->scaling = rmx_type;
3548 ret = 0;
3549 } else if (property == adev->mode_info.underscan_hborder_property) {
3550 dm_new_state->underscan_hborder = val;
3551 ret = 0;
3552 } else if (property == adev->mode_info.underscan_vborder_property) {
3553 dm_new_state->underscan_vborder = val;
3554 ret = 0;
3555 } else if (property == adev->mode_info.underscan_property) {
3556 dm_new_state->underscan_enable = val;
3557 ret = 0;
07e3a1cf
NK		 3558 } else if (property == adev->mode_info.max_bpc_property) {
3559 dm_new_state->max_bpc = val;
3560 ret = 0;
c1ee92f9
DF		 3561 } else if (property == adev->mode_info.abm_level_property) {
3562 dm_new_state->abm_level = val;
3563 ret = 0;
e7b07cee
HW		 3564 }
3565
3566 return ret;
3567}
3568
3ee6b26b
AD		 3569int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3570 const struct drm_connector_state *state,
3571 struct drm_property *property,
3572 uint64_t *val)
e7b07cee
HW		 3573{
3574 struct drm_device *dev = connector->dev;
3575 struct amdgpu_device *adev = dev->dev_private;
3576 struct dm_connector_state *dm_state =
3577 to_dm_connector_state(state);
3578 int ret = -EINVAL;
3579
3580 if (property == dev->mode_config.scaling_mode_property) {
3581 switch (dm_state->scaling) {
3582 case RMX_CENTER:
3583 *val = DRM_MODE_SCALE_CENTER;
3584 break;
3585 case RMX_ASPECT:
3586 *val = DRM_MODE_SCALE_ASPECT;
3587 break;
3588 case RMX_FULL:
3589 *val = DRM_MODE_SCALE_FULLSCREEN;
3590 break;
3591 case RMX_OFF:
3592 default:
3593 *val = DRM_MODE_SCALE_NONE;
3594 break;
3595 }
3596 ret = 0;
3597 } else if (property == adev->mode_info.underscan_hborder_property) {
3598 *val = dm_state->underscan_hborder;
3599 ret = 0;
3600 } else if (property == adev->mode_info.underscan_vborder_property) {
3601 *val = dm_state->underscan_vborder;
3602 ret = 0;
3603 } else if (property == adev->mode_info.underscan_property) {
3604 *val = dm_state->underscan_enable;
3605 ret = 0;
07e3a1cf
NK		 3606 } else if (property == adev->mode_info.max_bpc_property) {
3607 *val = dm_state->max_bpc;
3608 ret = 0;
c1ee92f9
DF		 3609 } else if (property == adev->mode_info.abm_level_property) {
3610 *val = dm_state->abm_level;
3611 ret = 0;
e7b07cee 3612 }
c1ee92f9 3613
e7b07cee
HW		 3614 return ret;
3615}
3616
7578ecda 3617static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 3618{
c84dec2f 3619 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3620 const struct dc_link *link = aconnector->dc_link;
3621 struct amdgpu_device *adev = connector->dev->dev_private;
3622 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 3623
e7b07cee
HW		 3624#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3625 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3626
89fc8d4e 3627 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 3628 link->type != dc_connection_none &&
3629 dm->backlight_dev) {
3630 backlight_device_unregister(dm->backlight_dev);
3631 dm->backlight_dev = NULL;
e7b07cee
HW		 3632 }
3633#endif
dcd5fb82
MF		 3634
3635 if (aconnector->dc_em_sink)
3636 dc_sink_release(aconnector->dc_em_sink);
3637 aconnector->dc_em_sink = NULL;
3638 if (aconnector->dc_sink)
3639 dc_sink_release(aconnector->dc_sink);
3640 aconnector->dc_sink = NULL;
3641
e86e8947 3642 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 3643 drm_connector_unregister(connector);
3644 drm_connector_cleanup(connector);
3645 kfree(connector);
3646}
3647
3648void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3649{
3650 struct dm_connector_state *state =
3651 to_dm_connector_state(connector->state);
3652
df099b9b
LSL		 3653 if (connector->state)
3654 __drm_atomic_helper_connector_destroy_state(connector->state);
3655
e7b07cee
HW		 3656 kfree(state);
3657
3658 state = kzalloc(sizeof(*state), GFP_KERNEL);
3659
3660 if (state) {
3661 state->scaling = RMX_OFF;
3662 state->underscan_enable = false;
3663 state->underscan_hborder = 0;
3664 state->underscan_vborder = 0;
49f1c44b 3665 state->max_bpc = 8;
e7b07cee 3666
df099b9b 3667 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 3668 }
3669}
3670
3ee6b26b
AD		 3671struct drm_connector_state *
3672amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 3673{
3674 struct dm_connector_state *state =
3675 to_dm_connector_state(connector->state);
3676
3677 struct dm_connector_state *new_state =
3678 kmemdup(state, sizeof(*state), GFP_KERNEL);
3679
98e6436d
AK		 3680 if (!new_state)
3681 return NULL;
e7b07cee 3682
98e6436d
AK		 3683 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3684
3685 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 3686 new_state->abm_level = state->abm_level;
922454c2
NK		 3687 new_state->scaling = state->scaling;
3688 new_state->underscan_enable = state->underscan_enable;
3689 new_state->underscan_hborder = state->underscan_hborder;
3690 new_state->underscan_vborder = state->underscan_vborder;
49f1c44b 3691 new_state->max_bpc = state->max_bpc;
98e6436d
AK		 3692
3693 return &new_state->base;
e7b07cee
HW		 3694}
3695
3696static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3697 .reset = amdgpu_dm_connector_funcs_reset,
3698 .detect = amdgpu_dm_connector_detect,
3699 .fill_modes = drm_helper_probe_single_connector_modes,
3700 .destroy = amdgpu_dm_connector_destroy,
3701 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3702 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3703 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3704 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3705};
3706
e7b07cee
HW		 3707static int get_modes(struct drm_connector *connector)
3708{
3709 return amdgpu_dm_connector_get_modes(connector);
3710}
3711
c84dec2f 3712static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3713{
3714 struct dc_sink_init_data init_params = {
3715 .link = aconnector->dc_link,
3716 .sink_signal = SIGNAL_TYPE_VIRTUAL
3717 };
70e8ffc5 3718 struct edid *edid;
e7b07cee 3719
a89ff457 3720 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 3721 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3722 aconnector->base.name);
3723
3724 aconnector->base.force = DRM_FORCE_OFF;
3725 aconnector->base.override_edid = false;
3726 return;
3727 }
3728
70e8ffc5
HW		 3729 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3730
e7b07cee
HW		 3731 aconnector->edid = edid;
3732
3733 aconnector->dc_em_sink = dc_link_add_remote_sink(
3734 aconnector->dc_link,
3735 (uint8_t *)edid,
3736 (edid->extensions + 1) * EDID_LENGTH,
3737 &init_params);
3738
dcd5fb82 3739 if (aconnector->base.force == DRM_FORCE_ON) {
e7b07cee
HW		 3740 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3741 aconnector->dc_link->local_sink :
3742 aconnector->dc_em_sink;
dcd5fb82
MF		 3743 dc_sink_retain(aconnector->dc_sink);
3744 }
e7b07cee
HW		 3745}
3746
c84dec2f 3747static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3748{
3749 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3750
1f6010a9
DF		 3751 /*
3752 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 3753 * Those settings have to be != 0 to get initial modeset
3754 */
3755 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3756 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3757 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3758 }
3759
3760
3761 aconnector->base.override_edid = true;
3762 create_eml_sink(aconnector);
3763}
3764
ba9ca088 3765enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 3766 struct drm_display_mode *mode)
e7b07cee
HW		 3767{
3768 int result = MODE_ERROR;
3769 struct dc_sink *dc_sink;
3770 struct amdgpu_device *adev = connector->dev->dev_private;
3771 /* TODO: Unhardcode stream count */
0971c40e 3772 struct dc_stream_state *stream;
c84dec2f 3773 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 3774 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 3775
3776 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3777 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3778 return result;
3779
1f6010a9
DF		 3780 /*
3781 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 3782 * EDID mgmt
3783 */
3784 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3785 !aconnector->dc_em_sink)
3786 handle_edid_mgmt(aconnector);
3787
c84dec2f 3788 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 3789
b830ebc9 3790 if (dc_sink == NULL) {
e7b07cee
HW		 3791 DRM_ERROR("dc_sink is NULL!\n");
3792 goto fail;
3793 }
3794
b333730d 3795 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
b830ebc9 3796 if (stream == NULL) {
e7b07cee
HW		 3797 DRM_ERROR("Failed to create stream for sink!\n");
3798 goto fail;
3799 }
3800
a39438f0
HW		 3801 dc_result = dc_validate_stream(adev->dm.dc, stream);
3802
3803 if (dc_result == DC_OK)
e7b07cee 3804 result = MODE_OK;
a39438f0 3805 else
9f921b14 3806 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 3807 mode->vdisplay,
3808 mode->hdisplay,
9f921b14
HW		 3809 mode->clock,
3810 dc_result);
e7b07cee
HW		 3811
3812 dc_stream_release(stream);
3813
3814fail:
3815 /* TODO: error handling*/
3816 return result;
3817}
3818
3819static const struct drm_connector_helper_funcs
3820amdgpu_dm_connector_helper_funcs = {
3821 /*
1f6010a9 3822 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 3823 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 3824 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 3825 * in get_modes call back, not just return the modes count
3826 */
e7b07cee
HW		 3827 .get_modes = get_modes,
3828 .mode_valid = amdgpu_dm_connector_mode_valid,
e7b07cee
HW		 3829};
3830
3831static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3832{
3833}
3834
3ee6b26b
AD		 3835static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3836 struct drm_crtc_state *state)
e7b07cee
HW		 3837{
3838 struct amdgpu_device *adev = crtc->dev->dev_private;
3839 struct dc *dc = adev->dm.dc;
3840 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3841 int ret = -EINVAL;
3842
9b690ef3
BL		 3843 if (unlikely(!dm_crtc_state->stream &&
3844 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 3845 WARN_ON(1);
3846 return ret;
3847 }
3848
1f6010a9 3849 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 3850 if (!dm_crtc_state->stream)
3851 return 0;
3852
62c933f9 3853 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 3854 return 0;
3855
3856 return ret;
3857}
3858
3ee6b26b
AD		 3859static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3860 const struct drm_display_mode *mode,
3861 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 3862{
3863 return true;
3864}
3865
3866static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3867 .disable = dm_crtc_helper_disable,
3868 .atomic_check = dm_crtc_helper_atomic_check,
3869 .mode_fixup = dm_crtc_helper_mode_fixup
3870};
3871
3872static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3873{
3874
3875}
3876
3ee6b26b
AD		 3877static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3878 struct drm_crtc_state *crtc_state,
3879 struct drm_connector_state *conn_state)
e7b07cee
HW		 3880{
3881 return 0;
3882}
3883
3884const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3885 .disable = dm_encoder_helper_disable,
3886 .atomic_check = dm_encoder_helper_atomic_check
3887};
3888
3889static void dm_drm_plane_reset(struct drm_plane *plane)
3890{
3891 struct dm_plane_state *amdgpu_state = NULL;
3892
3893 if (plane->state)
3894 plane->funcs->atomic_destroy_state(plane, plane->state);
3895
3896 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 3897 WARN_ON(amdgpu_state == NULL);
1f6010a9 3898
7ddaef96
NK		 3899 if (amdgpu_state)
3900 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
e7b07cee
HW		 3901}
3902
3903static struct drm_plane_state *
3904dm_drm_plane_duplicate_state(struct drm_plane *plane)
3905{
3906 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3907
3908 old_dm_plane_state = to_dm_plane_state(plane->state);
3909 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3910 if (!dm_plane_state)
3911 return NULL;
3912
3913 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3914
3be5262e
HW		 3915 if (old_dm_plane_state->dc_state) {
3916 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3917 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 3918 }
3919
3920 return &dm_plane_state->base;
3921}
3922
3923void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 3924 struct drm_plane_state *state)
e7b07cee
HW		 3925{
3926 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3927
3be5262e
HW		 3928 if (dm_plane_state->dc_state)
3929 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 3930
0627bbd3 3931 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 3932}
3933
3934static const struct drm_plane_funcs dm_plane_funcs = {
3935 .update_plane = drm_atomic_helper_update_plane,
3936 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 3937 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 3938 .reset = dm_drm_plane_reset,
3939 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3940 .atomic_destroy_state = dm_drm_plane_destroy_state,
3941};
3942
3ee6b26b
AD		 3943static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3944 struct drm_plane_state *new_state)
e7b07cee
HW		 3945{
3946 struct amdgpu_framebuffer *afb;
3947 struct drm_gem_object *obj;
5d43be0c 3948 struct amdgpu_device *adev;
e7b07cee 3949 struct amdgpu_bo *rbo;
e7b07cee 3950 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
e0634e8d 3951 uint64_t tiling_flags;
5d43be0c
CK		 3952 uint32_t domain;
3953 int r;
e7b07cee
HW		 3954
3955 dm_plane_state_old = to_dm_plane_state(plane->state);
3956 dm_plane_state_new = to_dm_plane_state(new_state);
3957
3958 if (!new_state->fb) {
f1ad2f5e 3959 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3960 return 0;
3961 }
3962
3963 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 3964 obj = new_state->fb->obj[0];
e7b07cee 3965 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3966 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3967 r = amdgpu_bo_reserve(rbo, false);
3968 if (unlikely(r != 0))
3969 return r;
3970
5d43be0c 3971 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 3972 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 3973 else
3974 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3975
7b7c6c81 3976 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 3977 if (unlikely(r != 0)) {
30b7c614
HW		 3978 if (r != -ERESTARTSYS)
3979 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
bb812f1e 3980 amdgpu_bo_unreserve(rbo);
e7b07cee
HW		 3981 return r;
3982 }
3983
bb812f1e
JZ		 3984 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3985 if (unlikely(r != 0)) {
3986 amdgpu_bo_unpin(rbo);
3987 amdgpu_bo_unreserve(rbo);
3988 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 3989 return r;
3990 }
7df7e505
NK		 3991
3992 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
3993
bb812f1e
JZ		 3994 amdgpu_bo_unreserve(rbo);
3995
7b7c6c81 3996 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 3997
3998 amdgpu_bo_ref(rbo);
3999
3be5262e
HW		 4000 if (dm_plane_state_new->dc_state &&
4001 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
4002 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 4003
e0634e8d
NK		 4004 fill_plane_tiling_attributes(
4005 adev, afb, plane_state, &plane_state->tiling_info,
4006 &plane_state->dcc, &plane_state->address, tiling_flags);
e7b07cee
HW		 4007 }
4008
e7b07cee
HW		 4009 return 0;
4010}
4011
3ee6b26b
AD		 4012static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
4013 struct drm_plane_state *old_state)
e7b07cee
HW		 4014{
4015 struct amdgpu_bo *rbo;
e7b07cee
HW		 4016 int r;
4017
4018 if (!old_state->fb)
4019 return;
4020
e68d14dd 4021 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 4022 r = amdgpu_bo_reserve(rbo, false);
4023 if (unlikely(r)) {
4024 DRM_ERROR("failed to reserve rbo before unpin\n");
4025 return;
b830ebc9
HW		 4026 }
4027
4028 amdgpu_bo_unpin(rbo);
4029 amdgpu_bo_unreserve(rbo);
4030 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 4031}
4032
7578ecda
AD		 4033static int dm_plane_atomic_check(struct drm_plane *plane,
4034 struct drm_plane_state *state)
cbd19488
AG		 4035{
4036 struct amdgpu_device *adev = plane->dev->dev_private;
4037 struct dc *dc = adev->dm.dc;
78171832
NK		 4038 struct dm_plane_state *dm_plane_state;
4039 struct rect src_rect, dst_rect, clip_rect;
4040 enum dc_rotation_angle rotation;
4041
4042 dm_plane_state = to_dm_plane_state(state);
cbd19488 4043
3be5262e 4044 if (!dm_plane_state->dc_state)
9a3329b1 4045 return 0;
cbd19488 4046
78171832
NK		 4047 if (!fill_rects_from_plane_state(state, &src_rect, &dst_rect,
4048 &clip_rect, &rotation))
a05bcff1
S		 4049 return -EINVAL;
4050
62c933f9 4051 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 4052 return 0;
4053
4054 return -EINVAL;
4055}
4056
674e78ac
NK		 4057static int dm_plane_atomic_async_check(struct drm_plane *plane,
4058 struct drm_plane_state *new_plane_state)
4059{
77acd1cd
NK		 4060 struct drm_plane_state *old_plane_state =
4061 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
4062
674e78ac
NK		 4063 /* Only support async updates on cursor planes. */
4064 if (plane->type != DRM_PLANE_TYPE_CURSOR)
4065 return -EINVAL;
4066
77acd1cd
NK		 4067 /*
4068 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
4069 * async commits so don't allow fb changes.
4070 */
4071 if (old_plane_state->fb != new_plane_state->fb)
4072 return -EINVAL;
4073
674e78ac
NK		 4074 return 0;
4075}
4076
4077static void dm_plane_atomic_async_update(struct drm_plane *plane,
4078 struct drm_plane_state *new_state)
4079{
4080 struct drm_plane_state *old_state =
4081 drm_atomic_get_old_plane_state(new_state->state, plane);
4082
4083 if (plane->state->fb != new_state->fb)
4084 drm_atomic_set_fb_for_plane(plane->state, new_state->fb);
4085
4086 plane->state->src_x = new_state->src_x;
4087 plane->state->src_y = new_state->src_y;
4088 plane->state->src_w = new_state->src_w;
4089 plane->state->src_h = new_state->src_h;
4090 plane->state->crtc_x = new_state->crtc_x;
4091 plane->state->crtc_y = new_state->crtc_y;
4092 plane->state->crtc_w = new_state->crtc_w;
4093 plane->state->crtc_h = new_state->crtc_h;
4094
4095 handle_cursor_update(plane, old_state);
4096}
4097
e7b07cee
HW		 4098static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
4099 .prepare_fb = dm_plane_helper_prepare_fb,
4100 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 4101 .atomic_check = dm_plane_atomic_check,
674e78ac
NK		 4102 .atomic_async_check = dm_plane_atomic_async_check,
4103 .atomic_async_update = dm_plane_atomic_async_update
e7b07cee
HW		 4104};
4105
4106/*
4107 * TODO: these are currently initialized to rgb formats only.
4108 * For future use cases we should either initialize them dynamically based on
4109 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 4110 * check will succeed, and let DC implement proper check
e7b07cee 4111 */
d90371b0 4112static const uint32_t rgb_formats[] = {
e7b07cee
HW		 4113 DRM_FORMAT_XRGB8888,
4114 DRM_FORMAT_ARGB8888,
4115 DRM_FORMAT_RGBA8888,
4116 DRM_FORMAT_XRGB2101010,
4117 DRM_FORMAT_XBGR2101010,
4118 DRM_FORMAT_ARGB2101010,
4119 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 4120 DRM_FORMAT_XBGR8888,
4121 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 4122};
4123
0d579c7e
NK		 4124static const uint32_t overlay_formats[] = {
4125 DRM_FORMAT_XRGB8888,
4126 DRM_FORMAT_ARGB8888,
4127 DRM_FORMAT_RGBA8888,
4128 DRM_FORMAT_XBGR8888,
4129 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 4130};
4131
4132static const u32 cursor_formats[] = {
4133 DRM_FORMAT_ARGB8888
4134};
4135
37c6a93b
NK		 4136static int get_plane_formats(const struct drm_plane *plane,
4137 const struct dc_plane_cap *plane_cap,
4138 uint32_t *formats, int max_formats)
e7b07cee 4139{
37c6a93b
NK		 4140 int i, num_formats = 0;
4141
4142 /*
4143 * TODO: Query support for each group of formats directly from
4144 * DC plane caps. This will require adding more formats to the
4145 * caps list.
4146 */
e7b07cee 4147
f180b4bc 4148 switch (plane->type) {
e7b07cee 4149 case DRM_PLANE_TYPE_PRIMARY:
37c6a93b
NK		 4150 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
4151 if (num_formats >= max_formats)
4152 break;
4153
4154 formats[num_formats++] = rgb_formats[i];
4155 }
4156
ea36ad34 4157 if (plane_cap && plane_cap->pixel_format_support.nv12)
37c6a93b 4158 formats[num_formats++] = DRM_FORMAT_NV12;
e7b07cee 4159 break;
37c6a93b 4160
e7b07cee 4161 case DRM_PLANE_TYPE_OVERLAY:
37c6a93b
NK		 4162 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
4163 if (num_formats >= max_formats)
4164 break;
4165
4166 formats[num_formats++] = overlay_formats[i];
4167 }
e7b07cee 4168 break;
37c6a93b 4169
e7b07cee 4170 case DRM_PLANE_TYPE_CURSOR:
37c6a93b
NK		 4171 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
4172 if (num_formats >= max_formats)
4173 break;
4174
4175 formats[num_formats++] = cursor_formats[i];
4176 }
e7b07cee
HW		 4177 break;
4178 }
4179
37c6a93b
NK		 4180 return num_formats;
4181}
4182
4183static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4184 struct drm_plane *plane,
4185 unsigned long possible_crtcs,
4186 const struct dc_plane_cap *plane_cap)
4187{
4188 uint32_t formats[32];
4189 int num_formats;
4190 int res = -EPERM;
4191
4192 num_formats = get_plane_formats(plane, plane_cap, formats,
4193 ARRAY_SIZE(formats));
4194
4195 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
4196 &dm_plane_funcs, formats, num_formats,
4197 NULL, plane->type, NULL);
4198 if (res)
4199 return res;
4200
cc1fec57
NK		 4201 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4202 plane_cap && plane_cap->per_pixel_alpha) {
d74004b6
NK		 4203 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4204 BIT(DRM_MODE_BLEND_PREMULTI);
4205
4206 drm_plane_create_alpha_property(plane);
4207 drm_plane_create_blend_mode_property(plane, blend_caps);
4208 }
4209
fc8e5230 4210 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
ea36ad34 4211 plane_cap && plane_cap->pixel_format_support.nv12) {
fc8e5230
NK		 4212 /* This only affects YUV formats. */
4213 drm_plane_create_color_properties(
4214 plane,
4215 BIT(DRM_COLOR_YCBCR_BT601) |
4216 BIT(DRM_COLOR_YCBCR_BT709),
4217 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
4218 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
4219 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
4220 }
4221
f180b4bc 4222 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 4223
96719c54 4224 /* Create (reset) the plane state */
f180b4bc
HW		 4225 if (plane->funcs->reset)
4226 plane->funcs->reset(plane);
96719c54 4227
37c6a93b 4228 return 0;
e7b07cee
HW		 4229}
4230
7578ecda
AD		 4231static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
4232 struct drm_plane *plane,
4233 uint32_t crtc_index)
e7b07cee
HW		 4234{
4235 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 4236 struct drm_plane *cursor_plane;
e7b07cee
HW		 4237
4238 int res = -ENOMEM;
4239
4240 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
4241 if (!cursor_plane)
4242 goto fail;
4243
f180b4bc 4244 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
cc1fec57 4245 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
e7b07cee
HW		 4246
4247 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
4248 if (!acrtc)
4249 goto fail;
4250
4251 res = drm_crtc_init_with_planes(
4252 dm->ddev,
4253 &acrtc->base,
4254 plane,
f180b4bc 4255 cursor_plane,
e7b07cee
HW		 4256 &amdgpu_dm_crtc_funcs, NULL);
4257
4258 if (res)
4259 goto fail;
4260
4261 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
4262
96719c54
HW		 4263 /* Create (reset) the plane state */
4264 if (acrtc->base.funcs->reset)
4265 acrtc->base.funcs->reset(&acrtc->base);
4266
e7b07cee
HW		 4267 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
4268 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4269
4270 acrtc->crtc_id = crtc_index;
4271 acrtc->base.enabled = false;
c37e2d29 4272 acrtc->otg_inst = -1;
e7b07cee
HW		 4273
4274 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 4275 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
4276 true, MAX_COLOR_LUT_ENTRIES);
086247a4 4277 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 4278
4279 return 0;
4280
4281fail:
b830ebc9
HW		 4282 kfree(acrtc);
4283 kfree(cursor_plane);
e7b07cee
HW		 4284 return res;
4285}
4286
4287
4288static int to_drm_connector_type(enum signal_type st)
4289{
4290 switch (st) {
4291 case SIGNAL_TYPE_HDMI_TYPE_A:
4292 return DRM_MODE_CONNECTOR_HDMIA;
4293 case SIGNAL_TYPE_EDP:
4294 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 4295 case SIGNAL_TYPE_LVDS:
4296 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 4297 case SIGNAL_TYPE_RGB:
4298 return DRM_MODE_CONNECTOR_VGA;
4299 case SIGNAL_TYPE_DISPLAY_PORT:
4300 case SIGNAL_TYPE_DISPLAY_PORT_MST:
4301 return DRM_MODE_CONNECTOR_DisplayPort;
4302 case SIGNAL_TYPE_DVI_DUAL_LINK:
4303 case SIGNAL_TYPE_DVI_SINGLE_LINK:
4304 return DRM_MODE_CONNECTOR_DVID;
4305 case SIGNAL_TYPE_VIRTUAL:
4306 return DRM_MODE_CONNECTOR_VIRTUAL;
4307
4308 default:
4309 return DRM_MODE_CONNECTOR_Unknown;
4310 }
4311}
4312
2b4c1c05
DV		 4313static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
4314{
4315 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
4316}
4317
e7b07cee
HW		 4318static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
4319{
e7b07cee
HW		 4320 struct drm_encoder *encoder;
4321 struct amdgpu_encoder *amdgpu_encoder;
4322
2b4c1c05 4323 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 4324
4325 if (encoder == NULL)
4326 return;
4327
4328 amdgpu_encoder = to_amdgpu_encoder(encoder);
4329
4330 amdgpu_encoder->native_mode.clock = 0;
4331
4332 if (!list_empty(&connector->probed_modes)) {
4333 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 4334
e7b07cee 4335 list_for_each_entry(preferred_mode,
b830ebc9
HW		 4336 &connector->probed_modes,
4337 head) {
4338 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
4339 amdgpu_encoder->native_mode = *preferred_mode;
4340
e7b07cee
HW		 4341 break;
4342 }
4343
4344 }
4345}
4346
3ee6b26b
AD		 4347static struct drm_display_mode *
4348amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4349 char *name,
4350 int hdisplay, int vdisplay)
e7b07cee
HW		 4351{
4352 struct drm_device *dev = encoder->dev;
4353 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4354 struct drm_display_mode *mode = NULL;
4355 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4356
4357 mode = drm_mode_duplicate(dev, native_mode);
4358
b830ebc9 4359 if (mode == NULL)
e7b07cee
HW		 4360 return NULL;
4361
4362 mode->hdisplay = hdisplay;
4363 mode->vdisplay = vdisplay;
4364 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 4365 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 4366
4367 return mode;
4368
4369}
4370
4371static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 4372 struct drm_connector *connector)
e7b07cee
HW		 4373{
4374 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4375 struct drm_display_mode *mode = NULL;
4376 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 4377 struct amdgpu_dm_connector *amdgpu_dm_connector =
4378 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4379 int i;
4380 int n;
4381 struct mode_size {
4382 char name[DRM_DISPLAY_MODE_LEN];
4383 int w;
4384 int h;
b830ebc9 4385 } common_modes[] = {
e7b07cee
HW		 4386 { "640x480", 640, 480},
4387 { "800x600", 800, 600},
4388 { "1024x768", 1024, 768},
4389 { "1280x720", 1280, 720},
4390 { "1280x800", 1280, 800},
4391 {"1280x1024", 1280, 1024},
4392 { "1440x900", 1440, 900},
4393 {"1680x1050", 1680, 1050},
4394 {"1600x1200", 1600, 1200},
4395 {"1920x1080", 1920, 1080},
4396 {"1920x1200", 1920, 1200}
4397 };
4398
b830ebc9 4399 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 4400
4401 for (i = 0; i < n; i++) {
4402 struct drm_display_mode *curmode = NULL;
4403 bool mode_existed = false;
4404
4405 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 4406 common_modes[i].h > native_mode->vdisplay ||
4407 (common_modes[i].w == native_mode->hdisplay &&
4408 common_modes[i].h == native_mode->vdisplay))
4409 continue;
e7b07cee
HW		 4410
4411 list_for_each_entry(curmode, &connector->probed_modes, head) {
4412 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 4413 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 4414 mode_existed = true;
4415 break;
4416 }
4417 }
4418
4419 if (mode_existed)
4420 continue;
4421
4422 mode = amdgpu_dm_create_common_mode(encoder,
4423 common_modes[i].name, common_modes[i].w,
4424 common_modes[i].h);
4425 drm_mode_probed_add(connector, mode);
c84dec2f 4426 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 4427 }
4428}
4429
3ee6b26b
AD		 4430static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4431 struct edid *edid)
e7b07cee 4432{
c84dec2f
HW		 4433 struct amdgpu_dm_connector *amdgpu_dm_connector =
4434 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4435
4436 if (edid) {
4437 /* empty probed_modes */
4438 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 4439 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 4440 drm_add_edid_modes(connector, edid);
4441
e7b07cee 4442 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 4443 } else {
c84dec2f 4444 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 4445 }
e7b07cee
HW		 4446}
4447
7578ecda 4448static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 4449{
c84dec2f
HW		 4450 struct amdgpu_dm_connector *amdgpu_dm_connector =
4451 to_amdgpu_dm_connector(connector);
e7b07cee 4452 struct drm_encoder *encoder;
c84dec2f 4453 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 4454
2b4c1c05 4455 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 4456
85ee15d6 4457 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 4458 amdgpu_dm_connector->num_modes =
4459 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 4460 } else {
4461 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4462 amdgpu_dm_connector_add_common_modes(encoder, connector);
4463 }
3e332d3a 4464 amdgpu_dm_fbc_init(connector);
5099114b 4465
c84dec2f 4466 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 4467}
4468
3ee6b26b
AD		 4469void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4470 struct amdgpu_dm_connector *aconnector,
4471 int connector_type,
4472 struct dc_link *link,
4473 int link_index)
e7b07cee
HW		 4474{
4475 struct amdgpu_device *adev = dm->ddev->dev_private;
4476
4477 aconnector->connector_id = link_index;
4478 aconnector->dc_link = link;
4479 aconnector->base.interlace_allowed = false;
4480 aconnector->base.doublescan_allowed = false;
4481 aconnector->base.stereo_allowed = false;
4482 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4483 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
e7b07cee
HW		 4484 mutex_init(&aconnector->hpd_lock);
4485
1f6010a9
DF		 4486 /*
4487 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 4488 * which means HPD hot plug not supported
4489 */
e7b07cee
HW		 4490 switch (connector_type) {
4491 case DRM_MODE_CONNECTOR_HDMIA:
4492 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4493 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4494 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 4495 break;
4496 case DRM_MODE_CONNECTOR_DisplayPort:
4497 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4498 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4499 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 4500 break;
4501 case DRM_MODE_CONNECTOR_DVID:
4502 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4503 break;
4504 default:
4505 break;
4506 }
4507
4508 drm_object_attach_property(&aconnector->base.base,
4509 dm->ddev->mode_config.scaling_mode_property,
4510 DRM_MODE_SCALE_NONE);
4511
4512 drm_object_attach_property(&aconnector->base.base,
4513 adev->mode_info.underscan_property,
4514 UNDERSCAN_OFF);
4515 drm_object_attach_property(&aconnector->base.base,
4516 adev->mode_info.underscan_hborder_property,
4517 0);
4518 drm_object_attach_property(&aconnector->base.base,
4519 adev->mode_info.underscan_vborder_property,
4520 0);
07e3a1cf
NK		 4521 drm_object_attach_property(&aconnector->base.base,
4522 adev->mode_info.max_bpc_property,
4523 0);
e7b07cee 4524
c1ee92f9
DF		 4525 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4526 dc_is_dmcu_initialized(adev->dm.dc)) {
4527 drm_object_attach_property(&aconnector->base.base,
4528 adev->mode_info.abm_level_property, 0);
4529 }
bb47de73
NK		 4530
4531 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7fad8da1
NK		 4532 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4533 connector_type == DRM_MODE_CONNECTOR_eDP) {
bb47de73
NK		 4534 drm_connector_attach_vrr_capable_property(
4535 &aconnector->base);
4536 }
e7b07cee
HW		 4537}
4538
7578ecda
AD		 4539static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4540 struct i2c_msg *msgs, int num)
e7b07cee
HW		 4541{
4542 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4543 struct ddc_service *ddc_service = i2c->ddc_service;
4544 struct i2c_command cmd;
4545 int i;
4546 int result = -EIO;
4547
b830ebc9 4548 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 4549
4550 if (!cmd.payloads)
4551 return result;
4552
4553 cmd.number_of_payloads = num;
4554 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4555 cmd.speed = 100;
4556
4557 for (i = 0; i < num; i++) {
4558 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4559 cmd.payloads[i].address = msgs[i].addr;
4560 cmd.payloads[i].length = msgs[i].len;
4561 cmd.payloads[i].data = msgs[i].buf;
4562 }
4563
c85e6e54
DF		 4564 if (dc_submit_i2c(
4565 ddc_service->ctx->dc,
4566 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 4567 &cmd))
4568 result = num;
4569
4570 kfree(cmd.payloads);
4571 return result;
4572}
4573
7578ecda 4574static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 4575{
4576 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4577}
4578
4579static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4580 .master_xfer = amdgpu_dm_i2c_xfer,
4581 .functionality = amdgpu_dm_i2c_func,
4582};
4583
3ee6b26b
AD		 4584static struct amdgpu_i2c_adapter *
4585create_i2c(struct ddc_service *ddc_service,
4586 int link_index,
4587 int *res)
e7b07cee
HW		 4588{
4589 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4590 struct amdgpu_i2c_adapter *i2c;
4591
b830ebc9 4592 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 4593 if (!i2c)
4594 return NULL;
e7b07cee
HW		 4595 i2c->base.owner = THIS_MODULE;
4596 i2c->base.class = I2C_CLASS_DDC;
4597 i2c->base.dev.parent = &adev->pdev->dev;
4598 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 4599 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 4600 i2c_set_adapdata(&i2c->base, i2c);
4601 i2c->ddc_service = ddc_service;
c85e6e54 4602 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 4603
4604 return i2c;
4605}
4606
89fc8d4e 4607
1f6010a9
DF		 4608/*
4609 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 4610 * dc_link which will be represented by this aconnector.
4611 */
7578ecda
AD		 4612static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4613 struct amdgpu_dm_connector *aconnector,
4614 uint32_t link_index,
4615 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 4616{
4617 int res = 0;
4618 int connector_type;
4619 struct dc *dc = dm->dc;
4620 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4621 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 4622
4623 link->priv = aconnector;
e7b07cee 4624
f1ad2f5e 4625 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 4626
4627 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 4628 if (!i2c) {
4629 DRM_ERROR("Failed to create i2c adapter data\n");
4630 return -ENOMEM;
4631 }
4632
e7b07cee
HW		 4633 aconnector->i2c = i2c;
4634 res = i2c_add_adapter(&i2c->base);
4635
4636 if (res) {
4637 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4638 goto out_free;
4639 }
4640
4641 connector_type = to_drm_connector_type(link->connector_signal);
4642
4643 res = drm_connector_init(
4644 dm->ddev,
4645 &aconnector->base,
4646 &amdgpu_dm_connector_funcs,
4647 connector_type);
4648
4649 if (res) {
4650 DRM_ERROR("connector_init failed\n");
4651 aconnector->connector_id = -1;
4652 goto out_free;
4653 }
4654
4655 drm_connector_helper_add(
4656 &aconnector->base,
4657 &amdgpu_dm_connector_helper_funcs);
4658
96719c54
HW		 4659 if (aconnector->base.funcs->reset)
4660 aconnector->base.funcs->reset(&aconnector->base);
4661
e7b07cee
HW		 4662 amdgpu_dm_connector_init_helper(
4663 dm,
4664 aconnector,
4665 connector_type,
4666 link,
4667 link_index);
4668
cde4c44d 4669 drm_connector_attach_encoder(
e7b07cee
HW		 4670 &aconnector->base, &aencoder->base);
4671
4672 drm_connector_register(&aconnector->base);
dc38fd9d
DF		 4673#if defined(CONFIG_DEBUG_FS)
4674 res = connector_debugfs_init(aconnector);
4675 if (res) {
4676 DRM_ERROR("Failed to create debugfs for connector");
4677 goto out_free;
4678 }
f258fee6
DF		 4679 aconnector->debugfs_dpcd_address = 0;
4680 aconnector->debugfs_dpcd_size = 0;
dc38fd9d 4681#endif
e7b07cee
HW		 4682
4683 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4684 || connector_type == DRM_MODE_CONNECTOR_eDP)
4685 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4686
e7b07cee
HW		 4687out_free:
4688 if (res) {
4689 kfree(i2c);
4690 aconnector->i2c = NULL;
4691 }
4692 return res;
4693}
4694
4695int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4696{
4697 switch (adev->mode_info.num_crtc) {
4698 case 1:
4699 return 0x1;
4700 case 2:
4701 return 0x3;
4702 case 3:
4703 return 0x7;
4704 case 4:
4705 return 0xf;
4706 case 5:
4707 return 0x1f;
4708 case 6:
4709 default:
4710 return 0x3f;
4711 }
4712}
4713
7578ecda
AD		 4714static int amdgpu_dm_encoder_init(struct drm_device *dev,
4715 struct amdgpu_encoder *aencoder,
4716 uint32_t link_index)
e7b07cee
HW		 4717{
4718 struct amdgpu_device *adev = dev->dev_private;
4719
4720 int res = drm_encoder_init(dev,
4721 &aencoder->base,
4722 &amdgpu_dm_encoder_funcs,
4723 DRM_MODE_ENCODER_TMDS,
4724 NULL);
4725
4726 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4727
4728 if (!res)
4729 aencoder->encoder_id = link_index;
4730 else
4731 aencoder->encoder_id = -1;
4732
4733 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4734
4735 return res;
4736}
4737
3ee6b26b
AD		 4738static void manage_dm_interrupts(struct amdgpu_device *adev,
4739 struct amdgpu_crtc *acrtc,
4740 bool enable)
e7b07cee
HW		 4741{
4742 /*
4743 * this is not correct translation but will work as soon as VBLANK
4744 * constant is the same as PFLIP
4745 */
4746 int irq_type =
734dd01d 4747 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 4748 adev,
4749 acrtc->crtc_id);
4750
4751 if (enable) {
4752 drm_crtc_vblank_on(&acrtc->base);
4753 amdgpu_irq_get(
4754 adev,
4755 &adev->pageflip_irq,
4756 irq_type);
4757 } else {
4758
4759 amdgpu_irq_put(
4760 adev,
4761 &adev->pageflip_irq,
4762 irq_type);
4763 drm_crtc_vblank_off(&acrtc->base);
4764 }
4765}
4766
3ee6b26b
AD		 4767static bool
4768is_scaling_state_different(const struct dm_connector_state *dm_state,
4769 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 4770{
4771 if (dm_state->scaling != old_dm_state->scaling)
4772 return true;
4773 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4774 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4775 return true;
4776 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4777 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4778 return true;
b830ebc9
HW		 4779 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4780 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4781 return true;
e7b07cee
HW		 4782 return false;
4783}
4784
3ee6b26b
AD		 4785static void remove_stream(struct amdgpu_device *adev,
4786 struct amdgpu_crtc *acrtc,
4787 struct dc_stream_state *stream)
e7b07cee
HW		 4788{
4789 /* this is the update mode case */
e7b07cee
HW		 4790
4791 acrtc->otg_inst = -1;
4792 acrtc->enabled = false;
4793}
4794
7578ecda
AD		 4795static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4796 struct dc_cursor_position *position)
2a8f6ccb 4797{
f4c2cc43 4798 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 4799 int x, y;
4800 int xorigin = 0, yorigin = 0;
4801
4802 if (!crtc || !plane->state->fb) {
4803 position->enable = false;
4804 position->x = 0;
4805 position->y = 0;
4806 return 0;
4807 }
4808
4809 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4810 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4811 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4812 __func__,
4813 plane->state->crtc_w,
4814 plane->state->crtc_h);
4815 return -EINVAL;
4816 }
4817
4818 x = plane->state->crtc_x;
4819 y = plane->state->crtc_y;
4820 /* avivo cursor are offset into the total surface */
4821 x += crtc->primary->state->src_x >> 16;
4822 y += crtc->primary->state->src_y >> 16;
4823 if (x < 0) {
4824 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4825 x = 0;
4826 }
4827 if (y < 0) {
4828 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4829 y = 0;
4830 }
4831 position->enable = true;
4832 position->x = x;
4833 position->y = y;
4834 position->x_hotspot = xorigin;
4835 position->y_hotspot = yorigin;
4836
4837 return 0;
4838}
4839
3ee6b26b
AD		 4840static void handle_cursor_update(struct drm_plane *plane,
4841 struct drm_plane_state *old_plane_state)
e7b07cee 4842{
674e78ac 4843 struct amdgpu_device *adev = plane->dev->dev_private;
2a8f6ccb
HW		 4844 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4845 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4846 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4847 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4848 uint64_t address = afb ? afb->address : 0;
4849 struct dc_cursor_position position;
4850 struct dc_cursor_attributes attributes;
4851 int ret;
4852
e7b07cee
HW		 4853 if (!plane->state->fb && !old_plane_state->fb)
4854 return;
4855
f1ad2f5e 4856 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 4857 __func__,
4858 amdgpu_crtc->crtc_id,
4859 plane->state->crtc_w,
4860 plane->state->crtc_h);
2a8f6ccb
HW		 4861
4862 ret = get_cursor_position(plane, crtc, &position);
4863 if (ret)
4864 return;
4865
4866 if (!position.enable) {
4867 /* turn off cursor */
674e78ac
NK		 4868 if (crtc_state && crtc_state->stream) {
4869 mutex_lock(&adev->dm.dc_lock);
2a8f6ccb
HW		 4870 dc_stream_set_cursor_position(crtc_state->stream,
4871 &position);
674e78ac
NK		 4872 mutex_unlock(&adev->dm.dc_lock);
4873 }
2a8f6ccb 4874 return;
e7b07cee 4875 }
e7b07cee 4876
2a8f6ccb
HW		 4877 amdgpu_crtc->cursor_width = plane->state->crtc_w;
4878 amdgpu_crtc->cursor_height = plane->state->crtc_h;
4879
4880 attributes.address.high_part = upper_32_bits(address);
4881 attributes.address.low_part = lower_32_bits(address);
4882 attributes.width = plane->state->crtc_w;
4883 attributes.height = plane->state->crtc_h;
4884 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4885 attributes.rotation_angle = 0;
4886 attributes.attribute_flags.value = 0;
4887
4888 attributes.pitch = attributes.width;
4889
886daac9 4890 if (crtc_state->stream) {
674e78ac 4891 mutex_lock(&adev->dm.dc_lock);
886daac9
JZ		 4892 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4893 &attributes))
4894 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 4895
2a8f6ccb
HW		 4896 if (!dc_stream_set_cursor_position(crtc_state->stream,
4897 &position))
4898 DRM_ERROR("DC failed to set cursor position\n");
674e78ac 4899 mutex_unlock(&adev->dm.dc_lock);
886daac9 4900 }
2a8f6ccb 4901}
e7b07cee
HW		 4902
4903static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4904{
4905
4906 assert_spin_locked(&acrtc->base.dev->event_lock);
4907 WARN_ON(acrtc->event);
4908
4909 acrtc->event = acrtc->base.state->event;
4910
4911 /* Set the flip status */
4912 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4913
4914 /* Mark this event as consumed */
4915 acrtc->base.state->event = NULL;
4916
4917 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4918 acrtc->crtc_id);
4919}
4920
bb47de73
NK		 4921static void update_freesync_state_on_stream(
4922 struct amdgpu_display_manager *dm,
4923 struct dm_crtc_state *new_crtc_state,
180db303
NK		 4924 struct dc_stream_state *new_stream,
4925 struct dc_plane_state *surface,
4926 u32 flip_timestamp_in_us)
bb47de73 4927{
180db303 4928 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params;
bb47de73 4929 struct dc_info_packet vrr_infopacket = {0};
bb47de73
NK		 4930
4931 if (!new_stream)
4932 return;
4933
4934 /*
4935 * TODO: Determine why min/max totals and vrefresh can be 0 here.
4936 * For now it's sufficient to just guard against these conditions.
4937 */
4938
4939 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
4940 return;
4941
180db303
NK		 4942 if (surface) {
4943 mod_freesync_handle_preflip(
4944 dm->freesync_module,
4945 surface,
4946 new_stream,
4947 flip_timestamp_in_us,
4948 &vrr_params);
4949 }
bb47de73
NK		 4950
4951 mod_freesync_build_vrr_infopacket(
4952 dm->freesync_module,
4953 new_stream,
180db303 4954 &vrr_params,
ecd0136b
HT		 4955 PACKET_TYPE_VRR,
4956 TRANSFER_FUNC_UNKNOWN,
bb47de73
NK		 4957 &vrr_infopacket);
4958
8a48b44c 4959 new_crtc_state->freesync_timing_changed |=
180db303
NK		 4960 (memcmp(&new_crtc_state->vrr_params.adjust,
4961 &vrr_params.adjust,
4962 sizeof(vrr_params.adjust)) != 0);
bb47de73 4963
8a48b44c 4964 new_crtc_state->freesync_vrr_info_changed |=
bb47de73
NK		 4965 (memcmp(&new_crtc_state->vrr_infopacket,
4966 &vrr_infopacket,
4967 sizeof(vrr_infopacket)) != 0);
4968
180db303 4969 new_crtc_state->vrr_params = vrr_params;
bb47de73
NK		 4970 new_crtc_state->vrr_infopacket = vrr_infopacket;
4971
180db303 4972 new_stream->adjust = new_crtc_state->vrr_params.adjust;
bb47de73
NK		 4973 new_stream->vrr_infopacket = vrr_infopacket;
4974
4975 if (new_crtc_state->freesync_vrr_info_changed)
4976 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
4977 new_crtc_state->base.crtc->base.id,
4978 (int)new_crtc_state->base.vrr_enabled,
180db303 4979 (int)vrr_params.state);
bb47de73
NK		 4980}
4981
e854194c
MK		 4982static void pre_update_freesync_state_on_stream(
4983 struct amdgpu_display_manager *dm,
4984 struct dm_crtc_state *new_crtc_state)
4985{
4986 struct dc_stream_state *new_stream = new_crtc_state->stream;
4987 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params;
4988 struct mod_freesync_config config = new_crtc_state->freesync_config;
4989
4990 if (!new_stream)
4991 return;
4992
4993 /*
4994 * TODO: Determine why min/max totals and vrefresh can be 0 here.
4995 * For now it's sufficient to just guard against these conditions.
4996 */
4997 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
4998 return;
4999
5000 if (new_crtc_state->vrr_supported &&
5001 config.min_refresh_in_uhz &&
5002 config.max_refresh_in_uhz) {
5003 config.state = new_crtc_state->base.vrr_enabled ?
5004 VRR_STATE_ACTIVE_VARIABLE :
5005 VRR_STATE_INACTIVE;
5006 } else {
5007 config.state = VRR_STATE_UNSUPPORTED;
5008 }
5009
5010 mod_freesync_build_vrr_params(dm->freesync_module,
5011 new_stream,
5012 &config, &vrr_params);
5013
5014 new_crtc_state->freesync_timing_changed |=
5015 (memcmp(&new_crtc_state->vrr_params.adjust,
5016 &vrr_params.adjust,
5017 sizeof(vrr_params.adjust)) != 0);
5018
5019 new_crtc_state->vrr_params = vrr_params;
5020}
5021
66b0c973
MK		 5022static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
5023 struct dm_crtc_state *new_state)
5024{
5025 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
5026 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
5027
5028 if (!old_vrr_active && new_vrr_active) {
5029 /* Transition VRR inactive -> active:
5030 * While VRR is active, we must not disable vblank irq, as a
5031 * reenable after disable would compute bogus vblank/pflip
5032 * timestamps if it likely happened inside display front-porch.
d2574c33
MK		 5033 *
5034 * We also need vupdate irq for the actual core vblank handling
5035 * at end of vblank.
66b0c973 5036 */
d2574c33 5037 dm_set_vupdate_irq(new_state->base.crtc, true);
66b0c973
MK		 5038 drm_crtc_vblank_get(new_state->base.crtc);
5039 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
5040 __func__, new_state->base.crtc->base.id);
5041 } else if (old_vrr_active && !new_vrr_active) {
5042 /* Transition VRR active -> inactive:
5043 * Allow vblank irq disable again for fixed refresh rate.
5044 */
d2574c33 5045 dm_set_vupdate_irq(new_state->base.crtc, false);
66b0c973
MK		 5046 drm_crtc_vblank_put(new_state->base.crtc);
5047 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
5048 __func__, new_state->base.crtc->base.id);
5049 }
5050}
5051
3be5262e 5052static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 5053 struct dc_state *dc_state,
3ee6b26b
AD		 5054 struct drm_device *dev,
5055 struct amdgpu_display_manager *dm,
5056 struct drm_crtc *pcrtc,
420cd472 5057 bool wait_for_vblank)
e7b07cee 5058{
8a48b44c
DF		 5059 uint32_t i, r;
5060 uint64_t timestamp_ns;
e7b07cee 5061 struct drm_plane *plane;
0bc9706d 5062 struct drm_plane_state *old_plane_state, *new_plane_state;
e7b07cee 5063 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 5064 struct drm_crtc_state *new_pcrtc_state =
5065 drm_atomic_get_new_crtc_state(state, pcrtc);
5066 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 5067 struct dm_crtc_state *dm_old_crtc_state =
5068 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
74aa7bd4 5069 int planes_count = 0, vpos, hpos;
e7b07cee 5070 unsigned long flags;
8a48b44c 5071 struct amdgpu_bo *abo;
09e5665a 5072 uint64_t tiling_flags;
fdd1fe57
MK		 5073 uint32_t target_vblank, last_flip_vblank;
5074 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
74aa7bd4 5075 bool pflip_present = false;
bc7f670e
DF		 5076 struct {
5077 struct dc_surface_update surface_updates[MAX_SURFACES];
5078 struct dc_plane_info plane_infos[MAX_SURFACES];
5079 struct dc_scaling_info scaling_infos[MAX_SURFACES];
74aa7bd4 5080 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
bc7f670e 5081 struct dc_stream_update stream_update;
74aa7bd4 5082 } *bundle;
bc7f670e 5083
74aa7bd4 5084 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8a48b44c 5085
74aa7bd4
DF		 5086 if (!bundle) {
5087 dm_error("Failed to allocate update bundle\n");
4b510503
NK		 5088 goto cleanup;
5089 }
e7b07cee
HW		 5090
5091 /* update planes when needed */
0bc9706d
LSL		 5092 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
5093 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 5094 struct drm_crtc_state *new_crtc_state;
0bc9706d 5095 struct drm_framebuffer *fb = new_plane_state->fb;
8a48b44c 5096 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
34bafd27 5097 bool plane_needs_flip;
c7af5f77 5098 struct dc_plane_state *dc_plane;
54d76575 5099 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee 5100
80c218d5
NK		 5101 /* Cursor plane is handled after stream updates */
5102 if (plane->type == DRM_PLANE_TYPE_CURSOR)
e7b07cee 5103 continue;
e7b07cee 5104
f5ba60fe
DD		 5105 if (!fb || !crtc || pcrtc != crtc)
5106 continue;
5107
5108 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
5109 if (!new_crtc_state->active)
e7b07cee
HW		 5110 continue;
5111
bc7f670e 5112 dc_plane = dm_new_plane_state->dc_state;
e7b07cee 5113
74aa7bd4 5114 bundle->surface_updates[planes_count].surface = dc_plane;
bc7f670e 5115 if (new_pcrtc_state->color_mgmt_changed) {
74aa7bd4
DF		 5116 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
5117 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
bc7f670e 5118 }
8a48b44c 5119
8a48b44c 5120
74aa7bd4 5121 bundle->scaling_infos[planes_count].scaling_quality = dc_plane->scaling_quality;
78171832
NK		 5122
5123 fill_rects_from_plane_state(new_plane_state,
5124 &bundle->scaling_infos[planes_count].src_rect,
5125 &bundle->scaling_infos[planes_count].dst_rect,
5126 &bundle->scaling_infos[planes_count].clip_rect,
5127 &bundle->plane_infos[planes_count].rotation);
5128
74aa7bd4 5129 bundle->surface_updates[planes_count].scaling_info = &bundle->scaling_infos[planes_count];
f7c8930d 5130
004fefa3
NK		 5131 fill_plane_color_attributes(
5132 new_plane_state, dc_plane,
5133 &bundle->plane_infos[planes_count].color_space);
f7c8930d 5134
74aa7bd4
DF		 5135 bundle->plane_infos[planes_count].format = dc_plane->format;
5136 bundle->plane_infos[planes_count].plane_size = dc_plane->plane_size;
74aa7bd4
DF		 5137 bundle->plane_infos[planes_count].horizontal_mirror = dc_plane->horizontal_mirror;
5138 bundle->plane_infos[planes_count].stereo_format = dc_plane->stereo_format;
5139 bundle->plane_infos[planes_count].tiling_info = dc_plane->tiling_info;
5140 bundle->plane_infos[planes_count].visible = dc_plane->visible;
d74004b6
NK		 5141 bundle->plane_infos[planes_count].global_alpha = dc_plane->global_alpha;
5142 bundle->plane_infos[planes_count].global_alpha_value = dc_plane->global_alpha_value;
74aa7bd4
DF		 5143 bundle->plane_infos[planes_count].per_pixel_alpha = dc_plane->per_pixel_alpha;
5144 bundle->plane_infos[planes_count].dcc = dc_plane->dcc;
5145 bundle->surface_updates[planes_count].plane_info = &bundle->plane_infos[planes_count];
8a48b44c 5146
f5031000 5147 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8a48b44c 5148
f5031000 5149 pflip_present = pflip_present || plane_needs_flip;
8a48b44c 5150
f5031000
DF		 5151 if (!plane_needs_flip) {
5152 planes_count += 1;
5153 continue;
5154 }
8a48b44c 5155
f5031000
DF		 5156 /*
5157 * TODO This might fail and hence better not used, wait
5158 * explicitly on fences instead
5159 * and in general should be called for
5160 * blocking commit to as per framework helpers
5161 */
5162 abo = gem_to_amdgpu_bo(fb->obj[0]);
5163 r = amdgpu_bo_reserve(abo, true);
5164 if (unlikely(r != 0)) {
5165 DRM_ERROR("failed to reserve buffer before flip\n");
5166 WARN_ON(1);
5167 }
8a48b44c 5168
f5031000
DF		 5169 /* Wait for all fences on this FB */
5170 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
5171 MAX_SCHEDULE_TIMEOUT) < 0);
8a48b44c 5172
f5031000 5173 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
8a48b44c 5174
f5031000 5175 amdgpu_bo_unreserve(abo);
8a48b44c 5176
09e5665a
NK		 5177 fill_plane_tiling_attributes(dm->adev, afb, dc_plane,
5178 &bundle->plane_infos[planes_count].tiling_info,
5179 &bundle->plane_infos[planes_count].dcc,
5180 &bundle->flip_addrs[planes_count].address,
5181 tiling_flags);
8a48b44c 5182
f5031000
DF		 5183 bundle->flip_addrs[planes_count].flip_immediate =
5184 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
8a48b44c 5185
f5031000
DF		 5186 timestamp_ns = ktime_get_ns();
5187 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
5188 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
5189 bundle->surface_updates[planes_count].surface = dc_plane;
8a48b44c 5190
f5031000
DF		 5191 if (!bundle->surface_updates[planes_count].surface) {
5192 DRM_ERROR("No surface for CRTC: id=%d\n",
5193 acrtc_attach->crtc_id);
5194 continue;
bc7f670e
DF		 5195 }
5196
f5031000
DF		 5197 if (plane == pcrtc->primary)
5198 update_freesync_state_on_stream(
5199 dm,
5200 acrtc_state,
5201 acrtc_state->stream,
5202 dc_plane,
5203 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
bc7f670e 5204
f5031000
DF		 5205 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
5206 __func__,
5207 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
5208 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
bc7f670e
DF		 5209
5210 planes_count += 1;
5211
8a48b44c
DF		 5212 }
5213
74aa7bd4 5214 if (pflip_present) {
634092b1
MK		 5215 if (!vrr_active) {
5216 /* Use old throttling in non-vrr fixed refresh rate mode
5217 * to keep flip scheduling based on target vblank counts
5218 * working in a backwards compatible way, e.g., for
5219 * clients using the GLX_OML_sync_control extension or
5220 * DRI3/Present extension with defined target_msc.
5221 */
fdd1fe57 5222 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
634092b1
MK		 5223 }
5224 else {
5225 /* For variable refresh rate mode only:
5226 * Get vblank of last completed flip to avoid > 1 vrr
5227 * flips per video frame by use of throttling, but allow
5228 * flip programming anywhere in the possibly large
5229 * variable vrr vblank interval for fine-grained flip
5230 * timing control and more opportunity to avoid stutter
5231 * on late submission of flips.
5232 */
5233 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5234 last_flip_vblank = acrtc_attach->last_flip_vblank;
5235 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5236 }
5237
fdd1fe57 5238 target_vblank = last_flip_vblank + wait_for_vblank;
8a48b44c
DF		 5239
5240 /*
5241 * Wait until we're out of the vertical blank period before the one
5242 * targeted by the flip
5243 */
5244 while ((acrtc_attach->enabled &&
5245 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
5246 0, &vpos, &hpos, NULL,
5247 NULL, &pcrtc->hwmode)
5248 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
5249 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
5250 (int)(target_vblank -
5251 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
5252 usleep_range(1000, 1100);
5253 }
5254
5255 if (acrtc_attach->base.state->event) {
5256 drm_crtc_vblank_get(pcrtc);
5257
5258 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5259
5260 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
5261 prepare_flip_isr(acrtc_attach);
5262
5263 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5264 }
5265
5266 if (acrtc_state->stream) {
5267
5268 if (acrtc_state->freesync_timing_changed)
74aa7bd4 5269 bundle->stream_update.adjust =
8a48b44c
DF		 5270 &acrtc_state->stream->adjust;
5271
5272 if (acrtc_state->freesync_vrr_info_changed)
74aa7bd4 5273 bundle->stream_update.vrr_infopacket =
8a48b44c 5274 &acrtc_state->stream->vrr_infopacket;
e7b07cee 5275 }
e7b07cee
HW		 5276 }
5277
5278 if (planes_count) {
bc7f670e 5279 if (new_pcrtc_state->mode_changed) {
74aa7bd4
DF		 5280 bundle->stream_update.src = acrtc_state->stream->src;
5281 bundle->stream_update.dst = acrtc_state->stream->dst;
e7b07cee
HW		 5282 }
5283
bc7f670e 5284 if (new_pcrtc_state->color_mgmt_changed)
74aa7bd4 5285 bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func;
bc7f670e 5286
8a48b44c 5287 acrtc_state->stream->abm_level = acrtc_state->abm_level;
bc7f670e 5288 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
74aa7bd4 5289 bundle->stream_update.abm_level = &acrtc_state->abm_level;
44d09c6a 5290
bc7f670e
DF		 5291 mutex_lock(&dm->dc_lock);
5292 dc_commit_updates_for_stream(dm->dc,
74aa7bd4 5293 bundle->surface_updates,
bc7f670e
DF		 5294 planes_count,
5295 acrtc_state->stream,
74aa7bd4 5296 &bundle->stream_update,
bc7f670e
DF		 5297 dc_state);
5298 mutex_unlock(&dm->dc_lock);
e7b07cee 5299 }
4b510503 5300
80c218d5
NK		 5301 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
5302 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5303 handle_cursor_update(plane, old_plane_state);
5304
4b510503 5305cleanup:
74aa7bd4 5306 kfree(bundle);
e7b07cee
HW		 5307}
5308
1f6010a9 5309/*
27b3f4fc
LSL		 5310 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
5311 * @crtc_state: the DRM CRTC state
5312 * @stream_state: the DC stream state.
5313 *
5314 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
5315 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
5316 */
5317static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
5318 struct dc_stream_state *stream_state)
5319{
b9952f93 5320 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
27b3f4fc 5321}
e7b07cee 5322
7578ecda
AD		 5323static int amdgpu_dm_atomic_commit(struct drm_device *dev,
5324 struct drm_atomic_state *state,
5325 bool nonblock)
e7b07cee
HW		 5326{
5327 struct drm_crtc *crtc;
c2cea706 5328 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 5329 struct amdgpu_device *adev = dev->dev_private;
5330 int i;
5331
5332 /*
5333 * We evade vblanks and pflips on crtc that
5334 * should be changed. We do it here to flush & disable
5335 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
5336 * it will update crtc->dm_crtc_state->stream pointer which is used in
5337 * the ISRs.
5338 */
c2cea706 5339 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 5340 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
428da2bd 5341 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 5342 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5343
428da2bd
NK		 5344 if (drm_atomic_crtc_needs_modeset(new_crtc_state)
5345 && dm_old_crtc_state->stream) {
5346 /*
43a6a02e
NK		 5347 * If the stream is removed and CRC capture was
5348 * enabled on the CRTC the extra vblank reference
5349 * needs to be dropped since CRC capture will be
5350 * disabled.
428da2bd 5351 */
43a6a02e
NK		 5352 if (!dm_new_crtc_state->stream
5353 && dm_new_crtc_state->crc_enabled) {
428da2bd
NK		 5354 drm_crtc_vblank_put(crtc);
5355 dm_new_crtc_state->crc_enabled = false;
5356 }
5357
e7b07cee 5358 manage_dm_interrupts(adev, acrtc, false);
428da2bd 5359 }
e7b07cee 5360 }
1f6010a9
DF		 5361 /*
5362 * Add check here for SoC's that support hardware cursor plane, to
5363 * unset legacy_cursor_update
5364 */
e7b07cee
HW		 5365
5366 return drm_atomic_helper_commit(dev, state, nonblock);
5367
5368 /*TODO Handle EINTR, reenable IRQ*/
5369}
5370
b8592b48
LL		 5371/**
5372 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
5373 * @state: The atomic state to commit
5374 *
5375 * This will tell DC to commit the constructed DC state from atomic_check,
5376 * programming the hardware. Any failures here implies a hardware failure, since
5377 * atomic check should have filtered anything non-kosher.
5378 */
7578ecda 5379static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 5380{
5381 struct drm_device *dev = state->dev;
5382 struct amdgpu_device *adev = dev->dev_private;
5383 struct amdgpu_display_manager *dm = &adev->dm;
5384 struct dm_atomic_state *dm_state;
eb3dc897 5385 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 5386 uint32_t i, j;
5cc6dcbd 5387 struct drm_crtc *crtc;
0bc9706d 5388 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 5389 unsigned long flags;
5390 bool wait_for_vblank = true;
5391 struct drm_connector *connector;
c2cea706 5392 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 5393 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 5394 int crtc_disable_count = 0;
e7b07cee
HW		 5395
5396 drm_atomic_helper_update_legacy_modeset_state(dev, state);
5397
eb3dc897
NK		 5398 dm_state = dm_atomic_get_new_state(state);
5399 if (dm_state && dm_state->context) {
5400 dc_state = dm_state->context;
5401 } else {
5402 /* No state changes, retain current state. */
813d20dc 5403 dc_state_temp = dc_create_state(dm->dc);
eb3dc897
NK		 5404 ASSERT(dc_state_temp);
5405 dc_state = dc_state_temp;
5406 dc_resource_state_copy_construct_current(dm->dc, dc_state);
5407 }
e7b07cee
HW		 5408
5409 /* update changed items */
0bc9706d 5410 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 5411 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5412
54d76575
LSL		 5413 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5414 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 5415
f1ad2f5e 5416 DRM_DEBUG_DRIVER(
e7b07cee
HW		 5417 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5418 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5419 "connectors_changed:%d\n",
5420 acrtc->crtc_id,
0bc9706d
LSL		 5421 new_crtc_state->enable,
5422 new_crtc_state->active,
5423 new_crtc_state->planes_changed,
5424 new_crtc_state->mode_changed,
5425 new_crtc_state->active_changed,
5426 new_crtc_state->connectors_changed);
e7b07cee 5427
27b3f4fc
LSL		 5428 /* Copy all transient state flags into dc state */
5429 if (dm_new_crtc_state->stream) {
5430 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5431 dm_new_crtc_state->stream);
5432 }
5433
e7b07cee
HW		 5434 /* handles headless hotplug case, updating new_state and
5435 * aconnector as needed
5436 */
5437
54d76575 5438 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 5439
f1ad2f5e 5440 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 5441
54d76575 5442 if (!dm_new_crtc_state->stream) {
e7b07cee 5443 /*
b830ebc9
HW		 5444 * this could happen because of issues with
5445 * userspace notifications delivery.
5446 * In this case userspace tries to set mode on
1f6010a9
DF		 5447 * display which is disconnected in fact.
5448 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 5449 * We expect reset mode will come soon.
5450 *
5451 * This can also happen when unplug is done
5452 * during resume sequence ended
5453 *
5454 * In this case, we want to pretend we still
5455 * have a sink to keep the pipe running so that
5456 * hw state is consistent with the sw state
5457 */
f1ad2f5e 5458 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 5459 __func__, acrtc->base.base.id);
5460 continue;
5461 }
5462
54d76575
LSL		 5463 if (dm_old_crtc_state->stream)
5464 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 5465
97028037
LP		 5466 pm_runtime_get_noresume(dev->dev);
5467
e7b07cee 5468 acrtc->enabled = true;
0bc9706d
LSL		 5469 acrtc->hw_mode = new_crtc_state->mode;
5470 crtc->hwmode = new_crtc_state->mode;
5471 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 5472 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 5473
5474 /* i.e. reset mode */
54d76575
LSL		 5475 if (dm_old_crtc_state->stream)
5476 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 5477 }
5478 } /* for_each_crtc_in_state() */
5479
eb3dc897
NK		 5480 if (dc_state) {
5481 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 5482 mutex_lock(&dm->dc_lock);
eb3dc897 5483 WARN_ON(!dc_commit_state(dm->dc, dc_state));
674e78ac 5484 mutex_unlock(&dm->dc_lock);
fa2123db 5485 }
e7b07cee 5486
0bc9706d 5487 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5488 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5489
54d76575 5490 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5491
54d76575 5492 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 5493 const struct dc_stream_status *status =
54d76575 5494 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5495
eb3dc897 5496 if (!status)
09f609c3
LL		 5497 status = dc_stream_get_status_from_state(dc_state,
5498 dm_new_crtc_state->stream);
eb3dc897 5499
e7b07cee 5500 if (!status)
54d76575 5501 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 5502 else
5503 acrtc->otg_inst = status->primary_otg_inst;
5504 }
5505 }
5506
02d6a6fc 5507 /* Handle connector state changes */
c2cea706 5508 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5509 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5510 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5511 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
19afd799
NC		 5512 struct dc_surface_update dummy_updates[MAX_SURFACES];
5513 struct dc_stream_update stream_update;
e7b07cee
HW		 5514 struct dc_stream_status *status = NULL;
5515
19afd799
NC		 5516 memset(&dummy_updates, 0, sizeof(dummy_updates));
5517 memset(&stream_update, 0, sizeof(stream_update));
5518
44d09c6a 5519 if (acrtc) {
0bc9706d 5520 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 5521 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5522 }
0bc9706d 5523
e7b07cee 5524 /* Skip any modesets/resets */
0bc9706d 5525 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 5526 continue;
5527
54d76575 5528 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 5529 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5530
c1ee92f9
DF		 5531 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5532 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5533 continue;
e7b07cee 5534
02d6a6fc
DF		 5535 if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) {
5536 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5537 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 5538
02d6a6fc
DF		 5539 stream_update.src = dm_new_crtc_state->stream->src;
5540 stream_update.dst = dm_new_crtc_state->stream->dst;
5541 }
5542
5543 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
5544 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
5545
5546 stream_update.abm_level = &dm_new_crtc_state->abm_level;
5547 }
70e8ffc5 5548
54d76575 5549 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5550 WARN_ON(!status);
3be5262e 5551 WARN_ON(!status->plane_count);
e7b07cee 5552
02d6a6fc
DF		 5553 /*
5554 * TODO: DC refuses to perform stream updates without a dc_surface_update.
5555 * Here we create an empty update on each plane.
5556 * To fix this, DC should permit updating only stream properties.
5557 */
5558 for (j = 0; j < status->plane_count; j++)
5559 dummy_updates[j].surface = status->plane_states[0];
5560
5561
5562 mutex_lock(&dm->dc_lock);
5563 dc_commit_updates_for_stream(dm->dc,
5564 dummy_updates,
5565 status->plane_count,
5566 dm_new_crtc_state->stream,
5567 &stream_update,
5568 dc_state);
5569 mutex_unlock(&dm->dc_lock);
e7b07cee
HW		 5570 }
5571
e854194c
MK		 5572 /* Update freesync state before amdgpu_dm_handle_vrr_transition(). */
5573 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5574 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5575 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
5576 }
5577
e1fc2dca
LSL		 5578 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5579 new_crtc_state, i) {
e7b07cee
HW		 5580 /*
5581 * loop to enable interrupts on newly arrived crtc
5582 */
e1fc2dca
LSL		 5583 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5584 bool modeset_needed;
b830ebc9 5585
fe2a1965
LP		 5586 if (old_crtc_state->active && !new_crtc_state->active)
5587 crtc_disable_count++;
5588
54d76575 5589 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca 5590 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
66b0c973
MK		 5591
5592 /* Handle vrr on->off / off->on transitions */
5593 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
5594 dm_new_crtc_state);
5595
e1fc2dca
LSL		 5596 modeset_needed = modeset_required(
5597 new_crtc_state,
5598 dm_new_crtc_state->stream,
5599 dm_old_crtc_state->stream);
5600
5601 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
5602 continue;
e7b07cee 5603
e7b07cee 5604 manage_dm_interrupts(adev, acrtc, true);
43a6a02e 5605
cc7e422d 5606#ifdef CONFIG_DEBUG_FS
43a6a02e
NK		 5607 /* The stream has changed so CRC capture needs to re-enabled. */
5608 if (dm_new_crtc_state->crc_enabled)
5609 amdgpu_dm_crtc_set_crc_source(crtc, "auto");
cc7e422d 5610#endif
e7b07cee
HW		 5611 }
5612
420cd472
DF		 5613 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
5614 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
5615 wait_for_vblank = false;
5616
e7b07cee 5617 /* update planes when needed per crtc*/
5cc6dcbd 5618 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 5619 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5620
54d76575 5621 if (dm_new_crtc_state->stream)
eb3dc897 5622 amdgpu_dm_commit_planes(state, dc_state, dev,
420cd472 5623 dm, crtc, wait_for_vblank);
e7b07cee
HW		 5624 }
5625
5626
5627 /*
5628 * send vblank event on all events not handled in flip and
5629 * mark consumed event for drm_atomic_helper_commit_hw_done
5630 */
5631 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 5632 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5633
0bc9706d
LSL		 5634 if (new_crtc_state->event)
5635 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 5636
0bc9706d 5637 new_crtc_state->event = NULL;
e7b07cee
HW		 5638 }
5639 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5640
29c8f234
LL		 5641 /* Signal HW programming completion */
5642 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 5643
5644 if (wait_for_vblank)
320a1274 5645 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 5646
5647 drm_atomic_helper_cleanup_planes(dev, state);
97028037 5648
1f6010a9
DF		 5649 /*
5650 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 5651 * so we can put the GPU into runtime suspend if we're not driving any
5652 * displays anymore
5653 */
fe2a1965
LP		 5654 for (i = 0; i < crtc_disable_count; i++)
5655 pm_runtime_put_autosuspend(dev->dev);
97028037 5656 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 5657
5658 if (dc_state_temp)
5659 dc_release_state(dc_state_temp);
e7b07cee
HW		 5660}
5661
5662
5663static int dm_force_atomic_commit(struct drm_connector *connector)
5664{
5665 int ret = 0;
5666 struct drm_device *ddev = connector->dev;
5667 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5668 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5669 struct drm_plane *plane = disconnected_acrtc->base.primary;
5670 struct drm_connector_state *conn_state;
5671 struct drm_crtc_state *crtc_state;
5672 struct drm_plane_state *plane_state;
5673
5674 if (!state)
5675 return -ENOMEM;
5676
5677 state->acquire_ctx = ddev->mode_config.acquire_ctx;
5678
5679 /* Construct an atomic state to restore previous display setting */
5680
5681 /*
5682 * Attach connectors to drm_atomic_state
5683 */
5684 conn_state = drm_atomic_get_connector_state(state, connector);
5685
5686 ret = PTR_ERR_OR_ZERO(conn_state);
5687 if (ret)
5688 goto err;
5689
5690 /* Attach crtc to drm_atomic_state*/
5691 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5692
5693 ret = PTR_ERR_OR_ZERO(crtc_state);
5694 if (ret)
5695 goto err;
5696
5697 /* force a restore */
5698 crtc_state->mode_changed = true;
5699
5700 /* Attach plane to drm_atomic_state */
5701 plane_state = drm_atomic_get_plane_state(state, plane);
5702
5703 ret = PTR_ERR_OR_ZERO(plane_state);
5704 if (ret)
5705 goto err;
5706
5707
5708 /* Call commit internally with the state we just constructed */
5709 ret = drm_atomic_commit(state);
5710 if (!ret)
5711 return 0;
5712
5713err:
5714 DRM_ERROR("Restoring old state failed with %i\n", ret);
5715 drm_atomic_state_put(state);
5716
5717 return ret;
5718}
5719
5720/*
1f6010a9
DF		 5721 * This function handles all cases when set mode does not come upon hotplug.
5722 * This includes when a display is unplugged then plugged back into the
5723 * same port and when running without usermode desktop manager supprot
e7b07cee 5724 */
3ee6b26b
AD		 5725void dm_restore_drm_connector_state(struct drm_device *dev,
5726 struct drm_connector *connector)
e7b07cee 5727{
c84dec2f 5728 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5729 struct amdgpu_crtc *disconnected_acrtc;
5730 struct dm_crtc_state *acrtc_state;
5731
5732 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5733 return;
5734
5735 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 5736 if (!disconnected_acrtc)
5737 return;
e7b07cee 5738
70e8ffc5
HW		 5739 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5740 if (!acrtc_state->stream)
e7b07cee
HW		 5741 return;
5742
5743 /*
5744 * If the previous sink is not released and different from the current,
5745 * we deduce we are in a state where we can not rely on usermode call
5746 * to turn on the display, so we do it here
5747 */
5748 if (acrtc_state->stream->sink != aconnector->dc_sink)
5749 dm_force_atomic_commit(&aconnector->base);
5750}
5751
1f6010a9 5752/*
e7b07cee
HW		 5753 * Grabs all modesetting locks to serialize against any blocking commits,
5754 * Waits for completion of all non blocking commits.
5755 */
3ee6b26b
AD		 5756static int do_aquire_global_lock(struct drm_device *dev,
5757 struct drm_atomic_state *state)
e7b07cee
HW		 5758{
5759 struct drm_crtc *crtc;
5760 struct drm_crtc_commit *commit;
5761 long ret;
5762
1f6010a9
DF		 5763 /*
5764 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 5765 * ensure that when the framework release it the
5766 * extra locks we are locking here will get released to
5767 */
5768 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
5769 if (ret)
5770 return ret;
5771
5772 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5773 spin_lock(&crtc->commit_lock);
5774 commit = list_first_entry_or_null(&crtc->commit_list,
5775 struct drm_crtc_commit, commit_entry);
5776 if (commit)
5777 drm_crtc_commit_get(commit);
5778 spin_unlock(&crtc->commit_lock);
5779
5780 if (!commit)
5781 continue;
5782
1f6010a9
DF		 5783 /*
5784 * Make sure all pending HW programming completed and
e7b07cee
HW		 5785 * page flips done
5786 */
5787 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
5788
5789 if (ret > 0)
5790 ret = wait_for_completion_interruptible_timeout(
5791 &commit->flip_done, 10*HZ);
5792
5793 if (ret == 0)
5794 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 5795 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 5796
5797 drm_crtc_commit_put(commit);
5798 }
5799
5800 return ret < 0 ? ret : 0;
5801}
5802
bb47de73
NK		 5803static void get_freesync_config_for_crtc(
5804 struct dm_crtc_state *new_crtc_state,
5805 struct dm_connector_state *new_con_state)
98e6436d
AK		 5806{
5807 struct mod_freesync_config config = {0};
98e6436d
AK		 5808 struct amdgpu_dm_connector *aconnector =
5809 to_amdgpu_dm_connector(new_con_state->base.connector);
a057ec46 5810 struct drm_display_mode *mode = &new_crtc_state->base.mode;
98e6436d 5811
a057ec46
IB		 5812 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
5813 aconnector->min_vfreq <= drm_mode_vrefresh(mode);
bb47de73 5814
a057ec46
IB		 5815 if (new_crtc_state->vrr_supported) {
5816 new_crtc_state->stream->ignore_msa_timing_param = true;
bb47de73 5817 config.state = new_crtc_state->base.vrr_enabled ?
98e6436d
AK		 5818 VRR_STATE_ACTIVE_VARIABLE :
5819 VRR_STATE_INACTIVE;
5820 config.min_refresh_in_uhz =
5821 aconnector->min_vfreq * 1000000;
5822 config.max_refresh_in_uhz =
5823 aconnector->max_vfreq * 1000000;
69ff8845 5824 config.vsif_supported = true;
180db303 5825 config.btr = true;
98e6436d
AK		 5826 }
5827
bb47de73
NK		 5828 new_crtc_state->freesync_config = config;
5829}
98e6436d 5830
bb47de73
NK		 5831static void reset_freesync_config_for_crtc(
5832 struct dm_crtc_state *new_crtc_state)
5833{
5834 new_crtc_state->vrr_supported = false;
98e6436d 5835
180db303
NK		 5836 memset(&new_crtc_state->vrr_params, 0,
5837 sizeof(new_crtc_state->vrr_params));
bb47de73
NK		 5838 memset(&new_crtc_state->vrr_infopacket, 0,
5839 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 5840}
5841
4b9674e5
LL		 5842static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
5843 struct drm_atomic_state *state,
5844 struct drm_crtc *crtc,
5845 struct drm_crtc_state *old_crtc_state,
5846 struct drm_crtc_state *new_crtc_state,
5847 bool enable,
5848 bool *lock_and_validation_needed)
e7b07cee 5849{
eb3dc897 5850 struct dm_atomic_state *dm_state = NULL;
54d76575 5851 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 5852 struct dc_stream_state *new_stream;
62f55537 5853 int ret = 0;
d4d4a645 5854
1f6010a9
DF		 5855 /*
5856 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
5857 * update changed items
5858 */
4b9674e5
LL		 5859 struct amdgpu_crtc *acrtc = NULL;
5860 struct amdgpu_dm_connector *aconnector = NULL;
5861 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
5862 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
5863 struct drm_plane_state *new_plane_state = NULL;
e7b07cee 5864
4b9674e5 5865 new_stream = NULL;
9635b754 5866
4b9674e5
LL		 5867 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5868 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5869 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 5870
4b9674e5 5871 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
f2877656 5872
4b9674e5
LL		 5873 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
5874 ret = -EINVAL;
5875 goto fail;
5876 }
f2877656 5877
4b9674e5 5878 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 5879
4b9674e5
LL		 5880 /* TODO This hack should go away */
5881 if (aconnector && enable) {
5882 /* Make sure fake sink is created in plug-in scenario */
5883 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
5884 &aconnector->base);
5885 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
5886 &aconnector->base);
19f89e23 5887
4b9674e5
LL		 5888 if (IS_ERR(drm_new_conn_state)) {
5889 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
5890 goto fail;
5891 }
19f89e23 5892
4b9674e5
LL		 5893 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
5894 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 5895
02d35a67
JFZ		 5896 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5897 goto skip_modeset;
5898
4b9674e5
LL		 5899 new_stream = create_stream_for_sink(aconnector,
5900 &new_crtc_state->mode,
5901 dm_new_conn_state,
5902 dm_old_crtc_state->stream);
19f89e23 5903
4b9674e5
LL		 5904 /*
5905 * we can have no stream on ACTION_SET if a display
5906 * was disconnected during S3, in this case it is not an
5907 * error, the OS will be updated after detection, and
5908 * will do the right thing on next atomic commit
5909 */
19f89e23 5910
4b9674e5
LL		 5911 if (!new_stream) {
5912 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5913 __func__, acrtc->base.base.id);
5914 ret = -ENOMEM;
5915 goto fail;
5916 }
e7b07cee 5917
4b9674e5 5918 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 5919
4b9674e5
LL		 5920 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
5921 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
5922 new_crtc_state->mode_changed = false;
5923 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
5924 new_crtc_state->mode_changed);
62f55537 5925 }
4b9674e5 5926 }
b830ebc9 5927
02d35a67 5928 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 5929 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5930 goto skip_modeset;
e7b07cee 5931
4b9674e5
LL		 5932 DRM_DEBUG_DRIVER(
5933 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5934 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5935 "connectors_changed:%d\n",
5936 acrtc->crtc_id,
5937 new_crtc_state->enable,
5938 new_crtc_state->active,
5939 new_crtc_state->planes_changed,
5940 new_crtc_state->mode_changed,
5941 new_crtc_state->active_changed,
5942 new_crtc_state->connectors_changed);
62f55537 5943
4b9674e5
LL		 5944 /* Remove stream for any changed/disabled CRTC */
5945 if (!enable) {
62f55537 5946
4b9674e5
LL		 5947 if (!dm_old_crtc_state->stream)
5948 goto skip_modeset;
eb3dc897 5949
4b9674e5
LL		 5950 ret = dm_atomic_get_state(state, &dm_state);
5951 if (ret)
5952 goto fail;
e7b07cee 5953
4b9674e5
LL		 5954 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
5955 crtc->base.id);
62f55537 5956
4b9674e5
LL		 5957 /* i.e. reset mode */
5958 if (dc_remove_stream_from_ctx(
5959 dm->dc,
5960 dm_state->context,
5961 dm_old_crtc_state->stream) != DC_OK) {
5962 ret = -EINVAL;
5963 goto fail;
5964 }
62f55537 5965
4b9674e5
LL		 5966 dc_stream_release(dm_old_crtc_state->stream);
5967 dm_new_crtc_state->stream = NULL;
bb47de73 5968
4b9674e5 5969 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 5970
4b9674e5 5971 *lock_and_validation_needed = true;
62f55537 5972
4b9674e5
LL		 5973 } else {/* Add stream for any updated/enabled CRTC */
5974 /*
5975 * Quick fix to prevent NULL pointer on new_stream when
5976 * added MST connectors not found in existing crtc_state in the chained mode
5977 * TODO: need to dig out the root cause of that
5978 */
5979 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
5980 goto skip_modeset;
62f55537 5981
4b9674e5
LL		 5982 if (modereset_required(new_crtc_state))
5983 goto skip_modeset;
62f55537 5984
4b9674e5
LL		 5985 if (modeset_required(new_crtc_state, new_stream,
5986 dm_old_crtc_state->stream)) {
62f55537 5987
4b9674e5 5988 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 5989
4b9674e5
LL		 5990 ret = dm_atomic_get_state(state, &dm_state);
5991 if (ret)
5992 goto fail;
27b3f4fc 5993
4b9674e5 5994 dm_new_crtc_state->stream = new_stream;
62f55537 5995
4b9674e5 5996 dc_stream_retain(new_stream);
1dc90497 5997
4b9674e5
LL		 5998 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
5999 crtc->base.id);
1dc90497 6000
4b9674e5
LL		 6001 if (dc_add_stream_to_ctx(
6002 dm->dc,
6003 dm_state->context,
6004 dm_new_crtc_state->stream) != DC_OK) {
6005 ret = -EINVAL;
6006 goto fail;
9b690ef3
BL		 6007 }
6008
4b9674e5
LL		 6009 *lock_and_validation_needed = true;
6010 }
6011 }
e277adc5 6012
4b9674e5
LL		 6013skip_modeset:
6014 /* Release extra reference */
6015 if (new_stream)
6016 dc_stream_release(new_stream);
e277adc5 6017
4b9674e5
LL		 6018 /*
6019 * We want to do dc stream updates that do not require a
6020 * full modeset below.
6021 */
6022 if (!(enable && aconnector && new_crtc_state->enable &&
6023 new_crtc_state->active))
6024 return 0;
6025 /*
6026 * Given above conditions, the dc state cannot be NULL because:
6027 * 1. We're in the process of enabling CRTCs (just been added
6028 * to the dc context, or already is on the context)
6029 * 2. Has a valid connector attached, and
6030 * 3. Is currently active and enabled.
6031 * => The dc stream state currently exists.
6032 */
6033 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 6034
4b9674e5
LL		 6035 /* Scaling or underscan settings */
6036 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
6037 update_stream_scaling_settings(
6038 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 6039
b05e2c5e
DF		 6040 /* ABM settings */
6041 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6042
4b9674e5
LL		 6043 /*
6044 * Color management settings. We also update color properties
6045 * when a modeset is needed, to ensure it gets reprogrammed.
6046 */
6047 if (dm_new_crtc_state->base.color_mgmt_changed ||
6048 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
6049 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
6050 if (ret)
6051 goto fail;
6052 amdgpu_dm_set_ctm(dm_new_crtc_state);
62f55537 6053 }
e7b07cee 6054
4b9674e5
LL		 6055 /* Update Freesync settings. */
6056 get_freesync_config_for_crtc(dm_new_crtc_state,
6057 dm_new_conn_state);
6058
62f55537 6059 return ret;
9635b754
DS		 6060
6061fail:
6062 if (new_stream)
6063 dc_stream_release(new_stream);
6064 return ret;
62f55537 6065}
9b690ef3 6066
9e869063
LL		 6067static int dm_update_plane_state(struct dc *dc,
6068 struct drm_atomic_state *state,
6069 struct drm_plane *plane,
6070 struct drm_plane_state *old_plane_state,
6071 struct drm_plane_state *new_plane_state,
6072 bool enable,
6073 bool *lock_and_validation_needed)
62f55537 6074{
eb3dc897
NK		 6075
6076 struct dm_atomic_state *dm_state = NULL;
62f55537 6077 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 6078 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 6079 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 6080 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 6081 /* TODO return page_flip_needed() function */
6082 bool pflip_needed = !state->allow_modeset;
6083 int ret = 0;
e7b07cee 6084
9b690ef3 6085
9e869063
LL		 6086 new_plane_crtc = new_plane_state->crtc;
6087 old_plane_crtc = old_plane_state->crtc;
6088 dm_new_plane_state = to_dm_plane_state(new_plane_state);
6089 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 6090
9e869063
LL		 6091 /*TODO Implement atomic check for cursor plane */
6092 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6093 return 0;
9b690ef3 6094
9e869063
LL		 6095 /* Remove any changed/removed planes */
6096 if (!enable) {
6097 if (pflip_needed &&
6098 plane->type != DRM_PLANE_TYPE_OVERLAY)
6099 return 0;
a7b06724 6100
9e869063
LL		 6101 if (!old_plane_crtc)
6102 return 0;
62f55537 6103
9e869063
LL		 6104 old_crtc_state = drm_atomic_get_old_crtc_state(
6105 state, old_plane_crtc);
6106 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 6107
9e869063
LL		 6108 if (!dm_old_crtc_state->stream)
6109 return 0;
62f55537 6110
9e869063
LL		 6111 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
6112 plane->base.id, old_plane_crtc->base.id);
9b690ef3 6113
9e869063
LL		 6114 ret = dm_atomic_get_state(state, &dm_state);
6115 if (ret)
6116 return ret;
eb3dc897 6117
9e869063
LL		 6118 if (!dc_remove_plane_from_context(
6119 dc,
6120 dm_old_crtc_state->stream,
6121 dm_old_plane_state->dc_state,
6122 dm_state->context)) {
62f55537 6123
9e869063
LL		 6124 ret = EINVAL;
6125 return ret;
6126 }
e7b07cee 6127
9b690ef3 6128
9e869063
LL		 6129 dc_plane_state_release(dm_old_plane_state->dc_state);
6130 dm_new_plane_state->dc_state = NULL;
1dc90497 6131
9e869063 6132 *lock_and_validation_needed = true;
1dc90497 6133
9e869063
LL		 6134 } else { /* Add new planes */
6135 struct dc_plane_state *dc_new_plane_state;
1dc90497 6136
9e869063
LL		 6137 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
6138 return 0;
e7b07cee 6139
9e869063
LL		 6140 if (!new_plane_crtc)
6141 return 0;
e7b07cee 6142
9e869063
LL		 6143 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
6144 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 6145
9e869063
LL		 6146 if (!dm_new_crtc_state->stream)
6147 return 0;
62f55537 6148
9e869063
LL		 6149 if (pflip_needed && plane->type != DRM_PLANE_TYPE_OVERLAY)
6150 return 0;
62f55537 6151
9e869063 6152 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 6153
9e869063
LL		 6154 dc_new_plane_state = dc_create_plane_state(dc);
6155 if (!dc_new_plane_state)
6156 return -ENOMEM;
62f55537 6157
9e869063
LL		 6158 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
6159 plane->base.id, new_plane_crtc->base.id);
8c45c5db 6160
9e869063
LL		 6161 ret = fill_plane_attributes(
6162 new_plane_crtc->dev->dev_private,
6163 dc_new_plane_state,
6164 new_plane_state,
6165 new_crtc_state);
6166 if (ret) {
6167 dc_plane_state_release(dc_new_plane_state);
6168 return ret;
6169 }
62f55537 6170
9e869063
LL		 6171 ret = dm_atomic_get_state(state, &dm_state);
6172 if (ret) {
6173 dc_plane_state_release(dc_new_plane_state);
6174 return ret;
6175 }
eb3dc897 6176
9e869063
LL		 6177 /*
6178 * Any atomic check errors that occur after this will
6179 * not need a release. The plane state will be attached
6180 * to the stream, and therefore part of the atomic
6181 * state. It'll be released when the atomic state is
6182 * cleaned.
6183 */
6184 if (!dc_add_plane_to_context(
6185 dc,
6186 dm_new_crtc_state->stream,
6187 dc_new_plane_state,
6188 dm_state->context)) {
62f55537 6189
9e869063
LL		 6190 dc_plane_state_release(dc_new_plane_state);
6191 return -EINVAL;
6192 }
8c45c5db 6193
9e869063 6194 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 6195
9e869063
LL		 6196 /* Tell DC to do a full surface update every time there
6197 * is a plane change. Inefficient, but works for now.
6198 */
6199 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
6200
6201 *lock_and_validation_needed = true;
62f55537 6202 }
e7b07cee
HW		 6203
6204
62f55537
AG		 6205 return ret;
6206}
a87fa993 6207
eb3dc897
NK		 6208static int
6209dm_determine_update_type_for_commit(struct dc *dc,
6210 struct drm_atomic_state *state,
6211 enum surface_update_type *out_type)
6212{
6213 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
6214 int i, j, num_plane, ret = 0;
a87fa993
BL		 6215 struct drm_plane_state *old_plane_state, *new_plane_state;
6216 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
6217 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
6218 struct drm_plane *plane;
6219
6220 struct drm_crtc *crtc;
6221 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
6222 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
6223 struct dc_stream_status *status = NULL;
6224
fe96b99d
GS		 6225 struct dc_surface_update *updates;
6226 struct dc_plane_state *surface;
a87fa993
BL		 6227 enum surface_update_type update_type = UPDATE_TYPE_FAST;
6228
fe96b99d
GS		 6229 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
6230 surface = kcalloc(MAX_SURFACES, sizeof(*surface), GFP_KERNEL);
6231
4f712911
BL		 6232 if (!updates || !surface) {
6233 DRM_ERROR("Plane or surface update failed to allocate");
6234 /* Set type to FULL to avoid crashing in DC*/
6235 update_type = UPDATE_TYPE_FULL;
eb3dc897 6236 goto cleanup;
4f712911 6237 }
a87fa993
BL		 6238
6239 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2aa632c5
NK		 6240 struct dc_stream_update stream_update;
6241
6242 memset(&stream_update, 0, sizeof(stream_update));
c448a53a 6243
a87fa993
BL		 6244 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6245 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
6246 num_plane = 0;
6247
6836d239
NK		 6248 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
6249 update_type = UPDATE_TYPE_FULL;
6250 goto cleanup;
6251 }
a87fa993 6252
6836d239 6253 if (!new_dm_crtc_state->stream)
c744e974 6254 continue;
eb3dc897 6255
c744e974
NK		 6256 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
6257 new_plane_crtc = new_plane_state->crtc;
6258 old_plane_crtc = old_plane_state->crtc;
6259 new_dm_plane_state = to_dm_plane_state(new_plane_state);
6260 old_dm_plane_state = to_dm_plane_state(old_plane_state);
eb3dc897 6261
c744e974
NK		 6262 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6263 continue;
eb3dc897 6264
6836d239
NK		 6265 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
6266 update_type = UPDATE_TYPE_FULL;
6267 goto cleanup;
6268 }
6269
c744e974
NK		 6270 if (!state->allow_modeset)
6271 continue;
a87fa993 6272
c744e974
NK		 6273 if (crtc != new_plane_crtc)
6274 continue;
6275
6276 updates[num_plane].surface = &surface[num_plane];
6277
6278 if (new_crtc_state->mode_changed) {
6279 updates[num_plane].surface->src_rect =
6280 new_dm_plane_state->dc_state->src_rect;
6281 updates[num_plane].surface->dst_rect =
6282 new_dm_plane_state->dc_state->dst_rect;
6283 updates[num_plane].surface->rotation =
6284 new_dm_plane_state->dc_state->rotation;
6285 updates[num_plane].surface->in_transfer_func =
6286 new_dm_plane_state->dc_state->in_transfer_func;
6287 stream_update.dst = new_dm_crtc_state->stream->dst;
6288 stream_update.src = new_dm_crtc_state->stream->src;
6289 }
6290
6291 if (new_crtc_state->color_mgmt_changed) {
6292 updates[num_plane].gamma =
6293 new_dm_plane_state->dc_state->gamma_correction;
6294 updates[num_plane].in_transfer_func =
6295 new_dm_plane_state->dc_state->in_transfer_func;
6296 stream_update.gamut_remap =
6297 &new_dm_crtc_state->stream->gamut_remap_matrix;
6298 stream_update.out_transfer_func =
6299 new_dm_crtc_state->stream->out_transfer_func;
a87fa993
BL		 6300 }
6301
c744e974
NK		 6302 num_plane++;
6303 }
6304
6305 if (num_plane == 0)
6306 continue;
6307
6308 ret = dm_atomic_get_state(state, &dm_state);
6309 if (ret)
6310 goto cleanup;
6311
6312 old_dm_state = dm_atomic_get_old_state(state);
6313 if (!old_dm_state) {
6314 ret = -EINVAL;
6315 goto cleanup;
6316 }
6317
6318 status = dc_stream_get_status_from_state(old_dm_state->context,
6319 new_dm_crtc_state->stream);
6320
6321 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
6322 &stream_update, status);
6323
6324 if (update_type > UPDATE_TYPE_MED) {
a87fa993 6325 update_type = UPDATE_TYPE_FULL;
eb3dc897 6326 goto cleanup;
a87fa993
BL		 6327 }
6328 }
6329
eb3dc897 6330cleanup:
a87fa993
BL		 6331 kfree(updates);
6332 kfree(surface);
6333
eb3dc897
NK		 6334 *out_type = update_type;
6335 return ret;
a87fa993 6336}
62f55537 6337
b8592b48
LL		 6338/**
6339 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
6340 * @dev: The DRM device
6341 * @state: The atomic state to commit
6342 *
6343 * Validate that the given atomic state is programmable by DC into hardware.
6344 * This involves constructing a &struct dc_state reflecting the new hardware
6345 * state we wish to commit, then querying DC to see if it is programmable. It's
6346 * important not to modify the existing DC state. Otherwise, atomic_check
6347 * may unexpectedly commit hardware changes.
6348 *
6349 * When validating the DC state, it's important that the right locks are
6350 * acquired. For full updates case which removes/adds/updates streams on one
6351 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
6352 * that any such full update commit will wait for completion of any outstanding
6353 * flip using DRMs synchronization events. See
6354 * dm_determine_update_type_for_commit()
6355 *
6356 * Note that DM adds the affected connectors for all CRTCs in state, when that
6357 * might not seem necessary. This is because DC stream creation requires the
6358 * DC sink, which is tied to the DRM connector state. Cleaning this up should
6359 * be possible but non-trivial - a possible TODO item.
6360 *
6361 * Return: -Error code if validation failed.
6362 */
7578ecda
AD		 6363static int amdgpu_dm_atomic_check(struct drm_device *dev,
6364 struct drm_atomic_state *state)
62f55537 6365{
62f55537 6366 struct amdgpu_device *adev = dev->dev_private;
eb3dc897 6367 struct dm_atomic_state *dm_state = NULL;
62f55537 6368 struct dc *dc = adev->dm.dc;
62f55537 6369 struct drm_connector *connector;
c2cea706 6370 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 6371 struct drm_crtc *crtc;
fc9e9920 6372 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 6373 struct drm_plane *plane;
6374 struct drm_plane_state *old_plane_state, *new_plane_state;
a87fa993
BL		 6375 enum surface_update_type update_type = UPDATE_TYPE_FAST;
6376 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
6377
1e88ad0a 6378 int ret, i;
e7b07cee 6379
62f55537
AG		 6380 /*
6381 * This bool will be set for true for any modeset/reset
6382 * or plane update which implies non fast surface update.
6383 */
6384 bool lock_and_validation_needed = false;
6385
6386 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 6387 if (ret)
6388 goto fail;
62f55537 6389
1e88ad0a
S		 6390 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6391 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 6392 !new_crtc_state->color_mgmt_changed &&
a93587b3 6393 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
1e88ad0a 6394 continue;
7bef1af3 6395
1e88ad0a
S		 6396 if (!new_crtc_state->enable)
6397 continue;
fc9e9920 6398
1e88ad0a
S		 6399 ret = drm_atomic_add_affected_connectors(state, crtc);
6400 if (ret)
6401 return ret;
fc9e9920 6402
1e88ad0a
S		 6403 ret = drm_atomic_add_affected_planes(state, crtc);
6404 if (ret)
6405 goto fail;
e7b07cee
HW		 6406 }
6407
2d9e6431
NK		 6408 /*
6409 * Add all primary and overlay planes on the CRTC to the state
6410 * whenever a plane is enabled to maintain correct z-ordering
6411 * and to enable fast surface updates.
6412 */
6413 drm_for_each_crtc(crtc, dev) {
6414 bool modified = false;
6415
6416 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
6417 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6418 continue;
6419
6420 if (new_plane_state->crtc == crtc ||
6421 old_plane_state->crtc == crtc) {
6422 modified = true;
6423 break;
6424 }
6425 }
6426
6427 if (!modified)
6428 continue;
6429
6430 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
6431 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6432 continue;
6433
6434 new_plane_state =
6435 drm_atomic_get_plane_state(state, plane);
6436
6437 if (IS_ERR(new_plane_state)) {
6438 ret = PTR_ERR(new_plane_state);
6439 goto fail;
6440 }
6441 }
6442 }
6443
62f55537 6444 /* Remove exiting planes if they are modified */
9e869063
LL		 6445 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6446 ret = dm_update_plane_state(dc, state, plane,
6447 old_plane_state,
6448 new_plane_state,
6449 false,
6450 &lock_and_validation_needed);
6451 if (ret)
6452 goto fail;
62f55537
AG		 6453 }
6454
6455 /* Disable all crtcs which require disable */
4b9674e5
LL		 6456 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6457 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6458 old_crtc_state,
6459 new_crtc_state,
6460 false,
6461 &lock_and_validation_needed);
6462 if (ret)
6463 goto fail;
62f55537
AG		 6464 }
6465
6466 /* Enable all crtcs which require enable */
4b9674e5
LL		 6467 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6468 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6469 old_crtc_state,
6470 new_crtc_state,
6471 true,
6472 &lock_and_validation_needed);
6473 if (ret)
6474 goto fail;
62f55537
AG		 6475 }
6476
6477 /* Add new/modified planes */
9e869063
LL		 6478 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6479 ret = dm_update_plane_state(dc, state, plane,
6480 old_plane_state,
6481 new_plane_state,
6482 true,
6483 &lock_and_validation_needed);
6484 if (ret)
6485 goto fail;
62f55537
AG		 6486 }
6487
b349f76e
ES		 6488 /* Run this here since we want to validate the streams we created */
6489 ret = drm_atomic_helper_check_planes(dev, state);
6490 if (ret)
6491 goto fail;
62f55537 6492
ebdd27e1 6493 /* Check scaling and underscan changes*/
1f6010a9 6494 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 6495 * new stream into context w\o causing full reset. Need to
6496 * decide how to handle.
6497 */
c2cea706 6498 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 6499 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6500 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6501 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 6502
6503 /* Skip any modesets/resets */
0bc9706d
LSL		 6504 if (!acrtc || drm_atomic_crtc_needs_modeset(
6505 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 6506 continue;
6507
b830ebc9 6508 /* Skip any thing not scale or underscan changes */
54d76575 6509 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 6510 continue;
6511
a87fa993 6512 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 6513 lock_and_validation_needed = true;
6514 }
6515
eb3dc897
NK		 6516 ret = dm_determine_update_type_for_commit(dc, state, &update_type);
6517 if (ret)
6518 goto fail;
a87fa993
BL		 6519
6520 if (overall_update_type < update_type)
6521 overall_update_type = update_type;
6522
6523 /*
6524 * lock_and_validation_needed was an old way to determine if we need to set
6525 * the global lock. Leaving it in to check if we broke any corner cases
6526 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
6527 * lock_and_validation_needed false = UPDATE_TYPE_FAST
6528 */
6529 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
6530 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
6531 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
6532 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
e7b07cee 6533
e7b07cee 6534
a87fa993 6535 if (overall_update_type > UPDATE_TYPE_FAST) {
eb3dc897
NK		 6536 ret = dm_atomic_get_state(state, &dm_state);
6537 if (ret)
6538 goto fail;
e7b07cee
HW		 6539
6540 ret = do_aquire_global_lock(dev, state);
6541 if (ret)
6542 goto fail;
1dc90497 6543
e750d56d 6544 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 6545 ret = -EINVAL;
6546 goto fail;
6547 }
674e78ac
NK		 6548 } else if (state->legacy_cursor_update) {
6549 /*
6550 * This is a fast cursor update coming from the plane update
6551 * helper, check if it can be done asynchronously for better
6552 * performance.
6553 */
6554 state->async_update = !drm_atomic_helper_async_check(dev, state);
e7b07cee
HW		 6555 }
6556
6557 /* Must be success */
6558 WARN_ON(ret);
6559 return ret;
6560
6561fail:
6562 if (ret == -EDEADLK)
01e28f9c 6563 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 6564 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 6565 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 6566 else
01e28f9c 6567 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 6568
6569 return ret;
6570}
6571
3ee6b26b
AD		 6572static bool is_dp_capable_without_timing_msa(struct dc *dc,
6573 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 6574{
6575 uint8_t dpcd_data;
6576 bool capable = false;
6577
c84dec2f 6578 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 6579 dm_helpers_dp_read_dpcd(
6580 NULL,
c84dec2f 6581 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 6582 DP_DOWN_STREAM_PORT_COUNT,
6583 &dpcd_data,
6584 sizeof(dpcd_data))) {
6585 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
6586 }
6587
6588 return capable;
6589}
98e6436d
AK		 6590void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
6591 struct edid *edid)
e7b07cee
HW		 6592{
6593 int i;
e7b07cee
HW		 6594 bool edid_check_required;
6595 struct detailed_timing *timing;
6596 struct detailed_non_pixel *data;
6597 struct detailed_data_monitor_range *range;
c84dec2f
HW		 6598 struct amdgpu_dm_connector *amdgpu_dm_connector =
6599 to_amdgpu_dm_connector(connector);
bb47de73 6600 struct dm_connector_state *dm_con_state = NULL;
e7b07cee
HW		 6601
6602 struct drm_device *dev = connector->dev;
6603 struct amdgpu_device *adev = dev->dev_private;
bb47de73 6604 bool freesync_capable = false;
b830ebc9 6605
8218d7f1
HW		 6606 if (!connector->state) {
6607 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 6608 goto update;
8218d7f1
HW		 6609 }
6610
98e6436d
AK		 6611 if (!edid) {
6612 dm_con_state = to_dm_connector_state(connector->state);
6613
6614 amdgpu_dm_connector->min_vfreq = 0;
6615 amdgpu_dm_connector->max_vfreq = 0;
6616 amdgpu_dm_connector->pixel_clock_mhz = 0;
6617
bb47de73 6618 goto update;
98e6436d
AK		 6619 }
6620
8218d7f1
HW		 6621 dm_con_state = to_dm_connector_state(connector->state);
6622
e7b07cee 6623 edid_check_required = false;
c84dec2f 6624 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee 6625 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
bb47de73 6626 goto update;
e7b07cee
HW		 6627 }
6628 if (!adev->dm.freesync_module)
bb47de73 6629 goto update;
e7b07cee
HW		 6630 /*
6631 * if edid non zero restrict freesync only for dp and edp
6632 */
6633 if (edid) {
c84dec2f
HW		 6634 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
6635 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 6636 edid_check_required = is_dp_capable_without_timing_msa(
6637 adev->dm.dc,
c84dec2f 6638 amdgpu_dm_connector);
e7b07cee
HW		 6639 }
6640 }
e7b07cee
HW		 6641 if (edid_check_required == true && (edid->version > 1 ||
6642 (edid->version == 1 && edid->revision > 1))) {
6643 for (i = 0; i < 4; i++) {
6644
6645 timing = &edid->detailed_timings[i];
6646 data = &timing->data.other_data;
6647 range = &data->data.range;
6648 /*
6649 * Check if monitor has continuous frequency mode
6650 */
6651 if (data->type != EDID_DETAIL_MONITOR_RANGE)
6652 continue;
6653 /*
6654 * Check for flag range limits only. If flag == 1 then
6655 * no additional timing information provided.
6656 * Default GTF, GTF Secondary curve and CVT are not
6657 * supported
6658 */
6659 if (range->flags != 1)
6660 continue;
6661
c84dec2f
HW		 6662 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6663 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6664 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 6665 range->pixel_clock_mhz * 10;
6666 break;
6667 }
6668
c84dec2f 6669 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 6670 amdgpu_dm_connector->min_vfreq > 10) {
6671
bb47de73 6672 freesync_capable = true;
e7b07cee
HW		 6673 }
6674 }
bb47de73
NK		 6675
6676update:
6677 if (dm_con_state)
6678 dm_con_state->freesync_capable = freesync_capable;
6679
6680 if (connector->vrr_capable_property)
6681 drm_connector_set_vrr_capable_property(connector,
6682 freesync_capable);
e7b07cee
HW		 6683}
6684
Linux 6.x block layer and io_uring tree(s)