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drm/amd/display: Use DC_LOG_DC in the trasform pixel function
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
f6e03f80 31#include "link_enc_cfg.h"
1dc90497 32#include "dc/inc/core_types.h"
a7669aff 33#include "dal_asic_id.h"
cdca3f21 34#include "dmub/dmub_srv.h"
743b9786
NK		 35#include "dc/inc/hw/dmcu.h"
36#include "dc/inc/hw/abm.h"
9a71c7d3 37#include "dc/dc_dmub_srv.h"
f9b4f20c 38#include "dc/dc_edid_parser.h"
81927e28 39#include "dc/dc_stat.h"
9d83722d 40#include "amdgpu_dm_trace.h"
028c4ccf 41#include "dpcd_defs.h"
bc33f5e5 42#include "link/protocols/link_dpcd.h"
028c4ccf 43#include "link_service_types.h"
1e5d4d8e
RL		 44#include "link/protocols/link_dp_capability.h"
45#include "link/protocols/link_ddc.h"
4562236b
HW		 46
47#include "vid.h"
48#include "amdgpu.h"
a49dcb88 49#include "amdgpu_display.h"
a94d5569 50#include "amdgpu_ucode.h"
4562236b
HW		 51#include "atom.h"
52#include "amdgpu_dm.h"
5d945cbc 53#include "amdgpu_dm_plane.h"
473683a0 54#include "amdgpu_dm_crtc.h"
52704fca 55#include "amdgpu_dm_hdcp.h"
6a99099f 56#include <drm/display/drm_hdcp_helper.h>
e7b07cee 57#include "amdgpu_pm.h"
1f579254 58#include "amdgpu_atombios.h"
4562236b
HW		 59
60#include "amd_shared.h"
61#include "amdgpu_dm_irq.h"
62#include "dm_helpers.h"
e7b07cee 63#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 64#if defined(CONFIG_DEBUG_FS)
65#include "amdgpu_dm_debugfs.h"
66#endif
f4594cd1 67#include "amdgpu_dm_psr.h"
4562236b
HW		 68
69#include "ivsrcid/ivsrcid_vislands30.h"
70
a6276e92 71#include <linux/backlight.h>
4562236b
HW		 72#include <linux/module.h>
73#include <linux/moduleparam.h>
e7b07cee 74#include <linux/types.h>
97028037 75#include <linux/pm_runtime.h>
09d21852 76#include <linux/pci.h>
a94d5569 77#include <linux/firmware.h>
6ce8f316 78#include <linux/component.h>
57b9f338 79#include <linux/dmi.h>
4562236b 80
da68386d 81#include <drm/display/drm_dp_mst_helper.h>
4fc8cb47 82#include <drm/display/drm_hdmi_helper.h>
4562236b 83#include <drm/drm_atomic.h>
674e78ac 84#include <drm/drm_atomic_uapi.h>
4562236b 85#include <drm/drm_atomic_helper.h>
90bb087f 86#include <drm/drm_blend.h>
09d21852 87#include <drm/drm_fourcc.h>
e7b07cee 88#include <drm/drm_edid.h>
09d21852 89#include <drm/drm_vblank.h>
6ce8f316 90#include <drm/drm_audio_component.h>
047de3f1 91#include <drm/drm_gem_atomic_helper.h>
30c63715 92#include <drm/drm_plane_helper.h>
4562236b 93
da11ef83
HG		 94#include <acpi/video.h>
95
5527cd06 96#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
ff5ef992 97
ad941f7a
FX		 98#include "dcn/dcn_1_0_offset.h"
99#include "dcn/dcn_1_0_sh_mask.h"
407e7517 100#include "soc15_hw_ip.h"
543036a2 101#include "soc15_common.h"
407e7517 102#include "vega10_ip_offset.h"
ff5ef992 103
543036a2
AP		 104#include "gc/gc_11_0_0_offset.h"
105#include "gc/gc_11_0_0_sh_mask.h"
106
e7b07cee 107#include "modules/inc/mod_freesync.h"
bbf854dc 108#include "modules/power/power_helpers.h"
e7b07cee 109
743b9786
NK		 110#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
111MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
79037324
BL		 112#define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
113MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
5ce868fc
BL		 114#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
115MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
71c0fd92
RL		 116#define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
117MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
469989ca
RL		 118#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
119MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
2a411205
BL		 120#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
121MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
656fe9b6
AP		 122#define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
123MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
1ebcaebd
NK		 124#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
125MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
e850f6b1
RL		 126#define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
127MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
b5b8ed44
QZ		 128#define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
129MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
de7cc1b4
PL		 130#define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
131MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
2200eb9e 132
577359ca
AP		 133#define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
134MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
135#define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
136MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
137
a94d5569
DF		 138#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
139MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 140
5ea23931
RL		 141#define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
142MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
143
8c7aea40
NK		 144/* Number of bytes in PSP header for firmware. */
145#define PSP_HEADER_BYTES 0x100
146
147/* Number of bytes in PSP footer for firmware. */
148#define PSP_FOOTER_BYTES 0x100
149
b8592b48
LL		 150/**
151 * DOC: overview
152 *
153 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
ec5c0ffa 154 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
b8592b48
LL		 155 * requests into DC requests, and DC responses into DRM responses.
156 *
157 * The root control structure is &struct amdgpu_display_manager.
158 */
159
7578ecda
AD		 160/* basic init/fini API */
161static int amdgpu_dm_init(struct amdgpu_device *adev);
162static void amdgpu_dm_fini(struct amdgpu_device *adev);
fe8858bb 163static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
7578ecda 164
0f877894
OV		 165static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
166{
167 switch (link->dpcd_caps.dongle_type) {
168 case DISPLAY_DONGLE_NONE:
169 return DRM_MODE_SUBCONNECTOR_Native;
170 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
171 return DRM_MODE_SUBCONNECTOR_VGA;
172 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
173 case DISPLAY_DONGLE_DP_DVI_DONGLE:
174 return DRM_MODE_SUBCONNECTOR_DVID;
175 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
176 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
177 return DRM_MODE_SUBCONNECTOR_HDMIA;
178 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
179 default:
180 return DRM_MODE_SUBCONNECTOR_Unknown;
181 }
182}
183
184static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
185{
186 struct dc_link *link = aconnector->dc_link;
187 struct drm_connector *connector = &aconnector->base;
188 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
189
190 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
191 return;
192
193 if (aconnector->dc_sink)
194 subconnector = get_subconnector_type(link);
195
196 drm_object_property_set_value(&connector->base,
197 connector->dev->mode_config.dp_subconnector_property,
198 subconnector);
199}
200
1f6010a9
DF		 201/*
202 * initializes drm_device display related structures, based on the information
7578ecda
AD		 203 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
204 * drm_encoder, drm_mode_config
205 *
206 * Returns 0 on success
207 */
208static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
209/* removes and deallocates the drm structures, created by the above function */
210static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
211
7578ecda
AD		 212static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
213 struct amdgpu_dm_connector *amdgpu_dm_connector,
ae67558b 214 u32 link_index,
7578ecda
AD		 215 struct amdgpu_encoder *amdgpu_encoder);
216static int amdgpu_dm_encoder_init(struct drm_device *dev,
217 struct amdgpu_encoder *aencoder,
218 uint32_t link_index);
219
220static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
221
7578ecda
AD		 222static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
223
224static int amdgpu_dm_atomic_check(struct drm_device *dev,
225 struct drm_atomic_state *state);
226
e27c41d5 227static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
c40a09e5 228static void handle_hpd_rx_irq(void *param);
e27c41d5 229
a85ba005
NC		 230static bool
231is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
232 struct drm_crtc_state *new_crtc_state);
4562236b
HW		 233/*
234 * dm_vblank_get_counter
235 *
236 * @brief
237 * Get counter for number of vertical blanks
238 *
239 * @param
240 * struct amdgpu_device *adev - [in] desired amdgpu device
241 * int disp_idx - [in] which CRTC to get the counter from
242 *
243 * @return
244 * Counter for vertical blanks
245 */
246static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
247{
248 if (crtc >= adev->mode_info.num_crtc)
249 return 0;
250 else {
251 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
252
585d450c 253 if (acrtc->dm_irq_params.stream == NULL) {
0971c40e
HW		 254 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
255 crtc);
4562236b
HW		 256 return 0;
257 }
258
585d450c 259 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
4562236b
HW		 260 }
261}
262
263static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 264 u32 *vbl, u32 *position)
4562236b 265{
ae67558b 266 u32 v_blank_start, v_blank_end, h_position, v_position;
81c50963 267
4562236b
HW		 268 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
269 return -EINVAL;
270 else {
271 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
272
585d450c 273 if (acrtc->dm_irq_params.stream == NULL) {
0971c40e
HW		 274 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
275 crtc);
4562236b
HW		 276 return 0;
277 }
278
81c50963
ST		 279 /*
280 * TODO rework base driver to use values directly.
281 * for now parse it back into reg-format
282 */
585d450c 283 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
81c50963
ST		 284 &v_blank_start,
285 &v_blank_end,
286 &h_position,
287 &v_position);
288
e806208d
AG		 289 *position = v_position | (h_position << 16);
290 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 291 }
292
293 return 0;
294}
295
296static bool dm_is_idle(void *handle)
297{
298 /* XXX todo */
299 return true;
300}
301
302static int dm_wait_for_idle(void *handle)
303{
304 /* XXX todo */
305 return 0;
306}
307
308static bool dm_check_soft_reset(void *handle)
309{
310 return false;
311}
312
313static int dm_soft_reset(void *handle)
314{
315 /* XXX todo */
316 return 0;
317}
318
3ee6b26b
AD		 319static struct amdgpu_crtc *
320get_crtc_by_otg_inst(struct amdgpu_device *adev,
321 int otg_inst)
4562236b 322{
4a580877 323 struct drm_device *dev = adev_to_drm(adev);
4562236b
HW		 324 struct drm_crtc *crtc;
325 struct amdgpu_crtc *amdgpu_crtc;
326
bcd74374 327 if (WARN_ON(otg_inst == -1))
4562236b 328 return adev->mode_info.crtcs[0];
4562236b
HW		 329
330 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
331 amdgpu_crtc = to_amdgpu_crtc(crtc);
332
333 if (amdgpu_crtc->otg_inst == otg_inst)
334 return amdgpu_crtc;
335 }
336
337 return NULL;
338}
339
a85ba005
NC		 340static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
341 struct dm_crtc_state *new_state)
342{
343 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
344 return true;
345 else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
346 return true;
347 else
348 return false;
349}
350
b8e8c934
HW		 351/**
352 * dm_pflip_high_irq() - Handle pageflip interrupt
353 * @interrupt_params: ignored
354 *
355 * Handles the pageflip interrupt by notifying all interested parties
356 * that the pageflip has been completed.
357 */
4562236b
HW		 358static void dm_pflip_high_irq(void *interrupt_params)
359{
4562236b
HW		 360 struct amdgpu_crtc *amdgpu_crtc;
361 struct common_irq_params *irq_params = interrupt_params;
362 struct amdgpu_device *adev = irq_params->adev;
363 unsigned long flags;
71bbe51a 364 struct drm_pending_vblank_event *e;
ae67558b 365 u32 vpos, hpos, v_blank_start, v_blank_end;
71bbe51a 366 bool vrr_active;
4562236b
HW		 367
368 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
369
370 /* IRQ could occur when in initial stage */
1f6010a9 371 /* TODO work and BO cleanup */
4562236b 372 if (amdgpu_crtc == NULL) {
cb2318b7 373 DC_LOG_PFLIP("CRTC is null, returning.\n");
4562236b
HW		 374 return;
375 }
376
4a580877 377 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
4562236b
HW		 378
379 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
cb2318b7 380 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
4562236b
HW		 381 amdgpu_crtc->pflip_status,
382 AMDGPU_FLIP_SUBMITTED,
383 amdgpu_crtc->crtc_id,
384 amdgpu_crtc);
4a580877 385 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
4562236b
HW		 386 return;
387 }
388
71bbe51a
MK		 389 /* page flip completed. */
390 e = amdgpu_crtc->event;
391 amdgpu_crtc->event = NULL;
4562236b 392
bcd74374 393 WARN_ON(!e);
1159898a 394
585d450c 395 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
71bbe51a
MK		 396
397 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
398 if (!vrr_active ||
585d450c 399 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
71bbe51a
MK		 400 &v_blank_end, &hpos, &vpos) ||
401 (vpos < v_blank_start)) {
402 /* Update to correct count and vblank timestamp if racing with
403 * vblank irq. This also updates to the correct vblank timestamp
404 * even in VRR mode, as scanout is past the front-porch atm.
405 */
406 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
1159898a 407
71bbe51a
MK		 408 /* Wake up userspace by sending the pageflip event with proper
409 * count and timestamp of vblank of flip completion.
410 */
411 if (e) {
412 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
413
414 /* Event sent, so done with vblank for this flip */
415 drm_crtc_vblank_put(&amdgpu_crtc->base);
416 }
417 } else if (e) {
418 /* VRR active and inside front-porch: vblank count and
419 * timestamp for pageflip event will only be up to date after
420 * drm_crtc_handle_vblank() has been executed from late vblank
421 * irq handler after start of back-porch (vline 0). We queue the
422 * pageflip event for send-out by drm_crtc_handle_vblank() with
423 * updated timestamp and count, once it runs after us.
424 *
425 * We need to open-code this instead of using the helper
426 * drm_crtc_arm_vblank_event(), as that helper would
427 * call drm_crtc_accurate_vblank_count(), which we must
428 * not call in VRR mode while we are in front-porch!
429 */
430
431 /* sequence will be replaced by real count during send-out. */
432 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
433 e->pipe = amdgpu_crtc->crtc_id;
434
4a580877 435 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
71bbe51a
MK		 436 e = NULL;
437 }
4562236b 438
fdd1fe57
MK		 439 /* Keep track of vblank of this flip for flip throttling. We use the
440 * cooked hw counter, as that one incremented at start of this vblank
441 * of pageflip completion, so last_flip_vblank is the forbidden count
442 * for queueing new pageflips if vsync + VRR is enabled.
443 */
5d1c59c4 444 amdgpu_crtc->dm_irq_params.last_flip_vblank =
e3eff4b5 445 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
fdd1fe57 446
54f5499a 447 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4a580877 448 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
4562236b 449
cb2318b7
VL		 450 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
451 amdgpu_crtc->crtc_id, amdgpu_crtc,
452 vrr_active, (int) !e);
4562236b
HW		 453}
454
d2574c33
MK		 455static void dm_vupdate_high_irq(void *interrupt_params)
456{
457 struct common_irq_params *irq_params = interrupt_params;
458 struct amdgpu_device *adev = irq_params->adev;
459 struct amdgpu_crtc *acrtc;
47588233
RS		 460 struct drm_device *drm_dev;
461 struct drm_vblank_crtc *vblank;
462 ktime_t frame_duration_ns, previous_timestamp;
09aef2c4 463 unsigned long flags;
585d450c 464 int vrr_active;
d2574c33
MK		 465
466 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
467
468 if (acrtc) {
585d450c 469 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
47588233
RS		 470 drm_dev = acrtc->base.dev;
471 vblank = &drm_dev->vblank[acrtc->base.index];
472 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
473 frame_duration_ns = vblank->time - previous_timestamp;
474
475 if (frame_duration_ns > 0) {
476 trace_amdgpu_refresh_rate_track(acrtc->base.index,
477 frame_duration_ns,
478 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
479 atomic64_set(&irq_params->previous_timestamp, vblank->time);
480 }
d2574c33 481
cb2318b7 482 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
7f2be468 483 acrtc->crtc_id,
585d450c 484 vrr_active);
d2574c33
MK		 485
486 /* Core vblank handling is done here after end of front-porch in
487 * vrr mode, as vblank timestamping will give valid results
488 * while now done after front-porch. This will also deliver
489 * page-flip completion events that have been queued to us
490 * if a pageflip happened inside front-porch.
491 */
585d450c 492 if (vrr_active) {
cc79950b 493 dm_crtc_handle_vblank(acrtc);
09aef2c4
MK		 494
495 /* BTR processing for pre-DCE12 ASICs */
585d450c 496 if (acrtc->dm_irq_params.stream &&
09aef2c4 497 adev->family < AMDGPU_FAMILY_AI) {
4a580877 498 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
09aef2c4
MK		 499 mod_freesync_handle_v_update(
500 adev->dm.freesync_module,
585d450c
AP		 501 acrtc->dm_irq_params.stream,
502 &acrtc->dm_irq_params.vrr_params);
09aef2c4
MK		 503
504 dc_stream_adjust_vmin_vmax(
505 adev->dm.dc,
585d450c
AP		 506 acrtc->dm_irq_params.stream,
507 &acrtc->dm_irq_params.vrr_params.adjust);
4a580877 508 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
09aef2c4
MK		 509 }
510 }
d2574c33
MK		 511 }
512}
513
b8e8c934
HW		 514/**
515 * dm_crtc_high_irq() - Handles CRTC interrupt
2346ef47 516 * @interrupt_params: used for determining the CRTC instance
b8e8c934
HW		 517 *
518 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
519 * event handler.
520 */
4562236b
HW		 521static void dm_crtc_high_irq(void *interrupt_params)
522{
523 struct common_irq_params *irq_params = interrupt_params;
524 struct amdgpu_device *adev = irq_params->adev;
4562236b 525 struct amdgpu_crtc *acrtc;
09aef2c4 526 unsigned long flags;
585d450c 527 int vrr_active;
4562236b 528
b57de80a 529 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
16f17eda
LL		 530 if (!acrtc)
531 return;
532
585d450c 533 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
16f17eda 534
cb2318b7 535 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
585d450c 536 vrr_active, acrtc->dm_irq_params.active_planes);
16f17eda 537
2346ef47
NK		 538 /**
539 * Core vblank handling at start of front-porch is only possible
540 * in non-vrr mode, as only there vblank timestamping will give
541 * valid results while done in front-porch. Otherwise defer it
542 * to dm_vupdate_high_irq after end of front-porch.
543 */
585d450c 544 if (!vrr_active)
cc79950b 545 dm_crtc_handle_vblank(acrtc);
2346ef47
NK		 546
547 /**
548 * Following stuff must happen at start of vblank, for crc
549 * computation and below-the-range btr support in vrr mode.
550 */
16f17eda 551 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
2346ef47
NK		 552
553 /* BTR updates need to happen before VUPDATE on Vega and above. */
554 if (adev->family < AMDGPU_FAMILY_AI)
555 return;
16f17eda 556
4a580877 557 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
16f17eda 558
585d450c
AP		 559 if (acrtc->dm_irq_params.stream &&
560 acrtc->dm_irq_params.vrr_params.supported &&
561 acrtc->dm_irq_params.freesync_config.state ==
562 VRR_STATE_ACTIVE_VARIABLE) {
2346ef47 563 mod_freesync_handle_v_update(adev->dm.freesync_module,
585d450c
AP		 564 acrtc->dm_irq_params.stream,
565 &acrtc->dm_irq_params.vrr_params);
16f17eda 566
585d450c
AP		 567 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
568 &acrtc->dm_irq_params.vrr_params.adjust);
16f17eda
LL		 569 }
570
2b5aed9a
MK		 571 /*
572 * If there aren't any active_planes then DCH HUBP may be clock-gated.
573 * In that case, pageflip completion interrupts won't fire and pageflip
574 * completion events won't get delivered. Prevent this by sending
575 * pending pageflip events from here if a flip is still pending.
576 *
577 * If any planes are enabled, use dm_pflip_high_irq() instead, to
578 * avoid race conditions between flip programming and completion,
579 * which could cause too early flip completion events.
580 */
2346ef47
NK		 581 if (adev->family >= AMDGPU_FAMILY_RV &&
582 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
585d450c 583 acrtc->dm_irq_params.active_planes == 0) {
16f17eda
LL		 584 if (acrtc->event) {
585 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
586 acrtc->event = NULL;
587 drm_crtc_vblank_put(&acrtc->base);
588 }
589 acrtc->pflip_status = AMDGPU_FLIP_NONE;
590 }
591
4a580877 592 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
16f17eda
LL		 593}
594
9e1178ef 595#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
86bc2219
WL		 596/**
597 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
598 * DCN generation ASICs
48e01bf4 599 * @interrupt_params: interrupt parameters
86bc2219
WL		 600 *
601 * Used to set crc window/read out crc value at vertical line 0 position
602 */
86bc2219
WL		 603static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
604{
605 struct common_irq_params *irq_params = interrupt_params;
606 struct amdgpu_device *adev = irq_params->adev;
607 struct amdgpu_crtc *acrtc;
608
609 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
610
611 if (!acrtc)
612 return;
613
614 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
615}
433e5dec 616#endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
86bc2219 617
e27c41d5 618/**
03f2abb0 619 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
e27c41d5
JS		 620 * @adev: amdgpu_device pointer
621 * @notify: dmub notification structure
622 *
623 * Dmub AUX or SET_CONFIG command completion processing callback
624 * Copies dmub notification to DM which is to be read by AUX command.
625 * issuing thread and also signals the event to wake up the thread.
626 */
240e6d25
IB		 627static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
628 struct dmub_notification *notify)
e27c41d5
JS		 629{
630 if (adev->dm.dmub_notify)
631 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
632 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
633 complete(&adev->dm.dmub_aux_transfer_done);
634}
635
636/**
637 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
638 * @adev: amdgpu_device pointer
639 * @notify: dmub notification structure
640 *
641 * Dmub Hpd interrupt processing callback. Gets displayindex through the
642 * ink index and calls helper to do the processing.
643 */
240e6d25
IB		 644static void dmub_hpd_callback(struct amdgpu_device *adev,
645 struct dmub_notification *notify)
e27c41d5
JS		 646{
647 struct amdgpu_dm_connector *aconnector;
f6e03f80 648 struct amdgpu_dm_connector *hpd_aconnector = NULL;
e27c41d5
JS		 649 struct drm_connector *connector;
650 struct drm_connector_list_iter iter;
651 struct dc_link *link;
ae67558b 652 u8 link_index = 0;
978ffac8 653 struct drm_device *dev;
e27c41d5
JS		 654
655 if (adev == NULL)
656 return;
657
658 if (notify == NULL) {
659 DRM_ERROR("DMUB HPD callback notification was NULL");
660 return;
661 }
662
663 if (notify->link_index > adev->dm.dc->link_count) {
664 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
665 return;
666 }
667
e27c41d5 668 link_index = notify->link_index;
e27c41d5 669 link = adev->dm.dc->links[link_index];
978ffac8 670 dev = adev->dm.ddev;
e27c41d5
JS		 671
672 drm_connector_list_iter_begin(dev, &iter);
673 drm_for_each_connector_iter(connector, &iter) {
674 aconnector = to_amdgpu_dm_connector(connector);
675 if (link && aconnector->dc_link == link) {
676 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
f6e03f80 677 hpd_aconnector = aconnector;
e27c41d5
JS		 678 break;
679 }
680 }
681 drm_connector_list_iter_end(&iter);
e27c41d5 682
c40a09e5
NK		 683 if (hpd_aconnector) {
684 if (notify->type == DMUB_NOTIFICATION_HPD)
685 handle_hpd_irq_helper(hpd_aconnector);
686 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
687 handle_hpd_rx_irq(hpd_aconnector);
688 }
e27c41d5
JS		 689}
690
691/**
692 * register_dmub_notify_callback - Sets callback for DMUB notify
693 * @adev: amdgpu_device pointer
694 * @type: Type of dmub notification
695 * @callback: Dmub interrupt callback function
696 * @dmub_int_thread_offload: offload indicator
697 *
698 * API to register a dmub callback handler for a dmub notification
699 * Also sets indicator whether callback processing to be offloaded.
700 * to dmub interrupt handling thread
701 * Return: true if successfully registered, false if there is existing registration
702 */
240e6d25
IB		 703static bool register_dmub_notify_callback(struct amdgpu_device *adev,
704 enum dmub_notification_type type,
705 dmub_notify_interrupt_callback_t callback,
706 bool dmub_int_thread_offload)
e27c41d5
JS		 707{
708 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
709 adev->dm.dmub_callback[type] = callback;
710 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
711 } else
712 return false;
713
714 return true;
715}
716
717static void dm_handle_hpd_work(struct work_struct *work)
718{
719 struct dmub_hpd_work *dmub_hpd_wrk;
720
721 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
722
723 if (!dmub_hpd_wrk->dmub_notify) {
724 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
725 return;
726 }
727
728 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
729 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
730 dmub_hpd_wrk->dmub_notify);
731 }
094b21c1
JS		 732
733 kfree(dmub_hpd_wrk->dmub_notify);
e27c41d5
JS		 734 kfree(dmub_hpd_wrk);
735
736}
737
e25515e2 738#define DMUB_TRACE_MAX_READ 64
81927e28
JS		 739/**
740 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
741 * @interrupt_params: used for determining the Outbox instance
742 *
743 * Handles the Outbox Interrupt
744 * event handler.
745 */
81927e28
JS		 746static void dm_dmub_outbox1_low_irq(void *interrupt_params)
747{
748 struct dmub_notification notify;
749 struct common_irq_params *irq_params = interrupt_params;
750 struct amdgpu_device *adev = irq_params->adev;
751 struct amdgpu_display_manager *dm = &adev->dm;
752 struct dmcub_trace_buf_entry entry = { 0 };
ae67558b 753 u32 count = 0;
e27c41d5 754 struct dmub_hpd_work *dmub_hpd_wrk;
f6e03f80 755 struct dc_link *plink = NULL;
81927e28 756
f6e03f80
JS		 757 if (dc_enable_dmub_notifications(adev->dm.dc) &&
758 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
e27c41d5 759
f6e03f80
JS		 760 do {
761 dc_stat_get_dmub_notification(adev->dm.dc, &notify);
a35faec3 762 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
f6e03f80
JS		 763 DRM_ERROR("DM: notify type %d invalid!", notify.type);
764 continue;
765 }
c40a09e5
NK		 766 if (!dm->dmub_callback[notify.type]) {
767 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
768 continue;
769 }
f6e03f80 770 if (dm->dmub_thread_offload[notify.type] == true) {
094b21c1
JS		 771 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
772 if (!dmub_hpd_wrk) {
773 DRM_ERROR("Failed to allocate dmub_hpd_wrk");
774 return;
775 }
776 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
777 if (!dmub_hpd_wrk->dmub_notify) {
778 kfree(dmub_hpd_wrk);
779 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
780 return;
781 }
782 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
783 if (dmub_hpd_wrk->dmub_notify)
784 memcpy(dmub_hpd_wrk->dmub_notify, &notify, sizeof(struct dmub_notification));
f6e03f80
JS		 785 dmub_hpd_wrk->adev = adev;
786 if (notify.type == DMUB_NOTIFICATION_HPD) {
787 plink = adev->dm.dc->links[notify.link_index];
788 if (plink) {
789 plink->hpd_status =
b97788e5 790 notify.hpd_status == DP_HPD_PLUG;
f6e03f80 791 }
e27c41d5 792 }
f6e03f80
JS		 793 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
794 } else {
795 dm->dmub_callback[notify.type](adev, &notify);
796 }
797 } while (notify.pending_notification);
81927e28
JS		 798 }
799
800
801 do {
802 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
803 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
804 entry.param0, entry.param1);
805
806 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
807 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
808 } else
809 break;
810
811 count++;
812
813 } while (count <= DMUB_TRACE_MAX_READ);
814
f6e03f80
JS		 815 if (count > DMUB_TRACE_MAX_READ)
816 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
81927e28 817}
86bc2219 818
4562236b
HW		 819static int dm_set_clockgating_state(void *handle,
820 enum amd_clockgating_state state)
821{
822 return 0;
823}
824
825static int dm_set_powergating_state(void *handle,
826 enum amd_powergating_state state)
827{
828 return 0;
829}
830
831/* Prototypes of private functions */
832static int dm_early_init(void* handle);
833
a32e24b4 834/* Allocate memory for FBC compressed data */
3e332d3a 835static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 836{
3e332d3a 837 struct drm_device *dev = connector->dev;
1348969a 838 struct amdgpu_device *adev = drm_to_adev(dev);
4d154b85 839 struct dm_compressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 840 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
841 struct drm_display_mode *mode;
42e67c3b
RL		 842 unsigned long max_size = 0;
843
844 if (adev->dm.dc->fbc_compressor == NULL)
845 return;
a32e24b4 846
3e332d3a 847 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 848 return;
849
3e332d3a
RL		 850 if (compressor->bo_ptr)
851 return;
42e67c3b 852
42e67c3b 853
3e332d3a
RL		 854 list_for_each_entry(mode, &connector->modes, head) {
855 if (max_size < mode->htotal * mode->vtotal)
856 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 857 }
858
859 if (max_size) {
860 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 861 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 862 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 863
864 if (r)
42e67c3b
RL		 865 DRM_ERROR("DM: Failed to initialize FBC\n");
866 else {
867 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
868 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
869 }
870
a32e24b4
RL		 871 }
872
873}
a32e24b4 874
6ce8f316
NK		 875static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
876 int pipe, bool *enabled,
877 unsigned char *buf, int max_bytes)
878{
879 struct drm_device *dev = dev_get_drvdata(kdev);
1348969a 880 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 881 struct drm_connector *connector;
882 struct drm_connector_list_iter conn_iter;
883 struct amdgpu_dm_connector *aconnector;
884 int ret = 0;
885
886 *enabled = false;
887
888 mutex_lock(&adev->dm.audio_lock);
889
890 drm_connector_list_iter_begin(dev, &conn_iter);
891 drm_for_each_connector_iter(connector, &conn_iter) {
892 aconnector = to_amdgpu_dm_connector(connector);
893 if (aconnector->audio_inst != port)
894 continue;
895
896 *enabled = true;
897 ret = drm_eld_size(connector->eld);
898 memcpy(buf, connector->eld, min(max_bytes, ret));
899
900 break;
901 }
902 drm_connector_list_iter_end(&conn_iter);
903
904 mutex_unlock(&adev->dm.audio_lock);
905
906 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
907
908 return ret;
909}
910
911static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
912 .get_eld = amdgpu_dm_audio_component_get_eld,
913};
914
915static int amdgpu_dm_audio_component_bind(struct device *kdev,
916 struct device *hda_kdev, void *data)
917{
918 struct drm_device *dev = dev_get_drvdata(kdev);
1348969a 919 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 920 struct drm_audio_component *acomp = data;
921
922 acomp->ops = &amdgpu_dm_audio_component_ops;
923 acomp->dev = kdev;
924 adev->dm.audio_component = acomp;
925
926 return 0;
927}
928
929static void amdgpu_dm_audio_component_unbind(struct device *kdev,
930 struct device *hda_kdev, void *data)
931{
932 struct drm_device *dev = dev_get_drvdata(kdev);
1348969a 933 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 934 struct drm_audio_component *acomp = data;
935
936 acomp->ops = NULL;
937 acomp->dev = NULL;
938 adev->dm.audio_component = NULL;
939}
940
941static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
942 .bind = amdgpu_dm_audio_component_bind,
943 .unbind = amdgpu_dm_audio_component_unbind,
944};
945
946static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
947{
948 int i, ret;
949
950 if (!amdgpu_audio)
951 return 0;
952
953 adev->mode_info.audio.enabled = true;
954
955 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
956
957 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
958 adev->mode_info.audio.pin[i].channels = -1;
959 adev->mode_info.audio.pin[i].rate = -1;
960 adev->mode_info.audio.pin[i].bits_per_sample = -1;
961 adev->mode_info.audio.pin[i].status_bits = 0;
962 adev->mode_info.audio.pin[i].category_code = 0;
963 adev->mode_info.audio.pin[i].connected = false;
964 adev->mode_info.audio.pin[i].id =
965 adev->dm.dc->res_pool->audios[i]->inst;
966 adev->mode_info.audio.pin[i].offset = 0;
967 }
968
969 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
970 if (ret < 0)
971 return ret;
972
973 adev->dm.audio_registered = true;
974
975 return 0;
976}
977
978static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
979{
980 if (!amdgpu_audio)
981 return;
982
983 if (!adev->mode_info.audio.enabled)
984 return;
985
986 if (adev->dm.audio_registered) {
987 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
988 adev->dm.audio_registered = false;
989 }
990
991 /* TODO: Disable audio? */
992
993 adev->mode_info.audio.enabled = false;
994}
995
dfd84d90 996static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
6ce8f316
NK		 997{
998 struct drm_audio_component *acomp = adev->dm.audio_component;
999
1000 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1001 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1002
1003 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1004 pin, -1);
1005 }
1006}
1007
743b9786
NK		 1008static int dm_dmub_hw_init(struct amdgpu_device *adev)
1009{
743b9786
NK		 1010 const struct dmcub_firmware_header_v1_0 *hdr;
1011 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
8c7aea40 1012 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
743b9786
NK		 1013 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1014 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1015 struct abm *abm = adev->dm.dc->res_pool->abm;
743b9786
NK		 1016 struct dmub_srv_hw_params hw_params;
1017 enum dmub_status status;
1018 const unsigned char *fw_inst_const, *fw_bss_data;
ae67558b 1019 u32 i, fw_inst_const_size, fw_bss_data_size;
743b9786
NK		 1020 bool has_hw_support;
1021
1022 if (!dmub_srv)
1023 /* DMUB isn't supported on the ASIC. */
1024 return 0;
1025
8c7aea40
NK		 1026 if (!fb_info) {
1027 DRM_ERROR("No framebuffer info for DMUB service.\n");
1028 return -EINVAL;
1029 }
1030
743b9786
NK		 1031 if (!dmub_fw) {
1032 /* Firmware required for DMUB support. */
1033 DRM_ERROR("No firmware provided for DMUB.\n");
1034 return -EINVAL;
1035 }
1036
1037 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1038 if (status != DMUB_STATUS_OK) {
1039 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1040 return -EINVAL;
1041 }
1042
1043 if (!has_hw_support) {
1044 DRM_INFO("DMUB unsupported on ASIC\n");
1045 return 0;
1046 }
1047
47e62dbd
NK		 1048 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1049 status = dmub_srv_hw_reset(dmub_srv);
1050 if (status != DMUB_STATUS_OK)
1051 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1052
743b9786
NK		 1053 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1054
743b9786
NK		 1055 fw_inst_const = dmub_fw->data +
1056 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
8c7aea40 1057 PSP_HEADER_BYTES;
743b9786
NK		 1058
1059 fw_bss_data = dmub_fw->data +
1060 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1061 le32_to_cpu(hdr->inst_const_bytes);
1062
1063 /* Copy firmware and bios info into FB memory. */
8c7aea40
NK		 1064 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1065 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1066
1067 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1068
ddde28a5
HW		 1069 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1070 * amdgpu_ucode_init_single_fw will load dmub firmware
1071 * fw_inst_const part to cw0; otherwise, the firmware back door load
1072 * will be done by dm_dmub_hw_init
1073 */
1074 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1075 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1076 fw_inst_const_size);
1077 }
1078
a576b345
NK		 1079 if (fw_bss_data_size)
1080 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1081 fw_bss_data, fw_bss_data_size);
ddde28a5
HW		 1082
1083 /* Copy firmware bios info into FB memory. */
8c7aea40
NK		 1084 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1085 adev->bios_size);
1086
1087 /* Reset regions that need to be reset. */
1088 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1089 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1090
1091 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1092 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1093
1094 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1095 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
743b9786
NK		 1096
1097 /* Initialize hardware. */
1098 memset(&hw_params, 0, sizeof(hw_params));
1099 hw_params.fb_base = adev->gmc.fb_start;
949933b0 1100 hw_params.fb_offset = adev->vm_manager.vram_base_offset;
743b9786 1101
31a7f4bb
HW		 1102 /* backdoor load firmware and trigger dmub running */
1103 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1104 hw_params.load_inst_const = true;
1105
743b9786
NK		 1106 if (dmcu)
1107 hw_params.psp_version = dmcu->psp_version;
1108
8c7aea40
NK		 1109 for (i = 0; i < fb_info->num_fb; ++i)
1110 hw_params.fb[i] = &fb_info->fb[i];
743b9786 1111
3b36f50d 1112 switch (adev->ip_versions[DCE_HWIP][0]) {
f6aa84b8
RL		 1113 case IP_VERSION(3, 1, 3):
1114 case IP_VERSION(3, 1, 4):
3b36f50d 1115 hw_params.dpia_supported = true;
7367540b 1116 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
5b109397
JS		 1117 break;
1118 default:
1119 break;
1120 }
1121
743b9786
NK		 1122 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1123 if (status != DMUB_STATUS_OK) {
1124 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1125 return -EINVAL;
1126 }
1127
1128 /* Wait for firmware load to finish. */
1129 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1130 if (status != DMUB_STATUS_OK)
1131 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1132
1133 /* Init DMCU and ABM if available. */
1134 if (dmcu && abm) {
1135 dmcu->funcs->dmcu_init(dmcu);
1136 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1137 }
1138
051b7887
RL		 1139 if (!adev->dm.dc->ctx->dmub_srv)
1140 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
9a71c7d3
NK		 1141 if (!adev->dm.dc->ctx->dmub_srv) {
1142 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1143 return -ENOMEM;
1144 }
1145
743b9786
NK		 1146 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1147 adev->dm.dmcub_fw_version);
1148
1149 return 0;
1150}
1151
79d6b935
NK		 1152static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1153{
1154 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1155 enum dmub_status status;
1156 bool init;
1157
1158 if (!dmub_srv) {
1159 /* DMUB isn't supported on the ASIC. */
1160 return;
1161 }
1162
1163 status = dmub_srv_is_hw_init(dmub_srv, &init);
1164 if (status != DMUB_STATUS_OK)
1165 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1166
1167 if (status == DMUB_STATUS_OK && init) {
1168 /* Wait for firmware load to finish. */
1169 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1170 if (status != DMUB_STATUS_OK)
1171 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1172 } else {
1173 /* Perform the full hardware initialization. */
1174 dm_dmub_hw_init(adev);
1175 }
1176}
1177
c0fb85ae 1178static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
c44a22b3 1179{
ae67558b
SS		 1180 u64 pt_base;
1181 u32 logical_addr_low;
1182 u32 logical_addr_high;
1183 u32 agp_base, agp_bot, agp_top;
c0fb85ae 1184 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
c44a22b3 1185
a0f884f5
NK		 1186 memset(pa_config, 0, sizeof(*pa_config));
1187
c0fb85ae
YZ		 1188 agp_base = 0;
1189 agp_bot = adev->gmc.agp_start >> 24;
1190 agp_top = adev->gmc.agp_end >> 24;
c44a22b3 1191
0294868f
AD		 1192 /* AGP aperture is disabled */
1193 if (agp_bot == agp_top) {
4d2c6e89 1194 logical_addr_low = adev->gmc.fb_start >> 18;
0294868f
AD		 1195 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1196 /*
1197 * Raven2 has a HW issue that it is unable to use the vram which
1198 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1199 * workaround that increase system aperture high address (add 1)
1200 * to get rid of the VM fault and hardware hang.
1201 */
1202 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1203 else
4d2c6e89 1204 logical_addr_high = adev->gmc.fb_end >> 18;
0294868f 1205 } else {
4d2c6e89 1206 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
0294868f
AD		 1207 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1208 /*
1209 * Raven2 has a HW issue that it is unable to use the vram which
1210 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1211 * workaround that increase system aperture high address (add 1)
1212 * to get rid of the VM fault and hardware hang.
1213 */
1214 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1215 else
1216 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1217 }
1218
1219 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
c44a22b3 1220
c0fb85ae
YZ		 1221 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1222 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1223 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1224 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1225 page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1226 page_table_base.low_part = lower_32_bits(pt_base);
c44a22b3 1227
c0fb85ae
YZ		 1228 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1229 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1230
1231 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1232 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1233 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1234
1235 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
949933b0 1236 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
c0fb85ae
YZ		 1237 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1238
1239 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1240 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1241 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1242
40e9f3f0 1243 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
c44a22b3 1244
c44a22b3 1245}
cae5c1ab 1246
028c4ccf
QZ		 1247static void force_connector_state(
1248 struct amdgpu_dm_connector *aconnector,
1249 enum drm_connector_force force_state)
1250{
1251 struct drm_connector *connector = &aconnector->base;
1252
1253 mutex_lock(&connector->dev->mode_config.mutex);
1254 aconnector->base.force = force_state;
1255 mutex_unlock(&connector->dev->mode_config.mutex);
1256
1257 mutex_lock(&aconnector->hpd_lock);
1258 drm_kms_helper_connector_hotplug_event(connector);
1259 mutex_unlock(&aconnector->hpd_lock);
1260}
1261
8e794421
WL		 1262static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1263{
1264 struct hpd_rx_irq_offload_work *offload_work;
1265 struct amdgpu_dm_connector *aconnector;
1266 struct dc_link *dc_link;
1267 struct amdgpu_device *adev;
1268 enum dc_connection_type new_connection_type = dc_connection_none;
1269 unsigned long flags;
028c4ccf
QZ		 1270 union test_response test_response;
1271
1272 memset(&test_response, 0, sizeof(test_response));
8e794421
WL		 1273
1274 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1275 aconnector = offload_work->offload_wq->aconnector;
1276
1277 if (!aconnector) {
1278 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1279 goto skip;
1280 }
1281
1282 adev = drm_to_adev(aconnector->base.dev);
1283 dc_link = aconnector->dc_link;
1284
1285 mutex_lock(&aconnector->hpd_lock);
54618888 1286 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
8e794421
WL		 1287 DRM_ERROR("KMS: Failed to detect connector\n");
1288 mutex_unlock(&aconnector->hpd_lock);
1289
1290 if (new_connection_type == dc_connection_none)
1291 goto skip;
1292
1293 if (amdgpu_in_reset(adev))
1294 goto skip;
1295
1296 mutex_lock(&adev->dm.dc_lock);
028c4ccf 1297 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
8e794421 1298 dc_link_dp_handle_automated_test(dc_link);
028c4ccf
QZ		 1299
1300 if (aconnector->timing_changed) {
1301 /* force connector disconnect and reconnect */
1302 force_connector_state(aconnector, DRM_FORCE_OFF);
1303 msleep(100);
1304 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1305 }
1306
1307 test_response.bits.ACK = 1;
1308
1309 core_link_write_dpcd(
1310 dc_link,
1311 DP_TEST_RESPONSE,
1312 &test_response.raw,
1313 sizeof(test_response));
1314 }
8e794421 1315 else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
c5a31f17 1316 dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
8e794421 1317 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
e322843e
HW		 1318 /* offload_work->data is from handle_hpd_rx_irq->
1319 * schedule_hpd_rx_offload_work.this is defer handle
1320 * for hpd short pulse. upon here, link status may be
1321 * changed, need get latest link status from dpcd
1322 * registers. if link status is good, skip run link
1323 * training again.
1324 */
1325 union hpd_irq_data irq_data;
1326
1327 memset(&irq_data, 0, sizeof(irq_data));
1328
1329 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1330 * request be added to work queue if link lost at end of dc_link_
1331 * dp_handle_link_loss
1332 */
8e794421
WL		 1333 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1334 offload_work->offload_wq->is_handling_link_loss = false;
1335 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
e322843e 1336
54618888 1337 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
e322843e
HW		 1338 dc_link_check_link_loss_status(dc_link, &irq_data))
1339 dc_link_dp_handle_link_loss(dc_link);
8e794421
WL		 1340 }
1341 mutex_unlock(&adev->dm.dc_lock);
1342
1343skip:
1344 kfree(offload_work);
1345
1346}
1347
1348static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1349{
1350 int max_caps = dc->caps.max_links;
1351 int i = 0;
1352 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1353
1354 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1355
1356 if (!hpd_rx_offload_wq)
1357 return NULL;
1358
1359
1360 for (i = 0; i < max_caps; i++) {
1361 hpd_rx_offload_wq[i].wq =
1362 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1363
1364 if (hpd_rx_offload_wq[i].wq == NULL) {
1365 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
7136f956 1366 goto out_err;
8e794421
WL		 1367 }
1368
1369 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1370 }
1371
1372 return hpd_rx_offload_wq;
7136f956
RM		 1373
1374out_err:
1375 for (i = 0; i < max_caps; i++) {
1376 if (hpd_rx_offload_wq[i].wq)
1377 destroy_workqueue(hpd_rx_offload_wq[i].wq);
1378 }
1379 kfree(hpd_rx_offload_wq);
1380 return NULL;
8e794421
WL		 1381}
1382
3ce51649
AD		 1383struct amdgpu_stutter_quirk {
1384 u16 chip_vendor;
1385 u16 chip_device;
1386 u16 subsys_vendor;
1387 u16 subsys_device;
1388 u8 revision;
1389};
1390
1391static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1392 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1393 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1394 { 0, 0, 0, 0, 0 },
1395};
1396
1397static bool dm_should_disable_stutter(struct pci_dev *pdev)
1398{
1399 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1400
1401 while (p && p->chip_device != 0) {
1402 if (pdev->vendor == p->chip_vendor &&
1403 pdev->device == p->chip_device &&
1404 pdev->subsystem_vendor == p->subsys_vendor &&
1405 pdev->subsystem_device == p->subsys_device &&
1406 pdev->revision == p->revision) {
1407 return true;
1408 }
1409 ++p;
1410 }
1411 return false;
1412}
1413
57b9f338
FZ		 1414static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1415 {
1416 .matches = {
1417 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1418 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1419 },
1420 },
1421 {
1422 .matches = {
1423 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1424 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1425 },
1426 },
1427 {
1428 .matches = {
1429 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1430 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1431 },
1432 },
503dc81c
TL		 1433 {
1434 .matches = {
1435 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1436 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1437 },
1438 },
1439 {
1440 .matches = {
1441 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1442 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1443 },
1444 },
1445 {
1446 .matches = {
1447 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1448 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1449 },
1450 },
1451 {
1452 .matches = {
1453 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1454 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1455 },
1456 },
1457 {
1458 .matches = {
1459 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1460 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1461 },
1462 },
1463 {
1464 .matches = {
1465 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1466 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1467 },
1468 },
57b9f338 1469 {}
503dc81c 1470 /* TODO: refactor this from a fixed table to a dynamic option */
57b9f338
FZ		 1471};
1472
1473static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1474{
1475 const struct dmi_system_id *dmi_id;
1476
1477 dm->aux_hpd_discon_quirk = false;
1478
1479 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1480 if (dmi_id) {
1481 dm->aux_hpd_discon_quirk = true;
1482 DRM_INFO("aux_hpd_discon_quirk attached\n");
1483 }
1484}
1485
7578ecda 1486static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 1487{
1488 struct dc_init_data init_data;
52704fca 1489 struct dc_callback_init init_params;
743b9786 1490 int r;
52704fca 1491
4a580877 1492 adev->dm.ddev = adev_to_drm(adev);
4562236b
HW		 1493 adev->dm.adev = adev;
1494
4562236b
HW		 1495 /* Zero all the fields */
1496 memset(&init_data, 0, sizeof(init_data));
52704fca 1497 memset(&init_params, 0, sizeof(init_params));
4562236b 1498
ead08b95 1499 mutex_init(&adev->dm.dpia_aux_lock);
674e78ac 1500 mutex_init(&adev->dm.dc_lock);
6ce8f316 1501 mutex_init(&adev->dm.audio_lock);
674e78ac 1502
4562236b
HW		 1503 if(amdgpu_dm_irq_init(adev)) {
1504 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1505 goto error;
1506 }
1507
1508 init_data.asic_id.chip_family = adev->family;
1509
2dc31ca1 1510 init_data.asic_id.pci_revision_id = adev->pdev->revision;
4562236b 1511 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
dae66a04 1512 init_data.asic_id.chip_id = adev->pdev->device;
4562236b 1513
770d13b1 1514 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 1515 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1516 init_data.asic_id.atombios_base_address =
1517 adev->mode_info.atom_context->bios;
1518
1519 init_data.driver = adev;
1520
1521 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1522
1523 if (!adev->dm.cgs_device) {
1524 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1525 goto error;
1526 }
1527
1528 init_data.cgs_device = adev->dm.cgs_device;
1529
4562236b
HW		 1530 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1531
fd546bc5
AD		 1532 switch (adev->ip_versions[DCE_HWIP][0]) {
1533 case IP_VERSION(2, 1, 0):
1534 switch (adev->dm.dmcub_fw_version) {
1535 case 0: /* development */
1536 case 0x1: /* linux-firmware.git hash 6d9f399 */
1537 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1538 init_data.flags.disable_dmcu = false;
1539 break;
1540 default:
1541 init_data.flags.disable_dmcu = true;
1542 }
1543 break;
1544 case IP_VERSION(2, 0, 3):
1545 init_data.flags.disable_dmcu = true;
1546 break;
1547 default:
1548 break;
1549 }
1550
60fb100b
AD		 1551 switch (adev->asic_type) {
1552 case CHIP_CARRIZO:
1553 case CHIP_STONEY:
1ebcaebd
NK		 1554 init_data.flags.gpu_vm_support = true;
1555 break;
60fb100b 1556 default:
1d789535 1557 switch (adev->ip_versions[DCE_HWIP][0]) {
559f591d
AD		 1558 case IP_VERSION(1, 0, 0):
1559 case IP_VERSION(1, 0, 1):
a7f520bf
AD		 1560 /* enable S/G on PCO and RV2 */
1561 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1562 (adev->apu_flags & AMD_APU_IS_PICASSO))
1563 init_data.flags.gpu_vm_support = true;
1564 break;
c4029779 1565 case IP_VERSION(2, 1, 0):
c08182f2 1566 case IP_VERSION(3, 0, 1):
8f56a0fe
AD		 1567 case IP_VERSION(3, 1, 2):
1568 case IP_VERSION(3, 1, 3):
69ed0c5d 1569 case IP_VERSION(3, 1, 4):
512e8475 1570 case IP_VERSION(3, 1, 5):
0fe382fb 1571 case IP_VERSION(3, 1, 6):
c08182f2
AD		 1572 init_data.flags.gpu_vm_support = true;
1573 break;
c08182f2
AD		 1574 default:
1575 break;
1576 }
60fb100b
AD		 1577 break;
1578 }
bf0207e1
AD		 1579 if (init_data.flags.gpu_vm_support &&
1580 (amdgpu_sg_display == 0))
1581 init_data.flags.gpu_vm_support = false;
6e227308 1582
a7f520bf
AD		 1583 if (init_data.flags.gpu_vm_support)
1584 adev->mode_info.gpu_vm_support = true;
1585
04b94af4
AD		 1586 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1587 init_data.flags.fbc_support = true;
1588
d99f38ae
AD		 1589 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1590 init_data.flags.multi_mon_pp_mclk_switch = true;
1591
eaf56410
LL		 1592 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1593 init_data.flags.disable_fractional_pwm = true;
a5148245
ZL		 1594
1595 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1596 init_data.flags.edp_no_power_sequencing = true;
eaf56410 1597
12320274
AP		 1598 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1599 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1600 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1601 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
12320274 1602
80c6d680
AP		 1603 /* Disable SubVP + DRR config by default */
1604 init_data.flags.disable_subvp_drr = true;
1605 if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
1606 init_data.flags.disable_subvp_drr = false;
1607
7aba117a 1608 init_data.flags.seamless_boot_edp_requested = false;
78ad75f8 1609
1edf5ae1 1610 if (check_seamless_boot_capability(adev)) {
7aba117a 1611 init_data.flags.seamless_boot_edp_requested = true;
1edf5ae1
ZL		 1612 init_data.flags.allow_seamless_boot_optimization = true;
1613 DRM_INFO("Seamless boot condition check passed\n");
1614 }
1615
a8201902
LM		 1616 init_data.flags.enable_mipi_converter_optimization = true;
1617
e5028e9f 1618 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
2a93292f 1619 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
e5028e9f 1620
0dd79532 1621 INIT_LIST_HEAD(&adev->dm.da_list);
57b9f338
FZ		 1622
1623 retrieve_dmi_info(&adev->dm);
1624
4562236b
HW		 1625 /* Display Core create. */
1626 adev->dm.dc = dc_create(&init_data);
1627
423788c7 1628 if (adev->dm.dc) {
76121231 1629 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 1630 } else {
76121231 1631 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 1632 goto error;
1633 }
4562236b 1634
8a791dab
HW		 1635 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1636 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1637 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1638 }
1639
f99d8762
HW		 1640 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1641 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
3ce51649
AD		 1642 if (dm_should_disable_stutter(adev->pdev))
1643 adev->dm.dc->debug.disable_stutter = true;
f99d8762 1644
8a791dab
HW		 1645 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1646 adev->dm.dc->debug.disable_stutter = true;
1647
2665f63a 1648 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
8a791dab 1649 adev->dm.dc->debug.disable_dsc = true;
2665f63a 1650 }
8a791dab
HW		 1651
1652 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1653 adev->dm.dc->debug.disable_clock_gate = true;
1654
cfb979f7
AP		 1655 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1656 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1657
792a0cdd
LL		 1658 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1659
d1bc26cb
FZ		 1660 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1661 adev->dm.dc->debug.ignore_cable_id = true;
1662
3d8fcc67
WL		 1663 /* TODO: There is a new drm mst change where the freedom of
1664 * vc_next_start_slot update is revoked/moved into drm, instead of in
1665 * driver. This forces us to make sure to get vc_next_start_slot updated
1666 * in drm function each time without considering if mst_state is active
1667 * or not. Otherwise, next time hotplug will give wrong start_slot
1668 * number. We are implementing a temporary solution to even notify drm
1669 * mst deallocation when link is no longer of MST type when uncommitting
1670 * the stream so we will have more time to work on a proper solution.
1671 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1672 * should notify drm to do a complete "reset" of its states and stop
1673 * calling further drm mst functions when link is no longer of an MST
1674 * type. This could happen when we unplug an MST hubs/displays. When
1675 * uncommit stream comes later after unplug, we should just reset
1676 * hardware states only.
1677 */
1678 adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1679
e3834491
FZ		 1680 if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1681 DRM_INFO("DP-HDMI FRL PCON supported\n");
1682
743b9786
NK		 1683 r = dm_dmub_hw_init(adev);
1684 if (r) {
1685 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1686 goto error;
1687 }
1688
bb6785c1
NK		 1689 dc_hardware_init(adev->dm.dc);
1690
8e794421
WL		 1691 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1692 if (!adev->dm.hpd_rx_offload_wq) {
1693 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1694 goto error;
1695 }
1696
3ca001af 1697 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
e6cd859d
AD		 1698 struct dc_phy_addr_space_config pa_config;
1699
0b08c54b 1700 mmhub_read_system_context(adev, &pa_config);
c0fb85ae 1701
0b08c54b
YZ		 1702 // Call the DC init_memory func
1703 dc_setup_system_context(adev->dm.dc, &pa_config);
1704 }
c0fb85ae 1705
4562236b
HW		 1706 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1707 if (!adev->dm.freesync_module) {
1708 DRM_ERROR(
1709 "amdgpu: failed to initialize freesync_module.\n");
1710 } else
f1ad2f5e 1711 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 1712 adev->dm.freesync_module);
1713
e277adc5
LSL		 1714 amdgpu_dm_init_color_mod();
1715
ea3b4242 1716 if (adev->dm.dc->caps.max_links > 0) {
09a5df6c
NK		 1717 adev->dm.vblank_control_workqueue =
1718 create_singlethread_workqueue("dm_vblank_control_workqueue");
1719 if (!adev->dm.vblank_control_workqueue)
ea3b4242 1720 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
ea3b4242 1721 }
ea3b4242 1722
c08182f2 1723 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
e50dc171 1724 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
52704fca 1725
96a3b32e
BL		 1726 if (!adev->dm.hdcp_workqueue)
1727 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1728 else
1729 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
52704fca 1730
96a3b32e
BL		 1731 dc_init_callbacks(adev->dm.dc, &init_params);
1732 }
9a65df19 1733#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
b8ff7e08 1734 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
cbd8f20b
AL		 1735 if (!adev->dm.secure_display_ctxs) {
1736 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1737 }
52704fca 1738#endif
11d526f1 1739 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
81927e28
JS		 1740 init_completion(&adev->dm.dmub_aux_transfer_done);
1741 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1742 if (!adev->dm.dmub_notify) {
1743 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1744 goto error;
1745 }
e27c41d5
JS		 1746
1747 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1748 if (!adev->dm.delayed_hpd_wq) {
1749 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1750 goto error;
1751 }
1752
81927e28 1753 amdgpu_dm_outbox_init(adev);
e27c41d5
JS		 1754 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1755 dmub_aux_setconfig_callback, false)) {
1756 DRM_ERROR("amdgpu: fail to register dmub aux callback");
1757 goto error;
1758 }
1759 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1760 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1761 goto error;
1762 }
c40a09e5
NK		 1763 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1764 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1765 goto error;
1766 }
81927e28
JS		 1767 }
1768
11d526f1
SW		 1769 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1770 * It is expected that DMUB will resend any pending notifications at this point, for
1771 * example HPD from DPIA.
1772 */
1773 if (dc_is_dmub_outbox_supported(adev->dm.dc))
1774 dc_enable_dmub_outbox(adev->dm.dc);
1775
1c43a48b
SW		 1776 if (amdgpu_dm_initialize_drm_device(adev)) {
1777 DRM_ERROR(
1778 "amdgpu: failed to initialize sw for display support.\n");
1779 goto error;
1780 }
1781
f74367e4
AD		 1782 /* create fake encoders for MST */
1783 dm_dp_create_fake_mst_encoders(adev);
1784
4562236b
HW		 1785 /* TODO: Add_display_info? */
1786
1787 /* TODO use dynamic cursor width */
4a580877
LT		 1788 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1789 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b 1790
4a580877 1791 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
4562236b
HW		 1792 DRM_ERROR(
1793 "amdgpu: failed to initialize sw for display support.\n");
1794 goto error;
1795 }
1796
c0fb85ae 1797
f1ad2f5e 1798 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 1799
1800 return 0;
1801error:
1802 amdgpu_dm_fini(adev);
1803
59d0f396 1804 return -EINVAL;
4562236b
HW		 1805}
1806
e9669fb7
AG		 1807static int amdgpu_dm_early_fini(void *handle)
1808{
1809 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1810
1811 amdgpu_dm_audio_fini(adev);
1812
1813 return 0;
1814}
1815
7578ecda 1816static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b 1817{
f74367e4
AD		 1818 int i;
1819
09a5df6c
NK		 1820 if (adev->dm.vblank_control_workqueue) {
1821 destroy_workqueue(adev->dm.vblank_control_workqueue);
1822 adev->dm.vblank_control_workqueue = NULL;
1823 }
09a5df6c 1824
4562236b 1825 amdgpu_dm_destroy_drm_device(&adev->dm);
c8bdf2b6 1826
9a65df19 1827#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1b11ff76 1828 if (adev->dm.secure_display_ctxs) {
c3d74960 1829 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1b11ff76
AL		 1830 if (adev->dm.secure_display_ctxs[i].crtc) {
1831 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1832 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1833 }
1834 }
1835 kfree(adev->dm.secure_display_ctxs);
1836 adev->dm.secure_display_ctxs = NULL;
9a65df19
WL		 1837 }
1838#endif
52704fca 1839 if (adev->dm.hdcp_workqueue) {
e96b1b29 1840 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
52704fca
BL		 1841 adev->dm.hdcp_workqueue = NULL;
1842 }
1843
1844 if (adev->dm.dc)
1845 dc_deinit_callbacks(adev->dm.dc);
51ba6912 1846
3beac533 1847 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
9a71c7d3 1848
81927e28
JS		 1849 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1850 kfree(adev->dm.dmub_notify);
1851 adev->dm.dmub_notify = NULL;
e27c41d5
JS		 1852 destroy_workqueue(adev->dm.delayed_hpd_wq);
1853 adev->dm.delayed_hpd_wq = NULL;
81927e28
JS		 1854 }
1855
743b9786
NK		 1856 if (adev->dm.dmub_bo)
1857 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1858 &adev->dm.dmub_bo_gpu_addr,
1859 &adev->dm.dmub_bo_cpu_addr);
52704fca 1860
006c26a0
AG		 1861 if (adev->dm.hpd_rx_offload_wq) {
1862 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1863 if (adev->dm.hpd_rx_offload_wq[i].wq) {
1864 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1865 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1866 }
1867 }
1868
1869 kfree(adev->dm.hpd_rx_offload_wq);
1870 adev->dm.hpd_rx_offload_wq = NULL;
1871 }
1872
c8bdf2b6
ED		 1873 /* DC Destroy TODO: Replace destroy DAL */
1874 if (adev->dm.dc)
1875 dc_destroy(&adev->dm.dc);
4562236b
HW		 1876 /*
1877 * TODO: pageflip, vlank interrupt
1878 *
1879 * amdgpu_dm_irq_fini(adev);
1880 */
1881
1882 if (adev->dm.cgs_device) {
1883 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1884 adev->dm.cgs_device = NULL;
1885 }
1886 if (adev->dm.freesync_module) {
1887 mod_freesync_destroy(adev->dm.freesync_module);
1888 adev->dm.freesync_module = NULL;
1889 }
674e78ac 1890
6ce8f316 1891 mutex_destroy(&adev->dm.audio_lock);
674e78ac 1892 mutex_destroy(&adev->dm.dc_lock);
ead08b95 1893 mutex_destroy(&adev->dm.dpia_aux_lock);
674e78ac 1894
4562236b
HW		 1895 return;
1896}
1897
a94d5569 1898static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 1899{
a7669aff 1900 const char *fw_name_dmcu = NULL;
a94d5569
DF		 1901 int r;
1902 const struct dmcu_firmware_header_v1_0 *hdr;
1903
1904 switch(adev->asic_type) {
55e56389
MR		 1905#if defined(CONFIG_DRM_AMD_DC_SI)
1906 case CHIP_TAHITI:
1907 case CHIP_PITCAIRN:
1908 case CHIP_VERDE:
1909 case CHIP_OLAND:
1910#endif
a94d5569
DF		 1911 case CHIP_BONAIRE:
1912 case CHIP_HAWAII:
1913 case CHIP_KAVERI:
1914 case CHIP_KABINI:
1915 case CHIP_MULLINS:
1916 case CHIP_TONGA:
1917 case CHIP_FIJI:
1918 case CHIP_CARRIZO:
1919 case CHIP_STONEY:
1920 case CHIP_POLARIS11:
1921 case CHIP_POLARIS10:
1922 case CHIP_POLARIS12:
1923 case CHIP_VEGAM:
1924 case CHIP_VEGA10:
1925 case CHIP_VEGA12:
1926 case CHIP_VEGA20:
1927 return 0;
5ea23931
RL		 1928 case CHIP_NAVI12:
1929 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1930 break;
a94d5569 1931 case CHIP_RAVEN:
a7669aff
HW		 1932 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1933 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1934 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1935 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1936 else
a7669aff 1937 return 0;
a94d5569
DF		 1938 break;
1939 default:
1d789535 1940 switch (adev->ip_versions[DCE_HWIP][0]) {
c08182f2
AD		 1941 case IP_VERSION(2, 0, 2):
1942 case IP_VERSION(2, 0, 3):
1943 case IP_VERSION(2, 0, 0):
1944 case IP_VERSION(2, 1, 0):
1945 case IP_VERSION(3, 0, 0):
1946 case IP_VERSION(3, 0, 2):
1947 case IP_VERSION(3, 0, 3):
1948 case IP_VERSION(3, 0, 1):
1949 case IP_VERSION(3, 1, 2):
1950 case IP_VERSION(3, 1, 3):
f3cd57e4 1951 case IP_VERSION(3, 1, 4):
b5b8ed44 1952 case IP_VERSION(3, 1, 5):
de7cc1b4 1953 case IP_VERSION(3, 1, 6):
577359ca
AP		 1954 case IP_VERSION(3, 2, 0):
1955 case IP_VERSION(3, 2, 1):
c08182f2
AD		 1956 return 0;
1957 default:
1958 break;
1959 }
a94d5569 1960 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 1961 return -EINVAL;
a94d5569
DF		 1962 }
1963
1964 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1965 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1966 return 0;
1967 }
1968
46fa9075
ML		 1969 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
1970 if (r == -ENODEV) {
a94d5569
DF		 1971 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1972 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1973 adev->dm.fw_dmcu = NULL;
1974 return 0;
1975 }
a94d5569
DF		 1976 if (r) {
1977 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1978 fw_name_dmcu);
51526637 1979 amdgpu_ucode_release(&adev->dm.fw_dmcu);
a94d5569
DF		 1980 return r;
1981 }
1982
1983 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1984 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1985 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1986 adev->firmware.fw_size +=
1987 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1988
1989 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1990 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1991 adev->firmware.fw_size +=
1992 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1993
ee6e89c0
DF		 1994 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1995
a94d5569
DF		 1996 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1997
4562236b
HW		 1998 return 0;
1999}
2000
743b9786
NK		 2001static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2002{
2003 struct amdgpu_device *adev = ctx;
2004
2005 return dm_read_reg(adev->dm.dc->ctx, address);
2006}
2007
2008static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2009 uint32_t value)
2010{
2011 struct amdgpu_device *adev = ctx;
2012
2013 return dm_write_reg(adev->dm.dc->ctx, address, value);
2014}
2015
2016static int dm_dmub_sw_init(struct amdgpu_device *adev)
2017{
2018 struct dmub_srv_create_params create_params;
8c7aea40
NK		 2019 struct dmub_srv_region_params region_params;
2020 struct dmub_srv_region_info region_info;
2021 struct dmub_srv_fb_params fb_params;
2022 struct dmub_srv_fb_info *fb_info;
2023 struct dmub_srv *dmub_srv;
743b9786 2024 const struct dmcub_firmware_header_v1_0 *hdr;
743b9786
NK		 2025 enum dmub_asic dmub_asic;
2026 enum dmub_status status;
2027 int r;
2028
1d789535 2029 switch (adev->ip_versions[DCE_HWIP][0]) {
c08182f2 2030 case IP_VERSION(2, 1, 0):
743b9786 2031 dmub_asic = DMUB_ASIC_DCN21;
743b9786 2032 break;
c08182f2 2033 case IP_VERSION(3, 0, 0):
35a45d63 2034 dmub_asic = DMUB_ASIC_DCN30;
79037324 2035 break;
c08182f2 2036 case IP_VERSION(3, 0, 1):
469989ca 2037 dmub_asic = DMUB_ASIC_DCN301;
469989ca 2038 break;
c08182f2 2039 case IP_VERSION(3, 0, 2):
2a411205 2040 dmub_asic = DMUB_ASIC_DCN302;
2a411205 2041 break;
c08182f2 2042 case IP_VERSION(3, 0, 3):
656fe9b6 2043 dmub_asic = DMUB_ASIC_DCN303;
656fe9b6 2044 break;
c08182f2
AD		 2045 case IP_VERSION(3, 1, 2):
2046 case IP_VERSION(3, 1, 3):
3137f792 2047 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
1ebcaebd 2048 break;
e850f6b1
RL		 2049 case IP_VERSION(3, 1, 4):
2050 dmub_asic = DMUB_ASIC_DCN314;
e850f6b1 2051 break;
b5b8ed44
QZ		 2052 case IP_VERSION(3, 1, 5):
2053 dmub_asic = DMUB_ASIC_DCN315;
b5b8ed44 2054 break;
de7cc1b4 2055 case IP_VERSION(3, 1, 6):
868f4357 2056 dmub_asic = DMUB_ASIC_DCN316;
de7cc1b4 2057 break;
577359ca
AP		 2058 case IP_VERSION(3, 2, 0):
2059 dmub_asic = DMUB_ASIC_DCN32;
577359ca
AP		 2060 break;
2061 case IP_VERSION(3, 2, 1):
2062 dmub_asic = DMUB_ASIC_DCN321;
577359ca 2063 break;
743b9786
NK		 2064 default:
2065 /* ASIC doesn't support DMUB. */
2066 return 0;
2067 }
2068
743b9786 2069 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
72a74a18 2070 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
743b9786 2071
9a6ed547
NK		 2072 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2073 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2074 AMDGPU_UCODE_ID_DMCUB;
2075 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2076 adev->dm.dmub_fw;
2077 adev->firmware.fw_size +=
2078 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
743b9786 2079
9a6ed547
NK		 2080 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2081 adev->dm.dmcub_fw_version);
2082 }
2083
743b9786 2084
8c7aea40
NK		 2085 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2086 dmub_srv = adev->dm.dmub_srv;
2087
2088 if (!dmub_srv) {
2089 DRM_ERROR("Failed to allocate DMUB service!\n");
2090 return -ENOMEM;
2091 }
2092
2093 memset(&create_params, 0, sizeof(create_params));
2094 create_params.user_ctx = adev;
2095 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2096 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2097 create_params.asic = dmub_asic;
2098
2099 /* Create the DMUB service. */
2100 status = dmub_srv_create(dmub_srv, &create_params);
2101 if (status != DMUB_STATUS_OK) {
2102 DRM_ERROR("Error creating DMUB service: %d\n", status);
2103 return -EINVAL;
2104 }
2105
2106 /* Calculate the size of all the regions for the DMUB service. */
2107 memset(&region_params, 0, sizeof(region_params));
2108
2109 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2110 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2111 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2112 region_params.vbios_size = adev->bios_size;
0922b899 2113 region_params.fw_bss_data = region_params.bss_data_size ?
1f0674fd
NK		 2114 adev->dm.dmub_fw->data +
2115 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
0922b899 2116 le32_to_cpu(hdr->inst_const_bytes) : NULL;
a576b345
NK		 2117 region_params.fw_inst_const =
2118 adev->dm.dmub_fw->data +
2119 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2120 PSP_HEADER_BYTES;
8c7aea40
NK		 2121
2122 status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2123 &region_info);
2124
2125 if (status != DMUB_STATUS_OK) {
2126 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2127 return -EINVAL;
2128 }
2129
2130 /*
2131 * Allocate a framebuffer based on the total size of all the regions.
2132 * TODO: Move this into GART.
2133 */
2134 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
58ab2c08
CK		 2135 AMDGPU_GEM_DOMAIN_VRAM |
2136 AMDGPU_GEM_DOMAIN_GTT,
2137 &adev->dm.dmub_bo,
8c7aea40
NK		 2138 &adev->dm.dmub_bo_gpu_addr,
2139 &adev->dm.dmub_bo_cpu_addr);
2140 if (r)
2141 return r;
2142
2143 /* Rebase the regions on the framebuffer address. */
2144 memset(&fb_params, 0, sizeof(fb_params));
2145 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2146 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2147 fb_params.region_info = &region_info;
2148
2149 adev->dm.dmub_fb_info =
2150 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2151 fb_info = adev->dm.dmub_fb_info;
2152
2153 if (!fb_info) {
2154 DRM_ERROR(
2155 "Failed to allocate framebuffer info for DMUB service!\n");
2156 return -ENOMEM;
2157 }
2158
2159 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2160 if (status != DMUB_STATUS_OK) {
2161 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2162 return -EINVAL;
2163 }
2164
743b9786
NK		 2165 return 0;
2166}
2167
a94d5569
DF		 2168static int dm_sw_init(void *handle)
2169{
2170 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
743b9786
NK		 2171 int r;
2172
2173 r = dm_dmub_sw_init(adev);
2174 if (r)
2175 return r;
a94d5569
DF		 2176
2177 return load_dmcu_fw(adev);
2178}
2179
4562236b
HW		 2180static int dm_sw_fini(void *handle)
2181{
a94d5569
DF		 2182 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2183
8c7aea40
NK		 2184 kfree(adev->dm.dmub_fb_info);
2185 adev->dm.dmub_fb_info = NULL;
2186
743b9786
NK		 2187 if (adev->dm.dmub_srv) {
2188 dmub_srv_destroy(adev->dm.dmub_srv);
2189 adev->dm.dmub_srv = NULL;
2190 }
2191
51526637
ML		 2192 amdgpu_ucode_release(&adev->dm.dmub_fw);
2193 amdgpu_ucode_release(&adev->dm.fw_dmcu);
a94d5569 2194
4562236b
HW		 2195 return 0;
2196}
2197
7abcf6b5 2198static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 2199{
c84dec2f 2200 struct amdgpu_dm_connector *aconnector;
4562236b 2201 struct drm_connector *connector;
f8d2d39e 2202 struct drm_connector_list_iter iter;
7abcf6b5 2203 int ret = 0;
4562236b 2204
f8d2d39e
LP		 2205 drm_connector_list_iter_begin(dev, &iter);
2206 drm_for_each_connector_iter(connector, &iter) {
b349f76e 2207 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 2208 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2209 aconnector->mst_mgr.aux) {
f1ad2f5e 2210 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
f8d2d39e
LP		 2211 aconnector,
2212 aconnector->base.base.id);
7abcf6b5
AG		 2213
2214 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2215 if (ret < 0) {
2216 DRM_ERROR("DM_MST: Failed to start MST\n");
f8d2d39e
LP		 2217 aconnector->dc_link->type =
2218 dc_connection_single;
3f6752b4
RL		 2219 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2220 aconnector->dc_link);
f8d2d39e 2221 break;
7abcf6b5 2222 }
f8d2d39e 2223 }
4562236b 2224 }
f8d2d39e 2225 drm_connector_list_iter_end(&iter);
4562236b 2226
7abcf6b5
AG		 2227 return ret;
2228}
2229
2230static int dm_late_init(void *handle)
2231{
42e67c3b 2232 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 2233
bbf854dc
DF		 2234 struct dmcu_iram_parameters params;
2235 unsigned int linear_lut[16];
2236 int i;
17bdb4a8 2237 struct dmcu *dmcu = NULL;
bbf854dc 2238
17bdb4a8
JFZ		 2239 dmcu = adev->dm.dc->res_pool->dmcu;
2240
bbf854dc
DF		 2241 for (i = 0; i < 16; i++)
2242 linear_lut[i] = 0xFFFF * i / 15;
2243
2244 params.set = 0;
75068994 2245 params.backlight_ramping_override = false;
bbf854dc
DF		 2246 params.backlight_ramping_start = 0xCCCC;
2247 params.backlight_ramping_reduction = 0xCCCCCCCC;
2248 params.backlight_lut_array_size = 16;
2249 params.backlight_lut_array = linear_lut;
2250
2ad0cdf9
AK		 2251 /* Min backlight level after ABM reduction, Don't allow below 1%
2252 * 0xFFFF x 0.01 = 0x28F
2253 */
2254 params.min_abm_backlight = 0x28F;
5cb32419 2255 /* In the case where abm is implemented on dmcub,
6e568e43
JW		 2256 * dmcu object will be null.
2257 * ABM 2.4 and up are implemented on dmcub.
2258 */
2259 if (dmcu) {
2260 if (!dmcu_load_iram(dmcu, params))
2261 return -EINVAL;
2262 } else if (adev->dm.dc->ctx->dmub_srv) {
2263 struct dc_link *edp_links[MAX_NUM_EDP];
2264 int edp_num;
bbf854dc 2265
7ae1dbe6 2266 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
6e568e43
JW		 2267 for (i = 0; i < edp_num; i++) {
2268 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2269 return -EINVAL;
2270 }
2271 }
bbf854dc 2272
4a580877 2273 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
4562236b
HW		 2274}
2275
2276static void s3_handle_mst(struct drm_device *dev, bool suspend)
2277{
c84dec2f 2278 struct amdgpu_dm_connector *aconnector;
4562236b 2279 struct drm_connector *connector;
f8d2d39e 2280 struct drm_connector_list_iter iter;
fe7553be
LP		 2281 struct drm_dp_mst_topology_mgr *mgr;
2282 int ret;
2283 bool need_hotplug = false;
4562236b 2284
f8d2d39e
LP		 2285 drm_connector_list_iter_begin(dev, &iter);
2286 drm_for_each_connector_iter(connector, &iter) {
fe7553be
LP		 2287 aconnector = to_amdgpu_dm_connector(connector);
2288 if (aconnector->dc_link->type != dc_connection_mst_branch ||
f0127cb1 2289 aconnector->mst_root)
fe7553be
LP		 2290 continue;
2291
2292 mgr = &aconnector->mst_mgr;
2293
2294 if (suspend) {
2295 drm_dp_mst_topology_mgr_suspend(mgr);
2296 } else {
1e5d4d8e
RL		 2297 /* if extended timeout is supported in hardware,
2298 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2299 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2300 */
2301 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2302 if (!dp_is_lttpr_present(aconnector->dc_link))
2303 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2304
6f85f738 2305 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
fe7553be 2306 if (ret < 0) {
84a8b390
WL		 2307 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2308 aconnector->dc_link);
fe7553be
LP		 2309 need_hotplug = true;
2310 }
2311 }
4562236b 2312 }
f8d2d39e 2313 drm_connector_list_iter_end(&iter);
fe7553be
LP		 2314
2315 if (need_hotplug)
2316 drm_kms_helper_hotplug_event(dev);
4562236b
HW		 2317}
2318
9340dfd3
HW		 2319static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2320{
9340dfd3
HW		 2321 int ret = 0;
2322
9340dfd3
HW		 2323 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2324 * on window driver dc implementation.
2325 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2326 * should be passed to smu during boot up and resume from s3.
2327 * boot up: dc calculate dcn watermark clock settings within dc_create,
2328 * dcn20_resource_construct
2329 * then call pplib functions below to pass the settings to smu:
2330 * smu_set_watermarks_for_clock_ranges
2331 * smu_set_watermarks_table
2332 * navi10_set_watermarks_table
2333 * smu_write_watermarks_table
2334 *
2335 * For Renoir, clock settings of dcn watermark are also fixed values.
2336 * dc has implemented different flow for window driver:
2337 * dc_hardware_init / dc_set_power_state
2338 * dcn10_init_hw
2339 * notify_wm_ranges
2340 * set_wm_ranges
2341 * -- Linux
2342 * smu_set_watermarks_for_clock_ranges
2343 * renoir_set_watermarks_table
2344 * smu_write_watermarks_table
2345 *
2346 * For Linux,
2347 * dc_hardware_init -> amdgpu_dm_init
2348 * dc_set_power_state --> dm_resume
2349 *
2350 * therefore, this function apply to navi10/12/14 but not Renoir
2351 * *
2352 */
1d789535 2353 switch (adev->ip_versions[DCE_HWIP][0]) {
c08182f2
AD		 2354 case IP_VERSION(2, 0, 2):
2355 case IP_VERSION(2, 0, 0):
9340dfd3
HW		 2356 break;
2357 default:
2358 return 0;
2359 }
2360
13f5dbd6 2361 ret = amdgpu_dpm_write_watermarks_table(adev);
e7a95eea
EQ		 2362 if (ret) {
2363 DRM_ERROR("Failed to update WMTABLE!\n");
2364 return ret;
9340dfd3
HW		 2365 }
2366
9340dfd3
HW		 2367 return 0;
2368}
2369
b8592b48
LL		 2370/**
2371 * dm_hw_init() - Initialize DC device
28d687ea 2372 * @handle: The base driver device containing the amdgpu_dm device.
b8592b48
LL		 2373 *
2374 * Initialize the &struct amdgpu_display_manager device. This involves calling
2375 * the initializers of each DM component, then populating the struct with them.
2376 *
2377 * Although the function implies hardware initialization, both hardware and
2378 * software are initialized here. Splitting them out to their relevant init
2379 * hooks is a future TODO item.
2380 *
2381 * Some notable things that are initialized here:
2382 *
2383 * - Display Core, both software and hardware
2384 * - DC modules that we need (freesync and color management)
2385 * - DRM software states
2386 * - Interrupt sources and handlers
2387 * - Vblank support
2388 * - Debug FS entries, if enabled
2389 */
4562236b
HW		 2390static int dm_hw_init(void *handle)
2391{
2392 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2393 /* Create DAL display manager */
2394 amdgpu_dm_init(adev);
4562236b
HW		 2395 amdgpu_dm_hpd_init(adev);
2396
4562236b
HW		 2397 return 0;
2398}
2399
b8592b48
LL		 2400/**
2401 * dm_hw_fini() - Teardown DC device
28d687ea 2402 * @handle: The base driver device containing the amdgpu_dm device.
b8592b48
LL		 2403 *
2404 * Teardown components within &struct amdgpu_display_manager that require
2405 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2406 * were loaded. Also flush IRQ workqueues and disable them.
2407 */
4562236b
HW		 2408static int dm_hw_fini(void *handle)
2409{
2410 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2411
2412 amdgpu_dm_hpd_fini(adev);
2413
2414 amdgpu_dm_irq_fini(adev);
21de3396 2415 amdgpu_dm_fini(adev);
4562236b
HW		 2416 return 0;
2417}
2418
cdaae837 2419
cdaae837
BL		 2420static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2421 struct dc_state *state, bool enable)
2422{
2423 enum dc_irq_source irq_source;
2424 struct amdgpu_crtc *acrtc;
2425 int rc = -EBUSY;
2426 int i = 0;
2427
2428 for (i = 0; i < state->stream_count; i++) {
2429 acrtc = get_crtc_by_otg_inst(
2430 adev, state->stream_status[i].primary_otg_inst);
2431
2432 if (acrtc && state->stream_status[i].plane_count != 0) {
2433 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2434 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
4711c033
LT		 2435 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2436 acrtc->crtc_id, enable ? "en" : "dis", rc);
cdaae837
BL		 2437 if (rc)
2438 DRM_WARN("Failed to %s pflip interrupts\n",
2439 enable ? "enable" : "disable");
2440
2441 if (enable) {
2442 rc = dm_enable_vblank(&acrtc->base);
2443 if (rc)
2444 DRM_WARN("Failed to enable vblank interrupts\n");
2445 } else {
2446 dm_disable_vblank(&acrtc->base);
2447 }
2448
2449 }
2450 }
2451
2452}
2453
dfd84d90 2454static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
cdaae837
BL		 2455{
2456 struct dc_state *context = NULL;
2457 enum dc_status res = DC_ERROR_UNEXPECTED;
2458 int i;
2459 struct dc_stream_state *del_streams[MAX_PIPES];
2460 int del_streams_count = 0;
2461
2462 memset(del_streams, 0, sizeof(del_streams));
2463
2464 context = dc_create_state(dc);
2465 if (context == NULL)
2466 goto context_alloc_fail;
2467
2468 dc_resource_state_copy_construct_current(dc, context);
2469
2470 /* First remove from context all streams */
2471 for (i = 0; i < context->stream_count; i++) {
2472 struct dc_stream_state *stream = context->streams[i];
2473
2474 del_streams[del_streams_count++] = stream;
2475 }
2476
2477 /* Remove all planes for removed streams and then remove the streams */
2478 for (i = 0; i < del_streams_count; i++) {
2479 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2480 res = DC_FAIL_DETACH_SURFACES;
2481 goto fail;
2482 }
2483
2484 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2485 if (res != DC_OK)
2486 goto fail;
2487 }
2488
b8272241 2489 res = dc_commit_streams(dc, context->streams, context->stream_count);
cdaae837
BL		 2490
2491fail:
2492 dc_release_state(context);
2493
2494context_alloc_fail:
2495 return res;
2496}
2497
8e794421
WL		 2498static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2499{
2500 int i;
2501
2502 if (dm->hpd_rx_offload_wq) {
2503 for (i = 0; i < dm->dc->caps.max_links; i++)
2504 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2505 }
2506}
2507
4562236b
HW		 2508static int dm_suspend(void *handle)
2509{
2510 struct amdgpu_device *adev = handle;
2511 struct amdgpu_display_manager *dm = &adev->dm;
2512 int ret = 0;
4562236b 2513
53b3f8f4 2514 if (amdgpu_in_reset(adev)) {
cdaae837 2515 mutex_lock(&dm->dc_lock);
98ab5f35 2516
98ab5f35 2517 dc_allow_idle_optimizations(adev->dm.dc, false);
98ab5f35 2518
cdaae837
BL		 2519 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2520
2521 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2522
2523 amdgpu_dm_commit_zero_streams(dm->dc);
2524
2525 amdgpu_dm_irq_suspend(adev);
2526
8e794421
WL		 2527 hpd_rx_irq_work_suspend(dm);
2528
cdaae837
BL		 2529 return ret;
2530 }
4562236b 2531
d2f0b53b 2532 WARN_ON(adev->dm.cached_state);
4a580877 2533 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
d2f0b53b 2534
4a580877 2535 s3_handle_mst(adev_to_drm(adev), true);
4562236b 2536
4562236b
HW		 2537 amdgpu_dm_irq_suspend(adev);
2538
8e794421
WL		 2539 hpd_rx_irq_work_suspend(dm);
2540
32f5062d 2541 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b 2542
1c2075d4 2543 return 0;
4562236b
HW		 2544}
2545
17ce8a69 2546struct amdgpu_dm_connector *
1daf8c63
AD		 2547amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2548 struct drm_crtc *crtc)
4562236b 2549{
ae67558b 2550 u32 i;
c2cea706 2551 struct drm_connector_state *new_con_state;
4562236b
HW		 2552 struct drm_connector *connector;
2553 struct drm_crtc *crtc_from_state;
2554
c2cea706
LSL		 2555 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2556 crtc_from_state = new_con_state->crtc;
4562236b
HW		 2557
2558 if (crtc_from_state == crtc)
c84dec2f 2559 return to_amdgpu_dm_connector(connector);
4562236b
HW		 2560 }
2561
2562 return NULL;
2563}
2564
fbbdadf2
BL		 2565static void emulated_link_detect(struct dc_link *link)
2566{
2567 struct dc_sink_init_data sink_init_data = { 0 };
2568 struct display_sink_capability sink_caps = { 0 };
2569 enum dc_edid_status edid_status;
2570 struct dc_context *dc_ctx = link->ctx;
2571 struct dc_sink *sink = NULL;
2572 struct dc_sink *prev_sink = NULL;
2573
2574 link->type = dc_connection_none;
2575 prev_sink = link->local_sink;
2576
30164a16
VL		 2577 if (prev_sink)
2578 dc_sink_release(prev_sink);
fbbdadf2
BL		 2579
2580 switch (link->connector_signal) {
2581 case SIGNAL_TYPE_HDMI_TYPE_A: {
2582 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2583 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2584 break;
2585 }
2586
2587 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2588 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2589 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2590 break;
2591 }
2592
2593 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2594 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2595 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2596 break;
2597 }
2598
2599 case SIGNAL_TYPE_LVDS: {
2600 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2601 sink_caps.signal = SIGNAL_TYPE_LVDS;
2602 break;
2603 }
2604
2605 case SIGNAL_TYPE_EDP: {
2606 sink_caps.transaction_type =
2607 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2608 sink_caps.signal = SIGNAL_TYPE_EDP;
2609 break;
2610 }
2611
2612 case SIGNAL_TYPE_DISPLAY_PORT: {
2613 sink_caps.transaction_type =
2614 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2615 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2616 break;
2617 }
2618
2619 default:
2620 DC_ERROR("Invalid connector type! signal:%d\n",
2621 link->connector_signal);
2622 return;
2623 }
2624
2625 sink_init_data.link = link;
2626 sink_init_data.sink_signal = sink_caps.signal;
2627
2628 sink = dc_sink_create(&sink_init_data);
2629 if (!sink) {
2630 DC_ERROR("Failed to create sink!\n");
2631 return;
2632 }
2633
dcd5fb82 2634 /* dc_sink_create returns a new reference */
fbbdadf2
BL		 2635 link->local_sink = sink;
2636
2637 edid_status = dm_helpers_read_local_edid(
2638 link->ctx,
2639 link,
2640 sink);
2641
2642 if (edid_status != EDID_OK)
2643 DC_ERROR("Failed to read EDID");
2644
2645}
2646
cdaae837
BL		 2647static void dm_gpureset_commit_state(struct dc_state *dc_state,
2648 struct amdgpu_display_manager *dm)
2649{
2650 struct {
2651 struct dc_surface_update surface_updates[MAX_SURFACES];
2652 struct dc_plane_info plane_infos[MAX_SURFACES];
2653 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2654 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2655 struct dc_stream_update stream_update;
2656 } * bundle;
2657 int k, m;
2658
2659 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2660
2661 if (!bundle) {
2662 dm_error("Failed to allocate update bundle\n");
2663 goto cleanup;
2664 }
2665
2666 for (k = 0; k < dc_state->stream_count; k++) {
2667 bundle->stream_update.stream = dc_state->streams[k];
2668
2669 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2670 bundle->surface_updates[m].surface =
2671 dc_state->stream_status->plane_states[m];
2672 bundle->surface_updates[m].surface->force_full_update =
2673 true;
2674 }
f7511289
RS		 2675
2676 dc_update_planes_and_stream(dm->dc,
2677 bundle->surface_updates,
cdaae837 2678 dc_state->stream_status->plane_count,
f7511289
RS		 2679 dc_state->streams[k],
2680 &bundle->stream_update);
cdaae837
BL		 2681 }
2682
2683cleanup:
2684 kfree(bundle);
2685
2686 return;
2687}
2688
4562236b
HW		 2689static int dm_resume(void *handle)
2690{
2691 struct amdgpu_device *adev = handle;
4a580877 2692 struct drm_device *ddev = adev_to_drm(adev);
4562236b 2693 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 2694 struct amdgpu_dm_connector *aconnector;
4562236b 2695 struct drm_connector *connector;
f8d2d39e 2696 struct drm_connector_list_iter iter;
4562236b 2697 struct drm_crtc *crtc;
c2cea706 2698 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 2699 struct dm_crtc_state *dm_new_crtc_state;
2700 struct drm_plane *plane;
2701 struct drm_plane_state *new_plane_state;
2702 struct dm_plane_state *dm_new_plane_state;
113b7a01 2703 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
fbbdadf2 2704 enum dc_connection_type new_connection_type = dc_connection_none;
cdaae837
BL		 2705 struct dc_state *dc_state;
2706 int i, r, j;
4562236b 2707
53b3f8f4 2708 if (amdgpu_in_reset(adev)) {
cdaae837
BL		 2709 dc_state = dm->cached_dc_state;
2710
6d63fcc2
NK		 2711 /*
2712 * The dc->current_state is backed up into dm->cached_dc_state
2713 * before we commit 0 streams.
2714 *
2715 * DC will clear link encoder assignments on the real state
2716 * but the changes won't propagate over to the copy we made
2717 * before the 0 streams commit.
2718 *
2719 * DC expects that link encoder assignments are *not* valid
32685b32
NK		 2720 * when committing a state, so as a workaround we can copy
2721 * off of the current state.
2722 *
2723 * We lose the previous assignments, but we had already
2724 * commit 0 streams anyway.
6d63fcc2 2725 */
32685b32 2726 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
6d63fcc2 2727
cdaae837
BL		 2728 r = dm_dmub_hw_init(adev);
2729 if (r)
2730 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2731
2732 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2733 dc_resume(dm->dc);
2734
2735 amdgpu_dm_irq_resume_early(adev);
2736
2737 for (i = 0; i < dc_state->stream_count; i++) {
2738 dc_state->streams[i]->mode_changed = true;
6984fa41
NK		 2739 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2740 dc_state->stream_status[i].plane_states[j]->update_flags.raw
cdaae837
BL		 2741 = 0xffffffff;
2742 }
2743 }
2744
11d526f1
SW		 2745 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2746 amdgpu_dm_outbox_init(adev);
2747 dc_enable_dmub_outbox(adev->dm.dc);
2748 }
2749
b8272241 2750 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
4562236b 2751
cdaae837
BL		 2752 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2753
2754 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2755
2756 dc_release_state(dm->cached_dc_state);
2757 dm->cached_dc_state = NULL;
2758
2759 amdgpu_dm_irq_resume_late(adev);
2760
2761 mutex_unlock(&dm->dc_lock);
2762
2763 return 0;
2764 }
113b7a01
LL		 2765 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2766 dc_release_state(dm_state->context);
2767 dm_state->context = dc_create_state(dm->dc);
2768 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2769 dc_resource_state_construct(dm->dc, dm_state->context);
2770
8c7aea40 2771 /* Before powering on DC we need to re-initialize DMUB. */
79d6b935 2772 dm_dmub_hw_resume(adev);
8c7aea40 2773
11d526f1
SW		 2774 /* Re-enable outbox interrupts for DPIA. */
2775 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2776 amdgpu_dm_outbox_init(adev);
2777 dc_enable_dmub_outbox(adev->dm.dc);
2778 }
2779
a80aa93d
ML		 2780 /* power on hardware */
2781 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2782
4562236b
HW		 2783 /* program HPD filter */
2784 dc_resume(dm->dc);
2785
4562236b
HW		 2786 /*
2787 * early enable HPD Rx IRQ, should be done before set mode as short
2788 * pulse interrupts are used for MST
2789 */
2790 amdgpu_dm_irq_resume_early(adev);
2791
d20ebea8 2792 /* On resume we need to rewrite the MSTM control bits to enable MST*/
684cd480
LP		 2793 s3_handle_mst(ddev, false);
2794
4562236b 2795 /* Do detection*/
f8d2d39e
LP		 2796 drm_connector_list_iter_begin(ddev, &iter);
2797 drm_for_each_connector_iter(connector, &iter) {
c84dec2f 2798 aconnector = to_amdgpu_dm_connector(connector);
4562236b 2799
7a7175a2
RL		 2800 if (!aconnector->dc_link)
2801 continue;
2802
4562236b
HW		 2803 /*
2804 * this is the case when traversing through already created
2805 * MST connectors, should be skipped
2806 */
7a7175a2 2807 if (aconnector->dc_link->type == dc_connection_mst_branch)
4562236b
HW		 2808 continue;
2809
03ea364c 2810 mutex_lock(&aconnector->hpd_lock);
54618888 2811 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
fbbdadf2
BL		 2812 DRM_ERROR("KMS: Failed to detect connector\n");
2813
15c735e7 2814 if (aconnector->base.force && new_connection_type == dc_connection_none) {
fbbdadf2 2815 emulated_link_detect(aconnector->dc_link);
15c735e7
WL		 2816 } else {
2817 mutex_lock(&dm->dc_lock);
fbbdadf2 2818 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
15c735e7
WL		 2819 mutex_unlock(&dm->dc_lock);
2820 }
3eb4eba4
RL		 2821
2822 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2823 aconnector->fake_enable = false;
2824
dcd5fb82
MF		 2825 if (aconnector->dc_sink)
2826 dc_sink_release(aconnector->dc_sink);
4562236b
HW		 2827 aconnector->dc_sink = NULL;
2828 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 2829 mutex_unlock(&aconnector->hpd_lock);
4562236b 2830 }
f8d2d39e 2831 drm_connector_list_iter_end(&iter);
4562236b 2832
1f6010a9 2833 /* Force mode set in atomic commit */
a80aa93d 2834 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 2835 new_crtc_state->active_changed = true;
4f346e65 2836
fcb4019e
LSL		 2837 /*
2838 * atomic_check is expected to create the dc states. We need to release
2839 * them here, since they were duplicated as part of the suspend
2840 * procedure.
2841 */
a80aa93d 2842 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 2843 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2844 if (dm_new_crtc_state->stream) {
2845 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2846 dc_stream_release(dm_new_crtc_state->stream);
2847 dm_new_crtc_state->stream = NULL;
2848 }
2849 }
2850
a80aa93d 2851 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 2852 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2853 if (dm_new_plane_state->dc_state) {
2854 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2855 dc_plane_state_release(dm_new_plane_state->dc_state);
2856 dm_new_plane_state->dc_state = NULL;
2857 }
2858 }
2859
2d1af6a1 2860 drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 2861
a80aa93d 2862 dm->cached_state = NULL;
0a214e2f 2863
9faa4237 2864 amdgpu_dm_irq_resume_late(adev);
4562236b 2865
9340dfd3
HW		 2866 amdgpu_dm_smu_write_watermarks_table(adev);
2867
2d1af6a1 2868 return 0;
4562236b
HW		 2869}
2870
b8592b48
LL		 2871/**
2872 * DOC: DM Lifecycle
2873 *
2874 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2875 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2876 * the base driver's device list to be initialized and torn down accordingly.
2877 *
2878 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2879 */
2880
4562236b
HW		 2881static const struct amd_ip_funcs amdgpu_dm_funcs = {
2882 .name = "dm",
2883 .early_init = dm_early_init,
7abcf6b5 2884 .late_init = dm_late_init,
4562236b
HW		 2885 .sw_init = dm_sw_init,
2886 .sw_fini = dm_sw_fini,
e9669fb7 2887 .early_fini = amdgpu_dm_early_fini,
4562236b
HW		 2888 .hw_init = dm_hw_init,
2889 .hw_fini = dm_hw_fini,
2890 .suspend = dm_suspend,
2891 .resume = dm_resume,
2892 .is_idle = dm_is_idle,
2893 .wait_for_idle = dm_wait_for_idle,
2894 .check_soft_reset = dm_check_soft_reset,
2895 .soft_reset = dm_soft_reset,
2896 .set_clockgating_state = dm_set_clockgating_state,
2897 .set_powergating_state = dm_set_powergating_state,
2898};
2899
2900const struct amdgpu_ip_block_version dm_ip_block =
2901{
2902 .type = AMD_IP_BLOCK_TYPE_DCE,
2903 .major = 1,
2904 .minor = 0,
2905 .rev = 0,
2906 .funcs = &amdgpu_dm_funcs,
2907};
2908
ca3268c4 2909
b8592b48
LL		 2910/**
2911 * DOC: atomic
2912 *
2913 * *WIP*
2914 */
0a323b84 2915
b3663f70 2916static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 2917 .fb_create = amdgpu_display_user_framebuffer_create,
dfbbfe3c 2918 .get_format_info = amd_get_format_info,
4562236b 2919 .atomic_check = amdgpu_dm_atomic_check,
0269764a 2920 .atomic_commit = drm_atomic_helper_commit,
54f5499a
AG		 2921};
2922
2923static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
a5c2c0d1
LP		 2924 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2925 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
4562236b
HW		 2926};
2927
94562810
RS		 2928static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2929{
94562810
RS		 2930 struct amdgpu_dm_backlight_caps *caps;
2931 struct amdgpu_display_manager *dm;
2932 struct drm_connector *conn_base;
2933 struct amdgpu_device *adev;
ec11fe37 2934 struct dc_link *link = NULL;
a61bb342 2935 struct drm_luminance_range_info *luminance_range;
7fd13bae 2936 int i;
94562810
RS		 2937
2938 if (!aconnector || !aconnector->dc_link)
2939 return;
2940
ec11fe37 2941 link = aconnector->dc_link;
2942 if (link->connector_signal != SIGNAL_TYPE_EDP)
2943 return;
2944
94562810 2945 conn_base = &aconnector->base;
1348969a 2946 adev = drm_to_adev(conn_base->dev);
94562810 2947 dm = &adev->dm;
7fd13bae
AD		 2948 for (i = 0; i < dm->num_of_edps; i++) {
2949 if (link == dm->backlight_link[i])
2950 break;
2951 }
2952 if (i >= dm->num_of_edps)
2953 return;
2954 caps = &dm->backlight_caps[i];
94562810
RS		 2955 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2956 caps->aux_support = false;
94562810 2957
d0ae0b64 2958 if (caps->ext_caps->bits.oled == 1 /*||
94562810 2959 caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
d0ae0b64 2960 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
94562810
RS		 2961 caps->aux_support = true;
2962
7a46f05e
TI		 2963 if (amdgpu_backlight == 0)
2964 caps->aux_support = false;
2965 else if (amdgpu_backlight == 1)
2966 caps->aux_support = true;
2967
a61bb342
JH		 2968 luminance_range = &conn_base->display_info.luminance_range;
2969 caps->aux_min_input_signal = luminance_range->min_luminance;
2970 caps->aux_max_input_signal = luminance_range->max_luminance;
94562810
RS		 2971}
2972
97e51c16
HW		 2973void amdgpu_dm_update_connector_after_detect(
2974 struct amdgpu_dm_connector *aconnector)
4562236b
HW		 2975{
2976 struct drm_connector *connector = &aconnector->base;
2977 struct drm_device *dev = connector->dev;
b73a22d3 2978 struct dc_sink *sink;
4562236b
HW		 2979
2980 /* MST handled by drm_mst framework */
2981 if (aconnector->mst_mgr.mst_state == true)
2982 return;
2983
4562236b 2984 sink = aconnector->dc_link->local_sink;
dcd5fb82
MF		 2985 if (sink)
2986 dc_sink_retain(sink);
4562236b 2987
1f6010a9
DF		 2988 /*
2989 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 2990 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 2991 * Skip if already done during boot.
4562236b
HW		 2992 */
2993 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2994 && aconnector->dc_em_sink) {
2995
1f6010a9
DF		 2996 /*
2997 * For S3 resume with headless use eml_sink to fake stream
2998 * because on resume connector->sink is set to NULL
4562236b
HW		 2999 */
3000 mutex_lock(&dev->mode_config.mutex);
3001
3002 if (sink) {
922aa1e1 3003 if (aconnector->dc_sink) {
98e6436d 3004 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 3005 /*
3006 * retain and release below are used to
3007 * bump up refcount for sink because the link doesn't point
3008 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 3009 * reshuffle by UMD we will get into unwanted dc_sink release
3010 */
dcd5fb82 3011 dc_sink_release(aconnector->dc_sink);
922aa1e1 3012 }
4562236b 3013 aconnector->dc_sink = sink;
dcd5fb82 3014 dc_sink_retain(aconnector->dc_sink);
98e6436d
AK		 3015 amdgpu_dm_update_freesync_caps(connector,
3016 aconnector->edid);
4562236b 3017 } else {
98e6436d 3018 amdgpu_dm_update_freesync_caps(connector, NULL);
dcd5fb82 3019 if (!aconnector->dc_sink) {
4562236b 3020 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1 3021 dc_sink_retain(aconnector->dc_sink);
dcd5fb82 3022 }
4562236b
HW		 3023 }
3024
3025 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 3026
3027 if (sink)
3028 dc_sink_release(sink);
4562236b
HW		 3029 return;
3030 }
3031
3032 /*
3033 * TODO: temporary guard to look for proper fix
3034 * if this sink is MST sink, we should not do anything
3035 */
dcd5fb82
MF		 3036 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3037 dc_sink_release(sink);
4562236b 3038 return;
dcd5fb82 3039 }
4562236b
HW		 3040
3041 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 3042 /*
3043 * We got a DP short pulse (Link Loss, DP CTS, etc...).
3044 * Do nothing!!
3045 */
f1ad2f5e 3046 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b 3047 aconnector->connector_id);
dcd5fb82
MF		 3048 if (sink)
3049 dc_sink_release(sink);
4562236b
HW		 3050 return;
3051 }
3052
f1ad2f5e 3053 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 3054 aconnector->connector_id, aconnector->dc_sink, sink);
3055
3056 mutex_lock(&dev->mode_config.mutex);
3057
1f6010a9
DF		 3058 /*
3059 * 1. Update status of the drm connector
3060 * 2. Send an event and let userspace tell us what to do
3061 */
4562236b 3062 if (sink) {
1f6010a9
DF		 3063 /*
3064 * TODO: check if we still need the S3 mode update workaround.
3065 * If yes, put it here.
3066 */
c64b0d6b 3067 if (aconnector->dc_sink) {
98e6436d 3068 amdgpu_dm_update_freesync_caps(connector, NULL);
c64b0d6b
VL		 3069 dc_sink_release(aconnector->dc_sink);
3070 }
4562236b
HW		 3071
3072 aconnector->dc_sink = sink;
dcd5fb82 3073 dc_sink_retain(aconnector->dc_sink);
900b3cb1 3074 if (sink->dc_edid.length == 0) {
4562236b 3075 aconnector->edid = NULL;
e6142dd5
AP		 3076 if (aconnector->dc_link->aux_mode) {
3077 drm_dp_cec_unset_edid(
3078 &aconnector->dm_dp_aux.aux);
3079 }
900b3cb1 3080 } else {
4562236b 3081 aconnector->edid =
e6142dd5 3082 (struct edid *)sink->dc_edid.raw_edid;
4562236b 3083
e6142dd5
AP		 3084 if (aconnector->dc_link->aux_mode)
3085 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3086 aconnector->edid);
4562236b 3087 }
e6142dd5 3088
028c4ccf
QZ		 3089 aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3090 if (!aconnector->timing_requested)
3091 dm_error("%s: failed to create aconnector->requested_timing\n", __func__);
3092
20543be9 3093 drm_connector_update_edid_property(connector, aconnector->edid);
98e6436d 3094 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
94562810 3095 update_connector_ext_caps(aconnector);
4562236b 3096 } else {
e86e8947 3097 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 3098 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 3099 drm_connector_update_edid_property(connector, NULL);
4562236b 3100 aconnector->num_modes = 0;
dcd5fb82 3101 dc_sink_release(aconnector->dc_sink);
4562236b 3102 aconnector->dc_sink = NULL;
5326c452 3103 aconnector->edid = NULL;
028c4ccf
QZ		 3104 kfree(aconnector->timing_requested);
3105 aconnector->timing_requested = NULL;
0c8620d6
BL		 3106 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3107 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3108 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
4562236b
HW		 3109 }
3110
3111 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82 3112
0f877894
OV		 3113 update_subconnector_property(aconnector);
3114
dcd5fb82
MF		 3115 if (sink)
3116 dc_sink_release(sink);
4562236b
HW		 3117}
3118
e27c41d5 3119static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
4562236b 3120{
4562236b
HW		 3121 struct drm_connector *connector = &aconnector->base;
3122 struct drm_device *dev = connector->dev;
fbbdadf2 3123 enum dc_connection_type new_connection_type = dc_connection_none;
1348969a 3124 struct amdgpu_device *adev = drm_to_adev(dev);
97f6c917 3125 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
15c735e7 3126 bool ret = false;
4562236b 3127
b972b4f9
HW		 3128 if (adev->dm.disable_hpd_irq)
3129 return;
3130
1f6010a9
DF		 3131 /*
3132 * In case of failure or MST no need to update connector status or notify the OS
3133 * since (for MST case) MST does this in its own context.
4562236b
HW		 3134 */
3135 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6 3136
97f6c917 3137 if (adev->dm.hdcp_workqueue) {
96a3b32e 3138 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
97f6c917
BL		 3139 dm_con_state->update_hdcp = true;
3140 }
2e0ac3d6
HW		 3141 if (aconnector->fake_enable)
3142 aconnector->fake_enable = false;
3143
028c4ccf
QZ		 3144 aconnector->timing_changed = false;
3145
54618888 3146 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
fbbdadf2
BL		 3147 DRM_ERROR("KMS: Failed to detect connector\n");
3148
3149 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3150 emulated_link_detect(aconnector->dc_link);
3151
fbbdadf2
BL		 3152 drm_modeset_lock_all(dev);
3153 dm_restore_drm_connector_state(dev, connector);
3154 drm_modeset_unlock_all(dev);
3155
3156 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
fc320a6f 3157 drm_kms_helper_connector_hotplug_event(connector);
15c735e7
WL		 3158 } else {
3159 mutex_lock(&adev->dm.dc_lock);
3160 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3161 mutex_unlock(&adev->dm.dc_lock);
3162 if (ret) {
3163 amdgpu_dm_update_connector_after_detect(aconnector);
fbbdadf2 3164
15c735e7
WL		 3165 drm_modeset_lock_all(dev);
3166 dm_restore_drm_connector_state(dev, connector);
3167 drm_modeset_unlock_all(dev);
4562236b 3168
15c735e7
WL		 3169 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3170 drm_kms_helper_connector_hotplug_event(connector);
3171 }
4562236b
HW		 3172 }
3173 mutex_unlock(&aconnector->hpd_lock);
3174
3175}
3176
e27c41d5
JS		 3177static void handle_hpd_irq(void *param)
3178{
3179 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3180
3181 handle_hpd_irq_helper(aconnector);
3182
3183}
3184
8e794421 3185static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
4562236b 3186{
ae67558b
SS		 3187 u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3188 u8 dret;
4562236b
HW		 3189 bool new_irq_handled = false;
3190 int dpcd_addr;
3191 int dpcd_bytes_to_read;
3192
3193 const int max_process_count = 30;
3194 int process_count = 0;
3195
3196 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3197
3198 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3199 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3200 /* DPCD 0x200 - 0x201 for downstream IRQ */
3201 dpcd_addr = DP_SINK_COUNT;
3202 } else {
3203 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3204 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3205 dpcd_addr = DP_SINK_COUNT_ESI;
3206 }
3207
3208 dret = drm_dp_dpcd_read(
3209 &aconnector->dm_dp_aux.aux,
3210 dpcd_addr,
3211 esi,
3212 dpcd_bytes_to_read);
3213
3214 while (dret == dpcd_bytes_to_read &&
3215 process_count < max_process_count) {
ae67558b 3216 u8 retry;
4562236b
HW		 3217 dret = 0;
3218
3219 process_count++;
3220
f1ad2f5e 3221 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 3222 /* handle HPD short pulse irq */
3223 if (aconnector->mst_mgr.mst_state)
3224 drm_dp_mst_hpd_irq(
3225 &aconnector->mst_mgr,
3226 esi,
3227 &new_irq_handled);
4562236b
HW		 3228
3229 if (new_irq_handled) {
3230 /* ACK at DPCD to notify down stream */
3231 const int ack_dpcd_bytes_to_write =
3232 dpcd_bytes_to_read - 1;
3233
3234 for (retry = 0; retry < 3; retry++) {
ae67558b 3235 u8 wret;
4562236b
HW		 3236
3237 wret = drm_dp_dpcd_write(
3238 &aconnector->dm_dp_aux.aux,
3239 dpcd_addr + 1,
3240 &esi[1],
3241 ack_dpcd_bytes_to_write);
3242 if (wret == ack_dpcd_bytes_to_write)
3243 break;
3244 }
3245
1f6010a9 3246 /* check if there is new irq to be handled */
4562236b
HW		 3247 dret = drm_dp_dpcd_read(
3248 &aconnector->dm_dp_aux.aux,
3249 dpcd_addr,
3250 esi,
3251 dpcd_bytes_to_read);
3252
3253 new_irq_handled = false;
d4a6e8a9 3254 } else {
4562236b 3255 break;
d4a6e8a9 3256 }
4562236b
HW		 3257 }
3258
3259 if (process_count == max_process_count)
f1ad2f5e 3260 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 3261}
3262
8e794421
WL		 3263static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3264 union hpd_irq_data hpd_irq_data)
3265{
3266 struct hpd_rx_irq_offload_work *offload_work =
3267 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3268
3269 if (!offload_work) {
3270 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3271 return;
3272 }
3273
3274 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3275 offload_work->data = hpd_irq_data;
3276 offload_work->offload_wq = offload_wq;
3277
3278 queue_work(offload_wq->wq, &offload_work->work);
3279 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3280}
3281
4562236b
HW		 3282static void handle_hpd_rx_irq(void *param)
3283{
c84dec2f 3284 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 3285 struct drm_connector *connector = &aconnector->base;
3286 struct drm_device *dev = connector->dev;
53cbf65c 3287 struct dc_link *dc_link = aconnector->dc_link;
4562236b 3288 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
c8ea79a8 3289 bool result = false;
fbbdadf2 3290 enum dc_connection_type new_connection_type = dc_connection_none;
c8ea79a8 3291 struct amdgpu_device *adev = drm_to_adev(dev);
2a0f9270 3292 union hpd_irq_data hpd_irq_data;
8e794421
WL		 3293 bool link_loss = false;
3294 bool has_left_work = false;
e322843e 3295 int idx = dc_link->link_index;
8e794421 3296 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
2a0f9270
BL		 3297
3298 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
4562236b 3299
b972b4f9
HW		 3300 if (adev->dm.disable_hpd_irq)
3301 return;
3302
1f6010a9
DF		 3303 /*
3304 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 3305 * conflict, after implement i2c helper, this mutex should be
3306 * retired.
3307 */
b86e7eef 3308 mutex_lock(&aconnector->hpd_lock);
4562236b 3309
8e794421
WL		 3310 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3311 &link_loss, true, &has_left_work);
3083a984 3312
8e794421
WL		 3313 if (!has_left_work)
3314 goto out;
3315
3316 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3317 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3318 goto out;
3319 }
3320
3321 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3322 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3323 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3324 dm_handle_mst_sideband_msg(aconnector);
3083a984
QZ		 3325 goto out;
3326 }
3083a984 3327
8e794421
WL		 3328 if (link_loss) {
3329 bool skip = false;
d2aa1356 3330
8e794421
WL		 3331 spin_lock(&offload_wq->offload_lock);
3332 skip = offload_wq->is_handling_link_loss;
3333
3334 if (!skip)
3335 offload_wq->is_handling_link_loss = true;
3336
3337 spin_unlock(&offload_wq->offload_lock);
3338
3339 if (!skip)
3340 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3341
3342 goto out;
3343 }
3344 }
c8ea79a8 3345
3083a984 3346out:
c8ea79a8 3347 if (result && !is_mst_root_connector) {
4562236b 3348 /* Downstream Port status changed. */
54618888 3349 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
fbbdadf2
BL		 3350 DRM_ERROR("KMS: Failed to detect connector\n");
3351
3352 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3353 emulated_link_detect(dc_link);
3354
3355 if (aconnector->fake_enable)
3356 aconnector->fake_enable = false;
3357
3358 amdgpu_dm_update_connector_after_detect(aconnector);
3359
3360
3361 drm_modeset_lock_all(dev);
3362 dm_restore_drm_connector_state(dev, connector);
3363 drm_modeset_unlock_all(dev);
3364
fc320a6f 3365 drm_kms_helper_connector_hotplug_event(connector);
15c735e7
WL		 3366 } else {
3367 bool ret = false;
88ac3dda 3368
15c735e7
WL		 3369 mutex_lock(&adev->dm.dc_lock);
3370 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3371 mutex_unlock(&adev->dm.dc_lock);
88ac3dda 3372
15c735e7
WL		 3373 if (ret) {
3374 if (aconnector->fake_enable)
3375 aconnector->fake_enable = false;
4562236b 3376
15c735e7 3377 amdgpu_dm_update_connector_after_detect(aconnector);
4562236b 3378
15c735e7
WL		 3379 drm_modeset_lock_all(dev);
3380 dm_restore_drm_connector_state(dev, connector);
3381 drm_modeset_unlock_all(dev);
4562236b 3382
15c735e7
WL		 3383 drm_kms_helper_connector_hotplug_event(connector);
3384 }
4562236b
HW		 3385 }
3386 }
95f247e7
DC		 3387 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3388 if (adev->dm.hdcp_workqueue)
3389 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3390 }
4562236b 3391
b86e7eef 3392 if (dc_link->type != dc_connection_mst_branch)
e86e8947 3393 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
b86e7eef
NC		 3394
3395 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 3396}
3397
3398static void register_hpd_handlers(struct amdgpu_device *adev)
3399{
4a580877 3400 struct drm_device *dev = adev_to_drm(adev);
4562236b 3401 struct drm_connector *connector;
c84dec2f 3402 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 3403 const struct dc_link *dc_link;
3404 struct dc_interrupt_params int_params = {0};
3405
3406 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3407 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3408
3409 list_for_each_entry(connector,
3410 &dev->mode_config.connector_list, head) {
3411
c84dec2f 3412 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 3413 dc_link = aconnector->dc_link;
3414
3415 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3416 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3417 int_params.irq_source = dc_link->irq_source_hpd;
3418
3419 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3420 handle_hpd_irq,
3421 (void *) aconnector);
3422 }
3423
3424 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3425
3426 /* Also register for DP short pulse (hpd_rx). */
3427 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3428 int_params.irq_source = dc_link->irq_source_hpd_rx;
3429
3430 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3431 handle_hpd_rx_irq,
3432 (void *) aconnector);
8e794421
WL		 3433
3434 if (adev->dm.hpd_rx_offload_wq)
e322843e 3435 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
8e794421 3436 aconnector;
4562236b
HW		 3437 }
3438 }
3439}
3440
55e56389
MR		 3441#if defined(CONFIG_DRM_AMD_DC_SI)
3442/* Register IRQ sources and initialize IRQ callbacks */
3443static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3444{
3445 struct dc *dc = adev->dm.dc;
3446 struct common_irq_params *c_irq_params;
3447 struct dc_interrupt_params int_params = {0};
3448 int r;
3449 int i;
3450 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3451
3452 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3453 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3454
3455 /*
3456 * Actions of amdgpu_irq_add_id():
3457 * 1. Register a set() function with base driver.
3458 * Base driver will call set() function to enable/disable an
3459 * interrupt in DC hardware.
3460 * 2. Register amdgpu_dm_irq_handler().
3461 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3462 * coming from DC hardware.
3463 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3464 * for acknowledging and handling. */
3465
3466 /* Use VBLANK interrupt */
3467 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3468 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3469 if (r) {
3470 DRM_ERROR("Failed to add crtc irq id!\n");
3471 return r;
3472 }
3473
3474 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3475 int_params.irq_source =
3476 dc_interrupt_to_irq_source(dc, i+1 , 0);
3477
3478 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3479
3480 c_irq_params->adev = adev;
3481 c_irq_params->irq_src = int_params.irq_source;
3482
3483 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3484 dm_crtc_high_irq, c_irq_params);
3485 }
3486
3487 /* Use GRPH_PFLIP interrupt */
3488 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3489 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3490 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3491 if (r) {
3492 DRM_ERROR("Failed to add page flip irq id!\n");
3493 return r;
3494 }
3495
3496 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3497 int_params.irq_source =
3498 dc_interrupt_to_irq_source(dc, i, 0);
3499
3500 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3501
3502 c_irq_params->adev = adev;
3503 c_irq_params->irq_src = int_params.irq_source;
3504
3505 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3506 dm_pflip_high_irq, c_irq_params);
3507
3508 }
3509
3510 /* HPD */
3511 r = amdgpu_irq_add_id(adev, client_id,
3512 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3513 if (r) {
3514 DRM_ERROR("Failed to add hpd irq id!\n");
3515 return r;
3516 }
3517
3518 register_hpd_handlers(adev);
3519
3520 return 0;
3521}
3522#endif
3523
4562236b
HW		 3524/* Register IRQ sources and initialize IRQ callbacks */
3525static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3526{
3527 struct dc *dc = adev->dm.dc;
3528 struct common_irq_params *c_irq_params;
3529 struct dc_interrupt_params int_params = {0};
3530 int r;
3531 int i;
1ffdeca6 3532 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 3533
c08182f2 3534 if (adev->family >= AMDGPU_FAMILY_AI)
3760f76c 3535 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 3536
3537 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3538 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3539
1f6010a9
DF		 3540 /*
3541 * Actions of amdgpu_irq_add_id():
4562236b
HW		 3542 * 1. Register a set() function with base driver.
3543 * Base driver will call set() function to enable/disable an
3544 * interrupt in DC hardware.
3545 * 2. Register amdgpu_dm_irq_handler().
3546 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3547 * coming from DC hardware.
3548 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3549 * for acknowledging and handling. */
3550
b57de80a 3551 /* Use VBLANK interrupt */
e9029155 3552 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 3553 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 3554 if (r) {
3555 DRM_ERROR("Failed to add crtc irq id!\n");
3556 return r;
3557 }
3558
3559 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3560 int_params.irq_source =
3d761e79 3561 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 3562
b57de80a 3563 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 3564
3565 c_irq_params->adev = adev;
3566 c_irq_params->irq_src = int_params.irq_source;
3567
3568 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3569 dm_crtc_high_irq, c_irq_params);
3570 }
3571
d2574c33
MK		 3572 /* Use VUPDATE interrupt */
3573 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3574 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3575 if (r) {
3576 DRM_ERROR("Failed to add vupdate irq id!\n");
3577 return r;
3578 }
3579
3580 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3581 int_params.irq_source =
3582 dc_interrupt_to_irq_source(dc, i, 0);
3583
3584 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3585
3586 c_irq_params->adev = adev;
3587 c_irq_params->irq_src = int_params.irq_source;
3588
3589 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3590 dm_vupdate_high_irq, c_irq_params);
3591 }
3592
3d761e79 3593 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 3594 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3595 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 3596 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 3597 if (r) {
3598 DRM_ERROR("Failed to add page flip irq id!\n");
3599 return r;
3600 }
3601
3602 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3603 int_params.irq_source =
3604 dc_interrupt_to_irq_source(dc, i, 0);
3605
3606 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3607
3608 c_irq_params->adev = adev;
3609 c_irq_params->irq_src = int_params.irq_source;
3610
3611 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3612 dm_pflip_high_irq, c_irq_params);
3613
3614 }
3615
3616 /* HPD */
2c8ad2d5
AD		 3617 r = amdgpu_irq_add_id(adev, client_id,
3618 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 3619 if (r) {
3620 DRM_ERROR("Failed to add hpd irq id!\n");
3621 return r;
3622 }
3623
3624 register_hpd_handlers(adev);
3625
3626 return 0;
3627}
3628
ff5ef992
AD		 3629/* Register IRQ sources and initialize IRQ callbacks */
3630static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3631{
3632 struct dc *dc = adev->dm.dc;
3633 struct common_irq_params *c_irq_params;
3634 struct dc_interrupt_params int_params = {0};
3635 int r;
3636 int i;
660d5406
WL		 3637#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3638 static const unsigned int vrtl_int_srcid[] = {
3639 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3640 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3641 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3642 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3643 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3644 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3645 };
3646#endif
ff5ef992
AD		 3647
3648 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3649 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3650
1f6010a9
DF		 3651 /*
3652 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 3653 * 1. Register a set() function with base driver.
3654 * Base driver will call set() function to enable/disable an
3655 * interrupt in DC hardware.
3656 * 2. Register amdgpu_dm_irq_handler().
3657 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3658 * coming from DC hardware.
3659 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3660 * for acknowledging and handling.
1f6010a9 3661 */
ff5ef992
AD		 3662
3663 /* Use VSTARTUP interrupt */
3664 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3665 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3666 i++) {
3760f76c 3667 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 3668
3669 if (r) {
3670 DRM_ERROR("Failed to add crtc irq id!\n");
3671 return r;
3672 }
3673
3674 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3675 int_params.irq_source =
3676 dc_interrupt_to_irq_source(dc, i, 0);
3677
3678 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3679
3680 c_irq_params->adev = adev;
3681 c_irq_params->irq_src = int_params.irq_source;
3682
2346ef47
NK		 3683 amdgpu_dm_irq_register_interrupt(
3684 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3685 }
3686
86bc2219
WL		 3687 /* Use otg vertical line interrupt */
3688#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
660d5406
WL		 3689 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3690 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3691 vrtl_int_srcid[i], &adev->vline0_irq);
86bc2219
WL		 3692
3693 if (r) {
3694 DRM_ERROR("Failed to add vline0 irq id!\n");
3695 return r;
3696 }
3697
3698 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3699 int_params.irq_source =
660d5406
WL		 3700 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3701
3702 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3703 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3704 break;
3705 }
86bc2219
WL		 3706
3707 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3708 - DC_IRQ_SOURCE_DC1_VLINE0];
3709
3710 c_irq_params->adev = adev;
3711 c_irq_params->irq_src = int_params.irq_source;
3712
3713 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3714 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3715 }
3716#endif
3717
2346ef47
NK		 3718 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3719 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3720 * to trigger at end of each vblank, regardless of state of the lock,
3721 * matching DCE behaviour.
3722 */
3723 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3724 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3725 i++) {
3726 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3727
3728 if (r) {
3729 DRM_ERROR("Failed to add vupdate irq id!\n");
3730 return r;
3731 }
3732
3733 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3734 int_params.irq_source =
3735 dc_interrupt_to_irq_source(dc, i, 0);
3736
3737 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3738
3739 c_irq_params->adev = adev;
3740 c_irq_params->irq_src = int_params.irq_source;
3741
ff5ef992 3742 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2346ef47 3743 dm_vupdate_high_irq, c_irq_params);
d2574c33
MK		 3744 }
3745
ff5ef992
AD		 3746 /* Use GRPH_PFLIP interrupt */
3747 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
de95753c 3748 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
ff5ef992 3749 i++) {
3760f76c 3750 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 3751 if (r) {
3752 DRM_ERROR("Failed to add page flip irq id!\n");
3753 return r;
3754 }
3755
3756 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3757 int_params.irq_source =
3758 dc_interrupt_to_irq_source(dc, i, 0);
3759
3760 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3761
3762 c_irq_params->adev = adev;
3763 c_irq_params->irq_src = int_params.irq_source;
3764
3765 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3766 dm_pflip_high_irq, c_irq_params);
3767
3768 }
3769
81927e28
JS		 3770 /* HPD */
3771 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3772 &adev->hpd_irq);
3773 if (r) {
3774 DRM_ERROR("Failed to add hpd irq id!\n");
3775 return r;
3776 }
a08f16cf 3777
81927e28 3778 register_hpd_handlers(adev);
a08f16cf 3779
81927e28
JS		 3780 return 0;
3781}
3782/* Register Outbox IRQ sources and initialize IRQ callbacks */
3783static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3784{
3785 struct dc *dc = adev->dm.dc;
3786 struct common_irq_params *c_irq_params;
3787 struct dc_interrupt_params int_params = {0};
3788 int r, i;
3789
3790 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3791 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3792
3793 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3794 &adev->dmub_outbox_irq);
3795 if (r) {
3796 DRM_ERROR("Failed to add outbox irq id!\n");
3797 return r;
3798 }
3799
3800 if (dc->ctx->dmub_srv) {
3801 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3802 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
a08f16cf 3803 int_params.irq_source =
81927e28 3804 dc_interrupt_to_irq_source(dc, i, 0);
a08f16cf 3805
81927e28 3806 c_irq_params = &adev->dm.dmub_outbox_params[0];
a08f16cf
LHM		 3807
3808 c_irq_params->adev = adev;
3809 c_irq_params->irq_src = int_params.irq_source;
3810
3811 amdgpu_dm_irq_register_interrupt(adev, &int_params,
81927e28 3812 dm_dmub_outbox1_low_irq, c_irq_params);
ff5ef992
AD		 3813 }
3814
ff5ef992
AD		 3815 return 0;
3816}
ff5ef992 3817
eb3dc897
NK		 3818/*
3819 * Acquires the lock for the atomic state object and returns
3820 * the new atomic state.
3821 *
3822 * This should only be called during atomic check.
3823 */
17ce8a69
RL		 3824int dm_atomic_get_state(struct drm_atomic_state *state,
3825 struct dm_atomic_state **dm_state)
eb3dc897
NK		 3826{
3827 struct drm_device *dev = state->dev;
1348969a 3828 struct amdgpu_device *adev = drm_to_adev(dev);
eb3dc897
NK		 3829 struct amdgpu_display_manager *dm = &adev->dm;
3830 struct drm_private_state *priv_state;
eb3dc897
NK		 3831
3832 if (*dm_state)
3833 return 0;
3834
eb3dc897
NK		 3835 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3836 if (IS_ERR(priv_state))
3837 return PTR_ERR(priv_state);
3838
3839 *dm_state = to_dm_atomic_state(priv_state);
3840
3841 return 0;
3842}
3843
dfd84d90 3844static struct dm_atomic_state *
eb3dc897
NK		 3845dm_atomic_get_new_state(struct drm_atomic_state *state)
3846{
3847 struct drm_device *dev = state->dev;
1348969a 3848 struct amdgpu_device *adev = drm_to_adev(dev);
eb3dc897
NK		 3849 struct amdgpu_display_manager *dm = &adev->dm;
3850 struct drm_private_obj *obj;
3851 struct drm_private_state *new_obj_state;
3852 int i;
3853
3854 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3855 if (obj->funcs == dm->atomic_obj.funcs)
3856 return to_dm_atomic_state(new_obj_state);
3857 }
3858
3859 return NULL;
3860}
3861
eb3dc897
NK		 3862static struct drm_private_state *
3863dm_atomic_duplicate_state(struct drm_private_obj *obj)
3864{
3865 struct dm_atomic_state *old_state, *new_state;
3866
3867 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3868 if (!new_state)
3869 return NULL;
3870
3871 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3872
813d20dc
AW		 3873 old_state = to_dm_atomic_state(obj->state);
3874
3875 if (old_state && old_state->context)
3876 new_state->context = dc_copy_state(old_state->context);
3877
eb3dc897
NK		 3878 if (!new_state->context) {
3879 kfree(new_state);
3880 return NULL;
3881 }
3882
eb3dc897
NK		 3883 return &new_state->base;
3884}
3885
3886static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3887 struct drm_private_state *state)
3888{
3889 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3890
3891 if (dm_state && dm_state->context)
3892 dc_release_state(dm_state->context);
3893
3894 kfree(dm_state);
3895}
3896
3897static struct drm_private_state_funcs dm_atomic_state_funcs = {
3898 .atomic_duplicate_state = dm_atomic_duplicate_state,
3899 .atomic_destroy_state = dm_atomic_destroy_state,
3900};
3901
4562236b
HW		 3902static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3903{
eb3dc897 3904 struct dm_atomic_state *state;
4562236b
HW		 3905 int r;
3906
3907 adev->mode_info.mode_config_initialized = true;
3908
4a580877
LT		 3909 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3910 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b 3911
4a580877
LT		 3912 adev_to_drm(adev)->mode_config.max_width = 16384;
3913 adev_to_drm(adev)->mode_config.max_height = 16384;
4562236b 3914
4a580877 3915 adev_to_drm(adev)->mode_config.preferred_depth = 24;
a6250bdb
AD		 3916 if (adev->asic_type == CHIP_HAWAII)
3917 /* disable prefer shadow for now due to hibernation issues */
3918 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3919 else
3920 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
1f6010a9 3921 /* indicates support for immediate flip */
4a580877 3922 adev_to_drm(adev)->mode_config.async_page_flip = true;
4562236b 3923
eb3dc897
NK		 3924 state = kzalloc(sizeof(*state), GFP_KERNEL);
3925 if (!state)
3926 return -ENOMEM;
3927
813d20dc 3928 state->context = dc_create_state(adev->dm.dc);
eb3dc897
NK		 3929 if (!state->context) {
3930 kfree(state);
3931 return -ENOMEM;
3932 }
3933
3934 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3935
4a580877 3936 drm_atomic_private_obj_init(adev_to_drm(adev),
8c1a765b 3937 &adev->dm.atomic_obj,
eb3dc897
NK		 3938 &state->base,
3939 &dm_atomic_state_funcs);
3940
3dc9b1ce 3941 r = amdgpu_display_modeset_create_props(adev);
b67a468a
DL		 3942 if (r) {
3943 dc_release_state(state->context);
3944 kfree(state);
4562236b 3945 return r;
b67a468a 3946 }
4562236b 3947
6ce8f316 3948 r = amdgpu_dm_audio_init(adev);
b67a468a
DL		 3949 if (r) {
3950 dc_release_state(state->context);
3951 kfree(state);
6ce8f316 3952 return r;
b67a468a 3953 }
6ce8f316 3954
4562236b
HW		 3955 return 0;
3956}
3957
206bbafe
DF		 3958#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3959#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
94562810 3960#define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
206bbafe 3961
7fd13bae
AD		 3962static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
3963 int bl_idx)
206bbafe
DF		 3964{
3965#if defined(CONFIG_ACPI)
3966 struct amdgpu_dm_backlight_caps caps;
3967
58965855
FS		 3968 memset(&caps, 0, sizeof(caps));
3969
7fd13bae 3970 if (dm->backlight_caps[bl_idx].caps_valid)
206bbafe
DF		 3971 return;
3972
f9b7f370 3973 amdgpu_acpi_get_backlight_caps(&caps);
206bbafe 3974 if (caps.caps_valid) {
7fd13bae 3975 dm->backlight_caps[bl_idx].caps_valid = true;
94562810
RS		 3976 if (caps.aux_support)
3977 return;
7fd13bae
AD		 3978 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
3979 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
206bbafe 3980 } else {
7fd13bae 3981 dm->backlight_caps[bl_idx].min_input_signal =
206bbafe 3982 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
7fd13bae 3983 dm->backlight_caps[bl_idx].max_input_signal =
206bbafe
DF		 3984 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3985 }
3986#else
7fd13bae 3987 if (dm->backlight_caps[bl_idx].aux_support)
94562810
RS		 3988 return;
3989
7fd13bae
AD		 3990 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3991 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 3992#endif
3993}
3994
69d9f427
AM		 3995static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3996 unsigned *min, unsigned *max)
94562810 3997{
94562810 3998 if (!caps)
69d9f427 3999 return 0;
94562810 4000
69d9f427
AM		 4001 if (caps->aux_support) {
4002 // Firmware limits are in nits, DC API wants millinits.
4003 *max = 1000 * caps->aux_max_input_signal;
4004 *min = 1000 * caps->aux_min_input_signal;
94562810 4005 } else {
69d9f427
AM		 4006 // Firmware limits are 8-bit, PWM control is 16-bit.
4007 *max = 0x101 * caps->max_input_signal;
4008 *min = 0x101 * caps->min_input_signal;
94562810 4009 }
69d9f427
AM		 4010 return 1;
4011}
94562810 4012
69d9f427
AM		 4013static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4014 uint32_t brightness)
4015{
4016 unsigned min, max;
94562810 4017
69d9f427
AM		 4018 if (!get_brightness_range(caps, &min, &max))
4019 return brightness;
4020
4021 // Rescale 0..255 to min..max
4022 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4023 AMDGPU_MAX_BL_LEVEL);
4024}
4025
4026static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4027 uint32_t brightness)
4028{
4029 unsigned min, max;
4030
4031 if (!get_brightness_range(caps, &min, &max))
4032 return brightness;
4033
4034 if (brightness < min)
4035 return 0;
4036 // Rescale min..max to 0..255
4037 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4038 max - min);
94562810
RS		 4039}
4040
4052287a 4041static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
7fd13bae 4042 int bl_idx,
3d6c9164 4043 u32 user_brightness)
4562236b 4044{
206bbafe 4045 struct amdgpu_dm_backlight_caps caps;
7fd13bae
AD		 4046 struct dc_link *link;
4047 u32 brightness;
94562810 4048 bool rc;
4562236b 4049
7fd13bae
AD		 4050 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4051 caps = dm->backlight_caps[bl_idx];
94562810 4052
7fd13bae 4053 dm->brightness[bl_idx] = user_brightness;
1f579254
AD		 4054 /* update scratch register */
4055 if (bl_idx == 0)
4056 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
7fd13bae
AD		 4057 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4058 link = (struct dc_link *)dm->backlight_link[bl_idx];
94562810 4059
3d6c9164 4060 /* Change brightness based on AUX property */
118b4627 4061 if (caps.aux_support) {
7fd13bae
AD		 4062 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4063 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4064 if (!rc)
4065 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
118b4627 4066 } else {
7fd13bae
AD		 4067 rc = dc_link_set_backlight_level(link, brightness, 0);
4068 if (!rc)
4069 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
118b4627 4070 }
94562810 4071
4052287a
S		 4072 if (rc)
4073 dm->actual_brightness[bl_idx] = user_brightness;
4562236b
HW		 4074}
4075
3d6c9164 4076static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4562236b 4077{
620a0d27 4078 struct amdgpu_display_manager *dm = bl_get_data(bd);
7fd13bae 4079 int i;
3d6c9164 4080
7fd13bae
AD		 4081 for (i = 0; i < dm->num_of_edps; i++) {
4082 if (bd == dm->backlight_dev[i])
4083 break;
4084 }
4085 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4086 i = 0;
4087 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
3d6c9164
AD		 4088
4089 return 0;
4090}
4091
7fd13bae
AD		 4092static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4093 int bl_idx)
3d6c9164 4094{
0ad3e64e 4095 struct amdgpu_dm_backlight_caps caps;
7fd13bae 4096 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
0ad3e64e 4097
7fd13bae
AD		 4098 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4099 caps = dm->backlight_caps[bl_idx];
620a0d27 4100
0ad3e64e 4101 if (caps.aux_support) {
0ad3e64e
AD		 4102 u32 avg, peak;
4103 bool rc;
4104
4105 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4106 if (!rc)
7fd13bae 4107 return dm->brightness[bl_idx];
0ad3e64e
AD		 4108 return convert_brightness_to_user(&caps, avg);
4109 } else {
7fd13bae 4110 int ret = dc_link_get_backlight_level(link);
0ad3e64e
AD		 4111
4112 if (ret == DC_ERROR_UNEXPECTED)
7fd13bae 4113 return dm->brightness[bl_idx];
0ad3e64e
AD		 4114 return convert_brightness_to_user(&caps, ret);
4115 }
4562236b
HW		 4116}
4117
3d6c9164
AD		 4118static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4119{
4120 struct amdgpu_display_manager *dm = bl_get_data(bd);
7fd13bae 4121 int i;
3d6c9164 4122
7fd13bae
AD		 4123 for (i = 0; i < dm->num_of_edps; i++) {
4124 if (bd == dm->backlight_dev[i])
4125 break;
4126 }
4127 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4128 i = 0;
4129 return amdgpu_dm_backlight_get_level(dm, i);
3d6c9164
AD		 4130}
4131
4562236b 4132static const struct backlight_ops amdgpu_dm_backlight_ops = {
bb264220 4133 .options = BL_CORE_SUSPENDRESUME,
4562236b
HW		 4134 .get_brightness = amdgpu_dm_backlight_get_brightness,
4135 .update_status = amdgpu_dm_backlight_update_status,
4136};
4137
7578ecda 4138static void
d24b77e4
HG		 4139amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm,
4140 struct amdgpu_dm_connector *aconnector)
4562236b
HW		 4141{
4142 char bl_name[16];
4143 struct backlight_properties props = { 0 };
4144
7fd13bae
AD		 4145 amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4146 dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
206bbafe 4147
da11ef83
HG		 4148 if (!acpi_video_backlight_use_native()) {
4149 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
c0f50c5d
HG		 4150 /* Try registering an ACPI video backlight device instead. */
4151 acpi_video_register_backlight();
da11ef83
HG		 4152 return;
4153 }
4154
4562236b 4155 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 4156 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 4157 props.type = BACKLIGHT_RAW;
4158
4159 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
7fd13bae 4160 adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4562236b 4161
7fd13bae 4162 dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
d24b77e4 4163 aconnector->base.kdev,
7fd13bae
AD		 4164 dm,
4165 &amdgpu_dm_backlight_ops,
4166 &props);
4562236b 4167
7fd13bae 4168 if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4562236b
HW		 4169 DRM_ERROR("DM: Backlight registration failed!\n");
4170 else
f1ad2f5e 4171 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b 4172}
4562236b 4173
df534fff 4174static int initialize_plane(struct amdgpu_display_manager *dm,
b2fddb13 4175 struct amdgpu_mode_info *mode_info, int plane_id,
cc1fec57
NK		 4176 enum drm_plane_type plane_type,
4177 const struct dc_plane_cap *plane_cap)
df534fff 4178{
f180b4bc 4179 struct drm_plane *plane;
df534fff
S		 4180 unsigned long possible_crtcs;
4181 int ret = 0;
4182
f180b4bc 4183 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 4184 if (!plane) {
4185 DRM_ERROR("KMS: Failed to allocate plane\n");
4186 return -ENOMEM;
4187 }
b2fddb13 4188 plane->type = plane_type;
df534fff
S		 4189
4190 /*
b2fddb13
NK		 4191 * HACK: IGT tests expect that the primary plane for a CRTC
4192 * can only have one possible CRTC. Only expose support for
4193 * any CRTC if they're not going to be used as a primary plane
4194 * for a CRTC - like overlay or underlay planes.
df534fff
S		 4195 */
4196 possible_crtcs = 1 << plane_id;
4197 if (plane_id >= dm->dc->caps.max_streams)
4198 possible_crtcs = 0xff;
4199
cc1fec57 4200 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
df534fff
S		 4201
4202 if (ret) {
4203 DRM_ERROR("KMS: Failed to initialize plane\n");
54087768 4204 kfree(plane);
df534fff
S		 4205 return ret;
4206 }
4207
54087768
NK		 4208 if (mode_info)
4209 mode_info->planes[plane_id] = plane;
4210
df534fff
S		 4211 return ret;
4212}
4213
89fc8d4e
HW		 4214
4215static void register_backlight_device(struct amdgpu_display_manager *dm,
d24b77e4 4216 struct amdgpu_dm_connector *aconnector,
89fc8d4e
HW		 4217 struct dc_link *link)
4218{
89fc8d4e
HW		 4219 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4220 link->type != dc_connection_none) {
1f6010a9
DF		 4221 /*
4222 * Event if registration failed, we should continue with
89fc8d4e
HW		 4223 * DM initialization because not having a backlight control
4224 * is better then a black screen.
4225 */
7fd13bae 4226 if (!dm->backlight_dev[dm->num_of_edps])
d24b77e4 4227 amdgpu_dm_register_backlight_device(dm, aconnector);
89fc8d4e 4228
7fd13bae 4229 if (dm->backlight_dev[dm->num_of_edps]) {
118b4627
ML		 4230 dm->backlight_link[dm->num_of_edps] = link;
4231 dm->num_of_edps++;
4232 }
89fc8d4e 4233 }
89fc8d4e
HW		 4234}
4235
acc96ae0 4236static void amdgpu_set_panel_orientation(struct drm_connector *connector);
89fc8d4e 4237
1f6010a9
DF		 4238/*
4239 * In this architecture, the association
4562236b
HW		 4240 * connector -> encoder -> crtc
4241 * id not really requried. The crtc and connector will hold the
4242 * display_index as an abstraction to use with DAL component
4243 *
4244 * Returns 0 on success
4245 */
7578ecda 4246static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 4247{
4248 struct amdgpu_display_manager *dm = &adev->dm;
ae67558b 4249 s32 i;
c84dec2f 4250 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 4251 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 4252 struct amdgpu_mode_info *mode_info = &adev->mode_info;
ae67558b
SS		 4253 u32 link_cnt;
4254 s32 primary_planes;
fbbdadf2 4255 enum dc_connection_type new_connection_type = dc_connection_none;
cc1fec57 4256 const struct dc_plane_cap *plane;
9470620e 4257 bool psr_feature_enabled = false;
35f33086 4258 int max_overlay = dm->dc->caps.max_slave_planes;
4562236b 4259
d58159de
AD		 4260 dm->display_indexes_num = dm->dc->caps.max_streams;
4261 /* Update the actual used number of crtc */
4262 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4263
60971b20 4264 amdgpu_dm_set_irq_funcs(adev);
4265
4562236b 4266 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 4267 if (amdgpu_dm_mode_config_init(dm->adev)) {
4268 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 4269 return -EINVAL;
4562236b
HW		 4270 }
4271
b2fddb13
NK		 4272 /* There is one primary plane per CRTC */
4273 primary_planes = dm->dc->caps.max_streams;
54087768 4274 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
efa6a8b7 4275
b2fddb13
NK		 4276 /*
4277 * Initialize primary planes, implicit planes for legacy IOCTLS.
4278 * Order is reversed to match iteration order in atomic check.
4279 */
4280 for (i = (primary_planes - 1); i >= 0; i--) {
cc1fec57
NK		 4281 plane = &dm->dc->caps.planes[i];
4282
b2fddb13 4283 if (initialize_plane(dm, mode_info, i,
cc1fec57 4284 DRM_PLANE_TYPE_PRIMARY, plane)) {
df534fff 4285 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 4286 goto fail;
d4e13b0d 4287 }
df534fff 4288 }
92f3ac40 4289
0d579c7e
NK		 4290 /*
4291 * Initialize overlay planes, index starting after primary planes.
4292 * These planes have a higher DRM index than the primary planes since
4293 * they should be considered as having a higher z-order.
4294 * Order is reversed to match iteration order in atomic check.
cc1fec57
NK		 4295 *
4296 * Only support DCN for now, and only expose one so we don't encourage
4297 * userspace to use up all the pipes.
0d579c7e 4298 */
cc1fec57
NK		 4299 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4300 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4301
8813381a
LL		 4302 /* Do not create overlay if MPO disabled */
4303 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4304 break;
4305
cc1fec57
NK		 4306 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4307 continue;
4308
4309 if (!plane->blends_with_above || !plane->blends_with_below)
4310 continue;
4311
ea36ad34 4312 if (!plane->pixel_format_support.argb8888)
cc1fec57
NK		 4313 continue;
4314
35f33086
BL		 4315 if (max_overlay-- == 0)
4316 break;
4317
54087768 4318 if (initialize_plane(dm, NULL, primary_planes + i,
cc1fec57 4319 DRM_PLANE_TYPE_OVERLAY, plane)) {
0d579c7e 4320 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 4321 goto fail;
d4e13b0d
AD		 4322 }
4323 }
4562236b 4324
d4e13b0d 4325 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 4326 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 4327 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 4328 goto fail;
4562236b 4329 }
4562236b 4330
81927e28 4331 /* Use Outbox interrupt */
1d789535 4332 switch (adev->ip_versions[DCE_HWIP][0]) {
c08182f2
AD		 4333 case IP_VERSION(3, 0, 0):
4334 case IP_VERSION(3, 1, 2):
4335 case IP_VERSION(3, 1, 3):
e850f6b1 4336 case IP_VERSION(3, 1, 4):
b5b8ed44 4337 case IP_VERSION(3, 1, 5):
de7cc1b4 4338 case IP_VERSION(3, 1, 6):
577359ca
AP		 4339 case IP_VERSION(3, 2, 0):
4340 case IP_VERSION(3, 2, 1):
c08182f2 4341 case IP_VERSION(2, 1, 0):
81927e28
JS		 4342 if (register_outbox_irq_handlers(dm->adev)) {
4343 DRM_ERROR("DM: Failed to initialize IRQ\n");
4344 goto fail;
4345 }
4346 break;
4347 default:
c08182f2 4348 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
1d789535 4349 adev->ip_versions[DCE_HWIP][0]);
81927e28 4350 }
9470620e
NK		 4351
4352 /* Determine whether to enable PSR support by default. */
4353 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4354 switch (adev->ip_versions[DCE_HWIP][0]) {
4355 case IP_VERSION(3, 1, 2):
4356 case IP_VERSION(3, 1, 3):
e850f6b1 4357 case IP_VERSION(3, 1, 4):
b5b8ed44 4358 case IP_VERSION(3, 1, 5):
de7cc1b4 4359 case IP_VERSION(3, 1, 6):
577359ca
AP		 4360 case IP_VERSION(3, 2, 0):
4361 case IP_VERSION(3, 2, 1):
9470620e
NK		 4362 psr_feature_enabled = true;
4363 break;
4364 default:
4365 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4366 break;
4367 }
4368 }
81927e28 4369
4562236b
HW		 4370 /* loops over all connectors on the board */
4371 for (i = 0; i < link_cnt; i++) {
89fc8d4e 4372 struct dc_link *link = NULL;
4562236b
HW		 4373
4374 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4375 DRM_ERROR(
4376 "KMS: Cannot support more than %d display indexes\n",
4377 AMDGPU_DM_MAX_DISPLAY_INDEX);
4378 continue;
4379 }
4380
4381 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4382 if (!aconnector)
cd8a2ae8 4383 goto fail;
4562236b
HW		 4384
4385 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 4386 if (!aencoder)
cd8a2ae8 4387 goto fail;
4562236b
HW		 4388
4389 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4390 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 4391 goto fail;
4562236b
HW		 4392 }
4393
4394 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4395 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 4396 goto fail;
4562236b
HW		 4397 }
4398
89fc8d4e
HW		 4399 link = dc_get_link_at_index(dm->dc, i);
4400
54618888 4401 if (!dc_link_detect_connection_type(link, &new_connection_type))
fbbdadf2
BL		 4402 DRM_ERROR("KMS: Failed to detect connector\n");
4403
4404 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4405 emulated_link_detect(link);
4406 amdgpu_dm_update_connector_after_detect(aconnector);
15c735e7
WL		 4407 } else {
4408 bool ret = false;
fbbdadf2 4409
15c735e7
WL		 4410 mutex_lock(&dm->dc_lock);
4411 ret = dc_link_detect(link, DETECT_REASON_BOOT);
4412 mutex_unlock(&dm->dc_lock);
4413
4414 if (ret) {
4415 amdgpu_dm_update_connector_after_detect(aconnector);
d24b77e4 4416 register_backlight_device(dm, aconnector, link);
89fc8d4e 4417
15c735e7
WL		 4418 if (dm->num_of_edps)
4419 update_connector_ext_caps(aconnector);
89fc8d4e 4420
15c735e7
WL		 4421 if (psr_feature_enabled)
4422 amdgpu_dm_set_psr_caps(link);
89fc8d4e 4423
15c735e7
WL		 4424 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4425 * PSR is also supported.
4426 */
4427 if (link->psr_settings.psr_feature_enabled)
4428 adev_to_drm(adev)->vblank_disable_immediate = false;
4429 }
4430 }
acc96ae0 4431 amdgpu_set_panel_orientation(&aconnector->base);
4562236b
HW		 4432 }
4433
c573e240
ML		 4434 /* If we didn't find a panel, notify the acpi video detection */
4435 if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4436 acpi_video_report_nolcd();
4437
4562236b
HW		 4438 /* Software is initialized. Now we can register interrupt handlers. */
4439 switch (adev->asic_type) {
55e56389
MR		 4440#if defined(CONFIG_DRM_AMD_DC_SI)
4441 case CHIP_TAHITI:
4442 case CHIP_PITCAIRN:
4443 case CHIP_VERDE:
4444 case CHIP_OLAND:
4445 if (dce60_register_irq_handlers(dm->adev)) {
4446 DRM_ERROR("DM: Failed to initialize IRQ\n");
4447 goto fail;
4448 }
4449 break;
4450#endif
4562236b
HW		 4451 case CHIP_BONAIRE:
4452 case CHIP_HAWAII:
cd4b356f
AD		 4453 case CHIP_KAVERI:
4454 case CHIP_KABINI:
4455 case CHIP_MULLINS:
4562236b
HW		 4456 case CHIP_TONGA:
4457 case CHIP_FIJI:
4458 case CHIP_CARRIZO:
4459 case CHIP_STONEY:
4460 case CHIP_POLARIS11:
4461 case CHIP_POLARIS10:
b264d345 4462 case CHIP_POLARIS12:
7737de91 4463 case CHIP_VEGAM:
2c8ad2d5 4464 case CHIP_VEGA10:
2325ff30 4465 case CHIP_VEGA12:
1fe6bf2f 4466 case CHIP_VEGA20:
4562236b
HW		 4467 if (dce110_register_irq_handlers(dm->adev)) {
4468 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 4469 goto fail;
4562236b
HW		 4470 }
4471 break;
4472 default:
1d789535 4473 switch (adev->ip_versions[DCE_HWIP][0]) {
559f591d
AD		 4474 case IP_VERSION(1, 0, 0):
4475 case IP_VERSION(1, 0, 1):
c08182f2
AD		 4476 case IP_VERSION(2, 0, 2):
4477 case IP_VERSION(2, 0, 3):
4478 case IP_VERSION(2, 0, 0):
4479 case IP_VERSION(2, 1, 0):
4480 case IP_VERSION(3, 0, 0):
4481 case IP_VERSION(3, 0, 2):
4482 case IP_VERSION(3, 0, 3):
4483 case IP_VERSION(3, 0, 1):
4484 case IP_VERSION(3, 1, 2):
4485 case IP_VERSION(3, 1, 3):
e850f6b1 4486 case IP_VERSION(3, 1, 4):
b5b8ed44 4487 case IP_VERSION(3, 1, 5):
de7cc1b4 4488 case IP_VERSION(3, 1, 6):
577359ca
AP		 4489 case IP_VERSION(3, 2, 0):
4490 case IP_VERSION(3, 2, 1):
c08182f2
AD		 4491 if (dcn10_register_irq_handlers(dm->adev)) {
4492 DRM_ERROR("DM: Failed to initialize IRQ\n");
4493 goto fail;
4494 }
4495 break;
4496 default:
2cbc6f42 4497 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
1d789535 4498 adev->ip_versions[DCE_HWIP][0]);
2cbc6f42 4499 goto fail;
c08182f2 4500 }
2cbc6f42 4501 break;
4562236b
HW		 4502 }
4503
4562236b 4504 return 0;
cd8a2ae8 4505fail:
4562236b 4506 kfree(aencoder);
4562236b 4507 kfree(aconnector);
54087768 4508
59d0f396 4509 return -EINVAL;
4562236b
HW		 4510}
4511
7578ecda 4512static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b 4513{
eb3dc897 4514 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 4515 return;
4516}
4517
4518/******************************************************************************
4519 * amdgpu_display_funcs functions
4520 *****************************************************************************/
4521
1f6010a9 4522/*
4562236b
HW		 4523 * dm_bandwidth_update - program display watermarks
4524 *
4525 * @adev: amdgpu_device pointer
4526 *
4527 * Calculate and program the display watermarks and line buffer allocation.
4528 */
4529static void dm_bandwidth_update(struct amdgpu_device *adev)
4530{
49c07a99 4531 /* TODO: implement later */
4562236b
HW		 4532}
4533
39cc5be2 4534static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 4535 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4536 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 4537 .backlight_set_level = NULL, /* never called for DC */
4538 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 4539 .hpd_sense = NULL,/* called unconditionally */
4540 .hpd_set_polarity = NULL, /* called unconditionally */
4541 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 4542 .page_flip_get_scanoutpos =
4543 dm_crtc_get_scanoutpos,/* called unconditionally */
4544 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4545 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 4546};
4547
4548#if defined(CONFIG_DEBUG_KERNEL_DC)
4549
3ee6b26b
AD		 4550static ssize_t s3_debug_store(struct device *device,
4551 struct device_attribute *attr,
4552 const char *buf,
4553 size_t count)
4562236b
HW		 4554{
4555 int ret;
4556 int s3_state;
ef1de361 4557 struct drm_device *drm_dev = dev_get_drvdata(device);
1348969a 4558 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4562236b
HW		 4559
4560 ret = kstrtoint(buf, 0, &s3_state);
4561
4562 if (ret == 0) {
4563 if (s3_state) {
4564 dm_resume(adev);
4a580877 4565 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4562236b
HW		 4566 } else
4567 dm_suspend(adev);
4568 }
4569
4570 return ret == 0 ? count : 0;
4571}
4572
4573DEVICE_ATTR_WO(s3_debug);
4574
4575#endif
4576
a7ab3451
ML		 4577static int dm_init_microcode(struct amdgpu_device *adev)
4578{
4579 char *fw_name_dmub;
4580 int r;
4581
4582 switch (adev->ip_versions[DCE_HWIP][0]) {
4583 case IP_VERSION(2, 1, 0):
4584 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4585 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4586 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4587 break;
4588 case IP_VERSION(3, 0, 0):
4589 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4590 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4591 else
4592 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4593 break;
4594 case IP_VERSION(3, 0, 1):
4595 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4596 break;
4597 case IP_VERSION(3, 0, 2):
4598 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4599 break;
4600 case IP_VERSION(3, 0, 3):
4601 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4602 break;
4603 case IP_VERSION(3, 1, 2):
4604 case IP_VERSION(3, 1, 3):
4605 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4606 break;
4607 case IP_VERSION(3, 1, 4):
4608 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4609 break;
4610 case IP_VERSION(3, 1, 5):
4611 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4612 break;
4613 case IP_VERSION(3, 1, 6):
4614 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4615 break;
4616 case IP_VERSION(3, 2, 0):
4617 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4618 break;
4619 case IP_VERSION(3, 2, 1):
4620 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4621 break;
4622 default:
4623 /* ASIC doesn't support DMUB. */
4624 return 0;
4625 }
4626 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4627 if (r)
4628 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4629 return r;
4630}
4631
4562236b
HW		 4632static int dm_early_init(void *handle)
4633{
4634 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
44900af0
AD		 4635 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4636 struct atom_context *ctx = mode_info->atom_context;
4637 int index = GetIndexIntoMasterTable(DATA, Object_Header);
4638 u16 data_offset;
4639
4640 /* if there is no object header, skip DM */
4641 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4642 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4643 dev_info(adev->dev, "No object header, skipping DM\n");
4644 return -ENOENT;
4645 }
4562236b 4646
4562236b 4647 switch (adev->asic_type) {
55e56389
MR		 4648#if defined(CONFIG_DRM_AMD_DC_SI)
4649 case CHIP_TAHITI:
4650 case CHIP_PITCAIRN:
4651 case CHIP_VERDE:
4652 adev->mode_info.num_crtc = 6;
4653 adev->mode_info.num_hpd = 6;
4654 adev->mode_info.num_dig = 6;
4655 break;
4656 case CHIP_OLAND:
4657 adev->mode_info.num_crtc = 2;
4658 adev->mode_info.num_hpd = 2;
4659 adev->mode_info.num_dig = 2;
4660 break;
4661#endif
4562236b
HW		 4662 case CHIP_BONAIRE:
4663 case CHIP_HAWAII:
4664 adev->mode_info.num_crtc = 6;
4665 adev->mode_info.num_hpd = 6;
4666 adev->mode_info.num_dig = 6;
4562236b 4667 break;
cd4b356f
AD		 4668 case CHIP_KAVERI:
4669 adev->mode_info.num_crtc = 4;
4670 adev->mode_info.num_hpd = 6;
4671 adev->mode_info.num_dig = 7;
cd4b356f
AD		 4672 break;
4673 case CHIP_KABINI:
4674 case CHIP_MULLINS:
4675 adev->mode_info.num_crtc = 2;
4676 adev->mode_info.num_hpd = 6;
4677 adev->mode_info.num_dig = 6;
cd4b356f 4678 break;
4562236b
HW		 4679 case CHIP_FIJI:
4680 case CHIP_TONGA:
4681 adev->mode_info.num_crtc = 6;
4682 adev->mode_info.num_hpd = 6;
4683 adev->mode_info.num_dig = 7;
4562236b
HW		 4684 break;
4685 case CHIP_CARRIZO:
4686 adev->mode_info.num_crtc = 3;
4687 adev->mode_info.num_hpd = 6;
4688 adev->mode_info.num_dig = 9;
4562236b
HW		 4689 break;
4690 case CHIP_STONEY:
4691 adev->mode_info.num_crtc = 2;
4692 adev->mode_info.num_hpd = 6;
4693 adev->mode_info.num_dig = 9;
4562236b
HW		 4694 break;
4695 case CHIP_POLARIS11:
b264d345 4696 case CHIP_POLARIS12:
4562236b
HW		 4697 adev->mode_info.num_crtc = 5;
4698 adev->mode_info.num_hpd = 5;
4699 adev->mode_info.num_dig = 5;
4562236b
HW		 4700 break;
4701 case CHIP_POLARIS10:
7737de91 4702 case CHIP_VEGAM:
4562236b
HW		 4703 adev->mode_info.num_crtc = 6;
4704 adev->mode_info.num_hpd = 6;
4705 adev->mode_info.num_dig = 6;
4562236b 4706 break;
2c8ad2d5 4707 case CHIP_VEGA10:
2325ff30 4708 case CHIP_VEGA12:
1fe6bf2f 4709 case CHIP_VEGA20:
2c8ad2d5
AD		 4710 adev->mode_info.num_crtc = 6;
4711 adev->mode_info.num_hpd = 6;
4712 adev->mode_info.num_dig = 6;
4713 break;
4562236b 4714 default:
cae5c1ab 4715
1d789535 4716 switch (adev->ip_versions[DCE_HWIP][0]) {
c08182f2
AD		 4717 case IP_VERSION(2, 0, 2):
4718 case IP_VERSION(3, 0, 0):
4719 adev->mode_info.num_crtc = 6;
4720 adev->mode_info.num_hpd = 6;
4721 adev->mode_info.num_dig = 6;
4722 break;
4723 case IP_VERSION(2, 0, 0):
4724 case IP_VERSION(3, 0, 2):
4725 adev->mode_info.num_crtc = 5;
4726 adev->mode_info.num_hpd = 5;
4727 adev->mode_info.num_dig = 5;
4728 break;
4729 case IP_VERSION(2, 0, 3):
4730 case IP_VERSION(3, 0, 3):
4731 adev->mode_info.num_crtc = 2;
4732 adev->mode_info.num_hpd = 2;
4733 adev->mode_info.num_dig = 2;
4734 break;
559f591d
AD		 4735 case IP_VERSION(1, 0, 0):
4736 case IP_VERSION(1, 0, 1):
c08182f2
AD		 4737 case IP_VERSION(3, 0, 1):
4738 case IP_VERSION(2, 1, 0):
4739 case IP_VERSION(3, 1, 2):
4740 case IP_VERSION(3, 1, 3):
e850f6b1 4741 case IP_VERSION(3, 1, 4):
b5b8ed44 4742 case IP_VERSION(3, 1, 5):
de7cc1b4 4743 case IP_VERSION(3, 1, 6):
577359ca
AP		 4744 case IP_VERSION(3, 2, 0):
4745 case IP_VERSION(3, 2, 1):
c08182f2
AD		 4746 adev->mode_info.num_crtc = 4;
4747 adev->mode_info.num_hpd = 4;
4748 adev->mode_info.num_dig = 4;
4749 break;
4750 default:
2cbc6f42 4751 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
1d789535 4752 adev->ip_versions[DCE_HWIP][0]);
2cbc6f42 4753 return -EINVAL;
c08182f2 4754 }
2cbc6f42 4755 break;
4562236b
HW		 4756 }
4757
39cc5be2
AD		 4758 if (adev->mode_info.funcs == NULL)
4759 adev->mode_info.funcs = &dm_display_funcs;
4760
1f6010a9
DF		 4761 /*
4762 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 4763 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 4764 * amdgpu_device_init()
4765 */
4562236b
HW		 4766#if defined(CONFIG_DEBUG_KERNEL_DC)
4767 device_create_file(
4a580877 4768 adev_to_drm(adev)->dev,
4562236b
HW		 4769 &dev_attr_s3_debug);
4770#endif
d09ef243 4771 adev->dc_enabled = true;
4562236b 4772
a7ab3451 4773 return dm_init_microcode(adev);
4562236b
HW		 4774}
4775
e7b07cee
HW		 4776static bool modereset_required(struct drm_crtc_state *crtc_state)
4777{
2afda735 4778 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
e7b07cee
HW		 4779}
4780
7578ecda 4781static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 4782{
4783 drm_encoder_cleanup(encoder);
4784 kfree(encoder);
4785}
4786
4787static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4788 .destroy = amdgpu_dm_encoder_destroy,
4789};
4790
5d945cbc
RS		 4791static int
4792fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4793 const enum surface_pixel_format format,
4794 enum dc_color_space *color_space)
6300b3bd 4795{
5d945cbc 4796 bool full_range;
6300b3bd 4797
5d945cbc
RS		 4798 *color_space = COLOR_SPACE_SRGB;
4799
4800 /* DRM color properties only affect non-RGB formats. */
4801 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4802 return 0;
4803
4804 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4805
4806 switch (plane_state->color_encoding) {
4807 case DRM_COLOR_YCBCR_BT601:
4808 if (full_range)
4809 *color_space = COLOR_SPACE_YCBCR601;
4810 else
4811 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
6300b3bd
MK		 4812 break;
4813
5d945cbc
RS		 4814 case DRM_COLOR_YCBCR_BT709:
4815 if (full_range)
4816 *color_space = COLOR_SPACE_YCBCR709;
4817 else
4818 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
6300b3bd
MK		 4819 break;
4820
5d945cbc
RS		 4821 case DRM_COLOR_YCBCR_BT2020:
4822 if (full_range)
4823 *color_space = COLOR_SPACE_2020_YCBCR;
4824 else
4825 return -EINVAL;
6300b3bd 4826 break;
6300b3bd 4827
5d945cbc
RS		 4828 default:
4829 return -EINVAL;
4830 }
6300b3bd 4831
5d945cbc 4832 return 0;
6300b3bd
MK		 4833}
4834
5d945cbc
RS		 4835static int
4836fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4837 const struct drm_plane_state *plane_state,
ae67558b 4838 const u64 tiling_flags,
5d945cbc
RS		 4839 struct dc_plane_info *plane_info,
4840 struct dc_plane_address *address,
4841 bool tmz_surface,
4842 bool force_disable_dcc)
e7b07cee 4843{
5d945cbc
RS		 4844 const struct drm_framebuffer *fb = plane_state->fb;
4845 const struct amdgpu_framebuffer *afb =
4846 to_amdgpu_framebuffer(plane_state->fb);
4847 int ret;
e7b07cee 4848
5d945cbc 4849 memset(plane_info, 0, sizeof(*plane_info));
e7b07cee 4850
5d945cbc
RS		 4851 switch (fb->format->format) {
4852 case DRM_FORMAT_C8:
4853 plane_info->format =
4854 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4855 break;
4856 case DRM_FORMAT_RGB565:
4857 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4858 break;
4859 case DRM_FORMAT_XRGB8888:
4860 case DRM_FORMAT_ARGB8888:
4861 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4862 break;
4863 case DRM_FORMAT_XRGB2101010:
4864 case DRM_FORMAT_ARGB2101010:
4865 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4866 break;
4867 case DRM_FORMAT_XBGR2101010:
4868 case DRM_FORMAT_ABGR2101010:
4869 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4870 break;
4871 case DRM_FORMAT_XBGR8888:
4872 case DRM_FORMAT_ABGR8888:
4873 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4874 break;
4875 case DRM_FORMAT_NV21:
4876 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4877 break;
4878 case DRM_FORMAT_NV12:
4879 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4880 break;
4881 case DRM_FORMAT_P010:
4882 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4883 break;
4884 case DRM_FORMAT_XRGB16161616F:
4885 case DRM_FORMAT_ARGB16161616F:
4886 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4887 break;
4888 case DRM_FORMAT_XBGR16161616F:
4889 case DRM_FORMAT_ABGR16161616F:
4890 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4891 break;
4892 case DRM_FORMAT_XRGB16161616:
4893 case DRM_FORMAT_ARGB16161616:
4894 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4895 break;
4896 case DRM_FORMAT_XBGR16161616:
4897 case DRM_FORMAT_ABGR16161616:
4898 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4899 break;
4900 default:
4901 DRM_ERROR(
4902 "Unsupported screen format %p4cc\n",
4903 &fb->format->format);
d89f6048 4904 return -EINVAL;
5d945cbc 4905 }
d89f6048 4906
5d945cbc
RS		 4907 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4908 case DRM_MODE_ROTATE_0:
4909 plane_info->rotation = ROTATION_ANGLE_0;
4910 break;
4911 case DRM_MODE_ROTATE_90:
4912 plane_info->rotation = ROTATION_ANGLE_90;
4913 break;
4914 case DRM_MODE_ROTATE_180:
4915 plane_info->rotation = ROTATION_ANGLE_180;
4916 break;
4917 case DRM_MODE_ROTATE_270:
4918 plane_info->rotation = ROTATION_ANGLE_270;
4919 break;
4920 default:
4921 plane_info->rotation = ROTATION_ANGLE_0;
4922 break;
4923 }
695af5f9 4924
695af5f9 4925
5d945cbc
RS		 4926 plane_info->visible = true;
4927 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee 4928
22c42b0e 4929 plane_info->layer_index = plane_state->normalized_zpos;
e7b07cee 4930
5d945cbc
RS		 4931 ret = fill_plane_color_attributes(plane_state, plane_info->format,
4932 &plane_info->color_space);
4933 if (ret)
4934 return ret;
e7b07cee 4935
5d945cbc
RS		 4936 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4937 plane_info->rotation, tiling_flags,
4938 &plane_info->tiling_info,
4939 &plane_info->plane_size,
4940 &plane_info->dcc, address,
4941 tmz_surface, force_disable_dcc);
4942 if (ret)
4943 return ret;
e7b07cee 4944
5d945cbc
RS		 4945 fill_blending_from_plane_state(
4946 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4947 &plane_info->global_alpha, &plane_info->global_alpha_value);
e7b07cee 4948
5d945cbc
RS		 4949 return 0;
4950}
e7b07cee 4951
5d945cbc
RS		 4952static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4953 struct dc_plane_state *dc_plane_state,
4954 struct drm_plane_state *plane_state,
4955 struct drm_crtc_state *crtc_state)
4956{
4957 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4958 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4959 struct dc_scaling_info scaling_info;
4960 struct dc_plane_info plane_info;
4961 int ret;
4962 bool force_disable_dcc = false;
6300b3bd 4963
5d945cbc
RS		 4964 ret = fill_dc_scaling_info(adev, plane_state, &scaling_info);
4965 if (ret)
4966 return ret;
e7b07cee 4967
5d945cbc
RS		 4968 dc_plane_state->src_rect = scaling_info.src_rect;
4969 dc_plane_state->dst_rect = scaling_info.dst_rect;
4970 dc_plane_state->clip_rect = scaling_info.clip_rect;
4971 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
6491f0c0 4972
5d945cbc
RS		 4973 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4974 ret = fill_dc_plane_info_and_addr(adev, plane_state,
4975 afb->tiling_flags,
4976 &plane_info,
4977 &dc_plane_state->address,
4978 afb->tmz_surface,
4979 force_disable_dcc);
4980 if (ret)
4981 return ret;
6491f0c0 4982
5d945cbc
RS		 4983 dc_plane_state->format = plane_info.format;
4984 dc_plane_state->color_space = plane_info.color_space;
4985 dc_plane_state->format = plane_info.format;
4986 dc_plane_state->plane_size = plane_info.plane_size;
4987 dc_plane_state->rotation = plane_info.rotation;
4988 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4989 dc_plane_state->stereo_format = plane_info.stereo_format;
4990 dc_plane_state->tiling_info = plane_info.tiling_info;
4991 dc_plane_state->visible = plane_info.visible;
4992 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4993 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
4994 dc_plane_state->global_alpha = plane_info.global_alpha;
4995 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4996 dc_plane_state->dcc = plane_info.dcc;
22c42b0e 4997 dc_plane_state->layer_index = plane_info.layer_index;
5d945cbc 4998 dc_plane_state->flip_int_enabled = true;
6491f0c0 4999
695af5f9 5000 /*
5d945cbc
RS		 5001 * Always set input transfer function, since plane state is refreshed
5002 * every time.
695af5f9 5003 */
5d945cbc
RS		 5004 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5005 if (ret)
5006 return ret;
e7b07cee 5007
695af5f9 5008 return 0;
4562236b 5009}
695af5f9 5010
30ebe415
HM		 5011static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5012 struct rect *dirty_rect, int32_t x,
ae67558b 5013 s32 y, s32 width, s32 height,
30ebe415
HM		 5014 int *i, bool ffu)
5015{
5016 if (*i > DC_MAX_DIRTY_RECTS)
5017 return;
5018
5019 if (*i == DC_MAX_DIRTY_RECTS)
5020 goto out;
5021
5022 dirty_rect->x = x;
5023 dirty_rect->y = y;
5024 dirty_rect->width = width;
5025 dirty_rect->height = height;
5026
5027 if (ffu)
5028 drm_dbg(plane->dev,
5029 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5030 plane->base.id, width, height);
5031 else
5032 drm_dbg(plane->dev,
5033 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5034 plane->base.id, x, y, width, height);
5035
5036out:
5037 (*i)++;
5038}
5039
5d945cbc
RS		 5040/**
5041 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5042 *
5043 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5044 * remote fb
5045 * @old_plane_state: Old state of @plane
5046 * @new_plane_state: New state of @plane
5047 * @crtc_state: New state of CRTC connected to the @plane
5048 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
d6ed6d0d 5049 * @dirty_regions_changed: dirty regions changed
5d945cbc
RS		 5050 *
5051 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5052 * (referred to as "damage clips" in DRM nomenclature) that require updating on
5053 * the eDP remote buffer. The responsibility of specifying the dirty regions is
5054 * amdgpu_dm's.
5055 *
5056 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5057 * plane with regions that require flushing to the eDP remote buffer. In
5058 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5059 * implicitly provide damage clips without any client support via the plane
5060 * bounds.
5d945cbc
RS		 5061 */
5062static void fill_dc_dirty_rects(struct drm_plane *plane,
5063 struct drm_plane_state *old_plane_state,
5064 struct drm_plane_state *new_plane_state,
5065 struct drm_crtc_state *crtc_state,
d6ed6d0d
TC		 5066 struct dc_flip_addrs *flip_addrs,
5067 bool *dirty_regions_changed)
5d945cbc
RS		 5068{
5069 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5070 struct rect *dirty_rects = flip_addrs->dirty_rects;
ae67558b 5071 u32 num_clips;
30ebe415 5072 struct drm_mode_rect *clips;
5d945cbc
RS		 5073 bool bb_changed;
5074 bool fb_changed;
ae67558b 5075 u32 i = 0;
d6ed6d0d 5076 *dirty_regions_changed = false;
e7b07cee 5077
7cc191ee
LL		 5078 /*
5079 * Cursor plane has it's own dirty rect update interface. See
5080 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5081 */
5082 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5083 return;
5084
30ebe415
HM		 5085 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5086 clips = drm_plane_get_damage_clips(new_plane_state);
5087
7cc191ee 5088 if (!dm_crtc_state->mpo_requested) {
30ebe415
HM		 5089 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5090 goto ffu;
5091
5092 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5093 fill_dc_dirty_rect(new_plane_state->plane,
5094 &dirty_rects[i], clips->x1,
5095 clips->y1, clips->x2 - clips->x1,
5096 clips->y2 - clips->y1,
5097 &flip_addrs->dirty_rect_count,
5098 false);
7cc191ee
LL		 5099 return;
5100 }
5101
5102 /*
5103 * MPO is requested. Add entire plane bounding box to dirty rects if
5104 * flipped to or damaged.
5105 *
5106 * If plane is moved or resized, also add old bounding box to dirty
5107 * rects.
5108 */
7cc191ee
LL		 5109 fb_changed = old_plane_state->fb->base.id !=
5110 new_plane_state->fb->base.id;
5111 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5112 old_plane_state->crtc_y != new_plane_state->crtc_y ||
5113 old_plane_state->crtc_w != new_plane_state->crtc_w ||
5114 old_plane_state->crtc_h != new_plane_state->crtc_h);
5115
30ebe415
HM		 5116 drm_dbg(plane->dev,
5117 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5118 new_plane_state->plane->base.id,
5119 bb_changed, fb_changed, num_clips);
7cc191ee 5120
d6ed6d0d
TC		 5121 *dirty_regions_changed = bb_changed;
5122
7cc191ee 5123 if (bb_changed) {
30ebe415
HM		 5124 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5125 new_plane_state->crtc_x,
5126 new_plane_state->crtc_y,
5127 new_plane_state->crtc_w,
5128 new_plane_state->crtc_h, &i, false);
5129
5130 /* Add old plane bounding-box if plane is moved or resized */
5131 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5132 old_plane_state->crtc_x,
5133 old_plane_state->crtc_y,
5134 old_plane_state->crtc_w,
5135 old_plane_state->crtc_h, &i, false);
5136 }
5137
5138 if (num_clips) {
5139 for (; i < num_clips; clips++)
5140 fill_dc_dirty_rect(new_plane_state->plane,
5141 &dirty_rects[i], clips->x1,
5142 clips->y1, clips->x2 - clips->x1,
5143 clips->y2 - clips->y1, &i, false);
5144 } else if (fb_changed && !bb_changed) {
5145 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5146 new_plane_state->crtc_x,
5147 new_plane_state->crtc_y,
5148 new_plane_state->crtc_w,
5149 new_plane_state->crtc_h, &i, false);
5150 }
5151
5152 if (i > DC_MAX_DIRTY_RECTS)
5153 goto ffu;
7cc191ee
LL		 5154
5155 flip_addrs->dirty_rect_count = i;
30ebe415
HM		 5156 return;
5157
5158ffu:
5159 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5160 dm_crtc_state->base.mode.crtc_hdisplay,
5161 dm_crtc_state->base.mode.crtc_vdisplay,
5162 &flip_addrs->dirty_rect_count, true);
7cc191ee
LL		 5163}
5164
3ee6b26b
AD		 5165static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5166 const struct dm_connector_state *dm_state,
5167 struct dc_stream_state *stream)
e7b07cee
HW		 5168{
5169 enum amdgpu_rmx_type rmx_type;
5170
5171 struct rect src = { 0 }; /* viewport in composition space*/
5172 struct rect dst = { 0 }; /* stream addressable area */
5173
5174 /* no mode. nothing to be done */
5175 if (!mode)
5176 return;
5177
5178 /* Full screen scaling by default */
5179 src.width = mode->hdisplay;
5180 src.height = mode->vdisplay;
5181 dst.width = stream->timing.h_addressable;
5182 dst.height = stream->timing.v_addressable;
5183
f4791779
HW		 5184 if (dm_state) {
5185 rmx_type = dm_state->scaling;
5186 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5187 if (src.width * dst.height <
5188 src.height * dst.width) {
5189 /* height needs less upscaling/more downscaling */
5190 dst.width = src.width *
5191 dst.height / src.height;
5192 } else {
5193 /* width needs less upscaling/more downscaling */
5194 dst.height = src.height *
5195 dst.width / src.width;
5196 }
5197 } else if (rmx_type == RMX_CENTER) {
5198 dst = src;
e7b07cee 5199 }
e7b07cee 5200
f4791779
HW		 5201 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5202 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 5203
f4791779
HW		 5204 if (dm_state->underscan_enable) {
5205 dst.x += dm_state->underscan_hborder / 2;
5206 dst.y += dm_state->underscan_vborder / 2;
5207 dst.width -= dm_state->underscan_hborder;
5208 dst.height -= dm_state->underscan_vborder;
5209 }
e7b07cee
HW		 5210 }
5211
5212 stream->src = src;
5213 stream->dst = dst;
5214
4711c033
LT		 5215 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
5216 dst.x, dst.y, dst.width, dst.height);
e7b07cee
HW		 5217
5218}
5219
3ee6b26b 5220static enum dc_color_depth
42ba01fc 5221convert_color_depth_from_display_info(const struct drm_connector *connector,
cbd14ae7 5222 bool is_y420, int requested_bpc)
e7b07cee 5223{
ae67558b 5224 u8 bpc;
01c22997 5225
1bc22f20
SW		 5226 if (is_y420) {
5227 bpc = 8;
5228
5229 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5230 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5231 bpc = 16;
5232 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5233 bpc = 12;
5234 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5235 bpc = 10;
5236 } else {
5237 bpc = (uint8_t)connector->display_info.bpc;
5238 /* Assume 8 bpc by default if no bpc is specified. */
5239 bpc = bpc ? bpc : 8;
5240 }
e7b07cee 5241
cbd14ae7 5242 if (requested_bpc > 0) {
01c22997
NK		 5243 /*
5244 * Cap display bpc based on the user requested value.
5245 *
5246 * The value for state->max_bpc may not correctly updated
5247 * depending on when the connector gets added to the state
5248 * or if this was called outside of atomic check, so it
5249 * can't be used directly.
5250 */
cbd14ae7 5251 bpc = min_t(u8, bpc, requested_bpc);
01c22997 5252
1825fd34
NK		 5253 /* Round down to the nearest even number. */
5254 bpc = bpc - (bpc & 1);
5255 }
07e3a1cf 5256
e7b07cee
HW		 5257 switch (bpc) {
5258 case 0:
1f6010a9
DF		 5259 /*
5260 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 5261 * EDID revision before 1.4
5262 * TODO: Fix edid parsing
5263 */
5264 return COLOR_DEPTH_888;
5265 case 6:
5266 return COLOR_DEPTH_666;
5267 case 8:
5268 return COLOR_DEPTH_888;
5269 case 10:
5270 return COLOR_DEPTH_101010;
5271 case 12:
5272 return COLOR_DEPTH_121212;
5273 case 14:
5274 return COLOR_DEPTH_141414;
5275 case 16:
5276 return COLOR_DEPTH_161616;
5277 default:
5278 return COLOR_DEPTH_UNDEFINED;
5279 }
5280}
5281
3ee6b26b
AD		 5282static enum dc_aspect_ratio
5283get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 5284{
e11d4147
LSL		 5285 /* 1-1 mapping, since both enums follow the HDMI spec. */
5286 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 5287}
5288
3ee6b26b
AD		 5289static enum dc_color_space
5290get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 5291{
5292 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5293
5294 switch (dc_crtc_timing->pixel_encoding) {
5295 case PIXEL_ENCODING_YCBCR422:
5296 case PIXEL_ENCODING_YCBCR444:
5297 case PIXEL_ENCODING_YCBCR420:
5298 {
5299 /*
5300 * 27030khz is the separation point between HDTV and SDTV
5301 * according to HDMI spec, we use YCbCr709 and YCbCr601
5302 * respectively
5303 */
380604e2 5304 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 5305 if (dc_crtc_timing->flags.Y_ONLY)
5306 color_space =
5307 COLOR_SPACE_YCBCR709_LIMITED;
5308 else
5309 color_space = COLOR_SPACE_YCBCR709;
5310 } else {
5311 if (dc_crtc_timing->flags.Y_ONLY)
5312 color_space =
5313 COLOR_SPACE_YCBCR601_LIMITED;
5314 else
5315 color_space = COLOR_SPACE_YCBCR601;
5316 }
5317
5318 }
5319 break;
5320 case PIXEL_ENCODING_RGB:
5321 color_space = COLOR_SPACE_SRGB;
5322 break;
5323
5324 default:
5325 WARN_ON(1);
5326 break;
5327 }
5328
5329 return color_space;
5330}
5331
ea117312
TA		 5332static bool adjust_colour_depth_from_display_info(
5333 struct dc_crtc_timing *timing_out,
5334 const struct drm_display_info *info)
400443e8 5335{
ea117312 5336 enum dc_color_depth depth = timing_out->display_color_depth;
400443e8 5337 int normalized_clk;
400443e8 5338 do {
380604e2 5339 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 5340 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5341 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5342 normalized_clk /= 2;
5343 /* Adjusting pix clock following on HDMI spec based on colour depth */
ea117312
TA		 5344 switch (depth) {
5345 case COLOR_DEPTH_888:
5346 break;
400443e8
ML		 5347 case COLOR_DEPTH_101010:
5348 normalized_clk = (normalized_clk * 30) / 24;
5349 break;
5350 case COLOR_DEPTH_121212:
5351 normalized_clk = (normalized_clk * 36) / 24;
5352 break;
5353 case COLOR_DEPTH_161616:
5354 normalized_clk = (normalized_clk * 48) / 24;
5355 break;
5356 default:
ea117312
TA		 5357 /* The above depths are the only ones valid for HDMI. */
5358 return false;
400443e8 5359 }
ea117312
TA		 5360 if (normalized_clk <= info->max_tmds_clock) {
5361 timing_out->display_color_depth = depth;
5362 return true;
5363 }
5364 } while (--depth > COLOR_DEPTH_666);
5365 return false;
400443e8 5366}
e7b07cee 5367
42ba01fc
NK		 5368static void fill_stream_properties_from_drm_display_mode(
5369 struct dc_stream_state *stream,
5370 const struct drm_display_mode *mode_in,
5371 const struct drm_connector *connector,
5372 const struct drm_connector_state *connector_state,
cbd14ae7
SW		 5373 const struct dc_stream_state *old_stream,
5374 int requested_bpc)
e7b07cee
HW		 5375{
5376 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 5377 const struct drm_display_info *info = &connector->display_info;
d4252eee 5378 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1cb1d477
WL		 5379 struct hdmi_vendor_infoframe hv_frame;
5380 struct hdmi_avi_infoframe avi_frame;
e7b07cee 5381
acf83f86
WL		 5382 memset(&hv_frame, 0, sizeof(hv_frame));
5383 memset(&avi_frame, 0, sizeof(avi_frame));
5384
e7b07cee
HW		 5385 timing_out->h_border_left = 0;
5386 timing_out->h_border_right = 0;
5387 timing_out->v_border_top = 0;
5388 timing_out->v_border_bottom = 0;
5389 /* TODO: un-hardcode */
fe61a2f1 5390 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 5391 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1 5392 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
d4252eee
SW		 5393 else if (drm_mode_is_420_also(info, mode_in)
5394 && aconnector->force_yuv420_output)
5395 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
c03d0b52 5396 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
ceb3dbb4 5397 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 5398 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5399 else
5400 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5401
5402 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5403 timing_out->display_color_depth = convert_color_depth_from_display_info(
cbd14ae7
SW		 5404 connector,
5405 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5406 requested_bpc);
e7b07cee
HW		 5407 timing_out->scan_type = SCANNING_TYPE_NODATA;
5408 timing_out->hdmi_vic = 0;
b333730d 5409
5d945cbc 5410 if (old_stream) {
b333730d
BL		 5411 timing_out->vic = old_stream->timing.vic;
5412 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5413 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5414 } else {
5415 timing_out->vic = drm_match_cea_mode(mode_in);
5416 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5417 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5418 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5419 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5420 }
e7b07cee 5421
1cb1d477
WL		 5422 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5423 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5424 timing_out->vic = avi_frame.video_code;
5425 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5426 timing_out->hdmi_vic = hv_frame.vic;
5427 }
5428
fe8858bb
NC		 5429 if (is_freesync_video_mode(mode_in, aconnector)) {
5430 timing_out->h_addressable = mode_in->hdisplay;
5431 timing_out->h_total = mode_in->htotal;
5432 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5433 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5434 timing_out->v_total = mode_in->vtotal;
5435 timing_out->v_addressable = mode_in->vdisplay;
5436 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5437 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5438 timing_out->pix_clk_100hz = mode_in->clock * 10;
5439 } else {
5440 timing_out->h_addressable = mode_in->crtc_hdisplay;
5441 timing_out->h_total = mode_in->crtc_htotal;
5442 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5443 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5444 timing_out->v_total = mode_in->crtc_vtotal;
5445 timing_out->v_addressable = mode_in->crtc_vdisplay;
5446 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5447 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5448 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5449 }
a85ba005 5450
e7b07cee 5451 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee 5452
e43a432c
AK		 5453 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5454 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ea117312
TA		 5455 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5456 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5457 drm_mode_is_420_also(info, mode_in) &&
5458 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5459 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5460 adjust_colour_depth_from_display_info(timing_out, info);
5461 }
5462 }
766f1792
JA		 5463
5464 stream->output_color_space = get_output_color_space(timing_out);
e7b07cee
HW		 5465}
5466
3ee6b26b
AD		 5467static void fill_audio_info(struct audio_info *audio_info,
5468 const struct drm_connector *drm_connector,
5469 const struct dc_sink *dc_sink)
e7b07cee
HW		 5470{
5471 int i = 0;
5472 int cea_revision = 0;
5473 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5474
5475 audio_info->manufacture_id = edid_caps->manufacturer_id;
5476 audio_info->product_id = edid_caps->product_id;
5477
5478 cea_revision = drm_connector->display_info.cea_rev;
5479
090afc1e 5480 strscpy(audio_info->display_name,
d2b2562c 5481 edid_caps->display_name,
090afc1e 5482 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 5483
b830ebc9 5484 if (cea_revision >= 3) {
e7b07cee
HW		 5485 audio_info->mode_count = edid_caps->audio_mode_count;
5486
5487 for (i = 0; i < audio_info->mode_count; ++i) {
5488 audio_info->modes[i].format_code =
5489 (enum audio_format_code)
5490 (edid_caps->audio_modes[i].format_code);
5491 audio_info->modes[i].channel_count =
5492 edid_caps->audio_modes[i].channel_count;
5493 audio_info->modes[i].sample_rates.all =
5494 edid_caps->audio_modes[i].sample_rate;
5495 audio_info->modes[i].sample_size =
5496 edid_caps->audio_modes[i].sample_size;
5497 }
5498 }
5499
5500 audio_info->flags.all = edid_caps->speaker_flags;
5501
5502 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 5503 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 5504 audio_info->video_latency = drm_connector->video_latency[0];
5505 audio_info->audio_latency = drm_connector->audio_latency[0];
5506 }
5507
5508 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5509
5510}
5511
3ee6b26b
AD		 5512static void
5513copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5514 struct drm_display_mode *dst_mode)
e7b07cee
HW		 5515{
5516 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5517 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5518 dst_mode->crtc_clock = src_mode->crtc_clock;
5519 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5520 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 5521 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 5522 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5523 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5524 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5525 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5526 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5527 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5528 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5529 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5530}
5531
3ee6b26b
AD		 5532static void
5533decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5534 const struct drm_display_mode *native_mode,
5535 bool scale_enabled)
e7b07cee
HW		 5536{
5537 if (scale_enabled) {
5538 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5539 } else if (native_mode->clock == drm_mode->clock &&
5540 native_mode->htotal == drm_mode->htotal &&
5541 native_mode->vtotal == drm_mode->vtotal) {
5542 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5543 } else {
5544 /* no scaling nor amdgpu inserted, no need to patch */
5545 }
5546}
5547
aed15309
ML		 5548static struct dc_sink *
5549create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 5550{
2e0ac3d6 5551 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 5552 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 5553 sink_init_data.link = aconnector->dc_link;
5554 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5555
5556 sink = dc_sink_create(&sink_init_data);
423788c7 5557 if (!sink) {
2e0ac3d6 5558 DRM_ERROR("Failed to create sink!\n");
aed15309 5559 return NULL;
423788c7 5560 }
2e0ac3d6 5561 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 5562
aed15309 5563 return sink;
2e0ac3d6
HW		 5564}
5565
fa2123db
ML		 5566static void set_multisync_trigger_params(
5567 struct dc_stream_state *stream)
5568{
ec372186
ML		 5569 struct dc_stream_state *master = NULL;
5570
fa2123db 5571 if (stream->triggered_crtc_reset.enabled) {
ec372186
ML		 5572 master = stream->triggered_crtc_reset.event_source;
5573 stream->triggered_crtc_reset.event =
5574 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5575 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5576 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
fa2123db
ML		 5577 }
5578}
5579
5580static void set_master_stream(struct dc_stream_state *stream_set[],
5581 int stream_count)
5582{
5583 int j, highest_rfr = 0, master_stream = 0;
5584
5585 for (j = 0; j < stream_count; j++) {
5586 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5587 int refresh_rate = 0;
5588
380604e2 5589 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 5590 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5591 if (refresh_rate > highest_rfr) {
5592 highest_rfr = refresh_rate;
5593 master_stream = j;
5594 }
5595 }
5596 }
5597 for (j = 0; j < stream_count; j++) {
03736f4c 5598 if (stream_set[j])
fa2123db
ML		 5599 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5600 }
5601}
5602
5603static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5604{
5605 int i = 0;
ec372186 5606 struct dc_stream_state *stream;
fa2123db
ML		 5607
5608 if (context->stream_count < 2)
5609 return;
5610 for (i = 0; i < context->stream_count ; i++) {
5611 if (!context->streams[i])
5612 continue;
1f6010a9
DF		 5613 /*
5614 * TODO: add a function to read AMD VSDB bits and set
fa2123db 5615 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 5616 * For now it's set to false
fa2123db 5617 */
fa2123db 5618 }
ec372186 5619
fa2123db 5620 set_master_stream(context->streams, context->stream_count);
ec372186
ML		 5621
5622 for (i = 0; i < context->stream_count ; i++) {
5623 stream = context->streams[i];
5624
5625 if (!stream)
5626 continue;
5627
5628 set_multisync_trigger_params(stream);
5629 }
fa2123db
ML		 5630}
5631
5d945cbc
RS		 5632/**
5633 * DOC: FreeSync Video
5634 *
5635 * When a userspace application wants to play a video, the content follows a
5636 * standard format definition that usually specifies the FPS for that format.
5637 * The below list illustrates some video format and the expected FPS,
5638 * respectively:
5639 *
5640 * - TV/NTSC (23.976 FPS)
5641 * - Cinema (24 FPS)
5642 * - TV/PAL (25 FPS)
5643 * - TV/NTSC (29.97 FPS)
5644 * - TV/NTSC (30 FPS)
5645 * - Cinema HFR (48 FPS)
5646 * - TV/PAL (50 FPS)
5647 * - Commonly used (60 FPS)
5648 * - Multiples of 24 (48,72,96 FPS)
5649 *
5650 * The list of standards video format is not huge and can be added to the
5651 * connector modeset list beforehand. With that, userspace can leverage
5652 * FreeSync to extends the front porch in order to attain the target refresh
5653 * rate. Such a switch will happen seamlessly, without screen blanking or
5654 * reprogramming of the output in any other way. If the userspace requests a
5655 * modesetting change compatible with FreeSync modes that only differ in the
5656 * refresh rate, DC will skip the full update and avoid blink during the
5657 * transition. For example, the video player can change the modesetting from
5658 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5659 * causing any display blink. This same concept can be applied to a mode
5660 * setting change.
5661 */
5662static struct drm_display_mode *
5663get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5664 bool use_probed_modes)
5665{
5666 struct drm_display_mode *m, *m_pref = NULL;
5667 u16 current_refresh, highest_refresh;
5668 struct list_head *list_head = use_probed_modes ?
5669 &aconnector->base.probed_modes :
5670 &aconnector->base.modes;
5671
5672 if (aconnector->freesync_vid_base.clock != 0)
5673 return &aconnector->freesync_vid_base;
5674
5675 /* Find the preferred mode */
5676 list_for_each_entry (m, list_head, head) {
5677 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5678 m_pref = m;
5679 break;
5680 }
5681 }
5682
5683 if (!m_pref) {
5684 /* Probably an EDID with no preferred mode. Fallback to first entry */
5685 m_pref = list_first_entry_or_null(
5686 &aconnector->base.modes, struct drm_display_mode, head);
5687 if (!m_pref) {
5688 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5689 return NULL;
5690 }
5691 }
5692
5693 highest_refresh = drm_mode_vrefresh(m_pref);
5694
5695 /*
5696 * Find the mode with highest refresh rate with same resolution.
5697 * For some monitors, preferred mode is not the mode with highest
5698 * supported refresh rate.
5699 */
5700 list_for_each_entry (m, list_head, head) {
5701 current_refresh = drm_mode_vrefresh(m);
5702
5703 if (m->hdisplay == m_pref->hdisplay &&
5704 m->vdisplay == m_pref->vdisplay &&
5705 highest_refresh < current_refresh) {
5706 highest_refresh = current_refresh;
5707 m_pref = m;
5708 }
5709 }
5710
5711 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5712 return m_pref;
5713}
5714
5715static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5716 struct amdgpu_dm_connector *aconnector)
5717{
5718 struct drm_display_mode *high_mode;
5719 int timing_diff;
5720
5721 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5722 if (!high_mode || !mode)
5723 return false;
5724
5725 timing_diff = high_mode->vtotal - mode->vtotal;
5726
5727 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5728 high_mode->hdisplay != mode->hdisplay ||
5729 high_mode->vdisplay != mode->vdisplay ||
5730 high_mode->hsync_start != mode->hsync_start ||
5731 high_mode->hsync_end != mode->hsync_end ||
5732 high_mode->htotal != mode->htotal ||
5733 high_mode->hskew != mode->hskew ||
5734 high_mode->vscan != mode->vscan ||
5735 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5736 high_mode->vsync_end - mode->vsync_end != timing_diff)
5737 return false;
5738 else
5739 return true;
5740}
5741
998b7ad2 5742static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5d945cbc
RS		 5743 struct dc_sink *sink, struct dc_stream_state *stream,
5744 struct dsc_dec_dpcd_caps *dsc_caps)
998b7ad2
FZ		 5745{
5746 stream->timing.flags.DSC = 0;
63ad5371 5747 dsc_caps->is_dsc_supported = false;
998b7ad2 5748
2665f63a 5749 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5d945cbc 5750 sink->sink_signal == SIGNAL_TYPE_EDP)) {
50b1f44e
FZ		 5751 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5752 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5753 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5754 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5755 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5756 dsc_caps);
998b7ad2
FZ		 5757 }
5758}
5759
5d945cbc 5760
2665f63a
ML		 5761static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5762 struct dc_sink *sink, struct dc_stream_state *stream,
5763 struct dsc_dec_dpcd_caps *dsc_caps,
5764 uint32_t max_dsc_target_bpp_limit_override)
5765{
5766 const struct dc_link_settings *verified_link_cap = NULL;
ae67558b
SS		 5767 u32 link_bw_in_kbps;
5768 u32 edp_min_bpp_x16, edp_max_bpp_x16;
2665f63a
ML		 5769 struct dc *dc = sink->ctx->dc;
5770 struct dc_dsc_bw_range bw_range = {0};
5771 struct dc_dsc_config dsc_cfg = {0};
de534c1c
MH		 5772 struct dc_dsc_config_options dsc_options = {0};
5773
5774 dc_dsc_get_default_config_option(dc, &dsc_options);
5775 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
2665f63a
ML		 5776
5777 verified_link_cap = dc_link_get_link_cap(stream->link);
5778 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5779 edp_min_bpp_x16 = 8 * 16;
5780 edp_max_bpp_x16 = 8 * 16;
5781
5782 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5783 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5784
5785 if (edp_max_bpp_x16 < edp_min_bpp_x16)
5786 edp_min_bpp_x16 = edp_max_bpp_x16;
5787
5788 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5789 dc->debug.dsc_min_slice_height_override,
5790 edp_min_bpp_x16, edp_max_bpp_x16,
5791 dsc_caps,
5792 &stream->timing,
5793 &bw_range)) {
5794
5795 if (bw_range.max_kbps < link_bw_in_kbps) {
5796 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5797 dsc_caps,
de534c1c 5798 &dsc_options,
2665f63a
ML		 5799 0,
5800 &stream->timing,
5801 &dsc_cfg)) {
5802 stream->timing.dsc_cfg = dsc_cfg;
5803 stream->timing.flags.DSC = 1;
5804 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5805 }
5806 return;
5807 }
5808 }
5809
5810 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5811 dsc_caps,
de534c1c 5812 &dsc_options,
2665f63a
ML		 5813 link_bw_in_kbps,
5814 &stream->timing,
5815 &dsc_cfg)) {
5816 stream->timing.dsc_cfg = dsc_cfg;
5817 stream->timing.flags.DSC = 1;
5818 }
5819}
5820
5d945cbc 5821
998b7ad2 5822static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5d945cbc
RS		 5823 struct dc_sink *sink, struct dc_stream_state *stream,
5824 struct dsc_dec_dpcd_caps *dsc_caps)
998b7ad2
FZ		 5825{
5826 struct drm_connector *drm_connector = &aconnector->base;
ae67558b 5827 u32 link_bandwidth_kbps;
2665f63a 5828 struct dc *dc = sink->ctx->dc;
ae67558b
SS		 5829 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5830 u32 dsc_max_supported_bw_in_kbps;
5831 u32 max_dsc_target_bpp_limit_override =
6e5abe94 5832 drm_connector->display_info.max_dsc_bpp;
de534c1c
MH		 5833 struct dc_dsc_config_options dsc_options = {0};
5834
5835 dc_dsc_get_default_config_option(dc, &dsc_options);
5836 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
998b7ad2
FZ		 5837
5838 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5839 dc_link_get_link_cap(aconnector->dc_link));
de7cc1b4 5840
998b7ad2
FZ		 5841 /* Set DSC policy according to dsc_clock_en */
5842 dc_dsc_policy_set_enable_dsc_when_not_needed(
5843 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5844
c17a34e0
IC		 5845 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5846 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
2665f63a
ML		 5847 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5848
5849 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5850
5851 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
50b1f44e
FZ		 5852 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5853 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
998b7ad2 5854 dsc_caps,
de534c1c 5855 &dsc_options,
998b7ad2
FZ		 5856 link_bandwidth_kbps,
5857 &stream->timing,
5858 &stream->timing.dsc_cfg)) {
50b1f44e 5859 stream->timing.flags.DSC = 1;
5d945cbc 5860 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
50b1f44e
FZ		 5861 }
5862 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5863 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5864 max_supported_bw_in_kbps = link_bandwidth_kbps;
5865 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5866
5867 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5868 max_supported_bw_in_kbps > 0 &&
5869 dsc_max_supported_bw_in_kbps > 0)
5870 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5871 dsc_caps,
de534c1c 5872 &dsc_options,
50b1f44e
FZ		 5873 dsc_max_supported_bw_in_kbps,
5874 &stream->timing,
5875 &stream->timing.dsc_cfg)) {
5876 stream->timing.flags.DSC = 1;
5877 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5878 __func__, drm_connector->name);
5879 }
998b7ad2
FZ		 5880 }
5881 }
5882
5883 /* Overwrite the stream flag if DSC is enabled through debugfs */
5884 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5885 stream->timing.flags.DSC = 1;
5886
5d945cbc
RS		 5887 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5888 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
a85ba005 5889
5d945cbc
RS		 5890 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5891 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
a85ba005 5892
5d945cbc
RS		 5893 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5894 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
a85ba005
NC		 5895}
5896
f11d9373 5897static struct dc_stream_state *
3ee6b26b
AD		 5898create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5899 const struct drm_display_mode *drm_mode,
b333730d 5900 const struct dm_connector_state *dm_state,
cbd14ae7
SW		 5901 const struct dc_stream_state *old_stream,
5902 int requested_bpc)
e7b07cee
HW		 5903{
5904 struct drm_display_mode *preferred_mode = NULL;
391ef035 5905 struct drm_connector *drm_connector;
42ba01fc
NK		 5906 const struct drm_connector_state *con_state =
5907 dm_state ? &dm_state->base : NULL;
0971c40e 5908 struct dc_stream_state *stream = NULL;
0a204ce0 5909 struct drm_display_mode mode;
a85ba005
NC		 5910 struct drm_display_mode saved_mode;
5911 struct drm_display_mode *freesync_mode = NULL;
e7b07cee 5912 bool native_mode_found = false;
b0781603
NK		 5913 bool recalculate_timing = false;
5914 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
b333730d 5915 int mode_refresh;
58124bf8 5916 int preferred_refresh = 0;
b1a98cf8 5917 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
df2f1015 5918 struct dsc_dec_dpcd_caps dsc_caps;
5d945cbc 5919
aed15309 5920 struct dc_sink *sink = NULL;
a85ba005 5921
0a204ce0 5922 drm_mode_init(&mode, drm_mode);
a85ba005
NC		 5923 memset(&saved_mode, 0, sizeof(saved_mode));
5924
b830ebc9 5925 if (aconnector == NULL) {
e7b07cee 5926 DRM_ERROR("aconnector is NULL!\n");
64245fa7 5927 return stream;
e7b07cee
HW		 5928 }
5929
e7b07cee 5930 drm_connector = &aconnector->base;
2e0ac3d6 5931
f4ac176e 5932 if (!aconnector->dc_sink) {
e3fa5c4c
JFZ		 5933 sink = create_fake_sink(aconnector);
5934 if (!sink)
5935 return stream;
aed15309
ML		 5936 } else {
5937 sink = aconnector->dc_sink;
dcd5fb82 5938 dc_sink_retain(sink);
f4ac176e 5939 }
2e0ac3d6 5940
aed15309 5941 stream = dc_create_stream_for_sink(sink);
4562236b 5942
b830ebc9 5943 if (stream == NULL) {
e7b07cee 5944 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 5945 goto finish;
e7b07cee
HW		 5946 }
5947
ceb3dbb4
JL		 5948 stream->dm_stream_context = aconnector;
5949
4a36fcba
WL		 5950 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5951 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5952
e7b07cee
HW		 5953 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5954 /* Search for preferred mode */
5955 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5956 native_mode_found = true;
5957 break;
5958 }
5959 }
5960 if (!native_mode_found)
5961 preferred_mode = list_first_entry_or_null(
5962 &aconnector->base.modes,
5963 struct drm_display_mode,
5964 head);
5965
b333730d
BL		 5966 mode_refresh = drm_mode_vrefresh(&mode);
5967
b830ebc9 5968 if (preferred_mode == NULL) {
1f6010a9
DF		 5969 /*
5970 * This may not be an error, the use case is when we have no
e7b07cee
HW		 5971 * usermode calls to reset and set mode upon hotplug. In this
5972 * case, we call set mode ourselves to restore the previous mode
5973 * and the modelist may not be filled in in time.
5974 */
f1ad2f5e 5975 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee 5976 } else {
4243c84a
MD		 5977 recalculate_timing = amdgpu_freesync_vid_mode &&
5978 is_freesync_video_mode(&mode, aconnector);
a85ba005
NC		 5979 if (recalculate_timing) {
5980 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
426c89aa
VS		 5981 drm_mode_copy(&saved_mode, &mode);
5982 drm_mode_copy(&mode, freesync_mode);
a85ba005
NC		 5983 } else {
5984 decide_crtc_timing_for_drm_display_mode(
5d945cbc 5985 &mode, preferred_mode, scale);
a85ba005 5986
b0781603
NK		 5987 preferred_refresh = drm_mode_vrefresh(preferred_mode);
5988 }
e7b07cee
HW		 5989 }
5990
a85ba005
NC		 5991 if (recalculate_timing)
5992 drm_mode_set_crtcinfo(&saved_mode, 0);
fe8858bb 5993 else if (!dm_state)
f783577c
JFZ		 5994 drm_mode_set_crtcinfo(&mode, 0);
5995
5d945cbc 5996 /*
b333730d
BL		 5997 * If scaling is enabled and refresh rate didn't change
5998 * we copy the vic and polarities of the old timings
5999 */
b0781603 6000 if (!scale || mode_refresh != preferred_refresh)
a85ba005
NC		 6001 fill_stream_properties_from_drm_display_mode(
6002 stream, &mode, &aconnector->base, con_state, NULL,
6003 requested_bpc);
b333730d 6004 else
a85ba005
NC		 6005 fill_stream_properties_from_drm_display_mode(
6006 stream, &mode, &aconnector->base, con_state, old_stream,
6007 requested_bpc);
b333730d 6008
028c4ccf
QZ		 6009 if (aconnector->timing_changed) {
6010 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6011 __func__,
6012 stream->timing.display_color_depth,
6013 aconnector->timing_requested->display_color_depth);
6014 stream->timing = *aconnector->timing_requested;
6015 }
6016
998b7ad2
FZ		 6017 /* SST DSC determination policy */
6018 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6019 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6020 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
39a4eb85 6021
e7b07cee
HW		 6022 update_stream_scaling_settings(&mode, dm_state, stream);
6023
6024 fill_audio_info(
6025 &stream->audio_info,
6026 drm_connector,
aed15309 6027 sink);
e7b07cee 6028
ceb3dbb4 6029 update_stream_signal(stream, sink);
9182b4cb 6030
d832fc3b 6031 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
75f77aaf
WL		 6032 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6033
8a488f5d
RL		 6034 if (stream->link->psr_settings.psr_feature_enabled) {
6035 //
6036 // should decide stream support vsc sdp colorimetry capability
6037 // before building vsc info packet
6038 //
6039 stream->use_vsc_sdp_for_colorimetry = false;
6040 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6041 stream->use_vsc_sdp_for_colorimetry =
6042 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6043 } else {
6044 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6045 stream->use_vsc_sdp_for_colorimetry = true;
8c322309 6046 }
b1a98cf8
MH		 6047 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6048 tf = TRANSFER_FUNC_GAMMA_22;
6049 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
1a365683
RL		 6050 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6051
8c322309 6052 }
aed15309 6053finish:
dcd5fb82 6054 dc_sink_release(sink);
9e3efe3e 6055
e7b07cee
HW		 6056 return stream;
6057}
6058
e7b07cee
HW		 6059static enum drm_connector_status
6060amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6061{
6062 bool connected;
c84dec2f 6063 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 6064
1f6010a9
DF		 6065 /*
6066 * Notes:
e7b07cee
HW		 6067 * 1. This interface is NOT called in context of HPD irq.
6068 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 6069 * makes it a bad place for *any* MST-related activity.
6070 */
e7b07cee 6071
8580d60b
HW		 6072 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6073 !aconnector->fake_enable)
e7b07cee
HW		 6074 connected = (aconnector->dc_sink != NULL);
6075 else
5d945cbc
RS		 6076 connected = (aconnector->base.force == DRM_FORCE_ON ||
6077 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
e7b07cee 6078
0f877894
OV		 6079 update_subconnector_property(aconnector);
6080
e7b07cee
HW		 6081 return (connected ? connector_status_connected :
6082 connector_status_disconnected);
6083}
6084
3ee6b26b
AD		 6085int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6086 struct drm_connector_state *connector_state,
6087 struct drm_property *property,
6088 uint64_t val)
e7b07cee
HW		 6089{
6090 struct drm_device *dev = connector->dev;
1348969a 6091 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 6092 struct dm_connector_state *dm_old_state =
6093 to_dm_connector_state(connector->state);
6094 struct dm_connector_state *dm_new_state =
6095 to_dm_connector_state(connector_state);
6096
6097 int ret = -EINVAL;
6098
6099 if (property == dev->mode_config.scaling_mode_property) {
6100 enum amdgpu_rmx_type rmx_type;
6101
6102 switch (val) {
6103 case DRM_MODE_SCALE_CENTER:
6104 rmx_type = RMX_CENTER;
6105 break;
6106 case DRM_MODE_SCALE_ASPECT:
6107 rmx_type = RMX_ASPECT;
6108 break;
6109 case DRM_MODE_SCALE_FULLSCREEN:
6110 rmx_type = RMX_FULL;
6111 break;
6112 case DRM_MODE_SCALE_NONE:
6113 default:
6114 rmx_type = RMX_OFF;
6115 break;
6116 }
6117
6118 if (dm_old_state->scaling == rmx_type)
6119 return 0;
6120
6121 dm_new_state->scaling = rmx_type;
6122 ret = 0;
6123 } else if (property == adev->mode_info.underscan_hborder_property) {
6124 dm_new_state->underscan_hborder = val;
6125 ret = 0;
6126 } else if (property == adev->mode_info.underscan_vborder_property) {
6127 dm_new_state->underscan_vborder = val;
6128 ret = 0;
6129 } else if (property == adev->mode_info.underscan_property) {
6130 dm_new_state->underscan_enable = val;
6131 ret = 0;
c1ee92f9
DF		 6132 } else if (property == adev->mode_info.abm_level_property) {
6133 dm_new_state->abm_level = val;
6134 ret = 0;
e7b07cee
HW		 6135 }
6136
6137 return ret;
6138}
6139
3ee6b26b
AD		 6140int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6141 const struct drm_connector_state *state,
6142 struct drm_property *property,
6143 uint64_t *val)
e7b07cee
HW		 6144{
6145 struct drm_device *dev = connector->dev;
1348969a 6146 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 6147 struct dm_connector_state *dm_state =
6148 to_dm_connector_state(state);
6149 int ret = -EINVAL;
6150
6151 if (property == dev->mode_config.scaling_mode_property) {
6152 switch (dm_state->scaling) {
6153 case RMX_CENTER:
6154 *val = DRM_MODE_SCALE_CENTER;
6155 break;
6156 case RMX_ASPECT:
6157 *val = DRM_MODE_SCALE_ASPECT;
6158 break;
6159 case RMX_FULL:
6160 *val = DRM_MODE_SCALE_FULLSCREEN;
6161 break;
6162 case RMX_OFF:
6163 default:
6164 *val = DRM_MODE_SCALE_NONE;
6165 break;
6166 }
6167 ret = 0;
6168 } else if (property == adev->mode_info.underscan_hborder_property) {
6169 *val = dm_state->underscan_hborder;
6170 ret = 0;
6171 } else if (property == adev->mode_info.underscan_vborder_property) {
6172 *val = dm_state->underscan_vborder;
6173 ret = 0;
6174 } else if (property == adev->mode_info.underscan_property) {
6175 *val = dm_state->underscan_enable;
6176 ret = 0;
c1ee92f9
DF		 6177 } else if (property == adev->mode_info.abm_level_property) {
6178 *val = dm_state->abm_level;
6179 ret = 0;
e7b07cee 6180 }
c1ee92f9 6181
e7b07cee
HW		 6182 return ret;
6183}
6184
526c654a
ED		 6185static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6186{
6187 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6188
6189 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6190}
6191
7578ecda 6192static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 6193{
c84dec2f 6194 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 6195 const struct dc_link *link = aconnector->dc_link;
1348969a 6196 struct amdgpu_device *adev = drm_to_adev(connector->dev);
e7b07cee 6197 struct amdgpu_display_manager *dm = &adev->dm;
7fd13bae 6198 int i;
ada8ce15 6199
5dff80bd 6200 /*
5d945cbc 6201 * Call only if mst_mgr was initialized before since it's not done
5dff80bd
AG		 6202 * for all connector types.
6203 */
6204 if (aconnector->mst_mgr.dev)
6205 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6206
7fd13bae
AD		 6207 for (i = 0; i < dm->num_of_edps; i++) {
6208 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
6209 backlight_device_unregister(dm->backlight_dev[i]);
6210 dm->backlight_dev[i] = NULL;
6211 }
e7b07cee 6212 }
dcd5fb82
MF		 6213
6214 if (aconnector->dc_em_sink)
6215 dc_sink_release(aconnector->dc_em_sink);
6216 aconnector->dc_em_sink = NULL;
6217 if (aconnector->dc_sink)
6218 dc_sink_release(aconnector->dc_sink);
6219 aconnector->dc_sink = NULL;
6220
e86e8947 6221 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 6222 drm_connector_unregister(connector);
6223 drm_connector_cleanup(connector);
526c654a
ED		 6224 if (aconnector->i2c) {
6225 i2c_del_adapter(&aconnector->i2c->base);
6226 kfree(aconnector->i2c);
6227 }
7daec99f 6228 kfree(aconnector->dm_dp_aux.aux.name);
526c654a 6229
e7b07cee
HW		 6230 kfree(connector);
6231}
6232
6233void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6234{
6235 struct dm_connector_state *state =
6236 to_dm_connector_state(connector->state);
6237
df099b9b
LSL		 6238 if (connector->state)
6239 __drm_atomic_helper_connector_destroy_state(connector->state);
6240
e7b07cee
HW		 6241 kfree(state);
6242
6243 state = kzalloc(sizeof(*state), GFP_KERNEL);
6244
6245 if (state) {
6246 state->scaling = RMX_OFF;
6247 state->underscan_enable = false;
6248 state->underscan_hborder = 0;
6249 state->underscan_vborder = 0;
01933ba4 6250 state->base.max_requested_bpc = 8;
3261e013
ML		 6251 state->vcpi_slots = 0;
6252 state->pbn = 0;
5d945cbc 6253
c3e50f89
NK		 6254 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6255 state->abm_level = amdgpu_dm_abm_level;
6256
df099b9b 6257 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 6258 }
6259}
6260
3ee6b26b
AD		 6261struct drm_connector_state *
6262amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 6263{
6264 struct dm_connector_state *state =
6265 to_dm_connector_state(connector->state);
6266
6267 struct dm_connector_state *new_state =
6268 kmemdup(state, sizeof(*state), GFP_KERNEL);
6269
98e6436d
AK		 6270 if (!new_state)
6271 return NULL;
e7b07cee 6272
98e6436d
AK		 6273 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6274
6275 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 6276 new_state->abm_level = state->abm_level;
922454c2
NK		 6277 new_state->scaling = state->scaling;
6278 new_state->underscan_enable = state->underscan_enable;
6279 new_state->underscan_hborder = state->underscan_hborder;
6280 new_state->underscan_vborder = state->underscan_vborder;
3261e013
ML		 6281 new_state->vcpi_slots = state->vcpi_slots;
6282 new_state->pbn = state->pbn;
98e6436d 6283 return &new_state->base;
e7b07cee
HW		 6284}
6285
14f04fa4
AD		 6286static int
6287amdgpu_dm_connector_late_register(struct drm_connector *connector)
6288{
6289 struct amdgpu_dm_connector *amdgpu_dm_connector =
6290 to_amdgpu_dm_connector(connector);
00a8037e 6291 int r;
14f04fa4 6292
00a8037e
AD		 6293 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6294 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6295 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6296 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6297 if (r)
6298 return r;
6299 }
6300
6301#if defined(CONFIG_DEBUG_FS)
14f04fa4
AD		 6302 connector_debugfs_init(amdgpu_dm_connector);
6303#endif
6304
6305 return 0;
6306}
6307
e7b07cee
HW		 6308static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6309 .reset = amdgpu_dm_connector_funcs_reset,
6310 .detect = amdgpu_dm_connector_detect,
6311 .fill_modes = drm_helper_probe_single_connector_modes,
6312 .destroy = amdgpu_dm_connector_destroy,
6313 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6314 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6315 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
526c654a 6316 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
14f04fa4 6317 .late_register = amdgpu_dm_connector_late_register,
526c654a 6318 .early_unregister = amdgpu_dm_connector_unregister
e7b07cee
HW		 6319};
6320
e7b07cee
HW		 6321static int get_modes(struct drm_connector *connector)
6322{
6323 return amdgpu_dm_connector_get_modes(connector);
6324}
6325
c84dec2f 6326static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 6327{
6328 struct dc_sink_init_data init_params = {
6329 .link = aconnector->dc_link,
6330 .sink_signal = SIGNAL_TYPE_VIRTUAL
6331 };
70e8ffc5 6332 struct edid *edid;
e7b07cee 6333
a89ff457 6334 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 6335 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6336 aconnector->base.name);
6337
6338 aconnector->base.force = DRM_FORCE_OFF;
e7b07cee
HW		 6339 return;
6340 }
6341
70e8ffc5
HW		 6342 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6343
e7b07cee
HW		 6344 aconnector->edid = edid;
6345
6346 aconnector->dc_em_sink = dc_link_add_remote_sink(
6347 aconnector->dc_link,
6348 (uint8_t *)edid,
6349 (edid->extensions + 1) * EDID_LENGTH,
6350 &init_params);
6351
dcd5fb82 6352 if (aconnector->base.force == DRM_FORCE_ON) {
e7b07cee
HW		 6353 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6354 aconnector->dc_link->local_sink :
6355 aconnector->dc_em_sink;
dcd5fb82
MF		 6356 dc_sink_retain(aconnector->dc_sink);
6357 }
e7b07cee
HW		 6358}
6359
c84dec2f 6360static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 6361{
6362 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6363
1f6010a9
DF		 6364 /*
6365 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 6366 * Those settings have to be != 0 to get initial modeset
6367 */
6368 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6369 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6370 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6371 }
6372
e7b07cee
HW		 6373 create_eml_sink(aconnector);
6374}
6375
5468c36d
FZ		 6376static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6377 struct dc_stream_state *stream)
6378{
6379 enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6380 struct dc_plane_state *dc_plane_state = NULL;
6381 struct dc_state *dc_state = NULL;
6382
6383 if (!stream)
6384 goto cleanup;
6385
6386 dc_plane_state = dc_create_plane_state(dc);
6387 if (!dc_plane_state)
6388 goto cleanup;
6389
6390 dc_state = dc_create_state(dc);
6391 if (!dc_state)
6392 goto cleanup;
6393
6394 /* populate stream to plane */
6395 dc_plane_state->src_rect.height = stream->src.height;
6396 dc_plane_state->src_rect.width = stream->src.width;
6397 dc_plane_state->dst_rect.height = stream->src.height;
6398 dc_plane_state->dst_rect.width = stream->src.width;
6399 dc_plane_state->clip_rect.height = stream->src.height;
6400 dc_plane_state->clip_rect.width = stream->src.width;
6401 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6402 dc_plane_state->plane_size.surface_size.height = stream->src.height;
6403 dc_plane_state->plane_size.surface_size.width = stream->src.width;
6404 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
6405 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
5468c36d
FZ		 6406 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6407 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6408 dc_plane_state->rotation = ROTATION_ANGLE_0;
6409 dc_plane_state->is_tiling_rotated = false;
6410 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6411
6412 dc_result = dc_validate_stream(dc, stream);
6413 if (dc_result == DC_OK)
6414 dc_result = dc_validate_plane(dc, dc_plane_state);
6415
6416 if (dc_result == DC_OK)
6417 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6418
6419 if (dc_result == DC_OK && !dc_add_plane_to_context(
6420 dc,
6421 stream,
6422 dc_plane_state,
6423 dc_state))
6424 dc_result = DC_FAIL_ATTACH_SURFACES;
6425
6426 if (dc_result == DC_OK)
6427 dc_result = dc_validate_global_state(dc, dc_state, true);
6428
6429cleanup:
6430 if (dc_state)
6431 dc_release_state(dc_state);
6432
6433 if (dc_plane_state)
6434 dc_plane_state_release(dc_plane_state);
6435
6436 return dc_result;
6437}
6438
17ce8a69 6439struct dc_stream_state *
cbd14ae7
SW		 6440create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6441 const struct drm_display_mode *drm_mode,
6442 const struct dm_connector_state *dm_state,
6443 const struct dc_stream_state *old_stream)
6444{
6445 struct drm_connector *connector = &aconnector->base;
1348969a 6446 struct amdgpu_device *adev = drm_to_adev(connector->dev);
cbd14ae7 6447 struct dc_stream_state *stream;
4b7da34b
SW		 6448 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6449 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
cbd14ae7
SW		 6450 enum dc_status dc_result = DC_OK;
6451
6452 do {
6453 stream = create_stream_for_sink(aconnector, drm_mode,
6454 dm_state, old_stream,
6455 requested_bpc);
6456 if (stream == NULL) {
6457 DRM_ERROR("Failed to create stream for sink!\n");
6458 break;
6459 }
6460
e9a7d236
RS		 6461 dc_result = dc_validate_stream(adev->dm.dc, stream);
6462 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
f04d275d 6463 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6464
5468c36d
FZ		 6465 if (dc_result == DC_OK)
6466 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6467
cbd14ae7 6468 if (dc_result != DC_OK) {
74a16675 6469 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
cbd14ae7
SW		 6470 drm_mode->hdisplay,
6471 drm_mode->vdisplay,
6472 drm_mode->clock,
74a16675
RS		 6473 dc_result,
6474 dc_status_to_str(dc_result));
cbd14ae7
SW		 6475
6476 dc_stream_release(stream);
6477 stream = NULL;
6478 requested_bpc -= 2; /* lower bpc to retry validation */
6479 }
6480
6481 } while (stream == NULL && requested_bpc >= 6);
6482
68eb3ae3
WS		 6483 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6484 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6485
6486 aconnector->force_yuv420_output = true;
6487 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6488 dm_state, old_stream);
6489 aconnector->force_yuv420_output = false;
6490 }
6491
cbd14ae7
SW		 6492 return stream;
6493}
6494
ba9ca088 6495enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 6496 struct drm_display_mode *mode)
e7b07cee
HW		 6497{
6498 int result = MODE_ERROR;
6499 struct dc_sink *dc_sink;
e7b07cee 6500 /* TODO: Unhardcode stream count */
0971c40e 6501 struct dc_stream_state *stream;
c84dec2f 6502 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 6503
6504 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6505 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6506 return result;
6507
1f6010a9
DF		 6508 /*
6509 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 6510 * EDID mgmt
6511 */
6512 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6513 !aconnector->dc_em_sink)
6514 handle_edid_mgmt(aconnector);
6515
c84dec2f 6516 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 6517
ad975f44
VL		 6518 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6519 aconnector->base.force != DRM_FORCE_ON) {
e7b07cee
HW		 6520 DRM_ERROR("dc_sink is NULL!\n");
6521 goto fail;
6522 }
6523
cbd14ae7
SW		 6524 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6525 if (stream) {
6526 dc_stream_release(stream);
e7b07cee 6527 result = MODE_OK;
cbd14ae7 6528 }
e7b07cee
HW		 6529
6530fail:
6531 /* TODO: error handling*/
6532 return result;
6533}
6534
88694af9
NK		 6535static int fill_hdr_info_packet(const struct drm_connector_state *state,
6536 struct dc_info_packet *out)
6537{
6538 struct hdmi_drm_infoframe frame;
6539 unsigned char buf[30]; /* 26 + 4 */
6540 ssize_t len;
6541 int ret, i;
6542
6543 memset(out, 0, sizeof(*out));
6544
6545 if (!state->hdr_output_metadata)
6546 return 0;
6547
6548 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6549 if (ret)
6550 return ret;
6551
6552 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6553 if (len < 0)
6554 return (int)len;
6555
6556 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6557 if (len != 30)
6558 return -EINVAL;
6559
6560 /* Prepare the infopacket for DC. */
6561 switch (state->connector->connector_type) {
6562 case DRM_MODE_CONNECTOR_HDMIA:
6563 out->hb0 = 0x87; /* type */
6564 out->hb1 = 0x01; /* version */
6565 out->hb2 = 0x1A; /* length */
6566 out->sb[0] = buf[3]; /* checksum */
6567 i = 1;
6568 break;
6569
6570 case DRM_MODE_CONNECTOR_DisplayPort:
6571 case DRM_MODE_CONNECTOR_eDP:
6572 out->hb0 = 0x00; /* sdp id, zero */
6573 out->hb1 = 0x87; /* type */
6574 out->hb2 = 0x1D; /* payload len - 1 */
6575 out->hb3 = (0x13 << 2); /* sdp version */
6576 out->sb[0] = 0x01; /* version */
6577 out->sb[1] = 0x1A; /* length */
6578 i = 2;
6579 break;
6580
6581 default:
6582 return -EINVAL;
6583 }
6584
6585 memcpy(&out->sb[i], &buf[4], 26);
6586 out->valid = true;
6587
6588 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6589 sizeof(out->sb), false);
6590
6591 return 0;
6592}
6593
88694af9
NK		 6594static int
6595amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
51e857af 6596 struct drm_atomic_state *state)
88694af9 6597{
51e857af
SP		 6598 struct drm_connector_state *new_con_state =
6599 drm_atomic_get_new_connector_state(state, conn);
88694af9
NK		 6600 struct drm_connector_state *old_con_state =
6601 drm_atomic_get_old_connector_state(state, conn);
6602 struct drm_crtc *crtc = new_con_state->crtc;
6603 struct drm_crtc_state *new_crtc_state;
a76eb429 6604 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
88694af9
NK		 6605 int ret;
6606
e8a98235
RS		 6607 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6608
a76eb429
LP		 6609 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6610 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6611 if (ret < 0)
6612 return ret;
6613 }
6614
88694af9
NK		 6615 if (!crtc)
6616 return 0;
6617
72921cdf 6618 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
88694af9
NK		 6619 struct dc_info_packet hdr_infopacket;
6620
6621 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6622 if (ret)
6623 return ret;
6624
6625 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6626 if (IS_ERR(new_crtc_state))
6627 return PTR_ERR(new_crtc_state);
6628
6629 /*
6630 * DC considers the stream backends changed if the
6631 * static metadata changes. Forcing the modeset also
6632 * gives a simple way for userspace to switch from
b232d4ed
NK		 6633 * 8bpc to 10bpc when setting the metadata to enter
6634 * or exit HDR.
6635 *
6636 * Changing the static metadata after it's been
6637 * set is permissible, however. So only force a
6638 * modeset if we're entering or exiting HDR.
88694af9 6639 */
b232d4ed
NK		 6640 new_crtc_state->mode_changed =
6641 !old_con_state->hdr_output_metadata ||
6642 !new_con_state->hdr_output_metadata;
88694af9
NK		 6643 }
6644
6645 return 0;
6646}
6647
e7b07cee
HW		 6648static const struct drm_connector_helper_funcs
6649amdgpu_dm_connector_helper_funcs = {
6650 /*
1f6010a9 6651 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 6652 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 6653 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 6654 * in get_modes call back, not just return the modes count
6655 */
e7b07cee
HW		 6656 .get_modes = get_modes,
6657 .mode_valid = amdgpu_dm_connector_mode_valid,
88694af9 6658 .atomic_check = amdgpu_dm_connector_atomic_check,
e7b07cee
HW		 6659};
6660
e7b07cee
HW		 6661static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6662{
6663
6664}
6665
f04d275d 6666int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
3261e013
ML		 6667{
6668 switch (display_color_depth) {
5d945cbc
RS		 6669 case COLOR_DEPTH_666:
6670 return 6;
6671 case COLOR_DEPTH_888:
6672 return 8;
6673 case COLOR_DEPTH_101010:
6674 return 10;
6675 case COLOR_DEPTH_121212:
6676 return 12;
6677 case COLOR_DEPTH_141414:
6678 return 14;
6679 case COLOR_DEPTH_161616:
6680 return 16;
6681 default:
6682 break;
6683 }
3261e013
ML		 6684 return 0;
6685}
6686
3ee6b26b
AD		 6687static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6688 struct drm_crtc_state *crtc_state,
6689 struct drm_connector_state *conn_state)
e7b07cee 6690{
3261e013
ML		 6691 struct drm_atomic_state *state = crtc_state->state;
6692 struct drm_connector *connector = conn_state->connector;
6693 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6694 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6695 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6696 struct drm_dp_mst_topology_mgr *mst_mgr;
6697 struct drm_dp_mst_port *mst_port;
4d07b0bc 6698 struct drm_dp_mst_topology_state *mst_state;
3261e013
ML		 6699 enum dc_color_depth color_depth;
6700 int clock, bpp = 0;
1bc22f20 6701 bool is_y420 = false;
3261e013 6702
f0127cb1 6703 if (!aconnector->mst_output_port || !aconnector->dc_sink)
3261e013
ML		 6704 return 0;
6705
f0127cb1
WL		 6706 mst_port = aconnector->mst_output_port;
6707 mst_mgr = &aconnector->mst_root->mst_mgr;
3261e013
ML		 6708
6709 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6710 return 0;
6711
4d07b0bc
LP		 6712 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6713 if (IS_ERR(mst_state))
6714 return PTR_ERR(mst_state);
6715
6716 if (!mst_state->pbn_div)
f0127cb1 6717 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
4d07b0bc 6718
3261e013 6719 if (!state->duplicated) {
cbd14ae7 6720 int max_bpc = conn_state->max_requested_bpc;
1bc22f20 6721 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
5d945cbc 6722 aconnector->force_yuv420_output;
cbd14ae7
SW		 6723 color_depth = convert_color_depth_from_display_info(connector,
6724 is_y420,
6725 max_bpc);
3261e013
ML		 6726 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6727 clock = adjusted_mode->clock;
dc48529f 6728 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
3261e013 6729 }
4d07b0bc
LP		 6730
6731 dm_new_connector_state->vcpi_slots =
6732 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6733 dm_new_connector_state->pbn);
3261e013
ML		 6734 if (dm_new_connector_state->vcpi_slots < 0) {
6735 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6736 return dm_new_connector_state->vcpi_slots;
6737 }
e7b07cee
HW		 6738 return 0;
6739}
6740
6741const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6742 .disable = dm_encoder_helper_disable,
6743 .atomic_check = dm_encoder_helper_atomic_check
6744};
6745
29b9ba74 6746static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6513104b
HW		 6747 struct dc_state *dc_state,
6748 struct dsc_mst_fairness_vars *vars)
29b9ba74
ML		 6749{
6750 struct dc_stream_state *stream = NULL;
6751 struct drm_connector *connector;
5760dcb9 6752 struct drm_connector_state *new_con_state;
29b9ba74
ML		 6753 struct amdgpu_dm_connector *aconnector;
6754 struct dm_connector_state *dm_conn_state;
7cce4cd6 6755 int i, j, ret;
a550bb16 6756 int vcpi, pbn_div, pbn, slot_num = 0;
29b9ba74 6757
5760dcb9 6758 for_each_new_connector_in_state(state, connector, new_con_state, i) {
29b9ba74
ML		 6759
6760 aconnector = to_amdgpu_dm_connector(connector);
6761
f0127cb1 6762 if (!aconnector->mst_output_port)
29b9ba74
ML		 6763 continue;
6764
6765 if (!new_con_state || !new_con_state->crtc)
6766 continue;
6767
6768 dm_conn_state = to_dm_connector_state(new_con_state);
6769
6770 for (j = 0; j < dc_state->stream_count; j++) {
6771 stream = dc_state->streams[j];
6772 if (!stream)
6773 continue;
6774
5d945cbc 6775 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
29b9ba74
ML		 6776 break;
6777
6778 stream = NULL;
6779 }
6780
6781 if (!stream)
6782 continue;
6783
29b9ba74 6784 pbn_div = dm_mst_get_pbn_divider(stream->link);
6513104b
HW		 6785 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6786 for (j = 0; j < dc_state->stream_count; j++) {
6787 if (vars[j].aconnector == aconnector) {
6788 pbn = vars[j].pbn;
6789 break;
6790 }
6791 }
6792
a550bb16
HW		 6793 if (j == dc_state->stream_count)
6794 continue;
6795
6796 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6797
6798 if (stream->timing.flags.DSC != 1) {
6799 dm_conn_state->pbn = pbn;
6800 dm_conn_state->vcpi_slots = slot_num;
6801
f0127cb1 6802 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
7cce4cd6
LP		 6803 dm_conn_state->pbn, false);
6804 if (ret < 0)
6805 return ret;
6806
a550bb16
HW		 6807 continue;
6808 }
6809
f0127cb1 6810 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
29b9ba74
ML		 6811 if (vcpi < 0)
6812 return vcpi;
6813
6814 dm_conn_state->pbn = pbn;
6815 dm_conn_state->vcpi_slots = vcpi;
6816 }
6817 return 0;
6818}
6819
e7b07cee
HW		 6820static int to_drm_connector_type(enum signal_type st)
6821{
6822 switch (st) {
6823 case SIGNAL_TYPE_HDMI_TYPE_A:
6824 return DRM_MODE_CONNECTOR_HDMIA;
6825 case SIGNAL_TYPE_EDP:
6826 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 6827 case SIGNAL_TYPE_LVDS:
6828 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 6829 case SIGNAL_TYPE_RGB:
6830 return DRM_MODE_CONNECTOR_VGA;
6831 case SIGNAL_TYPE_DISPLAY_PORT:
6832 case SIGNAL_TYPE_DISPLAY_PORT_MST:
6833 return DRM_MODE_CONNECTOR_DisplayPort;
6834 case SIGNAL_TYPE_DVI_DUAL_LINK:
6835 case SIGNAL_TYPE_DVI_SINGLE_LINK:
6836 return DRM_MODE_CONNECTOR_DVID;
6837 case SIGNAL_TYPE_VIRTUAL:
6838 return DRM_MODE_CONNECTOR_VIRTUAL;
6839
6840 default:
6841 return DRM_MODE_CONNECTOR_Unknown;
6842 }
6843}
6844
2b4c1c05
DV		 6845static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6846{
62afb4ad
JRS		 6847 struct drm_encoder *encoder;
6848
6849 /* There is only one encoder per connector */
6850 drm_connector_for_each_possible_encoder(connector, encoder)
6851 return encoder;
6852
6853 return NULL;
2b4c1c05
DV		 6854}
6855
e7b07cee
HW		 6856static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6857{
e7b07cee
HW		 6858 struct drm_encoder *encoder;
6859 struct amdgpu_encoder *amdgpu_encoder;
6860
2b4c1c05 6861 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 6862
6863 if (encoder == NULL)
6864 return;
6865
6866 amdgpu_encoder = to_amdgpu_encoder(encoder);
6867
6868 amdgpu_encoder->native_mode.clock = 0;
6869
6870 if (!list_empty(&connector->probed_modes)) {
6871 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 6872
e7b07cee 6873 list_for_each_entry(preferred_mode,
b830ebc9
HW		 6874 &connector->probed_modes,
6875 head) {
6876 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6877 amdgpu_encoder->native_mode = *preferred_mode;
6878
e7b07cee
HW		 6879 break;
6880 }
6881
6882 }
6883}
6884
3ee6b26b
AD		 6885static struct drm_display_mode *
6886amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6887 char *name,
6888 int hdisplay, int vdisplay)
e7b07cee
HW		 6889{
6890 struct drm_device *dev = encoder->dev;
6891 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6892 struct drm_display_mode *mode = NULL;
6893 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6894
6895 mode = drm_mode_duplicate(dev, native_mode);
6896
b830ebc9 6897 if (mode == NULL)
e7b07cee
HW		 6898 return NULL;
6899
6900 mode->hdisplay = hdisplay;
6901 mode->vdisplay = vdisplay;
6902 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 6903 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 6904
6905 return mode;
6906
6907}
6908
6909static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 6910 struct drm_connector *connector)
e7b07cee
HW		 6911{
6912 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6913 struct drm_display_mode *mode = NULL;
6914 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 6915 struct amdgpu_dm_connector *amdgpu_dm_connector =
6916 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 6917 int i;
6918 int n;
6919 struct mode_size {
6920 char name[DRM_DISPLAY_MODE_LEN];
6921 int w;
6922 int h;
b830ebc9 6923 } common_modes[] = {
e7b07cee
HW		 6924 { "640x480", 640, 480},
6925 { "800x600", 800, 600},
6926 { "1024x768", 1024, 768},
6927 { "1280x720", 1280, 720},
6928 { "1280x800", 1280, 800},
6929 {"1280x1024", 1280, 1024},
6930 { "1440x900", 1440, 900},
6931 {"1680x1050", 1680, 1050},
6932 {"1600x1200", 1600, 1200},
6933 {"1920x1080", 1920, 1080},
6934 {"1920x1200", 1920, 1200}
6935 };
6936
b830ebc9 6937 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 6938
6939 for (i = 0; i < n; i++) {
6940 struct drm_display_mode *curmode = NULL;
6941 bool mode_existed = false;
6942
6943 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 6944 common_modes[i].h > native_mode->vdisplay ||
6945 (common_modes[i].w == native_mode->hdisplay &&
6946 common_modes[i].h == native_mode->vdisplay))
6947 continue;
e7b07cee
HW		 6948
6949 list_for_each_entry(curmode, &connector->probed_modes, head) {
6950 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 6951 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 6952 mode_existed = true;
6953 break;
6954 }
6955 }
6956
6957 if (mode_existed)
6958 continue;
6959
6960 mode = amdgpu_dm_create_common_mode(encoder,
6961 common_modes[i].name, common_modes[i].w,
6962 common_modes[i].h);
588a7017
ZQ		 6963 if (!mode)
6964 continue;
6965
e7b07cee 6966 drm_mode_probed_add(connector, mode);
c84dec2f 6967 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 6968 }
6969}
6970
d77de788
SS		 6971static void amdgpu_set_panel_orientation(struct drm_connector *connector)
6972{
6973 struct drm_encoder *encoder;
6974 struct amdgpu_encoder *amdgpu_encoder;
6975 const struct drm_display_mode *native_mode;
6976
6977 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
6978 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
6979 return;
6980
acc96ae0
MW		 6981 mutex_lock(&connector->dev->mode_config.mutex);
6982 amdgpu_dm_connector_get_modes(connector);
6983 mutex_unlock(&connector->dev->mode_config.mutex);
6984
d77de788
SS		 6985 encoder = amdgpu_dm_connector_to_encoder(connector);
6986 if (!encoder)
6987 return;
6988
6989 amdgpu_encoder = to_amdgpu_encoder(encoder);
6990
6991 native_mode = &amdgpu_encoder->native_mode;
6992 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
6993 return;
6994
6995 drm_connector_set_panel_orientation_with_quirk(connector,
6996 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
6997 native_mode->hdisplay,
6998 native_mode->vdisplay);
6999}
7000
3ee6b26b
AD		 7001static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7002 struct edid *edid)
e7b07cee 7003{
c84dec2f
HW		 7004 struct amdgpu_dm_connector *amdgpu_dm_connector =
7005 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 7006
7007 if (edid) {
7008 /* empty probed_modes */
7009 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 7010 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 7011 drm_add_edid_modes(connector, edid);
7012
f1e5e913
YMM		 7013 /* sorting the probed modes before calling function
7014 * amdgpu_dm_get_native_mode() since EDID can have
7015 * more than one preferred mode. The modes that are
7016 * later in the probed mode list could be of higher
7017 * and preferred resolution. For example, 3840x2160
7018 * resolution in base EDID preferred timing and 4096x2160
7019 * preferred resolution in DID extension block later.
7020 */
7021 drm_mode_sort(&connector->probed_modes);
e7b07cee 7022 amdgpu_dm_get_native_mode(connector);
f9b4f20c
SW		 7023
7024 /* Freesync capabilities are reset by calling
7025 * drm_add_edid_modes() and need to be
7026 * restored here.
7027 */
7028 amdgpu_dm_update_freesync_caps(connector, edid);
a8d8d3dc 7029 } else {
c84dec2f 7030 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 7031 }
e7b07cee
HW		 7032}
7033
a85ba005
NC		 7034static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7035 struct drm_display_mode *mode)
7036{
7037 struct drm_display_mode *m;
7038
7039 list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7040 if (drm_mode_equal(m, mode))
7041 return true;
7042 }
7043
7044 return false;
7045}
7046
7047static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7048{
7049 const struct drm_display_mode *m;
7050 struct drm_display_mode *new_mode;
7051 uint i;
ae67558b 7052 u32 new_modes_count = 0;
a85ba005
NC		 7053
7054 /* Standard FPS values
7055 *
12cdff6b
SC		 7056 * 23.976 - TV/NTSC
7057 * 24 - Cinema
7058 * 25 - TV/PAL
7059 * 29.97 - TV/NTSC
7060 * 30 - TV/NTSC
7061 * 48 - Cinema HFR
7062 * 50 - TV/PAL
7063 * 60 - Commonly used
7064 * 48,72,96,120 - Multiples of 24
a85ba005 7065 */
ae67558b 7066 static const u32 common_rates[] = {
9ce5ed6e 7067 23976, 24000, 25000, 29970, 30000,
12cdff6b 7068 48000, 50000, 60000, 72000, 96000, 120000
9ce5ed6e 7069 };
a85ba005
NC		 7070
7071 /*
7072 * Find mode with highest refresh rate with the same resolution
7073 * as the preferred mode. Some monitors report a preferred mode
7074 * with lower resolution than the highest refresh rate supported.
7075 */
7076
7077 m = get_highest_refresh_rate_mode(aconnector, true);
7078 if (!m)
7079 return 0;
7080
7081 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
ae67558b
SS		 7082 u64 target_vtotal, target_vtotal_diff;
7083 u64 num, den;
a85ba005
NC		 7084
7085 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7086 continue;
7087
7088 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7089 common_rates[i] > aconnector->max_vfreq * 1000)
7090 continue;
7091
7092 num = (unsigned long long)m->clock * 1000 * 1000;
7093 den = common_rates[i] * (unsigned long long)m->htotal;
7094 target_vtotal = div_u64(num, den);
7095 target_vtotal_diff = target_vtotal - m->vtotal;
7096
7097 /* Check for illegal modes */
7098 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7099 m->vsync_end + target_vtotal_diff < m->vsync_start ||
7100 m->vtotal + target_vtotal_diff < m->vsync_end)
7101 continue;
7102
7103 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7104 if (!new_mode)
7105 goto out;
7106
7107 new_mode->vtotal += (u16)target_vtotal_diff;
7108 new_mode->vsync_start += (u16)target_vtotal_diff;
7109 new_mode->vsync_end += (u16)target_vtotal_diff;
7110 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7111 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7112
7113 if (!is_duplicate_mode(aconnector, new_mode)) {
7114 drm_mode_probed_add(&aconnector->base, new_mode);
7115 new_modes_count += 1;
7116 } else
7117 drm_mode_destroy(aconnector->base.dev, new_mode);
7118 }
7119 out:
7120 return new_modes_count;
7121}
7122
7123static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7124 struct edid *edid)
7125{
7126 struct amdgpu_dm_connector *amdgpu_dm_connector =
7127 to_amdgpu_dm_connector(connector);
7128
4243c84a 7129 if (!(amdgpu_freesync_vid_mode && edid))
a85ba005 7130 return;
fe8858bb 7131
a85ba005
NC		 7132 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7133 amdgpu_dm_connector->num_modes +=
7134 add_fs_modes(amdgpu_dm_connector);
7135}
7136
7578ecda 7137static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 7138{
c84dec2f
HW		 7139 struct amdgpu_dm_connector *amdgpu_dm_connector =
7140 to_amdgpu_dm_connector(connector);
e7b07cee 7141 struct drm_encoder *encoder;
c84dec2f 7142 struct edid *edid = amdgpu_dm_connector->edid;
c32699ca
JD		 7143 struct dc_link_settings *verified_link_cap =
7144 &amdgpu_dm_connector->dc_link->verified_link_cap;
e7b07cee 7145
2b4c1c05 7146 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 7147
5c0e6840 7148 if (!drm_edid_is_valid(edid)) {
1b369d3c
ML		 7149 amdgpu_dm_connector->num_modes =
7150 drm_add_modes_noedid(connector, 640, 480);
c32699ca
JD		 7151 if (link_dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7152 amdgpu_dm_connector->num_modes +=
7153 drm_add_modes_noedid(connector, 1920, 1080);
85ee15d6
ML		 7154 } else {
7155 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7156 amdgpu_dm_connector_add_common_modes(encoder, connector);
a85ba005 7157 amdgpu_dm_connector_add_freesync_modes(connector, edid);
85ee15d6 7158 }
3e332d3a 7159 amdgpu_dm_fbc_init(connector);
5099114b 7160
c84dec2f 7161 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 7162}
7163
3ee6b26b
AD		 7164void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7165 struct amdgpu_dm_connector *aconnector,
7166 int connector_type,
7167 struct dc_link *link,
7168 int link_index)
e7b07cee 7169{
1348969a 7170 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
e7b07cee 7171
f04bee34
NK		 7172 /*
7173 * Some of the properties below require access to state, like bpc.
7174 * Allocate some default initial connector state with our reset helper.
7175 */
7176 if (aconnector->base.funcs->reset)
7177 aconnector->base.funcs->reset(&aconnector->base);
7178
e7b07cee
HW		 7179 aconnector->connector_id = link_index;
7180 aconnector->dc_link = link;
7181 aconnector->base.interlace_allowed = false;
7182 aconnector->base.doublescan_allowed = false;
7183 aconnector->base.stereo_allowed = false;
7184 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7185 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
6ce8f316 7186 aconnector->audio_inst = -1;
5b49da02
SJK		 7187 aconnector->pack_sdp_v1_3 = false;
7188 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7189 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
e7b07cee
HW		 7190 mutex_init(&aconnector->hpd_lock);
7191
1f6010a9
DF		 7192 /*
7193 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 7194 * which means HPD hot plug not supported
7195 */
e7b07cee
HW		 7196 switch (connector_type) {
7197 case DRM_MODE_CONNECTOR_HDMIA:
7198 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 7199 aconnector->base.ycbcr_420_allowed =
9ea59d5a 7200 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 7201 break;
7202 case DRM_MODE_CONNECTOR_DisplayPort:
7203 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
d715c9a2 7204 link->link_enc = link_enc_cfg_get_link_enc(link);
7b201d53 7205 ASSERT(link->link_enc);
f6e03f80
JS		 7206 if (link->link_enc)
7207 aconnector->base.ycbcr_420_allowed =
9ea59d5a 7208 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 7209 break;
7210 case DRM_MODE_CONNECTOR_DVID:
7211 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7212 break;
7213 default:
7214 break;
7215 }
7216
7217 drm_object_attach_property(&aconnector->base.base,
7218 dm->ddev->mode_config.scaling_mode_property,
7219 DRM_MODE_SCALE_NONE);
7220
7221 drm_object_attach_property(&aconnector->base.base,
7222 adev->mode_info.underscan_property,
7223 UNDERSCAN_OFF);
7224 drm_object_attach_property(&aconnector->base.base,
7225 adev->mode_info.underscan_hborder_property,
7226 0);
7227 drm_object_attach_property(&aconnector->base.base,
7228 adev->mode_info.underscan_vborder_property,
7229 0);
1825fd34 7230
f0127cb1 7231 if (!aconnector->mst_root)
8c61b31e 7232 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
1825fd34 7233
4a8ca46b 7234 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
e47f1691 7235 aconnector->base.state->max_bpc = 16;
4a8ca46b 7236 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
e7b07cee 7237
c1ee92f9 7238 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5cb32419 7239 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
c1ee92f9
DF		 7240 drm_object_attach_property(&aconnector->base.base,
7241 adev->mode_info.abm_level_property, 0);
7242 }
bb47de73
NK		 7243
7244 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7fad8da1
NK		 7245 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7246 connector_type == DRM_MODE_CONNECTOR_eDP) {
e057b52c 7247 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
88694af9 7248
f0127cb1 7249 if (!aconnector->mst_root)
8c61b31e
JFZ		 7250 drm_connector_attach_vrr_capable_property(&aconnector->base);
7251
e22bb562 7252 if (adev->dm.hdcp_workqueue)
53e108aa 7253 drm_connector_attach_content_protection_property(&aconnector->base, true);
bb47de73 7254 }
e7b07cee
HW		 7255}
7256
7578ecda
AD		 7257static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7258 struct i2c_msg *msgs, int num)
e7b07cee
HW		 7259{
7260 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7261 struct ddc_service *ddc_service = i2c->ddc_service;
7262 struct i2c_command cmd;
7263 int i;
7264 int result = -EIO;
7265
b830ebc9 7266 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 7267
7268 if (!cmd.payloads)
7269 return result;
7270
7271 cmd.number_of_payloads = num;
7272 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7273 cmd.speed = 100;
7274
7275 for (i = 0; i < num; i++) {
7276 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7277 cmd.payloads[i].address = msgs[i].addr;
7278 cmd.payloads[i].length = msgs[i].len;
7279 cmd.payloads[i].data = msgs[i].buf;
7280 }
7281
c85e6e54
DF		 7282 if (dc_submit_i2c(
7283 ddc_service->ctx->dc,
22676bc5 7284 ddc_service->link->link_index,
e7b07cee
HW		 7285 &cmd))
7286 result = num;
7287
7288 kfree(cmd.payloads);
7289 return result;
7290}
7291
7578ecda 7292static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 7293{
7294 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7295}
7296
7297static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7298 .master_xfer = amdgpu_dm_i2c_xfer,
7299 .functionality = amdgpu_dm_i2c_func,
7300};
7301
3ee6b26b
AD		 7302static struct amdgpu_i2c_adapter *
7303create_i2c(struct ddc_service *ddc_service,
7304 int link_index,
7305 int *res)
e7b07cee
HW		 7306{
7307 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7308 struct amdgpu_i2c_adapter *i2c;
7309
b830ebc9 7310 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 7311 if (!i2c)
7312 return NULL;
e7b07cee
HW		 7313 i2c->base.owner = THIS_MODULE;
7314 i2c->base.class = I2C_CLASS_DDC;
7315 i2c->base.dev.parent = &adev->pdev->dev;
7316 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 7317 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 7318 i2c_set_adapdata(&i2c->base, i2c);
7319 i2c->ddc_service = ddc_service;
7320
7321 return i2c;
7322}
7323
89fc8d4e 7324
1f6010a9
DF		 7325/*
7326 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 7327 * dc_link which will be represented by this aconnector.
7328 */
7578ecda
AD		 7329static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7330 struct amdgpu_dm_connector *aconnector,
ae67558b 7331 u32 link_index,
7578ecda 7332 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 7333{
7334 int res = 0;
7335 int connector_type;
7336 struct dc *dc = dm->dc;
7337 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7338 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 7339
7340 link->priv = aconnector;
e7b07cee 7341
f1ad2f5e 7342 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 7343
7344 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 7345 if (!i2c) {
7346 DRM_ERROR("Failed to create i2c adapter data\n");
7347 return -ENOMEM;
7348 }
7349
e7b07cee
HW		 7350 aconnector->i2c = i2c;
7351 res = i2c_add_adapter(&i2c->base);
7352
7353 if (res) {
7354 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7355 goto out_free;
7356 }
7357
7358 connector_type = to_drm_connector_type(link->connector_signal);
7359
17165de2 7360 res = drm_connector_init_with_ddc(
e7b07cee
HW		 7361 dm->ddev,
7362 &aconnector->base,
7363 &amdgpu_dm_connector_funcs,
17165de2
AP		 7364 connector_type,
7365 &i2c->base);
e7b07cee
HW		 7366
7367 if (res) {
7368 DRM_ERROR("connector_init failed\n");
7369 aconnector->connector_id = -1;
7370 goto out_free;
7371 }
7372
7373 drm_connector_helper_add(
7374 &aconnector->base,
7375 &amdgpu_dm_connector_helper_funcs);
7376
7377 amdgpu_dm_connector_init_helper(
7378 dm,
7379 aconnector,
7380 connector_type,
7381 link,
7382 link_index);
7383
cde4c44d 7384 drm_connector_attach_encoder(
e7b07cee
HW		 7385 &aconnector->base, &aencoder->base);
7386
e7b07cee
HW		 7387 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7388 || connector_type == DRM_MODE_CONNECTOR_eDP)
7daec99f 7389 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
e7b07cee 7390
e7b07cee
HW		 7391out_free:
7392 if (res) {
7393 kfree(i2c);
7394 aconnector->i2c = NULL;
7395 }
7396 return res;
7397}
7398
7399int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7400{
7401 switch (adev->mode_info.num_crtc) {
7402 case 1:
7403 return 0x1;
7404 case 2:
7405 return 0x3;
7406 case 3:
7407 return 0x7;
7408 case 4:
7409 return 0xf;
7410 case 5:
7411 return 0x1f;
7412 case 6:
7413 default:
7414 return 0x3f;
7415 }
7416}
7417
7578ecda
AD		 7418static int amdgpu_dm_encoder_init(struct drm_device *dev,
7419 struct amdgpu_encoder *aencoder,
7420 uint32_t link_index)
e7b07cee 7421{
1348969a 7422 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 7423
7424 int res = drm_encoder_init(dev,
7425 &aencoder->base,
7426 &amdgpu_dm_encoder_funcs,
7427 DRM_MODE_ENCODER_TMDS,
7428 NULL);
7429
7430 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7431
7432 if (!res)
7433 aencoder->encoder_id = link_index;
7434 else
7435 aencoder->encoder_id = -1;
7436
7437 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7438
7439 return res;
7440}
7441
3ee6b26b
AD		 7442static void manage_dm_interrupts(struct amdgpu_device *adev,
7443 struct amdgpu_crtc *acrtc,
7444 bool enable)
e7b07cee
HW		 7445{
7446 /*
8fe684e9
NK		 7447 * We have no guarantee that the frontend index maps to the same
7448 * backend index - some even map to more than one.
7449 *
7450 * TODO: Use a different interrupt or check DC itself for the mapping.
e7b07cee
HW		 7451 */
7452 int irq_type =
734dd01d 7453 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 7454 adev,
7455 acrtc->crtc_id);
7456
7457 if (enable) {
7458 drm_crtc_vblank_on(&acrtc->base);
7459 amdgpu_irq_get(
7460 adev,
7461 &adev->pageflip_irq,
7462 irq_type);
86bc2219
WL		 7463#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7464 amdgpu_irq_get(
7465 adev,
7466 &adev->vline0_irq,
7467 irq_type);
7468#endif
e7b07cee 7469 } else {
86bc2219
WL		 7470#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7471 amdgpu_irq_put(
7472 adev,
7473 &adev->vline0_irq,
7474 irq_type);
7475#endif
e7b07cee
HW		 7476 amdgpu_irq_put(
7477 adev,
7478 &adev->pageflip_irq,
7479 irq_type);
7480 drm_crtc_vblank_off(&acrtc->base);
7481 }
7482}
7483
8fe684e9
NK		 7484static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7485 struct amdgpu_crtc *acrtc)
7486{
7487 int irq_type =
7488 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7489
7490 /**
7491 * This reads the current state for the IRQ and force reapplies
7492 * the setting to hardware.
7493 */
7494 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7495}
7496
3ee6b26b
AD		 7497static bool
7498is_scaling_state_different(const struct dm_connector_state *dm_state,
7499 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 7500{
7501 if (dm_state->scaling != old_dm_state->scaling)
7502 return true;
7503 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7504 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7505 return true;
7506 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7507 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7508 return true;
b830ebc9
HW		 7509 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7510 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7511 return true;
e7b07cee
HW		 7512 return false;
7513}
7514
e8fd3eeb 7515static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7516 struct drm_crtc_state *old_crtc_state,
7517 struct drm_connector_state *new_conn_state,
7518 struct drm_connector_state *old_conn_state,
7519 const struct drm_connector *connector,
7520 struct hdcp_workqueue *hdcp_w)
0c8620d6
BL		 7521{
7522 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
97f6c917 7523 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
0c8620d6 7524
e8fd3eeb 7525 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7526 connector->index, connector->status, connector->dpms);
7527 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7528 old_conn_state->content_protection, new_conn_state->content_protection);
7529
7530 if (old_crtc_state)
7531 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7532 old_crtc_state->enable,
7533 old_crtc_state->active,
7534 old_crtc_state->mode_changed,
7535 old_crtc_state->active_changed,
7536 old_crtc_state->connectors_changed);
7537
7538 if (new_crtc_state)
7539 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7540 new_crtc_state->enable,
7541 new_crtc_state->active,
7542 new_crtc_state->mode_changed,
7543 new_crtc_state->active_changed,
7544 new_crtc_state->connectors_changed);
7545
7546 /* hdcp content type change */
7547 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7548 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7549 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7550 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
53e108aa
BL		 7551 return true;
7552 }
7553
e8fd3eeb 7554 /* CP is being re enabled, ignore this */
7555 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7556 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7557 if (new_crtc_state && new_crtc_state->mode_changed) {
7558 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7559 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7560 return true;
0b8f42ab 7561 }
e8fd3eeb 7562 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7563 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
0c8620d6
BL		 7564 return false;
7565 }
7566
31c0ed90
BL		 7567 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7568 *
7569 * Handles: UNDESIRED -> ENABLED
7570 */
e8fd3eeb 7571 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7572 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7573 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
0c8620d6 7574
0d9a947b
QZ		 7575 /* Stream removed and re-enabled
7576 *
7577 * Can sometimes overlap with the HPD case,
7578 * thus set update_hdcp to false to avoid
7579 * setting HDCP multiple times.
7580 *
7581 * Handles: DESIRED -> DESIRED (Special case)
7582 */
e8fd3eeb 7583 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7584 new_conn_state->crtc && new_conn_state->crtc->enabled &&
0d9a947b
QZ		 7585 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7586 dm_con_state->update_hdcp = false;
e8fd3eeb 7587 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7588 __func__);
0d9a947b
QZ		 7589 return true;
7590 }
7591
7592 /* Hot-plug, headless s3, dpms
7593 *
7594 * Only start HDCP if the display is connected/enabled.
7595 * update_hdcp flag will be set to false until the next
7596 * HPD comes in.
31c0ed90
BL		 7597 *
7598 * Handles: DESIRED -> DESIRED (Special case)
0c8620d6 7599 */
e8fd3eeb 7600 if (dm_con_state->update_hdcp &&
7601 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7602 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
97f6c917 7603 dm_con_state->update_hdcp = false;
e8fd3eeb 7604 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7605 __func__);
0c8620d6 7606 return true;
97f6c917 7607 }
0c8620d6 7608
e8fd3eeb 7609 if (old_conn_state->content_protection == new_conn_state->content_protection) {
7610 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7611 if (new_crtc_state && new_crtc_state->mode_changed) {
7612 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7613 __func__);
7614 return true;
0b8f42ab 7615 }
e8fd3eeb 7616 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7617 __func__);
7618 return false;
0b8f42ab 7619 }
e8fd3eeb 7620
7621 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
0c8620d6 7622 return false;
e8fd3eeb 7623 }
0c8620d6 7624
e8fd3eeb 7625 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7626 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7627 __func__);
0c8620d6 7628 return true;
e8fd3eeb 7629 }
0c8620d6 7630
e8fd3eeb 7631 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
0c8620d6
BL		 7632 return false;
7633}
e8fd3eeb 7634
3ee6b26b
AD		 7635static void remove_stream(struct amdgpu_device *adev,
7636 struct amdgpu_crtc *acrtc,
7637 struct dc_stream_state *stream)
e7b07cee
HW		 7638{
7639 /* this is the update mode case */
e7b07cee
HW		 7640
7641 acrtc->otg_inst = -1;
7642 acrtc->enabled = false;
7643}
7644
e7b07cee
HW		 7645static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7646{
7647
7648 assert_spin_locked(&acrtc->base.dev->event_lock);
7649 WARN_ON(acrtc->event);
7650
7651 acrtc->event = acrtc->base.state->event;
7652
7653 /* Set the flip status */
7654 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7655
7656 /* Mark this event as consumed */
7657 acrtc->base.state->event = NULL;
7658
cb2318b7
VL		 7659 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7660 acrtc->crtc_id);
e7b07cee
HW		 7661}
7662
bb47de73
NK		 7663static void update_freesync_state_on_stream(
7664 struct amdgpu_display_manager *dm,
7665 struct dm_crtc_state *new_crtc_state,
180db303
NK		 7666 struct dc_stream_state *new_stream,
7667 struct dc_plane_state *surface,
7668 u32 flip_timestamp_in_us)
bb47de73 7669{
09aef2c4 7670 struct mod_vrr_params vrr_params;
bb47de73 7671 struct dc_info_packet vrr_infopacket = {0};
09aef2c4 7672 struct amdgpu_device *adev = dm->adev;
585d450c 7673 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
09aef2c4 7674 unsigned long flags;
4cda3243 7675 bool pack_sdp_v1_3 = false;
5b49da02
SJK		 7676 struct amdgpu_dm_connector *aconn;
7677 enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
bb47de73
NK		 7678
7679 if (!new_stream)
7680 return;
7681
7682 /*
7683 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7684 * For now it's sufficient to just guard against these conditions.
7685 */
7686
7687 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7688 return;
7689
4a580877 7690 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
585d450c 7691 vrr_params = acrtc->dm_irq_params.vrr_params;
09aef2c4 7692
180db303
NK		 7693 if (surface) {
7694 mod_freesync_handle_preflip(
7695 dm->freesync_module,
7696 surface,
7697 new_stream,
7698 flip_timestamp_in_us,
7699 &vrr_params);
09aef2c4
MK		 7700
7701 if (adev->family < AMDGPU_FAMILY_AI &&
7702 amdgpu_dm_vrr_active(new_crtc_state)) {
7703 mod_freesync_handle_v_update(dm->freesync_module,
7704 new_stream, &vrr_params);
e63e2491
EB		 7705
7706 /* Need to call this before the frame ends. */
7707 dc_stream_adjust_vmin_vmax(dm->dc,
7708 new_crtc_state->stream,
7709 &vrr_params.adjust);
09aef2c4 7710 }
180db303 7711 }
bb47de73 7712
5b49da02
SJK		 7713 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7714
7715 if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7716 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7717
7718 if (aconn->vsdb_info.amd_vsdb_version == 1)
7719 packet_type = PACKET_TYPE_FS_V1;
7720 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7721 packet_type = PACKET_TYPE_FS_V2;
7722 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7723 packet_type = PACKET_TYPE_FS_V3;
7724
7725 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7726 &new_stream->adaptive_sync_infopacket);
7727 }
7728
bb47de73
NK		 7729 mod_freesync_build_vrr_infopacket(
7730 dm->freesync_module,
7731 new_stream,
180db303 7732 &vrr_params,
5b49da02 7733 packet_type,
ecd0136b 7734 TRANSFER_FUNC_UNKNOWN,
4cda3243
MT		 7735 &vrr_infopacket,
7736 pack_sdp_v1_3);
bb47de73 7737
8a48b44c 7738 new_crtc_state->freesync_vrr_info_changed |=
bb47de73
NK		 7739 (memcmp(&new_crtc_state->vrr_infopacket,
7740 &vrr_infopacket,
7741 sizeof(vrr_infopacket)) != 0);
7742
585d450c 7743 acrtc->dm_irq_params.vrr_params = vrr_params;
bb47de73
NK		 7744 new_crtc_state->vrr_infopacket = vrr_infopacket;
7745
bb47de73 7746 new_stream->vrr_infopacket = vrr_infopacket;
7eaef116 7747 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
bb47de73
NK		 7748
7749 if (new_crtc_state->freesync_vrr_info_changed)
7750 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7751 new_crtc_state->base.crtc->base.id,
7752 (int)new_crtc_state->base.vrr_enabled,
180db303 7753 (int)vrr_params.state);
09aef2c4 7754
4a580877 7755 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
bb47de73
NK		 7756}
7757
585d450c 7758static void update_stream_irq_parameters(
e854194c
MK		 7759 struct amdgpu_display_manager *dm,
7760 struct dm_crtc_state *new_crtc_state)
7761{
7762 struct dc_stream_state *new_stream = new_crtc_state->stream;
09aef2c4 7763 struct mod_vrr_params vrr_params;
e854194c 7764 struct mod_freesync_config config = new_crtc_state->freesync_config;
09aef2c4 7765 struct amdgpu_device *adev = dm->adev;
585d450c 7766 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
09aef2c4 7767 unsigned long flags;
e854194c
MK		 7768
7769 if (!new_stream)
7770 return;
7771
7772 /*
7773 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7774 * For now it's sufficient to just guard against these conditions.
7775 */
7776 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7777 return;
7778
4a580877 7779 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
585d450c 7780 vrr_params = acrtc->dm_irq_params.vrr_params;
09aef2c4 7781
e854194c
MK		 7782 if (new_crtc_state->vrr_supported &&
7783 config.min_refresh_in_uhz &&
7784 config.max_refresh_in_uhz) {
a85ba005
NC		 7785 /*
7786 * if freesync compatible mode was set, config.state will be set
7787 * in atomic check
7788 */
7789 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7790 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7791 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7792 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7793 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7794 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7795 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7796 } else {
7797 config.state = new_crtc_state->base.vrr_enabled ?
7798 VRR_STATE_ACTIVE_VARIABLE :
7799 VRR_STATE_INACTIVE;
7800 }
e854194c
MK		 7801 } else {
7802 config.state = VRR_STATE_UNSUPPORTED;
7803 }
7804
7805 mod_freesync_build_vrr_params(dm->freesync_module,
7806 new_stream,
7807 &config, &vrr_params);
7808
585d450c
AP		 7809 new_crtc_state->freesync_config = config;
7810 /* Copy state for access from DM IRQ handler */
7811 acrtc->dm_irq_params.freesync_config = config;
7812 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7813 acrtc->dm_irq_params.vrr_params = vrr_params;
4a580877 7814 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
e854194c
MK		 7815}
7816
66b0c973
MK		 7817static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7818 struct dm_crtc_state *new_state)
7819{
7820 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
7821 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
7822
7823 if (!old_vrr_active && new_vrr_active) {
7824 /* Transition VRR inactive -> active:
7825 * While VRR is active, we must not disable vblank irq, as a
7826 * reenable after disable would compute bogus vblank/pflip
7827 * timestamps if it likely happened inside display front-porch.
d2574c33
MK		 7828 *
7829 * We also need vupdate irq for the actual core vblank handling
7830 * at end of vblank.
66b0c973 7831 */
8799c0be
YL		 7832 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0);
7833 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
66b0c973
MK		 7834 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7835 __func__, new_state->base.crtc->base.id);
7836 } else if (old_vrr_active && !new_vrr_active) {
7837 /* Transition VRR active -> inactive:
7838 * Allow vblank irq disable again for fixed refresh rate.
7839 */
8799c0be 7840 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0);
66b0c973
MK		 7841 drm_crtc_vblank_put(new_state->base.crtc);
7842 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7843 __func__, new_state->base.crtc->base.id);
7844 }
7845}
7846
8ad27806
NK		 7847static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7848{
7849 struct drm_plane *plane;
5760dcb9 7850 struct drm_plane_state *old_plane_state;
8ad27806
NK		 7851 int i;
7852
7853 /*
7854 * TODO: Make this per-stream so we don't issue redundant updates for
7855 * commits with multiple streams.
7856 */
5760dcb9 7857 for_each_old_plane_in_state(state, plane, old_plane_state, i)
8ad27806
NK		 7858 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7859 handle_cursor_update(plane, old_plane_state);
7860}
7861
3be5262e 7862static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 7863 struct dc_state *dc_state,
3ee6b26b
AD		 7864 struct drm_device *dev,
7865 struct amdgpu_display_manager *dm,
7866 struct drm_crtc *pcrtc,
420cd472 7867 bool wait_for_vblank)
e7b07cee 7868{
ae67558b 7869 u32 i;
d6ed6d0d 7870 u64 timestamp_ns = ktime_get_ns();
e7b07cee 7871 struct drm_plane *plane;
0bc9706d 7872 struct drm_plane_state *old_plane_state, *new_plane_state;
e7b07cee 7873 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 7874 struct drm_crtc_state *new_pcrtc_state =
7875 drm_atomic_get_new_crtc_state(state, pcrtc);
7876 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 7877 struct dm_crtc_state *dm_old_crtc_state =
7878 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
74aa7bd4 7879 int planes_count = 0, vpos, hpos;
e7b07cee 7880 unsigned long flags;
ae67558b 7881 u32 target_vblank, last_flip_vblank;
fdd1fe57 7882 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
cc79950b 7883 bool cursor_update = false;
74aa7bd4 7884 bool pflip_present = false;
d6ed6d0d 7885 bool dirty_rects_changed = false;
bc7f670e
DF		 7886 struct {
7887 struct dc_surface_update surface_updates[MAX_SURFACES];
7888 struct dc_plane_info plane_infos[MAX_SURFACES];
7889 struct dc_scaling_info scaling_infos[MAX_SURFACES];
74aa7bd4 7890 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
bc7f670e 7891 struct dc_stream_update stream_update;
74aa7bd4 7892 } *bundle;
bc7f670e 7893
74aa7bd4 7894 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8a48b44c 7895
74aa7bd4
DF		 7896 if (!bundle) {
7897 dm_error("Failed to allocate update bundle\n");
4b510503
NK		 7898 goto cleanup;
7899 }
e7b07cee 7900
8ad27806
NK		 7901 /*
7902 * Disable the cursor first if we're disabling all the planes.
7903 * It'll remain on the screen after the planes are re-enabled
7904 * if we don't.
7905 */
7906 if (acrtc_state->active_planes == 0)
7907 amdgpu_dm_commit_cursors(state);
7908
e7b07cee 7909 /* update planes when needed */
efc8278e 7910 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
0bc9706d 7911 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 7912 struct drm_crtc_state *new_crtc_state;
0bc9706d 7913 struct drm_framebuffer *fb = new_plane_state->fb;
6eed95b0 7914 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
34bafd27 7915 bool plane_needs_flip;
c7af5f77 7916 struct dc_plane_state *dc_plane;
54d76575 7917 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee 7918
80c218d5 7919 /* Cursor plane is handled after stream updates */
cc79950b
MD		 7920 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7921 if ((fb && crtc == pcrtc) ||
7922 (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7923 cursor_update = true;
7924
e7b07cee 7925 continue;
cc79950b 7926 }
e7b07cee 7927
f5ba60fe
DD		 7928 if (!fb || !crtc || pcrtc != crtc)
7929 continue;
7930
7931 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7932 if (!new_crtc_state->active)
e7b07cee
HW		 7933 continue;
7934
bc7f670e 7935 dc_plane = dm_new_plane_state->dc_state;
e7b07cee 7936
74aa7bd4 7937 bundle->surface_updates[planes_count].surface = dc_plane;
bc7f670e 7938 if (new_pcrtc_state->color_mgmt_changed) {
74aa7bd4
DF		 7939 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7940 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
44efb784 7941 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
bc7f670e 7942 }
8a48b44c 7943
4375d625 7944 fill_dc_scaling_info(dm->adev, new_plane_state,
695af5f9 7945 &bundle->scaling_infos[planes_count]);
8a48b44c 7946
695af5f9
NK		 7947 bundle->surface_updates[planes_count].scaling_info =
7948 &bundle->scaling_infos[planes_count];
8a48b44c 7949
f5031000 7950 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8a48b44c 7951
f5031000 7952 pflip_present = pflip_present || plane_needs_flip;
8a48b44c 7953
f5031000
DF		 7954 if (!plane_needs_flip) {
7955 planes_count += 1;
7956 continue;
7957 }
8a48b44c 7958
695af5f9 7959 fill_dc_plane_info_and_addr(
8ce5d842 7960 dm->adev, new_plane_state,
6eed95b0 7961 afb->tiling_flags,
695af5f9 7962 &bundle->plane_infos[planes_count],
87b7ebc2 7963 &bundle->flip_addrs[planes_count].address,
6eed95b0 7964 afb->tmz_surface, false);
87b7ebc2 7965
9f07550b 7966 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
87b7ebc2
RS		 7967 new_plane_state->plane->index,
7968 bundle->plane_infos[planes_count].dcc.enable);
695af5f9
NK		 7969
7970 bundle->surface_updates[planes_count].plane_info =
7971 &bundle->plane_infos[planes_count];
8a48b44c 7972
d6ed6d0d 7973 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
d852871c
HM		 7974 fill_dc_dirty_rects(plane, old_plane_state,
7975 new_plane_state, new_crtc_state,
d6ed6d0d
TC		 7976 &bundle->flip_addrs[planes_count],
7977 &dirty_rects_changed);
7978
7979 /*
7980 * If the dirty regions changed, PSR-SU need to be disabled temporarily
7981 * and enabled it again after dirty regions are stable to avoid video glitch.
7982 * PSR-SU will be enabled in vblank_control_worker() if user pause the video
7983 * during the PSR-SU was disabled.
7984 */
7985 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
7986 acrtc_attach->dm_irq_params.allow_psr_entry &&
7987#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
7988 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
7989#endif
7990 dirty_rects_changed) {
7991 mutex_lock(&dm->dc_lock);
7992 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
7993 timestamp_ns;
7994 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
7995 amdgpu_dm_psr_disable(acrtc_state->stream);
7996 mutex_unlock(&dm->dc_lock);
7997 }
7998 }
7cc191ee 7999
caff0e66
NK		 8000 /*
8001 * Only allow immediate flips for fast updates that don't
8002 * change FB pitch, DCC state, rotation or mirroing.
8003 */
f5031000 8004 bundle->flip_addrs[planes_count].flip_immediate =
4d85f45c 8005 crtc->state->async_flip &&
caff0e66 8006 acrtc_state->update_type == UPDATE_TYPE_FAST;
8a48b44c 8007
f5031000
DF		 8008 timestamp_ns = ktime_get_ns();
8009 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8010 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8011 bundle->surface_updates[planes_count].surface = dc_plane;
8a48b44c 8012
f5031000
DF		 8013 if (!bundle->surface_updates[planes_count].surface) {
8014 DRM_ERROR("No surface for CRTC: id=%d\n",
8015 acrtc_attach->crtc_id);
8016 continue;
bc7f670e
DF		 8017 }
8018
f5031000
DF		 8019 if (plane == pcrtc->primary)
8020 update_freesync_state_on_stream(
8021 dm,
8022 acrtc_state,
8023 acrtc_state->stream,
8024 dc_plane,
8025 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
bc7f670e 8026
9f07550b 8027 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
f5031000
DF		 8028 __func__,
8029 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8030 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
bc7f670e
DF		 8031
8032 planes_count += 1;
8033
8a48b44c
DF		 8034 }
8035
74aa7bd4 8036 if (pflip_present) {
634092b1
MK		 8037 if (!vrr_active) {
8038 /* Use old throttling in non-vrr fixed refresh rate mode
8039 * to keep flip scheduling based on target vblank counts
8040 * working in a backwards compatible way, e.g., for
8041 * clients using the GLX_OML_sync_control extension or
8042 * DRI3/Present extension with defined target_msc.
8043 */
e3eff4b5 8044 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
634092b1
MK		 8045 }
8046 else {
8047 /* For variable refresh rate mode only:
8048 * Get vblank of last completed flip to avoid > 1 vrr
8049 * flips per video frame by use of throttling, but allow
8050 * flip programming anywhere in the possibly large
8051 * variable vrr vblank interval for fine-grained flip
8052 * timing control and more opportunity to avoid stutter
8053 * on late submission of flips.
8054 */
8055 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5d1c59c4 8056 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
634092b1
MK		 8057 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8058 }
8059
fdd1fe57 8060 target_vblank = last_flip_vblank + wait_for_vblank;
8a48b44c
DF		 8061
8062 /*
8063 * Wait until we're out of the vertical blank period before the one
8064 * targeted by the flip
8065 */
8066 while ((acrtc_attach->enabled &&
8067 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8068 0, &vpos, &hpos, NULL,
8069 NULL, &pcrtc->hwmode)
8070 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8071 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8072 (int)(target_vblank -
e3eff4b5 8073 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8a48b44c
DF		 8074 usleep_range(1000, 1100);
8075 }
8076
8fe684e9
NK		 8077 /**
8078 * Prepare the flip event for the pageflip interrupt to handle.
8079 *
8080 * This only works in the case where we've already turned on the
8081 * appropriate hardware blocks (eg. HUBP) so in the transition case
8082 * from 0 -> n planes we have to skip a hardware generated event
8083 * and rely on sending it from software.
8084 */
8085 if (acrtc_attach->base.state->event &&
10a36226 8086 acrtc_state->active_planes > 0) {
8a48b44c
DF		 8087 drm_crtc_vblank_get(pcrtc);
8088
8089 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8090
8091 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8092 prepare_flip_isr(acrtc_attach);
8093
8094 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8095 }
8096
8097 if (acrtc_state->stream) {
8a48b44c 8098 if (acrtc_state->freesync_vrr_info_changed)
74aa7bd4 8099 bundle->stream_update.vrr_infopacket =
8a48b44c 8100 &acrtc_state->stream->vrr_infopacket;
e7b07cee 8101 }
cc79950b
MD		 8102 } else if (cursor_update && acrtc_state->active_planes > 0 &&
8103 acrtc_attach->base.state->event) {
8104 drm_crtc_vblank_get(pcrtc);
8105
8106 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8107
8108 acrtc_attach->event = acrtc_attach->base.state->event;
8109 acrtc_attach->base.state->event = NULL;
8110
8111 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
e7b07cee
HW		 8112 }
8113
bc92c065 8114 /* Update the planes if changed or disable if we don't have any. */
ed9656fb
ES		 8115 if ((planes_count || acrtc_state->active_planes == 0) &&
8116 acrtc_state->stream) {
58aa1c50
NK		 8117 /*
8118 * If PSR or idle optimizations are enabled then flush out
8119 * any pending work before hardware programming.
8120 */
06dd1888
NK		 8121 if (dm->vblank_control_workqueue)
8122 flush_workqueue(dm->vblank_control_workqueue);
58aa1c50 8123
b6e881c9 8124 bundle->stream_update.stream = acrtc_state->stream;
bc7f670e 8125 if (new_pcrtc_state->mode_changed) {
74aa7bd4
DF		 8126 bundle->stream_update.src = acrtc_state->stream->src;
8127 bundle->stream_update.dst = acrtc_state->stream->dst;
e7b07cee
HW		 8128 }
8129
cf020d49
NK		 8130 if (new_pcrtc_state->color_mgmt_changed) {
8131 /*
8132 * TODO: This isn't fully correct since we've actually
8133 * already modified the stream in place.
8134 */
8135 bundle->stream_update.gamut_remap =
8136 &acrtc_state->stream->gamut_remap_matrix;
8137 bundle->stream_update.output_csc_transform =
8138 &acrtc_state->stream->csc_color_matrix;
8139 bundle->stream_update.out_transfer_func =
8140 acrtc_state->stream->out_transfer_func;
8141 }
bc7f670e 8142
8a48b44c 8143 acrtc_state->stream->abm_level = acrtc_state->abm_level;
bc7f670e 8144 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
74aa7bd4 8145 bundle->stream_update.abm_level = &acrtc_state->abm_level;
44d09c6a 8146
e63e2491
EB		 8147 /*
8148 * If FreeSync state on the stream has changed then we need to
8149 * re-adjust the min/max bounds now that DC doesn't handle this
8150 * as part of commit.
8151 */
a85ba005 8152 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
e63e2491
EB		 8153 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8154 dc_stream_adjust_vmin_vmax(
8155 dm->dc, acrtc_state->stream,
585d450c 8156 &acrtc_attach->dm_irq_params.vrr_params.adjust);
e63e2491
EB		 8157 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8158 }
bc7f670e 8159 mutex_lock(&dm->dc_lock);
8c322309 8160 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
d1ebfdd8 8161 acrtc_state->stream->link->psr_settings.psr_allow_active)
8c322309
RL		 8162 amdgpu_dm_psr_disable(acrtc_state->stream);
8163
f7511289
RS		 8164 dc_update_planes_and_stream(dm->dc,
8165 bundle->surface_updates,
8166 planes_count,
8167 acrtc_state->stream,
8168 &bundle->stream_update);
8c322309 8169
8fe684e9
NK		 8170 /**
8171 * Enable or disable the interrupts on the backend.
8172 *
8173 * Most pipes are put into power gating when unused.
8174 *
8175 * When power gating is enabled on a pipe we lose the
8176 * interrupt enablement state when power gating is disabled.
8177 *
8178 * So we need to update the IRQ control state in hardware
8179 * whenever the pipe turns on (since it could be previously
8180 * power gated) or off (since some pipes can't be power gated
8181 * on some ASICs).
8182 */
8183 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
1348969a
LT		 8184 dm_update_pflip_irq_state(drm_to_adev(dev),
8185 acrtc_attach);
8fe684e9 8186
8c322309 8187 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
1cfbbdde 8188 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
d1ebfdd8 8189 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8c322309 8190 amdgpu_dm_link_setup_psr(acrtc_state->stream);
58aa1c50
NK		 8191
8192 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8193 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8194 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8195 struct amdgpu_dm_connector *aconn =
8196 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
1a365683
RL		 8197
8198 if (aconn->psr_skip_count > 0)
8199 aconn->psr_skip_count--;
58aa1c50
NK		 8200
8201 /* Allow PSR when skip count is 0. */
8202 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
7cc191ee
LL		 8203
8204 /*
8205 * If sink supports PSR SU, there is no need to rely on
8206 * a vblank event disable request to enable PSR. PSR SU
8207 * can be enabled immediately once OS demonstrates an
8208 * adequate number of fast atomic commits to notify KMD
8209 * of update events. See `vblank_control_worker()`.
8210 */
8211 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8212 acrtc_attach->dm_irq_params.allow_psr_entry &&
c0459bdd
AL		 8213#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8214 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8215#endif
d6ed6d0d
TC		 8216 !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8217 (timestamp_ns -
8218 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8219 500000000)
7cc191ee 8220 amdgpu_dm_psr_enable(acrtc_state->stream);
58aa1c50
NK		 8221 } else {
8222 acrtc_attach->dm_irq_params.allow_psr_entry = false;
8c322309
RL		 8223 }
8224
bc7f670e 8225 mutex_unlock(&dm->dc_lock);
e7b07cee 8226 }
4b510503 8227
8ad27806
NK		 8228 /*
8229 * Update cursor state *after* programming all the planes.
8230 * This avoids redundant programming in the case where we're going
8231 * to be disabling a single plane - those pipes are being disabled.
8232 */
8233 if (acrtc_state->active_planes)
8234 amdgpu_dm_commit_cursors(state);
80c218d5 8235
4b510503 8236cleanup:
74aa7bd4 8237 kfree(bundle);
e7b07cee
HW		 8238}
8239
6ce8f316
NK		 8240static void amdgpu_dm_commit_audio(struct drm_device *dev,
8241 struct drm_atomic_state *state)
8242{
1348969a 8243 struct amdgpu_device *adev = drm_to_adev(dev);
6ce8f316
NK		 8244 struct amdgpu_dm_connector *aconnector;
8245 struct drm_connector *connector;
8246 struct drm_connector_state *old_con_state, *new_con_state;
8247 struct drm_crtc_state *new_crtc_state;
8248 struct dm_crtc_state *new_dm_crtc_state;
8249 const struct dc_stream_status *status;
8250 int i, inst;
8251
8252 /* Notify device removals. */
8253 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8254 if (old_con_state->crtc != new_con_state->crtc) {
8255 /* CRTC changes require notification. */
8256 goto notify;
8257 }
8258
8259 if (!new_con_state->crtc)
8260 continue;
8261
8262 new_crtc_state = drm_atomic_get_new_crtc_state(
8263 state, new_con_state->crtc);
8264
8265 if (!new_crtc_state)
8266 continue;
8267
8268 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8269 continue;
8270
8271 notify:
8272 aconnector = to_amdgpu_dm_connector(connector);
8273
8274 mutex_lock(&adev->dm.audio_lock);
8275 inst = aconnector->audio_inst;
8276 aconnector->audio_inst = -1;
8277 mutex_unlock(&adev->dm.audio_lock);
8278
8279 amdgpu_dm_audio_eld_notify(adev, inst);
8280 }
8281
8282 /* Notify audio device additions. */
8283 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8284 if (!new_con_state->crtc)
8285 continue;
8286
8287 new_crtc_state = drm_atomic_get_new_crtc_state(
8288 state, new_con_state->crtc);
8289
8290 if (!new_crtc_state)
8291 continue;
8292
8293 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8294 continue;
8295
8296 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8297 if (!new_dm_crtc_state->stream)
8298 continue;
8299
8300 status = dc_stream_get_status(new_dm_crtc_state->stream);
8301 if (!status)
8302 continue;
8303
8304 aconnector = to_amdgpu_dm_connector(connector);
8305
8306 mutex_lock(&adev->dm.audio_lock);
8307 inst = status->audio_inst;
8308 aconnector->audio_inst = inst;
8309 mutex_unlock(&adev->dm.audio_lock);
8310
8311 amdgpu_dm_audio_eld_notify(adev, inst);
8312 }
8313}
8314
1f6010a9 8315/*
27b3f4fc
LSL		 8316 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8317 * @crtc_state: the DRM CRTC state
8318 * @stream_state: the DC stream state.
8319 *
8320 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8321 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8322 */
8323static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8324 struct dc_stream_state *stream_state)
8325{
b9952f93 8326 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
27b3f4fc 8327}
e7b07cee 8328
b8592b48
LL		 8329/**
8330 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8331 * @state: The atomic state to commit
8332 *
8333 * This will tell DC to commit the constructed DC state from atomic_check,
8334 * programming the hardware. Any failures here implies a hardware failure, since
8335 * atomic check should have filtered anything non-kosher.
8336 */
7578ecda 8337static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 8338{
8339 struct drm_device *dev = state->dev;
1348969a 8340 struct amdgpu_device *adev = drm_to_adev(dev);
e7b07cee
HW		 8341 struct amdgpu_display_manager *dm = &adev->dm;
8342 struct dm_atomic_state *dm_state;
eb3dc897 8343 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
ae67558b 8344 u32 i, j;
5cc6dcbd 8345 struct drm_crtc *crtc;
0bc9706d 8346 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 8347 unsigned long flags;
8348 bool wait_for_vblank = true;
8349 struct drm_connector *connector;
c2cea706 8350 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 8351 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 8352 int crtc_disable_count = 0;
6ee90e88 8353 bool mode_set_reset_required = false;
047de3f1 8354 int r;
e7b07cee 8355
e8a98235
RS		 8356 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8357
047de3f1
CK		 8358 r = drm_atomic_helper_wait_for_fences(dev, state, false);
8359 if (unlikely(r))
8360 DRM_ERROR("Waiting for fences timed out!");
8361
e7b07cee 8362 drm_atomic_helper_update_legacy_modeset_state(dev, state);
a5c2c0d1 8363 drm_dp_mst_atomic_wait_for_dependencies(state);
e7b07cee 8364
eb3dc897
NK		 8365 dm_state = dm_atomic_get_new_state(state);
8366 if (dm_state && dm_state->context) {
8367 dc_state = dm_state->context;
8368 } else {
8369 /* No state changes, retain current state. */
813d20dc 8370 dc_state_temp = dc_create_state(dm->dc);
eb3dc897
NK		 8371 ASSERT(dc_state_temp);
8372 dc_state = dc_state_temp;
8373 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8374 }
e7b07cee 8375
6d90a208
AP		 8376 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8377 new_crtc_state, i) {
8378 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8379
8380 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8381
8382 if (old_crtc_state->active &&
8383 (!new_crtc_state->active ||
8384 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8385 manage_dm_interrupts(adev, acrtc, false);
8386 dc_stream_release(dm_old_crtc_state->stream);
8387 }
8388 }
8389
8976f73b
RS		 8390 drm_atomic_helper_calc_timestamping_constants(state);
8391
e7b07cee 8392 /* update changed items */
0bc9706d 8393 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 8394 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 8395
54d76575
LSL		 8396 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8397 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 8398
9f07550b 8399 drm_dbg_state(state->dev,
e7b07cee
HW		 8400 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8401 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8402 "connectors_changed:%d\n",
8403 acrtc->crtc_id,
0bc9706d
LSL		 8404 new_crtc_state->enable,
8405 new_crtc_state->active,
8406 new_crtc_state->planes_changed,
8407 new_crtc_state->mode_changed,
8408 new_crtc_state->active_changed,
8409 new_crtc_state->connectors_changed);
e7b07cee 8410
5c68c652
VL		 8411 /* Disable cursor if disabling crtc */
8412 if (old_crtc_state->active && !new_crtc_state->active) {
8413 struct dc_cursor_position position;
8414
8415 memset(&position, 0, sizeof(position));
8416 mutex_lock(&dm->dc_lock);
8417 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8418 mutex_unlock(&dm->dc_lock);
8419 }
8420
27b3f4fc
LSL		 8421 /* Copy all transient state flags into dc state */
8422 if (dm_new_crtc_state->stream) {
8423 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8424 dm_new_crtc_state->stream);
8425 }
8426
e7b07cee
HW		 8427 /* handles headless hotplug case, updating new_state and
8428 * aconnector as needed
8429 */
8430
54d76575 8431 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 8432
4711c033 8433 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 8434
54d76575 8435 if (!dm_new_crtc_state->stream) {
e7b07cee 8436 /*
b830ebc9
HW		 8437 * this could happen because of issues with
8438 * userspace notifications delivery.
8439 * In this case userspace tries to set mode on
1f6010a9
DF		 8440 * display which is disconnected in fact.
8441 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 8442 * We expect reset mode will come soon.
8443 *
8444 * This can also happen when unplug is done
8445 * during resume sequence ended
8446 *
8447 * In this case, we want to pretend we still
8448 * have a sink to keep the pipe running so that
8449 * hw state is consistent with the sw state
8450 */
f1ad2f5e 8451 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 8452 __func__, acrtc->base.base.id);
8453 continue;
8454 }
8455
54d76575
LSL		 8456 if (dm_old_crtc_state->stream)
8457 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 8458
97028037
LP		 8459 pm_runtime_get_noresume(dev->dev);
8460
e7b07cee 8461 acrtc->enabled = true;
0bc9706d
LSL		 8462 acrtc->hw_mode = new_crtc_state->mode;
8463 crtc->hwmode = new_crtc_state->mode;
6ee90e88 8464 mode_set_reset_required = true;
0bc9706d 8465 } else if (modereset_required(new_crtc_state)) {
4711c033 8466 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 8467 /* i.e. reset mode */
6ee90e88 8468 if (dm_old_crtc_state->stream)
54d76575 8469 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
a85ba005 8470
6ee90e88 8471 mode_set_reset_required = true;
e7b07cee
HW		 8472 }
8473 } /* for_each_crtc_in_state() */
8474
eb3dc897 8475 if (dc_state) {
6ee90e88 8476 /* if there mode set or reset, disable eDP PSR */
58aa1c50 8477 if (mode_set_reset_required) {
06dd1888
NK		 8478 if (dm->vblank_control_workqueue)
8479 flush_workqueue(dm->vblank_control_workqueue);
cae5c1ab 8480
6ee90e88 8481 amdgpu_dm_psr_disable_all(dm);
58aa1c50 8482 }
6ee90e88 8483
eb3dc897 8484 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 8485 mutex_lock(&dm->dc_lock);
b8272241 8486 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
f3106c94
JC		 8487
8488 /* Allow idle optimization when vblank count is 0 for display off */
8489 if (dm->active_vblank_irq_count == 0)
8490 dc_allow_idle_optimizations(dm->dc, true);
674e78ac 8491 mutex_unlock(&dm->dc_lock);
fa2123db 8492 }
fe8858bb 8493
0bc9706d 8494 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 8495 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 8496
54d76575 8497 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 8498
54d76575 8499 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 8500 const struct dc_stream_status *status =
54d76575 8501 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 8502
eb3dc897 8503 if (!status)
09f609c3
LL		 8504 status = dc_stream_get_status_from_state(dc_state,
8505 dm_new_crtc_state->stream);
e7b07cee 8506 if (!status)
54d76575 8507 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 8508 else
8509 acrtc->otg_inst = status->primary_otg_inst;
8510 }
8511 }
0c8620d6
BL		 8512 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8513 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8514 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8515 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8516
e8fd3eeb 8517 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8518
8519 if (!connector)
8520 continue;
8521
8522 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8523 connector->index, connector->status, connector->dpms);
8524 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8525 old_con_state->content_protection, new_con_state->content_protection);
8526
8527 if (aconnector->dc_sink) {
8528 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8529 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8530 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8531 aconnector->dc_sink->edid_caps.display_name);
8532 }
8533 }
8534
0c8620d6 8535 new_crtc_state = NULL;
e8fd3eeb 8536 old_crtc_state = NULL;
0c8620d6 8537
e8fd3eeb 8538 if (acrtc) {
0c8620d6 8539 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
e8fd3eeb 8540 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8541 }
8542
8543 if (old_crtc_state)
8544 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8545 old_crtc_state->enable,
8546 old_crtc_state->active,
8547 old_crtc_state->mode_changed,
8548 old_crtc_state->active_changed,
8549 old_crtc_state->connectors_changed);
8550
8551 if (new_crtc_state)
8552 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8553 new_crtc_state->enable,
8554 new_crtc_state->active,
8555 new_crtc_state->mode_changed,
8556 new_crtc_state->active_changed,
8557 new_crtc_state->connectors_changed);
8558 }
8559
8560 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8561 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8562 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8563 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8564
8565 new_crtc_state = NULL;
8566 old_crtc_state = NULL;
8567
8568 if (acrtc) {
8569 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8570 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8571 }
0c8620d6
BL		 8572
8573 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8574
8575 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8576 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8577 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8578 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
97f6c917 8579 dm_new_con_state->update_hdcp = true;
0c8620d6
BL		 8580 continue;
8581 }
8582
e8fd3eeb 8583 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8584 old_con_state, connector, adev->dm.hdcp_workqueue)) {
82986fd6 8585 /* when display is unplugged from mst hub, connctor will
8586 * be destroyed within dm_dp_mst_connector_destroy. connector
8587 * hdcp perperties, like type, undesired, desired, enabled,
8588 * will be lost. So, save hdcp properties into hdcp_work within
8589 * amdgpu_dm_atomic_commit_tail. if the same display is
8590 * plugged back with same display index, its hdcp properties
8591 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8592 */
8593
e8fd3eeb 8594 bool enable_encryption = false;
8595
8596 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8597 enable_encryption = true;
8598
82986fd6 8599 if (aconnector->dc_link && aconnector->dc_sink &&
8600 aconnector->dc_link->type == dc_connection_mst_branch) {
8601 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8602 struct hdcp_workqueue *hdcp_w =
8603 &hdcp_work[aconnector->dc_link->link_index];
8604
8605 hdcp_w->hdcp_content_type[connector->index] =
8606 new_con_state->hdcp_content_type;
8607 hdcp_w->content_protection[connector->index] =
8608 new_con_state->content_protection;
8609 }
8610
e8fd3eeb 8611 if (new_crtc_state && new_crtc_state->mode_changed &&
8612 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8613 enable_encryption = true;
8614
8615 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8616
b1abe558
BL		 8617 hdcp_update_display(
8618 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
e8fd3eeb 8619 new_con_state->hdcp_content_type, enable_encryption);
8620 }
0c8620d6 8621 }
e7b07cee 8622
02d6a6fc 8623 /* Handle connector state changes */
c2cea706 8624 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 8625 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8626 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8627 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
efc8278e 8628 struct dc_surface_update dummy_updates[MAX_SURFACES];
19afd799 8629 struct dc_stream_update stream_update;
b232d4ed 8630 struct dc_info_packet hdr_packet;
e7b07cee 8631 struct dc_stream_status *status = NULL;
b232d4ed 8632 bool abm_changed, hdr_changed, scaling_changed;
e7b07cee 8633
efc8278e 8634 memset(&dummy_updates, 0, sizeof(dummy_updates));
19afd799
NC		 8635 memset(&stream_update, 0, sizeof(stream_update));
8636
44d09c6a 8637 if (acrtc) {
0bc9706d 8638 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 8639 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8640 }
0bc9706d 8641
e7b07cee 8642 /* Skip any modesets/resets */
0bc9706d 8643 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 8644 continue;
8645
54d76575 8646 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 8647 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8648
b232d4ed
NK		 8649 scaling_changed = is_scaling_state_different(dm_new_con_state,
8650 dm_old_con_state);
8651
8652 abm_changed = dm_new_crtc_state->abm_level !=
8653 dm_old_crtc_state->abm_level;
8654
8655 hdr_changed =
72921cdf 8656 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
b232d4ed
NK		 8657
8658 if (!scaling_changed && !abm_changed && !hdr_changed)
c1ee92f9 8659 continue;
e7b07cee 8660
b6e881c9 8661 stream_update.stream = dm_new_crtc_state->stream;
b232d4ed 8662 if (scaling_changed) {
02d6a6fc 8663 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
b6e881c9 8664 dm_new_con_state, dm_new_crtc_state->stream);
e7b07cee 8665
02d6a6fc
DF		 8666 stream_update.src = dm_new_crtc_state->stream->src;
8667 stream_update.dst = dm_new_crtc_state->stream->dst;
8668 }
8669
b232d4ed 8670 if (abm_changed) {
02d6a6fc
DF		 8671 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8672
8673 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8674 }
70e8ffc5 8675
b232d4ed
NK		 8676 if (hdr_changed) {
8677 fill_hdr_info_packet(new_con_state, &hdr_packet);
8678 stream_update.hdr_static_metadata = &hdr_packet;
8679 }
8680
54d76575 8681 status = dc_stream_get_status(dm_new_crtc_state->stream);
57738ae4
ND		 8682
8683 if (WARN_ON(!status))
8684 continue;
8685
3be5262e 8686 WARN_ON(!status->plane_count);
e7b07cee 8687
02d6a6fc
DF		 8688 /*
8689 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8690 * Here we create an empty update on each plane.
8691 * To fix this, DC should permit updating only stream properties.
8692 */
8693 for (j = 0; j < status->plane_count; j++)
efc8278e 8694 dummy_updates[j].surface = status->plane_states[0];
02d6a6fc
DF		 8695
8696
8697 mutex_lock(&dm->dc_lock);
f7511289
RS		 8698 dc_update_planes_and_stream(dm->dc,
8699 dummy_updates,
8700 status->plane_count,
8701 dm_new_crtc_state->stream,
8702 &stream_update);
02d6a6fc 8703 mutex_unlock(&dm->dc_lock);
e7b07cee
HW		 8704 }
8705
8fe684e9
NK		 8706 /**
8707 * Enable interrupts for CRTCs that are newly enabled or went through
8708 * a modeset. It was intentionally deferred until after the front end
8709 * state was modified to wait until the OTG was on and so the IRQ
8710 * handlers didn't access stale or invalid state.
8711 */
8712 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8713 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8e7b6fee
WL		 8714#ifdef CONFIG_DEBUG_FS
8715 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8799c0be
YL		 8716#endif
8717 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8718 if (old_crtc_state->active && !new_crtc_state->active)
8719 crtc_disable_count++;
8720
8721 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8722 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8723
8724 /* For freesync config update on crtc state and params for irq */
8725 update_stream_irq_parameters(dm, dm_new_crtc_state);
8726
8727#ifdef CONFIG_DEBUG_FS
d98af272
WL		 8728 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8729 cur_crc_src = acrtc->dm_irq_params.crc_src;
8730 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8e7b6fee 8731#endif
585d450c 8732
8fe684e9
NK		 8733 if (new_crtc_state->active &&
8734 (!old_crtc_state->active ||
8735 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
585d450c
AP		 8736 dc_stream_retain(dm_new_crtc_state->stream);
8737 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8fe684e9 8738 manage_dm_interrupts(adev, acrtc, true);
8799c0be
YL		 8739 }
8740 /* Handle vrr on->off / off->on transitions */
8741 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
e2881d6d 8742
24eb9374 8743#ifdef CONFIG_DEBUG_FS
8799c0be
YL		 8744 if (new_crtc_state->active &&
8745 (!old_crtc_state->active ||
8746 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8fe684e9
NK		 8747 /**
8748 * Frontend may have changed so reapply the CRC capture
8749 * settings for the stream.
8750 */
8e7b6fee 8751 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
86bc2219 8752#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
d98af272
WL		 8753 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8754 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
c0459bdd 8755 acrtc->dm_irq_params.window_param.update_win = true;
1b11ff76
AL		 8756
8757 /**
8758 * It takes 2 frames for HW to stably generate CRC when
8759 * resuming from suspend, so we set skip_frame_cnt 2.
8760 */
c0459bdd 8761 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
d98af272
WL		 8762 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8763 }
86bc2219 8764#endif
bbc49fc0
WL		 8765 if (amdgpu_dm_crtc_configure_crc_source(
8766 crtc, dm_new_crtc_state, cur_crc_src))
8767 DRM_DEBUG_DRIVER("Failed to configure crc source");
8799c0be 8768 }
8fe684e9 8769 }
2130b87b 8770#endif
8fe684e9 8771 }
e7b07cee 8772
420cd472 8773 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
4d85f45c 8774 if (new_crtc_state->async_flip)
420cd472
DF		 8775 wait_for_vblank = false;
8776
e7b07cee 8777 /* update planes when needed per crtc*/
5cc6dcbd 8778 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 8779 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 8780
54d76575 8781 if (dm_new_crtc_state->stream)
eb3dc897 8782 amdgpu_dm_commit_planes(state, dc_state, dev,
420cd472 8783 dm, crtc, wait_for_vblank);
e7b07cee
HW		 8784 }
8785
6ce8f316
NK		 8786 /* Update audio instances for each connector. */
8787 amdgpu_dm_commit_audio(dev, state);
8788
7230362c 8789 /* restore the backlight level */
7fd13bae
AD		 8790 for (i = 0; i < dm->num_of_edps; i++) {
8791 if (dm->backlight_dev[i] &&
4052287a 8792 (dm->actual_brightness[i] != dm->brightness[i]))
7fd13bae
AD		 8793 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8794 }
83a3439d 8795
e7b07cee
HW		 8796 /*
8797 * send vblank event on all events not handled in flip and
8798 * mark consumed event for drm_atomic_helper_commit_hw_done
8799 */
4a580877 8800 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
0bc9706d 8801 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 8802
0bc9706d
LSL		 8803 if (new_crtc_state->event)
8804 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 8805
0bc9706d 8806 new_crtc_state->event = NULL;
e7b07cee 8807 }
4a580877 8808 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
e7b07cee 8809
29c8f234
LL		 8810 /* Signal HW programming completion */
8811 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 8812
8813 if (wait_for_vblank)
320a1274 8814 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 8815
8816 drm_atomic_helper_cleanup_planes(dev, state);
97028037 8817
5f6fab24
AD		 8818 /* return the stolen vga memory back to VRAM */
8819 if (!adev->mman.keep_stolen_vga_memory)
8820 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8821 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8822
1f6010a9
DF		 8823 /*
8824 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 8825 * so we can put the GPU into runtime suspend if we're not driving any
8826 * displays anymore
8827 */
fe2a1965
LP		 8828 for (i = 0; i < crtc_disable_count; i++)
8829 pm_runtime_put_autosuspend(dev->dev);
97028037 8830 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 8831
8832 if (dc_state_temp)
8833 dc_release_state(dc_state_temp);
e7b07cee
HW		 8834}
8835
e7b07cee
HW		 8836static int dm_force_atomic_commit(struct drm_connector *connector)
8837{
8838 int ret = 0;
8839 struct drm_device *ddev = connector->dev;
8840 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8841 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8842 struct drm_plane *plane = disconnected_acrtc->base.primary;
8843 struct drm_connector_state *conn_state;
8844 struct drm_crtc_state *crtc_state;
8845 struct drm_plane_state *plane_state;
8846
8847 if (!state)
8848 return -ENOMEM;
8849
8850 state->acquire_ctx = ddev->mode_config.acquire_ctx;
8851
8852 /* Construct an atomic state to restore previous display setting */
8853
8854 /*
8855 * Attach connectors to drm_atomic_state
8856 */
8857 conn_state = drm_atomic_get_connector_state(state, connector);
8858
8859 ret = PTR_ERR_OR_ZERO(conn_state);
8860 if (ret)
2dc39051 8861 goto out;
e7b07cee
HW		 8862
8863 /* Attach crtc to drm_atomic_state*/
8864 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8865
8866 ret = PTR_ERR_OR_ZERO(crtc_state);
8867 if (ret)
2dc39051 8868 goto out;
e7b07cee
HW		 8869
8870 /* force a restore */
8871 crtc_state->mode_changed = true;
8872
8873 /* Attach plane to drm_atomic_state */
8874 plane_state = drm_atomic_get_plane_state(state, plane);
8875
8876 ret = PTR_ERR_OR_ZERO(plane_state);
8877 if (ret)
2dc39051 8878 goto out;
e7b07cee
HW		 8879
8880 /* Call commit internally with the state we just constructed */
8881 ret = drm_atomic_commit(state);
e7b07cee 8882
2dc39051 8883out:
e7b07cee 8884 drm_atomic_state_put(state);
2dc39051
VL		 8885 if (ret)
8886 DRM_ERROR("Restoring old state failed with %i\n", ret);
e7b07cee
HW		 8887
8888 return ret;
8889}
8890
8891/*
1f6010a9
DF		 8892 * This function handles all cases when set mode does not come upon hotplug.
8893 * This includes when a display is unplugged then plugged back into the
8894 * same port and when running without usermode desktop manager supprot
e7b07cee 8895 */
3ee6b26b
AD		 8896void dm_restore_drm_connector_state(struct drm_device *dev,
8897 struct drm_connector *connector)
e7b07cee 8898{
c84dec2f 8899 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 8900 struct amdgpu_crtc *disconnected_acrtc;
8901 struct dm_crtc_state *acrtc_state;
8902
8903 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8904 return;
8905
8906 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 8907 if (!disconnected_acrtc)
8908 return;
e7b07cee 8909
70e8ffc5
HW		 8910 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8911 if (!acrtc_state->stream)
e7b07cee
HW		 8912 return;
8913
8914 /*
8915 * If the previous sink is not released and different from the current,
8916 * we deduce we are in a state where we can not rely on usermode call
8917 * to turn on the display, so we do it here
8918 */
8919 if (acrtc_state->stream->sink != aconnector->dc_sink)
8920 dm_force_atomic_commit(&aconnector->base);
8921}
8922
1f6010a9 8923/*
e7b07cee
HW		 8924 * Grabs all modesetting locks to serialize against any blocking commits,
8925 * Waits for completion of all non blocking commits.
8926 */
3ee6b26b
AD		 8927static int do_aquire_global_lock(struct drm_device *dev,
8928 struct drm_atomic_state *state)
e7b07cee
HW		 8929{
8930 struct drm_crtc *crtc;
8931 struct drm_crtc_commit *commit;
8932 long ret;
8933
1f6010a9
DF		 8934 /*
8935 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 8936 * ensure that when the framework release it the
8937 * extra locks we are locking here will get released to
8938 */
8939 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8940 if (ret)
8941 return ret;
8942
8943 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8944 spin_lock(&crtc->commit_lock);
8945 commit = list_first_entry_or_null(&crtc->commit_list,
8946 struct drm_crtc_commit, commit_entry);
8947 if (commit)
8948 drm_crtc_commit_get(commit);
8949 spin_unlock(&crtc->commit_lock);
8950
8951 if (!commit)
8952 continue;
8953
1f6010a9
DF		 8954 /*
8955 * Make sure all pending HW programming completed and
e7b07cee
HW		 8956 * page flips done
8957 */
8958 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8959
8960 if (ret > 0)
8961 ret = wait_for_completion_interruptible_timeout(
8962 &commit->flip_done, 10*HZ);
8963
8964 if (ret == 0)
8965 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 8966 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 8967
8968 drm_crtc_commit_put(commit);
8969 }
8970
8971 return ret < 0 ? ret : 0;
8972}
8973
bb47de73
NK		 8974static void get_freesync_config_for_crtc(
8975 struct dm_crtc_state *new_crtc_state,
8976 struct dm_connector_state *new_con_state)
98e6436d
AK		 8977{
8978 struct mod_freesync_config config = {0};
98e6436d
AK		 8979 struct amdgpu_dm_connector *aconnector =
8980 to_amdgpu_dm_connector(new_con_state->base.connector);
a057ec46 8981 struct drm_display_mode *mode = &new_crtc_state->base.mode;
0ab925d3 8982 int vrefresh = drm_mode_vrefresh(mode);
a85ba005 8983 bool fs_vid_mode = false;
98e6436d 8984
a057ec46 8985 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
0ab925d3
NK		 8986 vrefresh >= aconnector->min_vfreq &&
8987 vrefresh <= aconnector->max_vfreq;
bb47de73 8988
6ffa6799 8989 if (new_crtc_state->vrr_supported) {
7e5098ab 8990 new_crtc_state->stream->ignore_msa_timing_param = true;
6ffa6799 8991 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
7e5098ab 8992
a85ba005
NC		 8993 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
8994 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
69ff8845 8995 config.vsif_supported = true;
180db303 8996 config.btr = true;
98e6436d 8997
a85ba005
NC		 8998 if (fs_vid_mode) {
8999 config.state = VRR_STATE_ACTIVE_FIXED;
9000 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9001 goto out;
9002 } else if (new_crtc_state->base.vrr_enabled) {
9003 config.state = VRR_STATE_ACTIVE_VARIABLE;
9004 } else {
9005 config.state = VRR_STATE_INACTIVE;
9006 }
9007 }
9008out:
bb47de73
NK		 9009 new_crtc_state->freesync_config = config;
9010}
98e6436d 9011
bb47de73
NK		 9012static void reset_freesync_config_for_crtc(
9013 struct dm_crtc_state *new_crtc_state)
9014{
9015 new_crtc_state->vrr_supported = false;
98e6436d 9016
bb47de73
NK		 9017 memset(&new_crtc_state->vrr_infopacket, 0,
9018 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 9019}
9020
a85ba005
NC		 9021static bool
9022is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9023 struct drm_crtc_state *new_crtc_state)
9024{
1cbd7887 9025 const struct drm_display_mode *old_mode, *new_mode;
a85ba005
NC		 9026
9027 if (!old_crtc_state || !new_crtc_state)
9028 return false;
9029
1cbd7887
VS		 9030 old_mode = &old_crtc_state->mode;
9031 new_mode = &new_crtc_state->mode;
9032
9033 if (old_mode->clock == new_mode->clock &&
9034 old_mode->hdisplay == new_mode->hdisplay &&
9035 old_mode->vdisplay == new_mode->vdisplay &&
9036 old_mode->htotal == new_mode->htotal &&
9037 old_mode->vtotal != new_mode->vtotal &&
9038 old_mode->hsync_start == new_mode->hsync_start &&
9039 old_mode->vsync_start != new_mode->vsync_start &&
9040 old_mode->hsync_end == new_mode->hsync_end &&
9041 old_mode->vsync_end != new_mode->vsync_end &&
9042 old_mode->hskew == new_mode->hskew &&
9043 old_mode->vscan == new_mode->vscan &&
9044 (old_mode->vsync_end - old_mode->vsync_start) ==
9045 (new_mode->vsync_end - new_mode->vsync_start))
a85ba005
NC		 9046 return true;
9047
9048 return false;
9049}
9050
9051static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
ae67558b 9052 u64 num, den, res;
a85ba005
NC		 9053 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9054
9055 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9056
9057 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9058 den = (unsigned long long)new_crtc_state->mode.htotal *
9059 (unsigned long long)new_crtc_state->mode.vtotal;
9060
9061 res = div_u64(num, den);
9062 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9063}
9064
f11d9373 9065static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
17ce8a69
RL		 9066 struct drm_atomic_state *state,
9067 struct drm_crtc *crtc,
9068 struct drm_crtc_state *old_crtc_state,
9069 struct drm_crtc_state *new_crtc_state,
9070 bool enable,
9071 bool *lock_and_validation_needed)
e7b07cee 9072{
eb3dc897 9073 struct dm_atomic_state *dm_state = NULL;
54d76575 9074 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 9075 struct dc_stream_state *new_stream;
62f55537 9076 int ret = 0;
d4d4a645 9077
1f6010a9
DF		 9078 /*
9079 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9080 * update changed items
9081 */
4b9674e5
LL		 9082 struct amdgpu_crtc *acrtc = NULL;
9083 struct amdgpu_dm_connector *aconnector = NULL;
9084 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9085 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
e7b07cee 9086
4b9674e5 9087 new_stream = NULL;
9635b754 9088
4b9674e5
LL		 9089 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9090 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9091 acrtc = to_amdgpu_crtc(crtc);
4b9674e5 9092 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 9093
4b9674e5
LL		 9094 /* TODO This hack should go away */
9095 if (aconnector && enable) {
9096 /* Make sure fake sink is created in plug-in scenario */
9097 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9098 &aconnector->base);
9099 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9100 &aconnector->base);
19f89e23 9101
4b9674e5
LL		 9102 if (IS_ERR(drm_new_conn_state)) {
9103 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9104 goto fail;
9105 }
19f89e23 9106
4b9674e5
LL		 9107 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9108 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 9109
02d35a67
JFZ		 9110 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9111 goto skip_modeset;
9112
cbd14ae7
SW		 9113 new_stream = create_validate_stream_for_sink(aconnector,
9114 &new_crtc_state->mode,
9115 dm_new_conn_state,
9116 dm_old_crtc_state->stream);
19f89e23 9117
4b9674e5
LL		 9118 /*
9119 * we can have no stream on ACTION_SET if a display
9120 * was disconnected during S3, in this case it is not an
9121 * error, the OS will be updated after detection, and
9122 * will do the right thing on next atomic commit
9123 */
19f89e23 9124
4b9674e5
LL		 9125 if (!new_stream) {
9126 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9127 __func__, acrtc->base.base.id);
9128 ret = -ENOMEM;
9129 goto fail;
9130 }
e7b07cee 9131
3d4e52d0
VL		 9132 /*
9133 * TODO: Check VSDB bits to decide whether this should
9134 * be enabled or not.
9135 */
9136 new_stream->triggered_crtc_reset.enabled =
9137 dm->force_timing_sync;
9138
4b9674e5 9139 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 9140
88694af9
NK		 9141 ret = fill_hdr_info_packet(drm_new_conn_state,
9142 &new_stream->hdr_static_metadata);
9143 if (ret)
9144 goto fail;
9145
7e930949
NK		 9146 /*
9147 * If we already removed the old stream from the context
9148 * (and set the new stream to NULL) then we can't reuse
9149 * the old stream even if the stream and scaling are unchanged.
9150 * We'll hit the BUG_ON and black screen.
9151 *
9152 * TODO: Refactor this function to allow this check to work
9153 * in all conditions.
9154 */
4243c84a
MD		 9155 if (amdgpu_freesync_vid_mode &&
9156 dm_new_crtc_state->stream &&
a85ba005
NC		 9157 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9158 goto skip_modeset;
9159
7e930949
NK		 9160 if (dm_new_crtc_state->stream &&
9161 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4b9674e5
LL		 9162 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9163 new_crtc_state->mode_changed = false;
9164 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9165 new_crtc_state->mode_changed);
62f55537 9166 }
4b9674e5 9167 }
b830ebc9 9168
02d35a67 9169 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 9170 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9171 goto skip_modeset;
e7b07cee 9172
9f07550b 9173 drm_dbg_state(state->dev,
4b9674e5
LL		 9174 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9175 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9176 "connectors_changed:%d\n",
9177 acrtc->crtc_id,
9178 new_crtc_state->enable,
9179 new_crtc_state->active,
9180 new_crtc_state->planes_changed,
9181 new_crtc_state->mode_changed,
9182 new_crtc_state->active_changed,
9183 new_crtc_state->connectors_changed);
62f55537 9184
4b9674e5
LL		 9185 /* Remove stream for any changed/disabled CRTC */
9186 if (!enable) {
62f55537 9187
4b9674e5
LL		 9188 if (!dm_old_crtc_state->stream)
9189 goto skip_modeset;
eb3dc897 9190
0f5f1ee4
AP		 9191 /* Unset freesync video if it was active before */
9192 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9193 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9194 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9195 }
9196
9197 /* Now check if we should set freesync video mode */
4243c84a 9198 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
a85ba005
NC		 9199 is_timing_unchanged_for_freesync(new_crtc_state,
9200 old_crtc_state)) {
9201 new_crtc_state->mode_changed = false;
9202 DRM_DEBUG_DRIVER(
9203 "Mode change not required for front porch change, "
9204 "setting mode_changed to %d",
9205 new_crtc_state->mode_changed);
9206
9207 set_freesync_fixed_config(dm_new_crtc_state);
9208
9209 goto skip_modeset;
4243c84a 9210 } else if (amdgpu_freesync_vid_mode && aconnector &&
a85ba005
NC		 9211 is_freesync_video_mode(&new_crtc_state->mode,
9212 aconnector)) {
e88ebd83
SC		 9213 struct drm_display_mode *high_mode;
9214
9215 high_mode = get_highest_refresh_rate_mode(aconnector, false);
9216 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9217 set_freesync_fixed_config(dm_new_crtc_state);
9218 }
a85ba005
NC		 9219 }
9220
4b9674e5
LL		 9221 ret = dm_atomic_get_state(state, &dm_state);
9222 if (ret)
9223 goto fail;
e7b07cee 9224
4b9674e5
LL		 9225 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9226 crtc->base.id);
62f55537 9227
4b9674e5
LL		 9228 /* i.e. reset mode */
9229 if (dc_remove_stream_from_ctx(
9230 dm->dc,
9231 dm_state->context,
9232 dm_old_crtc_state->stream) != DC_OK) {
9233 ret = -EINVAL;
9234 goto fail;
9235 }
62f55537 9236
4b9674e5
LL		 9237 dc_stream_release(dm_old_crtc_state->stream);
9238 dm_new_crtc_state->stream = NULL;
bb47de73 9239
4b9674e5 9240 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 9241
4b9674e5 9242 *lock_and_validation_needed = true;
62f55537 9243
4b9674e5
LL		 9244 } else {/* Add stream for any updated/enabled CRTC */
9245 /*
9246 * Quick fix to prevent NULL pointer on new_stream when
9247 * added MST connectors not found in existing crtc_state in the chained mode
9248 * TODO: need to dig out the root cause of that
9249 */
84a8b390 9250 if (!aconnector)
4b9674e5 9251 goto skip_modeset;
62f55537 9252
4b9674e5
LL		 9253 if (modereset_required(new_crtc_state))
9254 goto skip_modeset;
62f55537 9255
4b9674e5
LL		 9256 if (modeset_required(new_crtc_state, new_stream,
9257 dm_old_crtc_state->stream)) {
62f55537 9258
4b9674e5 9259 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 9260
4b9674e5
LL		 9261 ret = dm_atomic_get_state(state, &dm_state);
9262 if (ret)
9263 goto fail;
27b3f4fc 9264
4b9674e5 9265 dm_new_crtc_state->stream = new_stream;
62f55537 9266
4b9674e5 9267 dc_stream_retain(new_stream);
1dc90497 9268
4711c033
LT		 9269 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9270 crtc->base.id);
1dc90497 9271
4b9674e5
LL		 9272 if (dc_add_stream_to_ctx(
9273 dm->dc,
9274 dm_state->context,
9275 dm_new_crtc_state->stream) != DC_OK) {
9276 ret = -EINVAL;
9277 goto fail;
9b690ef3
BL		 9278 }
9279
4b9674e5
LL		 9280 *lock_and_validation_needed = true;
9281 }
9282 }
e277adc5 9283
4b9674e5
LL		 9284skip_modeset:
9285 /* Release extra reference */
9286 if (new_stream)
9287 dc_stream_release(new_stream);
e277adc5 9288
4b9674e5
LL		 9289 /*
9290 * We want to do dc stream updates that do not require a
9291 * full modeset below.
9292 */
2afda735 9293 if (!(enable && aconnector && new_crtc_state->active))
4b9674e5
LL		 9294 return 0;
9295 /*
9296 * Given above conditions, the dc state cannot be NULL because:
9297 * 1. We're in the process of enabling CRTCs (just been added
9298 * to the dc context, or already is on the context)
9299 * 2. Has a valid connector attached, and
9300 * 3. Is currently active and enabled.
9301 * => The dc stream state currently exists.
9302 */
9303 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 9304
4b9674e5 9305 /* Scaling or underscan settings */
c521fc31
RL		 9306 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9307 drm_atomic_crtc_needs_modeset(new_crtc_state))
4b9674e5
LL		 9308 update_stream_scaling_settings(
9309 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 9310
b05e2c5e
DF		 9311 /* ABM settings */
9312 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9313
4b9674e5
LL		 9314 /*
9315 * Color management settings. We also update color properties
9316 * when a modeset is needed, to ensure it gets reprogrammed.
9317 */
9318 if (dm_new_crtc_state->base.color_mgmt_changed ||
9319 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
cf020d49 9320 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
4b9674e5
LL		 9321 if (ret)
9322 goto fail;
62f55537 9323 }
e7b07cee 9324
4b9674e5
LL		 9325 /* Update Freesync settings. */
9326 get_freesync_config_for_crtc(dm_new_crtc_state,
9327 dm_new_conn_state);
9328
62f55537 9329 return ret;
9635b754
DS		 9330
9331fail:
9332 if (new_stream)
9333 dc_stream_release(new_stream);
9334 return ret;
62f55537 9335}
9b690ef3 9336
f6ff2a08
NK		 9337static bool should_reset_plane(struct drm_atomic_state *state,
9338 struct drm_plane *plane,
9339 struct drm_plane_state *old_plane_state,
9340 struct drm_plane_state *new_plane_state)
9341{
9342 struct drm_plane *other;
9343 struct drm_plane_state *old_other_state, *new_other_state;
9344 struct drm_crtc_state *new_crtc_state;
9345 int i;
9346
70a1efac
NK		 9347 /*
9348 * TODO: Remove this hack once the checks below are sufficient
9349 * enough to determine when we need to reset all the planes on
9350 * the stream.
9351 */
9352 if (state->allow_modeset)
9353 return true;
9354
f6ff2a08
NK		 9355 /* Exit early if we know that we're adding or removing the plane. */
9356 if (old_plane_state->crtc != new_plane_state->crtc)
9357 return true;
9358
9359 /* old crtc == new_crtc == NULL, plane not in context. */
9360 if (!new_plane_state->crtc)
9361 return false;
9362
9363 new_crtc_state =
9364 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9365
9366 if (!new_crtc_state)
9367 return true;
9368
7316c4ad
NK		 9369 /* CRTC Degamma changes currently require us to recreate planes. */
9370 if (new_crtc_state->color_mgmt_changed)
9371 return true;
9372
f6ff2a08
NK		 9373 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9374 return true;
9375
9376 /*
9377 * If there are any new primary or overlay planes being added or
9378 * removed then the z-order can potentially change. To ensure
9379 * correct z-order and pipe acquisition the current DC architecture
9380 * requires us to remove and recreate all existing planes.
9381 *
9382 * TODO: Come up with a more elegant solution for this.
9383 */
9384 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
6eed95b0 9385 struct amdgpu_framebuffer *old_afb, *new_afb;
f6ff2a08
NK		 9386 if (other->type == DRM_PLANE_TYPE_CURSOR)
9387 continue;
9388
9389 if (old_other_state->crtc != new_plane_state->crtc &&
9390 new_other_state->crtc != new_plane_state->crtc)
9391 continue;
9392
9393 if (old_other_state->crtc != new_other_state->crtc)
9394 return true;
9395
dc4cb30d
NK		 9396 /* Src/dst size and scaling updates. */
9397 if (old_other_state->src_w != new_other_state->src_w ||
9398 old_other_state->src_h != new_other_state->src_h ||
9399 old_other_state->crtc_w != new_other_state->crtc_w ||
9400 old_other_state->crtc_h != new_other_state->crtc_h)
9401 return true;
9402
9403 /* Rotation / mirroring updates. */
9404 if (old_other_state->rotation != new_other_state->rotation)
9405 return true;
9406
9407 /* Blending updates. */
9408 if (old_other_state->pixel_blend_mode !=
9409 new_other_state->pixel_blend_mode)
9410 return true;
9411
9412 /* Alpha updates. */
9413 if (old_other_state->alpha != new_other_state->alpha)
9414 return true;
9415
9416 /* Colorspace changes. */
9417 if (old_other_state->color_range != new_other_state->color_range ||
9418 old_other_state->color_encoding != new_other_state->color_encoding)
9419 return true;
9420
9a81cc60
NK		 9421 /* Framebuffer checks fall at the end. */
9422 if (!old_other_state->fb || !new_other_state->fb)
9423 continue;
9424
9425 /* Pixel format changes can require bandwidth updates. */
9426 if (old_other_state->fb->format != new_other_state->fb->format)
9427 return true;
9428
6eed95b0
BN		 9429 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9430 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9a81cc60
NK		 9431
9432 /* Tiling and DCC changes also require bandwidth updates. */
37384b3f
BN		 9433 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9434 old_afb->base.modifier != new_afb->base.modifier)
f6ff2a08
NK		 9435 return true;
9436 }
9437
9438 return false;
9439}
9440
b0455fda
SS		 9441static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9442 struct drm_plane_state *new_plane_state,
9443 struct drm_framebuffer *fb)
9444{
e72868c4
SS		 9445 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9446 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
b0455fda 9447 unsigned int pitch;
e72868c4 9448 bool linear;
b0455fda
SS		 9449
9450 if (fb->width > new_acrtc->max_cursor_width ||
9451 fb->height > new_acrtc->max_cursor_height) {
9452 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9453 new_plane_state->fb->width,
9454 new_plane_state->fb->height);
9455 return -EINVAL;
9456 }
9457 if (new_plane_state->src_w != fb->width << 16 ||
9458 new_plane_state->src_h != fb->height << 16) {
9459 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9460 return -EINVAL;
9461 }
9462
9463 /* Pitch in pixels */
9464 pitch = fb->pitches[0] / fb->format->cpp[0];
9465
9466 if (fb->width != pitch) {
9467 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9468 fb->width, pitch);
9469 return -EINVAL;
9470 }
9471
9472 switch (pitch) {
9473 case 64:
9474 case 128:
9475 case 256:
9476 /* FB pitch is supported by cursor plane */
9477 break;
9478 default:
9479 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9480 return -EINVAL;
9481 }
9482
e72868c4
SS		 9483 /* Core DRM takes care of checking FB modifiers, so we only need to
9484 * check tiling flags when the FB doesn't have a modifier. */
9485 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9486 if (adev->family < AMDGPU_FAMILY_AI) {
9487 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9488 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9489 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9490 } else {
9491 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9492 }
9493 if (!linear) {
9494 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9495 return -EINVAL;
9496 }
9497 }
9498
b0455fda
SS		 9499 return 0;
9500}
9501
9e869063
LL		 9502static int dm_update_plane_state(struct dc *dc,
9503 struct drm_atomic_state *state,
9504 struct drm_plane *plane,
9505 struct drm_plane_state *old_plane_state,
9506 struct drm_plane_state *new_plane_state,
9507 bool enable,
35f33086
BL		 9508 bool *lock_and_validation_needed,
9509 bool *is_top_most_overlay)
62f55537 9510{
eb3dc897
NK		 9511
9512 struct dm_atomic_state *dm_state = NULL;
62f55537 9513 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 9514 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 9515 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 9516 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
626bf90f 9517 struct amdgpu_crtc *new_acrtc;
f6ff2a08 9518 bool needs_reset;
62f55537 9519 int ret = 0;
e7b07cee 9520
9b690ef3 9521
9e869063
LL		 9522 new_plane_crtc = new_plane_state->crtc;
9523 old_plane_crtc = old_plane_state->crtc;
9524 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9525 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 9526
626bf90f
SS		 9527 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9528 if (!enable || !new_plane_crtc ||
9529 drm_atomic_plane_disabling(plane->state, new_plane_state))
9530 return 0;
9531
9532 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9533
5f581248
SS		 9534 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9535 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9536 return -EINVAL;
9537 }
9538
24f99d2b 9539 if (new_plane_state->fb) {
b0455fda
SS		 9540 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9541 new_plane_state->fb);
9542 if (ret)
9543 return ret;
24f99d2b
SS		 9544 }
9545
9e869063 9546 return 0;
626bf90f 9547 }
9b690ef3 9548
f6ff2a08
NK		 9549 needs_reset = should_reset_plane(state, plane, old_plane_state,
9550 new_plane_state);
9551
9e869063
LL		 9552 /* Remove any changed/removed planes */
9553 if (!enable) {
f6ff2a08 9554 if (!needs_reset)
9e869063 9555 return 0;
a7b06724 9556
9e869063
LL		 9557 if (!old_plane_crtc)
9558 return 0;
62f55537 9559
9e869063
LL		 9560 old_crtc_state = drm_atomic_get_old_crtc_state(
9561 state, old_plane_crtc);
9562 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 9563
9e869063
LL		 9564 if (!dm_old_crtc_state->stream)
9565 return 0;
62f55537 9566
9e869063
LL		 9567 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9568 plane->base.id, old_plane_crtc->base.id);
9b690ef3 9569
9e869063
LL		 9570 ret = dm_atomic_get_state(state, &dm_state);
9571 if (ret)
9572 return ret;
eb3dc897 9573
9e869063
LL		 9574 if (!dc_remove_plane_from_context(
9575 dc,
9576 dm_old_crtc_state->stream,
9577 dm_old_plane_state->dc_state,
9578 dm_state->context)) {
62f55537 9579
c3537613 9580 return -EINVAL;
9e869063 9581 }
e7b07cee 9582
9b690ef3 9583
9e869063
LL		 9584 dc_plane_state_release(dm_old_plane_state->dc_state);
9585 dm_new_plane_state->dc_state = NULL;
1dc90497 9586
9e869063 9587 *lock_and_validation_needed = true;
1dc90497 9588
9e869063
LL		 9589 } else { /* Add new planes */
9590 struct dc_plane_state *dc_new_plane_state;
1dc90497 9591
9e869063
LL		 9592 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9593 return 0;
e7b07cee 9594
9e869063
LL		 9595 if (!new_plane_crtc)
9596 return 0;
e7b07cee 9597
9e869063
LL		 9598 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9599 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 9600
9e869063
LL		 9601 if (!dm_new_crtc_state->stream)
9602 return 0;
62f55537 9603
f6ff2a08 9604 if (!needs_reset)
9e869063 9605 return 0;
62f55537 9606
8c44515b
AP		 9607 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9608 if (ret)
9609 return ret;
9610
9e869063 9611 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 9612
9e869063
LL		 9613 dc_new_plane_state = dc_create_plane_state(dc);
9614 if (!dc_new_plane_state)
9615 return -ENOMEM;
62f55537 9616
35f33086
BL		 9617 /* Block top most plane from being a video plane */
9618 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9619 if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9620 return -EINVAL;
9621 else
9622 *is_top_most_overlay = false;
9623 }
9624
4711c033
LT		 9625 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9626 plane->base.id, new_plane_crtc->base.id);
8c45c5db 9627
695af5f9 9628 ret = fill_dc_plane_attributes(
1348969a 9629 drm_to_adev(new_plane_crtc->dev),
9e869063
LL		 9630 dc_new_plane_state,
9631 new_plane_state,
9632 new_crtc_state);
9633 if (ret) {
9634 dc_plane_state_release(dc_new_plane_state);
9635 return ret;
9636 }
62f55537 9637
9e869063
LL		 9638 ret = dm_atomic_get_state(state, &dm_state);
9639 if (ret) {
9640 dc_plane_state_release(dc_new_plane_state);
9641 return ret;
9642 }
eb3dc897 9643
9e869063
LL		 9644 /*
9645 * Any atomic check errors that occur after this will
9646 * not need a release. The plane state will be attached
9647 * to the stream, and therefore part of the atomic
9648 * state. It'll be released when the atomic state is
9649 * cleaned.
9650 */
9651 if (!dc_add_plane_to_context(
9652 dc,
9653 dm_new_crtc_state->stream,
9654 dc_new_plane_state,
9655 dm_state->context)) {
62f55537 9656
9e869063
LL		 9657 dc_plane_state_release(dc_new_plane_state);
9658 return -EINVAL;
9659 }
8c45c5db 9660
9e869063 9661 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 9662
214993e1
ML		 9663 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9664
9e869063
LL		 9665 /* Tell DC to do a full surface update every time there
9666 * is a plane change. Inefficient, but works for now.
9667 */
9668 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9669
9670 *lock_and_validation_needed = true;
62f55537 9671 }
e7b07cee
HW		 9672
9673
62f55537
AG		 9674 return ret;
9675}
a87fa993 9676
69cb5629
VZ		 9677static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9678 int *src_w, int *src_h)
9679{
9680 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9681 case DRM_MODE_ROTATE_90:
9682 case DRM_MODE_ROTATE_270:
9683 *src_w = plane_state->src_h >> 16;
9684 *src_h = plane_state->src_w >> 16;
9685 break;
9686 case DRM_MODE_ROTATE_0:
9687 case DRM_MODE_ROTATE_180:
9688 default:
9689 *src_w = plane_state->src_w >> 16;
9690 *src_h = plane_state->src_h >> 16;
9691 break;
9692 }
9693}
9694
12f4849a
SS		 9695static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9696 struct drm_crtc *crtc,
9697 struct drm_crtc_state *new_crtc_state)
9698{
d1bfbe8a
SS		 9699 struct drm_plane *cursor = crtc->cursor, *underlying;
9700 struct drm_plane_state *new_cursor_state, *new_underlying_state;
9701 int i;
9702 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
69cb5629
VZ		 9703 int cursor_src_w, cursor_src_h;
9704 int underlying_src_w, underlying_src_h;
12f4849a
SS		 9705
9706 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9707 * cursor per pipe but it's going to inherit the scaling and
9708 * positioning from the underlying pipe. Check the cursor plane's
d1bfbe8a 9709 * blending properties match the underlying planes'. */
12f4849a 9710
d1bfbe8a
SS		 9711 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9712 if (!new_cursor_state || !new_cursor_state->fb) {
12f4849a
SS		 9713 return 0;
9714 }
9715
69cb5629
VZ		 9716 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9717 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9718 cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
12f4849a 9719
d1bfbe8a
SS		 9720 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9721 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9722 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9723 continue;
12f4849a 9724
d1bfbe8a
SS		 9725 /* Ignore disabled planes */
9726 if (!new_underlying_state->fb)
9727 continue;
9728
69cb5629
VZ		 9729 dm_get_oriented_plane_size(new_underlying_state,
9730 &underlying_src_w, &underlying_src_h);
9731 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9732 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
d1bfbe8a
SS		 9733
9734 if (cursor_scale_w != underlying_scale_w ||
9735 cursor_scale_h != underlying_scale_h) {
9736 drm_dbg_atomic(crtc->dev,
9737 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9738 cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9739 return -EINVAL;
9740 }
9741
9742 /* If this plane covers the whole CRTC, no need to check planes underneath */
9743 if (new_underlying_state->crtc_x <= 0 &&
9744 new_underlying_state->crtc_y <= 0 &&
9745 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9746 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9747 break;
12f4849a
SS		 9748 }
9749
9750 return 0;
9751}
9752
44be939f
ML		 9753static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9754{
9755 struct drm_connector *connector;
128f8ed5 9756 struct drm_connector_state *conn_state, *old_conn_state;
44be939f
ML		 9757 struct amdgpu_dm_connector *aconnector = NULL;
9758 int i;
128f8ed5
RL		 9759 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9760 if (!conn_state->crtc)
9761 conn_state = old_conn_state;
9762
44be939f
ML		 9763 if (conn_state->crtc != crtc)
9764 continue;
9765
9766 aconnector = to_amdgpu_dm_connector(connector);
f0127cb1 9767 if (!aconnector->mst_output_port || !aconnector->mst_root)
44be939f
ML		 9768 aconnector = NULL;
9769 else
9770 break;
9771 }
9772
9773 if (!aconnector)
9774 return 0;
9775
f0127cb1 9776 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
44be939f
ML		 9777}
9778
b8592b48
LL		 9779/**
9780 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
c620e79b 9781 *
b8592b48
LL		 9782 * @dev: The DRM device
9783 * @state: The atomic state to commit
9784 *
9785 * Validate that the given atomic state is programmable by DC into hardware.
9786 * This involves constructing a &struct dc_state reflecting the new hardware
9787 * state we wish to commit, then querying DC to see if it is programmable. It's
9788 * important not to modify the existing DC state. Otherwise, atomic_check
9789 * may unexpectedly commit hardware changes.
9790 *
9791 * When validating the DC state, it's important that the right locks are
9792 * acquired. For full updates case which removes/adds/updates streams on one
9793 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9794 * that any such full update commit will wait for completion of any outstanding
f6d7c7fa 9795 * flip using DRMs synchronization events.
b8592b48
LL		 9796 *
9797 * Note that DM adds the affected connectors for all CRTCs in state, when that
9798 * might not seem necessary. This is because DC stream creation requires the
9799 * DC sink, which is tied to the DRM connector state. Cleaning this up should
9800 * be possible but non-trivial - a possible TODO item.
9801 *
9802 * Return: -Error code if validation failed.
9803 */
7578ecda
AD		 9804static int amdgpu_dm_atomic_check(struct drm_device *dev,
9805 struct drm_atomic_state *state)
62f55537 9806{
1348969a 9807 struct amdgpu_device *adev = drm_to_adev(dev);
eb3dc897 9808 struct dm_atomic_state *dm_state = NULL;
62f55537 9809 struct dc *dc = adev->dm.dc;
62f55537 9810 struct drm_connector *connector;
c2cea706 9811 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 9812 struct drm_crtc *crtc;
fc9e9920 9813 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 9814 struct drm_plane *plane;
9815 struct drm_plane_state *old_plane_state, *new_plane_state;
74a16675 9816 enum dc_status status;
1e88ad0a 9817 int ret, i;
62f55537 9818 bool lock_and_validation_needed = false;
35f33086 9819 bool is_top_most_overlay = true;
214993e1 9820 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
cdf657fc
DA		 9821 struct drm_dp_mst_topology_mgr *mgr;
9822 struct drm_dp_mst_topology_state *mst_state;
6513104b 9823 struct dsc_mst_fairness_vars vars[MAX_PIPES];
62f55537 9824
e8a98235 9825 trace_amdgpu_dm_atomic_check_begin(state);
c44a22b3 9826
62f55537 9827 ret = drm_atomic_helper_check_modeset(dev, state);
68ca1c3e
S		 9828 if (ret) {
9829 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
01e28f9c 9830 goto fail;
68ca1c3e 9831 }
62f55537 9832
c5892a10
SW		 9833 /* Check connector changes */
9834 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9835 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9836 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9837
9838 /* Skip connectors that are disabled or part of modeset already. */
c5892a10
SW		 9839 if (!new_con_state->crtc)
9840 continue;
9841
9842 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9843 if (IS_ERR(new_crtc_state)) {
68ca1c3e 9844 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
c5892a10
SW		 9845 ret = PTR_ERR(new_crtc_state);
9846 goto fail;
9847 }
9848
3c6d1aeb 9849 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9850 dm_old_con_state->scaling != dm_new_con_state->scaling)
c5892a10
SW		 9851 new_crtc_state->connectors_changed = true;
9852 }
9853
349a19b2 9854 if (dc_resource_is_dsc_encoding_supported(dc)) {
44be939f
ML		 9855 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9856 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9857 ret = add_affected_mst_dsc_crtcs(state, crtc);
68ca1c3e
S		 9858 if (ret) {
9859 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
44be939f 9860 goto fail;
68ca1c3e 9861 }
44be939f
ML		 9862 }
9863 }
9864 }
1e88ad0a 9865 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
886876ec
EB		 9866 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9867
1e88ad0a 9868 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 9869 !new_crtc_state->color_mgmt_changed &&
886876ec
EB		 9870 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9871 dm_old_crtc_state->dsc_force_changed == false)
1e88ad0a 9872 continue;
7bef1af3 9873
03fc4cf4 9874 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
68ca1c3e
S		 9875 if (ret) {
9876 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
03fc4cf4 9877 goto fail;
68ca1c3e 9878 }
03fc4cf4 9879
1e88ad0a
S		 9880 if (!new_crtc_state->enable)
9881 continue;
fc9e9920 9882
1e88ad0a 9883 ret = drm_atomic_add_affected_connectors(state, crtc);
68ca1c3e
S		 9884 if (ret) {
9885 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
706bc8c5 9886 goto fail;
68ca1c3e 9887 }
fc9e9920 9888
1e88ad0a 9889 ret = drm_atomic_add_affected_planes(state, crtc);
68ca1c3e
S		 9890 if (ret) {
9891 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
1e88ad0a 9892 goto fail;
68ca1c3e 9893 }
115a385c 9894
cbac53f7 9895 if (dm_old_crtc_state->dsc_force_changed)
115a385c 9896 new_crtc_state->mode_changed = true;
e7b07cee
HW		 9897 }
9898
2d9e6431
NK		 9899 /*
9900 * Add all primary and overlay planes on the CRTC to the state
9901 * whenever a plane is enabled to maintain correct z-ordering
9902 * and to enable fast surface updates.
9903 */
9904 drm_for_each_crtc(crtc, dev) {
9905 bool modified = false;
9906
9907 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9908 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9909 continue;
9910
9911 if (new_plane_state->crtc == crtc ||
9912 old_plane_state->crtc == crtc) {
9913 modified = true;
9914 break;
9915 }
9916 }
9917
9918 if (!modified)
9919 continue;
9920
9921 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9922 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9923 continue;
9924
9925 new_plane_state =
9926 drm_atomic_get_plane_state(state, plane);
9927
9928 if (IS_ERR(new_plane_state)) {
9929 ret = PTR_ERR(new_plane_state);
68ca1c3e 9930 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
2d9e6431
NK		 9931 goto fail;
9932 }
9933 }
9934 }
9935
22c42b0e
LL		 9936 /*
9937 * DC consults the zpos (layer_index in DC terminology) to determine the
9938 * hw plane on which to enable the hw cursor (see
9939 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9940 * atomic state, so call drm helper to normalize zpos.
9941 */
ac0bb08d
LL		 9942 ret = drm_atomic_normalize_zpos(dev, state);
9943 if (ret) {
9944 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
9945 goto fail;
9946 }
22c42b0e 9947
62f55537 9948 /* Remove exiting planes if they are modified */
9e869063
LL		 9949 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9950 ret = dm_update_plane_state(dc, state, plane,
9951 old_plane_state,
9952 new_plane_state,
9953 false,
35f33086
BL		 9954 &lock_and_validation_needed,
9955 &is_top_most_overlay);
68ca1c3e
S		 9956 if (ret) {
9957 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9e869063 9958 goto fail;
68ca1c3e 9959 }
62f55537
AG		 9960 }
9961
9962 /* Disable all crtcs which require disable */
4b9674e5
LL		 9963 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9964 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9965 old_crtc_state,
9966 new_crtc_state,
9967 false,
9968 &lock_and_validation_needed);
68ca1c3e
S		 9969 if (ret) {
9970 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
4b9674e5 9971 goto fail;
68ca1c3e 9972 }
62f55537
AG		 9973 }
9974
9975 /* Enable all crtcs which require enable */
4b9674e5
LL		 9976 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9977 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9978 old_crtc_state,
9979 new_crtc_state,
9980 true,
9981 &lock_and_validation_needed);
68ca1c3e
S		 9982 if (ret) {
9983 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
4b9674e5 9984 goto fail;
68ca1c3e 9985 }
62f55537
AG		 9986 }
9987
9988 /* Add new/modified planes */
9e869063
LL		 9989 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9990 ret = dm_update_plane_state(dc, state, plane,
9991 old_plane_state,
9992 new_plane_state,
9993 true,
35f33086
BL		 9994 &lock_and_validation_needed,
9995 &is_top_most_overlay);
68ca1c3e
S		 9996 if (ret) {
9997 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9e869063 9998 goto fail;
68ca1c3e 9999 }
62f55537
AG		 10000 }
10001
876fcc42 10002 if (dc_resource_is_dsc_encoding_supported(dc)) {
7cce4cd6
LP		 10003 ret = pre_validate_dsc(state, &dm_state, vars);
10004 if (ret != 0)
876fcc42 10005 goto fail;
876fcc42 10006 }
876fcc42 10007
b349f76e
ES		 10008 /* Run this here since we want to validate the streams we created */
10009 ret = drm_atomic_helper_check_planes(dev, state);
68ca1c3e
S		 10010 if (ret) {
10011 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
b349f76e 10012 goto fail;
68ca1c3e 10013 }
62f55537 10014
214993e1
ML		 10015 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10016 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10017 if (dm_new_crtc_state->mpo_requested)
10018 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10019 }
10020
12f4849a
SS		 10021 /* Check cursor planes scaling */
10022 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10023 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
68ca1c3e
S		 10024 if (ret) {
10025 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
12f4849a 10026 goto fail;
68ca1c3e 10027 }
12f4849a
SS		 10028 }
10029
43d10d30
NK		 10030 if (state->legacy_cursor_update) {
10031 /*
10032 * This is a fast cursor update coming from the plane update
10033 * helper, check if it can be done asynchronously for better
10034 * performance.
10035 */
10036 state->async_update =
10037 !drm_atomic_helper_async_check(dev, state);
10038
10039 /*
10040 * Skip the remaining global validation if this is an async
10041 * update. Cursor updates can be done without affecting
10042 * state or bandwidth calcs and this avoids the performance
10043 * penalty of locking the private state object and
10044 * allocating a new dc_state.
10045 */
10046 if (state->async_update)
10047 return 0;
10048 }
10049
ebdd27e1 10050 /* Check scaling and underscan changes*/
1f6010a9 10051 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 10052 * new stream into context w\o causing full reset. Need to
10053 * decide how to handle.
10054 */
c2cea706 10055 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 10056 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10057 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10058 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 10059
10060 /* Skip any modesets/resets */
0bc9706d
LSL		 10061 if (!acrtc || drm_atomic_crtc_needs_modeset(
10062 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 10063 continue;
10064
b830ebc9 10065 /* Skip any thing not scale or underscan changes */
54d76575 10066 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 10067 continue;
10068
10069 lock_and_validation_needed = true;
10070 }
10071
c689e1e3
LP		 10072 /* set the slot info for each mst_state based on the link encoding format */
10073 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10074 struct amdgpu_dm_connector *aconnector;
10075 struct drm_connector *connector;
10076 struct drm_connector_list_iter iter;
10077 u8 link_coding_cap;
10078
10079 drm_connector_list_iter_begin(dev, &iter);
10080 drm_for_each_connector_iter(connector, &iter) {
10081 if (connector->index == mst_state->mgr->conn_base_id) {
10082 aconnector = to_amdgpu_dm_connector(connector);
10083 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10084 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10085
10086 break;
10087 }
10088 }
10089 drm_connector_list_iter_end(&iter);
10090 }
c689e1e3 10091
f6d7c7fa
NK		 10092 /**
10093 * Streams and planes are reset when there are changes that affect
10094 * bandwidth. Anything that affects bandwidth needs to go through
10095 * DC global validation to ensure that the configuration can be applied
10096 * to hardware.
10097 *
10098 * We have to currently stall out here in atomic_check for outstanding
10099 * commits to finish in this case because our IRQ handlers reference
10100 * DRM state directly - we can end up disabling interrupts too early
10101 * if we don't.
10102 *
10103 * TODO: Remove this stall and drop DM state private objects.
a87fa993 10104 */
f6d7c7fa 10105 if (lock_and_validation_needed) {
eb3dc897 10106 ret = dm_atomic_get_state(state, &dm_state);
68ca1c3e
S		 10107 if (ret) {
10108 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
eb3dc897 10109 goto fail;
68ca1c3e 10110 }
e7b07cee
HW		 10111
10112 ret = do_aquire_global_lock(dev, state);
68ca1c3e
S		 10113 if (ret) {
10114 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
e7b07cee 10115 goto fail;
68ca1c3e 10116 }
1dc90497 10117
7cce4cd6
LP		 10118 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10119 if (ret) {
68ca1c3e 10120 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
8c20a1ed 10121 goto fail;
68ca1c3e 10122 }
8c20a1ed 10123
6513104b 10124 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
68ca1c3e
S		 10125 if (ret) {
10126 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
29b9ba74 10127 goto fail;
68ca1c3e 10128 }
29b9ba74 10129
ded58c7b
ZL		 10130 /*
10131 * Perform validation of MST topology in the state:
10132 * We need to perform MST atomic check before calling
10133 * dc_validate_global_state(), or there is a chance
10134 * to get stuck in an infinite loop and hang eventually.
10135 */
10136 ret = drm_dp_mst_atomic_check(state);
68ca1c3e
S		 10137 if (ret) {
10138 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
ded58c7b 10139 goto fail;
68ca1c3e 10140 }
85fb8bb9 10141 status = dc_validate_global_state(dc, dm_state->context, true);
74a16675 10142 if (status != DC_OK) {
68ca1c3e 10143 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
74a16675 10144 dc_status_to_str(status), status);
e7b07cee
HW		 10145 ret = -EINVAL;
10146 goto fail;
10147 }
bd200d19 10148 } else {
674e78ac 10149 /*
bd200d19
NK		 10150 * The commit is a fast update. Fast updates shouldn't change
10151 * the DC context, affect global validation, and can have their
10152 * commit work done in parallel with other commits not touching
10153 * the same resource. If we have a new DC context as part of
10154 * the DM atomic state from validation we need to free it and
10155 * retain the existing one instead.
fde9f39a
MR		 10156 *
10157 * Furthermore, since the DM atomic state only contains the DC
10158 * context and can safely be annulled, we can free the state
10159 * and clear the associated private object now to free
10160 * some memory and avoid a possible use-after-free later.
674e78ac 10161 */
bd200d19 10162
fde9f39a
MR		 10163 for (i = 0; i < state->num_private_objs; i++) {
10164 struct drm_private_obj *obj = state->private_objs[i].ptr;
bd200d19 10165
fde9f39a
MR		 10166 if (obj->funcs == adev->dm.atomic_obj.funcs) {
10167 int j = state->num_private_objs-1;
bd200d19 10168
fde9f39a
MR		 10169 dm_atomic_destroy_state(obj,
10170 state->private_objs[i].state);
10171
10172 /* If i is not at the end of the array then the
10173 * last element needs to be moved to where i was
10174 * before the array can safely be truncated.
10175 */
10176 if (i != j)
10177 state->private_objs[i] =
10178 state->private_objs[j];
bd200d19 10179
fde9f39a
MR		 10180 state->private_objs[j].ptr = NULL;
10181 state->private_objs[j].state = NULL;
10182 state->private_objs[j].old_state = NULL;
10183 state->private_objs[j].new_state = NULL;
10184
10185 state->num_private_objs = j;
10186 break;
10187 }
bd200d19 10188 }
e7b07cee
HW		 10189 }
10190
caff0e66
NK		 10191 /* Store the overall update type for use later in atomic check. */
10192 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10193 struct dm_crtc_state *dm_new_crtc_state =
10194 to_dm_crtc_state(new_crtc_state);
10195
f6d7c7fa
NK		 10196 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10197 UPDATE_TYPE_FULL :
10198 UPDATE_TYPE_FAST;
e7b07cee
HW		 10199 }
10200
10201 /* Must be success */
10202 WARN_ON(ret);
e8a98235
RS		 10203
10204 trace_amdgpu_dm_atomic_check_finish(state, ret);
10205
e7b07cee
HW		 10206 return ret;
10207
10208fail:
10209 if (ret == -EDEADLK)
01e28f9c 10210 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 10211 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 10212 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 10213 else
01e28f9c 10214 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee 10215
e8a98235
RS		 10216 trace_amdgpu_dm_atomic_check_finish(state, ret);
10217
e7b07cee
HW		 10218 return ret;
10219}
10220
3ee6b26b
AD		 10221static bool is_dp_capable_without_timing_msa(struct dc *dc,
10222 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee 10223{
ae67558b 10224 u8 dpcd_data;
e7b07cee
HW		 10225 bool capable = false;
10226
c84dec2f 10227 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 10228 dm_helpers_dp_read_dpcd(
10229 NULL,
c84dec2f 10230 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 10231 DP_DOWN_STREAM_PORT_COUNT,
10232 &dpcd_data,
10233 sizeof(dpcd_data))) {
10234 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10235 }
10236
10237 return capable;
10238}
f9b4f20c 10239
46db138d
SW		 10240static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10241 unsigned int offset,
10242 unsigned int total_length,
ae67558b 10243 u8 *data,
46db138d
SW		 10244 unsigned int length,
10245 struct amdgpu_hdmi_vsdb_info *vsdb)
10246{
10247 bool res;
10248 union dmub_rb_cmd cmd;
10249 struct dmub_cmd_send_edid_cea *input;
10250 struct dmub_cmd_edid_cea_output *output;
10251
10252 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10253 return false;
10254
10255 memset(&cmd, 0, sizeof(cmd));
10256
10257 input = &cmd.edid_cea.data.input;
10258
10259 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10260 cmd.edid_cea.header.sub_type = 0;
10261 cmd.edid_cea.header.payload_bytes =
10262 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10263 input->offset = offset;
10264 input->length = length;
eb9e59eb 10265 input->cea_total_length = total_length;
46db138d
SW		 10266 memcpy(input->payload, data, length);
10267
10268 res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10269 if (!res) {
10270 DRM_ERROR("EDID CEA parser failed\n");
10271 return false;
10272 }
10273
10274 output = &cmd.edid_cea.data.output;
10275
10276 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10277 if (!output->ack.success) {
10278 DRM_ERROR("EDID CEA ack failed at offset %d\n",
10279 output->ack.offset);
10280 }
10281 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10282 if (!output->amd_vsdb.vsdb_found)
10283 return false;
10284
10285 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10286 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10287 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10288 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10289 } else {
b76a8062 10290 DRM_WARN("Unknown EDID CEA parser results\n");
46db138d
SW		 10291 return false;
10292 }
10293
10294 return true;
10295}
10296
10297static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
ae67558b 10298 u8 *edid_ext, int len,
f9b4f20c
SW		 10299 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10300{
10301 int i;
f9b4f20c
SW		 10302
10303 /* send extension block to DMCU for parsing */
10304 for (i = 0; i < len; i += 8) {
10305 bool res;
10306 int offset;
10307
10308 /* send 8 bytes a time */
46db138d 10309 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
f9b4f20c
SW		 10310 return false;
10311
10312 if (i+8 == len) {
10313 /* EDID block sent completed, expect result */
10314 int version, min_rate, max_rate;
10315
46db138d 10316 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
f9b4f20c
SW		 10317 if (res) {
10318 /* amd vsdb found */
10319 vsdb_info->freesync_supported = 1;
10320 vsdb_info->amd_vsdb_version = version;
10321 vsdb_info->min_refresh_rate_hz = min_rate;
10322 vsdb_info->max_refresh_rate_hz = max_rate;
10323 return true;
10324 }
10325 /* not amd vsdb */
10326 return false;
10327 }
10328
10329 /* check for ack*/
46db138d 10330 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
f9b4f20c
SW		 10331 if (!res)
10332 return false;
10333 }
10334
10335 return false;
10336}
10337
46db138d 10338static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
ae67558b 10339 u8 *edid_ext, int len,
46db138d
SW		 10340 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10341{
10342 int i;
10343
10344 /* send extension block to DMCU for parsing */
10345 for (i = 0; i < len; i += 8) {
10346 /* send 8 bytes a time */
10347 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10348 return false;
10349 }
10350
10351 return vsdb_info->freesync_supported;
10352}
10353
10354static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
ae67558b 10355 u8 *edid_ext, int len,
46db138d
SW		 10356 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10357{
10358 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
53f4da73 10359 bool ret;
46db138d 10360
53f4da73 10361 mutex_lock(&adev->dm.dc_lock);
46db138d 10362 if (adev->dm.dmub_srv)
53f4da73 10363 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
46db138d 10364 else
53f4da73
SW		 10365 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10366 mutex_unlock(&adev->dm.dc_lock);
10367 return ret;
46db138d
SW		 10368}
10369
7c7dd774 10370static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
f9b4f20c
SW		 10371 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10372{
ae67558b 10373 u8 *edid_ext = NULL;
f9b4f20c
SW		 10374 int i;
10375 bool valid_vsdb_found = false;
10376
10377 /*----- drm_find_cea_extension() -----*/
10378 /* No EDID or EDID extensions */
10379 if (edid == NULL || edid->extensions == 0)
7c7dd774 10380 return -ENODEV;
f9b4f20c
SW		 10381
10382 /* Find CEA extension */
10383 for (i = 0; i < edid->extensions; i++) {
10384 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10385 if (edid_ext[0] == CEA_EXT)
10386 break;
10387 }
10388
10389 if (i == edid->extensions)
7c7dd774 10390 return -ENODEV;
f9b4f20c
SW		 10391
10392 /*----- cea_db_offsets() -----*/
10393 if (edid_ext[0] != CEA_EXT)
7c7dd774 10394 return -ENODEV;
f9b4f20c
SW		 10395
10396 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
7c7dd774
AB		 10397
10398 return valid_vsdb_found ? i : -ENODEV;
f9b4f20c
SW		 10399}
10400
c620e79b
RS		 10401/**
10402 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10403 *
41ee1f18
AD		 10404 * @connector: Connector to query.
10405 * @edid: EDID from monitor
c620e79b
RS		 10406 *
10407 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10408 * track of some of the display information in the internal data struct used by
10409 * amdgpu_dm. This function checks which type of connector we need to set the
10410 * FreeSync parameters.
10411 */
98e6436d 10412void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
c620e79b 10413 struct edid *edid)
e7b07cee 10414{
eb0709ba 10415 int i = 0;
e7b07cee
HW		 10416 struct detailed_timing *timing;
10417 struct detailed_non_pixel *data;
10418 struct detailed_data_monitor_range *range;
c84dec2f
HW		 10419 struct amdgpu_dm_connector *amdgpu_dm_connector =
10420 to_amdgpu_dm_connector(connector);
bb47de73 10421 struct dm_connector_state *dm_con_state = NULL;
9ad54467 10422 struct dc_sink *sink;
e7b07cee
HW		 10423
10424 struct drm_device *dev = connector->dev;
1348969a 10425 struct amdgpu_device *adev = drm_to_adev(dev);
f9b4f20c 10426 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
c620e79b 10427 bool freesync_capable = false;
5b49da02 10428 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
b830ebc9 10429
8218d7f1
HW		 10430 if (!connector->state) {
10431 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 10432 goto update;
8218d7f1
HW		 10433 }
10434
9b2fdc33
AP		 10435 sink = amdgpu_dm_connector->dc_sink ?
10436 amdgpu_dm_connector->dc_sink :
10437 amdgpu_dm_connector->dc_em_sink;
10438
10439 if (!edid || !sink) {
98e6436d
AK		 10440 dm_con_state = to_dm_connector_state(connector->state);
10441
10442 amdgpu_dm_connector->min_vfreq = 0;
10443 amdgpu_dm_connector->max_vfreq = 0;
10444 amdgpu_dm_connector->pixel_clock_mhz = 0;
9b2fdc33
AP		 10445 connector->display_info.monitor_range.min_vfreq = 0;
10446 connector->display_info.monitor_range.max_vfreq = 0;
10447 freesync_capable = false;
98e6436d 10448
bb47de73 10449 goto update;
98e6436d
AK		 10450 }
10451
8218d7f1
HW		 10452 dm_con_state = to_dm_connector_state(connector->state);
10453
e7b07cee 10454 if (!adev->dm.freesync_module)
bb47de73 10455 goto update;
f9b4f20c 10456
9b2fdc33
AP		 10457 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10458 || sink->sink_signal == SIGNAL_TYPE_EDP) {
f9b4f20c
SW		 10459 bool edid_check_required = false;
10460
10461 if (edid) {
e7b07cee
HW		 10462 edid_check_required = is_dp_capable_without_timing_msa(
10463 adev->dm.dc,
c84dec2f 10464 amdgpu_dm_connector);
e7b07cee 10465 }
e7b07cee 10466
f9b4f20c
SW		 10467 if (edid_check_required == true && (edid->version > 1 ||
10468 (edid->version == 1 && edid->revision > 1))) {
10469 for (i = 0; i < 4; i++) {
e7b07cee 10470
f9b4f20c
SW		 10471 timing = &edid->detailed_timings[i];
10472 data = &timing->data.other_data;
10473 range = &data->data.range;
10474 /*
10475 * Check if monitor has continuous frequency mode
10476 */
10477 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10478 continue;
10479 /*
10480 * Check for flag range limits only. If flag == 1 then
10481 * no additional timing information provided.
10482 * Default GTF, GTF Secondary curve and CVT are not
10483 * supported
10484 */
10485 if (range->flags != 1)
10486 continue;
a0ffc3fd 10487
f9b4f20c
SW		 10488 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10489 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10490 amdgpu_dm_connector->pixel_clock_mhz =
10491 range->pixel_clock_mhz * 10;
a0ffc3fd 10492
f9b4f20c
SW		 10493 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10494 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
e7b07cee 10495
f9b4f20c
SW		 10496 break;
10497 }
98e6436d 10498
f9b4f20c
SW		 10499 if (amdgpu_dm_connector->max_vfreq -
10500 amdgpu_dm_connector->min_vfreq > 10) {
98e6436d 10501
f9b4f20c
SW		 10502 freesync_capable = true;
10503 }
10504 }
9b2fdc33 10505 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
7c7dd774
AB		 10506 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10507 if (i >= 0 && vsdb_info.freesync_supported) {
f9b4f20c
SW		 10508 timing = &edid->detailed_timings[i];
10509 data = &timing->data.other_data;
10510
10511 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
5b49da02
SJK		 10512 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10513 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10514 freesync_capable = true;
10515
10516 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10517 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10518 }
10519 }
10520
10521 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10522
10523 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10524 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10525 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10526
10527 amdgpu_dm_connector->pack_sdp_v1_3 = true;
10528 amdgpu_dm_connector->as_type = as_type;
10529 amdgpu_dm_connector->vsdb_info = vsdb_info;
10530
10531 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
f9b4f20c
SW		 10532 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10533 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10534 freesync_capable = true;
10535
10536 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10537 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
e7b07cee
HW		 10538 }
10539 }
bb47de73
NK		 10540
10541update:
10542 if (dm_con_state)
10543 dm_con_state->freesync_capable = freesync_capable;
10544
10545 if (connector->vrr_capable_property)
10546 drm_connector_set_vrr_capable_property(connector,
10547 freesync_capable);
e7b07cee
HW		 10548}
10549
3d4e52d0
VL		 10550void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10551{
1348969a 10552 struct amdgpu_device *adev = drm_to_adev(dev);
3d4e52d0
VL		 10553 struct dc *dc = adev->dm.dc;
10554 int i;
10555
10556 mutex_lock(&adev->dm.dc_lock);
10557 if (dc->current_state) {
10558 for (i = 0; i < dc->current_state->stream_count; ++i)
10559 dc->current_state->streams[i]
10560 ->triggered_crtc_reset.enabled =
10561 adev->dm.force_timing_sync;
10562
10563 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10564 dc_trigger_sync(dc, dc->current_state);
10565 }
10566 mutex_unlock(&adev->dm.dc_lock);
10567}
9d83722d
RS		 10568
10569void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
ae67558b 10570 u32 value, const char *func_name)
9d83722d
RS		 10571{
10572#ifdef DM_CHECK_ADDR_0
10573 if (address == 0) {
10574 DC_ERR("invalid register write. address = 0");
10575 return;
10576 }
10577#endif
10578 cgs_write_register(ctx->cgs_device, address, value);
10579 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10580}
10581
10582uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10583 const char *func_name)
10584{
ae67558b 10585 u32 value;
9d83722d
RS		 10586#ifdef DM_CHECK_ADDR_0
10587 if (address == 0) {
10588 DC_ERR("invalid register read; address = 0\n");
10589 return 0;
10590 }
10591#endif
10592
10593 if (ctx->dmub_srv &&
10594 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10595 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10596 ASSERT(false);
10597 return 0;
10598 }
10599
10600 value = cgs_read_register(ctx->cgs_device, address);
10601
10602 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10603
10604 return value;
10605}
81927e28 10606
ead08b95
SW		 10607int amdgpu_dm_process_dmub_aux_transfer_sync(
10608 struct dc_context *ctx,
10609 unsigned int link_index,
10610 struct aux_payload *payload,
10611 enum aux_return_code_type *operation_result)
88f52b1f
JS		 10612{
10613 struct amdgpu_device *adev = ctx->driver_context;
88f52b1f 10614 struct dmub_notification *p_notify = adev->dm.dmub_notify;
ead08b95 10615 int ret = -1;
88f52b1f 10616
ead08b95
SW		 10617 mutex_lock(&adev->dm.dpia_aux_lock);
10618 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10619 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10620 goto out;
10621 }
10622
10623 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10624 DRM_ERROR("wait_for_completion_timeout timeout!");
10625 *operation_result = AUX_RET_ERROR_TIMEOUT;
10626 goto out;
10627 }
10628
10629 if (p_notify->result != AUX_RET_SUCCESS) {
10630 /*
10631 * Transient states before tunneling is enabled could
10632 * lead to this error. We can ignore this for now.
10633 */
10634 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10635 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10636 payload->address, payload->length,
10637 p_notify->result);
88f52b1f 10638 }
ead08b95
SW		 10639 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10640 goto out;
10641 }
10642
10643
10644 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10645 if (!payload->write && p_notify->aux_reply.length &&
10646 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10647
10648 if (payload->length != p_notify->aux_reply.length) {
10649 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10650 p_notify->aux_reply.length,
10651 payload->address, payload->length);
10652 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10653 goto out;
88f52b1f 10654 }
ead08b95
SW		 10655
10656 memcpy(payload->data, p_notify->aux_reply.data,
10657 p_notify->aux_reply.length);
88f52b1f
JS		 10658 }
10659
ead08b95
SW		 10660 /* success */
10661 ret = p_notify->aux_reply.length;
10662 *operation_result = p_notify->result;
10663out:
0cf8307a 10664 reinit_completion(&adev->dm.dmub_aux_transfer_done);
ead08b95
SW		 10665 mutex_unlock(&adev->dm.dpia_aux_lock);
10666 return ret;
88f52b1f
JS		 10667}
10668
ead08b95
SW		 10669int amdgpu_dm_process_dmub_set_config_sync(
10670 struct dc_context *ctx,
10671 unsigned int link_index,
10672 struct set_config_cmd_payload *payload,
10673 enum set_config_status *operation_result)
81927e28
JS		 10674{
10675 struct amdgpu_device *adev = ctx->driver_context;
ead08b95
SW		 10676 bool is_cmd_complete;
10677 int ret;
81927e28 10678
ead08b95
SW		 10679 mutex_lock(&adev->dm.dpia_aux_lock);
10680 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10681 link_index, payload, adev->dm.dmub_notify);
88f52b1f 10682
ead08b95
SW		 10683 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10684 ret = 0;
10685 *operation_result = adev->dm.dmub_notify->sc_status;
10686 } else {
9e3a50d2 10687 DRM_ERROR("wait_for_completion_timeout timeout!");
ead08b95
SW		 10688 ret = -1;
10689 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
81927e28
JS		 10690 }
10691
0cf8307a
SW		 10692 if (!is_cmd_complete)
10693 reinit_completion(&adev->dm.dmub_aux_transfer_done);
ead08b95
SW		 10694 mutex_unlock(&adev->dm.dpia_aux_lock);
10695 return ret;
81927e28 10696}
1edf5ae1
ZL		 10697
10698/*
10699 * Check whether seamless boot is supported.
10700 *
10701 * So far we only support seamless boot on CHIP_VANGOGH.
10702 * If everything goes well, we may consider expanding
10703 * seamless boot to other ASICs.
10704 */
10705bool check_seamless_boot_capability(struct amdgpu_device *adev)
10706{
20875141
PY		 10707 switch (adev->ip_versions[DCE_HWIP][0]) {
10708 case IP_VERSION(3, 0, 1):
1edf5ae1
ZL		 10709 if (!adev->mman.keep_stolen_vga_memory)
10710 return true;
10711 break;
10712 default:
10713 break;
10714 }
10715
10716 return false;
10717}
Linux 6.x block layer and io_uring tree(s)