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drm/amd/powerplay: clear the swSMU code layer
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
1dc90497 31#include "dc/inc/core_types.h"
a7669aff 32#include "dal_asic_id.h"
4562236b
HW		 33
34#include "vid.h"
35#include "amdgpu.h"
a49dcb88 36#include "amdgpu_display.h"
a94d5569 37#include "amdgpu_ucode.h"
4562236b
HW		 38#include "atom.h"
39#include "amdgpu_dm.h"
52704fca
BL		 40#ifdef CONFIG_DRM_AMD_DC_HDCP
41#include "amdgpu_dm_hdcp.h"
42#endif
e7b07cee 43#include "amdgpu_pm.h"
4562236b
HW		 44
45#include "amd_shared.h"
46#include "amdgpu_dm_irq.h"
47#include "dm_helpers.h"
e7b07cee 48#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 49#if defined(CONFIG_DEBUG_FS)
50#include "amdgpu_dm_debugfs.h"
51#endif
4562236b
HW		 52
53#include "ivsrcid/ivsrcid_vislands30.h"
54
55#include <linux/module.h>
56#include <linux/moduleparam.h>
57#include <linux/version.h>
e7b07cee 58#include <linux/types.h>
97028037 59#include <linux/pm_runtime.h>
09d21852 60#include <linux/pci.h>
a94d5569 61#include <linux/firmware.h>
6ce8f316 62#include <linux/component.h>
4562236b
HW		 63
64#include <drm/drm_atomic.h>
674e78ac 65#include <drm/drm_atomic_uapi.h>
4562236b
HW		 66#include <drm/drm_atomic_helper.h>
67#include <drm/drm_dp_mst_helper.h>
e7b07cee 68#include <drm/drm_fb_helper.h>
09d21852 69#include <drm/drm_fourcc.h>
e7b07cee 70#include <drm/drm_edid.h>
09d21852 71#include <drm/drm_vblank.h>
6ce8f316 72#include <drm/drm_audio_component.h>
0c8620d6 73#include <drm/drm_hdcp.h>
4562236b 74
ff5ef992 75#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
5527cd06 76#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
ff5ef992 77
ad941f7a
FX		 78#include "dcn/dcn_1_0_offset.h"
79#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 80#include "soc15_hw_ip.h"
81#include "vega10_ip_offset.h"
ff5ef992
AD		 82
83#include "soc15_common.h"
84#endif
85
e7b07cee 86#include "modules/inc/mod_freesync.h"
bbf854dc 87#include "modules/power/power_helpers.h"
ecd0136b 88#include "modules/inc/mod_info_packet.h"
e7b07cee 89
a94d5569
DF		 90#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
91MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 92
b8592b48
LL		 93/**
94 * DOC: overview
95 *
96 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
97 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
98 * requests into DC requests, and DC responses into DRM responses.
99 *
100 * The root control structure is &struct amdgpu_display_manager.
101 */
102
7578ecda
AD		 103/* basic init/fini API */
104static int amdgpu_dm_init(struct amdgpu_device *adev);
105static void amdgpu_dm_fini(struct amdgpu_device *adev);
106
1f6010a9
DF		 107/*
108 * initializes drm_device display related structures, based on the information
7578ecda
AD		 109 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
110 * drm_encoder, drm_mode_config
111 *
112 * Returns 0 on success
113 */
114static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
115/* removes and deallocates the drm structures, created by the above function */
116static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
117
118static void
119amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
120
121static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 122 struct drm_plane *plane,
cc1fec57
NK		 123 unsigned long possible_crtcs,
124 const struct dc_plane_cap *plane_cap);
7578ecda
AD		 125static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
126 struct drm_plane *plane,
127 uint32_t link_index);
128static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
129 struct amdgpu_dm_connector *amdgpu_dm_connector,
130 uint32_t link_index,
131 struct amdgpu_encoder *amdgpu_encoder);
132static int amdgpu_dm_encoder_init(struct drm_device *dev,
133 struct amdgpu_encoder *aencoder,
134 uint32_t link_index);
135
136static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
137
138static int amdgpu_dm_atomic_commit(struct drm_device *dev,
139 struct drm_atomic_state *state,
140 bool nonblock);
141
142static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
143
144static int amdgpu_dm_atomic_check(struct drm_device *dev,
145 struct drm_atomic_state *state);
146
674e78ac
NK		 147static void handle_cursor_update(struct drm_plane *plane,
148 struct drm_plane_state *old_plane_state);
7578ecda 149
8c322309
RL		 150static void amdgpu_dm_set_psr_caps(struct dc_link *link);
151static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
152static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
153static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
154
155
4562236b
HW		 156/*
157 * dm_vblank_get_counter
158 *
159 * @brief
160 * Get counter for number of vertical blanks
161 *
162 * @param
163 * struct amdgpu_device *adev - [in] desired amdgpu device
164 * int disp_idx - [in] which CRTC to get the counter from
165 *
166 * @return
167 * Counter for vertical blanks
168 */
169static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
170{
171 if (crtc >= adev->mode_info.num_crtc)
172 return 0;
173 else {
174 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 175 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
176 acrtc->base.state);
4562236b 177
da5c47f6
AG		 178
179 if (acrtc_state->stream == NULL) {
0971c40e
HW		 180 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
181 crtc);
4562236b
HW		 182 return 0;
183 }
184
da5c47f6 185 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 186 }
187}
188
189static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 190 u32 *vbl, u32 *position)
4562236b 191{
81c50963
ST		 192 uint32_t v_blank_start, v_blank_end, h_position, v_position;
193
4562236b
HW		 194 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
195 return -EINVAL;
196 else {
197 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 198 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
199 acrtc->base.state);
4562236b 200
da5c47f6 201 if (acrtc_state->stream == NULL) {
0971c40e
HW		 202 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
203 crtc);
4562236b
HW		 204 return 0;
205 }
206
81c50963
ST		 207 /*
208 * TODO rework base driver to use values directly.
209 * for now parse it back into reg-format
210 */
da5c47f6 211 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 212 &v_blank_start,
213 &v_blank_end,
214 &h_position,
215 &v_position);
216
e806208d
AG		 217 *position = v_position | (h_position << 16);
218 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 219 }
220
221 return 0;
222}
223
224static bool dm_is_idle(void *handle)
225{
226 /* XXX todo */
227 return true;
228}
229
230static int dm_wait_for_idle(void *handle)
231{
232 /* XXX todo */
233 return 0;
234}
235
236static bool dm_check_soft_reset(void *handle)
237{
238 return false;
239}
240
241static int dm_soft_reset(void *handle)
242{
243 /* XXX todo */
244 return 0;
245}
246
3ee6b26b
AD		 247static struct amdgpu_crtc *
248get_crtc_by_otg_inst(struct amdgpu_device *adev,
249 int otg_inst)
4562236b
HW		 250{
251 struct drm_device *dev = adev->ddev;
252 struct drm_crtc *crtc;
253 struct amdgpu_crtc *amdgpu_crtc;
254
4562236b
HW		 255 if (otg_inst == -1) {
256 WARN_ON(1);
257 return adev->mode_info.crtcs[0];
258 }
259
260 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
261 amdgpu_crtc = to_amdgpu_crtc(crtc);
262
263 if (amdgpu_crtc->otg_inst == otg_inst)
264 return amdgpu_crtc;
265 }
266
267 return NULL;
268}
269
66b0c973
MK		 270static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
271{
272 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
273 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
274}
275
b8e8c934
HW		 276/**
277 * dm_pflip_high_irq() - Handle pageflip interrupt
278 * @interrupt_params: ignored
279 *
280 * Handles the pageflip interrupt by notifying all interested parties
281 * that the pageflip has been completed.
282 */
4562236b
HW		 283static void dm_pflip_high_irq(void *interrupt_params)
284{
4562236b
HW		 285 struct amdgpu_crtc *amdgpu_crtc;
286 struct common_irq_params *irq_params = interrupt_params;
287 struct amdgpu_device *adev = irq_params->adev;
288 unsigned long flags;
71bbe51a
MK		 289 struct drm_pending_vblank_event *e;
290 struct dm_crtc_state *acrtc_state;
291 uint32_t vpos, hpos, v_blank_start, v_blank_end;
292 bool vrr_active;
4562236b
HW		 293
294 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
295
296 /* IRQ could occur when in initial stage */
1f6010a9 297 /* TODO work and BO cleanup */
4562236b
HW		 298 if (amdgpu_crtc == NULL) {
299 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
300 return;
301 }
302
303 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 304
305 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
306 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
307 amdgpu_crtc->pflip_status,
308 AMDGPU_FLIP_SUBMITTED,
309 amdgpu_crtc->crtc_id,
310 amdgpu_crtc);
311 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
312 return;
313 }
314
71bbe51a
MK		 315 /* page flip completed. */
316 e = amdgpu_crtc->event;
317 amdgpu_crtc->event = NULL;
4562236b 318
71bbe51a
MK		 319 if (!e)
320 WARN_ON(1);
1159898a 321
71bbe51a
MK		 322 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
323 vrr_active = amdgpu_dm_vrr_active(acrtc_state);
324
325 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
326 if (!vrr_active ||
327 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
328 &v_blank_end, &hpos, &vpos) ||
329 (vpos < v_blank_start)) {
330 /* Update to correct count and vblank timestamp if racing with
331 * vblank irq. This also updates to the correct vblank timestamp
332 * even in VRR mode, as scanout is past the front-porch atm.
333 */
334 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
1159898a 335
71bbe51a
MK		 336 /* Wake up userspace by sending the pageflip event with proper
337 * count and timestamp of vblank of flip completion.
338 */
339 if (e) {
340 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
341
342 /* Event sent, so done with vblank for this flip */
343 drm_crtc_vblank_put(&amdgpu_crtc->base);
344 }
345 } else if (e) {
346 /* VRR active and inside front-porch: vblank count and
347 * timestamp for pageflip event will only be up to date after
348 * drm_crtc_handle_vblank() has been executed from late vblank
349 * irq handler after start of back-porch (vline 0). We queue the
350 * pageflip event for send-out by drm_crtc_handle_vblank() with
351 * updated timestamp and count, once it runs after us.
352 *
353 * We need to open-code this instead of using the helper
354 * drm_crtc_arm_vblank_event(), as that helper would
355 * call drm_crtc_accurate_vblank_count(), which we must
356 * not call in VRR mode while we are in front-porch!
357 */
358
359 /* sequence will be replaced by real count during send-out. */
360 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
361 e->pipe = amdgpu_crtc->crtc_id;
362
363 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
364 e = NULL;
365 }
4562236b 366
fdd1fe57
MK		 367 /* Keep track of vblank of this flip for flip throttling. We use the
368 * cooked hw counter, as that one incremented at start of this vblank
369 * of pageflip completion, so last_flip_vblank is the forbidden count
370 * for queueing new pageflips if vsync + VRR is enabled.
371 */
372 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
373 amdgpu_crtc->crtc_id);
374
54f5499a 375 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 376 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
377
71bbe51a
MK		 378 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
379 amdgpu_crtc->crtc_id, amdgpu_crtc,
380 vrr_active, (int) !e);
4562236b
HW		 381}
382
d2574c33
MK		 383static void dm_vupdate_high_irq(void *interrupt_params)
384{
385 struct common_irq_params *irq_params = interrupt_params;
386 struct amdgpu_device *adev = irq_params->adev;
387 struct amdgpu_crtc *acrtc;
388 struct dm_crtc_state *acrtc_state;
09aef2c4 389 unsigned long flags;
d2574c33
MK		 390
391 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
392
393 if (acrtc) {
394 acrtc_state = to_dm_crtc_state(acrtc->base.state);
395
396 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
397 amdgpu_dm_vrr_active(acrtc_state));
398
399 /* Core vblank handling is done here after end of front-porch in
400 * vrr mode, as vblank timestamping will give valid results
401 * while now done after front-porch. This will also deliver
402 * page-flip completion events that have been queued to us
403 * if a pageflip happened inside front-porch.
404 */
09aef2c4 405 if (amdgpu_dm_vrr_active(acrtc_state)) {
d2574c33 406 drm_crtc_handle_vblank(&acrtc->base);
09aef2c4
MK		 407
408 /* BTR processing for pre-DCE12 ASICs */
409 if (acrtc_state->stream &&
410 adev->family < AMDGPU_FAMILY_AI) {
411 spin_lock_irqsave(&adev->ddev->event_lock, flags);
412 mod_freesync_handle_v_update(
413 adev->dm.freesync_module,
414 acrtc_state->stream,
415 &acrtc_state->vrr_params);
416
417 dc_stream_adjust_vmin_vmax(
418 adev->dm.dc,
419 acrtc_state->stream,
420 &acrtc_state->vrr_params.adjust);
421 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
422 }
423 }
d2574c33
MK		 424 }
425}
426
b8e8c934
HW		 427/**
428 * dm_crtc_high_irq() - Handles CRTC interrupt
429 * @interrupt_params: ignored
430 *
431 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
432 * event handler.
433 */
4562236b
HW		 434static void dm_crtc_high_irq(void *interrupt_params)
435{
436 struct common_irq_params *irq_params = interrupt_params;
437 struct amdgpu_device *adev = irq_params->adev;
4562236b 438 struct amdgpu_crtc *acrtc;
180db303 439 struct dm_crtc_state *acrtc_state;
09aef2c4 440 unsigned long flags;
4562236b 441
b57de80a 442 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 443
e5d0170e 444 if (acrtc) {
180db303
NK		 445 acrtc_state = to_dm_crtc_state(acrtc->base.state);
446
d2574c33
MK		 447 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
448 amdgpu_dm_vrr_active(acrtc_state));
449
450 /* Core vblank handling at start of front-porch is only possible
451 * in non-vrr mode, as only there vblank timestamping will give
452 * valid results while done in front-porch. Otherwise defer it
453 * to dm_vupdate_high_irq after end of front-porch.
454 */
455 if (!amdgpu_dm_vrr_active(acrtc_state))
456 drm_crtc_handle_vblank(&acrtc->base);
457
458 /* Following stuff must happen at start of vblank, for crc
459 * computation and below-the-range btr support in vrr mode.
460 */
461 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
462
09aef2c4 463 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
180db303
NK		 464 acrtc_state->vrr_params.supported &&
465 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
09aef2c4 466 spin_lock_irqsave(&adev->ddev->event_lock, flags);
180db303
NK		 467 mod_freesync_handle_v_update(
468 adev->dm.freesync_module,
469 acrtc_state->stream,
470 &acrtc_state->vrr_params);
471
472 dc_stream_adjust_vmin_vmax(
473 adev->dm.dc,
474 acrtc_state->stream,
475 &acrtc_state->vrr_params.adjust);
09aef2c4 476 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
180db303 477 }
e5d0170e 478 }
4562236b
HW		 479}
480
481static int dm_set_clockgating_state(void *handle,
482 enum amd_clockgating_state state)
483{
484 return 0;
485}
486
487static int dm_set_powergating_state(void *handle,
488 enum amd_powergating_state state)
489{
490 return 0;
491}
492
493/* Prototypes of private functions */
494static int dm_early_init(void* handle);
495
a32e24b4 496/* Allocate memory for FBC compressed data */
3e332d3a 497static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 498{
3e332d3a
RL		 499 struct drm_device *dev = connector->dev;
500 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 501 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 502 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
503 struct drm_display_mode *mode;
42e67c3b
RL		 504 unsigned long max_size = 0;
505
506 if (adev->dm.dc->fbc_compressor == NULL)
507 return;
a32e24b4 508
3e332d3a 509 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 510 return;
511
3e332d3a
RL		 512 if (compressor->bo_ptr)
513 return;
42e67c3b 514
42e67c3b 515
3e332d3a
RL		 516 list_for_each_entry(mode, &connector->modes, head) {
517 if (max_size < mode->htotal * mode->vtotal)
518 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 519 }
520
521 if (max_size) {
522 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 523 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 524 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 525
526 if (r)
42e67c3b
RL		 527 DRM_ERROR("DM: Failed to initialize FBC\n");
528 else {
529 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
530 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
531 }
532
a32e24b4
RL		 533 }
534
535}
a32e24b4 536
6ce8f316
NK		 537static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
538 int pipe, bool *enabled,
539 unsigned char *buf, int max_bytes)
540{
541 struct drm_device *dev = dev_get_drvdata(kdev);
542 struct amdgpu_device *adev = dev->dev_private;
543 struct drm_connector *connector;
544 struct drm_connector_list_iter conn_iter;
545 struct amdgpu_dm_connector *aconnector;
546 int ret = 0;
547
548 *enabled = false;
549
550 mutex_lock(&adev->dm.audio_lock);
551
552 drm_connector_list_iter_begin(dev, &conn_iter);
553 drm_for_each_connector_iter(connector, &conn_iter) {
554 aconnector = to_amdgpu_dm_connector(connector);
555 if (aconnector->audio_inst != port)
556 continue;
557
558 *enabled = true;
559 ret = drm_eld_size(connector->eld);
560 memcpy(buf, connector->eld, min(max_bytes, ret));
561
562 break;
563 }
564 drm_connector_list_iter_end(&conn_iter);
565
566 mutex_unlock(&adev->dm.audio_lock);
567
568 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
569
570 return ret;
571}
572
573static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
574 .get_eld = amdgpu_dm_audio_component_get_eld,
575};
576
577static int amdgpu_dm_audio_component_bind(struct device *kdev,
578 struct device *hda_kdev, void *data)
579{
580 struct drm_device *dev = dev_get_drvdata(kdev);
581 struct amdgpu_device *adev = dev->dev_private;
582 struct drm_audio_component *acomp = data;
583
584 acomp->ops = &amdgpu_dm_audio_component_ops;
585 acomp->dev = kdev;
586 adev->dm.audio_component = acomp;
587
588 return 0;
589}
590
591static void amdgpu_dm_audio_component_unbind(struct device *kdev,
592 struct device *hda_kdev, void *data)
593{
594 struct drm_device *dev = dev_get_drvdata(kdev);
595 struct amdgpu_device *adev = dev->dev_private;
596 struct drm_audio_component *acomp = data;
597
598 acomp->ops = NULL;
599 acomp->dev = NULL;
600 adev->dm.audio_component = NULL;
601}
602
603static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
604 .bind = amdgpu_dm_audio_component_bind,
605 .unbind = amdgpu_dm_audio_component_unbind,
606};
607
608static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
609{
610 int i, ret;
611
612 if (!amdgpu_audio)
613 return 0;
614
615 adev->mode_info.audio.enabled = true;
616
617 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
618
619 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
620 adev->mode_info.audio.pin[i].channels = -1;
621 adev->mode_info.audio.pin[i].rate = -1;
622 adev->mode_info.audio.pin[i].bits_per_sample = -1;
623 adev->mode_info.audio.pin[i].status_bits = 0;
624 adev->mode_info.audio.pin[i].category_code = 0;
625 adev->mode_info.audio.pin[i].connected = false;
626 adev->mode_info.audio.pin[i].id =
627 adev->dm.dc->res_pool->audios[i]->inst;
628 adev->mode_info.audio.pin[i].offset = 0;
629 }
630
631 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
632 if (ret < 0)
633 return ret;
634
635 adev->dm.audio_registered = true;
636
637 return 0;
638}
639
640static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
641{
642 if (!amdgpu_audio)
643 return;
644
645 if (!adev->mode_info.audio.enabled)
646 return;
647
648 if (adev->dm.audio_registered) {
649 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
650 adev->dm.audio_registered = false;
651 }
652
653 /* TODO: Disable audio? */
654
655 adev->mode_info.audio.enabled = false;
656}
657
658void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
659{
660 struct drm_audio_component *acomp = adev->dm.audio_component;
661
662 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
663 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
664
665 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
666 pin, -1);
667 }
668}
669
7578ecda 670static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 671{
672 struct dc_init_data init_data;
52704fca
BL		 673#ifdef CONFIG_DRM_AMD_DC_HDCP
674 struct dc_callback_init init_params;
675#endif
676
4562236b
HW		 677 adev->dm.ddev = adev->ddev;
678 adev->dm.adev = adev;
679
4562236b
HW		 680 /* Zero all the fields */
681 memset(&init_data, 0, sizeof(init_data));
52704fca
BL		 682#ifdef CONFIG_DRM_AMD_DC_HDCP
683 memset(&init_params, 0, sizeof(init_params));
684#endif
4562236b 685
674e78ac 686 mutex_init(&adev->dm.dc_lock);
6ce8f316 687 mutex_init(&adev->dm.audio_lock);
674e78ac 688
4562236b
HW		 689 if(amdgpu_dm_irq_init(adev)) {
690 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
691 goto error;
692 }
693
694 init_data.asic_id.chip_family = adev->family;
695
696 init_data.asic_id.pci_revision_id = adev->rev_id;
697 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
698
770d13b1 699 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 700 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
701 init_data.asic_id.atombios_base_address =
702 adev->mode_info.atom_context->bios;
703
704 init_data.driver = adev;
705
706 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
707
708 if (!adev->dm.cgs_device) {
709 DRM_ERROR("amdgpu: failed to create cgs device.\n");
710 goto error;
711 }
712
713 init_data.cgs_device = adev->dm.cgs_device;
714
4562236b
HW		 715 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
716
6e227308
HW		 717 /*
718 * TODO debug why this doesn't work on Raven
719 */
720 if (adev->flags & AMD_IS_APU &&
721 adev->asic_type >= CHIP_CARRIZO &&
1c425915 722 adev->asic_type <= CHIP_RAVEN)
6e227308
HW		 723 init_data.flags.gpu_vm_support = true;
724
04b94af4
AD		 725 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
726 init_data.flags.fbc_support = true;
727
d99f38ae
AD		 728 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
729 init_data.flags.multi_mon_pp_mclk_switch = true;
730
27eaa492 731 init_data.flags.power_down_display_on_boot = true;
78ad75f8 732
48321c3d
HW		 733#ifdef CONFIG_DRM_AMD_DC_DCN2_0
734 init_data.soc_bounding_box = adev->dm.soc_bounding_box;
735#endif
27eaa492 736
4562236b
HW		 737 /* Display Core create. */
738 adev->dm.dc = dc_create(&init_data);
739
423788c7 740 if (adev->dm.dc) {
76121231 741 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 742 } else {
76121231 743 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 744 goto error;
745 }
4562236b 746
98bf2f52
JP		 747 dc_hardware_init(adev->dm.dc);
748
4562236b
HW		 749 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
750 if (!adev->dm.freesync_module) {
751 DRM_ERROR(
752 "amdgpu: failed to initialize freesync_module.\n");
753 } else
f1ad2f5e 754 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 755 adev->dm.freesync_module);
756
e277adc5
LSL		 757 amdgpu_dm_init_color_mod();
758
52704fca 759#ifdef CONFIG_DRM_AMD_DC_HDCP
96a3b32e
BL		 760 if (adev->asic_type >= CHIP_RAVEN) {
761 adev->dm.hdcp_workqueue = hdcp_create_workqueue(&adev->psp, &init_params.cp_psp, adev->dm.dc);
52704fca 762
96a3b32e
BL		 763 if (!adev->dm.hdcp_workqueue)
764 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
765 else
766 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
52704fca 767
96a3b32e
BL		 768 dc_init_callbacks(adev->dm.dc, &init_params);
769 }
52704fca 770#endif
4562236b
HW		 771 if (amdgpu_dm_initialize_drm_device(adev)) {
772 DRM_ERROR(
773 "amdgpu: failed to initialize sw for display support.\n");
774 goto error;
775 }
776
777 /* Update the actual used number of crtc */
778 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
779
780 /* TODO: Add_display_info? */
781
782 /* TODO use dynamic cursor width */
ce75805e
AG		 783 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
784 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 785
786 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
787 DRM_ERROR(
788 "amdgpu: failed to initialize sw for display support.\n");
789 goto error;
790 }
791
e498eb71
NK		 792#if defined(CONFIG_DEBUG_FS)
793 if (dtn_debugfs_init(adev))
794 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
795#endif
796
f1ad2f5e 797 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 798
799 return 0;
800error:
801 amdgpu_dm_fini(adev);
802
59d0f396 803 return -EINVAL;
4562236b
HW		 804}
805
7578ecda 806static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b 807{
6ce8f316
NK		 808 amdgpu_dm_audio_fini(adev);
809
4562236b 810 amdgpu_dm_destroy_drm_device(&adev->dm);
c8bdf2b6 811
52704fca
BL		 812#ifdef CONFIG_DRM_AMD_DC_HDCP
813 if (adev->dm.hdcp_workqueue) {
814 hdcp_destroy(adev->dm.hdcp_workqueue);
815 adev->dm.hdcp_workqueue = NULL;
816 }
817
818 if (adev->dm.dc)
819 dc_deinit_callbacks(adev->dm.dc);
820#endif
821
c8bdf2b6
ED		 822 /* DC Destroy TODO: Replace destroy DAL */
823 if (adev->dm.dc)
824 dc_destroy(&adev->dm.dc);
4562236b
HW		 825 /*
826 * TODO: pageflip, vlank interrupt
827 *
828 * amdgpu_dm_irq_fini(adev);
829 */
830
831 if (adev->dm.cgs_device) {
832 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
833 adev->dm.cgs_device = NULL;
834 }
835 if (adev->dm.freesync_module) {
836 mod_freesync_destroy(adev->dm.freesync_module);
837 adev->dm.freesync_module = NULL;
838 }
674e78ac 839
6ce8f316 840 mutex_destroy(&adev->dm.audio_lock);
674e78ac
NK		 841 mutex_destroy(&adev->dm.dc_lock);
842
4562236b
HW		 843 return;
844}
845
a94d5569 846static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 847{
a7669aff 848 const char *fw_name_dmcu = NULL;
a94d5569
DF		 849 int r;
850 const struct dmcu_firmware_header_v1_0 *hdr;
851
852 switch(adev->asic_type) {
853 case CHIP_BONAIRE:
854 case CHIP_HAWAII:
855 case CHIP_KAVERI:
856 case CHIP_KABINI:
857 case CHIP_MULLINS:
858 case CHIP_TONGA:
859 case CHIP_FIJI:
860 case CHIP_CARRIZO:
861 case CHIP_STONEY:
862 case CHIP_POLARIS11:
863 case CHIP_POLARIS10:
864 case CHIP_POLARIS12:
865 case CHIP_VEGAM:
866 case CHIP_VEGA10:
867 case CHIP_VEGA12:
868 case CHIP_VEGA20:
476e955d 869 case CHIP_NAVI10:
baebcf2e 870 case CHIP_NAVI14:
fbd2afe5 871 case CHIP_NAVI12:
30221ad8 872 case CHIP_RENOIR:
a94d5569
DF		 873 return 0;
874 case CHIP_RAVEN:
a7669aff
HW		 875 if (ASICREV_IS_PICASSO(adev->external_rev_id))
876 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
877 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
878 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
879 else
a7669aff 880 return 0;
a94d5569
DF		 881 break;
882 default:
883 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 884 return -EINVAL;
a94d5569
DF		 885 }
886
887 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
888 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
889 return 0;
890 }
891
892 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
893 if (r == -ENOENT) {
894 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
895 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
896 adev->dm.fw_dmcu = NULL;
897 return 0;
898 }
899 if (r) {
900 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
901 fw_name_dmcu);
902 return r;
903 }
904
905 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
906 if (r) {
907 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
908 fw_name_dmcu);
909 release_firmware(adev->dm.fw_dmcu);
910 adev->dm.fw_dmcu = NULL;
911 return r;
912 }
913
914 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
915 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
916 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
917 adev->firmware.fw_size +=
918 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
919
920 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
921 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
922 adev->firmware.fw_size +=
923 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
924
ee6e89c0
DF		 925 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
926
a94d5569
DF		 927 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
928
4562236b
HW		 929 return 0;
930}
931
a94d5569
DF		 932static int dm_sw_init(void *handle)
933{
934 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
935
936 return load_dmcu_fw(adev);
937}
938
4562236b
HW		 939static int dm_sw_fini(void *handle)
940{
a94d5569
DF		 941 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
942
943 if(adev->dm.fw_dmcu) {
944 release_firmware(adev->dm.fw_dmcu);
945 adev->dm.fw_dmcu = NULL;
946 }
947
4562236b
HW		 948 return 0;
949}
950
7abcf6b5 951static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 952{
c84dec2f 953 struct amdgpu_dm_connector *aconnector;
4562236b 954 struct drm_connector *connector;
f8d2d39e 955 struct drm_connector_list_iter iter;
7abcf6b5 956 int ret = 0;
4562236b 957
f8d2d39e
LP		 958 drm_connector_list_iter_begin(dev, &iter);
959 drm_for_each_connector_iter(connector, &iter) {
b349f76e 960 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 961 if (aconnector->dc_link->type == dc_connection_mst_branch &&
962 aconnector->mst_mgr.aux) {
f1ad2f5e 963 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
f8d2d39e
LP		 964 aconnector,
965 aconnector->base.base.id);
7abcf6b5
AG		 966
967 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
968 if (ret < 0) {
969 DRM_ERROR("DM_MST: Failed to start MST\n");
f8d2d39e
LP		 970 aconnector->dc_link->type =
971 dc_connection_single;
972 break;
7abcf6b5 973 }
f8d2d39e 974 }
4562236b 975 }
f8d2d39e 976 drm_connector_list_iter_end(&iter);
4562236b 977
7abcf6b5
AG		 978 return ret;
979}
980
981static int dm_late_init(void *handle)
982{
42e67c3b 983 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 984
bbf854dc
DF		 985 struct dmcu_iram_parameters params;
986 unsigned int linear_lut[16];
987 int i;
988 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
96cb7cf1 989 bool ret = false;
bbf854dc
DF		 990
991 for (i = 0; i < 16; i++)
992 linear_lut[i] = 0xFFFF * i / 15;
993
994 params.set = 0;
995 params.backlight_ramping_start = 0xCCCC;
996 params.backlight_ramping_reduction = 0xCCCCCCCC;
997 params.backlight_lut_array_size = 16;
998 params.backlight_lut_array = linear_lut;
999
2ad0cdf9
AK		 1000 /* Min backlight level after ABM reduction, Don't allow below 1%
1001 * 0xFFFF x 0.01 = 0x28F
1002 */
1003 params.min_abm_backlight = 0x28F;
1004
96cb7cf1 1005 /* todo will enable for navi10 */
1006 if (adev->asic_type <= CHIP_RAVEN) {
1007 ret = dmcu_load_iram(dmcu, params);
bbf854dc 1008
96cb7cf1 1009 if (!ret)
1010 return -EINVAL;
1011 }
bbf854dc 1012
42e67c3b 1013 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 1014}
1015
1016static void s3_handle_mst(struct drm_device *dev, bool suspend)
1017{
c84dec2f 1018 struct amdgpu_dm_connector *aconnector;
4562236b 1019 struct drm_connector *connector;
f8d2d39e 1020 struct drm_connector_list_iter iter;
fe7553be
LP		 1021 struct drm_dp_mst_topology_mgr *mgr;
1022 int ret;
1023 bool need_hotplug = false;
4562236b 1024
f8d2d39e
LP		 1025 drm_connector_list_iter_begin(dev, &iter);
1026 drm_for_each_connector_iter(connector, &iter) {
fe7553be
LP		 1027 aconnector = to_amdgpu_dm_connector(connector);
1028 if (aconnector->dc_link->type != dc_connection_mst_branch ||
1029 aconnector->mst_port)
1030 continue;
1031
1032 mgr = &aconnector->mst_mgr;
1033
1034 if (suspend) {
1035 drm_dp_mst_topology_mgr_suspend(mgr);
1036 } else {
1037 ret = drm_dp_mst_topology_mgr_resume(mgr);
1038 if (ret < 0) {
1039 drm_dp_mst_topology_mgr_set_mst(mgr, false);
1040 need_hotplug = true;
1041 }
1042 }
4562236b 1043 }
f8d2d39e 1044 drm_connector_list_iter_end(&iter);
fe7553be
LP		 1045
1046 if (need_hotplug)
1047 drm_kms_helper_hotplug_event(dev);
4562236b
HW		 1048}
1049
b8592b48
LL		 1050/**
1051 * dm_hw_init() - Initialize DC device
28d687ea 1052 * @handle: The base driver device containing the amdgpu_dm device.
b8592b48
LL		 1053 *
1054 * Initialize the &struct amdgpu_display_manager device. This involves calling
1055 * the initializers of each DM component, then populating the struct with them.
1056 *
1057 * Although the function implies hardware initialization, both hardware and
1058 * software are initialized here. Splitting them out to their relevant init
1059 * hooks is a future TODO item.
1060 *
1061 * Some notable things that are initialized here:
1062 *
1063 * - Display Core, both software and hardware
1064 * - DC modules that we need (freesync and color management)
1065 * - DRM software states
1066 * - Interrupt sources and handlers
1067 * - Vblank support
1068 * - Debug FS entries, if enabled
1069 */
4562236b
HW		 1070static int dm_hw_init(void *handle)
1071{
1072 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1073 /* Create DAL display manager */
1074 amdgpu_dm_init(adev);
4562236b
HW		 1075 amdgpu_dm_hpd_init(adev);
1076
4562236b
HW		 1077 return 0;
1078}
1079
b8592b48
LL		 1080/**
1081 * dm_hw_fini() - Teardown DC device
28d687ea 1082 * @handle: The base driver device containing the amdgpu_dm device.
b8592b48
LL		 1083 *
1084 * Teardown components within &struct amdgpu_display_manager that require
1085 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1086 * were loaded. Also flush IRQ workqueues and disable them.
1087 */
4562236b
HW		 1088static int dm_hw_fini(void *handle)
1089{
1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1091
1092 amdgpu_dm_hpd_fini(adev);
1093
1094 amdgpu_dm_irq_fini(adev);
21de3396 1095 amdgpu_dm_fini(adev);
4562236b
HW		 1096 return 0;
1097}
1098
1099static int dm_suspend(void *handle)
1100{
1101 struct amdgpu_device *adev = handle;
1102 struct amdgpu_display_manager *dm = &adev->dm;
1103 int ret = 0;
4562236b 1104
d2f0b53b
LHM		 1105 WARN_ON(adev->dm.cached_state);
1106 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
1107
4562236b
HW		 1108 s3_handle_mst(adev->ddev, true);
1109
4562236b
HW		 1110 amdgpu_dm_irq_suspend(adev);
1111
a3621485 1112
32f5062d 1113 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 1114
1115 return ret;
1116}
1117
1daf8c63
AD		 1118static struct amdgpu_dm_connector *
1119amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1120 struct drm_crtc *crtc)
4562236b
HW		 1121{
1122 uint32_t i;
c2cea706 1123 struct drm_connector_state *new_con_state;
4562236b
HW		 1124 struct drm_connector *connector;
1125 struct drm_crtc *crtc_from_state;
1126
c2cea706
LSL		 1127 for_each_new_connector_in_state(state, connector, new_con_state, i) {
1128 crtc_from_state = new_con_state->crtc;
4562236b
HW		 1129
1130 if (crtc_from_state == crtc)
c84dec2f 1131 return to_amdgpu_dm_connector(connector);
4562236b
HW		 1132 }
1133
1134 return NULL;
1135}
1136
fbbdadf2
BL		 1137static void emulated_link_detect(struct dc_link *link)
1138{
1139 struct dc_sink_init_data sink_init_data = { 0 };
1140 struct display_sink_capability sink_caps = { 0 };
1141 enum dc_edid_status edid_status;
1142 struct dc_context *dc_ctx = link->ctx;
1143 struct dc_sink *sink = NULL;
1144 struct dc_sink *prev_sink = NULL;
1145
1146 link->type = dc_connection_none;
1147 prev_sink = link->local_sink;
1148
1149 if (prev_sink != NULL)
1150 dc_sink_retain(prev_sink);
1151
1152 switch (link->connector_signal) {
1153 case SIGNAL_TYPE_HDMI_TYPE_A: {
1154 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1155 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1156 break;
1157 }
1158
1159 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1160 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1161 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1162 break;
1163 }
1164
1165 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1166 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1167 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1168 break;
1169 }
1170
1171 case SIGNAL_TYPE_LVDS: {
1172 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1173 sink_caps.signal = SIGNAL_TYPE_LVDS;
1174 break;
1175 }
1176
1177 case SIGNAL_TYPE_EDP: {
1178 sink_caps.transaction_type =
1179 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1180 sink_caps.signal = SIGNAL_TYPE_EDP;
1181 break;
1182 }
1183
1184 case SIGNAL_TYPE_DISPLAY_PORT: {
1185 sink_caps.transaction_type =
1186 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1187 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1188 break;
1189 }
1190
1191 default:
1192 DC_ERROR("Invalid connector type! signal:%d\n",
1193 link->connector_signal);
1194 return;
1195 }
1196
1197 sink_init_data.link = link;
1198 sink_init_data.sink_signal = sink_caps.signal;
1199
1200 sink = dc_sink_create(&sink_init_data);
1201 if (!sink) {
1202 DC_ERROR("Failed to create sink!\n");
1203 return;
1204 }
1205
dcd5fb82 1206 /* dc_sink_create returns a new reference */
fbbdadf2
BL		 1207 link->local_sink = sink;
1208
1209 edid_status = dm_helpers_read_local_edid(
1210 link->ctx,
1211 link,
1212 sink);
1213
1214 if (edid_status != EDID_OK)
1215 DC_ERROR("Failed to read EDID");
1216
1217}
1218
4562236b
HW		 1219static int dm_resume(void *handle)
1220{
1221 struct amdgpu_device *adev = handle;
4562236b
HW		 1222 struct drm_device *ddev = adev->ddev;
1223 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 1224 struct amdgpu_dm_connector *aconnector;
4562236b 1225 struct drm_connector *connector;
f8d2d39e 1226 struct drm_connector_list_iter iter;
4562236b 1227 struct drm_crtc *crtc;
c2cea706 1228 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 1229 struct dm_crtc_state *dm_new_crtc_state;
1230 struct drm_plane *plane;
1231 struct drm_plane_state *new_plane_state;
1232 struct dm_plane_state *dm_new_plane_state;
113b7a01 1233 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
fbbdadf2 1234 enum dc_connection_type new_connection_type = dc_connection_none;
a3621485 1235 int i;
4562236b 1236
113b7a01
LL		 1237 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1238 dc_release_state(dm_state->context);
1239 dm_state->context = dc_create_state(dm->dc);
1240 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1241 dc_resource_state_construct(dm->dc, dm_state->context);
1242
a80aa93d
ML		 1243 /* power on hardware */
1244 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1245
4562236b
HW		 1246 /* program HPD filter */
1247 dc_resume(dm->dc);
1248
4562236b
HW		 1249 /*
1250 * early enable HPD Rx IRQ, should be done before set mode as short
1251 * pulse interrupts are used for MST
1252 */
1253 amdgpu_dm_irq_resume_early(adev);
1254
684cd480
LP		 1255 /* On resume we need to rewrite the MSTM control bits to enable MST*/
1256 s3_handle_mst(ddev, false);
1257
4562236b 1258 /* Do detection*/
f8d2d39e
LP		 1259 drm_connector_list_iter_begin(ddev, &iter);
1260 drm_for_each_connector_iter(connector, &iter) {
c84dec2f 1261 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1262
1263 /*
1264 * this is the case when traversing through already created
1265 * MST connectors, should be skipped
1266 */
1267 if (aconnector->mst_port)
1268 continue;
1269
03ea364c 1270 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 1271 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1272 DRM_ERROR("KMS: Failed to detect connector\n");
1273
1274 if (aconnector->base.force && new_connection_type == dc_connection_none)
1275 emulated_link_detect(aconnector->dc_link);
1276 else
1277 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 1278
1279 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1280 aconnector->fake_enable = false;
1281
dcd5fb82
MF		 1282 if (aconnector->dc_sink)
1283 dc_sink_release(aconnector->dc_sink);
4562236b
HW		 1284 aconnector->dc_sink = NULL;
1285 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 1286 mutex_unlock(&aconnector->hpd_lock);
4562236b 1287 }
f8d2d39e 1288 drm_connector_list_iter_end(&iter);
4562236b 1289
1f6010a9 1290 /* Force mode set in atomic commit */
a80aa93d 1291 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 1292 new_crtc_state->active_changed = true;
4f346e65 1293
fcb4019e
LSL		 1294 /*
1295 * atomic_check is expected to create the dc states. We need to release
1296 * them here, since they were duplicated as part of the suspend
1297 * procedure.
1298 */
a80aa93d 1299 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 1300 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1301 if (dm_new_crtc_state->stream) {
1302 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1303 dc_stream_release(dm_new_crtc_state->stream);
1304 dm_new_crtc_state->stream = NULL;
1305 }
1306 }
1307
a80aa93d 1308 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 1309 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1310 if (dm_new_plane_state->dc_state) {
1311 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1312 dc_plane_state_release(dm_new_plane_state->dc_state);
1313 dm_new_plane_state->dc_state = NULL;
1314 }
1315 }
1316
2d1af6a1 1317 drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 1318
a80aa93d 1319 dm->cached_state = NULL;
0a214e2f 1320
9faa4237 1321 amdgpu_dm_irq_resume_late(adev);
4562236b 1322
2d1af6a1 1323 return 0;
4562236b
HW		 1324}
1325
b8592b48
LL		 1326/**
1327 * DOC: DM Lifecycle
1328 *
1329 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1330 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1331 * the base driver's device list to be initialized and torn down accordingly.
1332 *
1333 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1334 */
1335
4562236b
HW		 1336static const struct amd_ip_funcs amdgpu_dm_funcs = {
1337 .name = "dm",
1338 .early_init = dm_early_init,
7abcf6b5 1339 .late_init = dm_late_init,
4562236b
HW		 1340 .sw_init = dm_sw_init,
1341 .sw_fini = dm_sw_fini,
1342 .hw_init = dm_hw_init,
1343 .hw_fini = dm_hw_fini,
1344 .suspend = dm_suspend,
1345 .resume = dm_resume,
1346 .is_idle = dm_is_idle,
1347 .wait_for_idle = dm_wait_for_idle,
1348 .check_soft_reset = dm_check_soft_reset,
1349 .soft_reset = dm_soft_reset,
1350 .set_clockgating_state = dm_set_clockgating_state,
1351 .set_powergating_state = dm_set_powergating_state,
1352};
1353
1354const struct amdgpu_ip_block_version dm_ip_block =
1355{
1356 .type = AMD_IP_BLOCK_TYPE_DCE,
1357 .major = 1,
1358 .minor = 0,
1359 .rev = 0,
1360 .funcs = &amdgpu_dm_funcs,
1361};
1362
ca3268c4 1363
b8592b48
LL		 1364/**
1365 * DOC: atomic
1366 *
1367 * *WIP*
1368 */
0a323b84 1369
b3663f70 1370static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 1371 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 1372 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 1373 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 1374 .atomic_commit = amdgpu_dm_atomic_commit,
54f5499a
AG		 1375};
1376
1377static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1378 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 1379};
1380
7578ecda 1381static void
3ee6b26b 1382amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1383{
1384 struct drm_connector *connector = &aconnector->base;
1385 struct drm_device *dev = connector->dev;
b73a22d3 1386 struct dc_sink *sink;
4562236b
HW		 1387
1388 /* MST handled by drm_mst framework */
1389 if (aconnector->mst_mgr.mst_state == true)
1390 return;
1391
1392
1393 sink = aconnector->dc_link->local_sink;
dcd5fb82
MF		 1394 if (sink)
1395 dc_sink_retain(sink);
4562236b 1396
1f6010a9
DF		 1397 /*
1398 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 1399 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 1400 * Skip if already done during boot.
4562236b
HW		 1401 */
1402 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1403 && aconnector->dc_em_sink) {
1404
1f6010a9
DF		 1405 /*
1406 * For S3 resume with headless use eml_sink to fake stream
1407 * because on resume connector->sink is set to NULL
4562236b
HW		 1408 */
1409 mutex_lock(&dev->mode_config.mutex);
1410
1411 if (sink) {
922aa1e1 1412 if (aconnector->dc_sink) {
98e6436d 1413 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 1414 /*
1415 * retain and release below are used to
1416 * bump up refcount for sink because the link doesn't point
1417 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 1418 * reshuffle by UMD we will get into unwanted dc_sink release
1419 */
dcd5fb82 1420 dc_sink_release(aconnector->dc_sink);
922aa1e1 1421 }
4562236b 1422 aconnector->dc_sink = sink;
dcd5fb82 1423 dc_sink_retain(aconnector->dc_sink);
98e6436d
AK		 1424 amdgpu_dm_update_freesync_caps(connector,
1425 aconnector->edid);
4562236b 1426 } else {
98e6436d 1427 amdgpu_dm_update_freesync_caps(connector, NULL);
dcd5fb82 1428 if (!aconnector->dc_sink) {
4562236b 1429 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1 1430 dc_sink_retain(aconnector->dc_sink);
dcd5fb82 1431 }
4562236b
HW		 1432 }
1433
1434 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1435
1436 if (sink)
1437 dc_sink_release(sink);
4562236b
HW		 1438 return;
1439 }
1440
1441 /*
1442 * TODO: temporary guard to look for proper fix
1443 * if this sink is MST sink, we should not do anything
1444 */
dcd5fb82
MF		 1445 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1446 dc_sink_release(sink);
4562236b 1447 return;
dcd5fb82 1448 }
4562236b
HW		 1449
1450 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 1451 /*
1452 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1453 * Do nothing!!
1454 */
f1ad2f5e 1455 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b 1456 aconnector->connector_id);
dcd5fb82
MF		 1457 if (sink)
1458 dc_sink_release(sink);
4562236b
HW		 1459 return;
1460 }
1461
f1ad2f5e 1462 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 1463 aconnector->connector_id, aconnector->dc_sink, sink);
1464
1465 mutex_lock(&dev->mode_config.mutex);
1466
1f6010a9
DF		 1467 /*
1468 * 1. Update status of the drm connector
1469 * 2. Send an event and let userspace tell us what to do
1470 */
4562236b 1471 if (sink) {
1f6010a9
DF		 1472 /*
1473 * TODO: check if we still need the S3 mode update workaround.
1474 * If yes, put it here.
1475 */
4562236b 1476 if (aconnector->dc_sink)
98e6436d 1477 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1478
1479 aconnector->dc_sink = sink;
dcd5fb82 1480 dc_sink_retain(aconnector->dc_sink);
900b3cb1 1481 if (sink->dc_edid.length == 0) {
4562236b 1482 aconnector->edid = NULL;
e86e8947 1483 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 1484 } else {
4562236b
HW		 1485 aconnector->edid =
1486 (struct edid *) sink->dc_edid.raw_edid;
1487
1488
c555f023 1489 drm_connector_update_edid_property(connector,
4562236b 1490 aconnector->edid);
e86e8947
HV		 1491 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1492 aconnector->edid);
4562236b 1493 }
98e6436d 1494 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 1495
1496 } else {
e86e8947 1497 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 1498 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 1499 drm_connector_update_edid_property(connector, NULL);
4562236b 1500 aconnector->num_modes = 0;
dcd5fb82 1501 dc_sink_release(aconnector->dc_sink);
4562236b 1502 aconnector->dc_sink = NULL;
5326c452 1503 aconnector->edid = NULL;
0c8620d6
BL		 1504#ifdef CONFIG_DRM_AMD_DC_HDCP
1505 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
1506 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
1507 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
1508#endif
4562236b
HW		 1509 }
1510
1511 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1512
1513 if (sink)
1514 dc_sink_release(sink);
4562236b
HW		 1515}
1516
1517static void handle_hpd_irq(void *param)
1518{
c84dec2f 1519 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1520 struct drm_connector *connector = &aconnector->base;
1521 struct drm_device *dev = connector->dev;
fbbdadf2 1522 enum dc_connection_type new_connection_type = dc_connection_none;
0c8620d6
BL		 1523#ifdef CONFIG_DRM_AMD_DC_HDCP
1524 struct amdgpu_device *adev = dev->dev_private;
1525#endif
4562236b 1526
1f6010a9
DF		 1527 /*
1528 * In case of failure or MST no need to update connector status or notify the OS
1529 * since (for MST case) MST does this in its own context.
4562236b
HW		 1530 */
1531 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6 1532
0c8620d6 1533#ifdef CONFIG_DRM_AMD_DC_HDCP
96a3b32e
BL		 1534 if (adev->asic_type >= CHIP_RAVEN)
1535 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
0c8620d6 1536#endif
2e0ac3d6
HW		 1537 if (aconnector->fake_enable)
1538 aconnector->fake_enable = false;
1539
fbbdadf2
BL		 1540 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1541 DRM_ERROR("KMS: Failed to detect connector\n");
1542
1543 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1544 emulated_link_detect(aconnector->dc_link);
1545
1546
1547 drm_modeset_lock_all(dev);
1548 dm_restore_drm_connector_state(dev, connector);
1549 drm_modeset_unlock_all(dev);
1550
1551 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1552 drm_kms_helper_hotplug_event(dev);
1553
1554 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1555 amdgpu_dm_update_connector_after_detect(aconnector);
1556
1557
1558 drm_modeset_lock_all(dev);
1559 dm_restore_drm_connector_state(dev, connector);
1560 drm_modeset_unlock_all(dev);
1561
1562 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1563 drm_kms_helper_hotplug_event(dev);
1564 }
1565 mutex_unlock(&aconnector->hpd_lock);
1566
1567}
1568
c84dec2f 1569static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1570{
1571 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1572 uint8_t dret;
1573 bool new_irq_handled = false;
1574 int dpcd_addr;
1575 int dpcd_bytes_to_read;
1576
1577 const int max_process_count = 30;
1578 int process_count = 0;
1579
1580 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1581
1582 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1583 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1584 /* DPCD 0x200 - 0x201 for downstream IRQ */
1585 dpcd_addr = DP_SINK_COUNT;
1586 } else {
1587 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1588 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1589 dpcd_addr = DP_SINK_COUNT_ESI;
1590 }
1591
1592 dret = drm_dp_dpcd_read(
1593 &aconnector->dm_dp_aux.aux,
1594 dpcd_addr,
1595 esi,
1596 dpcd_bytes_to_read);
1597
1598 while (dret == dpcd_bytes_to_read &&
1599 process_count < max_process_count) {
1600 uint8_t retry;
1601 dret = 0;
1602
1603 process_count++;
1604
f1ad2f5e 1605 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1606 /* handle HPD short pulse irq */
1607 if (aconnector->mst_mgr.mst_state)
1608 drm_dp_mst_hpd_irq(
1609 &aconnector->mst_mgr,
1610 esi,
1611 &new_irq_handled);
4562236b
HW		 1612
1613 if (new_irq_handled) {
1614 /* ACK at DPCD to notify down stream */
1615 const int ack_dpcd_bytes_to_write =
1616 dpcd_bytes_to_read - 1;
1617
1618 for (retry = 0; retry < 3; retry++) {
1619 uint8_t wret;
1620
1621 wret = drm_dp_dpcd_write(
1622 &aconnector->dm_dp_aux.aux,
1623 dpcd_addr + 1,
1624 &esi[1],
1625 ack_dpcd_bytes_to_write);
1626 if (wret == ack_dpcd_bytes_to_write)
1627 break;
1628 }
1629
1f6010a9 1630 /* check if there is new irq to be handled */
4562236b
HW		 1631 dret = drm_dp_dpcd_read(
1632 &aconnector->dm_dp_aux.aux,
1633 dpcd_addr,
1634 esi,
1635 dpcd_bytes_to_read);
1636
1637 new_irq_handled = false;
d4a6e8a9 1638 } else {
4562236b 1639 break;
d4a6e8a9 1640 }
4562236b
HW		 1641 }
1642
1643 if (process_count == max_process_count)
f1ad2f5e 1644 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1645}
1646
1647static void handle_hpd_rx_irq(void *param)
1648{
c84dec2f 1649 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1650 struct drm_connector *connector = &aconnector->base;
1651 struct drm_device *dev = connector->dev;
53cbf65c 1652 struct dc_link *dc_link = aconnector->dc_link;
4562236b 1653 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
fbbdadf2 1654 enum dc_connection_type new_connection_type = dc_connection_none;
2a0f9270
BL		 1655#ifdef CONFIG_DRM_AMD_DC_HDCP
1656 union hpd_irq_data hpd_irq_data;
1657 struct amdgpu_device *adev = dev->dev_private;
1658
1659 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
1660#endif
4562236b 1661
1f6010a9
DF		 1662 /*
1663 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 1664 * conflict, after implement i2c helper, this mutex should be
1665 * retired.
1666 */
53cbf65c 1667 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1668 mutex_lock(&aconnector->hpd_lock);
1669
2a0f9270
BL		 1670
1671#ifdef CONFIG_DRM_AMD_DC_HDCP
1672 if (dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL) &&
1673#else
4e18814e 1674 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
2a0f9270 1675#endif
4562236b
HW		 1676 !is_mst_root_connector) {
1677 /* Downstream Port status changed. */
fbbdadf2
BL		 1678 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1679 DRM_ERROR("KMS: Failed to detect connector\n");
1680
1681 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1682 emulated_link_detect(dc_link);
1683
1684 if (aconnector->fake_enable)
1685 aconnector->fake_enable = false;
1686
1687 amdgpu_dm_update_connector_after_detect(aconnector);
1688
1689
1690 drm_modeset_lock_all(dev);
1691 dm_restore_drm_connector_state(dev, connector);
1692 drm_modeset_unlock_all(dev);
1693
1694 drm_kms_helper_hotplug_event(dev);
1695 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1696
1697 if (aconnector->fake_enable)
1698 aconnector->fake_enable = false;
1699
4562236b
HW		 1700 amdgpu_dm_update_connector_after_detect(aconnector);
1701
1702
1703 drm_modeset_lock_all(dev);
1704 dm_restore_drm_connector_state(dev, connector);
1705 drm_modeset_unlock_all(dev);
1706
1707 drm_kms_helper_hotplug_event(dev);
1708 }
1709 }
2a0f9270
BL		 1710#ifdef CONFIG_DRM_AMD_DC_HDCP
1711 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ)
1712 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
1713#endif
4562236b 1714 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1715 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1716 dm_handle_hpd_rx_irq(aconnector);
1717
e86e8947
HV		 1718 if (dc_link->type != dc_connection_mst_branch) {
1719 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 1720 mutex_unlock(&aconnector->hpd_lock);
e86e8947 1721 }
4562236b
HW		 1722}
1723
1724static void register_hpd_handlers(struct amdgpu_device *adev)
1725{
1726 struct drm_device *dev = adev->ddev;
1727 struct drm_connector *connector;
c84dec2f 1728 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1729 const struct dc_link *dc_link;
1730 struct dc_interrupt_params int_params = {0};
1731
1732 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1733 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1734
1735 list_for_each_entry(connector,
1736 &dev->mode_config.connector_list, head) {
1737
c84dec2f 1738 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1739 dc_link = aconnector->dc_link;
1740
1741 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1742 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1743 int_params.irq_source = dc_link->irq_source_hpd;
1744
1745 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1746 handle_hpd_irq,
1747 (void *) aconnector);
1748 }
1749
1750 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1751
1752 /* Also register for DP short pulse (hpd_rx). */
1753 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1754 int_params.irq_source = dc_link->irq_source_hpd_rx;
1755
1756 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1757 handle_hpd_rx_irq,
1758 (void *) aconnector);
1759 }
1760 }
1761}
1762
1763/* Register IRQ sources and initialize IRQ callbacks */
1764static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1765{
1766 struct dc *dc = adev->dm.dc;
1767 struct common_irq_params *c_irq_params;
1768 struct dc_interrupt_params int_params = {0};
1769 int r;
1770 int i;
1ffdeca6 1771 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 1772
84374725 1773 if (adev->asic_type >= CHIP_VEGA10)
3760f76c 1774 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1775
1776 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1777 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1778
1f6010a9
DF		 1779 /*
1780 * Actions of amdgpu_irq_add_id():
4562236b
HW		 1781 * 1. Register a set() function with base driver.
1782 * Base driver will call set() function to enable/disable an
1783 * interrupt in DC hardware.
1784 * 2. Register amdgpu_dm_irq_handler().
1785 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1786 * coming from DC hardware.
1787 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1788 * for acknowledging and handling. */
1789
b57de80a 1790 /* Use VBLANK interrupt */
e9029155 1791 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1792 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1793 if (r) {
1794 DRM_ERROR("Failed to add crtc irq id!\n");
1795 return r;
1796 }
1797
1798 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1799 int_params.irq_source =
3d761e79 1800 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1801
b57de80a 1802 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1803
1804 c_irq_params->adev = adev;
1805 c_irq_params->irq_src = int_params.irq_source;
1806
1807 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1808 dm_crtc_high_irq, c_irq_params);
1809 }
1810
d2574c33
MK		 1811 /* Use VUPDATE interrupt */
1812 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
1813 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
1814 if (r) {
1815 DRM_ERROR("Failed to add vupdate irq id!\n");
1816 return r;
1817 }
1818
1819 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1820 int_params.irq_source =
1821 dc_interrupt_to_irq_source(dc, i, 0);
1822
1823 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1824
1825 c_irq_params->adev = adev;
1826 c_irq_params->irq_src = int_params.irq_source;
1827
1828 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1829 dm_vupdate_high_irq, c_irq_params);
1830 }
1831
3d761e79 1832 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1833 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1834 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1835 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1836 if (r) {
1837 DRM_ERROR("Failed to add page flip irq id!\n");
1838 return r;
1839 }
1840
1841 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1842 int_params.irq_source =
1843 dc_interrupt_to_irq_source(dc, i, 0);
1844
1845 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1846
1847 c_irq_params->adev = adev;
1848 c_irq_params->irq_src = int_params.irq_source;
1849
1850 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1851 dm_pflip_high_irq, c_irq_params);
1852
1853 }
1854
1855 /* HPD */
2c8ad2d5
AD		 1856 r = amdgpu_irq_add_id(adev, client_id,
1857 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1858 if (r) {
1859 DRM_ERROR("Failed to add hpd irq id!\n");
1860 return r;
1861 }
1862
1863 register_hpd_handlers(adev);
1864
1865 return 0;
1866}
1867
ff5ef992
AD		 1868#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1869/* Register IRQ sources and initialize IRQ callbacks */
1870static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1871{
1872 struct dc *dc = adev->dm.dc;
1873 struct common_irq_params *c_irq_params;
1874 struct dc_interrupt_params int_params = {0};
1875 int r;
1876 int i;
1877
1878 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1879 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1880
1f6010a9
DF		 1881 /*
1882 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 1883 * 1. Register a set() function with base driver.
1884 * Base driver will call set() function to enable/disable an
1885 * interrupt in DC hardware.
1886 * 2. Register amdgpu_dm_irq_handler().
1887 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1888 * coming from DC hardware.
1889 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1890 * for acknowledging and handling.
1f6010a9 1891 */
ff5ef992
AD		 1892
1893 /* Use VSTARTUP interrupt */
1894 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1895 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1896 i++) {
3760f76c 1897 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1898
1899 if (r) {
1900 DRM_ERROR("Failed to add crtc irq id!\n");
1901 return r;
1902 }
1903
1904 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1905 int_params.irq_source =
1906 dc_interrupt_to_irq_source(dc, i, 0);
1907
1908 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1909
1910 c_irq_params->adev = adev;
1911 c_irq_params->irq_src = int_params.irq_source;
1912
1913 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1914 dm_crtc_high_irq, c_irq_params);
1915 }
1916
d2574c33
MK		 1917 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
1918 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
1919 * to trigger at end of each vblank, regardless of state of the lock,
1920 * matching DCE behaviour.
1921 */
1922 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
1923 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
1924 i++) {
1925 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
1926
1927 if (r) {
1928 DRM_ERROR("Failed to add vupdate irq id!\n");
1929 return r;
1930 }
1931
1932 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1933 int_params.irq_source =
1934 dc_interrupt_to_irq_source(dc, i, 0);
1935
1936 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1937
1938 c_irq_params->adev = adev;
1939 c_irq_params->irq_src = int_params.irq_source;
1940
1941 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1942 dm_vupdate_high_irq, c_irq_params);
1943 }
1944
ff5ef992
AD		 1945 /* Use GRPH_PFLIP interrupt */
1946 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1947 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1948 i++) {
3760f76c 1949 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1950 if (r) {
1951 DRM_ERROR("Failed to add page flip irq id!\n");
1952 return r;
1953 }
1954
1955 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1956 int_params.irq_source =
1957 dc_interrupt_to_irq_source(dc, i, 0);
1958
1959 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1960
1961 c_irq_params->adev = adev;
1962 c_irq_params->irq_src = int_params.irq_source;
1963
1964 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1965 dm_pflip_high_irq, c_irq_params);
1966
1967 }
1968
1969 /* HPD */
3760f76c 1970 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1971 &adev->hpd_irq);
1972 if (r) {
1973 DRM_ERROR("Failed to add hpd irq id!\n");
1974 return r;
1975 }
1976
1977 register_hpd_handlers(adev);
1978
1979 return 0;
1980}
1981#endif
1982
eb3dc897
NK		 1983/*
1984 * Acquires the lock for the atomic state object and returns
1985 * the new atomic state.
1986 *
1987 * This should only be called during atomic check.
1988 */
1989static int dm_atomic_get_state(struct drm_atomic_state *state,
1990 struct dm_atomic_state **dm_state)
1991{
1992 struct drm_device *dev = state->dev;
1993 struct amdgpu_device *adev = dev->dev_private;
1994 struct amdgpu_display_manager *dm = &adev->dm;
1995 struct drm_private_state *priv_state;
eb3dc897
NK		 1996
1997 if (*dm_state)
1998 return 0;
1999
eb3dc897
NK		 2000 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
2001 if (IS_ERR(priv_state))
2002 return PTR_ERR(priv_state);
2003
2004 *dm_state = to_dm_atomic_state(priv_state);
2005
2006 return 0;
2007}
2008
2009struct dm_atomic_state *
2010dm_atomic_get_new_state(struct drm_atomic_state *state)
2011{
2012 struct drm_device *dev = state->dev;
2013 struct amdgpu_device *adev = dev->dev_private;
2014 struct amdgpu_display_manager *dm = &adev->dm;
2015 struct drm_private_obj *obj;
2016 struct drm_private_state *new_obj_state;
2017 int i;
2018
2019 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
2020 if (obj->funcs == dm->atomic_obj.funcs)
2021 return to_dm_atomic_state(new_obj_state);
2022 }
2023
2024 return NULL;
2025}
2026
2027struct dm_atomic_state *
2028dm_atomic_get_old_state(struct drm_atomic_state *state)
2029{
2030 struct drm_device *dev = state->dev;
2031 struct amdgpu_device *adev = dev->dev_private;
2032 struct amdgpu_display_manager *dm = &adev->dm;
2033 struct drm_private_obj *obj;
2034 struct drm_private_state *old_obj_state;
2035 int i;
2036
2037 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
2038 if (obj->funcs == dm->atomic_obj.funcs)
2039 return to_dm_atomic_state(old_obj_state);
2040 }
2041
2042 return NULL;
2043}
2044
2045static struct drm_private_state *
2046dm_atomic_duplicate_state(struct drm_private_obj *obj)
2047{
2048 struct dm_atomic_state *old_state, *new_state;
2049
2050 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
2051 if (!new_state)
2052 return NULL;
2053
2054 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
2055
813d20dc
AW		 2056 old_state = to_dm_atomic_state(obj->state);
2057
2058 if (old_state && old_state->context)
2059 new_state->context = dc_copy_state(old_state->context);
2060
eb3dc897
NK		 2061 if (!new_state->context) {
2062 kfree(new_state);
2063 return NULL;
2064 }
2065
eb3dc897
NK		 2066 return &new_state->base;
2067}
2068
2069static void dm_atomic_destroy_state(struct drm_private_obj *obj,
2070 struct drm_private_state *state)
2071{
2072 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
2073
2074 if (dm_state && dm_state->context)
2075 dc_release_state(dm_state->context);
2076
2077 kfree(dm_state);
2078}
2079
2080static struct drm_private_state_funcs dm_atomic_state_funcs = {
2081 .atomic_duplicate_state = dm_atomic_duplicate_state,
2082 .atomic_destroy_state = dm_atomic_destroy_state,
2083};
2084
4562236b
HW		 2085static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
2086{
eb3dc897 2087 struct dm_atomic_state *state;
4562236b
HW		 2088 int r;
2089
2090 adev->mode_info.mode_config_initialized = true;
2091
4562236b 2092 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 2093 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 2094
2095 adev->ddev->mode_config.max_width = 16384;
2096 adev->ddev->mode_config.max_height = 16384;
2097
2098 adev->ddev->mode_config.preferred_depth = 24;
2099 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 2100 /* indicates support for immediate flip */
4562236b
HW		 2101 adev->ddev->mode_config.async_page_flip = true;
2102
770d13b1 2103 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 2104
eb3dc897
NK		 2105 state = kzalloc(sizeof(*state), GFP_KERNEL);
2106 if (!state)
2107 return -ENOMEM;
2108
813d20dc 2109 state->context = dc_create_state(adev->dm.dc);
eb3dc897
NK		 2110 if (!state->context) {
2111 kfree(state);
2112 return -ENOMEM;
2113 }
2114
2115 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
2116
8c1a765b
DA		 2117 drm_atomic_private_obj_init(adev->ddev,
2118 &adev->dm.atomic_obj,
eb3dc897
NK		 2119 &state->base,
2120 &dm_atomic_state_funcs);
2121
3dc9b1ce 2122 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 2123 if (r)
2124 return r;
2125
6ce8f316
NK		 2126 r = amdgpu_dm_audio_init(adev);
2127 if (r)
2128 return r;
2129
4562236b
HW		 2130 return 0;
2131}
2132
206bbafe
DF		 2133#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
2134#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2135
4562236b
HW		 2136#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2137 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2138
206bbafe
DF		 2139static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
2140{
2141#if defined(CONFIG_ACPI)
2142 struct amdgpu_dm_backlight_caps caps;
2143
2144 if (dm->backlight_caps.caps_valid)
2145 return;
2146
2147 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
2148 if (caps.caps_valid) {
2149 dm->backlight_caps.min_input_signal = caps.min_input_signal;
2150 dm->backlight_caps.max_input_signal = caps.max_input_signal;
2151 dm->backlight_caps.caps_valid = true;
2152 } else {
2153 dm->backlight_caps.min_input_signal =
2154 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2155 dm->backlight_caps.max_input_signal =
2156 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2157 }
2158#else
8bcbc9ef
DF		 2159 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2160 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 2161#endif
2162}
2163
4562236b
HW		 2164static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
2165{
2166 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe
DF		 2167 struct amdgpu_dm_backlight_caps caps;
2168 uint32_t brightness = bd->props.brightness;
4562236b 2169
206bbafe
DF		 2170 amdgpu_dm_update_backlight_caps(dm);
2171 caps = dm->backlight_caps;
0cafc82f 2172 /*
206bbafe
DF		 2173 * The brightness input is in the range 0-255
2174 * It needs to be rescaled to be between the
2175 * requested min and max input signal
2176 *
2177 * It also needs to be scaled up by 0x101 to
2178 * match the DC interface which has a range of
2179 * 0 to 0xffff
0cafc82f 2180 */
206bbafe
DF		 2181 brightness =
2182 brightness
2183 * 0x101
2184 * (caps.max_input_signal - caps.min_input_signal)
2185 / AMDGPU_MAX_BL_LEVEL
2186 + caps.min_input_signal * 0x101;
4562236b
HW		 2187
2188 if (dc_link_set_backlight_level(dm->backlight_link,
923fe495 2189 brightness, 0))
4562236b
HW		 2190 return 0;
2191 else
2192 return 1;
2193}
2194
2195static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
2196{
620a0d27
DF		 2197 struct amdgpu_display_manager *dm = bl_get_data(bd);
2198 int ret = dc_link_get_backlight_level(dm->backlight_link);
2199
2200 if (ret == DC_ERROR_UNEXPECTED)
2201 return bd->props.brightness;
2202 return ret;
4562236b
HW		 2203}
2204
2205static const struct backlight_ops amdgpu_dm_backlight_ops = {
c7c5be3c 2206 .options = BL_CORE_SUSPENDRESUME,
4562236b
HW		 2207 .get_brightness = amdgpu_dm_backlight_get_brightness,
2208 .update_status = amdgpu_dm_backlight_update_status,
2209};
2210
7578ecda
AD		 2211static void
2212amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2213{
2214 char bl_name[16];
2215 struct backlight_properties props = { 0 };
2216
206bbafe
DF		 2217 amdgpu_dm_update_backlight_caps(dm);
2218
4562236b 2219 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 2220 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 2221 props.type = BACKLIGHT_RAW;
2222
2223 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
2224 dm->adev->ddev->primary->index);
2225
2226 dm->backlight_dev = backlight_device_register(bl_name,
2227 dm->adev->ddev->dev,
2228 dm,
2229 &amdgpu_dm_backlight_ops,
2230 &props);
2231
74baea42 2232 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 2233 DRM_ERROR("DM: Backlight registration failed!\n");
2234 else
f1ad2f5e 2235 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 2236}
2237
2238#endif
2239
df534fff 2240static int initialize_plane(struct amdgpu_display_manager *dm,
b2fddb13 2241 struct amdgpu_mode_info *mode_info, int plane_id,
cc1fec57
NK		 2242 enum drm_plane_type plane_type,
2243 const struct dc_plane_cap *plane_cap)
df534fff 2244{
f180b4bc 2245 struct drm_plane *plane;
df534fff
S		 2246 unsigned long possible_crtcs;
2247 int ret = 0;
2248
f180b4bc 2249 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 2250 if (!plane) {
2251 DRM_ERROR("KMS: Failed to allocate plane\n");
2252 return -ENOMEM;
2253 }
b2fddb13 2254 plane->type = plane_type;
df534fff
S		 2255
2256 /*
b2fddb13
NK		 2257 * HACK: IGT tests expect that the primary plane for a CRTC
2258 * can only have one possible CRTC. Only expose support for
2259 * any CRTC if they're not going to be used as a primary plane
2260 * for a CRTC - like overlay or underlay planes.
df534fff
S		 2261 */
2262 possible_crtcs = 1 << plane_id;
2263 if (plane_id >= dm->dc->caps.max_streams)
2264 possible_crtcs = 0xff;
2265
cc1fec57 2266 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
df534fff
S		 2267
2268 if (ret) {
2269 DRM_ERROR("KMS: Failed to initialize plane\n");
54087768 2270 kfree(plane);
df534fff
S		 2271 return ret;
2272 }
2273
54087768
NK		 2274 if (mode_info)
2275 mode_info->planes[plane_id] = plane;
2276
df534fff
S		 2277 return ret;
2278}
2279
89fc8d4e
HW		 2280
2281static void register_backlight_device(struct amdgpu_display_manager *dm,
2282 struct dc_link *link)
2283{
2284#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2285 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2286
2287 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2288 link->type != dc_connection_none) {
1f6010a9
DF		 2289 /*
2290 * Event if registration failed, we should continue with
89fc8d4e
HW		 2291 * DM initialization because not having a backlight control
2292 * is better then a black screen.
2293 */
2294 amdgpu_dm_register_backlight_device(dm);
2295
2296 if (dm->backlight_dev)
2297 dm->backlight_link = link;
2298 }
2299#endif
2300}
2301
2302
1f6010a9
DF		 2303/*
2304 * In this architecture, the association
4562236b
HW		 2305 * connector -> encoder -> crtc
2306 * id not really requried. The crtc and connector will hold the
2307 * display_index as an abstraction to use with DAL component
2308 *
2309 * Returns 0 on success
2310 */
7578ecda 2311static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 2312{
2313 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 2314 int32_t i;
c84dec2f 2315 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 2316 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 2317 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 2318 uint32_t link_cnt;
cc1fec57 2319 int32_t primary_planes;
fbbdadf2 2320 enum dc_connection_type new_connection_type = dc_connection_none;
cc1fec57 2321 const struct dc_plane_cap *plane;
4562236b
HW		 2322
2323 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 2324 if (amdgpu_dm_mode_config_init(dm->adev)) {
2325 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 2326 return -EINVAL;
4562236b
HW		 2327 }
2328
b2fddb13
NK		 2329 /* There is one primary plane per CRTC */
2330 primary_planes = dm->dc->caps.max_streams;
54087768 2331 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
efa6a8b7 2332
b2fddb13
NK		 2333 /*
2334 * Initialize primary planes, implicit planes for legacy IOCTLS.
2335 * Order is reversed to match iteration order in atomic check.
2336 */
2337 for (i = (primary_planes - 1); i >= 0; i--) {
cc1fec57
NK		 2338 plane = &dm->dc->caps.planes[i];
2339
b2fddb13 2340 if (initialize_plane(dm, mode_info, i,
cc1fec57 2341 DRM_PLANE_TYPE_PRIMARY, plane)) {
df534fff 2342 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 2343 goto fail;
d4e13b0d 2344 }
df534fff 2345 }
92f3ac40 2346
0d579c7e
NK		 2347 /*
2348 * Initialize overlay planes, index starting after primary planes.
2349 * These planes have a higher DRM index than the primary planes since
2350 * they should be considered as having a higher z-order.
2351 * Order is reversed to match iteration order in atomic check.
cc1fec57
NK		 2352 *
2353 * Only support DCN for now, and only expose one so we don't encourage
2354 * userspace to use up all the pipes.
0d579c7e 2355 */
cc1fec57
NK		 2356 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2357 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2358
2359 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2360 continue;
2361
2362 if (!plane->blends_with_above || !plane->blends_with_below)
2363 continue;
2364
ea36ad34 2365 if (!plane->pixel_format_support.argb8888)
cc1fec57
NK		 2366 continue;
2367
54087768 2368 if (initialize_plane(dm, NULL, primary_planes + i,
cc1fec57 2369 DRM_PLANE_TYPE_OVERLAY, plane)) {
0d579c7e 2370 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 2371 goto fail;
d4e13b0d 2372 }
cc1fec57
NK		 2373
2374 /* Only create one overlay plane. */
2375 break;
d4e13b0d 2376 }
4562236b 2377
d4e13b0d 2378 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 2379 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 2380 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 2381 goto fail;
4562236b 2382 }
4562236b 2383
ab2541b6 2384 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 2385
2386 /* loops over all connectors on the board */
2387 for (i = 0; i < link_cnt; i++) {
89fc8d4e 2388 struct dc_link *link = NULL;
4562236b
HW		 2389
2390 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2391 DRM_ERROR(
2392 "KMS: Cannot support more than %d display indexes\n",
2393 AMDGPU_DM_MAX_DISPLAY_INDEX);
2394 continue;
2395 }
2396
2397 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2398 if (!aconnector)
cd8a2ae8 2399 goto fail;
4562236b
HW		 2400
2401 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 2402 if (!aencoder)
cd8a2ae8 2403 goto fail;
4562236b
HW		 2404
2405 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2406 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 2407 goto fail;
4562236b
HW		 2408 }
2409
2410 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2411 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 2412 goto fail;
4562236b
HW		 2413 }
2414
89fc8d4e
HW		 2415 link = dc_get_link_at_index(dm->dc, i);
2416
fbbdadf2
BL		 2417 if (!dc_link_detect_sink(link, &new_connection_type))
2418 DRM_ERROR("KMS: Failed to detect connector\n");
2419
2420 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2421 emulated_link_detect(link);
2422 amdgpu_dm_update_connector_after_detect(aconnector);
2423
2424 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 2425 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e 2426 register_backlight_device(dm, link);
8c322309 2427 amdgpu_dm_set_psr_caps(link);
89fc8d4e
HW		 2428 }
2429
2430
4562236b
HW		 2431 }
2432
2433 /* Software is initialized. Now we can register interrupt handlers. */
2434 switch (adev->asic_type) {
2435 case CHIP_BONAIRE:
2436 case CHIP_HAWAII:
cd4b356f
AD		 2437 case CHIP_KAVERI:
2438 case CHIP_KABINI:
2439 case CHIP_MULLINS:
4562236b
HW		 2440 case CHIP_TONGA:
2441 case CHIP_FIJI:
2442 case CHIP_CARRIZO:
2443 case CHIP_STONEY:
2444 case CHIP_POLARIS11:
2445 case CHIP_POLARIS10:
b264d345 2446 case CHIP_POLARIS12:
7737de91 2447 case CHIP_VEGAM:
2c8ad2d5 2448 case CHIP_VEGA10:
2325ff30 2449 case CHIP_VEGA12:
1fe6bf2f 2450 case CHIP_VEGA20:
4562236b
HW		 2451 if (dce110_register_irq_handlers(dm->adev)) {
2452 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2453 goto fail;
4562236b
HW		 2454 }
2455 break;
ff5ef992
AD		 2456#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2457 case CHIP_RAVEN:
476e955d 2458#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
fbd2afe5 2459 case CHIP_NAVI12:
476e955d 2460 case CHIP_NAVI10:
fce651e3 2461 case CHIP_NAVI14:
30221ad8
BL		 2462#endif
2463#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2464 case CHIP_RENOIR:
476e955d 2465#endif
ff5ef992
AD		 2466 if (dcn10_register_irq_handlers(dm->adev)) {
2467 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2468 goto fail;
ff5ef992
AD		 2469 }
2470 break;
2471#endif
4562236b 2472 default:
e63f8673 2473 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 2474 goto fail;
4562236b
HW		 2475 }
2476
1bc460a4
HW		 2477 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2478 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2479
4562236b 2480 return 0;
cd8a2ae8 2481fail:
4562236b 2482 kfree(aencoder);
4562236b 2483 kfree(aconnector);
54087768 2484
59d0f396 2485 return -EINVAL;
4562236b
HW		 2486}
2487
7578ecda 2488static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2489{
2490 drm_mode_config_cleanup(dm->ddev);
eb3dc897 2491 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 2492 return;
2493}
2494
2495/******************************************************************************
2496 * amdgpu_display_funcs functions
2497 *****************************************************************************/
2498
1f6010a9 2499/*
4562236b
HW		 2500 * dm_bandwidth_update - program display watermarks
2501 *
2502 * @adev: amdgpu_device pointer
2503 *
2504 * Calculate and program the display watermarks and line buffer allocation.
2505 */
2506static void dm_bandwidth_update(struct amdgpu_device *adev)
2507{
49c07a99 2508 /* TODO: implement later */
4562236b
HW		 2509}
2510
39cc5be2 2511static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 2512 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2513 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 2514 .backlight_set_level = NULL, /* never called for DC */
2515 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 2516 .hpd_sense = NULL,/* called unconditionally */
2517 .hpd_set_polarity = NULL, /* called unconditionally */
2518 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2519 .page_flip_get_scanoutpos =
2520 dm_crtc_get_scanoutpos,/* called unconditionally */
2521 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2522 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2523};
2524
2525#if defined(CONFIG_DEBUG_KERNEL_DC)
2526
3ee6b26b
AD		 2527static ssize_t s3_debug_store(struct device *device,
2528 struct device_attribute *attr,
2529 const char *buf,
2530 size_t count)
4562236b
HW		 2531{
2532 int ret;
2533 int s3_state;
ef1de361 2534 struct drm_device *drm_dev = dev_get_drvdata(device);
4562236b
HW		 2535 struct amdgpu_device *adev = drm_dev->dev_private;
2536
2537 ret = kstrtoint(buf, 0, &s3_state);
2538
2539 if (ret == 0) {
2540 if (s3_state) {
2541 dm_resume(adev);
4562236b
HW		 2542 drm_kms_helper_hotplug_event(adev->ddev);
2543 } else
2544 dm_suspend(adev);
2545 }
2546
2547 return ret == 0 ? count : 0;
2548}
2549
2550DEVICE_ATTR_WO(s3_debug);
2551
2552#endif
2553
2554static int dm_early_init(void *handle)
2555{
2556 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2557
4562236b
HW		 2558 switch (adev->asic_type) {
2559 case CHIP_BONAIRE:
2560 case CHIP_HAWAII:
2561 adev->mode_info.num_crtc = 6;
2562 adev->mode_info.num_hpd = 6;
2563 adev->mode_info.num_dig = 6;
4562236b 2564 break;
cd4b356f
AD		 2565 case CHIP_KAVERI:
2566 adev->mode_info.num_crtc = 4;
2567 adev->mode_info.num_hpd = 6;
2568 adev->mode_info.num_dig = 7;
cd4b356f
AD		 2569 break;
2570 case CHIP_KABINI:
2571 case CHIP_MULLINS:
2572 adev->mode_info.num_crtc = 2;
2573 adev->mode_info.num_hpd = 6;
2574 adev->mode_info.num_dig = 6;
cd4b356f 2575 break;
4562236b
HW		 2576 case CHIP_FIJI:
2577 case CHIP_TONGA:
2578 adev->mode_info.num_crtc = 6;
2579 adev->mode_info.num_hpd = 6;
2580 adev->mode_info.num_dig = 7;
4562236b
HW		 2581 break;
2582 case CHIP_CARRIZO:
2583 adev->mode_info.num_crtc = 3;
2584 adev->mode_info.num_hpd = 6;
2585 adev->mode_info.num_dig = 9;
4562236b
HW		 2586 break;
2587 case CHIP_STONEY:
2588 adev->mode_info.num_crtc = 2;
2589 adev->mode_info.num_hpd = 6;
2590 adev->mode_info.num_dig = 9;
4562236b
HW		 2591 break;
2592 case CHIP_POLARIS11:
b264d345 2593 case CHIP_POLARIS12:
4562236b
HW		 2594 adev->mode_info.num_crtc = 5;
2595 adev->mode_info.num_hpd = 5;
2596 adev->mode_info.num_dig = 5;
4562236b
HW		 2597 break;
2598 case CHIP_POLARIS10:
7737de91 2599 case CHIP_VEGAM:
4562236b
HW		 2600 adev->mode_info.num_crtc = 6;
2601 adev->mode_info.num_hpd = 6;
2602 adev->mode_info.num_dig = 6;
4562236b 2603 break;
2c8ad2d5 2604 case CHIP_VEGA10:
2325ff30 2605 case CHIP_VEGA12:
1fe6bf2f 2606 case CHIP_VEGA20:
2c8ad2d5
AD		 2607 adev->mode_info.num_crtc = 6;
2608 adev->mode_info.num_hpd = 6;
2609 adev->mode_info.num_dig = 6;
2610 break;
ff5ef992
AD		 2611#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2612 case CHIP_RAVEN:
2613 adev->mode_info.num_crtc = 4;
2614 adev->mode_info.num_hpd = 4;
2615 adev->mode_info.num_dig = 4;
ff5ef992 2616 break;
476e955d
HW		 2617#endif
2618#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2619 case CHIP_NAVI10:
fbd2afe5 2620 case CHIP_NAVI12:
476e955d
HW		 2621 adev->mode_info.num_crtc = 6;
2622 adev->mode_info.num_hpd = 6;
2623 adev->mode_info.num_dig = 6;
2624 break;
fce651e3
BL		 2625 case CHIP_NAVI14:
2626 adev->mode_info.num_crtc = 5;
2627 adev->mode_info.num_hpd = 5;
2628 adev->mode_info.num_dig = 5;
2629 break;
30221ad8
BL		 2630#endif
2631#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2632 case CHIP_RENOIR:
2633 adev->mode_info.num_crtc = 4;
2634 adev->mode_info.num_hpd = 4;
2635 adev->mode_info.num_dig = 4;
2636 break;
ff5ef992 2637#endif
4562236b 2638 default:
e63f8673 2639 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 2640 return -EINVAL;
2641 }
2642
c8dd5715
MD		 2643 amdgpu_dm_set_irq_funcs(adev);
2644
39cc5be2
AD		 2645 if (adev->mode_info.funcs == NULL)
2646 adev->mode_info.funcs = &dm_display_funcs;
2647
1f6010a9
DF		 2648 /*
2649 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 2650 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 2651 * amdgpu_device_init()
2652 */
4562236b
HW		 2653#if defined(CONFIG_DEBUG_KERNEL_DC)
2654 device_create_file(
2655 adev->ddev->dev,
2656 &dev_attr_s3_debug);
2657#endif
2658
2659 return 0;
2660}
2661
9b690ef3 2662static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 2663 struct dc_stream_state *new_stream,
2664 struct dc_stream_state *old_stream)
9b690ef3 2665{
e7b07cee
HW		 2666 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2667 return false;
2668
2669 if (!crtc_state->enable)
2670 return false;
2671
2672 return crtc_state->active;
2673}
2674
2675static bool modereset_required(struct drm_crtc_state *crtc_state)
2676{
2677 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2678 return false;
2679
2680 return !crtc_state->enable || !crtc_state->active;
2681}
2682
7578ecda 2683static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 2684{
2685 drm_encoder_cleanup(encoder);
2686 kfree(encoder);
2687}
2688
2689static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2690 .destroy = amdgpu_dm_encoder_destroy,
2691};
2692
e7b07cee 2693
695af5f9
NK		 2694static int fill_dc_scaling_info(const struct drm_plane_state *state,
2695 struct dc_scaling_info *scaling_info)
e7b07cee 2696{
6491f0c0 2697 int scale_w, scale_h;
e7b07cee 2698
695af5f9 2699 memset(scaling_info, 0, sizeof(*scaling_info));
e7b07cee 2700
695af5f9
NK		 2701 /* Source is fixed 16.16 but we ignore mantissa for now... */
2702 scaling_info->src_rect.x = state->src_x >> 16;
2703 scaling_info->src_rect.y = state->src_y >> 16;
e7b07cee 2704
695af5f9
NK		 2705 scaling_info->src_rect.width = state->src_w >> 16;
2706 if (scaling_info->src_rect.width == 0)
2707 return -EINVAL;
2708
2709 scaling_info->src_rect.height = state->src_h >> 16;
2710 if (scaling_info->src_rect.height == 0)
2711 return -EINVAL;
2712
2713 scaling_info->dst_rect.x = state->crtc_x;
2714 scaling_info->dst_rect.y = state->crtc_y;
e7b07cee
HW		 2715
2716 if (state->crtc_w == 0)
695af5f9 2717 return -EINVAL;
e7b07cee 2718
695af5f9 2719 scaling_info->dst_rect.width = state->crtc_w;
e7b07cee
HW		 2720
2721 if (state->crtc_h == 0)
695af5f9 2722 return -EINVAL;
e7b07cee 2723
695af5f9 2724 scaling_info->dst_rect.height = state->crtc_h;
e7b07cee 2725
695af5f9
NK		 2726 /* DRM doesn't specify clipping on destination output. */
2727 scaling_info->clip_rect = scaling_info->dst_rect;
e7b07cee 2728
6491f0c0
NK		 2729 /* TODO: Validate scaling per-format with DC plane caps */
2730 scale_w = scaling_info->dst_rect.width * 1000 /
2731 scaling_info->src_rect.width;
e7b07cee 2732
6491f0c0
NK		 2733 if (scale_w < 250 || scale_w > 16000)
2734 return -EINVAL;
2735
2736 scale_h = scaling_info->dst_rect.height * 1000 /
2737 scaling_info->src_rect.height;
2738
2739 if (scale_h < 250 || scale_h > 16000)
2740 return -EINVAL;
2741
695af5f9
NK		 2742 /*
2743 * The "scaling_quality" can be ignored for now, quality = 0 has DC
2744 * assume reasonable defaults based on the format.
2745 */
e7b07cee 2746
695af5f9 2747 return 0;
4562236b 2748}
695af5f9 2749
3ee6b26b 2750static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 2751 uint64_t *tiling_flags)
e7b07cee 2752{
e68d14dd 2753 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 2754 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 2755
e7b07cee 2756 if (unlikely(r)) {
1f6010a9 2757 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 2758 if (r != -ERESTARTSYS)
2759 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 2760 return r;
2761 }
2762
e7b07cee
HW		 2763 if (tiling_flags)
2764 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2765
2766 amdgpu_bo_unreserve(rbo);
2767
2768 return r;
2769}
2770
7df7e505
NK		 2771static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2772{
2773 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2774
2775 return offset ? (address + offset * 256) : 0;
2776}
2777
695af5f9
NK		 2778static int
2779fill_plane_dcc_attributes(struct amdgpu_device *adev,
2780 const struct amdgpu_framebuffer *afb,
2781 const enum surface_pixel_format format,
2782 const enum dc_rotation_angle rotation,
12e2b2d4 2783 const struct plane_size *plane_size,
695af5f9
NK		 2784 const union dc_tiling_info *tiling_info,
2785 const uint64_t info,
2786 struct dc_plane_dcc_param *dcc,
2787 struct dc_plane_address *address)
7df7e505
NK		 2788{
2789 struct dc *dc = adev->dm.dc;
8daa1218
NC		 2790 struct dc_dcc_surface_param input;
2791 struct dc_surface_dcc_cap output;
7df7e505
NK		 2792 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2793 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2794 uint64_t dcc_address;
2795
8daa1218
NC		 2796 memset(&input, 0, sizeof(input));
2797 memset(&output, 0, sizeof(output));
2798
7df7e505 2799 if (!offset)
09e5665a
NK		 2800 return 0;
2801
695af5f9 2802 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
09e5665a 2803 return 0;
7df7e505
NK		 2804
2805 if (!dc->cap_funcs.get_dcc_compression_cap)
09e5665a 2806 return -EINVAL;
7df7e505 2807
695af5f9 2808 input.format = format;
12e2b2d4
DL		 2809 input.surface_size.width = plane_size->surface_size.width;
2810 input.surface_size.height = plane_size->surface_size.height;
695af5f9 2811 input.swizzle_mode = tiling_info->gfx9.swizzle;
7df7e505 2812
695af5f9 2813 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
7df7e505 2814 input.scan = SCAN_DIRECTION_HORIZONTAL;
695af5f9 2815 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
7df7e505
NK		 2816 input.scan = SCAN_DIRECTION_VERTICAL;
2817
2818 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
09e5665a 2819 return -EINVAL;
7df7e505
NK		 2820
2821 if (!output.capable)
09e5665a 2822 return -EINVAL;
7df7e505
NK		 2823
2824 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
09e5665a 2825 return -EINVAL;
7df7e505 2826
09e5665a 2827 dcc->enable = 1;
12e2b2d4 2828 dcc->meta_pitch =
7df7e505 2829 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
12e2b2d4 2830 dcc->independent_64b_blks = i64b;
7df7e505
NK		 2831
2832 dcc_address = get_dcc_address(afb->address, info);
09e5665a
NK		 2833 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
2834 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
7df7e505 2835
09e5665a
NK		 2836 return 0;
2837}
2838
2839static int
320932bf 2840fill_plane_buffer_attributes(struct amdgpu_device *adev,
09e5665a 2841 const struct amdgpu_framebuffer *afb,
695af5f9
NK		 2842 const enum surface_pixel_format format,
2843 const enum dc_rotation_angle rotation,
2844 const uint64_t tiling_flags,
09e5665a 2845 union dc_tiling_info *tiling_info,
12e2b2d4 2846 struct plane_size *plane_size,
09e5665a 2847 struct dc_plane_dcc_param *dcc,
695af5f9 2848 struct dc_plane_address *address)
09e5665a 2849{
320932bf 2850 const struct drm_framebuffer *fb = &afb->base;
09e5665a
NK		 2851 int ret;
2852
2853 memset(tiling_info, 0, sizeof(*tiling_info));
320932bf 2854 memset(plane_size, 0, sizeof(*plane_size));
09e5665a 2855 memset(dcc, 0, sizeof(*dcc));
e0634e8d
NK		 2856 memset(address, 0, sizeof(*address));
2857
695af5f9 2858 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
12e2b2d4
DL		 2859 plane_size->surface_size.x = 0;
2860 plane_size->surface_size.y = 0;
2861 plane_size->surface_size.width = fb->width;
2862 plane_size->surface_size.height = fb->height;
2863 plane_size->surface_pitch =
320932bf
NK		 2864 fb->pitches[0] / fb->format->cpp[0];
2865
e0634e8d
NK		 2866 address->type = PLN_ADDR_TYPE_GRAPHICS;
2867 address->grph.addr.low_part = lower_32_bits(afb->address);
2868 address->grph.addr.high_part = upper_32_bits(afb->address);
1894478a 2869 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
1791e54f 2870 uint64_t chroma_addr = afb->address + fb->offsets[1];
e0634e8d 2871
12e2b2d4
DL		 2872 plane_size->surface_size.x = 0;
2873 plane_size->surface_size.y = 0;
2874 plane_size->surface_size.width = fb->width;
2875 plane_size->surface_size.height = fb->height;
2876 plane_size->surface_pitch =
320932bf
NK		 2877 fb->pitches[0] / fb->format->cpp[0];
2878
12e2b2d4
DL		 2879 plane_size->chroma_size.x = 0;
2880 plane_size->chroma_size.y = 0;
320932bf 2881 /* TODO: set these based on surface format */
12e2b2d4
DL		 2882 plane_size->chroma_size.width = fb->width / 2;
2883 plane_size->chroma_size.height = fb->height / 2;
320932bf 2884
12e2b2d4 2885 plane_size->chroma_pitch =
320932bf
NK		 2886 fb->pitches[1] / fb->format->cpp[1];
2887
e0634e8d
NK		 2888 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2889 address->video_progressive.luma_addr.low_part =
2890 lower_32_bits(afb->address);
2891 address->video_progressive.luma_addr.high_part =
2892 upper_32_bits(afb->address);
2893 address->video_progressive.chroma_addr.low_part =
2894 lower_32_bits(chroma_addr);
2895 address->video_progressive.chroma_addr.high_part =
2896 upper_32_bits(chroma_addr);
2897 }
09e5665a
NK		 2898
2899 /* Fill GFX8 params */
2900 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2901 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2902
2903 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2904 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2905 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2906 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2907 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2908
2909 /* XXX fix me for VI */
2910 tiling_info->gfx8.num_banks = num_banks;
2911 tiling_info->gfx8.array_mode =
2912 DC_ARRAY_2D_TILED_THIN1;
2913 tiling_info->gfx8.tile_split = tile_split;
2914 tiling_info->gfx8.bank_width = bankw;
2915 tiling_info->gfx8.bank_height = bankh;
2916 tiling_info->gfx8.tile_aspect = mtaspect;
2917 tiling_info->gfx8.tile_mode =
2918 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2919 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2920 == DC_ARRAY_1D_TILED_THIN1) {
2921 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2922 }
2923
2924 tiling_info->gfx8.pipe_config =
2925 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2926
2927 if (adev->asic_type == CHIP_VEGA10 ||
2928 adev->asic_type == CHIP_VEGA12 ||
2929 adev->asic_type == CHIP_VEGA20 ||
476e955d
HW		 2930#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2931 adev->asic_type == CHIP_NAVI10 ||
fce651e3 2932 adev->asic_type == CHIP_NAVI14 ||
fbd2afe5 2933 adev->asic_type == CHIP_NAVI12 ||
30221ad8
BL		 2934#endif
2935#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2936 adev->asic_type == CHIP_RENOIR ||
476e955d 2937#endif
09e5665a
NK		 2938 adev->asic_type == CHIP_RAVEN) {
2939 /* Fill GFX9 params */
2940 tiling_info->gfx9.num_pipes =
2941 adev->gfx.config.gb_addr_config_fields.num_pipes;
2942 tiling_info->gfx9.num_banks =
2943 adev->gfx.config.gb_addr_config_fields.num_banks;
2944 tiling_info->gfx9.pipe_interleave =
2945 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2946 tiling_info->gfx9.num_shader_engines =
2947 adev->gfx.config.gb_addr_config_fields.num_se;
2948 tiling_info->gfx9.max_compressed_frags =
2949 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2950 tiling_info->gfx9.num_rb_per_se =
2951 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2952 tiling_info->gfx9.swizzle =
2953 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2954 tiling_info->gfx9.shaderEnable = 1;
2955
695af5f9
NK		 2956 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
2957 plane_size, tiling_info,
2958 tiling_flags, dcc, address);
09e5665a
NK		 2959 if (ret)
2960 return ret;
2961 }
2962
2963 return 0;
7df7e505
NK		 2964}
2965
d74004b6 2966static void
695af5f9 2967fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
d74004b6
NK		 2968 bool *per_pixel_alpha, bool *global_alpha,
2969 int *global_alpha_value)
2970{
2971 *per_pixel_alpha = false;
2972 *global_alpha = false;
2973 *global_alpha_value = 0xff;
2974
2975 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
2976 return;
2977
2978 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
2979 static const uint32_t alpha_formats[] = {
2980 DRM_FORMAT_ARGB8888,
2981 DRM_FORMAT_RGBA8888,
2982 DRM_FORMAT_ABGR8888,
2983 };
2984 uint32_t format = plane_state->fb->format->format;
2985 unsigned int i;
2986
2987 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
2988 if (format == alpha_formats[i]) {
2989 *per_pixel_alpha = true;
2990 break;
2991 }
2992 }
2993 }
2994
2995 if (plane_state->alpha < 0xffff) {
2996 *global_alpha = true;
2997 *global_alpha_value = plane_state->alpha >> 8;
2998 }
2999}
3000
004fefa3
NK		 3001static int
3002fill_plane_color_attributes(const struct drm_plane_state *plane_state,
695af5f9 3003 const enum surface_pixel_format format,
004fefa3
NK		 3004 enum dc_color_space *color_space)
3005{
3006 bool full_range;
3007
3008 *color_space = COLOR_SPACE_SRGB;
3009
3010 /* DRM color properties only affect non-RGB formats. */
695af5f9 3011 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
004fefa3
NK		 3012 return 0;
3013
3014 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
3015
3016 switch (plane_state->color_encoding) {
3017 case DRM_COLOR_YCBCR_BT601:
3018 if (full_range)
3019 *color_space = COLOR_SPACE_YCBCR601;
3020 else
3021 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
3022 break;
3023
3024 case DRM_COLOR_YCBCR_BT709:
3025 if (full_range)
3026 *color_space = COLOR_SPACE_YCBCR709;
3027 else
3028 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
3029 break;
3030
3031 case DRM_COLOR_YCBCR_BT2020:
3032 if (full_range)
3033 *color_space = COLOR_SPACE_2020_YCBCR;
3034 else
3035 return -EINVAL;
3036 break;
3037
3038 default:
3039 return -EINVAL;
3040 }
3041
3042 return 0;
3043}
3044
695af5f9
NK		 3045static int
3046fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
3047 const struct drm_plane_state *plane_state,
3048 const uint64_t tiling_flags,
3049 struct dc_plane_info *plane_info,
3050 struct dc_plane_address *address)
3051{
3052 const struct drm_framebuffer *fb = plane_state->fb;
3053 const struct amdgpu_framebuffer *afb =
3054 to_amdgpu_framebuffer(plane_state->fb);
3055 struct drm_format_name_buf format_name;
3056 int ret;
3057
3058 memset(plane_info, 0, sizeof(*plane_info));
3059
3060 switch (fb->format->format) {
3061 case DRM_FORMAT_C8:
3062 plane_info->format =
3063 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
3064 break;
3065 case DRM_FORMAT_RGB565:
3066 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
3067 break;
3068 case DRM_FORMAT_XRGB8888:
3069 case DRM_FORMAT_ARGB8888:
3070 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
3071 break;
3072 case DRM_FORMAT_XRGB2101010:
3073 case DRM_FORMAT_ARGB2101010:
3074 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
3075 break;
3076 case DRM_FORMAT_XBGR2101010:
3077 case DRM_FORMAT_ABGR2101010:
3078 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
3079 break;
3080 case DRM_FORMAT_XBGR8888:
3081 case DRM_FORMAT_ABGR8888:
3082 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
3083 break;
3084 case DRM_FORMAT_NV21:
3085 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
3086 break;
3087 case DRM_FORMAT_NV12:
3088 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
3089 break;
3090 default:
3091 DRM_ERROR(
3092 "Unsupported screen format %s\n",
3093 drm_get_format_name(fb->format->format, &format_name));
3094 return -EINVAL;
3095 }
3096
3097 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
3098 case DRM_MODE_ROTATE_0:
3099 plane_info->rotation = ROTATION_ANGLE_0;
3100 break;
3101 case DRM_MODE_ROTATE_90:
3102 plane_info->rotation = ROTATION_ANGLE_90;
3103 break;
3104 case DRM_MODE_ROTATE_180:
3105 plane_info->rotation = ROTATION_ANGLE_180;
3106 break;
3107 case DRM_MODE_ROTATE_270:
3108 plane_info->rotation = ROTATION_ANGLE_270;
3109 break;
3110 default:
3111 plane_info->rotation = ROTATION_ANGLE_0;
3112 break;
3113 }
3114
3115 plane_info->visible = true;
3116 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
3117
6d83a32d
MS		 3118 plane_info->layer_index = 0;
3119
695af5f9
NK		 3120 ret = fill_plane_color_attributes(plane_state, plane_info->format,
3121 &plane_info->color_space);
3122 if (ret)
3123 return ret;
3124
3125 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
3126 plane_info->rotation, tiling_flags,
3127 &plane_info->tiling_info,
3128 &plane_info->plane_size,
3129 &plane_info->dcc, address);
3130 if (ret)
3131 return ret;
3132
3133 fill_blending_from_plane_state(
3134 plane_state, &plane_info->per_pixel_alpha,
3135 &plane_info->global_alpha, &plane_info->global_alpha_value);
3136
3137 return 0;
3138}
3139
3140static int fill_dc_plane_attributes(struct amdgpu_device *adev,
3141 struct dc_plane_state *dc_plane_state,
3142 struct drm_plane_state *plane_state,
3143 struct drm_crtc_state *crtc_state)
e7b07cee 3144{
cf020d49 3145 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
e7b07cee
HW		 3146 const struct amdgpu_framebuffer *amdgpu_fb =
3147 to_amdgpu_framebuffer(plane_state->fb);
695af5f9
NK		 3148 struct dc_scaling_info scaling_info;
3149 struct dc_plane_info plane_info;
3150 uint64_t tiling_flags;
3151 int ret;
e7b07cee 3152
695af5f9
NK		 3153 ret = fill_dc_scaling_info(plane_state, &scaling_info);
3154 if (ret)
3155 return ret;
e7b07cee 3156
695af5f9
NK		 3157 dc_plane_state->src_rect = scaling_info.src_rect;
3158 dc_plane_state->dst_rect = scaling_info.dst_rect;
3159 dc_plane_state->clip_rect = scaling_info.clip_rect;
3160 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
e7b07cee 3161
695af5f9 3162 ret = get_fb_info(amdgpu_fb, &tiling_flags);
e7b07cee
HW		 3163 if (ret)
3164 return ret;
3165
695af5f9
NK		 3166 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3167 &plane_info,
3168 &dc_plane_state->address);
004fefa3
NK		 3169 if (ret)
3170 return ret;
3171
695af5f9
NK		 3172 dc_plane_state->format = plane_info.format;
3173 dc_plane_state->color_space = plane_info.color_space;
3174 dc_plane_state->format = plane_info.format;
3175 dc_plane_state->plane_size = plane_info.plane_size;
3176 dc_plane_state->rotation = plane_info.rotation;
3177 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
3178 dc_plane_state->stereo_format = plane_info.stereo_format;
3179 dc_plane_state->tiling_info = plane_info.tiling_info;
3180 dc_plane_state->visible = plane_info.visible;
3181 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
3182 dc_plane_state->global_alpha = plane_info.global_alpha;
3183 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
3184 dc_plane_state->dcc = plane_info.dcc;
6d83a32d 3185 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
695af5f9 3186
e277adc5
LSL		 3187 /*
3188 * Always set input transfer function, since plane state is refreshed
3189 * every time.
3190 */
cf020d49
NK		 3191 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
3192 if (ret)
3193 return ret;
e7b07cee 3194
cf020d49 3195 return 0;
e7b07cee
HW		 3196}
3197
3ee6b26b
AD		 3198static void update_stream_scaling_settings(const struct drm_display_mode *mode,
3199 const struct dm_connector_state *dm_state,
3200 struct dc_stream_state *stream)
e7b07cee
HW		 3201{
3202 enum amdgpu_rmx_type rmx_type;
3203
3204 struct rect src = { 0 }; /* viewport in composition space*/
3205 struct rect dst = { 0 }; /* stream addressable area */
3206
3207 /* no mode. nothing to be done */
3208 if (!mode)
3209 return;
3210
3211 /* Full screen scaling by default */
3212 src.width = mode->hdisplay;
3213 src.height = mode->vdisplay;
3214 dst.width = stream->timing.h_addressable;
3215 dst.height = stream->timing.v_addressable;
3216
f4791779
HW		 3217 if (dm_state) {
3218 rmx_type = dm_state->scaling;
3219 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
3220 if (src.width * dst.height <
3221 src.height * dst.width) {
3222 /* height needs less upscaling/more downscaling */
3223 dst.width = src.width *
3224 dst.height / src.height;
3225 } else {
3226 /* width needs less upscaling/more downscaling */
3227 dst.height = src.height *
3228 dst.width / src.width;
3229 }
3230 } else if (rmx_type == RMX_CENTER) {
3231 dst = src;
e7b07cee 3232 }
e7b07cee 3233
f4791779
HW		 3234 dst.x = (stream->timing.h_addressable - dst.width) / 2;
3235 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 3236
f4791779
HW		 3237 if (dm_state->underscan_enable) {
3238 dst.x += dm_state->underscan_hborder / 2;
3239 dst.y += dm_state->underscan_vborder / 2;
3240 dst.width -= dm_state->underscan_hborder;
3241 dst.height -= dm_state->underscan_vborder;
3242 }
e7b07cee
HW		 3243 }
3244
3245 stream->src = src;
3246 stream->dst = dst;
3247
f1ad2f5e 3248 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 3249 dst.x, dst.y, dst.width, dst.height);
3250
3251}
3252
3ee6b26b 3253static enum dc_color_depth
42ba01fc
NK		 3254convert_color_depth_from_display_info(const struct drm_connector *connector,
3255 const struct drm_connector_state *state)
e7b07cee 3256{
01c22997
NK		 3257 uint8_t bpc = (uint8_t)connector->display_info.bpc;
3258
3259 /* Assume 8 bpc by default if no bpc is specified. */
3260 bpc = bpc ? bpc : 8;
e7b07cee 3261
01933ba4
NK		 3262 if (!state)
3263 state = connector->state;
3264
42ba01fc 3265 if (state) {
01c22997
NK		 3266 /*
3267 * Cap display bpc based on the user requested value.
3268 *
3269 * The value for state->max_bpc may not correctly updated
3270 * depending on when the connector gets added to the state
3271 * or if this was called outside of atomic check, so it
3272 * can't be used directly.
3273 */
3274 bpc = min(bpc, state->max_requested_bpc);
3275
1825fd34
NK		 3276 /* Round down to the nearest even number. */
3277 bpc = bpc - (bpc & 1);
3278 }
07e3a1cf 3279
e7b07cee
HW		 3280 switch (bpc) {
3281 case 0:
1f6010a9
DF		 3282 /*
3283 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 3284 * EDID revision before 1.4
3285 * TODO: Fix edid parsing
3286 */
3287 return COLOR_DEPTH_888;
3288 case 6:
3289 return COLOR_DEPTH_666;
3290 case 8:
3291 return COLOR_DEPTH_888;
3292 case 10:
3293 return COLOR_DEPTH_101010;
3294 case 12:
3295 return COLOR_DEPTH_121212;
3296 case 14:
3297 return COLOR_DEPTH_141414;
3298 case 16:
3299 return COLOR_DEPTH_161616;
3300 default:
3301 return COLOR_DEPTH_UNDEFINED;
3302 }
3303}
3304
3ee6b26b
AD		 3305static enum dc_aspect_ratio
3306get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 3307{
e11d4147
LSL		 3308 /* 1-1 mapping, since both enums follow the HDMI spec. */
3309 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 3310}
3311
3ee6b26b
AD		 3312static enum dc_color_space
3313get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 3314{
3315 enum dc_color_space color_space = COLOR_SPACE_SRGB;
3316
3317 switch (dc_crtc_timing->pixel_encoding) {
3318 case PIXEL_ENCODING_YCBCR422:
3319 case PIXEL_ENCODING_YCBCR444:
3320 case PIXEL_ENCODING_YCBCR420:
3321 {
3322 /*
3323 * 27030khz is the separation point between HDTV and SDTV
3324 * according to HDMI spec, we use YCbCr709 and YCbCr601
3325 * respectively
3326 */
380604e2 3327 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 3328 if (dc_crtc_timing->flags.Y_ONLY)
3329 color_space =
3330 COLOR_SPACE_YCBCR709_LIMITED;
3331 else
3332 color_space = COLOR_SPACE_YCBCR709;
3333 } else {
3334 if (dc_crtc_timing->flags.Y_ONLY)
3335 color_space =
3336 COLOR_SPACE_YCBCR601_LIMITED;
3337 else
3338 color_space = COLOR_SPACE_YCBCR601;
3339 }
3340
3341 }
3342 break;
3343 case PIXEL_ENCODING_RGB:
3344 color_space = COLOR_SPACE_SRGB;
3345 break;
3346
3347 default:
3348 WARN_ON(1);
3349 break;
3350 }
3351
3352 return color_space;
3353}
3354
400443e8
ML		 3355static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
3356{
3357 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3358 return;
3359
3360 timing_out->display_color_depth--;
3361}
3362
3363static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
3364 const struct drm_display_info *info)
3365{
3366 int normalized_clk;
3367 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3368 return;
3369 do {
380604e2 3370 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 3371 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3372 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3373 normalized_clk /= 2;
3374 /* Adjusting pix clock following on HDMI spec based on colour depth */
3375 switch (timing_out->display_color_depth) {
3376 case COLOR_DEPTH_101010:
3377 normalized_clk = (normalized_clk * 30) / 24;
3378 break;
3379 case COLOR_DEPTH_121212:
3380 normalized_clk = (normalized_clk * 36) / 24;
3381 break;
3382 case COLOR_DEPTH_161616:
3383 normalized_clk = (normalized_clk * 48) / 24;
3384 break;
3385 default:
3386 return;
3387 }
3388 if (normalized_clk <= info->max_tmds_clock)
3389 return;
3390 reduce_mode_colour_depth(timing_out);
3391
3392 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
3393
3394}
e7b07cee 3395
42ba01fc
NK		 3396static void fill_stream_properties_from_drm_display_mode(
3397 struct dc_stream_state *stream,
3398 const struct drm_display_mode *mode_in,
3399 const struct drm_connector *connector,
3400 const struct drm_connector_state *connector_state,
3401 const struct dc_stream_state *old_stream)
e7b07cee
HW		 3402{
3403 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 3404 const struct drm_display_info *info = &connector->display_info;
d4252eee 3405 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1cb1d477
WL		 3406 struct hdmi_vendor_infoframe hv_frame;
3407 struct hdmi_avi_infoframe avi_frame;
e7b07cee 3408
acf83f86
WL		 3409 memset(&hv_frame, 0, sizeof(hv_frame));
3410 memset(&avi_frame, 0, sizeof(avi_frame));
3411
e7b07cee
HW		 3412 timing_out->h_border_left = 0;
3413 timing_out->h_border_right = 0;
3414 timing_out->v_border_top = 0;
3415 timing_out->v_border_bottom = 0;
3416 /* TODO: un-hardcode */
fe61a2f1 3417 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 3418 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1 3419 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
d4252eee
SW		 3420 else if (drm_mode_is_420_also(info, mode_in)
3421 && aconnector->force_yuv420_output)
3422 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
fe61a2f1 3423 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
ceb3dbb4 3424 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 3425 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3426 else
3427 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3428
3429 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3430 timing_out->display_color_depth = convert_color_depth_from_display_info(
42ba01fc 3431 connector, connector_state);
e7b07cee
HW		 3432 timing_out->scan_type = SCANNING_TYPE_NODATA;
3433 timing_out->hdmi_vic = 0;
b333730d
BL		 3434
3435 if(old_stream) {
3436 timing_out->vic = old_stream->timing.vic;
3437 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3438 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3439 } else {
3440 timing_out->vic = drm_match_cea_mode(mode_in);
3441 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3442 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3443 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3444 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3445 }
e7b07cee 3446
1cb1d477
WL		 3447 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3448 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
3449 timing_out->vic = avi_frame.video_code;
3450 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
3451 timing_out->hdmi_vic = hv_frame.vic;
3452 }
3453
e7b07cee
HW		 3454 timing_out->h_addressable = mode_in->crtc_hdisplay;
3455 timing_out->h_total = mode_in->crtc_htotal;
3456 timing_out->h_sync_width =
3457 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3458 timing_out->h_front_porch =
3459 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3460 timing_out->v_total = mode_in->crtc_vtotal;
3461 timing_out->v_addressable = mode_in->crtc_vdisplay;
3462 timing_out->v_front_porch =
3463 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3464 timing_out->v_sync_width =
3465 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
380604e2 3466 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
e7b07cee 3467 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 3468
3469 stream->output_color_space = get_output_color_space(timing_out);
3470
e43a432c
AK		 3471 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3472 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ceb3dbb4 3473 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
400443e8 3474 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 3475}
3476
3ee6b26b
AD		 3477static void fill_audio_info(struct audio_info *audio_info,
3478 const struct drm_connector *drm_connector,
3479 const struct dc_sink *dc_sink)
e7b07cee
HW		 3480{
3481 int i = 0;
3482 int cea_revision = 0;
3483 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3484
3485 audio_info->manufacture_id = edid_caps->manufacturer_id;
3486 audio_info->product_id = edid_caps->product_id;
3487
3488 cea_revision = drm_connector->display_info.cea_rev;
3489
090afc1e 3490 strscpy(audio_info->display_name,
d2b2562c 3491 edid_caps->display_name,
090afc1e 3492 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 3493
b830ebc9 3494 if (cea_revision >= 3) {
e7b07cee
HW		 3495 audio_info->mode_count = edid_caps->audio_mode_count;
3496
3497 for (i = 0; i < audio_info->mode_count; ++i) {
3498 audio_info->modes[i].format_code =
3499 (enum audio_format_code)
3500 (edid_caps->audio_modes[i].format_code);
3501 audio_info->modes[i].channel_count =
3502 edid_caps->audio_modes[i].channel_count;
3503 audio_info->modes[i].sample_rates.all =
3504 edid_caps->audio_modes[i].sample_rate;
3505 audio_info->modes[i].sample_size =
3506 edid_caps->audio_modes[i].sample_size;
3507 }
3508 }
3509
3510 audio_info->flags.all = edid_caps->speaker_flags;
3511
3512 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 3513 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 3514 audio_info->video_latency = drm_connector->video_latency[0];
3515 audio_info->audio_latency = drm_connector->audio_latency[0];
3516 }
3517
3518 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3519
3520}
3521
3ee6b26b
AD		 3522static void
3523copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3524 struct drm_display_mode *dst_mode)
e7b07cee
HW		 3525{
3526 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3527 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3528 dst_mode->crtc_clock = src_mode->crtc_clock;
3529 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3530 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 3531 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 3532 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3533 dst_mode->crtc_htotal = src_mode->crtc_htotal;
3534 dst_mode->crtc_hskew = src_mode->crtc_hskew;
3535 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3536 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3537 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3538 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3539 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3540}
3541
3ee6b26b
AD		 3542static void
3543decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3544 const struct drm_display_mode *native_mode,
3545 bool scale_enabled)
e7b07cee
HW		 3546{
3547 if (scale_enabled) {
3548 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3549 } else if (native_mode->clock == drm_mode->clock &&
3550 native_mode->htotal == drm_mode->htotal &&
3551 native_mode->vtotal == drm_mode->vtotal) {
3552 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3553 } else {
3554 /* no scaling nor amdgpu inserted, no need to patch */
3555 }
3556}
3557
aed15309
ML		 3558static struct dc_sink *
3559create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 3560{
2e0ac3d6 3561 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 3562 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 3563 sink_init_data.link = aconnector->dc_link;
3564 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3565
3566 sink = dc_sink_create(&sink_init_data);
423788c7 3567 if (!sink) {
2e0ac3d6 3568 DRM_ERROR("Failed to create sink!\n");
aed15309 3569 return NULL;
423788c7 3570 }
2e0ac3d6 3571 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 3572
aed15309 3573 return sink;
2e0ac3d6
HW		 3574}
3575
fa2123db
ML		 3576static void set_multisync_trigger_params(
3577 struct dc_stream_state *stream)
3578{
3579 if (stream->triggered_crtc_reset.enabled) {
3580 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3581 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3582 }
3583}
3584
3585static void set_master_stream(struct dc_stream_state *stream_set[],
3586 int stream_count)
3587{
3588 int j, highest_rfr = 0, master_stream = 0;
3589
3590 for (j = 0; j < stream_count; j++) {
3591 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3592 int refresh_rate = 0;
3593
380604e2 3594 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 3595 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3596 if (refresh_rate > highest_rfr) {
3597 highest_rfr = refresh_rate;
3598 master_stream = j;
3599 }
3600 }
3601 }
3602 for (j = 0; j < stream_count; j++) {
03736f4c 3603 if (stream_set[j])
fa2123db
ML		 3604 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3605 }
3606}
3607
3608static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3609{
3610 int i = 0;
3611
3612 if (context->stream_count < 2)
3613 return;
3614 for (i = 0; i < context->stream_count ; i++) {
3615 if (!context->streams[i])
3616 continue;
1f6010a9
DF		 3617 /*
3618 * TODO: add a function to read AMD VSDB bits and set
fa2123db 3619 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 3620 * For now it's set to false
fa2123db
ML		 3621 */
3622 set_multisync_trigger_params(context->streams[i]);
3623 }
3624 set_master_stream(context->streams, context->stream_count);
3625}
3626
3ee6b26b
AD		 3627static struct dc_stream_state *
3628create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3629 const struct drm_display_mode *drm_mode,
b333730d
BL		 3630 const struct dm_connector_state *dm_state,
3631 const struct dc_stream_state *old_stream)
e7b07cee
HW		 3632{
3633 struct drm_display_mode *preferred_mode = NULL;
391ef035 3634 struct drm_connector *drm_connector;
42ba01fc
NK		 3635 const struct drm_connector_state *con_state =
3636 dm_state ? &dm_state->base : NULL;
0971c40e 3637 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 3638 struct drm_display_mode mode = *drm_mode;
3639 bool native_mode_found = false;
b333730d
BL		 3640 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3641 int mode_refresh;
58124bf8 3642 int preferred_refresh = 0;
df2f1015
DF		 3643#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3644 struct dsc_dec_dpcd_caps dsc_caps;
3645 uint32_t link_bandwidth_kbps;
3646#endif
b333730d 3647
aed15309 3648 struct dc_sink *sink = NULL;
b830ebc9 3649 if (aconnector == NULL) {
e7b07cee 3650 DRM_ERROR("aconnector is NULL!\n");
64245fa7 3651 return stream;
e7b07cee
HW		 3652 }
3653
e7b07cee 3654 drm_connector = &aconnector->base;
2e0ac3d6 3655
f4ac176e 3656 if (!aconnector->dc_sink) {
e3fa5c4c
JFZ		 3657 sink = create_fake_sink(aconnector);
3658 if (!sink)
3659 return stream;
aed15309
ML		 3660 } else {
3661 sink = aconnector->dc_sink;
dcd5fb82 3662 dc_sink_retain(sink);
f4ac176e 3663 }
2e0ac3d6 3664
aed15309 3665 stream = dc_create_stream_for_sink(sink);
4562236b 3666
b830ebc9 3667 if (stream == NULL) {
e7b07cee 3668 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 3669 goto finish;
e7b07cee
HW		 3670 }
3671
ceb3dbb4
JL		 3672 stream->dm_stream_context = aconnector;
3673
4a36fcba
WL		 3674 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
3675 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
3676
e7b07cee
HW		 3677 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3678 /* Search for preferred mode */
3679 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3680 native_mode_found = true;
3681 break;
3682 }
3683 }
3684 if (!native_mode_found)
3685 preferred_mode = list_first_entry_or_null(
3686 &aconnector->base.modes,
3687 struct drm_display_mode,
3688 head);
3689
b333730d
BL		 3690 mode_refresh = drm_mode_vrefresh(&mode);
3691
b830ebc9 3692 if (preferred_mode == NULL) {
1f6010a9
DF		 3693 /*
3694 * This may not be an error, the use case is when we have no
e7b07cee
HW		 3695 * usermode calls to reset and set mode upon hotplug. In this
3696 * case, we call set mode ourselves to restore the previous mode
3697 * and the modelist may not be filled in in time.
3698 */
f1ad2f5e 3699 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 3700 } else {
3701 decide_crtc_timing_for_drm_display_mode(
3702 &mode, preferred_mode,
f4791779 3703 dm_state ? (dm_state->scaling != RMX_OFF) : false);
58124bf8 3704 preferred_refresh = drm_mode_vrefresh(preferred_mode);
e7b07cee
HW		 3705 }
3706
f783577c
JFZ		 3707 if (!dm_state)
3708 drm_mode_set_crtcinfo(&mode, 0);
3709
b333730d
BL		 3710 /*
3711 * If scaling is enabled and refresh rate didn't change
3712 * we copy the vic and polarities of the old timings
3713 */
3714 if (!scale || mode_refresh != preferred_refresh)
3715 fill_stream_properties_from_drm_display_mode(stream,
42ba01fc 3716 &mode, &aconnector->base, con_state, NULL);
b333730d
BL		 3717 else
3718 fill_stream_properties_from_drm_display_mode(stream,
42ba01fc 3719 &mode, &aconnector->base, con_state, old_stream);
b333730d 3720
39a4eb85 3721#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
df2f1015
DF		 3722 stream->timing.flags.DSC = 0;
3723
3724 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3725 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3726 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
3727 &dsc_caps);
3728 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
3729 dc_link_get_link_cap(aconnector->dc_link));
3730
3731 if (dsc_caps.is_dsc_supported)
0417df16 3732 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
df2f1015 3733 &dsc_caps,
0417df16 3734 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
df2f1015
DF		 3735 link_bandwidth_kbps,
3736 &stream->timing,
3737 &stream->timing.dsc_cfg))
3738 stream->timing.flags.DSC = 1;
3739 }
39a4eb85
WL		 3740#endif
3741
e7b07cee
HW		 3742 update_stream_scaling_settings(&mode, dm_state, stream);
3743
3744 fill_audio_info(
3745 &stream->audio_info,
3746 drm_connector,
aed15309 3747 sink);
e7b07cee 3748
ceb3dbb4 3749 update_stream_signal(stream, sink);
9182b4cb 3750
d832fc3b
WL		 3751 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3752 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false);
8c322309
RL		 3753 if (stream->link->psr_feature_enabled) {
3754 struct dc *core_dc = stream->link->ctx->dc;
d832fc3b 3755
8c322309
RL		 3756 if (dc_is_dmcu_initialized(core_dc)) {
3757 struct dmcu *dmcu = core_dc->res_pool->dmcu;
3758
3759 stream->psr_version = dmcu->dmcu_version.psr_version;
3760 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
3761 }
3762 }
aed15309 3763finish:
dcd5fb82 3764 dc_sink_release(sink);
9e3efe3e 3765
e7b07cee
HW		 3766 return stream;
3767}
3768
7578ecda 3769static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 3770{
3771 drm_crtc_cleanup(crtc);
3772 kfree(crtc);
3773}
3774
3775static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 3776 struct drm_crtc_state *state)
e7b07cee
HW		 3777{
3778 struct dm_crtc_state *cur = to_dm_crtc_state(state);
3779
3780 /* TODO Destroy dc_stream objects are stream object is flattened */
3781 if (cur->stream)
3782 dc_stream_release(cur->stream);
3783
3784
3785 __drm_atomic_helper_crtc_destroy_state(state);
3786
3787
3788 kfree(state);
3789}
3790
3791static void dm_crtc_reset_state(struct drm_crtc *crtc)
3792{
3793 struct dm_crtc_state *state;
3794
3795 if (crtc->state)
3796 dm_crtc_destroy_state(crtc, crtc->state);
3797
3798 state = kzalloc(sizeof(*state), GFP_KERNEL);
3799 if (WARN_ON(!state))
3800 return;
3801
3802 crtc->state = &state->base;
3803 crtc->state->crtc = crtc;
3804
3805}
3806
3807static struct drm_crtc_state *
3808dm_crtc_duplicate_state(struct drm_crtc *crtc)
3809{
3810 struct dm_crtc_state *state, *cur;
3811
3812 cur = to_dm_crtc_state(crtc->state);
3813
3814 if (WARN_ON(!crtc->state))
3815 return NULL;
3816
2004f45e 3817 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 3818 if (!state)
3819 return NULL;
e7b07cee
HW		 3820
3821 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3822
3823 if (cur->stream) {
3824 state->stream = cur->stream;
3825 dc_stream_retain(state->stream);
3826 }
3827
d6ef9b41
NK		 3828 state->active_planes = cur->active_planes;
3829 state->interrupts_enabled = cur->interrupts_enabled;
180db303 3830 state->vrr_params = cur->vrr_params;
98e6436d 3831 state->vrr_infopacket = cur->vrr_infopacket;
c1ee92f9 3832 state->abm_level = cur->abm_level;
bb47de73
NK		 3833 state->vrr_supported = cur->vrr_supported;
3834 state->freesync_config = cur->freesync_config;
14b25846 3835 state->crc_src = cur->crc_src;
cf020d49
NK		 3836 state->cm_has_degamma = cur->cm_has_degamma;
3837 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
98e6436d 3838
e7b07cee
HW		 3839 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3840
3841 return &state->base;
3842}
3843
d2574c33
MK		 3844static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
3845{
3846 enum dc_irq_source irq_source;
3847 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3848 struct amdgpu_device *adev = crtc->dev->dev_private;
3849 int rc;
3850
3851 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
3852
3853 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3854
3855 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
3856 acrtc->crtc_id, enable ? "en" : "dis", rc);
3857 return rc;
3858}
589d2739
HW		 3859
3860static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3861{
3862 enum dc_irq_source irq_source;
3863 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3864 struct amdgpu_device *adev = crtc->dev->dev_private;
d2574c33
MK		 3865 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3866 int rc = 0;
3867
3868 if (enable) {
3869 /* vblank irq on -> Only need vupdate irq in vrr mode */
3870 if (amdgpu_dm_vrr_active(acrtc_state))
3871 rc = dm_set_vupdate_irq(crtc, true);
3872 } else {
3873 /* vblank irq off -> vupdate irq off */
3874 rc = dm_set_vupdate_irq(crtc, false);
3875 }
3876
3877 if (rc)
3878 return rc;
589d2739
HW		 3879
3880 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 3881 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 3882}
3883
3884static int dm_enable_vblank(struct drm_crtc *crtc)
3885{
3886 return dm_set_vblank(crtc, true);
3887}
3888
3889static void dm_disable_vblank(struct drm_crtc *crtc)
3890{
3891 dm_set_vblank(crtc, false);
3892}
3893
e7b07cee
HW		 3894/* Implemented only the options currently availible for the driver */
3895static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3896 .reset = dm_crtc_reset_state,
3897 .destroy = amdgpu_dm_crtc_destroy,
3898 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3899 .set_config = drm_atomic_helper_set_config,
3900 .page_flip = drm_atomic_helper_page_flip,
3901 .atomic_duplicate_state = dm_crtc_duplicate_state,
3902 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 3903 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 3904 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
8fb843d1 3905 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
589d2739
HW		 3906 .enable_vblank = dm_enable_vblank,
3907 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 3908};
3909
3910static enum drm_connector_status
3911amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3912{
3913 bool connected;
c84dec2f 3914 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 3915
1f6010a9
DF		 3916 /*
3917 * Notes:
e7b07cee
HW		 3918 * 1. This interface is NOT called in context of HPD irq.
3919 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 3920 * makes it a bad place for *any* MST-related activity.
3921 */
e7b07cee 3922
8580d60b
HW		 3923 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3924 !aconnector->fake_enable)
e7b07cee
HW		 3925 connected = (aconnector->dc_sink != NULL);
3926 else
3927 connected = (aconnector->base.force == DRM_FORCE_ON);
3928
3929 return (connected ? connector_status_connected :
3930 connector_status_disconnected);
3931}
3932
3ee6b26b
AD		 3933int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3934 struct drm_connector_state *connector_state,
3935 struct drm_property *property,
3936 uint64_t val)
e7b07cee
HW		 3937{
3938 struct drm_device *dev = connector->dev;
3939 struct amdgpu_device *adev = dev->dev_private;
3940 struct dm_connector_state *dm_old_state =
3941 to_dm_connector_state(connector->state);
3942 struct dm_connector_state *dm_new_state =
3943 to_dm_connector_state(connector_state);
3944
3945 int ret = -EINVAL;
3946
3947 if (property == dev->mode_config.scaling_mode_property) {
3948 enum amdgpu_rmx_type rmx_type;
3949
3950 switch (val) {
3951 case DRM_MODE_SCALE_CENTER:
3952 rmx_type = RMX_CENTER;
3953 break;
3954 case DRM_MODE_SCALE_ASPECT:
3955 rmx_type = RMX_ASPECT;
3956 break;
3957 case DRM_MODE_SCALE_FULLSCREEN:
3958 rmx_type = RMX_FULL;
3959 break;
3960 case DRM_MODE_SCALE_NONE:
3961 default:
3962 rmx_type = RMX_OFF;
3963 break;
3964 }
3965
3966 if (dm_old_state->scaling == rmx_type)
3967 return 0;
3968
3969 dm_new_state->scaling = rmx_type;
3970 ret = 0;
3971 } else if (property == adev->mode_info.underscan_hborder_property) {
3972 dm_new_state->underscan_hborder = val;
3973 ret = 0;
3974 } else if (property == adev->mode_info.underscan_vborder_property) {
3975 dm_new_state->underscan_vborder = val;
3976 ret = 0;
3977 } else if (property == adev->mode_info.underscan_property) {
3978 dm_new_state->underscan_enable = val;
3979 ret = 0;
c1ee92f9
DF		 3980 } else if (property == adev->mode_info.abm_level_property) {
3981 dm_new_state->abm_level = val;
3982 ret = 0;
e7b07cee
HW		 3983 }
3984
3985 return ret;
3986}
3987
3ee6b26b
AD		 3988int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3989 const struct drm_connector_state *state,
3990 struct drm_property *property,
3991 uint64_t *val)
e7b07cee
HW		 3992{
3993 struct drm_device *dev = connector->dev;
3994 struct amdgpu_device *adev = dev->dev_private;
3995 struct dm_connector_state *dm_state =
3996 to_dm_connector_state(state);
3997 int ret = -EINVAL;
3998
3999 if (property == dev->mode_config.scaling_mode_property) {
4000 switch (dm_state->scaling) {
4001 case RMX_CENTER:
4002 *val = DRM_MODE_SCALE_CENTER;
4003 break;
4004 case RMX_ASPECT:
4005 *val = DRM_MODE_SCALE_ASPECT;
4006 break;
4007 case RMX_FULL:
4008 *val = DRM_MODE_SCALE_FULLSCREEN;
4009 break;
4010 case RMX_OFF:
4011 default:
4012 *val = DRM_MODE_SCALE_NONE;
4013 break;
4014 }
4015 ret = 0;
4016 } else if (property == adev->mode_info.underscan_hborder_property) {
4017 *val = dm_state->underscan_hborder;
4018 ret = 0;
4019 } else if (property == adev->mode_info.underscan_vborder_property) {
4020 *val = dm_state->underscan_vborder;
4021 ret = 0;
4022 } else if (property == adev->mode_info.underscan_property) {
4023 *val = dm_state->underscan_enable;
4024 ret = 0;
c1ee92f9
DF		 4025 } else if (property == adev->mode_info.abm_level_property) {
4026 *val = dm_state->abm_level;
4027 ret = 0;
e7b07cee 4028 }
c1ee92f9 4029
e7b07cee
HW		 4030 return ret;
4031}
4032
526c654a
ED		 4033static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
4034{
4035 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
4036
4037 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
4038}
4039
7578ecda 4040static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 4041{
c84dec2f 4042 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4043 const struct dc_link *link = aconnector->dc_link;
4044 struct amdgpu_device *adev = connector->dev->dev_private;
4045 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 4046
e7b07cee
HW		 4047#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
4048 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
4049
89fc8d4e 4050 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 4051 link->type != dc_connection_none &&
4052 dm->backlight_dev) {
4053 backlight_device_unregister(dm->backlight_dev);
4054 dm->backlight_dev = NULL;
e7b07cee
HW		 4055 }
4056#endif
dcd5fb82
MF		 4057
4058 if (aconnector->dc_em_sink)
4059 dc_sink_release(aconnector->dc_em_sink);
4060 aconnector->dc_em_sink = NULL;
4061 if (aconnector->dc_sink)
4062 dc_sink_release(aconnector->dc_sink);
4063 aconnector->dc_sink = NULL;
4064
e86e8947 4065 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 4066 drm_connector_unregister(connector);
4067 drm_connector_cleanup(connector);
526c654a
ED		 4068 if (aconnector->i2c) {
4069 i2c_del_adapter(&aconnector->i2c->base);
4070 kfree(aconnector->i2c);
4071 }
4072
e7b07cee
HW		 4073 kfree(connector);
4074}
4075
4076void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
4077{
4078 struct dm_connector_state *state =
4079 to_dm_connector_state(connector->state);
4080
df099b9b
LSL		 4081 if (connector->state)
4082 __drm_atomic_helper_connector_destroy_state(connector->state);
4083
e7b07cee
HW		 4084 kfree(state);
4085
4086 state = kzalloc(sizeof(*state), GFP_KERNEL);
4087
4088 if (state) {
4089 state->scaling = RMX_OFF;
4090 state->underscan_enable = false;
4091 state->underscan_hborder = 0;
4092 state->underscan_vborder = 0;
01933ba4 4093 state->base.max_requested_bpc = 8;
e7b07cee 4094
c3e50f89
NK		 4095 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4096 state->abm_level = amdgpu_dm_abm_level;
4097
df099b9b 4098 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 4099 }
4100}
4101
3ee6b26b
AD		 4102struct drm_connector_state *
4103amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 4104{
4105 struct dm_connector_state *state =
4106 to_dm_connector_state(connector->state);
4107
4108 struct dm_connector_state *new_state =
4109 kmemdup(state, sizeof(*state), GFP_KERNEL);
4110
98e6436d
AK		 4111 if (!new_state)
4112 return NULL;
e7b07cee 4113
98e6436d
AK		 4114 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
4115
4116 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 4117 new_state->abm_level = state->abm_level;
922454c2
NK		 4118 new_state->scaling = state->scaling;
4119 new_state->underscan_enable = state->underscan_enable;
4120 new_state->underscan_hborder = state->underscan_hborder;
4121 new_state->underscan_vborder = state->underscan_vborder;
98e6436d
AK		 4122
4123 return &new_state->base;
e7b07cee
HW		 4124}
4125
4126static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
4127 .reset = amdgpu_dm_connector_funcs_reset,
4128 .detect = amdgpu_dm_connector_detect,
4129 .fill_modes = drm_helper_probe_single_connector_modes,
4130 .destroy = amdgpu_dm_connector_destroy,
4131 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
4132 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4133 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
526c654a
ED		 4134 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
4135 .early_unregister = amdgpu_dm_connector_unregister
e7b07cee
HW		 4136};
4137
e7b07cee
HW		 4138static int get_modes(struct drm_connector *connector)
4139{
4140 return amdgpu_dm_connector_get_modes(connector);
4141}
4142
c84dec2f 4143static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 4144{
4145 struct dc_sink_init_data init_params = {
4146 .link = aconnector->dc_link,
4147 .sink_signal = SIGNAL_TYPE_VIRTUAL
4148 };
70e8ffc5 4149 struct edid *edid;
e7b07cee 4150
a89ff457 4151 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 4152 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
4153 aconnector->base.name);
4154
4155 aconnector->base.force = DRM_FORCE_OFF;
4156 aconnector->base.override_edid = false;
4157 return;
4158 }
4159
70e8ffc5
HW		 4160 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
4161
e7b07cee
HW		 4162 aconnector->edid = edid;
4163
4164 aconnector->dc_em_sink = dc_link_add_remote_sink(
4165 aconnector->dc_link,
4166 (uint8_t *)edid,
4167 (edid->extensions + 1) * EDID_LENGTH,
4168 &init_params);
4169
dcd5fb82 4170 if (aconnector->base.force == DRM_FORCE_ON) {
e7b07cee
HW		 4171 aconnector->dc_sink = aconnector->dc_link->local_sink ?
4172 aconnector->dc_link->local_sink :
4173 aconnector->dc_em_sink;
dcd5fb82
MF		 4174 dc_sink_retain(aconnector->dc_sink);
4175 }
e7b07cee
HW		 4176}
4177
c84dec2f 4178static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 4179{
4180 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
4181
1f6010a9
DF		 4182 /*
4183 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 4184 * Those settings have to be != 0 to get initial modeset
4185 */
4186 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4187 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
4188 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
4189 }
4190
4191
4192 aconnector->base.override_edid = true;
4193 create_eml_sink(aconnector);
4194}
4195
ba9ca088 4196enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 4197 struct drm_display_mode *mode)
e7b07cee
HW		 4198{
4199 int result = MODE_ERROR;
4200 struct dc_sink *dc_sink;
4201 struct amdgpu_device *adev = connector->dev->dev_private;
4202 /* TODO: Unhardcode stream count */
0971c40e 4203 struct dc_stream_state *stream;
c84dec2f 4204 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 4205 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 4206
4207 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
4208 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
4209 return result;
4210
1f6010a9
DF		 4211 /*
4212 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 4213 * EDID mgmt
4214 */
4215 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
4216 !aconnector->dc_em_sink)
4217 handle_edid_mgmt(aconnector);
4218
c84dec2f 4219 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 4220
b830ebc9 4221 if (dc_sink == NULL) {
e7b07cee
HW		 4222 DRM_ERROR("dc_sink is NULL!\n");
4223 goto fail;
4224 }
4225
b333730d 4226 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
b830ebc9 4227 if (stream == NULL) {
e7b07cee
HW		 4228 DRM_ERROR("Failed to create stream for sink!\n");
4229 goto fail;
4230 }
4231
a39438f0
HW		 4232 dc_result = dc_validate_stream(adev->dm.dc, stream);
4233
4234 if (dc_result == DC_OK)
e7b07cee 4235 result = MODE_OK;
a39438f0 4236 else
9f921b14 4237 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 4238 mode->vdisplay,
4239 mode->hdisplay,
9f921b14
HW		 4240 mode->clock,
4241 dc_result);
e7b07cee
HW		 4242
4243 dc_stream_release(stream);
4244
4245fail:
4246 /* TODO: error handling*/
4247 return result;
4248}
4249
88694af9
NK		 4250static int fill_hdr_info_packet(const struct drm_connector_state *state,
4251 struct dc_info_packet *out)
4252{
4253 struct hdmi_drm_infoframe frame;
4254 unsigned char buf[30]; /* 26 + 4 */
4255 ssize_t len;
4256 int ret, i;
4257
4258 memset(out, 0, sizeof(*out));
4259
4260 if (!state->hdr_output_metadata)
4261 return 0;
4262
4263 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
4264 if (ret)
4265 return ret;
4266
4267 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
4268 if (len < 0)
4269 return (int)len;
4270
4271 /* Static metadata is a fixed 26 bytes + 4 byte header. */
4272 if (len != 30)
4273 return -EINVAL;
4274
4275 /* Prepare the infopacket for DC. */
4276 switch (state->connector->connector_type) {
4277 case DRM_MODE_CONNECTOR_HDMIA:
4278 out->hb0 = 0x87; /* type */
4279 out->hb1 = 0x01; /* version */
4280 out->hb2 = 0x1A; /* length */
4281 out->sb[0] = buf[3]; /* checksum */
4282 i = 1;
4283 break;
4284
4285 case DRM_MODE_CONNECTOR_DisplayPort:
4286 case DRM_MODE_CONNECTOR_eDP:
4287 out->hb0 = 0x00; /* sdp id, zero */
4288 out->hb1 = 0x87; /* type */
4289 out->hb2 = 0x1D; /* payload len - 1 */
4290 out->hb3 = (0x13 << 2); /* sdp version */
4291 out->sb[0] = 0x01; /* version */
4292 out->sb[1] = 0x1A; /* length */
4293 i = 2;
4294 break;
4295
4296 default:
4297 return -EINVAL;
4298 }
4299
4300 memcpy(&out->sb[i], &buf[4], 26);
4301 out->valid = true;
4302
4303 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
4304 sizeof(out->sb), false);
4305
4306 return 0;
4307}
4308
4309static bool
4310is_hdr_metadata_different(const struct drm_connector_state *old_state,
4311 const struct drm_connector_state *new_state)
4312{
4313 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
4314 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
4315
4316 if (old_blob != new_blob) {
4317 if (old_blob && new_blob &&
4318 old_blob->length == new_blob->length)
4319 return memcmp(old_blob->data, new_blob->data,
4320 old_blob->length);
4321
4322 return true;
4323 }
4324
4325 return false;
4326}
4327
4328static int
4329amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
51e857af 4330 struct drm_atomic_state *state)
88694af9 4331{
51e857af
SP		 4332 struct drm_connector_state *new_con_state =
4333 drm_atomic_get_new_connector_state(state, conn);
88694af9
NK		 4334 struct drm_connector_state *old_con_state =
4335 drm_atomic_get_old_connector_state(state, conn);
4336 struct drm_crtc *crtc = new_con_state->crtc;
4337 struct drm_crtc_state *new_crtc_state;
4338 int ret;
4339
4340 if (!crtc)
4341 return 0;
4342
4343 if (is_hdr_metadata_different(old_con_state, new_con_state)) {
4344 struct dc_info_packet hdr_infopacket;
4345
4346 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
4347 if (ret)
4348 return ret;
4349
4350 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
4351 if (IS_ERR(new_crtc_state))
4352 return PTR_ERR(new_crtc_state);
4353
4354 /*
4355 * DC considers the stream backends changed if the
4356 * static metadata changes. Forcing the modeset also
4357 * gives a simple way for userspace to switch from
b232d4ed
NK		 4358 * 8bpc to 10bpc when setting the metadata to enter
4359 * or exit HDR.
4360 *
4361 * Changing the static metadata after it's been
4362 * set is permissible, however. So only force a
4363 * modeset if we're entering or exiting HDR.
88694af9 4364 */
b232d4ed
NK		 4365 new_crtc_state->mode_changed =
4366 !old_con_state->hdr_output_metadata ||
4367 !new_con_state->hdr_output_metadata;
88694af9
NK		 4368 }
4369
4370 return 0;
4371}
4372
e7b07cee
HW		 4373static const struct drm_connector_helper_funcs
4374amdgpu_dm_connector_helper_funcs = {
4375 /*
1f6010a9 4376 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 4377 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 4378 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 4379 * in get_modes call back, not just return the modes count
4380 */
e7b07cee
HW		 4381 .get_modes = get_modes,
4382 .mode_valid = amdgpu_dm_connector_mode_valid,
88694af9 4383 .atomic_check = amdgpu_dm_connector_atomic_check,
e7b07cee
HW		 4384};
4385
4386static void dm_crtc_helper_disable(struct drm_crtc *crtc)
4387{
4388}
4389
bc92c065
NK		 4390static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
4391{
4392 struct drm_device *dev = new_crtc_state->crtc->dev;
4393 struct drm_plane *plane;
4394
4395 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
4396 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4397 return true;
4398 }
4399
4400 return false;
4401}
4402
d6ef9b41 4403static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
c14a005c
NK		 4404{
4405 struct drm_atomic_state *state = new_crtc_state->state;
4406 struct drm_plane *plane;
4407 int num_active = 0;
4408
4409 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
4410 struct drm_plane_state *new_plane_state;
4411
4412 /* Cursor planes are "fake". */
4413 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4414 continue;
4415
4416 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
4417
4418 if (!new_plane_state) {
4419 /*
4420 * The plane is enable on the CRTC and hasn't changed
4421 * state. This means that it previously passed
4422 * validation and is therefore enabled.
4423 */
4424 num_active += 1;
4425 continue;
4426 }
4427
4428 /* We need a framebuffer to be considered enabled. */
4429 num_active += (new_plane_state->fb != NULL);
4430 }
4431
d6ef9b41
NK		 4432 return num_active;
4433}
4434
4435/*
4436 * Sets whether interrupts should be enabled on a specific CRTC.
4437 * We require that the stream be enabled and that there exist active
4438 * DC planes on the stream.
4439 */
4440static void
4441dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
4442 struct drm_crtc_state *new_crtc_state)
4443{
4444 struct dm_crtc_state *dm_new_crtc_state =
4445 to_dm_crtc_state(new_crtc_state);
4446
4447 dm_new_crtc_state->active_planes = 0;
4448 dm_new_crtc_state->interrupts_enabled = false;
4449
4450 if (!dm_new_crtc_state->stream)
4451 return;
4452
4453 dm_new_crtc_state->active_planes =
4454 count_crtc_active_planes(new_crtc_state);
4455
4456 dm_new_crtc_state->interrupts_enabled =
4457 dm_new_crtc_state->active_planes > 0;
c14a005c
NK		 4458}
4459
3ee6b26b
AD		 4460static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
4461 struct drm_crtc_state *state)
e7b07cee
HW		 4462{
4463 struct amdgpu_device *adev = crtc->dev->dev_private;
4464 struct dc *dc = adev->dm.dc;
4465 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
4466 int ret = -EINVAL;
4467
d6ef9b41
NK		 4468 /*
4469 * Update interrupt state for the CRTC. This needs to happen whenever
4470 * the CRTC has changed or whenever any of its planes have changed.
4471 * Atomic check satisfies both of these requirements since the CRTC
4472 * is added to the state by DRM during drm_atomic_helper_check_planes.
4473 */
4474 dm_update_crtc_interrupt_state(crtc, state);
4475
9b690ef3
BL		 4476 if (unlikely(!dm_crtc_state->stream &&
4477 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 4478 WARN_ON(1);
4479 return ret;
4480 }
4481
1f6010a9 4482 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 4483 if (!dm_crtc_state->stream)
4484 return 0;
4485
bc92c065
NK		 4486 /*
4487 * We want at least one hardware plane enabled to use
4488 * the stream with a cursor enabled.
4489 */
c14a005c 4490 if (state->enable && state->active &&
bc92c065 4491 does_crtc_have_active_cursor(state) &&
d6ef9b41 4492 dm_crtc_state->active_planes == 0)
c14a005c
NK		 4493 return -EINVAL;
4494
62c933f9 4495 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 4496 return 0;
4497
4498 return ret;
4499}
4500
3ee6b26b
AD		 4501static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4502 const struct drm_display_mode *mode,
4503 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 4504{
4505 return true;
4506}
4507
4508static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4509 .disable = dm_crtc_helper_disable,
4510 .atomic_check = dm_crtc_helper_atomic_check,
4511 .mode_fixup = dm_crtc_helper_mode_fixup
4512};
4513
4514static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4515{
4516
4517}
4518
3ee6b26b
AD		 4519static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4520 struct drm_crtc_state *crtc_state,
4521 struct drm_connector_state *conn_state)
e7b07cee
HW		 4522{
4523 return 0;
4524}
4525
4526const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4527 .disable = dm_encoder_helper_disable,
4528 .atomic_check = dm_encoder_helper_atomic_check
4529};
4530
4531static void dm_drm_plane_reset(struct drm_plane *plane)
4532{
4533 struct dm_plane_state *amdgpu_state = NULL;
4534
4535 if (plane->state)
4536 plane->funcs->atomic_destroy_state(plane, plane->state);
4537
4538 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 4539 WARN_ON(amdgpu_state == NULL);
1f6010a9 4540
7ddaef96
NK		 4541 if (amdgpu_state)
4542 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
e7b07cee
HW		 4543}
4544
4545static struct drm_plane_state *
4546dm_drm_plane_duplicate_state(struct drm_plane *plane)
4547{
4548 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4549
4550 old_dm_plane_state = to_dm_plane_state(plane->state);
4551 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4552 if (!dm_plane_state)
4553 return NULL;
4554
4555 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4556
3be5262e
HW		 4557 if (old_dm_plane_state->dc_state) {
4558 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4559 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 4560 }
4561
4562 return &dm_plane_state->base;
4563}
4564
4565void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 4566 struct drm_plane_state *state)
e7b07cee
HW		 4567{
4568 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4569
3be5262e
HW		 4570 if (dm_plane_state->dc_state)
4571 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 4572
0627bbd3 4573 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 4574}
4575
4576static const struct drm_plane_funcs dm_plane_funcs = {
4577 .update_plane = drm_atomic_helper_update_plane,
4578 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 4579 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 4580 .reset = dm_drm_plane_reset,
4581 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
4582 .atomic_destroy_state = dm_drm_plane_destroy_state,
4583};
4584
3ee6b26b
AD		 4585static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
4586 struct drm_plane_state *new_state)
e7b07cee
HW		 4587{
4588 struct amdgpu_framebuffer *afb;
4589 struct drm_gem_object *obj;
5d43be0c 4590 struct amdgpu_device *adev;
e7b07cee 4591 struct amdgpu_bo *rbo;
e7b07cee 4592 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
0f257b09
CZ		 4593 struct list_head list;
4594 struct ttm_validate_buffer tv;
4595 struct ww_acquire_ctx ticket;
e0634e8d 4596 uint64_t tiling_flags;
5d43be0c
CK		 4597 uint32_t domain;
4598 int r;
e7b07cee
HW		 4599
4600 dm_plane_state_old = to_dm_plane_state(plane->state);
4601 dm_plane_state_new = to_dm_plane_state(new_state);
4602
4603 if (!new_state->fb) {
f1ad2f5e 4604 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 4605 return 0;
4606 }
4607
4608 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 4609 obj = new_state->fb->obj[0];
e7b07cee 4610 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 4611 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
0f257b09
CZ		 4612 INIT_LIST_HEAD(&list);
4613
4614 tv.bo = &rbo->tbo;
4615 tv.num_shared = 1;
4616 list_add(&tv.head, &list);
4617
4618 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true);
4619 if (r) {
4620 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
e7b07cee 4621 return r;
0f257b09 4622 }
e7b07cee 4623
5d43be0c 4624 if (plane->type != DRM_PLANE_TYPE_CURSOR)
f2bd8a0e 4625 domain = amdgpu_display_supported_domains(adev, rbo->flags);
5d43be0c
CK		 4626 else
4627 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 4628
7b7c6c81 4629 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 4630 if (unlikely(r != 0)) {
30b7c614
HW		 4631 if (r != -ERESTARTSYS)
4632 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
0f257b09 4633 ttm_eu_backoff_reservation(&ticket, &list);
e7b07cee
HW		 4634 return r;
4635 }
4636
bb812f1e
JZ		 4637 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
4638 if (unlikely(r != 0)) {
4639 amdgpu_bo_unpin(rbo);
0f257b09 4640 ttm_eu_backoff_reservation(&ticket, &list);
bb812f1e 4641 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 4642 return r;
4643 }
7df7e505
NK		 4644
4645 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
4646
0f257b09 4647 ttm_eu_backoff_reservation(&ticket, &list);
bb812f1e 4648
7b7c6c81 4649 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 4650
4651 amdgpu_bo_ref(rbo);
4652
3be5262e
HW		 4653 if (dm_plane_state_new->dc_state &&
4654 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
4655 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 4656
320932bf 4657 fill_plane_buffer_attributes(
695af5f9
NK		 4658 adev, afb, plane_state->format, plane_state->rotation,
4659 tiling_flags, &plane_state->tiling_info,
320932bf 4660 &plane_state->plane_size, &plane_state->dcc,
695af5f9 4661 &plane_state->address);
e7b07cee
HW		 4662 }
4663
e7b07cee
HW		 4664 return 0;
4665}
4666
3ee6b26b
AD		 4667static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
4668 struct drm_plane_state *old_state)
e7b07cee
HW		 4669{
4670 struct amdgpu_bo *rbo;
e7b07cee
HW		 4671 int r;
4672
4673 if (!old_state->fb)
4674 return;
4675
e68d14dd 4676 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 4677 r = amdgpu_bo_reserve(rbo, false);
4678 if (unlikely(r)) {
4679 DRM_ERROR("failed to reserve rbo before unpin\n");
4680 return;
b830ebc9
HW		 4681 }
4682
4683 amdgpu_bo_unpin(rbo);
4684 amdgpu_bo_unreserve(rbo);
4685 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 4686}
4687
7578ecda
AD		 4688static int dm_plane_atomic_check(struct drm_plane *plane,
4689 struct drm_plane_state *state)
cbd19488
AG		 4690{
4691 struct amdgpu_device *adev = plane->dev->dev_private;
4692 struct dc *dc = adev->dm.dc;
78171832 4693 struct dm_plane_state *dm_plane_state;
695af5f9
NK		 4694 struct dc_scaling_info scaling_info;
4695 int ret;
78171832
NK		 4696
4697 dm_plane_state = to_dm_plane_state(state);
cbd19488 4698
3be5262e 4699 if (!dm_plane_state->dc_state)
9a3329b1 4700 return 0;
cbd19488 4701
695af5f9
NK		 4702 ret = fill_dc_scaling_info(state, &scaling_info);
4703 if (ret)
4704 return ret;
a05bcff1 4705
62c933f9 4706 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 4707 return 0;
4708
4709 return -EINVAL;
4710}
4711
674e78ac
NK		 4712static int dm_plane_atomic_async_check(struct drm_plane *plane,
4713 struct drm_plane_state *new_plane_state)
4714{
4715 /* Only support async updates on cursor planes. */
4716 if (plane->type != DRM_PLANE_TYPE_CURSOR)
4717 return -EINVAL;
4718
4719 return 0;
4720}
4721
4722static void dm_plane_atomic_async_update(struct drm_plane *plane,
4723 struct drm_plane_state *new_state)
4724{
4725 struct drm_plane_state *old_state =
4726 drm_atomic_get_old_plane_state(new_state->state, plane);
4727
332af874 4728 swap(plane->state->fb, new_state->fb);
674e78ac
NK		 4729
4730 plane->state->src_x = new_state->src_x;
4731 plane->state->src_y = new_state->src_y;
4732 plane->state->src_w = new_state->src_w;
4733 plane->state->src_h = new_state->src_h;
4734 plane->state->crtc_x = new_state->crtc_x;
4735 plane->state->crtc_y = new_state->crtc_y;
4736 plane->state->crtc_w = new_state->crtc_w;
4737 plane->state->crtc_h = new_state->crtc_h;
4738
4739 handle_cursor_update(plane, old_state);
4740}
4741
e7b07cee
HW		 4742static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
4743 .prepare_fb = dm_plane_helper_prepare_fb,
4744 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 4745 .atomic_check = dm_plane_atomic_check,
674e78ac
NK		 4746 .atomic_async_check = dm_plane_atomic_async_check,
4747 .atomic_async_update = dm_plane_atomic_async_update
e7b07cee
HW		 4748};
4749
4750/*
4751 * TODO: these are currently initialized to rgb formats only.
4752 * For future use cases we should either initialize them dynamically based on
4753 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 4754 * check will succeed, and let DC implement proper check
e7b07cee 4755 */
d90371b0 4756static const uint32_t rgb_formats[] = {
e7b07cee
HW		 4757 DRM_FORMAT_XRGB8888,
4758 DRM_FORMAT_ARGB8888,
4759 DRM_FORMAT_RGBA8888,
4760 DRM_FORMAT_XRGB2101010,
4761 DRM_FORMAT_XBGR2101010,
4762 DRM_FORMAT_ARGB2101010,
4763 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 4764 DRM_FORMAT_XBGR8888,
4765 DRM_FORMAT_ABGR8888,
46dd9ff7 4766 DRM_FORMAT_RGB565,
e7b07cee
HW		 4767};
4768
0d579c7e
NK		 4769static const uint32_t overlay_formats[] = {
4770 DRM_FORMAT_XRGB8888,
4771 DRM_FORMAT_ARGB8888,
4772 DRM_FORMAT_RGBA8888,
4773 DRM_FORMAT_XBGR8888,
4774 DRM_FORMAT_ABGR8888,
7267a1a9 4775 DRM_FORMAT_RGB565
e7b07cee
HW		 4776};
4777
4778static const u32 cursor_formats[] = {
4779 DRM_FORMAT_ARGB8888
4780};
4781
37c6a93b
NK		 4782static int get_plane_formats(const struct drm_plane *plane,
4783 const struct dc_plane_cap *plane_cap,
4784 uint32_t *formats, int max_formats)
e7b07cee 4785{
37c6a93b
NK		 4786 int i, num_formats = 0;
4787
4788 /*
4789 * TODO: Query support for each group of formats directly from
4790 * DC plane caps. This will require adding more formats to the
4791 * caps list.
4792 */
e7b07cee 4793
f180b4bc 4794 switch (plane->type) {
e7b07cee 4795 case DRM_PLANE_TYPE_PRIMARY:
37c6a93b
NK		 4796 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
4797 if (num_formats >= max_formats)
4798 break;
4799
4800 formats[num_formats++] = rgb_formats[i];
4801 }
4802
ea36ad34 4803 if (plane_cap && plane_cap->pixel_format_support.nv12)
37c6a93b 4804 formats[num_formats++] = DRM_FORMAT_NV12;
e7b07cee 4805 break;
37c6a93b 4806
e7b07cee 4807 case DRM_PLANE_TYPE_OVERLAY:
37c6a93b
NK		 4808 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
4809 if (num_formats >= max_formats)
4810 break;
4811
4812 formats[num_formats++] = overlay_formats[i];
4813 }
e7b07cee 4814 break;
37c6a93b 4815
e7b07cee 4816 case DRM_PLANE_TYPE_CURSOR:
37c6a93b
NK		 4817 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
4818 if (num_formats >= max_formats)
4819 break;
4820
4821 formats[num_formats++] = cursor_formats[i];
4822 }
e7b07cee
HW		 4823 break;
4824 }
4825
37c6a93b
NK		 4826 return num_formats;
4827}
4828
4829static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4830 struct drm_plane *plane,
4831 unsigned long possible_crtcs,
4832 const struct dc_plane_cap *plane_cap)
4833{
4834 uint32_t formats[32];
4835 int num_formats;
4836 int res = -EPERM;
4837
4838 num_formats = get_plane_formats(plane, plane_cap, formats,
4839 ARRAY_SIZE(formats));
4840
4841 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
4842 &dm_plane_funcs, formats, num_formats,
4843 NULL, plane->type, NULL);
4844 if (res)
4845 return res;
4846
cc1fec57
NK		 4847 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4848 plane_cap && plane_cap->per_pixel_alpha) {
d74004b6
NK		 4849 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4850 BIT(DRM_MODE_BLEND_PREMULTI);
4851
4852 drm_plane_create_alpha_property(plane);
4853 drm_plane_create_blend_mode_property(plane, blend_caps);
4854 }
4855
fc8e5230 4856 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
ea36ad34 4857 plane_cap && plane_cap->pixel_format_support.nv12) {
fc8e5230
NK		 4858 /* This only affects YUV formats. */
4859 drm_plane_create_color_properties(
4860 plane,
4861 BIT(DRM_COLOR_YCBCR_BT601) |
4862 BIT(DRM_COLOR_YCBCR_BT709),
4863 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
4864 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
4865 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
4866 }
4867
f180b4bc 4868 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 4869
96719c54 4870 /* Create (reset) the plane state */
f180b4bc
HW		 4871 if (plane->funcs->reset)
4872 plane->funcs->reset(plane);
96719c54 4873
37c6a93b 4874 return 0;
e7b07cee
HW		 4875}
4876
7578ecda
AD		 4877static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
4878 struct drm_plane *plane,
4879 uint32_t crtc_index)
e7b07cee
HW		 4880{
4881 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 4882 struct drm_plane *cursor_plane;
e7b07cee
HW		 4883
4884 int res = -ENOMEM;
4885
4886 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
4887 if (!cursor_plane)
4888 goto fail;
4889
f180b4bc 4890 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
cc1fec57 4891 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
e7b07cee
HW		 4892
4893 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
4894 if (!acrtc)
4895 goto fail;
4896
4897 res = drm_crtc_init_with_planes(
4898 dm->ddev,
4899 &acrtc->base,
4900 plane,
f180b4bc 4901 cursor_plane,
e7b07cee
HW		 4902 &amdgpu_dm_crtc_funcs, NULL);
4903
4904 if (res)
4905 goto fail;
4906
4907 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
4908
96719c54
HW		 4909 /* Create (reset) the plane state */
4910 if (acrtc->base.funcs->reset)
4911 acrtc->base.funcs->reset(&acrtc->base);
4912
e7b07cee
HW		 4913 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
4914 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4915
4916 acrtc->crtc_id = crtc_index;
4917 acrtc->base.enabled = false;
c37e2d29 4918 acrtc->otg_inst = -1;
e7b07cee
HW		 4919
4920 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 4921 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
4922 true, MAX_COLOR_LUT_ENTRIES);
086247a4 4923 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 4924
4925 return 0;
4926
4927fail:
b830ebc9
HW		 4928 kfree(acrtc);
4929 kfree(cursor_plane);
e7b07cee
HW		 4930 return res;
4931}
4932
4933
4934static int to_drm_connector_type(enum signal_type st)
4935{
4936 switch (st) {
4937 case SIGNAL_TYPE_HDMI_TYPE_A:
4938 return DRM_MODE_CONNECTOR_HDMIA;
4939 case SIGNAL_TYPE_EDP:
4940 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 4941 case SIGNAL_TYPE_LVDS:
4942 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 4943 case SIGNAL_TYPE_RGB:
4944 return DRM_MODE_CONNECTOR_VGA;
4945 case SIGNAL_TYPE_DISPLAY_PORT:
4946 case SIGNAL_TYPE_DISPLAY_PORT_MST:
4947 return DRM_MODE_CONNECTOR_DisplayPort;
4948 case SIGNAL_TYPE_DVI_DUAL_LINK:
4949 case SIGNAL_TYPE_DVI_SINGLE_LINK:
4950 return DRM_MODE_CONNECTOR_DVID;
4951 case SIGNAL_TYPE_VIRTUAL:
4952 return DRM_MODE_CONNECTOR_VIRTUAL;
4953
4954 default:
4955 return DRM_MODE_CONNECTOR_Unknown;
4956 }
4957}
4958
2b4c1c05
DV		 4959static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
4960{
4961 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
4962}
4963
e7b07cee
HW		 4964static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
4965{
e7b07cee
HW		 4966 struct drm_encoder *encoder;
4967 struct amdgpu_encoder *amdgpu_encoder;
4968
2b4c1c05 4969 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 4970
4971 if (encoder == NULL)
4972 return;
4973
4974 amdgpu_encoder = to_amdgpu_encoder(encoder);
4975
4976 amdgpu_encoder->native_mode.clock = 0;
4977
4978 if (!list_empty(&connector->probed_modes)) {
4979 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 4980
e7b07cee 4981 list_for_each_entry(preferred_mode,
b830ebc9
HW		 4982 &connector->probed_modes,
4983 head) {
4984 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
4985 amdgpu_encoder->native_mode = *preferred_mode;
4986
e7b07cee
HW		 4987 break;
4988 }
4989
4990 }
4991}
4992
3ee6b26b
AD		 4993static struct drm_display_mode *
4994amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4995 char *name,
4996 int hdisplay, int vdisplay)
e7b07cee
HW		 4997{
4998 struct drm_device *dev = encoder->dev;
4999 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
5000 struct drm_display_mode *mode = NULL;
5001 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
5002
5003 mode = drm_mode_duplicate(dev, native_mode);
5004
b830ebc9 5005 if (mode == NULL)
e7b07cee
HW		 5006 return NULL;
5007
5008 mode->hdisplay = hdisplay;
5009 mode->vdisplay = vdisplay;
5010 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 5011 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 5012
5013 return mode;
5014
5015}
5016
5017static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 5018 struct drm_connector *connector)
e7b07cee
HW		 5019{
5020 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
5021 struct drm_display_mode *mode = NULL;
5022 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 5023 struct amdgpu_dm_connector *amdgpu_dm_connector =
5024 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5025 int i;
5026 int n;
5027 struct mode_size {
5028 char name[DRM_DISPLAY_MODE_LEN];
5029 int w;
5030 int h;
b830ebc9 5031 } common_modes[] = {
e7b07cee
HW		 5032 { "640x480", 640, 480},
5033 { "800x600", 800, 600},
5034 { "1024x768", 1024, 768},
5035 { "1280x720", 1280, 720},
5036 { "1280x800", 1280, 800},
5037 {"1280x1024", 1280, 1024},
5038 { "1440x900", 1440, 900},
5039 {"1680x1050", 1680, 1050},
5040 {"1600x1200", 1600, 1200},
5041 {"1920x1080", 1920, 1080},
5042 {"1920x1200", 1920, 1200}
5043 };
5044
b830ebc9 5045 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 5046
5047 for (i = 0; i < n; i++) {
5048 struct drm_display_mode *curmode = NULL;
5049 bool mode_existed = false;
5050
5051 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 5052 common_modes[i].h > native_mode->vdisplay ||
5053 (common_modes[i].w == native_mode->hdisplay &&
5054 common_modes[i].h == native_mode->vdisplay))
5055 continue;
e7b07cee
HW		 5056
5057 list_for_each_entry(curmode, &connector->probed_modes, head) {
5058 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 5059 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 5060 mode_existed = true;
5061 break;
5062 }
5063 }
5064
5065 if (mode_existed)
5066 continue;
5067
5068 mode = amdgpu_dm_create_common_mode(encoder,
5069 common_modes[i].name, common_modes[i].w,
5070 common_modes[i].h);
5071 drm_mode_probed_add(connector, mode);
c84dec2f 5072 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 5073 }
5074}
5075
3ee6b26b
AD		 5076static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
5077 struct edid *edid)
e7b07cee 5078{
c84dec2f
HW		 5079 struct amdgpu_dm_connector *amdgpu_dm_connector =
5080 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5081
5082 if (edid) {
5083 /* empty probed_modes */
5084 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 5085 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 5086 drm_add_edid_modes(connector, edid);
5087
f1e5e913
YMM		 5088 /* sorting the probed modes before calling function
5089 * amdgpu_dm_get_native_mode() since EDID can have
5090 * more than one preferred mode. The modes that are
5091 * later in the probed mode list could be of higher
5092 * and preferred resolution. For example, 3840x2160
5093 * resolution in base EDID preferred timing and 4096x2160
5094 * preferred resolution in DID extension block later.
5095 */
5096 drm_mode_sort(&connector->probed_modes);
e7b07cee 5097 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 5098 } else {
c84dec2f 5099 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 5100 }
e7b07cee
HW		 5101}
5102
7578ecda 5103static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 5104{
c84dec2f
HW		 5105 struct amdgpu_dm_connector *amdgpu_dm_connector =
5106 to_amdgpu_dm_connector(connector);
e7b07cee 5107 struct drm_encoder *encoder;
c84dec2f 5108 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 5109
2b4c1c05 5110 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 5111
85ee15d6 5112 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 5113 amdgpu_dm_connector->num_modes =
5114 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 5115 } else {
5116 amdgpu_dm_connector_ddc_get_modes(connector, edid);
5117 amdgpu_dm_connector_add_common_modes(encoder, connector);
5118 }
3e332d3a 5119 amdgpu_dm_fbc_init(connector);
5099114b 5120
c84dec2f 5121 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 5122}
5123
3ee6b26b
AD		 5124void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
5125 struct amdgpu_dm_connector *aconnector,
5126 int connector_type,
5127 struct dc_link *link,
5128 int link_index)
e7b07cee
HW		 5129{
5130 struct amdgpu_device *adev = dm->ddev->dev_private;
5131
f04bee34
NK		 5132 /*
5133 * Some of the properties below require access to state, like bpc.
5134 * Allocate some default initial connector state with our reset helper.
5135 */
5136 if (aconnector->base.funcs->reset)
5137 aconnector->base.funcs->reset(&aconnector->base);
5138
e7b07cee
HW		 5139 aconnector->connector_id = link_index;
5140 aconnector->dc_link = link;
5141 aconnector->base.interlace_allowed = false;
5142 aconnector->base.doublescan_allowed = false;
5143 aconnector->base.stereo_allowed = false;
5144 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
5145 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
6ce8f316 5146 aconnector->audio_inst = -1;
e7b07cee
HW		 5147 mutex_init(&aconnector->hpd_lock);
5148
1f6010a9
DF		 5149 /*
5150 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 5151 * which means HPD hot plug not supported
5152 */
e7b07cee
HW		 5153 switch (connector_type) {
5154 case DRM_MODE_CONNECTOR_HDMIA:
5155 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 5156 aconnector->base.ycbcr_420_allowed =
9ea59d5a 5157 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 5158 break;
5159 case DRM_MODE_CONNECTOR_DisplayPort:
5160 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 5161 aconnector->base.ycbcr_420_allowed =
9ea59d5a 5162 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 5163 break;
5164 case DRM_MODE_CONNECTOR_DVID:
5165 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5166 break;
5167 default:
5168 break;
5169 }
5170
5171 drm_object_attach_property(&aconnector->base.base,
5172 dm->ddev->mode_config.scaling_mode_property,
5173 DRM_MODE_SCALE_NONE);
5174
5175 drm_object_attach_property(&aconnector->base.base,
5176 adev->mode_info.underscan_property,
5177 UNDERSCAN_OFF);
5178 drm_object_attach_property(&aconnector->base.base,
5179 adev->mode_info.underscan_hborder_property,
5180 0);
5181 drm_object_attach_property(&aconnector->base.base,
5182 adev->mode_info.underscan_vborder_property,
5183 0);
1825fd34
NK		 5184
5185 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
5186
5187 /* This defaults to the max in the range, but we want 8bpc. */
5188 aconnector->base.state->max_bpc = 8;
5189 aconnector->base.state->max_requested_bpc = 8;
e7b07cee 5190
c1ee92f9
DF		 5191 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5192 dc_is_dmcu_initialized(adev->dm.dc)) {
5193 drm_object_attach_property(&aconnector->base.base,
5194 adev->mode_info.abm_level_property, 0);
5195 }
bb47de73
NK		 5196
5197 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7fad8da1
NK		 5198 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5199 connector_type == DRM_MODE_CONNECTOR_eDP) {
88694af9
NK		 5200 drm_object_attach_property(
5201 &aconnector->base.base,
5202 dm->ddev->mode_config.hdr_output_metadata_property, 0);
5203
bb47de73
NK		 5204 drm_connector_attach_vrr_capable_property(
5205 &aconnector->base);
0c8620d6 5206#ifdef CONFIG_DRM_AMD_DC_HDCP
96a3b32e
BL		 5207 if (adev->asic_type >= CHIP_RAVEN)
5208 drm_connector_attach_content_protection_property(&aconnector->base, false);
0c8620d6 5209#endif
bb47de73 5210 }
e7b07cee
HW		 5211}
5212
7578ecda
AD		 5213static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
5214 struct i2c_msg *msgs, int num)
e7b07cee
HW		 5215{
5216 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
5217 struct ddc_service *ddc_service = i2c->ddc_service;
5218 struct i2c_command cmd;
5219 int i;
5220 int result = -EIO;
5221
b830ebc9 5222 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 5223
5224 if (!cmd.payloads)
5225 return result;
5226
5227 cmd.number_of_payloads = num;
5228 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
5229 cmd.speed = 100;
5230
5231 for (i = 0; i < num; i++) {
5232 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
5233 cmd.payloads[i].address = msgs[i].addr;
5234 cmd.payloads[i].length = msgs[i].len;
5235 cmd.payloads[i].data = msgs[i].buf;
5236 }
5237
c85e6e54
DF		 5238 if (dc_submit_i2c(
5239 ddc_service->ctx->dc,
5240 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 5241 &cmd))
5242 result = num;
5243
5244 kfree(cmd.payloads);
5245 return result;
5246}
5247
7578ecda 5248static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 5249{
5250 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
5251}
5252
5253static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
5254 .master_xfer = amdgpu_dm_i2c_xfer,
5255 .functionality = amdgpu_dm_i2c_func,
5256};
5257
3ee6b26b
AD		 5258static struct amdgpu_i2c_adapter *
5259create_i2c(struct ddc_service *ddc_service,
5260 int link_index,
5261 int *res)
e7b07cee
HW		 5262{
5263 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
5264 struct amdgpu_i2c_adapter *i2c;
5265
b830ebc9 5266 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 5267 if (!i2c)
5268 return NULL;
e7b07cee
HW		 5269 i2c->base.owner = THIS_MODULE;
5270 i2c->base.class = I2C_CLASS_DDC;
5271 i2c->base.dev.parent = &adev->pdev->dev;
5272 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 5273 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 5274 i2c_set_adapdata(&i2c->base, i2c);
5275 i2c->ddc_service = ddc_service;
c85e6e54 5276 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 5277
5278 return i2c;
5279}
5280
89fc8d4e 5281
1f6010a9
DF		 5282/*
5283 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 5284 * dc_link which will be represented by this aconnector.
5285 */
7578ecda
AD		 5286static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
5287 struct amdgpu_dm_connector *aconnector,
5288 uint32_t link_index,
5289 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 5290{
5291 int res = 0;
5292 int connector_type;
5293 struct dc *dc = dm->dc;
5294 struct dc_link *link = dc_get_link_at_index(dc, link_index);
5295 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 5296
5297 link->priv = aconnector;
e7b07cee 5298
f1ad2f5e 5299 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 5300
5301 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 5302 if (!i2c) {
5303 DRM_ERROR("Failed to create i2c adapter data\n");
5304 return -ENOMEM;
5305 }
5306
e7b07cee
HW		 5307 aconnector->i2c = i2c;
5308 res = i2c_add_adapter(&i2c->base);
5309
5310 if (res) {
5311 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
5312 goto out_free;
5313 }
5314
5315 connector_type = to_drm_connector_type(link->connector_signal);
5316
5317 res = drm_connector_init(
5318 dm->ddev,
5319 &aconnector->base,
5320 &amdgpu_dm_connector_funcs,
5321 connector_type);
5322
5323 if (res) {
5324 DRM_ERROR("connector_init failed\n");
5325 aconnector->connector_id = -1;
5326 goto out_free;
5327 }
5328
5329 drm_connector_helper_add(
5330 &aconnector->base,
5331 &amdgpu_dm_connector_helper_funcs);
5332
5333 amdgpu_dm_connector_init_helper(
5334 dm,
5335 aconnector,
5336 connector_type,
5337 link,
5338 link_index);
5339
cde4c44d 5340 drm_connector_attach_encoder(
e7b07cee
HW		 5341 &aconnector->base, &aencoder->base);
5342
5343 drm_connector_register(&aconnector->base);
dc38fd9d 5344#if defined(CONFIG_DEBUG_FS)
4be8be78 5345 connector_debugfs_init(aconnector);
f258fee6
DF		 5346 aconnector->debugfs_dpcd_address = 0;
5347 aconnector->debugfs_dpcd_size = 0;
dc38fd9d 5348#endif
e7b07cee
HW		 5349
5350 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
5351 || connector_type == DRM_MODE_CONNECTOR_eDP)
5352 amdgpu_dm_initialize_dp_connector(dm, aconnector);
5353
e7b07cee
HW		 5354out_free:
5355 if (res) {
5356 kfree(i2c);
5357 aconnector->i2c = NULL;
5358 }
5359 return res;
5360}
5361
5362int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
5363{
5364 switch (adev->mode_info.num_crtc) {
5365 case 1:
5366 return 0x1;
5367 case 2:
5368 return 0x3;
5369 case 3:
5370 return 0x7;
5371 case 4:
5372 return 0xf;
5373 case 5:
5374 return 0x1f;
5375 case 6:
5376 default:
5377 return 0x3f;
5378 }
5379}
5380
7578ecda
AD		 5381static int amdgpu_dm_encoder_init(struct drm_device *dev,
5382 struct amdgpu_encoder *aencoder,
5383 uint32_t link_index)
e7b07cee
HW		 5384{
5385 struct amdgpu_device *adev = dev->dev_private;
5386
5387 int res = drm_encoder_init(dev,
5388 &aencoder->base,
5389 &amdgpu_dm_encoder_funcs,
5390 DRM_MODE_ENCODER_TMDS,
5391 NULL);
5392
5393 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
5394
5395 if (!res)
5396 aencoder->encoder_id = link_index;
5397 else
5398 aencoder->encoder_id = -1;
5399
5400 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
5401
5402 return res;
5403}
5404
3ee6b26b
AD		 5405static void manage_dm_interrupts(struct amdgpu_device *adev,
5406 struct amdgpu_crtc *acrtc,
5407 bool enable)
e7b07cee
HW		 5408{
5409 /*
5410 * this is not correct translation but will work as soon as VBLANK
5411 * constant is the same as PFLIP
5412 */
5413 int irq_type =
734dd01d 5414 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 5415 adev,
5416 acrtc->crtc_id);
5417
5418 if (enable) {
5419 drm_crtc_vblank_on(&acrtc->base);
5420 amdgpu_irq_get(
5421 adev,
5422 &adev->pageflip_irq,
5423 irq_type);
5424 } else {
5425
5426 amdgpu_irq_put(
5427 adev,
5428 &adev->pageflip_irq,
5429 irq_type);
5430 drm_crtc_vblank_off(&acrtc->base);
5431 }
5432}
5433
3ee6b26b
AD		 5434static bool
5435is_scaling_state_different(const struct dm_connector_state *dm_state,
5436 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 5437{
5438 if (dm_state->scaling != old_dm_state->scaling)
5439 return true;
5440 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
5441 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
5442 return true;
5443 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
5444 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
5445 return true;
b830ebc9
HW		 5446 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
5447 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
5448 return true;
e7b07cee
HW		 5449 return false;
5450}
5451
0c8620d6
BL		 5452#ifdef CONFIG_DRM_AMD_DC_HDCP
5453static bool is_content_protection_different(struct drm_connector_state *state,
5454 const struct drm_connector_state *old_state,
5455 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
5456{
5457 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5458
5459 /* CP is being re enabled, ignore this */
5460 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
5461 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
5462 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
5463 return false;
5464 }
5465
5466 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */
5467 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
5468 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
5469 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
5470
5471 /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
5472 * hot-plug, headless s3, dpms
5473 */
5474 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && connector->dpms == DRM_MODE_DPMS_ON &&
5475 aconnector->dc_sink != NULL)
5476 return true;
5477
5478 if (old_state->content_protection == state->content_protection)
5479 return false;
5480
5481 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
5482 return true;
5483
5484 return false;
5485}
5486
5487static void update_content_protection(struct drm_connector_state *state, const struct drm_connector *connector,
5488 struct hdcp_workqueue *hdcp_w)
5489{
5490 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5491
da3fd7ac
BL		 5492 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
5493 hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, aconnector);
5494 else if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
0c8620d6
BL		 5495 hdcp_remove_display(hdcp_w, aconnector->dc_link->link_index, aconnector->base.index);
5496
5497}
5498#endif
3ee6b26b
AD		 5499static void remove_stream(struct amdgpu_device *adev,
5500 struct amdgpu_crtc *acrtc,
5501 struct dc_stream_state *stream)
e7b07cee
HW		 5502{
5503 /* this is the update mode case */
e7b07cee
HW		 5504
5505 acrtc->otg_inst = -1;
5506 acrtc->enabled = false;
5507}
5508
7578ecda
AD		 5509static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
5510 struct dc_cursor_position *position)
2a8f6ccb 5511{
f4c2cc43 5512 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 5513 int x, y;
5514 int xorigin = 0, yorigin = 0;
5515
e371e19c
NK		 5516 position->enable = false;
5517 position->x = 0;
5518 position->y = 0;
5519
5520 if (!crtc || !plane->state->fb)
2a8f6ccb 5521 return 0;
2a8f6ccb
HW		 5522
5523 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
5524 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
5525 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
5526 __func__,
5527 plane->state->crtc_w,
5528 plane->state->crtc_h);
5529 return -EINVAL;
5530 }
5531
5532 x = plane->state->crtc_x;
5533 y = plane->state->crtc_y;
c14a005c 5534
e371e19c
NK		 5535 if (x <= -amdgpu_crtc->max_cursor_width ||
5536 y <= -amdgpu_crtc->max_cursor_height)
5537 return 0;
5538
c14a005c
NK		 5539 if (crtc->primary->state) {
5540 /* avivo cursor are offset into the total surface */
5541 x += crtc->primary->state->src_x >> 16;
5542 y += crtc->primary->state->src_y >> 16;
5543 }
5544
2a8f6ccb
HW		 5545 if (x < 0) {
5546 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
5547 x = 0;
5548 }
5549 if (y < 0) {
5550 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
5551 y = 0;
5552 }
5553 position->enable = true;
5554 position->x = x;
5555 position->y = y;
5556 position->x_hotspot = xorigin;
5557 position->y_hotspot = yorigin;
5558
5559 return 0;
5560}
5561
3ee6b26b
AD		 5562static void handle_cursor_update(struct drm_plane *plane,
5563 struct drm_plane_state *old_plane_state)
e7b07cee 5564{
674e78ac 5565 struct amdgpu_device *adev = plane->dev->dev_private;
2a8f6ccb
HW		 5566 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
5567 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
5568 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
5569 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5570 uint64_t address = afb ? afb->address : 0;
5571 struct dc_cursor_position position;
5572 struct dc_cursor_attributes attributes;
5573 int ret;
5574
e7b07cee
HW		 5575 if (!plane->state->fb && !old_plane_state->fb)
5576 return;
5577
f1ad2f5e 5578 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 5579 __func__,
5580 amdgpu_crtc->crtc_id,
5581 plane->state->crtc_w,
5582 plane->state->crtc_h);
2a8f6ccb
HW		 5583
5584 ret = get_cursor_position(plane, crtc, &position);
5585 if (ret)
5586 return;
5587
5588 if (!position.enable) {
5589 /* turn off cursor */
674e78ac
NK		 5590 if (crtc_state && crtc_state->stream) {
5591 mutex_lock(&adev->dm.dc_lock);
2a8f6ccb
HW		 5592 dc_stream_set_cursor_position(crtc_state->stream,
5593 &position);
674e78ac
NK		 5594 mutex_unlock(&adev->dm.dc_lock);
5595 }
2a8f6ccb 5596 return;
e7b07cee 5597 }
e7b07cee 5598
2a8f6ccb
HW		 5599 amdgpu_crtc->cursor_width = plane->state->crtc_w;
5600 amdgpu_crtc->cursor_height = plane->state->crtc_h;
5601
c1cefe11 5602 memset(&attributes, 0, sizeof(attributes));
2a8f6ccb
HW		 5603 attributes.address.high_part = upper_32_bits(address);
5604 attributes.address.low_part = lower_32_bits(address);
5605 attributes.width = plane->state->crtc_w;
5606 attributes.height = plane->state->crtc_h;
5607 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
5608 attributes.rotation_angle = 0;
5609 attributes.attribute_flags.value = 0;
5610
5611 attributes.pitch = attributes.width;
5612
886daac9 5613 if (crtc_state->stream) {
674e78ac 5614 mutex_lock(&adev->dm.dc_lock);
886daac9
JZ		 5615 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
5616 &attributes))
5617 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 5618
2a8f6ccb
HW		 5619 if (!dc_stream_set_cursor_position(crtc_state->stream,
5620 &position))
5621 DRM_ERROR("DC failed to set cursor position\n");
674e78ac 5622 mutex_unlock(&adev->dm.dc_lock);
886daac9 5623 }
2a8f6ccb 5624}
e7b07cee
HW		 5625
5626static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
5627{
5628
5629 assert_spin_locked(&acrtc->base.dev->event_lock);
5630 WARN_ON(acrtc->event);
5631
5632 acrtc->event = acrtc->base.state->event;
5633
5634 /* Set the flip status */
5635 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
5636
5637 /* Mark this event as consumed */
5638 acrtc->base.state->event = NULL;
5639
5640 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
5641 acrtc->crtc_id);
5642}
5643
bb47de73
NK		 5644static void update_freesync_state_on_stream(
5645 struct amdgpu_display_manager *dm,
5646 struct dm_crtc_state *new_crtc_state,
180db303
NK		 5647 struct dc_stream_state *new_stream,
5648 struct dc_plane_state *surface,
5649 u32 flip_timestamp_in_us)
bb47de73 5650{
09aef2c4 5651 struct mod_vrr_params vrr_params;
bb47de73 5652 struct dc_info_packet vrr_infopacket = {0};
09aef2c4
MK		 5653 struct amdgpu_device *adev = dm->adev;
5654 unsigned long flags;
bb47de73
NK		 5655
5656 if (!new_stream)
5657 return;
5658
5659 /*
5660 * TODO: Determine why min/max totals and vrefresh can be 0 here.
5661 * For now it's sufficient to just guard against these conditions.
5662 */
5663
5664 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5665 return;
5666
09aef2c4
MK		 5667 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5668 vrr_params = new_crtc_state->vrr_params;
5669
180db303
NK		 5670 if (surface) {
5671 mod_freesync_handle_preflip(
5672 dm->freesync_module,
5673 surface,
5674 new_stream,
5675 flip_timestamp_in_us,
5676 &vrr_params);
09aef2c4
MK		 5677
5678 if (adev->family < AMDGPU_FAMILY_AI &&
5679 amdgpu_dm_vrr_active(new_crtc_state)) {
5680 mod_freesync_handle_v_update(dm->freesync_module,
5681 new_stream, &vrr_params);
e63e2491
EB		 5682
5683 /* Need to call this before the frame ends. */
5684 dc_stream_adjust_vmin_vmax(dm->dc,
5685 new_crtc_state->stream,
5686 &vrr_params.adjust);
09aef2c4 5687 }
180db303 5688 }
bb47de73
NK		 5689
5690 mod_freesync_build_vrr_infopacket(
5691 dm->freesync_module,
5692 new_stream,
180db303 5693 &vrr_params,
ecd0136b
HT		 5694 PACKET_TYPE_VRR,
5695 TRANSFER_FUNC_UNKNOWN,
bb47de73
NK		 5696 &vrr_infopacket);
5697
8a48b44c 5698 new_crtc_state->freesync_timing_changed |=
180db303
NK		 5699 (memcmp(&new_crtc_state->vrr_params.adjust,
5700 &vrr_params.adjust,
5701 sizeof(vrr_params.adjust)) != 0);
bb47de73 5702
8a48b44c 5703 new_crtc_state->freesync_vrr_info_changed |=
bb47de73
NK		 5704 (memcmp(&new_crtc_state->vrr_infopacket,
5705 &vrr_infopacket,
5706 sizeof(vrr_infopacket)) != 0);
5707
180db303 5708 new_crtc_state->vrr_params = vrr_params;
bb47de73
NK		 5709 new_crtc_state->vrr_infopacket = vrr_infopacket;
5710
180db303 5711 new_stream->adjust = new_crtc_state->vrr_params.adjust;
bb47de73
NK		 5712 new_stream->vrr_infopacket = vrr_infopacket;
5713
5714 if (new_crtc_state->freesync_vrr_info_changed)
5715 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
5716 new_crtc_state->base.crtc->base.id,
5717 (int)new_crtc_state->base.vrr_enabled,
180db303 5718 (int)vrr_params.state);
09aef2c4
MK		 5719
5720 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
bb47de73
NK		 5721}
5722
e854194c
MK		 5723static void pre_update_freesync_state_on_stream(
5724 struct amdgpu_display_manager *dm,
5725 struct dm_crtc_state *new_crtc_state)
5726{
5727 struct dc_stream_state *new_stream = new_crtc_state->stream;
09aef2c4 5728 struct mod_vrr_params vrr_params;
e854194c 5729 struct mod_freesync_config config = new_crtc_state->freesync_config;
09aef2c4
MK		 5730 struct amdgpu_device *adev = dm->adev;
5731 unsigned long flags;
e854194c
MK		 5732
5733 if (!new_stream)
5734 return;
5735
5736 /*
5737 * TODO: Determine why min/max totals and vrefresh can be 0 here.
5738 * For now it's sufficient to just guard against these conditions.
5739 */
5740 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5741 return;
5742
09aef2c4
MK		 5743 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5744 vrr_params = new_crtc_state->vrr_params;
5745
e854194c
MK		 5746 if (new_crtc_state->vrr_supported &&
5747 config.min_refresh_in_uhz &&
5748 config.max_refresh_in_uhz) {
5749 config.state = new_crtc_state->base.vrr_enabled ?
5750 VRR_STATE_ACTIVE_VARIABLE :
5751 VRR_STATE_INACTIVE;
5752 } else {
5753 config.state = VRR_STATE_UNSUPPORTED;
5754 }
5755
5756 mod_freesync_build_vrr_params(dm->freesync_module,
5757 new_stream,
5758 &config, &vrr_params);
5759
5760 new_crtc_state->freesync_timing_changed |=
5761 (memcmp(&new_crtc_state->vrr_params.adjust,
5762 &vrr_params.adjust,
5763 sizeof(vrr_params.adjust)) != 0);
5764
5765 new_crtc_state->vrr_params = vrr_params;
09aef2c4 5766 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
e854194c
MK		 5767}
5768
66b0c973
MK		 5769static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
5770 struct dm_crtc_state *new_state)
5771{
5772 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
5773 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
5774
5775 if (!old_vrr_active && new_vrr_active) {
5776 /* Transition VRR inactive -> active:
5777 * While VRR is active, we must not disable vblank irq, as a
5778 * reenable after disable would compute bogus vblank/pflip
5779 * timestamps if it likely happened inside display front-porch.
d2574c33
MK		 5780 *
5781 * We also need vupdate irq for the actual core vblank handling
5782 * at end of vblank.
66b0c973 5783 */
d2574c33 5784 dm_set_vupdate_irq(new_state->base.crtc, true);
66b0c973
MK		 5785 drm_crtc_vblank_get(new_state->base.crtc);
5786 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
5787 __func__, new_state->base.crtc->base.id);
5788 } else if (old_vrr_active && !new_vrr_active) {
5789 /* Transition VRR active -> inactive:
5790 * Allow vblank irq disable again for fixed refresh rate.
5791 */
d2574c33 5792 dm_set_vupdate_irq(new_state->base.crtc, false);
66b0c973
MK		 5793 drm_crtc_vblank_put(new_state->base.crtc);
5794 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
5795 __func__, new_state->base.crtc->base.id);
5796 }
5797}
5798
8ad27806
NK		 5799static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
5800{
5801 struct drm_plane *plane;
5802 struct drm_plane_state *old_plane_state, *new_plane_state;
5803 int i;
5804
5805 /*
5806 * TODO: Make this per-stream so we don't issue redundant updates for
5807 * commits with multiple streams.
5808 */
5809 for_each_oldnew_plane_in_state(state, plane, old_plane_state,
5810 new_plane_state, i)
5811 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5812 handle_cursor_update(plane, old_plane_state);
5813}
5814
3be5262e 5815static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 5816 struct dc_state *dc_state,
3ee6b26b
AD		 5817 struct drm_device *dev,
5818 struct amdgpu_display_manager *dm,
5819 struct drm_crtc *pcrtc,
420cd472 5820 bool wait_for_vblank)
e7b07cee 5821{
570c91d5 5822 uint32_t i;
8a48b44c 5823 uint64_t timestamp_ns;
e7b07cee 5824 struct drm_plane *plane;
0bc9706d 5825 struct drm_plane_state *old_plane_state, *new_plane_state;
e7b07cee 5826 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 5827 struct drm_crtc_state *new_pcrtc_state =
5828 drm_atomic_get_new_crtc_state(state, pcrtc);
5829 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 5830 struct dm_crtc_state *dm_old_crtc_state =
5831 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
74aa7bd4 5832 int planes_count = 0, vpos, hpos;
570c91d5 5833 long r;
e7b07cee 5834 unsigned long flags;
8a48b44c 5835 struct amdgpu_bo *abo;
09e5665a 5836 uint64_t tiling_flags;
fdd1fe57
MK		 5837 uint32_t target_vblank, last_flip_vblank;
5838 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
74aa7bd4 5839 bool pflip_present = false;
8c322309 5840 bool swizzle = true;
bc7f670e
DF		 5841 struct {
5842 struct dc_surface_update surface_updates[MAX_SURFACES];
5843 struct dc_plane_info plane_infos[MAX_SURFACES];
5844 struct dc_scaling_info scaling_infos[MAX_SURFACES];
74aa7bd4 5845 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
bc7f670e 5846 struct dc_stream_update stream_update;
74aa7bd4 5847 } *bundle;
bc7f670e 5848
74aa7bd4 5849 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8a48b44c 5850
74aa7bd4
DF		 5851 if (!bundle) {
5852 dm_error("Failed to allocate update bundle\n");
4b510503
NK		 5853 goto cleanup;
5854 }
e7b07cee 5855
8ad27806
NK		 5856 /*
5857 * Disable the cursor first if we're disabling all the planes.
5858 * It'll remain on the screen after the planes are re-enabled
5859 * if we don't.
5860 */
5861 if (acrtc_state->active_planes == 0)
5862 amdgpu_dm_commit_cursors(state);
5863
e7b07cee 5864 /* update planes when needed */
0bc9706d
LSL		 5865 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
5866 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 5867 struct drm_crtc_state *new_crtc_state;
0bc9706d 5868 struct drm_framebuffer *fb = new_plane_state->fb;
34bafd27 5869 bool plane_needs_flip;
c7af5f77 5870 struct dc_plane_state *dc_plane;
54d76575 5871 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee 5872
80c218d5
NK		 5873 /* Cursor plane is handled after stream updates */
5874 if (plane->type == DRM_PLANE_TYPE_CURSOR)
e7b07cee 5875 continue;
e7b07cee 5876
f5ba60fe
DD		 5877 if (!fb || !crtc || pcrtc != crtc)
5878 continue;
5879
5880 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
5881 if (!new_crtc_state->active)
e7b07cee
HW		 5882 continue;
5883
bc7f670e 5884 dc_plane = dm_new_plane_state->dc_state;
e7b07cee 5885
8c322309
RL		 5886 if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle)
5887 swizzle = false;
5888
74aa7bd4 5889 bundle->surface_updates[planes_count].surface = dc_plane;
bc7f670e 5890 if (new_pcrtc_state->color_mgmt_changed) {
74aa7bd4
DF		 5891 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
5892 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
bc7f670e 5893 }
8a48b44c 5894
695af5f9
NK		 5895 fill_dc_scaling_info(new_plane_state,
5896 &bundle->scaling_infos[planes_count]);
8a48b44c 5897
695af5f9
NK		 5898 bundle->surface_updates[planes_count].scaling_info =
5899 &bundle->scaling_infos[planes_count];
8a48b44c 5900
f5031000 5901 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8a48b44c 5902
f5031000 5903 pflip_present = pflip_present || plane_needs_flip;
8a48b44c 5904
f5031000
DF		 5905 if (!plane_needs_flip) {
5906 planes_count += 1;
5907 continue;
5908 }
8a48b44c 5909
2fac0f53
CK		 5910 abo = gem_to_amdgpu_bo(fb->obj[0]);
5911
f8308898
AG		 5912 /*
5913 * Wait for all fences on this FB. Do limited wait to avoid
5914 * deadlock during GPU reset when this fence will not signal
5915 * but we hold reservation lock for the BO.
5916 */
52791eee 5917 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
2fac0f53 5918 false,
f8308898
AG		 5919 msecs_to_jiffies(5000));
5920 if (unlikely(r <= 0))
ed8a5fb2 5921 DRM_ERROR("Waiting for fences timed out!");
2fac0f53 5922
f5031000
DF		 5923 /*
5924 * TODO This might fail and hence better not used, wait
5925 * explicitly on fences instead
5926 * and in general should be called for
5927 * blocking commit to as per framework helpers
5928 */
f5031000 5929 r = amdgpu_bo_reserve(abo, true);
f8308898 5930 if (unlikely(r != 0))
f5031000 5931 DRM_ERROR("failed to reserve buffer before flip\n");
8a48b44c 5932
f5031000 5933 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
8a48b44c 5934
f5031000 5935 amdgpu_bo_unreserve(abo);
8a48b44c 5936
695af5f9
NK		 5937 fill_dc_plane_info_and_addr(
5938 dm->adev, new_plane_state, tiling_flags,
5939 &bundle->plane_infos[planes_count],
5940 &bundle->flip_addrs[planes_count].address);
5941
5942 bundle->surface_updates[planes_count].plane_info =
5943 &bundle->plane_infos[planes_count];
8a48b44c 5944
caff0e66
NK		 5945 /*
5946 * Only allow immediate flips for fast updates that don't
5947 * change FB pitch, DCC state, rotation or mirroing.
5948 */
f5031000 5949 bundle->flip_addrs[planes_count].flip_immediate =
caff0e66
NK		 5950 (crtc->state->pageflip_flags &
5951 DRM_MODE_PAGE_FLIP_ASYNC) != 0 &&
5952 acrtc_state->update_type == UPDATE_TYPE_FAST;
8a48b44c 5953
f5031000
DF		 5954 timestamp_ns = ktime_get_ns();
5955 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
5956 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
5957 bundle->surface_updates[planes_count].surface = dc_plane;
8a48b44c 5958
f5031000
DF		 5959 if (!bundle->surface_updates[planes_count].surface) {
5960 DRM_ERROR("No surface for CRTC: id=%d\n",
5961 acrtc_attach->crtc_id);
5962 continue;
bc7f670e
DF		 5963 }
5964
f5031000
DF		 5965 if (plane == pcrtc->primary)
5966 update_freesync_state_on_stream(
5967 dm,
5968 acrtc_state,
5969 acrtc_state->stream,
5970 dc_plane,
5971 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
bc7f670e 5972
f5031000
DF		 5973 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
5974 __func__,
5975 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
5976 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
bc7f670e
DF		 5977
5978 planes_count += 1;
5979
8a48b44c
DF		 5980 }
5981
74aa7bd4 5982 if (pflip_present) {
634092b1
MK		 5983 if (!vrr_active) {
5984 /* Use old throttling in non-vrr fixed refresh rate mode
5985 * to keep flip scheduling based on target vblank counts
5986 * working in a backwards compatible way, e.g., for
5987 * clients using the GLX_OML_sync_control extension or
5988 * DRI3/Present extension with defined target_msc.
5989 */
fdd1fe57 5990 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
634092b1
MK		 5991 }
5992 else {
5993 /* For variable refresh rate mode only:
5994 * Get vblank of last completed flip to avoid > 1 vrr
5995 * flips per video frame by use of throttling, but allow
5996 * flip programming anywhere in the possibly large
5997 * variable vrr vblank interval for fine-grained flip
5998 * timing control and more opportunity to avoid stutter
5999 * on late submission of flips.
6000 */
6001 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6002 last_flip_vblank = acrtc_attach->last_flip_vblank;
6003 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6004 }
6005
fdd1fe57 6006 target_vblank = last_flip_vblank + wait_for_vblank;
8a48b44c
DF		 6007
6008 /*
6009 * Wait until we're out of the vertical blank period before the one
6010 * targeted by the flip
6011 */
6012 while ((acrtc_attach->enabled &&
6013 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
6014 0, &vpos, &hpos, NULL,
6015 NULL, &pcrtc->hwmode)
6016 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
6017 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
6018 (int)(target_vblank -
6019 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
6020 usleep_range(1000, 1100);
6021 }
6022
6023 if (acrtc_attach->base.state->event) {
6024 drm_crtc_vblank_get(pcrtc);
6025
6026 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6027
6028 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
6029 prepare_flip_isr(acrtc_attach);
6030
6031 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6032 }
6033
6034 if (acrtc_state->stream) {
8a48b44c 6035 if (acrtc_state->freesync_vrr_info_changed)
74aa7bd4 6036 bundle->stream_update.vrr_infopacket =
8a48b44c 6037 &acrtc_state->stream->vrr_infopacket;
e7b07cee 6038 }
e7b07cee
HW		 6039 }
6040
bc92c065 6041 /* Update the planes if changed or disable if we don't have any. */
ed9656fb
ES		 6042 if ((planes_count || acrtc_state->active_planes == 0) &&
6043 acrtc_state->stream) {
b6e881c9 6044 bundle->stream_update.stream = acrtc_state->stream;
bc7f670e 6045 if (new_pcrtc_state->mode_changed) {
74aa7bd4
DF		 6046 bundle->stream_update.src = acrtc_state->stream->src;
6047 bundle->stream_update.dst = acrtc_state->stream->dst;
e7b07cee
HW		 6048 }
6049
cf020d49
NK		 6050 if (new_pcrtc_state->color_mgmt_changed) {
6051 /*
6052 * TODO: This isn't fully correct since we've actually
6053 * already modified the stream in place.
6054 */
6055 bundle->stream_update.gamut_remap =
6056 &acrtc_state->stream->gamut_remap_matrix;
6057 bundle->stream_update.output_csc_transform =
6058 &acrtc_state->stream->csc_color_matrix;
6059 bundle->stream_update.out_transfer_func =
6060 acrtc_state->stream->out_transfer_func;
6061 }
bc7f670e 6062
8a48b44c 6063 acrtc_state->stream->abm_level = acrtc_state->abm_level;
bc7f670e 6064 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
74aa7bd4 6065 bundle->stream_update.abm_level = &acrtc_state->abm_level;
44d09c6a 6066
e63e2491
EB		 6067 /*
6068 * If FreeSync state on the stream has changed then we need to
6069 * re-adjust the min/max bounds now that DC doesn't handle this
6070 * as part of commit.
6071 */
6072 if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
6073 amdgpu_dm_vrr_active(acrtc_state)) {
6074 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6075 dc_stream_adjust_vmin_vmax(
6076 dm->dc, acrtc_state->stream,
6077 &acrtc_state->vrr_params.adjust);
6078 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6079 }
bc7f670e 6080 mutex_lock(&dm->dc_lock);
8c322309
RL		 6081 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
6082 acrtc_state->stream->link->psr_allow_active)
6083 amdgpu_dm_psr_disable(acrtc_state->stream);
6084
bc7f670e 6085 dc_commit_updates_for_stream(dm->dc,
74aa7bd4 6086 bundle->surface_updates,
bc7f670e
DF		 6087 planes_count,
6088 acrtc_state->stream,
74aa7bd4 6089 &bundle->stream_update,
bc7f670e 6090 dc_state);
8c322309
RL		 6091
6092 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
6093 acrtc_state->stream->psr_version &&
6094 !acrtc_state->stream->link->psr_feature_enabled)
6095 amdgpu_dm_link_setup_psr(acrtc_state->stream);
6096 else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
6097 acrtc_state->stream->link->psr_feature_enabled &&
6098 !acrtc_state->stream->link->psr_allow_active &&
6099 swizzle) {
6100 amdgpu_dm_psr_enable(acrtc_state->stream);
6101 }
6102
bc7f670e 6103 mutex_unlock(&dm->dc_lock);
e7b07cee 6104 }
4b510503 6105
8ad27806
NK		 6106 /*
6107 * Update cursor state *after* programming all the planes.
6108 * This avoids redundant programming in the case where we're going
6109 * to be disabling a single plane - those pipes are being disabled.
6110 */
6111 if (acrtc_state->active_planes)
6112 amdgpu_dm_commit_cursors(state);
80c218d5 6113
4b510503 6114cleanup:
74aa7bd4 6115 kfree(bundle);
e7b07cee
HW		 6116}
6117
6ce8f316
NK		 6118static void amdgpu_dm_commit_audio(struct drm_device *dev,
6119 struct drm_atomic_state *state)
6120{
6121 struct amdgpu_device *adev = dev->dev_private;
6122 struct amdgpu_dm_connector *aconnector;
6123 struct drm_connector *connector;
6124 struct drm_connector_state *old_con_state, *new_con_state;
6125 struct drm_crtc_state *new_crtc_state;
6126 struct dm_crtc_state *new_dm_crtc_state;
6127 const struct dc_stream_status *status;
6128 int i, inst;
6129
6130 /* Notify device removals. */
6131 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6132 if (old_con_state->crtc != new_con_state->crtc) {
6133 /* CRTC changes require notification. */
6134 goto notify;
6135 }
6136
6137 if (!new_con_state->crtc)
6138 continue;
6139
6140 new_crtc_state = drm_atomic_get_new_crtc_state(
6141 state, new_con_state->crtc);
6142
6143 if (!new_crtc_state)
6144 continue;
6145
6146 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6147 continue;
6148
6149 notify:
6150 aconnector = to_amdgpu_dm_connector(connector);
6151
6152 mutex_lock(&adev->dm.audio_lock);
6153 inst = aconnector->audio_inst;
6154 aconnector->audio_inst = -1;
6155 mutex_unlock(&adev->dm.audio_lock);
6156
6157 amdgpu_dm_audio_eld_notify(adev, inst);
6158 }
6159
6160 /* Notify audio device additions. */
6161 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6162 if (!new_con_state->crtc)
6163 continue;
6164
6165 new_crtc_state = drm_atomic_get_new_crtc_state(
6166 state, new_con_state->crtc);
6167
6168 if (!new_crtc_state)
6169 continue;
6170
6171 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6172 continue;
6173
6174 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6175 if (!new_dm_crtc_state->stream)
6176 continue;
6177
6178 status = dc_stream_get_status(new_dm_crtc_state->stream);
6179 if (!status)
6180 continue;
6181
6182 aconnector = to_amdgpu_dm_connector(connector);
6183
6184 mutex_lock(&adev->dm.audio_lock);
6185 inst = status->audio_inst;
6186 aconnector->audio_inst = inst;
6187 mutex_unlock(&adev->dm.audio_lock);
6188
6189 amdgpu_dm_audio_eld_notify(adev, inst);
6190 }
6191}
6192
b5e83f6f
NK		 6193/*
6194 * Enable interrupts on CRTCs that are newly active, undergone
6195 * a modeset, or have active planes again.
6196 *
6197 * Done in two passes, based on the for_modeset flag:
6198 * Pass 1: For CRTCs going through modeset
6199 * Pass 2: For CRTCs going from 0 to n active planes
6200 *
6201 * Interrupts can only be enabled after the planes are programmed,
6202 * so this requires a two-pass approach since we don't want to
6203 * just defer the interrupts until after commit planes every time.
6204 */
6205static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
6206 struct drm_atomic_state *state,
6207 bool for_modeset)
6208{
6209 struct amdgpu_device *adev = dev->dev_private;
6210 struct drm_crtc *crtc;
6211 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6212 int i;
f0ee9b18 6213#ifdef CONFIG_DEBUG_FS
14b25846 6214 enum amdgpu_dm_pipe_crc_source source;
f0ee9b18 6215#endif
b5e83f6f
NK		 6216
6217 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6218 new_crtc_state, i) {
6219 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6220 struct dm_crtc_state *dm_new_crtc_state =
6221 to_dm_crtc_state(new_crtc_state);
6222 struct dm_crtc_state *dm_old_crtc_state =
6223 to_dm_crtc_state(old_crtc_state);
6224 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
6225 bool run_pass;
6226
6227 run_pass = (for_modeset && modeset) ||
6228 (!for_modeset && !modeset &&
6229 !dm_old_crtc_state->interrupts_enabled);
6230
6231 if (!run_pass)
6232 continue;
6233
b5e83f6f
NK		 6234 if (!dm_new_crtc_state->interrupts_enabled)
6235 continue;
6236
6237 manage_dm_interrupts(adev, acrtc, true);
6238
6239#ifdef CONFIG_DEBUG_FS
6240 /* The stream has changed so CRC capture needs to re-enabled. */
14b25846
DZ		 6241 source = dm_new_crtc_state->crc_src;
6242 if (amdgpu_dm_is_valid_crc_source(source)) {
57638021
NK		 6243 amdgpu_dm_crtc_configure_crc_source(
6244 crtc, dm_new_crtc_state,
6245 dm_new_crtc_state->crc_src);
b5e83f6f
NK		 6246 }
6247#endif
6248 }
6249}
6250
1f6010a9 6251/*
27b3f4fc
LSL		 6252 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
6253 * @crtc_state: the DRM CRTC state
6254 * @stream_state: the DC stream state.
6255 *
6256 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
6257 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
6258 */
6259static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
6260 struct dc_stream_state *stream_state)
6261{
b9952f93 6262 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
27b3f4fc 6263}
e7b07cee 6264
7578ecda
AD		 6265static int amdgpu_dm_atomic_commit(struct drm_device *dev,
6266 struct drm_atomic_state *state,
6267 bool nonblock)
e7b07cee
HW		 6268{
6269 struct drm_crtc *crtc;
c2cea706 6270 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 6271 struct amdgpu_device *adev = dev->dev_private;
6272 int i;
6273
6274 /*
d6ef9b41
NK		 6275 * We evade vblank and pflip interrupts on CRTCs that are undergoing
6276 * a modeset, being disabled, or have no active planes.
6277 *
6278 * It's done in atomic commit rather than commit tail for now since
6279 * some of these interrupt handlers access the current CRTC state and
6280 * potentially the stream pointer itself.
6281 *
6282 * Since the atomic state is swapped within atomic commit and not within
6283 * commit tail this would leave to new state (that hasn't been committed yet)
6284 * being accesssed from within the handlers.
6285 *
6286 * TODO: Fix this so we can do this in commit tail and not have to block
6287 * in atomic check.
e7b07cee 6288 */
c2cea706 6289 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 6290 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
428da2bd 6291 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 6292 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6293
d6ef9b41
NK		 6294 if (dm_old_crtc_state->interrupts_enabled &&
6295 (!dm_new_crtc_state->interrupts_enabled ||
57638021 6296 drm_atomic_crtc_needs_modeset(new_crtc_state)))
e7b07cee
HW		 6297 manage_dm_interrupts(adev, acrtc, false);
6298 }
1f6010a9
DF		 6299 /*
6300 * Add check here for SoC's that support hardware cursor plane, to
6301 * unset legacy_cursor_update
6302 */
e7b07cee
HW		 6303
6304 return drm_atomic_helper_commit(dev, state, nonblock);
6305
6306 /*TODO Handle EINTR, reenable IRQ*/
6307}
6308
b8592b48
LL		 6309/**
6310 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
6311 * @state: The atomic state to commit
6312 *
6313 * This will tell DC to commit the constructed DC state from atomic_check,
6314 * programming the hardware. Any failures here implies a hardware failure, since
6315 * atomic check should have filtered anything non-kosher.
6316 */
7578ecda 6317static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 6318{
6319 struct drm_device *dev = state->dev;
6320 struct amdgpu_device *adev = dev->dev_private;
6321 struct amdgpu_display_manager *dm = &adev->dm;
6322 struct dm_atomic_state *dm_state;
eb3dc897 6323 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 6324 uint32_t i, j;
5cc6dcbd 6325 struct drm_crtc *crtc;
0bc9706d 6326 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 6327 unsigned long flags;
6328 bool wait_for_vblank = true;
6329 struct drm_connector *connector;
c2cea706 6330 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 6331 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 6332 int crtc_disable_count = 0;
e7b07cee
HW		 6333
6334 drm_atomic_helper_update_legacy_modeset_state(dev, state);
6335
eb3dc897
NK		 6336 dm_state = dm_atomic_get_new_state(state);
6337 if (dm_state && dm_state->context) {
6338 dc_state = dm_state->context;
6339 } else {
6340 /* No state changes, retain current state. */
813d20dc 6341 dc_state_temp = dc_create_state(dm->dc);
eb3dc897
NK		 6342 ASSERT(dc_state_temp);
6343 dc_state = dc_state_temp;
6344 dc_resource_state_copy_construct_current(dm->dc, dc_state);
6345 }
e7b07cee
HW		 6346
6347 /* update changed items */
0bc9706d 6348 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 6349 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 6350
54d76575
LSL		 6351 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6352 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 6353
f1ad2f5e 6354 DRM_DEBUG_DRIVER(
e7b07cee
HW		 6355 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6356 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6357 "connectors_changed:%d\n",
6358 acrtc->crtc_id,
0bc9706d
LSL		 6359 new_crtc_state->enable,
6360 new_crtc_state->active,
6361 new_crtc_state->planes_changed,
6362 new_crtc_state->mode_changed,
6363 new_crtc_state->active_changed,
6364 new_crtc_state->connectors_changed);
e7b07cee 6365
27b3f4fc
LSL		 6366 /* Copy all transient state flags into dc state */
6367 if (dm_new_crtc_state->stream) {
6368 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
6369 dm_new_crtc_state->stream);
6370 }
6371
e7b07cee
HW		 6372 /* handles headless hotplug case, updating new_state and
6373 * aconnector as needed
6374 */
6375
54d76575 6376 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 6377
f1ad2f5e 6378 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 6379
54d76575 6380 if (!dm_new_crtc_state->stream) {
e7b07cee 6381 /*
b830ebc9
HW		 6382 * this could happen because of issues with
6383 * userspace notifications delivery.
6384 * In this case userspace tries to set mode on
1f6010a9
DF		 6385 * display which is disconnected in fact.
6386 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 6387 * We expect reset mode will come soon.
6388 *
6389 * This can also happen when unplug is done
6390 * during resume sequence ended
6391 *
6392 * In this case, we want to pretend we still
6393 * have a sink to keep the pipe running so that
6394 * hw state is consistent with the sw state
6395 */
f1ad2f5e 6396 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 6397 __func__, acrtc->base.base.id);
6398 continue;
6399 }
6400
54d76575
LSL		 6401 if (dm_old_crtc_state->stream)
6402 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 6403
97028037
LP		 6404 pm_runtime_get_noresume(dev->dev);
6405
e7b07cee 6406 acrtc->enabled = true;
0bc9706d
LSL		 6407 acrtc->hw_mode = new_crtc_state->mode;
6408 crtc->hwmode = new_crtc_state->mode;
6409 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 6410 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 6411 /* i.e. reset mode */
8c322309
RL		 6412 if (dm_old_crtc_state->stream) {
6413 if (dm_old_crtc_state->stream->link->psr_allow_active)
6414 amdgpu_dm_psr_disable(dm_old_crtc_state->stream);
6415
54d76575 6416 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8c322309 6417 }
e7b07cee
HW		 6418 }
6419 } /* for_each_crtc_in_state() */
6420
eb3dc897
NK		 6421 if (dc_state) {
6422 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 6423 mutex_lock(&dm->dc_lock);
eb3dc897 6424 WARN_ON(!dc_commit_state(dm->dc, dc_state));
674e78ac 6425 mutex_unlock(&dm->dc_lock);
fa2123db 6426 }
e7b07cee 6427
0bc9706d 6428 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 6429 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 6430
54d76575 6431 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 6432
54d76575 6433 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 6434 const struct dc_stream_status *status =
54d76575 6435 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 6436
eb3dc897 6437 if (!status)
09f609c3
LL		 6438 status = dc_stream_get_status_from_state(dc_state,
6439 dm_new_crtc_state->stream);
eb3dc897 6440
e7b07cee 6441 if (!status)
54d76575 6442 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 6443 else
6444 acrtc->otg_inst = status->primary_otg_inst;
6445 }
6446 }
0c8620d6
BL		 6447#ifdef CONFIG_DRM_AMD_DC_HDCP
6448 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6449 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6450 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6451 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6452
6453 new_crtc_state = NULL;
6454
6455 if (acrtc)
6456 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
6457
6458 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6459
6460 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
6461 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
6462 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
6463 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
6464 continue;
6465 }
6466
6467 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
6468 update_content_protection(new_con_state, connector, adev->dm.hdcp_workqueue);
6469 }
6470#endif
e7b07cee 6471
02d6a6fc 6472 /* Handle connector state changes */
c2cea706 6473 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 6474 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6475 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6476 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
19afd799
NC		 6477 struct dc_surface_update dummy_updates[MAX_SURFACES];
6478 struct dc_stream_update stream_update;
b232d4ed 6479 struct dc_info_packet hdr_packet;
e7b07cee 6480 struct dc_stream_status *status = NULL;
b232d4ed 6481 bool abm_changed, hdr_changed, scaling_changed;
e7b07cee 6482
19afd799
NC		 6483 memset(&dummy_updates, 0, sizeof(dummy_updates));
6484 memset(&stream_update, 0, sizeof(stream_update));
6485
44d09c6a 6486 if (acrtc) {
0bc9706d 6487 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 6488 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
6489 }
0bc9706d 6490
e7b07cee 6491 /* Skip any modesets/resets */
0bc9706d 6492 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 6493 continue;
6494
54d76575 6495 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 6496 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6497
b232d4ed
NK		 6498 scaling_changed = is_scaling_state_different(dm_new_con_state,
6499 dm_old_con_state);
6500
6501 abm_changed = dm_new_crtc_state->abm_level !=
6502 dm_old_crtc_state->abm_level;
6503
6504 hdr_changed =
6505 is_hdr_metadata_different(old_con_state, new_con_state);
6506
6507 if (!scaling_changed && !abm_changed && !hdr_changed)
c1ee92f9 6508 continue;
e7b07cee 6509
b6e881c9 6510 stream_update.stream = dm_new_crtc_state->stream;
b232d4ed 6511 if (scaling_changed) {
02d6a6fc 6512 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
b6e881c9 6513 dm_new_con_state, dm_new_crtc_state->stream);
e7b07cee 6514
02d6a6fc
DF		 6515 stream_update.src = dm_new_crtc_state->stream->src;
6516 stream_update.dst = dm_new_crtc_state->stream->dst;
6517 }
6518
b232d4ed 6519 if (abm_changed) {
02d6a6fc
DF		 6520 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
6521
6522 stream_update.abm_level = &dm_new_crtc_state->abm_level;
6523 }
70e8ffc5 6524
b232d4ed
NK		 6525 if (hdr_changed) {
6526 fill_hdr_info_packet(new_con_state, &hdr_packet);
6527 stream_update.hdr_static_metadata = &hdr_packet;
6528 }
6529
54d76575 6530 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 6531 WARN_ON(!status);
3be5262e 6532 WARN_ON(!status->plane_count);
e7b07cee 6533
02d6a6fc
DF		 6534 /*
6535 * TODO: DC refuses to perform stream updates without a dc_surface_update.
6536 * Here we create an empty update on each plane.
6537 * To fix this, DC should permit updating only stream properties.
6538 */
6539 for (j = 0; j < status->plane_count; j++)
6540 dummy_updates[j].surface = status->plane_states[0];
6541
6542
6543 mutex_lock(&dm->dc_lock);
6544 dc_commit_updates_for_stream(dm->dc,
6545 dummy_updates,
6546 status->plane_count,
6547 dm_new_crtc_state->stream,
6548 &stream_update,
6549 dc_state);
6550 mutex_unlock(&dm->dc_lock);
e7b07cee
HW		 6551 }
6552
b5e83f6f 6553 /* Count number of newly disabled CRTCs for dropping PM refs later. */
e1fc2dca 6554 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
057be086 6555 new_crtc_state, i) {
fe2a1965
LP		 6556 if (old_crtc_state->active && !new_crtc_state->active)
6557 crtc_disable_count++;
6558
54d76575 6559 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca 6560 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
66b0c973 6561
057be086
NK		 6562 /* Update freesync active state. */
6563 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
6564
66b0c973
MK		 6565 /* Handle vrr on->off / off->on transitions */
6566 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
6567 dm_new_crtc_state);
e7b07cee
HW		 6568 }
6569
b5e83f6f
NK		 6570 /* Enable interrupts for CRTCs going through a modeset. */
6571 amdgpu_dm_enable_crtc_interrupts(dev, state, true);
e7b07cee 6572
420cd472
DF		 6573 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
6574 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
6575 wait_for_vblank = false;
6576
e7b07cee 6577 /* update planes when needed per crtc*/
5cc6dcbd 6578 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 6579 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 6580
54d76575 6581 if (dm_new_crtc_state->stream)
eb3dc897 6582 amdgpu_dm_commit_planes(state, dc_state, dev,
420cd472 6583 dm, crtc, wait_for_vblank);
e7b07cee
HW		 6584 }
6585
b5e83f6f
NK		 6586 /* Enable interrupts for CRTCs going from 0 to n active planes. */
6587 amdgpu_dm_enable_crtc_interrupts(dev, state, false);
e7b07cee 6588
6ce8f316
NK		 6589 /* Update audio instances for each connector. */
6590 amdgpu_dm_commit_audio(dev, state);
6591
e7b07cee
HW		 6592 /*
6593 * send vblank event on all events not handled in flip and
6594 * mark consumed event for drm_atomic_helper_commit_hw_done
6595 */
6596 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 6597 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 6598
0bc9706d
LSL		 6599 if (new_crtc_state->event)
6600 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 6601
0bc9706d 6602 new_crtc_state->event = NULL;
e7b07cee
HW		 6603 }
6604 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6605
29c8f234
LL		 6606 /* Signal HW programming completion */
6607 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 6608
6609 if (wait_for_vblank)
320a1274 6610 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 6611
6612 drm_atomic_helper_cleanup_planes(dev, state);
97028037 6613
1f6010a9
DF		 6614 /*
6615 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 6616 * so we can put the GPU into runtime suspend if we're not driving any
6617 * displays anymore
6618 */
fe2a1965
LP		 6619 for (i = 0; i < crtc_disable_count; i++)
6620 pm_runtime_put_autosuspend(dev->dev);
97028037 6621 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 6622
6623 if (dc_state_temp)
6624 dc_release_state(dc_state_temp);
e7b07cee
HW		 6625}
6626
6627
6628static int dm_force_atomic_commit(struct drm_connector *connector)
6629{
6630 int ret = 0;
6631 struct drm_device *ddev = connector->dev;
6632 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
6633 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
6634 struct drm_plane *plane = disconnected_acrtc->base.primary;
6635 struct drm_connector_state *conn_state;
6636 struct drm_crtc_state *crtc_state;
6637 struct drm_plane_state *plane_state;
6638
6639 if (!state)
6640 return -ENOMEM;
6641
6642 state->acquire_ctx = ddev->mode_config.acquire_ctx;
6643
6644 /* Construct an atomic state to restore previous display setting */
6645
6646 /*
6647 * Attach connectors to drm_atomic_state
6648 */
6649 conn_state = drm_atomic_get_connector_state(state, connector);
6650
6651 ret = PTR_ERR_OR_ZERO(conn_state);
6652 if (ret)
6653 goto err;
6654
6655 /* Attach crtc to drm_atomic_state*/
6656 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
6657
6658 ret = PTR_ERR_OR_ZERO(crtc_state);
6659 if (ret)
6660 goto err;
6661
6662 /* force a restore */
6663 crtc_state->mode_changed = true;
6664
6665 /* Attach plane to drm_atomic_state */
6666 plane_state = drm_atomic_get_plane_state(state, plane);
6667
6668 ret = PTR_ERR_OR_ZERO(plane_state);
6669 if (ret)
6670 goto err;
6671
6672
6673 /* Call commit internally with the state we just constructed */
6674 ret = drm_atomic_commit(state);
6675 if (!ret)
6676 return 0;
6677
6678err:
6679 DRM_ERROR("Restoring old state failed with %i\n", ret);
6680 drm_atomic_state_put(state);
6681
6682 return ret;
6683}
6684
6685/*
1f6010a9
DF		 6686 * This function handles all cases when set mode does not come upon hotplug.
6687 * This includes when a display is unplugged then plugged back into the
6688 * same port and when running without usermode desktop manager supprot
e7b07cee 6689 */
3ee6b26b
AD		 6690void dm_restore_drm_connector_state(struct drm_device *dev,
6691 struct drm_connector *connector)
e7b07cee 6692{
c84dec2f 6693 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 6694 struct amdgpu_crtc *disconnected_acrtc;
6695 struct dm_crtc_state *acrtc_state;
6696
6697 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
6698 return;
6699
6700 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 6701 if (!disconnected_acrtc)
6702 return;
e7b07cee 6703
70e8ffc5
HW		 6704 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
6705 if (!acrtc_state->stream)
e7b07cee
HW		 6706 return;
6707
6708 /*
6709 * If the previous sink is not released and different from the current,
6710 * we deduce we are in a state where we can not rely on usermode call
6711 * to turn on the display, so we do it here
6712 */
6713 if (acrtc_state->stream->sink != aconnector->dc_sink)
6714 dm_force_atomic_commit(&aconnector->base);
6715}
6716
1f6010a9 6717/*
e7b07cee
HW		 6718 * Grabs all modesetting locks to serialize against any blocking commits,
6719 * Waits for completion of all non blocking commits.
6720 */
3ee6b26b
AD		 6721static int do_aquire_global_lock(struct drm_device *dev,
6722 struct drm_atomic_state *state)
e7b07cee
HW		 6723{
6724 struct drm_crtc *crtc;
6725 struct drm_crtc_commit *commit;
6726 long ret;
6727
1f6010a9
DF		 6728 /*
6729 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 6730 * ensure that when the framework release it the
6731 * extra locks we are locking here will get released to
6732 */
6733 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
6734 if (ret)
6735 return ret;
6736
6737 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6738 spin_lock(&crtc->commit_lock);
6739 commit = list_first_entry_or_null(&crtc->commit_list,
6740 struct drm_crtc_commit, commit_entry);
6741 if (commit)
6742 drm_crtc_commit_get(commit);
6743 spin_unlock(&crtc->commit_lock);
6744
6745 if (!commit)
6746 continue;
6747
1f6010a9
DF		 6748 /*
6749 * Make sure all pending HW programming completed and
e7b07cee
HW		 6750 * page flips done
6751 */
6752 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
6753
6754 if (ret > 0)
6755 ret = wait_for_completion_interruptible_timeout(
6756 &commit->flip_done, 10*HZ);
6757
6758 if (ret == 0)
6759 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 6760 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 6761
6762 drm_crtc_commit_put(commit);
6763 }
6764
6765 return ret < 0 ? ret : 0;
6766}
6767
bb47de73
NK		 6768static void get_freesync_config_for_crtc(
6769 struct dm_crtc_state *new_crtc_state,
6770 struct dm_connector_state *new_con_state)
98e6436d
AK		 6771{
6772 struct mod_freesync_config config = {0};
98e6436d
AK		 6773 struct amdgpu_dm_connector *aconnector =
6774 to_amdgpu_dm_connector(new_con_state->base.connector);
a057ec46 6775 struct drm_display_mode *mode = &new_crtc_state->base.mode;
0ab925d3 6776 int vrefresh = drm_mode_vrefresh(mode);
98e6436d 6777
a057ec46 6778 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
0ab925d3
NK		 6779 vrefresh >= aconnector->min_vfreq &&
6780 vrefresh <= aconnector->max_vfreq;
bb47de73 6781
a057ec46
IB		 6782 if (new_crtc_state->vrr_supported) {
6783 new_crtc_state->stream->ignore_msa_timing_param = true;
bb47de73 6784 config.state = new_crtc_state->base.vrr_enabled ?
98e6436d
AK		 6785 VRR_STATE_ACTIVE_VARIABLE :
6786 VRR_STATE_INACTIVE;
6787 config.min_refresh_in_uhz =
6788 aconnector->min_vfreq * 1000000;
6789 config.max_refresh_in_uhz =
6790 aconnector->max_vfreq * 1000000;
69ff8845 6791 config.vsif_supported = true;
180db303 6792 config.btr = true;
98e6436d
AK		 6793 }
6794
bb47de73
NK		 6795 new_crtc_state->freesync_config = config;
6796}
98e6436d 6797
bb47de73
NK		 6798static void reset_freesync_config_for_crtc(
6799 struct dm_crtc_state *new_crtc_state)
6800{
6801 new_crtc_state->vrr_supported = false;
98e6436d 6802
180db303
NK		 6803 memset(&new_crtc_state->vrr_params, 0,
6804 sizeof(new_crtc_state->vrr_params));
bb47de73
NK		 6805 memset(&new_crtc_state->vrr_infopacket, 0,
6806 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 6807}
6808
4b9674e5
LL		 6809static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
6810 struct drm_atomic_state *state,
6811 struct drm_crtc *crtc,
6812 struct drm_crtc_state *old_crtc_state,
6813 struct drm_crtc_state *new_crtc_state,
6814 bool enable,
6815 bool *lock_and_validation_needed)
e7b07cee 6816{
eb3dc897 6817 struct dm_atomic_state *dm_state = NULL;
54d76575 6818 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 6819 struct dc_stream_state *new_stream;
62f55537 6820 int ret = 0;
d4d4a645 6821
1f6010a9
DF		 6822 /*
6823 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
6824 * update changed items
6825 */
4b9674e5
LL		 6826 struct amdgpu_crtc *acrtc = NULL;
6827 struct amdgpu_dm_connector *aconnector = NULL;
6828 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
6829 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
e7b07cee 6830
4b9674e5 6831 new_stream = NULL;
9635b754 6832
4b9674e5
LL		 6833 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6834 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6835 acrtc = to_amdgpu_crtc(crtc);
4b9674e5 6836 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 6837
4b9674e5
LL		 6838 /* TODO This hack should go away */
6839 if (aconnector && enable) {
6840 /* Make sure fake sink is created in plug-in scenario */
6841 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
6842 &aconnector->base);
6843 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
6844 &aconnector->base);
19f89e23 6845
4b9674e5
LL		 6846 if (IS_ERR(drm_new_conn_state)) {
6847 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
6848 goto fail;
6849 }
19f89e23 6850
4b9674e5
LL		 6851 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
6852 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 6853
02d35a67
JFZ		 6854 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6855 goto skip_modeset;
6856
4b9674e5
LL		 6857 new_stream = create_stream_for_sink(aconnector,
6858 &new_crtc_state->mode,
6859 dm_new_conn_state,
6860 dm_old_crtc_state->stream);
19f89e23 6861
4b9674e5
LL		 6862 /*
6863 * we can have no stream on ACTION_SET if a display
6864 * was disconnected during S3, in this case it is not an
6865 * error, the OS will be updated after detection, and
6866 * will do the right thing on next atomic commit
6867 */
19f89e23 6868
4b9674e5
LL		 6869 if (!new_stream) {
6870 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6871 __func__, acrtc->base.base.id);
6872 ret = -ENOMEM;
6873 goto fail;
6874 }
e7b07cee 6875
4b9674e5 6876 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 6877
88694af9
NK		 6878 ret = fill_hdr_info_packet(drm_new_conn_state,
6879 &new_stream->hdr_static_metadata);
6880 if (ret)
6881 goto fail;
6882
7e930949
NK		 6883 /*
6884 * If we already removed the old stream from the context
6885 * (and set the new stream to NULL) then we can't reuse
6886 * the old stream even if the stream and scaling are unchanged.
6887 * We'll hit the BUG_ON and black screen.
6888 *
6889 * TODO: Refactor this function to allow this check to work
6890 * in all conditions.
6891 */
6892 if (dm_new_crtc_state->stream &&
6893 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4b9674e5
LL		 6894 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
6895 new_crtc_state->mode_changed = false;
6896 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
6897 new_crtc_state->mode_changed);
62f55537 6898 }
4b9674e5 6899 }
b830ebc9 6900
02d35a67 6901 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 6902 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6903 goto skip_modeset;
e7b07cee 6904
4b9674e5
LL		 6905 DRM_DEBUG_DRIVER(
6906 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6907 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6908 "connectors_changed:%d\n",
6909 acrtc->crtc_id,
6910 new_crtc_state->enable,
6911 new_crtc_state->active,
6912 new_crtc_state->planes_changed,
6913 new_crtc_state->mode_changed,
6914 new_crtc_state->active_changed,
6915 new_crtc_state->connectors_changed);
62f55537 6916
4b9674e5
LL		 6917 /* Remove stream for any changed/disabled CRTC */
6918 if (!enable) {
62f55537 6919
4b9674e5
LL		 6920 if (!dm_old_crtc_state->stream)
6921 goto skip_modeset;
eb3dc897 6922
4b9674e5
LL		 6923 ret = dm_atomic_get_state(state, &dm_state);
6924 if (ret)
6925 goto fail;
e7b07cee 6926
4b9674e5
LL		 6927 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
6928 crtc->base.id);
62f55537 6929
4b9674e5
LL		 6930 /* i.e. reset mode */
6931 if (dc_remove_stream_from_ctx(
6932 dm->dc,
6933 dm_state->context,
6934 dm_old_crtc_state->stream) != DC_OK) {
6935 ret = -EINVAL;
6936 goto fail;
6937 }
62f55537 6938
4b9674e5
LL		 6939 dc_stream_release(dm_old_crtc_state->stream);
6940 dm_new_crtc_state->stream = NULL;
bb47de73 6941
4b9674e5 6942 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 6943
4b9674e5 6944 *lock_and_validation_needed = true;
62f55537 6945
4b9674e5
LL		 6946 } else {/* Add stream for any updated/enabled CRTC */
6947 /*
6948 * Quick fix to prevent NULL pointer on new_stream when
6949 * added MST connectors not found in existing crtc_state in the chained mode
6950 * TODO: need to dig out the root cause of that
6951 */
6952 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
6953 goto skip_modeset;
62f55537 6954
4b9674e5
LL		 6955 if (modereset_required(new_crtc_state))
6956 goto skip_modeset;
62f55537 6957
4b9674e5
LL		 6958 if (modeset_required(new_crtc_state, new_stream,
6959 dm_old_crtc_state->stream)) {
62f55537 6960
4b9674e5 6961 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 6962
4b9674e5
LL		 6963 ret = dm_atomic_get_state(state, &dm_state);
6964 if (ret)
6965 goto fail;
27b3f4fc 6966
4b9674e5 6967 dm_new_crtc_state->stream = new_stream;
62f55537 6968
4b9674e5 6969 dc_stream_retain(new_stream);
1dc90497 6970
4b9674e5
LL		 6971 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
6972 crtc->base.id);
1dc90497 6973
4b9674e5
LL		 6974 if (dc_add_stream_to_ctx(
6975 dm->dc,
6976 dm_state->context,
6977 dm_new_crtc_state->stream) != DC_OK) {
6978 ret = -EINVAL;
6979 goto fail;
9b690ef3
BL		 6980 }
6981
4b9674e5
LL		 6982 *lock_and_validation_needed = true;
6983 }
6984 }
e277adc5 6985
4b9674e5
LL		 6986skip_modeset:
6987 /* Release extra reference */
6988 if (new_stream)
6989 dc_stream_release(new_stream);
e277adc5 6990
4b9674e5
LL		 6991 /*
6992 * We want to do dc stream updates that do not require a
6993 * full modeset below.
6994 */
6995 if (!(enable && aconnector && new_crtc_state->enable &&
6996 new_crtc_state->active))
6997 return 0;
6998 /*
6999 * Given above conditions, the dc state cannot be NULL because:
7000 * 1. We're in the process of enabling CRTCs (just been added
7001 * to the dc context, or already is on the context)
7002 * 2. Has a valid connector attached, and
7003 * 3. Is currently active and enabled.
7004 * => The dc stream state currently exists.
7005 */
7006 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 7007
4b9674e5
LL		 7008 /* Scaling or underscan settings */
7009 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
7010 update_stream_scaling_settings(
7011 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 7012
b05e2c5e
DF		 7013 /* ABM settings */
7014 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
7015
4b9674e5
LL		 7016 /*
7017 * Color management settings. We also update color properties
7018 * when a modeset is needed, to ensure it gets reprogrammed.
7019 */
7020 if (dm_new_crtc_state->base.color_mgmt_changed ||
7021 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
cf020d49 7022 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
4b9674e5
LL		 7023 if (ret)
7024 goto fail;
62f55537 7025 }
e7b07cee 7026
4b9674e5
LL		 7027 /* Update Freesync settings. */
7028 get_freesync_config_for_crtc(dm_new_crtc_state,
7029 dm_new_conn_state);
7030
62f55537 7031 return ret;
9635b754
DS		 7032
7033fail:
7034 if (new_stream)
7035 dc_stream_release(new_stream);
7036 return ret;
62f55537 7037}
9b690ef3 7038
f6ff2a08
NK		 7039static bool should_reset_plane(struct drm_atomic_state *state,
7040 struct drm_plane *plane,
7041 struct drm_plane_state *old_plane_state,
7042 struct drm_plane_state *new_plane_state)
7043{
7044 struct drm_plane *other;
7045 struct drm_plane_state *old_other_state, *new_other_state;
7046 struct drm_crtc_state *new_crtc_state;
7047 int i;
7048
70a1efac
NK		 7049 /*
7050 * TODO: Remove this hack once the checks below are sufficient
7051 * enough to determine when we need to reset all the planes on
7052 * the stream.
7053 */
7054 if (state->allow_modeset)
7055 return true;
7056
f6ff2a08
NK		 7057 /* Exit early if we know that we're adding or removing the plane. */
7058 if (old_plane_state->crtc != new_plane_state->crtc)
7059 return true;
7060
7061 /* old crtc == new_crtc == NULL, plane not in context. */
7062 if (!new_plane_state->crtc)
7063 return false;
7064
7065 new_crtc_state =
7066 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
7067
7068 if (!new_crtc_state)
7069 return true;
7070
7316c4ad
NK		 7071 /* CRTC Degamma changes currently require us to recreate planes. */
7072 if (new_crtc_state->color_mgmt_changed)
7073 return true;
7074
f6ff2a08
NK		 7075 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
7076 return true;
7077
7078 /*
7079 * If there are any new primary or overlay planes being added or
7080 * removed then the z-order can potentially change. To ensure
7081 * correct z-order and pipe acquisition the current DC architecture
7082 * requires us to remove and recreate all existing planes.
7083 *
7084 * TODO: Come up with a more elegant solution for this.
7085 */
7086 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
7087 if (other->type == DRM_PLANE_TYPE_CURSOR)
7088 continue;
7089
7090 if (old_other_state->crtc != new_plane_state->crtc &&
7091 new_other_state->crtc != new_plane_state->crtc)
7092 continue;
7093
7094 if (old_other_state->crtc != new_other_state->crtc)
7095 return true;
7096
7097 /* TODO: Remove this once we can handle fast format changes. */
7098 if (old_other_state->fb && new_other_state->fb &&
7099 old_other_state->fb->format != new_other_state->fb->format)
7100 return true;
7101 }
7102
7103 return false;
7104}
7105
9e869063
LL		 7106static int dm_update_plane_state(struct dc *dc,
7107 struct drm_atomic_state *state,
7108 struct drm_plane *plane,
7109 struct drm_plane_state *old_plane_state,
7110 struct drm_plane_state *new_plane_state,
7111 bool enable,
7112 bool *lock_and_validation_needed)
62f55537 7113{
eb3dc897
NK		 7114
7115 struct dm_atomic_state *dm_state = NULL;
62f55537 7116 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 7117 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 7118 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 7119 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
f6ff2a08 7120 bool needs_reset;
62f55537 7121 int ret = 0;
e7b07cee 7122
9b690ef3 7123
9e869063
LL		 7124 new_plane_crtc = new_plane_state->crtc;
7125 old_plane_crtc = old_plane_state->crtc;
7126 dm_new_plane_state = to_dm_plane_state(new_plane_state);
7127 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 7128
9e869063
LL		 7129 /*TODO Implement atomic check for cursor plane */
7130 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7131 return 0;
9b690ef3 7132
f6ff2a08
NK		 7133 needs_reset = should_reset_plane(state, plane, old_plane_state,
7134 new_plane_state);
7135
9e869063
LL		 7136 /* Remove any changed/removed planes */
7137 if (!enable) {
f6ff2a08 7138 if (!needs_reset)
9e869063 7139 return 0;
a7b06724 7140
9e869063
LL		 7141 if (!old_plane_crtc)
7142 return 0;
62f55537 7143
9e869063
LL		 7144 old_crtc_state = drm_atomic_get_old_crtc_state(
7145 state, old_plane_crtc);
7146 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 7147
9e869063
LL		 7148 if (!dm_old_crtc_state->stream)
7149 return 0;
62f55537 7150
9e869063
LL		 7151 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
7152 plane->base.id, old_plane_crtc->base.id);
9b690ef3 7153
9e869063
LL		 7154 ret = dm_atomic_get_state(state, &dm_state);
7155 if (ret)
7156 return ret;
eb3dc897 7157
9e869063
LL		 7158 if (!dc_remove_plane_from_context(
7159 dc,
7160 dm_old_crtc_state->stream,
7161 dm_old_plane_state->dc_state,
7162 dm_state->context)) {
62f55537 7163
9e869063
LL		 7164 ret = EINVAL;
7165 return ret;
7166 }
e7b07cee 7167
9b690ef3 7168
9e869063
LL		 7169 dc_plane_state_release(dm_old_plane_state->dc_state);
7170 dm_new_plane_state->dc_state = NULL;
1dc90497 7171
9e869063 7172 *lock_and_validation_needed = true;
1dc90497 7173
9e869063
LL		 7174 } else { /* Add new planes */
7175 struct dc_plane_state *dc_new_plane_state;
1dc90497 7176
9e869063
LL		 7177 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
7178 return 0;
e7b07cee 7179
9e869063
LL		 7180 if (!new_plane_crtc)
7181 return 0;
e7b07cee 7182
9e869063
LL		 7183 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
7184 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 7185
9e869063
LL		 7186 if (!dm_new_crtc_state->stream)
7187 return 0;
62f55537 7188
f6ff2a08 7189 if (!needs_reset)
9e869063 7190 return 0;
62f55537 7191
9e869063 7192 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 7193
9e869063
LL		 7194 dc_new_plane_state = dc_create_plane_state(dc);
7195 if (!dc_new_plane_state)
7196 return -ENOMEM;
62f55537 7197
9e869063
LL		 7198 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
7199 plane->base.id, new_plane_crtc->base.id);
8c45c5db 7200
695af5f9 7201 ret = fill_dc_plane_attributes(
9e869063
LL		 7202 new_plane_crtc->dev->dev_private,
7203 dc_new_plane_state,
7204 new_plane_state,
7205 new_crtc_state);
7206 if (ret) {
7207 dc_plane_state_release(dc_new_plane_state);
7208 return ret;
7209 }
62f55537 7210
9e869063
LL		 7211 ret = dm_atomic_get_state(state, &dm_state);
7212 if (ret) {
7213 dc_plane_state_release(dc_new_plane_state);
7214 return ret;
7215 }
eb3dc897 7216
9e869063
LL		 7217 /*
7218 * Any atomic check errors that occur after this will
7219 * not need a release. The plane state will be attached
7220 * to the stream, and therefore part of the atomic
7221 * state. It'll be released when the atomic state is
7222 * cleaned.
7223 */
7224 if (!dc_add_plane_to_context(
7225 dc,
7226 dm_new_crtc_state->stream,
7227 dc_new_plane_state,
7228 dm_state->context)) {
62f55537 7229
9e869063
LL		 7230 dc_plane_state_release(dc_new_plane_state);
7231 return -EINVAL;
7232 }
8c45c5db 7233
9e869063 7234 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 7235
9e869063
LL		 7236 /* Tell DC to do a full surface update every time there
7237 * is a plane change. Inefficient, but works for now.
7238 */
7239 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
7240
7241 *lock_and_validation_needed = true;
62f55537 7242 }
e7b07cee
HW		 7243
7244
62f55537
AG		 7245 return ret;
7246}
a87fa993 7247
eb3dc897 7248static int
f843b308 7249dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
eb3dc897
NK		 7250 struct drm_atomic_state *state,
7251 enum surface_update_type *out_type)
7252{
f843b308 7253 struct dc *dc = dm->dc;
eb3dc897
NK		 7254 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
7255 int i, j, num_plane, ret = 0;
a87fa993
BL		 7256 struct drm_plane_state *old_plane_state, *new_plane_state;
7257 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
7258 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
7259 struct drm_plane *plane;
7260
7261 struct drm_crtc *crtc;
7262 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
7263 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
7264 struct dc_stream_status *status = NULL;
7265
fe96b99d 7266 struct dc_surface_update *updates;
a87fa993
BL		 7267 enum surface_update_type update_type = UPDATE_TYPE_FAST;
7268
fe96b99d 7269 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
fe96b99d 7270
f843b308
NK		 7271 if (!updates) {
7272 DRM_ERROR("Failed to allocate plane updates\n");
4f712911
BL		 7273 /* Set type to FULL to avoid crashing in DC*/
7274 update_type = UPDATE_TYPE_FULL;
eb3dc897 7275 goto cleanup;
4f712911 7276 }
a87fa993
BL		 7277
7278 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
004b3938 7279 struct dc_scaling_info scaling_info;
2aa632c5
NK		 7280 struct dc_stream_update stream_update;
7281
7282 memset(&stream_update, 0, sizeof(stream_update));
c448a53a 7283
a87fa993
BL		 7284 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7285 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
7286 num_plane = 0;
7287
6836d239
NK		 7288 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
7289 update_type = UPDATE_TYPE_FULL;
7290 goto cleanup;
7291 }
a87fa993 7292
6836d239 7293 if (!new_dm_crtc_state->stream)
c744e974 7294 continue;
eb3dc897 7295
c744e974 7296 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
2cc450ce
NK		 7297 const struct amdgpu_framebuffer *amdgpu_fb =
7298 to_amdgpu_framebuffer(new_plane_state->fb);
7299 struct dc_plane_info plane_info;
7300 struct dc_flip_addrs flip_addr;
7301 uint64_t tiling_flags;
7302
c744e974
NK		 7303 new_plane_crtc = new_plane_state->crtc;
7304 old_plane_crtc = old_plane_state->crtc;
7305 new_dm_plane_state = to_dm_plane_state(new_plane_state);
7306 old_dm_plane_state = to_dm_plane_state(old_plane_state);
eb3dc897 7307
c744e974
NK		 7308 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7309 continue;
eb3dc897 7310
6836d239
NK		 7311 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
7312 update_type = UPDATE_TYPE_FULL;
7313 goto cleanup;
7314 }
7315
c744e974
NK		 7316 if (crtc != new_plane_crtc)
7317 continue;
7318
f843b308 7319 updates[num_plane].surface = new_dm_plane_state->dc_state;
c744e974
NK		 7320
7321 if (new_crtc_state->mode_changed) {
c744e974
NK		 7322 stream_update.dst = new_dm_crtc_state->stream->dst;
7323 stream_update.src = new_dm_crtc_state->stream->src;
7324 }
7325
7326 if (new_crtc_state->color_mgmt_changed) {
7327 updates[num_plane].gamma =
7328 new_dm_plane_state->dc_state->gamma_correction;
7329 updates[num_plane].in_transfer_func =
7330 new_dm_plane_state->dc_state->in_transfer_func;
7331 stream_update.gamut_remap =
7332 &new_dm_crtc_state->stream->gamut_remap_matrix;
cf020d49
NK		 7333 stream_update.output_csc_transform =
7334 &new_dm_crtc_state->stream->csc_color_matrix;
c744e974
NK		 7335 stream_update.out_transfer_func =
7336 new_dm_crtc_state->stream->out_transfer_func;
a87fa993
BL		 7337 }
7338
004b3938
NK		 7339 ret = fill_dc_scaling_info(new_plane_state,
7340 &scaling_info);
7341 if (ret)
7342 goto cleanup;
7343
7344 updates[num_plane].scaling_info = &scaling_info;
7345
2cc450ce
NK		 7346 if (amdgpu_fb) {
7347 ret = get_fb_info(amdgpu_fb, &tiling_flags);
7348 if (ret)
7349 goto cleanup;
7350
7351 memset(&flip_addr, 0, sizeof(flip_addr));
7352
7353 ret = fill_dc_plane_info_and_addr(
7354 dm->adev, new_plane_state, tiling_flags,
7355 &plane_info,
7356 &flip_addr.address);
7357 if (ret)
7358 goto cleanup;
7359
7360 updates[num_plane].plane_info = &plane_info;
7361 updates[num_plane].flip_addr = &flip_addr;
7362 }
7363
c744e974
NK		 7364 num_plane++;
7365 }
7366
7367 if (num_plane == 0)
7368 continue;
7369
7370 ret = dm_atomic_get_state(state, &dm_state);
7371 if (ret)
7372 goto cleanup;
7373
7374 old_dm_state = dm_atomic_get_old_state(state);
7375 if (!old_dm_state) {
7376 ret = -EINVAL;
7377 goto cleanup;
7378 }
7379
7380 status = dc_stream_get_status_from_state(old_dm_state->context,
7381 new_dm_crtc_state->stream);
b6e881c9 7382 stream_update.stream = new_dm_crtc_state->stream;
f843b308
NK		 7383 /*
7384 * TODO: DC modifies the surface during this call so we need
7385 * to lock here - find a way to do this without locking.
7386 */
7387 mutex_lock(&dm->dc_lock);
c744e974
NK		 7388 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
7389 &stream_update, status);
f843b308 7390 mutex_unlock(&dm->dc_lock);
c744e974
NK		 7391
7392 if (update_type > UPDATE_TYPE_MED) {
a87fa993 7393 update_type = UPDATE_TYPE_FULL;
eb3dc897 7394 goto cleanup;
a87fa993
BL		 7395 }
7396 }
7397
eb3dc897 7398cleanup:
a87fa993 7399 kfree(updates);
a87fa993 7400
eb3dc897
NK		 7401 *out_type = update_type;
7402 return ret;
a87fa993 7403}
62f55537 7404
b8592b48
LL		 7405/**
7406 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
7407 * @dev: The DRM device
7408 * @state: The atomic state to commit
7409 *
7410 * Validate that the given atomic state is programmable by DC into hardware.
7411 * This involves constructing a &struct dc_state reflecting the new hardware
7412 * state we wish to commit, then querying DC to see if it is programmable. It's
7413 * important not to modify the existing DC state. Otherwise, atomic_check
7414 * may unexpectedly commit hardware changes.
7415 *
7416 * When validating the DC state, it's important that the right locks are
7417 * acquired. For full updates case which removes/adds/updates streams on one
7418 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
7419 * that any such full update commit will wait for completion of any outstanding
7420 * flip using DRMs synchronization events. See
7421 * dm_determine_update_type_for_commit()
7422 *
7423 * Note that DM adds the affected connectors for all CRTCs in state, when that
7424 * might not seem necessary. This is because DC stream creation requires the
7425 * DC sink, which is tied to the DRM connector state. Cleaning this up should
7426 * be possible but non-trivial - a possible TODO item.
7427 *
7428 * Return: -Error code if validation failed.
7429 */
7578ecda
AD		 7430static int amdgpu_dm_atomic_check(struct drm_device *dev,
7431 struct drm_atomic_state *state)
62f55537 7432{
62f55537 7433 struct amdgpu_device *adev = dev->dev_private;
eb3dc897 7434 struct dm_atomic_state *dm_state = NULL;
62f55537 7435 struct dc *dc = adev->dm.dc;
62f55537 7436 struct drm_connector *connector;
c2cea706 7437 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 7438 struct drm_crtc *crtc;
fc9e9920 7439 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 7440 struct drm_plane *plane;
7441 struct drm_plane_state *old_plane_state, *new_plane_state;
a87fa993
BL		 7442 enum surface_update_type update_type = UPDATE_TYPE_FAST;
7443 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
7444
1e88ad0a 7445 int ret, i;
e7b07cee 7446
62f55537
AG		 7447 /*
7448 * This bool will be set for true for any modeset/reset
7449 * or plane update which implies non fast surface update.
7450 */
7451 bool lock_and_validation_needed = false;
7452
7453 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 7454 if (ret)
7455 goto fail;
62f55537 7456
1e88ad0a
S		 7457 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7458 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 7459 !new_crtc_state->color_mgmt_changed &&
a93587b3 7460 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
1e88ad0a 7461 continue;
7bef1af3 7462
1e88ad0a
S		 7463 if (!new_crtc_state->enable)
7464 continue;
fc9e9920 7465
1e88ad0a
S		 7466 ret = drm_atomic_add_affected_connectors(state, crtc);
7467 if (ret)
7468 return ret;
fc9e9920 7469
1e88ad0a
S		 7470 ret = drm_atomic_add_affected_planes(state, crtc);
7471 if (ret)
7472 goto fail;
e7b07cee
HW		 7473 }
7474
2d9e6431
NK		 7475 /*
7476 * Add all primary and overlay planes on the CRTC to the state
7477 * whenever a plane is enabled to maintain correct z-ordering
7478 * and to enable fast surface updates.
7479 */
7480 drm_for_each_crtc(crtc, dev) {
7481 bool modified = false;
7482
7483 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7484 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7485 continue;
7486
7487 if (new_plane_state->crtc == crtc ||
7488 old_plane_state->crtc == crtc) {
7489 modified = true;
7490 break;
7491 }
7492 }
7493
7494 if (!modified)
7495 continue;
7496
7497 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
7498 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7499 continue;
7500
7501 new_plane_state =
7502 drm_atomic_get_plane_state(state, plane);
7503
7504 if (IS_ERR(new_plane_state)) {
7505 ret = PTR_ERR(new_plane_state);
7506 goto fail;
7507 }
7508 }
7509 }
7510
62f55537 7511 /* Remove exiting planes if they are modified */
9e869063
LL		 7512 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7513 ret = dm_update_plane_state(dc, state, plane,
7514 old_plane_state,
7515 new_plane_state,
7516 false,
7517 &lock_and_validation_needed);
7518 if (ret)
7519 goto fail;
62f55537
AG		 7520 }
7521
7522 /* Disable all crtcs which require disable */
4b9674e5
LL		 7523 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7524 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7525 old_crtc_state,
7526 new_crtc_state,
7527 false,
7528 &lock_and_validation_needed);
7529 if (ret)
7530 goto fail;
62f55537
AG		 7531 }
7532
7533 /* Enable all crtcs which require enable */
4b9674e5
LL		 7534 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7535 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7536 old_crtc_state,
7537 new_crtc_state,
7538 true,
7539 &lock_and_validation_needed);
7540 if (ret)
7541 goto fail;
62f55537
AG		 7542 }
7543
7544 /* Add new/modified planes */
9e869063
LL		 7545 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7546 ret = dm_update_plane_state(dc, state, plane,
7547 old_plane_state,
7548 new_plane_state,
7549 true,
7550 &lock_and_validation_needed);
7551 if (ret)
7552 goto fail;
62f55537
AG		 7553 }
7554
b349f76e
ES		 7555 /* Run this here since we want to validate the streams we created */
7556 ret = drm_atomic_helper_check_planes(dev, state);
7557 if (ret)
7558 goto fail;
62f55537 7559
43d10d30
NK		 7560 if (state->legacy_cursor_update) {
7561 /*
7562 * This is a fast cursor update coming from the plane update
7563 * helper, check if it can be done asynchronously for better
7564 * performance.
7565 */
7566 state->async_update =
7567 !drm_atomic_helper_async_check(dev, state);
7568
7569 /*
7570 * Skip the remaining global validation if this is an async
7571 * update. Cursor updates can be done without affecting
7572 * state or bandwidth calcs and this avoids the performance
7573 * penalty of locking the private state object and
7574 * allocating a new dc_state.
7575 */
7576 if (state->async_update)
7577 return 0;
7578 }
7579
ebdd27e1 7580 /* Check scaling and underscan changes*/
1f6010a9 7581 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 7582 * new stream into context w\o causing full reset. Need to
7583 * decide how to handle.
7584 */
c2cea706 7585 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 7586 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
7587 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
7588 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 7589
7590 /* Skip any modesets/resets */
0bc9706d
LSL		 7591 if (!acrtc || drm_atomic_crtc_needs_modeset(
7592 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 7593 continue;
7594
b830ebc9 7595 /* Skip any thing not scale or underscan changes */
54d76575 7596 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 7597 continue;
7598
a87fa993 7599 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 7600 lock_and_validation_needed = true;
7601 }
7602
f843b308 7603 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
eb3dc897
NK		 7604 if (ret)
7605 goto fail;
a87fa993
BL		 7606
7607 if (overall_update_type < update_type)
7608 overall_update_type = update_type;
7609
7610 /*
7611 * lock_and_validation_needed was an old way to determine if we need to set
7612 * the global lock. Leaving it in to check if we broke any corner cases
7613 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
7614 * lock_and_validation_needed false = UPDATE_TYPE_FAST
7615 */
7616 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
7617 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
e7b07cee 7618
a87fa993 7619 if (overall_update_type > UPDATE_TYPE_FAST) {
eb3dc897
NK		 7620 ret = dm_atomic_get_state(state, &dm_state);
7621 if (ret)
7622 goto fail;
e7b07cee
HW		 7623
7624 ret = do_aquire_global_lock(dev, state);
7625 if (ret)
7626 goto fail;
1dc90497 7627
afcd526b 7628 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
e7b07cee
HW		 7629 ret = -EINVAL;
7630 goto fail;
7631 }
bd200d19 7632 } else {
674e78ac 7633 /*
bd200d19
NK		 7634 * The commit is a fast update. Fast updates shouldn't change
7635 * the DC context, affect global validation, and can have their
7636 * commit work done in parallel with other commits not touching
7637 * the same resource. If we have a new DC context as part of
7638 * the DM atomic state from validation we need to free it and
7639 * retain the existing one instead.
674e78ac 7640 */
bd200d19
NK		 7641 struct dm_atomic_state *new_dm_state, *old_dm_state;
7642
7643 new_dm_state = dm_atomic_get_new_state(state);
7644 old_dm_state = dm_atomic_get_old_state(state);
7645
7646 if (new_dm_state && old_dm_state) {
7647 if (new_dm_state->context)
7648 dc_release_state(new_dm_state->context);
7649
7650 new_dm_state->context = old_dm_state->context;
7651
7652 if (old_dm_state->context)
7653 dc_retain_state(old_dm_state->context);
7654 }
e7b07cee
HW		 7655 }
7656
caff0e66
NK		 7657 /* Store the overall update type for use later in atomic check. */
7658 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
7659 struct dm_crtc_state *dm_new_crtc_state =
7660 to_dm_crtc_state(new_crtc_state);
7661
7662 dm_new_crtc_state->update_type = (int)overall_update_type;
e7b07cee
HW		 7663 }
7664
7665 /* Must be success */
7666 WARN_ON(ret);
7667 return ret;
7668
7669fail:
7670 if (ret == -EDEADLK)
01e28f9c 7671 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 7672 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 7673 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 7674 else
01e28f9c 7675 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 7676
7677 return ret;
7678}
7679
3ee6b26b
AD		 7680static bool is_dp_capable_without_timing_msa(struct dc *dc,
7681 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 7682{
7683 uint8_t dpcd_data;
7684 bool capable = false;
7685
c84dec2f 7686 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 7687 dm_helpers_dp_read_dpcd(
7688 NULL,
c84dec2f 7689 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 7690 DP_DOWN_STREAM_PORT_COUNT,
7691 &dpcd_data,
7692 sizeof(dpcd_data))) {
7693 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
7694 }
7695
7696 return capable;
7697}
98e6436d
AK		 7698void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
7699 struct edid *edid)
e7b07cee
HW		 7700{
7701 int i;
e7b07cee
HW		 7702 bool edid_check_required;
7703 struct detailed_timing *timing;
7704 struct detailed_non_pixel *data;
7705 struct detailed_data_monitor_range *range;
c84dec2f
HW		 7706 struct amdgpu_dm_connector *amdgpu_dm_connector =
7707 to_amdgpu_dm_connector(connector);
bb47de73 7708 struct dm_connector_state *dm_con_state = NULL;
e7b07cee
HW		 7709
7710 struct drm_device *dev = connector->dev;
7711 struct amdgpu_device *adev = dev->dev_private;
bb47de73 7712 bool freesync_capable = false;
b830ebc9 7713
8218d7f1
HW		 7714 if (!connector->state) {
7715 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 7716 goto update;
8218d7f1
HW		 7717 }
7718
98e6436d
AK		 7719 if (!edid) {
7720 dm_con_state = to_dm_connector_state(connector->state);
7721
7722 amdgpu_dm_connector->min_vfreq = 0;
7723 amdgpu_dm_connector->max_vfreq = 0;
7724 amdgpu_dm_connector->pixel_clock_mhz = 0;
7725
bb47de73 7726 goto update;
98e6436d
AK		 7727 }
7728
8218d7f1
HW		 7729 dm_con_state = to_dm_connector_state(connector->state);
7730
e7b07cee 7731 edid_check_required = false;
c84dec2f 7732 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee 7733 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
bb47de73 7734 goto update;
e7b07cee
HW		 7735 }
7736 if (!adev->dm.freesync_module)
bb47de73 7737 goto update;
e7b07cee
HW		 7738 /*
7739 * if edid non zero restrict freesync only for dp and edp
7740 */
7741 if (edid) {
c84dec2f
HW		 7742 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
7743 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 7744 edid_check_required = is_dp_capable_without_timing_msa(
7745 adev->dm.dc,
c84dec2f 7746 amdgpu_dm_connector);
e7b07cee
HW		 7747 }
7748 }
e7b07cee
HW		 7749 if (edid_check_required == true && (edid->version > 1 ||
7750 (edid->version == 1 && edid->revision > 1))) {
7751 for (i = 0; i < 4; i++) {
7752
7753 timing = &edid->detailed_timings[i];
7754 data = &timing->data.other_data;
7755 range = &data->data.range;
7756 /*
7757 * Check if monitor has continuous frequency mode
7758 */
7759 if (data->type != EDID_DETAIL_MONITOR_RANGE)
7760 continue;
7761 /*
7762 * Check for flag range limits only. If flag == 1 then
7763 * no additional timing information provided.
7764 * Default GTF, GTF Secondary curve and CVT are not
7765 * supported
7766 */
7767 if (range->flags != 1)
7768 continue;
7769
c84dec2f
HW		 7770 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
7771 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
7772 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 7773 range->pixel_clock_mhz * 10;
7774 break;
7775 }
7776
c84dec2f 7777 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 7778 amdgpu_dm_connector->min_vfreq > 10) {
7779
bb47de73 7780 freesync_capable = true;
e7b07cee
HW		 7781 }
7782 }
bb47de73
NK		 7783
7784update:
7785 if (dm_con_state)
7786 dm_con_state->freesync_capable = freesync_capable;
7787
7788 if (connector->vrr_capable_property)
7789 drm_connector_set_vrr_capable_property(connector,
7790 freesync_capable);
e7b07cee
HW		 7791}
7792
8c322309
RL		 7793static void amdgpu_dm_set_psr_caps(struct dc_link *link)
7794{
7795 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
7796
7797 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
7798 return;
7799 if (link->type == dc_connection_none)
7800 return;
7801 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
7802 dpcd_data, sizeof(dpcd_data))) {
7803 link->psr_feature_enabled = dpcd_data[0] ? true:false;
7804 DRM_INFO("PSR support:%d\n", link->psr_feature_enabled);
7805 }
7806}
7807
7808/*
7809 * amdgpu_dm_link_setup_psr() - configure psr link
7810 * @stream: stream state
7811 *
7812 * Return: true if success
7813 */
7814static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
7815{
7816 struct dc_link *link = NULL;
7817 struct psr_config psr_config = {0};
7818 struct psr_context psr_context = {0};
7819 struct dc *dc = NULL;
7820 bool ret = false;
7821
7822 if (stream == NULL)
7823 return false;
7824
7825 link = stream->link;
7826 dc = link->ctx->dc;
7827
7828 psr_config.psr_version = dc->res_pool->dmcu->dmcu_version.psr_version;
7829
7830 if (psr_config.psr_version > 0) {
7831 psr_config.psr_exit_link_training_required = 0x1;
7832 psr_config.psr_frame_capture_indication_req = 0;
7833 psr_config.psr_rfb_setup_time = 0x37;
7834 psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
7835 psr_config.allow_smu_optimizations = 0x0;
7836
7837 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
7838
7839 }
7840 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_feature_enabled);
7841
7842 return ret;
7843}
7844
7845/*
7846 * amdgpu_dm_psr_enable() - enable psr f/w
7847 * @stream: stream state
7848 *
7849 * Return: true if success
7850 */
7851bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
7852{
7853 struct dc_link *link = stream->link;
7854 struct dc_static_screen_events triggers = {0};
7855
7856 DRM_DEBUG_DRIVER("Enabling psr...\n");
7857
7858 triggers.cursor_update = true;
7859 triggers.overlay_update = true;
7860 triggers.surface_update = true;
7861
7862 dc_stream_set_static_screen_events(link->ctx->dc,
7863 &stream, 1,
7864 &triggers);
7865
7866 return dc_link_set_psr_allow_active(link, true, false);
7867}
7868
7869/*
7870 * amdgpu_dm_psr_disable() - disable psr f/w
7871 * @stream: stream state
7872 *
7873 * Return: true if success
7874 */
7875static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
7876{
7877
7878 DRM_DEBUG_DRIVER("Disabling psr...\n");
7879
7880 return dc_link_set_psr_allow_active(stream->link, false, true);
7881}
Linux 6.x block layer and io_uring tree(s)