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drm/amd/display: dal 3.1.37
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
ad941f7a
FX		 62#include "dcn/dcn_1_0_offset.h"
63#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 64#include "soc15_hw_ip.h"
65#include "vega10_ip_offset.h"
ff5ef992
AD		 66
67#include "soc15_common.h"
68#endif
69
e7b07cee
HW		 70#include "modules/inc/mod_freesync.h"
71
72#include "i2caux_interface.h"
73
7578ecda
AD		 74/* basic init/fini API */
75static int amdgpu_dm_init(struct amdgpu_device *adev);
76static void amdgpu_dm_fini(struct amdgpu_device *adev);
77
78/* initializes drm_device display related structures, based on the information
79 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
80 * drm_encoder, drm_mode_config
81 *
82 * Returns 0 on success
83 */
84static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
85/* removes and deallocates the drm structures, created by the above function */
86static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
87
88static void
89amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
90
91static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
92 struct amdgpu_plane *aplane,
93 unsigned long possible_crtcs);
94static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
95 struct drm_plane *plane,
96 uint32_t link_index);
97static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
98 struct amdgpu_dm_connector *amdgpu_dm_connector,
99 uint32_t link_index,
100 struct amdgpu_encoder *amdgpu_encoder);
101static int amdgpu_dm_encoder_init(struct drm_device *dev,
102 struct amdgpu_encoder *aencoder,
103 uint32_t link_index);
104
105static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
106
107static int amdgpu_dm_atomic_commit(struct drm_device *dev,
108 struct drm_atomic_state *state,
109 bool nonblock);
110
111static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
112
113static int amdgpu_dm_atomic_check(struct drm_device *dev,
114 struct drm_atomic_state *state);
115
116
117
e7b07cee 118
e04a6123 119static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125 DRM_PLANE_TYPE_PRIMARY,
126};
127
e04a6123 128static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_PRIMARY,
132 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
133};
134
e04a6123 135static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_PRIMARY,
138 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
139};
140
4562236b
HW		 141/*
142 * dm_vblank_get_counter
143 *
144 * @brief
145 * Get counter for number of vertical blanks
146 *
147 * @param
148 * struct amdgpu_device *adev - [in] desired amdgpu device
149 * int disp_idx - [in] which CRTC to get the counter from
150 *
151 * @return
152 * Counter for vertical blanks
153 */
154static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
155{
156 if (crtc >= adev->mode_info.num_crtc)
157 return 0;
158 else {
159 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 160 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
161 acrtc->base.state);
4562236b 162
da5c47f6
AG		 163
164 if (acrtc_state->stream == NULL) {
0971c40e
HW		 165 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
166 crtc);
4562236b
HW		 167 return 0;
168 }
169
da5c47f6 170 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 171 }
172}
173
174static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 175 u32 *vbl, u32 *position)
4562236b 176{
81c50963
ST		 177 uint32_t v_blank_start, v_blank_end, h_position, v_position;
178
4562236b
HW		 179 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
180 return -EINVAL;
181 else {
182 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 183 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
184 acrtc->base.state);
4562236b 185
da5c47f6 186 if (acrtc_state->stream == NULL) {
0971c40e
HW		 187 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
188 crtc);
4562236b
HW		 189 return 0;
190 }
191
81c50963
ST		 192 /*
193 * TODO rework base driver to use values directly.
194 * for now parse it back into reg-format
195 */
da5c47f6 196 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 197 &v_blank_start,
198 &v_blank_end,
199 &h_position,
200 &v_position);
201
e806208d
AG		 202 *position = v_position | (h_position << 16);
203 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 204 }
205
206 return 0;
207}
208
209static bool dm_is_idle(void *handle)
210{
211 /* XXX todo */
212 return true;
213}
214
215static int dm_wait_for_idle(void *handle)
216{
217 /* XXX todo */
218 return 0;
219}
220
221static bool dm_check_soft_reset(void *handle)
222{
223 return false;
224}
225
226static int dm_soft_reset(void *handle)
227{
228 /* XXX todo */
229 return 0;
230}
231
3ee6b26b
AD		 232static struct amdgpu_crtc *
233get_crtc_by_otg_inst(struct amdgpu_device *adev,
234 int otg_inst)
4562236b
HW		 235{
236 struct drm_device *dev = adev->ddev;
237 struct drm_crtc *crtc;
238 struct amdgpu_crtc *amdgpu_crtc;
239
240 /*
241 * following if is check inherited from both functions where this one is
242 * used now. Need to be checked why it could happen.
243 */
244 if (otg_inst == -1) {
245 WARN_ON(1);
246 return adev->mode_info.crtcs[0];
247 }
248
249 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
250 amdgpu_crtc = to_amdgpu_crtc(crtc);
251
252 if (amdgpu_crtc->otg_inst == otg_inst)
253 return amdgpu_crtc;
254 }
255
256 return NULL;
257}
258
259static void dm_pflip_high_irq(void *interrupt_params)
260{
4562236b
HW		 261 struct amdgpu_crtc *amdgpu_crtc;
262 struct common_irq_params *irq_params = interrupt_params;
263 struct amdgpu_device *adev = irq_params->adev;
264 unsigned long flags;
265
266 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
267
268 /* IRQ could occur when in initial stage */
269 /*TODO work and BO cleanup */
270 if (amdgpu_crtc == NULL) {
271 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
272 return;
273 }
274
275 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 276
277 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
278 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
279 amdgpu_crtc->pflip_status,
280 AMDGPU_FLIP_SUBMITTED,
281 amdgpu_crtc->crtc_id,
282 amdgpu_crtc);
283 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
284 return;
285 }
286
4562236b
HW		 287
288 /* wakeup usersapce */
1159898a 289 if (amdgpu_crtc->event) {
753c66c9
MK		 290 /* Update to correct count/ts if racing with vblank irq */
291 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
292
54f5499a 293 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 294
54f5499a
AG		 295 /* page flip completed. clean up */
296 amdgpu_crtc->event = NULL;
1159898a 297
54f5499a
AG		 298 } else
299 WARN_ON(1);
4562236b 300
54f5499a 301 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 302 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
303
54f5499a
AG		 304 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
305 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 306
307 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 308}
309
310static void dm_crtc_high_irq(void *interrupt_params)
311{
312 struct common_irq_params *irq_params = interrupt_params;
313 struct amdgpu_device *adev = irq_params->adev;
314 uint8_t crtc_index = 0;
315 struct amdgpu_crtc *acrtc;
316
b57de80a 317 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 318
319 if (acrtc)
320 crtc_index = acrtc->crtc_id;
321
322 drm_handle_vblank(adev->ddev, crtc_index);
31aec354 323 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
4562236b
HW		 324}
325
326static int dm_set_clockgating_state(void *handle,
327 enum amd_clockgating_state state)
328{
329 return 0;
330}
331
332static int dm_set_powergating_state(void *handle,
333 enum amd_powergating_state state)
334{
335 return 0;
336}
337
338/* Prototypes of private functions */
339static int dm_early_init(void* handle);
340
341static void hotplug_notify_work_func(struct work_struct *work)
342{
343 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
344 struct drm_device *dev = dm->ddev;
345
346 drm_kms_helper_hotplug_event(dev);
347}
348
6ef39a62 349#if defined(CONFIG_DRM_AMD_DC_FBC)
a32e24b4 350/* Allocate memory for FBC compressed data */
3e332d3a 351static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 352{
3e332d3a
RL		 353 struct drm_device *dev = connector->dev;
354 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 355 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 356 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
357 struct drm_display_mode *mode;
42e67c3b
RL		 358 unsigned long max_size = 0;
359
360 if (adev->dm.dc->fbc_compressor == NULL)
361 return;
a32e24b4 362
3e332d3a 363 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 364 return;
365
3e332d3a
RL		 366 if (compressor->bo_ptr)
367 return;
42e67c3b 368
42e67c3b 369
3e332d3a
RL		 370 list_for_each_entry(mode, &connector->modes, head) {
371 if (max_size < mode->htotal * mode->vtotal)
372 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 373 }
374
375 if (max_size) {
376 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 377 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 378 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 379
380 if (r)
42e67c3b
RL		 381 DRM_ERROR("DM: Failed to initialize FBC\n");
382 else {
383 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
384 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
385 }
386
a32e24b4
RL		 387 }
388
389}
390#endif
391
392
4562236b
HW		 393/* Init display KMS
394 *
395 * Returns 0 on success
396 */
7578ecda 397static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 398{
399 struct dc_init_data init_data;
400 adev->dm.ddev = adev->ddev;
401 adev->dm.adev = adev;
402
4562236b
HW		 403 /* Zero all the fields */
404 memset(&init_data, 0, sizeof(init_data));
405
4562236b
HW		 406 if(amdgpu_dm_irq_init(adev)) {
407 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
408 goto error;
409 }
410
411 init_data.asic_id.chip_family = adev->family;
412
413 init_data.asic_id.pci_revision_id = adev->rev_id;
414 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
415
770d13b1 416 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 417 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
418 init_data.asic_id.atombios_base_address =
419 adev->mode_info.atom_context->bios;
420
421 init_data.driver = adev;
422
423 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
424
425 if (!adev->dm.cgs_device) {
426 DRM_ERROR("amdgpu: failed to create cgs device.\n");
427 goto error;
428 }
429
430 init_data.cgs_device = adev->dm.cgs_device;
431
432 adev->dm.dal = NULL;
433
434 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
435
f1ad2f5e
HW		 436 if (amdgpu_dc_log)
437 init_data.log_mask = DC_DEFAULT_LOG_MASK;
438 else
439 init_data.log_mask = DC_MIN_LOG_MASK;
01a526f3 440
6e227308
HW		 441 /*
442 * TODO debug why this doesn't work on Raven
443 */
444 if (adev->flags & AMD_IS_APU &&
445 adev->asic_type >= CHIP_CARRIZO &&
446 adev->asic_type < CHIP_RAVEN)
447 init_data.flags.gpu_vm_support = true;
448
4562236b
HW		 449 /* Display Core create. */
450 adev->dm.dc = dc_create(&init_data);
451
423788c7 452 if (adev->dm.dc) {
76121231 453 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 454 } else {
76121231 455 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 456 goto error;
457 }
4562236b
HW		 458
459 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
460
461 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
462 if (!adev->dm.freesync_module) {
463 DRM_ERROR(
464 "amdgpu: failed to initialize freesync_module.\n");
465 } else
f1ad2f5e 466 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 467 adev->dm.freesync_module);
468
e277adc5
LSL		 469 amdgpu_dm_init_color_mod();
470
4562236b
HW		 471 if (amdgpu_dm_initialize_drm_device(adev)) {
472 DRM_ERROR(
473 "amdgpu: failed to initialize sw for display support.\n");
474 goto error;
475 }
476
477 /* Update the actual used number of crtc */
478 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
479
480 /* TODO: Add_display_info? */
481
482 /* TODO use dynamic cursor width */
ce75805e
AG		 483 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
484 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 485
486 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
487 DRM_ERROR(
488 "amdgpu: failed to initialize sw for display support.\n");
489 goto error;
490 }
491
f1ad2f5e 492 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 493
494 return 0;
495error:
496 amdgpu_dm_fini(adev);
497
498 return -1;
499}
500
7578ecda 501static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 502{
503 amdgpu_dm_destroy_drm_device(&adev->dm);
504 /*
505 * TODO: pageflip, vlank interrupt
506 *
507 * amdgpu_dm_irq_fini(adev);
508 */
509
510 if (adev->dm.cgs_device) {
511 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
512 adev->dm.cgs_device = NULL;
513 }
514 if (adev->dm.freesync_module) {
515 mod_freesync_destroy(adev->dm.freesync_module);
516 adev->dm.freesync_module = NULL;
517 }
518 /* DC Destroy TODO: Replace destroy DAL */
21de3396 519 if (adev->dm.dc)
4562236b 520 dc_destroy(&adev->dm.dc);
4562236b
HW		 521 return;
522}
523
4562236b
HW		 524static int dm_sw_init(void *handle)
525{
526 return 0;
527}
528
529static int dm_sw_fini(void *handle)
530{
531 return 0;
532}
533
7abcf6b5 534static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 535{
c84dec2f 536 struct amdgpu_dm_connector *aconnector;
4562236b 537 struct drm_connector *connector;
7abcf6b5 538 int ret = 0;
4562236b
HW		 539
540 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
541
542 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 543 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 544 if (aconnector->dc_link->type == dc_connection_mst_branch &&
545 aconnector->mst_mgr.aux) {
f1ad2f5e 546 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 547 aconnector, aconnector->base.base.id);
548
549 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
550 if (ret < 0) {
551 DRM_ERROR("DM_MST: Failed to start MST\n");
552 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
553 return ret;
4562236b 554 }
7abcf6b5 555 }
4562236b
HW		 556 }
557
558 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 559 return ret;
560}
561
562static int dm_late_init(void *handle)
563{
42e67c3b 564 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 565
42e67c3b 566 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 567}
568
569static void s3_handle_mst(struct drm_device *dev, bool suspend)
570{
c84dec2f 571 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 572 struct drm_connector *connector;
573
574 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
575
576 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 577 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 578 if (aconnector->dc_link->type == dc_connection_mst_branch &&
579 !aconnector->mst_port) {
580
581 if (suspend)
582 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
583 else
584 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
585 }
586 }
587
588 drm_modeset_unlock(&dev->mode_config.connection_mutex);
589}
590
591static int dm_hw_init(void *handle)
592{
593 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
594 /* Create DAL display manager */
595 amdgpu_dm_init(adev);
4562236b
HW		 596 amdgpu_dm_hpd_init(adev);
597
4562236b
HW		 598 return 0;
599}
600
601static int dm_hw_fini(void *handle)
602{
603 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
604
605 amdgpu_dm_hpd_fini(adev);
606
607 amdgpu_dm_irq_fini(adev);
21de3396 608 amdgpu_dm_fini(adev);
4562236b
HW		 609 return 0;
610}
611
612static int dm_suspend(void *handle)
613{
614 struct amdgpu_device *adev = handle;
615 struct amdgpu_display_manager *dm = &adev->dm;
616 int ret = 0;
4562236b
HW		 617
618 s3_handle_mst(adev->ddev, true);
619
4562236b
HW		 620 amdgpu_dm_irq_suspend(adev);
621
0a214e2f 622 WARN_ON(adev->dm.cached_state);
a3621485
AG		 623 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
624
32f5062d 625 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 626
627 return ret;
628}
629
1daf8c63
AD		 630static struct amdgpu_dm_connector *
631amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
632 struct drm_crtc *crtc)
4562236b
HW		 633{
634 uint32_t i;
c2cea706 635 struct drm_connector_state *new_con_state;
4562236b
HW		 636 struct drm_connector *connector;
637 struct drm_crtc *crtc_from_state;
638
c2cea706
LSL		 639 for_each_new_connector_in_state(state, connector, new_con_state, i) {
640 crtc_from_state = new_con_state->crtc;
4562236b
HW		 641
642 if (crtc_from_state == crtc)
c84dec2f 643 return to_amdgpu_dm_connector(connector);
4562236b
HW		 644 }
645
646 return NULL;
647}
648
4562236b
HW		 649static int dm_resume(void *handle)
650{
651 struct amdgpu_device *adev = handle;
652 struct amdgpu_display_manager *dm = &adev->dm;
15b9bc9a 653 int ret = 0;
4562236b
HW		 654
655 /* power on hardware */
1fb0c9cc 656 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
4562236b 657
15b9bc9a
ML		 658 ret = amdgpu_dm_display_resume(adev);
659 return ret;
4562236b
HW		 660}
661
1ecfc3da 662int amdgpu_dm_display_resume(struct amdgpu_device *adev)
4562236b
HW		 663{
664 struct drm_device *ddev = adev->ddev;
665 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 666 struct amdgpu_dm_connector *aconnector;
4562236b 667 struct drm_connector *connector;
4562236b 668 struct drm_crtc *crtc;
c2cea706 669 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 670 struct dm_crtc_state *dm_new_crtc_state;
671 struct drm_plane *plane;
672 struct drm_plane_state *new_plane_state;
673 struct dm_plane_state *dm_new_plane_state;
674
a3621485
AG		 675 int ret = 0;
676 int i;
4562236b
HW		 677
678 /* program HPD filter */
679 dc_resume(dm->dc);
680
681 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
682 s3_handle_mst(ddev, false);
683
684 /*
685 * early enable HPD Rx IRQ, should be done before set mode as short
686 * pulse interrupts are used for MST
687 */
688 amdgpu_dm_irq_resume_early(adev);
689
4562236b
HW		 690 /* Do detection*/
691 list_for_each_entry(connector,
692 &ddev->mode_config.connector_list, head) {
c84dec2f 693 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 694
695 /*
696 * this is the case when traversing through already created
697 * MST connectors, should be skipped
698 */
699 if (aconnector->mst_port)
700 continue;
701
03ea364c 702 mutex_lock(&aconnector->hpd_lock);
8f38b66c 703 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 704
705 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
706 aconnector->fake_enable = false;
707
4562236b
HW		 708 aconnector->dc_sink = NULL;
709 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 710 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 711 }
712
a3621485 713 /* Force mode set in atomic comit */
c2cea706
LSL		 714 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
715 new_crtc_state->active_changed = true;
4f346e65 716
fcb4019e
LSL		 717 /*
718 * atomic_check is expected to create the dc states. We need to release
719 * them here, since they were duplicated as part of the suspend
720 * procedure.
721 */
722 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
723 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
724 if (dm_new_crtc_state->stream) {
725 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
726 dc_stream_release(dm_new_crtc_state->stream);
727 dm_new_crtc_state->stream = NULL;
728 }
729 }
730
731 for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
732 dm_new_plane_state = to_dm_plane_state(new_plane_state);
733 if (dm_new_plane_state->dc_state) {
734 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
735 dc_plane_state_release(dm_new_plane_state->dc_state);
736 dm_new_plane_state->dc_state = NULL;
737 }
738 }
739
a3621485 740 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 741
0a214e2f
AG		 742 adev->dm.cached_state = NULL;
743
9faa4237 744 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 745
746 return ret;
747}
748
749static const struct amd_ip_funcs amdgpu_dm_funcs = {
750 .name = "dm",
751 .early_init = dm_early_init,
7abcf6b5 752 .late_init = dm_late_init,
4562236b
HW		 753 .sw_init = dm_sw_init,
754 .sw_fini = dm_sw_fini,
755 .hw_init = dm_hw_init,
756 .hw_fini = dm_hw_fini,
757 .suspend = dm_suspend,
758 .resume = dm_resume,
759 .is_idle = dm_is_idle,
760 .wait_for_idle = dm_wait_for_idle,
761 .check_soft_reset = dm_check_soft_reset,
762 .soft_reset = dm_soft_reset,
763 .set_clockgating_state = dm_set_clockgating_state,
764 .set_powergating_state = dm_set_powergating_state,
765};
766
767const struct amdgpu_ip_block_version dm_ip_block =
768{
769 .type = AMD_IP_BLOCK_TYPE_DCE,
770 .major = 1,
771 .minor = 0,
772 .rev = 0,
773 .funcs = &amdgpu_dm_funcs,
774};
775
ca3268c4 776
7578ecda 777static struct drm_atomic_state *
ca3268c4
HW		 778dm_atomic_state_alloc(struct drm_device *dev)
779{
780 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
781
1dc90497 782 if (!state)
ca3268c4 783 return NULL;
1dc90497
AG		 784
785 if (drm_atomic_state_init(dev, &state->base) < 0)
786 goto fail;
787
ca3268c4 788 return &state->base;
1dc90497
AG		 789
790fail:
791 kfree(state);
792 return NULL;
ca3268c4
HW		 793}
794
0a323b84
AG		 795static void
796dm_atomic_state_clear(struct drm_atomic_state *state)
797{
798 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
799
800 if (dm_state->context) {
608ac7bb 801 dc_release_state(dm_state->context);
0a323b84
AG		 802 dm_state->context = NULL;
803 }
804
805 drm_atomic_state_default_clear(state);
806}
807
808static void
809dm_atomic_state_alloc_free(struct drm_atomic_state *state)
810{
811 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
812 drm_atomic_state_default_release(state);
813 kfree(dm_state);
814}
815
b3663f70 816static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 817 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 818 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 819 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 820 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 821 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 822 .atomic_state_clear = dm_atomic_state_clear,
823 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 824};
825
826static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
827 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 828};
829
7578ecda 830static void
3ee6b26b 831amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 832{
833 struct drm_connector *connector = &aconnector->base;
834 struct drm_device *dev = connector->dev;
b73a22d3 835 struct dc_sink *sink;
4562236b
HW		 836
837 /* MST handled by drm_mst framework */
838 if (aconnector->mst_mgr.mst_state == true)
839 return;
840
841
842 sink = aconnector->dc_link->local_sink;
843
844 /* Edid mgmt connector gets first update only in mode_valid hook and then
845 * the connector sink is set to either fake or physical sink depends on link status.
846 * don't do it here if u are during boot
847 */
848 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
849 && aconnector->dc_em_sink) {
850
ab2541b6 851 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 852 * because on resume connecotr->sink is set ti NULL
853 */
854 mutex_lock(&dev->mode_config.mutex);
855
856 if (sink) {
922aa1e1 857 if (aconnector->dc_sink) {
4562236b
HW		 858 amdgpu_dm_remove_sink_from_freesync_module(
859 connector);
922aa1e1
AG		 860 /* retain and release bellow are used for
861 * bump up refcount for sink because the link don't point
862 * to it anymore after disconnect so on next crtc to connector
863 * reshuffle by UMD we will get into unwanted dc_sink release
864 */
865 if (aconnector->dc_sink != aconnector->dc_em_sink)
866 dc_sink_release(aconnector->dc_sink);
867 }
4562236b
HW		 868 aconnector->dc_sink = sink;
869 amdgpu_dm_add_sink_to_freesync_module(
870 connector, aconnector->edid);
871 } else {
872 amdgpu_dm_remove_sink_from_freesync_module(connector);
873 if (!aconnector->dc_sink)
874 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 875 else if (aconnector->dc_sink != aconnector->dc_em_sink)
876 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 877 }
878
879 mutex_unlock(&dev->mode_config.mutex);
880 return;
881 }
882
883 /*
884 * TODO: temporary guard to look for proper fix
885 * if this sink is MST sink, we should not do anything
886 */
887 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
888 return;
889
890 if (aconnector->dc_sink == sink) {
891 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
892 * Do nothing!! */
f1ad2f5e 893 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 894 aconnector->connector_id);
895 return;
896 }
897
f1ad2f5e 898 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 899 aconnector->connector_id, aconnector->dc_sink, sink);
900
901 mutex_lock(&dev->mode_config.mutex);
902
903 /* 1. Update status of the drm connector
904 * 2. Send an event and let userspace tell us what to do */
905 if (sink) {
906 /* TODO: check if we still need the S3 mode update workaround.
907 * If yes, put it here. */
908 if (aconnector->dc_sink)
909 amdgpu_dm_remove_sink_from_freesync_module(
910 connector);
911
912 aconnector->dc_sink = sink;
900b3cb1 913 if (sink->dc_edid.length == 0) {
4562236b 914 aconnector->edid = NULL;
900b3cb1 915 } else {
4562236b
HW		 916 aconnector->edid =
917 (struct edid *) sink->dc_edid.raw_edid;
918
919
920 drm_mode_connector_update_edid_property(connector,
921 aconnector->edid);
922 }
923 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
924
925 } else {
926 amdgpu_dm_remove_sink_from_freesync_module(connector);
927 drm_mode_connector_update_edid_property(connector, NULL);
928 aconnector->num_modes = 0;
929 aconnector->dc_sink = NULL;
930 }
931
932 mutex_unlock(&dev->mode_config.mutex);
933}
934
935static void handle_hpd_irq(void *param)
936{
c84dec2f 937 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 938 struct drm_connector *connector = &aconnector->base;
939 struct drm_device *dev = connector->dev;
940
941 /* In case of failure or MST no need to update connector status or notify the OS
942 * since (for MST case) MST does this in it's own context.
943 */
944 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 945
946 if (aconnector->fake_enable)
947 aconnector->fake_enable = false;
948
8f38b66c 949 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 950 amdgpu_dm_update_connector_after_detect(aconnector);
951
952
953 drm_modeset_lock_all(dev);
954 dm_restore_drm_connector_state(dev, connector);
955 drm_modeset_unlock_all(dev);
956
957 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
958 drm_kms_helper_hotplug_event(dev);
959 }
960 mutex_unlock(&aconnector->hpd_lock);
961
962}
963
c84dec2f 964static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 965{
966 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
967 uint8_t dret;
968 bool new_irq_handled = false;
969 int dpcd_addr;
970 int dpcd_bytes_to_read;
971
972 const int max_process_count = 30;
973 int process_count = 0;
974
975 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
976
977 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
978 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
979 /* DPCD 0x200 - 0x201 for downstream IRQ */
980 dpcd_addr = DP_SINK_COUNT;
981 } else {
982 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
983 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
984 dpcd_addr = DP_SINK_COUNT_ESI;
985 }
986
987 dret = drm_dp_dpcd_read(
988 &aconnector->dm_dp_aux.aux,
989 dpcd_addr,
990 esi,
991 dpcd_bytes_to_read);
992
993 while (dret == dpcd_bytes_to_read &&
994 process_count < max_process_count) {
995 uint8_t retry;
996 dret = 0;
997
998 process_count++;
999
f1ad2f5e 1000 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1001 /* handle HPD short pulse irq */
1002 if (aconnector->mst_mgr.mst_state)
1003 drm_dp_mst_hpd_irq(
1004 &aconnector->mst_mgr,
1005 esi,
1006 &new_irq_handled);
4562236b
HW		 1007
1008 if (new_irq_handled) {
1009 /* ACK at DPCD to notify down stream */
1010 const int ack_dpcd_bytes_to_write =
1011 dpcd_bytes_to_read - 1;
1012
1013 for (retry = 0; retry < 3; retry++) {
1014 uint8_t wret;
1015
1016 wret = drm_dp_dpcd_write(
1017 &aconnector->dm_dp_aux.aux,
1018 dpcd_addr + 1,
1019 &esi[1],
1020 ack_dpcd_bytes_to_write);
1021 if (wret == ack_dpcd_bytes_to_write)
1022 break;
1023 }
1024
1025 /* check if there is new irq to be handle */
1026 dret = drm_dp_dpcd_read(
1027 &aconnector->dm_dp_aux.aux,
1028 dpcd_addr,
1029 esi,
1030 dpcd_bytes_to_read);
1031
1032 new_irq_handled = false;
d4a6e8a9 1033 } else {
4562236b 1034 break;
d4a6e8a9 1035 }
4562236b
HW		 1036 }
1037
1038 if (process_count == max_process_count)
f1ad2f5e 1039 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1040}
1041
1042static void handle_hpd_rx_irq(void *param)
1043{
c84dec2f 1044 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1045 struct drm_connector *connector = &aconnector->base;
1046 struct drm_device *dev = connector->dev;
53cbf65c 1047 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 1048 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1049
1050 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1051 * conflict, after implement i2c helper, this mutex should be
1052 * retired.
1053 */
53cbf65c 1054 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1055 mutex_lock(&aconnector->hpd_lock);
1056
53cbf65c 1057 if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
4562236b
HW		 1058 !is_mst_root_connector) {
1059 /* Downstream Port status changed. */
53cbf65c 1060 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1061
1062 if (aconnector->fake_enable)
1063 aconnector->fake_enable = false;
1064
4562236b
HW		 1065 amdgpu_dm_update_connector_after_detect(aconnector);
1066
1067
1068 drm_modeset_lock_all(dev);
1069 dm_restore_drm_connector_state(dev, connector);
1070 drm_modeset_unlock_all(dev);
1071
1072 drm_kms_helper_hotplug_event(dev);
1073 }
1074 }
1075 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1076 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1077 dm_handle_hpd_rx_irq(aconnector);
1078
53cbf65c 1079 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1080 mutex_unlock(&aconnector->hpd_lock);
1081}
1082
1083static void register_hpd_handlers(struct amdgpu_device *adev)
1084{
1085 struct drm_device *dev = adev->ddev;
1086 struct drm_connector *connector;
c84dec2f 1087 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1088 const struct dc_link *dc_link;
1089 struct dc_interrupt_params int_params = {0};
1090
1091 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1092 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1093
1094 list_for_each_entry(connector,
1095 &dev->mode_config.connector_list, head) {
1096
c84dec2f 1097 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1098 dc_link = aconnector->dc_link;
1099
1100 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1101 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1102 int_params.irq_source = dc_link->irq_source_hpd;
1103
1104 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1105 handle_hpd_irq,
1106 (void *) aconnector);
1107 }
1108
1109 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1110
1111 /* Also register for DP short pulse (hpd_rx). */
1112 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1113 int_params.irq_source = dc_link->irq_source_hpd_rx;
1114
1115 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1116 handle_hpd_rx_irq,
1117 (void *) aconnector);
1118 }
1119 }
1120}
1121
1122/* Register IRQ sources and initialize IRQ callbacks */
1123static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1124{
1125 struct dc *dc = adev->dm.dc;
1126 struct common_irq_params *c_irq_params;
1127 struct dc_interrupt_params int_params = {0};
1128 int r;
1129 int i;
2c8ad2d5
AD		 1130 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1131
ff5ef992
AD		 1132 if (adev->asic_type == CHIP_VEGA10 ||
1133 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1134 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1135
1136 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1137 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1138
1139 /* Actions of amdgpu_irq_add_id():
1140 * 1. Register a set() function with base driver.
1141 * Base driver will call set() function to enable/disable an
1142 * interrupt in DC hardware.
1143 * 2. Register amdgpu_dm_irq_handler().
1144 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1145 * coming from DC hardware.
1146 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1147 * for acknowledging and handling. */
1148
b57de80a 1149 /* Use VBLANK interrupt */
e9029155 1150 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1151 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1152 if (r) {
1153 DRM_ERROR("Failed to add crtc irq id!\n");
1154 return r;
1155 }
1156
1157 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1158 int_params.irq_source =
3d761e79 1159 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1160
b57de80a 1161 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1162
1163 c_irq_params->adev = adev;
1164 c_irq_params->irq_src = int_params.irq_source;
1165
1166 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1167 dm_crtc_high_irq, c_irq_params);
1168 }
1169
3d761e79 1170 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1171 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1172 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1173 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1174 if (r) {
1175 DRM_ERROR("Failed to add page flip irq id!\n");
1176 return r;
1177 }
1178
1179 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1180 int_params.irq_source =
1181 dc_interrupt_to_irq_source(dc, i, 0);
1182
1183 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1184
1185 c_irq_params->adev = adev;
1186 c_irq_params->irq_src = int_params.irq_source;
1187
1188 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1189 dm_pflip_high_irq, c_irq_params);
1190
1191 }
1192
1193 /* HPD */
2c8ad2d5
AD		 1194 r = amdgpu_irq_add_id(adev, client_id,
1195 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1196 if (r) {
1197 DRM_ERROR("Failed to add hpd irq id!\n");
1198 return r;
1199 }
1200
1201 register_hpd_handlers(adev);
1202
1203 return 0;
1204}
1205
ff5ef992
AD		 1206#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1207/* Register IRQ sources and initialize IRQ callbacks */
1208static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1209{
1210 struct dc *dc = adev->dm.dc;
1211 struct common_irq_params *c_irq_params;
1212 struct dc_interrupt_params int_params = {0};
1213 int r;
1214 int i;
1215
1216 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1217 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1218
1219 /* Actions of amdgpu_irq_add_id():
1220 * 1. Register a set() function with base driver.
1221 * Base driver will call set() function to enable/disable an
1222 * interrupt in DC hardware.
1223 * 2. Register amdgpu_dm_irq_handler().
1224 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1225 * coming from DC hardware.
1226 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1227 * for acknowledging and handling.
1228 * */
1229
1230 /* Use VSTARTUP interrupt */
1231 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1232 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1233 i++) {
1234 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1235
1236 if (r) {
1237 DRM_ERROR("Failed to add crtc irq id!\n");
1238 return r;
1239 }
1240
1241 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1242 int_params.irq_source =
1243 dc_interrupt_to_irq_source(dc, i, 0);
1244
1245 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1246
1247 c_irq_params->adev = adev;
1248 c_irq_params->irq_src = int_params.irq_source;
1249
1250 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1251 dm_crtc_high_irq, c_irq_params);
1252 }
1253
1254 /* Use GRPH_PFLIP interrupt */
1255 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1256 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1257 i++) {
1258 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1259 if (r) {
1260 DRM_ERROR("Failed to add page flip irq id!\n");
1261 return r;
1262 }
1263
1264 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1265 int_params.irq_source =
1266 dc_interrupt_to_irq_source(dc, i, 0);
1267
1268 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1269
1270 c_irq_params->adev = adev;
1271 c_irq_params->irq_src = int_params.irq_source;
1272
1273 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1274 dm_pflip_high_irq, c_irq_params);
1275
1276 }
1277
1278 /* HPD */
1279 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1280 &adev->hpd_irq);
1281 if (r) {
1282 DRM_ERROR("Failed to add hpd irq id!\n");
1283 return r;
1284 }
1285
1286 register_hpd_handlers(adev);
1287
1288 return 0;
1289}
1290#endif
1291
4562236b
HW		 1292static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1293{
1294 int r;
1295
1296 adev->mode_info.mode_config_initialized = true;
1297
4562236b 1298 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1299 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1300
1301 adev->ddev->mode_config.max_width = 16384;
1302 adev->ddev->mode_config.max_height = 16384;
1303
1304 adev->ddev->mode_config.preferred_depth = 24;
1305 adev->ddev->mode_config.prefer_shadow = 1;
1306 /* indicate support of immediate flip */
1307 adev->ddev->mode_config.async_page_flip = true;
1308
770d13b1 1309 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1310
3dc9b1ce 1311 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1312 if (r)
1313 return r;
1314
1315 return 0;
1316}
1317
1318#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1319 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1320
1321static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1322{
1323 struct amdgpu_display_manager *dm = bl_get_data(bd);
1324
1325 if (dc_link_set_backlight_level(dm->backlight_link,
1326 bd->props.brightness, 0, 0))
1327 return 0;
1328 else
1329 return 1;
1330}
1331
1332static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1333{
1334 return bd->props.brightness;
1335}
1336
1337static const struct backlight_ops amdgpu_dm_backlight_ops = {
1338 .get_brightness = amdgpu_dm_backlight_get_brightness,
1339 .update_status = amdgpu_dm_backlight_update_status,
1340};
1341
7578ecda
AD		 1342static void
1343amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1344{
1345 char bl_name[16];
1346 struct backlight_properties props = { 0 };
1347
1348 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1349 props.type = BACKLIGHT_RAW;
1350
1351 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1352 dm->adev->ddev->primary->index);
1353
1354 dm->backlight_dev = backlight_device_register(bl_name,
1355 dm->adev->ddev->dev,
1356 dm,
1357 &amdgpu_dm_backlight_ops,
1358 &props);
1359
74baea42 1360 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1361 DRM_ERROR("DM: Backlight registration failed!\n");
1362 else
f1ad2f5e 1363 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1364}
1365
1366#endif
1367
1368/* In this architecture, the association
1369 * connector -> encoder -> crtc
1370 * id not really requried. The crtc and connector will hold the
1371 * display_index as an abstraction to use with DAL component
1372 *
1373 * Returns 0 on success
1374 */
7578ecda 1375static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1376{
1377 struct amdgpu_display_manager *dm = &adev->dm;
1378 uint32_t i;
c84dec2f 1379 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1380 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1381 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1382 uint32_t link_cnt;
92f3ac40 1383 unsigned long possible_crtcs;
4562236b
HW		 1384
1385 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1386 if (amdgpu_dm_mode_config_init(dm->adev)) {
1387 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1388 return -1;
4562236b
HW		 1389 }
1390
3be5262e 1391 for (i = 0; i < dm->dc->caps.max_planes; i++) {
efa6a8b7
HW		 1392 struct amdgpu_plane *plane;
1393
1394 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1395 mode_info->planes[i] = plane;
1396
1397 if (!plane) {
3be5262e 1398 DRM_ERROR("KMS: Failed to allocate plane\n");
cd8a2ae8 1399 goto fail;
d4e13b0d 1400 }
efa6a8b7 1401 plane->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1402
1403 /*
1404 * HACK: IGT tests expect that each plane can only have one
1405 * one possible CRTC. For now, set one CRTC for each
1406 * plane that is not an underlay, but still allow multiple
1407 * CRTCs for underlay planes.
1408 */
1409 possible_crtcs = 1 << i;
1410 if (i >= dm->dc->caps.max_streams)
1411 possible_crtcs = 0xff;
1412
1413 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d 1414 DRM_ERROR("KMS: Failed to initialize plane\n");
cd8a2ae8 1415 goto fail;
d4e13b0d
AD		 1416 }
1417 }
4562236b 1418
d4e13b0d
AD		 1419 for (i = 0; i < dm->dc->caps.max_streams; i++)
1420 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1421 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1422 goto fail;
4562236b 1423 }
4562236b 1424
ab2541b6 1425 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1426
1427 /* loops over all connectors on the board */
1428 for (i = 0; i < link_cnt; i++) {
1429
1430 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1431 DRM_ERROR(
1432 "KMS: Cannot support more than %d display indexes\n",
1433 AMDGPU_DM_MAX_DISPLAY_INDEX);
1434 continue;
1435 }
1436
1437 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1438 if (!aconnector)
cd8a2ae8 1439 goto fail;
4562236b
HW		 1440
1441 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1442 if (!aencoder)
cd8a2ae8 1443 goto fail;
4562236b
HW		 1444
1445 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1446 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1447 goto fail;
4562236b
HW		 1448 }
1449
1450 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1451 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1452 goto fail;
4562236b
HW		 1453 }
1454
8f38b66c
HW		 1455 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1456 DETECT_REASON_BOOT))
4562236b
HW		 1457 amdgpu_dm_update_connector_after_detect(aconnector);
1458 }
1459
1460 /* Software is initialized. Now we can register interrupt handlers. */
1461 switch (adev->asic_type) {
1462 case CHIP_BONAIRE:
1463 case CHIP_HAWAII:
cd4b356f
AD		 1464 case CHIP_KAVERI:
1465 case CHIP_KABINI:
1466 case CHIP_MULLINS:
4562236b
HW		 1467 case CHIP_TONGA:
1468 case CHIP_FIJI:
1469 case CHIP_CARRIZO:
1470 case CHIP_STONEY:
1471 case CHIP_POLARIS11:
1472 case CHIP_POLARIS10:
b264d345 1473 case CHIP_POLARIS12:
2c8ad2d5 1474 case CHIP_VEGA10:
4562236b
HW		 1475 if (dce110_register_irq_handlers(dm->adev)) {
1476 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1477 goto fail;
4562236b
HW		 1478 }
1479 break;
ff5ef992
AD		 1480#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1481 case CHIP_RAVEN:
1482 if (dcn10_register_irq_handlers(dm->adev)) {
1483 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1484 goto fail;
ff5ef992 1485 }
79c24086
BL		 1486 /*
1487 * Temporary disable until pplib/smu interaction is implemented
1488 */
1489 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1490 break;
1491#endif
4562236b
HW		 1492 default:
1493 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 1494 goto fail;
4562236b
HW		 1495 }
1496
4562236b 1497 return 0;
cd8a2ae8 1498fail:
4562236b 1499 kfree(aencoder);
4562236b 1500 kfree(aconnector);
3be5262e 1501 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1502 kfree(mode_info->planes[i]);
4562236b
HW		 1503 return -1;
1504}
1505
7578ecda 1506static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1507{
1508 drm_mode_config_cleanup(dm->ddev);
1509 return;
1510}
1511
1512/******************************************************************************
1513 * amdgpu_display_funcs functions
1514 *****************************************************************************/
1515
1516/**
1517 * dm_bandwidth_update - program display watermarks
1518 *
1519 * @adev: amdgpu_device pointer
1520 *
1521 * Calculate and program the display watermarks and line buffer allocation.
1522 */
1523static void dm_bandwidth_update(struct amdgpu_device *adev)
1524{
49c07a99 1525 /* TODO: implement later */
4562236b
HW		 1526}
1527
1528static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1529 u8 level)
1530{
1531 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1532}
1533
1534static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1535{
1536 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1537 return 0;
1538}
1539
4562236b
HW		 1540static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1541 struct drm_file *filp)
1542{
1543 struct mod_freesync_params freesync_params;
ab2541b6 1544 uint8_t num_streams;
4562236b 1545 uint8_t i;
4562236b
HW		 1546
1547 struct amdgpu_device *adev = dev->dev_private;
1548 int r = 0;
1549
1550 /* Get freesync enable flag from DRM */
1551
ab2541b6 1552 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1553
ab2541b6 1554 for (i = 0; i < num_streams; i++) {
0971c40e 1555 struct dc_stream_state *stream;
ab2541b6 1556 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1557
1558 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1559 &stream, 1, &freesync_params);
4562236b
HW		 1560 }
1561
1562 return r;
1563}
1564
39cc5be2 1565static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1566 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1567 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4562236b
HW		 1568 .backlight_set_level =
1569 dm_set_backlight_level,/* called unconditionally */
1570 .backlight_get_level =
1571 dm_get_backlight_level,/* called unconditionally */
1572 .hpd_sense = NULL,/* called unconditionally */
1573 .hpd_set_polarity = NULL, /* called unconditionally */
1574 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1575 .page_flip_get_scanoutpos =
1576 dm_crtc_get_scanoutpos,/* called unconditionally */
1577 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1578 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1579 .notify_freesync = amdgpu_notify_freesync,
1580
1581};
1582
1583#if defined(CONFIG_DEBUG_KERNEL_DC)
1584
3ee6b26b
AD		 1585static ssize_t s3_debug_store(struct device *device,
1586 struct device_attribute *attr,
1587 const char *buf,
1588 size_t count)
4562236b
HW		 1589{
1590 int ret;
1591 int s3_state;
1592 struct pci_dev *pdev = to_pci_dev(device);
1593 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1594 struct amdgpu_device *adev = drm_dev->dev_private;
1595
1596 ret = kstrtoint(buf, 0, &s3_state);
1597
1598 if (ret == 0) {
1599 if (s3_state) {
1600 dm_resume(adev);
1601 amdgpu_dm_display_resume(adev);
1602 drm_kms_helper_hotplug_event(adev->ddev);
1603 } else
1604 dm_suspend(adev);
1605 }
1606
1607 return ret == 0 ? count : 0;
1608}
1609
1610DEVICE_ATTR_WO(s3_debug);
1611
1612#endif
1613
1614static int dm_early_init(void *handle)
1615{
1616 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1617
4562236b
HW		 1618 switch (adev->asic_type) {
1619 case CHIP_BONAIRE:
1620 case CHIP_HAWAII:
1621 adev->mode_info.num_crtc = 6;
1622 adev->mode_info.num_hpd = 6;
1623 adev->mode_info.num_dig = 6;
3be5262e 1624 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1625 break;
cd4b356f
AD		 1626 case CHIP_KAVERI:
1627 adev->mode_info.num_crtc = 4;
1628 adev->mode_info.num_hpd = 6;
1629 adev->mode_info.num_dig = 7;
1630 adev->mode_info.plane_type = dm_plane_type_default;
1631 break;
1632 case CHIP_KABINI:
1633 case CHIP_MULLINS:
1634 adev->mode_info.num_crtc = 2;
1635 adev->mode_info.num_hpd = 6;
1636 adev->mode_info.num_dig = 6;
1637 adev->mode_info.plane_type = dm_plane_type_default;
1638 break;
4562236b
HW		 1639 case CHIP_FIJI:
1640 case CHIP_TONGA:
1641 adev->mode_info.num_crtc = 6;
1642 adev->mode_info.num_hpd = 6;
1643 adev->mode_info.num_dig = 7;
3be5262e 1644 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1645 break;
1646 case CHIP_CARRIZO:
1647 adev->mode_info.num_crtc = 3;
1648 adev->mode_info.num_hpd = 6;
1649 adev->mode_info.num_dig = 9;
3be5262e 1650 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1651 break;
1652 case CHIP_STONEY:
1653 adev->mode_info.num_crtc = 2;
1654 adev->mode_info.num_hpd = 6;
1655 adev->mode_info.num_dig = 9;
3be5262e 1656 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1657 break;
1658 case CHIP_POLARIS11:
b264d345 1659 case CHIP_POLARIS12:
4562236b
HW		 1660 adev->mode_info.num_crtc = 5;
1661 adev->mode_info.num_hpd = 5;
1662 adev->mode_info.num_dig = 5;
3be5262e 1663 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1664 break;
1665 case CHIP_POLARIS10:
1666 adev->mode_info.num_crtc = 6;
1667 adev->mode_info.num_hpd = 6;
1668 adev->mode_info.num_dig = 6;
3be5262e 1669 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1670 break;
2c8ad2d5
AD		 1671 case CHIP_VEGA10:
1672 adev->mode_info.num_crtc = 6;
1673 adev->mode_info.num_hpd = 6;
1674 adev->mode_info.num_dig = 6;
3be5262e 1675 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1676 break;
ff5ef992
AD		 1677#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1678 case CHIP_RAVEN:
1679 adev->mode_info.num_crtc = 4;
1680 adev->mode_info.num_hpd = 4;
1681 adev->mode_info.num_dig = 4;
3be5262e 1682 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1683 break;
1684#endif
4562236b
HW		 1685 default:
1686 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1687 return -EINVAL;
1688 }
1689
c8dd5715
MD		 1690 amdgpu_dm_set_irq_funcs(adev);
1691
39cc5be2
AD		 1692 if (adev->mode_info.funcs == NULL)
1693 adev->mode_info.funcs = &dm_display_funcs;
1694
4562236b
HW		 1695 /* Note: Do NOT change adev->audio_endpt_rreg and
1696 * adev->audio_endpt_wreg because they are initialised in
1697 * amdgpu_device_init() */
1698#if defined(CONFIG_DEBUG_KERNEL_DC)
1699 device_create_file(
1700 adev->ddev->dev,
1701 &dev_attr_s3_debug);
1702#endif
1703
1704 return 0;
1705}
1706
9b690ef3 1707static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1708 struct dc_stream_state *new_stream,
1709 struct dc_stream_state *old_stream)
9b690ef3 1710{
e7b07cee
HW		 1711 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1712 return false;
1713
1714 if (!crtc_state->enable)
1715 return false;
1716
1717 return crtc_state->active;
1718}
1719
1720static bool modereset_required(struct drm_crtc_state *crtc_state)
1721{
1722 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1723 return false;
1724
1725 return !crtc_state->enable || !crtc_state->active;
1726}
1727
7578ecda 1728static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1729{
1730 drm_encoder_cleanup(encoder);
1731 kfree(encoder);
1732}
1733
1734static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1735 .destroy = amdgpu_dm_encoder_destroy,
1736};
1737
3ee6b26b
AD		 1738static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1739 struct dc_plane_state *plane_state)
e7b07cee 1740{
3be5262e
HW		 1741 plane_state->src_rect.x = state->src_x >> 16;
1742 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1743 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1744 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1745
3be5262e 1746 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1747 return false;
1748
3be5262e
HW		 1749 plane_state->src_rect.height = state->src_h >> 16;
1750 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1751 return false;
1752
3be5262e
HW		 1753 plane_state->dst_rect.x = state->crtc_x;
1754 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1755
1756 if (state->crtc_w == 0)
1757 return false;
1758
3be5262e 1759 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1760
1761 if (state->crtc_h == 0)
1762 return false;
1763
3be5262e 1764 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1765
3be5262e 1766 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1767
1768 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1769 case DRM_MODE_ROTATE_0:
3be5262e 1770 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1771 break;
1772 case DRM_MODE_ROTATE_90:
3be5262e 1773 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1774 break;
1775 case DRM_MODE_ROTATE_180:
3be5262e 1776 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1777 break;
1778 case DRM_MODE_ROTATE_270:
3be5262e 1779 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1780 break;
1781 default:
3be5262e 1782 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1783 break;
1784 }
1785
4562236b
HW		 1786 return true;
1787}
3ee6b26b 1788static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 1789 uint64_t *tiling_flags)
e7b07cee
HW		 1790{
1791 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1792 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1793
e7b07cee 1794 if (unlikely(r)) {
9bbc3031
JZ		 1795 // Don't show error msg. when return -ERESTARTSYS
1796 if (r != -ERESTARTSYS)
1797 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1798 return r;
1799 }
1800
e7b07cee
HW		 1801 if (tiling_flags)
1802 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1803
1804 amdgpu_bo_unreserve(rbo);
1805
1806 return r;
1807}
1808
3ee6b26b
AD		 1809static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1810 struct dc_plane_state *plane_state,
9817d5f5 1811 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 1812{
1813 uint64_t tiling_flags;
e7b07cee
HW		 1814 unsigned int awidth;
1815 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1816 int ret = 0;
1817 struct drm_format_name_buf format_name;
1818
1819 ret = get_fb_info(
1820 amdgpu_fb,
9817d5f5 1821 &tiling_flags);
e7b07cee
HW		 1822
1823 if (ret)
1824 return ret;
1825
1826 switch (fb->format->format) {
1827 case DRM_FORMAT_C8:
3be5262e 1828 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1829 break;
1830 case DRM_FORMAT_RGB565:
3be5262e 1831 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1832 break;
1833 case DRM_FORMAT_XRGB8888:
1834 case DRM_FORMAT_ARGB8888:
3be5262e 1835 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1836 break;
1837 case DRM_FORMAT_XRGB2101010:
1838 case DRM_FORMAT_ARGB2101010:
3be5262e 1839 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1840 break;
1841 case DRM_FORMAT_XBGR2101010:
1842 case DRM_FORMAT_ABGR2101010:
3be5262e 1843 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1844 break;
1845 case DRM_FORMAT_NV21:
3be5262e 1846 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1847 break;
1848 case DRM_FORMAT_NV12:
3be5262e 1849 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1850 break;
1851 default:
1852 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1853 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1854 return -EINVAL;
1855 }
1856
3be5262e
HW		 1857 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1858 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 1859 plane_state->plane_size.grph.surface_size.x = 0;
1860 plane_state->plane_size.grph.surface_size.y = 0;
1861 plane_state->plane_size.grph.surface_size.width = fb->width;
1862 plane_state->plane_size.grph.surface_size.height = fb->height;
1863 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1864 fb->pitches[0] / fb->format->cpp[0];
1865 /* TODO: unhardcode */
3be5262e 1866 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1867
1868 } else {
1869 awidth = ALIGN(fb->width, 64);
3be5262e 1870 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 1871 plane_state->plane_size.video.luma_size.x = 0;
1872 plane_state->plane_size.video.luma_size.y = 0;
1873 plane_state->plane_size.video.luma_size.width = awidth;
1874 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1875 /* TODO: unhardcode */
3be5262e 1876 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1877
3be5262e
HW		 1878 plane_state->plane_size.video.chroma_size.x = 0;
1879 plane_state->plane_size.video.chroma_size.y = 0;
1880 plane_state->plane_size.video.chroma_size.width = awidth;
1881 plane_state->plane_size.video.chroma_size.height = fb->height;
1882 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1883
1884 /* TODO: unhardcode */
3be5262e 1885 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1886 }
1887
3be5262e 1888 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1889
b830ebc9
HW		 1890 /* Fill GFX8 params */
1891 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1892 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1893
1894 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1895 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1896 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1897 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1898 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1899
1900 /* XXX fix me for VI */
3be5262e
HW		 1901 plane_state->tiling_info.gfx8.num_banks = num_banks;
1902 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1903 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1904 plane_state->tiling_info.gfx8.tile_split = tile_split;
1905 plane_state->tiling_info.gfx8.bank_width = bankw;
1906 plane_state->tiling_info.gfx8.bank_height = bankh;
1907 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1908 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1909 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1910 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1911 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1912 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1913 }
1914
3be5262e 1915 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1916 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1917
1918 if (adev->asic_type == CHIP_VEGA10 ||
1919 adev->asic_type == CHIP_RAVEN) {
1920 /* Fill GFX9 params */
3be5262e 1921 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1922 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1923 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1924 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1925 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1926 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1927 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1928 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1929 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1930 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1931 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1932 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1933 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1934 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1935 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1936 }
1937
3be5262e
HW		 1938 plane_state->visible = true;
1939 plane_state->scaling_quality.h_taps_c = 0;
1940 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1941
3be5262e
HW		 1942 /* is this needed? is plane_state zeroed at allocation? */
1943 plane_state->scaling_quality.h_taps = 0;
1944 plane_state->scaling_quality.v_taps = 0;
1945 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1946
1947 return ret;
1948
1949}
1950
3ee6b26b
AD		 1951static int fill_plane_attributes(struct amdgpu_device *adev,
1952 struct dc_plane_state *dc_plane_state,
1953 struct drm_plane_state *plane_state,
9817d5f5 1954 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 1955{
1956 const struct amdgpu_framebuffer *amdgpu_fb =
1957 to_amdgpu_framebuffer(plane_state->fb);
1958 const struct drm_crtc *crtc = plane_state->crtc;
1959 struct dc_transfer_func *input_tf;
1960 int ret = 0;
1961
3be5262e 1962 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1963 return -EINVAL;
1964
1965 ret = fill_plane_attributes_from_fb(
1966 crtc->dev->dev_private,
3be5262e 1967 dc_plane_state,
9817d5f5 1968 amdgpu_fb);
e7b07cee
HW		 1969
1970 if (ret)
1971 return ret;
1972
1973 input_tf = dc_create_transfer_func();
1974
1975 if (input_tf == NULL)
1976 return -ENOMEM;
1977
3be5262e 1978 dc_plane_state->in_transfer_func = input_tf;
e7b07cee 1979
e277adc5
LSL		 1980 /*
1981 * Always set input transfer function, since plane state is refreshed
1982 * every time.
1983 */
1984 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
e7b07cee
HW		 1985
1986 return ret;
1987}
1988
1989/*****************************************************************************/
1990
3ee6b26b
AD		 1991static void update_stream_scaling_settings(const struct drm_display_mode *mode,
1992 const struct dm_connector_state *dm_state,
1993 struct dc_stream_state *stream)
e7b07cee
HW		 1994{
1995 enum amdgpu_rmx_type rmx_type;
1996
1997 struct rect src = { 0 }; /* viewport in composition space*/
1998 struct rect dst = { 0 }; /* stream addressable area */
1999
2000 /* no mode. nothing to be done */
2001 if (!mode)
2002 return;
2003
2004 /* Full screen scaling by default */
2005 src.width = mode->hdisplay;
2006 src.height = mode->vdisplay;
2007 dst.width = stream->timing.h_addressable;
2008 dst.height = stream->timing.v_addressable;
2009
f4791779
HW		 2010 if (dm_state) {
2011 rmx_type = dm_state->scaling;
2012 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2013 if (src.width * dst.height <
2014 src.height * dst.width) {
2015 /* height needs less upscaling/more downscaling */
2016 dst.width = src.width *
2017 dst.height / src.height;
2018 } else {
2019 /* width needs less upscaling/more downscaling */
2020 dst.height = src.height *
2021 dst.width / src.width;
2022 }
2023 } else if (rmx_type == RMX_CENTER) {
2024 dst = src;
e7b07cee 2025 }
e7b07cee 2026
f4791779
HW		 2027 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2028 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2029
f4791779
HW		 2030 if (dm_state->underscan_enable) {
2031 dst.x += dm_state->underscan_hborder / 2;
2032 dst.y += dm_state->underscan_vborder / 2;
2033 dst.width -= dm_state->underscan_hborder;
2034 dst.height -= dm_state->underscan_vborder;
2035 }
e7b07cee
HW		 2036 }
2037
2038 stream->src = src;
2039 stream->dst = dst;
2040
f1ad2f5e 2041 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2042 dst.x, dst.y, dst.width, dst.height);
2043
2044}
2045
3ee6b26b
AD		 2046static enum dc_color_depth
2047convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2048{
2049 uint32_t bpc = connector->display_info.bpc;
2050
2051 /* Limited color depth to 8bit
b830ebc9
HW		 2052 * TODO: Still need to handle deep color
2053 */
e7b07cee
HW		 2054 if (bpc > 8)
2055 bpc = 8;
2056
2057 switch (bpc) {
2058 case 0:
2059 /* Temporary Work around, DRM don't parse color depth for
2060 * EDID revision before 1.4
2061 * TODO: Fix edid parsing
2062 */
2063 return COLOR_DEPTH_888;
2064 case 6:
2065 return COLOR_DEPTH_666;
2066 case 8:
2067 return COLOR_DEPTH_888;
2068 case 10:
2069 return COLOR_DEPTH_101010;
2070 case 12:
2071 return COLOR_DEPTH_121212;
2072 case 14:
2073 return COLOR_DEPTH_141414;
2074 case 16:
2075 return COLOR_DEPTH_161616;
2076 default:
2077 return COLOR_DEPTH_UNDEFINED;
2078 }
2079}
2080
3ee6b26b
AD		 2081static enum dc_aspect_ratio
2082get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2083{
2084 int32_t width = mode_in->crtc_hdisplay * 9;
2085 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2086
e7b07cee
HW		 2087 if ((width - height) < 10 && (width - height) > -10)
2088 return ASPECT_RATIO_16_9;
2089 else
2090 return ASPECT_RATIO_4_3;
2091}
2092
3ee6b26b
AD		 2093static enum dc_color_space
2094get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2095{
2096 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2097
2098 switch (dc_crtc_timing->pixel_encoding) {
2099 case PIXEL_ENCODING_YCBCR422:
2100 case PIXEL_ENCODING_YCBCR444:
2101 case PIXEL_ENCODING_YCBCR420:
2102 {
2103 /*
2104 * 27030khz is the separation point between HDTV and SDTV
2105 * according to HDMI spec, we use YCbCr709 and YCbCr601
2106 * respectively
2107 */
2108 if (dc_crtc_timing->pix_clk_khz > 27030) {
2109 if (dc_crtc_timing->flags.Y_ONLY)
2110 color_space =
2111 COLOR_SPACE_YCBCR709_LIMITED;
2112 else
2113 color_space = COLOR_SPACE_YCBCR709;
2114 } else {
2115 if (dc_crtc_timing->flags.Y_ONLY)
2116 color_space =
2117 COLOR_SPACE_YCBCR601_LIMITED;
2118 else
2119 color_space = COLOR_SPACE_YCBCR601;
2120 }
2121
2122 }
2123 break;
2124 case PIXEL_ENCODING_RGB:
2125 color_space = COLOR_SPACE_SRGB;
2126 break;
2127
2128 default:
2129 WARN_ON(1);
2130 break;
2131 }
2132
2133 return color_space;
2134}
2135
2136/*****************************************************************************/
2137
3ee6b26b
AD		 2138static void
2139fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2140 const struct drm_display_mode *mode_in,
2141 const struct drm_connector *connector)
e7b07cee
HW		 2142{
2143 struct dc_crtc_timing *timing_out = &stream->timing;
a6114e85 2144 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2145
e7b07cee
HW		 2146 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2147
2148 timing_out->h_border_left = 0;
2149 timing_out->h_border_right = 0;
2150 timing_out->v_border_top = 0;
2151 timing_out->v_border_bottom = 0;
2152 /* TODO: un-hardcode */
2153
2154 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2155 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2156 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2157 else
2158 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2159
2160 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2161 timing_out->display_color_depth = convert_color_depth_from_display_info(
2162 connector);
2163 timing_out->scan_type = SCANNING_TYPE_NODATA;
2164 timing_out->hdmi_vic = 0;
2165 timing_out->vic = drm_match_cea_mode(mode_in);
2166
2167 timing_out->h_addressable = mode_in->crtc_hdisplay;
2168 timing_out->h_total = mode_in->crtc_htotal;
2169 timing_out->h_sync_width =
2170 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2171 timing_out->h_front_porch =
2172 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2173 timing_out->v_total = mode_in->crtc_vtotal;
2174 timing_out->v_addressable = mode_in->crtc_vdisplay;
2175 timing_out->v_front_porch =
2176 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2177 timing_out->v_sync_width =
2178 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2179 timing_out->pix_clk_khz = mode_in->crtc_clock;
2180 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2181 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2182 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2183 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2184 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2185
2186 stream->output_color_space = get_output_color_space(timing_out);
2187
a6114e85
HW		 2188 tf->type = TF_TYPE_PREDEFINED;
2189 tf->tf = TRANSFER_FUNCTION_SRGB;
2190 stream->out_transfer_func = tf;
e7b07cee
HW		 2191}
2192
3ee6b26b
AD		 2193static void fill_audio_info(struct audio_info *audio_info,
2194 const struct drm_connector *drm_connector,
2195 const struct dc_sink *dc_sink)
e7b07cee
HW		 2196{
2197 int i = 0;
2198 int cea_revision = 0;
2199 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2200
2201 audio_info->manufacture_id = edid_caps->manufacturer_id;
2202 audio_info->product_id = edid_caps->product_id;
2203
2204 cea_revision = drm_connector->display_info.cea_rev;
2205
d2b2562c
TSD		 2206 strncpy(audio_info->display_name,
2207 edid_caps->display_name,
2208 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2209
b830ebc9 2210 if (cea_revision >= 3) {
e7b07cee
HW		 2211 audio_info->mode_count = edid_caps->audio_mode_count;
2212
2213 for (i = 0; i < audio_info->mode_count; ++i) {
2214 audio_info->modes[i].format_code =
2215 (enum audio_format_code)
2216 (edid_caps->audio_modes[i].format_code);
2217 audio_info->modes[i].channel_count =
2218 edid_caps->audio_modes[i].channel_count;
2219 audio_info->modes[i].sample_rates.all =
2220 edid_caps->audio_modes[i].sample_rate;
2221 audio_info->modes[i].sample_size =
2222 edid_caps->audio_modes[i].sample_size;
2223 }
2224 }
2225
2226 audio_info->flags.all = edid_caps->speaker_flags;
2227
2228 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2229 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2230 audio_info->video_latency = drm_connector->video_latency[0];
2231 audio_info->audio_latency = drm_connector->audio_latency[0];
2232 }
2233
2234 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2235
2236}
2237
3ee6b26b
AD		 2238static void
2239copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2240 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2241{
2242 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2243 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2244 dst_mode->crtc_clock = src_mode->crtc_clock;
2245 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2246 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2247 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2248 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2249 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2250 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2251 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2252 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2253 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2254 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2255 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2256}
2257
3ee6b26b
AD		 2258static void
2259decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2260 const struct drm_display_mode *native_mode,
2261 bool scale_enabled)
e7b07cee
HW		 2262{
2263 if (scale_enabled) {
2264 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2265 } else if (native_mode->clock == drm_mode->clock &&
2266 native_mode->htotal == drm_mode->htotal &&
2267 native_mode->vtotal == drm_mode->vtotal) {
2268 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2269 } else {
2270 /* no scaling nor amdgpu inserted, no need to patch */
2271 }
2272}
2273
423788c7 2274static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6
HW		 2275{
2276 struct dc_sink *sink = NULL;
2277 struct dc_sink_init_data sink_init_data = { 0 };
2278
2279 sink_init_data.link = aconnector->dc_link;
2280 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2281
2282 sink = dc_sink_create(&sink_init_data);
423788c7 2283 if (!sink) {
2e0ac3d6 2284 DRM_ERROR("Failed to create sink!\n");
423788c7
ES		 2285 return -ENOMEM;
2286 }
2e0ac3d6
HW		 2287
2288 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2289 aconnector->fake_enable = true;
2290
2291 aconnector->dc_sink = sink;
2292 aconnector->dc_link->local_sink = sink;
423788c7
ES		 2293
2294 return 0;
2e0ac3d6
HW		 2295}
2296
fa2123db
ML		 2297static void set_multisync_trigger_params(
2298 struct dc_stream_state *stream)
2299{
2300 if (stream->triggered_crtc_reset.enabled) {
2301 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2302 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2303 }
2304}
2305
2306static void set_master_stream(struct dc_stream_state *stream_set[],
2307 int stream_count)
2308{
2309 int j, highest_rfr = 0, master_stream = 0;
2310
2311 for (j = 0; j < stream_count; j++) {
2312 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2313 int refresh_rate = 0;
2314
2315 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2316 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2317 if (refresh_rate > highest_rfr) {
2318 highest_rfr = refresh_rate;
2319 master_stream = j;
2320 }
2321 }
2322 }
2323 for (j = 0; j < stream_count; j++) {
03736f4c 2324 if (stream_set[j])
fa2123db
ML		 2325 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2326 }
2327}
2328
2329static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2330{
2331 int i = 0;
2332
2333 if (context->stream_count < 2)
2334 return;
2335 for (i = 0; i < context->stream_count ; i++) {
2336 if (!context->streams[i])
2337 continue;
2338 /* TODO: add a function to read AMD VSDB bits and will set
2339 * crtc_sync_master.multi_sync_enabled flag
2340 * For now its set to false
2341 */
2342 set_multisync_trigger_params(context->streams[i]);
2343 }
2344 set_master_stream(context->streams, context->stream_count);
2345}
2346
3ee6b26b
AD		 2347static struct dc_stream_state *
2348create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2349 const struct drm_display_mode *drm_mode,
2350 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2351{
2352 struct drm_display_mode *preferred_mode = NULL;
391ef035 2353 struct drm_connector *drm_connector;
0971c40e 2354 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2355 struct drm_display_mode mode = *drm_mode;
2356 bool native_mode_found = false;
2357
b830ebc9 2358 if (aconnector == NULL) {
e7b07cee 2359 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2360 return stream;
e7b07cee
HW		 2361 }
2362
e7b07cee 2363 drm_connector = &aconnector->base;
2e0ac3d6 2364
f4ac176e
JZ		 2365 if (!aconnector->dc_sink) {
2366 /*
391ef035
JFZ		 2367 * Create dc_sink when necessary to MST
2368 * Don't apply fake_sink to MST
f4ac176e 2369 */
391ef035
JFZ		 2370 if (aconnector->mst_port) {
2371 dm_dp_mst_dc_sink_create(drm_connector);
64245fa7 2372 return stream;
391ef035 2373 }
f4ac176e 2374
423788c7 2375 if (create_fake_sink(aconnector))
64245fa7 2376 return stream;
f4ac176e 2377 }
2e0ac3d6 2378
e7b07cee 2379 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2380
b830ebc9 2381 if (stream == NULL) {
e7b07cee 2382 DRM_ERROR("Failed to create stream for sink!\n");
64245fa7 2383 return stream;
e7b07cee
HW		 2384 }
2385
2386 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2387 /* Search for preferred mode */
2388 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2389 native_mode_found = true;
2390 break;
2391 }
2392 }
2393 if (!native_mode_found)
2394 preferred_mode = list_first_entry_or_null(
2395 &aconnector->base.modes,
2396 struct drm_display_mode,
2397 head);
2398
b830ebc9 2399 if (preferred_mode == NULL) {
e7b07cee
HW		 2400 /* This may not be an error, the use case is when we we have no
2401 * usermode calls to reset and set mode upon hotplug. In this
2402 * case, we call set mode ourselves to restore the previous mode
2403 * and the modelist may not be filled in in time.
2404 */
f1ad2f5e 2405 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2406 } else {
2407 decide_crtc_timing_for_drm_display_mode(
2408 &mode, preferred_mode,
f4791779 2409 dm_state ? (dm_state->scaling != RMX_OFF) : false);
e7b07cee
HW		 2410 }
2411
f783577c
JFZ		 2412 if (!dm_state)
2413 drm_mode_set_crtcinfo(&mode, 0);
2414
e7b07cee
HW		 2415 fill_stream_properties_from_drm_display_mode(stream,
2416 &mode, &aconnector->base);
2417 update_stream_scaling_settings(&mode, dm_state, stream);
2418
2419 fill_audio_info(
2420 &stream->audio_info,
2421 drm_connector,
2422 aconnector->dc_sink);
2423
9182b4cb
HW		 2424 update_stream_signal(stream);
2425
e7b07cee
HW		 2426 return stream;
2427}
2428
7578ecda 2429static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2430{
2431 drm_crtc_cleanup(crtc);
2432 kfree(crtc);
2433}
2434
2435static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2436 struct drm_crtc_state *state)
e7b07cee
HW		 2437{
2438 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2439
2440 /* TODO Destroy dc_stream objects are stream object is flattened */
2441 if (cur->stream)
2442 dc_stream_release(cur->stream);
2443
2444
2445 __drm_atomic_helper_crtc_destroy_state(state);
2446
2447
2448 kfree(state);
2449}
2450
2451static void dm_crtc_reset_state(struct drm_crtc *crtc)
2452{
2453 struct dm_crtc_state *state;
2454
2455 if (crtc->state)
2456 dm_crtc_destroy_state(crtc, crtc->state);
2457
2458 state = kzalloc(sizeof(*state), GFP_KERNEL);
2459 if (WARN_ON(!state))
2460 return;
2461
2462 crtc->state = &state->base;
2463 crtc->state->crtc = crtc;
2464
2465}
2466
2467static struct drm_crtc_state *
2468dm_crtc_duplicate_state(struct drm_crtc *crtc)
2469{
2470 struct dm_crtc_state *state, *cur;
2471
2472 cur = to_dm_crtc_state(crtc->state);
2473
2474 if (WARN_ON(!crtc->state))
2475 return NULL;
2476
2004f45e 2477 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 2478 if (!state)
2479 return NULL;
e7b07cee
HW		 2480
2481 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2482
2483 if (cur->stream) {
2484 state->stream = cur->stream;
2485 dc_stream_retain(state->stream);
2486 }
2487
2488 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2489
2490 return &state->base;
2491}
2492
2493/* Implemented only the options currently availible for the driver */
2494static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2495 .reset = dm_crtc_reset_state,
2496 .destroy = amdgpu_dm_crtc_destroy,
2497 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2498 .set_config = drm_atomic_helper_set_config,
2499 .page_flip = drm_atomic_helper_page_flip,
2500 .atomic_duplicate_state = dm_crtc_duplicate_state,
2501 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 2502 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
e7b07cee
HW		 2503};
2504
2505static enum drm_connector_status
2506amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2507{
2508 bool connected;
c84dec2f 2509 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2510
2511 /* Notes:
2512 * 1. This interface is NOT called in context of HPD irq.
2513 * 2. This interface *is called* in context of user-mode ioctl. Which
2514 * makes it a bad place for *any* MST-related activit. */
2515
8580d60b
HW		 2516 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2517 !aconnector->fake_enable)
e7b07cee
HW		 2518 connected = (aconnector->dc_sink != NULL);
2519 else
2520 connected = (aconnector->base.force == DRM_FORCE_ON);
2521
2522 return (connected ? connector_status_connected :
2523 connector_status_disconnected);
2524}
2525
3ee6b26b
AD		 2526int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2527 struct drm_connector_state *connector_state,
2528 struct drm_property *property,
2529 uint64_t val)
e7b07cee
HW		 2530{
2531 struct drm_device *dev = connector->dev;
2532 struct amdgpu_device *adev = dev->dev_private;
2533 struct dm_connector_state *dm_old_state =
2534 to_dm_connector_state(connector->state);
2535 struct dm_connector_state *dm_new_state =
2536 to_dm_connector_state(connector_state);
2537
2538 int ret = -EINVAL;
2539
2540 if (property == dev->mode_config.scaling_mode_property) {
2541 enum amdgpu_rmx_type rmx_type;
2542
2543 switch (val) {
2544 case DRM_MODE_SCALE_CENTER:
2545 rmx_type = RMX_CENTER;
2546 break;
2547 case DRM_MODE_SCALE_ASPECT:
2548 rmx_type = RMX_ASPECT;
2549 break;
2550 case DRM_MODE_SCALE_FULLSCREEN:
2551 rmx_type = RMX_FULL;
2552 break;
2553 case DRM_MODE_SCALE_NONE:
2554 default:
2555 rmx_type = RMX_OFF;
2556 break;
2557 }
2558
2559 if (dm_old_state->scaling == rmx_type)
2560 return 0;
2561
2562 dm_new_state->scaling = rmx_type;
2563 ret = 0;
2564 } else if (property == adev->mode_info.underscan_hborder_property) {
2565 dm_new_state->underscan_hborder = val;
2566 ret = 0;
2567 } else if (property == adev->mode_info.underscan_vborder_property) {
2568 dm_new_state->underscan_vborder = val;
2569 ret = 0;
2570 } else if (property == adev->mode_info.underscan_property) {
2571 dm_new_state->underscan_enable = val;
2572 ret = 0;
2573 }
2574
2575 return ret;
2576}
2577
3ee6b26b
AD		 2578int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2579 const struct drm_connector_state *state,
2580 struct drm_property *property,
2581 uint64_t *val)
e7b07cee
HW		 2582{
2583 struct drm_device *dev = connector->dev;
2584 struct amdgpu_device *adev = dev->dev_private;
2585 struct dm_connector_state *dm_state =
2586 to_dm_connector_state(state);
2587 int ret = -EINVAL;
2588
2589 if (property == dev->mode_config.scaling_mode_property) {
2590 switch (dm_state->scaling) {
2591 case RMX_CENTER:
2592 *val = DRM_MODE_SCALE_CENTER;
2593 break;
2594 case RMX_ASPECT:
2595 *val = DRM_MODE_SCALE_ASPECT;
2596 break;
2597 case RMX_FULL:
2598 *val = DRM_MODE_SCALE_FULLSCREEN;
2599 break;
2600 case RMX_OFF:
2601 default:
2602 *val = DRM_MODE_SCALE_NONE;
2603 break;
2604 }
2605 ret = 0;
2606 } else if (property == adev->mode_info.underscan_hborder_property) {
2607 *val = dm_state->underscan_hborder;
2608 ret = 0;
2609 } else if (property == adev->mode_info.underscan_vborder_property) {
2610 *val = dm_state->underscan_vborder;
2611 ret = 0;
2612 } else if (property == adev->mode_info.underscan_property) {
2613 *val = dm_state->underscan_enable;
2614 ret = 0;
2615 }
2616 return ret;
2617}
2618
7578ecda 2619static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2620{
c84dec2f 2621 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2622 const struct dc_link *link = aconnector->dc_link;
2623 struct amdgpu_device *adev = connector->dev->dev_private;
2624 struct amdgpu_display_manager *dm = &adev->dm;
2625#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2626 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2627
2628 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2629 amdgpu_dm_register_backlight_device(dm);
2630
2631 if (dm->backlight_dev) {
2632 backlight_device_unregister(dm->backlight_dev);
2633 dm->backlight_dev = NULL;
2634 }
2635
2636 }
2637#endif
2638 drm_connector_unregister(connector);
2639 drm_connector_cleanup(connector);
2640 kfree(connector);
2641}
2642
2643void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2644{
2645 struct dm_connector_state *state =
2646 to_dm_connector_state(connector->state);
2647
2648 kfree(state);
2649
2650 state = kzalloc(sizeof(*state), GFP_KERNEL);
2651
2652 if (state) {
2653 state->scaling = RMX_OFF;
2654 state->underscan_enable = false;
2655 state->underscan_hborder = 0;
2656 state->underscan_vborder = 0;
2657
2658 connector->state = &state->base;
2659 connector->state->connector = connector;
2660 }
2661}
2662
3ee6b26b
AD		 2663struct drm_connector_state *
2664amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2665{
2666 struct dm_connector_state *state =
2667 to_dm_connector_state(connector->state);
2668
2669 struct dm_connector_state *new_state =
2670 kmemdup(state, sizeof(*state), GFP_KERNEL);
2671
2672 if (new_state) {
2673 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2674 &new_state->base);
e7b07cee
HW		 2675 return &new_state->base;
2676 }
2677
2678 return NULL;
2679}
2680
2681static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2682 .reset = amdgpu_dm_connector_funcs_reset,
2683 .detect = amdgpu_dm_connector_detect,
2684 .fill_modes = drm_helper_probe_single_connector_modes,
2685 .destroy = amdgpu_dm_connector_destroy,
2686 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2687 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2688 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2689 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2690};
2691
2692static struct drm_encoder *best_encoder(struct drm_connector *connector)
2693{
2694 int enc_id = connector->encoder_ids[0];
2695 struct drm_mode_object *obj;
2696 struct drm_encoder *encoder;
2697
f1ad2f5e 2698 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2699
2700 /* pick the encoder ids */
2701 if (enc_id) {
bd21a37d 2702 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2703 if (!obj) {
2704 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2705 return NULL;
2706 }
2707 encoder = obj_to_encoder(obj);
2708 return encoder;
2709 }
2710 DRM_ERROR("No encoder id\n");
2711 return NULL;
2712}
2713
2714static int get_modes(struct drm_connector *connector)
2715{
2716 return amdgpu_dm_connector_get_modes(connector);
2717}
2718
c84dec2f 2719static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2720{
2721 struct dc_sink_init_data init_params = {
2722 .link = aconnector->dc_link,
2723 .sink_signal = SIGNAL_TYPE_VIRTUAL
2724 };
70e8ffc5 2725 struct edid *edid;
e7b07cee 2726
a89ff457 2727 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 2728 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2729 aconnector->base.name);
2730
2731 aconnector->base.force = DRM_FORCE_OFF;
2732 aconnector->base.override_edid = false;
2733 return;
2734 }
2735
70e8ffc5
HW		 2736 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2737
e7b07cee
HW		 2738 aconnector->edid = edid;
2739
2740 aconnector->dc_em_sink = dc_link_add_remote_sink(
2741 aconnector->dc_link,
2742 (uint8_t *)edid,
2743 (edid->extensions + 1) * EDID_LENGTH,
2744 &init_params);
2745
a68d90e7 2746 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 2747 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2748 aconnector->dc_link->local_sink :
2749 aconnector->dc_em_sink;
2750}
2751
c84dec2f 2752static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2753{
2754 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2755
2756 /* In case of headless boot with force on for DP managed connector
2757 * Those settings have to be != 0 to get initial modeset
2758 */
2759 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2760 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2761 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2762 }
2763
2764
2765 aconnector->base.override_edid = true;
2766 create_eml_sink(aconnector);
2767}
2768
3ee6b26b
AD		 2769int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2770 struct drm_display_mode *mode)
e7b07cee
HW		 2771{
2772 int result = MODE_ERROR;
2773 struct dc_sink *dc_sink;
2774 struct amdgpu_device *adev = connector->dev->dev_private;
2775 /* TODO: Unhardcode stream count */
0971c40e 2776 struct dc_stream_state *stream;
c84dec2f 2777 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 2778 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 2779
2780 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2781 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2782 return result;
2783
2784 /* Only run this the first time mode_valid is called to initilialize
2785 * EDID mgmt
2786 */
2787 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2788 !aconnector->dc_em_sink)
2789 handle_edid_mgmt(aconnector);
2790
c84dec2f 2791 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2792
b830ebc9 2793 if (dc_sink == NULL) {
e7b07cee
HW		 2794 DRM_ERROR("dc_sink is NULL!\n");
2795 goto fail;
2796 }
2797
f4791779 2798 stream = create_stream_for_sink(aconnector, mode, NULL);
b830ebc9 2799 if (stream == NULL) {
e7b07cee
HW		 2800 DRM_ERROR("Failed to create stream for sink!\n");
2801 goto fail;
2802 }
2803
a39438f0
HW		 2804 dc_result = dc_validate_stream(adev->dm.dc, stream);
2805
2806 if (dc_result == DC_OK)
e7b07cee 2807 result = MODE_OK;
a39438f0 2808 else
9f921b14 2809 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 2810 mode->vdisplay,
2811 mode->hdisplay,
9f921b14
HW		 2812 mode->clock,
2813 dc_result);
e7b07cee
HW		 2814
2815 dc_stream_release(stream);
2816
2817fail:
2818 /* TODO: error handling*/
2819 return result;
2820}
2821
2822static const struct drm_connector_helper_funcs
2823amdgpu_dm_connector_helper_funcs = {
2824 /*
b830ebc9
HW		 2825 * If hotplug a second bigger display in FB Con mode, bigger resolution
2826 * modes will be filtered by drm_mode_validate_size(), and those modes
2827 * is missing after user start lightdm. So we need to renew modes list.
2828 * in get_modes call back, not just return the modes count
2829 */
e7b07cee
HW		 2830 .get_modes = get_modes,
2831 .mode_valid = amdgpu_dm_connector_mode_valid,
2832 .best_encoder = best_encoder
2833};
2834
2835static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2836{
2837}
2838
3ee6b26b
AD		 2839static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2840 struct drm_crtc_state *state)
e7b07cee
HW		 2841{
2842 struct amdgpu_device *adev = crtc->dev->dev_private;
2843 struct dc *dc = adev->dm.dc;
2844 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2845 int ret = -EINVAL;
2846
9b690ef3
BL		 2847 if (unlikely(!dm_crtc_state->stream &&
2848 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2849 WARN_ON(1);
2850 return ret;
2851 }
2852
2853 /* In some use cases, like reset, no stream is attached */
2854 if (!dm_crtc_state->stream)
2855 return 0;
2856
62c933f9 2857 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 2858 return 0;
2859
2860 return ret;
2861}
2862
3ee6b26b
AD		 2863static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2864 const struct drm_display_mode *mode,
2865 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2866{
2867 return true;
2868}
2869
2870static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2871 .disable = dm_crtc_helper_disable,
2872 .atomic_check = dm_crtc_helper_atomic_check,
2873 .mode_fixup = dm_crtc_helper_mode_fixup
2874};
2875
2876static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2877{
2878
2879}
2880
3ee6b26b
AD		 2881static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2882 struct drm_crtc_state *crtc_state,
2883 struct drm_connector_state *conn_state)
e7b07cee
HW		 2884{
2885 return 0;
2886}
2887
2888const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2889 .disable = dm_encoder_helper_disable,
2890 .atomic_check = dm_encoder_helper_atomic_check
2891};
2892
2893static void dm_drm_plane_reset(struct drm_plane *plane)
2894{
2895 struct dm_plane_state *amdgpu_state = NULL;
2896
2897 if (plane->state)
2898 plane->funcs->atomic_destroy_state(plane, plane->state);
2899
2900 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d
TSD		 2901 WARN_ON(amdgpu_state == NULL);
2902
e7b07cee
HW		 2903 if (amdgpu_state) {
2904 plane->state = &amdgpu_state->base;
2905 plane->state->plane = plane;
2906 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 2907 }
e7b07cee
HW		 2908}
2909
2910static struct drm_plane_state *
2911dm_drm_plane_duplicate_state(struct drm_plane *plane)
2912{
2913 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2914
2915 old_dm_plane_state = to_dm_plane_state(plane->state);
2916 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2917 if (!dm_plane_state)
2918 return NULL;
2919
2920 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2921
3be5262e
HW		 2922 if (old_dm_plane_state->dc_state) {
2923 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2924 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2925 }
2926
2927 return &dm_plane_state->base;
2928}
2929
2930void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2931 struct drm_plane_state *state)
e7b07cee
HW		 2932{
2933 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2934
3be5262e
HW		 2935 if (dm_plane_state->dc_state)
2936 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2937
0627bbd3 2938 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2939}
2940
2941static const struct drm_plane_funcs dm_plane_funcs = {
2942 .update_plane = drm_atomic_helper_update_plane,
2943 .disable_plane = drm_atomic_helper_disable_plane,
2944 .destroy = drm_plane_cleanup,
2945 .reset = dm_drm_plane_reset,
2946 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2947 .atomic_destroy_state = dm_drm_plane_destroy_state,
2948};
2949
3ee6b26b
AD		 2950static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2951 struct drm_plane_state *new_state)
e7b07cee
HW		 2952{
2953 struct amdgpu_framebuffer *afb;
2954 struct drm_gem_object *obj;
5d43be0c 2955 struct amdgpu_device *adev;
e7b07cee 2956 struct amdgpu_bo *rbo;
56087b31 2957 uint64_t chroma_addr = 0;
e7b07cee
HW		 2958 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2959 unsigned int awidth;
5d43be0c
CK		 2960 uint32_t domain;
2961 int r;
e7b07cee
HW		 2962
2963 dm_plane_state_old = to_dm_plane_state(plane->state);
2964 dm_plane_state_new = to_dm_plane_state(new_state);
2965
2966 if (!new_state->fb) {
f1ad2f5e 2967 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 2968 return 0;
2969 }
2970
2971 afb = to_amdgpu_framebuffer(new_state->fb);
2972
2973 obj = afb->obj;
2974 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 2975 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 2976 r = amdgpu_bo_reserve(rbo, false);
2977 if (unlikely(r != 0))
2978 return r;
2979
5d43be0c
CK		 2980 if (plane->type != DRM_PLANE_TYPE_CURSOR)
2981 domain = amdgpu_display_framebuffer_domains(adev);
2982 else
2983 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 2984
5d43be0c 2985 r = amdgpu_bo_pin(rbo, domain, &afb->address);
e7b07cee
HW		 2986
2987 amdgpu_bo_unreserve(rbo);
2988
2989 if (unlikely(r != 0)) {
30b7c614
HW		 2990 if (r != -ERESTARTSYS)
2991 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
e7b07cee
HW		 2992 return r;
2993 }
2994
2995 amdgpu_bo_ref(rbo);
2996
3be5262e
HW		 2997 if (dm_plane_state_new->dc_state &&
2998 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2999 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3000
3be5262e
HW		 3001 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3002 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3003 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 3004 } else {
3005 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3006 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3007 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3008 = lower_32_bits(afb->address);
56087b31
S		 3009 plane_state->address.video_progressive.luma_addr.high_part
3010 = upper_32_bits(afb->address);
35888630 3011 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3012 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3013 = lower_32_bits(chroma_addr);
3014 plane_state->address.video_progressive.chroma_addr.high_part
3015 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3016 }
3017 }
3018
3019 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
3020 * prepare and cleanup in drm_atomic_helper_prepare_planes
3021 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
3022 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
3023 * code touching fram buffers should be avoided for DC.
3024 */
3025 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3026 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
3027
3028 acrtc->cursor_bo = obj;
3029 }
3030 return 0;
3031}
3032
3ee6b26b
AD		 3033static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3034 struct drm_plane_state *old_state)
e7b07cee
HW		 3035{
3036 struct amdgpu_bo *rbo;
3037 struct amdgpu_framebuffer *afb;
3038 int r;
3039
3040 if (!old_state->fb)
3041 return;
3042
3043 afb = to_amdgpu_framebuffer(old_state->fb);
3044 rbo = gem_to_amdgpu_bo(afb->obj);
3045 r = amdgpu_bo_reserve(rbo, false);
3046 if (unlikely(r)) {
3047 DRM_ERROR("failed to reserve rbo before unpin\n");
3048 return;
b830ebc9
HW		 3049 }
3050
3051 amdgpu_bo_unpin(rbo);
3052 amdgpu_bo_unreserve(rbo);
3053 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3054}
3055
7578ecda
AD		 3056static int dm_plane_atomic_check(struct drm_plane *plane,
3057 struct drm_plane_state *state)
cbd19488
AG		 3058{
3059 struct amdgpu_device *adev = plane->dev->dev_private;
3060 struct dc *dc = adev->dm.dc;
3061 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3062
3be5262e 3063 if (!dm_plane_state->dc_state)
9a3329b1 3064 return 0;
cbd19488 3065
62c933f9 3066 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3067 return 0;
3068
3069 return -EINVAL;
3070}
3071
e7b07cee
HW		 3072static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3073 .prepare_fb = dm_plane_helper_prepare_fb,
3074 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3075 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3076};
3077
3078/*
3079 * TODO: these are currently initialized to rgb formats only.
3080 * For future use cases we should either initialize them dynamically based on
3081 * plane capabilities, or initialize this array to all formats, so internal drm
3082 * check will succeed, and let DC to implement proper check
3083 */
d90371b0 3084static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3085 DRM_FORMAT_RGB888,
3086 DRM_FORMAT_XRGB8888,
3087 DRM_FORMAT_ARGB8888,
3088 DRM_FORMAT_RGBA8888,
3089 DRM_FORMAT_XRGB2101010,
3090 DRM_FORMAT_XBGR2101010,
3091 DRM_FORMAT_ARGB2101010,
3092 DRM_FORMAT_ABGR2101010,
3093};
3094
99d1abf8 3095static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3096 DRM_FORMAT_NV12,
3097 DRM_FORMAT_NV21,
3098};
3099
3100static const u32 cursor_formats[] = {
3101 DRM_FORMAT_ARGB8888
3102};
3103
7578ecda
AD		 3104static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3105 struct amdgpu_plane *aplane,
3106 unsigned long possible_crtcs)
e7b07cee
HW		 3107{
3108 int res = -EPERM;
3109
3110 switch (aplane->base.type) {
3111 case DRM_PLANE_TYPE_PRIMARY:
3112 aplane->base.format_default = true;
3113
3114 res = drm_universal_plane_init(
3115 dm->adev->ddev,
3116 &aplane->base,
3117 possible_crtcs,
3118 &dm_plane_funcs,
3119 rgb_formats,
3120 ARRAY_SIZE(rgb_formats),
3121 NULL, aplane->base.type, NULL);
3122 break;
3123 case DRM_PLANE_TYPE_OVERLAY:
3124 res = drm_universal_plane_init(
3125 dm->adev->ddev,
3126 &aplane->base,
3127 possible_crtcs,
3128 &dm_plane_funcs,
3129 yuv_formats,
3130 ARRAY_SIZE(yuv_formats),
3131 NULL, aplane->base.type, NULL);
3132 break;
3133 case DRM_PLANE_TYPE_CURSOR:
3134 res = drm_universal_plane_init(
3135 dm->adev->ddev,
3136 &aplane->base,
3137 possible_crtcs,
3138 &dm_plane_funcs,
3139 cursor_formats,
3140 ARRAY_SIZE(cursor_formats),
3141 NULL, aplane->base.type, NULL);
3142 break;
3143 }
3144
3145 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3146
96719c54
HW		 3147 /* Create (reset) the plane state */
3148 if (aplane->base.funcs->reset)
3149 aplane->base.funcs->reset(&aplane->base);
3150
3151
e7b07cee
HW		 3152 return res;
3153}
3154
7578ecda
AD		 3155static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3156 struct drm_plane *plane,
3157 uint32_t crtc_index)
e7b07cee
HW		 3158{
3159 struct amdgpu_crtc *acrtc = NULL;
3160 struct amdgpu_plane *cursor_plane;
3161
3162 int res = -ENOMEM;
3163
3164 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3165 if (!cursor_plane)
3166 goto fail;
3167
3168 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3169 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3170
3171 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3172 if (!acrtc)
3173 goto fail;
3174
3175 res = drm_crtc_init_with_planes(
3176 dm->ddev,
3177 &acrtc->base,
3178 plane,
3179 &cursor_plane->base,
3180 &amdgpu_dm_crtc_funcs, NULL);
3181
3182 if (res)
3183 goto fail;
3184
3185 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3186
96719c54
HW		 3187 /* Create (reset) the plane state */
3188 if (acrtc->base.funcs->reset)
3189 acrtc->base.funcs->reset(&acrtc->base);
3190
e7b07cee
HW		 3191 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3192 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3193
3194 acrtc->crtc_id = crtc_index;
3195 acrtc->base.enabled = false;
3196
3197 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3198 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3199 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3200 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3201
3202 return 0;
3203
3204fail:
b830ebc9
HW		 3205 kfree(acrtc);
3206 kfree(cursor_plane);
e7b07cee
HW		 3207 return res;
3208}
3209
3210
3211static int to_drm_connector_type(enum signal_type st)
3212{
3213 switch (st) {
3214 case SIGNAL_TYPE_HDMI_TYPE_A:
3215 return DRM_MODE_CONNECTOR_HDMIA;
3216 case SIGNAL_TYPE_EDP:
3217 return DRM_MODE_CONNECTOR_eDP;
3218 case SIGNAL_TYPE_RGB:
3219 return DRM_MODE_CONNECTOR_VGA;
3220 case SIGNAL_TYPE_DISPLAY_PORT:
3221 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3222 return DRM_MODE_CONNECTOR_DisplayPort;
3223 case SIGNAL_TYPE_DVI_DUAL_LINK:
3224 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3225 return DRM_MODE_CONNECTOR_DVID;
3226 case SIGNAL_TYPE_VIRTUAL:
3227 return DRM_MODE_CONNECTOR_VIRTUAL;
3228
3229 default:
3230 return DRM_MODE_CONNECTOR_Unknown;
3231 }
3232}
3233
3234static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3235{
3236 const struct drm_connector_helper_funcs *helper =
3237 connector->helper_private;
3238 struct drm_encoder *encoder;
3239 struct amdgpu_encoder *amdgpu_encoder;
3240
3241 encoder = helper->best_encoder(connector);
3242
3243 if (encoder == NULL)
3244 return;
3245
3246 amdgpu_encoder = to_amdgpu_encoder(encoder);
3247
3248 amdgpu_encoder->native_mode.clock = 0;
3249
3250 if (!list_empty(&connector->probed_modes)) {
3251 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3252
e7b07cee 3253 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3254 &connector->probed_modes,
3255 head) {
3256 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3257 amdgpu_encoder->native_mode = *preferred_mode;
3258
e7b07cee
HW		 3259 break;
3260 }
3261
3262 }
3263}
3264
3ee6b26b
AD		 3265static struct drm_display_mode *
3266amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3267 char *name,
3268 int hdisplay, int vdisplay)
e7b07cee
HW		 3269{
3270 struct drm_device *dev = encoder->dev;
3271 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3272 struct drm_display_mode *mode = NULL;
3273 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3274
3275 mode = drm_mode_duplicate(dev, native_mode);
3276
b830ebc9 3277 if (mode == NULL)
e7b07cee
HW		 3278 return NULL;
3279
3280 mode->hdisplay = hdisplay;
3281 mode->vdisplay = vdisplay;
3282 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3283 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3284
3285 return mode;
3286
3287}
3288
3289static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3290 struct drm_connector *connector)
e7b07cee
HW		 3291{
3292 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3293 struct drm_display_mode *mode = NULL;
3294 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3295 struct amdgpu_dm_connector *amdgpu_dm_connector =
3296 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3297 int i;
3298 int n;
3299 struct mode_size {
3300 char name[DRM_DISPLAY_MODE_LEN];
3301 int w;
3302 int h;
b830ebc9 3303 } common_modes[] = {
e7b07cee
HW		 3304 { "640x480", 640, 480},
3305 { "800x600", 800, 600},
3306 { "1024x768", 1024, 768},
3307 { "1280x720", 1280, 720},
3308 { "1280x800", 1280, 800},
3309 {"1280x1024", 1280, 1024},
3310 { "1440x900", 1440, 900},
3311 {"1680x1050", 1680, 1050},
3312 {"1600x1200", 1600, 1200},
3313 {"1920x1080", 1920, 1080},
3314 {"1920x1200", 1920, 1200}
3315 };
3316
b830ebc9 3317 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3318
3319 for (i = 0; i < n; i++) {
3320 struct drm_display_mode *curmode = NULL;
3321 bool mode_existed = false;
3322
3323 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3324 common_modes[i].h > native_mode->vdisplay ||
3325 (common_modes[i].w == native_mode->hdisplay &&
3326 common_modes[i].h == native_mode->vdisplay))
3327 continue;
e7b07cee
HW		 3328
3329 list_for_each_entry(curmode, &connector->probed_modes, head) {
3330 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3331 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3332 mode_existed = true;
3333 break;
3334 }
3335 }
3336
3337 if (mode_existed)
3338 continue;
3339
3340 mode = amdgpu_dm_create_common_mode(encoder,
3341 common_modes[i].name, common_modes[i].w,
3342 common_modes[i].h);
3343 drm_mode_probed_add(connector, mode);
c84dec2f 3344 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3345 }
3346}
3347
3ee6b26b
AD		 3348static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3349 struct edid *edid)
e7b07cee 3350{
c84dec2f
HW		 3351 struct amdgpu_dm_connector *amdgpu_dm_connector =
3352 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3353
3354 if (edid) {
3355 /* empty probed_modes */
3356 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3357 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3358 drm_add_edid_modes(connector, edid);
3359
e7b07cee 3360 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3361 } else {
c84dec2f 3362 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3363 }
e7b07cee
HW		 3364}
3365
7578ecda 3366static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3367{
3368 const struct drm_connector_helper_funcs *helper =
3369 connector->helper_private;
c84dec2f
HW		 3370 struct amdgpu_dm_connector *amdgpu_dm_connector =
3371 to_amdgpu_dm_connector(connector);
e7b07cee 3372 struct drm_encoder *encoder;
c84dec2f 3373 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3374
3375 encoder = helper->best_encoder(connector);
e7b07cee
HW		 3376 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3377 amdgpu_dm_connector_add_common_modes(encoder, connector);
3e332d3a
RL		 3378
3379#if defined(CONFIG_DRM_AMD_DC_FBC)
3380 amdgpu_dm_fbc_init(connector);
3381#endif
c84dec2f 3382 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3383}
3384
3ee6b26b
AD		 3385void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3386 struct amdgpu_dm_connector *aconnector,
3387 int connector_type,
3388 struct dc_link *link,
3389 int link_index)
e7b07cee
HW		 3390{
3391 struct amdgpu_device *adev = dm->ddev->dev_private;
3392
3393 aconnector->connector_id = link_index;
3394 aconnector->dc_link = link;
3395 aconnector->base.interlace_allowed = false;
3396 aconnector->base.doublescan_allowed = false;
3397 aconnector->base.stereo_allowed = false;
3398 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3399 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3400
3401 mutex_init(&aconnector->hpd_lock);
3402
b830ebc9
HW		 3403 /* configure support HPD hot plug connector_>polled default value is 0
3404 * which means HPD hot plug not supported
3405 */
e7b07cee
HW		 3406 switch (connector_type) {
3407 case DRM_MODE_CONNECTOR_HDMIA:
3408 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3409 break;
3410 case DRM_MODE_CONNECTOR_DisplayPort:
3411 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3412 break;
3413 case DRM_MODE_CONNECTOR_DVID:
3414 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3415 break;
3416 default:
3417 break;
3418 }
3419
3420 drm_object_attach_property(&aconnector->base.base,
3421 dm->ddev->mode_config.scaling_mode_property,
3422 DRM_MODE_SCALE_NONE);
3423
3424 drm_object_attach_property(&aconnector->base.base,
3425 adev->mode_info.underscan_property,
3426 UNDERSCAN_OFF);
3427 drm_object_attach_property(&aconnector->base.base,
3428 adev->mode_info.underscan_hborder_property,
3429 0);
3430 drm_object_attach_property(&aconnector->base.base,
3431 adev->mode_info.underscan_vborder_property,
3432 0);
3433
3434}
3435
7578ecda
AD		 3436static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3437 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3438{
3439 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3440 struct ddc_service *ddc_service = i2c->ddc_service;
3441 struct i2c_command cmd;
3442 int i;
3443 int result = -EIO;
3444
b830ebc9 3445 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3446
3447 if (!cmd.payloads)
3448 return result;
3449
3450 cmd.number_of_payloads = num;
3451 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3452 cmd.speed = 100;
3453
3454 for (i = 0; i < num; i++) {
3455 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3456 cmd.payloads[i].address = msgs[i].addr;
3457 cmd.payloads[i].length = msgs[i].len;
3458 cmd.payloads[i].data = msgs[i].buf;
3459 }
3460
3461 if (dal_i2caux_submit_i2c_command(
3462 ddc_service->ctx->i2caux,
3463 ddc_service->ddc_pin,
3464 &cmd))
3465 result = num;
3466
3467 kfree(cmd.payloads);
3468 return result;
3469}
3470
7578ecda 3471static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3472{
3473 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3474}
3475
3476static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3477 .master_xfer = amdgpu_dm_i2c_xfer,
3478 .functionality = amdgpu_dm_i2c_func,
3479};
3480
3ee6b26b
AD		 3481static struct amdgpu_i2c_adapter *
3482create_i2c(struct ddc_service *ddc_service,
3483 int link_index,
3484 int *res)
e7b07cee
HW		 3485{
3486 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3487 struct amdgpu_i2c_adapter *i2c;
3488
b830ebc9 3489 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 3490 if (!i2c)
3491 return NULL;
e7b07cee
HW		 3492 i2c->base.owner = THIS_MODULE;
3493 i2c->base.class = I2C_CLASS_DDC;
3494 i2c->base.dev.parent = &adev->pdev->dev;
3495 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3496 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3497 i2c_set_adapdata(&i2c->base, i2c);
3498 i2c->ddc_service = ddc_service;
3499
3500 return i2c;
3501}
3502
3503/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3504 * dc_link which will be represented by this aconnector.
3505 */
7578ecda
AD		 3506static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3507 struct amdgpu_dm_connector *aconnector,
3508 uint32_t link_index,
3509 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3510{
3511 int res = 0;
3512 int connector_type;
3513 struct dc *dc = dm->dc;
3514 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3515 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 3516
3517 link->priv = aconnector;
e7b07cee 3518
f1ad2f5e 3519 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3520
3521 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 3522 if (!i2c) {
3523 DRM_ERROR("Failed to create i2c adapter data\n");
3524 return -ENOMEM;
3525 }
3526
e7b07cee
HW		 3527 aconnector->i2c = i2c;
3528 res = i2c_add_adapter(&i2c->base);
3529
3530 if (res) {
3531 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3532 goto out_free;
3533 }
3534
3535 connector_type = to_drm_connector_type(link->connector_signal);
3536
3537 res = drm_connector_init(
3538 dm->ddev,
3539 &aconnector->base,
3540 &amdgpu_dm_connector_funcs,
3541 connector_type);
3542
3543 if (res) {
3544 DRM_ERROR("connector_init failed\n");
3545 aconnector->connector_id = -1;
3546 goto out_free;
3547 }
3548
3549 drm_connector_helper_add(
3550 &aconnector->base,
3551 &amdgpu_dm_connector_helper_funcs);
3552
96719c54
HW		 3553 if (aconnector->base.funcs->reset)
3554 aconnector->base.funcs->reset(&aconnector->base);
3555
e7b07cee
HW		 3556 amdgpu_dm_connector_init_helper(
3557 dm,
3558 aconnector,
3559 connector_type,
3560 link,
3561 link_index);
3562
3563 drm_mode_connector_attach_encoder(
3564 &aconnector->base, &aencoder->base);
3565
3566 drm_connector_register(&aconnector->base);
3567
3568 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3569 || connector_type == DRM_MODE_CONNECTOR_eDP)
3570 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3571
3572#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3573 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3574
3575 /* NOTE: this currently will create backlight device even if a panel
3576 * is not connected to the eDP/LVDS connector.
3577 *
3578 * This is less than ideal but we don't have sink information at this
3579 * stage since detection happens after. We can't do detection earlier
3580 * since MST detection needs connectors to be created first.
3581 */
3582 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3583 /* Event if registration failed, we should continue with
3584 * DM initialization because not having a backlight control
b830ebc9
HW		 3585 * is better then a black screen.
3586 */
e7b07cee
HW		 3587 amdgpu_dm_register_backlight_device(dm);
3588
3589 if (dm->backlight_dev)
3590 dm->backlight_link = link;
3591 }
3592#endif
3593
3594out_free:
3595 if (res) {
3596 kfree(i2c);
3597 aconnector->i2c = NULL;
3598 }
3599 return res;
3600}
3601
3602int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3603{
3604 switch (adev->mode_info.num_crtc) {
3605 case 1:
3606 return 0x1;
3607 case 2:
3608 return 0x3;
3609 case 3:
3610 return 0x7;
3611 case 4:
3612 return 0xf;
3613 case 5:
3614 return 0x1f;
3615 case 6:
3616 default:
3617 return 0x3f;
3618 }
3619}
3620
7578ecda
AD		 3621static int amdgpu_dm_encoder_init(struct drm_device *dev,
3622 struct amdgpu_encoder *aencoder,
3623 uint32_t link_index)
e7b07cee
HW		 3624{
3625 struct amdgpu_device *adev = dev->dev_private;
3626
3627 int res = drm_encoder_init(dev,
3628 &aencoder->base,
3629 &amdgpu_dm_encoder_funcs,
3630 DRM_MODE_ENCODER_TMDS,
3631 NULL);
3632
3633 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3634
3635 if (!res)
3636 aencoder->encoder_id = link_index;
3637 else
3638 aencoder->encoder_id = -1;
3639
3640 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3641
3642 return res;
3643}
3644
3ee6b26b
AD		 3645static void manage_dm_interrupts(struct amdgpu_device *adev,
3646 struct amdgpu_crtc *acrtc,
3647 bool enable)
e7b07cee
HW		 3648{
3649 /*
3650 * this is not correct translation but will work as soon as VBLANK
3651 * constant is the same as PFLIP
3652 */
3653 int irq_type =
734dd01d 3654 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 3655 adev,
3656 acrtc->crtc_id);
3657
3658 if (enable) {
3659 drm_crtc_vblank_on(&acrtc->base);
3660 amdgpu_irq_get(
3661 adev,
3662 &adev->pageflip_irq,
3663 irq_type);
3664 } else {
3665
3666 amdgpu_irq_put(
3667 adev,
3668 &adev->pageflip_irq,
3669 irq_type);
3670 drm_crtc_vblank_off(&acrtc->base);
3671 }
3672}
3673
3ee6b26b
AD		 3674static bool
3675is_scaling_state_different(const struct dm_connector_state *dm_state,
3676 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3677{
3678 if (dm_state->scaling != old_dm_state->scaling)
3679 return true;
3680 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3681 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3682 return true;
3683 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3684 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3685 return true;
b830ebc9
HW		 3686 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3687 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3688 return true;
e7b07cee
HW		 3689 return false;
3690}
3691
3ee6b26b
AD		 3692static void remove_stream(struct amdgpu_device *adev,
3693 struct amdgpu_crtc *acrtc,
3694 struct dc_stream_state *stream)
e7b07cee
HW		 3695{
3696 /* this is the update mode case */
3697 if (adev->dm.freesync_module)
3698 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3699
3700 acrtc->otg_inst = -1;
3701 acrtc->enabled = false;
3702}
3703
7578ecda
AD		 3704static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3705 struct dc_cursor_position *position)
2a8f6ccb
HW		 3706{
3707 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3708 int x, y;
3709 int xorigin = 0, yorigin = 0;
3710
3711 if (!crtc || !plane->state->fb) {
3712 position->enable = false;
3713 position->x = 0;
3714 position->y = 0;
3715 return 0;
3716 }
3717
3718 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3719 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3720 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3721 __func__,
3722 plane->state->crtc_w,
3723 plane->state->crtc_h);
3724 return -EINVAL;
3725 }
3726
3727 x = plane->state->crtc_x;
3728 y = plane->state->crtc_y;
3729 /* avivo cursor are offset into the total surface */
3730 x += crtc->primary->state->src_x >> 16;
3731 y += crtc->primary->state->src_y >> 16;
3732 if (x < 0) {
3733 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3734 x = 0;
3735 }
3736 if (y < 0) {
3737 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3738 y = 0;
3739 }
3740 position->enable = true;
3741 position->x = x;
3742 position->y = y;
3743 position->x_hotspot = xorigin;
3744 position->y_hotspot = yorigin;
3745
3746 return 0;
3747}
3748
3ee6b26b
AD		 3749static void handle_cursor_update(struct drm_plane *plane,
3750 struct drm_plane_state *old_plane_state)
e7b07cee 3751{
2a8f6ccb
HW		 3752 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3753 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3754 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3755 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3756 uint64_t address = afb ? afb->address : 0;
3757 struct dc_cursor_position position;
3758 struct dc_cursor_attributes attributes;
3759 int ret;
3760
e7b07cee
HW		 3761 if (!plane->state->fb && !old_plane_state->fb)
3762 return;
3763
f1ad2f5e 3764 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3765 __func__,
3766 amdgpu_crtc->crtc_id,
3767 plane->state->crtc_w,
3768 plane->state->crtc_h);
2a8f6ccb
HW		 3769
3770 ret = get_cursor_position(plane, crtc, &position);
3771 if (ret)
3772 return;
3773
3774 if (!position.enable) {
3775 /* turn off cursor */
3776 if (crtc_state && crtc_state->stream)
3777 dc_stream_set_cursor_position(crtc_state->stream,
3778 &position);
3779 return;
e7b07cee 3780 }
e7b07cee 3781
2a8f6ccb
HW		 3782 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3783 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3784
3785 attributes.address.high_part = upper_32_bits(address);
3786 attributes.address.low_part = lower_32_bits(address);
3787 attributes.width = plane->state->crtc_w;
3788 attributes.height = plane->state->crtc_h;
3789 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3790 attributes.rotation_angle = 0;
3791 attributes.attribute_flags.value = 0;
3792
3793 attributes.pitch = attributes.width;
3794
886daac9
JZ		 3795 if (crtc_state->stream) {
3796 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3797 &attributes))
3798 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3799
2a8f6ccb
HW		 3800 if (!dc_stream_set_cursor_position(crtc_state->stream,
3801 &position))
3802 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3803 }
2a8f6ccb 3804}
e7b07cee
HW		 3805
3806static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3807{
3808
3809 assert_spin_locked(&acrtc->base.dev->event_lock);
3810 WARN_ON(acrtc->event);
3811
3812 acrtc->event = acrtc->base.state->event;
3813
3814 /* Set the flip status */
3815 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3816
3817 /* Mark this event as consumed */
3818 acrtc->base.state->event = NULL;
3819
3820 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3821 acrtc->crtc_id);
3822}
3823
3824/*
3825 * Executes flip
3826 *
3827 * Waits on all BO's fences and for proper vblank count
3828 */
3ee6b26b
AD		 3829static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3830 struct drm_framebuffer *fb,
bc6828e0
BL		 3831 uint32_t target,
3832 struct dc_state *state)
e7b07cee
HW		 3833{
3834 unsigned long flags;
3835 uint32_t target_vblank;
3836 int r, vpos, hpos;
3837 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3838 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3839 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3840 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3841 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3842 struct dc_flip_addrs addr = { {0} };
3be5262e 3843 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3844 struct dc_surface_update surface_updates[1] = { {0} };
3845 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3846
3847
3848 /* Prepare wait for target vblank early - before the fence-waits */
3849 target_vblank = target - drm_crtc_vblank_count(crtc) +
3850 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3851
b830ebc9 3852 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3853 * explicitly on fences instead
3854 * and in general should be called for
3855 * blocking commit to as per framework helpers
b830ebc9 3856 */
e7b07cee
HW		 3857 r = amdgpu_bo_reserve(abo, true);
3858 if (unlikely(r != 0)) {
3859 DRM_ERROR("failed to reserve buffer before flip\n");
3860 WARN_ON(1);
3861 }
3862
3863 /* Wait for all fences on this FB */
3864 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3865 MAX_SCHEDULE_TIMEOUT) < 0);
3866
3867 amdgpu_bo_unreserve(abo);
3868
3869 /* Wait until we're out of the vertical blank period before the one
3870 * targeted by the flip
3871 */
3872 while ((acrtc->enabled &&
aa8e286a
SL		 3873 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
3874 0, &vpos, &hpos, NULL,
3875 NULL, &crtc->hwmode)
e7b07cee
HW		 3876 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3877 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3878 (int)(target_vblank -
3879 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3880 usleep_range(1000, 1100);
3881 }
3882
3883 /* Flip */
3884 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3885 /* update crtc fb */
3886 crtc->primary->fb = fb;
3887
3888 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3889 WARN_ON(!acrtc_state->stream);
3890
3891 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3892 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3893 addr.flip_immediate = async_flip;
3894
3895
3896 if (acrtc->base.state->event)
3897 prepare_flip_isr(acrtc);
3898
3be5262e 3899 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3900 surface_updates->flip_addr = &addr;
3901
3902
bc6828e0
BL		 3903 dc_commit_updates_for_stream(adev->dm.dc,
3904 surface_updates,
3905 1,
3906 acrtc_state->stream,
3907 NULL,
3908 &surface_updates->surface,
3909 state);
e7b07cee
HW		 3910
3911 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3912 __func__,
3913 addr.address.grph.addr.high_part,
3914 addr.address.grph.addr.low_part);
3915
3916
3917 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3918}
3919
3be5262e 3920static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 3921 struct drm_device *dev,
3922 struct amdgpu_display_manager *dm,
3923 struct drm_crtc *pcrtc,
3924 bool *wait_for_vblank)
e7b07cee
HW		 3925{
3926 uint32_t i;
3927 struct drm_plane *plane;
0bc9706d 3928 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 3929 struct dc_stream_state *dc_stream_attach;
3be5262e 3930 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 3931 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 3932 struct drm_crtc_state *new_pcrtc_state =
3933 drm_atomic_get_new_crtc_state(state, pcrtc);
3934 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
bc6828e0 3935 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 3936 int planes_count = 0;
3937 unsigned long flags;
3938
3939 /* update planes when needed */
0bc9706d
LSL		 3940 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3941 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 3942 struct drm_crtc_state *new_crtc_state;
0bc9706d 3943 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 3944 bool pflip_needed;
54d76575 3945 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 3946
3947 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3948 handle_cursor_update(plane, old_plane_state);
3949 continue;
3950 }
3951
f5ba60fe
DD		 3952 if (!fb || !crtc || pcrtc != crtc)
3953 continue;
3954
3955 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
3956 if (!new_crtc_state->active)
e7b07cee
HW		 3957 continue;
3958
3959 pflip_needed = !state->allow_modeset;
3960
3961 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3962 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3963 DRM_ERROR("%s: acrtc %d, already busy\n",
3964 __func__,
3965 acrtc_attach->crtc_id);
b830ebc9 3966 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3967 WARN_ON(1);
3968 }
3969 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3970
3971 if (!pflip_needed) {
54d76575 3972 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 3973
54d76575 3974 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 3975
3976 dc_stream_attach = acrtc_state->stream;
3977 planes_count++;
3978
0bc9706d 3979 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 3980 /* Assume even ONE crtc with immediate flip means
3981 * entire can't wait for VBLANK
3982 * TODO Check if it's correct
3983 */
3984 *wait_for_vblank =
0bc9706d 3985 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 3986 false : true;
3987
3988 /* TODO: Needs rework for multiplane flip */
3989 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3990 drm_crtc_vblank_get(crtc);
3991
3992 amdgpu_dm_do_flip(
3993 crtc,
3994 fb,
bc6828e0
BL		 3995 drm_crtc_vblank_count(crtc) + *wait_for_vblank,
3996 dm_state->context);
e7b07cee
HW		 3997 }
3998
3999 }
4000
4001 if (planes_count) {
4002 unsigned long flags;
4003
0bc9706d 4004 if (new_pcrtc_state->event) {
e7b07cee
HW		 4005
4006 drm_crtc_vblank_get(pcrtc);
4007
4008 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4009 prepare_flip_isr(acrtc_attach);
4010 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4011 }
4012
3be5262e
HW		 4013 if (false == dc_commit_planes_to_stream(dm->dc,
4014 plane_states_constructed,
4015 planes_count,
bc6828e0
BL		 4016 dc_stream_attach,
4017 dm_state->context))
3be5262e 4018 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4019 } else {
4020 /*TODO BUG Here should go disable planes on CRTC. */
4021 }
4022}
4023
27b3f4fc
LSL		 4024/**
4025 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4026 * @crtc_state: the DRM CRTC state
4027 * @stream_state: the DC stream state.
4028 *
4029 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4030 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4031 */
4032static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4033 struct dc_stream_state *stream_state)
4034{
4035 stream_state->mode_changed = crtc_state->mode_changed;
4036}
e7b07cee 4037
7578ecda
AD		 4038static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4039 struct drm_atomic_state *state,
4040 bool nonblock)
e7b07cee
HW		 4041{
4042 struct drm_crtc *crtc;
c2cea706 4043 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4044 struct amdgpu_device *adev = dev->dev_private;
4045 int i;
4046
4047 /*
4048 * We evade vblanks and pflips on crtc that
4049 * should be changed. We do it here to flush & disable
4050 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4051 * it will update crtc->dm_crtc_state->stream pointer which is used in
4052 * the ISRs.
4053 */
c2cea706 4054 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4055 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 4056 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4057
54d76575 4058 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 4059 manage_dm_interrupts(adev, acrtc, false);
4060 }
fc9e9920
S		 4061 /* Add check here for SoC's that support hardware cursor plane, to
4062 * unset legacy_cursor_update */
e7b07cee
HW		 4063
4064 return drm_atomic_helper_commit(dev, state, nonblock);
4065
4066 /*TODO Handle EINTR, reenable IRQ*/
4067}
4068
7578ecda 4069static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4070{
4071 struct drm_device *dev = state->dev;
4072 struct amdgpu_device *adev = dev->dev_private;
4073 struct amdgpu_display_manager *dm = &adev->dm;
4074 struct dm_atomic_state *dm_state;
4075 uint32_t i, j;
5cc6dcbd 4076 struct drm_crtc *crtc;
0bc9706d 4077 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4078 unsigned long flags;
4079 bool wait_for_vblank = true;
4080 struct drm_connector *connector;
c2cea706 4081 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4082 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
e7b07cee
HW		 4083
4084 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4085
4086 dm_state = to_dm_atomic_state(state);
4087
4088 /* update changed items */
0bc9706d 4089 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4090 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4091
54d76575
LSL		 4092 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4093 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4094
f1ad2f5e 4095 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4096 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4097 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4098 "connectors_changed:%d\n",
4099 acrtc->crtc_id,
0bc9706d
LSL		 4100 new_crtc_state->enable,
4101 new_crtc_state->active,
4102 new_crtc_state->planes_changed,
4103 new_crtc_state->mode_changed,
4104 new_crtc_state->active_changed,
4105 new_crtc_state->connectors_changed);
e7b07cee 4106
27b3f4fc
LSL		 4107 /* Copy all transient state flags into dc state */
4108 if (dm_new_crtc_state->stream) {
4109 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4110 dm_new_crtc_state->stream);
4111 }
4112
e7b07cee
HW		 4113 /* handles headless hotplug case, updating new_state and
4114 * aconnector as needed
4115 */
4116
54d76575 4117 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4118
f1ad2f5e 4119 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4120
54d76575 4121 if (!dm_new_crtc_state->stream) {
e7b07cee 4122 /*
b830ebc9
HW		 4123 * this could happen because of issues with
4124 * userspace notifications delivery.
4125 * In this case userspace tries to set mode on
4126 * display which is disconnect in fact.
4127 * dc_sink in NULL in this case on aconnector.
4128 * We expect reset mode will come soon.
4129 *
4130 * This can also happen when unplug is done
4131 * during resume sequence ended
4132 *
4133 * In this case, we want to pretend we still
4134 * have a sink to keep the pipe running so that
4135 * hw state is consistent with the sw state
4136 */
f1ad2f5e 4137 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4138 __func__, acrtc->base.base.id);
4139 continue;
4140 }
4141
54d76575
LSL		 4142 if (dm_old_crtc_state->stream)
4143 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 4144
e7b07cee 4145 acrtc->enabled = true;
0bc9706d
LSL		 4146 acrtc->hw_mode = new_crtc_state->mode;
4147 crtc->hwmode = new_crtc_state->mode;
4148 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4149 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4150
4151 /* i.e. reset mode */
54d76575
LSL		 4152 if (dm_old_crtc_state->stream)
4153 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4154 }
4155 } /* for_each_crtc_in_state() */
4156
4157 /*
4158 * Add streams after required streams from new and replaced streams
4159 * are removed from freesync module
4160 */
4161 if (adev->dm.freesync_module) {
8b8f27f9
LSL		 4162 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4163 new_crtc_state, i) {
c84dec2f 4164 struct amdgpu_dm_connector *aconnector = NULL;
f01a2cf0
LSL		 4165 struct dm_connector_state *dm_new_con_state = NULL;
4166 struct amdgpu_crtc *acrtc = NULL;
1c77d4ee 4167 bool modeset_needed;
b830ebc9 4168
54d76575 4169 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1c77d4ee
LSL		 4170 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4171 modeset_needed = modeset_required(
4172 new_crtc_state,
4173 dm_new_crtc_state->stream,
4174 dm_old_crtc_state->stream);
4175 /* We add stream to freesync if:
4176 * 1. Said stream is not null, and
4177 * 2. A modeset is requested. This means that the
4178 * stream was removed previously, and needs to be
4179 * replaced.
4180 */
4181 if (dm_new_crtc_state->stream == NULL ||
4182 !modeset_needed)
4183 continue;
4184
f01a2cf0 4185 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4186
f01a2cf0
LSL		 4187 aconnector =
4188 amdgpu_dm_find_first_crtc_matching_connector(
4189 state, crtc);
e7b07cee 4190 if (!aconnector) {
8b8f27f9
LSL		 4191 DRM_DEBUG_DRIVER("Atomic commit: Failed to "
4192 "find connector for acrtc "
4193 "id:%d skipping freesync "
4194 "init\n",
4195 acrtc->crtc_id);
e7b07cee
HW		 4196 continue;
4197 }
4198
4199 mod_freesync_add_stream(adev->dm.freesync_module,
f01a2cf0
LSL		 4200 dm_new_crtc_state->stream,
4201 &aconnector->caps);
4202 new_con_state = drm_atomic_get_new_connector_state(
4203 state, &aconnector->base);
4204 dm_new_con_state = to_dm_connector_state(new_con_state);
4205
1c77d4ee
LSL		 4206 mod_freesync_set_user_enable(adev->dm.freesync_module,
4207 &dm_new_crtc_state->stream,
4208 1,
4209 &dm_new_con_state->user_enable);
bfe1708c 4210 }
e7b07cee
HW		 4211 }
4212
fa2123db
ML		 4213 if (dm_state->context) {
4214 dm_enable_per_frame_crtc_master_sync(dm_state->context);
608ac7bb 4215 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
fa2123db 4216 }
e7b07cee 4217
0bc9706d 4218 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4219 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4220
54d76575 4221 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4222
54d76575 4223 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4224 const struct dc_stream_status *status =
54d76575 4225 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4226
4227 if (!status)
54d76575 4228 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4229 else
4230 acrtc->otg_inst = status->primary_otg_inst;
4231 }
4232 }
4233
ebdd27e1 4234 /* Handle scaling and underscan changes*/
c2cea706 4235 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4236 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4237 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4238 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4239 struct dc_stream_status *status = NULL;
4240
0bc9706d
LSL		 4241 if (acrtc)
4242 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4243
e7b07cee 4244 /* Skip any modesets/resets */
0bc9706d 4245 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4246 continue;
4247
4248 /* Skip any thing not scale or underscan changes */
54d76575 4249 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4250 continue;
4251
54d76575 4252 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4253
54d76575
LSL		 4254 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4255 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4256
70e8ffc5
HW		 4257 if (!dm_new_crtc_state->stream)
4258 continue;
4259
54d76575 4260 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4261 WARN_ON(!status);
3be5262e 4262 WARN_ON(!status->plane_count);
e7b07cee 4263
e7b07cee 4264 /*TODO How it works with MPO ?*/
3be5262e 4265 if (!dc_commit_planes_to_stream(
e7b07cee 4266 dm->dc,
3be5262e
HW		 4267 status->plane_states,
4268 status->plane_count,
bc6828e0
BL		 4269 dm_new_crtc_state->stream,
4270 dm_state->context))
e7b07cee
HW		 4271 dm_error("%s: Failed to update stream scaling!\n", __func__);
4272 }
4273
e1fc2dca
LSL		 4274 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4275 new_crtc_state, i) {
e7b07cee
HW		 4276 /*
4277 * loop to enable interrupts on newly arrived crtc
4278 */
e1fc2dca
LSL		 4279 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4280 bool modeset_needed;
b830ebc9 4281
54d76575 4282 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 4283 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4284 modeset_needed = modeset_required(
4285 new_crtc_state,
4286 dm_new_crtc_state->stream,
4287 dm_old_crtc_state->stream);
4288
4289 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4290 continue;
e7b07cee
HW		 4291
4292 if (adev->dm.freesync_module)
4293 mod_freesync_notify_mode_change(
e1fc2dca
LSL		 4294 adev->dm.freesync_module,
4295 &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4296
4297 manage_dm_interrupts(adev, acrtc, true);
4298 }
4299
4300 /* update planes when needed per crtc*/
5cc6dcbd 4301 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4302 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4303
54d76575 4304 if (dm_new_crtc_state->stream)
5cc6dcbd 4305 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4306 }
4307
4308
4309 /*
4310 * send vblank event on all events not handled in flip and
4311 * mark consumed event for drm_atomic_helper_commit_hw_done
4312 */
4313 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4314 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4315
0bc9706d
LSL		 4316 if (new_crtc_state->event)
4317 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4318
0bc9706d 4319 new_crtc_state->event = NULL;
e7b07cee
HW		 4320 }
4321 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4322
4323 /* Signal HW programming completion */
4324 drm_atomic_helper_commit_hw_done(state);
4325
4326 if (wait_for_vblank)
320a1274 4327 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 4328
4329 drm_atomic_helper_cleanup_planes(dev, state);
4330}
4331
4332
4333static int dm_force_atomic_commit(struct drm_connector *connector)
4334{
4335 int ret = 0;
4336 struct drm_device *ddev = connector->dev;
4337 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4338 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4339 struct drm_plane *plane = disconnected_acrtc->base.primary;
4340 struct drm_connector_state *conn_state;
4341 struct drm_crtc_state *crtc_state;
4342 struct drm_plane_state *plane_state;
4343
4344 if (!state)
4345 return -ENOMEM;
4346
4347 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4348
4349 /* Construct an atomic state to restore previous display setting */
4350
4351 /*
4352 * Attach connectors to drm_atomic_state
4353 */
4354 conn_state = drm_atomic_get_connector_state(state, connector);
4355
4356 ret = PTR_ERR_OR_ZERO(conn_state);
4357 if (ret)
4358 goto err;
4359
4360 /* Attach crtc to drm_atomic_state*/
4361 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4362
4363 ret = PTR_ERR_OR_ZERO(crtc_state);
4364 if (ret)
4365 goto err;
4366
4367 /* force a restore */
4368 crtc_state->mode_changed = true;
4369
4370 /* Attach plane to drm_atomic_state */
4371 plane_state = drm_atomic_get_plane_state(state, plane);
4372
4373 ret = PTR_ERR_OR_ZERO(plane_state);
4374 if (ret)
4375 goto err;
4376
4377
4378 /* Call commit internally with the state we just constructed */
4379 ret = drm_atomic_commit(state);
4380 if (!ret)
4381 return 0;
4382
4383err:
4384 DRM_ERROR("Restoring old state failed with %i\n", ret);
4385 drm_atomic_state_put(state);
4386
4387 return ret;
4388}
4389
4390/*
4391 * This functions handle all cases when set mode does not come upon hotplug.
4392 * This include when the same display is unplugged then plugged back into the
4393 * same port and when we are running without usermode desktop manager supprot
4394 */
3ee6b26b
AD		 4395void dm_restore_drm_connector_state(struct drm_device *dev,
4396 struct drm_connector *connector)
e7b07cee 4397{
c84dec2f 4398 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4399 struct amdgpu_crtc *disconnected_acrtc;
4400 struct dm_crtc_state *acrtc_state;
4401
4402 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4403 return;
4404
4405 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 4406 if (!disconnected_acrtc)
4407 return;
e7b07cee 4408
70e8ffc5
HW		 4409 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4410 if (!acrtc_state->stream)
e7b07cee
HW		 4411 return;
4412
4413 /*
4414 * If the previous sink is not released and different from the current,
4415 * we deduce we are in a state where we can not rely on usermode call
4416 * to turn on the display, so we do it here
4417 */
4418 if (acrtc_state->stream->sink != aconnector->dc_sink)
4419 dm_force_atomic_commit(&aconnector->base);
4420}
4421
e7b07cee
HW		 4422/*`
4423 * Grabs all modesetting locks to serialize against any blocking commits,
4424 * Waits for completion of all non blocking commits.
4425 */
3ee6b26b
AD		 4426static int do_aquire_global_lock(struct drm_device *dev,
4427 struct drm_atomic_state *state)
e7b07cee
HW		 4428{
4429 struct drm_crtc *crtc;
4430 struct drm_crtc_commit *commit;
4431 long ret;
4432
4433 /* Adding all modeset locks to aquire_ctx will
4434 * ensure that when the framework release it the
4435 * extra locks we are locking here will get released to
4436 */
4437 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4438 if (ret)
4439 return ret;
4440
4441 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4442 spin_lock(&crtc->commit_lock);
4443 commit = list_first_entry_or_null(&crtc->commit_list,
4444 struct drm_crtc_commit, commit_entry);
4445 if (commit)
4446 drm_crtc_commit_get(commit);
4447 spin_unlock(&crtc->commit_lock);
4448
4449 if (!commit)
4450 continue;
4451
4452 /* Make sure all pending HW programming completed and
4453 * page flips done
4454 */
4455 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4456
4457 if (ret > 0)
4458 ret = wait_for_completion_interruptible_timeout(
4459 &commit->flip_done, 10*HZ);
4460
4461 if (ret == 0)
4462 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4463 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4464
4465 drm_crtc_commit_put(commit);
4466 }
4467
4468 return ret < 0 ? ret : 0;
4469}
4470
3ee6b26b
AD		 4471static int dm_update_crtcs_state(struct dc *dc,
4472 struct drm_atomic_state *state,
4473 bool enable,
4474 bool *lock_and_validation_needed)
e7b07cee 4475{
e7b07cee 4476 struct drm_crtc *crtc;
c2cea706 4477 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4478 int i;
54d76575 4479 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4480 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4481 struct dc_stream_state *new_stream;
62f55537 4482 int ret = 0;
d4d4a645 4483
62f55537
AG		 4484 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4485 /* update changed items */
c2cea706 4486 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4487 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4488 struct amdgpu_dm_connector *aconnector = NULL;
c2cea706 4489 struct drm_connector_state *new_con_state = NULL;
62f55537 4490 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4491
9635b754
DS		 4492 new_stream = NULL;
4493
54d76575
LSL		 4494 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4495 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4496 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4497
1daf8c63 4498 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4499
62f55537 4500 /* TODO This hack should go away */
f4ac176e
JZ		 4501 if (aconnector && enable) {
4502 // Make sure fake sink is created in plug-in scenario
c2cea706
LSL		 4503 new_con_state = drm_atomic_get_connector_state(state,
4504 &aconnector->base);
19f89e23 4505
c2cea706
LSL		 4506 if (IS_ERR(new_con_state)) {
4507 ret = PTR_ERR_OR_ZERO(new_con_state);
62f55537
AG		 4508 break;
4509 }
19f89e23 4510
c2cea706 4511 dm_conn_state = to_dm_connector_state(new_con_state);
19f89e23 4512
62f55537 4513 new_stream = create_stream_for_sink(aconnector,
c2cea706 4514 &new_crtc_state->mode,
62f55537 4515 dm_conn_state);
19f89e23 4516
62f55537
AG		 4517 /*
4518 * we can have no stream on ACTION_SET if a display
4519 * was disconnected during S3, in this case it not and
4520 * error, the OS will be updated after detection, and
4521 * do the right thing on next atomic commit
4522 */
19f89e23 4523
62f55537 4524 if (!new_stream) {
f1ad2f5e 4525 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4526 __func__, acrtc->base.base.id);
4527 break;
19f89e23 4528 }
e7b07cee 4529
a97599a4
LSL		 4530 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4531 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4532 new_crtc_state->mode_changed = false;
4533 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4534 new_crtc_state->mode_changed);
4535 }
62f55537 4536 }
b830ebc9 4537
c2cea706 4538 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4539 goto next_crtc;
e7b07cee 4540
f1ad2f5e 4541 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4542 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4543 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4544 "connectors_changed:%d\n",
4545 acrtc->crtc_id,
c2cea706
LSL		 4546 new_crtc_state->enable,
4547 new_crtc_state->active,
4548 new_crtc_state->planes_changed,
4549 new_crtc_state->mode_changed,
4550 new_crtc_state->active_changed,
4551 new_crtc_state->connectors_changed);
e7b07cee 4552
62f55537
AG		 4553 /* Remove stream for any changed/disabled CRTC */
4554 if (!enable) {
4555
54d76575 4556 if (!dm_old_crtc_state->stream)
9635b754 4557 goto next_crtc;
62f55537 4558
f1ad2f5e 4559 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4560 crtc->base.id);
e7b07cee 4561
1dc90497 4562 /* i.e. reset mode */
62c933f9 4563 if (dc_remove_stream_from_ctx(
62f55537
AG		 4564 dc,
4565 dm_state->context,
62c933f9 4566 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4567 ret = -EINVAL;
9635b754 4568 goto fail;
62f55537
AG		 4569 }
4570
54d76575
LSL		 4571 dc_stream_release(dm_old_crtc_state->stream);
4572 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4573
4574 *lock_and_validation_needed = true;
4575
4576 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4577 /*
4578 * Quick fix to prevent NULL pointer on new_stream when
4579 * added MST connectors not found in existing crtc_state in the chained mode
4580 * TODO: need to dig out the root cause of that
4581 */
4582 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4583 goto next_crtc;
62f55537 4584
c2cea706 4585 if (modereset_required(new_crtc_state))
9635b754 4586 goto next_crtc;
62f55537 4587
c2cea706 4588 if (modeset_required(new_crtc_state, new_stream,
54d76575 4589 dm_old_crtc_state->stream)) {
62f55537 4590
54d76575 4591 WARN_ON(dm_new_crtc_state->stream);
62f55537 4592
54d76575 4593 dm_new_crtc_state->stream = new_stream;
27b3f4fc 4594
62f55537
AG		 4595 dc_stream_retain(new_stream);
4596
f1ad2f5e 4597 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4598 crtc->base.id);
1dc90497 4599
13ab1b44 4600 if (dc_add_stream_to_ctx(
1dc90497
AG		 4601 dc,
4602 dm_state->context,
13ab1b44 4603 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4604 ret = -EINVAL;
9635b754 4605 goto fail;
1dc90497
AG		 4606 }
4607
62f55537 4608 *lock_and_validation_needed = true;
9b690ef3 4609 }
62f55537 4610 }
9b690ef3 4611
9635b754 4612next_crtc:
62f55537
AG		 4613 /* Release extra reference */
4614 if (new_stream)
4615 dc_stream_release(new_stream);
e277adc5
LSL		 4616
4617 /*
4618 * We want to do dc stream updates that do not require a
4619 * full modeset below.
4620 */
4621 if (!enable || !aconnector || modereset_required(new_crtc_state))
4622 continue;
4623 /*
4624 * Given above conditions, the dc state cannot be NULL because:
4625 * 1. We're attempting to enable a CRTC. Which has a...
4626 * 2. Valid connector attached, and
4627 * 3. User does not want to reset it (disable or mark inactive,
4628 * which can happen on a CRTC that's already disabled).
4629 * => It currently exists.
4630 */
4631 BUG_ON(dm_new_crtc_state->stream == NULL);
4632
4633 /* Color managment settings */
4634 if (dm_new_crtc_state->base.color_mgmt_changed) {
4635 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
4636 if (ret)
4637 goto fail;
4638 amdgpu_dm_set_ctm(dm_new_crtc_state);
4639 }
62f55537 4640 }
e7b07cee 4641
62f55537 4642 return ret;
9635b754
DS		 4643
4644fail:
4645 if (new_stream)
4646 dc_stream_release(new_stream);
4647 return ret;
62f55537 4648}
9b690ef3 4649
3ee6b26b
AD		 4650static int dm_update_planes_state(struct dc *dc,
4651 struct drm_atomic_state *state,
4652 bool enable,
4653 bool *lock_and_validation_needed)
62f55537
AG		 4654{
4655 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4656 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4657 struct drm_plane *plane;
4658 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4659 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4660 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4661 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4662 int i ;
4663 /* TODO return page_flip_needed() function */
4664 bool pflip_needed = !state->allow_modeset;
4665 int ret = 0;
e7b07cee 4666
62f55537
AG		 4667 if (pflip_needed)
4668 return ret;
9b690ef3 4669
62f55537
AG		 4670 /* Add new planes */
4671 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4672 new_plane_crtc = new_plane_state->crtc;
4673 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4674 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4675 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4676
4677 /*TODO Implement atomic check for cursor plane */
4678 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4679 continue;
9b690ef3 4680
62f55537
AG		 4681 /* Remove any changed/removed planes */
4682 if (!enable) {
a7b06724 4683
62f55537
AG		 4684 if (!old_plane_crtc)
4685 continue;
4686
0bc9706d
LSL		 4687 old_crtc_state = drm_atomic_get_old_crtc_state(
4688 state, old_plane_crtc);
54d76575 4689 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4690
54d76575 4691 if (!dm_old_crtc_state->stream)
62f55537
AG		 4692 continue;
4693
f1ad2f5e 4694 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4695 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4696
62f55537
AG		 4697 if (!dc_remove_plane_from_context(
4698 dc,
54d76575
LSL		 4699 dm_old_crtc_state->stream,
4700 dm_old_plane_state->dc_state,
62f55537
AG		 4701 dm_state->context)) {
4702
4703 ret = EINVAL;
4704 return ret;
e7b07cee
HW		 4705 }
4706
9b690ef3 4707
54d76575
LSL		 4708 dc_plane_state_release(dm_old_plane_state->dc_state);
4709 dm_new_plane_state->dc_state = NULL;
1dc90497 4710
62f55537 4711 *lock_and_validation_needed = true;
1dc90497 4712
62f55537 4713 } else { /* Add new planes */
1dc90497 4714
62f55537
AG		 4715 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4716 continue;
e7b07cee 4717
62f55537
AG		 4718 if (!new_plane_crtc)
4719 continue;
e7b07cee 4720
62f55537 4721 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4722 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4723
54d76575 4724 if (!dm_new_crtc_state->stream)
62f55537
AG		 4725 continue;
4726
4727
54d76575 4728 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4729
54d76575 4730 dm_new_plane_state->dc_state = dc_create_plane_state(dc);
62f55537 4731
f1ad2f5e 4732 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
62f55537
AG		 4733 plane->base.id, new_plane_crtc->base.id);
4734
54d76575 4735 if (!dm_new_plane_state->dc_state) {
62f55537
AG		 4736 ret = -EINVAL;
4737 return ret;
4738 }
4739
4740 ret = fill_plane_attributes(
4741 new_plane_crtc->dev->dev_private,
54d76575 4742 dm_new_plane_state->dc_state,
62f55537 4743 new_plane_state,
9817d5f5 4744 new_crtc_state);
62f55537
AG		 4745 if (ret)
4746 return ret;
4747
62f55537
AG		 4748 if (!dc_add_plane_to_context(
4749 dc,
54d76575
LSL		 4750 dm_new_crtc_state->stream,
4751 dm_new_plane_state->dc_state,
62f55537
AG		 4752 dm_state->context)) {
4753
4754 ret = -EINVAL;
4755 return ret;
e7b07cee 4756 }
62f55537 4757
000b59ea
LSL		 4758 /* Tell DC to do a full surface update every time there
4759 * is a plane change. Inefficient, but works for now.
4760 */
4761 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
4762
62f55537 4763 *lock_and_validation_needed = true;
e7b07cee 4764 }
62f55537 4765 }
e7b07cee
HW		 4766
4767
62f55537
AG		 4768 return ret;
4769}
4770
7578ecda
AD		 4771static int amdgpu_dm_atomic_check(struct drm_device *dev,
4772 struct drm_atomic_state *state)
62f55537 4773{
62f55537
AG		 4774 struct amdgpu_device *adev = dev->dev_private;
4775 struct dc *dc = adev->dm.dc;
4776 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4777 struct drm_connector *connector;
c2cea706 4778 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4779 struct drm_crtc *crtc;
fc9e9920 4780 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1e88ad0a 4781 int ret, i;
e7b07cee 4782
62f55537
AG		 4783 /*
4784 * This bool will be set for true for any modeset/reset
4785 * or plane update which implies non fast surface update.
4786 */
4787 bool lock_and_validation_needed = false;
4788
4789 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 4790 if (ret)
4791 goto fail;
62f55537 4792
1e88ad0a
S		 4793 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4794 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
4795 !new_crtc_state->color_mgmt_changed)
4796 continue;
7bef1af3 4797
1e88ad0a
S		 4798 if (!new_crtc_state->enable)
4799 continue;
fc9e9920 4800
1e88ad0a
S		 4801 ret = drm_atomic_add_affected_connectors(state, crtc);
4802 if (ret)
4803 return ret;
fc9e9920 4804
1e88ad0a
S		 4805 ret = drm_atomic_add_affected_planes(state, crtc);
4806 if (ret)
4807 goto fail;
e7b07cee
HW		 4808 }
4809
62f55537
AG		 4810 dm_state->context = dc_create_state();
4811 ASSERT(dm_state->context);
f36cc577 4812 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4813
4814 /* Remove exiting planes if they are modified */
4815 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4816 if (ret) {
4817 goto fail;
4818 }
4819
4820 /* Disable all crtcs which require disable */
4821 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4822 if (ret) {
4823 goto fail;
4824 }
4825
4826 /* Enable all crtcs which require enable */
4827 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4828 if (ret) {
4829 goto fail;
4830 }
4831
4832 /* Add new/modified planes */
4833 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4834 if (ret) {
4835 goto fail;
4836 }
4837
b349f76e
ES		 4838 /* Run this here since we want to validate the streams we created */
4839 ret = drm_atomic_helper_check_planes(dev, state);
4840 if (ret)
4841 goto fail;
62f55537 4842
ebdd27e1 4843 /* Check scaling and underscan changes*/
e7b07cee
HW		 4844 /*TODO Removed scaling changes validation due to inability to commit
4845 * new stream into context w\o causing full reset. Need to
4846 * decide how to handle.
4847 */
c2cea706 4848 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4849 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4850 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4851 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4852
4853 /* Skip any modesets/resets */
0bc9706d
LSL		 4854 if (!acrtc || drm_atomic_crtc_needs_modeset(
4855 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 4856 continue;
4857
b830ebc9 4858 /* Skip any thing not scale or underscan changes */
54d76575 4859 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4860 continue;
4861
4862 lock_and_validation_needed = true;
4863 }
4864
e7b07cee
HW		 4865 /*
4866 * For full updates case when
4867 * removing/adding/updating streams on once CRTC while flipping
4868 * on another CRTC,
4869 * acquiring global lock will guarantee that any such full
4870 * update commit
4871 * will wait for completion of any outstanding flip using DRMs
4872 * synchronization events.
4873 */
4874
4875 if (lock_and_validation_needed) {
4876
4877 ret = do_aquire_global_lock(dev, state);
4878 if (ret)
4879 goto fail;
1dc90497 4880
e750d56d 4881 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 4882 ret = -EINVAL;
4883 goto fail;
4884 }
4885 }
4886
4887 /* Must be success */
4888 WARN_ON(ret);
4889 return ret;
4890
4891fail:
4892 if (ret == -EDEADLK)
01e28f9c 4893 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 4894 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 4895 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 4896 else
01e28f9c 4897 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 4898
4899 return ret;
4900}
4901
3ee6b26b
AD		 4902static bool is_dp_capable_without_timing_msa(struct dc *dc,
4903 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 4904{
4905 uint8_t dpcd_data;
4906 bool capable = false;
4907
c84dec2f 4908 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 4909 dm_helpers_dp_read_dpcd(
4910 NULL,
c84dec2f 4911 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 4912 DP_DOWN_STREAM_PORT_COUNT,
4913 &dpcd_data,
4914 sizeof(dpcd_data))) {
4915 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4916 }
4917
4918 return capable;
4919}
3ee6b26b
AD		 4920void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4921 struct edid *edid)
e7b07cee
HW		 4922{
4923 int i;
4924 uint64_t val_capable;
4925 bool edid_check_required;
4926 struct detailed_timing *timing;
4927 struct detailed_non_pixel *data;
4928 struct detailed_data_monitor_range *range;
c84dec2f
HW		 4929 struct amdgpu_dm_connector *amdgpu_dm_connector =
4930 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4931
4932 struct drm_device *dev = connector->dev;
4933 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4934
e7b07cee 4935 edid_check_required = false;
c84dec2f 4936 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 4937 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4938 return;
4939 }
4940 if (!adev->dm.freesync_module)
4941 return;
4942 /*
4943 * if edid non zero restrict freesync only for dp and edp
4944 */
4945 if (edid) {
c84dec2f
HW		 4946 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4947 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 4948 edid_check_required = is_dp_capable_without_timing_msa(
4949 adev->dm.dc,
c84dec2f 4950 amdgpu_dm_connector);
e7b07cee
HW		 4951 }
4952 }
4953 val_capable = 0;
4954 if (edid_check_required == true && (edid->version > 1 ||
4955 (edid->version == 1 && edid->revision > 1))) {
4956 for (i = 0; i < 4; i++) {
4957
4958 timing = &edid->detailed_timings[i];
4959 data = &timing->data.other_data;
4960 range = &data->data.range;
4961 /*
4962 * Check if monitor has continuous frequency mode
4963 */
4964 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4965 continue;
4966 /*
4967 * Check for flag range limits only. If flag == 1 then
4968 * no additional timing information provided.
4969 * Default GTF, GTF Secondary curve and CVT are not
4970 * supported
4971 */
4972 if (range->flags != 1)
4973 continue;
4974
c84dec2f
HW		 4975 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
4976 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
4977 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 4978 range->pixel_clock_mhz * 10;
4979 break;
4980 }
4981
c84dec2f
HW		 4982 if (amdgpu_dm_connector->max_vfreq -
4983 amdgpu_dm_connector->min_vfreq > 10) {
4984 amdgpu_dm_connector->caps.supported = true;
4985 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
4986 amdgpu_dm_connector->min_vfreq * 1000000;
4987 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
4988 amdgpu_dm_connector->max_vfreq * 1000000;
e7b07cee
HW		 4989 val_capable = 1;
4990 }
4991 }
4992
4993 /*
4994 * TODO figure out how to notify user-mode or DRM of freesync caps
4995 * once we figure out how to deal with freesync in an upstreamable
4996 * fashion
4997 */
4998
4999}
5000
3ee6b26b 5001void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 5002{
5003 /*
5004 * TODO fill in once we figure out how to deal with freesync in
5005 * an upstreamable fashion
5006 */
5007}
Linux 6.x block layer and io_uring tree(s)