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drm/amd/display: Initialize HDCP work queue
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
1dc90497 31#include "dc/inc/core_types.h"
a7669aff 32#include "dal_asic_id.h"
4562236b
HW		 33
34#include "vid.h"
35#include "amdgpu.h"
a49dcb88 36#include "amdgpu_display.h"
a94d5569 37#include "amdgpu_ucode.h"
4562236b
HW		 38#include "atom.h"
39#include "amdgpu_dm.h"
52704fca
BL		 40#ifdef CONFIG_DRM_AMD_DC_HDCP
41#include "amdgpu_dm_hdcp.h"
42#endif
e7b07cee 43#include "amdgpu_pm.h"
4562236b
HW		 44
45#include "amd_shared.h"
46#include "amdgpu_dm_irq.h"
47#include "dm_helpers.h"
e7b07cee 48#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 49#if defined(CONFIG_DEBUG_FS)
50#include "amdgpu_dm_debugfs.h"
51#endif
4562236b
HW		 52
53#include "ivsrcid/ivsrcid_vislands30.h"
54
55#include <linux/module.h>
56#include <linux/moduleparam.h>
57#include <linux/version.h>
e7b07cee 58#include <linux/types.h>
97028037 59#include <linux/pm_runtime.h>
09d21852 60#include <linux/pci.h>
a94d5569 61#include <linux/firmware.h>
6ce8f316 62#include <linux/component.h>
4562236b
HW		 63
64#include <drm/drm_atomic.h>
674e78ac 65#include <drm/drm_atomic_uapi.h>
4562236b
HW		 66#include <drm/drm_atomic_helper.h>
67#include <drm/drm_dp_mst_helper.h>
e7b07cee 68#include <drm/drm_fb_helper.h>
09d21852 69#include <drm/drm_fourcc.h>
e7b07cee 70#include <drm/drm_edid.h>
09d21852 71#include <drm/drm_vblank.h>
6ce8f316 72#include <drm/drm_audio_component.h>
4562236b 73
ff5ef992 74#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
5527cd06 75#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
ff5ef992 76
ad941f7a
FX		 77#include "dcn/dcn_1_0_offset.h"
78#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 79#include "soc15_hw_ip.h"
80#include "vega10_ip_offset.h"
ff5ef992
AD		 81
82#include "soc15_common.h"
83#endif
84
e7b07cee 85#include "modules/inc/mod_freesync.h"
bbf854dc 86#include "modules/power/power_helpers.h"
ecd0136b 87#include "modules/inc/mod_info_packet.h"
e7b07cee 88
a94d5569
DF		 89#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
90MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 91
b8592b48
LL		 92/**
93 * DOC: overview
94 *
95 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
96 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
97 * requests into DC requests, and DC responses into DRM responses.
98 *
99 * The root control structure is &struct amdgpu_display_manager.
100 */
101
7578ecda
AD		 102/* basic init/fini API */
103static int amdgpu_dm_init(struct amdgpu_device *adev);
104static void amdgpu_dm_fini(struct amdgpu_device *adev);
105
1f6010a9
DF		 106/*
107 * initializes drm_device display related structures, based on the information
7578ecda
AD		 108 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
109 * drm_encoder, drm_mode_config
110 *
111 * Returns 0 on success
112 */
113static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
114/* removes and deallocates the drm structures, created by the above function */
115static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
116
117static void
118amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
119
120static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 121 struct drm_plane *plane,
cc1fec57
NK		 122 unsigned long possible_crtcs,
123 const struct dc_plane_cap *plane_cap);
7578ecda
AD		 124static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
125 struct drm_plane *plane,
126 uint32_t link_index);
127static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
128 struct amdgpu_dm_connector *amdgpu_dm_connector,
129 uint32_t link_index,
130 struct amdgpu_encoder *amdgpu_encoder);
131static int amdgpu_dm_encoder_init(struct drm_device *dev,
132 struct amdgpu_encoder *aencoder,
133 uint32_t link_index);
134
135static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
136
137static int amdgpu_dm_atomic_commit(struct drm_device *dev,
138 struct drm_atomic_state *state,
139 bool nonblock);
140
141static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
142
143static int amdgpu_dm_atomic_check(struct drm_device *dev,
144 struct drm_atomic_state *state);
145
674e78ac
NK		 146static void handle_cursor_update(struct drm_plane *plane,
147 struct drm_plane_state *old_plane_state);
7578ecda 148
4562236b
HW		 149/*
150 * dm_vblank_get_counter
151 *
152 * @brief
153 * Get counter for number of vertical blanks
154 *
155 * @param
156 * struct amdgpu_device *adev - [in] desired amdgpu device
157 * int disp_idx - [in] which CRTC to get the counter from
158 *
159 * @return
160 * Counter for vertical blanks
161 */
162static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
163{
164 if (crtc >= adev->mode_info.num_crtc)
165 return 0;
166 else {
167 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 168 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
169 acrtc->base.state);
4562236b 170
da5c47f6
AG		 171
172 if (acrtc_state->stream == NULL) {
0971c40e
HW		 173 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
174 crtc);
4562236b
HW		 175 return 0;
176 }
177
da5c47f6 178 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 179 }
180}
181
182static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 183 u32 *vbl, u32 *position)
4562236b 184{
81c50963
ST		 185 uint32_t v_blank_start, v_blank_end, h_position, v_position;
186
4562236b
HW		 187 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
188 return -EINVAL;
189 else {
190 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 191 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
192 acrtc->base.state);
4562236b 193
da5c47f6 194 if (acrtc_state->stream == NULL) {
0971c40e
HW		 195 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
196 crtc);
4562236b
HW		 197 return 0;
198 }
199
81c50963
ST		 200 /*
201 * TODO rework base driver to use values directly.
202 * for now parse it back into reg-format
203 */
da5c47f6 204 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 205 &v_blank_start,
206 &v_blank_end,
207 &h_position,
208 &v_position);
209
e806208d
AG		 210 *position = v_position | (h_position << 16);
211 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 212 }
213
214 return 0;
215}
216
217static bool dm_is_idle(void *handle)
218{
219 /* XXX todo */
220 return true;
221}
222
223static int dm_wait_for_idle(void *handle)
224{
225 /* XXX todo */
226 return 0;
227}
228
229static bool dm_check_soft_reset(void *handle)
230{
231 return false;
232}
233
234static int dm_soft_reset(void *handle)
235{
236 /* XXX todo */
237 return 0;
238}
239
3ee6b26b
AD		 240static struct amdgpu_crtc *
241get_crtc_by_otg_inst(struct amdgpu_device *adev,
242 int otg_inst)
4562236b
HW		 243{
244 struct drm_device *dev = adev->ddev;
245 struct drm_crtc *crtc;
246 struct amdgpu_crtc *amdgpu_crtc;
247
4562236b
HW		 248 if (otg_inst == -1) {
249 WARN_ON(1);
250 return adev->mode_info.crtcs[0];
251 }
252
253 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
254 amdgpu_crtc = to_amdgpu_crtc(crtc);
255
256 if (amdgpu_crtc->otg_inst == otg_inst)
257 return amdgpu_crtc;
258 }
259
260 return NULL;
261}
262
66b0c973
MK		 263static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
264{
265 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
266 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
267}
268
4562236b
HW		 269static void dm_pflip_high_irq(void *interrupt_params)
270{
4562236b
HW		 271 struct amdgpu_crtc *amdgpu_crtc;
272 struct common_irq_params *irq_params = interrupt_params;
273 struct amdgpu_device *adev = irq_params->adev;
274 unsigned long flags;
71bbe51a
MK		 275 struct drm_pending_vblank_event *e;
276 struct dm_crtc_state *acrtc_state;
277 uint32_t vpos, hpos, v_blank_start, v_blank_end;
278 bool vrr_active;
4562236b
HW		 279
280 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
281
282 /* IRQ could occur when in initial stage */
1f6010a9 283 /* TODO work and BO cleanup */
4562236b
HW		 284 if (amdgpu_crtc == NULL) {
285 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
286 return;
287 }
288
289 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 290
291 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
292 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
293 amdgpu_crtc->pflip_status,
294 AMDGPU_FLIP_SUBMITTED,
295 amdgpu_crtc->crtc_id,
296 amdgpu_crtc);
297 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
298 return;
299 }
300
71bbe51a
MK		 301 /* page flip completed. */
302 e = amdgpu_crtc->event;
303 amdgpu_crtc->event = NULL;
4562236b 304
71bbe51a
MK		 305 if (!e)
306 WARN_ON(1);
1159898a 307
71bbe51a
MK		 308 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
309 vrr_active = amdgpu_dm_vrr_active(acrtc_state);
310
311 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
312 if (!vrr_active ||
313 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
314 &v_blank_end, &hpos, &vpos) ||
315 (vpos < v_blank_start)) {
316 /* Update to correct count and vblank timestamp if racing with
317 * vblank irq. This also updates to the correct vblank timestamp
318 * even in VRR mode, as scanout is past the front-porch atm.
319 */
320 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
1159898a 321
71bbe51a
MK		 322 /* Wake up userspace by sending the pageflip event with proper
323 * count and timestamp of vblank of flip completion.
324 */
325 if (e) {
326 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
327
328 /* Event sent, so done with vblank for this flip */
329 drm_crtc_vblank_put(&amdgpu_crtc->base);
330 }
331 } else if (e) {
332 /* VRR active and inside front-porch: vblank count and
333 * timestamp for pageflip event will only be up to date after
334 * drm_crtc_handle_vblank() has been executed from late vblank
335 * irq handler after start of back-porch (vline 0). We queue the
336 * pageflip event for send-out by drm_crtc_handle_vblank() with
337 * updated timestamp and count, once it runs after us.
338 *
339 * We need to open-code this instead of using the helper
340 * drm_crtc_arm_vblank_event(), as that helper would
341 * call drm_crtc_accurate_vblank_count(), which we must
342 * not call in VRR mode while we are in front-porch!
343 */
344
345 /* sequence will be replaced by real count during send-out. */
346 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
347 e->pipe = amdgpu_crtc->crtc_id;
348
349 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
350 e = NULL;
351 }
4562236b 352
fdd1fe57
MK		 353 /* Keep track of vblank of this flip for flip throttling. We use the
354 * cooked hw counter, as that one incremented at start of this vblank
355 * of pageflip completion, so last_flip_vblank is the forbidden count
356 * for queueing new pageflips if vsync + VRR is enabled.
357 */
358 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
359 amdgpu_crtc->crtc_id);
360
54f5499a 361 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 362 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
363
71bbe51a
MK		 364 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
365 amdgpu_crtc->crtc_id, amdgpu_crtc,
366 vrr_active, (int) !e);
4562236b
HW		 367}
368
d2574c33
MK		 369static void dm_vupdate_high_irq(void *interrupt_params)
370{
371 struct common_irq_params *irq_params = interrupt_params;
372 struct amdgpu_device *adev = irq_params->adev;
373 struct amdgpu_crtc *acrtc;
374 struct dm_crtc_state *acrtc_state;
09aef2c4 375 unsigned long flags;
d2574c33
MK		 376
377 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
378
379 if (acrtc) {
380 acrtc_state = to_dm_crtc_state(acrtc->base.state);
381
382 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
383 amdgpu_dm_vrr_active(acrtc_state));
384
385 /* Core vblank handling is done here after end of front-porch in
386 * vrr mode, as vblank timestamping will give valid results
387 * while now done after front-porch. This will also deliver
388 * page-flip completion events that have been queued to us
389 * if a pageflip happened inside front-porch.
390 */
09aef2c4 391 if (amdgpu_dm_vrr_active(acrtc_state)) {
d2574c33 392 drm_crtc_handle_vblank(&acrtc->base);
09aef2c4
MK		 393
394 /* BTR processing for pre-DCE12 ASICs */
395 if (acrtc_state->stream &&
396 adev->family < AMDGPU_FAMILY_AI) {
397 spin_lock_irqsave(&adev->ddev->event_lock, flags);
398 mod_freesync_handle_v_update(
399 adev->dm.freesync_module,
400 acrtc_state->stream,
401 &acrtc_state->vrr_params);
402
403 dc_stream_adjust_vmin_vmax(
404 adev->dm.dc,
405 acrtc_state->stream,
406 &acrtc_state->vrr_params.adjust);
407 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
408 }
409 }
d2574c33
MK		 410 }
411}
412
4562236b
HW		 413static void dm_crtc_high_irq(void *interrupt_params)
414{
415 struct common_irq_params *irq_params = interrupt_params;
416 struct amdgpu_device *adev = irq_params->adev;
4562236b 417 struct amdgpu_crtc *acrtc;
180db303 418 struct dm_crtc_state *acrtc_state;
09aef2c4 419 unsigned long flags;
4562236b 420
b57de80a 421 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 422
e5d0170e 423 if (acrtc) {
180db303
NK		 424 acrtc_state = to_dm_crtc_state(acrtc->base.state);
425
d2574c33
MK		 426 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
427 amdgpu_dm_vrr_active(acrtc_state));
428
429 /* Core vblank handling at start of front-porch is only possible
430 * in non-vrr mode, as only there vblank timestamping will give
431 * valid results while done in front-porch. Otherwise defer it
432 * to dm_vupdate_high_irq after end of front-porch.
433 */
434 if (!amdgpu_dm_vrr_active(acrtc_state))
435 drm_crtc_handle_vblank(&acrtc->base);
436
437 /* Following stuff must happen at start of vblank, for crc
438 * computation and below-the-range btr support in vrr mode.
439 */
440 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
441
09aef2c4 442 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
180db303
NK		 443 acrtc_state->vrr_params.supported &&
444 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
09aef2c4 445 spin_lock_irqsave(&adev->ddev->event_lock, flags);
180db303
NK		 446 mod_freesync_handle_v_update(
447 adev->dm.freesync_module,
448 acrtc_state->stream,
449 &acrtc_state->vrr_params);
450
451 dc_stream_adjust_vmin_vmax(
452 adev->dm.dc,
453 acrtc_state->stream,
454 &acrtc_state->vrr_params.adjust);
09aef2c4 455 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
180db303 456 }
e5d0170e 457 }
4562236b
HW		 458}
459
460static int dm_set_clockgating_state(void *handle,
461 enum amd_clockgating_state state)
462{
463 return 0;
464}
465
466static int dm_set_powergating_state(void *handle,
467 enum amd_powergating_state state)
468{
469 return 0;
470}
471
472/* Prototypes of private functions */
473static int dm_early_init(void* handle);
474
a32e24b4 475/* Allocate memory for FBC compressed data */
3e332d3a 476static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 477{
3e332d3a
RL		 478 struct drm_device *dev = connector->dev;
479 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 480 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 481 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
482 struct drm_display_mode *mode;
42e67c3b
RL		 483 unsigned long max_size = 0;
484
485 if (adev->dm.dc->fbc_compressor == NULL)
486 return;
a32e24b4 487
3e332d3a 488 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 489 return;
490
3e332d3a
RL		 491 if (compressor->bo_ptr)
492 return;
42e67c3b 493
42e67c3b 494
3e332d3a
RL		 495 list_for_each_entry(mode, &connector->modes, head) {
496 if (max_size < mode->htotal * mode->vtotal)
497 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 498 }
499
500 if (max_size) {
501 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 502 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 503 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 504
505 if (r)
42e67c3b
RL		 506 DRM_ERROR("DM: Failed to initialize FBC\n");
507 else {
508 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
509 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
510 }
511
a32e24b4
RL		 512 }
513
514}
a32e24b4 515
6ce8f316
NK		 516static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
517 int pipe, bool *enabled,
518 unsigned char *buf, int max_bytes)
519{
520 struct drm_device *dev = dev_get_drvdata(kdev);
521 struct amdgpu_device *adev = dev->dev_private;
522 struct drm_connector *connector;
523 struct drm_connector_list_iter conn_iter;
524 struct amdgpu_dm_connector *aconnector;
525 int ret = 0;
526
527 *enabled = false;
528
529 mutex_lock(&adev->dm.audio_lock);
530
531 drm_connector_list_iter_begin(dev, &conn_iter);
532 drm_for_each_connector_iter(connector, &conn_iter) {
533 aconnector = to_amdgpu_dm_connector(connector);
534 if (aconnector->audio_inst != port)
535 continue;
536
537 *enabled = true;
538 ret = drm_eld_size(connector->eld);
539 memcpy(buf, connector->eld, min(max_bytes, ret));
540
541 break;
542 }
543 drm_connector_list_iter_end(&conn_iter);
544
545 mutex_unlock(&adev->dm.audio_lock);
546
547 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
548
549 return ret;
550}
551
552static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
553 .get_eld = amdgpu_dm_audio_component_get_eld,
554};
555
556static int amdgpu_dm_audio_component_bind(struct device *kdev,
557 struct device *hda_kdev, void *data)
558{
559 struct drm_device *dev = dev_get_drvdata(kdev);
560 struct amdgpu_device *adev = dev->dev_private;
561 struct drm_audio_component *acomp = data;
562
563 acomp->ops = &amdgpu_dm_audio_component_ops;
564 acomp->dev = kdev;
565 adev->dm.audio_component = acomp;
566
567 return 0;
568}
569
570static void amdgpu_dm_audio_component_unbind(struct device *kdev,
571 struct device *hda_kdev, void *data)
572{
573 struct drm_device *dev = dev_get_drvdata(kdev);
574 struct amdgpu_device *adev = dev->dev_private;
575 struct drm_audio_component *acomp = data;
576
577 acomp->ops = NULL;
578 acomp->dev = NULL;
579 adev->dm.audio_component = NULL;
580}
581
582static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
583 .bind = amdgpu_dm_audio_component_bind,
584 .unbind = amdgpu_dm_audio_component_unbind,
585};
586
587static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
588{
589 int i, ret;
590
591 if (!amdgpu_audio)
592 return 0;
593
594 adev->mode_info.audio.enabled = true;
595
596 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
597
598 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
599 adev->mode_info.audio.pin[i].channels = -1;
600 adev->mode_info.audio.pin[i].rate = -1;
601 adev->mode_info.audio.pin[i].bits_per_sample = -1;
602 adev->mode_info.audio.pin[i].status_bits = 0;
603 adev->mode_info.audio.pin[i].category_code = 0;
604 adev->mode_info.audio.pin[i].connected = false;
605 adev->mode_info.audio.pin[i].id =
606 adev->dm.dc->res_pool->audios[i]->inst;
607 adev->mode_info.audio.pin[i].offset = 0;
608 }
609
610 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
611 if (ret < 0)
612 return ret;
613
614 adev->dm.audio_registered = true;
615
616 return 0;
617}
618
619static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
620{
621 if (!amdgpu_audio)
622 return;
623
624 if (!adev->mode_info.audio.enabled)
625 return;
626
627 if (adev->dm.audio_registered) {
628 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
629 adev->dm.audio_registered = false;
630 }
631
632 /* TODO: Disable audio? */
633
634 adev->mode_info.audio.enabled = false;
635}
636
637void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
638{
639 struct drm_audio_component *acomp = adev->dm.audio_component;
640
641 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
642 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
643
644 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
645 pin, -1);
646 }
647}
648
7578ecda 649static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 650{
651 struct dc_init_data init_data;
52704fca
BL		 652#ifdef CONFIG_DRM_AMD_DC_HDCP
653 struct dc_callback_init init_params;
654#endif
655
4562236b
HW		 656 adev->dm.ddev = adev->ddev;
657 adev->dm.adev = adev;
658
4562236b
HW		 659 /* Zero all the fields */
660 memset(&init_data, 0, sizeof(init_data));
52704fca
BL		 661#ifdef CONFIG_DRM_AMD_DC_HDCP
662 memset(&init_params, 0, sizeof(init_params));
663#endif
4562236b 664
674e78ac 665 mutex_init(&adev->dm.dc_lock);
6ce8f316 666 mutex_init(&adev->dm.audio_lock);
674e78ac 667
4562236b
HW		 668 if(amdgpu_dm_irq_init(adev)) {
669 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
670 goto error;
671 }
672
673 init_data.asic_id.chip_family = adev->family;
674
675 init_data.asic_id.pci_revision_id = adev->rev_id;
676 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
677
770d13b1 678 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 679 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
680 init_data.asic_id.atombios_base_address =
681 adev->mode_info.atom_context->bios;
682
683 init_data.driver = adev;
684
685 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
686
687 if (!adev->dm.cgs_device) {
688 DRM_ERROR("amdgpu: failed to create cgs device.\n");
689 goto error;
690 }
691
692 init_data.cgs_device = adev->dm.cgs_device;
693
4562236b
HW		 694 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
695
6e227308
HW		 696 /*
697 * TODO debug why this doesn't work on Raven
698 */
699 if (adev->flags & AMD_IS_APU &&
700 adev->asic_type >= CHIP_CARRIZO &&
1c425915 701 adev->asic_type <= CHIP_RAVEN)
6e227308
HW		 702 init_data.flags.gpu_vm_support = true;
703
04b94af4
AD		 704 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
705 init_data.flags.fbc_support = true;
706
d99f38ae
AD		 707 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
708 init_data.flags.multi_mon_pp_mclk_switch = true;
709
27eaa492 710 init_data.flags.power_down_display_on_boot = true;
78ad75f8 711
48321c3d
HW		 712#ifdef CONFIG_DRM_AMD_DC_DCN2_0
713 init_data.soc_bounding_box = adev->dm.soc_bounding_box;
714#endif
27eaa492 715
4562236b
HW		 716 /* Display Core create. */
717 adev->dm.dc = dc_create(&init_data);
718
423788c7 719 if (adev->dm.dc) {
76121231 720 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 721 } else {
76121231 722 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 723 goto error;
724 }
4562236b 725
98bf2f52
JP		 726 dc_hardware_init(adev->dm.dc);
727
4562236b
HW		 728 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
729 if (!adev->dm.freesync_module) {
730 DRM_ERROR(
731 "amdgpu: failed to initialize freesync_module.\n");
732 } else
f1ad2f5e 733 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 734 adev->dm.freesync_module);
735
e277adc5
LSL		 736 amdgpu_dm_init_color_mod();
737
52704fca
BL		 738#ifdef CONFIG_DRM_AMD_DC_HDCP
739 adev->dm.hdcp_workqueue = hdcp_create_workqueue(&adev->psp, &init_params.cp_psp, adev->dm.dc);
740
741 if (!adev->dm.hdcp_workqueue)
742 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
743 else
744 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
745
746 dc_init_callbacks(adev->dm.dc, &init_params);
747#endif
4562236b
HW		 748 if (amdgpu_dm_initialize_drm_device(adev)) {
749 DRM_ERROR(
750 "amdgpu: failed to initialize sw for display support.\n");
751 goto error;
752 }
753
754 /* Update the actual used number of crtc */
755 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
756
757 /* TODO: Add_display_info? */
758
759 /* TODO use dynamic cursor width */
ce75805e
AG		 760 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
761 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 762
763 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
764 DRM_ERROR(
765 "amdgpu: failed to initialize sw for display support.\n");
766 goto error;
767 }
768
e498eb71
NK		 769#if defined(CONFIG_DEBUG_FS)
770 if (dtn_debugfs_init(adev))
771 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
772#endif
773
f1ad2f5e 774 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 775
776 return 0;
777error:
778 amdgpu_dm_fini(adev);
779
59d0f396 780 return -EINVAL;
4562236b
HW		 781}
782
7578ecda 783static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b 784{
6ce8f316
NK		 785 amdgpu_dm_audio_fini(adev);
786
4562236b 787 amdgpu_dm_destroy_drm_device(&adev->dm);
c8bdf2b6 788
52704fca
BL		 789#ifdef CONFIG_DRM_AMD_DC_HDCP
790 if (adev->dm.hdcp_workqueue) {
791 hdcp_destroy(adev->dm.hdcp_workqueue);
792 adev->dm.hdcp_workqueue = NULL;
793 }
794
795 if (adev->dm.dc)
796 dc_deinit_callbacks(adev->dm.dc);
797#endif
798
c8bdf2b6
ED		 799 /* DC Destroy TODO: Replace destroy DAL */
800 if (adev->dm.dc)
801 dc_destroy(&adev->dm.dc);
4562236b
HW		 802 /*
803 * TODO: pageflip, vlank interrupt
804 *
805 * amdgpu_dm_irq_fini(adev);
806 */
807
808 if (adev->dm.cgs_device) {
809 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
810 adev->dm.cgs_device = NULL;
811 }
812 if (adev->dm.freesync_module) {
813 mod_freesync_destroy(adev->dm.freesync_module);
814 adev->dm.freesync_module = NULL;
815 }
674e78ac 816
6ce8f316 817 mutex_destroy(&adev->dm.audio_lock);
674e78ac
NK		 818 mutex_destroy(&adev->dm.dc_lock);
819
4562236b
HW		 820 return;
821}
822
a94d5569 823static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 824{
a7669aff 825 const char *fw_name_dmcu = NULL;
a94d5569
DF		 826 int r;
827 const struct dmcu_firmware_header_v1_0 *hdr;
828
829 switch(adev->asic_type) {
830 case CHIP_BONAIRE:
831 case CHIP_HAWAII:
832 case CHIP_KAVERI:
833 case CHIP_KABINI:
834 case CHIP_MULLINS:
835 case CHIP_TONGA:
836 case CHIP_FIJI:
837 case CHIP_CARRIZO:
838 case CHIP_STONEY:
839 case CHIP_POLARIS11:
840 case CHIP_POLARIS10:
841 case CHIP_POLARIS12:
842 case CHIP_VEGAM:
843 case CHIP_VEGA10:
844 case CHIP_VEGA12:
845 case CHIP_VEGA20:
476e955d 846 case CHIP_NAVI10:
baebcf2e 847 case CHIP_NAVI14:
fbd2afe5 848 case CHIP_NAVI12:
30221ad8 849 case CHIP_RENOIR:
a94d5569
DF		 850 return 0;
851 case CHIP_RAVEN:
a7669aff
HW		 852 if (ASICREV_IS_PICASSO(adev->external_rev_id))
853 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
854 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
855 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
856 else
a7669aff 857 return 0;
a94d5569
DF		 858 break;
859 default:
860 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 861 return -EINVAL;
a94d5569
DF		 862 }
863
864 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
865 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
866 return 0;
867 }
868
869 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
870 if (r == -ENOENT) {
871 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
872 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
873 adev->dm.fw_dmcu = NULL;
874 return 0;
875 }
876 if (r) {
877 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
878 fw_name_dmcu);
879 return r;
880 }
881
882 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
883 if (r) {
884 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
885 fw_name_dmcu);
886 release_firmware(adev->dm.fw_dmcu);
887 adev->dm.fw_dmcu = NULL;
888 return r;
889 }
890
891 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
892 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
893 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
894 adev->firmware.fw_size +=
895 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
896
897 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
898 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
899 adev->firmware.fw_size +=
900 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
901
ee6e89c0
DF		 902 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
903
a94d5569
DF		 904 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
905
4562236b
HW		 906 return 0;
907}
908
a94d5569
DF		 909static int dm_sw_init(void *handle)
910{
911 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
912
913 return load_dmcu_fw(adev);
914}
915
4562236b
HW		 916static int dm_sw_fini(void *handle)
917{
a94d5569
DF		 918 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
919
920 if(adev->dm.fw_dmcu) {
921 release_firmware(adev->dm.fw_dmcu);
922 adev->dm.fw_dmcu = NULL;
923 }
924
4562236b
HW		 925 return 0;
926}
927
7abcf6b5 928static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 929{
c84dec2f 930 struct amdgpu_dm_connector *aconnector;
4562236b 931 struct drm_connector *connector;
7abcf6b5 932 int ret = 0;
4562236b
HW		 933
934 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
935
936 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 937 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 938 if (aconnector->dc_link->type == dc_connection_mst_branch &&
939 aconnector->mst_mgr.aux) {
f1ad2f5e 940 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 941 aconnector, aconnector->base.base.id);
942
943 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
944 if (ret < 0) {
945 DRM_ERROR("DM_MST: Failed to start MST\n");
946 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
947 return ret;
4562236b 948 }
7abcf6b5 949 }
4562236b
HW		 950 }
951
952 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 953 return ret;
954}
955
956static int dm_late_init(void *handle)
957{
42e67c3b 958 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 959
bbf854dc
DF		 960 struct dmcu_iram_parameters params;
961 unsigned int linear_lut[16];
962 int i;
963 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
96cb7cf1 964 bool ret = false;
bbf854dc
DF		 965
966 for (i = 0; i < 16; i++)
967 linear_lut[i] = 0xFFFF * i / 15;
968
969 params.set = 0;
970 params.backlight_ramping_start = 0xCCCC;
971 params.backlight_ramping_reduction = 0xCCCCCCCC;
972 params.backlight_lut_array_size = 16;
973 params.backlight_lut_array = linear_lut;
974
2ad0cdf9
AK		 975 /* Min backlight level after ABM reduction, Don't allow below 1%
976 * 0xFFFF x 0.01 = 0x28F
977 */
978 params.min_abm_backlight = 0x28F;
979
96cb7cf1 980 /* todo will enable for navi10 */
981 if (adev->asic_type <= CHIP_RAVEN) {
982 ret = dmcu_load_iram(dmcu, params);
bbf854dc 983
96cb7cf1 984 if (!ret)
985 return -EINVAL;
986 }
bbf854dc 987
42e67c3b 988 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 989}
990
991static void s3_handle_mst(struct drm_device *dev, bool suspend)
992{
c84dec2f 993 struct amdgpu_dm_connector *aconnector;
4562236b 994 struct drm_connector *connector;
fe7553be
LP		 995 struct drm_dp_mst_topology_mgr *mgr;
996 int ret;
997 bool need_hotplug = false;
4562236b
HW		 998
999 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1000
fe7553be
LP		 1001 list_for_each_entry(connector, &dev->mode_config.connector_list,
1002 head) {
1003 aconnector = to_amdgpu_dm_connector(connector);
1004 if (aconnector->dc_link->type != dc_connection_mst_branch ||
1005 aconnector->mst_port)
1006 continue;
1007
1008 mgr = &aconnector->mst_mgr;
1009
1010 if (suspend) {
1011 drm_dp_mst_topology_mgr_suspend(mgr);
1012 } else {
1013 ret = drm_dp_mst_topology_mgr_resume(mgr);
1014 if (ret < 0) {
1015 drm_dp_mst_topology_mgr_set_mst(mgr, false);
1016 need_hotplug = true;
1017 }
1018 }
4562236b
HW		 1019 }
1020
1021 drm_modeset_unlock(&dev->mode_config.connection_mutex);
fe7553be
LP		 1022
1023 if (need_hotplug)
1024 drm_kms_helper_hotplug_event(dev);
4562236b
HW		 1025}
1026
b8592b48
LL		 1027/**
1028 * dm_hw_init() - Initialize DC device
1029 * @handle: The base driver device containing the amdpgu_dm device.
1030 *
1031 * Initialize the &struct amdgpu_display_manager device. This involves calling
1032 * the initializers of each DM component, then populating the struct with them.
1033 *
1034 * Although the function implies hardware initialization, both hardware and
1035 * software are initialized here. Splitting them out to their relevant init
1036 * hooks is a future TODO item.
1037 *
1038 * Some notable things that are initialized here:
1039 *
1040 * - Display Core, both software and hardware
1041 * - DC modules that we need (freesync and color management)
1042 * - DRM software states
1043 * - Interrupt sources and handlers
1044 * - Vblank support
1045 * - Debug FS entries, if enabled
1046 */
4562236b
HW		 1047static int dm_hw_init(void *handle)
1048{
1049 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050 /* Create DAL display manager */
1051 amdgpu_dm_init(adev);
4562236b
HW		 1052 amdgpu_dm_hpd_init(adev);
1053
4562236b
HW		 1054 return 0;
1055}
1056
b8592b48
LL		 1057/**
1058 * dm_hw_fini() - Teardown DC device
1059 * @handle: The base driver device containing the amdpgu_dm device.
1060 *
1061 * Teardown components within &struct amdgpu_display_manager that require
1062 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1063 * were loaded. Also flush IRQ workqueues and disable them.
1064 */
4562236b
HW		 1065static int dm_hw_fini(void *handle)
1066{
1067 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1068
1069 amdgpu_dm_hpd_fini(adev);
1070
1071 amdgpu_dm_irq_fini(adev);
21de3396 1072 amdgpu_dm_fini(adev);
4562236b
HW		 1073 return 0;
1074}
1075
1076static int dm_suspend(void *handle)
1077{
1078 struct amdgpu_device *adev = handle;
1079 struct amdgpu_display_manager *dm = &adev->dm;
1080 int ret = 0;
4562236b 1081
d2f0b53b
LHM		 1082 WARN_ON(adev->dm.cached_state);
1083 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
1084
4562236b
HW		 1085 s3_handle_mst(adev->ddev, true);
1086
4562236b
HW		 1087 amdgpu_dm_irq_suspend(adev);
1088
a3621485 1089
32f5062d 1090 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 1091
1092 return ret;
1093}
1094
1daf8c63
AD		 1095static struct amdgpu_dm_connector *
1096amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1097 struct drm_crtc *crtc)
4562236b
HW		 1098{
1099 uint32_t i;
c2cea706 1100 struct drm_connector_state *new_con_state;
4562236b
HW		 1101 struct drm_connector *connector;
1102 struct drm_crtc *crtc_from_state;
1103
c2cea706
LSL		 1104 for_each_new_connector_in_state(state, connector, new_con_state, i) {
1105 crtc_from_state = new_con_state->crtc;
4562236b
HW		 1106
1107 if (crtc_from_state == crtc)
c84dec2f 1108 return to_amdgpu_dm_connector(connector);
4562236b
HW		 1109 }
1110
1111 return NULL;
1112}
1113
fbbdadf2
BL		 1114static void emulated_link_detect(struct dc_link *link)
1115{
1116 struct dc_sink_init_data sink_init_data = { 0 };
1117 struct display_sink_capability sink_caps = { 0 };
1118 enum dc_edid_status edid_status;
1119 struct dc_context *dc_ctx = link->ctx;
1120 struct dc_sink *sink = NULL;
1121 struct dc_sink *prev_sink = NULL;
1122
1123 link->type = dc_connection_none;
1124 prev_sink = link->local_sink;
1125
1126 if (prev_sink != NULL)
1127 dc_sink_retain(prev_sink);
1128
1129 switch (link->connector_signal) {
1130 case SIGNAL_TYPE_HDMI_TYPE_A: {
1131 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1132 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1133 break;
1134 }
1135
1136 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1137 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1138 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1139 break;
1140 }
1141
1142 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1143 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1144 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1145 break;
1146 }
1147
1148 case SIGNAL_TYPE_LVDS: {
1149 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1150 sink_caps.signal = SIGNAL_TYPE_LVDS;
1151 break;
1152 }
1153
1154 case SIGNAL_TYPE_EDP: {
1155 sink_caps.transaction_type =
1156 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1157 sink_caps.signal = SIGNAL_TYPE_EDP;
1158 break;
1159 }
1160
1161 case SIGNAL_TYPE_DISPLAY_PORT: {
1162 sink_caps.transaction_type =
1163 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1164 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1165 break;
1166 }
1167
1168 default:
1169 DC_ERROR("Invalid connector type! signal:%d\n",
1170 link->connector_signal);
1171 return;
1172 }
1173
1174 sink_init_data.link = link;
1175 sink_init_data.sink_signal = sink_caps.signal;
1176
1177 sink = dc_sink_create(&sink_init_data);
1178 if (!sink) {
1179 DC_ERROR("Failed to create sink!\n");
1180 return;
1181 }
1182
dcd5fb82 1183 /* dc_sink_create returns a new reference */
fbbdadf2
BL		 1184 link->local_sink = sink;
1185
1186 edid_status = dm_helpers_read_local_edid(
1187 link->ctx,
1188 link,
1189 sink);
1190
1191 if (edid_status != EDID_OK)
1192 DC_ERROR("Failed to read EDID");
1193
1194}
1195
4562236b
HW		 1196static int dm_resume(void *handle)
1197{
1198 struct amdgpu_device *adev = handle;
4562236b
HW		 1199 struct drm_device *ddev = adev->ddev;
1200 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 1201 struct amdgpu_dm_connector *aconnector;
4562236b 1202 struct drm_connector *connector;
4562236b 1203 struct drm_crtc *crtc;
c2cea706 1204 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 1205 struct dm_crtc_state *dm_new_crtc_state;
1206 struct drm_plane *plane;
1207 struct drm_plane_state *new_plane_state;
1208 struct dm_plane_state *dm_new_plane_state;
113b7a01 1209 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
fbbdadf2 1210 enum dc_connection_type new_connection_type = dc_connection_none;
a3621485 1211 int i;
4562236b 1212
113b7a01
LL		 1213 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1214 dc_release_state(dm_state->context);
1215 dm_state->context = dc_create_state(dm->dc);
1216 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1217 dc_resource_state_construct(dm->dc, dm_state->context);
1218
a80aa93d
ML		 1219 /* power on hardware */
1220 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1221
4562236b
HW		 1222 /* program HPD filter */
1223 dc_resume(dm->dc);
1224
1225 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
1226 s3_handle_mst(ddev, false);
1227
1228 /*
1229 * early enable HPD Rx IRQ, should be done before set mode as short
1230 * pulse interrupts are used for MST
1231 */
1232 amdgpu_dm_irq_resume_early(adev);
1233
4562236b 1234 /* Do detection*/
a80aa93d 1235 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 1236 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1237
1238 /*
1239 * this is the case when traversing through already created
1240 * MST connectors, should be skipped
1241 */
1242 if (aconnector->mst_port)
1243 continue;
1244
03ea364c 1245 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 1246 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1247 DRM_ERROR("KMS: Failed to detect connector\n");
1248
1249 if (aconnector->base.force && new_connection_type == dc_connection_none)
1250 emulated_link_detect(aconnector->dc_link);
1251 else
1252 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 1253
1254 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1255 aconnector->fake_enable = false;
1256
dcd5fb82
MF		 1257 if (aconnector->dc_sink)
1258 dc_sink_release(aconnector->dc_sink);
4562236b
HW		 1259 aconnector->dc_sink = NULL;
1260 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 1261 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 1262 }
1263
1f6010a9 1264 /* Force mode set in atomic commit */
a80aa93d 1265 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 1266 new_crtc_state->active_changed = true;
4f346e65 1267
fcb4019e
LSL		 1268 /*
1269 * atomic_check is expected to create the dc states. We need to release
1270 * them here, since they were duplicated as part of the suspend
1271 * procedure.
1272 */
a80aa93d 1273 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 1274 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1275 if (dm_new_crtc_state->stream) {
1276 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1277 dc_stream_release(dm_new_crtc_state->stream);
1278 dm_new_crtc_state->stream = NULL;
1279 }
1280 }
1281
a80aa93d 1282 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 1283 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1284 if (dm_new_plane_state->dc_state) {
1285 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1286 dc_plane_state_release(dm_new_plane_state->dc_state);
1287 dm_new_plane_state->dc_state = NULL;
1288 }
1289 }
1290
2d1af6a1 1291 drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 1292
a80aa93d 1293 dm->cached_state = NULL;
0a214e2f 1294
9faa4237 1295 amdgpu_dm_irq_resume_late(adev);
4562236b 1296
2d1af6a1 1297 return 0;
4562236b
HW		 1298}
1299
b8592b48
LL		 1300/**
1301 * DOC: DM Lifecycle
1302 *
1303 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1304 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1305 * the base driver's device list to be initialized and torn down accordingly.
1306 *
1307 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1308 */
1309
4562236b
HW		 1310static const struct amd_ip_funcs amdgpu_dm_funcs = {
1311 .name = "dm",
1312 .early_init = dm_early_init,
7abcf6b5 1313 .late_init = dm_late_init,
4562236b
HW		 1314 .sw_init = dm_sw_init,
1315 .sw_fini = dm_sw_fini,
1316 .hw_init = dm_hw_init,
1317 .hw_fini = dm_hw_fini,
1318 .suspend = dm_suspend,
1319 .resume = dm_resume,
1320 .is_idle = dm_is_idle,
1321 .wait_for_idle = dm_wait_for_idle,
1322 .check_soft_reset = dm_check_soft_reset,
1323 .soft_reset = dm_soft_reset,
1324 .set_clockgating_state = dm_set_clockgating_state,
1325 .set_powergating_state = dm_set_powergating_state,
1326};
1327
1328const struct amdgpu_ip_block_version dm_ip_block =
1329{
1330 .type = AMD_IP_BLOCK_TYPE_DCE,
1331 .major = 1,
1332 .minor = 0,
1333 .rev = 0,
1334 .funcs = &amdgpu_dm_funcs,
1335};
1336
ca3268c4 1337
b8592b48
LL		 1338/**
1339 * DOC: atomic
1340 *
1341 * *WIP*
1342 */
0a323b84 1343
b3663f70 1344static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 1345 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 1346 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 1347 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 1348 .atomic_commit = amdgpu_dm_atomic_commit,
54f5499a
AG		 1349};
1350
1351static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1352 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 1353};
1354
7578ecda 1355static void
3ee6b26b 1356amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1357{
1358 struct drm_connector *connector = &aconnector->base;
1359 struct drm_device *dev = connector->dev;
b73a22d3 1360 struct dc_sink *sink;
4562236b
HW		 1361
1362 /* MST handled by drm_mst framework */
1363 if (aconnector->mst_mgr.mst_state == true)
1364 return;
1365
1366
1367 sink = aconnector->dc_link->local_sink;
dcd5fb82
MF		 1368 if (sink)
1369 dc_sink_retain(sink);
4562236b 1370
1f6010a9
DF		 1371 /*
1372 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 1373 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 1374 * Skip if already done during boot.
4562236b
HW		 1375 */
1376 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1377 && aconnector->dc_em_sink) {
1378
1f6010a9
DF		 1379 /*
1380 * For S3 resume with headless use eml_sink to fake stream
1381 * because on resume connector->sink is set to NULL
4562236b
HW		 1382 */
1383 mutex_lock(&dev->mode_config.mutex);
1384
1385 if (sink) {
922aa1e1 1386 if (aconnector->dc_sink) {
98e6436d 1387 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 1388 /*
1389 * retain and release below are used to
1390 * bump up refcount for sink because the link doesn't point
1391 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 1392 * reshuffle by UMD we will get into unwanted dc_sink release
1393 */
dcd5fb82 1394 dc_sink_release(aconnector->dc_sink);
922aa1e1 1395 }
4562236b 1396 aconnector->dc_sink = sink;
dcd5fb82 1397 dc_sink_retain(aconnector->dc_sink);
98e6436d
AK		 1398 amdgpu_dm_update_freesync_caps(connector,
1399 aconnector->edid);
4562236b 1400 } else {
98e6436d 1401 amdgpu_dm_update_freesync_caps(connector, NULL);
dcd5fb82 1402 if (!aconnector->dc_sink) {
4562236b 1403 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1 1404 dc_sink_retain(aconnector->dc_sink);
dcd5fb82 1405 }
4562236b
HW		 1406 }
1407
1408 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1409
1410 if (sink)
1411 dc_sink_release(sink);
4562236b
HW		 1412 return;
1413 }
1414
1415 /*
1416 * TODO: temporary guard to look for proper fix
1417 * if this sink is MST sink, we should not do anything
1418 */
dcd5fb82
MF		 1419 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1420 dc_sink_release(sink);
4562236b 1421 return;
dcd5fb82 1422 }
4562236b
HW		 1423
1424 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 1425 /*
1426 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1427 * Do nothing!!
1428 */
f1ad2f5e 1429 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b 1430 aconnector->connector_id);
dcd5fb82
MF		 1431 if (sink)
1432 dc_sink_release(sink);
4562236b
HW		 1433 return;
1434 }
1435
f1ad2f5e 1436 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 1437 aconnector->connector_id, aconnector->dc_sink, sink);
1438
1439 mutex_lock(&dev->mode_config.mutex);
1440
1f6010a9
DF		 1441 /*
1442 * 1. Update status of the drm connector
1443 * 2. Send an event and let userspace tell us what to do
1444 */
4562236b 1445 if (sink) {
1f6010a9
DF		 1446 /*
1447 * TODO: check if we still need the S3 mode update workaround.
1448 * If yes, put it here.
1449 */
4562236b 1450 if (aconnector->dc_sink)
98e6436d 1451 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1452
1453 aconnector->dc_sink = sink;
dcd5fb82 1454 dc_sink_retain(aconnector->dc_sink);
900b3cb1 1455 if (sink->dc_edid.length == 0) {
4562236b 1456 aconnector->edid = NULL;
e86e8947 1457 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 1458 } else {
4562236b
HW		 1459 aconnector->edid =
1460 (struct edid *) sink->dc_edid.raw_edid;
1461
1462
c555f023 1463 drm_connector_update_edid_property(connector,
4562236b 1464 aconnector->edid);
e86e8947
HV		 1465 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1466 aconnector->edid);
4562236b 1467 }
98e6436d 1468 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 1469
1470 } else {
e86e8947 1471 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 1472 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 1473 drm_connector_update_edid_property(connector, NULL);
4562236b 1474 aconnector->num_modes = 0;
dcd5fb82 1475 dc_sink_release(aconnector->dc_sink);
4562236b 1476 aconnector->dc_sink = NULL;
5326c452 1477 aconnector->edid = NULL;
4562236b
HW		 1478 }
1479
1480 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1481
1482 if (sink)
1483 dc_sink_release(sink);
4562236b
HW		 1484}
1485
1486static void handle_hpd_irq(void *param)
1487{
c84dec2f 1488 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1489 struct drm_connector *connector = &aconnector->base;
1490 struct drm_device *dev = connector->dev;
fbbdadf2 1491 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1492
1f6010a9
DF		 1493 /*
1494 * In case of failure or MST no need to update connector status or notify the OS
1495 * since (for MST case) MST does this in its own context.
4562236b
HW		 1496 */
1497 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 1498
1499 if (aconnector->fake_enable)
1500 aconnector->fake_enable = false;
1501
fbbdadf2
BL		 1502 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1503 DRM_ERROR("KMS: Failed to detect connector\n");
1504
1505 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1506 emulated_link_detect(aconnector->dc_link);
1507
1508
1509 drm_modeset_lock_all(dev);
1510 dm_restore_drm_connector_state(dev, connector);
1511 drm_modeset_unlock_all(dev);
1512
1513 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1514 drm_kms_helper_hotplug_event(dev);
1515
1516 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1517 amdgpu_dm_update_connector_after_detect(aconnector);
1518
1519
1520 drm_modeset_lock_all(dev);
1521 dm_restore_drm_connector_state(dev, connector);
1522 drm_modeset_unlock_all(dev);
1523
1524 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1525 drm_kms_helper_hotplug_event(dev);
1526 }
1527 mutex_unlock(&aconnector->hpd_lock);
1528
1529}
1530
c84dec2f 1531static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1532{
1533 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1534 uint8_t dret;
1535 bool new_irq_handled = false;
1536 int dpcd_addr;
1537 int dpcd_bytes_to_read;
1538
1539 const int max_process_count = 30;
1540 int process_count = 0;
1541
1542 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1543
1544 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1545 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1546 /* DPCD 0x200 - 0x201 for downstream IRQ */
1547 dpcd_addr = DP_SINK_COUNT;
1548 } else {
1549 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1550 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1551 dpcd_addr = DP_SINK_COUNT_ESI;
1552 }
1553
1554 dret = drm_dp_dpcd_read(
1555 &aconnector->dm_dp_aux.aux,
1556 dpcd_addr,
1557 esi,
1558 dpcd_bytes_to_read);
1559
1560 while (dret == dpcd_bytes_to_read &&
1561 process_count < max_process_count) {
1562 uint8_t retry;
1563 dret = 0;
1564
1565 process_count++;
1566
f1ad2f5e 1567 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1568 /* handle HPD short pulse irq */
1569 if (aconnector->mst_mgr.mst_state)
1570 drm_dp_mst_hpd_irq(
1571 &aconnector->mst_mgr,
1572 esi,
1573 &new_irq_handled);
4562236b
HW		 1574
1575 if (new_irq_handled) {
1576 /* ACK at DPCD to notify down stream */
1577 const int ack_dpcd_bytes_to_write =
1578 dpcd_bytes_to_read - 1;
1579
1580 for (retry = 0; retry < 3; retry++) {
1581 uint8_t wret;
1582
1583 wret = drm_dp_dpcd_write(
1584 &aconnector->dm_dp_aux.aux,
1585 dpcd_addr + 1,
1586 &esi[1],
1587 ack_dpcd_bytes_to_write);
1588 if (wret == ack_dpcd_bytes_to_write)
1589 break;
1590 }
1591
1f6010a9 1592 /* check if there is new irq to be handled */
4562236b
HW		 1593 dret = drm_dp_dpcd_read(
1594 &aconnector->dm_dp_aux.aux,
1595 dpcd_addr,
1596 esi,
1597 dpcd_bytes_to_read);
1598
1599 new_irq_handled = false;
d4a6e8a9 1600 } else {
4562236b 1601 break;
d4a6e8a9 1602 }
4562236b
HW		 1603 }
1604
1605 if (process_count == max_process_count)
f1ad2f5e 1606 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1607}
1608
1609static void handle_hpd_rx_irq(void *param)
1610{
c84dec2f 1611 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1612 struct drm_connector *connector = &aconnector->base;
1613 struct drm_device *dev = connector->dev;
53cbf65c 1614 struct dc_link *dc_link = aconnector->dc_link;
4562236b 1615 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
fbbdadf2 1616 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1617
1f6010a9
DF		 1618 /*
1619 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 1620 * conflict, after implement i2c helper, this mutex should be
1621 * retired.
1622 */
53cbf65c 1623 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1624 mutex_lock(&aconnector->hpd_lock);
1625
4e18814e 1626 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1627 !is_mst_root_connector) {
1628 /* Downstream Port status changed. */
fbbdadf2
BL		 1629 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1630 DRM_ERROR("KMS: Failed to detect connector\n");
1631
1632 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1633 emulated_link_detect(dc_link);
1634
1635 if (aconnector->fake_enable)
1636 aconnector->fake_enable = false;
1637
1638 amdgpu_dm_update_connector_after_detect(aconnector);
1639
1640
1641 drm_modeset_lock_all(dev);
1642 dm_restore_drm_connector_state(dev, connector);
1643 drm_modeset_unlock_all(dev);
1644
1645 drm_kms_helper_hotplug_event(dev);
1646 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1647
1648 if (aconnector->fake_enable)
1649 aconnector->fake_enable = false;
1650
4562236b
HW		 1651 amdgpu_dm_update_connector_after_detect(aconnector);
1652
1653
1654 drm_modeset_lock_all(dev);
1655 dm_restore_drm_connector_state(dev, connector);
1656 drm_modeset_unlock_all(dev);
1657
1658 drm_kms_helper_hotplug_event(dev);
1659 }
1660 }
1661 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1662 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1663 dm_handle_hpd_rx_irq(aconnector);
1664
e86e8947
HV		 1665 if (dc_link->type != dc_connection_mst_branch) {
1666 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 1667 mutex_unlock(&aconnector->hpd_lock);
e86e8947 1668 }
4562236b
HW		 1669}
1670
1671static void register_hpd_handlers(struct amdgpu_device *adev)
1672{
1673 struct drm_device *dev = adev->ddev;
1674 struct drm_connector *connector;
c84dec2f 1675 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1676 const struct dc_link *dc_link;
1677 struct dc_interrupt_params int_params = {0};
1678
1679 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1680 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1681
1682 list_for_each_entry(connector,
1683 &dev->mode_config.connector_list, head) {
1684
c84dec2f 1685 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1686 dc_link = aconnector->dc_link;
1687
1688 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1689 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1690 int_params.irq_source = dc_link->irq_source_hpd;
1691
1692 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1693 handle_hpd_irq,
1694 (void *) aconnector);
1695 }
1696
1697 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1698
1699 /* Also register for DP short pulse (hpd_rx). */
1700 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1701 int_params.irq_source = dc_link->irq_source_hpd_rx;
1702
1703 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1704 handle_hpd_rx_irq,
1705 (void *) aconnector);
1706 }
1707 }
1708}
1709
1710/* Register IRQ sources and initialize IRQ callbacks */
1711static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1712{
1713 struct dc *dc = adev->dm.dc;
1714 struct common_irq_params *c_irq_params;
1715 struct dc_interrupt_params int_params = {0};
1716 int r;
1717 int i;
1ffdeca6 1718 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 1719
84374725 1720 if (adev->asic_type >= CHIP_VEGA10)
3760f76c 1721 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1722
1723 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1724 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1725
1f6010a9
DF		 1726 /*
1727 * Actions of amdgpu_irq_add_id():
4562236b
HW		 1728 * 1. Register a set() function with base driver.
1729 * Base driver will call set() function to enable/disable an
1730 * interrupt in DC hardware.
1731 * 2. Register amdgpu_dm_irq_handler().
1732 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1733 * coming from DC hardware.
1734 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1735 * for acknowledging and handling. */
1736
b57de80a 1737 /* Use VBLANK interrupt */
e9029155 1738 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1739 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1740 if (r) {
1741 DRM_ERROR("Failed to add crtc irq id!\n");
1742 return r;
1743 }
1744
1745 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1746 int_params.irq_source =
3d761e79 1747 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1748
b57de80a 1749 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1750
1751 c_irq_params->adev = adev;
1752 c_irq_params->irq_src = int_params.irq_source;
1753
1754 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1755 dm_crtc_high_irq, c_irq_params);
1756 }
1757
d2574c33
MK		 1758 /* Use VUPDATE interrupt */
1759 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
1760 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
1761 if (r) {
1762 DRM_ERROR("Failed to add vupdate irq id!\n");
1763 return r;
1764 }
1765
1766 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1767 int_params.irq_source =
1768 dc_interrupt_to_irq_source(dc, i, 0);
1769
1770 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1771
1772 c_irq_params->adev = adev;
1773 c_irq_params->irq_src = int_params.irq_source;
1774
1775 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1776 dm_vupdate_high_irq, c_irq_params);
1777 }
1778
3d761e79 1779 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1780 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1781 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1782 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1783 if (r) {
1784 DRM_ERROR("Failed to add page flip irq id!\n");
1785 return r;
1786 }
1787
1788 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1789 int_params.irq_source =
1790 dc_interrupt_to_irq_source(dc, i, 0);
1791
1792 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1793
1794 c_irq_params->adev = adev;
1795 c_irq_params->irq_src = int_params.irq_source;
1796
1797 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1798 dm_pflip_high_irq, c_irq_params);
1799
1800 }
1801
1802 /* HPD */
2c8ad2d5
AD		 1803 r = amdgpu_irq_add_id(adev, client_id,
1804 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1805 if (r) {
1806 DRM_ERROR("Failed to add hpd irq id!\n");
1807 return r;
1808 }
1809
1810 register_hpd_handlers(adev);
1811
1812 return 0;
1813}
1814
ff5ef992
AD		 1815#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1816/* Register IRQ sources and initialize IRQ callbacks */
1817static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1818{
1819 struct dc *dc = adev->dm.dc;
1820 struct common_irq_params *c_irq_params;
1821 struct dc_interrupt_params int_params = {0};
1822 int r;
1823 int i;
1824
1825 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1826 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1827
1f6010a9
DF		 1828 /*
1829 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 1830 * 1. Register a set() function with base driver.
1831 * Base driver will call set() function to enable/disable an
1832 * interrupt in DC hardware.
1833 * 2. Register amdgpu_dm_irq_handler().
1834 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1835 * coming from DC hardware.
1836 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1837 * for acknowledging and handling.
1f6010a9 1838 */
ff5ef992
AD		 1839
1840 /* Use VSTARTUP interrupt */
1841 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1842 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1843 i++) {
3760f76c 1844 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1845
1846 if (r) {
1847 DRM_ERROR("Failed to add crtc irq id!\n");
1848 return r;
1849 }
1850
1851 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1852 int_params.irq_source =
1853 dc_interrupt_to_irq_source(dc, i, 0);
1854
1855 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1856
1857 c_irq_params->adev = adev;
1858 c_irq_params->irq_src = int_params.irq_source;
1859
1860 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1861 dm_crtc_high_irq, c_irq_params);
1862 }
1863
d2574c33
MK		 1864 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
1865 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
1866 * to trigger at end of each vblank, regardless of state of the lock,
1867 * matching DCE behaviour.
1868 */
1869 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
1870 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
1871 i++) {
1872 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
1873
1874 if (r) {
1875 DRM_ERROR("Failed to add vupdate irq id!\n");
1876 return r;
1877 }
1878
1879 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1880 int_params.irq_source =
1881 dc_interrupt_to_irq_source(dc, i, 0);
1882
1883 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1884
1885 c_irq_params->adev = adev;
1886 c_irq_params->irq_src = int_params.irq_source;
1887
1888 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1889 dm_vupdate_high_irq, c_irq_params);
1890 }
1891
ff5ef992
AD		 1892 /* Use GRPH_PFLIP interrupt */
1893 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1894 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1895 i++) {
3760f76c 1896 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1897 if (r) {
1898 DRM_ERROR("Failed to add page flip irq id!\n");
1899 return r;
1900 }
1901
1902 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1903 int_params.irq_source =
1904 dc_interrupt_to_irq_source(dc, i, 0);
1905
1906 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1907
1908 c_irq_params->adev = adev;
1909 c_irq_params->irq_src = int_params.irq_source;
1910
1911 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1912 dm_pflip_high_irq, c_irq_params);
1913
1914 }
1915
1916 /* HPD */
3760f76c 1917 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1918 &adev->hpd_irq);
1919 if (r) {
1920 DRM_ERROR("Failed to add hpd irq id!\n");
1921 return r;
1922 }
1923
1924 register_hpd_handlers(adev);
1925
1926 return 0;
1927}
1928#endif
1929
eb3dc897
NK		 1930/*
1931 * Acquires the lock for the atomic state object and returns
1932 * the new atomic state.
1933 *
1934 * This should only be called during atomic check.
1935 */
1936static int dm_atomic_get_state(struct drm_atomic_state *state,
1937 struct dm_atomic_state **dm_state)
1938{
1939 struct drm_device *dev = state->dev;
1940 struct amdgpu_device *adev = dev->dev_private;
1941 struct amdgpu_display_manager *dm = &adev->dm;
1942 struct drm_private_state *priv_state;
eb3dc897
NK		 1943
1944 if (*dm_state)
1945 return 0;
1946
eb3dc897
NK		 1947 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1948 if (IS_ERR(priv_state))
1949 return PTR_ERR(priv_state);
1950
1951 *dm_state = to_dm_atomic_state(priv_state);
1952
1953 return 0;
1954}
1955
1956struct dm_atomic_state *
1957dm_atomic_get_new_state(struct drm_atomic_state *state)
1958{
1959 struct drm_device *dev = state->dev;
1960 struct amdgpu_device *adev = dev->dev_private;
1961 struct amdgpu_display_manager *dm = &adev->dm;
1962 struct drm_private_obj *obj;
1963 struct drm_private_state *new_obj_state;
1964 int i;
1965
1966 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1967 if (obj->funcs == dm->atomic_obj.funcs)
1968 return to_dm_atomic_state(new_obj_state);
1969 }
1970
1971 return NULL;
1972}
1973
1974struct dm_atomic_state *
1975dm_atomic_get_old_state(struct drm_atomic_state *state)
1976{
1977 struct drm_device *dev = state->dev;
1978 struct amdgpu_device *adev = dev->dev_private;
1979 struct amdgpu_display_manager *dm = &adev->dm;
1980 struct drm_private_obj *obj;
1981 struct drm_private_state *old_obj_state;
1982 int i;
1983
1984 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1985 if (obj->funcs == dm->atomic_obj.funcs)
1986 return to_dm_atomic_state(old_obj_state);
1987 }
1988
1989 return NULL;
1990}
1991
1992static struct drm_private_state *
1993dm_atomic_duplicate_state(struct drm_private_obj *obj)
1994{
1995 struct dm_atomic_state *old_state, *new_state;
1996
1997 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1998 if (!new_state)
1999 return NULL;
2000
2001 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
2002
813d20dc
AW		 2003 old_state = to_dm_atomic_state(obj->state);
2004
2005 if (old_state && old_state->context)
2006 new_state->context = dc_copy_state(old_state->context);
2007
eb3dc897
NK		 2008 if (!new_state->context) {
2009 kfree(new_state);
2010 return NULL;
2011 }
2012
eb3dc897
NK		 2013 return &new_state->base;
2014}
2015
2016static void dm_atomic_destroy_state(struct drm_private_obj *obj,
2017 struct drm_private_state *state)
2018{
2019 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
2020
2021 if (dm_state && dm_state->context)
2022 dc_release_state(dm_state->context);
2023
2024 kfree(dm_state);
2025}
2026
2027static struct drm_private_state_funcs dm_atomic_state_funcs = {
2028 .atomic_duplicate_state = dm_atomic_duplicate_state,
2029 .atomic_destroy_state = dm_atomic_destroy_state,
2030};
2031
4562236b
HW		 2032static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
2033{
eb3dc897 2034 struct dm_atomic_state *state;
4562236b
HW		 2035 int r;
2036
2037 adev->mode_info.mode_config_initialized = true;
2038
4562236b 2039 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 2040 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 2041
2042 adev->ddev->mode_config.max_width = 16384;
2043 adev->ddev->mode_config.max_height = 16384;
2044
2045 adev->ddev->mode_config.preferred_depth = 24;
2046 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 2047 /* indicates support for immediate flip */
4562236b
HW		 2048 adev->ddev->mode_config.async_page_flip = true;
2049
770d13b1 2050 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 2051
eb3dc897
NK		 2052 state = kzalloc(sizeof(*state), GFP_KERNEL);
2053 if (!state)
2054 return -ENOMEM;
2055
813d20dc 2056 state->context = dc_create_state(adev->dm.dc);
eb3dc897
NK		 2057 if (!state->context) {
2058 kfree(state);
2059 return -ENOMEM;
2060 }
2061
2062 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
2063
8c1a765b
DA		 2064 drm_atomic_private_obj_init(adev->ddev,
2065 &adev->dm.atomic_obj,
eb3dc897
NK		 2066 &state->base,
2067 &dm_atomic_state_funcs);
2068
3dc9b1ce 2069 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 2070 if (r)
2071 return r;
2072
6ce8f316
NK		 2073 r = amdgpu_dm_audio_init(adev);
2074 if (r)
2075 return r;
2076
4562236b
HW		 2077 return 0;
2078}
2079
206bbafe
DF		 2080#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
2081#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2082
4562236b
HW		 2083#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2084 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2085
206bbafe
DF		 2086static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
2087{
2088#if defined(CONFIG_ACPI)
2089 struct amdgpu_dm_backlight_caps caps;
2090
2091 if (dm->backlight_caps.caps_valid)
2092 return;
2093
2094 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
2095 if (caps.caps_valid) {
2096 dm->backlight_caps.min_input_signal = caps.min_input_signal;
2097 dm->backlight_caps.max_input_signal = caps.max_input_signal;
2098 dm->backlight_caps.caps_valid = true;
2099 } else {
2100 dm->backlight_caps.min_input_signal =
2101 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2102 dm->backlight_caps.max_input_signal =
2103 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2104 }
2105#else
8bcbc9ef
DF		 2106 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2107 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 2108#endif
2109}
2110
4562236b
HW		 2111static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
2112{
2113 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe
DF		 2114 struct amdgpu_dm_backlight_caps caps;
2115 uint32_t brightness = bd->props.brightness;
4562236b 2116
206bbafe
DF		 2117 amdgpu_dm_update_backlight_caps(dm);
2118 caps = dm->backlight_caps;
0cafc82f 2119 /*
206bbafe
DF		 2120 * The brightness input is in the range 0-255
2121 * It needs to be rescaled to be between the
2122 * requested min and max input signal
2123 *
2124 * It also needs to be scaled up by 0x101 to
2125 * match the DC interface which has a range of
2126 * 0 to 0xffff
0cafc82f 2127 */
206bbafe
DF		 2128 brightness =
2129 brightness
2130 * 0x101
2131 * (caps.max_input_signal - caps.min_input_signal)
2132 / AMDGPU_MAX_BL_LEVEL
2133 + caps.min_input_signal * 0x101;
4562236b
HW		 2134
2135 if (dc_link_set_backlight_level(dm->backlight_link,
923fe495 2136 brightness, 0))
4562236b
HW		 2137 return 0;
2138 else
2139 return 1;
2140}
2141
2142static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
2143{
620a0d27
DF		 2144 struct amdgpu_display_manager *dm = bl_get_data(bd);
2145 int ret = dc_link_get_backlight_level(dm->backlight_link);
2146
2147 if (ret == DC_ERROR_UNEXPECTED)
2148 return bd->props.brightness;
2149 return ret;
4562236b
HW		 2150}
2151
2152static const struct backlight_ops amdgpu_dm_backlight_ops = {
2153 .get_brightness = amdgpu_dm_backlight_get_brightness,
2154 .update_status = amdgpu_dm_backlight_update_status,
2155};
2156
7578ecda
AD		 2157static void
2158amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2159{
2160 char bl_name[16];
2161 struct backlight_properties props = { 0 };
2162
206bbafe
DF		 2163 amdgpu_dm_update_backlight_caps(dm);
2164
4562236b 2165 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 2166 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 2167 props.type = BACKLIGHT_RAW;
2168
2169 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
2170 dm->adev->ddev->primary->index);
2171
2172 dm->backlight_dev = backlight_device_register(bl_name,
2173 dm->adev->ddev->dev,
2174 dm,
2175 &amdgpu_dm_backlight_ops,
2176 &props);
2177
74baea42 2178 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 2179 DRM_ERROR("DM: Backlight registration failed!\n");
2180 else
f1ad2f5e 2181 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 2182}
2183
2184#endif
2185
df534fff 2186static int initialize_plane(struct amdgpu_display_manager *dm,
b2fddb13 2187 struct amdgpu_mode_info *mode_info, int plane_id,
cc1fec57
NK		 2188 enum drm_plane_type plane_type,
2189 const struct dc_plane_cap *plane_cap)
df534fff 2190{
f180b4bc 2191 struct drm_plane *plane;
df534fff
S		 2192 unsigned long possible_crtcs;
2193 int ret = 0;
2194
f180b4bc 2195 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 2196 if (!plane) {
2197 DRM_ERROR("KMS: Failed to allocate plane\n");
2198 return -ENOMEM;
2199 }
b2fddb13 2200 plane->type = plane_type;
df534fff
S		 2201
2202 /*
b2fddb13
NK		 2203 * HACK: IGT tests expect that the primary plane for a CRTC
2204 * can only have one possible CRTC. Only expose support for
2205 * any CRTC if they're not going to be used as a primary plane
2206 * for a CRTC - like overlay or underlay planes.
df534fff
S		 2207 */
2208 possible_crtcs = 1 << plane_id;
2209 if (plane_id >= dm->dc->caps.max_streams)
2210 possible_crtcs = 0xff;
2211
cc1fec57 2212 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
df534fff
S		 2213
2214 if (ret) {
2215 DRM_ERROR("KMS: Failed to initialize plane\n");
54087768 2216 kfree(plane);
df534fff
S		 2217 return ret;
2218 }
2219
54087768
NK		 2220 if (mode_info)
2221 mode_info->planes[plane_id] = plane;
2222
df534fff
S		 2223 return ret;
2224}
2225
89fc8d4e
HW		 2226
2227static void register_backlight_device(struct amdgpu_display_manager *dm,
2228 struct dc_link *link)
2229{
2230#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2231 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2232
2233 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2234 link->type != dc_connection_none) {
1f6010a9
DF		 2235 /*
2236 * Event if registration failed, we should continue with
89fc8d4e
HW		 2237 * DM initialization because not having a backlight control
2238 * is better then a black screen.
2239 */
2240 amdgpu_dm_register_backlight_device(dm);
2241
2242 if (dm->backlight_dev)
2243 dm->backlight_link = link;
2244 }
2245#endif
2246}
2247
2248
1f6010a9
DF		 2249/*
2250 * In this architecture, the association
4562236b
HW		 2251 * connector -> encoder -> crtc
2252 * id not really requried. The crtc and connector will hold the
2253 * display_index as an abstraction to use with DAL component
2254 *
2255 * Returns 0 on success
2256 */
7578ecda 2257static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 2258{
2259 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 2260 int32_t i;
c84dec2f 2261 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 2262 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 2263 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 2264 uint32_t link_cnt;
cc1fec57 2265 int32_t primary_planes;
fbbdadf2 2266 enum dc_connection_type new_connection_type = dc_connection_none;
cc1fec57 2267 const struct dc_plane_cap *plane;
4562236b
HW		 2268
2269 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 2270 if (amdgpu_dm_mode_config_init(dm->adev)) {
2271 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 2272 return -EINVAL;
4562236b
HW		 2273 }
2274
b2fddb13
NK		 2275 /* There is one primary plane per CRTC */
2276 primary_planes = dm->dc->caps.max_streams;
54087768 2277 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
efa6a8b7 2278
b2fddb13
NK		 2279 /*
2280 * Initialize primary planes, implicit planes for legacy IOCTLS.
2281 * Order is reversed to match iteration order in atomic check.
2282 */
2283 for (i = (primary_planes - 1); i >= 0; i--) {
cc1fec57
NK		 2284 plane = &dm->dc->caps.planes[i];
2285
b2fddb13 2286 if (initialize_plane(dm, mode_info, i,
cc1fec57 2287 DRM_PLANE_TYPE_PRIMARY, plane)) {
df534fff 2288 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 2289 goto fail;
d4e13b0d 2290 }
df534fff 2291 }
92f3ac40 2292
0d579c7e
NK		 2293 /*
2294 * Initialize overlay planes, index starting after primary planes.
2295 * These planes have a higher DRM index than the primary planes since
2296 * they should be considered as having a higher z-order.
2297 * Order is reversed to match iteration order in atomic check.
cc1fec57
NK		 2298 *
2299 * Only support DCN for now, and only expose one so we don't encourage
2300 * userspace to use up all the pipes.
0d579c7e 2301 */
cc1fec57
NK		 2302 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2303 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2304
2305 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2306 continue;
2307
2308 if (!plane->blends_with_above || !plane->blends_with_below)
2309 continue;
2310
ea36ad34 2311 if (!plane->pixel_format_support.argb8888)
cc1fec57
NK		 2312 continue;
2313
54087768 2314 if (initialize_plane(dm, NULL, primary_planes + i,
cc1fec57 2315 DRM_PLANE_TYPE_OVERLAY, plane)) {
0d579c7e 2316 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 2317 goto fail;
d4e13b0d 2318 }
cc1fec57
NK		 2319
2320 /* Only create one overlay plane. */
2321 break;
d4e13b0d 2322 }
4562236b 2323
d4e13b0d 2324 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 2325 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 2326 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 2327 goto fail;
4562236b 2328 }
4562236b 2329
ab2541b6 2330 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 2331
2332 /* loops over all connectors on the board */
2333 for (i = 0; i < link_cnt; i++) {
89fc8d4e 2334 struct dc_link *link = NULL;
4562236b
HW		 2335
2336 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2337 DRM_ERROR(
2338 "KMS: Cannot support more than %d display indexes\n",
2339 AMDGPU_DM_MAX_DISPLAY_INDEX);
2340 continue;
2341 }
2342
2343 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2344 if (!aconnector)
cd8a2ae8 2345 goto fail;
4562236b
HW		 2346
2347 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 2348 if (!aencoder)
cd8a2ae8 2349 goto fail;
4562236b
HW		 2350
2351 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2352 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 2353 goto fail;
4562236b
HW		 2354 }
2355
2356 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2357 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 2358 goto fail;
4562236b
HW		 2359 }
2360
89fc8d4e
HW		 2361 link = dc_get_link_at_index(dm->dc, i);
2362
fbbdadf2
BL		 2363 if (!dc_link_detect_sink(link, &new_connection_type))
2364 DRM_ERROR("KMS: Failed to detect connector\n");
2365
2366 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2367 emulated_link_detect(link);
2368 amdgpu_dm_update_connector_after_detect(aconnector);
2369
2370 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 2371 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 2372 register_backlight_device(dm, link);
2373 }
2374
2375
4562236b
HW		 2376 }
2377
2378 /* Software is initialized. Now we can register interrupt handlers. */
2379 switch (adev->asic_type) {
2380 case CHIP_BONAIRE:
2381 case CHIP_HAWAII:
cd4b356f
AD		 2382 case CHIP_KAVERI:
2383 case CHIP_KABINI:
2384 case CHIP_MULLINS:
4562236b
HW		 2385 case CHIP_TONGA:
2386 case CHIP_FIJI:
2387 case CHIP_CARRIZO:
2388 case CHIP_STONEY:
2389 case CHIP_POLARIS11:
2390 case CHIP_POLARIS10:
b264d345 2391 case CHIP_POLARIS12:
7737de91 2392 case CHIP_VEGAM:
2c8ad2d5 2393 case CHIP_VEGA10:
2325ff30 2394 case CHIP_VEGA12:
1fe6bf2f 2395 case CHIP_VEGA20:
4562236b
HW		 2396 if (dce110_register_irq_handlers(dm->adev)) {
2397 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2398 goto fail;
4562236b
HW		 2399 }
2400 break;
ff5ef992
AD		 2401#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2402 case CHIP_RAVEN:
476e955d 2403#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
fbd2afe5 2404 case CHIP_NAVI12:
476e955d 2405 case CHIP_NAVI10:
fce651e3 2406 case CHIP_NAVI14:
30221ad8
BL		 2407#endif
2408#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2409 case CHIP_RENOIR:
476e955d 2410#endif
ff5ef992
AD		 2411 if (dcn10_register_irq_handlers(dm->adev)) {
2412 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2413 goto fail;
ff5ef992
AD		 2414 }
2415 break;
2416#endif
4562236b 2417 default:
e63f8673 2418 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 2419 goto fail;
4562236b
HW		 2420 }
2421
1bc460a4
HW		 2422 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2423 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
811bc15b
AL		 2424 if (adev->asic_type == CHIP_RENOIR)
2425 dm->dc->debug.disable_stutter = true;
1bc460a4 2426
4562236b 2427 return 0;
cd8a2ae8 2428fail:
4562236b 2429 kfree(aencoder);
4562236b 2430 kfree(aconnector);
54087768 2431
59d0f396 2432 return -EINVAL;
4562236b
HW		 2433}
2434
7578ecda 2435static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2436{
2437 drm_mode_config_cleanup(dm->ddev);
eb3dc897 2438 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 2439 return;
2440}
2441
2442/******************************************************************************
2443 * amdgpu_display_funcs functions
2444 *****************************************************************************/
2445
1f6010a9 2446/*
4562236b
HW		 2447 * dm_bandwidth_update - program display watermarks
2448 *
2449 * @adev: amdgpu_device pointer
2450 *
2451 * Calculate and program the display watermarks and line buffer allocation.
2452 */
2453static void dm_bandwidth_update(struct amdgpu_device *adev)
2454{
49c07a99 2455 /* TODO: implement later */
4562236b
HW		 2456}
2457
39cc5be2 2458static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 2459 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2460 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 2461 .backlight_set_level = NULL, /* never called for DC */
2462 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 2463 .hpd_sense = NULL,/* called unconditionally */
2464 .hpd_set_polarity = NULL, /* called unconditionally */
2465 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2466 .page_flip_get_scanoutpos =
2467 dm_crtc_get_scanoutpos,/* called unconditionally */
2468 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2469 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2470};
2471
2472#if defined(CONFIG_DEBUG_KERNEL_DC)
2473
3ee6b26b
AD		 2474static ssize_t s3_debug_store(struct device *device,
2475 struct device_attribute *attr,
2476 const char *buf,
2477 size_t count)
4562236b
HW		 2478{
2479 int ret;
2480 int s3_state;
ef1de361 2481 struct drm_device *drm_dev = dev_get_drvdata(device);
4562236b
HW		 2482 struct amdgpu_device *adev = drm_dev->dev_private;
2483
2484 ret = kstrtoint(buf, 0, &s3_state);
2485
2486 if (ret == 0) {
2487 if (s3_state) {
2488 dm_resume(adev);
4562236b
HW		 2489 drm_kms_helper_hotplug_event(adev->ddev);
2490 } else
2491 dm_suspend(adev);
2492 }
2493
2494 return ret == 0 ? count : 0;
2495}
2496
2497DEVICE_ATTR_WO(s3_debug);
2498
2499#endif
2500
2501static int dm_early_init(void *handle)
2502{
2503 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2504
4562236b
HW		 2505 switch (adev->asic_type) {
2506 case CHIP_BONAIRE:
2507 case CHIP_HAWAII:
2508 adev->mode_info.num_crtc = 6;
2509 adev->mode_info.num_hpd = 6;
2510 adev->mode_info.num_dig = 6;
4562236b 2511 break;
cd4b356f
AD		 2512 case CHIP_KAVERI:
2513 adev->mode_info.num_crtc = 4;
2514 adev->mode_info.num_hpd = 6;
2515 adev->mode_info.num_dig = 7;
cd4b356f
AD		 2516 break;
2517 case CHIP_KABINI:
2518 case CHIP_MULLINS:
2519 adev->mode_info.num_crtc = 2;
2520 adev->mode_info.num_hpd = 6;
2521 adev->mode_info.num_dig = 6;
cd4b356f 2522 break;
4562236b
HW		 2523 case CHIP_FIJI:
2524 case CHIP_TONGA:
2525 adev->mode_info.num_crtc = 6;
2526 adev->mode_info.num_hpd = 6;
2527 adev->mode_info.num_dig = 7;
4562236b
HW		 2528 break;
2529 case CHIP_CARRIZO:
2530 adev->mode_info.num_crtc = 3;
2531 adev->mode_info.num_hpd = 6;
2532 adev->mode_info.num_dig = 9;
4562236b
HW		 2533 break;
2534 case CHIP_STONEY:
2535 adev->mode_info.num_crtc = 2;
2536 adev->mode_info.num_hpd = 6;
2537 adev->mode_info.num_dig = 9;
4562236b
HW		 2538 break;
2539 case CHIP_POLARIS11:
b264d345 2540 case CHIP_POLARIS12:
4562236b
HW		 2541 adev->mode_info.num_crtc = 5;
2542 adev->mode_info.num_hpd = 5;
2543 adev->mode_info.num_dig = 5;
4562236b
HW		 2544 break;
2545 case CHIP_POLARIS10:
7737de91 2546 case CHIP_VEGAM:
4562236b
HW		 2547 adev->mode_info.num_crtc = 6;
2548 adev->mode_info.num_hpd = 6;
2549 adev->mode_info.num_dig = 6;
4562236b 2550 break;
2c8ad2d5 2551 case CHIP_VEGA10:
2325ff30 2552 case CHIP_VEGA12:
1fe6bf2f 2553 case CHIP_VEGA20:
2c8ad2d5
AD		 2554 adev->mode_info.num_crtc = 6;
2555 adev->mode_info.num_hpd = 6;
2556 adev->mode_info.num_dig = 6;
2557 break;
ff5ef992
AD		 2558#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2559 case CHIP_RAVEN:
2560 adev->mode_info.num_crtc = 4;
2561 adev->mode_info.num_hpd = 4;
2562 adev->mode_info.num_dig = 4;
ff5ef992 2563 break;
476e955d
HW		 2564#endif
2565#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2566 case CHIP_NAVI10:
fbd2afe5 2567 case CHIP_NAVI12:
476e955d
HW		 2568 adev->mode_info.num_crtc = 6;
2569 adev->mode_info.num_hpd = 6;
2570 adev->mode_info.num_dig = 6;
2571 break;
fce651e3
BL		 2572 case CHIP_NAVI14:
2573 adev->mode_info.num_crtc = 5;
2574 adev->mode_info.num_hpd = 5;
2575 adev->mode_info.num_dig = 5;
2576 break;
30221ad8
BL		 2577#endif
2578#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2579 case CHIP_RENOIR:
2580 adev->mode_info.num_crtc = 4;
2581 adev->mode_info.num_hpd = 4;
2582 adev->mode_info.num_dig = 4;
2583 break;
ff5ef992 2584#endif
4562236b 2585 default:
e63f8673 2586 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 2587 return -EINVAL;
2588 }
2589
c8dd5715
MD		 2590 amdgpu_dm_set_irq_funcs(adev);
2591
39cc5be2
AD		 2592 if (adev->mode_info.funcs == NULL)
2593 adev->mode_info.funcs = &dm_display_funcs;
2594
1f6010a9
DF		 2595 /*
2596 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 2597 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 2598 * amdgpu_device_init()
2599 */
4562236b
HW		 2600#if defined(CONFIG_DEBUG_KERNEL_DC)
2601 device_create_file(
2602 adev->ddev->dev,
2603 &dev_attr_s3_debug);
2604#endif
2605
2606 return 0;
2607}
2608
9b690ef3 2609static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 2610 struct dc_stream_state *new_stream,
2611 struct dc_stream_state *old_stream)
9b690ef3 2612{
e7b07cee
HW		 2613 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2614 return false;
2615
2616 if (!crtc_state->enable)
2617 return false;
2618
2619 return crtc_state->active;
2620}
2621
2622static bool modereset_required(struct drm_crtc_state *crtc_state)
2623{
2624 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2625 return false;
2626
2627 return !crtc_state->enable || !crtc_state->active;
2628}
2629
7578ecda 2630static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 2631{
2632 drm_encoder_cleanup(encoder);
2633 kfree(encoder);
2634}
2635
2636static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2637 .destroy = amdgpu_dm_encoder_destroy,
2638};
2639
e7b07cee 2640
695af5f9
NK		 2641static int fill_dc_scaling_info(const struct drm_plane_state *state,
2642 struct dc_scaling_info *scaling_info)
e7b07cee 2643{
6491f0c0 2644 int scale_w, scale_h;
e7b07cee 2645
695af5f9 2646 memset(scaling_info, 0, sizeof(*scaling_info));
e7b07cee 2647
695af5f9
NK		 2648 /* Source is fixed 16.16 but we ignore mantissa for now... */
2649 scaling_info->src_rect.x = state->src_x >> 16;
2650 scaling_info->src_rect.y = state->src_y >> 16;
e7b07cee 2651
695af5f9
NK		 2652 scaling_info->src_rect.width = state->src_w >> 16;
2653 if (scaling_info->src_rect.width == 0)
2654 return -EINVAL;
2655
2656 scaling_info->src_rect.height = state->src_h >> 16;
2657 if (scaling_info->src_rect.height == 0)
2658 return -EINVAL;
2659
2660 scaling_info->dst_rect.x = state->crtc_x;
2661 scaling_info->dst_rect.y = state->crtc_y;
e7b07cee
HW		 2662
2663 if (state->crtc_w == 0)
695af5f9 2664 return -EINVAL;
e7b07cee 2665
695af5f9 2666 scaling_info->dst_rect.width = state->crtc_w;
e7b07cee
HW		 2667
2668 if (state->crtc_h == 0)
695af5f9 2669 return -EINVAL;
e7b07cee 2670
695af5f9 2671 scaling_info->dst_rect.height = state->crtc_h;
e7b07cee 2672
695af5f9
NK		 2673 /* DRM doesn't specify clipping on destination output. */
2674 scaling_info->clip_rect = scaling_info->dst_rect;
e7b07cee 2675
6491f0c0
NK		 2676 /* TODO: Validate scaling per-format with DC plane caps */
2677 scale_w = scaling_info->dst_rect.width * 1000 /
2678 scaling_info->src_rect.width;
e7b07cee 2679
6491f0c0
NK		 2680 if (scale_w < 250 || scale_w > 16000)
2681 return -EINVAL;
2682
2683 scale_h = scaling_info->dst_rect.height * 1000 /
2684 scaling_info->src_rect.height;
2685
2686 if (scale_h < 250 || scale_h > 16000)
2687 return -EINVAL;
2688
695af5f9
NK		 2689 /*
2690 * The "scaling_quality" can be ignored for now, quality = 0 has DC
2691 * assume reasonable defaults based on the format.
2692 */
e7b07cee 2693
695af5f9 2694 return 0;
4562236b 2695}
695af5f9 2696
3ee6b26b 2697static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 2698 uint64_t *tiling_flags)
e7b07cee 2699{
e68d14dd 2700 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 2701 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 2702
e7b07cee 2703 if (unlikely(r)) {
1f6010a9 2704 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 2705 if (r != -ERESTARTSYS)
2706 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 2707 return r;
2708 }
2709
e7b07cee
HW		 2710 if (tiling_flags)
2711 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2712
2713 amdgpu_bo_unreserve(rbo);
2714
2715 return r;
2716}
2717
7df7e505
NK		 2718static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2719{
2720 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2721
2722 return offset ? (address + offset * 256) : 0;
2723}
2724
695af5f9
NK		 2725static int
2726fill_plane_dcc_attributes(struct amdgpu_device *adev,
2727 const struct amdgpu_framebuffer *afb,
2728 const enum surface_pixel_format format,
2729 const enum dc_rotation_angle rotation,
12e2b2d4 2730 const struct plane_size *plane_size,
695af5f9
NK		 2731 const union dc_tiling_info *tiling_info,
2732 const uint64_t info,
2733 struct dc_plane_dcc_param *dcc,
2734 struct dc_plane_address *address)
7df7e505
NK		 2735{
2736 struct dc *dc = adev->dm.dc;
8daa1218
NC		 2737 struct dc_dcc_surface_param input;
2738 struct dc_surface_dcc_cap output;
7df7e505
NK		 2739 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2740 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2741 uint64_t dcc_address;
2742
8daa1218
NC		 2743 memset(&input, 0, sizeof(input));
2744 memset(&output, 0, sizeof(output));
2745
7df7e505 2746 if (!offset)
09e5665a
NK		 2747 return 0;
2748
695af5f9 2749 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
09e5665a 2750 return 0;
7df7e505
NK		 2751
2752 if (!dc->cap_funcs.get_dcc_compression_cap)
09e5665a 2753 return -EINVAL;
7df7e505 2754
695af5f9 2755 input.format = format;
12e2b2d4
DL		 2756 input.surface_size.width = plane_size->surface_size.width;
2757 input.surface_size.height = plane_size->surface_size.height;
695af5f9 2758 input.swizzle_mode = tiling_info->gfx9.swizzle;
7df7e505 2759
695af5f9 2760 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
7df7e505 2761 input.scan = SCAN_DIRECTION_HORIZONTAL;
695af5f9 2762 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
7df7e505
NK		 2763 input.scan = SCAN_DIRECTION_VERTICAL;
2764
2765 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
09e5665a 2766 return -EINVAL;
7df7e505
NK		 2767
2768 if (!output.capable)
09e5665a 2769 return -EINVAL;
7df7e505
NK		 2770
2771 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
09e5665a 2772 return -EINVAL;
7df7e505 2773
09e5665a 2774 dcc->enable = 1;
12e2b2d4 2775 dcc->meta_pitch =
7df7e505 2776 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
12e2b2d4 2777 dcc->independent_64b_blks = i64b;
7df7e505
NK		 2778
2779 dcc_address = get_dcc_address(afb->address, info);
09e5665a
NK		 2780 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
2781 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
7df7e505 2782
09e5665a
NK		 2783 return 0;
2784}
2785
2786static int
320932bf 2787fill_plane_buffer_attributes(struct amdgpu_device *adev,
09e5665a 2788 const struct amdgpu_framebuffer *afb,
695af5f9
NK		 2789 const enum surface_pixel_format format,
2790 const enum dc_rotation_angle rotation,
2791 const uint64_t tiling_flags,
09e5665a 2792 union dc_tiling_info *tiling_info,
12e2b2d4 2793 struct plane_size *plane_size,
09e5665a 2794 struct dc_plane_dcc_param *dcc,
695af5f9 2795 struct dc_plane_address *address)
09e5665a 2796{
320932bf 2797 const struct drm_framebuffer *fb = &afb->base;
09e5665a
NK		 2798 int ret;
2799
2800 memset(tiling_info, 0, sizeof(*tiling_info));
320932bf 2801 memset(plane_size, 0, sizeof(*plane_size));
09e5665a 2802 memset(dcc, 0, sizeof(*dcc));
e0634e8d
NK		 2803 memset(address, 0, sizeof(*address));
2804
695af5f9 2805 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
12e2b2d4
DL		 2806 plane_size->surface_size.x = 0;
2807 plane_size->surface_size.y = 0;
2808 plane_size->surface_size.width = fb->width;
2809 plane_size->surface_size.height = fb->height;
2810 plane_size->surface_pitch =
320932bf
NK		 2811 fb->pitches[0] / fb->format->cpp[0];
2812
e0634e8d
NK		 2813 address->type = PLN_ADDR_TYPE_GRAPHICS;
2814 address->grph.addr.low_part = lower_32_bits(afb->address);
2815 address->grph.addr.high_part = upper_32_bits(afb->address);
1894478a 2816 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
1791e54f 2817 uint64_t chroma_addr = afb->address + fb->offsets[1];
e0634e8d 2818
12e2b2d4
DL		 2819 plane_size->surface_size.x = 0;
2820 plane_size->surface_size.y = 0;
2821 plane_size->surface_size.width = fb->width;
2822 plane_size->surface_size.height = fb->height;
2823 plane_size->surface_pitch =
320932bf
NK		 2824 fb->pitches[0] / fb->format->cpp[0];
2825
12e2b2d4
DL		 2826 plane_size->chroma_size.x = 0;
2827 plane_size->chroma_size.y = 0;
320932bf 2828 /* TODO: set these based on surface format */
12e2b2d4
DL		 2829 plane_size->chroma_size.width = fb->width / 2;
2830 plane_size->chroma_size.height = fb->height / 2;
320932bf 2831
12e2b2d4 2832 plane_size->chroma_pitch =
320932bf
NK		 2833 fb->pitches[1] / fb->format->cpp[1];
2834
e0634e8d
NK		 2835 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2836 address->video_progressive.luma_addr.low_part =
2837 lower_32_bits(afb->address);
2838 address->video_progressive.luma_addr.high_part =
2839 upper_32_bits(afb->address);
2840 address->video_progressive.chroma_addr.low_part =
2841 lower_32_bits(chroma_addr);
2842 address->video_progressive.chroma_addr.high_part =
2843 upper_32_bits(chroma_addr);
2844 }
09e5665a
NK		 2845
2846 /* Fill GFX8 params */
2847 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2848 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2849
2850 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2851 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2852 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2853 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2854 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2855
2856 /* XXX fix me for VI */
2857 tiling_info->gfx8.num_banks = num_banks;
2858 tiling_info->gfx8.array_mode =
2859 DC_ARRAY_2D_TILED_THIN1;
2860 tiling_info->gfx8.tile_split = tile_split;
2861 tiling_info->gfx8.bank_width = bankw;
2862 tiling_info->gfx8.bank_height = bankh;
2863 tiling_info->gfx8.tile_aspect = mtaspect;
2864 tiling_info->gfx8.tile_mode =
2865 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2866 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2867 == DC_ARRAY_1D_TILED_THIN1) {
2868 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2869 }
2870
2871 tiling_info->gfx8.pipe_config =
2872 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2873
2874 if (adev->asic_type == CHIP_VEGA10 ||
2875 adev->asic_type == CHIP_VEGA12 ||
2876 adev->asic_type == CHIP_VEGA20 ||
476e955d
HW		 2877#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2878 adev->asic_type == CHIP_NAVI10 ||
fce651e3 2879 adev->asic_type == CHIP_NAVI14 ||
fbd2afe5 2880 adev->asic_type == CHIP_NAVI12 ||
30221ad8
BL		 2881#endif
2882#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2883 adev->asic_type == CHIP_RENOIR ||
476e955d 2884#endif
09e5665a
NK		 2885 adev->asic_type == CHIP_RAVEN) {
2886 /* Fill GFX9 params */
2887 tiling_info->gfx9.num_pipes =
2888 adev->gfx.config.gb_addr_config_fields.num_pipes;
2889 tiling_info->gfx9.num_banks =
2890 adev->gfx.config.gb_addr_config_fields.num_banks;
2891 tiling_info->gfx9.pipe_interleave =
2892 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2893 tiling_info->gfx9.num_shader_engines =
2894 adev->gfx.config.gb_addr_config_fields.num_se;
2895 tiling_info->gfx9.max_compressed_frags =
2896 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2897 tiling_info->gfx9.num_rb_per_se =
2898 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2899 tiling_info->gfx9.swizzle =
2900 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2901 tiling_info->gfx9.shaderEnable = 1;
2902
695af5f9
NK		 2903 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
2904 plane_size, tiling_info,
2905 tiling_flags, dcc, address);
09e5665a
NK		 2906 if (ret)
2907 return ret;
2908 }
2909
2910 return 0;
7df7e505
NK		 2911}
2912
d74004b6 2913static void
695af5f9 2914fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
d74004b6
NK		 2915 bool *per_pixel_alpha, bool *global_alpha,
2916 int *global_alpha_value)
2917{
2918 *per_pixel_alpha = false;
2919 *global_alpha = false;
2920 *global_alpha_value = 0xff;
2921
2922 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
2923 return;
2924
2925 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
2926 static const uint32_t alpha_formats[] = {
2927 DRM_FORMAT_ARGB8888,
2928 DRM_FORMAT_RGBA8888,
2929 DRM_FORMAT_ABGR8888,
2930 };
2931 uint32_t format = plane_state->fb->format->format;
2932 unsigned int i;
2933
2934 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
2935 if (format == alpha_formats[i]) {
2936 *per_pixel_alpha = true;
2937 break;
2938 }
2939 }
2940 }
2941
2942 if (plane_state->alpha < 0xffff) {
2943 *global_alpha = true;
2944 *global_alpha_value = plane_state->alpha >> 8;
2945 }
2946}
2947
004fefa3
NK		 2948static int
2949fill_plane_color_attributes(const struct drm_plane_state *plane_state,
695af5f9 2950 const enum surface_pixel_format format,
004fefa3
NK		 2951 enum dc_color_space *color_space)
2952{
2953 bool full_range;
2954
2955 *color_space = COLOR_SPACE_SRGB;
2956
2957 /* DRM color properties only affect non-RGB formats. */
695af5f9 2958 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
004fefa3
NK		 2959 return 0;
2960
2961 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
2962
2963 switch (plane_state->color_encoding) {
2964 case DRM_COLOR_YCBCR_BT601:
2965 if (full_range)
2966 *color_space = COLOR_SPACE_YCBCR601;
2967 else
2968 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
2969 break;
2970
2971 case DRM_COLOR_YCBCR_BT709:
2972 if (full_range)
2973 *color_space = COLOR_SPACE_YCBCR709;
2974 else
2975 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
2976 break;
2977
2978 case DRM_COLOR_YCBCR_BT2020:
2979 if (full_range)
2980 *color_space = COLOR_SPACE_2020_YCBCR;
2981 else
2982 return -EINVAL;
2983 break;
2984
2985 default:
2986 return -EINVAL;
2987 }
2988
2989 return 0;
2990}
2991
695af5f9
NK		 2992static int
2993fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
2994 const struct drm_plane_state *plane_state,
2995 const uint64_t tiling_flags,
2996 struct dc_plane_info *plane_info,
2997 struct dc_plane_address *address)
2998{
2999 const struct drm_framebuffer *fb = plane_state->fb;
3000 const struct amdgpu_framebuffer *afb =
3001 to_amdgpu_framebuffer(plane_state->fb);
3002 struct drm_format_name_buf format_name;
3003 int ret;
3004
3005 memset(plane_info, 0, sizeof(*plane_info));
3006
3007 switch (fb->format->format) {
3008 case DRM_FORMAT_C8:
3009 plane_info->format =
3010 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
3011 break;
3012 case DRM_FORMAT_RGB565:
3013 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
3014 break;
3015 case DRM_FORMAT_XRGB8888:
3016 case DRM_FORMAT_ARGB8888:
3017 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
3018 break;
3019 case DRM_FORMAT_XRGB2101010:
3020 case DRM_FORMAT_ARGB2101010:
3021 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
3022 break;
3023 case DRM_FORMAT_XBGR2101010:
3024 case DRM_FORMAT_ABGR2101010:
3025 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
3026 break;
3027 case DRM_FORMAT_XBGR8888:
3028 case DRM_FORMAT_ABGR8888:
3029 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
3030 break;
3031 case DRM_FORMAT_NV21:
3032 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
3033 break;
3034 case DRM_FORMAT_NV12:
3035 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
3036 break;
3037 default:
3038 DRM_ERROR(
3039 "Unsupported screen format %s\n",
3040 drm_get_format_name(fb->format->format, &format_name));
3041 return -EINVAL;
3042 }
3043
3044 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
3045 case DRM_MODE_ROTATE_0:
3046 plane_info->rotation = ROTATION_ANGLE_0;
3047 break;
3048 case DRM_MODE_ROTATE_90:
3049 plane_info->rotation = ROTATION_ANGLE_90;
3050 break;
3051 case DRM_MODE_ROTATE_180:
3052 plane_info->rotation = ROTATION_ANGLE_180;
3053 break;
3054 case DRM_MODE_ROTATE_270:
3055 plane_info->rotation = ROTATION_ANGLE_270;
3056 break;
3057 default:
3058 plane_info->rotation = ROTATION_ANGLE_0;
3059 break;
3060 }
3061
3062 plane_info->visible = true;
3063 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
3064
6d83a32d
MS		 3065 plane_info->layer_index = 0;
3066
695af5f9
NK		 3067 ret = fill_plane_color_attributes(plane_state, plane_info->format,
3068 &plane_info->color_space);
3069 if (ret)
3070 return ret;
3071
3072 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
3073 plane_info->rotation, tiling_flags,
3074 &plane_info->tiling_info,
3075 &plane_info->plane_size,
3076 &plane_info->dcc, address);
3077 if (ret)
3078 return ret;
3079
3080 fill_blending_from_plane_state(
3081 plane_state, &plane_info->per_pixel_alpha,
3082 &plane_info->global_alpha, &plane_info->global_alpha_value);
3083
3084 return 0;
3085}
3086
3087static int fill_dc_plane_attributes(struct amdgpu_device *adev,
3088 struct dc_plane_state *dc_plane_state,
3089 struct drm_plane_state *plane_state,
3090 struct drm_crtc_state *crtc_state)
e7b07cee 3091{
cf020d49 3092 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
e7b07cee
HW		 3093 const struct amdgpu_framebuffer *amdgpu_fb =
3094 to_amdgpu_framebuffer(plane_state->fb);
695af5f9
NK		 3095 struct dc_scaling_info scaling_info;
3096 struct dc_plane_info plane_info;
3097 uint64_t tiling_flags;
3098 int ret;
e7b07cee 3099
695af5f9
NK		 3100 ret = fill_dc_scaling_info(plane_state, &scaling_info);
3101 if (ret)
3102 return ret;
e7b07cee 3103
695af5f9
NK		 3104 dc_plane_state->src_rect = scaling_info.src_rect;
3105 dc_plane_state->dst_rect = scaling_info.dst_rect;
3106 dc_plane_state->clip_rect = scaling_info.clip_rect;
3107 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
e7b07cee 3108
695af5f9 3109 ret = get_fb_info(amdgpu_fb, &tiling_flags);
e7b07cee
HW		 3110 if (ret)
3111 return ret;
3112
695af5f9
NK		 3113 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3114 &plane_info,
3115 &dc_plane_state->address);
004fefa3
NK		 3116 if (ret)
3117 return ret;
3118
695af5f9
NK		 3119 dc_plane_state->format = plane_info.format;
3120 dc_plane_state->color_space = plane_info.color_space;
3121 dc_plane_state->format = plane_info.format;
3122 dc_plane_state->plane_size = plane_info.plane_size;
3123 dc_plane_state->rotation = plane_info.rotation;
3124 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
3125 dc_plane_state->stereo_format = plane_info.stereo_format;
3126 dc_plane_state->tiling_info = plane_info.tiling_info;
3127 dc_plane_state->visible = plane_info.visible;
3128 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
3129 dc_plane_state->global_alpha = plane_info.global_alpha;
3130 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
3131 dc_plane_state->dcc = plane_info.dcc;
6d83a32d 3132 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
695af5f9 3133
e277adc5
LSL		 3134 /*
3135 * Always set input transfer function, since plane state is refreshed
3136 * every time.
3137 */
cf020d49
NK		 3138 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
3139 if (ret)
3140 return ret;
e7b07cee 3141
cf020d49 3142 return 0;
e7b07cee
HW		 3143}
3144
3ee6b26b
AD		 3145static void update_stream_scaling_settings(const struct drm_display_mode *mode,
3146 const struct dm_connector_state *dm_state,
3147 struct dc_stream_state *stream)
e7b07cee
HW		 3148{
3149 enum amdgpu_rmx_type rmx_type;
3150
3151 struct rect src = { 0 }; /* viewport in composition space*/
3152 struct rect dst = { 0 }; /* stream addressable area */
3153
3154 /* no mode. nothing to be done */
3155 if (!mode)
3156 return;
3157
3158 /* Full screen scaling by default */
3159 src.width = mode->hdisplay;
3160 src.height = mode->vdisplay;
3161 dst.width = stream->timing.h_addressable;
3162 dst.height = stream->timing.v_addressable;
3163
f4791779
HW		 3164 if (dm_state) {
3165 rmx_type = dm_state->scaling;
3166 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
3167 if (src.width * dst.height <
3168 src.height * dst.width) {
3169 /* height needs less upscaling/more downscaling */
3170 dst.width = src.width *
3171 dst.height / src.height;
3172 } else {
3173 /* width needs less upscaling/more downscaling */
3174 dst.height = src.height *
3175 dst.width / src.width;
3176 }
3177 } else if (rmx_type == RMX_CENTER) {
3178 dst = src;
e7b07cee 3179 }
e7b07cee 3180
f4791779
HW		 3181 dst.x = (stream->timing.h_addressable - dst.width) / 2;
3182 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 3183
f4791779
HW		 3184 if (dm_state->underscan_enable) {
3185 dst.x += dm_state->underscan_hborder / 2;
3186 dst.y += dm_state->underscan_vborder / 2;
3187 dst.width -= dm_state->underscan_hborder;
3188 dst.height -= dm_state->underscan_vborder;
3189 }
e7b07cee
HW		 3190 }
3191
3192 stream->src = src;
3193 stream->dst = dst;
3194
f1ad2f5e 3195 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 3196 dst.x, dst.y, dst.width, dst.height);
3197
3198}
3199
3ee6b26b 3200static enum dc_color_depth
42ba01fc
NK		 3201convert_color_depth_from_display_info(const struct drm_connector *connector,
3202 const struct drm_connector_state *state)
e7b07cee 3203{
01c22997
NK		 3204 uint8_t bpc = (uint8_t)connector->display_info.bpc;
3205
3206 /* Assume 8 bpc by default if no bpc is specified. */
3207 bpc = bpc ? bpc : 8;
e7b07cee 3208
01933ba4
NK		 3209 if (!state)
3210 state = connector->state;
3211
42ba01fc 3212 if (state) {
01c22997
NK		 3213 /*
3214 * Cap display bpc based on the user requested value.
3215 *
3216 * The value for state->max_bpc may not correctly updated
3217 * depending on when the connector gets added to the state
3218 * or if this was called outside of atomic check, so it
3219 * can't be used directly.
3220 */
3221 bpc = min(bpc, state->max_requested_bpc);
3222
1825fd34
NK		 3223 /* Round down to the nearest even number. */
3224 bpc = bpc - (bpc & 1);
3225 }
07e3a1cf 3226
e7b07cee
HW		 3227 switch (bpc) {
3228 case 0:
1f6010a9
DF		 3229 /*
3230 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 3231 * EDID revision before 1.4
3232 * TODO: Fix edid parsing
3233 */
3234 return COLOR_DEPTH_888;
3235 case 6:
3236 return COLOR_DEPTH_666;
3237 case 8:
3238 return COLOR_DEPTH_888;
3239 case 10:
3240 return COLOR_DEPTH_101010;
3241 case 12:
3242 return COLOR_DEPTH_121212;
3243 case 14:
3244 return COLOR_DEPTH_141414;
3245 case 16:
3246 return COLOR_DEPTH_161616;
3247 default:
3248 return COLOR_DEPTH_UNDEFINED;
3249 }
3250}
3251
3ee6b26b
AD		 3252static enum dc_aspect_ratio
3253get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 3254{
e11d4147
LSL		 3255 /* 1-1 mapping, since both enums follow the HDMI spec. */
3256 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 3257}
3258
3ee6b26b
AD		 3259static enum dc_color_space
3260get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 3261{
3262 enum dc_color_space color_space = COLOR_SPACE_SRGB;
3263
3264 switch (dc_crtc_timing->pixel_encoding) {
3265 case PIXEL_ENCODING_YCBCR422:
3266 case PIXEL_ENCODING_YCBCR444:
3267 case PIXEL_ENCODING_YCBCR420:
3268 {
3269 /*
3270 * 27030khz is the separation point between HDTV and SDTV
3271 * according to HDMI spec, we use YCbCr709 and YCbCr601
3272 * respectively
3273 */
380604e2 3274 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 3275 if (dc_crtc_timing->flags.Y_ONLY)
3276 color_space =
3277 COLOR_SPACE_YCBCR709_LIMITED;
3278 else
3279 color_space = COLOR_SPACE_YCBCR709;
3280 } else {
3281 if (dc_crtc_timing->flags.Y_ONLY)
3282 color_space =
3283 COLOR_SPACE_YCBCR601_LIMITED;
3284 else
3285 color_space = COLOR_SPACE_YCBCR601;
3286 }
3287
3288 }
3289 break;
3290 case PIXEL_ENCODING_RGB:
3291 color_space = COLOR_SPACE_SRGB;
3292 break;
3293
3294 default:
3295 WARN_ON(1);
3296 break;
3297 }
3298
3299 return color_space;
3300}
3301
400443e8
ML		 3302static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
3303{
3304 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3305 return;
3306
3307 timing_out->display_color_depth--;
3308}
3309
3310static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
3311 const struct drm_display_info *info)
3312{
3313 int normalized_clk;
3314 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3315 return;
3316 do {
380604e2 3317 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 3318 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3319 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3320 normalized_clk /= 2;
3321 /* Adjusting pix clock following on HDMI spec based on colour depth */
3322 switch (timing_out->display_color_depth) {
3323 case COLOR_DEPTH_101010:
3324 normalized_clk = (normalized_clk * 30) / 24;
3325 break;
3326 case COLOR_DEPTH_121212:
3327 normalized_clk = (normalized_clk * 36) / 24;
3328 break;
3329 case COLOR_DEPTH_161616:
3330 normalized_clk = (normalized_clk * 48) / 24;
3331 break;
3332 default:
3333 return;
3334 }
3335 if (normalized_clk <= info->max_tmds_clock)
3336 return;
3337 reduce_mode_colour_depth(timing_out);
3338
3339 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
3340
3341}
e7b07cee 3342
42ba01fc
NK		 3343static void fill_stream_properties_from_drm_display_mode(
3344 struct dc_stream_state *stream,
3345 const struct drm_display_mode *mode_in,
3346 const struct drm_connector *connector,
3347 const struct drm_connector_state *connector_state,
3348 const struct dc_stream_state *old_stream)
e7b07cee
HW		 3349{
3350 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 3351 const struct drm_display_info *info = &connector->display_info;
d4252eee 3352 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3353 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
3354
3355 timing_out->h_border_left = 0;
3356 timing_out->h_border_right = 0;
3357 timing_out->v_border_top = 0;
3358 timing_out->v_border_bottom = 0;
3359 /* TODO: un-hardcode */
fe61a2f1 3360 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 3361 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1 3362 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
d4252eee
SW		 3363 else if (drm_mode_is_420_also(info, mode_in)
3364 && aconnector->force_yuv420_output)
3365 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
fe61a2f1 3366 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
ceb3dbb4 3367 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 3368 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3369 else
3370 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3371
3372 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3373 timing_out->display_color_depth = convert_color_depth_from_display_info(
42ba01fc 3374 connector, connector_state);
e7b07cee
HW		 3375 timing_out->scan_type = SCANNING_TYPE_NODATA;
3376 timing_out->hdmi_vic = 0;
b333730d
BL		 3377
3378 if(old_stream) {
3379 timing_out->vic = old_stream->timing.vic;
3380 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3381 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3382 } else {
3383 timing_out->vic = drm_match_cea_mode(mode_in);
3384 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3385 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3386 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3387 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3388 }
e7b07cee
HW		 3389
3390 timing_out->h_addressable = mode_in->crtc_hdisplay;
3391 timing_out->h_total = mode_in->crtc_htotal;
3392 timing_out->h_sync_width =
3393 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3394 timing_out->h_front_porch =
3395 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3396 timing_out->v_total = mode_in->crtc_vtotal;
3397 timing_out->v_addressable = mode_in->crtc_vdisplay;
3398 timing_out->v_front_porch =
3399 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3400 timing_out->v_sync_width =
3401 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
380604e2 3402 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
e7b07cee 3403 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 3404
3405 stream->output_color_space = get_output_color_space(timing_out);
3406
e43a432c
AK		 3407 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3408 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ceb3dbb4 3409 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
400443e8 3410 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 3411}
3412
3ee6b26b
AD		 3413static void fill_audio_info(struct audio_info *audio_info,
3414 const struct drm_connector *drm_connector,
3415 const struct dc_sink *dc_sink)
e7b07cee
HW		 3416{
3417 int i = 0;
3418 int cea_revision = 0;
3419 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3420
3421 audio_info->manufacture_id = edid_caps->manufacturer_id;
3422 audio_info->product_id = edid_caps->product_id;
3423
3424 cea_revision = drm_connector->display_info.cea_rev;
3425
090afc1e 3426 strscpy(audio_info->display_name,
d2b2562c 3427 edid_caps->display_name,
090afc1e 3428 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 3429
b830ebc9 3430 if (cea_revision >= 3) {
e7b07cee
HW		 3431 audio_info->mode_count = edid_caps->audio_mode_count;
3432
3433 for (i = 0; i < audio_info->mode_count; ++i) {
3434 audio_info->modes[i].format_code =
3435 (enum audio_format_code)
3436 (edid_caps->audio_modes[i].format_code);
3437 audio_info->modes[i].channel_count =
3438 edid_caps->audio_modes[i].channel_count;
3439 audio_info->modes[i].sample_rates.all =
3440 edid_caps->audio_modes[i].sample_rate;
3441 audio_info->modes[i].sample_size =
3442 edid_caps->audio_modes[i].sample_size;
3443 }
3444 }
3445
3446 audio_info->flags.all = edid_caps->speaker_flags;
3447
3448 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 3449 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 3450 audio_info->video_latency = drm_connector->video_latency[0];
3451 audio_info->audio_latency = drm_connector->audio_latency[0];
3452 }
3453
3454 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3455
3456}
3457
3ee6b26b
AD		 3458static void
3459copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3460 struct drm_display_mode *dst_mode)
e7b07cee
HW		 3461{
3462 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3463 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3464 dst_mode->crtc_clock = src_mode->crtc_clock;
3465 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3466 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 3467 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 3468 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3469 dst_mode->crtc_htotal = src_mode->crtc_htotal;
3470 dst_mode->crtc_hskew = src_mode->crtc_hskew;
3471 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3472 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3473 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3474 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3475 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3476}
3477
3ee6b26b
AD		 3478static void
3479decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3480 const struct drm_display_mode *native_mode,
3481 bool scale_enabled)
e7b07cee
HW		 3482{
3483 if (scale_enabled) {
3484 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3485 } else if (native_mode->clock == drm_mode->clock &&
3486 native_mode->htotal == drm_mode->htotal &&
3487 native_mode->vtotal == drm_mode->vtotal) {
3488 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3489 } else {
3490 /* no scaling nor amdgpu inserted, no need to patch */
3491 }
3492}
3493
aed15309
ML		 3494static struct dc_sink *
3495create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 3496{
2e0ac3d6 3497 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 3498 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 3499 sink_init_data.link = aconnector->dc_link;
3500 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3501
3502 sink = dc_sink_create(&sink_init_data);
423788c7 3503 if (!sink) {
2e0ac3d6 3504 DRM_ERROR("Failed to create sink!\n");
aed15309 3505 return NULL;
423788c7 3506 }
2e0ac3d6 3507 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 3508
aed15309 3509 return sink;
2e0ac3d6
HW		 3510}
3511
fa2123db
ML		 3512static void set_multisync_trigger_params(
3513 struct dc_stream_state *stream)
3514{
3515 if (stream->triggered_crtc_reset.enabled) {
3516 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3517 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3518 }
3519}
3520
3521static void set_master_stream(struct dc_stream_state *stream_set[],
3522 int stream_count)
3523{
3524 int j, highest_rfr = 0, master_stream = 0;
3525
3526 for (j = 0; j < stream_count; j++) {
3527 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3528 int refresh_rate = 0;
3529
380604e2 3530 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 3531 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3532 if (refresh_rate > highest_rfr) {
3533 highest_rfr = refresh_rate;
3534 master_stream = j;
3535 }
3536 }
3537 }
3538 for (j = 0; j < stream_count; j++) {
03736f4c 3539 if (stream_set[j])
fa2123db
ML		 3540 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3541 }
3542}
3543
3544static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3545{
3546 int i = 0;
3547
3548 if (context->stream_count < 2)
3549 return;
3550 for (i = 0; i < context->stream_count ; i++) {
3551 if (!context->streams[i])
3552 continue;
1f6010a9
DF		 3553 /*
3554 * TODO: add a function to read AMD VSDB bits and set
fa2123db 3555 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 3556 * For now it's set to false
fa2123db
ML		 3557 */
3558 set_multisync_trigger_params(context->streams[i]);
3559 }
3560 set_master_stream(context->streams, context->stream_count);
3561}
3562
3ee6b26b
AD		 3563static struct dc_stream_state *
3564create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3565 const struct drm_display_mode *drm_mode,
b333730d
BL		 3566 const struct dm_connector_state *dm_state,
3567 const struct dc_stream_state *old_stream)
e7b07cee
HW		 3568{
3569 struct drm_display_mode *preferred_mode = NULL;
391ef035 3570 struct drm_connector *drm_connector;
42ba01fc
NK		 3571 const struct drm_connector_state *con_state =
3572 dm_state ? &dm_state->base : NULL;
0971c40e 3573 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 3574 struct drm_display_mode mode = *drm_mode;
3575 bool native_mode_found = false;
b333730d
BL		 3576 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3577 int mode_refresh;
58124bf8 3578 int preferred_refresh = 0;
df2f1015
DF		 3579#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3580 struct dsc_dec_dpcd_caps dsc_caps;
3581 uint32_t link_bandwidth_kbps;
3582#endif
b333730d 3583
aed15309 3584 struct dc_sink *sink = NULL;
b830ebc9 3585 if (aconnector == NULL) {
e7b07cee 3586 DRM_ERROR("aconnector is NULL!\n");
64245fa7 3587 return stream;
e7b07cee
HW		 3588 }
3589
e7b07cee 3590 drm_connector = &aconnector->base;
2e0ac3d6 3591
f4ac176e 3592 if (!aconnector->dc_sink) {
e3fa5c4c
JFZ		 3593 sink = create_fake_sink(aconnector);
3594 if (!sink)
3595 return stream;
aed15309
ML		 3596 } else {
3597 sink = aconnector->dc_sink;
dcd5fb82 3598 dc_sink_retain(sink);
f4ac176e 3599 }
2e0ac3d6 3600
aed15309 3601 stream = dc_create_stream_for_sink(sink);
4562236b 3602
b830ebc9 3603 if (stream == NULL) {
e7b07cee 3604 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 3605 goto finish;
e7b07cee
HW		 3606 }
3607
ceb3dbb4
JL		 3608 stream->dm_stream_context = aconnector;
3609
e7b07cee
HW		 3610 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3611 /* Search for preferred mode */
3612 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3613 native_mode_found = true;
3614 break;
3615 }
3616 }
3617 if (!native_mode_found)
3618 preferred_mode = list_first_entry_or_null(
3619 &aconnector->base.modes,
3620 struct drm_display_mode,
3621 head);
3622
b333730d
BL		 3623 mode_refresh = drm_mode_vrefresh(&mode);
3624
b830ebc9 3625 if (preferred_mode == NULL) {
1f6010a9
DF		 3626 /*
3627 * This may not be an error, the use case is when we have no
e7b07cee
HW		 3628 * usermode calls to reset and set mode upon hotplug. In this
3629 * case, we call set mode ourselves to restore the previous mode
3630 * and the modelist may not be filled in in time.
3631 */
f1ad2f5e 3632 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 3633 } else {
3634 decide_crtc_timing_for_drm_display_mode(
3635 &mode, preferred_mode,
f4791779 3636 dm_state ? (dm_state->scaling != RMX_OFF) : false);
58124bf8 3637 preferred_refresh = drm_mode_vrefresh(preferred_mode);
e7b07cee
HW		 3638 }
3639
f783577c
JFZ		 3640 if (!dm_state)
3641 drm_mode_set_crtcinfo(&mode, 0);
3642
b333730d
BL		 3643 /*
3644 * If scaling is enabled and refresh rate didn't change
3645 * we copy the vic and polarities of the old timings
3646 */
3647 if (!scale || mode_refresh != preferred_refresh)
3648 fill_stream_properties_from_drm_display_mode(stream,
42ba01fc 3649 &mode, &aconnector->base, con_state, NULL);
b333730d
BL		 3650 else
3651 fill_stream_properties_from_drm_display_mode(stream,
42ba01fc 3652 &mode, &aconnector->base, con_state, old_stream);
b333730d 3653
39a4eb85 3654#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
df2f1015
DF		 3655 stream->timing.flags.DSC = 0;
3656
3657 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3658 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3659 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
3660 &dsc_caps);
3661 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
3662 dc_link_get_link_cap(aconnector->dc_link));
3663
3664 if (dsc_caps.is_dsc_supported)
0417df16 3665 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
df2f1015 3666 &dsc_caps,
0417df16 3667 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
df2f1015
DF		 3668 link_bandwidth_kbps,
3669 &stream->timing,
3670 &stream->timing.dsc_cfg))
3671 stream->timing.flags.DSC = 1;
3672 }
39a4eb85
WL		 3673#endif
3674
e7b07cee
HW		 3675 update_stream_scaling_settings(&mode, dm_state, stream);
3676
3677 fill_audio_info(
3678 &stream->audio_info,
3679 drm_connector,
aed15309 3680 sink);
e7b07cee 3681
ceb3dbb4 3682 update_stream_signal(stream, sink);
9182b4cb 3683
aed15309 3684finish:
dcd5fb82 3685 dc_sink_release(sink);
9e3efe3e 3686
e7b07cee
HW		 3687 return stream;
3688}
3689
7578ecda 3690static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 3691{
3692 drm_crtc_cleanup(crtc);
3693 kfree(crtc);
3694}
3695
3696static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 3697 struct drm_crtc_state *state)
e7b07cee
HW		 3698{
3699 struct dm_crtc_state *cur = to_dm_crtc_state(state);
3700
3701 /* TODO Destroy dc_stream objects are stream object is flattened */
3702 if (cur->stream)
3703 dc_stream_release(cur->stream);
3704
3705
3706 __drm_atomic_helper_crtc_destroy_state(state);
3707
3708
3709 kfree(state);
3710}
3711
3712static void dm_crtc_reset_state(struct drm_crtc *crtc)
3713{
3714 struct dm_crtc_state *state;
3715
3716 if (crtc->state)
3717 dm_crtc_destroy_state(crtc, crtc->state);
3718
3719 state = kzalloc(sizeof(*state), GFP_KERNEL);
3720 if (WARN_ON(!state))
3721 return;
3722
3723 crtc->state = &state->base;
3724 crtc->state->crtc = crtc;
3725
3726}
3727
3728static struct drm_crtc_state *
3729dm_crtc_duplicate_state(struct drm_crtc *crtc)
3730{
3731 struct dm_crtc_state *state, *cur;
3732
3733 cur = to_dm_crtc_state(crtc->state);
3734
3735 if (WARN_ON(!crtc->state))
3736 return NULL;
3737
2004f45e 3738 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 3739 if (!state)
3740 return NULL;
e7b07cee
HW		 3741
3742 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3743
3744 if (cur->stream) {
3745 state->stream = cur->stream;
3746 dc_stream_retain(state->stream);
3747 }
3748
d6ef9b41
NK		 3749 state->active_planes = cur->active_planes;
3750 state->interrupts_enabled = cur->interrupts_enabled;
180db303 3751 state->vrr_params = cur->vrr_params;
98e6436d 3752 state->vrr_infopacket = cur->vrr_infopacket;
c1ee92f9 3753 state->abm_level = cur->abm_level;
bb47de73
NK		 3754 state->vrr_supported = cur->vrr_supported;
3755 state->freesync_config = cur->freesync_config;
14b25846 3756 state->crc_src = cur->crc_src;
cf020d49
NK		 3757 state->cm_has_degamma = cur->cm_has_degamma;
3758 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
98e6436d 3759
e7b07cee
HW		 3760 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3761
3762 return &state->base;
3763}
3764
d2574c33
MK		 3765static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
3766{
3767 enum dc_irq_source irq_source;
3768 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3769 struct amdgpu_device *adev = crtc->dev->dev_private;
3770 int rc;
3771
3772 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
3773
3774 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3775
3776 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
3777 acrtc->crtc_id, enable ? "en" : "dis", rc);
3778 return rc;
3779}
589d2739
HW		 3780
3781static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3782{
3783 enum dc_irq_source irq_source;
3784 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3785 struct amdgpu_device *adev = crtc->dev->dev_private;
d2574c33
MK		 3786 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3787 int rc = 0;
3788
3789 if (enable) {
3790 /* vblank irq on -> Only need vupdate irq in vrr mode */
3791 if (amdgpu_dm_vrr_active(acrtc_state))
3792 rc = dm_set_vupdate_irq(crtc, true);
3793 } else {
3794 /* vblank irq off -> vupdate irq off */
3795 rc = dm_set_vupdate_irq(crtc, false);
3796 }
3797
3798 if (rc)
3799 return rc;
589d2739
HW		 3800
3801 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 3802 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 3803}
3804
3805static int dm_enable_vblank(struct drm_crtc *crtc)
3806{
3807 return dm_set_vblank(crtc, true);
3808}
3809
3810static void dm_disable_vblank(struct drm_crtc *crtc)
3811{
3812 dm_set_vblank(crtc, false);
3813}
3814
e7b07cee
HW		 3815/* Implemented only the options currently availible for the driver */
3816static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3817 .reset = dm_crtc_reset_state,
3818 .destroy = amdgpu_dm_crtc_destroy,
3819 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3820 .set_config = drm_atomic_helper_set_config,
3821 .page_flip = drm_atomic_helper_page_flip,
3822 .atomic_duplicate_state = dm_crtc_duplicate_state,
3823 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 3824 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 3825 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
8fb843d1 3826 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
589d2739
HW		 3827 .enable_vblank = dm_enable_vblank,
3828 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 3829};
3830
3831static enum drm_connector_status
3832amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3833{
3834 bool connected;
c84dec2f 3835 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 3836
1f6010a9
DF		 3837 /*
3838 * Notes:
e7b07cee
HW		 3839 * 1. This interface is NOT called in context of HPD irq.
3840 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 3841 * makes it a bad place for *any* MST-related activity.
3842 */
e7b07cee 3843
8580d60b
HW		 3844 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3845 !aconnector->fake_enable)
e7b07cee
HW		 3846 connected = (aconnector->dc_sink != NULL);
3847 else
3848 connected = (aconnector->base.force == DRM_FORCE_ON);
3849
3850 return (connected ? connector_status_connected :
3851 connector_status_disconnected);
3852}
3853
3ee6b26b
AD		 3854int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3855 struct drm_connector_state *connector_state,
3856 struct drm_property *property,
3857 uint64_t val)
e7b07cee
HW		 3858{
3859 struct drm_device *dev = connector->dev;
3860 struct amdgpu_device *adev = dev->dev_private;
3861 struct dm_connector_state *dm_old_state =
3862 to_dm_connector_state(connector->state);
3863 struct dm_connector_state *dm_new_state =
3864 to_dm_connector_state(connector_state);
3865
3866 int ret = -EINVAL;
3867
3868 if (property == dev->mode_config.scaling_mode_property) {
3869 enum amdgpu_rmx_type rmx_type;
3870
3871 switch (val) {
3872 case DRM_MODE_SCALE_CENTER:
3873 rmx_type = RMX_CENTER;
3874 break;
3875 case DRM_MODE_SCALE_ASPECT:
3876 rmx_type = RMX_ASPECT;
3877 break;
3878 case DRM_MODE_SCALE_FULLSCREEN:
3879 rmx_type = RMX_FULL;
3880 break;
3881 case DRM_MODE_SCALE_NONE:
3882 default:
3883 rmx_type = RMX_OFF;
3884 break;
3885 }
3886
3887 if (dm_old_state->scaling == rmx_type)
3888 return 0;
3889
3890 dm_new_state->scaling = rmx_type;
3891 ret = 0;
3892 } else if (property == adev->mode_info.underscan_hborder_property) {
3893 dm_new_state->underscan_hborder = val;
3894 ret = 0;
3895 } else if (property == adev->mode_info.underscan_vborder_property) {
3896 dm_new_state->underscan_vborder = val;
3897 ret = 0;
3898 } else if (property == adev->mode_info.underscan_property) {
3899 dm_new_state->underscan_enable = val;
3900 ret = 0;
c1ee92f9
DF		 3901 } else if (property == adev->mode_info.abm_level_property) {
3902 dm_new_state->abm_level = val;
3903 ret = 0;
e7b07cee
HW		 3904 }
3905
3906 return ret;
3907}
3908
3ee6b26b
AD		 3909int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3910 const struct drm_connector_state *state,
3911 struct drm_property *property,
3912 uint64_t *val)
e7b07cee
HW		 3913{
3914 struct drm_device *dev = connector->dev;
3915 struct amdgpu_device *adev = dev->dev_private;
3916 struct dm_connector_state *dm_state =
3917 to_dm_connector_state(state);
3918 int ret = -EINVAL;
3919
3920 if (property == dev->mode_config.scaling_mode_property) {
3921 switch (dm_state->scaling) {
3922 case RMX_CENTER:
3923 *val = DRM_MODE_SCALE_CENTER;
3924 break;
3925 case RMX_ASPECT:
3926 *val = DRM_MODE_SCALE_ASPECT;
3927 break;
3928 case RMX_FULL:
3929 *val = DRM_MODE_SCALE_FULLSCREEN;
3930 break;
3931 case RMX_OFF:
3932 default:
3933 *val = DRM_MODE_SCALE_NONE;
3934 break;
3935 }
3936 ret = 0;
3937 } else if (property == adev->mode_info.underscan_hborder_property) {
3938 *val = dm_state->underscan_hborder;
3939 ret = 0;
3940 } else if (property == adev->mode_info.underscan_vborder_property) {
3941 *val = dm_state->underscan_vborder;
3942 ret = 0;
3943 } else if (property == adev->mode_info.underscan_property) {
3944 *val = dm_state->underscan_enable;
3945 ret = 0;
c1ee92f9
DF		 3946 } else if (property == adev->mode_info.abm_level_property) {
3947 *val = dm_state->abm_level;
3948 ret = 0;
e7b07cee 3949 }
c1ee92f9 3950
e7b07cee
HW		 3951 return ret;
3952}
3953
526c654a
ED		 3954static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
3955{
3956 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
3957
3958 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
3959}
3960
7578ecda 3961static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 3962{
c84dec2f 3963 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3964 const struct dc_link *link = aconnector->dc_link;
3965 struct amdgpu_device *adev = connector->dev->dev_private;
3966 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 3967
e7b07cee
HW		 3968#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3969 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3970
89fc8d4e 3971 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 3972 link->type != dc_connection_none &&
3973 dm->backlight_dev) {
3974 backlight_device_unregister(dm->backlight_dev);
3975 dm->backlight_dev = NULL;
e7b07cee
HW		 3976 }
3977#endif
dcd5fb82
MF		 3978
3979 if (aconnector->dc_em_sink)
3980 dc_sink_release(aconnector->dc_em_sink);
3981 aconnector->dc_em_sink = NULL;
3982 if (aconnector->dc_sink)
3983 dc_sink_release(aconnector->dc_sink);
3984 aconnector->dc_sink = NULL;
3985
e86e8947 3986 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 3987 drm_connector_unregister(connector);
3988 drm_connector_cleanup(connector);
526c654a
ED		 3989 if (aconnector->i2c) {
3990 i2c_del_adapter(&aconnector->i2c->base);
3991 kfree(aconnector->i2c);
3992 }
3993
e7b07cee
HW		 3994 kfree(connector);
3995}
3996
3997void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3998{
3999 struct dm_connector_state *state =
4000 to_dm_connector_state(connector->state);
4001
df099b9b
LSL		 4002 if (connector->state)
4003 __drm_atomic_helper_connector_destroy_state(connector->state);
4004
e7b07cee
HW		 4005 kfree(state);
4006
4007 state = kzalloc(sizeof(*state), GFP_KERNEL);
4008
4009 if (state) {
4010 state->scaling = RMX_OFF;
4011 state->underscan_enable = false;
4012 state->underscan_hborder = 0;
4013 state->underscan_vborder = 0;
01933ba4 4014 state->base.max_requested_bpc = 8;
e7b07cee 4015
c3e50f89
NK		 4016 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4017 state->abm_level = amdgpu_dm_abm_level;
4018
df099b9b 4019 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 4020 }
4021}
4022
3ee6b26b
AD		 4023struct drm_connector_state *
4024amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 4025{
4026 struct dm_connector_state *state =
4027 to_dm_connector_state(connector->state);
4028
4029 struct dm_connector_state *new_state =
4030 kmemdup(state, sizeof(*state), GFP_KERNEL);
4031
98e6436d
AK		 4032 if (!new_state)
4033 return NULL;
e7b07cee 4034
98e6436d
AK		 4035 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
4036
4037 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 4038 new_state->abm_level = state->abm_level;
922454c2
NK		 4039 new_state->scaling = state->scaling;
4040 new_state->underscan_enable = state->underscan_enable;
4041 new_state->underscan_hborder = state->underscan_hborder;
4042 new_state->underscan_vborder = state->underscan_vborder;
98e6436d
AK		 4043
4044 return &new_state->base;
e7b07cee
HW		 4045}
4046
4047static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
4048 .reset = amdgpu_dm_connector_funcs_reset,
4049 .detect = amdgpu_dm_connector_detect,
4050 .fill_modes = drm_helper_probe_single_connector_modes,
4051 .destroy = amdgpu_dm_connector_destroy,
4052 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
4053 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4054 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
526c654a
ED		 4055 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
4056 .early_unregister = amdgpu_dm_connector_unregister
e7b07cee
HW		 4057};
4058
e7b07cee
HW		 4059static int get_modes(struct drm_connector *connector)
4060{
4061 return amdgpu_dm_connector_get_modes(connector);
4062}
4063
c84dec2f 4064static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 4065{
4066 struct dc_sink_init_data init_params = {
4067 .link = aconnector->dc_link,
4068 .sink_signal = SIGNAL_TYPE_VIRTUAL
4069 };
70e8ffc5 4070 struct edid *edid;
e7b07cee 4071
a89ff457 4072 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 4073 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
4074 aconnector->base.name);
4075
4076 aconnector->base.force = DRM_FORCE_OFF;
4077 aconnector->base.override_edid = false;
4078 return;
4079 }
4080
70e8ffc5
HW		 4081 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
4082
e7b07cee
HW		 4083 aconnector->edid = edid;
4084
4085 aconnector->dc_em_sink = dc_link_add_remote_sink(
4086 aconnector->dc_link,
4087 (uint8_t *)edid,
4088 (edid->extensions + 1) * EDID_LENGTH,
4089 &init_params);
4090
dcd5fb82 4091 if (aconnector->base.force == DRM_FORCE_ON) {
e7b07cee
HW		 4092 aconnector->dc_sink = aconnector->dc_link->local_sink ?
4093 aconnector->dc_link->local_sink :
4094 aconnector->dc_em_sink;
dcd5fb82
MF		 4095 dc_sink_retain(aconnector->dc_sink);
4096 }
e7b07cee
HW		 4097}
4098
c84dec2f 4099static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 4100{
4101 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
4102
1f6010a9
DF		 4103 /*
4104 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 4105 * Those settings have to be != 0 to get initial modeset
4106 */
4107 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4108 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
4109 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
4110 }
4111
4112
4113 aconnector->base.override_edid = true;
4114 create_eml_sink(aconnector);
4115}
4116
ba9ca088 4117enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 4118 struct drm_display_mode *mode)
e7b07cee
HW		 4119{
4120 int result = MODE_ERROR;
4121 struct dc_sink *dc_sink;
4122 struct amdgpu_device *adev = connector->dev->dev_private;
4123 /* TODO: Unhardcode stream count */
0971c40e 4124 struct dc_stream_state *stream;
c84dec2f 4125 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 4126 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 4127
4128 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
4129 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
4130 return result;
4131
1f6010a9
DF		 4132 /*
4133 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 4134 * EDID mgmt
4135 */
4136 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
4137 !aconnector->dc_em_sink)
4138 handle_edid_mgmt(aconnector);
4139
c84dec2f 4140 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 4141
b830ebc9 4142 if (dc_sink == NULL) {
e7b07cee
HW		 4143 DRM_ERROR("dc_sink is NULL!\n");
4144 goto fail;
4145 }
4146
b333730d 4147 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
b830ebc9 4148 if (stream == NULL) {
e7b07cee
HW		 4149 DRM_ERROR("Failed to create stream for sink!\n");
4150 goto fail;
4151 }
4152
a39438f0
HW		 4153 dc_result = dc_validate_stream(adev->dm.dc, stream);
4154
4155 if (dc_result == DC_OK)
e7b07cee 4156 result = MODE_OK;
a39438f0 4157 else
9f921b14 4158 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 4159 mode->vdisplay,
4160 mode->hdisplay,
9f921b14
HW		 4161 mode->clock,
4162 dc_result);
e7b07cee
HW		 4163
4164 dc_stream_release(stream);
4165
4166fail:
4167 /* TODO: error handling*/
4168 return result;
4169}
4170
88694af9
NK		 4171static int fill_hdr_info_packet(const struct drm_connector_state *state,
4172 struct dc_info_packet *out)
4173{
4174 struct hdmi_drm_infoframe frame;
4175 unsigned char buf[30]; /* 26 + 4 */
4176 ssize_t len;
4177 int ret, i;
4178
4179 memset(out, 0, sizeof(*out));
4180
4181 if (!state->hdr_output_metadata)
4182 return 0;
4183
4184 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
4185 if (ret)
4186 return ret;
4187
4188 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
4189 if (len < 0)
4190 return (int)len;
4191
4192 /* Static metadata is a fixed 26 bytes + 4 byte header. */
4193 if (len != 30)
4194 return -EINVAL;
4195
4196 /* Prepare the infopacket for DC. */
4197 switch (state->connector->connector_type) {
4198 case DRM_MODE_CONNECTOR_HDMIA:
4199 out->hb0 = 0x87; /* type */
4200 out->hb1 = 0x01; /* version */
4201 out->hb2 = 0x1A; /* length */
4202 out->sb[0] = buf[3]; /* checksum */
4203 i = 1;
4204 break;
4205
4206 case DRM_MODE_CONNECTOR_DisplayPort:
4207 case DRM_MODE_CONNECTOR_eDP:
4208 out->hb0 = 0x00; /* sdp id, zero */
4209 out->hb1 = 0x87; /* type */
4210 out->hb2 = 0x1D; /* payload len - 1 */
4211 out->hb3 = (0x13 << 2); /* sdp version */
4212 out->sb[0] = 0x01; /* version */
4213 out->sb[1] = 0x1A; /* length */
4214 i = 2;
4215 break;
4216
4217 default:
4218 return -EINVAL;
4219 }
4220
4221 memcpy(&out->sb[i], &buf[4], 26);
4222 out->valid = true;
4223
4224 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
4225 sizeof(out->sb), false);
4226
4227 return 0;
4228}
4229
4230static bool
4231is_hdr_metadata_different(const struct drm_connector_state *old_state,
4232 const struct drm_connector_state *new_state)
4233{
4234 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
4235 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
4236
4237 if (old_blob != new_blob) {
4238 if (old_blob && new_blob &&
4239 old_blob->length == new_blob->length)
4240 return memcmp(old_blob->data, new_blob->data,
4241 old_blob->length);
4242
4243 return true;
4244 }
4245
4246 return false;
4247}
4248
4249static int
4250amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
51e857af 4251 struct drm_atomic_state *state)
88694af9 4252{
51e857af
SP		 4253 struct drm_connector_state *new_con_state =
4254 drm_atomic_get_new_connector_state(state, conn);
88694af9
NK		 4255 struct drm_connector_state *old_con_state =
4256 drm_atomic_get_old_connector_state(state, conn);
4257 struct drm_crtc *crtc = new_con_state->crtc;
4258 struct drm_crtc_state *new_crtc_state;
4259 int ret;
4260
4261 if (!crtc)
4262 return 0;
4263
4264 if (is_hdr_metadata_different(old_con_state, new_con_state)) {
4265 struct dc_info_packet hdr_infopacket;
4266
4267 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
4268 if (ret)
4269 return ret;
4270
4271 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
4272 if (IS_ERR(new_crtc_state))
4273 return PTR_ERR(new_crtc_state);
4274
4275 /*
4276 * DC considers the stream backends changed if the
4277 * static metadata changes. Forcing the modeset also
4278 * gives a simple way for userspace to switch from
b232d4ed
NK		 4279 * 8bpc to 10bpc when setting the metadata to enter
4280 * or exit HDR.
4281 *
4282 * Changing the static metadata after it's been
4283 * set is permissible, however. So only force a
4284 * modeset if we're entering or exiting HDR.
88694af9 4285 */
b232d4ed
NK		 4286 new_crtc_state->mode_changed =
4287 !old_con_state->hdr_output_metadata ||
4288 !new_con_state->hdr_output_metadata;
88694af9
NK		 4289 }
4290
4291 return 0;
4292}
4293
e7b07cee
HW		 4294static const struct drm_connector_helper_funcs
4295amdgpu_dm_connector_helper_funcs = {
4296 /*
1f6010a9 4297 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 4298 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 4299 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 4300 * in get_modes call back, not just return the modes count
4301 */
e7b07cee
HW		 4302 .get_modes = get_modes,
4303 .mode_valid = amdgpu_dm_connector_mode_valid,
88694af9 4304 .atomic_check = amdgpu_dm_connector_atomic_check,
e7b07cee
HW		 4305};
4306
4307static void dm_crtc_helper_disable(struct drm_crtc *crtc)
4308{
4309}
4310
bc92c065
NK		 4311static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
4312{
4313 struct drm_device *dev = new_crtc_state->crtc->dev;
4314 struct drm_plane *plane;
4315
4316 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
4317 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4318 return true;
4319 }
4320
4321 return false;
4322}
4323
d6ef9b41 4324static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
c14a005c
NK		 4325{
4326 struct drm_atomic_state *state = new_crtc_state->state;
4327 struct drm_plane *plane;
4328 int num_active = 0;
4329
4330 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
4331 struct drm_plane_state *new_plane_state;
4332
4333 /* Cursor planes are "fake". */
4334 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4335 continue;
4336
4337 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
4338
4339 if (!new_plane_state) {
4340 /*
4341 * The plane is enable on the CRTC and hasn't changed
4342 * state. This means that it previously passed
4343 * validation and is therefore enabled.
4344 */
4345 num_active += 1;
4346 continue;
4347 }
4348
4349 /* We need a framebuffer to be considered enabled. */
4350 num_active += (new_plane_state->fb != NULL);
4351 }
4352
d6ef9b41
NK		 4353 return num_active;
4354}
4355
4356/*
4357 * Sets whether interrupts should be enabled on a specific CRTC.
4358 * We require that the stream be enabled and that there exist active
4359 * DC planes on the stream.
4360 */
4361static void
4362dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
4363 struct drm_crtc_state *new_crtc_state)
4364{
4365 struct dm_crtc_state *dm_new_crtc_state =
4366 to_dm_crtc_state(new_crtc_state);
4367
4368 dm_new_crtc_state->active_planes = 0;
4369 dm_new_crtc_state->interrupts_enabled = false;
4370
4371 if (!dm_new_crtc_state->stream)
4372 return;
4373
4374 dm_new_crtc_state->active_planes =
4375 count_crtc_active_planes(new_crtc_state);
4376
4377 dm_new_crtc_state->interrupts_enabled =
4378 dm_new_crtc_state->active_planes > 0;
c14a005c
NK		 4379}
4380
3ee6b26b
AD		 4381static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
4382 struct drm_crtc_state *state)
e7b07cee
HW		 4383{
4384 struct amdgpu_device *adev = crtc->dev->dev_private;
4385 struct dc *dc = adev->dm.dc;
4386 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
4387 int ret = -EINVAL;
4388
d6ef9b41
NK		 4389 /*
4390 * Update interrupt state for the CRTC. This needs to happen whenever
4391 * the CRTC has changed or whenever any of its planes have changed.
4392 * Atomic check satisfies both of these requirements since the CRTC
4393 * is added to the state by DRM during drm_atomic_helper_check_planes.
4394 */
4395 dm_update_crtc_interrupt_state(crtc, state);
4396
9b690ef3
BL		 4397 if (unlikely(!dm_crtc_state->stream &&
4398 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 4399 WARN_ON(1);
4400 return ret;
4401 }
4402
1f6010a9 4403 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 4404 if (!dm_crtc_state->stream)
4405 return 0;
4406
bc92c065
NK		 4407 /*
4408 * We want at least one hardware plane enabled to use
4409 * the stream with a cursor enabled.
4410 */
c14a005c 4411 if (state->enable && state->active &&
bc92c065 4412 does_crtc_have_active_cursor(state) &&
d6ef9b41 4413 dm_crtc_state->active_planes == 0)
c14a005c
NK		 4414 return -EINVAL;
4415
62c933f9 4416 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 4417 return 0;
4418
4419 return ret;
4420}
4421
3ee6b26b
AD		 4422static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4423 const struct drm_display_mode *mode,
4424 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 4425{
4426 return true;
4427}
4428
4429static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4430 .disable = dm_crtc_helper_disable,
4431 .atomic_check = dm_crtc_helper_atomic_check,
4432 .mode_fixup = dm_crtc_helper_mode_fixup
4433};
4434
4435static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4436{
4437
4438}
4439
3ee6b26b
AD		 4440static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4441 struct drm_crtc_state *crtc_state,
4442 struct drm_connector_state *conn_state)
e7b07cee
HW		 4443{
4444 return 0;
4445}
4446
4447const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4448 .disable = dm_encoder_helper_disable,
4449 .atomic_check = dm_encoder_helper_atomic_check
4450};
4451
4452static void dm_drm_plane_reset(struct drm_plane *plane)
4453{
4454 struct dm_plane_state *amdgpu_state = NULL;
4455
4456 if (plane->state)
4457 plane->funcs->atomic_destroy_state(plane, plane->state);
4458
4459 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 4460 WARN_ON(amdgpu_state == NULL);
1f6010a9 4461
7ddaef96
NK		 4462 if (amdgpu_state)
4463 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
e7b07cee
HW		 4464}
4465
4466static struct drm_plane_state *
4467dm_drm_plane_duplicate_state(struct drm_plane *plane)
4468{
4469 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4470
4471 old_dm_plane_state = to_dm_plane_state(plane->state);
4472 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4473 if (!dm_plane_state)
4474 return NULL;
4475
4476 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4477
3be5262e
HW		 4478 if (old_dm_plane_state->dc_state) {
4479 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4480 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 4481 }
4482
4483 return &dm_plane_state->base;
4484}
4485
4486void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 4487 struct drm_plane_state *state)
e7b07cee
HW		 4488{
4489 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4490
3be5262e
HW		 4491 if (dm_plane_state->dc_state)
4492 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 4493
0627bbd3 4494 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 4495}
4496
4497static const struct drm_plane_funcs dm_plane_funcs = {
4498 .update_plane = drm_atomic_helper_update_plane,
4499 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 4500 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 4501 .reset = dm_drm_plane_reset,
4502 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
4503 .atomic_destroy_state = dm_drm_plane_destroy_state,
4504};
4505
3ee6b26b
AD		 4506static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
4507 struct drm_plane_state *new_state)
e7b07cee
HW		 4508{
4509 struct amdgpu_framebuffer *afb;
4510 struct drm_gem_object *obj;
5d43be0c 4511 struct amdgpu_device *adev;
e7b07cee 4512 struct amdgpu_bo *rbo;
e7b07cee 4513 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
0f257b09
CZ		 4514 struct list_head list;
4515 struct ttm_validate_buffer tv;
4516 struct ww_acquire_ctx ticket;
e0634e8d 4517 uint64_t tiling_flags;
5d43be0c
CK		 4518 uint32_t domain;
4519 int r;
e7b07cee
HW		 4520
4521 dm_plane_state_old = to_dm_plane_state(plane->state);
4522 dm_plane_state_new = to_dm_plane_state(new_state);
4523
4524 if (!new_state->fb) {
f1ad2f5e 4525 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 4526 return 0;
4527 }
4528
4529 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 4530 obj = new_state->fb->obj[0];
e7b07cee 4531 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 4532 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
0f257b09
CZ		 4533 INIT_LIST_HEAD(&list);
4534
4535 tv.bo = &rbo->tbo;
4536 tv.num_shared = 1;
4537 list_add(&tv.head, &list);
4538
4539 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true);
4540 if (r) {
4541 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
e7b07cee 4542 return r;
0f257b09 4543 }
e7b07cee 4544
5d43be0c 4545 if (plane->type != DRM_PLANE_TYPE_CURSOR)
f2bd8a0e 4546 domain = amdgpu_display_supported_domains(adev, rbo->flags);
5d43be0c
CK		 4547 else
4548 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 4549
7b7c6c81 4550 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 4551 if (unlikely(r != 0)) {
30b7c614
HW		 4552 if (r != -ERESTARTSYS)
4553 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
0f257b09 4554 ttm_eu_backoff_reservation(&ticket, &list);
e7b07cee
HW		 4555 return r;
4556 }
4557
bb812f1e
JZ		 4558 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
4559 if (unlikely(r != 0)) {
4560 amdgpu_bo_unpin(rbo);
0f257b09 4561 ttm_eu_backoff_reservation(&ticket, &list);
bb812f1e 4562 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 4563 return r;
4564 }
7df7e505
NK		 4565
4566 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
4567
0f257b09 4568 ttm_eu_backoff_reservation(&ticket, &list);
bb812f1e 4569
7b7c6c81 4570 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 4571
4572 amdgpu_bo_ref(rbo);
4573
3be5262e
HW		 4574 if (dm_plane_state_new->dc_state &&
4575 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
4576 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 4577
320932bf 4578 fill_plane_buffer_attributes(
695af5f9
NK		 4579 adev, afb, plane_state->format, plane_state->rotation,
4580 tiling_flags, &plane_state->tiling_info,
320932bf 4581 &plane_state->plane_size, &plane_state->dcc,
695af5f9 4582 &plane_state->address);
e7b07cee
HW		 4583 }
4584
e7b07cee
HW		 4585 return 0;
4586}
4587
3ee6b26b
AD		 4588static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
4589 struct drm_plane_state *old_state)
e7b07cee
HW		 4590{
4591 struct amdgpu_bo *rbo;
e7b07cee
HW		 4592 int r;
4593
4594 if (!old_state->fb)
4595 return;
4596
e68d14dd 4597 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 4598 r = amdgpu_bo_reserve(rbo, false);
4599 if (unlikely(r)) {
4600 DRM_ERROR("failed to reserve rbo before unpin\n");
4601 return;
b830ebc9
HW		 4602 }
4603
4604 amdgpu_bo_unpin(rbo);
4605 amdgpu_bo_unreserve(rbo);
4606 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 4607}
4608
7578ecda
AD		 4609static int dm_plane_atomic_check(struct drm_plane *plane,
4610 struct drm_plane_state *state)
cbd19488
AG		 4611{
4612 struct amdgpu_device *adev = plane->dev->dev_private;
4613 struct dc *dc = adev->dm.dc;
78171832 4614 struct dm_plane_state *dm_plane_state;
695af5f9
NK		 4615 struct dc_scaling_info scaling_info;
4616 int ret;
78171832
NK		 4617
4618 dm_plane_state = to_dm_plane_state(state);
cbd19488 4619
3be5262e 4620 if (!dm_plane_state->dc_state)
9a3329b1 4621 return 0;
cbd19488 4622
695af5f9
NK		 4623 ret = fill_dc_scaling_info(state, &scaling_info);
4624 if (ret)
4625 return ret;
a05bcff1 4626
62c933f9 4627 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 4628 return 0;
4629
4630 return -EINVAL;
4631}
4632
674e78ac
NK		 4633static int dm_plane_atomic_async_check(struct drm_plane *plane,
4634 struct drm_plane_state *new_plane_state)
4635{
4636 /* Only support async updates on cursor planes. */
4637 if (plane->type != DRM_PLANE_TYPE_CURSOR)
4638 return -EINVAL;
4639
4640 return 0;
4641}
4642
4643static void dm_plane_atomic_async_update(struct drm_plane *plane,
4644 struct drm_plane_state *new_state)
4645{
4646 struct drm_plane_state *old_state =
4647 drm_atomic_get_old_plane_state(new_state->state, plane);
4648
332af874 4649 swap(plane->state->fb, new_state->fb);
674e78ac
NK		 4650
4651 plane->state->src_x = new_state->src_x;
4652 plane->state->src_y = new_state->src_y;
4653 plane->state->src_w = new_state->src_w;
4654 plane->state->src_h = new_state->src_h;
4655 plane->state->crtc_x = new_state->crtc_x;
4656 plane->state->crtc_y = new_state->crtc_y;
4657 plane->state->crtc_w = new_state->crtc_w;
4658 plane->state->crtc_h = new_state->crtc_h;
4659
4660 handle_cursor_update(plane, old_state);
4661}
4662
e7b07cee
HW		 4663static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
4664 .prepare_fb = dm_plane_helper_prepare_fb,
4665 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 4666 .atomic_check = dm_plane_atomic_check,
674e78ac
NK		 4667 .atomic_async_check = dm_plane_atomic_async_check,
4668 .atomic_async_update = dm_plane_atomic_async_update
e7b07cee
HW		 4669};
4670
4671/*
4672 * TODO: these are currently initialized to rgb formats only.
4673 * For future use cases we should either initialize them dynamically based on
4674 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 4675 * check will succeed, and let DC implement proper check
e7b07cee 4676 */
d90371b0 4677static const uint32_t rgb_formats[] = {
e7b07cee
HW		 4678 DRM_FORMAT_XRGB8888,
4679 DRM_FORMAT_ARGB8888,
4680 DRM_FORMAT_RGBA8888,
4681 DRM_FORMAT_XRGB2101010,
4682 DRM_FORMAT_XBGR2101010,
4683 DRM_FORMAT_ARGB2101010,
4684 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 4685 DRM_FORMAT_XBGR8888,
4686 DRM_FORMAT_ABGR8888,
46dd9ff7 4687 DRM_FORMAT_RGB565,
e7b07cee
HW		 4688};
4689
0d579c7e
NK		 4690static const uint32_t overlay_formats[] = {
4691 DRM_FORMAT_XRGB8888,
4692 DRM_FORMAT_ARGB8888,
4693 DRM_FORMAT_RGBA8888,
4694 DRM_FORMAT_XBGR8888,
4695 DRM_FORMAT_ABGR8888,
7267a1a9 4696 DRM_FORMAT_RGB565
e7b07cee
HW		 4697};
4698
4699static const u32 cursor_formats[] = {
4700 DRM_FORMAT_ARGB8888
4701};
4702
37c6a93b
NK		 4703static int get_plane_formats(const struct drm_plane *plane,
4704 const struct dc_plane_cap *plane_cap,
4705 uint32_t *formats, int max_formats)
e7b07cee 4706{
37c6a93b
NK		 4707 int i, num_formats = 0;
4708
4709 /*
4710 * TODO: Query support for each group of formats directly from
4711 * DC plane caps. This will require adding more formats to the
4712 * caps list.
4713 */
e7b07cee 4714
f180b4bc 4715 switch (plane->type) {
e7b07cee 4716 case DRM_PLANE_TYPE_PRIMARY:
37c6a93b
NK		 4717 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
4718 if (num_formats >= max_formats)
4719 break;
4720
4721 formats[num_formats++] = rgb_formats[i];
4722 }
4723
ea36ad34 4724 if (plane_cap && plane_cap->pixel_format_support.nv12)
37c6a93b 4725 formats[num_formats++] = DRM_FORMAT_NV12;
e7b07cee 4726 break;
37c6a93b 4727
e7b07cee 4728 case DRM_PLANE_TYPE_OVERLAY:
37c6a93b
NK		 4729 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
4730 if (num_formats >= max_formats)
4731 break;
4732
4733 formats[num_formats++] = overlay_formats[i];
4734 }
e7b07cee 4735 break;
37c6a93b 4736
e7b07cee 4737 case DRM_PLANE_TYPE_CURSOR:
37c6a93b
NK		 4738 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
4739 if (num_formats >= max_formats)
4740 break;
4741
4742 formats[num_formats++] = cursor_formats[i];
4743 }
e7b07cee
HW		 4744 break;
4745 }
4746
37c6a93b
NK		 4747 return num_formats;
4748}
4749
4750static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4751 struct drm_plane *plane,
4752 unsigned long possible_crtcs,
4753 const struct dc_plane_cap *plane_cap)
4754{
4755 uint32_t formats[32];
4756 int num_formats;
4757 int res = -EPERM;
4758
4759 num_formats = get_plane_formats(plane, plane_cap, formats,
4760 ARRAY_SIZE(formats));
4761
4762 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
4763 &dm_plane_funcs, formats, num_formats,
4764 NULL, plane->type, NULL);
4765 if (res)
4766 return res;
4767
cc1fec57
NK		 4768 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4769 plane_cap && plane_cap->per_pixel_alpha) {
d74004b6
NK		 4770 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4771 BIT(DRM_MODE_BLEND_PREMULTI);
4772
4773 drm_plane_create_alpha_property(plane);
4774 drm_plane_create_blend_mode_property(plane, blend_caps);
4775 }
4776
fc8e5230 4777 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
ea36ad34 4778 plane_cap && plane_cap->pixel_format_support.nv12) {
fc8e5230
NK		 4779 /* This only affects YUV formats. */
4780 drm_plane_create_color_properties(
4781 plane,
4782 BIT(DRM_COLOR_YCBCR_BT601) |
4783 BIT(DRM_COLOR_YCBCR_BT709),
4784 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
4785 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
4786 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
4787 }
4788
f180b4bc 4789 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 4790
96719c54 4791 /* Create (reset) the plane state */
f180b4bc
HW		 4792 if (plane->funcs->reset)
4793 plane->funcs->reset(plane);
96719c54 4794
37c6a93b 4795 return 0;
e7b07cee
HW		 4796}
4797
7578ecda
AD		 4798static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
4799 struct drm_plane *plane,
4800 uint32_t crtc_index)
e7b07cee
HW		 4801{
4802 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 4803 struct drm_plane *cursor_plane;
e7b07cee
HW		 4804
4805 int res = -ENOMEM;
4806
4807 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
4808 if (!cursor_plane)
4809 goto fail;
4810
f180b4bc 4811 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
cc1fec57 4812 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
e7b07cee
HW		 4813
4814 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
4815 if (!acrtc)
4816 goto fail;
4817
4818 res = drm_crtc_init_with_planes(
4819 dm->ddev,
4820 &acrtc->base,
4821 plane,
f180b4bc 4822 cursor_plane,
e7b07cee
HW		 4823 &amdgpu_dm_crtc_funcs, NULL);
4824
4825 if (res)
4826 goto fail;
4827
4828 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
4829
96719c54
HW		 4830 /* Create (reset) the plane state */
4831 if (acrtc->base.funcs->reset)
4832 acrtc->base.funcs->reset(&acrtc->base);
4833
e7b07cee
HW		 4834 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
4835 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4836
4837 acrtc->crtc_id = crtc_index;
4838 acrtc->base.enabled = false;
c37e2d29 4839 acrtc->otg_inst = -1;
e7b07cee
HW		 4840
4841 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 4842 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
4843 true, MAX_COLOR_LUT_ENTRIES);
086247a4 4844 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 4845
4846 return 0;
4847
4848fail:
b830ebc9
HW		 4849 kfree(acrtc);
4850 kfree(cursor_plane);
e7b07cee
HW		 4851 return res;
4852}
4853
4854
4855static int to_drm_connector_type(enum signal_type st)
4856{
4857 switch (st) {
4858 case SIGNAL_TYPE_HDMI_TYPE_A:
4859 return DRM_MODE_CONNECTOR_HDMIA;
4860 case SIGNAL_TYPE_EDP:
4861 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 4862 case SIGNAL_TYPE_LVDS:
4863 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 4864 case SIGNAL_TYPE_RGB:
4865 return DRM_MODE_CONNECTOR_VGA;
4866 case SIGNAL_TYPE_DISPLAY_PORT:
4867 case SIGNAL_TYPE_DISPLAY_PORT_MST:
4868 return DRM_MODE_CONNECTOR_DisplayPort;
4869 case SIGNAL_TYPE_DVI_DUAL_LINK:
4870 case SIGNAL_TYPE_DVI_SINGLE_LINK:
4871 return DRM_MODE_CONNECTOR_DVID;
4872 case SIGNAL_TYPE_VIRTUAL:
4873 return DRM_MODE_CONNECTOR_VIRTUAL;
4874
4875 default:
4876 return DRM_MODE_CONNECTOR_Unknown;
4877 }
4878}
4879
2b4c1c05
DV		 4880static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
4881{
4882 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
4883}
4884
e7b07cee
HW		 4885static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
4886{
e7b07cee
HW		 4887 struct drm_encoder *encoder;
4888 struct amdgpu_encoder *amdgpu_encoder;
4889
2b4c1c05 4890 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 4891
4892 if (encoder == NULL)
4893 return;
4894
4895 amdgpu_encoder = to_amdgpu_encoder(encoder);
4896
4897 amdgpu_encoder->native_mode.clock = 0;
4898
4899 if (!list_empty(&connector->probed_modes)) {
4900 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 4901
e7b07cee 4902 list_for_each_entry(preferred_mode,
b830ebc9
HW		 4903 &connector->probed_modes,
4904 head) {
4905 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
4906 amdgpu_encoder->native_mode = *preferred_mode;
4907
e7b07cee
HW		 4908 break;
4909 }
4910
4911 }
4912}
4913
3ee6b26b
AD		 4914static struct drm_display_mode *
4915amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4916 char *name,
4917 int hdisplay, int vdisplay)
e7b07cee
HW		 4918{
4919 struct drm_device *dev = encoder->dev;
4920 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4921 struct drm_display_mode *mode = NULL;
4922 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4923
4924 mode = drm_mode_duplicate(dev, native_mode);
4925
b830ebc9 4926 if (mode == NULL)
e7b07cee
HW		 4927 return NULL;
4928
4929 mode->hdisplay = hdisplay;
4930 mode->vdisplay = vdisplay;
4931 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 4932 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 4933
4934 return mode;
4935
4936}
4937
4938static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 4939 struct drm_connector *connector)
e7b07cee
HW		 4940{
4941 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4942 struct drm_display_mode *mode = NULL;
4943 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 4944 struct amdgpu_dm_connector *amdgpu_dm_connector =
4945 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4946 int i;
4947 int n;
4948 struct mode_size {
4949 char name[DRM_DISPLAY_MODE_LEN];
4950 int w;
4951 int h;
b830ebc9 4952 } common_modes[] = {
e7b07cee
HW		 4953 { "640x480", 640, 480},
4954 { "800x600", 800, 600},
4955 { "1024x768", 1024, 768},
4956 { "1280x720", 1280, 720},
4957 { "1280x800", 1280, 800},
4958 {"1280x1024", 1280, 1024},
4959 { "1440x900", 1440, 900},
4960 {"1680x1050", 1680, 1050},
4961 {"1600x1200", 1600, 1200},
4962 {"1920x1080", 1920, 1080},
4963 {"1920x1200", 1920, 1200}
4964 };
4965
b830ebc9 4966 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 4967
4968 for (i = 0; i < n; i++) {
4969 struct drm_display_mode *curmode = NULL;
4970 bool mode_existed = false;
4971
4972 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 4973 common_modes[i].h > native_mode->vdisplay ||
4974 (common_modes[i].w == native_mode->hdisplay &&
4975 common_modes[i].h == native_mode->vdisplay))
4976 continue;
e7b07cee
HW		 4977
4978 list_for_each_entry(curmode, &connector->probed_modes, head) {
4979 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 4980 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 4981 mode_existed = true;
4982 break;
4983 }
4984 }
4985
4986 if (mode_existed)
4987 continue;
4988
4989 mode = amdgpu_dm_create_common_mode(encoder,
4990 common_modes[i].name, common_modes[i].w,
4991 common_modes[i].h);
4992 drm_mode_probed_add(connector, mode);
c84dec2f 4993 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 4994 }
4995}
4996
3ee6b26b
AD		 4997static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4998 struct edid *edid)
e7b07cee 4999{
c84dec2f
HW		 5000 struct amdgpu_dm_connector *amdgpu_dm_connector =
5001 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5002
5003 if (edid) {
5004 /* empty probed_modes */
5005 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 5006 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 5007 drm_add_edid_modes(connector, edid);
5008
f1e5e913
YMM		 5009 /* sorting the probed modes before calling function
5010 * amdgpu_dm_get_native_mode() since EDID can have
5011 * more than one preferred mode. The modes that are
5012 * later in the probed mode list could be of higher
5013 * and preferred resolution. For example, 3840x2160
5014 * resolution in base EDID preferred timing and 4096x2160
5015 * preferred resolution in DID extension block later.
5016 */
5017 drm_mode_sort(&connector->probed_modes);
e7b07cee 5018 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 5019 } else {
c84dec2f 5020 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 5021 }
e7b07cee
HW		 5022}
5023
7578ecda 5024static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 5025{
c84dec2f
HW		 5026 struct amdgpu_dm_connector *amdgpu_dm_connector =
5027 to_amdgpu_dm_connector(connector);
e7b07cee 5028 struct drm_encoder *encoder;
c84dec2f 5029 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 5030
2b4c1c05 5031 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 5032
85ee15d6 5033 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 5034 amdgpu_dm_connector->num_modes =
5035 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 5036 } else {
5037 amdgpu_dm_connector_ddc_get_modes(connector, edid);
5038 amdgpu_dm_connector_add_common_modes(encoder, connector);
5039 }
3e332d3a 5040 amdgpu_dm_fbc_init(connector);
5099114b 5041
c84dec2f 5042 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 5043}
5044
3ee6b26b
AD		 5045void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
5046 struct amdgpu_dm_connector *aconnector,
5047 int connector_type,
5048 struct dc_link *link,
5049 int link_index)
e7b07cee
HW		 5050{
5051 struct amdgpu_device *adev = dm->ddev->dev_private;
5052
f04bee34
NK		 5053 /*
5054 * Some of the properties below require access to state, like bpc.
5055 * Allocate some default initial connector state with our reset helper.
5056 */
5057 if (aconnector->base.funcs->reset)
5058 aconnector->base.funcs->reset(&aconnector->base);
5059
e7b07cee
HW		 5060 aconnector->connector_id = link_index;
5061 aconnector->dc_link = link;
5062 aconnector->base.interlace_allowed = false;
5063 aconnector->base.doublescan_allowed = false;
5064 aconnector->base.stereo_allowed = false;
5065 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
5066 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
6ce8f316 5067 aconnector->audio_inst = -1;
e7b07cee
HW		 5068 mutex_init(&aconnector->hpd_lock);
5069
1f6010a9
DF		 5070 /*
5071 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 5072 * which means HPD hot plug not supported
5073 */
e7b07cee
HW		 5074 switch (connector_type) {
5075 case DRM_MODE_CONNECTOR_HDMIA:
5076 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 5077 aconnector->base.ycbcr_420_allowed =
9ea59d5a 5078 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 5079 break;
5080 case DRM_MODE_CONNECTOR_DisplayPort:
5081 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 5082 aconnector->base.ycbcr_420_allowed =
9ea59d5a 5083 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 5084 break;
5085 case DRM_MODE_CONNECTOR_DVID:
5086 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5087 break;
5088 default:
5089 break;
5090 }
5091
5092 drm_object_attach_property(&aconnector->base.base,
5093 dm->ddev->mode_config.scaling_mode_property,
5094 DRM_MODE_SCALE_NONE);
5095
5096 drm_object_attach_property(&aconnector->base.base,
5097 adev->mode_info.underscan_property,
5098 UNDERSCAN_OFF);
5099 drm_object_attach_property(&aconnector->base.base,
5100 adev->mode_info.underscan_hborder_property,
5101 0);
5102 drm_object_attach_property(&aconnector->base.base,
5103 adev->mode_info.underscan_vborder_property,
5104 0);
1825fd34
NK		 5105
5106 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
5107
5108 /* This defaults to the max in the range, but we want 8bpc. */
5109 aconnector->base.state->max_bpc = 8;
5110 aconnector->base.state->max_requested_bpc = 8;
e7b07cee 5111
c1ee92f9
DF		 5112 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5113 dc_is_dmcu_initialized(adev->dm.dc)) {
5114 drm_object_attach_property(&aconnector->base.base,
5115 adev->mode_info.abm_level_property, 0);
5116 }
bb47de73
NK		 5117
5118 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7fad8da1
NK		 5119 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5120 connector_type == DRM_MODE_CONNECTOR_eDP) {
88694af9
NK		 5121 drm_object_attach_property(
5122 &aconnector->base.base,
5123 dm->ddev->mode_config.hdr_output_metadata_property, 0);
5124
bb47de73
NK		 5125 drm_connector_attach_vrr_capable_property(
5126 &aconnector->base);
5127 }
e7b07cee
HW		 5128}
5129
7578ecda
AD		 5130static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
5131 struct i2c_msg *msgs, int num)
e7b07cee
HW		 5132{
5133 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
5134 struct ddc_service *ddc_service = i2c->ddc_service;
5135 struct i2c_command cmd;
5136 int i;
5137 int result = -EIO;
5138
b830ebc9 5139 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 5140
5141 if (!cmd.payloads)
5142 return result;
5143
5144 cmd.number_of_payloads = num;
5145 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
5146 cmd.speed = 100;
5147
5148 for (i = 0; i < num; i++) {
5149 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
5150 cmd.payloads[i].address = msgs[i].addr;
5151 cmd.payloads[i].length = msgs[i].len;
5152 cmd.payloads[i].data = msgs[i].buf;
5153 }
5154
c85e6e54
DF		 5155 if (dc_submit_i2c(
5156 ddc_service->ctx->dc,
5157 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 5158 &cmd))
5159 result = num;
5160
5161 kfree(cmd.payloads);
5162 return result;
5163}
5164
7578ecda 5165static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 5166{
5167 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
5168}
5169
5170static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
5171 .master_xfer = amdgpu_dm_i2c_xfer,
5172 .functionality = amdgpu_dm_i2c_func,
5173};
5174
3ee6b26b
AD		 5175static struct amdgpu_i2c_adapter *
5176create_i2c(struct ddc_service *ddc_service,
5177 int link_index,
5178 int *res)
e7b07cee
HW		 5179{
5180 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
5181 struct amdgpu_i2c_adapter *i2c;
5182
b830ebc9 5183 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 5184 if (!i2c)
5185 return NULL;
e7b07cee
HW		 5186 i2c->base.owner = THIS_MODULE;
5187 i2c->base.class = I2C_CLASS_DDC;
5188 i2c->base.dev.parent = &adev->pdev->dev;
5189 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 5190 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 5191 i2c_set_adapdata(&i2c->base, i2c);
5192 i2c->ddc_service = ddc_service;
c85e6e54 5193 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 5194
5195 return i2c;
5196}
5197
89fc8d4e 5198
1f6010a9
DF		 5199/*
5200 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 5201 * dc_link which will be represented by this aconnector.
5202 */
7578ecda
AD		 5203static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
5204 struct amdgpu_dm_connector *aconnector,
5205 uint32_t link_index,
5206 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 5207{
5208 int res = 0;
5209 int connector_type;
5210 struct dc *dc = dm->dc;
5211 struct dc_link *link = dc_get_link_at_index(dc, link_index);
5212 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 5213
5214 link->priv = aconnector;
e7b07cee 5215
f1ad2f5e 5216 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 5217
5218 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 5219 if (!i2c) {
5220 DRM_ERROR("Failed to create i2c adapter data\n");
5221 return -ENOMEM;
5222 }
5223
e7b07cee
HW		 5224 aconnector->i2c = i2c;
5225 res = i2c_add_adapter(&i2c->base);
5226
5227 if (res) {
5228 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
5229 goto out_free;
5230 }
5231
5232 connector_type = to_drm_connector_type(link->connector_signal);
5233
5234 res = drm_connector_init(
5235 dm->ddev,
5236 &aconnector->base,
5237 &amdgpu_dm_connector_funcs,
5238 connector_type);
5239
5240 if (res) {
5241 DRM_ERROR("connector_init failed\n");
5242 aconnector->connector_id = -1;
5243 goto out_free;
5244 }
5245
5246 drm_connector_helper_add(
5247 &aconnector->base,
5248 &amdgpu_dm_connector_helper_funcs);
5249
5250 amdgpu_dm_connector_init_helper(
5251 dm,
5252 aconnector,
5253 connector_type,
5254 link,
5255 link_index);
5256
cde4c44d 5257 drm_connector_attach_encoder(
e7b07cee
HW		 5258 &aconnector->base, &aencoder->base);
5259
5260 drm_connector_register(&aconnector->base);
dc38fd9d 5261#if defined(CONFIG_DEBUG_FS)
4be8be78 5262 connector_debugfs_init(aconnector);
f258fee6
DF		 5263 aconnector->debugfs_dpcd_address = 0;
5264 aconnector->debugfs_dpcd_size = 0;
dc38fd9d 5265#endif
e7b07cee
HW		 5266
5267 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
5268 || connector_type == DRM_MODE_CONNECTOR_eDP)
5269 amdgpu_dm_initialize_dp_connector(dm, aconnector);
5270
e7b07cee
HW		 5271out_free:
5272 if (res) {
5273 kfree(i2c);
5274 aconnector->i2c = NULL;
5275 }
5276 return res;
5277}
5278
5279int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
5280{
5281 switch (adev->mode_info.num_crtc) {
5282 case 1:
5283 return 0x1;
5284 case 2:
5285 return 0x3;
5286 case 3:
5287 return 0x7;
5288 case 4:
5289 return 0xf;
5290 case 5:
5291 return 0x1f;
5292 case 6:
5293 default:
5294 return 0x3f;
5295 }
5296}
5297
7578ecda
AD		 5298static int amdgpu_dm_encoder_init(struct drm_device *dev,
5299 struct amdgpu_encoder *aencoder,
5300 uint32_t link_index)
e7b07cee
HW		 5301{
5302 struct amdgpu_device *adev = dev->dev_private;
5303
5304 int res = drm_encoder_init(dev,
5305 &aencoder->base,
5306 &amdgpu_dm_encoder_funcs,
5307 DRM_MODE_ENCODER_TMDS,
5308 NULL);
5309
5310 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
5311
5312 if (!res)
5313 aencoder->encoder_id = link_index;
5314 else
5315 aencoder->encoder_id = -1;
5316
5317 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
5318
5319 return res;
5320}
5321
3ee6b26b
AD		 5322static void manage_dm_interrupts(struct amdgpu_device *adev,
5323 struct amdgpu_crtc *acrtc,
5324 bool enable)
e7b07cee
HW		 5325{
5326 /*
5327 * this is not correct translation but will work as soon as VBLANK
5328 * constant is the same as PFLIP
5329 */
5330 int irq_type =
734dd01d 5331 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 5332 adev,
5333 acrtc->crtc_id);
5334
5335 if (enable) {
5336 drm_crtc_vblank_on(&acrtc->base);
5337 amdgpu_irq_get(
5338 adev,
5339 &adev->pageflip_irq,
5340 irq_type);
5341 } else {
5342
5343 amdgpu_irq_put(
5344 adev,
5345 &adev->pageflip_irq,
5346 irq_type);
5347 drm_crtc_vblank_off(&acrtc->base);
5348 }
5349}
5350
3ee6b26b
AD		 5351static bool
5352is_scaling_state_different(const struct dm_connector_state *dm_state,
5353 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 5354{
5355 if (dm_state->scaling != old_dm_state->scaling)
5356 return true;
5357 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
5358 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
5359 return true;
5360 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
5361 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
5362 return true;
b830ebc9
HW		 5363 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
5364 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
5365 return true;
e7b07cee
HW		 5366 return false;
5367}
5368
3ee6b26b
AD		 5369static void remove_stream(struct amdgpu_device *adev,
5370 struct amdgpu_crtc *acrtc,
5371 struct dc_stream_state *stream)
e7b07cee
HW		 5372{
5373 /* this is the update mode case */
e7b07cee
HW		 5374
5375 acrtc->otg_inst = -1;
5376 acrtc->enabled = false;
5377}
5378
7578ecda
AD		 5379static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
5380 struct dc_cursor_position *position)
2a8f6ccb 5381{
f4c2cc43 5382 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 5383 int x, y;
5384 int xorigin = 0, yorigin = 0;
5385
e371e19c
NK		 5386 position->enable = false;
5387 position->x = 0;
5388 position->y = 0;
5389
5390 if (!crtc || !plane->state->fb)
2a8f6ccb 5391 return 0;
2a8f6ccb
HW		 5392
5393 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
5394 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
5395 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
5396 __func__,
5397 plane->state->crtc_w,
5398 plane->state->crtc_h);
5399 return -EINVAL;
5400 }
5401
5402 x = plane->state->crtc_x;
5403 y = plane->state->crtc_y;
c14a005c 5404
e371e19c
NK		 5405 if (x <= -amdgpu_crtc->max_cursor_width ||
5406 y <= -amdgpu_crtc->max_cursor_height)
5407 return 0;
5408
c14a005c
NK		 5409 if (crtc->primary->state) {
5410 /* avivo cursor are offset into the total surface */
5411 x += crtc->primary->state->src_x >> 16;
5412 y += crtc->primary->state->src_y >> 16;
5413 }
5414
2a8f6ccb
HW		 5415 if (x < 0) {
5416 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
5417 x = 0;
5418 }
5419 if (y < 0) {
5420 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
5421 y = 0;
5422 }
5423 position->enable = true;
5424 position->x = x;
5425 position->y = y;
5426 position->x_hotspot = xorigin;
5427 position->y_hotspot = yorigin;
5428
5429 return 0;
5430}
5431
3ee6b26b
AD		 5432static void handle_cursor_update(struct drm_plane *plane,
5433 struct drm_plane_state *old_plane_state)
e7b07cee 5434{
674e78ac 5435 struct amdgpu_device *adev = plane->dev->dev_private;
2a8f6ccb
HW		 5436 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
5437 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
5438 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
5439 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5440 uint64_t address = afb ? afb->address : 0;
5441 struct dc_cursor_position position;
5442 struct dc_cursor_attributes attributes;
5443 int ret;
5444
e7b07cee
HW		 5445 if (!plane->state->fb && !old_plane_state->fb)
5446 return;
5447
f1ad2f5e 5448 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 5449 __func__,
5450 amdgpu_crtc->crtc_id,
5451 plane->state->crtc_w,
5452 plane->state->crtc_h);
2a8f6ccb
HW		 5453
5454 ret = get_cursor_position(plane, crtc, &position);
5455 if (ret)
5456 return;
5457
5458 if (!position.enable) {
5459 /* turn off cursor */
674e78ac
NK		 5460 if (crtc_state && crtc_state->stream) {
5461 mutex_lock(&adev->dm.dc_lock);
2a8f6ccb
HW		 5462 dc_stream_set_cursor_position(crtc_state->stream,
5463 &position);
674e78ac
NK		 5464 mutex_unlock(&adev->dm.dc_lock);
5465 }
2a8f6ccb 5466 return;
e7b07cee 5467 }
e7b07cee 5468
2a8f6ccb
HW		 5469 amdgpu_crtc->cursor_width = plane->state->crtc_w;
5470 amdgpu_crtc->cursor_height = plane->state->crtc_h;
5471
c1cefe11 5472 memset(&attributes, 0, sizeof(attributes));
2a8f6ccb
HW		 5473 attributes.address.high_part = upper_32_bits(address);
5474 attributes.address.low_part = lower_32_bits(address);
5475 attributes.width = plane->state->crtc_w;
5476 attributes.height = plane->state->crtc_h;
5477 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
5478 attributes.rotation_angle = 0;
5479 attributes.attribute_flags.value = 0;
5480
5481 attributes.pitch = attributes.width;
5482
886daac9 5483 if (crtc_state->stream) {
674e78ac 5484 mutex_lock(&adev->dm.dc_lock);
886daac9
JZ		 5485 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
5486 &attributes))
5487 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 5488
2a8f6ccb
HW		 5489 if (!dc_stream_set_cursor_position(crtc_state->stream,
5490 &position))
5491 DRM_ERROR("DC failed to set cursor position\n");
674e78ac 5492 mutex_unlock(&adev->dm.dc_lock);
886daac9 5493 }
2a8f6ccb 5494}
e7b07cee
HW		 5495
5496static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
5497{
5498
5499 assert_spin_locked(&acrtc->base.dev->event_lock);
5500 WARN_ON(acrtc->event);
5501
5502 acrtc->event = acrtc->base.state->event;
5503
5504 /* Set the flip status */
5505 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
5506
5507 /* Mark this event as consumed */
5508 acrtc->base.state->event = NULL;
5509
5510 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
5511 acrtc->crtc_id);
5512}
5513
bb47de73
NK		 5514static void update_freesync_state_on_stream(
5515 struct amdgpu_display_manager *dm,
5516 struct dm_crtc_state *new_crtc_state,
180db303
NK		 5517 struct dc_stream_state *new_stream,
5518 struct dc_plane_state *surface,
5519 u32 flip_timestamp_in_us)
bb47de73 5520{
09aef2c4 5521 struct mod_vrr_params vrr_params;
bb47de73 5522 struct dc_info_packet vrr_infopacket = {0};
09aef2c4
MK		 5523 struct amdgpu_device *adev = dm->adev;
5524 unsigned long flags;
bb47de73
NK		 5525
5526 if (!new_stream)
5527 return;
5528
5529 /*
5530 * TODO: Determine why min/max totals and vrefresh can be 0 here.
5531 * For now it's sufficient to just guard against these conditions.
5532 */
5533
5534 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5535 return;
5536
09aef2c4
MK		 5537 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5538 vrr_params = new_crtc_state->vrr_params;
5539
180db303
NK		 5540 if (surface) {
5541 mod_freesync_handle_preflip(
5542 dm->freesync_module,
5543 surface,
5544 new_stream,
5545 flip_timestamp_in_us,
5546 &vrr_params);
09aef2c4
MK		 5547
5548 if (adev->family < AMDGPU_FAMILY_AI &&
5549 amdgpu_dm_vrr_active(new_crtc_state)) {
5550 mod_freesync_handle_v_update(dm->freesync_module,
5551 new_stream, &vrr_params);
e63e2491
EB		 5552
5553 /* Need to call this before the frame ends. */
5554 dc_stream_adjust_vmin_vmax(dm->dc,
5555 new_crtc_state->stream,
5556 &vrr_params.adjust);
09aef2c4 5557 }
180db303 5558 }
bb47de73
NK		 5559
5560 mod_freesync_build_vrr_infopacket(
5561 dm->freesync_module,
5562 new_stream,
180db303 5563 &vrr_params,
ecd0136b
HT		 5564 PACKET_TYPE_VRR,
5565 TRANSFER_FUNC_UNKNOWN,
bb47de73
NK		 5566 &vrr_infopacket);
5567
8a48b44c 5568 new_crtc_state->freesync_timing_changed |=
180db303
NK		 5569 (memcmp(&new_crtc_state->vrr_params.adjust,
5570 &vrr_params.adjust,
5571 sizeof(vrr_params.adjust)) != 0);
bb47de73 5572
8a48b44c 5573 new_crtc_state->freesync_vrr_info_changed |=
bb47de73
NK		 5574 (memcmp(&new_crtc_state->vrr_infopacket,
5575 &vrr_infopacket,
5576 sizeof(vrr_infopacket)) != 0);
5577
180db303 5578 new_crtc_state->vrr_params = vrr_params;
bb47de73
NK		 5579 new_crtc_state->vrr_infopacket = vrr_infopacket;
5580
180db303 5581 new_stream->adjust = new_crtc_state->vrr_params.adjust;
bb47de73
NK		 5582 new_stream->vrr_infopacket = vrr_infopacket;
5583
5584 if (new_crtc_state->freesync_vrr_info_changed)
5585 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
5586 new_crtc_state->base.crtc->base.id,
5587 (int)new_crtc_state->base.vrr_enabled,
180db303 5588 (int)vrr_params.state);
09aef2c4
MK		 5589
5590 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
bb47de73
NK		 5591}
5592
e854194c
MK		 5593static void pre_update_freesync_state_on_stream(
5594 struct amdgpu_display_manager *dm,
5595 struct dm_crtc_state *new_crtc_state)
5596{
5597 struct dc_stream_state *new_stream = new_crtc_state->stream;
09aef2c4 5598 struct mod_vrr_params vrr_params;
e854194c 5599 struct mod_freesync_config config = new_crtc_state->freesync_config;
09aef2c4
MK		 5600 struct amdgpu_device *adev = dm->adev;
5601 unsigned long flags;
e854194c
MK		 5602
5603 if (!new_stream)
5604 return;
5605
5606 /*
5607 * TODO: Determine why min/max totals and vrefresh can be 0 here.
5608 * For now it's sufficient to just guard against these conditions.
5609 */
5610 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5611 return;
5612
09aef2c4
MK		 5613 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5614 vrr_params = new_crtc_state->vrr_params;
5615
e854194c
MK		 5616 if (new_crtc_state->vrr_supported &&
5617 config.min_refresh_in_uhz &&
5618 config.max_refresh_in_uhz) {
5619 config.state = new_crtc_state->base.vrr_enabled ?
5620 VRR_STATE_ACTIVE_VARIABLE :
5621 VRR_STATE_INACTIVE;
5622 } else {
5623 config.state = VRR_STATE_UNSUPPORTED;
5624 }
5625
5626 mod_freesync_build_vrr_params(dm->freesync_module,
5627 new_stream,
5628 &config, &vrr_params);
5629
5630 new_crtc_state->freesync_timing_changed |=
5631 (memcmp(&new_crtc_state->vrr_params.adjust,
5632 &vrr_params.adjust,
5633 sizeof(vrr_params.adjust)) != 0);
5634
5635 new_crtc_state->vrr_params = vrr_params;
09aef2c4 5636 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
e854194c
MK		 5637}
5638
66b0c973
MK		 5639static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
5640 struct dm_crtc_state *new_state)
5641{
5642 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
5643 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
5644
5645 if (!old_vrr_active && new_vrr_active) {
5646 /* Transition VRR inactive -> active:
5647 * While VRR is active, we must not disable vblank irq, as a
5648 * reenable after disable would compute bogus vblank/pflip
5649 * timestamps if it likely happened inside display front-porch.
d2574c33
MK		 5650 *
5651 * We also need vupdate irq for the actual core vblank handling
5652 * at end of vblank.
66b0c973 5653 */
d2574c33 5654 dm_set_vupdate_irq(new_state->base.crtc, true);
66b0c973
MK		 5655 drm_crtc_vblank_get(new_state->base.crtc);
5656 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
5657 __func__, new_state->base.crtc->base.id);
5658 } else if (old_vrr_active && !new_vrr_active) {
5659 /* Transition VRR active -> inactive:
5660 * Allow vblank irq disable again for fixed refresh rate.
5661 */
d2574c33 5662 dm_set_vupdate_irq(new_state->base.crtc, false);
66b0c973
MK		 5663 drm_crtc_vblank_put(new_state->base.crtc);
5664 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
5665 __func__, new_state->base.crtc->base.id);
5666 }
5667}
5668
8ad27806
NK		 5669static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
5670{
5671 struct drm_plane *plane;
5672 struct drm_plane_state *old_plane_state, *new_plane_state;
5673 int i;
5674
5675 /*
5676 * TODO: Make this per-stream so we don't issue redundant updates for
5677 * commits with multiple streams.
5678 */
5679 for_each_oldnew_plane_in_state(state, plane, old_plane_state,
5680 new_plane_state, i)
5681 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5682 handle_cursor_update(plane, old_plane_state);
5683}
5684
3be5262e 5685static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 5686 struct dc_state *dc_state,
3ee6b26b
AD		 5687 struct drm_device *dev,
5688 struct amdgpu_display_manager *dm,
5689 struct drm_crtc *pcrtc,
420cd472 5690 bool wait_for_vblank)
e7b07cee 5691{
570c91d5 5692 uint32_t i;
8a48b44c 5693 uint64_t timestamp_ns;
e7b07cee 5694 struct drm_plane *plane;
0bc9706d 5695 struct drm_plane_state *old_plane_state, *new_plane_state;
e7b07cee 5696 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 5697 struct drm_crtc_state *new_pcrtc_state =
5698 drm_atomic_get_new_crtc_state(state, pcrtc);
5699 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 5700 struct dm_crtc_state *dm_old_crtc_state =
5701 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
74aa7bd4 5702 int planes_count = 0, vpos, hpos;
570c91d5 5703 long r;
e7b07cee 5704 unsigned long flags;
8a48b44c 5705 struct amdgpu_bo *abo;
09e5665a 5706 uint64_t tiling_flags;
fdd1fe57
MK		 5707 uint32_t target_vblank, last_flip_vblank;
5708 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
74aa7bd4 5709 bool pflip_present = false;
bc7f670e
DF		 5710 struct {
5711 struct dc_surface_update surface_updates[MAX_SURFACES];
5712 struct dc_plane_info plane_infos[MAX_SURFACES];
5713 struct dc_scaling_info scaling_infos[MAX_SURFACES];
74aa7bd4 5714 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
bc7f670e 5715 struct dc_stream_update stream_update;
74aa7bd4 5716 } *bundle;
bc7f670e 5717
74aa7bd4 5718 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8a48b44c 5719
74aa7bd4
DF		 5720 if (!bundle) {
5721 dm_error("Failed to allocate update bundle\n");
4b510503
NK		 5722 goto cleanup;
5723 }
e7b07cee 5724
8ad27806
NK		 5725 /*
5726 * Disable the cursor first if we're disabling all the planes.
5727 * It'll remain on the screen after the planes are re-enabled
5728 * if we don't.
5729 */
5730 if (acrtc_state->active_planes == 0)
5731 amdgpu_dm_commit_cursors(state);
5732
e7b07cee 5733 /* update planes when needed */
0bc9706d
LSL		 5734 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
5735 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 5736 struct drm_crtc_state *new_crtc_state;
0bc9706d 5737 struct drm_framebuffer *fb = new_plane_state->fb;
34bafd27 5738 bool plane_needs_flip;
c7af5f77 5739 struct dc_plane_state *dc_plane;
54d76575 5740 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee 5741
80c218d5
NK		 5742 /* Cursor plane is handled after stream updates */
5743 if (plane->type == DRM_PLANE_TYPE_CURSOR)
e7b07cee 5744 continue;
e7b07cee 5745
f5ba60fe
DD		 5746 if (!fb || !crtc || pcrtc != crtc)
5747 continue;
5748
5749 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
5750 if (!new_crtc_state->active)
e7b07cee
HW		 5751 continue;
5752
bc7f670e 5753 dc_plane = dm_new_plane_state->dc_state;
e7b07cee 5754
74aa7bd4 5755 bundle->surface_updates[planes_count].surface = dc_plane;
bc7f670e 5756 if (new_pcrtc_state->color_mgmt_changed) {
74aa7bd4
DF		 5757 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
5758 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
bc7f670e 5759 }
8a48b44c 5760
695af5f9
NK		 5761 fill_dc_scaling_info(new_plane_state,
5762 &bundle->scaling_infos[planes_count]);
8a48b44c 5763
695af5f9
NK		 5764 bundle->surface_updates[planes_count].scaling_info =
5765 &bundle->scaling_infos[planes_count];
8a48b44c 5766
f5031000 5767 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8a48b44c 5768
f5031000 5769 pflip_present = pflip_present || plane_needs_flip;
8a48b44c 5770
f5031000
DF		 5771 if (!plane_needs_flip) {
5772 planes_count += 1;
5773 continue;
5774 }
8a48b44c 5775
2fac0f53
CK		 5776 abo = gem_to_amdgpu_bo(fb->obj[0]);
5777
f8308898
AG		 5778 /*
5779 * Wait for all fences on this FB. Do limited wait to avoid
5780 * deadlock during GPU reset when this fence will not signal
5781 * but we hold reservation lock for the BO.
5782 */
52791eee 5783 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
2fac0f53 5784 false,
f8308898
AG		 5785 msecs_to_jiffies(5000));
5786 if (unlikely(r <= 0))
ed8a5fb2 5787 DRM_ERROR("Waiting for fences timed out!");
2fac0f53 5788
f5031000
DF		 5789 /*
5790 * TODO This might fail and hence better not used, wait
5791 * explicitly on fences instead
5792 * and in general should be called for
5793 * blocking commit to as per framework helpers
5794 */
f5031000 5795 r = amdgpu_bo_reserve(abo, true);
f8308898 5796 if (unlikely(r != 0))
f5031000 5797 DRM_ERROR("failed to reserve buffer before flip\n");
8a48b44c 5798
f5031000 5799 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
8a48b44c 5800
f5031000 5801 amdgpu_bo_unreserve(abo);
8a48b44c 5802
695af5f9
NK		 5803 fill_dc_plane_info_and_addr(
5804 dm->adev, new_plane_state, tiling_flags,
5805 &bundle->plane_infos[planes_count],
5806 &bundle->flip_addrs[planes_count].address);
5807
5808 bundle->surface_updates[planes_count].plane_info =
5809 &bundle->plane_infos[planes_count];
8a48b44c 5810
caff0e66
NK		 5811 /*
5812 * Only allow immediate flips for fast updates that don't
5813 * change FB pitch, DCC state, rotation or mirroing.
5814 */
f5031000 5815 bundle->flip_addrs[planes_count].flip_immediate =
caff0e66
NK		 5816 (crtc->state->pageflip_flags &
5817 DRM_MODE_PAGE_FLIP_ASYNC) != 0 &&
5818 acrtc_state->update_type == UPDATE_TYPE_FAST;
8a48b44c 5819
f5031000
DF		 5820 timestamp_ns = ktime_get_ns();
5821 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
5822 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
5823 bundle->surface_updates[planes_count].surface = dc_plane;
8a48b44c 5824
f5031000
DF		 5825 if (!bundle->surface_updates[planes_count].surface) {
5826 DRM_ERROR("No surface for CRTC: id=%d\n",
5827 acrtc_attach->crtc_id);
5828 continue;
bc7f670e
DF		 5829 }
5830
f5031000
DF		 5831 if (plane == pcrtc->primary)
5832 update_freesync_state_on_stream(
5833 dm,
5834 acrtc_state,
5835 acrtc_state->stream,
5836 dc_plane,
5837 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
bc7f670e 5838
f5031000
DF		 5839 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
5840 __func__,
5841 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
5842 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
bc7f670e
DF		 5843
5844 planes_count += 1;
5845
8a48b44c
DF		 5846 }
5847
74aa7bd4 5848 if (pflip_present) {
634092b1
MK		 5849 if (!vrr_active) {
5850 /* Use old throttling in non-vrr fixed refresh rate mode
5851 * to keep flip scheduling based on target vblank counts
5852 * working in a backwards compatible way, e.g., for
5853 * clients using the GLX_OML_sync_control extension or
5854 * DRI3/Present extension with defined target_msc.
5855 */
fdd1fe57 5856 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
634092b1
MK		 5857 }
5858 else {
5859 /* For variable refresh rate mode only:
5860 * Get vblank of last completed flip to avoid > 1 vrr
5861 * flips per video frame by use of throttling, but allow
5862 * flip programming anywhere in the possibly large
5863 * variable vrr vblank interval for fine-grained flip
5864 * timing control and more opportunity to avoid stutter
5865 * on late submission of flips.
5866 */
5867 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5868 last_flip_vblank = acrtc_attach->last_flip_vblank;
5869 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5870 }
5871
fdd1fe57 5872 target_vblank = last_flip_vblank + wait_for_vblank;
8a48b44c
DF		 5873
5874 /*
5875 * Wait until we're out of the vertical blank period before the one
5876 * targeted by the flip
5877 */
5878 while ((acrtc_attach->enabled &&
5879 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
5880 0, &vpos, &hpos, NULL,
5881 NULL, &pcrtc->hwmode)
5882 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
5883 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
5884 (int)(target_vblank -
5885 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
5886 usleep_range(1000, 1100);
5887 }
5888
5889 if (acrtc_attach->base.state->event) {
5890 drm_crtc_vblank_get(pcrtc);
5891
5892 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5893
5894 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
5895 prepare_flip_isr(acrtc_attach);
5896
5897 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5898 }
5899
5900 if (acrtc_state->stream) {
8a48b44c 5901 if (acrtc_state->freesync_vrr_info_changed)
74aa7bd4 5902 bundle->stream_update.vrr_infopacket =
8a48b44c 5903 &acrtc_state->stream->vrr_infopacket;
e7b07cee 5904 }
e7b07cee
HW		 5905 }
5906
bc92c065 5907 /* Update the planes if changed or disable if we don't have any. */
ed9656fb
ES		 5908 if ((planes_count || acrtc_state->active_planes == 0) &&
5909 acrtc_state->stream) {
b6e881c9 5910 bundle->stream_update.stream = acrtc_state->stream;
bc7f670e 5911 if (new_pcrtc_state->mode_changed) {
74aa7bd4
DF		 5912 bundle->stream_update.src = acrtc_state->stream->src;
5913 bundle->stream_update.dst = acrtc_state->stream->dst;
e7b07cee
HW		 5914 }
5915
cf020d49
NK		 5916 if (new_pcrtc_state->color_mgmt_changed) {
5917 /*
5918 * TODO: This isn't fully correct since we've actually
5919 * already modified the stream in place.
5920 */
5921 bundle->stream_update.gamut_remap =
5922 &acrtc_state->stream->gamut_remap_matrix;
5923 bundle->stream_update.output_csc_transform =
5924 &acrtc_state->stream->csc_color_matrix;
5925 bundle->stream_update.out_transfer_func =
5926 acrtc_state->stream->out_transfer_func;
5927 }
bc7f670e 5928
8a48b44c 5929 acrtc_state->stream->abm_level = acrtc_state->abm_level;
bc7f670e 5930 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
74aa7bd4 5931 bundle->stream_update.abm_level = &acrtc_state->abm_level;
44d09c6a 5932
e63e2491
EB		 5933 /*
5934 * If FreeSync state on the stream has changed then we need to
5935 * re-adjust the min/max bounds now that DC doesn't handle this
5936 * as part of commit.
5937 */
5938 if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
5939 amdgpu_dm_vrr_active(acrtc_state)) {
5940 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5941 dc_stream_adjust_vmin_vmax(
5942 dm->dc, acrtc_state->stream,
5943 &acrtc_state->vrr_params.adjust);
5944 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5945 }
5946
bc7f670e
DF		 5947 mutex_lock(&dm->dc_lock);
5948 dc_commit_updates_for_stream(dm->dc,
74aa7bd4 5949 bundle->surface_updates,
bc7f670e
DF		 5950 planes_count,
5951 acrtc_state->stream,
74aa7bd4 5952 &bundle->stream_update,
bc7f670e
DF		 5953 dc_state);
5954 mutex_unlock(&dm->dc_lock);
e7b07cee 5955 }
4b510503 5956
8ad27806
NK		 5957 /*
5958 * Update cursor state *after* programming all the planes.
5959 * This avoids redundant programming in the case where we're going
5960 * to be disabling a single plane - those pipes are being disabled.
5961 */
5962 if (acrtc_state->active_planes)
5963 amdgpu_dm_commit_cursors(state);
80c218d5 5964
4b510503 5965cleanup:
74aa7bd4 5966 kfree(bundle);
e7b07cee
HW		 5967}
5968
6ce8f316
NK		 5969static void amdgpu_dm_commit_audio(struct drm_device *dev,
5970 struct drm_atomic_state *state)
5971{
5972 struct amdgpu_device *adev = dev->dev_private;
5973 struct amdgpu_dm_connector *aconnector;
5974 struct drm_connector *connector;
5975 struct drm_connector_state *old_con_state, *new_con_state;
5976 struct drm_crtc_state *new_crtc_state;
5977 struct dm_crtc_state *new_dm_crtc_state;
5978 const struct dc_stream_status *status;
5979 int i, inst;
5980
5981 /* Notify device removals. */
5982 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5983 if (old_con_state->crtc != new_con_state->crtc) {
5984 /* CRTC changes require notification. */
5985 goto notify;
5986 }
5987
5988 if (!new_con_state->crtc)
5989 continue;
5990
5991 new_crtc_state = drm_atomic_get_new_crtc_state(
5992 state, new_con_state->crtc);
5993
5994 if (!new_crtc_state)
5995 continue;
5996
5997 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5998 continue;
5999
6000 notify:
6001 aconnector = to_amdgpu_dm_connector(connector);
6002
6003 mutex_lock(&adev->dm.audio_lock);
6004 inst = aconnector->audio_inst;
6005 aconnector->audio_inst = -1;
6006 mutex_unlock(&adev->dm.audio_lock);
6007
6008 amdgpu_dm_audio_eld_notify(adev, inst);
6009 }
6010
6011 /* Notify audio device additions. */
6012 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6013 if (!new_con_state->crtc)
6014 continue;
6015
6016 new_crtc_state = drm_atomic_get_new_crtc_state(
6017 state, new_con_state->crtc);
6018
6019 if (!new_crtc_state)
6020 continue;
6021
6022 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6023 continue;
6024
6025 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6026 if (!new_dm_crtc_state->stream)
6027 continue;
6028
6029 status = dc_stream_get_status(new_dm_crtc_state->stream);
6030 if (!status)
6031 continue;
6032
6033 aconnector = to_amdgpu_dm_connector(connector);
6034
6035 mutex_lock(&adev->dm.audio_lock);
6036 inst = status->audio_inst;
6037 aconnector->audio_inst = inst;
6038 mutex_unlock(&adev->dm.audio_lock);
6039
6040 amdgpu_dm_audio_eld_notify(adev, inst);
6041 }
6042}
6043
b5e83f6f
NK		 6044/*
6045 * Enable interrupts on CRTCs that are newly active, undergone
6046 * a modeset, or have active planes again.
6047 *
6048 * Done in two passes, based on the for_modeset flag:
6049 * Pass 1: For CRTCs going through modeset
6050 * Pass 2: For CRTCs going from 0 to n active planes
6051 *
6052 * Interrupts can only be enabled after the planes are programmed,
6053 * so this requires a two-pass approach since we don't want to
6054 * just defer the interrupts until after commit planes every time.
6055 */
6056static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
6057 struct drm_atomic_state *state,
6058 bool for_modeset)
6059{
6060 struct amdgpu_device *adev = dev->dev_private;
6061 struct drm_crtc *crtc;
6062 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6063 int i;
14b25846 6064 enum amdgpu_dm_pipe_crc_source source;
b5e83f6f
NK		 6065
6066 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6067 new_crtc_state, i) {
6068 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6069 struct dm_crtc_state *dm_new_crtc_state =
6070 to_dm_crtc_state(new_crtc_state);
6071 struct dm_crtc_state *dm_old_crtc_state =
6072 to_dm_crtc_state(old_crtc_state);
6073 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
6074 bool run_pass;
6075
6076 run_pass = (for_modeset && modeset) ||
6077 (!for_modeset && !modeset &&
6078 !dm_old_crtc_state->interrupts_enabled);
6079
6080 if (!run_pass)
6081 continue;
6082
b5e83f6f
NK		 6083 if (!dm_new_crtc_state->interrupts_enabled)
6084 continue;
6085
6086 manage_dm_interrupts(adev, acrtc, true);
6087
6088#ifdef CONFIG_DEBUG_FS
6089 /* The stream has changed so CRC capture needs to re-enabled. */
14b25846
DZ		 6090 source = dm_new_crtc_state->crc_src;
6091 if (amdgpu_dm_is_valid_crc_source(source)) {
57638021
NK		 6092 amdgpu_dm_crtc_configure_crc_source(
6093 crtc, dm_new_crtc_state,
6094 dm_new_crtc_state->crc_src);
b5e83f6f
NK		 6095 }
6096#endif
6097 }
6098}
6099
1f6010a9 6100/*
27b3f4fc
LSL		 6101 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
6102 * @crtc_state: the DRM CRTC state
6103 * @stream_state: the DC stream state.
6104 *
6105 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
6106 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
6107 */
6108static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
6109 struct dc_stream_state *stream_state)
6110{
b9952f93 6111 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
27b3f4fc 6112}
e7b07cee 6113
7578ecda
AD		 6114static int amdgpu_dm_atomic_commit(struct drm_device *dev,
6115 struct drm_atomic_state *state,
6116 bool nonblock)
e7b07cee
HW		 6117{
6118 struct drm_crtc *crtc;
c2cea706 6119 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 6120 struct amdgpu_device *adev = dev->dev_private;
6121 int i;
6122
6123 /*
d6ef9b41
NK		 6124 * We evade vblank and pflip interrupts on CRTCs that are undergoing
6125 * a modeset, being disabled, or have no active planes.
6126 *
6127 * It's done in atomic commit rather than commit tail for now since
6128 * some of these interrupt handlers access the current CRTC state and
6129 * potentially the stream pointer itself.
6130 *
6131 * Since the atomic state is swapped within atomic commit and not within
6132 * commit tail this would leave to new state (that hasn't been committed yet)
6133 * being accesssed from within the handlers.
6134 *
6135 * TODO: Fix this so we can do this in commit tail and not have to block
6136 * in atomic check.
e7b07cee 6137 */
c2cea706 6138 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 6139 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
428da2bd 6140 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 6141 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6142
d6ef9b41
NK		 6143 if (dm_old_crtc_state->interrupts_enabled &&
6144 (!dm_new_crtc_state->interrupts_enabled ||
57638021 6145 drm_atomic_crtc_needs_modeset(new_crtc_state)))
e7b07cee
HW		 6146 manage_dm_interrupts(adev, acrtc, false);
6147 }
1f6010a9
DF		 6148 /*
6149 * Add check here for SoC's that support hardware cursor plane, to
6150 * unset legacy_cursor_update
6151 */
e7b07cee
HW		 6152
6153 return drm_atomic_helper_commit(dev, state, nonblock);
6154
6155 /*TODO Handle EINTR, reenable IRQ*/
6156}
6157
b8592b48
LL		 6158/**
6159 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
6160 * @state: The atomic state to commit
6161 *
6162 * This will tell DC to commit the constructed DC state from atomic_check,
6163 * programming the hardware. Any failures here implies a hardware failure, since
6164 * atomic check should have filtered anything non-kosher.
6165 */
7578ecda 6166static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 6167{
6168 struct drm_device *dev = state->dev;
6169 struct amdgpu_device *adev = dev->dev_private;
6170 struct amdgpu_display_manager *dm = &adev->dm;
6171 struct dm_atomic_state *dm_state;
eb3dc897 6172 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 6173 uint32_t i, j;
5cc6dcbd 6174 struct drm_crtc *crtc;
0bc9706d 6175 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 6176 unsigned long flags;
6177 bool wait_for_vblank = true;
6178 struct drm_connector *connector;
c2cea706 6179 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 6180 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 6181 int crtc_disable_count = 0;
e7b07cee
HW		 6182
6183 drm_atomic_helper_update_legacy_modeset_state(dev, state);
6184
eb3dc897
NK		 6185 dm_state = dm_atomic_get_new_state(state);
6186 if (dm_state && dm_state->context) {
6187 dc_state = dm_state->context;
6188 } else {
6189 /* No state changes, retain current state. */
813d20dc 6190 dc_state_temp = dc_create_state(dm->dc);
eb3dc897
NK		 6191 ASSERT(dc_state_temp);
6192 dc_state = dc_state_temp;
6193 dc_resource_state_copy_construct_current(dm->dc, dc_state);
6194 }
e7b07cee
HW		 6195
6196 /* update changed items */
0bc9706d 6197 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 6198 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 6199
54d76575
LSL		 6200 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6201 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 6202
f1ad2f5e 6203 DRM_DEBUG_DRIVER(
e7b07cee
HW		 6204 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6205 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6206 "connectors_changed:%d\n",
6207 acrtc->crtc_id,
0bc9706d
LSL		 6208 new_crtc_state->enable,
6209 new_crtc_state->active,
6210 new_crtc_state->planes_changed,
6211 new_crtc_state->mode_changed,
6212 new_crtc_state->active_changed,
6213 new_crtc_state->connectors_changed);
e7b07cee 6214
27b3f4fc
LSL		 6215 /* Copy all transient state flags into dc state */
6216 if (dm_new_crtc_state->stream) {
6217 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
6218 dm_new_crtc_state->stream);
6219 }
6220
e7b07cee
HW		 6221 /* handles headless hotplug case, updating new_state and
6222 * aconnector as needed
6223 */
6224
54d76575 6225 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 6226
f1ad2f5e 6227 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 6228
54d76575 6229 if (!dm_new_crtc_state->stream) {
e7b07cee 6230 /*
b830ebc9
HW		 6231 * this could happen because of issues with
6232 * userspace notifications delivery.
6233 * In this case userspace tries to set mode on
1f6010a9
DF		 6234 * display which is disconnected in fact.
6235 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 6236 * We expect reset mode will come soon.
6237 *
6238 * This can also happen when unplug is done
6239 * during resume sequence ended
6240 *
6241 * In this case, we want to pretend we still
6242 * have a sink to keep the pipe running so that
6243 * hw state is consistent with the sw state
6244 */
f1ad2f5e 6245 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 6246 __func__, acrtc->base.base.id);
6247 continue;
6248 }
6249
54d76575
LSL		 6250 if (dm_old_crtc_state->stream)
6251 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 6252
97028037
LP		 6253 pm_runtime_get_noresume(dev->dev);
6254
e7b07cee 6255 acrtc->enabled = true;
0bc9706d
LSL		 6256 acrtc->hw_mode = new_crtc_state->mode;
6257 crtc->hwmode = new_crtc_state->mode;
6258 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 6259 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 6260
6261 /* i.e. reset mode */
54d76575
LSL		 6262 if (dm_old_crtc_state->stream)
6263 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 6264 }
6265 } /* for_each_crtc_in_state() */
6266
eb3dc897
NK		 6267 if (dc_state) {
6268 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 6269 mutex_lock(&dm->dc_lock);
eb3dc897 6270 WARN_ON(!dc_commit_state(dm->dc, dc_state));
674e78ac 6271 mutex_unlock(&dm->dc_lock);
fa2123db 6272 }
e7b07cee 6273
0bc9706d 6274 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 6275 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 6276
54d76575 6277 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 6278
54d76575 6279 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 6280 const struct dc_stream_status *status =
54d76575 6281 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 6282
eb3dc897 6283 if (!status)
09f609c3
LL		 6284 status = dc_stream_get_status_from_state(dc_state,
6285 dm_new_crtc_state->stream);
eb3dc897 6286
e7b07cee 6287 if (!status)
54d76575 6288 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 6289 else
6290 acrtc->otg_inst = status->primary_otg_inst;
6291 }
6292 }
6293
02d6a6fc 6294 /* Handle connector state changes */
c2cea706 6295 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 6296 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6297 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6298 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
19afd799
NC		 6299 struct dc_surface_update dummy_updates[MAX_SURFACES];
6300 struct dc_stream_update stream_update;
b232d4ed 6301 struct dc_info_packet hdr_packet;
e7b07cee 6302 struct dc_stream_status *status = NULL;
b232d4ed 6303 bool abm_changed, hdr_changed, scaling_changed;
e7b07cee 6304
19afd799
NC		 6305 memset(&dummy_updates, 0, sizeof(dummy_updates));
6306 memset(&stream_update, 0, sizeof(stream_update));
6307
44d09c6a 6308 if (acrtc) {
0bc9706d 6309 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 6310 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
6311 }
0bc9706d 6312
e7b07cee 6313 /* Skip any modesets/resets */
0bc9706d 6314 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 6315 continue;
6316
54d76575 6317 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 6318 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6319
b232d4ed
NK		 6320 scaling_changed = is_scaling_state_different(dm_new_con_state,
6321 dm_old_con_state);
6322
6323 abm_changed = dm_new_crtc_state->abm_level !=
6324 dm_old_crtc_state->abm_level;
6325
6326 hdr_changed =
6327 is_hdr_metadata_different(old_con_state, new_con_state);
6328
6329 if (!scaling_changed && !abm_changed && !hdr_changed)
c1ee92f9 6330 continue;
e7b07cee 6331
b6e881c9 6332 stream_update.stream = dm_new_crtc_state->stream;
b232d4ed 6333 if (scaling_changed) {
02d6a6fc 6334 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
b6e881c9 6335 dm_new_con_state, dm_new_crtc_state->stream);
e7b07cee 6336
02d6a6fc
DF		 6337 stream_update.src = dm_new_crtc_state->stream->src;
6338 stream_update.dst = dm_new_crtc_state->stream->dst;
6339 }
6340
b232d4ed 6341 if (abm_changed) {
02d6a6fc
DF		 6342 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
6343
6344 stream_update.abm_level = &dm_new_crtc_state->abm_level;
6345 }
70e8ffc5 6346
b232d4ed
NK		 6347 if (hdr_changed) {
6348 fill_hdr_info_packet(new_con_state, &hdr_packet);
6349 stream_update.hdr_static_metadata = &hdr_packet;
6350 }
6351
54d76575 6352 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 6353 WARN_ON(!status);
3be5262e 6354 WARN_ON(!status->plane_count);
e7b07cee 6355
02d6a6fc
DF		 6356 /*
6357 * TODO: DC refuses to perform stream updates without a dc_surface_update.
6358 * Here we create an empty update on each plane.
6359 * To fix this, DC should permit updating only stream properties.
6360 */
6361 for (j = 0; j < status->plane_count; j++)
6362 dummy_updates[j].surface = status->plane_states[0];
6363
6364
6365 mutex_lock(&dm->dc_lock);
6366 dc_commit_updates_for_stream(dm->dc,
6367 dummy_updates,
6368 status->plane_count,
6369 dm_new_crtc_state->stream,
6370 &stream_update,
6371 dc_state);
6372 mutex_unlock(&dm->dc_lock);
e7b07cee
HW		 6373 }
6374
b5e83f6f 6375 /* Count number of newly disabled CRTCs for dropping PM refs later. */
e1fc2dca 6376 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
057be086 6377 new_crtc_state, i) {
fe2a1965
LP		 6378 if (old_crtc_state->active && !new_crtc_state->active)
6379 crtc_disable_count++;
6380
54d76575 6381 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca 6382 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
66b0c973 6383
057be086
NK		 6384 /* Update freesync active state. */
6385 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
6386
66b0c973
MK		 6387 /* Handle vrr on->off / off->on transitions */
6388 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
6389 dm_new_crtc_state);
e7b07cee
HW		 6390 }
6391
b5e83f6f
NK		 6392 /* Enable interrupts for CRTCs going through a modeset. */
6393 amdgpu_dm_enable_crtc_interrupts(dev, state, true);
e7b07cee 6394
420cd472
DF		 6395 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
6396 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
6397 wait_for_vblank = false;
6398
e7b07cee 6399 /* update planes when needed per crtc*/
5cc6dcbd 6400 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 6401 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 6402
54d76575 6403 if (dm_new_crtc_state->stream)
eb3dc897 6404 amdgpu_dm_commit_planes(state, dc_state, dev,
420cd472 6405 dm, crtc, wait_for_vblank);
e7b07cee
HW		 6406 }
6407
b5e83f6f
NK		 6408 /* Enable interrupts for CRTCs going from 0 to n active planes. */
6409 amdgpu_dm_enable_crtc_interrupts(dev, state, false);
e7b07cee 6410
6ce8f316
NK		 6411 /* Update audio instances for each connector. */
6412 amdgpu_dm_commit_audio(dev, state);
6413
e7b07cee
HW		 6414 /*
6415 * send vblank event on all events not handled in flip and
6416 * mark consumed event for drm_atomic_helper_commit_hw_done
6417 */
6418 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 6419 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 6420
0bc9706d
LSL		 6421 if (new_crtc_state->event)
6422 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 6423
0bc9706d 6424 new_crtc_state->event = NULL;
e7b07cee
HW		 6425 }
6426 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6427
29c8f234
LL		 6428 /* Signal HW programming completion */
6429 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 6430
6431 if (wait_for_vblank)
320a1274 6432 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 6433
6434 drm_atomic_helper_cleanup_planes(dev, state);
97028037 6435
1f6010a9
DF		 6436 /*
6437 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 6438 * so we can put the GPU into runtime suspend if we're not driving any
6439 * displays anymore
6440 */
fe2a1965
LP		 6441 for (i = 0; i < crtc_disable_count; i++)
6442 pm_runtime_put_autosuspend(dev->dev);
97028037 6443 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 6444
6445 if (dc_state_temp)
6446 dc_release_state(dc_state_temp);
e7b07cee
HW		 6447}
6448
6449
6450static int dm_force_atomic_commit(struct drm_connector *connector)
6451{
6452 int ret = 0;
6453 struct drm_device *ddev = connector->dev;
6454 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
6455 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
6456 struct drm_plane *plane = disconnected_acrtc->base.primary;
6457 struct drm_connector_state *conn_state;
6458 struct drm_crtc_state *crtc_state;
6459 struct drm_plane_state *plane_state;
6460
6461 if (!state)
6462 return -ENOMEM;
6463
6464 state->acquire_ctx = ddev->mode_config.acquire_ctx;
6465
6466 /* Construct an atomic state to restore previous display setting */
6467
6468 /*
6469 * Attach connectors to drm_atomic_state
6470 */
6471 conn_state = drm_atomic_get_connector_state(state, connector);
6472
6473 ret = PTR_ERR_OR_ZERO(conn_state);
6474 if (ret)
6475 goto err;
6476
6477 /* Attach crtc to drm_atomic_state*/
6478 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
6479
6480 ret = PTR_ERR_OR_ZERO(crtc_state);
6481 if (ret)
6482 goto err;
6483
6484 /* force a restore */
6485 crtc_state->mode_changed = true;
6486
6487 /* Attach plane to drm_atomic_state */
6488 plane_state = drm_atomic_get_plane_state(state, plane);
6489
6490 ret = PTR_ERR_OR_ZERO(plane_state);
6491 if (ret)
6492 goto err;
6493
6494
6495 /* Call commit internally with the state we just constructed */
6496 ret = drm_atomic_commit(state);
6497 if (!ret)
6498 return 0;
6499
6500err:
6501 DRM_ERROR("Restoring old state failed with %i\n", ret);
6502 drm_atomic_state_put(state);
6503
6504 return ret;
6505}
6506
6507/*
1f6010a9
DF		 6508 * This function handles all cases when set mode does not come upon hotplug.
6509 * This includes when a display is unplugged then plugged back into the
6510 * same port and when running without usermode desktop manager supprot
e7b07cee 6511 */
3ee6b26b
AD		 6512void dm_restore_drm_connector_state(struct drm_device *dev,
6513 struct drm_connector *connector)
e7b07cee 6514{
c84dec2f 6515 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 6516 struct amdgpu_crtc *disconnected_acrtc;
6517 struct dm_crtc_state *acrtc_state;
6518
6519 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
6520 return;
6521
6522 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 6523 if (!disconnected_acrtc)
6524 return;
e7b07cee 6525
70e8ffc5
HW		 6526 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
6527 if (!acrtc_state->stream)
e7b07cee
HW		 6528 return;
6529
6530 /*
6531 * If the previous sink is not released and different from the current,
6532 * we deduce we are in a state where we can not rely on usermode call
6533 * to turn on the display, so we do it here
6534 */
6535 if (acrtc_state->stream->sink != aconnector->dc_sink)
6536 dm_force_atomic_commit(&aconnector->base);
6537}
6538
1f6010a9 6539/*
e7b07cee
HW		 6540 * Grabs all modesetting locks to serialize against any blocking commits,
6541 * Waits for completion of all non blocking commits.
6542 */
3ee6b26b
AD		 6543static int do_aquire_global_lock(struct drm_device *dev,
6544 struct drm_atomic_state *state)
e7b07cee
HW		 6545{
6546 struct drm_crtc *crtc;
6547 struct drm_crtc_commit *commit;
6548 long ret;
6549
1f6010a9
DF		 6550 /*
6551 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 6552 * ensure that when the framework release it the
6553 * extra locks we are locking here will get released to
6554 */
6555 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
6556 if (ret)
6557 return ret;
6558
6559 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6560 spin_lock(&crtc->commit_lock);
6561 commit = list_first_entry_or_null(&crtc->commit_list,
6562 struct drm_crtc_commit, commit_entry);
6563 if (commit)
6564 drm_crtc_commit_get(commit);
6565 spin_unlock(&crtc->commit_lock);
6566
6567 if (!commit)
6568 continue;
6569
1f6010a9
DF		 6570 /*
6571 * Make sure all pending HW programming completed and
e7b07cee
HW		 6572 * page flips done
6573 */
6574 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
6575
6576 if (ret > 0)
6577 ret = wait_for_completion_interruptible_timeout(
6578 &commit->flip_done, 10*HZ);
6579
6580 if (ret == 0)
6581 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 6582 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 6583
6584 drm_crtc_commit_put(commit);
6585 }
6586
6587 return ret < 0 ? ret : 0;
6588}
6589
bb47de73
NK		 6590static void get_freesync_config_for_crtc(
6591 struct dm_crtc_state *new_crtc_state,
6592 struct dm_connector_state *new_con_state)
98e6436d
AK		 6593{
6594 struct mod_freesync_config config = {0};
98e6436d
AK		 6595 struct amdgpu_dm_connector *aconnector =
6596 to_amdgpu_dm_connector(new_con_state->base.connector);
a057ec46 6597 struct drm_display_mode *mode = &new_crtc_state->base.mode;
0ab925d3 6598 int vrefresh = drm_mode_vrefresh(mode);
98e6436d 6599
a057ec46 6600 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
0ab925d3
NK		 6601 vrefresh >= aconnector->min_vfreq &&
6602 vrefresh <= aconnector->max_vfreq;
bb47de73 6603
a057ec46
IB		 6604 if (new_crtc_state->vrr_supported) {
6605 new_crtc_state->stream->ignore_msa_timing_param = true;
bb47de73 6606 config.state = new_crtc_state->base.vrr_enabled ?
98e6436d
AK		 6607 VRR_STATE_ACTIVE_VARIABLE :
6608 VRR_STATE_INACTIVE;
6609 config.min_refresh_in_uhz =
6610 aconnector->min_vfreq * 1000000;
6611 config.max_refresh_in_uhz =
6612 aconnector->max_vfreq * 1000000;
69ff8845 6613 config.vsif_supported = true;
180db303 6614 config.btr = true;
98e6436d
AK		 6615 }
6616
bb47de73
NK		 6617 new_crtc_state->freesync_config = config;
6618}
98e6436d 6619
bb47de73
NK		 6620static void reset_freesync_config_for_crtc(
6621 struct dm_crtc_state *new_crtc_state)
6622{
6623 new_crtc_state->vrr_supported = false;
98e6436d 6624
180db303
NK		 6625 memset(&new_crtc_state->vrr_params, 0,
6626 sizeof(new_crtc_state->vrr_params));
bb47de73
NK		 6627 memset(&new_crtc_state->vrr_infopacket, 0,
6628 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 6629}
6630
4b9674e5
LL		 6631static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
6632 struct drm_atomic_state *state,
6633 struct drm_crtc *crtc,
6634 struct drm_crtc_state *old_crtc_state,
6635 struct drm_crtc_state *new_crtc_state,
6636 bool enable,
6637 bool *lock_and_validation_needed)
e7b07cee 6638{
eb3dc897 6639 struct dm_atomic_state *dm_state = NULL;
54d76575 6640 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 6641 struct dc_stream_state *new_stream;
62f55537 6642 int ret = 0;
d4d4a645 6643
1f6010a9
DF		 6644 /*
6645 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
6646 * update changed items
6647 */
4b9674e5
LL		 6648 struct amdgpu_crtc *acrtc = NULL;
6649 struct amdgpu_dm_connector *aconnector = NULL;
6650 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
6651 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
e7b07cee 6652
4b9674e5 6653 new_stream = NULL;
9635b754 6654
4b9674e5
LL		 6655 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6656 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6657 acrtc = to_amdgpu_crtc(crtc);
4b9674e5 6658 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 6659
4b9674e5
LL		 6660 /* TODO This hack should go away */
6661 if (aconnector && enable) {
6662 /* Make sure fake sink is created in plug-in scenario */
6663 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
6664 &aconnector->base);
6665 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
6666 &aconnector->base);
19f89e23 6667
4b9674e5
LL		 6668 if (IS_ERR(drm_new_conn_state)) {
6669 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
6670 goto fail;
6671 }
19f89e23 6672
4b9674e5
LL		 6673 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
6674 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 6675
02d35a67
JFZ		 6676 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6677 goto skip_modeset;
6678
4b9674e5
LL		 6679 new_stream = create_stream_for_sink(aconnector,
6680 &new_crtc_state->mode,
6681 dm_new_conn_state,
6682 dm_old_crtc_state->stream);
19f89e23 6683
4b9674e5
LL		 6684 /*
6685 * we can have no stream on ACTION_SET if a display
6686 * was disconnected during S3, in this case it is not an
6687 * error, the OS will be updated after detection, and
6688 * will do the right thing on next atomic commit
6689 */
19f89e23 6690
4b9674e5
LL		 6691 if (!new_stream) {
6692 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6693 __func__, acrtc->base.base.id);
6694 ret = -ENOMEM;
6695 goto fail;
6696 }
e7b07cee 6697
4b9674e5 6698 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 6699
88694af9
NK		 6700 ret = fill_hdr_info_packet(drm_new_conn_state,
6701 &new_stream->hdr_static_metadata);
6702 if (ret)
6703 goto fail;
6704
7e930949
NK		 6705 /*
6706 * If we already removed the old stream from the context
6707 * (and set the new stream to NULL) then we can't reuse
6708 * the old stream even if the stream and scaling are unchanged.
6709 * We'll hit the BUG_ON and black screen.
6710 *
6711 * TODO: Refactor this function to allow this check to work
6712 * in all conditions.
6713 */
6714 if (dm_new_crtc_state->stream &&
6715 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4b9674e5
LL		 6716 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
6717 new_crtc_state->mode_changed = false;
6718 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
6719 new_crtc_state->mode_changed);
62f55537 6720 }
4b9674e5 6721 }
b830ebc9 6722
02d35a67 6723 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 6724 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6725 goto skip_modeset;
e7b07cee 6726
4b9674e5
LL		 6727 DRM_DEBUG_DRIVER(
6728 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6729 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6730 "connectors_changed:%d\n",
6731 acrtc->crtc_id,
6732 new_crtc_state->enable,
6733 new_crtc_state->active,
6734 new_crtc_state->planes_changed,
6735 new_crtc_state->mode_changed,
6736 new_crtc_state->active_changed,
6737 new_crtc_state->connectors_changed);
62f55537 6738
4b9674e5
LL		 6739 /* Remove stream for any changed/disabled CRTC */
6740 if (!enable) {
62f55537 6741
4b9674e5
LL		 6742 if (!dm_old_crtc_state->stream)
6743 goto skip_modeset;
eb3dc897 6744
4b9674e5
LL		 6745 ret = dm_atomic_get_state(state, &dm_state);
6746 if (ret)
6747 goto fail;
e7b07cee 6748
4b9674e5
LL		 6749 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
6750 crtc->base.id);
62f55537 6751
4b9674e5
LL		 6752 /* i.e. reset mode */
6753 if (dc_remove_stream_from_ctx(
6754 dm->dc,
6755 dm_state->context,
6756 dm_old_crtc_state->stream) != DC_OK) {
6757 ret = -EINVAL;
6758 goto fail;
6759 }
62f55537 6760
4b9674e5
LL		 6761 dc_stream_release(dm_old_crtc_state->stream);
6762 dm_new_crtc_state->stream = NULL;
bb47de73 6763
4b9674e5 6764 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 6765
4b9674e5 6766 *lock_and_validation_needed = true;
62f55537 6767
4b9674e5
LL		 6768 } else {/* Add stream for any updated/enabled CRTC */
6769 /*
6770 * Quick fix to prevent NULL pointer on new_stream when
6771 * added MST connectors not found in existing crtc_state in the chained mode
6772 * TODO: need to dig out the root cause of that
6773 */
6774 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
6775 goto skip_modeset;
62f55537 6776
4b9674e5
LL		 6777 if (modereset_required(new_crtc_state))
6778 goto skip_modeset;
62f55537 6779
4b9674e5
LL		 6780 if (modeset_required(new_crtc_state, new_stream,
6781 dm_old_crtc_state->stream)) {
62f55537 6782
4b9674e5 6783 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 6784
4b9674e5
LL		 6785 ret = dm_atomic_get_state(state, &dm_state);
6786 if (ret)
6787 goto fail;
27b3f4fc 6788
4b9674e5 6789 dm_new_crtc_state->stream = new_stream;
62f55537 6790
4b9674e5 6791 dc_stream_retain(new_stream);
1dc90497 6792
4b9674e5
LL		 6793 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
6794 crtc->base.id);
1dc90497 6795
4b9674e5
LL		 6796 if (dc_add_stream_to_ctx(
6797 dm->dc,
6798 dm_state->context,
6799 dm_new_crtc_state->stream) != DC_OK) {
6800 ret = -EINVAL;
6801 goto fail;
9b690ef3
BL		 6802 }
6803
4b9674e5
LL		 6804 *lock_and_validation_needed = true;
6805 }
6806 }
e277adc5 6807
4b9674e5
LL		 6808skip_modeset:
6809 /* Release extra reference */
6810 if (new_stream)
6811 dc_stream_release(new_stream);
e277adc5 6812
4b9674e5
LL		 6813 /*
6814 * We want to do dc stream updates that do not require a
6815 * full modeset below.
6816 */
6817 if (!(enable && aconnector && new_crtc_state->enable &&
6818 new_crtc_state->active))
6819 return 0;
6820 /*
6821 * Given above conditions, the dc state cannot be NULL because:
6822 * 1. We're in the process of enabling CRTCs (just been added
6823 * to the dc context, or already is on the context)
6824 * 2. Has a valid connector attached, and
6825 * 3. Is currently active and enabled.
6826 * => The dc stream state currently exists.
6827 */
6828 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 6829
4b9674e5
LL		 6830 /* Scaling or underscan settings */
6831 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
6832 update_stream_scaling_settings(
6833 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 6834
b05e2c5e
DF		 6835 /* ABM settings */
6836 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6837
4b9674e5
LL		 6838 /*
6839 * Color management settings. We also update color properties
6840 * when a modeset is needed, to ensure it gets reprogrammed.
6841 */
6842 if (dm_new_crtc_state->base.color_mgmt_changed ||
6843 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
cf020d49 6844 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
4b9674e5
LL		 6845 if (ret)
6846 goto fail;
62f55537 6847 }
e7b07cee 6848
4b9674e5
LL		 6849 /* Update Freesync settings. */
6850 get_freesync_config_for_crtc(dm_new_crtc_state,
6851 dm_new_conn_state);
6852
62f55537 6853 return ret;
9635b754
DS		 6854
6855fail:
6856 if (new_stream)
6857 dc_stream_release(new_stream);
6858 return ret;
62f55537 6859}
9b690ef3 6860
f6ff2a08
NK		 6861static bool should_reset_plane(struct drm_atomic_state *state,
6862 struct drm_plane *plane,
6863 struct drm_plane_state *old_plane_state,
6864 struct drm_plane_state *new_plane_state)
6865{
6866 struct drm_plane *other;
6867 struct drm_plane_state *old_other_state, *new_other_state;
6868 struct drm_crtc_state *new_crtc_state;
6869 int i;
6870
70a1efac
NK		 6871 /*
6872 * TODO: Remove this hack once the checks below are sufficient
6873 * enough to determine when we need to reset all the planes on
6874 * the stream.
6875 */
6876 if (state->allow_modeset)
6877 return true;
6878
f6ff2a08
NK		 6879 /* Exit early if we know that we're adding or removing the plane. */
6880 if (old_plane_state->crtc != new_plane_state->crtc)
6881 return true;
6882
6883 /* old crtc == new_crtc == NULL, plane not in context. */
6884 if (!new_plane_state->crtc)
6885 return false;
6886
6887 new_crtc_state =
6888 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
6889
6890 if (!new_crtc_state)
6891 return true;
6892
7316c4ad
NK		 6893 /* CRTC Degamma changes currently require us to recreate planes. */
6894 if (new_crtc_state->color_mgmt_changed)
6895 return true;
6896
f6ff2a08
NK		 6897 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
6898 return true;
6899
6900 /*
6901 * If there are any new primary or overlay planes being added or
6902 * removed then the z-order can potentially change. To ensure
6903 * correct z-order and pipe acquisition the current DC architecture
6904 * requires us to remove and recreate all existing planes.
6905 *
6906 * TODO: Come up with a more elegant solution for this.
6907 */
6908 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
6909 if (other->type == DRM_PLANE_TYPE_CURSOR)
6910 continue;
6911
6912 if (old_other_state->crtc != new_plane_state->crtc &&
6913 new_other_state->crtc != new_plane_state->crtc)
6914 continue;
6915
6916 if (old_other_state->crtc != new_other_state->crtc)
6917 return true;
6918
6919 /* TODO: Remove this once we can handle fast format changes. */
6920 if (old_other_state->fb && new_other_state->fb &&
6921 old_other_state->fb->format != new_other_state->fb->format)
6922 return true;
6923 }
6924
6925 return false;
6926}
6927
9e869063
LL		 6928static int dm_update_plane_state(struct dc *dc,
6929 struct drm_atomic_state *state,
6930 struct drm_plane *plane,
6931 struct drm_plane_state *old_plane_state,
6932 struct drm_plane_state *new_plane_state,
6933 bool enable,
6934 bool *lock_and_validation_needed)
62f55537 6935{
eb3dc897
NK		 6936
6937 struct dm_atomic_state *dm_state = NULL;
62f55537 6938 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 6939 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 6940 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 6941 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
f6ff2a08 6942 bool needs_reset;
62f55537 6943 int ret = 0;
e7b07cee 6944
9b690ef3 6945
9e869063
LL		 6946 new_plane_crtc = new_plane_state->crtc;
6947 old_plane_crtc = old_plane_state->crtc;
6948 dm_new_plane_state = to_dm_plane_state(new_plane_state);
6949 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 6950
9e869063
LL		 6951 /*TODO Implement atomic check for cursor plane */
6952 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6953 return 0;
9b690ef3 6954
f6ff2a08
NK		 6955 needs_reset = should_reset_plane(state, plane, old_plane_state,
6956 new_plane_state);
6957
9e869063
LL		 6958 /* Remove any changed/removed planes */
6959 if (!enable) {
f6ff2a08 6960 if (!needs_reset)
9e869063 6961 return 0;
a7b06724 6962
9e869063
LL		 6963 if (!old_plane_crtc)
6964 return 0;
62f55537 6965
9e869063
LL		 6966 old_crtc_state = drm_atomic_get_old_crtc_state(
6967 state, old_plane_crtc);
6968 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 6969
9e869063
LL		 6970 if (!dm_old_crtc_state->stream)
6971 return 0;
62f55537 6972
9e869063
LL		 6973 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
6974 plane->base.id, old_plane_crtc->base.id);
9b690ef3 6975
9e869063
LL		 6976 ret = dm_atomic_get_state(state, &dm_state);
6977 if (ret)
6978 return ret;
eb3dc897 6979
9e869063
LL		 6980 if (!dc_remove_plane_from_context(
6981 dc,
6982 dm_old_crtc_state->stream,
6983 dm_old_plane_state->dc_state,
6984 dm_state->context)) {
62f55537 6985
9e869063
LL		 6986 ret = EINVAL;
6987 return ret;
6988 }
e7b07cee 6989
9b690ef3 6990
9e869063
LL		 6991 dc_plane_state_release(dm_old_plane_state->dc_state);
6992 dm_new_plane_state->dc_state = NULL;
1dc90497 6993
9e869063 6994 *lock_and_validation_needed = true;
1dc90497 6995
9e869063
LL		 6996 } else { /* Add new planes */
6997 struct dc_plane_state *dc_new_plane_state;
1dc90497 6998
9e869063
LL		 6999 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
7000 return 0;
e7b07cee 7001
9e869063
LL		 7002 if (!new_plane_crtc)
7003 return 0;
e7b07cee 7004
9e869063
LL		 7005 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
7006 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 7007
9e869063
LL		 7008 if (!dm_new_crtc_state->stream)
7009 return 0;
62f55537 7010
f6ff2a08 7011 if (!needs_reset)
9e869063 7012 return 0;
62f55537 7013
9e869063 7014 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 7015
9e869063
LL		 7016 dc_new_plane_state = dc_create_plane_state(dc);
7017 if (!dc_new_plane_state)
7018 return -ENOMEM;
62f55537 7019
9e869063
LL		 7020 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
7021 plane->base.id, new_plane_crtc->base.id);
8c45c5db 7022
695af5f9 7023 ret = fill_dc_plane_attributes(
9e869063
LL		 7024 new_plane_crtc->dev->dev_private,
7025 dc_new_plane_state,
7026 new_plane_state,
7027 new_crtc_state);
7028 if (ret) {
7029 dc_plane_state_release(dc_new_plane_state);
7030 return ret;
7031 }
62f55537 7032
9e869063
LL		 7033 ret = dm_atomic_get_state(state, &dm_state);
7034 if (ret) {
7035 dc_plane_state_release(dc_new_plane_state);
7036 return ret;
7037 }
eb3dc897 7038
9e869063
LL		 7039 /*
7040 * Any atomic check errors that occur after this will
7041 * not need a release. The plane state will be attached
7042 * to the stream, and therefore part of the atomic
7043 * state. It'll be released when the atomic state is
7044 * cleaned.
7045 */
7046 if (!dc_add_plane_to_context(
7047 dc,
7048 dm_new_crtc_state->stream,
7049 dc_new_plane_state,
7050 dm_state->context)) {
62f55537 7051
9e869063
LL		 7052 dc_plane_state_release(dc_new_plane_state);
7053 return -EINVAL;
7054 }
8c45c5db 7055
9e869063 7056 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 7057
9e869063
LL		 7058 /* Tell DC to do a full surface update every time there
7059 * is a plane change. Inefficient, but works for now.
7060 */
7061 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
7062
7063 *lock_and_validation_needed = true;
62f55537 7064 }
e7b07cee
HW		 7065
7066
62f55537
AG		 7067 return ret;
7068}
a87fa993 7069
eb3dc897 7070static int
f843b308 7071dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
eb3dc897
NK		 7072 struct drm_atomic_state *state,
7073 enum surface_update_type *out_type)
7074{
f843b308 7075 struct dc *dc = dm->dc;
eb3dc897
NK		 7076 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
7077 int i, j, num_plane, ret = 0;
a87fa993
BL		 7078 struct drm_plane_state *old_plane_state, *new_plane_state;
7079 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
7080 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
7081 struct drm_plane *plane;
7082
7083 struct drm_crtc *crtc;
7084 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
7085 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
7086 struct dc_stream_status *status = NULL;
7087
fe96b99d 7088 struct dc_surface_update *updates;
a87fa993
BL		 7089 enum surface_update_type update_type = UPDATE_TYPE_FAST;
7090
fe96b99d 7091 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
fe96b99d 7092
f843b308
NK		 7093 if (!updates) {
7094 DRM_ERROR("Failed to allocate plane updates\n");
4f712911
BL		 7095 /* Set type to FULL to avoid crashing in DC*/
7096 update_type = UPDATE_TYPE_FULL;
eb3dc897 7097 goto cleanup;
4f712911 7098 }
a87fa993
BL		 7099
7100 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
004b3938 7101 struct dc_scaling_info scaling_info;
2aa632c5
NK		 7102 struct dc_stream_update stream_update;
7103
7104 memset(&stream_update, 0, sizeof(stream_update));
c448a53a 7105
a87fa993
BL		 7106 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7107 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
7108 num_plane = 0;
7109
6836d239
NK		 7110 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
7111 update_type = UPDATE_TYPE_FULL;
7112 goto cleanup;
7113 }
a87fa993 7114
6836d239 7115 if (!new_dm_crtc_state->stream)
c744e974 7116 continue;
eb3dc897 7117
c744e974 7118 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
2cc450ce
NK		 7119 const struct amdgpu_framebuffer *amdgpu_fb =
7120 to_amdgpu_framebuffer(new_plane_state->fb);
7121 struct dc_plane_info plane_info;
7122 struct dc_flip_addrs flip_addr;
7123 uint64_t tiling_flags;
7124
c744e974
NK		 7125 new_plane_crtc = new_plane_state->crtc;
7126 old_plane_crtc = old_plane_state->crtc;
7127 new_dm_plane_state = to_dm_plane_state(new_plane_state);
7128 old_dm_plane_state = to_dm_plane_state(old_plane_state);
eb3dc897 7129
c744e974
NK		 7130 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7131 continue;
eb3dc897 7132
6836d239
NK		 7133 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
7134 update_type = UPDATE_TYPE_FULL;
7135 goto cleanup;
7136 }
7137
c744e974
NK		 7138 if (crtc != new_plane_crtc)
7139 continue;
7140
f843b308 7141 updates[num_plane].surface = new_dm_plane_state->dc_state;
c744e974
NK		 7142
7143 if (new_crtc_state->mode_changed) {
c744e974
NK		 7144 stream_update.dst = new_dm_crtc_state->stream->dst;
7145 stream_update.src = new_dm_crtc_state->stream->src;
7146 }
7147
7148 if (new_crtc_state->color_mgmt_changed) {
7149 updates[num_plane].gamma =
7150 new_dm_plane_state->dc_state->gamma_correction;
7151 updates[num_plane].in_transfer_func =
7152 new_dm_plane_state->dc_state->in_transfer_func;
7153 stream_update.gamut_remap =
7154 &new_dm_crtc_state->stream->gamut_remap_matrix;
cf020d49
NK		 7155 stream_update.output_csc_transform =
7156 &new_dm_crtc_state->stream->csc_color_matrix;
c744e974
NK		 7157 stream_update.out_transfer_func =
7158 new_dm_crtc_state->stream->out_transfer_func;
a87fa993
BL		 7159 }
7160
004b3938
NK		 7161 ret = fill_dc_scaling_info(new_plane_state,
7162 &scaling_info);
7163 if (ret)
7164 goto cleanup;
7165
7166 updates[num_plane].scaling_info = &scaling_info;
7167
2cc450ce
NK		 7168 if (amdgpu_fb) {
7169 ret = get_fb_info(amdgpu_fb, &tiling_flags);
7170 if (ret)
7171 goto cleanup;
7172
7173 memset(&flip_addr, 0, sizeof(flip_addr));
7174
7175 ret = fill_dc_plane_info_and_addr(
7176 dm->adev, new_plane_state, tiling_flags,
7177 &plane_info,
7178 &flip_addr.address);
7179 if (ret)
7180 goto cleanup;
7181
7182 updates[num_plane].plane_info = &plane_info;
7183 updates[num_plane].flip_addr = &flip_addr;
7184 }
7185
c744e974
NK		 7186 num_plane++;
7187 }
7188
7189 if (num_plane == 0)
7190 continue;
7191
7192 ret = dm_atomic_get_state(state, &dm_state);
7193 if (ret)
7194 goto cleanup;
7195
7196 old_dm_state = dm_atomic_get_old_state(state);
7197 if (!old_dm_state) {
7198 ret = -EINVAL;
7199 goto cleanup;
7200 }
7201
7202 status = dc_stream_get_status_from_state(old_dm_state->context,
7203 new_dm_crtc_state->stream);
b6e881c9 7204 stream_update.stream = new_dm_crtc_state->stream;
f843b308
NK		 7205 /*
7206 * TODO: DC modifies the surface during this call so we need
7207 * to lock here - find a way to do this without locking.
7208 */
7209 mutex_lock(&dm->dc_lock);
c744e974
NK		 7210 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
7211 &stream_update, status);
f843b308 7212 mutex_unlock(&dm->dc_lock);
c744e974
NK		 7213
7214 if (update_type > UPDATE_TYPE_MED) {
a87fa993 7215 update_type = UPDATE_TYPE_FULL;
eb3dc897 7216 goto cleanup;
a87fa993
BL		 7217 }
7218 }
7219
eb3dc897 7220cleanup:
a87fa993 7221 kfree(updates);
a87fa993 7222
eb3dc897
NK		 7223 *out_type = update_type;
7224 return ret;
a87fa993 7225}
62f55537 7226
b8592b48
LL		 7227/**
7228 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
7229 * @dev: The DRM device
7230 * @state: The atomic state to commit
7231 *
7232 * Validate that the given atomic state is programmable by DC into hardware.
7233 * This involves constructing a &struct dc_state reflecting the new hardware
7234 * state we wish to commit, then querying DC to see if it is programmable. It's
7235 * important not to modify the existing DC state. Otherwise, atomic_check
7236 * may unexpectedly commit hardware changes.
7237 *
7238 * When validating the DC state, it's important that the right locks are
7239 * acquired. For full updates case which removes/adds/updates streams on one
7240 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
7241 * that any such full update commit will wait for completion of any outstanding
7242 * flip using DRMs synchronization events. See
7243 * dm_determine_update_type_for_commit()
7244 *
7245 * Note that DM adds the affected connectors for all CRTCs in state, when that
7246 * might not seem necessary. This is because DC stream creation requires the
7247 * DC sink, which is tied to the DRM connector state. Cleaning this up should
7248 * be possible but non-trivial - a possible TODO item.
7249 *
7250 * Return: -Error code if validation failed.
7251 */
7578ecda
AD		 7252static int amdgpu_dm_atomic_check(struct drm_device *dev,
7253 struct drm_atomic_state *state)
62f55537 7254{
62f55537 7255 struct amdgpu_device *adev = dev->dev_private;
eb3dc897 7256 struct dm_atomic_state *dm_state = NULL;
62f55537 7257 struct dc *dc = adev->dm.dc;
62f55537 7258 struct drm_connector *connector;
c2cea706 7259 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 7260 struct drm_crtc *crtc;
fc9e9920 7261 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 7262 struct drm_plane *plane;
7263 struct drm_plane_state *old_plane_state, *new_plane_state;
a87fa993
BL		 7264 enum surface_update_type update_type = UPDATE_TYPE_FAST;
7265 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
7266
1e88ad0a 7267 int ret, i;
e7b07cee 7268
62f55537
AG		 7269 /*
7270 * This bool will be set for true for any modeset/reset
7271 * or plane update which implies non fast surface update.
7272 */
7273 bool lock_and_validation_needed = false;
7274
7275 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 7276 if (ret)
7277 goto fail;
62f55537 7278
1e88ad0a
S		 7279 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7280 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 7281 !new_crtc_state->color_mgmt_changed &&
a93587b3 7282 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
1e88ad0a 7283 continue;
7bef1af3 7284
1e88ad0a
S		 7285 if (!new_crtc_state->enable)
7286 continue;
fc9e9920 7287
1e88ad0a
S		 7288 ret = drm_atomic_add_affected_connectors(state, crtc);
7289 if (ret)
7290 return ret;
fc9e9920 7291
1e88ad0a
S		 7292 ret = drm_atomic_add_affected_planes(state, crtc);
7293 if (ret)
7294 goto fail;
e7b07cee
HW		 7295 }
7296
2d9e6431
NK		 7297 /*
7298 * Add all primary and overlay planes on the CRTC to the state
7299 * whenever a plane is enabled to maintain correct z-ordering
7300 * and to enable fast surface updates.
7301 */
7302 drm_for_each_crtc(crtc, dev) {
7303 bool modified = false;
7304
7305 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7306 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7307 continue;
7308
7309 if (new_plane_state->crtc == crtc ||
7310 old_plane_state->crtc == crtc) {
7311 modified = true;
7312 break;
7313 }
7314 }
7315
7316 if (!modified)
7317 continue;
7318
7319 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
7320 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7321 continue;
7322
7323 new_plane_state =
7324 drm_atomic_get_plane_state(state, plane);
7325
7326 if (IS_ERR(new_plane_state)) {
7327 ret = PTR_ERR(new_plane_state);
7328 goto fail;
7329 }
7330 }
7331 }
7332
62f55537 7333 /* Remove exiting planes if they are modified */
9e869063
LL		 7334 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7335 ret = dm_update_plane_state(dc, state, plane,
7336 old_plane_state,
7337 new_plane_state,
7338 false,
7339 &lock_and_validation_needed);
7340 if (ret)
7341 goto fail;
62f55537
AG		 7342 }
7343
7344 /* Disable all crtcs which require disable */
4b9674e5
LL		 7345 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7346 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7347 old_crtc_state,
7348 new_crtc_state,
7349 false,
7350 &lock_and_validation_needed);
7351 if (ret)
7352 goto fail;
62f55537
AG		 7353 }
7354
7355 /* Enable all crtcs which require enable */
4b9674e5
LL		 7356 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7357 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7358 old_crtc_state,
7359 new_crtc_state,
7360 true,
7361 &lock_and_validation_needed);
7362 if (ret)
7363 goto fail;
62f55537
AG		 7364 }
7365
7366 /* Add new/modified planes */
9e869063
LL		 7367 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7368 ret = dm_update_plane_state(dc, state, plane,
7369 old_plane_state,
7370 new_plane_state,
7371 true,
7372 &lock_and_validation_needed);
7373 if (ret)
7374 goto fail;
62f55537
AG		 7375 }
7376
b349f76e
ES		 7377 /* Run this here since we want to validate the streams we created */
7378 ret = drm_atomic_helper_check_planes(dev, state);
7379 if (ret)
7380 goto fail;
62f55537 7381
43d10d30
NK		 7382 if (state->legacy_cursor_update) {
7383 /*
7384 * This is a fast cursor update coming from the plane update
7385 * helper, check if it can be done asynchronously for better
7386 * performance.
7387 */
7388 state->async_update =
7389 !drm_atomic_helper_async_check(dev, state);
7390
7391 /*
7392 * Skip the remaining global validation if this is an async
7393 * update. Cursor updates can be done without affecting
7394 * state or bandwidth calcs and this avoids the performance
7395 * penalty of locking the private state object and
7396 * allocating a new dc_state.
7397 */
7398 if (state->async_update)
7399 return 0;
7400 }
7401
ebdd27e1 7402 /* Check scaling and underscan changes*/
1f6010a9 7403 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 7404 * new stream into context w\o causing full reset. Need to
7405 * decide how to handle.
7406 */
c2cea706 7407 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 7408 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
7409 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
7410 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 7411
7412 /* Skip any modesets/resets */
0bc9706d
LSL		 7413 if (!acrtc || drm_atomic_crtc_needs_modeset(
7414 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 7415 continue;
7416
b830ebc9 7417 /* Skip any thing not scale or underscan changes */
54d76575 7418 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 7419 continue;
7420
a87fa993 7421 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 7422 lock_and_validation_needed = true;
7423 }
7424
f843b308 7425 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
eb3dc897
NK		 7426 if (ret)
7427 goto fail;
a87fa993
BL		 7428
7429 if (overall_update_type < update_type)
7430 overall_update_type = update_type;
7431
7432 /*
7433 * lock_and_validation_needed was an old way to determine if we need to set
7434 * the global lock. Leaving it in to check if we broke any corner cases
7435 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
7436 * lock_and_validation_needed false = UPDATE_TYPE_FAST
7437 */
7438 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
7439 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
e7b07cee 7440
a87fa993 7441 if (overall_update_type > UPDATE_TYPE_FAST) {
eb3dc897
NK		 7442 ret = dm_atomic_get_state(state, &dm_state);
7443 if (ret)
7444 goto fail;
e7b07cee
HW		 7445
7446 ret = do_aquire_global_lock(dev, state);
7447 if (ret)
7448 goto fail;
1dc90497 7449
afcd526b 7450 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
e7b07cee
HW		 7451 ret = -EINVAL;
7452 goto fail;
7453 }
bd200d19 7454 } else {
674e78ac 7455 /*
bd200d19
NK		 7456 * The commit is a fast update. Fast updates shouldn't change
7457 * the DC context, affect global validation, and can have their
7458 * commit work done in parallel with other commits not touching
7459 * the same resource. If we have a new DC context as part of
7460 * the DM atomic state from validation we need to free it and
7461 * retain the existing one instead.
674e78ac 7462 */
bd200d19
NK		 7463 struct dm_atomic_state *new_dm_state, *old_dm_state;
7464
7465 new_dm_state = dm_atomic_get_new_state(state);
7466 old_dm_state = dm_atomic_get_old_state(state);
7467
7468 if (new_dm_state && old_dm_state) {
7469 if (new_dm_state->context)
7470 dc_release_state(new_dm_state->context);
7471
7472 new_dm_state->context = old_dm_state->context;
7473
7474 if (old_dm_state->context)
7475 dc_retain_state(old_dm_state->context);
7476 }
e7b07cee
HW		 7477 }
7478
caff0e66
NK		 7479 /* Store the overall update type for use later in atomic check. */
7480 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
7481 struct dm_crtc_state *dm_new_crtc_state =
7482 to_dm_crtc_state(new_crtc_state);
7483
7484 dm_new_crtc_state->update_type = (int)overall_update_type;
e7b07cee
HW		 7485 }
7486
7487 /* Must be success */
7488 WARN_ON(ret);
7489 return ret;
7490
7491fail:
7492 if (ret == -EDEADLK)
01e28f9c 7493 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 7494 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 7495 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 7496 else
01e28f9c 7497 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 7498
7499 return ret;
7500}
7501
3ee6b26b
AD		 7502static bool is_dp_capable_without_timing_msa(struct dc *dc,
7503 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 7504{
7505 uint8_t dpcd_data;
7506 bool capable = false;
7507
c84dec2f 7508 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 7509 dm_helpers_dp_read_dpcd(
7510 NULL,
c84dec2f 7511 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 7512 DP_DOWN_STREAM_PORT_COUNT,
7513 &dpcd_data,
7514 sizeof(dpcd_data))) {
7515 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
7516 }
7517
7518 return capable;
7519}
98e6436d
AK		 7520void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
7521 struct edid *edid)
e7b07cee
HW		 7522{
7523 int i;
e7b07cee
HW		 7524 bool edid_check_required;
7525 struct detailed_timing *timing;
7526 struct detailed_non_pixel *data;
7527 struct detailed_data_monitor_range *range;
c84dec2f
HW		 7528 struct amdgpu_dm_connector *amdgpu_dm_connector =
7529 to_amdgpu_dm_connector(connector);
bb47de73 7530 struct dm_connector_state *dm_con_state = NULL;
e7b07cee
HW		 7531
7532 struct drm_device *dev = connector->dev;
7533 struct amdgpu_device *adev = dev->dev_private;
bb47de73 7534 bool freesync_capable = false;
b830ebc9 7535
8218d7f1
HW		 7536 if (!connector->state) {
7537 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 7538 goto update;
8218d7f1
HW		 7539 }
7540
98e6436d
AK		 7541 if (!edid) {
7542 dm_con_state = to_dm_connector_state(connector->state);
7543
7544 amdgpu_dm_connector->min_vfreq = 0;
7545 amdgpu_dm_connector->max_vfreq = 0;
7546 amdgpu_dm_connector->pixel_clock_mhz = 0;
7547
bb47de73 7548 goto update;
98e6436d
AK		 7549 }
7550
8218d7f1
HW		 7551 dm_con_state = to_dm_connector_state(connector->state);
7552
e7b07cee 7553 edid_check_required = false;
c84dec2f 7554 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee 7555 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
bb47de73 7556 goto update;
e7b07cee
HW		 7557 }
7558 if (!adev->dm.freesync_module)
bb47de73 7559 goto update;
e7b07cee
HW		 7560 /*
7561 * if edid non zero restrict freesync only for dp and edp
7562 */
7563 if (edid) {
c84dec2f
HW		 7564 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
7565 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 7566 edid_check_required = is_dp_capable_without_timing_msa(
7567 adev->dm.dc,
c84dec2f 7568 amdgpu_dm_connector);
e7b07cee
HW		 7569 }
7570 }
e7b07cee
HW		 7571 if (edid_check_required == true && (edid->version > 1 ||
7572 (edid->version == 1 && edid->revision > 1))) {
7573 for (i = 0; i < 4; i++) {
7574
7575 timing = &edid->detailed_timings[i];
7576 data = &timing->data.other_data;
7577 range = &data->data.range;
7578 /*
7579 * Check if monitor has continuous frequency mode
7580 */
7581 if (data->type != EDID_DETAIL_MONITOR_RANGE)
7582 continue;
7583 /*
7584 * Check for flag range limits only. If flag == 1 then
7585 * no additional timing information provided.
7586 * Default GTF, GTF Secondary curve and CVT are not
7587 * supported
7588 */
7589 if (range->flags != 1)
7590 continue;
7591
c84dec2f
HW		 7592 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
7593 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
7594 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 7595 range->pixel_clock_mhz * 10;
7596 break;
7597 }
7598
c84dec2f 7599 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 7600 amdgpu_dm_connector->min_vfreq > 10) {
7601
bb47de73 7602 freesync_capable = true;
e7b07cee
HW		 7603 }
7604 }
bb47de73
NK		 7605
7606update:
7607 if (dm_con_state)
7608 dm_con_state->freesync_capable = freesync_capable;
7609
7610 if (connector->vrr_capable_property)
7611 drm_connector_set_vrr_capable_property(connector,
7612 freesync_capable);
e7b07cee
HW		 7613}
7614
Linux 6.x block layer and io_uring tree(s)