projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: Correct get_crtc_scanoutpos behavior when vpos >= vtotal
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
a94d5569 33#include "amdgpu_ucode.h"
4562236b
HW		 34#include "atom.h"
35#include "amdgpu_dm.h"
e7b07cee 36#include "amdgpu_pm.h"
4562236b
HW		 37
38#include "amd_shared.h"
39#include "amdgpu_dm_irq.h"
40#include "dm_helpers.h"
e7b07cee 41#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 42#if defined(CONFIG_DEBUG_FS)
43#include "amdgpu_dm_debugfs.h"
44#endif
4562236b
HW		 45
46#include "ivsrcid/ivsrcid_vislands30.h"
47
48#include <linux/module.h>
49#include <linux/moduleparam.h>
50#include <linux/version.h>
e7b07cee 51#include <linux/types.h>
97028037 52#include <linux/pm_runtime.h>
a94d5569 53#include <linux/firmware.h>
4562236b 54
e7b07cee 55#include <drm/drmP.h>
4562236b
HW		 56#include <drm/drm_atomic.h>
57#include <drm/drm_atomic_helper.h>
58#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 59#include <drm/drm_fb_helper.h>
60#include <drm/drm_edid.h>
4562236b 61
ff5ef992
AD		 62#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
63#include "ivsrcid/irqsrcs_dcn_1_0.h"
64
ad941f7a
FX		 65#include "dcn/dcn_1_0_offset.h"
66#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 67#include "soc15_hw_ip.h"
68#include "vega10_ip_offset.h"
ff5ef992
AD		 69
70#include "soc15_common.h"
71#endif
72
e7b07cee 73#include "modules/inc/mod_freesync.h"
bbf854dc 74#include "modules/power/power_helpers.h"
e7b07cee 75
a94d5569
DF		 76#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
77MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 78
b8592b48
LL		 79/**
80 * DOC: overview
81 *
82 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
83 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
84 * requests into DC requests, and DC responses into DRM responses.
85 *
86 * The root control structure is &struct amdgpu_display_manager.
87 */
88
7578ecda
AD		 89/* basic init/fini API */
90static int amdgpu_dm_init(struct amdgpu_device *adev);
91static void amdgpu_dm_fini(struct amdgpu_device *adev);
92
1f6010a9
DF		 93/*
94 * initializes drm_device display related structures, based on the information
7578ecda
AD		 95 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
96 * drm_encoder, drm_mode_config
97 *
98 * Returns 0 on success
99 */
100static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
101/* removes and deallocates the drm structures, created by the above function */
102static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
103
104static void
105amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
106
107static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 108 struct drm_plane *plane,
7578ecda
AD		 109 unsigned long possible_crtcs);
110static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
111 struct drm_plane *plane,
112 uint32_t link_index);
113static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
114 struct amdgpu_dm_connector *amdgpu_dm_connector,
115 uint32_t link_index,
116 struct amdgpu_encoder *amdgpu_encoder);
117static int amdgpu_dm_encoder_init(struct drm_device *dev,
118 struct amdgpu_encoder *aencoder,
119 uint32_t link_index);
120
121static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
122
123static int amdgpu_dm_atomic_commit(struct drm_device *dev,
124 struct drm_atomic_state *state,
125 bool nonblock);
126
127static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
128
129static int amdgpu_dm_atomic_check(struct drm_device *dev,
130 struct drm_atomic_state *state);
131
132
133
e7b07cee 134
e04a6123 135static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_PRIMARY,
138 DRM_PLANE_TYPE_PRIMARY,
139 DRM_PLANE_TYPE_PRIMARY,
140 DRM_PLANE_TYPE_PRIMARY,
141 DRM_PLANE_TYPE_PRIMARY,
142};
143
e04a6123 144static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 145 DRM_PLANE_TYPE_PRIMARY,
146 DRM_PLANE_TYPE_PRIMARY,
147 DRM_PLANE_TYPE_PRIMARY,
148 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
149};
150
e04a6123 151static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 152 DRM_PLANE_TYPE_PRIMARY,
153 DRM_PLANE_TYPE_PRIMARY,
154 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
155};
156
4562236b
HW		 157/*
158 * dm_vblank_get_counter
159 *
160 * @brief
161 * Get counter for number of vertical blanks
162 *
163 * @param
164 * struct amdgpu_device *adev - [in] desired amdgpu device
165 * int disp_idx - [in] which CRTC to get the counter from
166 *
167 * @return
168 * Counter for vertical blanks
169 */
170static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
171{
172 if (crtc >= adev->mode_info.num_crtc)
173 return 0;
174 else {
175 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 176 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
177 acrtc->base.state);
4562236b 178
da5c47f6
AG		 179
180 if (acrtc_state->stream == NULL) {
0971c40e
HW		 181 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
182 crtc);
4562236b
HW		 183 return 0;
184 }
185
da5c47f6 186 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 187 }
188}
189
190static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 191 u32 *vbl, u32 *position)
4562236b 192{
81c50963
ST		 193 uint32_t v_blank_start, v_blank_end, h_position, v_position;
194
4562236b
HW		 195 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
196 return -EINVAL;
197 else {
198 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 199 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
200 acrtc->base.state);
4562236b 201
da5c47f6 202 if (acrtc_state->stream == NULL) {
0971c40e
HW		 203 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
204 crtc);
4562236b
HW		 205 return 0;
206 }
207
81c50963
ST		 208 /*
209 * TODO rework base driver to use values directly.
210 * for now parse it back into reg-format
211 */
da5c47f6 212 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 213 &v_blank_start,
214 &v_blank_end,
215 &h_position,
216 &v_position);
217
e806208d
AG		 218 *position = v_position | (h_position << 16);
219 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 220 }
221
222 return 0;
223}
224
225static bool dm_is_idle(void *handle)
226{
227 /* XXX todo */
228 return true;
229}
230
231static int dm_wait_for_idle(void *handle)
232{
233 /* XXX todo */
234 return 0;
235}
236
237static bool dm_check_soft_reset(void *handle)
238{
239 return false;
240}
241
242static int dm_soft_reset(void *handle)
243{
244 /* XXX todo */
245 return 0;
246}
247
3ee6b26b
AD		 248static struct amdgpu_crtc *
249get_crtc_by_otg_inst(struct amdgpu_device *adev,
250 int otg_inst)
4562236b
HW		 251{
252 struct drm_device *dev = adev->ddev;
253 struct drm_crtc *crtc;
254 struct amdgpu_crtc *amdgpu_crtc;
255
4562236b
HW		 256 if (otg_inst == -1) {
257 WARN_ON(1);
258 return adev->mode_info.crtcs[0];
259 }
260
261 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
262 amdgpu_crtc = to_amdgpu_crtc(crtc);
263
264 if (amdgpu_crtc->otg_inst == otg_inst)
265 return amdgpu_crtc;
266 }
267
268 return NULL;
269}
270
271static void dm_pflip_high_irq(void *interrupt_params)
272{
4562236b
HW		 273 struct amdgpu_crtc *amdgpu_crtc;
274 struct common_irq_params *irq_params = interrupt_params;
275 struct amdgpu_device *adev = irq_params->adev;
276 unsigned long flags;
277
278 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
279
280 /* IRQ could occur when in initial stage */
1f6010a9 281 /* TODO work and BO cleanup */
4562236b
HW		 282 if (amdgpu_crtc == NULL) {
283 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
284 return;
285 }
286
287 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 288
289 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
290 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
291 amdgpu_crtc->pflip_status,
292 AMDGPU_FLIP_SUBMITTED,
293 amdgpu_crtc->crtc_id,
294 amdgpu_crtc);
295 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
296 return;
297 }
298
4562236b 299
1f6010a9 300 /* wake up userspace */
1159898a 301 if (amdgpu_crtc->event) {
1f6010a9 302 /* Update to correct count(s) if racing with vblank irq */
753c66c9
MK		 303 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
304
54f5499a 305 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 306
54f5499a
AG		 307 /* page flip completed. clean up */
308 amdgpu_crtc->event = NULL;
1159898a 309
54f5499a
AG		 310 } else
311 WARN_ON(1);
4562236b 312
54f5499a 313 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 314 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
315
54f5499a
AG		 316 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
317 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 318
319 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 320}
321
322static void dm_crtc_high_irq(void *interrupt_params)
323{
324 struct common_irq_params *irq_params = interrupt_params;
325 struct amdgpu_device *adev = irq_params->adev;
4562236b
HW		 326 struct amdgpu_crtc *acrtc;
327
b57de80a 328 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 329
e5d0170e
LSL		 330 if (acrtc) {
331 drm_crtc_handle_vblank(&acrtc->base);
332 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
333 }
4562236b
HW		 334}
335
336static int dm_set_clockgating_state(void *handle,
337 enum amd_clockgating_state state)
338{
339 return 0;
340}
341
342static int dm_set_powergating_state(void *handle,
343 enum amd_powergating_state state)
344{
345 return 0;
346}
347
348/* Prototypes of private functions */
349static int dm_early_init(void* handle);
350
a32e24b4 351/* Allocate memory for FBC compressed data */
3e332d3a 352static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 353{
3e332d3a
RL		 354 struct drm_device *dev = connector->dev;
355 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 356 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 357 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
358 struct drm_display_mode *mode;
42e67c3b
RL		 359 unsigned long max_size = 0;
360
361 if (adev->dm.dc->fbc_compressor == NULL)
362 return;
a32e24b4 363
3e332d3a 364 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 365 return;
366
3e332d3a
RL		 367 if (compressor->bo_ptr)
368 return;
42e67c3b 369
42e67c3b 370
3e332d3a
RL		 371 list_for_each_entry(mode, &connector->modes, head) {
372 if (max_size < mode->htotal * mode->vtotal)
373 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 374 }
375
376 if (max_size) {
377 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 378 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 379 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 380
381 if (r)
42e67c3b
RL		 382 DRM_ERROR("DM: Failed to initialize FBC\n");
383 else {
384 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
385 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
386 }
387
a32e24b4
RL		 388 }
389
390}
a32e24b4 391
7578ecda 392static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 393{
394 struct dc_init_data init_data;
395 adev->dm.ddev = adev->ddev;
396 adev->dm.adev = adev;
397
4562236b
HW		 398 /* Zero all the fields */
399 memset(&init_data, 0, sizeof(init_data));
400
4562236b
HW		 401 if(amdgpu_dm_irq_init(adev)) {
402 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
403 goto error;
404 }
405
406 init_data.asic_id.chip_family = adev->family;
407
408 init_data.asic_id.pci_revision_id = adev->rev_id;
409 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
410
770d13b1 411 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 412 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
413 init_data.asic_id.atombios_base_address =
414 adev->mode_info.atom_context->bios;
415
416 init_data.driver = adev;
417
418 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
419
420 if (!adev->dm.cgs_device) {
421 DRM_ERROR("amdgpu: failed to create cgs device.\n");
422 goto error;
423 }
424
425 init_data.cgs_device = adev->dm.cgs_device;
426
4562236b
HW		 427 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
428
6e227308
HW		 429 /*
430 * TODO debug why this doesn't work on Raven
431 */
432 if (adev->flags & AMD_IS_APU &&
433 adev->asic_type >= CHIP_CARRIZO &&
434 adev->asic_type < CHIP_RAVEN)
435 init_data.flags.gpu_vm_support = true;
436
04b94af4
AD		 437 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
438 init_data.flags.fbc_support = true;
439
4562236b
HW		 440 /* Display Core create. */
441 adev->dm.dc = dc_create(&init_data);
442
423788c7 443 if (adev->dm.dc) {
76121231 444 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 445 } else {
76121231 446 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 447 goto error;
448 }
4562236b 449
4562236b
HW		 450 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
451 if (!adev->dm.freesync_module) {
452 DRM_ERROR(
453 "amdgpu: failed to initialize freesync_module.\n");
454 } else
f1ad2f5e 455 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 456 adev->dm.freesync_module);
457
e277adc5
LSL		 458 amdgpu_dm_init_color_mod();
459
4562236b
HW		 460 if (amdgpu_dm_initialize_drm_device(adev)) {
461 DRM_ERROR(
462 "amdgpu: failed to initialize sw for display support.\n");
463 goto error;
464 }
465
466 /* Update the actual used number of crtc */
467 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
468
469 /* TODO: Add_display_info? */
470
471 /* TODO use dynamic cursor width */
ce75805e
AG		 472 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
473 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 474
475 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
476 DRM_ERROR(
477 "amdgpu: failed to initialize sw for display support.\n");
478 goto error;
479 }
480
e498eb71
NK		 481#if defined(CONFIG_DEBUG_FS)
482 if (dtn_debugfs_init(adev))
483 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
484#endif
485
f1ad2f5e 486 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 487
488 return 0;
489error:
490 amdgpu_dm_fini(adev);
491
59d0f396 492 return -EINVAL;
4562236b
HW		 493}
494
7578ecda 495static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 496{
497 amdgpu_dm_destroy_drm_device(&adev->dm);
498 /*
499 * TODO: pageflip, vlank interrupt
500 *
501 * amdgpu_dm_irq_fini(adev);
502 */
503
504 if (adev->dm.cgs_device) {
505 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
506 adev->dm.cgs_device = NULL;
507 }
508 if (adev->dm.freesync_module) {
509 mod_freesync_destroy(adev->dm.freesync_module);
510 adev->dm.freesync_module = NULL;
511 }
512 /* DC Destroy TODO: Replace destroy DAL */
21de3396 513 if (adev->dm.dc)
4562236b 514 dc_destroy(&adev->dm.dc);
4562236b
HW		 515 return;
516}
517
a94d5569 518static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 519{
a94d5569
DF		 520 const char *fw_name_dmcu;
521 int r;
522 const struct dmcu_firmware_header_v1_0 *hdr;
523
524 switch(adev->asic_type) {
525 case CHIP_BONAIRE:
526 case CHIP_HAWAII:
527 case CHIP_KAVERI:
528 case CHIP_KABINI:
529 case CHIP_MULLINS:
530 case CHIP_TONGA:
531 case CHIP_FIJI:
532 case CHIP_CARRIZO:
533 case CHIP_STONEY:
534 case CHIP_POLARIS11:
535 case CHIP_POLARIS10:
536 case CHIP_POLARIS12:
537 case CHIP_VEGAM:
538 case CHIP_VEGA10:
539 case CHIP_VEGA12:
540 case CHIP_VEGA20:
541 return 0;
542 case CHIP_RAVEN:
543 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
544 break;
545 default:
546 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 547 return -EINVAL;
a94d5569
DF		 548 }
549
550 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
551 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
552 return 0;
553 }
554
555 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
556 if (r == -ENOENT) {
557 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
558 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
559 adev->dm.fw_dmcu = NULL;
560 return 0;
561 }
562 if (r) {
563 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
564 fw_name_dmcu);
565 return r;
566 }
567
568 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
569 if (r) {
570 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
571 fw_name_dmcu);
572 release_firmware(adev->dm.fw_dmcu);
573 adev->dm.fw_dmcu = NULL;
574 return r;
575 }
576
577 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
578 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
579 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
580 adev->firmware.fw_size +=
581 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
582
583 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
584 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
585 adev->firmware.fw_size +=
586 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
587
ee6e89c0
DF		 588 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
589
a94d5569
DF		 590 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
591
4562236b
HW		 592 return 0;
593}
594
a94d5569
DF		 595static int dm_sw_init(void *handle)
596{
597 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
598
599 return load_dmcu_fw(adev);
600}
601
4562236b
HW		 602static int dm_sw_fini(void *handle)
603{
a94d5569
DF		 604 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
605
606 if(adev->dm.fw_dmcu) {
607 release_firmware(adev->dm.fw_dmcu);
608 adev->dm.fw_dmcu = NULL;
609 }
610
4562236b
HW		 611 return 0;
612}
613
7abcf6b5 614static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 615{
c84dec2f 616 struct amdgpu_dm_connector *aconnector;
4562236b 617 struct drm_connector *connector;
7abcf6b5 618 int ret = 0;
4562236b
HW		 619
620 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
621
622 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 623 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 624 if (aconnector->dc_link->type == dc_connection_mst_branch &&
625 aconnector->mst_mgr.aux) {
f1ad2f5e 626 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 627 aconnector, aconnector->base.base.id);
628
629 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
630 if (ret < 0) {
631 DRM_ERROR("DM_MST: Failed to start MST\n");
632 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
633 return ret;
4562236b 634 }
7abcf6b5 635 }
4562236b
HW		 636 }
637
638 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 639 return ret;
640}
641
642static int dm_late_init(void *handle)
643{
42e67c3b 644 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 645
bbf854dc
DF		 646 struct dmcu_iram_parameters params;
647 unsigned int linear_lut[16];
648 int i;
649 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
650 bool ret;
651
652 for (i = 0; i < 16; i++)
653 linear_lut[i] = 0xFFFF * i / 15;
654
655 params.set = 0;
656 params.backlight_ramping_start = 0xCCCC;
657 params.backlight_ramping_reduction = 0xCCCCCCCC;
658 params.backlight_lut_array_size = 16;
659 params.backlight_lut_array = linear_lut;
660
661 ret = dmcu_load_iram(dmcu, params);
662
663 if (!ret)
664 return -EINVAL;
665
42e67c3b 666 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 667}
668
669static void s3_handle_mst(struct drm_device *dev, bool suspend)
670{
c84dec2f 671 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 672 struct drm_connector *connector;
673
674 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
675
676 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 677 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 678 if (aconnector->dc_link->type == dc_connection_mst_branch &&
679 !aconnector->mst_port) {
680
681 if (suspend)
682 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
683 else
684 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
685 }
686 }
687
688 drm_modeset_unlock(&dev->mode_config.connection_mutex);
689}
690
b8592b48
LL		 691/**
692 * dm_hw_init() - Initialize DC device
693 * @handle: The base driver device containing the amdpgu_dm device.
694 *
695 * Initialize the &struct amdgpu_display_manager device. This involves calling
696 * the initializers of each DM component, then populating the struct with them.
697 *
698 * Although the function implies hardware initialization, both hardware and
699 * software are initialized here. Splitting them out to their relevant init
700 * hooks is a future TODO item.
701 *
702 * Some notable things that are initialized here:
703 *
704 * - Display Core, both software and hardware
705 * - DC modules that we need (freesync and color management)
706 * - DRM software states
707 * - Interrupt sources and handlers
708 * - Vblank support
709 * - Debug FS entries, if enabled
710 */
4562236b
HW		 711static int dm_hw_init(void *handle)
712{
713 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
714 /* Create DAL display manager */
715 amdgpu_dm_init(adev);
4562236b
HW		 716 amdgpu_dm_hpd_init(adev);
717
4562236b
HW		 718 return 0;
719}
720
b8592b48
LL		 721/**
722 * dm_hw_fini() - Teardown DC device
723 * @handle: The base driver device containing the amdpgu_dm device.
724 *
725 * Teardown components within &struct amdgpu_display_manager that require
726 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
727 * were loaded. Also flush IRQ workqueues and disable them.
728 */
4562236b
HW		 729static int dm_hw_fini(void *handle)
730{
731 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
732
733 amdgpu_dm_hpd_fini(adev);
734
735 amdgpu_dm_irq_fini(adev);
21de3396 736 amdgpu_dm_fini(adev);
4562236b
HW		 737 return 0;
738}
739
740static int dm_suspend(void *handle)
741{
742 struct amdgpu_device *adev = handle;
743 struct amdgpu_display_manager *dm = &adev->dm;
744 int ret = 0;
4562236b
HW		 745
746 s3_handle_mst(adev->ddev, true);
747
4562236b
HW		 748 amdgpu_dm_irq_suspend(adev);
749
0a214e2f 750 WARN_ON(adev->dm.cached_state);
a3621485
AG		 751 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
752
32f5062d 753 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 754
755 return ret;
756}
757
1daf8c63
AD		 758static struct amdgpu_dm_connector *
759amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
760 struct drm_crtc *crtc)
4562236b
HW		 761{
762 uint32_t i;
c2cea706 763 struct drm_connector_state *new_con_state;
4562236b
HW		 764 struct drm_connector *connector;
765 struct drm_crtc *crtc_from_state;
766
c2cea706
LSL		 767 for_each_new_connector_in_state(state, connector, new_con_state, i) {
768 crtc_from_state = new_con_state->crtc;
4562236b
HW		 769
770 if (crtc_from_state == crtc)
c84dec2f 771 return to_amdgpu_dm_connector(connector);
4562236b
HW		 772 }
773
774 return NULL;
775}
776
fbbdadf2
BL		 777static void emulated_link_detect(struct dc_link *link)
778{
779 struct dc_sink_init_data sink_init_data = { 0 };
780 struct display_sink_capability sink_caps = { 0 };
781 enum dc_edid_status edid_status;
782 struct dc_context *dc_ctx = link->ctx;
783 struct dc_sink *sink = NULL;
784 struct dc_sink *prev_sink = NULL;
785
786 link->type = dc_connection_none;
787 prev_sink = link->local_sink;
788
789 if (prev_sink != NULL)
790 dc_sink_retain(prev_sink);
791
792 switch (link->connector_signal) {
793 case SIGNAL_TYPE_HDMI_TYPE_A: {
794 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
795 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
796 break;
797 }
798
799 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
800 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
801 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
802 break;
803 }
804
805 case SIGNAL_TYPE_DVI_DUAL_LINK: {
806 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
807 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
808 break;
809 }
810
811 case SIGNAL_TYPE_LVDS: {
812 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
813 sink_caps.signal = SIGNAL_TYPE_LVDS;
814 break;
815 }
816
817 case SIGNAL_TYPE_EDP: {
818 sink_caps.transaction_type =
819 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
820 sink_caps.signal = SIGNAL_TYPE_EDP;
821 break;
822 }
823
824 case SIGNAL_TYPE_DISPLAY_PORT: {
825 sink_caps.transaction_type =
826 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
827 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
828 break;
829 }
830
831 default:
832 DC_ERROR("Invalid connector type! signal:%d\n",
833 link->connector_signal);
834 return;
835 }
836
837 sink_init_data.link = link;
838 sink_init_data.sink_signal = sink_caps.signal;
839
840 sink = dc_sink_create(&sink_init_data);
841 if (!sink) {
842 DC_ERROR("Failed to create sink!\n");
843 return;
844 }
845
846 link->local_sink = sink;
847
848 edid_status = dm_helpers_read_local_edid(
849 link->ctx,
850 link,
851 sink);
852
853 if (edid_status != EDID_OK)
854 DC_ERROR("Failed to read EDID");
855
856}
857
4562236b
HW		 858static int dm_resume(void *handle)
859{
860 struct amdgpu_device *adev = handle;
4562236b
HW		 861 struct drm_device *ddev = adev->ddev;
862 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 863 struct amdgpu_dm_connector *aconnector;
4562236b 864 struct drm_connector *connector;
4562236b 865 struct drm_crtc *crtc;
c2cea706 866 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 867 struct dm_crtc_state *dm_new_crtc_state;
868 struct drm_plane *plane;
869 struct drm_plane_state *new_plane_state;
870 struct dm_plane_state *dm_new_plane_state;
fbbdadf2 871 enum dc_connection_type new_connection_type = dc_connection_none;
a80aa93d 872 int ret;
a3621485 873 int i;
4562236b 874
a80aa93d
ML		 875 /* power on hardware */
876 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
877
4562236b
HW		 878 /* program HPD filter */
879 dc_resume(dm->dc);
880
881 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
882 s3_handle_mst(ddev, false);
883
884 /*
885 * early enable HPD Rx IRQ, should be done before set mode as short
886 * pulse interrupts are used for MST
887 */
888 amdgpu_dm_irq_resume_early(adev);
889
4562236b 890 /* Do detection*/
a80aa93d 891 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 892 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 893
894 /*
895 * this is the case when traversing through already created
896 * MST connectors, should be skipped
897 */
898 if (aconnector->mst_port)
899 continue;
900
03ea364c 901 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 902 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
903 DRM_ERROR("KMS: Failed to detect connector\n");
904
905 if (aconnector->base.force && new_connection_type == dc_connection_none)
906 emulated_link_detect(aconnector->dc_link);
907 else
908 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 909
910 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
911 aconnector->fake_enable = false;
912
4562236b
HW		 913 aconnector->dc_sink = NULL;
914 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 915 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 916 }
917
1f6010a9 918 /* Force mode set in atomic commit */
a80aa93d 919 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 920 new_crtc_state->active_changed = true;
4f346e65 921
fcb4019e
LSL		 922 /*
923 * atomic_check is expected to create the dc states. We need to release
924 * them here, since they were duplicated as part of the suspend
925 * procedure.
926 */
a80aa93d 927 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 928 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
929 if (dm_new_crtc_state->stream) {
930 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
931 dc_stream_release(dm_new_crtc_state->stream);
932 dm_new_crtc_state->stream = NULL;
933 }
934 }
935
a80aa93d 936 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 937 dm_new_plane_state = to_dm_plane_state(new_plane_state);
938 if (dm_new_plane_state->dc_state) {
939 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
940 dc_plane_state_release(dm_new_plane_state->dc_state);
941 dm_new_plane_state->dc_state = NULL;
942 }
943 }
944
a80aa93d 945 ret = drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 946
a80aa93d 947 dm->cached_state = NULL;
0a214e2f 948
9faa4237 949 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 950
951 return ret;
952}
953
b8592b48
LL		 954/**
955 * DOC: DM Lifecycle
956 *
957 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
958 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
959 * the base driver's device list to be initialized and torn down accordingly.
960 *
961 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
962 */
963
4562236b
HW		 964static const struct amd_ip_funcs amdgpu_dm_funcs = {
965 .name = "dm",
966 .early_init = dm_early_init,
7abcf6b5 967 .late_init = dm_late_init,
4562236b
HW		 968 .sw_init = dm_sw_init,
969 .sw_fini = dm_sw_fini,
970 .hw_init = dm_hw_init,
971 .hw_fini = dm_hw_fini,
972 .suspend = dm_suspend,
973 .resume = dm_resume,
974 .is_idle = dm_is_idle,
975 .wait_for_idle = dm_wait_for_idle,
976 .check_soft_reset = dm_check_soft_reset,
977 .soft_reset = dm_soft_reset,
978 .set_clockgating_state = dm_set_clockgating_state,
979 .set_powergating_state = dm_set_powergating_state,
980};
981
982const struct amdgpu_ip_block_version dm_ip_block =
983{
984 .type = AMD_IP_BLOCK_TYPE_DCE,
985 .major = 1,
986 .minor = 0,
987 .rev = 0,
988 .funcs = &amdgpu_dm_funcs,
989};
990
ca3268c4 991
b8592b48
LL		 992/**
993 * DOC: atomic
994 *
995 * *WIP*
996 */
997
b3663f70 998static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 999 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 1000 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 1001 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 1002 .atomic_commit = amdgpu_dm_atomic_commit,
54f5499a
AG		 1003};
1004
1005static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1006 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 1007};
1008
7578ecda 1009static void
3ee6b26b 1010amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1011{
1012 struct drm_connector *connector = &aconnector->base;
1013 struct drm_device *dev = connector->dev;
b73a22d3 1014 struct dc_sink *sink;
4562236b
HW		 1015
1016 /* MST handled by drm_mst framework */
1017 if (aconnector->mst_mgr.mst_state == true)
1018 return;
1019
1020
1021 sink = aconnector->dc_link->local_sink;
1022
1f6010a9
DF		 1023 /*
1024 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 1025 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 1026 * Skip if already done during boot.
4562236b
HW		 1027 */
1028 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1029 && aconnector->dc_em_sink) {
1030
1f6010a9
DF		 1031 /*
1032 * For S3 resume with headless use eml_sink to fake stream
1033 * because on resume connector->sink is set to NULL
4562236b
HW		 1034 */
1035 mutex_lock(&dev->mode_config.mutex);
1036
1037 if (sink) {
922aa1e1 1038 if (aconnector->dc_sink) {
98e6436d 1039 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 1040 /*
1041 * retain and release below are used to
1042 * bump up refcount for sink because the link doesn't point
1043 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 1044 * reshuffle by UMD we will get into unwanted dc_sink release
1045 */
1046 if (aconnector->dc_sink != aconnector->dc_em_sink)
1047 dc_sink_release(aconnector->dc_sink);
1048 }
4562236b 1049 aconnector->dc_sink = sink;
98e6436d
AK		 1050 amdgpu_dm_update_freesync_caps(connector,
1051 aconnector->edid);
4562236b 1052 } else {
98e6436d 1053 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1054 if (!aconnector->dc_sink)
1055 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 1056 else if (aconnector->dc_sink != aconnector->dc_em_sink)
1057 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 1058 }
1059
1060 mutex_unlock(&dev->mode_config.mutex);
1061 return;
1062 }
1063
1064 /*
1065 * TODO: temporary guard to look for proper fix
1066 * if this sink is MST sink, we should not do anything
1067 */
1068 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
1069 return;
1070
1071 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 1072 /*
1073 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1074 * Do nothing!!
1075 */
f1ad2f5e 1076 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 1077 aconnector->connector_id);
1078 return;
1079 }
1080
f1ad2f5e 1081 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 1082 aconnector->connector_id, aconnector->dc_sink, sink);
1083
1084 mutex_lock(&dev->mode_config.mutex);
1085
1f6010a9
DF		 1086 /*
1087 * 1. Update status of the drm connector
1088 * 2. Send an event and let userspace tell us what to do
1089 */
4562236b 1090 if (sink) {
1f6010a9
DF		 1091 /*
1092 * TODO: check if we still need the S3 mode update workaround.
1093 * If yes, put it here.
1094 */
4562236b 1095 if (aconnector->dc_sink)
98e6436d 1096 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1097
1098 aconnector->dc_sink = sink;
900b3cb1 1099 if (sink->dc_edid.length == 0) {
4562236b 1100 aconnector->edid = NULL;
e86e8947 1101 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 1102 } else {
4562236b
HW		 1103 aconnector->edid =
1104 (struct edid *) sink->dc_edid.raw_edid;
1105
1106
c555f023 1107 drm_connector_update_edid_property(connector,
4562236b 1108 aconnector->edid);
e86e8947
HV		 1109 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1110 aconnector->edid);
4562236b 1111 }
98e6436d 1112 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 1113
1114 } else {
e86e8947 1115 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 1116 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 1117 drm_connector_update_edid_property(connector, NULL);
4562236b
HW		 1118 aconnector->num_modes = 0;
1119 aconnector->dc_sink = NULL;
5326c452 1120 aconnector->edid = NULL;
4562236b
HW		 1121 }
1122
1123 mutex_unlock(&dev->mode_config.mutex);
1124}
1125
1126static void handle_hpd_irq(void *param)
1127{
c84dec2f 1128 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1129 struct drm_connector *connector = &aconnector->base;
1130 struct drm_device *dev = connector->dev;
fbbdadf2 1131 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1132
1f6010a9
DF		 1133 /*
1134 * In case of failure or MST no need to update connector status or notify the OS
1135 * since (for MST case) MST does this in its own context.
4562236b
HW		 1136 */
1137 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 1138
1139 if (aconnector->fake_enable)
1140 aconnector->fake_enable = false;
1141
fbbdadf2
BL		 1142 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1143 DRM_ERROR("KMS: Failed to detect connector\n");
1144
1145 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1146 emulated_link_detect(aconnector->dc_link);
1147
1148
1149 drm_modeset_lock_all(dev);
1150 dm_restore_drm_connector_state(dev, connector);
1151 drm_modeset_unlock_all(dev);
1152
1153 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1154 drm_kms_helper_hotplug_event(dev);
1155
1156 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1157 amdgpu_dm_update_connector_after_detect(aconnector);
1158
1159
1160 drm_modeset_lock_all(dev);
1161 dm_restore_drm_connector_state(dev, connector);
1162 drm_modeset_unlock_all(dev);
1163
1164 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1165 drm_kms_helper_hotplug_event(dev);
1166 }
1167 mutex_unlock(&aconnector->hpd_lock);
1168
1169}
1170
c84dec2f 1171static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1172{
1173 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1174 uint8_t dret;
1175 bool new_irq_handled = false;
1176 int dpcd_addr;
1177 int dpcd_bytes_to_read;
1178
1179 const int max_process_count = 30;
1180 int process_count = 0;
1181
1182 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1183
1184 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1185 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1186 /* DPCD 0x200 - 0x201 for downstream IRQ */
1187 dpcd_addr = DP_SINK_COUNT;
1188 } else {
1189 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1190 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1191 dpcd_addr = DP_SINK_COUNT_ESI;
1192 }
1193
1194 dret = drm_dp_dpcd_read(
1195 &aconnector->dm_dp_aux.aux,
1196 dpcd_addr,
1197 esi,
1198 dpcd_bytes_to_read);
1199
1200 while (dret == dpcd_bytes_to_read &&
1201 process_count < max_process_count) {
1202 uint8_t retry;
1203 dret = 0;
1204
1205 process_count++;
1206
f1ad2f5e 1207 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1208 /* handle HPD short pulse irq */
1209 if (aconnector->mst_mgr.mst_state)
1210 drm_dp_mst_hpd_irq(
1211 &aconnector->mst_mgr,
1212 esi,
1213 &new_irq_handled);
4562236b
HW		 1214
1215 if (new_irq_handled) {
1216 /* ACK at DPCD to notify down stream */
1217 const int ack_dpcd_bytes_to_write =
1218 dpcd_bytes_to_read - 1;
1219
1220 for (retry = 0; retry < 3; retry++) {
1221 uint8_t wret;
1222
1223 wret = drm_dp_dpcd_write(
1224 &aconnector->dm_dp_aux.aux,
1225 dpcd_addr + 1,
1226 &esi[1],
1227 ack_dpcd_bytes_to_write);
1228 if (wret == ack_dpcd_bytes_to_write)
1229 break;
1230 }
1231
1f6010a9 1232 /* check if there is new irq to be handled */
4562236b
HW		 1233 dret = drm_dp_dpcd_read(
1234 &aconnector->dm_dp_aux.aux,
1235 dpcd_addr,
1236 esi,
1237 dpcd_bytes_to_read);
1238
1239 new_irq_handled = false;
d4a6e8a9 1240 } else {
4562236b 1241 break;
d4a6e8a9 1242 }
4562236b
HW		 1243 }
1244
1245 if (process_count == max_process_count)
f1ad2f5e 1246 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1247}
1248
1249static void handle_hpd_rx_irq(void *param)
1250{
c84dec2f 1251 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1252 struct drm_connector *connector = &aconnector->base;
1253 struct drm_device *dev = connector->dev;
53cbf65c 1254 struct dc_link *dc_link = aconnector->dc_link;
4562236b 1255 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
fbbdadf2 1256 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1257
1f6010a9
DF		 1258 /*
1259 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 1260 * conflict, after implement i2c helper, this mutex should be
1261 * retired.
1262 */
53cbf65c 1263 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1264 mutex_lock(&aconnector->hpd_lock);
1265
4e18814e 1266 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1267 !is_mst_root_connector) {
1268 /* Downstream Port status changed. */
fbbdadf2
BL		 1269 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1270 DRM_ERROR("KMS: Failed to detect connector\n");
1271
1272 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1273 emulated_link_detect(dc_link);
1274
1275 if (aconnector->fake_enable)
1276 aconnector->fake_enable = false;
1277
1278 amdgpu_dm_update_connector_after_detect(aconnector);
1279
1280
1281 drm_modeset_lock_all(dev);
1282 dm_restore_drm_connector_state(dev, connector);
1283 drm_modeset_unlock_all(dev);
1284
1285 drm_kms_helper_hotplug_event(dev);
1286 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1287
1288 if (aconnector->fake_enable)
1289 aconnector->fake_enable = false;
1290
4562236b
HW		 1291 amdgpu_dm_update_connector_after_detect(aconnector);
1292
1293
1294 drm_modeset_lock_all(dev);
1295 dm_restore_drm_connector_state(dev, connector);
1296 drm_modeset_unlock_all(dev);
1297
1298 drm_kms_helper_hotplug_event(dev);
1299 }
1300 }
1301 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1302 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1303 dm_handle_hpd_rx_irq(aconnector);
1304
e86e8947
HV		 1305 if (dc_link->type != dc_connection_mst_branch) {
1306 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 1307 mutex_unlock(&aconnector->hpd_lock);
e86e8947 1308 }
4562236b
HW		 1309}
1310
1311static void register_hpd_handlers(struct amdgpu_device *adev)
1312{
1313 struct drm_device *dev = adev->ddev;
1314 struct drm_connector *connector;
c84dec2f 1315 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1316 const struct dc_link *dc_link;
1317 struct dc_interrupt_params int_params = {0};
1318
1319 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1320 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1321
1322 list_for_each_entry(connector,
1323 &dev->mode_config.connector_list, head) {
1324
c84dec2f 1325 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1326 dc_link = aconnector->dc_link;
1327
1328 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1329 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1330 int_params.irq_source = dc_link->irq_source_hpd;
1331
1332 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1333 handle_hpd_irq,
1334 (void *) aconnector);
1335 }
1336
1337 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1338
1339 /* Also register for DP short pulse (hpd_rx). */
1340 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1341 int_params.irq_source = dc_link->irq_source_hpd_rx;
1342
1343 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1344 handle_hpd_rx_irq,
1345 (void *) aconnector);
1346 }
1347 }
1348}
1349
1350/* Register IRQ sources and initialize IRQ callbacks */
1351static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1352{
1353 struct dc *dc = adev->dm.dc;
1354 struct common_irq_params *c_irq_params;
1355 struct dc_interrupt_params int_params = {0};
1356 int r;
1357 int i;
1ffdeca6 1358 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 1359
ff5ef992 1360 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1361 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1362 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1363 adev->asic_type == CHIP_RAVEN)
3760f76c 1364 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1365
1366 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1367 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1368
1f6010a9
DF		 1369 /*
1370 * Actions of amdgpu_irq_add_id():
4562236b
HW		 1371 * 1. Register a set() function with base driver.
1372 * Base driver will call set() function to enable/disable an
1373 * interrupt in DC hardware.
1374 * 2. Register amdgpu_dm_irq_handler().
1375 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1376 * coming from DC hardware.
1377 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1378 * for acknowledging and handling. */
1379
b57de80a 1380 /* Use VBLANK interrupt */
e9029155 1381 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1382 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1383 if (r) {
1384 DRM_ERROR("Failed to add crtc irq id!\n");
1385 return r;
1386 }
1387
1388 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1389 int_params.irq_source =
3d761e79 1390 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1391
b57de80a 1392 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1393
1394 c_irq_params->adev = adev;
1395 c_irq_params->irq_src = int_params.irq_source;
1396
1397 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1398 dm_crtc_high_irq, c_irq_params);
1399 }
1400
3d761e79 1401 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1402 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1403 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1404 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1405 if (r) {
1406 DRM_ERROR("Failed to add page flip irq id!\n");
1407 return r;
1408 }
1409
1410 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1411 int_params.irq_source =
1412 dc_interrupt_to_irq_source(dc, i, 0);
1413
1414 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1415
1416 c_irq_params->adev = adev;
1417 c_irq_params->irq_src = int_params.irq_source;
1418
1419 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1420 dm_pflip_high_irq, c_irq_params);
1421
1422 }
1423
1424 /* HPD */
2c8ad2d5
AD		 1425 r = amdgpu_irq_add_id(adev, client_id,
1426 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1427 if (r) {
1428 DRM_ERROR("Failed to add hpd irq id!\n");
1429 return r;
1430 }
1431
1432 register_hpd_handlers(adev);
1433
1434 return 0;
1435}
1436
ff5ef992
AD		 1437#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1438/* Register IRQ sources and initialize IRQ callbacks */
1439static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1440{
1441 struct dc *dc = adev->dm.dc;
1442 struct common_irq_params *c_irq_params;
1443 struct dc_interrupt_params int_params = {0};
1444 int r;
1445 int i;
1446
1447 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1448 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1449
1f6010a9
DF		 1450 /*
1451 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 1452 * 1. Register a set() function with base driver.
1453 * Base driver will call set() function to enable/disable an
1454 * interrupt in DC hardware.
1455 * 2. Register amdgpu_dm_irq_handler().
1456 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1457 * coming from DC hardware.
1458 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1459 * for acknowledging and handling.
1f6010a9 1460 */
ff5ef992
AD		 1461
1462 /* Use VSTARTUP interrupt */
1463 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1464 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1465 i++) {
3760f76c 1466 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1467
1468 if (r) {
1469 DRM_ERROR("Failed to add crtc irq id!\n");
1470 return r;
1471 }
1472
1473 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1474 int_params.irq_source =
1475 dc_interrupt_to_irq_source(dc, i, 0);
1476
1477 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1478
1479 c_irq_params->adev = adev;
1480 c_irq_params->irq_src = int_params.irq_source;
1481
1482 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1483 dm_crtc_high_irq, c_irq_params);
1484 }
1485
1486 /* Use GRPH_PFLIP interrupt */
1487 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1488 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1489 i++) {
3760f76c 1490 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1491 if (r) {
1492 DRM_ERROR("Failed to add page flip irq id!\n");
1493 return r;
1494 }
1495
1496 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1497 int_params.irq_source =
1498 dc_interrupt_to_irq_source(dc, i, 0);
1499
1500 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1501
1502 c_irq_params->adev = adev;
1503 c_irq_params->irq_src = int_params.irq_source;
1504
1505 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1506 dm_pflip_high_irq, c_irq_params);
1507
1508 }
1509
1510 /* HPD */
3760f76c 1511 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1512 &adev->hpd_irq);
1513 if (r) {
1514 DRM_ERROR("Failed to add hpd irq id!\n");
1515 return r;
1516 }
1517
1518 register_hpd_handlers(adev);
1519
1520 return 0;
1521}
1522#endif
1523
eb3dc897
NK		 1524/*
1525 * Acquires the lock for the atomic state object and returns
1526 * the new atomic state.
1527 *
1528 * This should only be called during atomic check.
1529 */
1530static int dm_atomic_get_state(struct drm_atomic_state *state,
1531 struct dm_atomic_state **dm_state)
1532{
1533 struct drm_device *dev = state->dev;
1534 struct amdgpu_device *adev = dev->dev_private;
1535 struct amdgpu_display_manager *dm = &adev->dm;
1536 struct drm_private_state *priv_state;
1537 int ret;
1538
1539 if (*dm_state)
1540 return 0;
1541
1542 ret = drm_modeset_lock(&dm->atomic_obj_lock, state->acquire_ctx);
1543 if (ret)
1544 return ret;
1545
1546 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1547 if (IS_ERR(priv_state))
1548 return PTR_ERR(priv_state);
1549
1550 *dm_state = to_dm_atomic_state(priv_state);
1551
1552 return 0;
1553}
1554
1555struct dm_atomic_state *
1556dm_atomic_get_new_state(struct drm_atomic_state *state)
1557{
1558 struct drm_device *dev = state->dev;
1559 struct amdgpu_device *adev = dev->dev_private;
1560 struct amdgpu_display_manager *dm = &adev->dm;
1561 struct drm_private_obj *obj;
1562 struct drm_private_state *new_obj_state;
1563 int i;
1564
1565 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1566 if (obj->funcs == dm->atomic_obj.funcs)
1567 return to_dm_atomic_state(new_obj_state);
1568 }
1569
1570 return NULL;
1571}
1572
1573struct dm_atomic_state *
1574dm_atomic_get_old_state(struct drm_atomic_state *state)
1575{
1576 struct drm_device *dev = state->dev;
1577 struct amdgpu_device *adev = dev->dev_private;
1578 struct amdgpu_display_manager *dm = &adev->dm;
1579 struct drm_private_obj *obj;
1580 struct drm_private_state *old_obj_state;
1581 int i;
1582
1583 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1584 if (obj->funcs == dm->atomic_obj.funcs)
1585 return to_dm_atomic_state(old_obj_state);
1586 }
1587
1588 return NULL;
1589}
1590
1591static struct drm_private_state *
1592dm_atomic_duplicate_state(struct drm_private_obj *obj)
1593{
1594 struct dm_atomic_state *old_state, *new_state;
1595
1596 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1597 if (!new_state)
1598 return NULL;
1599
1600 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1601
1602 new_state->context = dc_create_state();
1603 if (!new_state->context) {
1604 kfree(new_state);
1605 return NULL;
1606 }
1607
1608 old_state = to_dm_atomic_state(obj->state);
1609 if (old_state && old_state->context)
1610 dc_resource_state_copy_construct(old_state->context,
1611 new_state->context);
1612
1613 return &new_state->base;
1614}
1615
1616static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1617 struct drm_private_state *state)
1618{
1619 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1620
1621 if (dm_state && dm_state->context)
1622 dc_release_state(dm_state->context);
1623
1624 kfree(dm_state);
1625}
1626
1627static struct drm_private_state_funcs dm_atomic_state_funcs = {
1628 .atomic_duplicate_state = dm_atomic_duplicate_state,
1629 .atomic_destroy_state = dm_atomic_destroy_state,
1630};
1631
4562236b
HW		 1632static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1633{
eb3dc897 1634 struct dm_atomic_state *state;
4562236b
HW		 1635 int r;
1636
1637 adev->mode_info.mode_config_initialized = true;
1638
4562236b 1639 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1640 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1641
1642 adev->ddev->mode_config.max_width = 16384;
1643 adev->ddev->mode_config.max_height = 16384;
1644
1645 adev->ddev->mode_config.preferred_depth = 24;
1646 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 1647 /* indicates support for immediate flip */
4562236b
HW		 1648 adev->ddev->mode_config.async_page_flip = true;
1649
770d13b1 1650 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1651
eb3dc897
NK		 1652 drm_modeset_lock_init(&adev->dm.atomic_obj_lock);
1653
1654 state = kzalloc(sizeof(*state), GFP_KERNEL);
1655 if (!state)
1656 return -ENOMEM;
1657
1658 state->context = dc_create_state();
1659 if (!state->context) {
1660 kfree(state);
1661 return -ENOMEM;
1662 }
1663
1664 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1665
1666 drm_atomic_private_obj_init(&adev->dm.atomic_obj,
1667 &state->base,
1668 &dm_atomic_state_funcs);
1669
3dc9b1ce 1670 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1671 if (r)
1672 return r;
1673
1674 return 0;
1675}
1676
206bbafe
DF		 1677#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1678#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1679
4562236b
HW		 1680#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1681 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1682
206bbafe
DF		 1683static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1684{
1685#if defined(CONFIG_ACPI)
1686 struct amdgpu_dm_backlight_caps caps;
1687
1688 if (dm->backlight_caps.caps_valid)
1689 return;
1690
1691 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1692 if (caps.caps_valid) {
1693 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1694 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1695 dm->backlight_caps.caps_valid = true;
1696 } else {
1697 dm->backlight_caps.min_input_signal =
1698 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1699 dm->backlight_caps.max_input_signal =
1700 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1701 }
1702#else
8bcbc9ef
DF		 1703 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1704 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 1705#endif
1706}
1707
4562236b
HW		 1708static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1709{
1710 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe
DF		 1711 struct amdgpu_dm_backlight_caps caps;
1712 uint32_t brightness = bd->props.brightness;
4562236b 1713
206bbafe
DF		 1714 amdgpu_dm_update_backlight_caps(dm);
1715 caps = dm->backlight_caps;
0cafc82f 1716 /*
206bbafe
DF		 1717 * The brightness input is in the range 0-255
1718 * It needs to be rescaled to be between the
1719 * requested min and max input signal
1720 *
1721 * It also needs to be scaled up by 0x101 to
1722 * match the DC interface which has a range of
1723 * 0 to 0xffff
0cafc82f 1724 */
206bbafe
DF		 1725 brightness =
1726 brightness
1727 * 0x101
1728 * (caps.max_input_signal - caps.min_input_signal)
1729 / AMDGPU_MAX_BL_LEVEL
1730 + caps.min_input_signal * 0x101;
262485a5 1731
4562236b 1732 if (dc_link_set_backlight_level(dm->backlight_link,
694d0775 1733 brightness, 0, 0))
4562236b
HW		 1734 return 0;
1735 else
1736 return 1;
1737}
1738
1739static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1740{
620a0d27
DF		 1741 struct amdgpu_display_manager *dm = bl_get_data(bd);
1742 int ret = dc_link_get_backlight_level(dm->backlight_link);
1743
1744 if (ret == DC_ERROR_UNEXPECTED)
1745 return bd->props.brightness;
1746 return ret;
4562236b
HW		 1747}
1748
1749static const struct backlight_ops amdgpu_dm_backlight_ops = {
1750 .get_brightness = amdgpu_dm_backlight_get_brightness,
1751 .update_status = amdgpu_dm_backlight_update_status,
1752};
1753
7578ecda
AD		 1754static void
1755amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1756{
1757 char bl_name[16];
1758 struct backlight_properties props = { 0 };
1759
206bbafe
DF		 1760 amdgpu_dm_update_backlight_caps(dm);
1761
4562236b 1762 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 1763 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 1764 props.type = BACKLIGHT_RAW;
1765
1766 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1767 dm->adev->ddev->primary->index);
1768
1769 dm->backlight_dev = backlight_device_register(bl_name,
1770 dm->adev->ddev->dev,
1771 dm,
1772 &amdgpu_dm_backlight_ops,
1773 &props);
1774
74baea42 1775 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1776 DRM_ERROR("DM: Backlight registration failed!\n");
1777 else
f1ad2f5e 1778 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1779}
1780
1781#endif
1782
df534fff
S		 1783static int initialize_plane(struct amdgpu_display_manager *dm,
1784 struct amdgpu_mode_info *mode_info,
1785 int plane_id)
1786{
f180b4bc 1787 struct drm_plane *plane;
df534fff
S		 1788 unsigned long possible_crtcs;
1789 int ret = 0;
1790
f180b4bc 1791 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 1792 mode_info->planes[plane_id] = plane;
1793
1794 if (!plane) {
1795 DRM_ERROR("KMS: Failed to allocate plane\n");
1796 return -ENOMEM;
1797 }
f180b4bc 1798 plane->type = mode_info->plane_type[plane_id];
df534fff
S		 1799
1800 /*
1f6010a9 1801 * HACK: IGT tests expect that each plane can only have
df534fff
S		 1802 * one possible CRTC. For now, set one CRTC for each
1803 * plane that is not an underlay, but still allow multiple
1804 * CRTCs for underlay planes.
1805 */
1806 possible_crtcs = 1 << plane_id;
1807 if (plane_id >= dm->dc->caps.max_streams)
1808 possible_crtcs = 0xff;
1809
1810 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1811
1812 if (ret) {
1813 DRM_ERROR("KMS: Failed to initialize plane\n");
1814 return ret;
1815 }
1816
1817 return ret;
1818}
1819
89fc8d4e
HW		 1820
1821static void register_backlight_device(struct amdgpu_display_manager *dm,
1822 struct dc_link *link)
1823{
1824#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1825 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1826
1827 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1828 link->type != dc_connection_none) {
1f6010a9
DF		 1829 /*
1830 * Event if registration failed, we should continue with
89fc8d4e
HW		 1831 * DM initialization because not having a backlight control
1832 * is better then a black screen.
1833 */
1834 amdgpu_dm_register_backlight_device(dm);
1835
1836 if (dm->backlight_dev)
1837 dm->backlight_link = link;
1838 }
1839#endif
1840}
1841
1842
1f6010a9
DF		 1843/*
1844 * In this architecture, the association
4562236b
HW		 1845 * connector -> encoder -> crtc
1846 * id not really requried. The crtc and connector will hold the
1847 * display_index as an abstraction to use with DAL component
1848 *
1849 * Returns 0 on success
1850 */
7578ecda 1851static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1852{
1853 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 1854 int32_t i;
c84dec2f 1855 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1856 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1857 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1858 uint32_t link_cnt;
df534fff 1859 int32_t total_overlay_planes, total_primary_planes;
fbbdadf2 1860 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b
HW		 1861
1862 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1863 if (amdgpu_dm_mode_config_init(dm->adev)) {
1864 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 1865 return -EINVAL;
4562236b
HW		 1866 }
1867
df534fff
S		 1868 /* Identify the number of planes to be initialized */
1869 total_overlay_planes = dm->dc->caps.max_slave_planes;
1870 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
efa6a8b7 1871
df534fff
S		 1872 /* First initialize overlay planes, index starting after primary planes */
1873 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1874 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1875 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 1876 goto fail;
d4e13b0d 1877 }
df534fff 1878 }
92f3ac40 1879
df534fff
S		 1880 /* Initialize primary planes */
1881 for (i = (total_primary_planes - 1); i >= 0; i--) {
1882 if (initialize_plane(dm, mode_info, i)) {
1883 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 1884 goto fail;
d4e13b0d
AD		 1885 }
1886 }
4562236b 1887
d4e13b0d 1888 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 1889 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 1890 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1891 goto fail;
4562236b 1892 }
4562236b 1893
ab2541b6 1894 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1895
1896 /* loops over all connectors on the board */
1897 for (i = 0; i < link_cnt; i++) {
89fc8d4e 1898 struct dc_link *link = NULL;
4562236b
HW		 1899
1900 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1901 DRM_ERROR(
1902 "KMS: Cannot support more than %d display indexes\n",
1903 AMDGPU_DM_MAX_DISPLAY_INDEX);
1904 continue;
1905 }
1906
1907 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1908 if (!aconnector)
cd8a2ae8 1909 goto fail;
4562236b
HW		 1910
1911 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1912 if (!aencoder)
cd8a2ae8 1913 goto fail;
4562236b
HW		 1914
1915 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1916 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1917 goto fail;
4562236b
HW		 1918 }
1919
1920 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1921 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1922 goto fail;
4562236b
HW		 1923 }
1924
89fc8d4e
HW		 1925 link = dc_get_link_at_index(dm->dc, i);
1926
fbbdadf2
BL		 1927 if (!dc_link_detect_sink(link, &new_connection_type))
1928 DRM_ERROR("KMS: Failed to detect connector\n");
1929
1930 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1931 emulated_link_detect(link);
1932 amdgpu_dm_update_connector_after_detect(aconnector);
1933
1934 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 1935 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 1936 register_backlight_device(dm, link);
1937 }
1938
1939
4562236b
HW		 1940 }
1941
1942 /* Software is initialized. Now we can register interrupt handlers. */
1943 switch (adev->asic_type) {
1944 case CHIP_BONAIRE:
1945 case CHIP_HAWAII:
cd4b356f
AD		 1946 case CHIP_KAVERI:
1947 case CHIP_KABINI:
1948 case CHIP_MULLINS:
4562236b
HW		 1949 case CHIP_TONGA:
1950 case CHIP_FIJI:
1951 case CHIP_CARRIZO:
1952 case CHIP_STONEY:
1953 case CHIP_POLARIS11:
1954 case CHIP_POLARIS10:
b264d345 1955 case CHIP_POLARIS12:
7737de91 1956 case CHIP_VEGAM:
2c8ad2d5 1957 case CHIP_VEGA10:
2325ff30 1958 case CHIP_VEGA12:
1fe6bf2f 1959 case CHIP_VEGA20:
4562236b
HW		 1960 if (dce110_register_irq_handlers(dm->adev)) {
1961 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1962 goto fail;
4562236b
HW		 1963 }
1964 break;
ff5ef992
AD		 1965#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1966 case CHIP_RAVEN:
1967 if (dcn10_register_irq_handlers(dm->adev)) {
1968 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1969 goto fail;
ff5ef992
AD		 1970 }
1971 break;
1972#endif
4562236b 1973 default:
e63f8673 1974 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 1975 goto fail;
4562236b
HW		 1976 }
1977
1bc460a4
HW		 1978 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1979 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1980
4562236b 1981 return 0;
cd8a2ae8 1982fail:
4562236b 1983 kfree(aencoder);
4562236b 1984 kfree(aconnector);
3be5262e 1985 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1986 kfree(mode_info->planes[i]);
59d0f396 1987 return -EINVAL;
4562236b
HW		 1988}
1989
7578ecda 1990static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1991{
1992 drm_mode_config_cleanup(dm->ddev);
eb3dc897 1993 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 1994 return;
1995}
1996
1997/******************************************************************************
1998 * amdgpu_display_funcs functions
1999 *****************************************************************************/
2000
1f6010a9 2001/*
4562236b
HW		 2002 * dm_bandwidth_update - program display watermarks
2003 *
2004 * @adev: amdgpu_device pointer
2005 *
2006 * Calculate and program the display watermarks and line buffer allocation.
2007 */
2008static void dm_bandwidth_update(struct amdgpu_device *adev)
2009{
49c07a99 2010 /* TODO: implement later */
4562236b
HW		 2011}
2012
4562236b
HW		 2013static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
2014 struct drm_file *filp)
2015{
98e6436d
AK		 2016 struct drm_atomic_state *state;
2017 struct drm_modeset_acquire_ctx ctx;
2018 struct drm_crtc *crtc;
2019 struct drm_connector *connector;
2020 struct drm_connector_state *old_con_state, *new_con_state;
2021 int ret = 0;
4562236b 2022 uint8_t i;
98e6436d 2023 bool enable = false;
4562236b 2024
98e6436d 2025 drm_modeset_acquire_init(&ctx, 0);
4562236b 2026
98e6436d
AK		 2027 state = drm_atomic_state_alloc(dev);
2028 if (!state) {
2029 ret = -ENOMEM;
2030 goto out;
2031 }
2032 state->acquire_ctx = &ctx;
2033
2034retry:
2035 drm_for_each_crtc(crtc, dev) {
2036 ret = drm_atomic_add_affected_connectors(state, crtc);
2037 if (ret)
2038 goto fail;
2039
2040 /* TODO rework amdgpu_dm_commit_planes so we don't need this */
2041 ret = drm_atomic_add_affected_planes(state, crtc);
2042 if (ret)
2043 goto fail;
2044 }
4562236b 2045
98e6436d
AK		 2046 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
2047 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
2048 struct drm_crtc_state *new_crtc_state;
2049 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
2050 struct dm_crtc_state *dm_new_crtc_state;
4562236b 2051
98e6436d
AK		 2052 if (!acrtc) {
2053 ASSERT(0);
2054 continue;
2055 }
4562236b 2056
98e6436d
AK		 2057 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
2058 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4562236b 2059
98e6436d 2060 dm_new_crtc_state->freesync_enabled = enable;
4562236b
HW		 2061 }
2062
98e6436d
AK		 2063 ret = drm_atomic_commit(state);
2064
2065fail:
2066 if (ret == -EDEADLK) {
2067 drm_atomic_state_clear(state);
2068 drm_modeset_backoff(&ctx);
2069 goto retry;
2070 }
2071
2072 drm_atomic_state_put(state);
2073
2074out:
2075 drm_modeset_drop_locks(&ctx);
2076 drm_modeset_acquire_fini(&ctx);
2077 return ret;
4562236b
HW		 2078}
2079
39cc5be2 2080static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 2081 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2082 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 2083 .backlight_set_level = NULL, /* never called for DC */
2084 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 2085 .hpd_sense = NULL,/* called unconditionally */
2086 .hpd_set_polarity = NULL, /* called unconditionally */
2087 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2088 .page_flip_get_scanoutpos =
2089 dm_crtc_get_scanoutpos,/* called unconditionally */
2090 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2091 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2092 .notify_freesync = amdgpu_notify_freesync,
2093
2094};
2095
2096#if defined(CONFIG_DEBUG_KERNEL_DC)
2097
3ee6b26b
AD		 2098static ssize_t s3_debug_store(struct device *device,
2099 struct device_attribute *attr,
2100 const char *buf,
2101 size_t count)
4562236b
HW		 2102{
2103 int ret;
2104 int s3_state;
2105 struct pci_dev *pdev = to_pci_dev(device);
2106 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2107 struct amdgpu_device *adev = drm_dev->dev_private;
2108
2109 ret = kstrtoint(buf, 0, &s3_state);
2110
2111 if (ret == 0) {
2112 if (s3_state) {
2113 dm_resume(adev);
4562236b
HW		 2114 drm_kms_helper_hotplug_event(adev->ddev);
2115 } else
2116 dm_suspend(adev);
2117 }
2118
2119 return ret == 0 ? count : 0;
2120}
2121
2122DEVICE_ATTR_WO(s3_debug);
2123
2124#endif
2125
2126static int dm_early_init(void *handle)
2127{
2128 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2129
4562236b
HW		 2130 switch (adev->asic_type) {
2131 case CHIP_BONAIRE:
2132 case CHIP_HAWAII:
2133 adev->mode_info.num_crtc = 6;
2134 adev->mode_info.num_hpd = 6;
2135 adev->mode_info.num_dig = 6;
3be5262e 2136 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 2137 break;
cd4b356f
AD		 2138 case CHIP_KAVERI:
2139 adev->mode_info.num_crtc = 4;
2140 adev->mode_info.num_hpd = 6;
2141 adev->mode_info.num_dig = 7;
2142 adev->mode_info.plane_type = dm_plane_type_default;
2143 break;
2144 case CHIP_KABINI:
2145 case CHIP_MULLINS:
2146 adev->mode_info.num_crtc = 2;
2147 adev->mode_info.num_hpd = 6;
2148 adev->mode_info.num_dig = 6;
2149 adev->mode_info.plane_type = dm_plane_type_default;
2150 break;
4562236b
HW		 2151 case CHIP_FIJI:
2152 case CHIP_TONGA:
2153 adev->mode_info.num_crtc = 6;
2154 adev->mode_info.num_hpd = 6;
2155 adev->mode_info.num_dig = 7;
3be5262e 2156 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 2157 break;
2158 case CHIP_CARRIZO:
2159 adev->mode_info.num_crtc = 3;
2160 adev->mode_info.num_hpd = 6;
2161 adev->mode_info.num_dig = 9;
3be5262e 2162 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 2163 break;
2164 case CHIP_STONEY:
2165 adev->mode_info.num_crtc = 2;
2166 adev->mode_info.num_hpd = 6;
2167 adev->mode_info.num_dig = 9;
3be5262e 2168 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 2169 break;
2170 case CHIP_POLARIS11:
b264d345 2171 case CHIP_POLARIS12:
4562236b
HW		 2172 adev->mode_info.num_crtc = 5;
2173 adev->mode_info.num_hpd = 5;
2174 adev->mode_info.num_dig = 5;
3be5262e 2175 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 2176 break;
2177 case CHIP_POLARIS10:
7737de91 2178 case CHIP_VEGAM:
4562236b
HW		 2179 adev->mode_info.num_crtc = 6;
2180 adev->mode_info.num_hpd = 6;
2181 adev->mode_info.num_dig = 6;
3be5262e 2182 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 2183 break;
2c8ad2d5 2184 case CHIP_VEGA10:
2325ff30 2185 case CHIP_VEGA12:
1fe6bf2f 2186 case CHIP_VEGA20:
2c8ad2d5
AD		 2187 adev->mode_info.num_crtc = 6;
2188 adev->mode_info.num_hpd = 6;
2189 adev->mode_info.num_dig = 6;
3be5262e 2190 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 2191 break;
ff5ef992
AD		 2192#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2193 case CHIP_RAVEN:
2194 adev->mode_info.num_crtc = 4;
2195 adev->mode_info.num_hpd = 4;
2196 adev->mode_info.num_dig = 4;
3be5262e 2197 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 2198 break;
2199#endif
4562236b 2200 default:
e63f8673 2201 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 2202 return -EINVAL;
2203 }
2204
c8dd5715
MD		 2205 amdgpu_dm_set_irq_funcs(adev);
2206
39cc5be2
AD		 2207 if (adev->mode_info.funcs == NULL)
2208 adev->mode_info.funcs = &dm_display_funcs;
2209
1f6010a9
DF		 2210 /*
2211 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 2212 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 2213 * amdgpu_device_init()
2214 */
4562236b
HW		 2215#if defined(CONFIG_DEBUG_KERNEL_DC)
2216 device_create_file(
2217 adev->ddev->dev,
2218 &dev_attr_s3_debug);
2219#endif
2220
2221 return 0;
2222}
2223
9b690ef3 2224static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 2225 struct dc_stream_state *new_stream,
2226 struct dc_stream_state *old_stream)
9b690ef3 2227{
e7b07cee
HW		 2228 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2229 return false;
2230
2231 if (!crtc_state->enable)
2232 return false;
2233
2234 return crtc_state->active;
2235}
2236
2237static bool modereset_required(struct drm_crtc_state *crtc_state)
2238{
2239 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2240 return false;
2241
2242 return !crtc_state->enable || !crtc_state->active;
2243}
2244
7578ecda 2245static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 2246{
2247 drm_encoder_cleanup(encoder);
2248 kfree(encoder);
2249}
2250
2251static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2252 .destroy = amdgpu_dm_encoder_destroy,
2253};
2254
3ee6b26b
AD		 2255static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
2256 struct dc_plane_state *plane_state)
e7b07cee 2257{
3be5262e
HW		 2258 plane_state->src_rect.x = state->src_x >> 16;
2259 plane_state->src_rect.y = state->src_y >> 16;
1f6010a9 2260 /* we ignore the mantissa for now and do not deal with floating pixels :( */
3be5262e 2261 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 2262
3be5262e 2263 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 2264 return false;
2265
3be5262e
HW		 2266 plane_state->src_rect.height = state->src_h >> 16;
2267 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 2268 return false;
2269
3be5262e
HW		 2270 plane_state->dst_rect.x = state->crtc_x;
2271 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 2272
2273 if (state->crtc_w == 0)
2274 return false;
2275
3be5262e 2276 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 2277
2278 if (state->crtc_h == 0)
2279 return false;
2280
3be5262e 2281 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 2282
3be5262e 2283 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 2284
2285 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
2286 case DRM_MODE_ROTATE_0:
3be5262e 2287 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2288 break;
2289 case DRM_MODE_ROTATE_90:
3be5262e 2290 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 2291 break;
2292 case DRM_MODE_ROTATE_180:
3be5262e 2293 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 2294 break;
2295 case DRM_MODE_ROTATE_270:
3be5262e 2296 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 2297 break;
2298 default:
3be5262e 2299 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2300 break;
2301 }
2302
4562236b
HW		 2303 return true;
2304}
3ee6b26b 2305static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 2306 uint64_t *tiling_flags)
e7b07cee 2307{
e68d14dd 2308 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 2309 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 2310
e7b07cee 2311 if (unlikely(r)) {
1f6010a9 2312 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 2313 if (r != -ERESTARTSYS)
2314 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 2315 return r;
2316 }
2317
e7b07cee
HW		 2318 if (tiling_flags)
2319 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2320
2321 amdgpu_bo_unreserve(rbo);
2322
2323 return r;
2324}
2325
3ee6b26b
AD		 2326static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
2327 struct dc_plane_state *plane_state,
9817d5f5 2328 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 2329{
2330 uint64_t tiling_flags;
e7b07cee
HW		 2331 unsigned int awidth;
2332 const struct drm_framebuffer *fb = &amdgpu_fb->base;
2333 int ret = 0;
2334 struct drm_format_name_buf format_name;
2335
2336 ret = get_fb_info(
2337 amdgpu_fb,
9817d5f5 2338 &tiling_flags);
e7b07cee
HW		 2339
2340 if (ret)
2341 return ret;
2342
2343 switch (fb->format->format) {
2344 case DRM_FORMAT_C8:
3be5262e 2345 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 2346 break;
2347 case DRM_FORMAT_RGB565:
3be5262e 2348 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 2349 break;
2350 case DRM_FORMAT_XRGB8888:
2351 case DRM_FORMAT_ARGB8888:
3be5262e 2352 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 2353 break;
2354 case DRM_FORMAT_XRGB2101010:
2355 case DRM_FORMAT_ARGB2101010:
3be5262e 2356 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 2357 break;
2358 case DRM_FORMAT_XBGR2101010:
2359 case DRM_FORMAT_ABGR2101010:
3be5262e 2360 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee 2361 break;
bcd47f60
MR		 2362 case DRM_FORMAT_XBGR8888:
2363 case DRM_FORMAT_ABGR8888:
2364 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2365 break;
e7b07cee 2366 case DRM_FORMAT_NV21:
3be5262e 2367 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 2368 break;
2369 case DRM_FORMAT_NV12:
3be5262e 2370 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 2371 break;
2372 default:
2373 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 2374 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 2375 return -EINVAL;
2376 }
2377
3be5262e
HW		 2378 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2379 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 2380 plane_state->plane_size.grph.surface_size.x = 0;
2381 plane_state->plane_size.grph.surface_size.y = 0;
2382 plane_state->plane_size.grph.surface_size.width = fb->width;
2383 plane_state->plane_size.grph.surface_size.height = fb->height;
2384 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 2385 fb->pitches[0] / fb->format->cpp[0];
2386 /* TODO: unhardcode */
3be5262e 2387 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 2388
2389 } else {
2390 awidth = ALIGN(fb->width, 64);
3be5262e 2391 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 2392 plane_state->plane_size.video.luma_size.x = 0;
2393 plane_state->plane_size.video.luma_size.y = 0;
2394 plane_state->plane_size.video.luma_size.width = awidth;
2395 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 2396 /* TODO: unhardcode */
3be5262e 2397 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 2398
3be5262e
HW		 2399 plane_state->plane_size.video.chroma_size.x = 0;
2400 plane_state->plane_size.video.chroma_size.y = 0;
2401 plane_state->plane_size.video.chroma_size.width = awidth;
2402 plane_state->plane_size.video.chroma_size.height = fb->height;
2403 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 2404
2405 /* TODO: unhardcode */
3be5262e 2406 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 2407 }
2408
3be5262e 2409 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 2410
b830ebc9
HW		 2411 /* Fill GFX8 params */
2412 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2413 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 2414
2415 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2416 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2417 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2418 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2419 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2420
2421 /* XXX fix me for VI */
3be5262e
HW		 2422 plane_state->tiling_info.gfx8.num_banks = num_banks;
2423 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 2424 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 2425 plane_state->tiling_info.gfx8.tile_split = tile_split;
2426 plane_state->tiling_info.gfx8.bank_width = bankw;
2427 plane_state->tiling_info.gfx8.bank_height = bankh;
2428 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2429 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 2430 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2431 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2432 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 2433 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 2434 }
2435
3be5262e 2436 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 2437 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2438
2439 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 2440 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 2441 adev->asic_type == CHIP_VEGA20 ||
e7b07cee
HW		 2442 adev->asic_type == CHIP_RAVEN) {
2443 /* Fill GFX9 params */
3be5262e 2444 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 2445 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 2446 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 2447 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 2448 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 2449 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 2450 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 2451 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 2452 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 2453 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 2454 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 2455 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 2456 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 2457 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 2458 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 2459 }
2460
3be5262e
HW		 2461 plane_state->visible = true;
2462 plane_state->scaling_quality.h_taps_c = 0;
2463 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 2464
3be5262e
HW		 2465 /* is this needed? is plane_state zeroed at allocation? */
2466 plane_state->scaling_quality.h_taps = 0;
2467 plane_state->scaling_quality.v_taps = 0;
2468 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 2469
2470 return ret;
2471
2472}
2473
3ee6b26b
AD		 2474static int fill_plane_attributes(struct amdgpu_device *adev,
2475 struct dc_plane_state *dc_plane_state,
2476 struct drm_plane_state *plane_state,
9817d5f5 2477 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2478{
2479 const struct amdgpu_framebuffer *amdgpu_fb =
2480 to_amdgpu_framebuffer(plane_state->fb);
2481 const struct drm_crtc *crtc = plane_state->crtc;
e7b07cee
HW		 2482 int ret = 0;
2483
3be5262e 2484 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 2485 return -EINVAL;
2486
2487 ret = fill_plane_attributes_from_fb(
2488 crtc->dev->dev_private,
3be5262e 2489 dc_plane_state,
9817d5f5 2490 amdgpu_fb);
e7b07cee
HW		 2491
2492 if (ret)
2493 return ret;
2494
e277adc5
LSL		 2495 /*
2496 * Always set input transfer function, since plane state is refreshed
2497 * every time.
2498 */
2499 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2500 if (ret) {
2501 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2502 dc_plane_state->in_transfer_func = NULL;
2503 }
e7b07cee
HW		 2504
2505 return ret;
2506}
2507
3ee6b26b
AD		 2508static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2509 const struct dm_connector_state *dm_state,
2510 struct dc_stream_state *stream)
e7b07cee
HW		 2511{
2512 enum amdgpu_rmx_type rmx_type;
2513
2514 struct rect src = { 0 }; /* viewport in composition space*/
2515 struct rect dst = { 0 }; /* stream addressable area */
2516
2517 /* no mode. nothing to be done */
2518 if (!mode)
2519 return;
2520
2521 /* Full screen scaling by default */
2522 src.width = mode->hdisplay;
2523 src.height = mode->vdisplay;
2524 dst.width = stream->timing.h_addressable;
2525 dst.height = stream->timing.v_addressable;
2526
f4791779
HW		 2527 if (dm_state) {
2528 rmx_type = dm_state->scaling;
2529 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2530 if (src.width * dst.height <
2531 src.height * dst.width) {
2532 /* height needs less upscaling/more downscaling */
2533 dst.width = src.width *
2534 dst.height / src.height;
2535 } else {
2536 /* width needs less upscaling/more downscaling */
2537 dst.height = src.height *
2538 dst.width / src.width;
2539 }
2540 } else if (rmx_type == RMX_CENTER) {
2541 dst = src;
e7b07cee 2542 }
e7b07cee 2543
f4791779
HW		 2544 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2545 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2546
f4791779
HW		 2547 if (dm_state->underscan_enable) {
2548 dst.x += dm_state->underscan_hborder / 2;
2549 dst.y += dm_state->underscan_vborder / 2;
2550 dst.width -= dm_state->underscan_hborder;
2551 dst.height -= dm_state->underscan_vborder;
2552 }
e7b07cee
HW		 2553 }
2554
2555 stream->src = src;
2556 stream->dst = dst;
2557
f1ad2f5e 2558 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2559 dst.x, dst.y, dst.width, dst.height);
2560
2561}
2562
3ee6b26b
AD		 2563static enum dc_color_depth
2564convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee 2565{
cedde71c
NK		 2566 struct dm_connector_state *dm_conn_state =
2567 to_dm_connector_state(connector->state);
e7b07cee
HW		 2568 uint32_t bpc = connector->display_info.bpc;
2569
cedde71c
NK		 2570 /* TODO: Remove this when there's support for max_bpc in drm */
2571 if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2572 /* Round down to nearest even number. */
2573 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2574
e7b07cee
HW		 2575 switch (bpc) {
2576 case 0:
1f6010a9
DF		 2577 /*
2578 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 2579 * EDID revision before 1.4
2580 * TODO: Fix edid parsing
2581 */
2582 return COLOR_DEPTH_888;
2583 case 6:
2584 return COLOR_DEPTH_666;
2585 case 8:
2586 return COLOR_DEPTH_888;
2587 case 10:
2588 return COLOR_DEPTH_101010;
2589 case 12:
2590 return COLOR_DEPTH_121212;
2591 case 14:
2592 return COLOR_DEPTH_141414;
2593 case 16:
2594 return COLOR_DEPTH_161616;
2595 default:
2596 return COLOR_DEPTH_UNDEFINED;
2597 }
2598}
2599
3ee6b26b
AD		 2600static enum dc_aspect_ratio
2601get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 2602{
e11d4147
LSL		 2603 /* 1-1 mapping, since both enums follow the HDMI spec. */
2604 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 2605}
2606
3ee6b26b
AD		 2607static enum dc_color_space
2608get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2609{
2610 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2611
2612 switch (dc_crtc_timing->pixel_encoding) {
2613 case PIXEL_ENCODING_YCBCR422:
2614 case PIXEL_ENCODING_YCBCR444:
2615 case PIXEL_ENCODING_YCBCR420:
2616 {
2617 /*
2618 * 27030khz is the separation point between HDTV and SDTV
2619 * according to HDMI spec, we use YCbCr709 and YCbCr601
2620 * respectively
2621 */
2622 if (dc_crtc_timing->pix_clk_khz > 27030) {
2623 if (dc_crtc_timing->flags.Y_ONLY)
2624 color_space =
2625 COLOR_SPACE_YCBCR709_LIMITED;
2626 else
2627 color_space = COLOR_SPACE_YCBCR709;
2628 } else {
2629 if (dc_crtc_timing->flags.Y_ONLY)
2630 color_space =
2631 COLOR_SPACE_YCBCR601_LIMITED;
2632 else
2633 color_space = COLOR_SPACE_YCBCR601;
2634 }
2635
2636 }
2637 break;
2638 case PIXEL_ENCODING_RGB:
2639 color_space = COLOR_SPACE_SRGB;
2640 break;
2641
2642 default:
2643 WARN_ON(1);
2644 break;
2645 }
2646
2647 return color_space;
2648}
2649
400443e8
ML		 2650static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2651{
2652 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2653 return;
2654
2655 timing_out->display_color_depth--;
2656}
2657
2658static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2659 const struct drm_display_info *info)
2660{
2661 int normalized_clk;
2662 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2663 return;
2664 do {
2665 normalized_clk = timing_out->pix_clk_khz;
2666 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2667 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2668 normalized_clk /= 2;
2669 /* Adjusting pix clock following on HDMI spec based on colour depth */
2670 switch (timing_out->display_color_depth) {
2671 case COLOR_DEPTH_101010:
2672 normalized_clk = (normalized_clk * 30) / 24;
2673 break;
2674 case COLOR_DEPTH_121212:
2675 normalized_clk = (normalized_clk * 36) / 24;
2676 break;
2677 case COLOR_DEPTH_161616:
2678 normalized_clk = (normalized_clk * 48) / 24;
2679 break;
2680 default:
2681 return;
2682 }
2683 if (normalized_clk <= info->max_tmds_clock)
2684 return;
2685 reduce_mode_colour_depth(timing_out);
2686
2687 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2688
2689}
e7b07cee 2690
3ee6b26b
AD		 2691static void
2692fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2693 const struct drm_display_mode *mode_in,
b333730d
BL		 2694 const struct drm_connector *connector,
2695 const struct dc_stream_state *old_stream)
e7b07cee
HW		 2696{
2697 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 2698 const struct drm_display_info *info = &connector->display_info;
b830ebc9 2699
e7b07cee
HW		 2700 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2701
2702 timing_out->h_border_left = 0;
2703 timing_out->h_border_right = 0;
2704 timing_out->v_border_top = 0;
2705 timing_out->v_border_bottom = 0;
2706 /* TODO: un-hardcode */
fe61a2f1
ML		 2707 if (drm_mode_is_420_only(info, mode_in)
2708 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2709 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2710 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
e7b07cee
HW		 2711 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2712 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2713 else
2714 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2715
2716 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2717 timing_out->display_color_depth = convert_color_depth_from_display_info(
2718 connector);
2719 timing_out->scan_type = SCANNING_TYPE_NODATA;
2720 timing_out->hdmi_vic = 0;
b333730d
BL		 2721
2722 if(old_stream) {
2723 timing_out->vic = old_stream->timing.vic;
2724 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
2725 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
2726 } else {
2727 timing_out->vic = drm_match_cea_mode(mode_in);
2728 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2729 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2730 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2731 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2732 }
e7b07cee
HW		 2733
2734 timing_out->h_addressable = mode_in->crtc_hdisplay;
2735 timing_out->h_total = mode_in->crtc_htotal;
2736 timing_out->h_sync_width =
2737 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2738 timing_out->h_front_porch =
2739 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2740 timing_out->v_total = mode_in->crtc_vtotal;
2741 timing_out->v_addressable = mode_in->crtc_vdisplay;
2742 timing_out->v_front_porch =
2743 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2744 timing_out->v_sync_width =
2745 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2746 timing_out->pix_clk_khz = mode_in->crtc_clock;
2747 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 2748
2749 stream->output_color_space = get_output_color_space(timing_out);
2750
e43a432c
AK		 2751 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2752 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
400443e8
ML		 2753 if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2754 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 2755}
2756
3ee6b26b
AD		 2757static void fill_audio_info(struct audio_info *audio_info,
2758 const struct drm_connector *drm_connector,
2759 const struct dc_sink *dc_sink)
e7b07cee
HW		 2760{
2761 int i = 0;
2762 int cea_revision = 0;
2763 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2764
2765 audio_info->manufacture_id = edid_caps->manufacturer_id;
2766 audio_info->product_id = edid_caps->product_id;
2767
2768 cea_revision = drm_connector->display_info.cea_rev;
2769
d2b2562c
TSD		 2770 strncpy(audio_info->display_name,
2771 edid_caps->display_name,
2772 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2773
b830ebc9 2774 if (cea_revision >= 3) {
e7b07cee
HW		 2775 audio_info->mode_count = edid_caps->audio_mode_count;
2776
2777 for (i = 0; i < audio_info->mode_count; ++i) {
2778 audio_info->modes[i].format_code =
2779 (enum audio_format_code)
2780 (edid_caps->audio_modes[i].format_code);
2781 audio_info->modes[i].channel_count =
2782 edid_caps->audio_modes[i].channel_count;
2783 audio_info->modes[i].sample_rates.all =
2784 edid_caps->audio_modes[i].sample_rate;
2785 audio_info->modes[i].sample_size =
2786 edid_caps->audio_modes[i].sample_size;
2787 }
2788 }
2789
2790 audio_info->flags.all = edid_caps->speaker_flags;
2791
2792 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2793 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2794 audio_info->video_latency = drm_connector->video_latency[0];
2795 audio_info->audio_latency = drm_connector->audio_latency[0];
2796 }
2797
2798 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2799
2800}
2801
3ee6b26b
AD		 2802static void
2803copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2804 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2805{
2806 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2807 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2808 dst_mode->crtc_clock = src_mode->crtc_clock;
2809 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2810 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2811 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2812 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2813 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2814 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2815 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2816 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2817 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2818 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2819 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2820}
2821
3ee6b26b
AD		 2822static void
2823decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2824 const struct drm_display_mode *native_mode,
2825 bool scale_enabled)
e7b07cee
HW		 2826{
2827 if (scale_enabled) {
2828 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2829 } else if (native_mode->clock == drm_mode->clock &&
2830 native_mode->htotal == drm_mode->htotal &&
2831 native_mode->vtotal == drm_mode->vtotal) {
2832 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2833 } else {
2834 /* no scaling nor amdgpu inserted, no need to patch */
2835 }
2836}
2837
aed15309
ML		 2838static struct dc_sink *
2839create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 2840{
2e0ac3d6 2841 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 2842 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 2843 sink_init_data.link = aconnector->dc_link;
2844 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2845
2846 sink = dc_sink_create(&sink_init_data);
423788c7 2847 if (!sink) {
2e0ac3d6 2848 DRM_ERROR("Failed to create sink!\n");
aed15309 2849 return NULL;
423788c7 2850 }
2e0ac3d6 2851 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 2852
aed15309 2853 return sink;
2e0ac3d6
HW		 2854}
2855
fa2123db
ML		 2856static void set_multisync_trigger_params(
2857 struct dc_stream_state *stream)
2858{
2859 if (stream->triggered_crtc_reset.enabled) {
2860 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2861 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2862 }
2863}
2864
2865static void set_master_stream(struct dc_stream_state *stream_set[],
2866 int stream_count)
2867{
2868 int j, highest_rfr = 0, master_stream = 0;
2869
2870 for (j = 0; j < stream_count; j++) {
2871 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2872 int refresh_rate = 0;
2873
2874 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2875 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2876 if (refresh_rate > highest_rfr) {
2877 highest_rfr = refresh_rate;
2878 master_stream = j;
2879 }
2880 }
2881 }
2882 for (j = 0; j < stream_count; j++) {
03736f4c 2883 if (stream_set[j])
fa2123db
ML		 2884 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2885 }
2886}
2887
2888static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2889{
2890 int i = 0;
2891
2892 if (context->stream_count < 2)
2893 return;
2894 for (i = 0; i < context->stream_count ; i++) {
2895 if (!context->streams[i])
2896 continue;
1f6010a9
DF		 2897 /*
2898 * TODO: add a function to read AMD VSDB bits and set
fa2123db 2899 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 2900 * For now it's set to false
fa2123db
ML		 2901 */
2902 set_multisync_trigger_params(context->streams[i]);
2903 }
2904 set_master_stream(context->streams, context->stream_count);
2905}
2906
3ee6b26b
AD		 2907static struct dc_stream_state *
2908create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2909 const struct drm_display_mode *drm_mode,
b333730d
BL		 2910 const struct dm_connector_state *dm_state,
2911 const struct dc_stream_state *old_stream)
e7b07cee
HW		 2912{
2913 struct drm_display_mode *preferred_mode = NULL;
391ef035 2914 struct drm_connector *drm_connector;
0971c40e 2915 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2916 struct drm_display_mode mode = *drm_mode;
2917 bool native_mode_found = false;
b333730d
BL		 2918 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
2919 int mode_refresh;
2920 int preferred_refresh;
2921
aed15309 2922 struct dc_sink *sink = NULL;
b830ebc9 2923 if (aconnector == NULL) {
e7b07cee 2924 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2925 return stream;
e7b07cee
HW		 2926 }
2927
e7b07cee 2928 drm_connector = &aconnector->base;
2e0ac3d6 2929
f4ac176e 2930 if (!aconnector->dc_sink) {
8be17ac9
JFZ		 2931 if (!aconnector->mst_port) {
2932 sink = create_fake_sink(aconnector);
2933 if (!sink)
2934 return stream;
391ef035 2935 }
aed15309
ML		 2936 } else {
2937 sink = aconnector->dc_sink;
f4ac176e 2938 }
2e0ac3d6 2939
aed15309 2940 stream = dc_create_stream_for_sink(sink);
4562236b 2941
b830ebc9 2942 if (stream == NULL) {
e7b07cee 2943 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 2944 goto finish;
e7b07cee
HW		 2945 }
2946
2947 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2948 /* Search for preferred mode */
2949 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2950 native_mode_found = true;
2951 break;
2952 }
2953 }
2954 if (!native_mode_found)
2955 preferred_mode = list_first_entry_or_null(
2956 &aconnector->base.modes,
2957 struct drm_display_mode,
2958 head);
2959
b333730d
BL		 2960 mode_refresh = drm_mode_vrefresh(&mode);
2961
b830ebc9 2962 if (preferred_mode == NULL) {
1f6010a9
DF		 2963 /*
2964 * This may not be an error, the use case is when we have no
e7b07cee
HW		 2965 * usermode calls to reset and set mode upon hotplug. In this
2966 * case, we call set mode ourselves to restore the previous mode
2967 * and the modelist may not be filled in in time.
2968 */
f1ad2f5e 2969 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2970 } else {
2971 decide_crtc_timing_for_drm_display_mode(
2972 &mode, preferred_mode,
f4791779 2973 dm_state ? (dm_state->scaling != RMX_OFF) : false);
e7b07cee
HW		 2974 }
2975
f783577c
JFZ		 2976 if (!dm_state)
2977 drm_mode_set_crtcinfo(&mode, 0);
2978
b333730d
BL		 2979 preferred_refresh = drm_mode_vrefresh(preferred_mode);
2980
2981 /*
2982 * If scaling is enabled and refresh rate didn't change
2983 * we copy the vic and polarities of the old timings
2984 */
2985 if (!scale || mode_refresh != preferred_refresh)
2986 fill_stream_properties_from_drm_display_mode(stream,
2987 &mode, &aconnector->base, NULL);
2988 else
2989 fill_stream_properties_from_drm_display_mode(stream,
2990 &mode, &aconnector->base, old_stream);
2991
e7b07cee
HW		 2992 update_stream_scaling_settings(&mode, dm_state, stream);
2993
2994 fill_audio_info(
2995 &stream->audio_info,
2996 drm_connector,
aed15309 2997 sink);
e7b07cee 2998
9182b4cb
HW		 2999 update_stream_signal(stream);
3000
9e3efe3e
HW		 3001 if (dm_state && dm_state->freesync_capable)
3002 stream->ignore_msa_timing_param = true;
aed15309 3003finish:
fbbdadf2 3004 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON)
aed15309 3005 dc_sink_release(sink);
9e3efe3e 3006
e7b07cee
HW		 3007 return stream;
3008}
3009
7578ecda 3010static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 3011{
3012 drm_crtc_cleanup(crtc);
3013 kfree(crtc);
3014}
3015
3016static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 3017 struct drm_crtc_state *state)
e7b07cee
HW		 3018{
3019 struct dm_crtc_state *cur = to_dm_crtc_state(state);
3020
3021 /* TODO Destroy dc_stream objects are stream object is flattened */
3022 if (cur->stream)
3023 dc_stream_release(cur->stream);
3024
3025
3026 __drm_atomic_helper_crtc_destroy_state(state);
3027
3028
3029 kfree(state);
3030}
3031
3032static void dm_crtc_reset_state(struct drm_crtc *crtc)
3033{
3034 struct dm_crtc_state *state;
3035
3036 if (crtc->state)
3037 dm_crtc_destroy_state(crtc, crtc->state);
3038
3039 state = kzalloc(sizeof(*state), GFP_KERNEL);
3040 if (WARN_ON(!state))
3041 return;
3042
3043 crtc->state = &state->base;
3044 crtc->state->crtc = crtc;
3045
3046}
3047
3048static struct drm_crtc_state *
3049dm_crtc_duplicate_state(struct drm_crtc *crtc)
3050{
3051 struct dm_crtc_state *state, *cur;
3052
3053 cur = to_dm_crtc_state(crtc->state);
3054
3055 if (WARN_ON(!crtc->state))
3056 return NULL;
3057
2004f45e 3058 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 3059 if (!state)
3060 return NULL;
e7b07cee
HW		 3061
3062 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3063
3064 if (cur->stream) {
3065 state->stream = cur->stream;
3066 dc_stream_retain(state->stream);
3067 }
3068
98e6436d
AK		 3069 state->adjust = cur->adjust;
3070 state->vrr_infopacket = cur->vrr_infopacket;
3071 state->freesync_enabled = cur->freesync_enabled;
c1ee92f9 3072 state->abm_level = cur->abm_level;
98e6436d 3073
e7b07cee
HW		 3074 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3075
3076 return &state->base;
3077}
3078
589d2739
HW		 3079
3080static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3081{
3082 enum dc_irq_source irq_source;
3083 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3084 struct amdgpu_device *adev = crtc->dev->dev_private;
3085
3086 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 3087 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 3088}
3089
3090static int dm_enable_vblank(struct drm_crtc *crtc)
3091{
3092 return dm_set_vblank(crtc, true);
3093}
3094
3095static void dm_disable_vblank(struct drm_crtc *crtc)
3096{
3097 dm_set_vblank(crtc, false);
3098}
3099
e7b07cee
HW		 3100/* Implemented only the options currently availible for the driver */
3101static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3102 .reset = dm_crtc_reset_state,
3103 .destroy = amdgpu_dm_crtc_destroy,
3104 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3105 .set_config = drm_atomic_helper_set_config,
3106 .page_flip = drm_atomic_helper_page_flip,
3107 .atomic_duplicate_state = dm_crtc_duplicate_state,
3108 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 3109 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 3110 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
589d2739
HW		 3111 .enable_vblank = dm_enable_vblank,
3112 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 3113};
3114
3115static enum drm_connector_status
3116amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3117{
3118 bool connected;
c84dec2f 3119 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 3120
1f6010a9
DF		 3121 /*
3122 * Notes:
e7b07cee
HW		 3123 * 1. This interface is NOT called in context of HPD irq.
3124 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 3125 * makes it a bad place for *any* MST-related activity.
3126 */
e7b07cee 3127
8580d60b
HW		 3128 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3129 !aconnector->fake_enable)
e7b07cee
HW		 3130 connected = (aconnector->dc_sink != NULL);
3131 else
3132 connected = (aconnector->base.force == DRM_FORCE_ON);
3133
3134 return (connected ? connector_status_connected :
3135 connector_status_disconnected);
3136}
3137
3ee6b26b
AD		 3138int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3139 struct drm_connector_state *connector_state,
3140 struct drm_property *property,
3141 uint64_t val)
e7b07cee
HW		 3142{
3143 struct drm_device *dev = connector->dev;
3144 struct amdgpu_device *adev = dev->dev_private;
3145 struct dm_connector_state *dm_old_state =
3146 to_dm_connector_state(connector->state);
3147 struct dm_connector_state *dm_new_state =
3148 to_dm_connector_state(connector_state);
3149
3150 int ret = -EINVAL;
3151
3152 if (property == dev->mode_config.scaling_mode_property) {
3153 enum amdgpu_rmx_type rmx_type;
3154
3155 switch (val) {
3156 case DRM_MODE_SCALE_CENTER:
3157 rmx_type = RMX_CENTER;
3158 break;
3159 case DRM_MODE_SCALE_ASPECT:
3160 rmx_type = RMX_ASPECT;
3161 break;
3162 case DRM_MODE_SCALE_FULLSCREEN:
3163 rmx_type = RMX_FULL;
3164 break;
3165 case DRM_MODE_SCALE_NONE:
e7b07cee
HW		 3166 rmx_type = RMX_OFF;
3167 break;
91b66c47
BL		 3168 default:
3169 rmx_type = RMX_ASPECT;
3170 break;
e7b07cee
HW		 3171 }
3172
3173 if (dm_old_state->scaling == rmx_type)
3174 return 0;
3175
3176 dm_new_state->scaling = rmx_type;
3177 ret = 0;
3178 } else if (property == adev->mode_info.underscan_hborder_property) {
3179 dm_new_state->underscan_hborder = val;
3180 ret = 0;
3181 } else if (property == adev->mode_info.underscan_vborder_property) {
3182 dm_new_state->underscan_vborder = val;
3183 ret = 0;
3184 } else if (property == adev->mode_info.underscan_property) {
3185 dm_new_state->underscan_enable = val;
3186 ret = 0;
cedde71c
NK		 3187 } else if (property == adev->mode_info.max_bpc_property) {
3188 dm_new_state->max_bpc = val;
3189 ret = 0;
c1ee92f9
DF		 3190 } else if (property == adev->mode_info.abm_level_property) {
3191 dm_new_state->abm_level = val;
3192 ret = 0;
e7b07cee
HW		 3193 }
3194
3195 return ret;
3196}
3197
3ee6b26b
AD		 3198int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3199 const struct drm_connector_state *state,
3200 struct drm_property *property,
3201 uint64_t *val)
e7b07cee
HW		 3202{
3203 struct drm_device *dev = connector->dev;
3204 struct amdgpu_device *adev = dev->dev_private;
3205 struct dm_connector_state *dm_state =
3206 to_dm_connector_state(state);
3207 int ret = -EINVAL;
3208
3209 if (property == dev->mode_config.scaling_mode_property) {
3210 switch (dm_state->scaling) {
3211 case RMX_CENTER:
3212 *val = DRM_MODE_SCALE_CENTER;
3213 break;
3214 case RMX_ASPECT:
3215 *val = DRM_MODE_SCALE_ASPECT;
3216 break;
3217 case RMX_FULL:
3218 *val = DRM_MODE_SCALE_FULLSCREEN;
3219 break;
3220 case RMX_OFF:
3221 default:
3222 *val = DRM_MODE_SCALE_NONE;
3223 break;
3224 }
3225 ret = 0;
3226 } else if (property == adev->mode_info.underscan_hborder_property) {
3227 *val = dm_state->underscan_hborder;
3228 ret = 0;
3229 } else if (property == adev->mode_info.underscan_vborder_property) {
3230 *val = dm_state->underscan_vborder;
3231 ret = 0;
3232 } else if (property == adev->mode_info.underscan_property) {
3233 *val = dm_state->underscan_enable;
3234 ret = 0;
cedde71c
NK		 3235 } else if (property == adev->mode_info.max_bpc_property) {
3236 *val = dm_state->max_bpc;
3237 ret = 0;
c1ee92f9
DF		 3238 } else if (property == adev->mode_info.abm_level_property) {
3239 *val = dm_state->abm_level;
3240 ret = 0;
e7b07cee 3241 }
c1ee92f9 3242
e7b07cee
HW		 3243 return ret;
3244}
3245
7578ecda 3246static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 3247{
c84dec2f 3248 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3249 const struct dc_link *link = aconnector->dc_link;
3250 struct amdgpu_device *adev = connector->dev->dev_private;
3251 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 3252
e7b07cee
HW		 3253#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3254 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3255
89fc8d4e 3256 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 3257 link->type != dc_connection_none &&
3258 dm->backlight_dev) {
3259 backlight_device_unregister(dm->backlight_dev);
3260 dm->backlight_dev = NULL;
e7b07cee
HW		 3261 }
3262#endif
e86e8947 3263 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 3264 drm_connector_unregister(connector);
3265 drm_connector_cleanup(connector);
3266 kfree(connector);
3267}
3268
3269void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3270{
3271 struct dm_connector_state *state =
3272 to_dm_connector_state(connector->state);
3273
df099b9b
LSL		 3274 if (connector->state)
3275 __drm_atomic_helper_connector_destroy_state(connector->state);
3276
e7b07cee
HW		 3277 kfree(state);
3278
3279 state = kzalloc(sizeof(*state), GFP_KERNEL);
3280
3281 if (state) {
91b66c47 3282 state->scaling = RMX_ASPECT;
e7b07cee
HW		 3283 state->underscan_enable = false;
3284 state->underscan_hborder = 0;
3285 state->underscan_vborder = 0;
3286
df099b9b 3287 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 3288 }
3289}
3290
3ee6b26b
AD		 3291struct drm_connector_state *
3292amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 3293{
3294 struct dm_connector_state *state =
3295 to_dm_connector_state(connector->state);
3296
3297 struct dm_connector_state *new_state =
3298 kmemdup(state, sizeof(*state), GFP_KERNEL);
3299
98e6436d
AK		 3300 if (!new_state)
3301 return NULL;
e7b07cee 3302
98e6436d
AK		 3303 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3304
3305 new_state->freesync_capable = state->freesync_capable;
3306 new_state->freesync_enable = state->freesync_enable;
c1ee92f9 3307 new_state->abm_level = state->abm_level;
98e6436d
AK		 3308
3309 return &new_state->base;
e7b07cee
HW		 3310}
3311
3312static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3313 .reset = amdgpu_dm_connector_funcs_reset,
3314 .detect = amdgpu_dm_connector_detect,
3315 .fill_modes = drm_helper_probe_single_connector_modes,
3316 .destroy = amdgpu_dm_connector_destroy,
3317 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3318 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3319 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3320 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3321};
3322
e7b07cee
HW		 3323static int get_modes(struct drm_connector *connector)
3324{
3325 return amdgpu_dm_connector_get_modes(connector);
3326}
3327
c84dec2f 3328static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3329{
3330 struct dc_sink_init_data init_params = {
3331 .link = aconnector->dc_link,
3332 .sink_signal = SIGNAL_TYPE_VIRTUAL
3333 };
70e8ffc5 3334 struct edid *edid;
e7b07cee 3335
a89ff457 3336 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 3337 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3338 aconnector->base.name);
3339
3340 aconnector->base.force = DRM_FORCE_OFF;
3341 aconnector->base.override_edid = false;
3342 return;
3343 }
3344
70e8ffc5
HW		 3345 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3346
e7b07cee
HW		 3347 aconnector->edid = edid;
3348
3349 aconnector->dc_em_sink = dc_link_add_remote_sink(
3350 aconnector->dc_link,
3351 (uint8_t *)edid,
3352 (edid->extensions + 1) * EDID_LENGTH,
3353 &init_params);
3354
a68d90e7 3355 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 3356 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3357 aconnector->dc_link->local_sink :
3358 aconnector->dc_em_sink;
3359}
3360
c84dec2f 3361static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3362{
3363 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3364
1f6010a9
DF		 3365 /*
3366 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 3367 * Those settings have to be != 0 to get initial modeset
3368 */
3369 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3370 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3371 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3372 }
3373
3374
3375 aconnector->base.override_edid = true;
3376 create_eml_sink(aconnector);
3377}
3378
ba9ca088 3379enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 3380 struct drm_display_mode *mode)
e7b07cee
HW		 3381{
3382 int result = MODE_ERROR;
3383 struct dc_sink *dc_sink;
3384 struct amdgpu_device *adev = connector->dev->dev_private;
3385 /* TODO: Unhardcode stream count */
0971c40e 3386 struct dc_stream_state *stream;
c84dec2f 3387 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 3388 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 3389
3390 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3391 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3392 return result;
3393
1f6010a9
DF		 3394 /*
3395 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 3396 * EDID mgmt
3397 */
3398 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3399 !aconnector->dc_em_sink)
3400 handle_edid_mgmt(aconnector);
3401
c84dec2f 3402 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 3403
b830ebc9 3404 if (dc_sink == NULL) {
e7b07cee
HW		 3405 DRM_ERROR("dc_sink is NULL!\n");
3406 goto fail;
3407 }
3408
b333730d 3409 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
b830ebc9 3410 if (stream == NULL) {
e7b07cee
HW		 3411 DRM_ERROR("Failed to create stream for sink!\n");
3412 goto fail;
3413 }
3414
a39438f0
HW		 3415 dc_result = dc_validate_stream(adev->dm.dc, stream);
3416
3417 if (dc_result == DC_OK)
e7b07cee 3418 result = MODE_OK;
a39438f0 3419 else
9f921b14 3420 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 3421 mode->vdisplay,
3422 mode->hdisplay,
9f921b14
HW		 3423 mode->clock,
3424 dc_result);
e7b07cee
HW		 3425
3426 dc_stream_release(stream);
3427
3428fail:
3429 /* TODO: error handling*/
3430 return result;
3431}
3432
3433static const struct drm_connector_helper_funcs
3434amdgpu_dm_connector_helper_funcs = {
3435 /*
1f6010a9 3436 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 3437 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 3438 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 3439 * in get_modes call back, not just return the modes count
3440 */
e7b07cee
HW		 3441 .get_modes = get_modes,
3442 .mode_valid = amdgpu_dm_connector_mode_valid,
e7b07cee
HW		 3443};
3444
3445static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3446{
3447}
3448
3ee6b26b
AD		 3449static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3450 struct drm_crtc_state *state)
e7b07cee
HW		 3451{
3452 struct amdgpu_device *adev = crtc->dev->dev_private;
3453 struct dc *dc = adev->dm.dc;
3454 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3455 int ret = -EINVAL;
3456
9b690ef3
BL		 3457 if (unlikely(!dm_crtc_state->stream &&
3458 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 3459 WARN_ON(1);
3460 return ret;
3461 }
3462
1f6010a9 3463 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 3464 if (!dm_crtc_state->stream)
3465 return 0;
3466
62c933f9 3467 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 3468 return 0;
3469
3470 return ret;
3471}
3472
3ee6b26b
AD		 3473static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3474 const struct drm_display_mode *mode,
3475 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 3476{
3477 return true;
3478}
3479
3480static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3481 .disable = dm_crtc_helper_disable,
3482 .atomic_check = dm_crtc_helper_atomic_check,
3483 .mode_fixup = dm_crtc_helper_mode_fixup
3484};
3485
3486static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3487{
3488
3489}
3490
3ee6b26b
AD		 3491static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3492 struct drm_crtc_state *crtc_state,
3493 struct drm_connector_state *conn_state)
e7b07cee
HW		 3494{
3495 return 0;
3496}
3497
3498const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3499 .disable = dm_encoder_helper_disable,
3500 .atomic_check = dm_encoder_helper_atomic_check
3501};
3502
3503static void dm_drm_plane_reset(struct drm_plane *plane)
3504{
3505 struct dm_plane_state *amdgpu_state = NULL;
3506
3507 if (plane->state)
3508 plane->funcs->atomic_destroy_state(plane, plane->state);
3509
3510 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 3511 WARN_ON(amdgpu_state == NULL);
1f6010a9 3512
e7b07cee
HW		 3513 if (amdgpu_state) {
3514 plane->state = &amdgpu_state->base;
3515 plane->state->plane = plane;
3516 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 3517 }
e7b07cee
HW		 3518}
3519
3520static struct drm_plane_state *
3521dm_drm_plane_duplicate_state(struct drm_plane *plane)
3522{
3523 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3524
3525 old_dm_plane_state = to_dm_plane_state(plane->state);
3526 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3527 if (!dm_plane_state)
3528 return NULL;
3529
3530 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3531
3be5262e
HW		 3532 if (old_dm_plane_state->dc_state) {
3533 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3534 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 3535 }
3536
3537 return &dm_plane_state->base;
3538}
3539
3540void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 3541 struct drm_plane_state *state)
e7b07cee
HW		 3542{
3543 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3544
3be5262e
HW		 3545 if (dm_plane_state->dc_state)
3546 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 3547
0627bbd3 3548 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 3549}
3550
3551static const struct drm_plane_funcs dm_plane_funcs = {
3552 .update_plane = drm_atomic_helper_update_plane,
3553 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 3554 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 3555 .reset = dm_drm_plane_reset,
3556 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3557 .atomic_destroy_state = dm_drm_plane_destroy_state,
3558};
3559
3ee6b26b
AD		 3560static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3561 struct drm_plane_state *new_state)
e7b07cee
HW		 3562{
3563 struct amdgpu_framebuffer *afb;
3564 struct drm_gem_object *obj;
5d43be0c 3565 struct amdgpu_device *adev;
e7b07cee 3566 struct amdgpu_bo *rbo;
56087b31 3567 uint64_t chroma_addr = 0;
e7b07cee
HW		 3568 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3569 unsigned int awidth;
5d43be0c
CK		 3570 uint32_t domain;
3571 int r;
e7b07cee
HW		 3572
3573 dm_plane_state_old = to_dm_plane_state(plane->state);
3574 dm_plane_state_new = to_dm_plane_state(new_state);
3575
3576 if (!new_state->fb) {
f1ad2f5e 3577 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3578 return 0;
3579 }
3580
3581 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 3582 obj = new_state->fb->obj[0];
e7b07cee 3583 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3584 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3585 r = amdgpu_bo_reserve(rbo, false);
3586 if (unlikely(r != 0))
3587 return r;
3588
5d43be0c 3589 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 3590 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 3591 else
3592 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3593
7b7c6c81 3594 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 3595 if (unlikely(r != 0)) {
30b7c614
HW		 3596 if (r != -ERESTARTSYS)
3597 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
bb812f1e 3598 amdgpu_bo_unreserve(rbo);
e7b07cee
HW		 3599 return r;
3600 }
3601
bb812f1e
JZ		 3602 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3603 if (unlikely(r != 0)) {
3604 amdgpu_bo_unpin(rbo);
3605 amdgpu_bo_unreserve(rbo);
3606 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 3607 return r;
3608 }
bb812f1e
JZ		 3609 amdgpu_bo_unreserve(rbo);
3610
7b7c6c81 3611 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 3612
3613 amdgpu_bo_ref(rbo);
3614
3be5262e
HW		 3615 if (dm_plane_state_new->dc_state &&
3616 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3617 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3618
3be5262e
HW		 3619 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3620 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3621 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 3622 } else {
3623 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3624 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3625 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3626 = lower_32_bits(afb->address);
56087b31
S		 3627 plane_state->address.video_progressive.luma_addr.high_part
3628 = upper_32_bits(afb->address);
35888630 3629 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3630 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3631 = lower_32_bits(chroma_addr);
3632 plane_state->address.video_progressive.chroma_addr.high_part
3633 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3634 }
3635 }
3636
e7b07cee
HW		 3637 return 0;
3638}
3639
3ee6b26b
AD		 3640static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3641 struct drm_plane_state *old_state)
e7b07cee
HW		 3642{
3643 struct amdgpu_bo *rbo;
e7b07cee
HW		 3644 int r;
3645
3646 if (!old_state->fb)
3647 return;
3648
e68d14dd 3649 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 3650 r = amdgpu_bo_reserve(rbo, false);
3651 if (unlikely(r)) {
3652 DRM_ERROR("failed to reserve rbo before unpin\n");
3653 return;
b830ebc9
HW		 3654 }
3655
3656 amdgpu_bo_unpin(rbo);
3657 amdgpu_bo_unreserve(rbo);
3658 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3659}
3660
7578ecda
AD		 3661static int dm_plane_atomic_check(struct drm_plane *plane,
3662 struct drm_plane_state *state)
cbd19488
AG		 3663{
3664 struct amdgpu_device *adev = plane->dev->dev_private;
3665 struct dc *dc = adev->dm.dc;
3666 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3667
3be5262e 3668 if (!dm_plane_state->dc_state)
9a3329b1 3669 return 0;
cbd19488 3670
a05bcff1
S		 3671 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3672 return -EINVAL;
3673
62c933f9 3674 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3675 return 0;
3676
3677 return -EINVAL;
3678}
3679
e7b07cee
HW		 3680static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3681 .prepare_fb = dm_plane_helper_prepare_fb,
3682 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3683 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3684};
3685
3686/*
3687 * TODO: these are currently initialized to rgb formats only.
3688 * For future use cases we should either initialize them dynamically based on
3689 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 3690 * check will succeed, and let DC implement proper check
e7b07cee 3691 */
d90371b0 3692static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3693 DRM_FORMAT_RGB888,
3694 DRM_FORMAT_XRGB8888,
3695 DRM_FORMAT_ARGB8888,
3696 DRM_FORMAT_RGBA8888,
3697 DRM_FORMAT_XRGB2101010,
3698 DRM_FORMAT_XBGR2101010,
3699 DRM_FORMAT_ARGB2101010,
3700 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 3701 DRM_FORMAT_XBGR8888,
3702 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 3703};
3704
99d1abf8 3705static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3706 DRM_FORMAT_NV12,
3707 DRM_FORMAT_NV21,
3708};
3709
3710static const u32 cursor_formats[] = {
3711 DRM_FORMAT_ARGB8888
3712};
3713
7578ecda 3714static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 3715 struct drm_plane *plane,
7578ecda 3716 unsigned long possible_crtcs)
e7b07cee
HW		 3717{
3718 int res = -EPERM;
3719
f180b4bc 3720 switch (plane->type) {
e7b07cee 3721 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3722 res = drm_universal_plane_init(
3723 dm->adev->ddev,
f180b4bc 3724 plane,
e7b07cee
HW		 3725 possible_crtcs,
3726 &dm_plane_funcs,
3727 rgb_formats,
3728 ARRAY_SIZE(rgb_formats),
f180b4bc 3729 NULL, plane->type, NULL);
e7b07cee
HW		 3730 break;
3731 case DRM_PLANE_TYPE_OVERLAY:
3732 res = drm_universal_plane_init(
3733 dm->adev->ddev,
f180b4bc 3734 plane,
e7b07cee
HW		 3735 possible_crtcs,
3736 &dm_plane_funcs,
3737 yuv_formats,
3738 ARRAY_SIZE(yuv_formats),
f180b4bc 3739 NULL, plane->type, NULL);
e7b07cee
HW		 3740 break;
3741 case DRM_PLANE_TYPE_CURSOR:
3742 res = drm_universal_plane_init(
3743 dm->adev->ddev,
f180b4bc 3744 plane,
e7b07cee
HW		 3745 possible_crtcs,
3746 &dm_plane_funcs,
3747 cursor_formats,
3748 ARRAY_SIZE(cursor_formats),
f180b4bc 3749 NULL, plane->type, NULL);
e7b07cee
HW		 3750 break;
3751 }
3752
f180b4bc 3753 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 3754
96719c54 3755 /* Create (reset) the plane state */
f180b4bc
HW		 3756 if (plane->funcs->reset)
3757 plane->funcs->reset(plane);
96719c54
HW		 3758
3759
e7b07cee
HW		 3760 return res;
3761}
3762
7578ecda
AD		 3763static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3764 struct drm_plane *plane,
3765 uint32_t crtc_index)
e7b07cee
HW		 3766{
3767 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 3768 struct drm_plane *cursor_plane;
e7b07cee
HW		 3769
3770 int res = -ENOMEM;
3771
3772 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3773 if (!cursor_plane)
3774 goto fail;
3775
f180b4bc 3776 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
e7b07cee
HW		 3777 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3778
3779 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3780 if (!acrtc)
3781 goto fail;
3782
3783 res = drm_crtc_init_with_planes(
3784 dm->ddev,
3785 &acrtc->base,
3786 plane,
f180b4bc 3787 cursor_plane,
e7b07cee
HW		 3788 &amdgpu_dm_crtc_funcs, NULL);
3789
3790 if (res)
3791 goto fail;
3792
3793 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3794
96719c54
HW		 3795 /* Create (reset) the plane state */
3796 if (acrtc->base.funcs->reset)
3797 acrtc->base.funcs->reset(&acrtc->base);
3798
e7b07cee
HW		 3799 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3800 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3801
3802 acrtc->crtc_id = crtc_index;
3803 acrtc->base.enabled = false;
c37e2d29 3804 acrtc->otg_inst = -1;
e7b07cee
HW		 3805
3806 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3807 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3808 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3809 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3810
3811 return 0;
3812
3813fail:
b830ebc9
HW		 3814 kfree(acrtc);
3815 kfree(cursor_plane);
e7b07cee
HW		 3816 return res;
3817}
3818
3819
3820static int to_drm_connector_type(enum signal_type st)
3821{
3822 switch (st) {
3823 case SIGNAL_TYPE_HDMI_TYPE_A:
3824 return DRM_MODE_CONNECTOR_HDMIA;
3825 case SIGNAL_TYPE_EDP:
3826 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 3827 case SIGNAL_TYPE_LVDS:
3828 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 3829 case SIGNAL_TYPE_RGB:
3830 return DRM_MODE_CONNECTOR_VGA;
3831 case SIGNAL_TYPE_DISPLAY_PORT:
3832 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3833 return DRM_MODE_CONNECTOR_DisplayPort;
3834 case SIGNAL_TYPE_DVI_DUAL_LINK:
3835 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3836 return DRM_MODE_CONNECTOR_DVID;
3837 case SIGNAL_TYPE_VIRTUAL:
3838 return DRM_MODE_CONNECTOR_VIRTUAL;
3839
3840 default:
3841 return DRM_MODE_CONNECTOR_Unknown;
3842 }
3843}
3844
2b4c1c05
DV		 3845static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
3846{
3847 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
3848}
3849
e7b07cee
HW		 3850static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3851{
e7b07cee
HW		 3852 struct drm_encoder *encoder;
3853 struct amdgpu_encoder *amdgpu_encoder;
3854
2b4c1c05 3855 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 3856
3857 if (encoder == NULL)
3858 return;
3859
3860 amdgpu_encoder = to_amdgpu_encoder(encoder);
3861
3862 amdgpu_encoder->native_mode.clock = 0;
3863
3864 if (!list_empty(&connector->probed_modes)) {
3865 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3866
e7b07cee 3867 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3868 &connector->probed_modes,
3869 head) {
3870 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3871 amdgpu_encoder->native_mode = *preferred_mode;
3872
e7b07cee
HW		 3873 break;
3874 }
3875
3876 }
3877}
3878
3ee6b26b
AD		 3879static struct drm_display_mode *
3880amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3881 char *name,
3882 int hdisplay, int vdisplay)
e7b07cee
HW		 3883{
3884 struct drm_device *dev = encoder->dev;
3885 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3886 struct drm_display_mode *mode = NULL;
3887 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3888
3889 mode = drm_mode_duplicate(dev, native_mode);
3890
b830ebc9 3891 if (mode == NULL)
e7b07cee
HW		 3892 return NULL;
3893
3894 mode->hdisplay = hdisplay;
3895 mode->vdisplay = vdisplay;
3896 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3897 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3898
3899 return mode;
3900
3901}
3902
3903static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3904 struct drm_connector *connector)
e7b07cee
HW		 3905{
3906 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3907 struct drm_display_mode *mode = NULL;
3908 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3909 struct amdgpu_dm_connector *amdgpu_dm_connector =
3910 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3911 int i;
3912 int n;
3913 struct mode_size {
3914 char name[DRM_DISPLAY_MODE_LEN];
3915 int w;
3916 int h;
b830ebc9 3917 } common_modes[] = {
e7b07cee
HW		 3918 { "640x480", 640, 480},
3919 { "800x600", 800, 600},
3920 { "1024x768", 1024, 768},
3921 { "1280x720", 1280, 720},
3922 { "1280x800", 1280, 800},
3923 {"1280x1024", 1280, 1024},
3924 { "1440x900", 1440, 900},
3925 {"1680x1050", 1680, 1050},
3926 {"1600x1200", 1600, 1200},
3927 {"1920x1080", 1920, 1080},
3928 {"1920x1200", 1920, 1200}
3929 };
3930
b830ebc9 3931 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3932
3933 for (i = 0; i < n; i++) {
3934 struct drm_display_mode *curmode = NULL;
3935 bool mode_existed = false;
3936
3937 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3938 common_modes[i].h > native_mode->vdisplay ||
3939 (common_modes[i].w == native_mode->hdisplay &&
3940 common_modes[i].h == native_mode->vdisplay))
3941 continue;
e7b07cee
HW		 3942
3943 list_for_each_entry(curmode, &connector->probed_modes, head) {
3944 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3945 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3946 mode_existed = true;
3947 break;
3948 }
3949 }
3950
3951 if (mode_existed)
3952 continue;
3953
3954 mode = amdgpu_dm_create_common_mode(encoder,
3955 common_modes[i].name, common_modes[i].w,
3956 common_modes[i].h);
3957 drm_mode_probed_add(connector, mode);
c84dec2f 3958 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3959 }
3960}
3961
3ee6b26b
AD		 3962static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3963 struct edid *edid)
e7b07cee 3964{
c84dec2f
HW		 3965 struct amdgpu_dm_connector *amdgpu_dm_connector =
3966 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3967
3968 if (edid) {
3969 /* empty probed_modes */
3970 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3971 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3972 drm_add_edid_modes(connector, edid);
3973
e7b07cee 3974 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3975 } else {
c84dec2f 3976 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3977 }
e7b07cee
HW		 3978}
3979
7578ecda 3980static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 3981{
c84dec2f
HW		 3982 struct amdgpu_dm_connector *amdgpu_dm_connector =
3983 to_amdgpu_dm_connector(connector);
e7b07cee 3984 struct drm_encoder *encoder;
c84dec2f 3985 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 3986
2b4c1c05 3987 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 3988
85ee15d6 3989 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 3990 amdgpu_dm_connector->num_modes =
3991 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 3992 } else {
3993 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3994 amdgpu_dm_connector_add_common_modes(encoder, connector);
3995 }
3e332d3a 3996 amdgpu_dm_fbc_init(connector);
5099114b 3997
c84dec2f 3998 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3999}
4000
3ee6b26b
AD		 4001void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4002 struct amdgpu_dm_connector *aconnector,
4003 int connector_type,
4004 struct dc_link *link,
4005 int link_index)
e7b07cee
HW		 4006{
4007 struct amdgpu_device *adev = dm->ddev->dev_private;
4008
4009 aconnector->connector_id = link_index;
4010 aconnector->dc_link = link;
4011 aconnector->base.interlace_allowed = false;
4012 aconnector->base.doublescan_allowed = false;
4013 aconnector->base.stereo_allowed = false;
4014 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4015 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
e7b07cee
HW		 4016 mutex_init(&aconnector->hpd_lock);
4017
1f6010a9
DF		 4018 /*
4019 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 4020 * which means HPD hot plug not supported
4021 */
e7b07cee
HW		 4022 switch (connector_type) {
4023 case DRM_MODE_CONNECTOR_HDMIA:
4024 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4025 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4026 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 4027 break;
4028 case DRM_MODE_CONNECTOR_DisplayPort:
4029 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4030 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4031 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 4032 break;
4033 case DRM_MODE_CONNECTOR_DVID:
4034 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4035 break;
4036 default:
4037 break;
4038 }
4039
4040 drm_object_attach_property(&aconnector->base.base,
4041 dm->ddev->mode_config.scaling_mode_property,
4042 DRM_MODE_SCALE_NONE);
4043
4044 drm_object_attach_property(&aconnector->base.base,
4045 adev->mode_info.underscan_property,
4046 UNDERSCAN_OFF);
4047 drm_object_attach_property(&aconnector->base.base,
4048 adev->mode_info.underscan_hborder_property,
4049 0);
4050 drm_object_attach_property(&aconnector->base.base,
4051 adev->mode_info.underscan_vborder_property,
4052 0);
cedde71c
NK		 4053 drm_object_attach_property(&aconnector->base.base,
4054 adev->mode_info.max_bpc_property,
4055 0);
e7b07cee 4056
c1ee92f9
DF		 4057 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4058 dc_is_dmcu_initialized(adev->dm.dc)) {
4059 drm_object_attach_property(&aconnector->base.base,
4060 adev->mode_info.abm_level_property, 0);
4061 }
e7b07cee
HW		 4062}
4063
7578ecda
AD		 4064static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4065 struct i2c_msg *msgs, int num)
e7b07cee
HW		 4066{
4067 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4068 struct ddc_service *ddc_service = i2c->ddc_service;
4069 struct i2c_command cmd;
4070 int i;
4071 int result = -EIO;
4072
b830ebc9 4073 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 4074
4075 if (!cmd.payloads)
4076 return result;
4077
4078 cmd.number_of_payloads = num;
4079 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4080 cmd.speed = 100;
4081
4082 for (i = 0; i < num; i++) {
4083 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4084 cmd.payloads[i].address = msgs[i].addr;
4085 cmd.payloads[i].length = msgs[i].len;
4086 cmd.payloads[i].data = msgs[i].buf;
4087 }
4088
c85e6e54
DF		 4089 if (dc_submit_i2c(
4090 ddc_service->ctx->dc,
4091 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 4092 &cmd))
4093 result = num;
4094
4095 kfree(cmd.payloads);
4096 return result;
4097}
4098
7578ecda 4099static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 4100{
4101 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4102}
4103
4104static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4105 .master_xfer = amdgpu_dm_i2c_xfer,
4106 .functionality = amdgpu_dm_i2c_func,
4107};
4108
3ee6b26b
AD		 4109static struct amdgpu_i2c_adapter *
4110create_i2c(struct ddc_service *ddc_service,
4111 int link_index,
4112 int *res)
e7b07cee
HW		 4113{
4114 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4115 struct amdgpu_i2c_adapter *i2c;
4116
b830ebc9 4117 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 4118 if (!i2c)
4119 return NULL;
e7b07cee
HW		 4120 i2c->base.owner = THIS_MODULE;
4121 i2c->base.class = I2C_CLASS_DDC;
4122 i2c->base.dev.parent = &adev->pdev->dev;
4123 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 4124 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 4125 i2c_set_adapdata(&i2c->base, i2c);
4126 i2c->ddc_service = ddc_service;
c85e6e54 4127 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 4128
4129 return i2c;
4130}
4131
89fc8d4e 4132
1f6010a9
DF		 4133/*
4134 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 4135 * dc_link which will be represented by this aconnector.
4136 */
7578ecda
AD		 4137static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4138 struct amdgpu_dm_connector *aconnector,
4139 uint32_t link_index,
4140 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 4141{
4142 int res = 0;
4143 int connector_type;
4144 struct dc *dc = dm->dc;
4145 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4146 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 4147
4148 link->priv = aconnector;
e7b07cee 4149
f1ad2f5e 4150 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 4151
4152 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 4153 if (!i2c) {
4154 DRM_ERROR("Failed to create i2c adapter data\n");
4155 return -ENOMEM;
4156 }
4157
e7b07cee
HW		 4158 aconnector->i2c = i2c;
4159 res = i2c_add_adapter(&i2c->base);
4160
4161 if (res) {
4162 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4163 goto out_free;
4164 }
4165
4166 connector_type = to_drm_connector_type(link->connector_signal);
4167
4168 res = drm_connector_init(
4169 dm->ddev,
4170 &aconnector->base,
4171 &amdgpu_dm_connector_funcs,
4172 connector_type);
4173
4174 if (res) {
4175 DRM_ERROR("connector_init failed\n");
4176 aconnector->connector_id = -1;
4177 goto out_free;
4178 }
4179
4180 drm_connector_helper_add(
4181 &aconnector->base,
4182 &amdgpu_dm_connector_helper_funcs);
4183
96719c54
HW		 4184 if (aconnector->base.funcs->reset)
4185 aconnector->base.funcs->reset(&aconnector->base);
4186
e7b07cee
HW		 4187 amdgpu_dm_connector_init_helper(
4188 dm,
4189 aconnector,
4190 connector_type,
4191 link,
4192 link_index);
4193
cde4c44d 4194 drm_connector_attach_encoder(
e7b07cee
HW		 4195 &aconnector->base, &aencoder->base);
4196
4197 drm_connector_register(&aconnector->base);
dc38fd9d
DF		 4198#if defined(CONFIG_DEBUG_FS)
4199 res = connector_debugfs_init(aconnector);
4200 if (res) {
4201 DRM_ERROR("Failed to create debugfs for connector");
4202 goto out_free;
4203 }
4204#endif
e7b07cee
HW		 4205
4206 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4207 || connector_type == DRM_MODE_CONNECTOR_eDP)
4208 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4209
e7b07cee
HW		 4210out_free:
4211 if (res) {
4212 kfree(i2c);
4213 aconnector->i2c = NULL;
4214 }
4215 return res;
4216}
4217
4218int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4219{
4220 switch (adev->mode_info.num_crtc) {
4221 case 1:
4222 return 0x1;
4223 case 2:
4224 return 0x3;
4225 case 3:
4226 return 0x7;
4227 case 4:
4228 return 0xf;
4229 case 5:
4230 return 0x1f;
4231 case 6:
4232 default:
4233 return 0x3f;
4234 }
4235}
4236
7578ecda
AD		 4237static int amdgpu_dm_encoder_init(struct drm_device *dev,
4238 struct amdgpu_encoder *aencoder,
4239 uint32_t link_index)
e7b07cee
HW		 4240{
4241 struct amdgpu_device *adev = dev->dev_private;
4242
4243 int res = drm_encoder_init(dev,
4244 &aencoder->base,
4245 &amdgpu_dm_encoder_funcs,
4246 DRM_MODE_ENCODER_TMDS,
4247 NULL);
4248
4249 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4250
4251 if (!res)
4252 aencoder->encoder_id = link_index;
4253 else
4254 aencoder->encoder_id = -1;
4255
4256 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4257
4258 return res;
4259}
4260
3ee6b26b
AD		 4261static void manage_dm_interrupts(struct amdgpu_device *adev,
4262 struct amdgpu_crtc *acrtc,
4263 bool enable)
e7b07cee
HW		 4264{
4265 /*
4266 * this is not correct translation but will work as soon as VBLANK
4267 * constant is the same as PFLIP
4268 */
4269 int irq_type =
734dd01d 4270 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 4271 adev,
4272 acrtc->crtc_id);
4273
4274 if (enable) {
4275 drm_crtc_vblank_on(&acrtc->base);
4276 amdgpu_irq_get(
4277 adev,
4278 &adev->pageflip_irq,
4279 irq_type);
4280 } else {
4281
4282 amdgpu_irq_put(
4283 adev,
4284 &adev->pageflip_irq,
4285 irq_type);
4286 drm_crtc_vblank_off(&acrtc->base);
4287 }
4288}
4289
3ee6b26b
AD		 4290static bool
4291is_scaling_state_different(const struct dm_connector_state *dm_state,
4292 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 4293{
4294 if (dm_state->scaling != old_dm_state->scaling)
4295 return true;
4296 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4297 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4298 return true;
4299 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4300 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4301 return true;
b830ebc9
HW		 4302 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4303 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4304 return true;
e7b07cee
HW		 4305 return false;
4306}
4307
3ee6b26b
AD		 4308static void remove_stream(struct amdgpu_device *adev,
4309 struct amdgpu_crtc *acrtc,
4310 struct dc_stream_state *stream)
e7b07cee
HW		 4311{
4312 /* this is the update mode case */
e7b07cee
HW		 4313
4314 acrtc->otg_inst = -1;
4315 acrtc->enabled = false;
4316}
4317
7578ecda
AD		 4318static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4319 struct dc_cursor_position *position)
2a8f6ccb 4320{
f4c2cc43 4321 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 4322 int x, y;
4323 int xorigin = 0, yorigin = 0;
4324
4325 if (!crtc || !plane->state->fb) {
4326 position->enable = false;
4327 position->x = 0;
4328 position->y = 0;
4329 return 0;
4330 }
4331
4332 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4333 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4334 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4335 __func__,
4336 plane->state->crtc_w,
4337 plane->state->crtc_h);
4338 return -EINVAL;
4339 }
4340
4341 x = plane->state->crtc_x;
4342 y = plane->state->crtc_y;
4343 /* avivo cursor are offset into the total surface */
4344 x += crtc->primary->state->src_x >> 16;
4345 y += crtc->primary->state->src_y >> 16;
4346 if (x < 0) {
4347 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4348 x = 0;
4349 }
4350 if (y < 0) {
4351 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4352 y = 0;
4353 }
4354 position->enable = true;
4355 position->x = x;
4356 position->y = y;
4357 position->x_hotspot = xorigin;
4358 position->y_hotspot = yorigin;
4359
4360 return 0;
4361}
4362
3ee6b26b
AD		 4363static void handle_cursor_update(struct drm_plane *plane,
4364 struct drm_plane_state *old_plane_state)
e7b07cee 4365{
2a8f6ccb
HW		 4366 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4367 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4368 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4369 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4370 uint64_t address = afb ? afb->address : 0;
4371 struct dc_cursor_position position;
4372 struct dc_cursor_attributes attributes;
4373 int ret;
4374
e7b07cee
HW		 4375 if (!plane->state->fb && !old_plane_state->fb)
4376 return;
4377
f1ad2f5e 4378 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 4379 __func__,
4380 amdgpu_crtc->crtc_id,
4381 plane->state->crtc_w,
4382 plane->state->crtc_h);
2a8f6ccb
HW		 4383
4384 ret = get_cursor_position(plane, crtc, &position);
4385 if (ret)
4386 return;
4387
4388 if (!position.enable) {
4389 /* turn off cursor */
4390 if (crtc_state && crtc_state->stream)
4391 dc_stream_set_cursor_position(crtc_state->stream,
4392 &position);
4393 return;
e7b07cee 4394 }
e7b07cee 4395
2a8f6ccb
HW		 4396 amdgpu_crtc->cursor_width = plane->state->crtc_w;
4397 amdgpu_crtc->cursor_height = plane->state->crtc_h;
4398
4399 attributes.address.high_part = upper_32_bits(address);
4400 attributes.address.low_part = lower_32_bits(address);
4401 attributes.width = plane->state->crtc_w;
4402 attributes.height = plane->state->crtc_h;
4403 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4404 attributes.rotation_angle = 0;
4405 attributes.attribute_flags.value = 0;
4406
4407 attributes.pitch = attributes.width;
4408
886daac9
JZ		 4409 if (crtc_state->stream) {
4410 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4411 &attributes))
4412 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 4413
2a8f6ccb
HW		 4414 if (!dc_stream_set_cursor_position(crtc_state->stream,
4415 &position))
4416 DRM_ERROR("DC failed to set cursor position\n");
886daac9 4417 }
2a8f6ccb 4418}
e7b07cee
HW		 4419
4420static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4421{
4422
4423 assert_spin_locked(&acrtc->base.dev->event_lock);
4424 WARN_ON(acrtc->event);
4425
4426 acrtc->event = acrtc->base.state->event;
4427
4428 /* Set the flip status */
4429 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4430
4431 /* Mark this event as consumed */
4432 acrtc->base.state->event = NULL;
4433
4434 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4435 acrtc->crtc_id);
4436}
4437
eb3dc897
NK		 4438struct dc_stream_status *dc_state_get_stream_status(
4439 struct dc_state *state,
4440 struct dc_stream_state *stream)
4441{
4442 uint8_t i;
4443
4444 for (i = 0; i < state->stream_count; i++) {
4445 if (stream == state->streams[i])
4446 return &state->stream_status[i];
4447 }
4448
4449 return NULL;
4450}
4451
e7b07cee
HW		 4452/*
4453 * Executes flip
4454 *
4455 * Waits on all BO's fences and for proper vblank count
4456 */
3ee6b26b
AD		 4457static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
4458 struct drm_framebuffer *fb,
bc6828e0
BL		 4459 uint32_t target,
4460 struct dc_state *state)
e7b07cee
HW		 4461{
4462 unsigned long flags;
4463 uint32_t target_vblank;
4464 int r, vpos, hpos;
4465 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4466 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
e68d14dd 4467 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
e7b07cee 4468 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 4469 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 4470 struct dc_flip_addrs addr = { {0} };
3be5262e 4471 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 4472 struct dc_surface_update surface_updates[1] = { {0} };
4473 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
d999853e 4474 struct dc_stream_status *stream_status;
e7b07cee
HW		 4475
4476
4477 /* Prepare wait for target vblank early - before the fence-waits */
23effc11 4478 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
e7b07cee
HW		 4479 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
4480
1f6010a9
DF		 4481 /*
4482 * TODO This might fail and hence better not used, wait
e7b07cee
HW		 4483 * explicitly on fences instead
4484 * and in general should be called for
4485 * blocking commit to as per framework helpers
b830ebc9 4486 */
e7b07cee
HW		 4487 r = amdgpu_bo_reserve(abo, true);
4488 if (unlikely(r != 0)) {
4489 DRM_ERROR("failed to reserve buffer before flip\n");
4490 WARN_ON(1);
4491 }
4492
4493 /* Wait for all fences on this FB */
4494 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
4495 MAX_SCHEDULE_TIMEOUT) < 0);
4496
4497 amdgpu_bo_unreserve(abo);
4498
1f6010a9
DF		 4499 /*
4500 * Wait until we're out of the vertical blank period before the one
e7b07cee
HW		 4501 * targeted by the flip
4502 */
4503 while ((acrtc->enabled &&
aa8e286a
SL		 4504 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
4505 0, &vpos, &hpos, NULL,
4506 NULL, &crtc->hwmode)
e7b07cee
HW		 4507 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4508 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4509 (int)(target_vblank -
4510 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
4511 usleep_range(1000, 1100);
4512 }
4513
4514 /* Flip */
4515 spin_lock_irqsave(&crtc->dev->event_lock, flags);
e7b07cee
HW		 4516
4517 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
4518 WARN_ON(!acrtc_state->stream);
4519
4520 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
4521 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
4522 addr.flip_immediate = async_flip;
4523
4524
4525 if (acrtc->base.state->event)
4526 prepare_flip_isr(acrtc);
4527
4de9f38b
S		 4528 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4529
d999853e
NK		 4530 stream_status = dc_stream_get_status(acrtc_state->stream);
4531 if (!stream_status) {
4532 DRM_ERROR("No stream status for CRTC: id=%d\n",
4533 acrtc->crtc_id);
4534 return;
4535 }
4536
4537 surface_updates->surface = stream_status->plane_states[0];
4538 if (!surface_updates->surface) {
4539 DRM_ERROR("No surface for CRTC: id=%d\n",
4540 acrtc->crtc_id);
4541 return;
4542 }
e7b07cee
HW		 4543 surface_updates->flip_addr = &addr;
4544
bc6828e0
BL		 4545 dc_commit_updates_for_stream(adev->dm.dc,
4546 surface_updates,
4547 1,
4548 acrtc_state->stream,
4549 NULL,
4550 &surface_updates->surface,
4551 state);
e7b07cee
HW		 4552
4553 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
4554 __func__,
4555 addr.address.grph.addr.high_part,
4556 addr.address.grph.addr.low_part);
e7b07cee
HW		 4557}
4558
44d09c6a
HW		 4559/*
4560 * TODO this whole function needs to go
4561 *
4562 * dc_surface_update is needlessly complex. See if we can just replace this
4563 * with a dc_plane_state and follow the atomic model a bit more closely here.
4564 */
4565static bool commit_planes_to_stream(
4566 struct dc *dc,
4567 struct dc_plane_state **plane_states,
4568 uint8_t new_plane_count,
4569 struct dm_crtc_state *dm_new_crtc_state,
4570 struct dm_crtc_state *dm_old_crtc_state,
4571 struct dc_state *state)
4572{
4573 /* no need to dynamically allocate this. it's pretty small */
4574 struct dc_surface_update updates[MAX_SURFACES];
4575 struct dc_flip_addrs *flip_addr;
4576 struct dc_plane_info *plane_info;
4577 struct dc_scaling_info *scaling_info;
4578 int i;
4579 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
4580 struct dc_stream_update *stream_update =
4581 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
c1ee92f9 4582 unsigned int abm_level;
44d09c6a
HW		 4583
4584 if (!stream_update) {
4585 BREAK_TO_DEBUGGER();
4586 return false;
4587 }
4588
4589 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
4590 GFP_KERNEL);
4591 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
4592 GFP_KERNEL);
4593 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
4594 GFP_KERNEL);
4595
4596 if (!flip_addr || !plane_info || !scaling_info) {
4597 kfree(flip_addr);
4598 kfree(plane_info);
4599 kfree(scaling_info);
4600 kfree(stream_update);
4601 return false;
4602 }
4603
4604 memset(updates, 0, sizeof(updates));
4605
4606 stream_update->src = dc_stream->src;
4607 stream_update->dst = dc_stream->dst;
4608 stream_update->out_transfer_func = dc_stream->out_transfer_func;
4609
98e6436d
AK		 4610 if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) {
4611 stream_update->vrr_infopacket = &dc_stream->vrr_infopacket;
4612 stream_update->adjust = &dc_stream->adjust;
4613 }
4614
c1ee92f9
DF		 4615 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
4616 abm_level = dm_new_crtc_state->abm_level;
4617 stream_update->abm_level = &abm_level;
4618 }
4619
44d09c6a
HW		 4620 for (i = 0; i < new_plane_count; i++) {
4621 updates[i].surface = plane_states[i];
4622 updates[i].gamma =
4623 (struct dc_gamma *)plane_states[i]->gamma_correction;
4624 updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4625 flip_addr[i].address = plane_states[i]->address;
4626 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4627 plane_info[i].color_space = plane_states[i]->color_space;
44d09c6a
HW		 4628 plane_info[i].format = plane_states[i]->format;
4629 plane_info[i].plane_size = plane_states[i]->plane_size;
4630 plane_info[i].rotation = plane_states[i]->rotation;
4631 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4632 plane_info[i].stereo_format = plane_states[i]->stereo_format;
4633 plane_info[i].tiling_info = plane_states[i]->tiling_info;
4634 plane_info[i].visible = plane_states[i]->visible;
4635 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4636 plane_info[i].dcc = plane_states[i]->dcc;
4637 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4638 scaling_info[i].src_rect = plane_states[i]->src_rect;
4639 scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4640 scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4641
4642 updates[i].flip_addr = &flip_addr[i];
4643 updates[i].plane_info = &plane_info[i];
4644 updates[i].scaling_info = &scaling_info[i];
4645 }
4646
4647 dc_commit_updates_for_stream(
4648 dc,
4649 updates,
4650 new_plane_count,
4651 dc_stream, stream_update, plane_states, state);
4652
4653 kfree(flip_addr);
4654 kfree(plane_info);
4655 kfree(scaling_info);
4656 kfree(stream_update);
4657 return true;
4658}
4659
3be5262e 4660static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 4661 struct dc_state *dc_state,
3ee6b26b
AD		 4662 struct drm_device *dev,
4663 struct amdgpu_display_manager *dm,
4664 struct drm_crtc *pcrtc,
4665 bool *wait_for_vblank)
e7b07cee
HW		 4666{
4667 uint32_t i;
4668 struct drm_plane *plane;
0bc9706d 4669 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 4670 struct dc_stream_state *dc_stream_attach;
3be5262e 4671 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 4672 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 4673 struct drm_crtc_state *new_pcrtc_state =
4674 drm_atomic_get_new_crtc_state(state, pcrtc);
4675 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 4676 struct dm_crtc_state *dm_old_crtc_state =
4677 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
e7b07cee
HW		 4678 int planes_count = 0;
4679 unsigned long flags;
4680
4681 /* update planes when needed */
0bc9706d
LSL		 4682 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4683 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 4684 struct drm_crtc_state *new_crtc_state;
0bc9706d 4685 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 4686 bool pflip_needed;
54d76575 4687 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 4688
4689 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4690 handle_cursor_update(plane, old_plane_state);
4691 continue;
4692 }
4693
f5ba60fe
DD		 4694 if (!fb || !crtc || pcrtc != crtc)
4695 continue;
4696
4697 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4698 if (!new_crtc_state->active)
e7b07cee
HW		 4699 continue;
4700
4701 pflip_needed = !state->allow_modeset;
4702
4703 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4704 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 4705 DRM_ERROR("%s: acrtc %d, already busy\n",
4706 __func__,
4707 acrtc_attach->crtc_id);
b830ebc9 4708 /* In commit tail framework this cannot happen */
e7b07cee
HW		 4709 WARN_ON(1);
4710 }
4711 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4712
a2a330ad 4713 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
54d76575 4714 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 4715
54d76575 4716 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 4717
4718 dc_stream_attach = acrtc_state->stream;
4719 planes_count++;
4720
0bc9706d 4721 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 4722 /* Assume even ONE crtc with immediate flip means
4723 * entire can't wait for VBLANK
4724 * TODO Check if it's correct
4725 */
4726 *wait_for_vblank =
0bc9706d 4727 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 4728 false : true;
4729
4730 /* TODO: Needs rework for multiplane flip */
4731 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4732 drm_crtc_vblank_get(crtc);
4733
4734 amdgpu_dm_do_flip(
4735 crtc,
4736 fb,
23effc11 4737 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
eb3dc897 4738 dc_state);
e7b07cee
HW		 4739 }
4740
4741 }
4742
4743 if (planes_count) {
4744 unsigned long flags;
4745
0bc9706d 4746 if (new_pcrtc_state->event) {
e7b07cee
HW		 4747
4748 drm_crtc_vblank_get(pcrtc);
4749
4750 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4751 prepare_flip_isr(acrtc_attach);
4752 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4753 }
4754
98e6436d
AK		 4755 dc_stream_attach->adjust = acrtc_state->adjust;
4756 dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket;
c1ee92f9 4757 dc_stream_attach->abm_level = acrtc_state->abm_level;
44d09c6a
HW		 4758
4759 if (false == commit_planes_to_stream(dm->dc,
3be5262e
HW		 4760 plane_states_constructed,
4761 planes_count,
44d09c6a
HW		 4762 acrtc_state,
4763 dm_old_crtc_state,
eb3dc897 4764 dc_state))
3be5262e 4765 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4766 } else {
4767 /*TODO BUG Here should go disable planes on CRTC. */
4768 }
4769}
4770
1f6010a9 4771/*
27b3f4fc
LSL		 4772 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4773 * @crtc_state: the DRM CRTC state
4774 * @stream_state: the DC stream state.
4775 *
4776 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4777 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4778 */
4779static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4780 struct dc_stream_state *stream_state)
4781{
4782 stream_state->mode_changed = crtc_state->mode_changed;
4783}
e7b07cee 4784
7578ecda
AD		 4785static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4786 struct drm_atomic_state *state,
4787 bool nonblock)
e7b07cee
HW		 4788{
4789 struct drm_crtc *crtc;
c2cea706 4790 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4791 struct amdgpu_device *adev = dev->dev_private;
4792 int i;
4793
4794 /*
4795 * We evade vblanks and pflips on crtc that
4796 * should be changed. We do it here to flush & disable
4797 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4798 * it will update crtc->dm_crtc_state->stream pointer which is used in
4799 * the ISRs.
4800 */
c2cea706 4801 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4802 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 4803 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4804
54d76575 4805 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 4806 manage_dm_interrupts(adev, acrtc, false);
4807 }
1f6010a9
DF		 4808 /*
4809 * Add check here for SoC's that support hardware cursor plane, to
4810 * unset legacy_cursor_update
4811 */
e7b07cee
HW		 4812
4813 return drm_atomic_helper_commit(dev, state, nonblock);
4814
4815 /*TODO Handle EINTR, reenable IRQ*/
4816}
4817
b8592b48
LL		 4818/**
4819 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
4820 * @state: The atomic state to commit
4821 *
4822 * This will tell DC to commit the constructed DC state from atomic_check,
4823 * programming the hardware. Any failures here implies a hardware failure, since
4824 * atomic check should have filtered anything non-kosher.
4825 */
7578ecda 4826static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4827{
4828 struct drm_device *dev = state->dev;
4829 struct amdgpu_device *adev = dev->dev_private;
4830 struct amdgpu_display_manager *dm = &adev->dm;
4831 struct dm_atomic_state *dm_state;
eb3dc897 4832 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 4833 uint32_t i, j;
5cc6dcbd 4834 struct drm_crtc *crtc;
0bc9706d 4835 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4836 unsigned long flags;
4837 bool wait_for_vblank = true;
4838 struct drm_connector *connector;
c2cea706 4839 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4840 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 4841 int crtc_disable_count = 0;
e7b07cee
HW		 4842
4843 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4844
eb3dc897
NK		 4845 dm_state = dm_atomic_get_new_state(state);
4846 if (dm_state && dm_state->context) {
4847 dc_state = dm_state->context;
4848 } else {
4849 /* No state changes, retain current state. */
4850 dc_state_temp = dc_create_state();
4851 ASSERT(dc_state_temp);
4852 dc_state = dc_state_temp;
4853 dc_resource_state_copy_construct_current(dm->dc, dc_state);
4854 }
e7b07cee
HW		 4855
4856 /* update changed items */
0bc9706d 4857 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4858 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4859
54d76575
LSL		 4860 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4861 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4862
f1ad2f5e 4863 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4864 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4865 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4866 "connectors_changed:%d\n",
4867 acrtc->crtc_id,
0bc9706d
LSL		 4868 new_crtc_state->enable,
4869 new_crtc_state->active,
4870 new_crtc_state->planes_changed,
4871 new_crtc_state->mode_changed,
4872 new_crtc_state->active_changed,
4873 new_crtc_state->connectors_changed);
e7b07cee 4874
27b3f4fc
LSL		 4875 /* Copy all transient state flags into dc state */
4876 if (dm_new_crtc_state->stream) {
4877 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4878 dm_new_crtc_state->stream);
4879 }
4880
e7b07cee
HW		 4881 /* handles headless hotplug case, updating new_state and
4882 * aconnector as needed
4883 */
4884
54d76575 4885 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4886
f1ad2f5e 4887 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4888
54d76575 4889 if (!dm_new_crtc_state->stream) {
e7b07cee 4890 /*
b830ebc9
HW		 4891 * this could happen because of issues with
4892 * userspace notifications delivery.
4893 * In this case userspace tries to set mode on
1f6010a9
DF		 4894 * display which is disconnected in fact.
4895 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 4896 * We expect reset mode will come soon.
4897 *
4898 * This can also happen when unplug is done
4899 * during resume sequence ended
4900 *
4901 * In this case, we want to pretend we still
4902 * have a sink to keep the pipe running so that
4903 * hw state is consistent with the sw state
4904 */
f1ad2f5e 4905 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4906 __func__, acrtc->base.base.id);
4907 continue;
4908 }
4909
54d76575
LSL		 4910 if (dm_old_crtc_state->stream)
4911 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 4912
97028037
LP		 4913 pm_runtime_get_noresume(dev->dev);
4914
e7b07cee 4915 acrtc->enabled = true;
0bc9706d
LSL		 4916 acrtc->hw_mode = new_crtc_state->mode;
4917 crtc->hwmode = new_crtc_state->mode;
4918 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4919 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4920
4921 /* i.e. reset mode */
54d76575
LSL		 4922 if (dm_old_crtc_state->stream)
4923 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4924 }
4925 } /* for_each_crtc_in_state() */
4926
eb3dc897
NK		 4927 if (dc_state) {
4928 dm_enable_per_frame_crtc_master_sync(dc_state);
4929 WARN_ON(!dc_commit_state(dm->dc, dc_state));
fa2123db 4930 }
e7b07cee 4931
0bc9706d 4932 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4933 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4934
54d76575 4935 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4936
54d76575 4937 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4938 const struct dc_stream_status *status =
54d76575 4939 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4940
eb3dc897
NK		 4941 if (!status)
4942 status = dc_state_get_stream_status(dc_state,
4943 dm_new_crtc_state->stream);
4944
e7b07cee 4945 if (!status)
54d76575 4946 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4947 else
4948 acrtc->otg_inst = status->primary_otg_inst;
4949 }
4950 }
4951
c1ee92f9 4952 /* Handle scaling, underscan, and abm changes*/
c2cea706 4953 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4954 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4955 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4956 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4957 struct dc_stream_status *status = NULL;
4958
44d09c6a 4959 if (acrtc) {
0bc9706d 4960 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 4961 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
4962 }
0bc9706d 4963
e7b07cee 4964 /* Skip any modesets/resets */
0bc9706d 4965 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4966 continue;
4967
e7b07cee 4968
54d76575 4969 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 4970 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4971
4972 /* Skip anything that is not scaling or underscan changes */
4973 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
4974 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
4975 continue;
e7b07cee 4976
54d76575
LSL		 4977 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4978 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4979
70e8ffc5
HW		 4980 if (!dm_new_crtc_state->stream)
4981 continue;
4982
54d76575 4983 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4984 WARN_ON(!status);
3be5262e 4985 WARN_ON(!status->plane_count);
e7b07cee 4986
98e6436d
AK		 4987 dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust;
4988 dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket;
c1ee92f9 4989 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
98e6436d 4990
e7b07cee 4991 /*TODO How it works with MPO ?*/
44d09c6a 4992 if (!commit_planes_to_stream(
e7b07cee 4993 dm->dc,
3be5262e
HW		 4994 status->plane_states,
4995 status->plane_count,
44d09c6a
HW		 4996 dm_new_crtc_state,
4997 to_dm_crtc_state(old_crtc_state),
bc6828e0 4998 dm_state->context))
e7b07cee
HW		 4999 dm_error("%s: Failed to update stream scaling!\n", __func__);
5000 }
5001
e1fc2dca
LSL		 5002 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5003 new_crtc_state, i) {
e7b07cee
HW		 5004 /*
5005 * loop to enable interrupts on newly arrived crtc
5006 */
e1fc2dca
LSL		 5007 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5008 bool modeset_needed;
b830ebc9 5009
fe2a1965
LP		 5010 if (old_crtc_state->active && !new_crtc_state->active)
5011 crtc_disable_count++;
5012
54d76575 5013 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 5014 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5015 modeset_needed = modeset_required(
5016 new_crtc_state,
5017 dm_new_crtc_state->stream,
5018 dm_old_crtc_state->stream);
5019
5020 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
5021 continue;
e7b07cee 5022
e7b07cee
HW		 5023 manage_dm_interrupts(adev, acrtc, true);
5024 }
5025
5026 /* update planes when needed per crtc*/
5cc6dcbd 5027 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 5028 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5029
54d76575 5030 if (dm_new_crtc_state->stream)
eb3dc897
NK		 5031 amdgpu_dm_commit_planes(state, dc_state, dev,
5032 dm, crtc, &wait_for_vblank);
e7b07cee
HW		 5033 }
5034
5035
5036 /*
5037 * send vblank event on all events not handled in flip and
5038 * mark consumed event for drm_atomic_helper_commit_hw_done
5039 */
5040 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 5041 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5042
0bc9706d
LSL		 5043 if (new_crtc_state->event)
5044 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 5045
0bc9706d 5046 new_crtc_state->event = NULL;
e7b07cee
HW		 5047 }
5048 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5049
e7b07cee
HW		 5050
5051 if (wait_for_vblank)
320a1274 5052 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee 5053
717276b9
S		 5054 /*
5055 * FIXME:
5056 * Delay hw_done() until flip_done() is signaled. This is to block
5057 * another commit from freeing the CRTC state while we're still
5058 * waiting on flip_done.
5059 */
5060 drm_atomic_helper_commit_hw_done(state);
5061
e7b07cee 5062 drm_atomic_helper_cleanup_planes(dev, state);
97028037 5063
1f6010a9
DF		 5064 /*
5065 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 5066 * so we can put the GPU into runtime suspend if we're not driving any
5067 * displays anymore
5068 */
fe2a1965
LP		 5069 for (i = 0; i < crtc_disable_count; i++)
5070 pm_runtime_put_autosuspend(dev->dev);
97028037 5071 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 5072
5073 if (dc_state_temp)
5074 dc_release_state(dc_state_temp);
e7b07cee
HW		 5075}
5076
5077
5078static int dm_force_atomic_commit(struct drm_connector *connector)
5079{
5080 int ret = 0;
5081 struct drm_device *ddev = connector->dev;
5082 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5083 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5084 struct drm_plane *plane = disconnected_acrtc->base.primary;
5085 struct drm_connector_state *conn_state;
5086 struct drm_crtc_state *crtc_state;
5087 struct drm_plane_state *plane_state;
5088
5089 if (!state)
5090 return -ENOMEM;
5091
5092 state->acquire_ctx = ddev->mode_config.acquire_ctx;
5093
5094 /* Construct an atomic state to restore previous display setting */
5095
5096 /*
5097 * Attach connectors to drm_atomic_state
5098 */
5099 conn_state = drm_atomic_get_connector_state(state, connector);
5100
5101 ret = PTR_ERR_OR_ZERO(conn_state);
5102 if (ret)
5103 goto err;
5104
5105 /* Attach crtc to drm_atomic_state*/
5106 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5107
5108 ret = PTR_ERR_OR_ZERO(crtc_state);
5109 if (ret)
5110 goto err;
5111
5112 /* force a restore */
5113 crtc_state->mode_changed = true;
5114
5115 /* Attach plane to drm_atomic_state */
5116 plane_state = drm_atomic_get_plane_state(state, plane);
5117
5118 ret = PTR_ERR_OR_ZERO(plane_state);
5119 if (ret)
5120 goto err;
5121
5122
5123 /* Call commit internally with the state we just constructed */
5124 ret = drm_atomic_commit(state);
5125 if (!ret)
5126 return 0;
5127
5128err:
5129 DRM_ERROR("Restoring old state failed with %i\n", ret);
5130 drm_atomic_state_put(state);
5131
5132 return ret;
5133}
5134
5135/*
1f6010a9
DF		 5136 * This function handles all cases when set mode does not come upon hotplug.
5137 * This includes when a display is unplugged then plugged back into the
5138 * same port and when running without usermode desktop manager supprot
e7b07cee 5139 */
3ee6b26b
AD		 5140void dm_restore_drm_connector_state(struct drm_device *dev,
5141 struct drm_connector *connector)
e7b07cee 5142{
c84dec2f 5143 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5144 struct amdgpu_crtc *disconnected_acrtc;
5145 struct dm_crtc_state *acrtc_state;
5146
5147 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5148 return;
5149
5150 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 5151 if (!disconnected_acrtc)
5152 return;
e7b07cee 5153
70e8ffc5
HW		 5154 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5155 if (!acrtc_state->stream)
e7b07cee
HW		 5156 return;
5157
5158 /*
5159 * If the previous sink is not released and different from the current,
5160 * we deduce we are in a state where we can not rely on usermode call
5161 * to turn on the display, so we do it here
5162 */
5163 if (acrtc_state->stream->sink != aconnector->dc_sink)
5164 dm_force_atomic_commit(&aconnector->base);
5165}
5166
1f6010a9 5167/*
e7b07cee
HW		 5168 * Grabs all modesetting locks to serialize against any blocking commits,
5169 * Waits for completion of all non blocking commits.
5170 */
3ee6b26b
AD		 5171static int do_aquire_global_lock(struct drm_device *dev,
5172 struct drm_atomic_state *state)
e7b07cee
HW		 5173{
5174 struct drm_crtc *crtc;
5175 struct drm_crtc_commit *commit;
5176 long ret;
5177
1f6010a9
DF		 5178 /*
5179 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 5180 * ensure that when the framework release it the
5181 * extra locks we are locking here will get released to
5182 */
5183 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
5184 if (ret)
5185 return ret;
5186
5187 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5188 spin_lock(&crtc->commit_lock);
5189 commit = list_first_entry_or_null(&crtc->commit_list,
5190 struct drm_crtc_commit, commit_entry);
5191 if (commit)
5192 drm_crtc_commit_get(commit);
5193 spin_unlock(&crtc->commit_lock);
5194
5195 if (!commit)
5196 continue;
5197
1f6010a9
DF		 5198 /*
5199 * Make sure all pending HW programming completed and
e7b07cee
HW		 5200 * page flips done
5201 */
5202 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
5203
5204 if (ret > 0)
5205 ret = wait_for_completion_interruptible_timeout(
5206 &commit->flip_done, 10*HZ);
5207
5208 if (ret == 0)
5209 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 5210 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 5211
5212 drm_crtc_commit_put(commit);
5213 }
5214
5215 return ret < 0 ? ret : 0;
5216}
5217
98e6436d
AK		 5218void set_freesync_on_stream(struct amdgpu_display_manager *dm,
5219 struct dm_crtc_state *new_crtc_state,
5220 struct dm_connector_state *new_con_state,
5221 struct dc_stream_state *new_stream)
5222{
5223 struct mod_freesync_config config = {0};
5224 struct mod_vrr_params vrr = {0};
5225 struct dc_info_packet vrr_infopacket = {0};
5226 struct amdgpu_dm_connector *aconnector =
5227 to_amdgpu_dm_connector(new_con_state->base.connector);
5228
5229 if (new_con_state->freesync_capable &&
5230 new_con_state->freesync_enable) {
5231 config.state = new_crtc_state->freesync_enabled ?
5232 VRR_STATE_ACTIVE_VARIABLE :
5233 VRR_STATE_INACTIVE;
5234 config.min_refresh_in_uhz =
5235 aconnector->min_vfreq * 1000000;
5236 config.max_refresh_in_uhz =
5237 aconnector->max_vfreq * 1000000;
69ff8845 5238 config.vsif_supported = true;
98e6436d
AK		 5239 }
5240
5241 mod_freesync_build_vrr_params(dm->freesync_module,
5242 new_stream,
5243 &config, &vrr);
5244
5245 mod_freesync_build_vrr_infopacket(dm->freesync_module,
5246 new_stream,
5247 &vrr,
c2791297
S		 5248 packet_type_fs1,
5249 NULL,
98e6436d
AK		 5250 &vrr_infopacket);
5251
5252 new_crtc_state->adjust = vrr.adjust;
5253 new_crtc_state->vrr_infopacket = vrr_infopacket;
5254}
5255
5256static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
3ee6b26b
AD		 5257 struct drm_atomic_state *state,
5258 bool enable,
5259 bool *lock_and_validation_needed)
e7b07cee 5260{
eb3dc897 5261 struct dm_atomic_state *dm_state = NULL;
e7b07cee 5262 struct drm_crtc *crtc;
c2cea706 5263 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 5264 int i;
54d76575 5265 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 5266 struct dc_stream_state *new_stream;
62f55537 5267 int ret = 0;
d4d4a645 5268
1f6010a9
DF		 5269 /*
5270 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
5271 * update changed items
5272 */
c2cea706 5273 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 5274 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 5275 struct amdgpu_dm_connector *aconnector = NULL;
a9e8d275
DF		 5276 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
5277 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
f2877656 5278 struct drm_plane_state *new_plane_state = NULL;
e7b07cee 5279
9635b754
DS		 5280 new_stream = NULL;
5281
54d76575
LSL		 5282 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5283 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 5284 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 5285
f2877656
HW		 5286 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
5287
5288 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
5289 ret = -EINVAL;
5290 goto fail;
5291 }
5292
1daf8c63 5293 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 5294
62f55537 5295 /* TODO This hack should go away */
f4ac176e 5296 if (aconnector && enable) {
1f6010a9 5297 /* Make sure fake sink is created in plug-in scenario */
a9e8d275 5298 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
c2cea706 5299 &aconnector->base);
a9e8d275
DF		 5300 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
5301 &aconnector->base);
19f89e23 5302
a9e8d275
DF		 5303 if (IS_ERR(drm_new_conn_state)) {
5304 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
62f55537
AG		 5305 break;
5306 }
19f89e23 5307
a9e8d275
DF		 5308 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
5309 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 5310
62f55537 5311 new_stream = create_stream_for_sink(aconnector,
c2cea706 5312 &new_crtc_state->mode,
b333730d
BL		 5313 dm_new_conn_state,
5314 dm_old_crtc_state->stream);
19f89e23 5315
62f55537
AG		 5316 /*
5317 * we can have no stream on ACTION_SET if a display
1f6010a9 5318 * was disconnected during S3, in this case it is not an
62f55537 5319 * error, the OS will be updated after detection, and
1f6010a9 5320 * will do the right thing on next atomic commit
62f55537 5321 */
19f89e23 5322
62f55537 5323 if (!new_stream) {
f1ad2f5e 5324 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 5325 __func__, acrtc->base.base.id);
5326 break;
19f89e23 5327 }
e7b07cee 5328
98e6436d
AK		 5329 set_freesync_on_stream(dm, dm_new_crtc_state,
5330 dm_new_conn_state, new_stream);
5331
c1ee92f9
DF		 5332 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
5333
a97599a4
LSL		 5334 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
5335 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
5336 new_crtc_state->mode_changed = false;
5337 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
5338 new_crtc_state->mode_changed);
5339 }
62f55537 5340 }
b830ebc9 5341
98e6436d
AK		 5342 if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled)
5343 new_crtc_state->mode_changed = true;
5344
c2cea706 5345 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 5346 goto next_crtc;
e7b07cee 5347
f1ad2f5e 5348 DRM_DEBUG_DRIVER(
e7b07cee
HW		 5349 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5350 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5351 "connectors_changed:%d\n",
5352 acrtc->crtc_id,
c2cea706
LSL		 5353 new_crtc_state->enable,
5354 new_crtc_state->active,
5355 new_crtc_state->planes_changed,
5356 new_crtc_state->mode_changed,
5357 new_crtc_state->active_changed,
5358 new_crtc_state->connectors_changed);
e7b07cee 5359
62f55537
AG		 5360 /* Remove stream for any changed/disabled CRTC */
5361 if (!enable) {
5362
54d76575 5363 if (!dm_old_crtc_state->stream)
9635b754 5364 goto next_crtc;
62f55537 5365
eb3dc897
NK		 5366 ret = dm_atomic_get_state(state, &dm_state);
5367 if (ret)
5368 goto fail;
5369
f1ad2f5e 5370 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 5371 crtc->base.id);
e7b07cee 5372
1dc90497 5373 /* i.e. reset mode */
62c933f9 5374 if (dc_remove_stream_from_ctx(
98e6436d 5375 dm->dc,
62f55537 5376 dm_state->context,
62c933f9 5377 dm_old_crtc_state->stream) != DC_OK) {
62f55537 5378 ret = -EINVAL;
9635b754 5379 goto fail;
62f55537
AG		 5380 }
5381
54d76575
LSL		 5382 dc_stream_release(dm_old_crtc_state->stream);
5383 dm_new_crtc_state->stream = NULL;
62f55537
AG		 5384
5385 *lock_and_validation_needed = true;
5386
5387 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 5388 /*
5389 * Quick fix to prevent NULL pointer on new_stream when
5390 * added MST connectors not found in existing crtc_state in the chained mode
5391 * TODO: need to dig out the root cause of that
5392 */
5393 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 5394 goto next_crtc;
62f55537 5395
c2cea706 5396 if (modereset_required(new_crtc_state))
9635b754 5397 goto next_crtc;
62f55537 5398
c2cea706 5399 if (modeset_required(new_crtc_state, new_stream,
54d76575 5400 dm_old_crtc_state->stream)) {
62f55537 5401
54d76575 5402 WARN_ON(dm_new_crtc_state->stream);
62f55537 5403
eb3dc897
NK		 5404 ret = dm_atomic_get_state(state, &dm_state);
5405 if (ret)
5406 goto fail;
5407
54d76575 5408 dm_new_crtc_state->stream = new_stream;
27b3f4fc 5409
62f55537
AG		 5410 dc_stream_retain(new_stream);
5411
f1ad2f5e 5412 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 5413 crtc->base.id);
1dc90497 5414
13ab1b44 5415 if (dc_add_stream_to_ctx(
98e6436d 5416 dm->dc,
1dc90497 5417 dm_state->context,
13ab1b44 5418 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 5419 ret = -EINVAL;
9635b754 5420 goto fail;
1dc90497
AG		 5421 }
5422
62f55537 5423 *lock_and_validation_needed = true;
9b690ef3 5424 }
62f55537 5425 }
9b690ef3 5426
9635b754 5427next_crtc:
62f55537
AG		 5428 /* Release extra reference */
5429 if (new_stream)
5430 dc_stream_release(new_stream);
e277adc5
LSL		 5431
5432 /*
5433 * We want to do dc stream updates that do not require a
5434 * full modeset below.
5435 */
20fa2ff0
LSL		 5436 if (!(enable && aconnector && new_crtc_state->enable &&
5437 new_crtc_state->active))
e277adc5
LSL		 5438 continue;
5439 /*
5440 * Given above conditions, the dc state cannot be NULL because:
20fa2ff0
LSL		 5441 * 1. We're in the process of enabling CRTCs (just been added
5442 * to the dc context, or already is on the context)
5443 * 2. Has a valid connector attached, and
5444 * 3. Is currently active and enabled.
5445 * => The dc stream state currently exists.
e277adc5
LSL		 5446 */
5447 BUG_ON(dm_new_crtc_state->stream == NULL);
5448
a9e8d275
DF		 5449 /* Scaling or underscan settings */
5450 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
5451 update_stream_scaling_settings(
5452 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
5453
bc13f2f8
LSL		 5454 /*
5455 * Color management settings. We also update color properties
5456 * when a modeset is needed, to ensure it gets reprogrammed.
5457 */
5458 if (dm_new_crtc_state->base.color_mgmt_changed ||
5459 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
e277adc5
LSL		 5460 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
5461 if (ret)
5462 goto fail;
5463 amdgpu_dm_set_ctm(dm_new_crtc_state);
5464 }
98e6436d
AK		 5465
5466
62f55537 5467 }
e7b07cee 5468
62f55537 5469 return ret;
9635b754
DS		 5470
5471fail:
5472 if (new_stream)
5473 dc_stream_release(new_stream);
5474 return ret;
62f55537 5475}
9b690ef3 5476
3ee6b26b
AD		 5477static int dm_update_planes_state(struct dc *dc,
5478 struct drm_atomic_state *state,
5479 bool enable,
5480 bool *lock_and_validation_needed)
62f55537 5481{
eb3dc897
NK		 5482
5483 struct dm_atomic_state *dm_state = NULL;
62f55537 5484 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 5485 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 5486 struct drm_plane *plane;
5487 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 5488 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 5489 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 5490 int i ;
5491 /* TODO return page_flip_needed() function */
5492 bool pflip_needed = !state->allow_modeset;
5493 int ret = 0;
e7b07cee 5494
9b690ef3 5495
df534fff
S		 5496 /* Add new planes, in reverse order as DC expectation */
5497 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
62f55537
AG		 5498 new_plane_crtc = new_plane_state->crtc;
5499 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 5500 dm_new_plane_state = to_dm_plane_state(new_plane_state);
5501 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 5502
5503 /*TODO Implement atomic check for cursor plane */
5504 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5505 continue;
9b690ef3 5506
62f55537
AG		 5507 /* Remove any changed/removed planes */
5508 if (!enable) {
a2a330ad
S		 5509 if (pflip_needed &&
5510 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 5511 continue;
a7b06724 5512
62f55537
AG		 5513 if (!old_plane_crtc)
5514 continue;
5515
0bc9706d
LSL		 5516 old_crtc_state = drm_atomic_get_old_crtc_state(
5517 state, old_plane_crtc);
54d76575 5518 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 5519
54d76575 5520 if (!dm_old_crtc_state->stream)
62f55537
AG		 5521 continue;
5522
f2877656 5523 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 5524 plane->base.id, old_plane_crtc->base.id);
9b690ef3 5525
eb3dc897
NK		 5526 ret = dm_atomic_get_state(state, &dm_state);
5527 if (ret)
5528 return ret;
5529
62f55537
AG		 5530 if (!dc_remove_plane_from_context(
5531 dc,
54d76575
LSL		 5532 dm_old_crtc_state->stream,
5533 dm_old_plane_state->dc_state,
62f55537
AG		 5534 dm_state->context)) {
5535
5536 ret = EINVAL;
5537 return ret;
e7b07cee
HW		 5538 }
5539
9b690ef3 5540
54d76575
LSL		 5541 dc_plane_state_release(dm_old_plane_state->dc_state);
5542 dm_new_plane_state->dc_state = NULL;
1dc90497 5543
62f55537 5544 *lock_and_validation_needed = true;
1dc90497 5545
62f55537 5546 } else { /* Add new planes */
8c45c5db 5547 struct dc_plane_state *dc_new_plane_state;
1dc90497 5548
62f55537
AG		 5549 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
5550 continue;
e7b07cee 5551
62f55537
AG		 5552 if (!new_plane_crtc)
5553 continue;
e7b07cee 5554
62f55537 5555 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 5556 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 5557
54d76575 5558 if (!dm_new_crtc_state->stream)
62f55537
AG		 5559 continue;
5560
a2a330ad
S		 5561 if (pflip_needed &&
5562 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 5563 continue;
62f55537 5564
54d76575 5565 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 5566
8c45c5db 5567 dc_new_plane_state = dc_create_plane_state(dc);
d5400aab
LSL		 5568 if (!dc_new_plane_state)
5569 return -ENOMEM;
62f55537 5570
8c45c5db
LSL		 5571 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5572 plane->base.id, new_plane_crtc->base.id);
5573
62f55537
AG		 5574 ret = fill_plane_attributes(
5575 new_plane_crtc->dev->dev_private,
8c45c5db 5576 dc_new_plane_state,
62f55537 5577 new_plane_state,
9817d5f5 5578 new_crtc_state);
8c45c5db
LSL		 5579 if (ret) {
5580 dc_plane_state_release(dc_new_plane_state);
62f55537 5581 return ret;
8c45c5db 5582 }
62f55537 5583
eb3dc897
NK		 5584 ret = dm_atomic_get_state(state, &dm_state);
5585 if (ret) {
5586 dc_plane_state_release(dc_new_plane_state);
5587 return ret;
5588 }
5589
8c45c5db
LSL		 5590 /*
5591 * Any atomic check errors that occur after this will
5592 * not need a release. The plane state will be attached
5593 * to the stream, and therefore part of the atomic
5594 * state. It'll be released when the atomic state is
5595 * cleaned.
5596 */
62f55537
AG		 5597 if (!dc_add_plane_to_context(
5598 dc,
54d76575 5599 dm_new_crtc_state->stream,
8c45c5db 5600 dc_new_plane_state,
62f55537
AG		 5601 dm_state->context)) {
5602
8c45c5db 5603 dc_plane_state_release(dc_new_plane_state);
d5400aab 5604 return -EINVAL;
e7b07cee 5605 }
62f55537 5606
8c45c5db
LSL		 5607 dm_new_plane_state->dc_state = dc_new_plane_state;
5608
000b59ea
LSL		 5609 /* Tell DC to do a full surface update every time there
5610 * is a plane change. Inefficient, but works for now.
5611 */
5612 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5613
62f55537 5614 *lock_and_validation_needed = true;
e7b07cee 5615 }
62f55537 5616 }
e7b07cee
HW		 5617
5618
62f55537
AG		 5619 return ret;
5620}
a87fa993 5621
eb3dc897
NK		 5622static int
5623dm_determine_update_type_for_commit(struct dc *dc,
5624 struct drm_atomic_state *state,
5625 enum surface_update_type *out_type)
5626{
5627 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
5628 int i, j, num_plane, ret = 0;
a87fa993
BL		 5629 struct drm_plane_state *old_plane_state, *new_plane_state;
5630 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
5631 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5632 struct drm_plane *plane;
5633
5634 struct drm_crtc *crtc;
5635 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
5636 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
5637 struct dc_stream_status *status = NULL;
5638
5639 struct dc_surface_update *updates = kzalloc(MAX_SURFACES * sizeof(struct dc_surface_update), GFP_KERNEL);
5640 struct dc_plane_state *surface = kzalloc(MAX_SURFACES * sizeof(struct dc_plane_state), GFP_KERNEL);
5641 struct dc_stream_update stream_update;
5642 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5643
4f712911
BL		 5644 if (!updates || !surface) {
5645 DRM_ERROR("Plane or surface update failed to allocate");
5646 /* Set type to FULL to avoid crashing in DC*/
5647 update_type = UPDATE_TYPE_FULL;
eb3dc897 5648 goto cleanup;
4f712911 5649 }
a87fa993
BL		 5650
5651 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5652 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5653 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
5654 num_plane = 0;
5655
5656 if (new_dm_crtc_state->stream) {
5657
5658 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5659 new_plane_crtc = new_plane_state->crtc;
5660 old_plane_crtc = old_plane_state->crtc;
5661 new_dm_plane_state = to_dm_plane_state(new_plane_state);
5662 old_dm_plane_state = to_dm_plane_state(old_plane_state);
5663
5664 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5665 continue;
5666
5667 if (!state->allow_modeset)
5668 continue;
5669
5670 if (crtc == new_plane_crtc) {
5671 updates[num_plane].surface = &surface[num_plane];
5672
5673 if (new_crtc_state->mode_changed) {
5674 updates[num_plane].surface->src_rect =
5675 new_dm_plane_state->dc_state->src_rect;
5676 updates[num_plane].surface->dst_rect =
5677 new_dm_plane_state->dc_state->dst_rect;
5678 updates[num_plane].surface->rotation =
5679 new_dm_plane_state->dc_state->rotation;
5680 updates[num_plane].surface->in_transfer_func =
5681 new_dm_plane_state->dc_state->in_transfer_func;
5682 stream_update.dst = new_dm_crtc_state->stream->dst;
5683 stream_update.src = new_dm_crtc_state->stream->src;
5684 }
5685
5686 if (new_crtc_state->color_mgmt_changed) {
5687 updates[num_plane].gamma =
5688 new_dm_plane_state->dc_state->gamma_correction;
5689 updates[num_plane].in_transfer_func =
5690 new_dm_plane_state->dc_state->in_transfer_func;
5691 stream_update.gamut_remap =
5692 &new_dm_crtc_state->stream->gamut_remap_matrix;
5693 stream_update.out_transfer_func =
5694 new_dm_crtc_state->stream->out_transfer_func;
5695 }
5696
5697 num_plane++;
5698 }
5699 }
5700
5701 if (num_plane > 0) {
eb3dc897
NK		 5702 ret = dm_atomic_get_state(state, &dm_state);
5703 if (ret)
5704 goto cleanup;
5705
5706 old_dm_state = dm_atomic_get_old_state(state);
5707 if (!old_dm_state) {
5708 ret = -EINVAL;
5709 goto cleanup;
5710 }
5711
5712 status = dc_state_get_stream_status(old_dm_state->context,
5713 new_dm_crtc_state->stream);
5714
a87fa993
BL		 5715 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5716 &stream_update, status);
5717
5718 if (update_type > UPDATE_TYPE_MED) {
5719 update_type = UPDATE_TYPE_FULL;
eb3dc897 5720 goto cleanup;
a87fa993
BL		 5721 }
5722 }
5723
5724 } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) {
5725 update_type = UPDATE_TYPE_FULL;
eb3dc897 5726 goto cleanup;
a87fa993
BL		 5727 }
5728 }
5729
eb3dc897 5730cleanup:
a87fa993
BL		 5731 kfree(updates);
5732 kfree(surface);
5733
eb3dc897
NK		 5734 *out_type = update_type;
5735 return ret;
a87fa993 5736}
62f55537 5737
b8592b48
LL		 5738/**
5739 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
5740 * @dev: The DRM device
5741 * @state: The atomic state to commit
5742 *
5743 * Validate that the given atomic state is programmable by DC into hardware.
5744 * This involves constructing a &struct dc_state reflecting the new hardware
5745 * state we wish to commit, then querying DC to see if it is programmable. It's
5746 * important not to modify the existing DC state. Otherwise, atomic_check
5747 * may unexpectedly commit hardware changes.
5748 *
5749 * When validating the DC state, it's important that the right locks are
5750 * acquired. For full updates case which removes/adds/updates streams on one
5751 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
5752 * that any such full update commit will wait for completion of any outstanding
5753 * flip using DRMs synchronization events. See
5754 * dm_determine_update_type_for_commit()
5755 *
5756 * Note that DM adds the affected connectors for all CRTCs in state, when that
5757 * might not seem necessary. This is because DC stream creation requires the
5758 * DC sink, which is tied to the DRM connector state. Cleaning this up should
5759 * be possible but non-trivial - a possible TODO item.
5760 *
5761 * Return: -Error code if validation failed.
5762 */
7578ecda
AD		 5763static int amdgpu_dm_atomic_check(struct drm_device *dev,
5764 struct drm_atomic_state *state)
62f55537 5765{
62f55537 5766 struct amdgpu_device *adev = dev->dev_private;
eb3dc897 5767 struct dm_atomic_state *dm_state = NULL;
62f55537 5768 struct dc *dc = adev->dm.dc;
62f55537 5769 struct drm_connector *connector;
c2cea706 5770 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 5771 struct drm_crtc *crtc;
fc9e9920 5772 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
a87fa993
BL		 5773 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5774 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
5775
1e88ad0a 5776 int ret, i;
e7b07cee 5777
62f55537
AG		 5778 /*
5779 * This bool will be set for true for any modeset/reset
5780 * or plane update which implies non fast surface update.
5781 */
5782 bool lock_and_validation_needed = false;
5783
5784 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 5785 if (ret)
5786 goto fail;
62f55537 5787
1e88ad0a 5788 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
98e6436d
AK		 5789 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5790 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5791
1e88ad0a 5792 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d
AK		 5793 !new_crtc_state->color_mgmt_changed &&
5794 (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled))
1e88ad0a 5795 continue;
7bef1af3 5796
1e88ad0a
S		 5797 if (!new_crtc_state->enable)
5798 continue;
fc9e9920 5799
1e88ad0a
S		 5800 ret = drm_atomic_add_affected_connectors(state, crtc);
5801 if (ret)
5802 return ret;
fc9e9920 5803
1e88ad0a
S		 5804 ret = drm_atomic_add_affected_planes(state, crtc);
5805 if (ret)
5806 goto fail;
e7b07cee
HW		 5807 }
5808
62f55537
AG		 5809 /* Remove exiting planes if they are modified */
5810 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
5811 if (ret) {
5812 goto fail;
5813 }
5814
5815 /* Disable all crtcs which require disable */
98e6436d 5816 ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed);
62f55537
AG		 5817 if (ret) {
5818 goto fail;
5819 }
5820
5821 /* Enable all crtcs which require enable */
98e6436d 5822 ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed);
62f55537
AG		 5823 if (ret) {
5824 goto fail;
5825 }
5826
5827 /* Add new/modified planes */
5828 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
5829 if (ret) {
5830 goto fail;
5831 }
5832
b349f76e
ES		 5833 /* Run this here since we want to validate the streams we created */
5834 ret = drm_atomic_helper_check_planes(dev, state);
5835 if (ret)
5836 goto fail;
62f55537 5837
ebdd27e1 5838 /* Check scaling and underscan changes*/
1f6010a9 5839 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 5840 * new stream into context w\o causing full reset. Need to
5841 * decide how to handle.
5842 */
c2cea706 5843 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5844 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5845 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5846 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 5847
5848 /* Skip any modesets/resets */
0bc9706d
LSL		 5849 if (!acrtc || drm_atomic_crtc_needs_modeset(
5850 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 5851 continue;
5852
b830ebc9 5853 /* Skip any thing not scale or underscan changes */
54d76575 5854 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 5855 continue;
5856
a87fa993 5857 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 5858 lock_and_validation_needed = true;
5859 }
5860
eb3dc897
NK		 5861 ret = dm_determine_update_type_for_commit(dc, state, &update_type);
5862 if (ret)
5863 goto fail;
a87fa993
BL		 5864
5865 if (overall_update_type < update_type)
5866 overall_update_type = update_type;
5867
5868 /*
5869 * lock_and_validation_needed was an old way to determine if we need to set
5870 * the global lock. Leaving it in to check if we broke any corner cases
5871 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
5872 * lock_and_validation_needed false = UPDATE_TYPE_FAST
5873 */
5874 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
5875 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
5876 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
5877 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
e7b07cee 5878
e7b07cee 5879
a87fa993 5880 if (overall_update_type > UPDATE_TYPE_FAST) {
eb3dc897
NK		 5881 ret = dm_atomic_get_state(state, &dm_state);
5882 if (ret)
5883 goto fail;
e7b07cee
HW		 5884
5885 ret = do_aquire_global_lock(dev, state);
5886 if (ret)
5887 goto fail;
1dc90497 5888
e750d56d 5889 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 5890 ret = -EINVAL;
5891 goto fail;
5892 }
5893 }
5894
5895 /* Must be success */
5896 WARN_ON(ret);
5897 return ret;
5898
5899fail:
5900 if (ret == -EDEADLK)
01e28f9c 5901 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 5902 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 5903 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 5904 else
01e28f9c 5905 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 5906
5907 return ret;
5908}
5909
3ee6b26b
AD		 5910static bool is_dp_capable_without_timing_msa(struct dc *dc,
5911 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 5912{
5913 uint8_t dpcd_data;
5914 bool capable = false;
5915
c84dec2f 5916 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 5917 dm_helpers_dp_read_dpcd(
5918 NULL,
c84dec2f 5919 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 5920 DP_DOWN_STREAM_PORT_COUNT,
5921 &dpcd_data,
5922 sizeof(dpcd_data))) {
5923 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
5924 }
5925
5926 return capable;
5927}
98e6436d
AK		 5928void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
5929 struct edid *edid)
e7b07cee
HW		 5930{
5931 int i;
e7b07cee
HW		 5932 bool edid_check_required;
5933 struct detailed_timing *timing;
5934 struct detailed_non_pixel *data;
5935 struct detailed_data_monitor_range *range;
c84dec2f
HW		 5936 struct amdgpu_dm_connector *amdgpu_dm_connector =
5937 to_amdgpu_dm_connector(connector);
8218d7f1 5938 struct dm_connector_state *dm_con_state;
e7b07cee
HW		 5939
5940 struct drm_device *dev = connector->dev;
5941 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 5942
8218d7f1
HW		 5943 if (!connector->state) {
5944 DRM_ERROR("%s - Connector has no state", __func__);
5945 return;
5946 }
5947
98e6436d
AK		 5948 if (!edid) {
5949 dm_con_state = to_dm_connector_state(connector->state);
5950
5951 amdgpu_dm_connector->min_vfreq = 0;
5952 amdgpu_dm_connector->max_vfreq = 0;
5953 amdgpu_dm_connector->pixel_clock_mhz = 0;
5954
5955 dm_con_state->freesync_capable = false;
5956 dm_con_state->freesync_enable = false;
5957 return;
5958 }
5959
8218d7f1
HW		 5960 dm_con_state = to_dm_connector_state(connector->state);
5961
e7b07cee 5962 edid_check_required = false;
c84dec2f 5963 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 5964 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
5965 return;
5966 }
5967 if (!adev->dm.freesync_module)
5968 return;
5969 /*
5970 * if edid non zero restrict freesync only for dp and edp
5971 */
5972 if (edid) {
c84dec2f
HW		 5973 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
5974 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 5975 edid_check_required = is_dp_capable_without_timing_msa(
5976 adev->dm.dc,
c84dec2f 5977 amdgpu_dm_connector);
e7b07cee
HW		 5978 }
5979 }
8218d7f1 5980 dm_con_state->freesync_capable = false;
e7b07cee
HW		 5981 if (edid_check_required == true && (edid->version > 1 ||
5982 (edid->version == 1 && edid->revision > 1))) {
5983 for (i = 0; i < 4; i++) {
5984
5985 timing = &edid->detailed_timings[i];
5986 data = &timing->data.other_data;
5987 range = &data->data.range;
5988 /*
5989 * Check if monitor has continuous frequency mode
5990 */
5991 if (data->type != EDID_DETAIL_MONITOR_RANGE)
5992 continue;
5993 /*
5994 * Check for flag range limits only. If flag == 1 then
5995 * no additional timing information provided.
5996 * Default GTF, GTF Secondary curve and CVT are not
5997 * supported
5998 */
5999 if (range->flags != 1)
6000 continue;
6001
c84dec2f
HW		 6002 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6003 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6004 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 6005 range->pixel_clock_mhz * 10;
6006 break;
6007 }
6008
c84dec2f 6009 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 6010 amdgpu_dm_connector->min_vfreq > 10) {
6011
8218d7f1 6012 dm_con_state->freesync_capable = true;
e7b07cee
HW		 6013 }
6014 }
e7b07cee
HW		 6015}
6016
Linux 6.x block layer and io_uring tree(s)