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drm/amd/display: Let updates with no scaling changes be fast
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
1dc90497 31#include "dc/inc/core_types.h"
4562236b
HW		 32
33#include "vid.h"
34#include "amdgpu.h"
a49dcb88 35#include "amdgpu_display.h"
a94d5569 36#include "amdgpu_ucode.h"
4562236b
HW		 37#include "atom.h"
38#include "amdgpu_dm.h"
e7b07cee 39#include "amdgpu_pm.h"
4562236b
HW		 40
41#include "amd_shared.h"
42#include "amdgpu_dm_irq.h"
43#include "dm_helpers.h"
e7b07cee 44#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 45#if defined(CONFIG_DEBUG_FS)
46#include "amdgpu_dm_debugfs.h"
47#endif
4562236b
HW		 48
49#include "ivsrcid/ivsrcid_vislands30.h"
50
51#include <linux/module.h>
52#include <linux/moduleparam.h>
53#include <linux/version.h>
e7b07cee 54#include <linux/types.h>
97028037 55#include <linux/pm_runtime.h>
a94d5569 56#include <linux/firmware.h>
4562236b 57
e7b07cee 58#include <drm/drmP.h>
4562236b 59#include <drm/drm_atomic.h>
674e78ac 60#include <drm/drm_atomic_uapi.h>
4562236b
HW		 61#include <drm/drm_atomic_helper.h>
62#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 63#include <drm/drm_fb_helper.h>
64#include <drm/drm_edid.h>
4562236b 65
ff5ef992
AD		 66#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
67#include "ivsrcid/irqsrcs_dcn_1_0.h"
68
ad941f7a
FX		 69#include "dcn/dcn_1_0_offset.h"
70#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 71#include "soc15_hw_ip.h"
72#include "vega10_ip_offset.h"
ff5ef992
AD		 73
74#include "soc15_common.h"
75#endif
76
e7b07cee 77#include "modules/inc/mod_freesync.h"
bbf854dc 78#include "modules/power/power_helpers.h"
ecd0136b 79#include "modules/inc/mod_info_packet.h"
e7b07cee 80
a94d5569
DF		 81#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
82MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 83
b8592b48
LL		 84/**
85 * DOC: overview
86 *
87 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
88 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
89 * requests into DC requests, and DC responses into DRM responses.
90 *
91 * The root control structure is &struct amdgpu_display_manager.
92 */
93
7578ecda
AD		 94/* basic init/fini API */
95static int amdgpu_dm_init(struct amdgpu_device *adev);
96static void amdgpu_dm_fini(struct amdgpu_device *adev);
97
1f6010a9
DF		 98/*
99 * initializes drm_device display related structures, based on the information
7578ecda
AD		 100 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
101 * drm_encoder, drm_mode_config
102 *
103 * Returns 0 on success
104 */
105static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
106/* removes and deallocates the drm structures, created by the above function */
107static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
108
109static void
110amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
111
112static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 113 struct drm_plane *plane,
7578ecda
AD		 114 unsigned long possible_crtcs);
115static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
116 struct drm_plane *plane,
117 uint32_t link_index);
118static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
119 struct amdgpu_dm_connector *amdgpu_dm_connector,
120 uint32_t link_index,
121 struct amdgpu_encoder *amdgpu_encoder);
122static int amdgpu_dm_encoder_init(struct drm_device *dev,
123 struct amdgpu_encoder *aencoder,
124 uint32_t link_index);
125
126static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
127
128static int amdgpu_dm_atomic_commit(struct drm_device *dev,
129 struct drm_atomic_state *state,
130 bool nonblock);
131
132static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
133
134static int amdgpu_dm_atomic_check(struct drm_device *dev,
135 struct drm_atomic_state *state);
136
674e78ac
NK		 137static void handle_cursor_update(struct drm_plane *plane,
138 struct drm_plane_state *old_plane_state);
7578ecda
AD		 139
140
e7b07cee 141
e04a6123 142static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 143 DRM_PLANE_TYPE_PRIMARY,
144 DRM_PLANE_TYPE_PRIMARY,
145 DRM_PLANE_TYPE_PRIMARY,
146 DRM_PLANE_TYPE_PRIMARY,
147 DRM_PLANE_TYPE_PRIMARY,
148 DRM_PLANE_TYPE_PRIMARY,
149};
150
e04a6123 151static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 152 DRM_PLANE_TYPE_PRIMARY,
153 DRM_PLANE_TYPE_PRIMARY,
154 DRM_PLANE_TYPE_PRIMARY,
155 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
156};
157
e04a6123 158static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 159 DRM_PLANE_TYPE_PRIMARY,
160 DRM_PLANE_TYPE_PRIMARY,
161 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
162};
163
4562236b
HW		 164/*
165 * dm_vblank_get_counter
166 *
167 * @brief
168 * Get counter for number of vertical blanks
169 *
170 * @param
171 * struct amdgpu_device *adev - [in] desired amdgpu device
172 * int disp_idx - [in] which CRTC to get the counter from
173 *
174 * @return
175 * Counter for vertical blanks
176 */
177static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
178{
179 if (crtc >= adev->mode_info.num_crtc)
180 return 0;
181 else {
182 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 183 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
184 acrtc->base.state);
4562236b 185
da5c47f6
AG		 186
187 if (acrtc_state->stream == NULL) {
0971c40e
HW		 188 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
189 crtc);
4562236b
HW		 190 return 0;
191 }
192
da5c47f6 193 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 194 }
195}
196
197static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 198 u32 *vbl, u32 *position)
4562236b 199{
81c50963
ST		 200 uint32_t v_blank_start, v_blank_end, h_position, v_position;
201
4562236b
HW		 202 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
203 return -EINVAL;
204 else {
205 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 206 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
207 acrtc->base.state);
4562236b 208
da5c47f6 209 if (acrtc_state->stream == NULL) {
0971c40e
HW		 210 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
211 crtc);
4562236b
HW		 212 return 0;
213 }
214
81c50963
ST		 215 /*
216 * TODO rework base driver to use values directly.
217 * for now parse it back into reg-format
218 */
da5c47f6 219 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 220 &v_blank_start,
221 &v_blank_end,
222 &h_position,
223 &v_position);
224
e806208d
AG		 225 *position = v_position | (h_position << 16);
226 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 227 }
228
229 return 0;
230}
231
232static bool dm_is_idle(void *handle)
233{
234 /* XXX todo */
235 return true;
236}
237
238static int dm_wait_for_idle(void *handle)
239{
240 /* XXX todo */
241 return 0;
242}
243
244static bool dm_check_soft_reset(void *handle)
245{
246 return false;
247}
248
249static int dm_soft_reset(void *handle)
250{
251 /* XXX todo */
252 return 0;
253}
254
3ee6b26b
AD		 255static struct amdgpu_crtc *
256get_crtc_by_otg_inst(struct amdgpu_device *adev,
257 int otg_inst)
4562236b
HW		 258{
259 struct drm_device *dev = adev->ddev;
260 struct drm_crtc *crtc;
261 struct amdgpu_crtc *amdgpu_crtc;
262
4562236b
HW		 263 if (otg_inst == -1) {
264 WARN_ON(1);
265 return adev->mode_info.crtcs[0];
266 }
267
268 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
269 amdgpu_crtc = to_amdgpu_crtc(crtc);
270
271 if (amdgpu_crtc->otg_inst == otg_inst)
272 return amdgpu_crtc;
273 }
274
275 return NULL;
276}
277
278static void dm_pflip_high_irq(void *interrupt_params)
279{
4562236b
HW		 280 struct amdgpu_crtc *amdgpu_crtc;
281 struct common_irq_params *irq_params = interrupt_params;
282 struct amdgpu_device *adev = irq_params->adev;
283 unsigned long flags;
284
285 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
286
287 /* IRQ could occur when in initial stage */
1f6010a9 288 /* TODO work and BO cleanup */
4562236b
HW		 289 if (amdgpu_crtc == NULL) {
290 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
291 return;
292 }
293
294 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 295
296 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
297 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
298 amdgpu_crtc->pflip_status,
299 AMDGPU_FLIP_SUBMITTED,
300 amdgpu_crtc->crtc_id,
301 amdgpu_crtc);
302 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
303 return;
304 }
305
4562236b 306
1f6010a9 307 /* wake up userspace */
1159898a 308 if (amdgpu_crtc->event) {
1f6010a9 309 /* Update to correct count(s) if racing with vblank irq */
753c66c9
MK		 310 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
311
54f5499a 312 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 313
54f5499a
AG		 314 /* page flip completed. clean up */
315 amdgpu_crtc->event = NULL;
1159898a 316
54f5499a
AG		 317 } else
318 WARN_ON(1);
4562236b 319
54f5499a 320 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 321 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
322
54f5499a
AG		 323 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
324 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 325
326 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 327}
328
329static void dm_crtc_high_irq(void *interrupt_params)
330{
331 struct common_irq_params *irq_params = interrupt_params;
332 struct amdgpu_device *adev = irq_params->adev;
4562236b 333 struct amdgpu_crtc *acrtc;
180db303 334 struct dm_crtc_state *acrtc_state;
4562236b 335
b57de80a 336 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 337
e5d0170e
LSL		 338 if (acrtc) {
339 drm_crtc_handle_vblank(&acrtc->base);
340 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
180db303
NK		 341
342 acrtc_state = to_dm_crtc_state(acrtc->base.state);
343
344 if (acrtc_state->stream &&
345 acrtc_state->vrr_params.supported &&
346 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
347 mod_freesync_handle_v_update(
348 adev->dm.freesync_module,
349 acrtc_state->stream,
350 &acrtc_state->vrr_params);
351
352 dc_stream_adjust_vmin_vmax(
353 adev->dm.dc,
354 acrtc_state->stream,
355 &acrtc_state->vrr_params.adjust);
356 }
e5d0170e 357 }
4562236b
HW		 358}
359
360static int dm_set_clockgating_state(void *handle,
361 enum amd_clockgating_state state)
362{
363 return 0;
364}
365
366static int dm_set_powergating_state(void *handle,
367 enum amd_powergating_state state)
368{
369 return 0;
370}
371
372/* Prototypes of private functions */
373static int dm_early_init(void* handle);
374
a32e24b4 375/* Allocate memory for FBC compressed data */
3e332d3a 376static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 377{
3e332d3a
RL		 378 struct drm_device *dev = connector->dev;
379 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 380 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 381 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
382 struct drm_display_mode *mode;
42e67c3b
RL		 383 unsigned long max_size = 0;
384
385 if (adev->dm.dc->fbc_compressor == NULL)
386 return;
a32e24b4 387
3e332d3a 388 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 389 return;
390
3e332d3a
RL		 391 if (compressor->bo_ptr)
392 return;
42e67c3b 393
42e67c3b 394
3e332d3a
RL		 395 list_for_each_entry(mode, &connector->modes, head) {
396 if (max_size < mode->htotal * mode->vtotal)
397 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 398 }
399
400 if (max_size) {
401 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 402 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 403 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 404
405 if (r)
42e67c3b
RL		 406 DRM_ERROR("DM: Failed to initialize FBC\n");
407 else {
408 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
409 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
410 }
411
a32e24b4
RL		 412 }
413
414}
a32e24b4 415
7578ecda 416static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 417{
418 struct dc_init_data init_data;
419 adev->dm.ddev = adev->ddev;
420 adev->dm.adev = adev;
421
4562236b
HW		 422 /* Zero all the fields */
423 memset(&init_data, 0, sizeof(init_data));
424
674e78ac
NK		 425 mutex_init(&adev->dm.dc_lock);
426
4562236b
HW		 427 if(amdgpu_dm_irq_init(adev)) {
428 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
429 goto error;
430 }
431
432 init_data.asic_id.chip_family = adev->family;
433
434 init_data.asic_id.pci_revision_id = adev->rev_id;
435 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
436
770d13b1 437 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 438 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
439 init_data.asic_id.atombios_base_address =
440 adev->mode_info.atom_context->bios;
441
442 init_data.driver = adev;
443
444 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
445
446 if (!adev->dm.cgs_device) {
447 DRM_ERROR("amdgpu: failed to create cgs device.\n");
448 goto error;
449 }
450
451 init_data.cgs_device = adev->dm.cgs_device;
452
4562236b
HW		 453 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
454
6e227308
HW		 455 /*
456 * TODO debug why this doesn't work on Raven
457 */
458 if (adev->flags & AMD_IS_APU &&
459 adev->asic_type >= CHIP_CARRIZO &&
460 adev->asic_type < CHIP_RAVEN)
461 init_data.flags.gpu_vm_support = true;
462
04b94af4
AD		 463 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
464 init_data.flags.fbc_support = true;
465
4562236b
HW		 466 /* Display Core create. */
467 adev->dm.dc = dc_create(&init_data);
468
423788c7 469 if (adev->dm.dc) {
76121231 470 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 471 } else {
76121231 472 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 473 goto error;
474 }
4562236b 475
4562236b
HW		 476 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
477 if (!adev->dm.freesync_module) {
478 DRM_ERROR(
479 "amdgpu: failed to initialize freesync_module.\n");
480 } else
f1ad2f5e 481 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 482 adev->dm.freesync_module);
483
e277adc5
LSL		 484 amdgpu_dm_init_color_mod();
485
4562236b
HW		 486 if (amdgpu_dm_initialize_drm_device(adev)) {
487 DRM_ERROR(
488 "amdgpu: failed to initialize sw for display support.\n");
489 goto error;
490 }
491
492 /* Update the actual used number of crtc */
493 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
494
495 /* TODO: Add_display_info? */
496
497 /* TODO use dynamic cursor width */
ce75805e
AG		 498 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
499 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 500
501 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
502 DRM_ERROR(
503 "amdgpu: failed to initialize sw for display support.\n");
504 goto error;
505 }
506
e498eb71
NK		 507#if defined(CONFIG_DEBUG_FS)
508 if (dtn_debugfs_init(adev))
509 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
510#endif
511
f1ad2f5e 512 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 513
514 return 0;
515error:
516 amdgpu_dm_fini(adev);
517
59d0f396 518 return -EINVAL;
4562236b
HW		 519}
520
7578ecda 521static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 522{
523 amdgpu_dm_destroy_drm_device(&adev->dm);
524 /*
525 * TODO: pageflip, vlank interrupt
526 *
527 * amdgpu_dm_irq_fini(adev);
528 */
529
530 if (adev->dm.cgs_device) {
531 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
532 adev->dm.cgs_device = NULL;
533 }
534 if (adev->dm.freesync_module) {
535 mod_freesync_destroy(adev->dm.freesync_module);
536 adev->dm.freesync_module = NULL;
537 }
538 /* DC Destroy TODO: Replace destroy DAL */
21de3396 539 if (adev->dm.dc)
4562236b 540 dc_destroy(&adev->dm.dc);
674e78ac
NK		 541
542 mutex_destroy(&adev->dm.dc_lock);
543
4562236b
HW		 544 return;
545}
546
a94d5569 547static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 548{
a94d5569
DF		 549 const char *fw_name_dmcu;
550 int r;
551 const struct dmcu_firmware_header_v1_0 *hdr;
552
553 switch(adev->asic_type) {
554 case CHIP_BONAIRE:
555 case CHIP_HAWAII:
556 case CHIP_KAVERI:
557 case CHIP_KABINI:
558 case CHIP_MULLINS:
559 case CHIP_TONGA:
560 case CHIP_FIJI:
561 case CHIP_CARRIZO:
562 case CHIP_STONEY:
563 case CHIP_POLARIS11:
564 case CHIP_POLARIS10:
565 case CHIP_POLARIS12:
566 case CHIP_VEGAM:
567 case CHIP_VEGA10:
568 case CHIP_VEGA12:
569 case CHIP_VEGA20:
570 return 0;
571 case CHIP_RAVEN:
572 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
573 break;
574 default:
575 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 576 return -EINVAL;
a94d5569
DF		 577 }
578
579 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
580 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
581 return 0;
582 }
583
584 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
585 if (r == -ENOENT) {
586 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
587 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
588 adev->dm.fw_dmcu = NULL;
589 return 0;
590 }
591 if (r) {
592 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
593 fw_name_dmcu);
594 return r;
595 }
596
597 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
598 if (r) {
599 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
600 fw_name_dmcu);
601 release_firmware(adev->dm.fw_dmcu);
602 adev->dm.fw_dmcu = NULL;
603 return r;
604 }
605
606 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
607 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
608 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
609 adev->firmware.fw_size +=
610 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
611
612 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
613 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
614 adev->firmware.fw_size +=
615 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
616
ee6e89c0
DF		 617 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
618
a94d5569
DF		 619 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
620
4562236b
HW		 621 return 0;
622}
623
a94d5569
DF		 624static int dm_sw_init(void *handle)
625{
626 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
627
628 return load_dmcu_fw(adev);
629}
630
4562236b
HW		 631static int dm_sw_fini(void *handle)
632{
a94d5569
DF		 633 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
634
635 if(adev->dm.fw_dmcu) {
636 release_firmware(adev->dm.fw_dmcu);
637 adev->dm.fw_dmcu = NULL;
638 }
639
4562236b
HW		 640 return 0;
641}
642
7abcf6b5 643static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 644{
c84dec2f 645 struct amdgpu_dm_connector *aconnector;
4562236b 646 struct drm_connector *connector;
7abcf6b5 647 int ret = 0;
4562236b
HW		 648
649 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
650
651 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 652 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 653 if (aconnector->dc_link->type == dc_connection_mst_branch &&
654 aconnector->mst_mgr.aux) {
f1ad2f5e 655 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 656 aconnector, aconnector->base.base.id);
657
658 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
659 if (ret < 0) {
660 DRM_ERROR("DM_MST: Failed to start MST\n");
661 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
662 return ret;
4562236b 663 }
7abcf6b5 664 }
4562236b
HW		 665 }
666
667 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 668 return ret;
669}
670
671static int dm_late_init(void *handle)
672{
42e67c3b 673 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 674
bbf854dc
DF		 675 struct dmcu_iram_parameters params;
676 unsigned int linear_lut[16];
677 int i;
678 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
679 bool ret;
680
681 for (i = 0; i < 16; i++)
682 linear_lut[i] = 0xFFFF * i / 15;
683
684 params.set = 0;
685 params.backlight_ramping_start = 0xCCCC;
686 params.backlight_ramping_reduction = 0xCCCCCCCC;
687 params.backlight_lut_array_size = 16;
688 params.backlight_lut_array = linear_lut;
689
690 ret = dmcu_load_iram(dmcu, params);
691
692 if (!ret)
693 return -EINVAL;
694
42e67c3b 695 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 696}
697
698static void s3_handle_mst(struct drm_device *dev, bool suspend)
699{
c84dec2f 700 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 701 struct drm_connector *connector;
702
703 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
704
705 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 706 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 707 if (aconnector->dc_link->type == dc_connection_mst_branch &&
708 !aconnector->mst_port) {
709
710 if (suspend)
711 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
712 else
713 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
714 }
715 }
716
717 drm_modeset_unlock(&dev->mode_config.connection_mutex);
718}
719
b8592b48
LL		 720/**
721 * dm_hw_init() - Initialize DC device
722 * @handle: The base driver device containing the amdpgu_dm device.
723 *
724 * Initialize the &struct amdgpu_display_manager device. This involves calling
725 * the initializers of each DM component, then populating the struct with them.
726 *
727 * Although the function implies hardware initialization, both hardware and
728 * software are initialized here. Splitting them out to their relevant init
729 * hooks is a future TODO item.
730 *
731 * Some notable things that are initialized here:
732 *
733 * - Display Core, both software and hardware
734 * - DC modules that we need (freesync and color management)
735 * - DRM software states
736 * - Interrupt sources and handlers
737 * - Vblank support
738 * - Debug FS entries, if enabled
739 */
4562236b
HW		 740static int dm_hw_init(void *handle)
741{
742 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
743 /* Create DAL display manager */
744 amdgpu_dm_init(adev);
4562236b
HW		 745 amdgpu_dm_hpd_init(adev);
746
4562236b
HW		 747 return 0;
748}
749
b8592b48
LL		 750/**
751 * dm_hw_fini() - Teardown DC device
752 * @handle: The base driver device containing the amdpgu_dm device.
753 *
754 * Teardown components within &struct amdgpu_display_manager that require
755 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
756 * were loaded. Also flush IRQ workqueues and disable them.
757 */
4562236b
HW		 758static int dm_hw_fini(void *handle)
759{
760 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
761
762 amdgpu_dm_hpd_fini(adev);
763
764 amdgpu_dm_irq_fini(adev);
21de3396 765 amdgpu_dm_fini(adev);
4562236b
HW		 766 return 0;
767}
768
769static int dm_suspend(void *handle)
770{
771 struct amdgpu_device *adev = handle;
772 struct amdgpu_display_manager *dm = &adev->dm;
773 int ret = 0;
4562236b
HW		 774
775 s3_handle_mst(adev->ddev, true);
776
4562236b
HW		 777 amdgpu_dm_irq_suspend(adev);
778
0a214e2f 779 WARN_ON(adev->dm.cached_state);
a3621485
AG		 780 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
781
32f5062d 782 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 783
784 return ret;
785}
786
1daf8c63
AD		 787static struct amdgpu_dm_connector *
788amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
789 struct drm_crtc *crtc)
4562236b
HW		 790{
791 uint32_t i;
c2cea706 792 struct drm_connector_state *new_con_state;
4562236b
HW		 793 struct drm_connector *connector;
794 struct drm_crtc *crtc_from_state;
795
c2cea706
LSL		 796 for_each_new_connector_in_state(state, connector, new_con_state, i) {
797 crtc_from_state = new_con_state->crtc;
4562236b
HW		 798
799 if (crtc_from_state == crtc)
c84dec2f 800 return to_amdgpu_dm_connector(connector);
4562236b
HW		 801 }
802
803 return NULL;
804}
805
fbbdadf2
BL		 806static void emulated_link_detect(struct dc_link *link)
807{
808 struct dc_sink_init_data sink_init_data = { 0 };
809 struct display_sink_capability sink_caps = { 0 };
810 enum dc_edid_status edid_status;
811 struct dc_context *dc_ctx = link->ctx;
812 struct dc_sink *sink = NULL;
813 struct dc_sink *prev_sink = NULL;
814
815 link->type = dc_connection_none;
816 prev_sink = link->local_sink;
817
818 if (prev_sink != NULL)
819 dc_sink_retain(prev_sink);
820
821 switch (link->connector_signal) {
822 case SIGNAL_TYPE_HDMI_TYPE_A: {
823 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
824 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
825 break;
826 }
827
828 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
829 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
830 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
831 break;
832 }
833
834 case SIGNAL_TYPE_DVI_DUAL_LINK: {
835 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
836 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
837 break;
838 }
839
840 case SIGNAL_TYPE_LVDS: {
841 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
842 sink_caps.signal = SIGNAL_TYPE_LVDS;
843 break;
844 }
845
846 case SIGNAL_TYPE_EDP: {
847 sink_caps.transaction_type =
848 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
849 sink_caps.signal = SIGNAL_TYPE_EDP;
850 break;
851 }
852
853 case SIGNAL_TYPE_DISPLAY_PORT: {
854 sink_caps.transaction_type =
855 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
856 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
857 break;
858 }
859
860 default:
861 DC_ERROR("Invalid connector type! signal:%d\n",
862 link->connector_signal);
863 return;
864 }
865
866 sink_init_data.link = link;
867 sink_init_data.sink_signal = sink_caps.signal;
868
869 sink = dc_sink_create(&sink_init_data);
870 if (!sink) {
871 DC_ERROR("Failed to create sink!\n");
872 return;
873 }
874
875 link->local_sink = sink;
876
877 edid_status = dm_helpers_read_local_edid(
878 link->ctx,
879 link,
880 sink);
881
882 if (edid_status != EDID_OK)
883 DC_ERROR("Failed to read EDID");
884
885}
886
4562236b
HW		 887static int dm_resume(void *handle)
888{
889 struct amdgpu_device *adev = handle;
4562236b
HW		 890 struct drm_device *ddev = adev->ddev;
891 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 892 struct amdgpu_dm_connector *aconnector;
4562236b 893 struct drm_connector *connector;
4562236b 894 struct drm_crtc *crtc;
c2cea706 895 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 896 struct dm_crtc_state *dm_new_crtc_state;
897 struct drm_plane *plane;
898 struct drm_plane_state *new_plane_state;
899 struct dm_plane_state *dm_new_plane_state;
fbbdadf2 900 enum dc_connection_type new_connection_type = dc_connection_none;
a80aa93d 901 int ret;
a3621485 902 int i;
4562236b 903
a80aa93d
ML		 904 /* power on hardware */
905 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
906
4562236b
HW		 907 /* program HPD filter */
908 dc_resume(dm->dc);
909
910 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
911 s3_handle_mst(ddev, false);
912
913 /*
914 * early enable HPD Rx IRQ, should be done before set mode as short
915 * pulse interrupts are used for MST
916 */
917 amdgpu_dm_irq_resume_early(adev);
918
4562236b 919 /* Do detection*/
a80aa93d 920 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 921 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 922
923 /*
924 * this is the case when traversing through already created
925 * MST connectors, should be skipped
926 */
927 if (aconnector->mst_port)
928 continue;
929
03ea364c 930 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 931 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
932 DRM_ERROR("KMS: Failed to detect connector\n");
933
934 if (aconnector->base.force && new_connection_type == dc_connection_none)
935 emulated_link_detect(aconnector->dc_link);
936 else
937 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 938
939 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
940 aconnector->fake_enable = false;
941
4562236b
HW		 942 aconnector->dc_sink = NULL;
943 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 944 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 945 }
946
1f6010a9 947 /* Force mode set in atomic commit */
a80aa93d 948 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 949 new_crtc_state->active_changed = true;
4f346e65 950
fcb4019e
LSL		 951 /*
952 * atomic_check is expected to create the dc states. We need to release
953 * them here, since they were duplicated as part of the suspend
954 * procedure.
955 */
a80aa93d 956 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 957 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
958 if (dm_new_crtc_state->stream) {
959 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
960 dc_stream_release(dm_new_crtc_state->stream);
961 dm_new_crtc_state->stream = NULL;
962 }
963 }
964
a80aa93d 965 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 966 dm_new_plane_state = to_dm_plane_state(new_plane_state);
967 if (dm_new_plane_state->dc_state) {
968 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
969 dc_plane_state_release(dm_new_plane_state->dc_state);
970 dm_new_plane_state->dc_state = NULL;
971 }
972 }
973
a80aa93d 974 ret = drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 975
a80aa93d 976 dm->cached_state = NULL;
0a214e2f 977
9faa4237 978 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 979
980 return ret;
981}
982
b8592b48
LL		 983/**
984 * DOC: DM Lifecycle
985 *
986 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
987 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
988 * the base driver's device list to be initialized and torn down accordingly.
989 *
990 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
991 */
992
4562236b
HW		 993static const struct amd_ip_funcs amdgpu_dm_funcs = {
994 .name = "dm",
995 .early_init = dm_early_init,
7abcf6b5 996 .late_init = dm_late_init,
4562236b
HW		 997 .sw_init = dm_sw_init,
998 .sw_fini = dm_sw_fini,
999 .hw_init = dm_hw_init,
1000 .hw_fini = dm_hw_fini,
1001 .suspend = dm_suspend,
1002 .resume = dm_resume,
1003 .is_idle = dm_is_idle,
1004 .wait_for_idle = dm_wait_for_idle,
1005 .check_soft_reset = dm_check_soft_reset,
1006 .soft_reset = dm_soft_reset,
1007 .set_clockgating_state = dm_set_clockgating_state,
1008 .set_powergating_state = dm_set_powergating_state,
1009};
1010
1011const struct amdgpu_ip_block_version dm_ip_block =
1012{
1013 .type = AMD_IP_BLOCK_TYPE_DCE,
1014 .major = 1,
1015 .minor = 0,
1016 .rev = 0,
1017 .funcs = &amdgpu_dm_funcs,
1018};
1019
ca3268c4 1020
b8592b48
LL		 1021/**
1022 * DOC: atomic
1023 *
1024 * *WIP*
1025 */
0a323b84 1026
b3663f70 1027static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 1028 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 1029 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 1030 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 1031 .atomic_commit = amdgpu_dm_atomic_commit,
54f5499a
AG		 1032};
1033
1034static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1035 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 1036};
1037
7578ecda 1038static void
3ee6b26b 1039amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1040{
1041 struct drm_connector *connector = &aconnector->base;
1042 struct drm_device *dev = connector->dev;
b73a22d3 1043 struct dc_sink *sink;
4562236b
HW		 1044
1045 /* MST handled by drm_mst framework */
1046 if (aconnector->mst_mgr.mst_state == true)
1047 return;
1048
1049
1050 sink = aconnector->dc_link->local_sink;
1051
1f6010a9
DF		 1052 /*
1053 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 1054 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 1055 * Skip if already done during boot.
4562236b
HW		 1056 */
1057 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1058 && aconnector->dc_em_sink) {
1059
1f6010a9
DF		 1060 /*
1061 * For S3 resume with headless use eml_sink to fake stream
1062 * because on resume connector->sink is set to NULL
4562236b
HW		 1063 */
1064 mutex_lock(&dev->mode_config.mutex);
1065
1066 if (sink) {
922aa1e1 1067 if (aconnector->dc_sink) {
98e6436d 1068 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 1069 /*
1070 * retain and release below are used to
1071 * bump up refcount for sink because the link doesn't point
1072 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 1073 * reshuffle by UMD we will get into unwanted dc_sink release
1074 */
1075 if (aconnector->dc_sink != aconnector->dc_em_sink)
1076 dc_sink_release(aconnector->dc_sink);
1077 }
4562236b 1078 aconnector->dc_sink = sink;
98e6436d
AK		 1079 amdgpu_dm_update_freesync_caps(connector,
1080 aconnector->edid);
4562236b 1081 } else {
98e6436d 1082 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1083 if (!aconnector->dc_sink)
1084 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 1085 else if (aconnector->dc_sink != aconnector->dc_em_sink)
1086 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 1087 }
1088
1089 mutex_unlock(&dev->mode_config.mutex);
1090 return;
1091 }
1092
1093 /*
1094 * TODO: temporary guard to look for proper fix
1095 * if this sink is MST sink, we should not do anything
1096 */
1097 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
1098 return;
1099
1100 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 1101 /*
1102 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1103 * Do nothing!!
1104 */
f1ad2f5e 1105 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 1106 aconnector->connector_id);
1107 return;
1108 }
1109
f1ad2f5e 1110 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 1111 aconnector->connector_id, aconnector->dc_sink, sink);
1112
1113 mutex_lock(&dev->mode_config.mutex);
1114
1f6010a9
DF		 1115 /*
1116 * 1. Update status of the drm connector
1117 * 2. Send an event and let userspace tell us what to do
1118 */
4562236b 1119 if (sink) {
1f6010a9
DF		 1120 /*
1121 * TODO: check if we still need the S3 mode update workaround.
1122 * If yes, put it here.
1123 */
4562236b 1124 if (aconnector->dc_sink)
98e6436d 1125 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1126
1127 aconnector->dc_sink = sink;
900b3cb1 1128 if (sink->dc_edid.length == 0) {
4562236b 1129 aconnector->edid = NULL;
e86e8947 1130 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 1131 } else {
4562236b
HW		 1132 aconnector->edid =
1133 (struct edid *) sink->dc_edid.raw_edid;
1134
1135
c555f023 1136 drm_connector_update_edid_property(connector,
4562236b 1137 aconnector->edid);
e86e8947
HV		 1138 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1139 aconnector->edid);
4562236b 1140 }
98e6436d 1141 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 1142
1143 } else {
e86e8947 1144 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 1145 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 1146 drm_connector_update_edid_property(connector, NULL);
4562236b
HW		 1147 aconnector->num_modes = 0;
1148 aconnector->dc_sink = NULL;
5326c452 1149 aconnector->edid = NULL;
4562236b
HW		 1150 }
1151
1152 mutex_unlock(&dev->mode_config.mutex);
1153}
1154
1155static void handle_hpd_irq(void *param)
1156{
c84dec2f 1157 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1158 struct drm_connector *connector = &aconnector->base;
1159 struct drm_device *dev = connector->dev;
fbbdadf2 1160 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1161
1f6010a9
DF		 1162 /*
1163 * In case of failure or MST no need to update connector status or notify the OS
1164 * since (for MST case) MST does this in its own context.
4562236b
HW		 1165 */
1166 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 1167
1168 if (aconnector->fake_enable)
1169 aconnector->fake_enable = false;
1170
fbbdadf2
BL		 1171 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1172 DRM_ERROR("KMS: Failed to detect connector\n");
1173
1174 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1175 emulated_link_detect(aconnector->dc_link);
1176
1177
1178 drm_modeset_lock_all(dev);
1179 dm_restore_drm_connector_state(dev, connector);
1180 drm_modeset_unlock_all(dev);
1181
1182 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1183 drm_kms_helper_hotplug_event(dev);
1184
1185 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1186 amdgpu_dm_update_connector_after_detect(aconnector);
1187
1188
1189 drm_modeset_lock_all(dev);
1190 dm_restore_drm_connector_state(dev, connector);
1191 drm_modeset_unlock_all(dev);
1192
1193 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1194 drm_kms_helper_hotplug_event(dev);
1195 }
1196 mutex_unlock(&aconnector->hpd_lock);
1197
1198}
1199
c84dec2f 1200static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1201{
1202 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1203 uint8_t dret;
1204 bool new_irq_handled = false;
1205 int dpcd_addr;
1206 int dpcd_bytes_to_read;
1207
1208 const int max_process_count = 30;
1209 int process_count = 0;
1210
1211 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1212
1213 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1214 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1215 /* DPCD 0x200 - 0x201 for downstream IRQ */
1216 dpcd_addr = DP_SINK_COUNT;
1217 } else {
1218 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1219 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1220 dpcd_addr = DP_SINK_COUNT_ESI;
1221 }
1222
1223 dret = drm_dp_dpcd_read(
1224 &aconnector->dm_dp_aux.aux,
1225 dpcd_addr,
1226 esi,
1227 dpcd_bytes_to_read);
1228
1229 while (dret == dpcd_bytes_to_read &&
1230 process_count < max_process_count) {
1231 uint8_t retry;
1232 dret = 0;
1233
1234 process_count++;
1235
f1ad2f5e 1236 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1237 /* handle HPD short pulse irq */
1238 if (aconnector->mst_mgr.mst_state)
1239 drm_dp_mst_hpd_irq(
1240 &aconnector->mst_mgr,
1241 esi,
1242 &new_irq_handled);
4562236b
HW		 1243
1244 if (new_irq_handled) {
1245 /* ACK at DPCD to notify down stream */
1246 const int ack_dpcd_bytes_to_write =
1247 dpcd_bytes_to_read - 1;
1248
1249 for (retry = 0; retry < 3; retry++) {
1250 uint8_t wret;
1251
1252 wret = drm_dp_dpcd_write(
1253 &aconnector->dm_dp_aux.aux,
1254 dpcd_addr + 1,
1255 &esi[1],
1256 ack_dpcd_bytes_to_write);
1257 if (wret == ack_dpcd_bytes_to_write)
1258 break;
1259 }
1260
1f6010a9 1261 /* check if there is new irq to be handled */
4562236b
HW		 1262 dret = drm_dp_dpcd_read(
1263 &aconnector->dm_dp_aux.aux,
1264 dpcd_addr,
1265 esi,
1266 dpcd_bytes_to_read);
1267
1268 new_irq_handled = false;
d4a6e8a9 1269 } else {
4562236b 1270 break;
d4a6e8a9 1271 }
4562236b
HW		 1272 }
1273
1274 if (process_count == max_process_count)
f1ad2f5e 1275 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1276}
1277
1278static void handle_hpd_rx_irq(void *param)
1279{
c84dec2f 1280 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1281 struct drm_connector *connector = &aconnector->base;
1282 struct drm_device *dev = connector->dev;
53cbf65c 1283 struct dc_link *dc_link = aconnector->dc_link;
4562236b 1284 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
fbbdadf2 1285 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1286
1f6010a9
DF		 1287 /*
1288 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 1289 * conflict, after implement i2c helper, this mutex should be
1290 * retired.
1291 */
53cbf65c 1292 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1293 mutex_lock(&aconnector->hpd_lock);
1294
4e18814e 1295 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1296 !is_mst_root_connector) {
1297 /* Downstream Port status changed. */
fbbdadf2
BL		 1298 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1299 DRM_ERROR("KMS: Failed to detect connector\n");
1300
1301 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1302 emulated_link_detect(dc_link);
1303
1304 if (aconnector->fake_enable)
1305 aconnector->fake_enable = false;
1306
1307 amdgpu_dm_update_connector_after_detect(aconnector);
1308
1309
1310 drm_modeset_lock_all(dev);
1311 dm_restore_drm_connector_state(dev, connector);
1312 drm_modeset_unlock_all(dev);
1313
1314 drm_kms_helper_hotplug_event(dev);
1315 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1316
1317 if (aconnector->fake_enable)
1318 aconnector->fake_enable = false;
1319
4562236b
HW		 1320 amdgpu_dm_update_connector_after_detect(aconnector);
1321
1322
1323 drm_modeset_lock_all(dev);
1324 dm_restore_drm_connector_state(dev, connector);
1325 drm_modeset_unlock_all(dev);
1326
1327 drm_kms_helper_hotplug_event(dev);
1328 }
1329 }
1330 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1331 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1332 dm_handle_hpd_rx_irq(aconnector);
1333
e86e8947
HV		 1334 if (dc_link->type != dc_connection_mst_branch) {
1335 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 1336 mutex_unlock(&aconnector->hpd_lock);
e86e8947 1337 }
4562236b
HW		 1338}
1339
1340static void register_hpd_handlers(struct amdgpu_device *adev)
1341{
1342 struct drm_device *dev = adev->ddev;
1343 struct drm_connector *connector;
c84dec2f 1344 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1345 const struct dc_link *dc_link;
1346 struct dc_interrupt_params int_params = {0};
1347
1348 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1349 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1350
1351 list_for_each_entry(connector,
1352 &dev->mode_config.connector_list, head) {
1353
c84dec2f 1354 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1355 dc_link = aconnector->dc_link;
1356
1357 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1358 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1359 int_params.irq_source = dc_link->irq_source_hpd;
1360
1361 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1362 handle_hpd_irq,
1363 (void *) aconnector);
1364 }
1365
1366 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1367
1368 /* Also register for DP short pulse (hpd_rx). */
1369 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1370 int_params.irq_source = dc_link->irq_source_hpd_rx;
1371
1372 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1373 handle_hpd_rx_irq,
1374 (void *) aconnector);
1375 }
1376 }
1377}
1378
1379/* Register IRQ sources and initialize IRQ callbacks */
1380static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1381{
1382 struct dc *dc = adev->dm.dc;
1383 struct common_irq_params *c_irq_params;
1384 struct dc_interrupt_params int_params = {0};
1385 int r;
1386 int i;
1ffdeca6 1387 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 1388
ff5ef992 1389 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1390 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1391 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1392 adev->asic_type == CHIP_RAVEN)
3760f76c 1393 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1394
1395 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1396 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1397
1f6010a9
DF		 1398 /*
1399 * Actions of amdgpu_irq_add_id():
4562236b
HW		 1400 * 1. Register a set() function with base driver.
1401 * Base driver will call set() function to enable/disable an
1402 * interrupt in DC hardware.
1403 * 2. Register amdgpu_dm_irq_handler().
1404 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1405 * coming from DC hardware.
1406 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1407 * for acknowledging and handling. */
1408
b57de80a 1409 /* Use VBLANK interrupt */
e9029155 1410 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1411 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1412 if (r) {
1413 DRM_ERROR("Failed to add crtc irq id!\n");
1414 return r;
1415 }
1416
1417 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1418 int_params.irq_source =
3d761e79 1419 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1420
b57de80a 1421 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1422
1423 c_irq_params->adev = adev;
1424 c_irq_params->irq_src = int_params.irq_source;
1425
1426 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1427 dm_crtc_high_irq, c_irq_params);
1428 }
1429
3d761e79 1430 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1431 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1432 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1433 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1434 if (r) {
1435 DRM_ERROR("Failed to add page flip irq id!\n");
1436 return r;
1437 }
1438
1439 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1440 int_params.irq_source =
1441 dc_interrupt_to_irq_source(dc, i, 0);
1442
1443 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1444
1445 c_irq_params->adev = adev;
1446 c_irq_params->irq_src = int_params.irq_source;
1447
1448 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1449 dm_pflip_high_irq, c_irq_params);
1450
1451 }
1452
1453 /* HPD */
2c8ad2d5
AD		 1454 r = amdgpu_irq_add_id(adev, client_id,
1455 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1456 if (r) {
1457 DRM_ERROR("Failed to add hpd irq id!\n");
1458 return r;
1459 }
1460
1461 register_hpd_handlers(adev);
1462
1463 return 0;
1464}
1465
ff5ef992
AD		 1466#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1467/* Register IRQ sources and initialize IRQ callbacks */
1468static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1469{
1470 struct dc *dc = adev->dm.dc;
1471 struct common_irq_params *c_irq_params;
1472 struct dc_interrupt_params int_params = {0};
1473 int r;
1474 int i;
1475
1476 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1477 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1478
1f6010a9
DF		 1479 /*
1480 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 1481 * 1. Register a set() function with base driver.
1482 * Base driver will call set() function to enable/disable an
1483 * interrupt in DC hardware.
1484 * 2. Register amdgpu_dm_irq_handler().
1485 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1486 * coming from DC hardware.
1487 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1488 * for acknowledging and handling.
1f6010a9 1489 */
ff5ef992
AD		 1490
1491 /* Use VSTARTUP interrupt */
1492 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1493 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1494 i++) {
3760f76c 1495 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1496
1497 if (r) {
1498 DRM_ERROR("Failed to add crtc irq id!\n");
1499 return r;
1500 }
1501
1502 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1503 int_params.irq_source =
1504 dc_interrupt_to_irq_source(dc, i, 0);
1505
1506 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1507
1508 c_irq_params->adev = adev;
1509 c_irq_params->irq_src = int_params.irq_source;
1510
1511 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1512 dm_crtc_high_irq, c_irq_params);
1513 }
1514
1515 /* Use GRPH_PFLIP interrupt */
1516 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1517 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1518 i++) {
3760f76c 1519 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1520 if (r) {
1521 DRM_ERROR("Failed to add page flip irq id!\n");
1522 return r;
1523 }
1524
1525 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1526 int_params.irq_source =
1527 dc_interrupt_to_irq_source(dc, i, 0);
1528
1529 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1530
1531 c_irq_params->adev = adev;
1532 c_irq_params->irq_src = int_params.irq_source;
1533
1534 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1535 dm_pflip_high_irq, c_irq_params);
1536
1537 }
1538
1539 /* HPD */
3760f76c 1540 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1541 &adev->hpd_irq);
1542 if (r) {
1543 DRM_ERROR("Failed to add hpd irq id!\n");
1544 return r;
1545 }
1546
1547 register_hpd_handlers(adev);
1548
1549 return 0;
1550}
1551#endif
1552
eb3dc897
NK		 1553/*
1554 * Acquires the lock for the atomic state object and returns
1555 * the new atomic state.
1556 *
1557 * This should only be called during atomic check.
1558 */
1559static int dm_atomic_get_state(struct drm_atomic_state *state,
1560 struct dm_atomic_state **dm_state)
1561{
1562 struct drm_device *dev = state->dev;
1563 struct amdgpu_device *adev = dev->dev_private;
1564 struct amdgpu_display_manager *dm = &adev->dm;
1565 struct drm_private_state *priv_state;
1566 int ret;
1567
1568 if (*dm_state)
1569 return 0;
1570
1571 ret = drm_modeset_lock(&dm->atomic_obj_lock, state->acquire_ctx);
1572 if (ret)
1573 return ret;
1574
1575 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1576 if (IS_ERR(priv_state))
1577 return PTR_ERR(priv_state);
1578
1579 *dm_state = to_dm_atomic_state(priv_state);
1580
1581 return 0;
1582}
1583
1584struct dm_atomic_state *
1585dm_atomic_get_new_state(struct drm_atomic_state *state)
1586{
1587 struct drm_device *dev = state->dev;
1588 struct amdgpu_device *adev = dev->dev_private;
1589 struct amdgpu_display_manager *dm = &adev->dm;
1590 struct drm_private_obj *obj;
1591 struct drm_private_state *new_obj_state;
1592 int i;
1593
1594 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1595 if (obj->funcs == dm->atomic_obj.funcs)
1596 return to_dm_atomic_state(new_obj_state);
1597 }
1598
1599 return NULL;
1600}
1601
1602struct dm_atomic_state *
1603dm_atomic_get_old_state(struct drm_atomic_state *state)
1604{
1605 struct drm_device *dev = state->dev;
1606 struct amdgpu_device *adev = dev->dev_private;
1607 struct amdgpu_display_manager *dm = &adev->dm;
1608 struct drm_private_obj *obj;
1609 struct drm_private_state *old_obj_state;
1610 int i;
1611
1612 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1613 if (obj->funcs == dm->atomic_obj.funcs)
1614 return to_dm_atomic_state(old_obj_state);
1615 }
1616
1617 return NULL;
1618}
1619
1620static struct drm_private_state *
1621dm_atomic_duplicate_state(struct drm_private_obj *obj)
1622{
1623 struct dm_atomic_state *old_state, *new_state;
1624
1625 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1626 if (!new_state)
1627 return NULL;
1628
1629 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1630
1631 new_state->context = dc_create_state();
1632 if (!new_state->context) {
1633 kfree(new_state);
1634 return NULL;
1635 }
1636
1637 old_state = to_dm_atomic_state(obj->state);
1638 if (old_state && old_state->context)
1639 dc_resource_state_copy_construct(old_state->context,
1640 new_state->context);
1641
1642 return &new_state->base;
1643}
1644
1645static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1646 struct drm_private_state *state)
1647{
1648 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1649
1650 if (dm_state && dm_state->context)
1651 dc_release_state(dm_state->context);
1652
1653 kfree(dm_state);
1654}
1655
1656static struct drm_private_state_funcs dm_atomic_state_funcs = {
1657 .atomic_duplicate_state = dm_atomic_duplicate_state,
1658 .atomic_destroy_state = dm_atomic_destroy_state,
1659};
1660
4562236b
HW		 1661static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1662{
eb3dc897 1663 struct dm_atomic_state *state;
4562236b
HW		 1664 int r;
1665
1666 adev->mode_info.mode_config_initialized = true;
1667
4562236b 1668 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1669 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1670
1671 adev->ddev->mode_config.max_width = 16384;
1672 adev->ddev->mode_config.max_height = 16384;
1673
1674 adev->ddev->mode_config.preferred_depth = 24;
1675 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 1676 /* indicates support for immediate flip */
4562236b
HW		 1677 adev->ddev->mode_config.async_page_flip = true;
1678
770d13b1 1679 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1680
eb3dc897
NK		 1681 drm_modeset_lock_init(&adev->dm.atomic_obj_lock);
1682
1683 state = kzalloc(sizeof(*state), GFP_KERNEL);
1684 if (!state)
1685 return -ENOMEM;
1686
1687 state->context = dc_create_state();
1688 if (!state->context) {
1689 kfree(state);
1690 return -ENOMEM;
1691 }
1692
1693 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1694
8c1a765b
DA		 1695 drm_atomic_private_obj_init(adev->ddev,
1696 &adev->dm.atomic_obj,
eb3dc897
NK		 1697 &state->base,
1698 &dm_atomic_state_funcs);
1699
3dc9b1ce 1700 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1701 if (r)
1702 return r;
1703
1704 return 0;
1705}
1706
206bbafe
DF		 1707#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1708#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1709
4562236b
HW		 1710#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1711 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1712
206bbafe
DF		 1713static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1714{
1715#if defined(CONFIG_ACPI)
1716 struct amdgpu_dm_backlight_caps caps;
1717
1718 if (dm->backlight_caps.caps_valid)
1719 return;
1720
1721 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1722 if (caps.caps_valid) {
1723 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1724 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1725 dm->backlight_caps.caps_valid = true;
1726 } else {
1727 dm->backlight_caps.min_input_signal =
1728 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1729 dm->backlight_caps.max_input_signal =
1730 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1731 }
1732#else
8bcbc9ef
DF		 1733 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1734 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 1735#endif
1736}
1737
4562236b
HW		 1738static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1739{
1740 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe
DF		 1741 struct amdgpu_dm_backlight_caps caps;
1742 uint32_t brightness = bd->props.brightness;
4562236b 1743
206bbafe
DF		 1744 amdgpu_dm_update_backlight_caps(dm);
1745 caps = dm->backlight_caps;
0cafc82f 1746 /*
206bbafe
DF		 1747 * The brightness input is in the range 0-255
1748 * It needs to be rescaled to be between the
1749 * requested min and max input signal
1750 *
1751 * It also needs to be scaled up by 0x101 to
1752 * match the DC interface which has a range of
1753 * 0 to 0xffff
0cafc82f 1754 */
206bbafe
DF		 1755 brightness =
1756 brightness
1757 * 0x101
1758 * (caps.max_input_signal - caps.min_input_signal)
1759 / AMDGPU_MAX_BL_LEVEL
1760 + caps.min_input_signal * 0x101;
4562236b
HW		 1761
1762 if (dc_link_set_backlight_level(dm->backlight_link,
923fe495 1763 brightness, 0))
4562236b
HW		 1764 return 0;
1765 else
1766 return 1;
1767}
1768
1769static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1770{
620a0d27
DF		 1771 struct amdgpu_display_manager *dm = bl_get_data(bd);
1772 int ret = dc_link_get_backlight_level(dm->backlight_link);
1773
1774 if (ret == DC_ERROR_UNEXPECTED)
1775 return bd->props.brightness;
1776 return ret;
4562236b
HW		 1777}
1778
1779static const struct backlight_ops amdgpu_dm_backlight_ops = {
1780 .get_brightness = amdgpu_dm_backlight_get_brightness,
1781 .update_status = amdgpu_dm_backlight_update_status,
1782};
1783
7578ecda
AD		 1784static void
1785amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1786{
1787 char bl_name[16];
1788 struct backlight_properties props = { 0 };
1789
206bbafe
DF		 1790 amdgpu_dm_update_backlight_caps(dm);
1791
4562236b 1792 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 1793 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 1794 props.type = BACKLIGHT_RAW;
1795
1796 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1797 dm->adev->ddev->primary->index);
1798
1799 dm->backlight_dev = backlight_device_register(bl_name,
1800 dm->adev->ddev->dev,
1801 dm,
1802 &amdgpu_dm_backlight_ops,
1803 &props);
1804
74baea42 1805 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1806 DRM_ERROR("DM: Backlight registration failed!\n");
1807 else
f1ad2f5e 1808 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1809}
1810
1811#endif
1812
df534fff
S		 1813static int initialize_plane(struct amdgpu_display_manager *dm,
1814 struct amdgpu_mode_info *mode_info,
1815 int plane_id)
1816{
f180b4bc 1817 struct drm_plane *plane;
df534fff
S		 1818 unsigned long possible_crtcs;
1819 int ret = 0;
1820
f180b4bc 1821 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 1822 mode_info->planes[plane_id] = plane;
1823
1824 if (!plane) {
1825 DRM_ERROR("KMS: Failed to allocate plane\n");
1826 return -ENOMEM;
1827 }
f180b4bc 1828 plane->type = mode_info->plane_type[plane_id];
df534fff
S		 1829
1830 /*
1f6010a9 1831 * HACK: IGT tests expect that each plane can only have
df534fff
S		 1832 * one possible CRTC. For now, set one CRTC for each
1833 * plane that is not an underlay, but still allow multiple
1834 * CRTCs for underlay planes.
1835 */
1836 possible_crtcs = 1 << plane_id;
1837 if (plane_id >= dm->dc->caps.max_streams)
1838 possible_crtcs = 0xff;
1839
1840 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1841
1842 if (ret) {
1843 DRM_ERROR("KMS: Failed to initialize plane\n");
1844 return ret;
1845 }
1846
1847 return ret;
1848}
1849
89fc8d4e
HW		 1850
1851static void register_backlight_device(struct amdgpu_display_manager *dm,
1852 struct dc_link *link)
1853{
1854#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1855 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1856
1857 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1858 link->type != dc_connection_none) {
1f6010a9
DF		 1859 /*
1860 * Event if registration failed, we should continue with
89fc8d4e
HW		 1861 * DM initialization because not having a backlight control
1862 * is better then a black screen.
1863 */
1864 amdgpu_dm_register_backlight_device(dm);
1865
1866 if (dm->backlight_dev)
1867 dm->backlight_link = link;
1868 }
1869#endif
1870}
1871
1872
1f6010a9
DF		 1873/*
1874 * In this architecture, the association
4562236b
HW		 1875 * connector -> encoder -> crtc
1876 * id not really requried. The crtc and connector will hold the
1877 * display_index as an abstraction to use with DAL component
1878 *
1879 * Returns 0 on success
1880 */
7578ecda 1881static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1882{
1883 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 1884 int32_t i;
c84dec2f 1885 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1886 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1887 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1888 uint32_t link_cnt;
df534fff 1889 int32_t total_overlay_planes, total_primary_planes;
fbbdadf2 1890 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b
HW		 1891
1892 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1893 if (amdgpu_dm_mode_config_init(dm->adev)) {
1894 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 1895 return -EINVAL;
4562236b
HW		 1896 }
1897
df534fff
S		 1898 /* Identify the number of planes to be initialized */
1899 total_overlay_planes = dm->dc->caps.max_slave_planes;
1900 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
efa6a8b7 1901
df534fff
S		 1902 /* First initialize overlay planes, index starting after primary planes */
1903 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1904 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1905 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 1906 goto fail;
d4e13b0d 1907 }
df534fff 1908 }
92f3ac40 1909
df534fff
S		 1910 /* Initialize primary planes */
1911 for (i = (total_primary_planes - 1); i >= 0; i--) {
1912 if (initialize_plane(dm, mode_info, i)) {
1913 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 1914 goto fail;
d4e13b0d
AD		 1915 }
1916 }
4562236b 1917
d4e13b0d 1918 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 1919 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 1920 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1921 goto fail;
4562236b 1922 }
4562236b 1923
ab2541b6 1924 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1925
1926 /* loops over all connectors on the board */
1927 for (i = 0; i < link_cnt; i++) {
89fc8d4e 1928 struct dc_link *link = NULL;
4562236b
HW		 1929
1930 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1931 DRM_ERROR(
1932 "KMS: Cannot support more than %d display indexes\n",
1933 AMDGPU_DM_MAX_DISPLAY_INDEX);
1934 continue;
1935 }
1936
1937 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1938 if (!aconnector)
cd8a2ae8 1939 goto fail;
4562236b
HW		 1940
1941 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1942 if (!aencoder)
cd8a2ae8 1943 goto fail;
4562236b
HW		 1944
1945 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1946 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1947 goto fail;
4562236b
HW		 1948 }
1949
1950 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1951 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1952 goto fail;
4562236b
HW		 1953 }
1954
89fc8d4e
HW		 1955 link = dc_get_link_at_index(dm->dc, i);
1956
fbbdadf2
BL		 1957 if (!dc_link_detect_sink(link, &new_connection_type))
1958 DRM_ERROR("KMS: Failed to detect connector\n");
1959
1960 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1961 emulated_link_detect(link);
1962 amdgpu_dm_update_connector_after_detect(aconnector);
1963
1964 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 1965 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 1966 register_backlight_device(dm, link);
1967 }
1968
1969
4562236b
HW		 1970 }
1971
1972 /* Software is initialized. Now we can register interrupt handlers. */
1973 switch (adev->asic_type) {
1974 case CHIP_BONAIRE:
1975 case CHIP_HAWAII:
cd4b356f
AD		 1976 case CHIP_KAVERI:
1977 case CHIP_KABINI:
1978 case CHIP_MULLINS:
4562236b
HW		 1979 case CHIP_TONGA:
1980 case CHIP_FIJI:
1981 case CHIP_CARRIZO:
1982 case CHIP_STONEY:
1983 case CHIP_POLARIS11:
1984 case CHIP_POLARIS10:
b264d345 1985 case CHIP_POLARIS12:
7737de91 1986 case CHIP_VEGAM:
2c8ad2d5 1987 case CHIP_VEGA10:
2325ff30 1988 case CHIP_VEGA12:
1fe6bf2f 1989 case CHIP_VEGA20:
4562236b
HW		 1990 if (dce110_register_irq_handlers(dm->adev)) {
1991 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1992 goto fail;
4562236b
HW		 1993 }
1994 break;
ff5ef992
AD		 1995#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1996 case CHIP_RAVEN:
1997 if (dcn10_register_irq_handlers(dm->adev)) {
1998 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1999 goto fail;
ff5ef992
AD		 2000 }
2001 break;
2002#endif
4562236b 2003 default:
e63f8673 2004 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 2005 goto fail;
4562236b
HW		 2006 }
2007
1bc460a4
HW		 2008 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2009 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2010
4562236b 2011 return 0;
cd8a2ae8 2012fail:
4562236b 2013 kfree(aencoder);
4562236b 2014 kfree(aconnector);
3be5262e 2015 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 2016 kfree(mode_info->planes[i]);
59d0f396 2017 return -EINVAL;
4562236b
HW		 2018}
2019
7578ecda 2020static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2021{
2022 drm_mode_config_cleanup(dm->ddev);
eb3dc897 2023 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 2024 return;
2025}
2026
2027/******************************************************************************
2028 * amdgpu_display_funcs functions
2029 *****************************************************************************/
2030
1f6010a9 2031/*
4562236b
HW		 2032 * dm_bandwidth_update - program display watermarks
2033 *
2034 * @adev: amdgpu_device pointer
2035 *
2036 * Calculate and program the display watermarks and line buffer allocation.
2037 */
2038static void dm_bandwidth_update(struct amdgpu_device *adev)
2039{
49c07a99 2040 /* TODO: implement later */
4562236b
HW		 2041}
2042
39cc5be2 2043static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 2044 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2045 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 2046 .backlight_set_level = NULL, /* never called for DC */
2047 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 2048 .hpd_sense = NULL,/* called unconditionally */
2049 .hpd_set_polarity = NULL, /* called unconditionally */
2050 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2051 .page_flip_get_scanoutpos =
2052 dm_crtc_get_scanoutpos,/* called unconditionally */
2053 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2054 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2055};
2056
2057#if defined(CONFIG_DEBUG_KERNEL_DC)
2058
3ee6b26b
AD		 2059static ssize_t s3_debug_store(struct device *device,
2060 struct device_attribute *attr,
2061 const char *buf,
2062 size_t count)
4562236b
HW		 2063{
2064 int ret;
2065 int s3_state;
2066 struct pci_dev *pdev = to_pci_dev(device);
2067 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2068 struct amdgpu_device *adev = drm_dev->dev_private;
2069
2070 ret = kstrtoint(buf, 0, &s3_state);
2071
2072 if (ret == 0) {
2073 if (s3_state) {
2074 dm_resume(adev);
4562236b
HW		 2075 drm_kms_helper_hotplug_event(adev->ddev);
2076 } else
2077 dm_suspend(adev);
2078 }
2079
2080 return ret == 0 ? count : 0;
2081}
2082
2083DEVICE_ATTR_WO(s3_debug);
2084
2085#endif
2086
2087static int dm_early_init(void *handle)
2088{
2089 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2090
4562236b
HW		 2091 switch (adev->asic_type) {
2092 case CHIP_BONAIRE:
2093 case CHIP_HAWAII:
2094 adev->mode_info.num_crtc = 6;
2095 adev->mode_info.num_hpd = 6;
2096 adev->mode_info.num_dig = 6;
3be5262e 2097 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 2098 break;
cd4b356f
AD		 2099 case CHIP_KAVERI:
2100 adev->mode_info.num_crtc = 4;
2101 adev->mode_info.num_hpd = 6;
2102 adev->mode_info.num_dig = 7;
2103 adev->mode_info.plane_type = dm_plane_type_default;
2104 break;
2105 case CHIP_KABINI:
2106 case CHIP_MULLINS:
2107 adev->mode_info.num_crtc = 2;
2108 adev->mode_info.num_hpd = 6;
2109 adev->mode_info.num_dig = 6;
2110 adev->mode_info.plane_type = dm_plane_type_default;
2111 break;
4562236b
HW		 2112 case CHIP_FIJI:
2113 case CHIP_TONGA:
2114 adev->mode_info.num_crtc = 6;
2115 adev->mode_info.num_hpd = 6;
2116 adev->mode_info.num_dig = 7;
3be5262e 2117 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 2118 break;
2119 case CHIP_CARRIZO:
2120 adev->mode_info.num_crtc = 3;
2121 adev->mode_info.num_hpd = 6;
2122 adev->mode_info.num_dig = 9;
3be5262e 2123 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 2124 break;
2125 case CHIP_STONEY:
2126 adev->mode_info.num_crtc = 2;
2127 adev->mode_info.num_hpd = 6;
2128 adev->mode_info.num_dig = 9;
3be5262e 2129 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 2130 break;
2131 case CHIP_POLARIS11:
b264d345 2132 case CHIP_POLARIS12:
4562236b
HW		 2133 adev->mode_info.num_crtc = 5;
2134 adev->mode_info.num_hpd = 5;
2135 adev->mode_info.num_dig = 5;
3be5262e 2136 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 2137 break;
2138 case CHIP_POLARIS10:
7737de91 2139 case CHIP_VEGAM:
4562236b
HW		 2140 adev->mode_info.num_crtc = 6;
2141 adev->mode_info.num_hpd = 6;
2142 adev->mode_info.num_dig = 6;
3be5262e 2143 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 2144 break;
2c8ad2d5 2145 case CHIP_VEGA10:
2325ff30 2146 case CHIP_VEGA12:
1fe6bf2f 2147 case CHIP_VEGA20:
2c8ad2d5
AD		 2148 adev->mode_info.num_crtc = 6;
2149 adev->mode_info.num_hpd = 6;
2150 adev->mode_info.num_dig = 6;
3be5262e 2151 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 2152 break;
ff5ef992
AD		 2153#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2154 case CHIP_RAVEN:
2155 adev->mode_info.num_crtc = 4;
2156 adev->mode_info.num_hpd = 4;
2157 adev->mode_info.num_dig = 4;
3be5262e 2158 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 2159 break;
2160#endif
4562236b 2161 default:
e63f8673 2162 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 2163 return -EINVAL;
2164 }
2165
c8dd5715
MD		 2166 amdgpu_dm_set_irq_funcs(adev);
2167
39cc5be2
AD		 2168 if (adev->mode_info.funcs == NULL)
2169 adev->mode_info.funcs = &dm_display_funcs;
2170
1f6010a9
DF		 2171 /*
2172 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 2173 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 2174 * amdgpu_device_init()
2175 */
4562236b
HW		 2176#if defined(CONFIG_DEBUG_KERNEL_DC)
2177 device_create_file(
2178 adev->ddev->dev,
2179 &dev_attr_s3_debug);
2180#endif
2181
2182 return 0;
2183}
2184
9b690ef3 2185static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 2186 struct dc_stream_state *new_stream,
2187 struct dc_stream_state *old_stream)
9b690ef3 2188{
e7b07cee
HW		 2189 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2190 return false;
2191
2192 if (!crtc_state->enable)
2193 return false;
2194
2195 return crtc_state->active;
2196}
2197
2198static bool modereset_required(struct drm_crtc_state *crtc_state)
2199{
2200 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2201 return false;
2202
2203 return !crtc_state->enable || !crtc_state->active;
2204}
2205
7578ecda 2206static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 2207{
2208 drm_encoder_cleanup(encoder);
2209 kfree(encoder);
2210}
2211
2212static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2213 .destroy = amdgpu_dm_encoder_destroy,
2214};
2215
3ee6b26b
AD		 2216static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
2217 struct dc_plane_state *plane_state)
e7b07cee 2218{
3be5262e
HW		 2219 plane_state->src_rect.x = state->src_x >> 16;
2220 plane_state->src_rect.y = state->src_y >> 16;
1f6010a9 2221 /* we ignore the mantissa for now and do not deal with floating pixels :( */
3be5262e 2222 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 2223
3be5262e 2224 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 2225 return false;
2226
3be5262e
HW		 2227 plane_state->src_rect.height = state->src_h >> 16;
2228 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 2229 return false;
2230
3be5262e
HW		 2231 plane_state->dst_rect.x = state->crtc_x;
2232 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 2233
2234 if (state->crtc_w == 0)
2235 return false;
2236
3be5262e 2237 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 2238
2239 if (state->crtc_h == 0)
2240 return false;
2241
3be5262e 2242 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 2243
3be5262e 2244 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 2245
2246 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
2247 case DRM_MODE_ROTATE_0:
3be5262e 2248 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2249 break;
2250 case DRM_MODE_ROTATE_90:
3be5262e 2251 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 2252 break;
2253 case DRM_MODE_ROTATE_180:
3be5262e 2254 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 2255 break;
2256 case DRM_MODE_ROTATE_270:
3be5262e 2257 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 2258 break;
2259 default:
3be5262e 2260 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2261 break;
2262 }
2263
4562236b
HW		 2264 return true;
2265}
3ee6b26b 2266static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 2267 uint64_t *tiling_flags)
e7b07cee 2268{
e68d14dd 2269 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 2270 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 2271
e7b07cee 2272 if (unlikely(r)) {
1f6010a9 2273 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 2274 if (r != -ERESTARTSYS)
2275 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 2276 return r;
2277 }
2278
e7b07cee
HW		 2279 if (tiling_flags)
2280 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2281
2282 amdgpu_bo_unreserve(rbo);
2283
2284 return r;
2285}
2286
7df7e505
NK		 2287static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2288{
2289 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2290
2291 return offset ? (address + offset * 256) : 0;
2292}
2293
2294static bool fill_plane_dcc_attributes(struct amdgpu_device *adev,
2295 const struct amdgpu_framebuffer *afb,
2296 struct dc_plane_state *plane_state,
2297 uint64_t info)
2298{
2299 struct dc *dc = adev->dm.dc;
2300 struct dc_dcc_surface_param input = {0};
2301 struct dc_surface_dcc_cap output = {0};
2302 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2303 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2304 uint64_t dcc_address;
2305
2306 if (!offset)
2307 return false;
2308
2309 if (!dc->cap_funcs.get_dcc_compression_cap)
2310 return false;
2311
2312 input.format = plane_state->format;
2313 input.surface_size.width =
2314 plane_state->plane_size.grph.surface_size.width;
2315 input.surface_size.height =
2316 plane_state->plane_size.grph.surface_size.height;
2317 input.swizzle_mode = plane_state->tiling_info.gfx9.swizzle;
2318
2319 if (plane_state->rotation == ROTATION_ANGLE_0 ||
2320 plane_state->rotation == ROTATION_ANGLE_180)
2321 input.scan = SCAN_DIRECTION_HORIZONTAL;
2322 else if (plane_state->rotation == ROTATION_ANGLE_90 ||
2323 plane_state->rotation == ROTATION_ANGLE_270)
2324 input.scan = SCAN_DIRECTION_VERTICAL;
2325
2326 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2327 return false;
2328
2329 if (!output.capable)
2330 return false;
2331
2332 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2333 return false;
2334
2335 plane_state->dcc.enable = 1;
2336 plane_state->dcc.grph.meta_pitch =
2337 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2338 plane_state->dcc.grph.independent_64b_blks = i64b;
2339
2340 dcc_address = get_dcc_address(afb->address, info);
2341 plane_state->address.grph.meta_addr.low_part =
2342 lower_32_bits(dcc_address);
2343 plane_state->address.grph.meta_addr.high_part =
2344 upper_32_bits(dcc_address);
2345
2346 return true;
2347}
2348
3ee6b26b
AD		 2349static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
2350 struct dc_plane_state *plane_state,
9817d5f5 2351 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 2352{
2353 uint64_t tiling_flags;
e7b07cee
HW		 2354 unsigned int awidth;
2355 const struct drm_framebuffer *fb = &amdgpu_fb->base;
2356 int ret = 0;
2357 struct drm_format_name_buf format_name;
2358
2359 ret = get_fb_info(
2360 amdgpu_fb,
9817d5f5 2361 &tiling_flags);
e7b07cee
HW		 2362
2363 if (ret)
2364 return ret;
2365
2366 switch (fb->format->format) {
2367 case DRM_FORMAT_C8:
3be5262e 2368 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 2369 break;
2370 case DRM_FORMAT_RGB565:
3be5262e 2371 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 2372 break;
2373 case DRM_FORMAT_XRGB8888:
2374 case DRM_FORMAT_ARGB8888:
3be5262e 2375 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 2376 break;
2377 case DRM_FORMAT_XRGB2101010:
2378 case DRM_FORMAT_ARGB2101010:
3be5262e 2379 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 2380 break;
2381 case DRM_FORMAT_XBGR2101010:
2382 case DRM_FORMAT_ABGR2101010:
3be5262e 2383 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee 2384 break;
bcd47f60
MR		 2385 case DRM_FORMAT_XBGR8888:
2386 case DRM_FORMAT_ABGR8888:
2387 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2388 break;
e7b07cee 2389 case DRM_FORMAT_NV21:
3be5262e 2390 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 2391 break;
2392 case DRM_FORMAT_NV12:
3be5262e 2393 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 2394 break;
2395 default:
2396 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 2397 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 2398 return -EINVAL;
2399 }
2400
7df7e505
NK		 2401 memset(&plane_state->address, 0, sizeof(plane_state->address));
2402 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
2403 memset(&plane_state->dcc, 0, sizeof(plane_state->dcc));
2404
3be5262e
HW		 2405 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2406 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 2407 plane_state->plane_size.grph.surface_size.x = 0;
2408 plane_state->plane_size.grph.surface_size.y = 0;
2409 plane_state->plane_size.grph.surface_size.width = fb->width;
2410 plane_state->plane_size.grph.surface_size.height = fb->height;
2411 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 2412 fb->pitches[0] / fb->format->cpp[0];
2413 /* TODO: unhardcode */
3be5262e 2414 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 2415
2416 } else {
2417 awidth = ALIGN(fb->width, 64);
3be5262e 2418 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 2419 plane_state->plane_size.video.luma_size.x = 0;
2420 plane_state->plane_size.video.luma_size.y = 0;
2421 plane_state->plane_size.video.luma_size.width = awidth;
2422 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 2423 /* TODO: unhardcode */
3be5262e 2424 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 2425
3be5262e
HW		 2426 plane_state->plane_size.video.chroma_size.x = 0;
2427 plane_state->plane_size.video.chroma_size.y = 0;
2428 plane_state->plane_size.video.chroma_size.width = awidth;
2429 plane_state->plane_size.video.chroma_size.height = fb->height;
2430 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 2431
2432 /* TODO: unhardcode */
3be5262e 2433 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 2434 }
2435
b830ebc9
HW		 2436 /* Fill GFX8 params */
2437 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2438 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 2439
2440 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2441 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2442 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2443 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2444 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2445
2446 /* XXX fix me for VI */
3be5262e
HW		 2447 plane_state->tiling_info.gfx8.num_banks = num_banks;
2448 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 2449 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 2450 plane_state->tiling_info.gfx8.tile_split = tile_split;
2451 plane_state->tiling_info.gfx8.bank_width = bankw;
2452 plane_state->tiling_info.gfx8.bank_height = bankh;
2453 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2454 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 2455 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2456 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2457 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 2458 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 2459 }
2460
3be5262e 2461 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 2462 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2463
2464 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 2465 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 2466 adev->asic_type == CHIP_VEGA20 ||
e7b07cee
HW		 2467 adev->asic_type == CHIP_RAVEN) {
2468 /* Fill GFX9 params */
3be5262e 2469 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 2470 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 2471 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 2472 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 2473 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 2474 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 2475 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 2476 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 2477 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 2478 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 2479 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 2480 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 2481 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 2482 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 2483 plane_state->tiling_info.gfx9.shaderEnable = 1;
7df7e505
NK		 2484
2485 fill_plane_dcc_attributes(adev, amdgpu_fb, plane_state,
2486 tiling_flags);
e7b07cee
HW		 2487 }
2488
3be5262e
HW		 2489 plane_state->visible = true;
2490 plane_state->scaling_quality.h_taps_c = 0;
2491 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 2492
3be5262e
HW		 2493 /* is this needed? is plane_state zeroed at allocation? */
2494 plane_state->scaling_quality.h_taps = 0;
2495 plane_state->scaling_quality.v_taps = 0;
2496 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 2497
2498 return ret;
2499
2500}
2501
3ee6b26b
AD		 2502static int fill_plane_attributes(struct amdgpu_device *adev,
2503 struct dc_plane_state *dc_plane_state,
2504 struct drm_plane_state *plane_state,
9817d5f5 2505 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2506{
2507 const struct amdgpu_framebuffer *amdgpu_fb =
2508 to_amdgpu_framebuffer(plane_state->fb);
2509 const struct drm_crtc *crtc = plane_state->crtc;
e7b07cee
HW		 2510 int ret = 0;
2511
3be5262e 2512 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 2513 return -EINVAL;
2514
2515 ret = fill_plane_attributes_from_fb(
2516 crtc->dev->dev_private,
3be5262e 2517 dc_plane_state,
9817d5f5 2518 amdgpu_fb);
e7b07cee
HW		 2519
2520 if (ret)
2521 return ret;
2522
e277adc5
LSL		 2523 /*
2524 * Always set input transfer function, since plane state is refreshed
2525 * every time.
2526 */
2527 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2528 if (ret) {
2529 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2530 dc_plane_state->in_transfer_func = NULL;
2531 }
e7b07cee
HW		 2532
2533 return ret;
2534}
2535
3ee6b26b
AD		 2536static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2537 const struct dm_connector_state *dm_state,
2538 struct dc_stream_state *stream)
e7b07cee
HW		 2539{
2540 enum amdgpu_rmx_type rmx_type;
2541
2542 struct rect src = { 0 }; /* viewport in composition space*/
2543 struct rect dst = { 0 }; /* stream addressable area */
2544
2545 /* no mode. nothing to be done */
2546 if (!mode)
2547 return;
2548
2549 /* Full screen scaling by default */
2550 src.width = mode->hdisplay;
2551 src.height = mode->vdisplay;
2552 dst.width = stream->timing.h_addressable;
2553 dst.height = stream->timing.v_addressable;
2554
f4791779
HW		 2555 if (dm_state) {
2556 rmx_type = dm_state->scaling;
2557 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2558 if (src.width * dst.height <
2559 src.height * dst.width) {
2560 /* height needs less upscaling/more downscaling */
2561 dst.width = src.width *
2562 dst.height / src.height;
2563 } else {
2564 /* width needs less upscaling/more downscaling */
2565 dst.height = src.height *
2566 dst.width / src.width;
2567 }
2568 } else if (rmx_type == RMX_CENTER) {
2569 dst = src;
e7b07cee 2570 }
e7b07cee 2571
f4791779
HW		 2572 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2573 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2574
f4791779
HW		 2575 if (dm_state->underscan_enable) {
2576 dst.x += dm_state->underscan_hborder / 2;
2577 dst.y += dm_state->underscan_vborder / 2;
2578 dst.width -= dm_state->underscan_hborder;
2579 dst.height -= dm_state->underscan_vborder;
2580 }
e7b07cee
HW		 2581 }
2582
2583 stream->src = src;
2584 stream->dst = dst;
2585
f1ad2f5e 2586 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2587 dst.x, dst.y, dst.width, dst.height);
2588
2589}
2590
3ee6b26b
AD		 2591static enum dc_color_depth
2592convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee 2593{
07e3a1cf
NK		 2594 struct dm_connector_state *dm_conn_state =
2595 to_dm_connector_state(connector->state);
e7b07cee
HW		 2596 uint32_t bpc = connector->display_info.bpc;
2597
07e3a1cf
NK		 2598 /* TODO: Remove this when there's support for max_bpc in drm */
2599 if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2600 /* Round down to nearest even number. */
2601 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2602
e7b07cee
HW		 2603 switch (bpc) {
2604 case 0:
1f6010a9
DF		 2605 /*
2606 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 2607 * EDID revision before 1.4
2608 * TODO: Fix edid parsing
2609 */
2610 return COLOR_DEPTH_888;
2611 case 6:
2612 return COLOR_DEPTH_666;
2613 case 8:
2614 return COLOR_DEPTH_888;
2615 case 10:
2616 return COLOR_DEPTH_101010;
2617 case 12:
2618 return COLOR_DEPTH_121212;
2619 case 14:
2620 return COLOR_DEPTH_141414;
2621 case 16:
2622 return COLOR_DEPTH_161616;
2623 default:
2624 return COLOR_DEPTH_UNDEFINED;
2625 }
2626}
2627
3ee6b26b
AD		 2628static enum dc_aspect_ratio
2629get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 2630{
e11d4147
LSL		 2631 /* 1-1 mapping, since both enums follow the HDMI spec. */
2632 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 2633}
2634
3ee6b26b
AD		 2635static enum dc_color_space
2636get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2637{
2638 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2639
2640 switch (dc_crtc_timing->pixel_encoding) {
2641 case PIXEL_ENCODING_YCBCR422:
2642 case PIXEL_ENCODING_YCBCR444:
2643 case PIXEL_ENCODING_YCBCR420:
2644 {
2645 /*
2646 * 27030khz is the separation point between HDTV and SDTV
2647 * according to HDMI spec, we use YCbCr709 and YCbCr601
2648 * respectively
2649 */
380604e2 2650 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 2651 if (dc_crtc_timing->flags.Y_ONLY)
2652 color_space =
2653 COLOR_SPACE_YCBCR709_LIMITED;
2654 else
2655 color_space = COLOR_SPACE_YCBCR709;
2656 } else {
2657 if (dc_crtc_timing->flags.Y_ONLY)
2658 color_space =
2659 COLOR_SPACE_YCBCR601_LIMITED;
2660 else
2661 color_space = COLOR_SPACE_YCBCR601;
2662 }
2663
2664 }
2665 break;
2666 case PIXEL_ENCODING_RGB:
2667 color_space = COLOR_SPACE_SRGB;
2668 break;
2669
2670 default:
2671 WARN_ON(1);
2672 break;
2673 }
2674
2675 return color_space;
2676}
2677
400443e8
ML		 2678static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2679{
2680 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2681 return;
2682
2683 timing_out->display_color_depth--;
2684}
2685
2686static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2687 const struct drm_display_info *info)
2688{
2689 int normalized_clk;
2690 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2691 return;
2692 do {
380604e2 2693 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 2694 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2695 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2696 normalized_clk /= 2;
2697 /* Adjusting pix clock following on HDMI spec based on colour depth */
2698 switch (timing_out->display_color_depth) {
2699 case COLOR_DEPTH_101010:
2700 normalized_clk = (normalized_clk * 30) / 24;
2701 break;
2702 case COLOR_DEPTH_121212:
2703 normalized_clk = (normalized_clk * 36) / 24;
2704 break;
2705 case COLOR_DEPTH_161616:
2706 normalized_clk = (normalized_clk * 48) / 24;
2707 break;
2708 default:
2709 return;
2710 }
2711 if (normalized_clk <= info->max_tmds_clock)
2712 return;
2713 reduce_mode_colour_depth(timing_out);
2714
2715 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2716
2717}
e7b07cee 2718
3ee6b26b
AD		 2719static void
2720fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2721 const struct drm_display_mode *mode_in,
b333730d
BL		 2722 const struct drm_connector *connector,
2723 const struct dc_stream_state *old_stream)
e7b07cee
HW		 2724{
2725 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 2726 const struct drm_display_info *info = &connector->display_info;
b830ebc9 2727
e7b07cee
HW		 2728 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2729
2730 timing_out->h_border_left = 0;
2731 timing_out->h_border_right = 0;
2732 timing_out->v_border_top = 0;
2733 timing_out->v_border_bottom = 0;
2734 /* TODO: un-hardcode */
fe61a2f1 2735 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 2736 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1
ML		 2737 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2738 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
ceb3dbb4 2739 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 2740 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2741 else
2742 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2743
2744 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2745 timing_out->display_color_depth = convert_color_depth_from_display_info(
2746 connector);
2747 timing_out->scan_type = SCANNING_TYPE_NODATA;
2748 timing_out->hdmi_vic = 0;
b333730d
BL		 2749
2750 if(old_stream) {
2751 timing_out->vic = old_stream->timing.vic;
2752 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
2753 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
2754 } else {
2755 timing_out->vic = drm_match_cea_mode(mode_in);
2756 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2757 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2758 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2759 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2760 }
e7b07cee
HW		 2761
2762 timing_out->h_addressable = mode_in->crtc_hdisplay;
2763 timing_out->h_total = mode_in->crtc_htotal;
2764 timing_out->h_sync_width =
2765 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2766 timing_out->h_front_porch =
2767 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2768 timing_out->v_total = mode_in->crtc_vtotal;
2769 timing_out->v_addressable = mode_in->crtc_vdisplay;
2770 timing_out->v_front_porch =
2771 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2772 timing_out->v_sync_width =
2773 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
380604e2 2774 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
e7b07cee 2775 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 2776
2777 stream->output_color_space = get_output_color_space(timing_out);
2778
e43a432c
AK		 2779 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2780 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ceb3dbb4 2781 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
400443e8 2782 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 2783}
2784
3ee6b26b
AD		 2785static void fill_audio_info(struct audio_info *audio_info,
2786 const struct drm_connector *drm_connector,
2787 const struct dc_sink *dc_sink)
e7b07cee
HW		 2788{
2789 int i = 0;
2790 int cea_revision = 0;
2791 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2792
2793 audio_info->manufacture_id = edid_caps->manufacturer_id;
2794 audio_info->product_id = edid_caps->product_id;
2795
2796 cea_revision = drm_connector->display_info.cea_rev;
2797
090afc1e 2798 strscpy(audio_info->display_name,
d2b2562c 2799 edid_caps->display_name,
090afc1e 2800 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 2801
b830ebc9 2802 if (cea_revision >= 3) {
e7b07cee
HW		 2803 audio_info->mode_count = edid_caps->audio_mode_count;
2804
2805 for (i = 0; i < audio_info->mode_count; ++i) {
2806 audio_info->modes[i].format_code =
2807 (enum audio_format_code)
2808 (edid_caps->audio_modes[i].format_code);
2809 audio_info->modes[i].channel_count =
2810 edid_caps->audio_modes[i].channel_count;
2811 audio_info->modes[i].sample_rates.all =
2812 edid_caps->audio_modes[i].sample_rate;
2813 audio_info->modes[i].sample_size =
2814 edid_caps->audio_modes[i].sample_size;
2815 }
2816 }
2817
2818 audio_info->flags.all = edid_caps->speaker_flags;
2819
2820 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2821 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2822 audio_info->video_latency = drm_connector->video_latency[0];
2823 audio_info->audio_latency = drm_connector->audio_latency[0];
2824 }
2825
2826 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2827
2828}
2829
3ee6b26b
AD		 2830static void
2831copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2832 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2833{
2834 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2835 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2836 dst_mode->crtc_clock = src_mode->crtc_clock;
2837 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2838 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2839 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2840 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2841 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2842 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2843 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2844 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2845 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2846 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2847 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2848}
2849
3ee6b26b
AD		 2850static void
2851decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2852 const struct drm_display_mode *native_mode,
2853 bool scale_enabled)
e7b07cee
HW		 2854{
2855 if (scale_enabled) {
2856 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2857 } else if (native_mode->clock == drm_mode->clock &&
2858 native_mode->htotal == drm_mode->htotal &&
2859 native_mode->vtotal == drm_mode->vtotal) {
2860 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2861 } else {
2862 /* no scaling nor amdgpu inserted, no need to patch */
2863 }
2864}
2865
aed15309
ML		 2866static struct dc_sink *
2867create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 2868{
2e0ac3d6 2869 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 2870 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 2871 sink_init_data.link = aconnector->dc_link;
2872 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2873
2874 sink = dc_sink_create(&sink_init_data);
423788c7 2875 if (!sink) {
2e0ac3d6 2876 DRM_ERROR("Failed to create sink!\n");
aed15309 2877 return NULL;
423788c7 2878 }
2e0ac3d6 2879 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 2880
aed15309 2881 return sink;
2e0ac3d6
HW		 2882}
2883
fa2123db
ML		 2884static void set_multisync_trigger_params(
2885 struct dc_stream_state *stream)
2886{
2887 if (stream->triggered_crtc_reset.enabled) {
2888 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2889 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2890 }
2891}
2892
2893static void set_master_stream(struct dc_stream_state *stream_set[],
2894 int stream_count)
2895{
2896 int j, highest_rfr = 0, master_stream = 0;
2897
2898 for (j = 0; j < stream_count; j++) {
2899 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2900 int refresh_rate = 0;
2901
380604e2 2902 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 2903 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2904 if (refresh_rate > highest_rfr) {
2905 highest_rfr = refresh_rate;
2906 master_stream = j;
2907 }
2908 }
2909 }
2910 for (j = 0; j < stream_count; j++) {
03736f4c 2911 if (stream_set[j])
fa2123db
ML		 2912 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2913 }
2914}
2915
2916static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2917{
2918 int i = 0;
2919
2920 if (context->stream_count < 2)
2921 return;
2922 for (i = 0; i < context->stream_count ; i++) {
2923 if (!context->streams[i])
2924 continue;
1f6010a9
DF		 2925 /*
2926 * TODO: add a function to read AMD VSDB bits and set
fa2123db 2927 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 2928 * For now it's set to false
fa2123db
ML		 2929 */
2930 set_multisync_trigger_params(context->streams[i]);
2931 }
2932 set_master_stream(context->streams, context->stream_count);
2933}
2934
3ee6b26b
AD		 2935static struct dc_stream_state *
2936create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2937 const struct drm_display_mode *drm_mode,
b333730d
BL		 2938 const struct dm_connector_state *dm_state,
2939 const struct dc_stream_state *old_stream)
e7b07cee
HW		 2940{
2941 struct drm_display_mode *preferred_mode = NULL;
391ef035 2942 struct drm_connector *drm_connector;
0971c40e 2943 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2944 struct drm_display_mode mode = *drm_mode;
2945 bool native_mode_found = false;
b333730d
BL		 2946 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
2947 int mode_refresh;
58124bf8 2948 int preferred_refresh = 0;
b333730d 2949
aed15309 2950 struct dc_sink *sink = NULL;
b830ebc9 2951 if (aconnector == NULL) {
e7b07cee 2952 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2953 return stream;
e7b07cee
HW		 2954 }
2955
e7b07cee 2956 drm_connector = &aconnector->base;
2e0ac3d6 2957
f4ac176e 2958 if (!aconnector->dc_sink) {
8be17ac9
JFZ		 2959 if (!aconnector->mst_port) {
2960 sink = create_fake_sink(aconnector);
2961 if (!sink)
2962 return stream;
391ef035 2963 }
aed15309
ML		 2964 } else {
2965 sink = aconnector->dc_sink;
f4ac176e 2966 }
2e0ac3d6 2967
aed15309 2968 stream = dc_create_stream_for_sink(sink);
4562236b 2969
b830ebc9 2970 if (stream == NULL) {
e7b07cee 2971 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 2972 goto finish;
e7b07cee
HW		 2973 }
2974
ceb3dbb4
JL		 2975 stream->dm_stream_context = aconnector;
2976
e7b07cee
HW		 2977 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2978 /* Search for preferred mode */
2979 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2980 native_mode_found = true;
2981 break;
2982 }
2983 }
2984 if (!native_mode_found)
2985 preferred_mode = list_first_entry_or_null(
2986 &aconnector->base.modes,
2987 struct drm_display_mode,
2988 head);
2989
b333730d
BL		 2990 mode_refresh = drm_mode_vrefresh(&mode);
2991
b830ebc9 2992 if (preferred_mode == NULL) {
1f6010a9
DF		 2993 /*
2994 * This may not be an error, the use case is when we have no
e7b07cee
HW		 2995 * usermode calls to reset and set mode upon hotplug. In this
2996 * case, we call set mode ourselves to restore the previous mode
2997 * and the modelist may not be filled in in time.
2998 */
f1ad2f5e 2999 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 3000 } else {
3001 decide_crtc_timing_for_drm_display_mode(
3002 &mode, preferred_mode,
f4791779 3003 dm_state ? (dm_state->scaling != RMX_OFF) : false);
58124bf8 3004 preferred_refresh = drm_mode_vrefresh(preferred_mode);
e7b07cee
HW		 3005 }
3006
f783577c
JFZ		 3007 if (!dm_state)
3008 drm_mode_set_crtcinfo(&mode, 0);
3009
b333730d
BL		 3010 /*
3011 * If scaling is enabled and refresh rate didn't change
3012 * we copy the vic and polarities of the old timings
3013 */
3014 if (!scale || mode_refresh != preferred_refresh)
3015 fill_stream_properties_from_drm_display_mode(stream,
3016 &mode, &aconnector->base, NULL);
3017 else
3018 fill_stream_properties_from_drm_display_mode(stream,
3019 &mode, &aconnector->base, old_stream);
3020
e7b07cee
HW		 3021 update_stream_scaling_settings(&mode, dm_state, stream);
3022
3023 fill_audio_info(
3024 &stream->audio_info,
3025 drm_connector,
aed15309 3026 sink);
e7b07cee 3027
ceb3dbb4 3028 update_stream_signal(stream, sink);
9182b4cb 3029
9e3efe3e
HW		 3030 if (dm_state && dm_state->freesync_capable)
3031 stream->ignore_msa_timing_param = true;
ecd0136b 3032
aed15309 3033finish:
fbbdadf2 3034 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON)
aed15309 3035 dc_sink_release(sink);
9e3efe3e 3036
e7b07cee
HW		 3037 return stream;
3038}
3039
7578ecda 3040static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 3041{
3042 drm_crtc_cleanup(crtc);
3043 kfree(crtc);
3044}
3045
3046static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 3047 struct drm_crtc_state *state)
e7b07cee
HW		 3048{
3049 struct dm_crtc_state *cur = to_dm_crtc_state(state);
3050
3051 /* TODO Destroy dc_stream objects are stream object is flattened */
3052 if (cur->stream)
3053 dc_stream_release(cur->stream);
3054
3055
3056 __drm_atomic_helper_crtc_destroy_state(state);
3057
3058
3059 kfree(state);
3060}
3061
3062static void dm_crtc_reset_state(struct drm_crtc *crtc)
3063{
3064 struct dm_crtc_state *state;
3065
3066 if (crtc->state)
3067 dm_crtc_destroy_state(crtc, crtc->state);
3068
3069 state = kzalloc(sizeof(*state), GFP_KERNEL);
3070 if (WARN_ON(!state))
3071 return;
3072
3073 crtc->state = &state->base;
3074 crtc->state->crtc = crtc;
3075
3076}
3077
3078static struct drm_crtc_state *
3079dm_crtc_duplicate_state(struct drm_crtc *crtc)
3080{
3081 struct dm_crtc_state *state, *cur;
3082
3083 cur = to_dm_crtc_state(crtc->state);
3084
3085 if (WARN_ON(!crtc->state))
3086 return NULL;
3087
2004f45e 3088 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 3089 if (!state)
3090 return NULL;
e7b07cee
HW		 3091
3092 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3093
3094 if (cur->stream) {
3095 state->stream = cur->stream;
3096 dc_stream_retain(state->stream);
3097 }
3098
180db303 3099 state->vrr_params = cur->vrr_params;
98e6436d 3100 state->vrr_infopacket = cur->vrr_infopacket;
c1ee92f9 3101 state->abm_level = cur->abm_level;
bb47de73
NK		 3102 state->vrr_supported = cur->vrr_supported;
3103 state->freesync_config = cur->freesync_config;
ed20dc0d 3104 state->crc_enabled = cur->crc_enabled;
98e6436d 3105
e7b07cee
HW		 3106 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3107
3108 return &state->base;
3109}
3110
589d2739
HW		 3111
3112static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3113{
3114 enum dc_irq_source irq_source;
3115 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3116 struct amdgpu_device *adev = crtc->dev->dev_private;
3117
3118 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 3119 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 3120}
3121
3122static int dm_enable_vblank(struct drm_crtc *crtc)
3123{
3124 return dm_set_vblank(crtc, true);
3125}
3126
3127static void dm_disable_vblank(struct drm_crtc *crtc)
3128{
3129 dm_set_vblank(crtc, false);
3130}
3131
e7b07cee
HW		 3132/* Implemented only the options currently availible for the driver */
3133static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3134 .reset = dm_crtc_reset_state,
3135 .destroy = amdgpu_dm_crtc_destroy,
3136 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3137 .set_config = drm_atomic_helper_set_config,
3138 .page_flip = drm_atomic_helper_page_flip,
3139 .atomic_duplicate_state = dm_crtc_duplicate_state,
3140 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 3141 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 3142 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
589d2739
HW		 3143 .enable_vblank = dm_enable_vblank,
3144 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 3145};
3146
3147static enum drm_connector_status
3148amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3149{
3150 bool connected;
c84dec2f 3151 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 3152
1f6010a9
DF		 3153 /*
3154 * Notes:
e7b07cee
HW		 3155 * 1. This interface is NOT called in context of HPD irq.
3156 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 3157 * makes it a bad place for *any* MST-related activity.
3158 */
e7b07cee 3159
8580d60b
HW		 3160 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3161 !aconnector->fake_enable)
e7b07cee
HW		 3162 connected = (aconnector->dc_sink != NULL);
3163 else
3164 connected = (aconnector->base.force == DRM_FORCE_ON);
3165
3166 return (connected ? connector_status_connected :
3167 connector_status_disconnected);
3168}
3169
3ee6b26b
AD		 3170int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3171 struct drm_connector_state *connector_state,
3172 struct drm_property *property,
3173 uint64_t val)
e7b07cee
HW		 3174{
3175 struct drm_device *dev = connector->dev;
3176 struct amdgpu_device *adev = dev->dev_private;
3177 struct dm_connector_state *dm_old_state =
3178 to_dm_connector_state(connector->state);
3179 struct dm_connector_state *dm_new_state =
3180 to_dm_connector_state(connector_state);
3181
3182 int ret = -EINVAL;
3183
3184 if (property == dev->mode_config.scaling_mode_property) {
3185 enum amdgpu_rmx_type rmx_type;
3186
3187 switch (val) {
3188 case DRM_MODE_SCALE_CENTER:
3189 rmx_type = RMX_CENTER;
3190 break;
3191 case DRM_MODE_SCALE_ASPECT:
3192 rmx_type = RMX_ASPECT;
3193 break;
3194 case DRM_MODE_SCALE_FULLSCREEN:
3195 rmx_type = RMX_FULL;
3196 break;
3197 case DRM_MODE_SCALE_NONE:
3198 default:
3199 rmx_type = RMX_OFF;
3200 break;
3201 }
3202
3203 if (dm_old_state->scaling == rmx_type)
3204 return 0;
3205
3206 dm_new_state->scaling = rmx_type;
3207 ret = 0;
3208 } else if (property == adev->mode_info.underscan_hborder_property) {
3209 dm_new_state->underscan_hborder = val;
3210 ret = 0;
3211 } else if (property == adev->mode_info.underscan_vborder_property) {
3212 dm_new_state->underscan_vborder = val;
3213 ret = 0;
3214 } else if (property == adev->mode_info.underscan_property) {
3215 dm_new_state->underscan_enable = val;
3216 ret = 0;
07e3a1cf
NK		 3217 } else if (property == adev->mode_info.max_bpc_property) {
3218 dm_new_state->max_bpc = val;
3219 ret = 0;
c1ee92f9
DF		 3220 } else if (property == adev->mode_info.abm_level_property) {
3221 dm_new_state->abm_level = val;
3222 ret = 0;
e7b07cee
HW		 3223 }
3224
3225 return ret;
3226}
3227
3ee6b26b
AD		 3228int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3229 const struct drm_connector_state *state,
3230 struct drm_property *property,
3231 uint64_t *val)
e7b07cee
HW		 3232{
3233 struct drm_device *dev = connector->dev;
3234 struct amdgpu_device *adev = dev->dev_private;
3235 struct dm_connector_state *dm_state =
3236 to_dm_connector_state(state);
3237 int ret = -EINVAL;
3238
3239 if (property == dev->mode_config.scaling_mode_property) {
3240 switch (dm_state->scaling) {
3241 case RMX_CENTER:
3242 *val = DRM_MODE_SCALE_CENTER;
3243 break;
3244 case RMX_ASPECT:
3245 *val = DRM_MODE_SCALE_ASPECT;
3246 break;
3247 case RMX_FULL:
3248 *val = DRM_MODE_SCALE_FULLSCREEN;
3249 break;
3250 case RMX_OFF:
3251 default:
3252 *val = DRM_MODE_SCALE_NONE;
3253 break;
3254 }
3255 ret = 0;
3256 } else if (property == adev->mode_info.underscan_hborder_property) {
3257 *val = dm_state->underscan_hborder;
3258 ret = 0;
3259 } else if (property == adev->mode_info.underscan_vborder_property) {
3260 *val = dm_state->underscan_vborder;
3261 ret = 0;
3262 } else if (property == adev->mode_info.underscan_property) {
3263 *val = dm_state->underscan_enable;
3264 ret = 0;
07e3a1cf
NK		 3265 } else if (property == adev->mode_info.max_bpc_property) {
3266 *val = dm_state->max_bpc;
3267 ret = 0;
c1ee92f9
DF		 3268 } else if (property == adev->mode_info.abm_level_property) {
3269 *val = dm_state->abm_level;
3270 ret = 0;
e7b07cee 3271 }
c1ee92f9 3272
e7b07cee
HW		 3273 return ret;
3274}
3275
7578ecda 3276static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 3277{
c84dec2f 3278 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3279 const struct dc_link *link = aconnector->dc_link;
3280 struct amdgpu_device *adev = connector->dev->dev_private;
3281 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 3282
e7b07cee
HW		 3283#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3284 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3285
89fc8d4e 3286 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 3287 link->type != dc_connection_none &&
3288 dm->backlight_dev) {
3289 backlight_device_unregister(dm->backlight_dev);
3290 dm->backlight_dev = NULL;
e7b07cee
HW		 3291 }
3292#endif
e86e8947 3293 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 3294 drm_connector_unregister(connector);
3295 drm_connector_cleanup(connector);
3296 kfree(connector);
3297}
3298
3299void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3300{
3301 struct dm_connector_state *state =
3302 to_dm_connector_state(connector->state);
3303
df099b9b
LSL		 3304 if (connector->state)
3305 __drm_atomic_helper_connector_destroy_state(connector->state);
3306
e7b07cee
HW		 3307 kfree(state);
3308
3309 state = kzalloc(sizeof(*state), GFP_KERNEL);
3310
3311 if (state) {
3312 state->scaling = RMX_OFF;
3313 state->underscan_enable = false;
3314 state->underscan_hborder = 0;
3315 state->underscan_vborder = 0;
49f1c44b 3316 state->max_bpc = 8;
e7b07cee 3317
df099b9b 3318 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 3319 }
3320}
3321
3ee6b26b
AD		 3322struct drm_connector_state *
3323amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 3324{
3325 struct dm_connector_state *state =
3326 to_dm_connector_state(connector->state);
3327
3328 struct dm_connector_state *new_state =
3329 kmemdup(state, sizeof(*state), GFP_KERNEL);
3330
98e6436d
AK		 3331 if (!new_state)
3332 return NULL;
e7b07cee 3333
98e6436d
AK		 3334 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3335
3336 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 3337 new_state->abm_level = state->abm_level;
922454c2
NK		 3338 new_state->scaling = state->scaling;
3339 new_state->underscan_enable = state->underscan_enable;
3340 new_state->underscan_hborder = state->underscan_hborder;
3341 new_state->underscan_vborder = state->underscan_vborder;
49f1c44b 3342 new_state->max_bpc = state->max_bpc;
98e6436d
AK		 3343
3344 return &new_state->base;
e7b07cee
HW		 3345}
3346
3347static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3348 .reset = amdgpu_dm_connector_funcs_reset,
3349 .detect = amdgpu_dm_connector_detect,
3350 .fill_modes = drm_helper_probe_single_connector_modes,
3351 .destroy = amdgpu_dm_connector_destroy,
3352 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3353 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3354 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3355 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3356};
3357
e7b07cee
HW		 3358static int get_modes(struct drm_connector *connector)
3359{
3360 return amdgpu_dm_connector_get_modes(connector);
3361}
3362
c84dec2f 3363static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3364{
3365 struct dc_sink_init_data init_params = {
3366 .link = aconnector->dc_link,
3367 .sink_signal = SIGNAL_TYPE_VIRTUAL
3368 };
70e8ffc5 3369 struct edid *edid;
e7b07cee 3370
a89ff457 3371 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 3372 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3373 aconnector->base.name);
3374
3375 aconnector->base.force = DRM_FORCE_OFF;
3376 aconnector->base.override_edid = false;
3377 return;
3378 }
3379
70e8ffc5
HW		 3380 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3381
e7b07cee
HW		 3382 aconnector->edid = edid;
3383
3384 aconnector->dc_em_sink = dc_link_add_remote_sink(
3385 aconnector->dc_link,
3386 (uint8_t *)edid,
3387 (edid->extensions + 1) * EDID_LENGTH,
3388 &init_params);
3389
a68d90e7 3390 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 3391 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3392 aconnector->dc_link->local_sink :
3393 aconnector->dc_em_sink;
3394}
3395
c84dec2f 3396static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3397{
3398 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3399
1f6010a9
DF		 3400 /*
3401 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 3402 * Those settings have to be != 0 to get initial modeset
3403 */
3404 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3405 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3406 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3407 }
3408
3409
3410 aconnector->base.override_edid = true;
3411 create_eml_sink(aconnector);
3412}
3413
ba9ca088 3414enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 3415 struct drm_display_mode *mode)
e7b07cee
HW		 3416{
3417 int result = MODE_ERROR;
3418 struct dc_sink *dc_sink;
3419 struct amdgpu_device *adev = connector->dev->dev_private;
3420 /* TODO: Unhardcode stream count */
0971c40e 3421 struct dc_stream_state *stream;
c84dec2f 3422 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 3423 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 3424
3425 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3426 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3427 return result;
3428
1f6010a9
DF		 3429 /*
3430 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 3431 * EDID mgmt
3432 */
3433 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3434 !aconnector->dc_em_sink)
3435 handle_edid_mgmt(aconnector);
3436
c84dec2f 3437 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 3438
b830ebc9 3439 if (dc_sink == NULL) {
e7b07cee
HW		 3440 DRM_ERROR("dc_sink is NULL!\n");
3441 goto fail;
3442 }
3443
b333730d 3444 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
b830ebc9 3445 if (stream == NULL) {
e7b07cee
HW		 3446 DRM_ERROR("Failed to create stream for sink!\n");
3447 goto fail;
3448 }
3449
a39438f0
HW		 3450 dc_result = dc_validate_stream(adev->dm.dc, stream);
3451
3452 if (dc_result == DC_OK)
e7b07cee 3453 result = MODE_OK;
a39438f0 3454 else
9f921b14 3455 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 3456 mode->vdisplay,
3457 mode->hdisplay,
9f921b14
HW		 3458 mode->clock,
3459 dc_result);
e7b07cee
HW		 3460
3461 dc_stream_release(stream);
3462
3463fail:
3464 /* TODO: error handling*/
3465 return result;
3466}
3467
3468static const struct drm_connector_helper_funcs
3469amdgpu_dm_connector_helper_funcs = {
3470 /*
1f6010a9 3471 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 3472 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 3473 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 3474 * in get_modes call back, not just return the modes count
3475 */
e7b07cee
HW		 3476 .get_modes = get_modes,
3477 .mode_valid = amdgpu_dm_connector_mode_valid,
e7b07cee
HW		 3478};
3479
3480static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3481{
3482}
3483
3ee6b26b
AD		 3484static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3485 struct drm_crtc_state *state)
e7b07cee
HW		 3486{
3487 struct amdgpu_device *adev = crtc->dev->dev_private;
3488 struct dc *dc = adev->dm.dc;
3489 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3490 int ret = -EINVAL;
3491
9b690ef3
BL		 3492 if (unlikely(!dm_crtc_state->stream &&
3493 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 3494 WARN_ON(1);
3495 return ret;
3496 }
3497
1f6010a9 3498 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 3499 if (!dm_crtc_state->stream)
3500 return 0;
3501
62c933f9 3502 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 3503 return 0;
3504
3505 return ret;
3506}
3507
3ee6b26b
AD		 3508static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3509 const struct drm_display_mode *mode,
3510 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 3511{
3512 return true;
3513}
3514
3515static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3516 .disable = dm_crtc_helper_disable,
3517 .atomic_check = dm_crtc_helper_atomic_check,
3518 .mode_fixup = dm_crtc_helper_mode_fixup
3519};
3520
3521static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3522{
3523
3524}
3525
3ee6b26b
AD		 3526static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3527 struct drm_crtc_state *crtc_state,
3528 struct drm_connector_state *conn_state)
e7b07cee
HW		 3529{
3530 return 0;
3531}
3532
3533const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3534 .disable = dm_encoder_helper_disable,
3535 .atomic_check = dm_encoder_helper_atomic_check
3536};
3537
3538static void dm_drm_plane_reset(struct drm_plane *plane)
3539{
3540 struct dm_plane_state *amdgpu_state = NULL;
3541
3542 if (plane->state)
3543 plane->funcs->atomic_destroy_state(plane, plane->state);
3544
3545 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 3546 WARN_ON(amdgpu_state == NULL);
1f6010a9 3547
e7b07cee
HW		 3548 if (amdgpu_state) {
3549 plane->state = &amdgpu_state->base;
3550 plane->state->plane = plane;
3551 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 3552 }
e7b07cee
HW		 3553}
3554
3555static struct drm_plane_state *
3556dm_drm_plane_duplicate_state(struct drm_plane *plane)
3557{
3558 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3559
3560 old_dm_plane_state = to_dm_plane_state(plane->state);
3561 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3562 if (!dm_plane_state)
3563 return NULL;
3564
3565 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3566
3be5262e
HW		 3567 if (old_dm_plane_state->dc_state) {
3568 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3569 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 3570 }
3571
3572 return &dm_plane_state->base;
3573}
3574
3575void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 3576 struct drm_plane_state *state)
e7b07cee
HW		 3577{
3578 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3579
3be5262e
HW		 3580 if (dm_plane_state->dc_state)
3581 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 3582
0627bbd3 3583 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 3584}
3585
3586static const struct drm_plane_funcs dm_plane_funcs = {
3587 .update_plane = drm_atomic_helper_update_plane,
3588 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 3589 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 3590 .reset = dm_drm_plane_reset,
3591 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3592 .atomic_destroy_state = dm_drm_plane_destroy_state,
3593};
3594
3ee6b26b
AD		 3595static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3596 struct drm_plane_state *new_state)
e7b07cee
HW		 3597{
3598 struct amdgpu_framebuffer *afb;
3599 struct drm_gem_object *obj;
5d43be0c 3600 struct amdgpu_device *adev;
e7b07cee 3601 struct amdgpu_bo *rbo;
56087b31 3602 uint64_t chroma_addr = 0;
e7b07cee 3603 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
7df7e505 3604 uint64_t tiling_flags, dcc_address;
e7b07cee 3605 unsigned int awidth;
5d43be0c
CK		 3606 uint32_t domain;
3607 int r;
e7b07cee
HW		 3608
3609 dm_plane_state_old = to_dm_plane_state(plane->state);
3610 dm_plane_state_new = to_dm_plane_state(new_state);
3611
3612 if (!new_state->fb) {
f1ad2f5e 3613 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3614 return 0;
3615 }
3616
3617 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 3618 obj = new_state->fb->obj[0];
e7b07cee 3619 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3620 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3621 r = amdgpu_bo_reserve(rbo, false);
3622 if (unlikely(r != 0))
3623 return r;
3624
5d43be0c 3625 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 3626 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 3627 else
3628 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3629
7b7c6c81 3630 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 3631 if (unlikely(r != 0)) {
30b7c614
HW		 3632 if (r != -ERESTARTSYS)
3633 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
bb812f1e 3634 amdgpu_bo_unreserve(rbo);
e7b07cee
HW		 3635 return r;
3636 }
3637
bb812f1e
JZ		 3638 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3639 if (unlikely(r != 0)) {
3640 amdgpu_bo_unpin(rbo);
3641 amdgpu_bo_unreserve(rbo);
3642 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 3643 return r;
3644 }
7df7e505
NK		 3645
3646 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
3647
bb812f1e
JZ		 3648 amdgpu_bo_unreserve(rbo);
3649
7b7c6c81 3650 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 3651
3652 amdgpu_bo_ref(rbo);
3653
3be5262e
HW		 3654 if (dm_plane_state_new->dc_state &&
3655 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3656 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3657
3be5262e
HW		 3658 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3659 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3660 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
7df7e505
NK		 3661
3662 dcc_address =
3663 get_dcc_address(afb->address, tiling_flags);
3664 plane_state->address.grph.meta_addr.low_part =
3665 lower_32_bits(dcc_address);
3666 plane_state->address.grph.meta_addr.high_part =
3667 upper_32_bits(dcc_address);
e7b07cee
HW		 3668 } else {
3669 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3670 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3671 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3672 = lower_32_bits(afb->address);
56087b31
S		 3673 plane_state->address.video_progressive.luma_addr.high_part
3674 = upper_32_bits(afb->address);
35888630 3675 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3676 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3677 = lower_32_bits(chroma_addr);
3678 plane_state->address.video_progressive.chroma_addr.high_part
3679 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3680 }
3681 }
3682
e7b07cee
HW		 3683 return 0;
3684}
3685
3ee6b26b
AD		 3686static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3687 struct drm_plane_state *old_state)
e7b07cee
HW		 3688{
3689 struct amdgpu_bo *rbo;
e7b07cee
HW		 3690 int r;
3691
3692 if (!old_state->fb)
3693 return;
3694
e68d14dd 3695 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 3696 r = amdgpu_bo_reserve(rbo, false);
3697 if (unlikely(r)) {
3698 DRM_ERROR("failed to reserve rbo before unpin\n");
3699 return;
b830ebc9
HW		 3700 }
3701
3702 amdgpu_bo_unpin(rbo);
3703 amdgpu_bo_unreserve(rbo);
3704 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3705}
3706
7578ecda
AD		 3707static int dm_plane_atomic_check(struct drm_plane *plane,
3708 struct drm_plane_state *state)
cbd19488
AG		 3709{
3710 struct amdgpu_device *adev = plane->dev->dev_private;
3711 struct dc *dc = adev->dm.dc;
3712 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3713
3be5262e 3714 if (!dm_plane_state->dc_state)
9a3329b1 3715 return 0;
cbd19488 3716
a05bcff1
S		 3717 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3718 return -EINVAL;
3719
62c933f9 3720 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3721 return 0;
3722
3723 return -EINVAL;
3724}
3725
674e78ac
NK		 3726static int dm_plane_atomic_async_check(struct drm_plane *plane,
3727 struct drm_plane_state *new_plane_state)
3728{
77acd1cd
NK		 3729 struct drm_plane_state *old_plane_state =
3730 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
3731
674e78ac
NK		 3732 /* Only support async updates on cursor planes. */
3733 if (plane->type != DRM_PLANE_TYPE_CURSOR)
3734 return -EINVAL;
3735
77acd1cd
NK		 3736 /*
3737 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
3738 * async commits so don't allow fb changes.
3739 */
3740 if (old_plane_state->fb != new_plane_state->fb)
3741 return -EINVAL;
3742
674e78ac
NK		 3743 return 0;
3744}
3745
3746static void dm_plane_atomic_async_update(struct drm_plane *plane,
3747 struct drm_plane_state *new_state)
3748{
3749 struct drm_plane_state *old_state =
3750 drm_atomic_get_old_plane_state(new_state->state, plane);
3751
3752 if (plane->state->fb != new_state->fb)
3753 drm_atomic_set_fb_for_plane(plane->state, new_state->fb);
3754
3755 plane->state->src_x = new_state->src_x;
3756 plane->state->src_y = new_state->src_y;
3757 plane->state->src_w = new_state->src_w;
3758 plane->state->src_h = new_state->src_h;
3759 plane->state->crtc_x = new_state->crtc_x;
3760 plane->state->crtc_y = new_state->crtc_y;
3761 plane->state->crtc_w = new_state->crtc_w;
3762 plane->state->crtc_h = new_state->crtc_h;
3763
3764 handle_cursor_update(plane, old_state);
3765}
3766
e7b07cee
HW		 3767static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3768 .prepare_fb = dm_plane_helper_prepare_fb,
3769 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3770 .atomic_check = dm_plane_atomic_check,
674e78ac
NK		 3771 .atomic_async_check = dm_plane_atomic_async_check,
3772 .atomic_async_update = dm_plane_atomic_async_update
e7b07cee
HW		 3773};
3774
3775/*
3776 * TODO: these are currently initialized to rgb formats only.
3777 * For future use cases we should either initialize them dynamically based on
3778 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 3779 * check will succeed, and let DC implement proper check
e7b07cee 3780 */
d90371b0 3781static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3782 DRM_FORMAT_RGB888,
3783 DRM_FORMAT_XRGB8888,
3784 DRM_FORMAT_ARGB8888,
3785 DRM_FORMAT_RGBA8888,
3786 DRM_FORMAT_XRGB2101010,
3787 DRM_FORMAT_XBGR2101010,
3788 DRM_FORMAT_ARGB2101010,
3789 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 3790 DRM_FORMAT_XBGR8888,
3791 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 3792};
3793
99d1abf8 3794static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3795 DRM_FORMAT_NV12,
3796 DRM_FORMAT_NV21,
3797};
3798
3799static const u32 cursor_formats[] = {
3800 DRM_FORMAT_ARGB8888
3801};
3802
7578ecda 3803static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 3804 struct drm_plane *plane,
7578ecda 3805 unsigned long possible_crtcs)
e7b07cee
HW		 3806{
3807 int res = -EPERM;
3808
f180b4bc 3809 switch (plane->type) {
e7b07cee 3810 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3811 res = drm_universal_plane_init(
3812 dm->adev->ddev,
f180b4bc 3813 plane,
e7b07cee
HW		 3814 possible_crtcs,
3815 &dm_plane_funcs,
3816 rgb_formats,
3817 ARRAY_SIZE(rgb_formats),
f180b4bc 3818 NULL, plane->type, NULL);
e7b07cee
HW		 3819 break;
3820 case DRM_PLANE_TYPE_OVERLAY:
3821 res = drm_universal_plane_init(
3822 dm->adev->ddev,
f180b4bc 3823 plane,
e7b07cee
HW		 3824 possible_crtcs,
3825 &dm_plane_funcs,
3826 yuv_formats,
3827 ARRAY_SIZE(yuv_formats),
f180b4bc 3828 NULL, plane->type, NULL);
e7b07cee
HW		 3829 break;
3830 case DRM_PLANE_TYPE_CURSOR:
3831 res = drm_universal_plane_init(
3832 dm->adev->ddev,
f180b4bc 3833 plane,
e7b07cee
HW		 3834 possible_crtcs,
3835 &dm_plane_funcs,
3836 cursor_formats,
3837 ARRAY_SIZE(cursor_formats),
f180b4bc 3838 NULL, plane->type, NULL);
e7b07cee
HW		 3839 break;
3840 }
3841
f180b4bc 3842 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 3843
96719c54 3844 /* Create (reset) the plane state */
f180b4bc
HW		 3845 if (plane->funcs->reset)
3846 plane->funcs->reset(plane);
96719c54
HW		 3847
3848
e7b07cee
HW		 3849 return res;
3850}
3851
7578ecda
AD		 3852static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3853 struct drm_plane *plane,
3854 uint32_t crtc_index)
e7b07cee
HW		 3855{
3856 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 3857 struct drm_plane *cursor_plane;
e7b07cee
HW		 3858
3859 int res = -ENOMEM;
3860
3861 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3862 if (!cursor_plane)
3863 goto fail;
3864
f180b4bc 3865 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
e7b07cee
HW		 3866 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3867
3868 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3869 if (!acrtc)
3870 goto fail;
3871
3872 res = drm_crtc_init_with_planes(
3873 dm->ddev,
3874 &acrtc->base,
3875 plane,
f180b4bc 3876 cursor_plane,
e7b07cee
HW		 3877 &amdgpu_dm_crtc_funcs, NULL);
3878
3879 if (res)
3880 goto fail;
3881
3882 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3883
96719c54
HW		 3884 /* Create (reset) the plane state */
3885 if (acrtc->base.funcs->reset)
3886 acrtc->base.funcs->reset(&acrtc->base);
3887
e7b07cee
HW		 3888 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3889 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3890
3891 acrtc->crtc_id = crtc_index;
3892 acrtc->base.enabled = false;
c37e2d29 3893 acrtc->otg_inst = -1;
e7b07cee
HW		 3894
3895 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3896 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3897 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3898 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3899
3900 return 0;
3901
3902fail:
b830ebc9
HW		 3903 kfree(acrtc);
3904 kfree(cursor_plane);
e7b07cee
HW		 3905 return res;
3906}
3907
3908
3909static int to_drm_connector_type(enum signal_type st)
3910{
3911 switch (st) {
3912 case SIGNAL_TYPE_HDMI_TYPE_A:
3913 return DRM_MODE_CONNECTOR_HDMIA;
3914 case SIGNAL_TYPE_EDP:
3915 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 3916 case SIGNAL_TYPE_LVDS:
3917 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 3918 case SIGNAL_TYPE_RGB:
3919 return DRM_MODE_CONNECTOR_VGA;
3920 case SIGNAL_TYPE_DISPLAY_PORT:
3921 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3922 return DRM_MODE_CONNECTOR_DisplayPort;
3923 case SIGNAL_TYPE_DVI_DUAL_LINK:
3924 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3925 return DRM_MODE_CONNECTOR_DVID;
3926 case SIGNAL_TYPE_VIRTUAL:
3927 return DRM_MODE_CONNECTOR_VIRTUAL;
3928
3929 default:
3930 return DRM_MODE_CONNECTOR_Unknown;
3931 }
3932}
3933
2b4c1c05
DV		 3934static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
3935{
3936 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
3937}
3938
e7b07cee
HW		 3939static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3940{
e7b07cee
HW		 3941 struct drm_encoder *encoder;
3942 struct amdgpu_encoder *amdgpu_encoder;
3943
2b4c1c05 3944 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 3945
3946 if (encoder == NULL)
3947 return;
3948
3949 amdgpu_encoder = to_amdgpu_encoder(encoder);
3950
3951 amdgpu_encoder->native_mode.clock = 0;
3952
3953 if (!list_empty(&connector->probed_modes)) {
3954 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3955
e7b07cee 3956 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3957 &connector->probed_modes,
3958 head) {
3959 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3960 amdgpu_encoder->native_mode = *preferred_mode;
3961
e7b07cee
HW		 3962 break;
3963 }
3964
3965 }
3966}
3967
3ee6b26b
AD		 3968static struct drm_display_mode *
3969amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3970 char *name,
3971 int hdisplay, int vdisplay)
e7b07cee
HW		 3972{
3973 struct drm_device *dev = encoder->dev;
3974 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3975 struct drm_display_mode *mode = NULL;
3976 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3977
3978 mode = drm_mode_duplicate(dev, native_mode);
3979
b830ebc9 3980 if (mode == NULL)
e7b07cee
HW		 3981 return NULL;
3982
3983 mode->hdisplay = hdisplay;
3984 mode->vdisplay = vdisplay;
3985 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 3986 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 3987
3988 return mode;
3989
3990}
3991
3992static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3993 struct drm_connector *connector)
e7b07cee
HW		 3994{
3995 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3996 struct drm_display_mode *mode = NULL;
3997 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3998 struct amdgpu_dm_connector *amdgpu_dm_connector =
3999 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4000 int i;
4001 int n;
4002 struct mode_size {
4003 char name[DRM_DISPLAY_MODE_LEN];
4004 int w;
4005 int h;
b830ebc9 4006 } common_modes[] = {
e7b07cee
HW		 4007 { "640x480", 640, 480},
4008 { "800x600", 800, 600},
4009 { "1024x768", 1024, 768},
4010 { "1280x720", 1280, 720},
4011 { "1280x800", 1280, 800},
4012 {"1280x1024", 1280, 1024},
4013 { "1440x900", 1440, 900},
4014 {"1680x1050", 1680, 1050},
4015 {"1600x1200", 1600, 1200},
4016 {"1920x1080", 1920, 1080},
4017 {"1920x1200", 1920, 1200}
4018 };
4019
b830ebc9 4020 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 4021
4022 for (i = 0; i < n; i++) {
4023 struct drm_display_mode *curmode = NULL;
4024 bool mode_existed = false;
4025
4026 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 4027 common_modes[i].h > native_mode->vdisplay ||
4028 (common_modes[i].w == native_mode->hdisplay &&
4029 common_modes[i].h == native_mode->vdisplay))
4030 continue;
e7b07cee
HW		 4031
4032 list_for_each_entry(curmode, &connector->probed_modes, head) {
4033 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 4034 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 4035 mode_existed = true;
4036 break;
4037 }
4038 }
4039
4040 if (mode_existed)
4041 continue;
4042
4043 mode = amdgpu_dm_create_common_mode(encoder,
4044 common_modes[i].name, common_modes[i].w,
4045 common_modes[i].h);
4046 drm_mode_probed_add(connector, mode);
c84dec2f 4047 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 4048 }
4049}
4050
3ee6b26b
AD		 4051static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4052 struct edid *edid)
e7b07cee 4053{
c84dec2f
HW		 4054 struct amdgpu_dm_connector *amdgpu_dm_connector =
4055 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4056
4057 if (edid) {
4058 /* empty probed_modes */
4059 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 4060 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 4061 drm_add_edid_modes(connector, edid);
4062
e7b07cee 4063 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 4064 } else {
c84dec2f 4065 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 4066 }
e7b07cee
HW		 4067}
4068
7578ecda 4069static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 4070{
c84dec2f
HW		 4071 struct amdgpu_dm_connector *amdgpu_dm_connector =
4072 to_amdgpu_dm_connector(connector);
e7b07cee 4073 struct drm_encoder *encoder;
c84dec2f 4074 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 4075
2b4c1c05 4076 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 4077
85ee15d6 4078 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 4079 amdgpu_dm_connector->num_modes =
4080 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 4081 } else {
4082 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4083 amdgpu_dm_connector_add_common_modes(encoder, connector);
4084 }
3e332d3a 4085 amdgpu_dm_fbc_init(connector);
5099114b 4086
c84dec2f 4087 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 4088}
4089
3ee6b26b
AD		 4090void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4091 struct amdgpu_dm_connector *aconnector,
4092 int connector_type,
4093 struct dc_link *link,
4094 int link_index)
e7b07cee
HW		 4095{
4096 struct amdgpu_device *adev = dm->ddev->dev_private;
4097
4098 aconnector->connector_id = link_index;
4099 aconnector->dc_link = link;
4100 aconnector->base.interlace_allowed = false;
4101 aconnector->base.doublescan_allowed = false;
4102 aconnector->base.stereo_allowed = false;
4103 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4104 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
e7b07cee
HW		 4105 mutex_init(&aconnector->hpd_lock);
4106
1f6010a9
DF		 4107 /*
4108 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 4109 * which means HPD hot plug not supported
4110 */
e7b07cee
HW		 4111 switch (connector_type) {
4112 case DRM_MODE_CONNECTOR_HDMIA:
4113 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4114 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4115 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 4116 break;
4117 case DRM_MODE_CONNECTOR_DisplayPort:
4118 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4119 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4120 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 4121 break;
4122 case DRM_MODE_CONNECTOR_DVID:
4123 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4124 break;
4125 default:
4126 break;
4127 }
4128
4129 drm_object_attach_property(&aconnector->base.base,
4130 dm->ddev->mode_config.scaling_mode_property,
4131 DRM_MODE_SCALE_NONE);
4132
4133 drm_object_attach_property(&aconnector->base.base,
4134 adev->mode_info.underscan_property,
4135 UNDERSCAN_OFF);
4136 drm_object_attach_property(&aconnector->base.base,
4137 adev->mode_info.underscan_hborder_property,
4138 0);
4139 drm_object_attach_property(&aconnector->base.base,
4140 adev->mode_info.underscan_vborder_property,
4141 0);
07e3a1cf
NK		 4142 drm_object_attach_property(&aconnector->base.base,
4143 adev->mode_info.max_bpc_property,
4144 0);
e7b07cee 4145
c1ee92f9
DF		 4146 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4147 dc_is_dmcu_initialized(adev->dm.dc)) {
4148 drm_object_attach_property(&aconnector->base.base,
4149 adev->mode_info.abm_level_property, 0);
4150 }
bb47de73
NK		 4151
4152 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
4153 connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
4154 drm_connector_attach_vrr_capable_property(
4155 &aconnector->base);
4156 }
e7b07cee
HW		 4157}
4158
7578ecda
AD		 4159static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4160 struct i2c_msg *msgs, int num)
e7b07cee
HW		 4161{
4162 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4163 struct ddc_service *ddc_service = i2c->ddc_service;
4164 struct i2c_command cmd;
4165 int i;
4166 int result = -EIO;
4167
b830ebc9 4168 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 4169
4170 if (!cmd.payloads)
4171 return result;
4172
4173 cmd.number_of_payloads = num;
4174 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4175 cmd.speed = 100;
4176
4177 for (i = 0; i < num; i++) {
4178 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4179 cmd.payloads[i].address = msgs[i].addr;
4180 cmd.payloads[i].length = msgs[i].len;
4181 cmd.payloads[i].data = msgs[i].buf;
4182 }
4183
c85e6e54
DF		 4184 if (dc_submit_i2c(
4185 ddc_service->ctx->dc,
4186 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 4187 &cmd))
4188 result = num;
4189
4190 kfree(cmd.payloads);
4191 return result;
4192}
4193
7578ecda 4194static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 4195{
4196 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4197}
4198
4199static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4200 .master_xfer = amdgpu_dm_i2c_xfer,
4201 .functionality = amdgpu_dm_i2c_func,
4202};
4203
3ee6b26b
AD		 4204static struct amdgpu_i2c_adapter *
4205create_i2c(struct ddc_service *ddc_service,
4206 int link_index,
4207 int *res)
e7b07cee
HW		 4208{
4209 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4210 struct amdgpu_i2c_adapter *i2c;
4211
b830ebc9 4212 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 4213 if (!i2c)
4214 return NULL;
e7b07cee
HW		 4215 i2c->base.owner = THIS_MODULE;
4216 i2c->base.class = I2C_CLASS_DDC;
4217 i2c->base.dev.parent = &adev->pdev->dev;
4218 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 4219 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 4220 i2c_set_adapdata(&i2c->base, i2c);
4221 i2c->ddc_service = ddc_service;
c85e6e54 4222 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 4223
4224 return i2c;
4225}
4226
89fc8d4e 4227
1f6010a9
DF		 4228/*
4229 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 4230 * dc_link which will be represented by this aconnector.
4231 */
7578ecda
AD		 4232static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4233 struct amdgpu_dm_connector *aconnector,
4234 uint32_t link_index,
4235 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 4236{
4237 int res = 0;
4238 int connector_type;
4239 struct dc *dc = dm->dc;
4240 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4241 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 4242
4243 link->priv = aconnector;
e7b07cee 4244
f1ad2f5e 4245 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 4246
4247 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 4248 if (!i2c) {
4249 DRM_ERROR("Failed to create i2c adapter data\n");
4250 return -ENOMEM;
4251 }
4252
e7b07cee
HW		 4253 aconnector->i2c = i2c;
4254 res = i2c_add_adapter(&i2c->base);
4255
4256 if (res) {
4257 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4258 goto out_free;
4259 }
4260
4261 connector_type = to_drm_connector_type(link->connector_signal);
4262
4263 res = drm_connector_init(
4264 dm->ddev,
4265 &aconnector->base,
4266 &amdgpu_dm_connector_funcs,
4267 connector_type);
4268
4269 if (res) {
4270 DRM_ERROR("connector_init failed\n");
4271 aconnector->connector_id = -1;
4272 goto out_free;
4273 }
4274
4275 drm_connector_helper_add(
4276 &aconnector->base,
4277 &amdgpu_dm_connector_helper_funcs);
4278
96719c54
HW		 4279 if (aconnector->base.funcs->reset)
4280 aconnector->base.funcs->reset(&aconnector->base);
4281
e7b07cee
HW		 4282 amdgpu_dm_connector_init_helper(
4283 dm,
4284 aconnector,
4285 connector_type,
4286 link,
4287 link_index);
4288
cde4c44d 4289 drm_connector_attach_encoder(
e7b07cee
HW		 4290 &aconnector->base, &aencoder->base);
4291
4292 drm_connector_register(&aconnector->base);
dc38fd9d
DF		 4293#if defined(CONFIG_DEBUG_FS)
4294 res = connector_debugfs_init(aconnector);
4295 if (res) {
4296 DRM_ERROR("Failed to create debugfs for connector");
4297 goto out_free;
4298 }
4299#endif
e7b07cee
HW		 4300
4301 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4302 || connector_type == DRM_MODE_CONNECTOR_eDP)
4303 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4304
e7b07cee
HW		 4305out_free:
4306 if (res) {
4307 kfree(i2c);
4308 aconnector->i2c = NULL;
4309 }
4310 return res;
4311}
4312
4313int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4314{
4315 switch (adev->mode_info.num_crtc) {
4316 case 1:
4317 return 0x1;
4318 case 2:
4319 return 0x3;
4320 case 3:
4321 return 0x7;
4322 case 4:
4323 return 0xf;
4324 case 5:
4325 return 0x1f;
4326 case 6:
4327 default:
4328 return 0x3f;
4329 }
4330}
4331
7578ecda
AD		 4332static int amdgpu_dm_encoder_init(struct drm_device *dev,
4333 struct amdgpu_encoder *aencoder,
4334 uint32_t link_index)
e7b07cee
HW		 4335{
4336 struct amdgpu_device *adev = dev->dev_private;
4337
4338 int res = drm_encoder_init(dev,
4339 &aencoder->base,
4340 &amdgpu_dm_encoder_funcs,
4341 DRM_MODE_ENCODER_TMDS,
4342 NULL);
4343
4344 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4345
4346 if (!res)
4347 aencoder->encoder_id = link_index;
4348 else
4349 aencoder->encoder_id = -1;
4350
4351 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4352
4353 return res;
4354}
4355
3ee6b26b
AD		 4356static void manage_dm_interrupts(struct amdgpu_device *adev,
4357 struct amdgpu_crtc *acrtc,
4358 bool enable)
e7b07cee
HW		 4359{
4360 /*
4361 * this is not correct translation but will work as soon as VBLANK
4362 * constant is the same as PFLIP
4363 */
4364 int irq_type =
734dd01d 4365 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 4366 adev,
4367 acrtc->crtc_id);
4368
4369 if (enable) {
4370 drm_crtc_vblank_on(&acrtc->base);
4371 amdgpu_irq_get(
4372 adev,
4373 &adev->pageflip_irq,
4374 irq_type);
4375 } else {
4376
4377 amdgpu_irq_put(
4378 adev,
4379 &adev->pageflip_irq,
4380 irq_type);
4381 drm_crtc_vblank_off(&acrtc->base);
4382 }
4383}
4384
3ee6b26b
AD		 4385static bool
4386is_scaling_state_different(const struct dm_connector_state *dm_state,
4387 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 4388{
4389 if (dm_state->scaling != old_dm_state->scaling)
4390 return true;
4391 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4392 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4393 return true;
4394 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4395 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4396 return true;
b830ebc9
HW		 4397 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4398 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4399 return true;
e7b07cee
HW		 4400 return false;
4401}
4402
3ee6b26b
AD		 4403static void remove_stream(struct amdgpu_device *adev,
4404 struct amdgpu_crtc *acrtc,
4405 struct dc_stream_state *stream)
e7b07cee
HW		 4406{
4407 /* this is the update mode case */
e7b07cee
HW		 4408
4409 acrtc->otg_inst = -1;
4410 acrtc->enabled = false;
4411}
4412
7578ecda
AD		 4413static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4414 struct dc_cursor_position *position)
2a8f6ccb 4415{
f4c2cc43 4416 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 4417 int x, y;
4418 int xorigin = 0, yorigin = 0;
4419
4420 if (!crtc || !plane->state->fb) {
4421 position->enable = false;
4422 position->x = 0;
4423 position->y = 0;
4424 return 0;
4425 }
4426
4427 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4428 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4429 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4430 __func__,
4431 plane->state->crtc_w,
4432 plane->state->crtc_h);
4433 return -EINVAL;
4434 }
4435
4436 x = plane->state->crtc_x;
4437 y = plane->state->crtc_y;
4438 /* avivo cursor are offset into the total surface */
4439 x += crtc->primary->state->src_x >> 16;
4440 y += crtc->primary->state->src_y >> 16;
4441 if (x < 0) {
4442 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4443 x = 0;
4444 }
4445 if (y < 0) {
4446 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4447 y = 0;
4448 }
4449 position->enable = true;
4450 position->x = x;
4451 position->y = y;
4452 position->x_hotspot = xorigin;
4453 position->y_hotspot = yorigin;
4454
4455 return 0;
4456}
4457
3ee6b26b
AD		 4458static void handle_cursor_update(struct drm_plane *plane,
4459 struct drm_plane_state *old_plane_state)
e7b07cee 4460{
674e78ac 4461 struct amdgpu_device *adev = plane->dev->dev_private;
2a8f6ccb
HW		 4462 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4463 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4464 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4465 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4466 uint64_t address = afb ? afb->address : 0;
4467 struct dc_cursor_position position;
4468 struct dc_cursor_attributes attributes;
4469 int ret;
4470
e7b07cee
HW		 4471 if (!plane->state->fb && !old_plane_state->fb)
4472 return;
4473
f1ad2f5e 4474 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 4475 __func__,
4476 amdgpu_crtc->crtc_id,
4477 plane->state->crtc_w,
4478 plane->state->crtc_h);
2a8f6ccb
HW		 4479
4480 ret = get_cursor_position(plane, crtc, &position);
4481 if (ret)
4482 return;
4483
4484 if (!position.enable) {
4485 /* turn off cursor */
674e78ac
NK		 4486 if (crtc_state && crtc_state->stream) {
4487 mutex_lock(&adev->dm.dc_lock);
2a8f6ccb
HW		 4488 dc_stream_set_cursor_position(crtc_state->stream,
4489 &position);
674e78ac
NK		 4490 mutex_unlock(&adev->dm.dc_lock);
4491 }
2a8f6ccb 4492 return;
e7b07cee 4493 }
e7b07cee 4494
2a8f6ccb
HW		 4495 amdgpu_crtc->cursor_width = plane->state->crtc_w;
4496 amdgpu_crtc->cursor_height = plane->state->crtc_h;
4497
4498 attributes.address.high_part = upper_32_bits(address);
4499 attributes.address.low_part = lower_32_bits(address);
4500 attributes.width = plane->state->crtc_w;
4501 attributes.height = plane->state->crtc_h;
4502 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4503 attributes.rotation_angle = 0;
4504 attributes.attribute_flags.value = 0;
4505
4506 attributes.pitch = attributes.width;
4507
886daac9 4508 if (crtc_state->stream) {
674e78ac 4509 mutex_lock(&adev->dm.dc_lock);
886daac9
JZ		 4510 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4511 &attributes))
4512 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 4513
2a8f6ccb
HW		 4514 if (!dc_stream_set_cursor_position(crtc_state->stream,
4515 &position))
4516 DRM_ERROR("DC failed to set cursor position\n");
674e78ac 4517 mutex_unlock(&adev->dm.dc_lock);
886daac9 4518 }
2a8f6ccb 4519}
e7b07cee
HW		 4520
4521static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4522{
4523
4524 assert_spin_locked(&acrtc->base.dev->event_lock);
4525 WARN_ON(acrtc->event);
4526
4527 acrtc->event = acrtc->base.state->event;
4528
4529 /* Set the flip status */
4530 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4531
4532 /* Mark this event as consumed */
4533 acrtc->base.state->event = NULL;
4534
4535 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4536 acrtc->crtc_id);
4537}
4538
bb47de73
NK		 4539static void update_freesync_state_on_stream(
4540 struct amdgpu_display_manager *dm,
4541 struct dm_crtc_state *new_crtc_state,
180db303
NK		 4542 struct dc_stream_state *new_stream,
4543 struct dc_plane_state *surface,
4544 u32 flip_timestamp_in_us)
bb47de73 4545{
180db303 4546 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params;
bb47de73
NK		 4547 struct dc_info_packet vrr_infopacket = {0};
4548 struct mod_freesync_config config = new_crtc_state->freesync_config;
4549
4550 if (!new_stream)
4551 return;
4552
4553 /*
4554 * TODO: Determine why min/max totals and vrefresh can be 0 here.
4555 * For now it's sufficient to just guard against these conditions.
4556 */
4557
4558 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
4559 return;
4560
4561 if (new_crtc_state->vrr_supported &&
4562 config.min_refresh_in_uhz &&
4563 config.max_refresh_in_uhz) {
4564 config.state = new_crtc_state->base.vrr_enabled ?
4565 VRR_STATE_ACTIVE_VARIABLE :
4566 VRR_STATE_INACTIVE;
4567 } else {
4568 config.state = VRR_STATE_UNSUPPORTED;
4569 }
4570
4571 mod_freesync_build_vrr_params(dm->freesync_module,
4572 new_stream,
180db303
NK		 4573 &config, &vrr_params);
4574
4575 if (surface) {
4576 mod_freesync_handle_preflip(
4577 dm->freesync_module,
4578 surface,
4579 new_stream,
4580 flip_timestamp_in_us,
4581 &vrr_params);
4582 }
bb47de73
NK		 4583
4584 mod_freesync_build_vrr_infopacket(
4585 dm->freesync_module,
4586 new_stream,
180db303 4587 &vrr_params,
ecd0136b
HT		 4588 PACKET_TYPE_VRR,
4589 TRANSFER_FUNC_UNKNOWN,
bb47de73
NK		 4590 &vrr_infopacket);
4591
4592 new_crtc_state->freesync_timing_changed =
180db303
NK		 4593 (memcmp(&new_crtc_state->vrr_params.adjust,
4594 &vrr_params.adjust,
4595 sizeof(vrr_params.adjust)) != 0);
bb47de73
NK		 4596
4597 new_crtc_state->freesync_vrr_info_changed =
4598 (memcmp(&new_crtc_state->vrr_infopacket,
4599 &vrr_infopacket,
4600 sizeof(vrr_infopacket)) != 0);
4601
180db303 4602 new_crtc_state->vrr_params = vrr_params;
bb47de73
NK		 4603 new_crtc_state->vrr_infopacket = vrr_infopacket;
4604
180db303 4605 new_stream->adjust = new_crtc_state->vrr_params.adjust;
bb47de73
NK		 4606 new_stream->vrr_infopacket = vrr_infopacket;
4607
4608 if (new_crtc_state->freesync_vrr_info_changed)
4609 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
4610 new_crtc_state->base.crtc->base.id,
4611 (int)new_crtc_state->base.vrr_enabled,
180db303 4612 (int)vrr_params.state);
bb47de73
NK		 4613
4614 if (new_crtc_state->freesync_timing_changed)
4615 DRM_DEBUG_KMS("VRR timing update: crtc=%u min=%u max=%u\n",
4616 new_crtc_state->base.crtc->base.id,
180db303
NK		 4617 vrr_params.adjust.v_total_min,
4618 vrr_params.adjust.v_total_max);
bb47de73
NK		 4619}
4620
e7b07cee
HW		 4621/*
4622 * Executes flip
4623 *
4624 * Waits on all BO's fences and for proper vblank count
4625 */
3ee6b26b
AD		 4626static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
4627 struct drm_framebuffer *fb,
bc6828e0
BL		 4628 uint32_t target,
4629 struct dc_state *state)
e7b07cee
HW		 4630{
4631 unsigned long flags;
9136e81e 4632 uint64_t timestamp_ns;
e7b07cee
HW		 4633 uint32_t target_vblank;
4634 int r, vpos, hpos;
4635 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4636 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
e68d14dd 4637 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
e7b07cee 4638 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 4639 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 4640 struct dc_flip_addrs addr = { {0} };
3be5262e 4641 /* TODO eliminate or rename surface_update */
e7b07cee 4642 struct dc_surface_update surface_updates[1] = { {0} };
bb47de73 4643 struct dc_stream_update stream_update = {0};
e7b07cee 4644 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
d999853e 4645 struct dc_stream_status *stream_status;
180db303 4646 struct dc_plane_state *surface;
7df7e505 4647 uint64_t tiling_flags, dcc_address;
e7b07cee
HW		 4648
4649
4650 /* Prepare wait for target vblank early - before the fence-waits */
23effc11 4651 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
e7b07cee
HW		 4652 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
4653
1f6010a9
DF		 4654 /*
4655 * TODO This might fail and hence better not used, wait
e7b07cee
HW		 4656 * explicitly on fences instead
4657 * and in general should be called for
4658 * blocking commit to as per framework helpers
b830ebc9 4659 */
e7b07cee
HW		 4660 r = amdgpu_bo_reserve(abo, true);
4661 if (unlikely(r != 0)) {
4662 DRM_ERROR("failed to reserve buffer before flip\n");
4663 WARN_ON(1);
4664 }
4665
4666 /* Wait for all fences on this FB */
4667 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
4668 MAX_SCHEDULE_TIMEOUT) < 0);
4669
7df7e505
NK		 4670 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
4671
e7b07cee
HW		 4672 amdgpu_bo_unreserve(abo);
4673
1f6010a9
DF		 4674 /*
4675 * Wait until we're out of the vertical blank period before the one
e7b07cee
HW		 4676 * targeted by the flip
4677 */
4678 while ((acrtc->enabled &&
aa8e286a
SL		 4679 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
4680 0, &vpos, &hpos, NULL,
4681 NULL, &crtc->hwmode)
e7b07cee
HW		 4682 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4683 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4684 (int)(target_vblank -
4685 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
4686 usleep_range(1000, 1100);
4687 }
4688
4689 /* Flip */
4690 spin_lock_irqsave(&crtc->dev->event_lock, flags);
e7b07cee
HW		 4691
4692 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
4693 WARN_ON(!acrtc_state->stream);
4694
4695 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
4696 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
7df7e505
NK		 4697
4698 dcc_address = get_dcc_address(afb->address, tiling_flags);
4699 addr.address.grph.meta_addr.low_part = lower_32_bits(dcc_address);
4700 addr.address.grph.meta_addr.high_part = upper_32_bits(dcc_address);
4701
e7b07cee
HW		 4702 addr.flip_immediate = async_flip;
4703
9136e81e
NK		 4704 timestamp_ns = ktime_get_ns();
4705 addr.flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
e7b07cee
HW		 4706
4707
4708 if (acrtc->base.state->event)
4709 prepare_flip_isr(acrtc);
4710
4de9f38b
S		 4711 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4712
d999853e
NK		 4713 stream_status = dc_stream_get_status(acrtc_state->stream);
4714 if (!stream_status) {
4715 DRM_ERROR("No stream status for CRTC: id=%d\n",
4716 acrtc->crtc_id);
4717 return;
4718 }
4719
180db303
NK		 4720 surface = stream_status->plane_states[0];
4721 surface_updates->surface = surface;
4722
4723 if (!surface) {
d999853e
NK		 4724 DRM_ERROR("No surface for CRTC: id=%d\n",
4725 acrtc->crtc_id);
4726 return;
4727 }
e7b07cee
HW		 4728 surface_updates->flip_addr = &addr;
4729
bb47de73
NK		 4730 if (acrtc_state->stream) {
4731 update_freesync_state_on_stream(
4732 &adev->dm,
4733 acrtc_state,
180db303
NK		 4734 acrtc_state->stream,
4735 surface,
4736 addr.flip_timestamp_in_us);
bb47de73
NK		 4737
4738 if (acrtc_state->freesync_timing_changed)
4739 stream_update.adjust =
4740 &acrtc_state->stream->adjust;
4741
4742 if (acrtc_state->freesync_vrr_info_changed)
4743 stream_update.vrr_infopacket =
4744 &acrtc_state->stream->vrr_infopacket;
4745 }
4746
180db303
NK		 4747 /* Update surface timing information. */
4748 surface->time.time_elapsed_in_us[surface->time.index] =
4749 addr.flip_timestamp_in_us - surface->time.prev_update_time_in_us;
4750 surface->time.prev_update_time_in_us = addr.flip_timestamp_in_us;
4751 surface->time.index++;
4752 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
4753 surface->time.index = 0;
4754
674e78ac 4755 mutex_lock(&adev->dm.dc_lock);
180db303 4756
bc6828e0
BL		 4757 dc_commit_updates_for_stream(adev->dm.dc,
4758 surface_updates,
4759 1,
4760 acrtc_state->stream,
bb47de73 4761 &stream_update,
bc6828e0 4762 state);
674e78ac 4763 mutex_unlock(&adev->dm.dc_lock);
e7b07cee
HW		 4764
4765 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
4766 __func__,
4767 addr.address.grph.addr.high_part,
4768 addr.address.grph.addr.low_part);
e7b07cee
HW		 4769}
4770
44d09c6a
HW		 4771/*
4772 * TODO this whole function needs to go
4773 *
4774 * dc_surface_update is needlessly complex. See if we can just replace this
4775 * with a dc_plane_state and follow the atomic model a bit more closely here.
4776 */
4777static bool commit_planes_to_stream(
674e78ac 4778 struct amdgpu_display_manager *dm,
44d09c6a
HW		 4779 struct dc *dc,
4780 struct dc_plane_state **plane_states,
4781 uint8_t new_plane_count,
4782 struct dm_crtc_state *dm_new_crtc_state,
4783 struct dm_crtc_state *dm_old_crtc_state,
4784 struct dc_state *state)
4785{
4786 /* no need to dynamically allocate this. it's pretty small */
4787 struct dc_surface_update updates[MAX_SURFACES];
4788 struct dc_flip_addrs *flip_addr;
4789 struct dc_plane_info *plane_info;
4790 struct dc_scaling_info *scaling_info;
4791 int i;
4792 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
4793 struct dc_stream_update *stream_update =
4794 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
c1ee92f9 4795 unsigned int abm_level;
44d09c6a
HW		 4796
4797 if (!stream_update) {
4798 BREAK_TO_DEBUGGER();
4799 return false;
4800 }
4801
4802 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
4803 GFP_KERNEL);
4804 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
4805 GFP_KERNEL);
4806 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
4807 GFP_KERNEL);
4808
4809 if (!flip_addr || !plane_info || !scaling_info) {
4810 kfree(flip_addr);
4811 kfree(plane_info);
4812 kfree(scaling_info);
4813 kfree(stream_update);
4814 return false;
4815 }
4816
4817 memset(updates, 0, sizeof(updates));
4818
4819 stream_update->src = dc_stream->src;
4820 stream_update->dst = dc_stream->dst;
4821 stream_update->out_transfer_func = dc_stream->out_transfer_func;
4822
c1ee92f9
DF		 4823 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
4824 abm_level = dm_new_crtc_state->abm_level;
4825 stream_update->abm_level = &abm_level;
98e6436d
AK		 4826 }
4827
44d09c6a
HW		 4828 for (i = 0; i < new_plane_count; i++) {
4829 updates[i].surface = plane_states[i];
4830 updates[i].gamma =
4831 (struct dc_gamma *)plane_states[i]->gamma_correction;
4832 updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4833 flip_addr[i].address = plane_states[i]->address;
4834 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4835 plane_info[i].color_space = plane_states[i]->color_space;
44d09c6a
HW		 4836 plane_info[i].format = plane_states[i]->format;
4837 plane_info[i].plane_size = plane_states[i]->plane_size;
4838 plane_info[i].rotation = plane_states[i]->rotation;
4839 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4840 plane_info[i].stereo_format = plane_states[i]->stereo_format;
4841 plane_info[i].tiling_info = plane_states[i]->tiling_info;
4842 plane_info[i].visible = plane_states[i]->visible;
4843 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4844 plane_info[i].dcc = plane_states[i]->dcc;
4845 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4846 scaling_info[i].src_rect = plane_states[i]->src_rect;
4847 scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4848 scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4849
4850 updates[i].flip_addr = &flip_addr[i];
4851 updates[i].plane_info = &plane_info[i];
4852 updates[i].scaling_info = &scaling_info[i];
4853 }
4854
674e78ac 4855 mutex_lock(&dm->dc_lock);
44d09c6a
HW		 4856 dc_commit_updates_for_stream(
4857 dc,
4858 updates,
4859 new_plane_count,
cfdb60f7 4860 dc_stream, stream_update, state);
674e78ac 4861 mutex_unlock(&dm->dc_lock);
44d09c6a
HW		 4862
4863 kfree(flip_addr);
4864 kfree(plane_info);
4865 kfree(scaling_info);
4866 kfree(stream_update);
4867 return true;
4868}
4869
3be5262e 4870static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 4871 struct dc_state *dc_state,
3ee6b26b
AD		 4872 struct drm_device *dev,
4873 struct amdgpu_display_manager *dm,
4874 struct drm_crtc *pcrtc,
4875 bool *wait_for_vblank)
e7b07cee
HW		 4876{
4877 uint32_t i;
4878 struct drm_plane *plane;
0bc9706d 4879 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 4880 struct dc_stream_state *dc_stream_attach;
3be5262e 4881 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 4882 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 4883 struct drm_crtc_state *new_pcrtc_state =
4884 drm_atomic_get_new_crtc_state(state, pcrtc);
4885 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 4886 struct dm_crtc_state *dm_old_crtc_state =
4887 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
e7b07cee
HW		 4888 int planes_count = 0;
4889 unsigned long flags;
4890
4891 /* update planes when needed */
0bc9706d
LSL		 4892 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4893 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 4894 struct drm_crtc_state *new_crtc_state;
0bc9706d 4895 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 4896 bool pflip_needed;
54d76575 4897 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 4898
4899 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4900 handle_cursor_update(plane, old_plane_state);
4901 continue;
4902 }
4903
f5ba60fe
DD		 4904 if (!fb || !crtc || pcrtc != crtc)
4905 continue;
4906
4907 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4908 if (!new_crtc_state->active)
e7b07cee
HW		 4909 continue;
4910
4911 pflip_needed = !state->allow_modeset;
4912
4913 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4914 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 4915 DRM_ERROR("%s: acrtc %d, already busy\n",
4916 __func__,
4917 acrtc_attach->crtc_id);
b830ebc9 4918 /* In commit tail framework this cannot happen */
e7b07cee
HW		 4919 WARN_ON(1);
4920 }
4921 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4922
a2a330ad 4923 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
54d76575 4924 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 4925
54d76575 4926 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 4927
4928 dc_stream_attach = acrtc_state->stream;
4929 planes_count++;
4930
0bc9706d 4931 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 4932 /* Assume even ONE crtc with immediate flip means
4933 * entire can't wait for VBLANK
4934 * TODO Check if it's correct
4935 */
4936 *wait_for_vblank =
0bc9706d 4937 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 4938 false : true;
4939
4940 /* TODO: Needs rework for multiplane flip */
4941 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4942 drm_crtc_vblank_get(crtc);
4943
4944 amdgpu_dm_do_flip(
4945 crtc,
4946 fb,
23effc11 4947 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
eb3dc897 4948 dc_state);
e7b07cee
HW		 4949 }
4950
4951 }
4952
4953 if (planes_count) {
4954 unsigned long flags;
4955
0bc9706d 4956 if (new_pcrtc_state->event) {
e7b07cee
HW		 4957
4958 drm_crtc_vblank_get(pcrtc);
4959
4960 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4961 prepare_flip_isr(acrtc_attach);
4962 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4963 }
4964
c1ee92f9 4965 dc_stream_attach->abm_level = acrtc_state->abm_level;
44d09c6a 4966
674e78ac
NK		 4967 if (false == commit_planes_to_stream(dm,
4968 dm->dc,
3be5262e
HW		 4969 plane_states_constructed,
4970 planes_count,
44d09c6a
HW		 4971 acrtc_state,
4972 dm_old_crtc_state,
eb3dc897 4973 dc_state))
3be5262e 4974 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4975 } else {
4976 /*TODO BUG Here should go disable planes on CRTC. */
4977 }
4978}
4979
1f6010a9 4980/*
27b3f4fc
LSL		 4981 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4982 * @crtc_state: the DRM CRTC state
4983 * @stream_state: the DC stream state.
4984 *
4985 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4986 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4987 */
4988static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4989 struct dc_stream_state *stream_state)
4990{
4991 stream_state->mode_changed = crtc_state->mode_changed;
4992}
e7b07cee 4993
7578ecda
AD		 4994static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4995 struct drm_atomic_state *state,
4996 bool nonblock)
e7b07cee
HW		 4997{
4998 struct drm_crtc *crtc;
c2cea706 4999 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 5000 struct amdgpu_device *adev = dev->dev_private;
5001 int i;
5002
5003 /*
5004 * We evade vblanks and pflips on crtc that
5005 * should be changed. We do it here to flush & disable
5006 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
5007 * it will update crtc->dm_crtc_state->stream pointer which is used in
5008 * the ISRs.
5009 */
c2cea706 5010 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 5011 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 5012 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5013
54d76575 5014 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 5015 manage_dm_interrupts(adev, acrtc, false);
5016 }
1f6010a9
DF		 5017 /*
5018 * Add check here for SoC's that support hardware cursor plane, to
5019 * unset legacy_cursor_update
5020 */
e7b07cee
HW		 5021
5022 return drm_atomic_helper_commit(dev, state, nonblock);
5023
5024 /*TODO Handle EINTR, reenable IRQ*/
5025}
5026
b8592b48
LL		 5027/**
5028 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
5029 * @state: The atomic state to commit
5030 *
5031 * This will tell DC to commit the constructed DC state from atomic_check,
5032 * programming the hardware. Any failures here implies a hardware failure, since
5033 * atomic check should have filtered anything non-kosher.
5034 */
7578ecda 5035static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 5036{
5037 struct drm_device *dev = state->dev;
5038 struct amdgpu_device *adev = dev->dev_private;
5039 struct amdgpu_display_manager *dm = &adev->dm;
5040 struct dm_atomic_state *dm_state;
eb3dc897 5041 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 5042 uint32_t i, j;
5cc6dcbd 5043 struct drm_crtc *crtc;
0bc9706d 5044 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 5045 unsigned long flags;
5046 bool wait_for_vblank = true;
5047 struct drm_connector *connector;
c2cea706 5048 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 5049 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 5050 int crtc_disable_count = 0;
e7b07cee
HW		 5051
5052 drm_atomic_helper_update_legacy_modeset_state(dev, state);
5053
eb3dc897
NK		 5054 dm_state = dm_atomic_get_new_state(state);
5055 if (dm_state && dm_state->context) {
5056 dc_state = dm_state->context;
5057 } else {
5058 /* No state changes, retain current state. */
5059 dc_state_temp = dc_create_state();
5060 ASSERT(dc_state_temp);
5061 dc_state = dc_state_temp;
5062 dc_resource_state_copy_construct_current(dm->dc, dc_state);
5063 }
e7b07cee
HW		 5064
5065 /* update changed items */
0bc9706d 5066 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 5067 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5068
54d76575
LSL		 5069 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5070 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 5071
f1ad2f5e 5072 DRM_DEBUG_DRIVER(
e7b07cee
HW		 5073 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5074 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5075 "connectors_changed:%d\n",
5076 acrtc->crtc_id,
0bc9706d
LSL		 5077 new_crtc_state->enable,
5078 new_crtc_state->active,
5079 new_crtc_state->planes_changed,
5080 new_crtc_state->mode_changed,
5081 new_crtc_state->active_changed,
5082 new_crtc_state->connectors_changed);
e7b07cee 5083
27b3f4fc
LSL		 5084 /* Copy all transient state flags into dc state */
5085 if (dm_new_crtc_state->stream) {
5086 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5087 dm_new_crtc_state->stream);
5088 }
5089
e7b07cee
HW		 5090 /* handles headless hotplug case, updating new_state and
5091 * aconnector as needed
5092 */
5093
54d76575 5094 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 5095
f1ad2f5e 5096 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 5097
54d76575 5098 if (!dm_new_crtc_state->stream) {
e7b07cee 5099 /*
b830ebc9
HW		 5100 * this could happen because of issues with
5101 * userspace notifications delivery.
5102 * In this case userspace tries to set mode on
1f6010a9
DF		 5103 * display which is disconnected in fact.
5104 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 5105 * We expect reset mode will come soon.
5106 *
5107 * This can also happen when unplug is done
5108 * during resume sequence ended
5109 *
5110 * In this case, we want to pretend we still
5111 * have a sink to keep the pipe running so that
5112 * hw state is consistent with the sw state
5113 */
f1ad2f5e 5114 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 5115 __func__, acrtc->base.base.id);
5116 continue;
5117 }
5118
54d76575
LSL		 5119 if (dm_old_crtc_state->stream)
5120 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 5121
97028037
LP		 5122 pm_runtime_get_noresume(dev->dev);
5123
e7b07cee 5124 acrtc->enabled = true;
0bc9706d
LSL		 5125 acrtc->hw_mode = new_crtc_state->mode;
5126 crtc->hwmode = new_crtc_state->mode;
5127 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 5128 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 5129
5130 /* i.e. reset mode */
54d76575
LSL		 5131 if (dm_old_crtc_state->stream)
5132 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 5133 }
5134 } /* for_each_crtc_in_state() */
5135
eb3dc897
NK		 5136 if (dc_state) {
5137 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 5138 mutex_lock(&dm->dc_lock);
eb3dc897 5139 WARN_ON(!dc_commit_state(dm->dc, dc_state));
674e78ac 5140 mutex_unlock(&dm->dc_lock);
fa2123db 5141 }
e7b07cee 5142
0bc9706d 5143 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5144 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5145
54d76575 5146 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5147
54d76575 5148 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 5149 const struct dc_stream_status *status =
54d76575 5150 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5151
eb3dc897 5152 if (!status)
09f609c3
LL		 5153 status = dc_stream_get_status_from_state(dc_state,
5154 dm_new_crtc_state->stream);
eb3dc897 5155
e7b07cee 5156 if (!status)
54d76575 5157 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 5158 else
5159 acrtc->otg_inst = status->primary_otg_inst;
5160 }
5161 }
5162
c1ee92f9 5163 /* Handle scaling, underscan, and abm changes*/
c2cea706 5164 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5165 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5166 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5167 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 5168 struct dc_stream_status *status = NULL;
5169
44d09c6a 5170 if (acrtc) {
0bc9706d 5171 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 5172 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5173 }
0bc9706d 5174
e7b07cee 5175 /* Skip any modesets/resets */
0bc9706d 5176 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 5177 continue;
5178
e7b07cee 5179
54d76575 5180 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 5181 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5182
5183 /* Skip anything that is not scaling or underscan changes */
5184 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5185 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5186 continue;
e7b07cee 5187
54d76575
LSL		 5188 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5189 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 5190
70e8ffc5
HW		 5191 if (!dm_new_crtc_state->stream)
5192 continue;
5193
54d76575 5194 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5195 WARN_ON(!status);
3be5262e 5196 WARN_ON(!status->plane_count);
e7b07cee 5197
c1ee92f9 5198 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
98e6436d 5199
e7b07cee 5200 /*TODO How it works with MPO ?*/
44d09c6a 5201 if (!commit_planes_to_stream(
674e78ac 5202 dm,
e7b07cee 5203 dm->dc,
3be5262e
HW		 5204 status->plane_states,
5205 status->plane_count,
44d09c6a
HW		 5206 dm_new_crtc_state,
5207 to_dm_crtc_state(old_crtc_state),
fb6e4709 5208 dc_state))
e7b07cee
HW		 5209 dm_error("%s: Failed to update stream scaling!\n", __func__);
5210 }
5211
e1fc2dca
LSL		 5212 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5213 new_crtc_state, i) {
e7b07cee
HW		 5214 /*
5215 * loop to enable interrupts on newly arrived crtc
5216 */
e1fc2dca
LSL		 5217 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5218 bool modeset_needed;
b830ebc9 5219
fe2a1965
LP		 5220 if (old_crtc_state->active && !new_crtc_state->active)
5221 crtc_disable_count++;
5222
54d76575 5223 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 5224 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5225 modeset_needed = modeset_required(
5226 new_crtc_state,
5227 dm_new_crtc_state->stream,
5228 dm_old_crtc_state->stream);
5229
5230 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
5231 continue;
e7b07cee 5232
e7b07cee
HW		 5233 manage_dm_interrupts(adev, acrtc, true);
5234 }
5235
5236 /* update planes when needed per crtc*/
5cc6dcbd 5237 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 5238 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5239
54d76575 5240 if (dm_new_crtc_state->stream)
eb3dc897
NK		 5241 amdgpu_dm_commit_planes(state, dc_state, dev,
5242 dm, crtc, &wait_for_vblank);
e7b07cee
HW		 5243 }
5244
5245
5246 /*
5247 * send vblank event on all events not handled in flip and
5248 * mark consumed event for drm_atomic_helper_commit_hw_done
5249 */
5250 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 5251 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5252
0bc9706d
LSL		 5253 if (new_crtc_state->event)
5254 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 5255
0bc9706d 5256 new_crtc_state->event = NULL;
e7b07cee
HW		 5257 }
5258 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5259
29c8f234
LL		 5260 /* Signal HW programming completion */
5261 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 5262
5263 if (wait_for_vblank)
320a1274 5264 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 5265
5266 drm_atomic_helper_cleanup_planes(dev, state);
97028037 5267
1f6010a9
DF		 5268 /*
5269 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 5270 * so we can put the GPU into runtime suspend if we're not driving any
5271 * displays anymore
5272 */
fe2a1965
LP		 5273 for (i = 0; i < crtc_disable_count; i++)
5274 pm_runtime_put_autosuspend(dev->dev);
97028037 5275 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 5276
5277 if (dc_state_temp)
5278 dc_release_state(dc_state_temp);
e7b07cee
HW		 5279}
5280
5281
5282static int dm_force_atomic_commit(struct drm_connector *connector)
5283{
5284 int ret = 0;
5285 struct drm_device *ddev = connector->dev;
5286 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5287 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5288 struct drm_plane *plane = disconnected_acrtc->base.primary;
5289 struct drm_connector_state *conn_state;
5290 struct drm_crtc_state *crtc_state;
5291 struct drm_plane_state *plane_state;
5292
5293 if (!state)
5294 return -ENOMEM;
5295
5296 state->acquire_ctx = ddev->mode_config.acquire_ctx;
5297
5298 /* Construct an atomic state to restore previous display setting */
5299
5300 /*
5301 * Attach connectors to drm_atomic_state
5302 */
5303 conn_state = drm_atomic_get_connector_state(state, connector);
5304
5305 ret = PTR_ERR_OR_ZERO(conn_state);
5306 if (ret)
5307 goto err;
5308
5309 /* Attach crtc to drm_atomic_state*/
5310 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5311
5312 ret = PTR_ERR_OR_ZERO(crtc_state);
5313 if (ret)
5314 goto err;
5315
5316 /* force a restore */
5317 crtc_state->mode_changed = true;
5318
5319 /* Attach plane to drm_atomic_state */
5320 plane_state = drm_atomic_get_plane_state(state, plane);
5321
5322 ret = PTR_ERR_OR_ZERO(plane_state);
5323 if (ret)
5324 goto err;
5325
5326
5327 /* Call commit internally with the state we just constructed */
5328 ret = drm_atomic_commit(state);
5329 if (!ret)
5330 return 0;
5331
5332err:
5333 DRM_ERROR("Restoring old state failed with %i\n", ret);
5334 drm_atomic_state_put(state);
5335
5336 return ret;
5337}
5338
5339/*
1f6010a9
DF		 5340 * This function handles all cases when set mode does not come upon hotplug.
5341 * This includes when a display is unplugged then plugged back into the
5342 * same port and when running without usermode desktop manager supprot
e7b07cee 5343 */
3ee6b26b
AD		 5344void dm_restore_drm_connector_state(struct drm_device *dev,
5345 struct drm_connector *connector)
e7b07cee 5346{
c84dec2f 5347 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5348 struct amdgpu_crtc *disconnected_acrtc;
5349 struct dm_crtc_state *acrtc_state;
5350
5351 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5352 return;
5353
5354 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 5355 if (!disconnected_acrtc)
5356 return;
e7b07cee 5357
70e8ffc5
HW		 5358 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5359 if (!acrtc_state->stream)
e7b07cee
HW		 5360 return;
5361
5362 /*
5363 * If the previous sink is not released and different from the current,
5364 * we deduce we are in a state where we can not rely on usermode call
5365 * to turn on the display, so we do it here
5366 */
5367 if (acrtc_state->stream->sink != aconnector->dc_sink)
5368 dm_force_atomic_commit(&aconnector->base);
5369}
5370
1f6010a9 5371/*
e7b07cee
HW		 5372 * Grabs all modesetting locks to serialize against any blocking commits,
5373 * Waits for completion of all non blocking commits.
5374 */
3ee6b26b
AD		 5375static int do_aquire_global_lock(struct drm_device *dev,
5376 struct drm_atomic_state *state)
e7b07cee
HW		 5377{
5378 struct drm_crtc *crtc;
5379 struct drm_crtc_commit *commit;
5380 long ret;
5381
1f6010a9
DF		 5382 /*
5383 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 5384 * ensure that when the framework release it the
5385 * extra locks we are locking here will get released to
5386 */
5387 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
5388 if (ret)
5389 return ret;
5390
5391 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5392 spin_lock(&crtc->commit_lock);
5393 commit = list_first_entry_or_null(&crtc->commit_list,
5394 struct drm_crtc_commit, commit_entry);
5395 if (commit)
5396 drm_crtc_commit_get(commit);
5397 spin_unlock(&crtc->commit_lock);
5398
5399 if (!commit)
5400 continue;
5401
1f6010a9
DF		 5402 /*
5403 * Make sure all pending HW programming completed and
e7b07cee
HW		 5404 * page flips done
5405 */
5406 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
5407
5408 if (ret > 0)
5409 ret = wait_for_completion_interruptible_timeout(
5410 &commit->flip_done, 10*HZ);
5411
5412 if (ret == 0)
5413 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 5414 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 5415
5416 drm_crtc_commit_put(commit);
5417 }
5418
5419 return ret < 0 ? ret : 0;
5420}
5421
bb47de73
NK		 5422static void get_freesync_config_for_crtc(
5423 struct dm_crtc_state *new_crtc_state,
5424 struct dm_connector_state *new_con_state)
98e6436d
AK		 5425{
5426 struct mod_freesync_config config = {0};
98e6436d
AK		 5427 struct amdgpu_dm_connector *aconnector =
5428 to_amdgpu_dm_connector(new_con_state->base.connector);
5429
bb47de73
NK		 5430 new_crtc_state->vrr_supported = new_con_state->freesync_capable;
5431
5432 if (new_con_state->freesync_capable) {
5433 config.state = new_crtc_state->base.vrr_enabled ?
98e6436d
AK		 5434 VRR_STATE_ACTIVE_VARIABLE :
5435 VRR_STATE_INACTIVE;
5436 config.min_refresh_in_uhz =
5437 aconnector->min_vfreq * 1000000;
5438 config.max_refresh_in_uhz =
5439 aconnector->max_vfreq * 1000000;
69ff8845 5440 config.vsif_supported = true;
180db303 5441 config.btr = true;
98e6436d
AK		 5442 }
5443
bb47de73
NK		 5444 new_crtc_state->freesync_config = config;
5445}
98e6436d 5446
bb47de73
NK		 5447static void reset_freesync_config_for_crtc(
5448 struct dm_crtc_state *new_crtc_state)
5449{
5450 new_crtc_state->vrr_supported = false;
98e6436d 5451
180db303
NK		 5452 memset(&new_crtc_state->vrr_params, 0,
5453 sizeof(new_crtc_state->vrr_params));
bb47de73
NK		 5454 memset(&new_crtc_state->vrr_infopacket, 0,
5455 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 5456}
5457
4b9674e5
LL		 5458static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
5459 struct drm_atomic_state *state,
5460 struct drm_crtc *crtc,
5461 struct drm_crtc_state *old_crtc_state,
5462 struct drm_crtc_state *new_crtc_state,
5463 bool enable,
5464 bool *lock_and_validation_needed)
e7b07cee 5465{
eb3dc897 5466 struct dm_atomic_state *dm_state = NULL;
54d76575 5467 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 5468 struct dc_stream_state *new_stream;
62f55537 5469 int ret = 0;
d4d4a645 5470
1f6010a9
DF		 5471 /*
5472 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
5473 * update changed items
5474 */
4b9674e5
LL		 5475 struct amdgpu_crtc *acrtc = NULL;
5476 struct amdgpu_dm_connector *aconnector = NULL;
5477 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
5478 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
5479 struct drm_plane_state *new_plane_state = NULL;
e7b07cee 5480
4b9674e5 5481 new_stream = NULL;
9635b754 5482
4b9674e5
LL		 5483 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5484 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5485 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 5486
4b9674e5 5487 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
f2877656 5488
4b9674e5
LL		 5489 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
5490 ret = -EINVAL;
5491 goto fail;
5492 }
f2877656 5493
4b9674e5 5494 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 5495
4b9674e5
LL		 5496 /* TODO This hack should go away */
5497 if (aconnector && enable) {
5498 /* Make sure fake sink is created in plug-in scenario */
5499 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
5500 &aconnector->base);
5501 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
5502 &aconnector->base);
19f89e23 5503
4b9674e5
LL		 5504 if (IS_ERR(drm_new_conn_state)) {
5505 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
5506 goto fail;
5507 }
19f89e23 5508
4b9674e5
LL		 5509 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
5510 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 5511
02d35a67
JFZ		 5512 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5513 goto skip_modeset;
5514
4b9674e5
LL		 5515 new_stream = create_stream_for_sink(aconnector,
5516 &new_crtc_state->mode,
5517 dm_new_conn_state,
5518 dm_old_crtc_state->stream);
19f89e23 5519
4b9674e5
LL		 5520 /*
5521 * we can have no stream on ACTION_SET if a display
5522 * was disconnected during S3, in this case it is not an
5523 * error, the OS will be updated after detection, and
5524 * will do the right thing on next atomic commit
5525 */
19f89e23 5526
4b9674e5
LL		 5527 if (!new_stream) {
5528 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5529 __func__, acrtc->base.base.id);
5530 ret = -ENOMEM;
5531 goto fail;
5532 }
e7b07cee 5533
4b9674e5 5534 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 5535
4b9674e5
LL		 5536 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
5537 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
5538 new_crtc_state->mode_changed = false;
5539 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
5540 new_crtc_state->mode_changed);
62f55537 5541 }
4b9674e5 5542 }
b830ebc9 5543
02d35a67 5544 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 5545 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5546 goto skip_modeset;
e7b07cee 5547
4b9674e5
LL		 5548 DRM_DEBUG_DRIVER(
5549 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5550 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5551 "connectors_changed:%d\n",
5552 acrtc->crtc_id,
5553 new_crtc_state->enable,
5554 new_crtc_state->active,
5555 new_crtc_state->planes_changed,
5556 new_crtc_state->mode_changed,
5557 new_crtc_state->active_changed,
5558 new_crtc_state->connectors_changed);
62f55537 5559
4b9674e5
LL		 5560 /* Remove stream for any changed/disabled CRTC */
5561 if (!enable) {
62f55537 5562
4b9674e5
LL		 5563 if (!dm_old_crtc_state->stream)
5564 goto skip_modeset;
eb3dc897 5565
4b9674e5
LL		 5566 ret = dm_atomic_get_state(state, &dm_state);
5567 if (ret)
5568 goto fail;
e7b07cee 5569
4b9674e5
LL		 5570 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
5571 crtc->base.id);
62f55537 5572
4b9674e5
LL		 5573 /* i.e. reset mode */
5574 if (dc_remove_stream_from_ctx(
5575 dm->dc,
5576 dm_state->context,
5577 dm_old_crtc_state->stream) != DC_OK) {
5578 ret = -EINVAL;
5579 goto fail;
5580 }
62f55537 5581
4b9674e5
LL		 5582 dc_stream_release(dm_old_crtc_state->stream);
5583 dm_new_crtc_state->stream = NULL;
bb47de73 5584
4b9674e5 5585 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 5586
4b9674e5 5587 *lock_and_validation_needed = true;
62f55537 5588
4b9674e5
LL		 5589 } else {/* Add stream for any updated/enabled CRTC */
5590 /*
5591 * Quick fix to prevent NULL pointer on new_stream when
5592 * added MST connectors not found in existing crtc_state in the chained mode
5593 * TODO: need to dig out the root cause of that
5594 */
5595 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
5596 goto skip_modeset;
62f55537 5597
4b9674e5
LL		 5598 if (modereset_required(new_crtc_state))
5599 goto skip_modeset;
62f55537 5600
4b9674e5
LL		 5601 if (modeset_required(new_crtc_state, new_stream,
5602 dm_old_crtc_state->stream)) {
62f55537 5603
4b9674e5 5604 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 5605
4b9674e5
LL		 5606 ret = dm_atomic_get_state(state, &dm_state);
5607 if (ret)
5608 goto fail;
27b3f4fc 5609
4b9674e5 5610 dm_new_crtc_state->stream = new_stream;
62f55537 5611
4b9674e5 5612 dc_stream_retain(new_stream);
1dc90497 5613
4b9674e5
LL		 5614 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
5615 crtc->base.id);
1dc90497 5616
4b9674e5
LL		 5617 if (dc_add_stream_to_ctx(
5618 dm->dc,
5619 dm_state->context,
5620 dm_new_crtc_state->stream) != DC_OK) {
5621 ret = -EINVAL;
5622 goto fail;
9b690ef3
BL		 5623 }
5624
4b9674e5
LL		 5625 *lock_and_validation_needed = true;
5626 }
5627 }
e277adc5 5628
4b9674e5
LL		 5629skip_modeset:
5630 /* Release extra reference */
5631 if (new_stream)
5632 dc_stream_release(new_stream);
e277adc5 5633
4b9674e5
LL		 5634 /*
5635 * We want to do dc stream updates that do not require a
5636 * full modeset below.
5637 */
5638 if (!(enable && aconnector && new_crtc_state->enable &&
5639 new_crtc_state->active))
5640 return 0;
5641 /*
5642 * Given above conditions, the dc state cannot be NULL because:
5643 * 1. We're in the process of enabling CRTCs (just been added
5644 * to the dc context, or already is on the context)
5645 * 2. Has a valid connector attached, and
5646 * 3. Is currently active and enabled.
5647 * => The dc stream state currently exists.
5648 */
5649 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 5650
4b9674e5
LL		 5651 /* Scaling or underscan settings */
5652 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
5653 update_stream_scaling_settings(
5654 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 5655
4b9674e5
LL		 5656 /*
5657 * Color management settings. We also update color properties
5658 * when a modeset is needed, to ensure it gets reprogrammed.
5659 */
5660 if (dm_new_crtc_state->base.color_mgmt_changed ||
5661 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
5662 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
5663 if (ret)
5664 goto fail;
5665 amdgpu_dm_set_ctm(dm_new_crtc_state);
62f55537 5666 }
e7b07cee 5667
4b9674e5
LL		 5668 /* Update Freesync settings. */
5669 get_freesync_config_for_crtc(dm_new_crtc_state,
5670 dm_new_conn_state);
5671
62f55537 5672 return ret;
9635b754
DS		 5673
5674fail:
5675 if (new_stream)
5676 dc_stream_release(new_stream);
5677 return ret;
62f55537 5678}
9b690ef3 5679
9e869063
LL		 5680static int dm_update_plane_state(struct dc *dc,
5681 struct drm_atomic_state *state,
5682 struct drm_plane *plane,
5683 struct drm_plane_state *old_plane_state,
5684 struct drm_plane_state *new_plane_state,
5685 bool enable,
5686 bool *lock_and_validation_needed)
62f55537 5687{
eb3dc897
NK		 5688
5689 struct dm_atomic_state *dm_state = NULL;
62f55537 5690 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 5691 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 5692 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 5693 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 5694 /* TODO return page_flip_needed() function */
5695 bool pflip_needed = !state->allow_modeset;
5696 int ret = 0;
e7b07cee 5697
9b690ef3 5698
9e869063
LL		 5699 new_plane_crtc = new_plane_state->crtc;
5700 old_plane_crtc = old_plane_state->crtc;
5701 dm_new_plane_state = to_dm_plane_state(new_plane_state);
5702 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 5703
9e869063
LL		 5704 /*TODO Implement atomic check for cursor plane */
5705 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5706 return 0;
9b690ef3 5707
9e869063
LL		 5708 /* Remove any changed/removed planes */
5709 if (!enable) {
5710 if (pflip_needed &&
5711 plane->type != DRM_PLANE_TYPE_OVERLAY)
5712 return 0;
a7b06724 5713
9e869063
LL		 5714 if (!old_plane_crtc)
5715 return 0;
62f55537 5716
9e869063
LL		 5717 old_crtc_state = drm_atomic_get_old_crtc_state(
5718 state, old_plane_crtc);
5719 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 5720
9e869063
LL		 5721 if (!dm_old_crtc_state->stream)
5722 return 0;
62f55537 5723
9e869063
LL		 5724 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
5725 plane->base.id, old_plane_crtc->base.id);
9b690ef3 5726
9e869063
LL		 5727 ret = dm_atomic_get_state(state, &dm_state);
5728 if (ret)
5729 return ret;
eb3dc897 5730
9e869063
LL		 5731 if (!dc_remove_plane_from_context(
5732 dc,
5733 dm_old_crtc_state->stream,
5734 dm_old_plane_state->dc_state,
5735 dm_state->context)) {
62f55537 5736
9e869063
LL		 5737 ret = EINVAL;
5738 return ret;
5739 }
e7b07cee 5740
9b690ef3 5741
9e869063
LL		 5742 dc_plane_state_release(dm_old_plane_state->dc_state);
5743 dm_new_plane_state->dc_state = NULL;
1dc90497 5744
9e869063 5745 *lock_and_validation_needed = true;
1dc90497 5746
9e869063
LL		 5747 } else { /* Add new planes */
5748 struct dc_plane_state *dc_new_plane_state;
1dc90497 5749
9e869063
LL		 5750 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
5751 return 0;
e7b07cee 5752
9e869063
LL		 5753 if (!new_plane_crtc)
5754 return 0;
e7b07cee 5755
9e869063
LL		 5756 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
5757 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 5758
9e869063
LL		 5759 if (!dm_new_crtc_state->stream)
5760 return 0;
62f55537 5761
9e869063
LL		 5762 if (pflip_needed && plane->type != DRM_PLANE_TYPE_OVERLAY)
5763 return 0;
62f55537 5764
9e869063 5765 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 5766
9e869063
LL		 5767 dc_new_plane_state = dc_create_plane_state(dc);
5768 if (!dc_new_plane_state)
5769 return -ENOMEM;
62f55537 5770
9e869063
LL		 5771 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5772 plane->base.id, new_plane_crtc->base.id);
8c45c5db 5773
9e869063
LL		 5774 ret = fill_plane_attributes(
5775 new_plane_crtc->dev->dev_private,
5776 dc_new_plane_state,
5777 new_plane_state,
5778 new_crtc_state);
5779 if (ret) {
5780 dc_plane_state_release(dc_new_plane_state);
5781 return ret;
5782 }
62f55537 5783
9e869063
LL		 5784 ret = dm_atomic_get_state(state, &dm_state);
5785 if (ret) {
5786 dc_plane_state_release(dc_new_plane_state);
5787 return ret;
5788 }
eb3dc897 5789
9e869063
LL		 5790 /*
5791 * Any atomic check errors that occur after this will
5792 * not need a release. The plane state will be attached
5793 * to the stream, and therefore part of the atomic
5794 * state. It'll be released when the atomic state is
5795 * cleaned.
5796 */
5797 if (!dc_add_plane_to_context(
5798 dc,
5799 dm_new_crtc_state->stream,
5800 dc_new_plane_state,
5801 dm_state->context)) {
62f55537 5802
9e869063
LL		 5803 dc_plane_state_release(dc_new_plane_state);
5804 return -EINVAL;
5805 }
8c45c5db 5806
9e869063 5807 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 5808
9e869063
LL		 5809 /* Tell DC to do a full surface update every time there
5810 * is a plane change. Inefficient, but works for now.
5811 */
5812 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5813
5814 *lock_and_validation_needed = true;
62f55537 5815 }
e7b07cee
HW		 5816
5817
62f55537
AG		 5818 return ret;
5819}
a87fa993 5820
eb3dc897
NK		 5821static int
5822dm_determine_update_type_for_commit(struct dc *dc,
5823 struct drm_atomic_state *state,
5824 enum surface_update_type *out_type)
5825{
5826 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
5827 int i, j, num_plane, ret = 0;
a87fa993
BL		 5828 struct drm_plane_state *old_plane_state, *new_plane_state;
5829 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
5830 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5831 struct drm_plane *plane;
5832
5833 struct drm_crtc *crtc;
5834 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
5835 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
5836 struct dc_stream_status *status = NULL;
5837
fe96b99d
GS		 5838 struct dc_surface_update *updates;
5839 struct dc_plane_state *surface;
a87fa993
BL		 5840 struct dc_stream_update stream_update;
5841 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5842
fe96b99d
GS		 5843 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
5844 surface = kcalloc(MAX_SURFACES, sizeof(*surface), GFP_KERNEL);
5845
4f712911
BL		 5846 if (!updates || !surface) {
5847 DRM_ERROR("Plane or surface update failed to allocate");
5848 /* Set type to FULL to avoid crashing in DC*/
5849 update_type = UPDATE_TYPE_FULL;
eb3dc897 5850 goto cleanup;
4f712911 5851 }
a87fa993
BL		 5852
5853 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5854 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5855 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
5856 num_plane = 0;
5857
5858 if (new_dm_crtc_state->stream) {
5859
5860 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5861 new_plane_crtc = new_plane_state->crtc;
5862 old_plane_crtc = old_plane_state->crtc;
5863 new_dm_plane_state = to_dm_plane_state(new_plane_state);
5864 old_dm_plane_state = to_dm_plane_state(old_plane_state);
5865
5866 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5867 continue;
5868
5869 if (!state->allow_modeset)
5870 continue;
5871
5872 if (crtc == new_plane_crtc) {
5873 updates[num_plane].surface = &surface[num_plane];
5874
5875 if (new_crtc_state->mode_changed) {
5876 updates[num_plane].surface->src_rect =
5877 new_dm_plane_state->dc_state->src_rect;
5878 updates[num_plane].surface->dst_rect =
5879 new_dm_plane_state->dc_state->dst_rect;
5880 updates[num_plane].surface->rotation =
5881 new_dm_plane_state->dc_state->rotation;
5882 updates[num_plane].surface->in_transfer_func =
5883 new_dm_plane_state->dc_state->in_transfer_func;
5884 stream_update.dst = new_dm_crtc_state->stream->dst;
5885 stream_update.src = new_dm_crtc_state->stream->src;
5886 }
5887
5888 if (new_crtc_state->color_mgmt_changed) {
5889 updates[num_plane].gamma =
5890 new_dm_plane_state->dc_state->gamma_correction;
5891 updates[num_plane].in_transfer_func =
5892 new_dm_plane_state->dc_state->in_transfer_func;
5893 stream_update.gamut_remap =
5894 &new_dm_crtc_state->stream->gamut_remap_matrix;
5895 stream_update.out_transfer_func =
5896 new_dm_crtc_state->stream->out_transfer_func;
5897 }
5898
5899 num_plane++;
5900 }
5901 }
5902
5903 if (num_plane > 0) {
eb3dc897
NK		 5904 ret = dm_atomic_get_state(state, &dm_state);
5905 if (ret)
5906 goto cleanup;
5907
5908 old_dm_state = dm_atomic_get_old_state(state);
5909 if (!old_dm_state) {
5910 ret = -EINVAL;
5911 goto cleanup;
5912 }
5913
09f609c3
LL		 5914 status = dc_stream_get_status_from_state(old_dm_state->context,
5915 new_dm_crtc_state->stream);
eb3dc897 5916
a87fa993
BL		 5917 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5918 &stream_update, status);
5919
5920 if (update_type > UPDATE_TYPE_MED) {
5921 update_type = UPDATE_TYPE_FULL;
eb3dc897 5922 goto cleanup;
a87fa993
BL		 5923 }
5924 }
5925
5926 } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) {
5927 update_type = UPDATE_TYPE_FULL;
eb3dc897 5928 goto cleanup;
a87fa993
BL		 5929 }
5930 }
5931
eb3dc897 5932cleanup:
a87fa993
BL		 5933 kfree(updates);
5934 kfree(surface);
5935
eb3dc897
NK		 5936 *out_type = update_type;
5937 return ret;
a87fa993 5938}
62f55537 5939
b8592b48
LL		 5940/**
5941 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
5942 * @dev: The DRM device
5943 * @state: The atomic state to commit
5944 *
5945 * Validate that the given atomic state is programmable by DC into hardware.
5946 * This involves constructing a &struct dc_state reflecting the new hardware
5947 * state we wish to commit, then querying DC to see if it is programmable. It's
5948 * important not to modify the existing DC state. Otherwise, atomic_check
5949 * may unexpectedly commit hardware changes.
5950 *
5951 * When validating the DC state, it's important that the right locks are
5952 * acquired. For full updates case which removes/adds/updates streams on one
5953 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
5954 * that any such full update commit will wait for completion of any outstanding
5955 * flip using DRMs synchronization events. See
5956 * dm_determine_update_type_for_commit()
5957 *
5958 * Note that DM adds the affected connectors for all CRTCs in state, when that
5959 * might not seem necessary. This is because DC stream creation requires the
5960 * DC sink, which is tied to the DRM connector state. Cleaning this up should
5961 * be possible but non-trivial - a possible TODO item.
5962 *
5963 * Return: -Error code if validation failed.
5964 */
7578ecda
AD		 5965static int amdgpu_dm_atomic_check(struct drm_device *dev,
5966 struct drm_atomic_state *state)
62f55537 5967{
62f55537 5968 struct amdgpu_device *adev = dev->dev_private;
eb3dc897 5969 struct dm_atomic_state *dm_state = NULL;
62f55537 5970 struct dc *dc = adev->dm.dc;
62f55537 5971 struct drm_connector *connector;
c2cea706 5972 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 5973 struct drm_crtc *crtc;
fc9e9920 5974 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 5975 struct drm_plane *plane;
5976 struct drm_plane_state *old_plane_state, *new_plane_state;
a87fa993
BL		 5977 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5978 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
5979
1e88ad0a 5980 int ret, i;
e7b07cee 5981
62f55537
AG		 5982 /*
5983 * This bool will be set for true for any modeset/reset
5984 * or plane update which implies non fast surface update.
5985 */
5986 bool lock_and_validation_needed = false;
5987
5988 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 5989 if (ret)
5990 goto fail;
62f55537 5991
1e88ad0a
S		 5992 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5993 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 5994 !new_crtc_state->color_mgmt_changed &&
a93587b3 5995 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
1e88ad0a 5996 continue;
7bef1af3 5997
1e88ad0a
S		 5998 if (!new_crtc_state->enable)
5999 continue;
fc9e9920 6000
1e88ad0a
S		 6001 ret = drm_atomic_add_affected_connectors(state, crtc);
6002 if (ret)
6003 return ret;
fc9e9920 6004
1e88ad0a
S		 6005 ret = drm_atomic_add_affected_planes(state, crtc);
6006 if (ret)
6007 goto fail;
e7b07cee
HW		 6008 }
6009
62f55537 6010 /* Remove exiting planes if they are modified */
9e869063
LL		 6011 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6012 ret = dm_update_plane_state(dc, state, plane,
6013 old_plane_state,
6014 new_plane_state,
6015 false,
6016 &lock_and_validation_needed);
6017 if (ret)
6018 goto fail;
62f55537
AG		 6019 }
6020
6021 /* Disable all crtcs which require disable */
4b9674e5
LL		 6022 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6023 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6024 old_crtc_state,
6025 new_crtc_state,
6026 false,
6027 &lock_and_validation_needed);
6028 if (ret)
6029 goto fail;
62f55537
AG		 6030 }
6031
6032 /* Enable all crtcs which require enable */
4b9674e5
LL		 6033 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6034 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6035 old_crtc_state,
6036 new_crtc_state,
6037 true,
6038 &lock_and_validation_needed);
6039 if (ret)
6040 goto fail;
62f55537
AG		 6041 }
6042
6043 /* Add new/modified planes */
9e869063
LL		 6044 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6045 ret = dm_update_plane_state(dc, state, plane,
6046 old_plane_state,
6047 new_plane_state,
6048 true,
6049 &lock_and_validation_needed);
6050 if (ret)
6051 goto fail;
62f55537
AG		 6052 }
6053
b349f76e
ES		 6054 /* Run this here since we want to validate the streams we created */
6055 ret = drm_atomic_helper_check_planes(dev, state);
6056 if (ret)
6057 goto fail;
62f55537 6058
ebdd27e1 6059 /* Check scaling and underscan changes*/
1f6010a9 6060 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 6061 * new stream into context w\o causing full reset. Need to
6062 * decide how to handle.
6063 */
c2cea706 6064 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 6065 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6066 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6067 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 6068
6069 /* Skip any modesets/resets */
0bc9706d
LSL		 6070 if (!acrtc || drm_atomic_crtc_needs_modeset(
6071 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 6072 continue;
6073
b830ebc9 6074 /* Skip any thing not scale or underscan changes */
54d76575 6075 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 6076 continue;
6077
a87fa993 6078 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 6079 lock_and_validation_needed = true;
6080 }
6081
eb3dc897
NK		 6082 ret = dm_determine_update_type_for_commit(dc, state, &update_type);
6083 if (ret)
6084 goto fail;
a87fa993
BL		 6085
6086 if (overall_update_type < update_type)
6087 overall_update_type = update_type;
6088
6089 /*
6090 * lock_and_validation_needed was an old way to determine if we need to set
6091 * the global lock. Leaving it in to check if we broke any corner cases
6092 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
6093 * lock_and_validation_needed false = UPDATE_TYPE_FAST
6094 */
6095 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
6096 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
6097 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
6098 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
e7b07cee 6099
e7b07cee 6100
a87fa993 6101 if (overall_update_type > UPDATE_TYPE_FAST) {
eb3dc897
NK		 6102 ret = dm_atomic_get_state(state, &dm_state);
6103 if (ret)
6104 goto fail;
e7b07cee
HW		 6105
6106 ret = do_aquire_global_lock(dev, state);
6107 if (ret)
6108 goto fail;
1dc90497 6109
e750d56d 6110 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 6111 ret = -EINVAL;
6112 goto fail;
6113 }
674e78ac
NK		 6114 } else if (state->legacy_cursor_update) {
6115 /*
6116 * This is a fast cursor update coming from the plane update
6117 * helper, check if it can be done asynchronously for better
6118 * performance.
6119 */
6120 state->async_update = !drm_atomic_helper_async_check(dev, state);
e7b07cee
HW		 6121 }
6122
6123 /* Must be success */
6124 WARN_ON(ret);
6125 return ret;
6126
6127fail:
6128 if (ret == -EDEADLK)
01e28f9c 6129 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 6130 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 6131 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 6132 else
01e28f9c 6133 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 6134
6135 return ret;
6136}
6137
3ee6b26b
AD		 6138static bool is_dp_capable_without_timing_msa(struct dc *dc,
6139 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 6140{
6141 uint8_t dpcd_data;
6142 bool capable = false;
6143
c84dec2f 6144 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 6145 dm_helpers_dp_read_dpcd(
6146 NULL,
c84dec2f 6147 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 6148 DP_DOWN_STREAM_PORT_COUNT,
6149 &dpcd_data,
6150 sizeof(dpcd_data))) {
6151 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
6152 }
6153
6154 return capable;
6155}
98e6436d
AK		 6156void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
6157 struct edid *edid)
e7b07cee
HW		 6158{
6159 int i;
e7b07cee
HW		 6160 bool edid_check_required;
6161 struct detailed_timing *timing;
6162 struct detailed_non_pixel *data;
6163 struct detailed_data_monitor_range *range;
c84dec2f
HW		 6164 struct amdgpu_dm_connector *amdgpu_dm_connector =
6165 to_amdgpu_dm_connector(connector);
bb47de73 6166 struct dm_connector_state *dm_con_state = NULL;
e7b07cee
HW		 6167
6168 struct drm_device *dev = connector->dev;
6169 struct amdgpu_device *adev = dev->dev_private;
bb47de73 6170 bool freesync_capable = false;
b830ebc9 6171
8218d7f1
HW		 6172 if (!connector->state) {
6173 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 6174 goto update;
8218d7f1
HW		 6175 }
6176
98e6436d
AK		 6177 if (!edid) {
6178 dm_con_state = to_dm_connector_state(connector->state);
6179
6180 amdgpu_dm_connector->min_vfreq = 0;
6181 amdgpu_dm_connector->max_vfreq = 0;
6182 amdgpu_dm_connector->pixel_clock_mhz = 0;
6183
bb47de73 6184 goto update;
98e6436d
AK		 6185 }
6186
8218d7f1
HW		 6187 dm_con_state = to_dm_connector_state(connector->state);
6188
e7b07cee 6189 edid_check_required = false;
c84dec2f 6190 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee 6191 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
bb47de73 6192 goto update;
e7b07cee
HW		 6193 }
6194 if (!adev->dm.freesync_module)
bb47de73 6195 goto update;
e7b07cee
HW		 6196 /*
6197 * if edid non zero restrict freesync only for dp and edp
6198 */
6199 if (edid) {
c84dec2f
HW		 6200 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
6201 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 6202 edid_check_required = is_dp_capable_without_timing_msa(
6203 adev->dm.dc,
c84dec2f 6204 amdgpu_dm_connector);
e7b07cee
HW		 6205 }
6206 }
e7b07cee
HW		 6207 if (edid_check_required == true && (edid->version > 1 ||
6208 (edid->version == 1 && edid->revision > 1))) {
6209 for (i = 0; i < 4; i++) {
6210
6211 timing = &edid->detailed_timings[i];
6212 data = &timing->data.other_data;
6213 range = &data->data.range;
6214 /*
6215 * Check if monitor has continuous frequency mode
6216 */
6217 if (data->type != EDID_DETAIL_MONITOR_RANGE)
6218 continue;
6219 /*
6220 * Check for flag range limits only. If flag == 1 then
6221 * no additional timing information provided.
6222 * Default GTF, GTF Secondary curve and CVT are not
6223 * supported
6224 */
6225 if (range->flags != 1)
6226 continue;
6227
c84dec2f
HW		 6228 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6229 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6230 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 6231 range->pixel_clock_mhz * 10;
6232 break;
6233 }
6234
c84dec2f 6235 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 6236 amdgpu_dm_connector->min_vfreq > 10) {
6237
bb47de73 6238 freesync_capable = true;
e7b07cee
HW		 6239 }
6240 }
bb47de73
NK		 6241
6242update:
6243 if (dm_con_state)
6244 dm_con_state->freesync_capable = freesync_capable;
6245
6246 if (connector->vrr_capable_property)
6247 drm_connector_set_vrr_capable_property(connector,
6248 freesync_capable);
e7b07cee
HW		 6249}
6250
Linux 6.x block layer and io_uring tree(s)