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drm/amd/display: Add connector debugfs for "output_bpc"
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
1dc90497 31#include "dc/inc/core_types.h"
a7669aff 32#include "dal_asic_id.h"
4562236b
HW		 33
34#include "vid.h"
35#include "amdgpu.h"
a49dcb88 36#include "amdgpu_display.h"
a94d5569 37#include "amdgpu_ucode.h"
4562236b
HW		 38#include "atom.h"
39#include "amdgpu_dm.h"
e7b07cee 40#include "amdgpu_pm.h"
4562236b
HW		 41
42#include "amd_shared.h"
43#include "amdgpu_dm_irq.h"
44#include "dm_helpers.h"
e7b07cee 45#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 46#if defined(CONFIG_DEBUG_FS)
47#include "amdgpu_dm_debugfs.h"
48#endif
4562236b
HW		 49
50#include "ivsrcid/ivsrcid_vislands30.h"
51
52#include <linux/module.h>
53#include <linux/moduleparam.h>
54#include <linux/version.h>
e7b07cee 55#include <linux/types.h>
97028037 56#include <linux/pm_runtime.h>
a94d5569 57#include <linux/firmware.h>
4562236b 58
e7b07cee 59#include <drm/drmP.h>
4562236b 60#include <drm/drm_atomic.h>
674e78ac 61#include <drm/drm_atomic_uapi.h>
4562236b
HW		 62#include <drm/drm_atomic_helper.h>
63#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 64#include <drm/drm_fb_helper.h>
65#include <drm/drm_edid.h>
4562236b 66
ff5ef992
AD		 67#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
68#include "ivsrcid/irqsrcs_dcn_1_0.h"
69
ad941f7a
FX		 70#include "dcn/dcn_1_0_offset.h"
71#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 72#include "soc15_hw_ip.h"
73#include "vega10_ip_offset.h"
ff5ef992
AD		 74
75#include "soc15_common.h"
76#endif
77
e7b07cee 78#include "modules/inc/mod_freesync.h"
bbf854dc 79#include "modules/power/power_helpers.h"
ecd0136b 80#include "modules/inc/mod_info_packet.h"
e7b07cee 81
a94d5569
DF		 82#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
83MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 84
b8592b48
LL		 85/**
86 * DOC: overview
87 *
88 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
89 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
90 * requests into DC requests, and DC responses into DRM responses.
91 *
92 * The root control structure is &struct amdgpu_display_manager.
93 */
94
7578ecda
AD		 95/* basic init/fini API */
96static int amdgpu_dm_init(struct amdgpu_device *adev);
97static void amdgpu_dm_fini(struct amdgpu_device *adev);
98
1f6010a9
DF		 99/*
100 * initializes drm_device display related structures, based on the information
7578ecda
AD		 101 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
102 * drm_encoder, drm_mode_config
103 *
104 * Returns 0 on success
105 */
106static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
107/* removes and deallocates the drm structures, created by the above function */
108static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
109
110static void
111amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
112
113static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 114 struct drm_plane *plane,
cc1fec57
NK		 115 unsigned long possible_crtcs,
116 const struct dc_plane_cap *plane_cap);
7578ecda
AD		 117static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
118 struct drm_plane *plane,
119 uint32_t link_index);
120static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
121 struct amdgpu_dm_connector *amdgpu_dm_connector,
122 uint32_t link_index,
123 struct amdgpu_encoder *amdgpu_encoder);
124static int amdgpu_dm_encoder_init(struct drm_device *dev,
125 struct amdgpu_encoder *aencoder,
126 uint32_t link_index);
127
128static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
129
130static int amdgpu_dm_atomic_commit(struct drm_device *dev,
131 struct drm_atomic_state *state,
132 bool nonblock);
133
134static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
135
136static int amdgpu_dm_atomic_check(struct drm_device *dev,
137 struct drm_atomic_state *state);
138
674e78ac
NK		 139static void handle_cursor_update(struct drm_plane *plane,
140 struct drm_plane_state *old_plane_state);
7578ecda 141
4562236b
HW		 142/*
143 * dm_vblank_get_counter
144 *
145 * @brief
146 * Get counter for number of vertical blanks
147 *
148 * @param
149 * struct amdgpu_device *adev - [in] desired amdgpu device
150 * int disp_idx - [in] which CRTC to get the counter from
151 *
152 * @return
153 * Counter for vertical blanks
154 */
155static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
156{
157 if (crtc >= adev->mode_info.num_crtc)
158 return 0;
159 else {
160 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 161 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
162 acrtc->base.state);
4562236b 163
da5c47f6
AG		 164
165 if (acrtc_state->stream == NULL) {
0971c40e
HW		 166 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
167 crtc);
4562236b
HW		 168 return 0;
169 }
170
da5c47f6 171 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 172 }
173}
174
175static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 176 u32 *vbl, u32 *position)
4562236b 177{
81c50963
ST		 178 uint32_t v_blank_start, v_blank_end, h_position, v_position;
179
4562236b
HW		 180 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
181 return -EINVAL;
182 else {
183 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 184 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
185 acrtc->base.state);
4562236b 186
da5c47f6 187 if (acrtc_state->stream == NULL) {
0971c40e
HW		 188 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
189 crtc);
4562236b
HW		 190 return 0;
191 }
192
81c50963
ST		 193 /*
194 * TODO rework base driver to use values directly.
195 * for now parse it back into reg-format
196 */
da5c47f6 197 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 198 &v_blank_start,
199 &v_blank_end,
200 &h_position,
201 &v_position);
202
e806208d
AG		 203 *position = v_position | (h_position << 16);
204 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 205 }
206
207 return 0;
208}
209
210static bool dm_is_idle(void *handle)
211{
212 /* XXX todo */
213 return true;
214}
215
216static int dm_wait_for_idle(void *handle)
217{
218 /* XXX todo */
219 return 0;
220}
221
222static bool dm_check_soft_reset(void *handle)
223{
224 return false;
225}
226
227static int dm_soft_reset(void *handle)
228{
229 /* XXX todo */
230 return 0;
231}
232
3ee6b26b
AD		 233static struct amdgpu_crtc *
234get_crtc_by_otg_inst(struct amdgpu_device *adev,
235 int otg_inst)
4562236b
HW		 236{
237 struct drm_device *dev = adev->ddev;
238 struct drm_crtc *crtc;
239 struct amdgpu_crtc *amdgpu_crtc;
240
4562236b
HW		 241 if (otg_inst == -1) {
242 WARN_ON(1);
243 return adev->mode_info.crtcs[0];
244 }
245
246 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
247 amdgpu_crtc = to_amdgpu_crtc(crtc);
248
249 if (amdgpu_crtc->otg_inst == otg_inst)
250 return amdgpu_crtc;
251 }
252
253 return NULL;
254}
255
66b0c973
MK		 256static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
257{
258 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
259 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
260}
261
4562236b
HW		 262static void dm_pflip_high_irq(void *interrupt_params)
263{
4562236b
HW		 264 struct amdgpu_crtc *amdgpu_crtc;
265 struct common_irq_params *irq_params = interrupt_params;
266 struct amdgpu_device *adev = irq_params->adev;
267 unsigned long flags;
71bbe51a
MK		 268 struct drm_pending_vblank_event *e;
269 struct dm_crtc_state *acrtc_state;
270 uint32_t vpos, hpos, v_blank_start, v_blank_end;
271 bool vrr_active;
4562236b
HW		 272
273 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
274
275 /* IRQ could occur when in initial stage */
1f6010a9 276 /* TODO work and BO cleanup */
4562236b
HW		 277 if (amdgpu_crtc == NULL) {
278 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
279 return;
280 }
281
282 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 283
284 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
285 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
286 amdgpu_crtc->pflip_status,
287 AMDGPU_FLIP_SUBMITTED,
288 amdgpu_crtc->crtc_id,
289 amdgpu_crtc);
290 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
291 return;
292 }
293
71bbe51a
MK		 294 /* page flip completed. */
295 e = amdgpu_crtc->event;
296 amdgpu_crtc->event = NULL;
4562236b 297
71bbe51a
MK		 298 if (!e)
299 WARN_ON(1);
1159898a 300
71bbe51a
MK		 301 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
302 vrr_active = amdgpu_dm_vrr_active(acrtc_state);
303
304 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
305 if (!vrr_active ||
306 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
307 &v_blank_end, &hpos, &vpos) ||
308 (vpos < v_blank_start)) {
309 /* Update to correct count and vblank timestamp if racing with
310 * vblank irq. This also updates to the correct vblank timestamp
311 * even in VRR mode, as scanout is past the front-porch atm.
312 */
313 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
1159898a 314
71bbe51a
MK		 315 /* Wake up userspace by sending the pageflip event with proper
316 * count and timestamp of vblank of flip completion.
317 */
318 if (e) {
319 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
320
321 /* Event sent, so done with vblank for this flip */
322 drm_crtc_vblank_put(&amdgpu_crtc->base);
323 }
324 } else if (e) {
325 /* VRR active and inside front-porch: vblank count and
326 * timestamp for pageflip event will only be up to date after
327 * drm_crtc_handle_vblank() has been executed from late vblank
328 * irq handler after start of back-porch (vline 0). We queue the
329 * pageflip event for send-out by drm_crtc_handle_vblank() with
330 * updated timestamp and count, once it runs after us.
331 *
332 * We need to open-code this instead of using the helper
333 * drm_crtc_arm_vblank_event(), as that helper would
334 * call drm_crtc_accurate_vblank_count(), which we must
335 * not call in VRR mode while we are in front-porch!
336 */
337
338 /* sequence will be replaced by real count during send-out. */
339 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
340 e->pipe = amdgpu_crtc->crtc_id;
341
342 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
343 e = NULL;
344 }
4562236b 345
fdd1fe57
MK		 346 /* Keep track of vblank of this flip for flip throttling. We use the
347 * cooked hw counter, as that one incremented at start of this vblank
348 * of pageflip completion, so last_flip_vblank is the forbidden count
349 * for queueing new pageflips if vsync + VRR is enabled.
350 */
351 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
352 amdgpu_crtc->crtc_id);
353
54f5499a 354 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 355 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
356
71bbe51a
MK		 357 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
358 amdgpu_crtc->crtc_id, amdgpu_crtc,
359 vrr_active, (int) !e);
4562236b
HW		 360}
361
d2574c33
MK		 362static void dm_vupdate_high_irq(void *interrupt_params)
363{
364 struct common_irq_params *irq_params = interrupt_params;
365 struct amdgpu_device *adev = irq_params->adev;
366 struct amdgpu_crtc *acrtc;
367 struct dm_crtc_state *acrtc_state;
09aef2c4 368 unsigned long flags;
d2574c33
MK		 369
370 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
371
372 if (acrtc) {
373 acrtc_state = to_dm_crtc_state(acrtc->base.state);
374
375 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
376 amdgpu_dm_vrr_active(acrtc_state));
377
378 /* Core vblank handling is done here after end of front-porch in
379 * vrr mode, as vblank timestamping will give valid results
380 * while now done after front-porch. This will also deliver
381 * page-flip completion events that have been queued to us
382 * if a pageflip happened inside front-porch.
383 */
09aef2c4 384 if (amdgpu_dm_vrr_active(acrtc_state)) {
d2574c33 385 drm_crtc_handle_vblank(&acrtc->base);
09aef2c4
MK		 386
387 /* BTR processing for pre-DCE12 ASICs */
388 if (acrtc_state->stream &&
389 adev->family < AMDGPU_FAMILY_AI) {
390 spin_lock_irqsave(&adev->ddev->event_lock, flags);
391 mod_freesync_handle_v_update(
392 adev->dm.freesync_module,
393 acrtc_state->stream,
394 &acrtc_state->vrr_params);
395
396 dc_stream_adjust_vmin_vmax(
397 adev->dm.dc,
398 acrtc_state->stream,
399 &acrtc_state->vrr_params.adjust);
400 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
401 }
402 }
d2574c33
MK		 403 }
404}
405
4562236b
HW		 406static void dm_crtc_high_irq(void *interrupt_params)
407{
408 struct common_irq_params *irq_params = interrupt_params;
409 struct amdgpu_device *adev = irq_params->adev;
4562236b 410 struct amdgpu_crtc *acrtc;
180db303 411 struct dm_crtc_state *acrtc_state;
09aef2c4 412 unsigned long flags;
4562236b 413
b57de80a 414 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 415
e5d0170e 416 if (acrtc) {
180db303
NK		 417 acrtc_state = to_dm_crtc_state(acrtc->base.state);
418
d2574c33
MK		 419 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
420 amdgpu_dm_vrr_active(acrtc_state));
421
422 /* Core vblank handling at start of front-porch is only possible
423 * in non-vrr mode, as only there vblank timestamping will give
424 * valid results while done in front-porch. Otherwise defer it
425 * to dm_vupdate_high_irq after end of front-porch.
426 */
427 if (!amdgpu_dm_vrr_active(acrtc_state))
428 drm_crtc_handle_vblank(&acrtc->base);
429
430 /* Following stuff must happen at start of vblank, for crc
431 * computation and below-the-range btr support in vrr mode.
432 */
433 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
434
09aef2c4 435 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
180db303
NK		 436 acrtc_state->vrr_params.supported &&
437 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
09aef2c4 438 spin_lock_irqsave(&adev->ddev->event_lock, flags);
180db303
NK		 439 mod_freesync_handle_v_update(
440 adev->dm.freesync_module,
441 acrtc_state->stream,
442 &acrtc_state->vrr_params);
443
444 dc_stream_adjust_vmin_vmax(
445 adev->dm.dc,
446 acrtc_state->stream,
447 &acrtc_state->vrr_params.adjust);
09aef2c4 448 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
180db303 449 }
e5d0170e 450 }
4562236b
HW		 451}
452
453static int dm_set_clockgating_state(void *handle,
454 enum amd_clockgating_state state)
455{
456 return 0;
457}
458
459static int dm_set_powergating_state(void *handle,
460 enum amd_powergating_state state)
461{
462 return 0;
463}
464
465/* Prototypes of private functions */
466static int dm_early_init(void* handle);
467
a32e24b4 468/* Allocate memory for FBC compressed data */
3e332d3a 469static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 470{
3e332d3a
RL		 471 struct drm_device *dev = connector->dev;
472 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 473 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 474 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
475 struct drm_display_mode *mode;
42e67c3b
RL		 476 unsigned long max_size = 0;
477
478 if (adev->dm.dc->fbc_compressor == NULL)
479 return;
a32e24b4 480
3e332d3a 481 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 482 return;
483
3e332d3a
RL		 484 if (compressor->bo_ptr)
485 return;
42e67c3b 486
42e67c3b 487
3e332d3a
RL		 488 list_for_each_entry(mode, &connector->modes, head) {
489 if (max_size < mode->htotal * mode->vtotal)
490 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 491 }
492
493 if (max_size) {
494 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 495 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 496 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 497
498 if (r)
42e67c3b
RL		 499 DRM_ERROR("DM: Failed to initialize FBC\n");
500 else {
501 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
502 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
503 }
504
a32e24b4
RL		 505 }
506
507}
a32e24b4 508
7578ecda 509static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 510{
511 struct dc_init_data init_data;
512 adev->dm.ddev = adev->ddev;
513 adev->dm.adev = adev;
514
4562236b
HW		 515 /* Zero all the fields */
516 memset(&init_data, 0, sizeof(init_data));
517
674e78ac
NK		 518 mutex_init(&adev->dm.dc_lock);
519
4562236b
HW		 520 if(amdgpu_dm_irq_init(adev)) {
521 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
522 goto error;
523 }
524
525 init_data.asic_id.chip_family = adev->family;
526
527 init_data.asic_id.pci_revision_id = adev->rev_id;
528 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
529
770d13b1 530 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 531 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
532 init_data.asic_id.atombios_base_address =
533 adev->mode_info.atom_context->bios;
534
535 init_data.driver = adev;
536
537 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
538
539 if (!adev->dm.cgs_device) {
540 DRM_ERROR("amdgpu: failed to create cgs device.\n");
541 goto error;
542 }
543
544 init_data.cgs_device = adev->dm.cgs_device;
545
4562236b
HW		 546 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
547
6e227308
HW		 548 /*
549 * TODO debug why this doesn't work on Raven
550 */
551 if (adev->flags & AMD_IS_APU &&
552 adev->asic_type >= CHIP_CARRIZO &&
553 adev->asic_type < CHIP_RAVEN)
554 init_data.flags.gpu_vm_support = true;
555
04b94af4
AD		 556 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
557 init_data.flags.fbc_support = true;
558
27eaa492
TL		 559 init_data.flags.power_down_display_on_boot = true;
560
4562236b
HW		 561 /* Display Core create. */
562 adev->dm.dc = dc_create(&init_data);
563
423788c7 564 if (adev->dm.dc) {
76121231 565 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 566 } else {
76121231 567 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 568 goto error;
569 }
4562236b 570
4562236b
HW		 571 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
572 if (!adev->dm.freesync_module) {
573 DRM_ERROR(
574 "amdgpu: failed to initialize freesync_module.\n");
575 } else
f1ad2f5e 576 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 577 adev->dm.freesync_module);
578
e277adc5
LSL		 579 amdgpu_dm_init_color_mod();
580
4562236b
HW		 581 if (amdgpu_dm_initialize_drm_device(adev)) {
582 DRM_ERROR(
583 "amdgpu: failed to initialize sw for display support.\n");
584 goto error;
585 }
586
587 /* Update the actual used number of crtc */
588 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
589
590 /* TODO: Add_display_info? */
591
592 /* TODO use dynamic cursor width */
ce75805e
AG		 593 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
594 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 595
596 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
597 DRM_ERROR(
598 "amdgpu: failed to initialize sw for display support.\n");
599 goto error;
600 }
601
e498eb71
NK		 602#if defined(CONFIG_DEBUG_FS)
603 if (dtn_debugfs_init(adev))
604 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
605#endif
606
f1ad2f5e 607 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 608
609 return 0;
610error:
611 amdgpu_dm_fini(adev);
612
59d0f396 613 return -EINVAL;
4562236b
HW		 614}
615
7578ecda 616static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 617{
618 amdgpu_dm_destroy_drm_device(&adev->dm);
c8bdf2b6
ED		 619
620 /* DC Destroy TODO: Replace destroy DAL */
621 if (adev->dm.dc)
622 dc_destroy(&adev->dm.dc);
4562236b
HW		 623 /*
624 * TODO: pageflip, vlank interrupt
625 *
626 * amdgpu_dm_irq_fini(adev);
627 */
628
629 if (adev->dm.cgs_device) {
630 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
631 adev->dm.cgs_device = NULL;
632 }
633 if (adev->dm.freesync_module) {
634 mod_freesync_destroy(adev->dm.freesync_module);
635 adev->dm.freesync_module = NULL;
636 }
674e78ac
NK		 637
638 mutex_destroy(&adev->dm.dc_lock);
639
4562236b
HW		 640 return;
641}
642
a94d5569 643static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 644{
a7669aff 645 const char *fw_name_dmcu = NULL;
a94d5569
DF		 646 int r;
647 const struct dmcu_firmware_header_v1_0 *hdr;
648
649 switch(adev->asic_type) {
650 case CHIP_BONAIRE:
651 case CHIP_HAWAII:
652 case CHIP_KAVERI:
653 case CHIP_KABINI:
654 case CHIP_MULLINS:
655 case CHIP_TONGA:
656 case CHIP_FIJI:
657 case CHIP_CARRIZO:
658 case CHIP_STONEY:
659 case CHIP_POLARIS11:
660 case CHIP_POLARIS10:
661 case CHIP_POLARIS12:
662 case CHIP_VEGAM:
663 case CHIP_VEGA10:
664 case CHIP_VEGA12:
665 case CHIP_VEGA20:
666 return 0;
667 case CHIP_RAVEN:
a7669aff
HW		 668 if (ASICREV_IS_PICASSO(adev->external_rev_id))
669 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
670 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
671 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
672 else
a7669aff 673 return 0;
a94d5569
DF		 674 break;
675 default:
676 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 677 return -EINVAL;
a94d5569
DF		 678 }
679
680 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
681 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
682 return 0;
683 }
684
685 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
686 if (r == -ENOENT) {
687 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
688 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
689 adev->dm.fw_dmcu = NULL;
690 return 0;
691 }
692 if (r) {
693 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
694 fw_name_dmcu);
695 return r;
696 }
697
698 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
699 if (r) {
700 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
701 fw_name_dmcu);
702 release_firmware(adev->dm.fw_dmcu);
703 adev->dm.fw_dmcu = NULL;
704 return r;
705 }
706
707 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
708 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
709 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
710 adev->firmware.fw_size +=
711 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
712
713 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
714 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
715 adev->firmware.fw_size +=
716 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
717
ee6e89c0
DF		 718 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
719
a94d5569
DF		 720 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
721
4562236b
HW		 722 return 0;
723}
724
a94d5569
DF		 725static int dm_sw_init(void *handle)
726{
727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
728
729 return load_dmcu_fw(adev);
730}
731
4562236b
HW		 732static int dm_sw_fini(void *handle)
733{
a94d5569
DF		 734 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
735
736 if(adev->dm.fw_dmcu) {
737 release_firmware(adev->dm.fw_dmcu);
738 adev->dm.fw_dmcu = NULL;
739 }
740
4562236b
HW		 741 return 0;
742}
743
7abcf6b5 744static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 745{
c84dec2f 746 struct amdgpu_dm_connector *aconnector;
4562236b 747 struct drm_connector *connector;
7abcf6b5 748 int ret = 0;
4562236b
HW		 749
750 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
751
752 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 753 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 754 if (aconnector->dc_link->type == dc_connection_mst_branch &&
755 aconnector->mst_mgr.aux) {
f1ad2f5e 756 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 757 aconnector, aconnector->base.base.id);
758
759 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
760 if (ret < 0) {
761 DRM_ERROR("DM_MST: Failed to start MST\n");
762 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
763 return ret;
4562236b 764 }
7abcf6b5 765 }
4562236b
HW		 766 }
767
768 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 769 return ret;
770}
771
772static int dm_late_init(void *handle)
773{
42e67c3b 774 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 775
bbf854dc
DF		 776 struct dmcu_iram_parameters params;
777 unsigned int linear_lut[16];
778 int i;
779 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
780 bool ret;
781
782 for (i = 0; i < 16; i++)
783 linear_lut[i] = 0xFFFF * i / 15;
784
785 params.set = 0;
786 params.backlight_ramping_start = 0xCCCC;
787 params.backlight_ramping_reduction = 0xCCCCCCCC;
788 params.backlight_lut_array_size = 16;
789 params.backlight_lut_array = linear_lut;
790
791 ret = dmcu_load_iram(dmcu, params);
792
793 if (!ret)
794 return -EINVAL;
795
42e67c3b 796 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 797}
798
799static void s3_handle_mst(struct drm_device *dev, bool suspend)
800{
c84dec2f 801 struct amdgpu_dm_connector *aconnector;
4562236b 802 struct drm_connector *connector;
fe7553be
LP		 803 struct drm_dp_mst_topology_mgr *mgr;
804 int ret;
805 bool need_hotplug = false;
4562236b
HW		 806
807 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
808
fe7553be
LP		 809 list_for_each_entry(connector, &dev->mode_config.connector_list,
810 head) {
811 aconnector = to_amdgpu_dm_connector(connector);
812 if (aconnector->dc_link->type != dc_connection_mst_branch ||
813 aconnector->mst_port)
814 continue;
815
816 mgr = &aconnector->mst_mgr;
817
818 if (suspend) {
819 drm_dp_mst_topology_mgr_suspend(mgr);
820 } else {
821 ret = drm_dp_mst_topology_mgr_resume(mgr);
822 if (ret < 0) {
823 drm_dp_mst_topology_mgr_set_mst(mgr, false);
824 need_hotplug = true;
825 }
826 }
4562236b
HW		 827 }
828
829 drm_modeset_unlock(&dev->mode_config.connection_mutex);
fe7553be
LP		 830
831 if (need_hotplug)
832 drm_kms_helper_hotplug_event(dev);
4562236b
HW		 833}
834
b8592b48
LL		 835/**
836 * dm_hw_init() - Initialize DC device
837 * @handle: The base driver device containing the amdpgu_dm device.
838 *
839 * Initialize the &struct amdgpu_display_manager device. This involves calling
840 * the initializers of each DM component, then populating the struct with them.
841 *
842 * Although the function implies hardware initialization, both hardware and
843 * software are initialized here. Splitting them out to their relevant init
844 * hooks is a future TODO item.
845 *
846 * Some notable things that are initialized here:
847 *
848 * - Display Core, both software and hardware
849 * - DC modules that we need (freesync and color management)
850 * - DRM software states
851 * - Interrupt sources and handlers
852 * - Vblank support
853 * - Debug FS entries, if enabled
854 */
4562236b
HW		 855static int dm_hw_init(void *handle)
856{
857 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
858 /* Create DAL display manager */
859 amdgpu_dm_init(adev);
4562236b
HW		 860 amdgpu_dm_hpd_init(adev);
861
4562236b
HW		 862 return 0;
863}
864
b8592b48
LL		 865/**
866 * dm_hw_fini() - Teardown DC device
867 * @handle: The base driver device containing the amdpgu_dm device.
868 *
869 * Teardown components within &struct amdgpu_display_manager that require
870 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
871 * were loaded. Also flush IRQ workqueues and disable them.
872 */
4562236b
HW		 873static int dm_hw_fini(void *handle)
874{
875 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
876
877 amdgpu_dm_hpd_fini(adev);
878
879 amdgpu_dm_irq_fini(adev);
21de3396 880 amdgpu_dm_fini(adev);
4562236b
HW		 881 return 0;
882}
883
884static int dm_suspend(void *handle)
885{
886 struct amdgpu_device *adev = handle;
887 struct amdgpu_display_manager *dm = &adev->dm;
888 int ret = 0;
4562236b 889
d2f0b53b
LHM		 890 WARN_ON(adev->dm.cached_state);
891 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
892
4562236b
HW		 893 s3_handle_mst(adev->ddev, true);
894
4562236b
HW		 895 amdgpu_dm_irq_suspend(adev);
896
a3621485 897
32f5062d 898 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 899
900 return ret;
901}
902
1daf8c63
AD		 903static struct amdgpu_dm_connector *
904amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
905 struct drm_crtc *crtc)
4562236b
HW		 906{
907 uint32_t i;
c2cea706 908 struct drm_connector_state *new_con_state;
4562236b
HW		 909 struct drm_connector *connector;
910 struct drm_crtc *crtc_from_state;
911
c2cea706
LSL		 912 for_each_new_connector_in_state(state, connector, new_con_state, i) {
913 crtc_from_state = new_con_state->crtc;
4562236b
HW		 914
915 if (crtc_from_state == crtc)
c84dec2f 916 return to_amdgpu_dm_connector(connector);
4562236b
HW		 917 }
918
919 return NULL;
920}
921
fbbdadf2
BL		 922static void emulated_link_detect(struct dc_link *link)
923{
924 struct dc_sink_init_data sink_init_data = { 0 };
925 struct display_sink_capability sink_caps = { 0 };
926 enum dc_edid_status edid_status;
927 struct dc_context *dc_ctx = link->ctx;
928 struct dc_sink *sink = NULL;
929 struct dc_sink *prev_sink = NULL;
930
931 link->type = dc_connection_none;
932 prev_sink = link->local_sink;
933
934 if (prev_sink != NULL)
935 dc_sink_retain(prev_sink);
936
937 switch (link->connector_signal) {
938 case SIGNAL_TYPE_HDMI_TYPE_A: {
939 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
940 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
941 break;
942 }
943
944 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
945 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
946 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
947 break;
948 }
949
950 case SIGNAL_TYPE_DVI_DUAL_LINK: {
951 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
952 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
953 break;
954 }
955
956 case SIGNAL_TYPE_LVDS: {
957 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
958 sink_caps.signal = SIGNAL_TYPE_LVDS;
959 break;
960 }
961
962 case SIGNAL_TYPE_EDP: {
963 sink_caps.transaction_type =
964 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
965 sink_caps.signal = SIGNAL_TYPE_EDP;
966 break;
967 }
968
969 case SIGNAL_TYPE_DISPLAY_PORT: {
970 sink_caps.transaction_type =
971 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
972 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
973 break;
974 }
975
976 default:
977 DC_ERROR("Invalid connector type! signal:%d\n",
978 link->connector_signal);
979 return;
980 }
981
982 sink_init_data.link = link;
983 sink_init_data.sink_signal = sink_caps.signal;
984
985 sink = dc_sink_create(&sink_init_data);
986 if (!sink) {
987 DC_ERROR("Failed to create sink!\n");
988 return;
989 }
990
dcd5fb82 991 /* dc_sink_create returns a new reference */
fbbdadf2
BL		 992 link->local_sink = sink;
993
994 edid_status = dm_helpers_read_local_edid(
995 link->ctx,
996 link,
997 sink);
998
999 if (edid_status != EDID_OK)
1000 DC_ERROR("Failed to read EDID");
1001
1002}
1003
4562236b
HW		 1004static int dm_resume(void *handle)
1005{
1006 struct amdgpu_device *adev = handle;
4562236b
HW		 1007 struct drm_device *ddev = adev->ddev;
1008 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 1009 struct amdgpu_dm_connector *aconnector;
4562236b 1010 struct drm_connector *connector;
4562236b 1011 struct drm_crtc *crtc;
c2cea706 1012 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 1013 struct dm_crtc_state *dm_new_crtc_state;
1014 struct drm_plane *plane;
1015 struct drm_plane_state *new_plane_state;
1016 struct dm_plane_state *dm_new_plane_state;
113b7a01 1017 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
fbbdadf2 1018 enum dc_connection_type new_connection_type = dc_connection_none;
a3621485 1019 int i;
4562236b 1020
113b7a01
LL		 1021 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1022 dc_release_state(dm_state->context);
1023 dm_state->context = dc_create_state(dm->dc);
1024 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1025 dc_resource_state_construct(dm->dc, dm_state->context);
1026
a80aa93d
ML		 1027 /* power on hardware */
1028 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1029
4562236b
HW		 1030 /* program HPD filter */
1031 dc_resume(dm->dc);
1032
1033 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
1034 s3_handle_mst(ddev, false);
1035
1036 /*
1037 * early enable HPD Rx IRQ, should be done before set mode as short
1038 * pulse interrupts are used for MST
1039 */
1040 amdgpu_dm_irq_resume_early(adev);
1041
4562236b 1042 /* Do detection*/
a80aa93d 1043 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 1044 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1045
1046 /*
1047 * this is the case when traversing through already created
1048 * MST connectors, should be skipped
1049 */
1050 if (aconnector->mst_port)
1051 continue;
1052
03ea364c 1053 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 1054 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1055 DRM_ERROR("KMS: Failed to detect connector\n");
1056
1057 if (aconnector->base.force && new_connection_type == dc_connection_none)
1058 emulated_link_detect(aconnector->dc_link);
1059 else
1060 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 1061
1062 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1063 aconnector->fake_enable = false;
1064
dcd5fb82
MF		 1065 if (aconnector->dc_sink)
1066 dc_sink_release(aconnector->dc_sink);
4562236b
HW		 1067 aconnector->dc_sink = NULL;
1068 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 1069 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 1070 }
1071
1f6010a9 1072 /* Force mode set in atomic commit */
a80aa93d 1073 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 1074 new_crtc_state->active_changed = true;
4f346e65 1075
fcb4019e
LSL		 1076 /*
1077 * atomic_check is expected to create the dc states. We need to release
1078 * them here, since they were duplicated as part of the suspend
1079 * procedure.
1080 */
a80aa93d 1081 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 1082 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1083 if (dm_new_crtc_state->stream) {
1084 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1085 dc_stream_release(dm_new_crtc_state->stream);
1086 dm_new_crtc_state->stream = NULL;
1087 }
1088 }
1089
a80aa93d 1090 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 1091 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1092 if (dm_new_plane_state->dc_state) {
1093 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1094 dc_plane_state_release(dm_new_plane_state->dc_state);
1095 dm_new_plane_state->dc_state = NULL;
1096 }
1097 }
1098
2d1af6a1 1099 drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 1100
a80aa93d 1101 dm->cached_state = NULL;
0a214e2f 1102
9faa4237 1103 amdgpu_dm_irq_resume_late(adev);
4562236b 1104
2d1af6a1 1105 return 0;
4562236b
HW		 1106}
1107
b8592b48
LL		 1108/**
1109 * DOC: DM Lifecycle
1110 *
1111 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1112 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1113 * the base driver's device list to be initialized and torn down accordingly.
1114 *
1115 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1116 */
1117
4562236b
HW		 1118static const struct amd_ip_funcs amdgpu_dm_funcs = {
1119 .name = "dm",
1120 .early_init = dm_early_init,
7abcf6b5 1121 .late_init = dm_late_init,
4562236b
HW		 1122 .sw_init = dm_sw_init,
1123 .sw_fini = dm_sw_fini,
1124 .hw_init = dm_hw_init,
1125 .hw_fini = dm_hw_fini,
1126 .suspend = dm_suspend,
1127 .resume = dm_resume,
1128 .is_idle = dm_is_idle,
1129 .wait_for_idle = dm_wait_for_idle,
1130 .check_soft_reset = dm_check_soft_reset,
1131 .soft_reset = dm_soft_reset,
1132 .set_clockgating_state = dm_set_clockgating_state,
1133 .set_powergating_state = dm_set_powergating_state,
1134};
1135
1136const struct amdgpu_ip_block_version dm_ip_block =
1137{
1138 .type = AMD_IP_BLOCK_TYPE_DCE,
1139 .major = 1,
1140 .minor = 0,
1141 .rev = 0,
1142 .funcs = &amdgpu_dm_funcs,
1143};
1144
ca3268c4 1145
b8592b48
LL		 1146/**
1147 * DOC: atomic
1148 *
1149 * *WIP*
1150 */
0a323b84 1151
b3663f70 1152static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 1153 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 1154 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 1155 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 1156 .atomic_commit = amdgpu_dm_atomic_commit,
54f5499a
AG		 1157};
1158
1159static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1160 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 1161};
1162
7578ecda 1163static void
3ee6b26b 1164amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1165{
1166 struct drm_connector *connector = &aconnector->base;
1167 struct drm_device *dev = connector->dev;
b73a22d3 1168 struct dc_sink *sink;
4562236b
HW		 1169
1170 /* MST handled by drm_mst framework */
1171 if (aconnector->mst_mgr.mst_state == true)
1172 return;
1173
1174
1175 sink = aconnector->dc_link->local_sink;
dcd5fb82
MF		 1176 if (sink)
1177 dc_sink_retain(sink);
4562236b 1178
1f6010a9
DF		 1179 /*
1180 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 1181 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 1182 * Skip if already done during boot.
4562236b
HW		 1183 */
1184 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1185 && aconnector->dc_em_sink) {
1186
1f6010a9
DF		 1187 /*
1188 * For S3 resume with headless use eml_sink to fake stream
1189 * because on resume connector->sink is set to NULL
4562236b
HW		 1190 */
1191 mutex_lock(&dev->mode_config.mutex);
1192
1193 if (sink) {
922aa1e1 1194 if (aconnector->dc_sink) {
98e6436d 1195 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 1196 /*
1197 * retain and release below are used to
1198 * bump up refcount for sink because the link doesn't point
1199 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 1200 * reshuffle by UMD we will get into unwanted dc_sink release
1201 */
dcd5fb82 1202 dc_sink_release(aconnector->dc_sink);
922aa1e1 1203 }
4562236b 1204 aconnector->dc_sink = sink;
dcd5fb82 1205 dc_sink_retain(aconnector->dc_sink);
98e6436d
AK		 1206 amdgpu_dm_update_freesync_caps(connector,
1207 aconnector->edid);
4562236b 1208 } else {
98e6436d 1209 amdgpu_dm_update_freesync_caps(connector, NULL);
dcd5fb82 1210 if (!aconnector->dc_sink) {
4562236b 1211 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1 1212 dc_sink_retain(aconnector->dc_sink);
dcd5fb82 1213 }
4562236b
HW		 1214 }
1215
1216 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1217
1218 if (sink)
1219 dc_sink_release(sink);
4562236b
HW		 1220 return;
1221 }
1222
1223 /*
1224 * TODO: temporary guard to look for proper fix
1225 * if this sink is MST sink, we should not do anything
1226 */
dcd5fb82
MF		 1227 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1228 dc_sink_release(sink);
4562236b 1229 return;
dcd5fb82 1230 }
4562236b
HW		 1231
1232 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 1233 /*
1234 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1235 * Do nothing!!
1236 */
f1ad2f5e 1237 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b 1238 aconnector->connector_id);
dcd5fb82
MF		 1239 if (sink)
1240 dc_sink_release(sink);
4562236b
HW		 1241 return;
1242 }
1243
f1ad2f5e 1244 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 1245 aconnector->connector_id, aconnector->dc_sink, sink);
1246
1247 mutex_lock(&dev->mode_config.mutex);
1248
1f6010a9
DF		 1249 /*
1250 * 1. Update status of the drm connector
1251 * 2. Send an event and let userspace tell us what to do
1252 */
4562236b 1253 if (sink) {
1f6010a9
DF		 1254 /*
1255 * TODO: check if we still need the S3 mode update workaround.
1256 * If yes, put it here.
1257 */
4562236b 1258 if (aconnector->dc_sink)
98e6436d 1259 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1260
1261 aconnector->dc_sink = sink;
dcd5fb82 1262 dc_sink_retain(aconnector->dc_sink);
900b3cb1 1263 if (sink->dc_edid.length == 0) {
4562236b 1264 aconnector->edid = NULL;
e86e8947 1265 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 1266 } else {
4562236b
HW		 1267 aconnector->edid =
1268 (struct edid *) sink->dc_edid.raw_edid;
1269
1270
c555f023 1271 drm_connector_update_edid_property(connector,
4562236b 1272 aconnector->edid);
e86e8947
HV		 1273 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1274 aconnector->edid);
4562236b 1275 }
98e6436d 1276 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 1277
1278 } else {
e86e8947 1279 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 1280 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 1281 drm_connector_update_edid_property(connector, NULL);
4562236b 1282 aconnector->num_modes = 0;
dcd5fb82 1283 dc_sink_release(aconnector->dc_sink);
4562236b 1284 aconnector->dc_sink = NULL;
5326c452 1285 aconnector->edid = NULL;
4562236b
HW		 1286 }
1287
1288 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1289
1290 if (sink)
1291 dc_sink_release(sink);
4562236b
HW		 1292}
1293
1294static void handle_hpd_irq(void *param)
1295{
c84dec2f 1296 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1297 struct drm_connector *connector = &aconnector->base;
1298 struct drm_device *dev = connector->dev;
fbbdadf2 1299 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1300
1f6010a9
DF		 1301 /*
1302 * In case of failure or MST no need to update connector status or notify the OS
1303 * since (for MST case) MST does this in its own context.
4562236b
HW		 1304 */
1305 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 1306
1307 if (aconnector->fake_enable)
1308 aconnector->fake_enable = false;
1309
fbbdadf2
BL		 1310 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1311 DRM_ERROR("KMS: Failed to detect connector\n");
1312
1313 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1314 emulated_link_detect(aconnector->dc_link);
1315
1316
1317 drm_modeset_lock_all(dev);
1318 dm_restore_drm_connector_state(dev, connector);
1319 drm_modeset_unlock_all(dev);
1320
1321 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1322 drm_kms_helper_hotplug_event(dev);
1323
1324 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1325 amdgpu_dm_update_connector_after_detect(aconnector);
1326
1327
1328 drm_modeset_lock_all(dev);
1329 dm_restore_drm_connector_state(dev, connector);
1330 drm_modeset_unlock_all(dev);
1331
1332 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1333 drm_kms_helper_hotplug_event(dev);
1334 }
1335 mutex_unlock(&aconnector->hpd_lock);
1336
1337}
1338
c84dec2f 1339static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1340{
1341 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1342 uint8_t dret;
1343 bool new_irq_handled = false;
1344 int dpcd_addr;
1345 int dpcd_bytes_to_read;
1346
1347 const int max_process_count = 30;
1348 int process_count = 0;
1349
1350 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1351
1352 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1353 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1354 /* DPCD 0x200 - 0x201 for downstream IRQ */
1355 dpcd_addr = DP_SINK_COUNT;
1356 } else {
1357 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1358 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1359 dpcd_addr = DP_SINK_COUNT_ESI;
1360 }
1361
1362 dret = drm_dp_dpcd_read(
1363 &aconnector->dm_dp_aux.aux,
1364 dpcd_addr,
1365 esi,
1366 dpcd_bytes_to_read);
1367
1368 while (dret == dpcd_bytes_to_read &&
1369 process_count < max_process_count) {
1370 uint8_t retry;
1371 dret = 0;
1372
1373 process_count++;
1374
f1ad2f5e 1375 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1376 /* handle HPD short pulse irq */
1377 if (aconnector->mst_mgr.mst_state)
1378 drm_dp_mst_hpd_irq(
1379 &aconnector->mst_mgr,
1380 esi,
1381 &new_irq_handled);
4562236b
HW		 1382
1383 if (new_irq_handled) {
1384 /* ACK at DPCD to notify down stream */
1385 const int ack_dpcd_bytes_to_write =
1386 dpcd_bytes_to_read - 1;
1387
1388 for (retry = 0; retry < 3; retry++) {
1389 uint8_t wret;
1390
1391 wret = drm_dp_dpcd_write(
1392 &aconnector->dm_dp_aux.aux,
1393 dpcd_addr + 1,
1394 &esi[1],
1395 ack_dpcd_bytes_to_write);
1396 if (wret == ack_dpcd_bytes_to_write)
1397 break;
1398 }
1399
1f6010a9 1400 /* check if there is new irq to be handled */
4562236b
HW		 1401 dret = drm_dp_dpcd_read(
1402 &aconnector->dm_dp_aux.aux,
1403 dpcd_addr,
1404 esi,
1405 dpcd_bytes_to_read);
1406
1407 new_irq_handled = false;
d4a6e8a9 1408 } else {
4562236b 1409 break;
d4a6e8a9 1410 }
4562236b
HW		 1411 }
1412
1413 if (process_count == max_process_count)
f1ad2f5e 1414 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1415}
1416
1417static void handle_hpd_rx_irq(void *param)
1418{
c84dec2f 1419 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1420 struct drm_connector *connector = &aconnector->base;
1421 struct drm_device *dev = connector->dev;
53cbf65c 1422 struct dc_link *dc_link = aconnector->dc_link;
4562236b 1423 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
fbbdadf2 1424 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1425
1f6010a9
DF		 1426 /*
1427 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 1428 * conflict, after implement i2c helper, this mutex should be
1429 * retired.
1430 */
53cbf65c 1431 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1432 mutex_lock(&aconnector->hpd_lock);
1433
4e18814e 1434 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1435 !is_mst_root_connector) {
1436 /* Downstream Port status changed. */
fbbdadf2
BL		 1437 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1438 DRM_ERROR("KMS: Failed to detect connector\n");
1439
1440 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1441 emulated_link_detect(dc_link);
1442
1443 if (aconnector->fake_enable)
1444 aconnector->fake_enable = false;
1445
1446 amdgpu_dm_update_connector_after_detect(aconnector);
1447
1448
1449 drm_modeset_lock_all(dev);
1450 dm_restore_drm_connector_state(dev, connector);
1451 drm_modeset_unlock_all(dev);
1452
1453 drm_kms_helper_hotplug_event(dev);
1454 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1455
1456 if (aconnector->fake_enable)
1457 aconnector->fake_enable = false;
1458
4562236b
HW		 1459 amdgpu_dm_update_connector_after_detect(aconnector);
1460
1461
1462 drm_modeset_lock_all(dev);
1463 dm_restore_drm_connector_state(dev, connector);
1464 drm_modeset_unlock_all(dev);
1465
1466 drm_kms_helper_hotplug_event(dev);
1467 }
1468 }
1469 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1470 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1471 dm_handle_hpd_rx_irq(aconnector);
1472
e86e8947
HV		 1473 if (dc_link->type != dc_connection_mst_branch) {
1474 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 1475 mutex_unlock(&aconnector->hpd_lock);
e86e8947 1476 }
4562236b
HW		 1477}
1478
1479static void register_hpd_handlers(struct amdgpu_device *adev)
1480{
1481 struct drm_device *dev = adev->ddev;
1482 struct drm_connector *connector;
c84dec2f 1483 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1484 const struct dc_link *dc_link;
1485 struct dc_interrupt_params int_params = {0};
1486
1487 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1488 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1489
1490 list_for_each_entry(connector,
1491 &dev->mode_config.connector_list, head) {
1492
c84dec2f 1493 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1494 dc_link = aconnector->dc_link;
1495
1496 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1497 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1498 int_params.irq_source = dc_link->irq_source_hpd;
1499
1500 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1501 handle_hpd_irq,
1502 (void *) aconnector);
1503 }
1504
1505 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1506
1507 /* Also register for DP short pulse (hpd_rx). */
1508 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1509 int_params.irq_source = dc_link->irq_source_hpd_rx;
1510
1511 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1512 handle_hpd_rx_irq,
1513 (void *) aconnector);
1514 }
1515 }
1516}
1517
1518/* Register IRQ sources and initialize IRQ callbacks */
1519static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1520{
1521 struct dc *dc = adev->dm.dc;
1522 struct common_irq_params *c_irq_params;
1523 struct dc_interrupt_params int_params = {0};
1524 int r;
1525 int i;
1ffdeca6 1526 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 1527
ff5ef992 1528 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1529 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1530 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1531 adev->asic_type == CHIP_RAVEN)
3760f76c 1532 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1533
1534 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1535 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1536
1f6010a9
DF		 1537 /*
1538 * Actions of amdgpu_irq_add_id():
4562236b
HW		 1539 * 1. Register a set() function with base driver.
1540 * Base driver will call set() function to enable/disable an
1541 * interrupt in DC hardware.
1542 * 2. Register amdgpu_dm_irq_handler().
1543 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1544 * coming from DC hardware.
1545 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1546 * for acknowledging and handling. */
1547
b57de80a 1548 /* Use VBLANK interrupt */
e9029155 1549 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1550 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1551 if (r) {
1552 DRM_ERROR("Failed to add crtc irq id!\n");
1553 return r;
1554 }
1555
1556 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1557 int_params.irq_source =
3d761e79 1558 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1559
b57de80a 1560 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1561
1562 c_irq_params->adev = adev;
1563 c_irq_params->irq_src = int_params.irq_source;
1564
1565 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1566 dm_crtc_high_irq, c_irq_params);
1567 }
1568
d2574c33
MK		 1569 /* Use VUPDATE interrupt */
1570 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
1571 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
1572 if (r) {
1573 DRM_ERROR("Failed to add vupdate irq id!\n");
1574 return r;
1575 }
1576
1577 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1578 int_params.irq_source =
1579 dc_interrupt_to_irq_source(dc, i, 0);
1580
1581 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1582
1583 c_irq_params->adev = adev;
1584 c_irq_params->irq_src = int_params.irq_source;
1585
1586 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1587 dm_vupdate_high_irq, c_irq_params);
1588 }
1589
3d761e79 1590 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1591 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1592 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1593 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1594 if (r) {
1595 DRM_ERROR("Failed to add page flip irq id!\n");
1596 return r;
1597 }
1598
1599 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1600 int_params.irq_source =
1601 dc_interrupt_to_irq_source(dc, i, 0);
1602
1603 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1604
1605 c_irq_params->adev = adev;
1606 c_irq_params->irq_src = int_params.irq_source;
1607
1608 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1609 dm_pflip_high_irq, c_irq_params);
1610
1611 }
1612
1613 /* HPD */
2c8ad2d5
AD		 1614 r = amdgpu_irq_add_id(adev, client_id,
1615 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1616 if (r) {
1617 DRM_ERROR("Failed to add hpd irq id!\n");
1618 return r;
1619 }
1620
1621 register_hpd_handlers(adev);
1622
1623 return 0;
1624}
1625
ff5ef992
AD		 1626#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1627/* Register IRQ sources and initialize IRQ callbacks */
1628static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1629{
1630 struct dc *dc = adev->dm.dc;
1631 struct common_irq_params *c_irq_params;
1632 struct dc_interrupt_params int_params = {0};
1633 int r;
1634 int i;
1635
1636 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1637 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1638
1f6010a9
DF		 1639 /*
1640 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 1641 * 1. Register a set() function with base driver.
1642 * Base driver will call set() function to enable/disable an
1643 * interrupt in DC hardware.
1644 * 2. Register amdgpu_dm_irq_handler().
1645 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1646 * coming from DC hardware.
1647 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1648 * for acknowledging and handling.
1f6010a9 1649 */
ff5ef992
AD		 1650
1651 /* Use VSTARTUP interrupt */
1652 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1653 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1654 i++) {
3760f76c 1655 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1656
1657 if (r) {
1658 DRM_ERROR("Failed to add crtc irq id!\n");
1659 return r;
1660 }
1661
1662 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1663 int_params.irq_source =
1664 dc_interrupt_to_irq_source(dc, i, 0);
1665
1666 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1667
1668 c_irq_params->adev = adev;
1669 c_irq_params->irq_src = int_params.irq_source;
1670
1671 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1672 dm_crtc_high_irq, c_irq_params);
1673 }
1674
d2574c33
MK		 1675 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
1676 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
1677 * to trigger at end of each vblank, regardless of state of the lock,
1678 * matching DCE behaviour.
1679 */
1680 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
1681 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
1682 i++) {
1683 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
1684
1685 if (r) {
1686 DRM_ERROR("Failed to add vupdate irq id!\n");
1687 return r;
1688 }
1689
1690 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1691 int_params.irq_source =
1692 dc_interrupt_to_irq_source(dc, i, 0);
1693
1694 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1695
1696 c_irq_params->adev = adev;
1697 c_irq_params->irq_src = int_params.irq_source;
1698
1699 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1700 dm_vupdate_high_irq, c_irq_params);
1701 }
1702
ff5ef992
AD		 1703 /* Use GRPH_PFLIP interrupt */
1704 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1705 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1706 i++) {
3760f76c 1707 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1708 if (r) {
1709 DRM_ERROR("Failed to add page flip irq id!\n");
1710 return r;
1711 }
1712
1713 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1714 int_params.irq_source =
1715 dc_interrupt_to_irq_source(dc, i, 0);
1716
1717 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1718
1719 c_irq_params->adev = adev;
1720 c_irq_params->irq_src = int_params.irq_source;
1721
1722 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1723 dm_pflip_high_irq, c_irq_params);
1724
1725 }
1726
1727 /* HPD */
3760f76c 1728 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1729 &adev->hpd_irq);
1730 if (r) {
1731 DRM_ERROR("Failed to add hpd irq id!\n");
1732 return r;
1733 }
1734
1735 register_hpd_handlers(adev);
1736
1737 return 0;
1738}
1739#endif
1740
eb3dc897
NK		 1741/*
1742 * Acquires the lock for the atomic state object and returns
1743 * the new atomic state.
1744 *
1745 * This should only be called during atomic check.
1746 */
1747static int dm_atomic_get_state(struct drm_atomic_state *state,
1748 struct dm_atomic_state **dm_state)
1749{
1750 struct drm_device *dev = state->dev;
1751 struct amdgpu_device *adev = dev->dev_private;
1752 struct amdgpu_display_manager *dm = &adev->dm;
1753 struct drm_private_state *priv_state;
eb3dc897
NK		 1754
1755 if (*dm_state)
1756 return 0;
1757
eb3dc897
NK		 1758 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1759 if (IS_ERR(priv_state))
1760 return PTR_ERR(priv_state);
1761
1762 *dm_state = to_dm_atomic_state(priv_state);
1763
1764 return 0;
1765}
1766
1767struct dm_atomic_state *
1768dm_atomic_get_new_state(struct drm_atomic_state *state)
1769{
1770 struct drm_device *dev = state->dev;
1771 struct amdgpu_device *adev = dev->dev_private;
1772 struct amdgpu_display_manager *dm = &adev->dm;
1773 struct drm_private_obj *obj;
1774 struct drm_private_state *new_obj_state;
1775 int i;
1776
1777 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1778 if (obj->funcs == dm->atomic_obj.funcs)
1779 return to_dm_atomic_state(new_obj_state);
1780 }
1781
1782 return NULL;
1783}
1784
1785struct dm_atomic_state *
1786dm_atomic_get_old_state(struct drm_atomic_state *state)
1787{
1788 struct drm_device *dev = state->dev;
1789 struct amdgpu_device *adev = dev->dev_private;
1790 struct amdgpu_display_manager *dm = &adev->dm;
1791 struct drm_private_obj *obj;
1792 struct drm_private_state *old_obj_state;
1793 int i;
1794
1795 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1796 if (obj->funcs == dm->atomic_obj.funcs)
1797 return to_dm_atomic_state(old_obj_state);
1798 }
1799
1800 return NULL;
1801}
1802
1803static struct drm_private_state *
1804dm_atomic_duplicate_state(struct drm_private_obj *obj)
1805{
1806 struct dm_atomic_state *old_state, *new_state;
1807
1808 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1809 if (!new_state)
1810 return NULL;
1811
1812 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1813
813d20dc
AW		 1814 old_state = to_dm_atomic_state(obj->state);
1815
1816 if (old_state && old_state->context)
1817 new_state->context = dc_copy_state(old_state->context);
1818
eb3dc897
NK		 1819 if (!new_state->context) {
1820 kfree(new_state);
1821 return NULL;
1822 }
1823
eb3dc897
NK		 1824 return &new_state->base;
1825}
1826
1827static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1828 struct drm_private_state *state)
1829{
1830 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1831
1832 if (dm_state && dm_state->context)
1833 dc_release_state(dm_state->context);
1834
1835 kfree(dm_state);
1836}
1837
1838static struct drm_private_state_funcs dm_atomic_state_funcs = {
1839 .atomic_duplicate_state = dm_atomic_duplicate_state,
1840 .atomic_destroy_state = dm_atomic_destroy_state,
1841};
1842
4562236b
HW		 1843static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1844{
eb3dc897 1845 struct dm_atomic_state *state;
4562236b
HW		 1846 int r;
1847
1848 adev->mode_info.mode_config_initialized = true;
1849
4562236b 1850 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1851 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1852
1853 adev->ddev->mode_config.max_width = 16384;
1854 adev->ddev->mode_config.max_height = 16384;
1855
1856 adev->ddev->mode_config.preferred_depth = 24;
1857 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 1858 /* indicates support for immediate flip */
4562236b
HW		 1859 adev->ddev->mode_config.async_page_flip = true;
1860
770d13b1 1861 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1862
eb3dc897
NK		 1863 state = kzalloc(sizeof(*state), GFP_KERNEL);
1864 if (!state)
1865 return -ENOMEM;
1866
813d20dc 1867 state->context = dc_create_state(adev->dm.dc);
eb3dc897
NK		 1868 if (!state->context) {
1869 kfree(state);
1870 return -ENOMEM;
1871 }
1872
1873 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1874
8c1a765b
DA		 1875 drm_atomic_private_obj_init(adev->ddev,
1876 &adev->dm.atomic_obj,
eb3dc897
NK		 1877 &state->base,
1878 &dm_atomic_state_funcs);
1879
3dc9b1ce 1880 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1881 if (r)
1882 return r;
1883
1884 return 0;
1885}
1886
206bbafe
DF		 1887#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1888#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1889
4562236b
HW		 1890#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1891 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1892
206bbafe
DF		 1893static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1894{
1895#if defined(CONFIG_ACPI)
1896 struct amdgpu_dm_backlight_caps caps;
1897
1898 if (dm->backlight_caps.caps_valid)
1899 return;
1900
1901 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1902 if (caps.caps_valid) {
1903 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1904 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1905 dm->backlight_caps.caps_valid = true;
1906 } else {
1907 dm->backlight_caps.min_input_signal =
1908 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1909 dm->backlight_caps.max_input_signal =
1910 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1911 }
1912#else
8bcbc9ef
DF		 1913 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1914 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 1915#endif
1916}
1917
4562236b
HW		 1918static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1919{
1920 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe
DF		 1921 struct amdgpu_dm_backlight_caps caps;
1922 uint32_t brightness = bd->props.brightness;
4562236b 1923
206bbafe
DF		 1924 amdgpu_dm_update_backlight_caps(dm);
1925 caps = dm->backlight_caps;
0cafc82f 1926 /*
206bbafe
DF		 1927 * The brightness input is in the range 0-255
1928 * It needs to be rescaled to be between the
1929 * requested min and max input signal
1930 *
1931 * It also needs to be scaled up by 0x101 to
1932 * match the DC interface which has a range of
1933 * 0 to 0xffff
0cafc82f 1934 */
206bbafe
DF		 1935 brightness =
1936 brightness
1937 * 0x101
1938 * (caps.max_input_signal - caps.min_input_signal)
1939 / AMDGPU_MAX_BL_LEVEL
1940 + caps.min_input_signal * 0x101;
4562236b
HW		 1941
1942 if (dc_link_set_backlight_level(dm->backlight_link,
923fe495 1943 brightness, 0))
4562236b
HW		 1944 return 0;
1945 else
1946 return 1;
1947}
1948
1949static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1950{
620a0d27
DF		 1951 struct amdgpu_display_manager *dm = bl_get_data(bd);
1952 int ret = dc_link_get_backlight_level(dm->backlight_link);
1953
1954 if (ret == DC_ERROR_UNEXPECTED)
1955 return bd->props.brightness;
1956 return ret;
4562236b
HW		 1957}
1958
1959static const struct backlight_ops amdgpu_dm_backlight_ops = {
1960 .get_brightness = amdgpu_dm_backlight_get_brightness,
1961 .update_status = amdgpu_dm_backlight_update_status,
1962};
1963
7578ecda
AD		 1964static void
1965amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1966{
1967 char bl_name[16];
1968 struct backlight_properties props = { 0 };
1969
206bbafe
DF		 1970 amdgpu_dm_update_backlight_caps(dm);
1971
4562236b 1972 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 1973 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 1974 props.type = BACKLIGHT_RAW;
1975
1976 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1977 dm->adev->ddev->primary->index);
1978
1979 dm->backlight_dev = backlight_device_register(bl_name,
1980 dm->adev->ddev->dev,
1981 dm,
1982 &amdgpu_dm_backlight_ops,
1983 &props);
1984
74baea42 1985 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1986 DRM_ERROR("DM: Backlight registration failed!\n");
1987 else
f1ad2f5e 1988 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1989}
1990
1991#endif
1992
df534fff 1993static int initialize_plane(struct amdgpu_display_manager *dm,
b2fddb13 1994 struct amdgpu_mode_info *mode_info, int plane_id,
cc1fec57
NK		 1995 enum drm_plane_type plane_type,
1996 const struct dc_plane_cap *plane_cap)
df534fff 1997{
f180b4bc 1998 struct drm_plane *plane;
df534fff
S		 1999 unsigned long possible_crtcs;
2000 int ret = 0;
2001
f180b4bc 2002 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 2003 if (!plane) {
2004 DRM_ERROR("KMS: Failed to allocate plane\n");
2005 return -ENOMEM;
2006 }
b2fddb13 2007 plane->type = plane_type;
df534fff
S		 2008
2009 /*
b2fddb13
NK		 2010 * HACK: IGT tests expect that the primary plane for a CRTC
2011 * can only have one possible CRTC. Only expose support for
2012 * any CRTC if they're not going to be used as a primary plane
2013 * for a CRTC - like overlay or underlay planes.
df534fff
S		 2014 */
2015 possible_crtcs = 1 << plane_id;
2016 if (plane_id >= dm->dc->caps.max_streams)
2017 possible_crtcs = 0xff;
2018
cc1fec57 2019 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
df534fff
S		 2020
2021 if (ret) {
2022 DRM_ERROR("KMS: Failed to initialize plane\n");
54087768 2023 kfree(plane);
df534fff
S		 2024 return ret;
2025 }
2026
54087768
NK		 2027 if (mode_info)
2028 mode_info->planes[plane_id] = plane;
2029
df534fff
S		 2030 return ret;
2031}
2032
89fc8d4e
HW		 2033
2034static void register_backlight_device(struct amdgpu_display_manager *dm,
2035 struct dc_link *link)
2036{
2037#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2038 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2039
2040 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2041 link->type != dc_connection_none) {
1f6010a9
DF		 2042 /*
2043 * Event if registration failed, we should continue with
89fc8d4e
HW		 2044 * DM initialization because not having a backlight control
2045 * is better then a black screen.
2046 */
2047 amdgpu_dm_register_backlight_device(dm);
2048
2049 if (dm->backlight_dev)
2050 dm->backlight_link = link;
2051 }
2052#endif
2053}
2054
2055
1f6010a9
DF		 2056/*
2057 * In this architecture, the association
4562236b
HW		 2058 * connector -> encoder -> crtc
2059 * id not really requried. The crtc and connector will hold the
2060 * display_index as an abstraction to use with DAL component
2061 *
2062 * Returns 0 on success
2063 */
7578ecda 2064static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 2065{
2066 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 2067 int32_t i;
c84dec2f 2068 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 2069 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 2070 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 2071 uint32_t link_cnt;
cc1fec57 2072 int32_t primary_planes;
fbbdadf2 2073 enum dc_connection_type new_connection_type = dc_connection_none;
cc1fec57 2074 const struct dc_plane_cap *plane;
4562236b
HW		 2075
2076 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 2077 if (amdgpu_dm_mode_config_init(dm->adev)) {
2078 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 2079 return -EINVAL;
4562236b
HW		 2080 }
2081
b2fddb13
NK		 2082 /* There is one primary plane per CRTC */
2083 primary_planes = dm->dc->caps.max_streams;
54087768 2084 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
efa6a8b7 2085
b2fddb13
NK		 2086 /*
2087 * Initialize primary planes, implicit planes for legacy IOCTLS.
2088 * Order is reversed to match iteration order in atomic check.
2089 */
2090 for (i = (primary_planes - 1); i >= 0; i--) {
cc1fec57
NK		 2091 plane = &dm->dc->caps.planes[i];
2092
b2fddb13 2093 if (initialize_plane(dm, mode_info, i,
cc1fec57 2094 DRM_PLANE_TYPE_PRIMARY, plane)) {
df534fff 2095 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 2096 goto fail;
d4e13b0d 2097 }
df534fff 2098 }
92f3ac40 2099
0d579c7e
NK		 2100 /*
2101 * Initialize overlay planes, index starting after primary planes.
2102 * These planes have a higher DRM index than the primary planes since
2103 * they should be considered as having a higher z-order.
2104 * Order is reversed to match iteration order in atomic check.
cc1fec57
NK		 2105 *
2106 * Only support DCN for now, and only expose one so we don't encourage
2107 * userspace to use up all the pipes.
0d579c7e 2108 */
cc1fec57
NK		 2109 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2110 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2111
2112 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2113 continue;
2114
2115 if (!plane->blends_with_above || !plane->blends_with_below)
2116 continue;
2117
ea36ad34 2118 if (!plane->pixel_format_support.argb8888)
cc1fec57
NK		 2119 continue;
2120
54087768 2121 if (initialize_plane(dm, NULL, primary_planes + i,
cc1fec57 2122 DRM_PLANE_TYPE_OVERLAY, plane)) {
0d579c7e 2123 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 2124 goto fail;
d4e13b0d 2125 }
cc1fec57
NK		 2126
2127 /* Only create one overlay plane. */
2128 break;
d4e13b0d 2129 }
4562236b 2130
d4e13b0d 2131 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 2132 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 2133 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 2134 goto fail;
4562236b 2135 }
4562236b 2136
ab2541b6 2137 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 2138
2139 /* loops over all connectors on the board */
2140 for (i = 0; i < link_cnt; i++) {
89fc8d4e 2141 struct dc_link *link = NULL;
4562236b
HW		 2142
2143 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2144 DRM_ERROR(
2145 "KMS: Cannot support more than %d display indexes\n",
2146 AMDGPU_DM_MAX_DISPLAY_INDEX);
2147 continue;
2148 }
2149
2150 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2151 if (!aconnector)
cd8a2ae8 2152 goto fail;
4562236b
HW		 2153
2154 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 2155 if (!aencoder)
cd8a2ae8 2156 goto fail;
4562236b
HW		 2157
2158 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2159 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 2160 goto fail;
4562236b
HW		 2161 }
2162
2163 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2164 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 2165 goto fail;
4562236b
HW		 2166 }
2167
89fc8d4e
HW		 2168 link = dc_get_link_at_index(dm->dc, i);
2169
fbbdadf2
BL		 2170 if (!dc_link_detect_sink(link, &new_connection_type))
2171 DRM_ERROR("KMS: Failed to detect connector\n");
2172
2173 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2174 emulated_link_detect(link);
2175 amdgpu_dm_update_connector_after_detect(aconnector);
2176
2177 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 2178 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 2179 register_backlight_device(dm, link);
2180 }
2181
2182
4562236b
HW		 2183 }
2184
2185 /* Software is initialized. Now we can register interrupt handlers. */
2186 switch (adev->asic_type) {
2187 case CHIP_BONAIRE:
2188 case CHIP_HAWAII:
cd4b356f
AD		 2189 case CHIP_KAVERI:
2190 case CHIP_KABINI:
2191 case CHIP_MULLINS:
4562236b
HW		 2192 case CHIP_TONGA:
2193 case CHIP_FIJI:
2194 case CHIP_CARRIZO:
2195 case CHIP_STONEY:
2196 case CHIP_POLARIS11:
2197 case CHIP_POLARIS10:
b264d345 2198 case CHIP_POLARIS12:
7737de91 2199 case CHIP_VEGAM:
2c8ad2d5 2200 case CHIP_VEGA10:
2325ff30 2201 case CHIP_VEGA12:
1fe6bf2f 2202 case CHIP_VEGA20:
4562236b
HW		 2203 if (dce110_register_irq_handlers(dm->adev)) {
2204 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2205 goto fail;
4562236b
HW		 2206 }
2207 break;
ff5ef992
AD		 2208#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2209 case CHIP_RAVEN:
2210 if (dcn10_register_irq_handlers(dm->adev)) {
2211 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2212 goto fail;
ff5ef992
AD		 2213 }
2214 break;
2215#endif
4562236b 2216 default:
e63f8673 2217 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 2218 goto fail;
4562236b
HW		 2219 }
2220
1bc460a4
HW		 2221 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2222 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2223
4562236b 2224 return 0;
cd8a2ae8 2225fail:
4562236b 2226 kfree(aencoder);
4562236b 2227 kfree(aconnector);
54087768 2228
59d0f396 2229 return -EINVAL;
4562236b
HW		 2230}
2231
7578ecda 2232static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2233{
2234 drm_mode_config_cleanup(dm->ddev);
eb3dc897 2235 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 2236 return;
2237}
2238
2239/******************************************************************************
2240 * amdgpu_display_funcs functions
2241 *****************************************************************************/
2242
1f6010a9 2243/*
4562236b
HW		 2244 * dm_bandwidth_update - program display watermarks
2245 *
2246 * @adev: amdgpu_device pointer
2247 *
2248 * Calculate and program the display watermarks and line buffer allocation.
2249 */
2250static void dm_bandwidth_update(struct amdgpu_device *adev)
2251{
49c07a99 2252 /* TODO: implement later */
4562236b
HW		 2253}
2254
39cc5be2 2255static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 2256 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2257 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 2258 .backlight_set_level = NULL, /* never called for DC */
2259 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 2260 .hpd_sense = NULL,/* called unconditionally */
2261 .hpd_set_polarity = NULL, /* called unconditionally */
2262 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2263 .page_flip_get_scanoutpos =
2264 dm_crtc_get_scanoutpos,/* called unconditionally */
2265 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2266 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2267};
2268
2269#if defined(CONFIG_DEBUG_KERNEL_DC)
2270
3ee6b26b
AD		 2271static ssize_t s3_debug_store(struct device *device,
2272 struct device_attribute *attr,
2273 const char *buf,
2274 size_t count)
4562236b
HW		 2275{
2276 int ret;
2277 int s3_state;
2278 struct pci_dev *pdev = to_pci_dev(device);
2279 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2280 struct amdgpu_device *adev = drm_dev->dev_private;
2281
2282 ret = kstrtoint(buf, 0, &s3_state);
2283
2284 if (ret == 0) {
2285 if (s3_state) {
2286 dm_resume(adev);
4562236b
HW		 2287 drm_kms_helper_hotplug_event(adev->ddev);
2288 } else
2289 dm_suspend(adev);
2290 }
2291
2292 return ret == 0 ? count : 0;
2293}
2294
2295DEVICE_ATTR_WO(s3_debug);
2296
2297#endif
2298
2299static int dm_early_init(void *handle)
2300{
2301 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2302
4562236b
HW		 2303 switch (adev->asic_type) {
2304 case CHIP_BONAIRE:
2305 case CHIP_HAWAII:
2306 adev->mode_info.num_crtc = 6;
2307 adev->mode_info.num_hpd = 6;
2308 adev->mode_info.num_dig = 6;
4562236b 2309 break;
cd4b356f
AD		 2310 case CHIP_KAVERI:
2311 adev->mode_info.num_crtc = 4;
2312 adev->mode_info.num_hpd = 6;
2313 adev->mode_info.num_dig = 7;
cd4b356f
AD		 2314 break;
2315 case CHIP_KABINI:
2316 case CHIP_MULLINS:
2317 adev->mode_info.num_crtc = 2;
2318 adev->mode_info.num_hpd = 6;
2319 adev->mode_info.num_dig = 6;
cd4b356f 2320 break;
4562236b
HW		 2321 case CHIP_FIJI:
2322 case CHIP_TONGA:
2323 adev->mode_info.num_crtc = 6;
2324 adev->mode_info.num_hpd = 6;
2325 adev->mode_info.num_dig = 7;
4562236b
HW		 2326 break;
2327 case CHIP_CARRIZO:
2328 adev->mode_info.num_crtc = 3;
2329 adev->mode_info.num_hpd = 6;
2330 adev->mode_info.num_dig = 9;
4562236b
HW		 2331 break;
2332 case CHIP_STONEY:
2333 adev->mode_info.num_crtc = 2;
2334 adev->mode_info.num_hpd = 6;
2335 adev->mode_info.num_dig = 9;
4562236b
HW		 2336 break;
2337 case CHIP_POLARIS11:
b264d345 2338 case CHIP_POLARIS12:
4562236b
HW		 2339 adev->mode_info.num_crtc = 5;
2340 adev->mode_info.num_hpd = 5;
2341 adev->mode_info.num_dig = 5;
4562236b
HW		 2342 break;
2343 case CHIP_POLARIS10:
7737de91 2344 case CHIP_VEGAM:
4562236b
HW		 2345 adev->mode_info.num_crtc = 6;
2346 adev->mode_info.num_hpd = 6;
2347 adev->mode_info.num_dig = 6;
4562236b 2348 break;
2c8ad2d5 2349 case CHIP_VEGA10:
2325ff30 2350 case CHIP_VEGA12:
1fe6bf2f 2351 case CHIP_VEGA20:
2c8ad2d5
AD		 2352 adev->mode_info.num_crtc = 6;
2353 adev->mode_info.num_hpd = 6;
2354 adev->mode_info.num_dig = 6;
2355 break;
ff5ef992
AD		 2356#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2357 case CHIP_RAVEN:
2358 adev->mode_info.num_crtc = 4;
2359 adev->mode_info.num_hpd = 4;
2360 adev->mode_info.num_dig = 4;
ff5ef992
AD		 2361 break;
2362#endif
4562236b 2363 default:
e63f8673 2364 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 2365 return -EINVAL;
2366 }
2367
c8dd5715
MD		 2368 amdgpu_dm_set_irq_funcs(adev);
2369
39cc5be2
AD		 2370 if (adev->mode_info.funcs == NULL)
2371 adev->mode_info.funcs = &dm_display_funcs;
2372
1f6010a9
DF		 2373 /*
2374 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 2375 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 2376 * amdgpu_device_init()
2377 */
4562236b
HW		 2378#if defined(CONFIG_DEBUG_KERNEL_DC)
2379 device_create_file(
2380 adev->ddev->dev,
2381 &dev_attr_s3_debug);
2382#endif
2383
2384 return 0;
2385}
2386
9b690ef3 2387static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 2388 struct dc_stream_state *new_stream,
2389 struct dc_stream_state *old_stream)
9b690ef3 2390{
e7b07cee
HW		 2391 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2392 return false;
2393
2394 if (!crtc_state->enable)
2395 return false;
2396
2397 return crtc_state->active;
2398}
2399
2400static bool modereset_required(struct drm_crtc_state *crtc_state)
2401{
2402 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2403 return false;
2404
2405 return !crtc_state->enable || !crtc_state->active;
2406}
2407
7578ecda 2408static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 2409{
2410 drm_encoder_cleanup(encoder);
2411 kfree(encoder);
2412}
2413
2414static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2415 .destroy = amdgpu_dm_encoder_destroy,
2416};
2417
e7b07cee 2418
695af5f9
NK		 2419static int fill_dc_scaling_info(const struct drm_plane_state *state,
2420 struct dc_scaling_info *scaling_info)
e7b07cee 2421{
6491f0c0 2422 int scale_w, scale_h;
e7b07cee 2423
695af5f9 2424 memset(scaling_info, 0, sizeof(*scaling_info));
e7b07cee 2425
695af5f9
NK		 2426 /* Source is fixed 16.16 but we ignore mantissa for now... */
2427 scaling_info->src_rect.x = state->src_x >> 16;
2428 scaling_info->src_rect.y = state->src_y >> 16;
e7b07cee 2429
695af5f9
NK		 2430 scaling_info->src_rect.width = state->src_w >> 16;
2431 if (scaling_info->src_rect.width == 0)
2432 return -EINVAL;
2433
2434 scaling_info->src_rect.height = state->src_h >> 16;
2435 if (scaling_info->src_rect.height == 0)
2436 return -EINVAL;
2437
2438 scaling_info->dst_rect.x = state->crtc_x;
2439 scaling_info->dst_rect.y = state->crtc_y;
e7b07cee
HW		 2440
2441 if (state->crtc_w == 0)
695af5f9 2442 return -EINVAL;
e7b07cee 2443
695af5f9 2444 scaling_info->dst_rect.width = state->crtc_w;
e7b07cee
HW		 2445
2446 if (state->crtc_h == 0)
695af5f9 2447 return -EINVAL;
e7b07cee 2448
695af5f9 2449 scaling_info->dst_rect.height = state->crtc_h;
e7b07cee 2450
695af5f9
NK		 2451 /* DRM doesn't specify clipping on destination output. */
2452 scaling_info->clip_rect = scaling_info->dst_rect;
e7b07cee 2453
6491f0c0
NK		 2454 /* TODO: Validate scaling per-format with DC plane caps */
2455 scale_w = scaling_info->dst_rect.width * 1000 /
2456 scaling_info->src_rect.width;
e7b07cee 2457
6491f0c0
NK		 2458 if (scale_w < 250 || scale_w > 16000)
2459 return -EINVAL;
2460
2461 scale_h = scaling_info->dst_rect.height * 1000 /
2462 scaling_info->src_rect.height;
2463
2464 if (scale_h < 250 || scale_h > 16000)
2465 return -EINVAL;
2466
695af5f9
NK		 2467 /*
2468 * The "scaling_quality" can be ignored for now, quality = 0 has DC
2469 * assume reasonable defaults based on the format.
2470 */
e7b07cee 2471
695af5f9 2472 return 0;
4562236b 2473}
695af5f9 2474
3ee6b26b 2475static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 2476 uint64_t *tiling_flags)
e7b07cee 2477{
e68d14dd 2478 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 2479 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 2480
e7b07cee 2481 if (unlikely(r)) {
1f6010a9 2482 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 2483 if (r != -ERESTARTSYS)
2484 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 2485 return r;
2486 }
2487
e7b07cee
HW		 2488 if (tiling_flags)
2489 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2490
2491 amdgpu_bo_unreserve(rbo);
2492
2493 return r;
2494}
2495
7df7e505
NK		 2496static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2497{
2498 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2499
2500 return offset ? (address + offset * 256) : 0;
2501}
2502
695af5f9
NK		 2503static int
2504fill_plane_dcc_attributes(struct amdgpu_device *adev,
2505 const struct amdgpu_framebuffer *afb,
2506 const enum surface_pixel_format format,
2507 const enum dc_rotation_angle rotation,
2508 const union plane_size *plane_size,
2509 const union dc_tiling_info *tiling_info,
2510 const uint64_t info,
2511 struct dc_plane_dcc_param *dcc,
2512 struct dc_plane_address *address)
7df7e505
NK		 2513{
2514 struct dc *dc = adev->dm.dc;
8daa1218
NC		 2515 struct dc_dcc_surface_param input;
2516 struct dc_surface_dcc_cap output;
7df7e505
NK		 2517 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2518 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2519 uint64_t dcc_address;
2520
8daa1218
NC		 2521 memset(&input, 0, sizeof(input));
2522 memset(&output, 0, sizeof(output));
2523
7df7e505 2524 if (!offset)
09e5665a
NK		 2525 return 0;
2526
695af5f9 2527 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
09e5665a 2528 return 0;
7df7e505
NK		 2529
2530 if (!dc->cap_funcs.get_dcc_compression_cap)
09e5665a 2531 return -EINVAL;
7df7e505 2532
695af5f9
NK		 2533 input.format = format;
2534 input.surface_size.width = plane_size->grph.surface_size.width;
2535 input.surface_size.height = plane_size->grph.surface_size.height;
2536 input.swizzle_mode = tiling_info->gfx9.swizzle;
7df7e505 2537
695af5f9 2538 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
7df7e505 2539 input.scan = SCAN_DIRECTION_HORIZONTAL;
695af5f9 2540 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
7df7e505
NK		 2541 input.scan = SCAN_DIRECTION_VERTICAL;
2542
2543 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
09e5665a 2544 return -EINVAL;
7df7e505
NK		 2545
2546 if (!output.capable)
09e5665a 2547 return -EINVAL;
7df7e505
NK		 2548
2549 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
09e5665a 2550 return -EINVAL;
7df7e505 2551
09e5665a
NK		 2552 dcc->enable = 1;
2553 dcc->grph.meta_pitch =
7df7e505 2554 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
09e5665a 2555 dcc->grph.independent_64b_blks = i64b;
7df7e505
NK		 2556
2557 dcc_address = get_dcc_address(afb->address, info);
09e5665a
NK		 2558 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
2559 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
7df7e505 2560
09e5665a
NK		 2561 return 0;
2562}
2563
2564static int
320932bf 2565fill_plane_buffer_attributes(struct amdgpu_device *adev,
09e5665a 2566 const struct amdgpu_framebuffer *afb,
695af5f9
NK		 2567 const enum surface_pixel_format format,
2568 const enum dc_rotation_angle rotation,
2569 const uint64_t tiling_flags,
09e5665a 2570 union dc_tiling_info *tiling_info,
320932bf 2571 union plane_size *plane_size,
09e5665a 2572 struct dc_plane_dcc_param *dcc,
695af5f9 2573 struct dc_plane_address *address)
09e5665a 2574{
320932bf 2575 const struct drm_framebuffer *fb = &afb->base;
09e5665a
NK		 2576 int ret;
2577
2578 memset(tiling_info, 0, sizeof(*tiling_info));
320932bf 2579 memset(plane_size, 0, sizeof(*plane_size));
09e5665a 2580 memset(dcc, 0, sizeof(*dcc));
e0634e8d
NK		 2581 memset(address, 0, sizeof(*address));
2582
695af5f9 2583 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
320932bf
NK		 2584 plane_size->grph.surface_size.x = 0;
2585 plane_size->grph.surface_size.y = 0;
2586 plane_size->grph.surface_size.width = fb->width;
2587 plane_size->grph.surface_size.height = fb->height;
2588 plane_size->grph.surface_pitch =
2589 fb->pitches[0] / fb->format->cpp[0];
2590
e0634e8d
NK		 2591 address->type = PLN_ADDR_TYPE_GRAPHICS;
2592 address->grph.addr.low_part = lower_32_bits(afb->address);
2593 address->grph.addr.high_part = upper_32_bits(afb->address);
1894478a 2594 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
1791e54f 2595 uint64_t chroma_addr = afb->address + fb->offsets[1];
e0634e8d 2596
320932bf
NK		 2597 plane_size->video.luma_size.x = 0;
2598 plane_size->video.luma_size.y = 0;
2599 plane_size->video.luma_size.width = fb->width;
2600 plane_size->video.luma_size.height = fb->height;
2601 plane_size->video.luma_pitch =
2602 fb->pitches[0] / fb->format->cpp[0];
2603
2604 plane_size->video.chroma_size.x = 0;
2605 plane_size->video.chroma_size.y = 0;
2606 /* TODO: set these based on surface format */
2607 plane_size->video.chroma_size.width = fb->width / 2;
2608 plane_size->video.chroma_size.height = fb->height / 2;
2609
2610 plane_size->video.chroma_pitch =
2611 fb->pitches[1] / fb->format->cpp[1];
2612
e0634e8d
NK		 2613 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2614 address->video_progressive.luma_addr.low_part =
2615 lower_32_bits(afb->address);
2616 address->video_progressive.luma_addr.high_part =
2617 upper_32_bits(afb->address);
2618 address->video_progressive.chroma_addr.low_part =
2619 lower_32_bits(chroma_addr);
2620 address->video_progressive.chroma_addr.high_part =
2621 upper_32_bits(chroma_addr);
2622 }
09e5665a
NK		 2623
2624 /* Fill GFX8 params */
2625 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2626 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2627
2628 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2629 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2630 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2631 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2632 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2633
2634 /* XXX fix me for VI */
2635 tiling_info->gfx8.num_banks = num_banks;
2636 tiling_info->gfx8.array_mode =
2637 DC_ARRAY_2D_TILED_THIN1;
2638 tiling_info->gfx8.tile_split = tile_split;
2639 tiling_info->gfx8.bank_width = bankw;
2640 tiling_info->gfx8.bank_height = bankh;
2641 tiling_info->gfx8.tile_aspect = mtaspect;
2642 tiling_info->gfx8.tile_mode =
2643 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2644 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2645 == DC_ARRAY_1D_TILED_THIN1) {
2646 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2647 }
2648
2649 tiling_info->gfx8.pipe_config =
2650 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2651
2652 if (adev->asic_type == CHIP_VEGA10 ||
2653 adev->asic_type == CHIP_VEGA12 ||
2654 adev->asic_type == CHIP_VEGA20 ||
2655 adev->asic_type == CHIP_RAVEN) {
2656 /* Fill GFX9 params */
2657 tiling_info->gfx9.num_pipes =
2658 adev->gfx.config.gb_addr_config_fields.num_pipes;
2659 tiling_info->gfx9.num_banks =
2660 adev->gfx.config.gb_addr_config_fields.num_banks;
2661 tiling_info->gfx9.pipe_interleave =
2662 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2663 tiling_info->gfx9.num_shader_engines =
2664 adev->gfx.config.gb_addr_config_fields.num_se;
2665 tiling_info->gfx9.max_compressed_frags =
2666 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2667 tiling_info->gfx9.num_rb_per_se =
2668 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2669 tiling_info->gfx9.swizzle =
2670 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2671 tiling_info->gfx9.shaderEnable = 1;
2672
695af5f9
NK		 2673 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
2674 plane_size, tiling_info,
2675 tiling_flags, dcc, address);
09e5665a
NK		 2676 if (ret)
2677 return ret;
2678 }
2679
2680 return 0;
7df7e505
NK		 2681}
2682
d74004b6 2683static void
695af5f9 2684fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
d74004b6
NK		 2685 bool *per_pixel_alpha, bool *global_alpha,
2686 int *global_alpha_value)
2687{
2688 *per_pixel_alpha = false;
2689 *global_alpha = false;
2690 *global_alpha_value = 0xff;
2691
2692 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
2693 return;
2694
2695 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
2696 static const uint32_t alpha_formats[] = {
2697 DRM_FORMAT_ARGB8888,
2698 DRM_FORMAT_RGBA8888,
2699 DRM_FORMAT_ABGR8888,
2700 };
2701 uint32_t format = plane_state->fb->format->format;
2702 unsigned int i;
2703
2704 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
2705 if (format == alpha_formats[i]) {
2706 *per_pixel_alpha = true;
2707 break;
2708 }
2709 }
2710 }
2711
2712 if (plane_state->alpha < 0xffff) {
2713 *global_alpha = true;
2714 *global_alpha_value = plane_state->alpha >> 8;
2715 }
2716}
2717
004fefa3
NK		 2718static int
2719fill_plane_color_attributes(const struct drm_plane_state *plane_state,
695af5f9 2720 const enum surface_pixel_format format,
004fefa3
NK		 2721 enum dc_color_space *color_space)
2722{
2723 bool full_range;
2724
2725 *color_space = COLOR_SPACE_SRGB;
2726
2727 /* DRM color properties only affect non-RGB formats. */
695af5f9 2728 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
004fefa3
NK		 2729 return 0;
2730
2731 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
2732
2733 switch (plane_state->color_encoding) {
2734 case DRM_COLOR_YCBCR_BT601:
2735 if (full_range)
2736 *color_space = COLOR_SPACE_YCBCR601;
2737 else
2738 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
2739 break;
2740
2741 case DRM_COLOR_YCBCR_BT709:
2742 if (full_range)
2743 *color_space = COLOR_SPACE_YCBCR709;
2744 else
2745 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
2746 break;
2747
2748 case DRM_COLOR_YCBCR_BT2020:
2749 if (full_range)
2750 *color_space = COLOR_SPACE_2020_YCBCR;
2751 else
2752 return -EINVAL;
2753 break;
2754
2755 default:
2756 return -EINVAL;
2757 }
2758
2759 return 0;
2760}
2761
695af5f9
NK		 2762static int
2763fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
2764 const struct drm_plane_state *plane_state,
2765 const uint64_t tiling_flags,
2766 struct dc_plane_info *plane_info,
2767 struct dc_plane_address *address)
2768{
2769 const struct drm_framebuffer *fb = plane_state->fb;
2770 const struct amdgpu_framebuffer *afb =
2771 to_amdgpu_framebuffer(plane_state->fb);
2772 struct drm_format_name_buf format_name;
2773 int ret;
2774
2775 memset(plane_info, 0, sizeof(*plane_info));
2776
2777 switch (fb->format->format) {
2778 case DRM_FORMAT_C8:
2779 plane_info->format =
2780 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
2781 break;
2782 case DRM_FORMAT_RGB565:
2783 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
2784 break;
2785 case DRM_FORMAT_XRGB8888:
2786 case DRM_FORMAT_ARGB8888:
2787 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
2788 break;
2789 case DRM_FORMAT_XRGB2101010:
2790 case DRM_FORMAT_ARGB2101010:
2791 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
2792 break;
2793 case DRM_FORMAT_XBGR2101010:
2794 case DRM_FORMAT_ABGR2101010:
2795 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
2796 break;
2797 case DRM_FORMAT_XBGR8888:
2798 case DRM_FORMAT_ABGR8888:
2799 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2800 break;
2801 case DRM_FORMAT_NV21:
2802 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
2803 break;
2804 case DRM_FORMAT_NV12:
2805 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
2806 break;
2807 default:
2808 DRM_ERROR(
2809 "Unsupported screen format %s\n",
2810 drm_get_format_name(fb->format->format, &format_name));
2811 return -EINVAL;
2812 }
2813
2814 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
2815 case DRM_MODE_ROTATE_0:
2816 plane_info->rotation = ROTATION_ANGLE_0;
2817 break;
2818 case DRM_MODE_ROTATE_90:
2819 plane_info->rotation = ROTATION_ANGLE_90;
2820 break;
2821 case DRM_MODE_ROTATE_180:
2822 plane_info->rotation = ROTATION_ANGLE_180;
2823 break;
2824 case DRM_MODE_ROTATE_270:
2825 plane_info->rotation = ROTATION_ANGLE_270;
2826 break;
2827 default:
2828 plane_info->rotation = ROTATION_ANGLE_0;
2829 break;
2830 }
2831
2832 plane_info->visible = true;
2833 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
2834
2835 ret = fill_plane_color_attributes(plane_state, plane_info->format,
2836 &plane_info->color_space);
2837 if (ret)
2838 return ret;
2839
2840 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
2841 plane_info->rotation, tiling_flags,
2842 &plane_info->tiling_info,
2843 &plane_info->plane_size,
2844 &plane_info->dcc, address);
2845 if (ret)
2846 return ret;
2847
2848 fill_blending_from_plane_state(
2849 plane_state, &plane_info->per_pixel_alpha,
2850 &plane_info->global_alpha, &plane_info->global_alpha_value);
2851
2852 return 0;
2853}
2854
2855static int fill_dc_plane_attributes(struct amdgpu_device *adev,
2856 struct dc_plane_state *dc_plane_state,
2857 struct drm_plane_state *plane_state,
2858 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2859{
2860 const struct amdgpu_framebuffer *amdgpu_fb =
2861 to_amdgpu_framebuffer(plane_state->fb);
695af5f9
NK		 2862 struct dc_scaling_info scaling_info;
2863 struct dc_plane_info plane_info;
2864 uint64_t tiling_flags;
2865 int ret;
e7b07cee 2866
695af5f9
NK		 2867 ret = fill_dc_scaling_info(plane_state, &scaling_info);
2868 if (ret)
2869 return ret;
e7b07cee 2870
695af5f9
NK		 2871 dc_plane_state->src_rect = scaling_info.src_rect;
2872 dc_plane_state->dst_rect = scaling_info.dst_rect;
2873 dc_plane_state->clip_rect = scaling_info.clip_rect;
2874 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
e7b07cee 2875
695af5f9 2876 ret = get_fb_info(amdgpu_fb, &tiling_flags);
e7b07cee
HW		 2877 if (ret)
2878 return ret;
2879
695af5f9
NK		 2880 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
2881 &plane_info,
2882 &dc_plane_state->address);
004fefa3
NK		 2883 if (ret)
2884 return ret;
2885
695af5f9
NK		 2886 dc_plane_state->format = plane_info.format;
2887 dc_plane_state->color_space = plane_info.color_space;
2888 dc_plane_state->format = plane_info.format;
2889 dc_plane_state->plane_size = plane_info.plane_size;
2890 dc_plane_state->rotation = plane_info.rotation;
2891 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
2892 dc_plane_state->stereo_format = plane_info.stereo_format;
2893 dc_plane_state->tiling_info = plane_info.tiling_info;
2894 dc_plane_state->visible = plane_info.visible;
2895 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
2896 dc_plane_state->global_alpha = plane_info.global_alpha;
2897 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
2898 dc_plane_state->dcc = plane_info.dcc;
2899
e277adc5
LSL		 2900 /*
2901 * Always set input transfer function, since plane state is refreshed
2902 * every time.
2903 */
2904 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2905 if (ret) {
2906 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2907 dc_plane_state->in_transfer_func = NULL;
2908 }
e7b07cee
HW		 2909
2910 return ret;
2911}
2912
3ee6b26b
AD		 2913static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2914 const struct dm_connector_state *dm_state,
2915 struct dc_stream_state *stream)
e7b07cee
HW		 2916{
2917 enum amdgpu_rmx_type rmx_type;
2918
2919 struct rect src = { 0 }; /* viewport in composition space*/
2920 struct rect dst = { 0 }; /* stream addressable area */
2921
2922 /* no mode. nothing to be done */
2923 if (!mode)
2924 return;
2925
2926 /* Full screen scaling by default */
2927 src.width = mode->hdisplay;
2928 src.height = mode->vdisplay;
2929 dst.width = stream->timing.h_addressable;
2930 dst.height = stream->timing.v_addressable;
2931
f4791779
HW		 2932 if (dm_state) {
2933 rmx_type = dm_state->scaling;
2934 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2935 if (src.width * dst.height <
2936 src.height * dst.width) {
2937 /* height needs less upscaling/more downscaling */
2938 dst.width = src.width *
2939 dst.height / src.height;
2940 } else {
2941 /* width needs less upscaling/more downscaling */
2942 dst.height = src.height *
2943 dst.width / src.width;
2944 }
2945 } else if (rmx_type == RMX_CENTER) {
2946 dst = src;
e7b07cee 2947 }
e7b07cee 2948
f4791779
HW		 2949 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2950 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2951
f4791779
HW		 2952 if (dm_state->underscan_enable) {
2953 dst.x += dm_state->underscan_hborder / 2;
2954 dst.y += dm_state->underscan_vborder / 2;
2955 dst.width -= dm_state->underscan_hborder;
2956 dst.height -= dm_state->underscan_vborder;
2957 }
e7b07cee
HW		 2958 }
2959
2960 stream->src = src;
2961 stream->dst = dst;
2962
f1ad2f5e 2963 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2964 dst.x, dst.y, dst.width, dst.height);
2965
2966}
2967
3ee6b26b 2968static enum dc_color_depth
42ba01fc
NK		 2969convert_color_depth_from_display_info(const struct drm_connector *connector,
2970 const struct drm_connector_state *state)
e7b07cee
HW		 2971{
2972 uint32_t bpc = connector->display_info.bpc;
2973
42ba01fc
NK		 2974 if (state) {
2975 bpc = state->max_bpc;
1825fd34
NK		 2976 /* Round down to the nearest even number. */
2977 bpc = bpc - (bpc & 1);
2978 }
07e3a1cf 2979
e7b07cee
HW		 2980 switch (bpc) {
2981 case 0:
1f6010a9
DF		 2982 /*
2983 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 2984 * EDID revision before 1.4
2985 * TODO: Fix edid parsing
2986 */
2987 return COLOR_DEPTH_888;
2988 case 6:
2989 return COLOR_DEPTH_666;
2990 case 8:
2991 return COLOR_DEPTH_888;
2992 case 10:
2993 return COLOR_DEPTH_101010;
2994 case 12:
2995 return COLOR_DEPTH_121212;
2996 case 14:
2997 return COLOR_DEPTH_141414;
2998 case 16:
2999 return COLOR_DEPTH_161616;
3000 default:
3001 return COLOR_DEPTH_UNDEFINED;
3002 }
3003}
3004
3ee6b26b
AD		 3005static enum dc_aspect_ratio
3006get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 3007{
e11d4147
LSL		 3008 /* 1-1 mapping, since both enums follow the HDMI spec. */
3009 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 3010}
3011
3ee6b26b
AD		 3012static enum dc_color_space
3013get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 3014{
3015 enum dc_color_space color_space = COLOR_SPACE_SRGB;
3016
3017 switch (dc_crtc_timing->pixel_encoding) {
3018 case PIXEL_ENCODING_YCBCR422:
3019 case PIXEL_ENCODING_YCBCR444:
3020 case PIXEL_ENCODING_YCBCR420:
3021 {
3022 /*
3023 * 27030khz is the separation point between HDTV and SDTV
3024 * according to HDMI spec, we use YCbCr709 and YCbCr601
3025 * respectively
3026 */
380604e2 3027 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 3028 if (dc_crtc_timing->flags.Y_ONLY)
3029 color_space =
3030 COLOR_SPACE_YCBCR709_LIMITED;
3031 else
3032 color_space = COLOR_SPACE_YCBCR709;
3033 } else {
3034 if (dc_crtc_timing->flags.Y_ONLY)
3035 color_space =
3036 COLOR_SPACE_YCBCR601_LIMITED;
3037 else
3038 color_space = COLOR_SPACE_YCBCR601;
3039 }
3040
3041 }
3042 break;
3043 case PIXEL_ENCODING_RGB:
3044 color_space = COLOR_SPACE_SRGB;
3045 break;
3046
3047 default:
3048 WARN_ON(1);
3049 break;
3050 }
3051
3052 return color_space;
3053}
3054
400443e8
ML		 3055static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
3056{
3057 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3058 return;
3059
3060 timing_out->display_color_depth--;
3061}
3062
3063static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
3064 const struct drm_display_info *info)
3065{
3066 int normalized_clk;
3067 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3068 return;
3069 do {
380604e2 3070 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 3071 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3072 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3073 normalized_clk /= 2;
3074 /* Adjusting pix clock following on HDMI spec based on colour depth */
3075 switch (timing_out->display_color_depth) {
3076 case COLOR_DEPTH_101010:
3077 normalized_clk = (normalized_clk * 30) / 24;
3078 break;
3079 case COLOR_DEPTH_121212:
3080 normalized_clk = (normalized_clk * 36) / 24;
3081 break;
3082 case COLOR_DEPTH_161616:
3083 normalized_clk = (normalized_clk * 48) / 24;
3084 break;
3085 default:
3086 return;
3087 }
3088 if (normalized_clk <= info->max_tmds_clock)
3089 return;
3090 reduce_mode_colour_depth(timing_out);
3091
3092 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
3093
3094}
e7b07cee 3095
42ba01fc
NK		 3096static void fill_stream_properties_from_drm_display_mode(
3097 struct dc_stream_state *stream,
3098 const struct drm_display_mode *mode_in,
3099 const struct drm_connector *connector,
3100 const struct drm_connector_state *connector_state,
3101 const struct dc_stream_state *old_stream)
e7b07cee
HW		 3102{
3103 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 3104 const struct drm_display_info *info = &connector->display_info;
b830ebc9 3105
e7b07cee
HW		 3106 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
3107
3108 timing_out->h_border_left = 0;
3109 timing_out->h_border_right = 0;
3110 timing_out->v_border_top = 0;
3111 timing_out->v_border_bottom = 0;
3112 /* TODO: un-hardcode */
fe61a2f1 3113 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 3114 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1
ML		 3115 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3116 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
ceb3dbb4 3117 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 3118 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3119 else
3120 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3121
3122 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3123 timing_out->display_color_depth = convert_color_depth_from_display_info(
42ba01fc 3124 connector, connector_state);
e7b07cee
HW		 3125 timing_out->scan_type = SCANNING_TYPE_NODATA;
3126 timing_out->hdmi_vic = 0;
b333730d
BL		 3127
3128 if(old_stream) {
3129 timing_out->vic = old_stream->timing.vic;
3130 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3131 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3132 } else {
3133 timing_out->vic = drm_match_cea_mode(mode_in);
3134 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3135 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3136 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3137 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3138 }
e7b07cee
HW		 3139
3140 timing_out->h_addressable = mode_in->crtc_hdisplay;
3141 timing_out->h_total = mode_in->crtc_htotal;
3142 timing_out->h_sync_width =
3143 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3144 timing_out->h_front_porch =
3145 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3146 timing_out->v_total = mode_in->crtc_vtotal;
3147 timing_out->v_addressable = mode_in->crtc_vdisplay;
3148 timing_out->v_front_porch =
3149 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3150 timing_out->v_sync_width =
3151 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
380604e2 3152 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
e7b07cee 3153 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 3154
3155 stream->output_color_space = get_output_color_space(timing_out);
3156
e43a432c
AK		 3157 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3158 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ceb3dbb4 3159 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
400443e8 3160 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 3161}
3162
3ee6b26b
AD		 3163static void fill_audio_info(struct audio_info *audio_info,
3164 const struct drm_connector *drm_connector,
3165 const struct dc_sink *dc_sink)
e7b07cee
HW		 3166{
3167 int i = 0;
3168 int cea_revision = 0;
3169 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3170
3171 audio_info->manufacture_id = edid_caps->manufacturer_id;
3172 audio_info->product_id = edid_caps->product_id;
3173
3174 cea_revision = drm_connector->display_info.cea_rev;
3175
090afc1e 3176 strscpy(audio_info->display_name,
d2b2562c 3177 edid_caps->display_name,
090afc1e 3178 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 3179
b830ebc9 3180 if (cea_revision >= 3) {
e7b07cee
HW		 3181 audio_info->mode_count = edid_caps->audio_mode_count;
3182
3183 for (i = 0; i < audio_info->mode_count; ++i) {
3184 audio_info->modes[i].format_code =
3185 (enum audio_format_code)
3186 (edid_caps->audio_modes[i].format_code);
3187 audio_info->modes[i].channel_count =
3188 edid_caps->audio_modes[i].channel_count;
3189 audio_info->modes[i].sample_rates.all =
3190 edid_caps->audio_modes[i].sample_rate;
3191 audio_info->modes[i].sample_size =
3192 edid_caps->audio_modes[i].sample_size;
3193 }
3194 }
3195
3196 audio_info->flags.all = edid_caps->speaker_flags;
3197
3198 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 3199 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 3200 audio_info->video_latency = drm_connector->video_latency[0];
3201 audio_info->audio_latency = drm_connector->audio_latency[0];
3202 }
3203
3204 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3205
3206}
3207
3ee6b26b
AD		 3208static void
3209copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3210 struct drm_display_mode *dst_mode)
e7b07cee
HW		 3211{
3212 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3213 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3214 dst_mode->crtc_clock = src_mode->crtc_clock;
3215 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3216 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 3217 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 3218 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3219 dst_mode->crtc_htotal = src_mode->crtc_htotal;
3220 dst_mode->crtc_hskew = src_mode->crtc_hskew;
3221 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3222 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3223 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3224 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3225 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3226}
3227
3ee6b26b
AD		 3228static void
3229decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3230 const struct drm_display_mode *native_mode,
3231 bool scale_enabled)
e7b07cee
HW		 3232{
3233 if (scale_enabled) {
3234 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3235 } else if (native_mode->clock == drm_mode->clock &&
3236 native_mode->htotal == drm_mode->htotal &&
3237 native_mode->vtotal == drm_mode->vtotal) {
3238 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3239 } else {
3240 /* no scaling nor amdgpu inserted, no need to patch */
3241 }
3242}
3243
aed15309
ML		 3244static struct dc_sink *
3245create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 3246{
2e0ac3d6 3247 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 3248 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 3249 sink_init_data.link = aconnector->dc_link;
3250 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3251
3252 sink = dc_sink_create(&sink_init_data);
423788c7 3253 if (!sink) {
2e0ac3d6 3254 DRM_ERROR("Failed to create sink!\n");
aed15309 3255 return NULL;
423788c7 3256 }
2e0ac3d6 3257 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 3258
aed15309 3259 return sink;
2e0ac3d6
HW		 3260}
3261
fa2123db
ML		 3262static void set_multisync_trigger_params(
3263 struct dc_stream_state *stream)
3264{
3265 if (stream->triggered_crtc_reset.enabled) {
3266 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3267 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3268 }
3269}
3270
3271static void set_master_stream(struct dc_stream_state *stream_set[],
3272 int stream_count)
3273{
3274 int j, highest_rfr = 0, master_stream = 0;
3275
3276 for (j = 0; j < stream_count; j++) {
3277 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3278 int refresh_rate = 0;
3279
380604e2 3280 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 3281 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3282 if (refresh_rate > highest_rfr) {
3283 highest_rfr = refresh_rate;
3284 master_stream = j;
3285 }
3286 }
3287 }
3288 for (j = 0; j < stream_count; j++) {
03736f4c 3289 if (stream_set[j])
fa2123db
ML		 3290 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3291 }
3292}
3293
3294static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3295{
3296 int i = 0;
3297
3298 if (context->stream_count < 2)
3299 return;
3300 for (i = 0; i < context->stream_count ; i++) {
3301 if (!context->streams[i])
3302 continue;
1f6010a9
DF		 3303 /*
3304 * TODO: add a function to read AMD VSDB bits and set
fa2123db 3305 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 3306 * For now it's set to false
fa2123db
ML		 3307 */
3308 set_multisync_trigger_params(context->streams[i]);
3309 }
3310 set_master_stream(context->streams, context->stream_count);
3311}
3312
3ee6b26b
AD		 3313static struct dc_stream_state *
3314create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3315 const struct drm_display_mode *drm_mode,
b333730d
BL		 3316 const struct dm_connector_state *dm_state,
3317 const struct dc_stream_state *old_stream)
e7b07cee
HW		 3318{
3319 struct drm_display_mode *preferred_mode = NULL;
391ef035 3320 struct drm_connector *drm_connector;
42ba01fc
NK		 3321 const struct drm_connector_state *con_state =
3322 dm_state ? &dm_state->base : NULL;
0971c40e 3323 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 3324 struct drm_display_mode mode = *drm_mode;
3325 bool native_mode_found = false;
b333730d
BL		 3326 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3327 int mode_refresh;
58124bf8 3328 int preferred_refresh = 0;
b333730d 3329
aed15309 3330 struct dc_sink *sink = NULL;
b830ebc9 3331 if (aconnector == NULL) {
e7b07cee 3332 DRM_ERROR("aconnector is NULL!\n");
64245fa7 3333 return stream;
e7b07cee
HW		 3334 }
3335
e7b07cee 3336 drm_connector = &aconnector->base;
2e0ac3d6 3337
f4ac176e 3338 if (!aconnector->dc_sink) {
e3fa5c4c
JFZ		 3339 sink = create_fake_sink(aconnector);
3340 if (!sink)
3341 return stream;
aed15309
ML		 3342 } else {
3343 sink = aconnector->dc_sink;
dcd5fb82 3344 dc_sink_retain(sink);
f4ac176e 3345 }
2e0ac3d6 3346
aed15309 3347 stream = dc_create_stream_for_sink(sink);
4562236b 3348
b830ebc9 3349 if (stream == NULL) {
e7b07cee 3350 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 3351 goto finish;
e7b07cee
HW		 3352 }
3353
ceb3dbb4
JL		 3354 stream->dm_stream_context = aconnector;
3355
e7b07cee
HW		 3356 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3357 /* Search for preferred mode */
3358 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3359 native_mode_found = true;
3360 break;
3361 }
3362 }
3363 if (!native_mode_found)
3364 preferred_mode = list_first_entry_or_null(
3365 &aconnector->base.modes,
3366 struct drm_display_mode,
3367 head);
3368
b333730d
BL		 3369 mode_refresh = drm_mode_vrefresh(&mode);
3370
b830ebc9 3371 if (preferred_mode == NULL) {
1f6010a9
DF		 3372 /*
3373 * This may not be an error, the use case is when we have no
e7b07cee
HW		 3374 * usermode calls to reset and set mode upon hotplug. In this
3375 * case, we call set mode ourselves to restore the previous mode
3376 * and the modelist may not be filled in in time.
3377 */
f1ad2f5e 3378 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 3379 } else {
3380 decide_crtc_timing_for_drm_display_mode(
3381 &mode, preferred_mode,
f4791779 3382 dm_state ? (dm_state->scaling != RMX_OFF) : false);
58124bf8 3383 preferred_refresh = drm_mode_vrefresh(preferred_mode);
e7b07cee
HW		 3384 }
3385
f783577c
JFZ		 3386 if (!dm_state)
3387 drm_mode_set_crtcinfo(&mode, 0);
3388
b333730d
BL		 3389 /*
3390 * If scaling is enabled and refresh rate didn't change
3391 * we copy the vic and polarities of the old timings
3392 */
3393 if (!scale || mode_refresh != preferred_refresh)
3394 fill_stream_properties_from_drm_display_mode(stream,
42ba01fc 3395 &mode, &aconnector->base, con_state, NULL);
b333730d
BL		 3396 else
3397 fill_stream_properties_from_drm_display_mode(stream,
42ba01fc 3398 &mode, &aconnector->base, con_state, old_stream);
b333730d 3399
e7b07cee
HW		 3400 update_stream_scaling_settings(&mode, dm_state, stream);
3401
3402 fill_audio_info(
3403 &stream->audio_info,
3404 drm_connector,
aed15309 3405 sink);
e7b07cee 3406
ceb3dbb4 3407 update_stream_signal(stream, sink);
9182b4cb 3408
aed15309 3409finish:
dcd5fb82 3410 dc_sink_release(sink);
9e3efe3e 3411
e7b07cee
HW		 3412 return stream;
3413}
3414
7578ecda 3415static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 3416{
3417 drm_crtc_cleanup(crtc);
3418 kfree(crtc);
3419}
3420
3421static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 3422 struct drm_crtc_state *state)
e7b07cee
HW		 3423{
3424 struct dm_crtc_state *cur = to_dm_crtc_state(state);
3425
3426 /* TODO Destroy dc_stream objects are stream object is flattened */
3427 if (cur->stream)
3428 dc_stream_release(cur->stream);
3429
3430
3431 __drm_atomic_helper_crtc_destroy_state(state);
3432
3433
3434 kfree(state);
3435}
3436
3437static void dm_crtc_reset_state(struct drm_crtc *crtc)
3438{
3439 struct dm_crtc_state *state;
3440
3441 if (crtc->state)
3442 dm_crtc_destroy_state(crtc, crtc->state);
3443
3444 state = kzalloc(sizeof(*state), GFP_KERNEL);
3445 if (WARN_ON(!state))
3446 return;
3447
3448 crtc->state = &state->base;
3449 crtc->state->crtc = crtc;
3450
3451}
3452
3453static struct drm_crtc_state *
3454dm_crtc_duplicate_state(struct drm_crtc *crtc)
3455{
3456 struct dm_crtc_state *state, *cur;
3457
3458 cur = to_dm_crtc_state(crtc->state);
3459
3460 if (WARN_ON(!crtc->state))
3461 return NULL;
3462
2004f45e 3463 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 3464 if (!state)
3465 return NULL;
e7b07cee
HW		 3466
3467 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3468
3469 if (cur->stream) {
3470 state->stream = cur->stream;
3471 dc_stream_retain(state->stream);
3472 }
3473
d6ef9b41
NK		 3474 state->active_planes = cur->active_planes;
3475 state->interrupts_enabled = cur->interrupts_enabled;
180db303 3476 state->vrr_params = cur->vrr_params;
98e6436d 3477 state->vrr_infopacket = cur->vrr_infopacket;
c1ee92f9 3478 state->abm_level = cur->abm_level;
bb47de73
NK		 3479 state->vrr_supported = cur->vrr_supported;
3480 state->freesync_config = cur->freesync_config;
ed20dc0d 3481 state->crc_enabled = cur->crc_enabled;
98e6436d 3482
e7b07cee
HW		 3483 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3484
3485 return &state->base;
3486}
3487
d2574c33
MK		 3488static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
3489{
3490 enum dc_irq_source irq_source;
3491 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3492 struct amdgpu_device *adev = crtc->dev->dev_private;
3493 int rc;
3494
3495 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
3496
3497 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3498
3499 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
3500 acrtc->crtc_id, enable ? "en" : "dis", rc);
3501 return rc;
3502}
589d2739
HW		 3503
3504static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3505{
3506 enum dc_irq_source irq_source;
3507 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3508 struct amdgpu_device *adev = crtc->dev->dev_private;
d2574c33
MK		 3509 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3510 int rc = 0;
3511
3512 if (enable) {
3513 /* vblank irq on -> Only need vupdate irq in vrr mode */
3514 if (amdgpu_dm_vrr_active(acrtc_state))
3515 rc = dm_set_vupdate_irq(crtc, true);
3516 } else {
3517 /* vblank irq off -> vupdate irq off */
3518 rc = dm_set_vupdate_irq(crtc, false);
3519 }
3520
3521 if (rc)
3522 return rc;
589d2739
HW		 3523
3524 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 3525 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 3526}
3527
3528static int dm_enable_vblank(struct drm_crtc *crtc)
3529{
3530 return dm_set_vblank(crtc, true);
3531}
3532
3533static void dm_disable_vblank(struct drm_crtc *crtc)
3534{
3535 dm_set_vblank(crtc, false);
3536}
3537
e7b07cee
HW		 3538/* Implemented only the options currently availible for the driver */
3539static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3540 .reset = dm_crtc_reset_state,
3541 .destroy = amdgpu_dm_crtc_destroy,
3542 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3543 .set_config = drm_atomic_helper_set_config,
3544 .page_flip = drm_atomic_helper_page_flip,
3545 .atomic_duplicate_state = dm_crtc_duplicate_state,
3546 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 3547 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 3548 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
589d2739
HW		 3549 .enable_vblank = dm_enable_vblank,
3550 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 3551};
3552
3553static enum drm_connector_status
3554amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3555{
3556 bool connected;
c84dec2f 3557 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 3558
1f6010a9
DF		 3559 /*
3560 * Notes:
e7b07cee
HW		 3561 * 1. This interface is NOT called in context of HPD irq.
3562 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 3563 * makes it a bad place for *any* MST-related activity.
3564 */
e7b07cee 3565
8580d60b
HW		 3566 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3567 !aconnector->fake_enable)
e7b07cee
HW		 3568 connected = (aconnector->dc_sink != NULL);
3569 else
3570 connected = (aconnector->base.force == DRM_FORCE_ON);
3571
3572 return (connected ? connector_status_connected :
3573 connector_status_disconnected);
3574}
3575
3ee6b26b
AD		 3576int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3577 struct drm_connector_state *connector_state,
3578 struct drm_property *property,
3579 uint64_t val)
e7b07cee
HW		 3580{
3581 struct drm_device *dev = connector->dev;
3582 struct amdgpu_device *adev = dev->dev_private;
3583 struct dm_connector_state *dm_old_state =
3584 to_dm_connector_state(connector->state);
3585 struct dm_connector_state *dm_new_state =
3586 to_dm_connector_state(connector_state);
3587
3588 int ret = -EINVAL;
3589
3590 if (property == dev->mode_config.scaling_mode_property) {
3591 enum amdgpu_rmx_type rmx_type;
3592
3593 switch (val) {
3594 case DRM_MODE_SCALE_CENTER:
3595 rmx_type = RMX_CENTER;
3596 break;
3597 case DRM_MODE_SCALE_ASPECT:
3598 rmx_type = RMX_ASPECT;
3599 break;
3600 case DRM_MODE_SCALE_FULLSCREEN:
3601 rmx_type = RMX_FULL;
3602 break;
3603 case DRM_MODE_SCALE_NONE:
3604 default:
3605 rmx_type = RMX_OFF;
3606 break;
3607 }
3608
3609 if (dm_old_state->scaling == rmx_type)
3610 return 0;
3611
3612 dm_new_state->scaling = rmx_type;
3613 ret = 0;
3614 } else if (property == adev->mode_info.underscan_hborder_property) {
3615 dm_new_state->underscan_hborder = val;
3616 ret = 0;
3617 } else if (property == adev->mode_info.underscan_vborder_property) {
3618 dm_new_state->underscan_vborder = val;
3619 ret = 0;
3620 } else if (property == adev->mode_info.underscan_property) {
3621 dm_new_state->underscan_enable = val;
3622 ret = 0;
c1ee92f9
DF		 3623 } else if (property == adev->mode_info.abm_level_property) {
3624 dm_new_state->abm_level = val;
3625 ret = 0;
e7b07cee
HW		 3626 }
3627
3628 return ret;
3629}
3630
3ee6b26b
AD		 3631int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3632 const struct drm_connector_state *state,
3633 struct drm_property *property,
3634 uint64_t *val)
e7b07cee
HW		 3635{
3636 struct drm_device *dev = connector->dev;
3637 struct amdgpu_device *adev = dev->dev_private;
3638 struct dm_connector_state *dm_state =
3639 to_dm_connector_state(state);
3640 int ret = -EINVAL;
3641
3642 if (property == dev->mode_config.scaling_mode_property) {
3643 switch (dm_state->scaling) {
3644 case RMX_CENTER:
3645 *val = DRM_MODE_SCALE_CENTER;
3646 break;
3647 case RMX_ASPECT:
3648 *val = DRM_MODE_SCALE_ASPECT;
3649 break;
3650 case RMX_FULL:
3651 *val = DRM_MODE_SCALE_FULLSCREEN;
3652 break;
3653 case RMX_OFF:
3654 default:
3655 *val = DRM_MODE_SCALE_NONE;
3656 break;
3657 }
3658 ret = 0;
3659 } else if (property == adev->mode_info.underscan_hborder_property) {
3660 *val = dm_state->underscan_hborder;
3661 ret = 0;
3662 } else if (property == adev->mode_info.underscan_vborder_property) {
3663 *val = dm_state->underscan_vborder;
3664 ret = 0;
3665 } else if (property == adev->mode_info.underscan_property) {
3666 *val = dm_state->underscan_enable;
3667 ret = 0;
c1ee92f9
DF		 3668 } else if (property == adev->mode_info.abm_level_property) {
3669 *val = dm_state->abm_level;
3670 ret = 0;
e7b07cee 3671 }
c1ee92f9 3672
e7b07cee
HW		 3673 return ret;
3674}
3675
526c654a
ED		 3676static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
3677{
3678 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
3679
3680 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
3681}
3682
7578ecda 3683static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 3684{
c84dec2f 3685 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3686 const struct dc_link *link = aconnector->dc_link;
3687 struct amdgpu_device *adev = connector->dev->dev_private;
3688 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 3689
e7b07cee
HW		 3690#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3691 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3692
89fc8d4e 3693 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 3694 link->type != dc_connection_none &&
3695 dm->backlight_dev) {
3696 backlight_device_unregister(dm->backlight_dev);
3697 dm->backlight_dev = NULL;
e7b07cee
HW		 3698 }
3699#endif
dcd5fb82
MF		 3700
3701 if (aconnector->dc_em_sink)
3702 dc_sink_release(aconnector->dc_em_sink);
3703 aconnector->dc_em_sink = NULL;
3704 if (aconnector->dc_sink)
3705 dc_sink_release(aconnector->dc_sink);
3706 aconnector->dc_sink = NULL;
3707
e86e8947 3708 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 3709 drm_connector_unregister(connector);
3710 drm_connector_cleanup(connector);
526c654a
ED		 3711 if (aconnector->i2c) {
3712 i2c_del_adapter(&aconnector->i2c->base);
3713 kfree(aconnector->i2c);
3714 }
3715
e7b07cee
HW		 3716 kfree(connector);
3717}
3718
3719void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3720{
3721 struct dm_connector_state *state =
3722 to_dm_connector_state(connector->state);
3723
df099b9b
LSL		 3724 if (connector->state)
3725 __drm_atomic_helper_connector_destroy_state(connector->state);
3726
e7b07cee
HW		 3727 kfree(state);
3728
3729 state = kzalloc(sizeof(*state), GFP_KERNEL);
3730
3731 if (state) {
3732 state->scaling = RMX_OFF;
3733 state->underscan_enable = false;
3734 state->underscan_hborder = 0;
3735 state->underscan_vborder = 0;
3736
df099b9b 3737 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 3738 }
3739}
3740
3ee6b26b
AD		 3741struct drm_connector_state *
3742amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 3743{
3744 struct dm_connector_state *state =
3745 to_dm_connector_state(connector->state);
3746
3747 struct dm_connector_state *new_state =
3748 kmemdup(state, sizeof(*state), GFP_KERNEL);
3749
98e6436d
AK		 3750 if (!new_state)
3751 return NULL;
e7b07cee 3752
98e6436d
AK		 3753 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3754
3755 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 3756 new_state->abm_level = state->abm_level;
922454c2
NK		 3757 new_state->scaling = state->scaling;
3758 new_state->underscan_enable = state->underscan_enable;
3759 new_state->underscan_hborder = state->underscan_hborder;
3760 new_state->underscan_vborder = state->underscan_vborder;
98e6436d
AK		 3761
3762 return &new_state->base;
e7b07cee
HW		 3763}
3764
3765static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3766 .reset = amdgpu_dm_connector_funcs_reset,
3767 .detect = amdgpu_dm_connector_detect,
3768 .fill_modes = drm_helper_probe_single_connector_modes,
3769 .destroy = amdgpu_dm_connector_destroy,
3770 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3771 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3772 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
526c654a
ED		 3773 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
3774 .early_unregister = amdgpu_dm_connector_unregister
e7b07cee
HW		 3775};
3776
e7b07cee
HW		 3777static int get_modes(struct drm_connector *connector)
3778{
3779 return amdgpu_dm_connector_get_modes(connector);
3780}
3781
c84dec2f 3782static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3783{
3784 struct dc_sink_init_data init_params = {
3785 .link = aconnector->dc_link,
3786 .sink_signal = SIGNAL_TYPE_VIRTUAL
3787 };
70e8ffc5 3788 struct edid *edid;
e7b07cee 3789
a89ff457 3790 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 3791 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3792 aconnector->base.name);
3793
3794 aconnector->base.force = DRM_FORCE_OFF;
3795 aconnector->base.override_edid = false;
3796 return;
3797 }
3798
70e8ffc5
HW		 3799 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3800
e7b07cee
HW		 3801 aconnector->edid = edid;
3802
3803 aconnector->dc_em_sink = dc_link_add_remote_sink(
3804 aconnector->dc_link,
3805 (uint8_t *)edid,
3806 (edid->extensions + 1) * EDID_LENGTH,
3807 &init_params);
3808
dcd5fb82 3809 if (aconnector->base.force == DRM_FORCE_ON) {
e7b07cee
HW		 3810 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3811 aconnector->dc_link->local_sink :
3812 aconnector->dc_em_sink;
dcd5fb82
MF		 3813 dc_sink_retain(aconnector->dc_sink);
3814 }
e7b07cee
HW		 3815}
3816
c84dec2f 3817static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3818{
3819 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3820
1f6010a9
DF		 3821 /*
3822 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 3823 * Those settings have to be != 0 to get initial modeset
3824 */
3825 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3826 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3827 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3828 }
3829
3830
3831 aconnector->base.override_edid = true;
3832 create_eml_sink(aconnector);
3833}
3834
ba9ca088 3835enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 3836 struct drm_display_mode *mode)
e7b07cee
HW		 3837{
3838 int result = MODE_ERROR;
3839 struct dc_sink *dc_sink;
3840 struct amdgpu_device *adev = connector->dev->dev_private;
3841 /* TODO: Unhardcode stream count */
0971c40e 3842 struct dc_stream_state *stream;
c84dec2f 3843 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 3844 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 3845
3846 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3847 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3848 return result;
3849
1f6010a9
DF		 3850 /*
3851 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 3852 * EDID mgmt
3853 */
3854 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3855 !aconnector->dc_em_sink)
3856 handle_edid_mgmt(aconnector);
3857
c84dec2f 3858 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 3859
b830ebc9 3860 if (dc_sink == NULL) {
e7b07cee
HW		 3861 DRM_ERROR("dc_sink is NULL!\n");
3862 goto fail;
3863 }
3864
b333730d 3865 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
b830ebc9 3866 if (stream == NULL) {
e7b07cee
HW		 3867 DRM_ERROR("Failed to create stream for sink!\n");
3868 goto fail;
3869 }
3870
a39438f0
HW		 3871 dc_result = dc_validate_stream(adev->dm.dc, stream);
3872
3873 if (dc_result == DC_OK)
e7b07cee 3874 result = MODE_OK;
a39438f0 3875 else
9f921b14 3876 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 3877 mode->vdisplay,
3878 mode->hdisplay,
9f921b14
HW		 3879 mode->clock,
3880 dc_result);
e7b07cee
HW		 3881
3882 dc_stream_release(stream);
3883
3884fail:
3885 /* TODO: error handling*/
3886 return result;
3887}
3888
88694af9
NK		 3889static int fill_hdr_info_packet(const struct drm_connector_state *state,
3890 struct dc_info_packet *out)
3891{
3892 struct hdmi_drm_infoframe frame;
3893 unsigned char buf[30]; /* 26 + 4 */
3894 ssize_t len;
3895 int ret, i;
3896
3897 memset(out, 0, sizeof(*out));
3898
3899 if (!state->hdr_output_metadata)
3900 return 0;
3901
3902 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
3903 if (ret)
3904 return ret;
3905
3906 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
3907 if (len < 0)
3908 return (int)len;
3909
3910 /* Static metadata is a fixed 26 bytes + 4 byte header. */
3911 if (len != 30)
3912 return -EINVAL;
3913
3914 /* Prepare the infopacket for DC. */
3915 switch (state->connector->connector_type) {
3916 case DRM_MODE_CONNECTOR_HDMIA:
3917 out->hb0 = 0x87; /* type */
3918 out->hb1 = 0x01; /* version */
3919 out->hb2 = 0x1A; /* length */
3920 out->sb[0] = buf[3]; /* checksum */
3921 i = 1;
3922 break;
3923
3924 case DRM_MODE_CONNECTOR_DisplayPort:
3925 case DRM_MODE_CONNECTOR_eDP:
3926 out->hb0 = 0x00; /* sdp id, zero */
3927 out->hb1 = 0x87; /* type */
3928 out->hb2 = 0x1D; /* payload len - 1 */
3929 out->hb3 = (0x13 << 2); /* sdp version */
3930 out->sb[0] = 0x01; /* version */
3931 out->sb[1] = 0x1A; /* length */
3932 i = 2;
3933 break;
3934
3935 default:
3936 return -EINVAL;
3937 }
3938
3939 memcpy(&out->sb[i], &buf[4], 26);
3940 out->valid = true;
3941
3942 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
3943 sizeof(out->sb), false);
3944
3945 return 0;
3946}
3947
3948static bool
3949is_hdr_metadata_different(const struct drm_connector_state *old_state,
3950 const struct drm_connector_state *new_state)
3951{
3952 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
3953 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
3954
3955 if (old_blob != new_blob) {
3956 if (old_blob && new_blob &&
3957 old_blob->length == new_blob->length)
3958 return memcmp(old_blob->data, new_blob->data,
3959 old_blob->length);
3960
3961 return true;
3962 }
3963
3964 return false;
3965}
3966
3967static int
3968amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
3969 struct drm_connector_state *new_con_state)
3970{
3971 struct drm_atomic_state *state = new_con_state->state;
3972 struct drm_connector_state *old_con_state =
3973 drm_atomic_get_old_connector_state(state, conn);
3974 struct drm_crtc *crtc = new_con_state->crtc;
3975 struct drm_crtc_state *new_crtc_state;
3976 int ret;
3977
3978 if (!crtc)
3979 return 0;
3980
3981 if (is_hdr_metadata_different(old_con_state, new_con_state)) {
3982 struct dc_info_packet hdr_infopacket;
3983
3984 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
3985 if (ret)
3986 return ret;
3987
3988 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
3989 if (IS_ERR(new_crtc_state))
3990 return PTR_ERR(new_crtc_state);
3991
3992 /*
3993 * DC considers the stream backends changed if the
3994 * static metadata changes. Forcing the modeset also
3995 * gives a simple way for userspace to switch from
b232d4ed
NK		 3996 * 8bpc to 10bpc when setting the metadata to enter
3997 * or exit HDR.
3998 *
3999 * Changing the static metadata after it's been
4000 * set is permissible, however. So only force a
4001 * modeset if we're entering or exiting HDR.
88694af9 4002 */
b232d4ed
NK		 4003 new_crtc_state->mode_changed =
4004 !old_con_state->hdr_output_metadata ||
4005 !new_con_state->hdr_output_metadata;
88694af9
NK		 4006 }
4007
4008 return 0;
4009}
4010
e7b07cee
HW		 4011static const struct drm_connector_helper_funcs
4012amdgpu_dm_connector_helper_funcs = {
4013 /*
1f6010a9 4014 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 4015 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 4016 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 4017 * in get_modes call back, not just return the modes count
4018 */
e7b07cee
HW		 4019 .get_modes = get_modes,
4020 .mode_valid = amdgpu_dm_connector_mode_valid,
88694af9 4021 .atomic_check = amdgpu_dm_connector_atomic_check,
e7b07cee
HW		 4022};
4023
4024static void dm_crtc_helper_disable(struct drm_crtc *crtc)
4025{
4026}
4027
bc92c065
NK		 4028static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
4029{
4030 struct drm_device *dev = new_crtc_state->crtc->dev;
4031 struct drm_plane *plane;
4032
4033 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
4034 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4035 return true;
4036 }
4037
4038 return false;
4039}
4040
d6ef9b41 4041static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
c14a005c
NK		 4042{
4043 struct drm_atomic_state *state = new_crtc_state->state;
4044 struct drm_plane *plane;
4045 int num_active = 0;
4046
4047 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
4048 struct drm_plane_state *new_plane_state;
4049
4050 /* Cursor planes are "fake". */
4051 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4052 continue;
4053
4054 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
4055
4056 if (!new_plane_state) {
4057 /*
4058 * The plane is enable on the CRTC and hasn't changed
4059 * state. This means that it previously passed
4060 * validation and is therefore enabled.
4061 */
4062 num_active += 1;
4063 continue;
4064 }
4065
4066 /* We need a framebuffer to be considered enabled. */
4067 num_active += (new_plane_state->fb != NULL);
4068 }
4069
d6ef9b41
NK		 4070 return num_active;
4071}
4072
4073/*
4074 * Sets whether interrupts should be enabled on a specific CRTC.
4075 * We require that the stream be enabled and that there exist active
4076 * DC planes on the stream.
4077 */
4078static void
4079dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
4080 struct drm_crtc_state *new_crtc_state)
4081{
4082 struct dm_crtc_state *dm_new_crtc_state =
4083 to_dm_crtc_state(new_crtc_state);
4084
4085 dm_new_crtc_state->active_planes = 0;
4086 dm_new_crtc_state->interrupts_enabled = false;
4087
4088 if (!dm_new_crtc_state->stream)
4089 return;
4090
4091 dm_new_crtc_state->active_planes =
4092 count_crtc_active_planes(new_crtc_state);
4093
4094 dm_new_crtc_state->interrupts_enabled =
4095 dm_new_crtc_state->active_planes > 0;
c14a005c
NK		 4096}
4097
3ee6b26b
AD		 4098static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
4099 struct drm_crtc_state *state)
e7b07cee
HW		 4100{
4101 struct amdgpu_device *adev = crtc->dev->dev_private;
4102 struct dc *dc = adev->dm.dc;
4103 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
4104 int ret = -EINVAL;
4105
d6ef9b41
NK		 4106 /*
4107 * Update interrupt state for the CRTC. This needs to happen whenever
4108 * the CRTC has changed or whenever any of its planes have changed.
4109 * Atomic check satisfies both of these requirements since the CRTC
4110 * is added to the state by DRM during drm_atomic_helper_check_planes.
4111 */
4112 dm_update_crtc_interrupt_state(crtc, state);
4113
9b690ef3
BL		 4114 if (unlikely(!dm_crtc_state->stream &&
4115 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 4116 WARN_ON(1);
4117 return ret;
4118 }
4119
1f6010a9 4120 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 4121 if (!dm_crtc_state->stream)
4122 return 0;
4123
bc92c065
NK		 4124 /*
4125 * We want at least one hardware plane enabled to use
4126 * the stream with a cursor enabled.
4127 */
c14a005c 4128 if (state->enable && state->active &&
bc92c065 4129 does_crtc_have_active_cursor(state) &&
d6ef9b41 4130 dm_crtc_state->active_planes == 0)
c14a005c
NK		 4131 return -EINVAL;
4132
62c933f9 4133 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 4134 return 0;
4135
4136 return ret;
4137}
4138
3ee6b26b
AD		 4139static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4140 const struct drm_display_mode *mode,
4141 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 4142{
4143 return true;
4144}
4145
4146static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4147 .disable = dm_crtc_helper_disable,
4148 .atomic_check = dm_crtc_helper_atomic_check,
4149 .mode_fixup = dm_crtc_helper_mode_fixup
4150};
4151
4152static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4153{
4154
4155}
4156
3ee6b26b
AD		 4157static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4158 struct drm_crtc_state *crtc_state,
4159 struct drm_connector_state *conn_state)
e7b07cee
HW		 4160{
4161 return 0;
4162}
4163
4164const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4165 .disable = dm_encoder_helper_disable,
4166 .atomic_check = dm_encoder_helper_atomic_check
4167};
4168
4169static void dm_drm_plane_reset(struct drm_plane *plane)
4170{
4171 struct dm_plane_state *amdgpu_state = NULL;
4172
4173 if (plane->state)
4174 plane->funcs->atomic_destroy_state(plane, plane->state);
4175
4176 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 4177 WARN_ON(amdgpu_state == NULL);
1f6010a9 4178
7ddaef96
NK		 4179 if (amdgpu_state)
4180 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
e7b07cee
HW		 4181}
4182
4183static struct drm_plane_state *
4184dm_drm_plane_duplicate_state(struct drm_plane *plane)
4185{
4186 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4187
4188 old_dm_plane_state = to_dm_plane_state(plane->state);
4189 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4190 if (!dm_plane_state)
4191 return NULL;
4192
4193 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4194
3be5262e
HW		 4195 if (old_dm_plane_state->dc_state) {
4196 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4197 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 4198 }
4199
4200 return &dm_plane_state->base;
4201}
4202
4203void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 4204 struct drm_plane_state *state)
e7b07cee
HW		 4205{
4206 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4207
3be5262e
HW		 4208 if (dm_plane_state->dc_state)
4209 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 4210
0627bbd3 4211 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 4212}
4213
4214static const struct drm_plane_funcs dm_plane_funcs = {
4215 .update_plane = drm_atomic_helper_update_plane,
4216 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 4217 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 4218 .reset = dm_drm_plane_reset,
4219 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
4220 .atomic_destroy_state = dm_drm_plane_destroy_state,
4221};
4222
3ee6b26b
AD		 4223static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
4224 struct drm_plane_state *new_state)
e7b07cee
HW		 4225{
4226 struct amdgpu_framebuffer *afb;
4227 struct drm_gem_object *obj;
5d43be0c 4228 struct amdgpu_device *adev;
e7b07cee 4229 struct amdgpu_bo *rbo;
e7b07cee 4230 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
0f257b09
CZ		 4231 struct list_head list;
4232 struct ttm_validate_buffer tv;
4233 struct ww_acquire_ctx ticket;
e0634e8d 4234 uint64_t tiling_flags;
5d43be0c
CK		 4235 uint32_t domain;
4236 int r;
e7b07cee
HW		 4237
4238 dm_plane_state_old = to_dm_plane_state(plane->state);
4239 dm_plane_state_new = to_dm_plane_state(new_state);
4240
4241 if (!new_state->fb) {
f1ad2f5e 4242 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 4243 return 0;
4244 }
4245
4246 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 4247 obj = new_state->fb->obj[0];
e7b07cee 4248 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 4249 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
0f257b09
CZ		 4250 INIT_LIST_HEAD(&list);
4251
4252 tv.bo = &rbo->tbo;
4253 tv.num_shared = 1;
4254 list_add(&tv.head, &list);
4255
4256 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true);
4257 if (r) {
4258 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
e7b07cee 4259 return r;
0f257b09 4260 }
e7b07cee 4261
5d43be0c 4262 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 4263 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 4264 else
4265 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 4266
7b7c6c81 4267 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 4268 if (unlikely(r != 0)) {
30b7c614
HW		 4269 if (r != -ERESTARTSYS)
4270 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
0f257b09 4271 ttm_eu_backoff_reservation(&ticket, &list);
e7b07cee
HW		 4272 return r;
4273 }
4274
bb812f1e
JZ		 4275 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
4276 if (unlikely(r != 0)) {
4277 amdgpu_bo_unpin(rbo);
0f257b09 4278 ttm_eu_backoff_reservation(&ticket, &list);
bb812f1e 4279 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 4280 return r;
4281 }
7df7e505
NK		 4282
4283 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
4284
0f257b09 4285 ttm_eu_backoff_reservation(&ticket, &list);
bb812f1e 4286
7b7c6c81 4287 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 4288
4289 amdgpu_bo_ref(rbo);
4290
3be5262e
HW		 4291 if (dm_plane_state_new->dc_state &&
4292 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
4293 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 4294
320932bf 4295 fill_plane_buffer_attributes(
695af5f9
NK		 4296 adev, afb, plane_state->format, plane_state->rotation,
4297 tiling_flags, &plane_state->tiling_info,
320932bf 4298 &plane_state->plane_size, &plane_state->dcc,
695af5f9 4299 &plane_state->address);
e7b07cee
HW		 4300 }
4301
e7b07cee
HW		 4302 return 0;
4303}
4304
3ee6b26b
AD		 4305static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
4306 struct drm_plane_state *old_state)
e7b07cee
HW		 4307{
4308 struct amdgpu_bo *rbo;
e7b07cee
HW		 4309 int r;
4310
4311 if (!old_state->fb)
4312 return;
4313
e68d14dd 4314 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 4315 r = amdgpu_bo_reserve(rbo, false);
4316 if (unlikely(r)) {
4317 DRM_ERROR("failed to reserve rbo before unpin\n");
4318 return;
b830ebc9
HW		 4319 }
4320
4321 amdgpu_bo_unpin(rbo);
4322 amdgpu_bo_unreserve(rbo);
4323 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 4324}
4325
7578ecda
AD		 4326static int dm_plane_atomic_check(struct drm_plane *plane,
4327 struct drm_plane_state *state)
cbd19488
AG		 4328{
4329 struct amdgpu_device *adev = plane->dev->dev_private;
4330 struct dc *dc = adev->dm.dc;
78171832 4331 struct dm_plane_state *dm_plane_state;
695af5f9
NK		 4332 struct dc_scaling_info scaling_info;
4333 int ret;
78171832
NK		 4334
4335 dm_plane_state = to_dm_plane_state(state);
cbd19488 4336
3be5262e 4337 if (!dm_plane_state->dc_state)
9a3329b1 4338 return 0;
cbd19488 4339
695af5f9
NK		 4340 ret = fill_dc_scaling_info(state, &scaling_info);
4341 if (ret)
4342 return ret;
a05bcff1 4343
62c933f9 4344 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 4345 return 0;
4346
4347 return -EINVAL;
4348}
4349
674e78ac
NK		 4350static int dm_plane_atomic_async_check(struct drm_plane *plane,
4351 struct drm_plane_state *new_plane_state)
4352{
77acd1cd
NK		 4353 struct drm_plane_state *old_plane_state =
4354 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
4355
674e78ac
NK		 4356 /* Only support async updates on cursor planes. */
4357 if (plane->type != DRM_PLANE_TYPE_CURSOR)
4358 return -EINVAL;
4359
77acd1cd
NK		 4360 /*
4361 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
4362 * async commits so don't allow fb changes.
4363 */
4364 if (old_plane_state->fb != new_plane_state->fb)
4365 return -EINVAL;
4366
674e78ac
NK		 4367 return 0;
4368}
4369
4370static void dm_plane_atomic_async_update(struct drm_plane *plane,
4371 struct drm_plane_state *new_state)
4372{
4373 struct drm_plane_state *old_state =
4374 drm_atomic_get_old_plane_state(new_state->state, plane);
4375
4376 if (plane->state->fb != new_state->fb)
4377 drm_atomic_set_fb_for_plane(plane->state, new_state->fb);
4378
4379 plane->state->src_x = new_state->src_x;
4380 plane->state->src_y = new_state->src_y;
4381 plane->state->src_w = new_state->src_w;
4382 plane->state->src_h = new_state->src_h;
4383 plane->state->crtc_x = new_state->crtc_x;
4384 plane->state->crtc_y = new_state->crtc_y;
4385 plane->state->crtc_w = new_state->crtc_w;
4386 plane->state->crtc_h = new_state->crtc_h;
4387
4388 handle_cursor_update(plane, old_state);
4389}
4390
e7b07cee
HW		 4391static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
4392 .prepare_fb = dm_plane_helper_prepare_fb,
4393 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 4394 .atomic_check = dm_plane_atomic_check,
674e78ac
NK		 4395 .atomic_async_check = dm_plane_atomic_async_check,
4396 .atomic_async_update = dm_plane_atomic_async_update
e7b07cee
HW		 4397};
4398
4399/*
4400 * TODO: these are currently initialized to rgb formats only.
4401 * For future use cases we should either initialize them dynamically based on
4402 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 4403 * check will succeed, and let DC implement proper check
e7b07cee 4404 */
d90371b0 4405static const uint32_t rgb_formats[] = {
e7b07cee
HW		 4406 DRM_FORMAT_XRGB8888,
4407 DRM_FORMAT_ARGB8888,
4408 DRM_FORMAT_RGBA8888,
4409 DRM_FORMAT_XRGB2101010,
4410 DRM_FORMAT_XBGR2101010,
4411 DRM_FORMAT_ARGB2101010,
4412 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 4413 DRM_FORMAT_XBGR8888,
4414 DRM_FORMAT_ABGR8888,
46dd9ff7 4415 DRM_FORMAT_RGB565,
e7b07cee
HW		 4416};
4417
0d579c7e
NK		 4418static const uint32_t overlay_formats[] = {
4419 DRM_FORMAT_XRGB8888,
4420 DRM_FORMAT_ARGB8888,
4421 DRM_FORMAT_RGBA8888,
4422 DRM_FORMAT_XBGR8888,
4423 DRM_FORMAT_ABGR8888,
7267a1a9 4424 DRM_FORMAT_RGB565
e7b07cee
HW		 4425};
4426
4427static const u32 cursor_formats[] = {
4428 DRM_FORMAT_ARGB8888
4429};
4430
37c6a93b
NK		 4431static int get_plane_formats(const struct drm_plane *plane,
4432 const struct dc_plane_cap *plane_cap,
4433 uint32_t *formats, int max_formats)
e7b07cee 4434{
37c6a93b
NK		 4435 int i, num_formats = 0;
4436
4437 /*
4438 * TODO: Query support for each group of formats directly from
4439 * DC plane caps. This will require adding more formats to the
4440 * caps list.
4441 */
e7b07cee 4442
f180b4bc 4443 switch (plane->type) {
e7b07cee 4444 case DRM_PLANE_TYPE_PRIMARY:
37c6a93b
NK		 4445 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
4446 if (num_formats >= max_formats)
4447 break;
4448
4449 formats[num_formats++] = rgb_formats[i];
4450 }
4451
ea36ad34 4452 if (plane_cap && plane_cap->pixel_format_support.nv12)
37c6a93b 4453 formats[num_formats++] = DRM_FORMAT_NV12;
e7b07cee 4454 break;
37c6a93b 4455
e7b07cee 4456 case DRM_PLANE_TYPE_OVERLAY:
37c6a93b
NK		 4457 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
4458 if (num_formats >= max_formats)
4459 break;
4460
4461 formats[num_formats++] = overlay_formats[i];
4462 }
e7b07cee 4463 break;
37c6a93b 4464
e7b07cee 4465 case DRM_PLANE_TYPE_CURSOR:
37c6a93b
NK		 4466 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
4467 if (num_formats >= max_formats)
4468 break;
4469
4470 formats[num_formats++] = cursor_formats[i];
4471 }
e7b07cee
HW		 4472 break;
4473 }
4474
37c6a93b
NK		 4475 return num_formats;
4476}
4477
4478static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4479 struct drm_plane *plane,
4480 unsigned long possible_crtcs,
4481 const struct dc_plane_cap *plane_cap)
4482{
4483 uint32_t formats[32];
4484 int num_formats;
4485 int res = -EPERM;
4486
4487 num_formats = get_plane_formats(plane, plane_cap, formats,
4488 ARRAY_SIZE(formats));
4489
4490 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
4491 &dm_plane_funcs, formats, num_formats,
4492 NULL, plane->type, NULL);
4493 if (res)
4494 return res;
4495
cc1fec57
NK		 4496 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4497 plane_cap && plane_cap->per_pixel_alpha) {
d74004b6
NK		 4498 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4499 BIT(DRM_MODE_BLEND_PREMULTI);
4500
4501 drm_plane_create_alpha_property(plane);
4502 drm_plane_create_blend_mode_property(plane, blend_caps);
4503 }
4504
fc8e5230 4505 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
ea36ad34 4506 plane_cap && plane_cap->pixel_format_support.nv12) {
fc8e5230
NK		 4507 /* This only affects YUV formats. */
4508 drm_plane_create_color_properties(
4509 plane,
4510 BIT(DRM_COLOR_YCBCR_BT601) |
4511 BIT(DRM_COLOR_YCBCR_BT709),
4512 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
4513 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
4514 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
4515 }
4516
f180b4bc 4517 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 4518
96719c54 4519 /* Create (reset) the plane state */
f180b4bc
HW		 4520 if (plane->funcs->reset)
4521 plane->funcs->reset(plane);
96719c54 4522
37c6a93b 4523 return 0;
e7b07cee
HW		 4524}
4525
7578ecda
AD		 4526static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
4527 struct drm_plane *plane,
4528 uint32_t crtc_index)
e7b07cee
HW		 4529{
4530 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 4531 struct drm_plane *cursor_plane;
e7b07cee
HW		 4532
4533 int res = -ENOMEM;
4534
4535 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
4536 if (!cursor_plane)
4537 goto fail;
4538
f180b4bc 4539 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
cc1fec57 4540 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
e7b07cee
HW		 4541
4542 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
4543 if (!acrtc)
4544 goto fail;
4545
4546 res = drm_crtc_init_with_planes(
4547 dm->ddev,
4548 &acrtc->base,
4549 plane,
f180b4bc 4550 cursor_plane,
e7b07cee
HW		 4551 &amdgpu_dm_crtc_funcs, NULL);
4552
4553 if (res)
4554 goto fail;
4555
4556 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
4557
96719c54
HW		 4558 /* Create (reset) the plane state */
4559 if (acrtc->base.funcs->reset)
4560 acrtc->base.funcs->reset(&acrtc->base);
4561
e7b07cee
HW		 4562 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
4563 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4564
4565 acrtc->crtc_id = crtc_index;
4566 acrtc->base.enabled = false;
c37e2d29 4567 acrtc->otg_inst = -1;
e7b07cee
HW		 4568
4569 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 4570 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
4571 true, MAX_COLOR_LUT_ENTRIES);
086247a4 4572 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 4573
4574 return 0;
4575
4576fail:
b830ebc9
HW		 4577 kfree(acrtc);
4578 kfree(cursor_plane);
e7b07cee
HW		 4579 return res;
4580}
4581
4582
4583static int to_drm_connector_type(enum signal_type st)
4584{
4585 switch (st) {
4586 case SIGNAL_TYPE_HDMI_TYPE_A:
4587 return DRM_MODE_CONNECTOR_HDMIA;
4588 case SIGNAL_TYPE_EDP:
4589 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 4590 case SIGNAL_TYPE_LVDS:
4591 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 4592 case SIGNAL_TYPE_RGB:
4593 return DRM_MODE_CONNECTOR_VGA;
4594 case SIGNAL_TYPE_DISPLAY_PORT:
4595 case SIGNAL_TYPE_DISPLAY_PORT_MST:
4596 return DRM_MODE_CONNECTOR_DisplayPort;
4597 case SIGNAL_TYPE_DVI_DUAL_LINK:
4598 case SIGNAL_TYPE_DVI_SINGLE_LINK:
4599 return DRM_MODE_CONNECTOR_DVID;
4600 case SIGNAL_TYPE_VIRTUAL:
4601 return DRM_MODE_CONNECTOR_VIRTUAL;
4602
4603 default:
4604 return DRM_MODE_CONNECTOR_Unknown;
4605 }
4606}
4607
2b4c1c05
DV		 4608static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
4609{
4610 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
4611}
4612
e7b07cee
HW		 4613static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
4614{
e7b07cee
HW		 4615 struct drm_encoder *encoder;
4616 struct amdgpu_encoder *amdgpu_encoder;
4617
2b4c1c05 4618 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 4619
4620 if (encoder == NULL)
4621 return;
4622
4623 amdgpu_encoder = to_amdgpu_encoder(encoder);
4624
4625 amdgpu_encoder->native_mode.clock = 0;
4626
4627 if (!list_empty(&connector->probed_modes)) {
4628 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 4629
e7b07cee 4630 list_for_each_entry(preferred_mode,
b830ebc9
HW		 4631 &connector->probed_modes,
4632 head) {
4633 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
4634 amdgpu_encoder->native_mode = *preferred_mode;
4635
e7b07cee
HW		 4636 break;
4637 }
4638
4639 }
4640}
4641
3ee6b26b
AD		 4642static struct drm_display_mode *
4643amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4644 char *name,
4645 int hdisplay, int vdisplay)
e7b07cee
HW		 4646{
4647 struct drm_device *dev = encoder->dev;
4648 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4649 struct drm_display_mode *mode = NULL;
4650 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4651
4652 mode = drm_mode_duplicate(dev, native_mode);
4653
b830ebc9 4654 if (mode == NULL)
e7b07cee
HW		 4655 return NULL;
4656
4657 mode->hdisplay = hdisplay;
4658 mode->vdisplay = vdisplay;
4659 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 4660 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 4661
4662 return mode;
4663
4664}
4665
4666static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 4667 struct drm_connector *connector)
e7b07cee
HW		 4668{
4669 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4670 struct drm_display_mode *mode = NULL;
4671 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 4672 struct amdgpu_dm_connector *amdgpu_dm_connector =
4673 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4674 int i;
4675 int n;
4676 struct mode_size {
4677 char name[DRM_DISPLAY_MODE_LEN];
4678 int w;
4679 int h;
b830ebc9 4680 } common_modes[] = {
e7b07cee
HW		 4681 { "640x480", 640, 480},
4682 { "800x600", 800, 600},
4683 { "1024x768", 1024, 768},
4684 { "1280x720", 1280, 720},
4685 { "1280x800", 1280, 800},
4686 {"1280x1024", 1280, 1024},
4687 { "1440x900", 1440, 900},
4688 {"1680x1050", 1680, 1050},
4689 {"1600x1200", 1600, 1200},
4690 {"1920x1080", 1920, 1080},
4691 {"1920x1200", 1920, 1200}
4692 };
4693
b830ebc9 4694 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 4695
4696 for (i = 0; i < n; i++) {
4697 struct drm_display_mode *curmode = NULL;
4698 bool mode_existed = false;
4699
4700 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 4701 common_modes[i].h > native_mode->vdisplay ||
4702 (common_modes[i].w == native_mode->hdisplay &&
4703 common_modes[i].h == native_mode->vdisplay))
4704 continue;
e7b07cee
HW		 4705
4706 list_for_each_entry(curmode, &connector->probed_modes, head) {
4707 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 4708 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 4709 mode_existed = true;
4710 break;
4711 }
4712 }
4713
4714 if (mode_existed)
4715 continue;
4716
4717 mode = amdgpu_dm_create_common_mode(encoder,
4718 common_modes[i].name, common_modes[i].w,
4719 common_modes[i].h);
4720 drm_mode_probed_add(connector, mode);
c84dec2f 4721 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 4722 }
4723}
4724
3ee6b26b
AD		 4725static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4726 struct edid *edid)
e7b07cee 4727{
c84dec2f
HW		 4728 struct amdgpu_dm_connector *amdgpu_dm_connector =
4729 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4730
4731 if (edid) {
4732 /* empty probed_modes */
4733 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 4734 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 4735 drm_add_edid_modes(connector, edid);
4736
f1e5e913
YMM		 4737 /* sorting the probed modes before calling function
4738 * amdgpu_dm_get_native_mode() since EDID can have
4739 * more than one preferred mode. The modes that are
4740 * later in the probed mode list could be of higher
4741 * and preferred resolution. For example, 3840x2160
4742 * resolution in base EDID preferred timing and 4096x2160
4743 * preferred resolution in DID extension block later.
4744 */
4745 drm_mode_sort(&connector->probed_modes);
e7b07cee 4746 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 4747 } else {
c84dec2f 4748 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 4749 }
e7b07cee
HW		 4750}
4751
7578ecda 4752static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 4753{
c84dec2f
HW		 4754 struct amdgpu_dm_connector *amdgpu_dm_connector =
4755 to_amdgpu_dm_connector(connector);
e7b07cee 4756 struct drm_encoder *encoder;
c84dec2f 4757 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 4758
2b4c1c05 4759 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 4760
85ee15d6 4761 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 4762 amdgpu_dm_connector->num_modes =
4763 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 4764 } else {
4765 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4766 amdgpu_dm_connector_add_common_modes(encoder, connector);
4767 }
3e332d3a 4768 amdgpu_dm_fbc_init(connector);
5099114b 4769
c84dec2f 4770 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 4771}
4772
3ee6b26b
AD		 4773void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4774 struct amdgpu_dm_connector *aconnector,
4775 int connector_type,
4776 struct dc_link *link,
4777 int link_index)
e7b07cee
HW		 4778{
4779 struct amdgpu_device *adev = dm->ddev->dev_private;
4780
4781 aconnector->connector_id = link_index;
4782 aconnector->dc_link = link;
4783 aconnector->base.interlace_allowed = false;
4784 aconnector->base.doublescan_allowed = false;
4785 aconnector->base.stereo_allowed = false;
4786 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4787 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
e7b07cee
HW		 4788 mutex_init(&aconnector->hpd_lock);
4789
1f6010a9
DF		 4790 /*
4791 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 4792 * which means HPD hot plug not supported
4793 */
e7b07cee
HW		 4794 switch (connector_type) {
4795 case DRM_MODE_CONNECTOR_HDMIA:
4796 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4797 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4798 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 4799 break;
4800 case DRM_MODE_CONNECTOR_DisplayPort:
4801 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4802 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4803 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 4804 break;
4805 case DRM_MODE_CONNECTOR_DVID:
4806 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4807 break;
4808 default:
4809 break;
4810 }
4811
4812 drm_object_attach_property(&aconnector->base.base,
4813 dm->ddev->mode_config.scaling_mode_property,
4814 DRM_MODE_SCALE_NONE);
4815
4816 drm_object_attach_property(&aconnector->base.base,
4817 adev->mode_info.underscan_property,
4818 UNDERSCAN_OFF);
4819 drm_object_attach_property(&aconnector->base.base,
4820 adev->mode_info.underscan_hborder_property,
4821 0);
4822 drm_object_attach_property(&aconnector->base.base,
4823 adev->mode_info.underscan_vborder_property,
4824 0);
1825fd34
NK		 4825
4826 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
4827
4828 /* This defaults to the max in the range, but we want 8bpc. */
4829 aconnector->base.state->max_bpc = 8;
4830 aconnector->base.state->max_requested_bpc = 8;
e7b07cee 4831
c1ee92f9
DF		 4832 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4833 dc_is_dmcu_initialized(adev->dm.dc)) {
4834 drm_object_attach_property(&aconnector->base.base,
4835 adev->mode_info.abm_level_property, 0);
4836 }
bb47de73
NK		 4837
4838 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7fad8da1
NK		 4839 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4840 connector_type == DRM_MODE_CONNECTOR_eDP) {
88694af9
NK		 4841 drm_object_attach_property(
4842 &aconnector->base.base,
4843 dm->ddev->mode_config.hdr_output_metadata_property, 0);
4844
bb47de73
NK		 4845 drm_connector_attach_vrr_capable_property(
4846 &aconnector->base);
4847 }
e7b07cee
HW		 4848}
4849
7578ecda
AD		 4850static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4851 struct i2c_msg *msgs, int num)
e7b07cee
HW		 4852{
4853 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4854 struct ddc_service *ddc_service = i2c->ddc_service;
4855 struct i2c_command cmd;
4856 int i;
4857 int result = -EIO;
4858
b830ebc9 4859 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 4860
4861 if (!cmd.payloads)
4862 return result;
4863
4864 cmd.number_of_payloads = num;
4865 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4866 cmd.speed = 100;
4867
4868 for (i = 0; i < num; i++) {
4869 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4870 cmd.payloads[i].address = msgs[i].addr;
4871 cmd.payloads[i].length = msgs[i].len;
4872 cmd.payloads[i].data = msgs[i].buf;
4873 }
4874
c85e6e54
DF		 4875 if (dc_submit_i2c(
4876 ddc_service->ctx->dc,
4877 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 4878 &cmd))
4879 result = num;
4880
4881 kfree(cmd.payloads);
4882 return result;
4883}
4884
7578ecda 4885static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 4886{
4887 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4888}
4889
4890static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4891 .master_xfer = amdgpu_dm_i2c_xfer,
4892 .functionality = amdgpu_dm_i2c_func,
4893};
4894
3ee6b26b
AD		 4895static struct amdgpu_i2c_adapter *
4896create_i2c(struct ddc_service *ddc_service,
4897 int link_index,
4898 int *res)
e7b07cee
HW		 4899{
4900 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4901 struct amdgpu_i2c_adapter *i2c;
4902
b830ebc9 4903 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 4904 if (!i2c)
4905 return NULL;
e7b07cee
HW		 4906 i2c->base.owner = THIS_MODULE;
4907 i2c->base.class = I2C_CLASS_DDC;
4908 i2c->base.dev.parent = &adev->pdev->dev;
4909 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 4910 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 4911 i2c_set_adapdata(&i2c->base, i2c);
4912 i2c->ddc_service = ddc_service;
c85e6e54 4913 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 4914
4915 return i2c;
4916}
4917
89fc8d4e 4918
1f6010a9
DF		 4919/*
4920 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 4921 * dc_link which will be represented by this aconnector.
4922 */
7578ecda
AD		 4923static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4924 struct amdgpu_dm_connector *aconnector,
4925 uint32_t link_index,
4926 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 4927{
4928 int res = 0;
4929 int connector_type;
4930 struct dc *dc = dm->dc;
4931 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4932 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 4933
4934 link->priv = aconnector;
e7b07cee 4935
f1ad2f5e 4936 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 4937
4938 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 4939 if (!i2c) {
4940 DRM_ERROR("Failed to create i2c adapter data\n");
4941 return -ENOMEM;
4942 }
4943
e7b07cee
HW		 4944 aconnector->i2c = i2c;
4945 res = i2c_add_adapter(&i2c->base);
4946
4947 if (res) {
4948 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4949 goto out_free;
4950 }
4951
4952 connector_type = to_drm_connector_type(link->connector_signal);
4953
4954 res = drm_connector_init(
4955 dm->ddev,
4956 &aconnector->base,
4957 &amdgpu_dm_connector_funcs,
4958 connector_type);
4959
4960 if (res) {
4961 DRM_ERROR("connector_init failed\n");
4962 aconnector->connector_id = -1;
4963 goto out_free;
4964 }
4965
4966 drm_connector_helper_add(
4967 &aconnector->base,
4968 &amdgpu_dm_connector_helper_funcs);
4969
96719c54
HW		 4970 if (aconnector->base.funcs->reset)
4971 aconnector->base.funcs->reset(&aconnector->base);
4972
e7b07cee
HW		 4973 amdgpu_dm_connector_init_helper(
4974 dm,
4975 aconnector,
4976 connector_type,
4977 link,
4978 link_index);
4979
cde4c44d 4980 drm_connector_attach_encoder(
e7b07cee
HW		 4981 &aconnector->base, &aencoder->base);
4982
4983 drm_connector_register(&aconnector->base);
dc38fd9d
DF		 4984#if defined(CONFIG_DEBUG_FS)
4985 res = connector_debugfs_init(aconnector);
4986 if (res) {
4987 DRM_ERROR("Failed to create debugfs for connector");
4988 goto out_free;
4989 }
f258fee6
DF		 4990 aconnector->debugfs_dpcd_address = 0;
4991 aconnector->debugfs_dpcd_size = 0;
dc38fd9d 4992#endif
e7b07cee
HW		 4993
4994 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4995 || connector_type == DRM_MODE_CONNECTOR_eDP)
4996 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4997
e7b07cee
HW		 4998out_free:
4999 if (res) {
5000 kfree(i2c);
5001 aconnector->i2c = NULL;
5002 }
5003 return res;
5004}
5005
5006int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
5007{
5008 switch (adev->mode_info.num_crtc) {
5009 case 1:
5010 return 0x1;
5011 case 2:
5012 return 0x3;
5013 case 3:
5014 return 0x7;
5015 case 4:
5016 return 0xf;
5017 case 5:
5018 return 0x1f;
5019 case 6:
5020 default:
5021 return 0x3f;
5022 }
5023}
5024
7578ecda
AD		 5025static int amdgpu_dm_encoder_init(struct drm_device *dev,
5026 struct amdgpu_encoder *aencoder,
5027 uint32_t link_index)
e7b07cee
HW		 5028{
5029 struct amdgpu_device *adev = dev->dev_private;
5030
5031 int res = drm_encoder_init(dev,
5032 &aencoder->base,
5033 &amdgpu_dm_encoder_funcs,
5034 DRM_MODE_ENCODER_TMDS,
5035 NULL);
5036
5037 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
5038
5039 if (!res)
5040 aencoder->encoder_id = link_index;
5041 else
5042 aencoder->encoder_id = -1;
5043
5044 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
5045
5046 return res;
5047}
5048
3ee6b26b
AD		 5049static void manage_dm_interrupts(struct amdgpu_device *adev,
5050 struct amdgpu_crtc *acrtc,
5051 bool enable)
e7b07cee
HW		 5052{
5053 /*
5054 * this is not correct translation but will work as soon as VBLANK
5055 * constant is the same as PFLIP
5056 */
5057 int irq_type =
734dd01d 5058 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 5059 adev,
5060 acrtc->crtc_id);
5061
5062 if (enable) {
5063 drm_crtc_vblank_on(&acrtc->base);
5064 amdgpu_irq_get(
5065 adev,
5066 &adev->pageflip_irq,
5067 irq_type);
5068 } else {
5069
5070 amdgpu_irq_put(
5071 adev,
5072 &adev->pageflip_irq,
5073 irq_type);
5074 drm_crtc_vblank_off(&acrtc->base);
5075 }
5076}
5077
3ee6b26b
AD		 5078static bool
5079is_scaling_state_different(const struct dm_connector_state *dm_state,
5080 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 5081{
5082 if (dm_state->scaling != old_dm_state->scaling)
5083 return true;
5084 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
5085 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
5086 return true;
5087 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
5088 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
5089 return true;
b830ebc9
HW		 5090 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
5091 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
5092 return true;
e7b07cee
HW		 5093 return false;
5094}
5095
3ee6b26b
AD		 5096static void remove_stream(struct amdgpu_device *adev,
5097 struct amdgpu_crtc *acrtc,
5098 struct dc_stream_state *stream)
e7b07cee
HW		 5099{
5100 /* this is the update mode case */
e7b07cee
HW		 5101
5102 acrtc->otg_inst = -1;
5103 acrtc->enabled = false;
5104}
5105
7578ecda
AD		 5106static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
5107 struct dc_cursor_position *position)
2a8f6ccb 5108{
f4c2cc43 5109 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 5110 int x, y;
5111 int xorigin = 0, yorigin = 0;
5112
e371e19c
NK		 5113 position->enable = false;
5114 position->x = 0;
5115 position->y = 0;
5116
5117 if (!crtc || !plane->state->fb)
2a8f6ccb 5118 return 0;
2a8f6ccb
HW		 5119
5120 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
5121 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
5122 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
5123 __func__,
5124 plane->state->crtc_w,
5125 plane->state->crtc_h);
5126 return -EINVAL;
5127 }
5128
5129 x = plane->state->crtc_x;
5130 y = plane->state->crtc_y;
c14a005c 5131
e371e19c
NK		 5132 if (x <= -amdgpu_crtc->max_cursor_width ||
5133 y <= -amdgpu_crtc->max_cursor_height)
5134 return 0;
5135
c14a005c
NK		 5136 if (crtc->primary->state) {
5137 /* avivo cursor are offset into the total surface */
5138 x += crtc->primary->state->src_x >> 16;
5139 y += crtc->primary->state->src_y >> 16;
5140 }
5141
2a8f6ccb
HW		 5142 if (x < 0) {
5143 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
5144 x = 0;
5145 }
5146 if (y < 0) {
5147 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
5148 y = 0;
5149 }
5150 position->enable = true;
5151 position->x = x;
5152 position->y = y;
5153 position->x_hotspot = xorigin;
5154 position->y_hotspot = yorigin;
5155
5156 return 0;
5157}
5158
3ee6b26b
AD		 5159static void handle_cursor_update(struct drm_plane *plane,
5160 struct drm_plane_state *old_plane_state)
e7b07cee 5161{
674e78ac 5162 struct amdgpu_device *adev = plane->dev->dev_private;
2a8f6ccb
HW		 5163 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
5164 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
5165 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
5166 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5167 uint64_t address = afb ? afb->address : 0;
5168 struct dc_cursor_position position;
5169 struct dc_cursor_attributes attributes;
5170 int ret;
5171
e7b07cee
HW		 5172 if (!plane->state->fb && !old_plane_state->fb)
5173 return;
5174
f1ad2f5e 5175 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 5176 __func__,
5177 amdgpu_crtc->crtc_id,
5178 plane->state->crtc_w,
5179 plane->state->crtc_h);
2a8f6ccb
HW		 5180
5181 ret = get_cursor_position(plane, crtc, &position);
5182 if (ret)
5183 return;
5184
5185 if (!position.enable) {
5186 /* turn off cursor */
674e78ac
NK		 5187 if (crtc_state && crtc_state->stream) {
5188 mutex_lock(&adev->dm.dc_lock);
2a8f6ccb
HW		 5189 dc_stream_set_cursor_position(crtc_state->stream,
5190 &position);
674e78ac
NK		 5191 mutex_unlock(&adev->dm.dc_lock);
5192 }
2a8f6ccb 5193 return;
e7b07cee 5194 }
e7b07cee 5195
2a8f6ccb
HW		 5196 amdgpu_crtc->cursor_width = plane->state->crtc_w;
5197 amdgpu_crtc->cursor_height = plane->state->crtc_h;
5198
c1cefe11 5199 memset(&attributes, 0, sizeof(attributes));
2a8f6ccb
HW		 5200 attributes.address.high_part = upper_32_bits(address);
5201 attributes.address.low_part = lower_32_bits(address);
5202 attributes.width = plane->state->crtc_w;
5203 attributes.height = plane->state->crtc_h;
5204 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
5205 attributes.rotation_angle = 0;
5206 attributes.attribute_flags.value = 0;
5207
5208 attributes.pitch = attributes.width;
5209
886daac9 5210 if (crtc_state->stream) {
674e78ac 5211 mutex_lock(&adev->dm.dc_lock);
886daac9
JZ		 5212 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
5213 &attributes))
5214 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 5215
2a8f6ccb
HW		 5216 if (!dc_stream_set_cursor_position(crtc_state->stream,
5217 &position))
5218 DRM_ERROR("DC failed to set cursor position\n");
674e78ac 5219 mutex_unlock(&adev->dm.dc_lock);
886daac9 5220 }
2a8f6ccb 5221}
e7b07cee
HW		 5222
5223static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
5224{
5225
5226 assert_spin_locked(&acrtc->base.dev->event_lock);
5227 WARN_ON(acrtc->event);
5228
5229 acrtc->event = acrtc->base.state->event;
5230
5231 /* Set the flip status */
5232 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
5233
5234 /* Mark this event as consumed */
5235 acrtc->base.state->event = NULL;
5236
5237 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
5238 acrtc->crtc_id);
5239}
5240
bb47de73
NK		 5241static void update_freesync_state_on_stream(
5242 struct amdgpu_display_manager *dm,
5243 struct dm_crtc_state *new_crtc_state,
180db303
NK		 5244 struct dc_stream_state *new_stream,
5245 struct dc_plane_state *surface,
5246 u32 flip_timestamp_in_us)
bb47de73 5247{
09aef2c4 5248 struct mod_vrr_params vrr_params;
bb47de73 5249 struct dc_info_packet vrr_infopacket = {0};
09aef2c4
MK		 5250 struct amdgpu_device *adev = dm->adev;
5251 unsigned long flags;
bb47de73
NK		 5252
5253 if (!new_stream)
5254 return;
5255
5256 /*
5257 * TODO: Determine why min/max totals and vrefresh can be 0 here.
5258 * For now it's sufficient to just guard against these conditions.
5259 */
5260
5261 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5262 return;
5263
09aef2c4
MK		 5264 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5265 vrr_params = new_crtc_state->vrr_params;
5266
180db303
NK		 5267 if (surface) {
5268 mod_freesync_handle_preflip(
5269 dm->freesync_module,
5270 surface,
5271 new_stream,
5272 flip_timestamp_in_us,
5273 &vrr_params);
09aef2c4
MK		 5274
5275 if (adev->family < AMDGPU_FAMILY_AI &&
5276 amdgpu_dm_vrr_active(new_crtc_state)) {
5277 mod_freesync_handle_v_update(dm->freesync_module,
5278 new_stream, &vrr_params);
e63e2491
EB		 5279
5280 /* Need to call this before the frame ends. */
5281 dc_stream_adjust_vmin_vmax(dm->dc,
5282 new_crtc_state->stream,
5283 &vrr_params.adjust);
09aef2c4 5284 }
180db303 5285 }
bb47de73
NK		 5286
5287 mod_freesync_build_vrr_infopacket(
5288 dm->freesync_module,
5289 new_stream,
180db303 5290 &vrr_params,
ecd0136b
HT		 5291 PACKET_TYPE_VRR,
5292 TRANSFER_FUNC_UNKNOWN,
bb47de73
NK		 5293 &vrr_infopacket);
5294
8a48b44c 5295 new_crtc_state->freesync_timing_changed |=
180db303
NK		 5296 (memcmp(&new_crtc_state->vrr_params.adjust,
5297 &vrr_params.adjust,
5298 sizeof(vrr_params.adjust)) != 0);
bb47de73 5299
8a48b44c 5300 new_crtc_state->freesync_vrr_info_changed |=
bb47de73
NK		 5301 (memcmp(&new_crtc_state->vrr_infopacket,
5302 &vrr_infopacket,
5303 sizeof(vrr_infopacket)) != 0);
5304
180db303 5305 new_crtc_state->vrr_params = vrr_params;
bb47de73
NK		 5306 new_crtc_state->vrr_infopacket = vrr_infopacket;
5307
180db303 5308 new_stream->adjust = new_crtc_state->vrr_params.adjust;
bb47de73
NK		 5309 new_stream->vrr_infopacket = vrr_infopacket;
5310
5311 if (new_crtc_state->freesync_vrr_info_changed)
5312 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
5313 new_crtc_state->base.crtc->base.id,
5314 (int)new_crtc_state->base.vrr_enabled,
180db303 5315 (int)vrr_params.state);
09aef2c4
MK		 5316
5317 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
bb47de73
NK		 5318}
5319
e854194c
MK		 5320static void pre_update_freesync_state_on_stream(
5321 struct amdgpu_display_manager *dm,
5322 struct dm_crtc_state *new_crtc_state)
5323{
5324 struct dc_stream_state *new_stream = new_crtc_state->stream;
09aef2c4 5325 struct mod_vrr_params vrr_params;
e854194c 5326 struct mod_freesync_config config = new_crtc_state->freesync_config;
09aef2c4
MK		 5327 struct amdgpu_device *adev = dm->adev;
5328 unsigned long flags;
e854194c
MK		 5329
5330 if (!new_stream)
5331 return;
5332
5333 /*
5334 * TODO: Determine why min/max totals and vrefresh can be 0 here.
5335 * For now it's sufficient to just guard against these conditions.
5336 */
5337 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5338 return;
5339
09aef2c4
MK		 5340 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5341 vrr_params = new_crtc_state->vrr_params;
5342
e854194c
MK		 5343 if (new_crtc_state->vrr_supported &&
5344 config.min_refresh_in_uhz &&
5345 config.max_refresh_in_uhz) {
5346 config.state = new_crtc_state->base.vrr_enabled ?
5347 VRR_STATE_ACTIVE_VARIABLE :
5348 VRR_STATE_INACTIVE;
5349 } else {
5350 config.state = VRR_STATE_UNSUPPORTED;
5351 }
5352
5353 mod_freesync_build_vrr_params(dm->freesync_module,
5354 new_stream,
5355 &config, &vrr_params);
5356
5357 new_crtc_state->freesync_timing_changed |=
5358 (memcmp(&new_crtc_state->vrr_params.adjust,
5359 &vrr_params.adjust,
5360 sizeof(vrr_params.adjust)) != 0);
5361
5362 new_crtc_state->vrr_params = vrr_params;
09aef2c4 5363 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
e854194c
MK		 5364}
5365
66b0c973
MK		 5366static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
5367 struct dm_crtc_state *new_state)
5368{
5369 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
5370 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
5371
5372 if (!old_vrr_active && new_vrr_active) {
5373 /* Transition VRR inactive -> active:
5374 * While VRR is active, we must not disable vblank irq, as a
5375 * reenable after disable would compute bogus vblank/pflip
5376 * timestamps if it likely happened inside display front-porch.
d2574c33
MK		 5377 *
5378 * We also need vupdate irq for the actual core vblank handling
5379 * at end of vblank.
66b0c973 5380 */
d2574c33 5381 dm_set_vupdate_irq(new_state->base.crtc, true);
66b0c973
MK		 5382 drm_crtc_vblank_get(new_state->base.crtc);
5383 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
5384 __func__, new_state->base.crtc->base.id);
5385 } else if (old_vrr_active && !new_vrr_active) {
5386 /* Transition VRR active -> inactive:
5387 * Allow vblank irq disable again for fixed refresh rate.
5388 */
d2574c33 5389 dm_set_vupdate_irq(new_state->base.crtc, false);
66b0c973
MK		 5390 drm_crtc_vblank_put(new_state->base.crtc);
5391 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
5392 __func__, new_state->base.crtc->base.id);
5393 }
5394}
5395
8ad27806
NK		 5396static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
5397{
5398 struct drm_plane *plane;
5399 struct drm_plane_state *old_plane_state, *new_plane_state;
5400 int i;
5401
5402 /*
5403 * TODO: Make this per-stream so we don't issue redundant updates for
5404 * commits with multiple streams.
5405 */
5406 for_each_oldnew_plane_in_state(state, plane, old_plane_state,
5407 new_plane_state, i)
5408 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5409 handle_cursor_update(plane, old_plane_state);
5410}
5411
3be5262e 5412static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 5413 struct dc_state *dc_state,
3ee6b26b
AD		 5414 struct drm_device *dev,
5415 struct amdgpu_display_manager *dm,
5416 struct drm_crtc *pcrtc,
420cd472 5417 bool wait_for_vblank)
e7b07cee 5418{
570c91d5 5419 uint32_t i;
8a48b44c 5420 uint64_t timestamp_ns;
e7b07cee 5421 struct drm_plane *plane;
0bc9706d 5422 struct drm_plane_state *old_plane_state, *new_plane_state;
e7b07cee 5423 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 5424 struct drm_crtc_state *new_pcrtc_state =
5425 drm_atomic_get_new_crtc_state(state, pcrtc);
5426 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 5427 struct dm_crtc_state *dm_old_crtc_state =
5428 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
74aa7bd4 5429 int planes_count = 0, vpos, hpos;
570c91d5 5430 long r;
e7b07cee 5431 unsigned long flags;
8a48b44c 5432 struct amdgpu_bo *abo;
09e5665a 5433 uint64_t tiling_flags;
fdd1fe57
MK		 5434 uint32_t target_vblank, last_flip_vblank;
5435 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
74aa7bd4 5436 bool pflip_present = false;
bc7f670e
DF		 5437 struct {
5438 struct dc_surface_update surface_updates[MAX_SURFACES];
5439 struct dc_plane_info plane_infos[MAX_SURFACES];
5440 struct dc_scaling_info scaling_infos[MAX_SURFACES];
74aa7bd4 5441 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
bc7f670e 5442 struct dc_stream_update stream_update;
74aa7bd4 5443 } *bundle;
bc7f670e 5444
74aa7bd4 5445 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8a48b44c 5446
74aa7bd4
DF		 5447 if (!bundle) {
5448 dm_error("Failed to allocate update bundle\n");
4b510503
NK		 5449 goto cleanup;
5450 }
e7b07cee 5451
8ad27806
NK		 5452 /*
5453 * Disable the cursor first if we're disabling all the planes.
5454 * It'll remain on the screen after the planes are re-enabled
5455 * if we don't.
5456 */
5457 if (acrtc_state->active_planes == 0)
5458 amdgpu_dm_commit_cursors(state);
5459
e7b07cee 5460 /* update planes when needed */
0bc9706d
LSL		 5461 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
5462 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 5463 struct drm_crtc_state *new_crtc_state;
0bc9706d 5464 struct drm_framebuffer *fb = new_plane_state->fb;
34bafd27 5465 bool plane_needs_flip;
c7af5f77 5466 struct dc_plane_state *dc_plane;
54d76575 5467 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee 5468
80c218d5
NK		 5469 /* Cursor plane is handled after stream updates */
5470 if (plane->type == DRM_PLANE_TYPE_CURSOR)
e7b07cee 5471 continue;
e7b07cee 5472
f5ba60fe
DD		 5473 if (!fb || !crtc || pcrtc != crtc)
5474 continue;
5475
5476 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
5477 if (!new_crtc_state->active)
e7b07cee
HW		 5478 continue;
5479
bc7f670e 5480 dc_plane = dm_new_plane_state->dc_state;
e7b07cee 5481
74aa7bd4 5482 bundle->surface_updates[planes_count].surface = dc_plane;
bc7f670e 5483 if (new_pcrtc_state->color_mgmt_changed) {
74aa7bd4
DF		 5484 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
5485 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
bc7f670e 5486 }
8a48b44c 5487
695af5f9
NK		 5488 fill_dc_scaling_info(new_plane_state,
5489 &bundle->scaling_infos[planes_count]);
8a48b44c 5490
695af5f9
NK		 5491 bundle->surface_updates[planes_count].scaling_info =
5492 &bundle->scaling_infos[planes_count];
8a48b44c 5493
f5031000 5494 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8a48b44c 5495
f5031000 5496 pflip_present = pflip_present || plane_needs_flip;
8a48b44c 5497
f5031000
DF		 5498 if (!plane_needs_flip) {
5499 planes_count += 1;
5500 continue;
5501 }
8a48b44c 5502
2fac0f53
CK		 5503 abo = gem_to_amdgpu_bo(fb->obj[0]);
5504
f8308898
AG		 5505 /*
5506 * Wait for all fences on this FB. Do limited wait to avoid
5507 * deadlock during GPU reset when this fence will not signal
5508 * but we hold reservation lock for the BO.
5509 */
2fac0f53
CK		 5510 r = reservation_object_wait_timeout_rcu(abo->tbo.resv, true,
5511 false,
f8308898
AG		 5512 msecs_to_jiffies(5000));
5513 if (unlikely(r <= 0))
5514 DRM_ERROR("Waiting for fences timed out or interrupted!");
2fac0f53 5515
f5031000
DF		 5516 /*
5517 * TODO This might fail and hence better not used, wait
5518 * explicitly on fences instead
5519 * and in general should be called for
5520 * blocking commit to as per framework helpers
5521 */
f5031000 5522 r = amdgpu_bo_reserve(abo, true);
f8308898 5523 if (unlikely(r != 0))
f5031000 5524 DRM_ERROR("failed to reserve buffer before flip\n");
8a48b44c 5525
f5031000 5526 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
8a48b44c 5527
f5031000 5528 amdgpu_bo_unreserve(abo);
8a48b44c 5529
695af5f9
NK		 5530 fill_dc_plane_info_and_addr(
5531 dm->adev, new_plane_state, tiling_flags,
5532 &bundle->plane_infos[planes_count],
5533 &bundle->flip_addrs[planes_count].address);
5534
5535 bundle->surface_updates[planes_count].plane_info =
5536 &bundle->plane_infos[planes_count];
8a48b44c 5537
f5031000
DF		 5538 bundle->flip_addrs[planes_count].flip_immediate =
5539 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
8a48b44c 5540
f5031000
DF		 5541 timestamp_ns = ktime_get_ns();
5542 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
5543 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
5544 bundle->surface_updates[planes_count].surface = dc_plane;
8a48b44c 5545
f5031000
DF		 5546 if (!bundle->surface_updates[planes_count].surface) {
5547 DRM_ERROR("No surface for CRTC: id=%d\n",
5548 acrtc_attach->crtc_id);
5549 continue;
bc7f670e
DF		 5550 }
5551
f5031000
DF		 5552 if (plane == pcrtc->primary)
5553 update_freesync_state_on_stream(
5554 dm,
5555 acrtc_state,
5556 acrtc_state->stream,
5557 dc_plane,
5558 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
bc7f670e 5559
f5031000
DF		 5560 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
5561 __func__,
5562 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
5563 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
bc7f670e
DF		 5564
5565 planes_count += 1;
5566
8a48b44c
DF		 5567 }
5568
74aa7bd4 5569 if (pflip_present) {
634092b1
MK		 5570 if (!vrr_active) {
5571 /* Use old throttling in non-vrr fixed refresh rate mode
5572 * to keep flip scheduling based on target vblank counts
5573 * working in a backwards compatible way, e.g., for
5574 * clients using the GLX_OML_sync_control extension or
5575 * DRI3/Present extension with defined target_msc.
5576 */
fdd1fe57 5577 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
634092b1
MK		 5578 }
5579 else {
5580 /* For variable refresh rate mode only:
5581 * Get vblank of last completed flip to avoid > 1 vrr
5582 * flips per video frame by use of throttling, but allow
5583 * flip programming anywhere in the possibly large
5584 * variable vrr vblank interval for fine-grained flip
5585 * timing control and more opportunity to avoid stutter
5586 * on late submission of flips.
5587 */
5588 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5589 last_flip_vblank = acrtc_attach->last_flip_vblank;
5590 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5591 }
5592
fdd1fe57 5593 target_vblank = last_flip_vblank + wait_for_vblank;
8a48b44c
DF		 5594
5595 /*
5596 * Wait until we're out of the vertical blank period before the one
5597 * targeted by the flip
5598 */
5599 while ((acrtc_attach->enabled &&
5600 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
5601 0, &vpos, &hpos, NULL,
5602 NULL, &pcrtc->hwmode)
5603 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
5604 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
5605 (int)(target_vblank -
5606 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
5607 usleep_range(1000, 1100);
5608 }
5609
5610 if (acrtc_attach->base.state->event) {
5611 drm_crtc_vblank_get(pcrtc);
5612
5613 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5614
5615 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
5616 prepare_flip_isr(acrtc_attach);
5617
5618 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5619 }
5620
5621 if (acrtc_state->stream) {
8a48b44c 5622 if (acrtc_state->freesync_vrr_info_changed)
74aa7bd4 5623 bundle->stream_update.vrr_infopacket =
8a48b44c 5624 &acrtc_state->stream->vrr_infopacket;
e7b07cee 5625 }
e7b07cee
HW		 5626 }
5627
bc92c065
NK		 5628 /* Update the planes if changed or disable if we don't have any. */
5629 if (planes_count || acrtc_state->active_planes == 0) {
bc7f670e 5630 if (new_pcrtc_state->mode_changed) {
74aa7bd4
DF		 5631 bundle->stream_update.src = acrtc_state->stream->src;
5632 bundle->stream_update.dst = acrtc_state->stream->dst;
e7b07cee
HW		 5633 }
5634
bc7f670e 5635 if (new_pcrtc_state->color_mgmt_changed)
74aa7bd4 5636 bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func;
bc7f670e 5637
8a48b44c 5638 acrtc_state->stream->abm_level = acrtc_state->abm_level;
bc7f670e 5639 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
74aa7bd4 5640 bundle->stream_update.abm_level = &acrtc_state->abm_level;
44d09c6a 5641
e63e2491
EB		 5642 /*
5643 * If FreeSync state on the stream has changed then we need to
5644 * re-adjust the min/max bounds now that DC doesn't handle this
5645 * as part of commit.
5646 */
5647 if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
5648 amdgpu_dm_vrr_active(acrtc_state)) {
5649 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5650 dc_stream_adjust_vmin_vmax(
5651 dm->dc, acrtc_state->stream,
5652 &acrtc_state->vrr_params.adjust);
5653 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5654 }
5655
bc7f670e
DF		 5656 mutex_lock(&dm->dc_lock);
5657 dc_commit_updates_for_stream(dm->dc,
74aa7bd4 5658 bundle->surface_updates,
bc7f670e
DF		 5659 planes_count,
5660 acrtc_state->stream,
74aa7bd4 5661 &bundle->stream_update,
bc7f670e
DF		 5662 dc_state);
5663 mutex_unlock(&dm->dc_lock);
e7b07cee 5664 }
4b510503 5665
8ad27806
NK		 5666 /*
5667 * Update cursor state *after* programming all the planes.
5668 * This avoids redundant programming in the case where we're going
5669 * to be disabling a single plane - those pipes are being disabled.
5670 */
5671 if (acrtc_state->active_planes)
5672 amdgpu_dm_commit_cursors(state);
80c218d5 5673
4b510503 5674cleanup:
74aa7bd4 5675 kfree(bundle);
e7b07cee
HW		 5676}
5677
b5e83f6f
NK		 5678/*
5679 * Enable interrupts on CRTCs that are newly active, undergone
5680 * a modeset, or have active planes again.
5681 *
5682 * Done in two passes, based on the for_modeset flag:
5683 * Pass 1: For CRTCs going through modeset
5684 * Pass 2: For CRTCs going from 0 to n active planes
5685 *
5686 * Interrupts can only be enabled after the planes are programmed,
5687 * so this requires a two-pass approach since we don't want to
5688 * just defer the interrupts until after commit planes every time.
5689 */
5690static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
5691 struct drm_atomic_state *state,
5692 bool for_modeset)
5693{
5694 struct amdgpu_device *adev = dev->dev_private;
5695 struct drm_crtc *crtc;
5696 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5697 int i;
5698
5699 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5700 new_crtc_state, i) {
5701 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5702 struct dm_crtc_state *dm_new_crtc_state =
5703 to_dm_crtc_state(new_crtc_state);
5704 struct dm_crtc_state *dm_old_crtc_state =
5705 to_dm_crtc_state(old_crtc_state);
5706 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
5707 bool run_pass;
5708
5709 run_pass = (for_modeset && modeset) ||
5710 (!for_modeset && !modeset &&
5711 !dm_old_crtc_state->interrupts_enabled);
5712
5713 if (!run_pass)
5714 continue;
5715
b5e83f6f
NK		 5716 if (!dm_new_crtc_state->interrupts_enabled)
5717 continue;
5718
5719 manage_dm_interrupts(adev, acrtc, true);
5720
5721#ifdef CONFIG_DEBUG_FS
5722 /* The stream has changed so CRC capture needs to re-enabled. */
5723 if (dm_new_crtc_state->crc_enabled) {
5724 dm_new_crtc_state->crc_enabled = false;
5725 amdgpu_dm_crtc_set_crc_source(crtc, "auto");
5726 }
5727#endif
5728 }
5729}
5730
1f6010a9 5731/*
27b3f4fc
LSL		 5732 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
5733 * @crtc_state: the DRM CRTC state
5734 * @stream_state: the DC stream state.
5735 *
5736 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
5737 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
5738 */
5739static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
5740 struct dc_stream_state *stream_state)
5741{
b9952f93 5742 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
27b3f4fc 5743}
e7b07cee 5744
7578ecda
AD		 5745static int amdgpu_dm_atomic_commit(struct drm_device *dev,
5746 struct drm_atomic_state *state,
5747 bool nonblock)
e7b07cee
HW		 5748{
5749 struct drm_crtc *crtc;
c2cea706 5750 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 5751 struct amdgpu_device *adev = dev->dev_private;
5752 int i;
5753
5754 /*
d6ef9b41
NK		 5755 * We evade vblank and pflip interrupts on CRTCs that are undergoing
5756 * a modeset, being disabled, or have no active planes.
5757 *
5758 * It's done in atomic commit rather than commit tail for now since
5759 * some of these interrupt handlers access the current CRTC state and
5760 * potentially the stream pointer itself.
5761 *
5762 * Since the atomic state is swapped within atomic commit and not within
5763 * commit tail this would leave to new state (that hasn't been committed yet)
5764 * being accesssed from within the handlers.
5765 *
5766 * TODO: Fix this so we can do this in commit tail and not have to block
5767 * in atomic check.
e7b07cee 5768 */
c2cea706 5769 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 5770 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
428da2bd 5771 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 5772 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5773
d6ef9b41
NK		 5774 if (dm_old_crtc_state->interrupts_enabled &&
5775 (!dm_new_crtc_state->interrupts_enabled ||
5776 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
428da2bd 5777 /*
e39575b9
NK		 5778 * Drop the extra vblank reference added by CRC
5779 * capture if applicable.
428da2bd 5780 */
e39575b9 5781 if (dm_new_crtc_state->crc_enabled)
428da2bd 5782 drm_crtc_vblank_put(crtc);
e39575b9
NK		 5783
5784 /*
5785 * Only keep CRC capture enabled if there's
5786 * still a stream for the CRTC.
5787 */
5788 if (!dm_new_crtc_state->stream)
428da2bd 5789 dm_new_crtc_state->crc_enabled = false;
428da2bd 5790
e7b07cee 5791 manage_dm_interrupts(adev, acrtc, false);
428da2bd 5792 }
e7b07cee 5793 }
1f6010a9
DF		 5794 /*
5795 * Add check here for SoC's that support hardware cursor plane, to
5796 * unset legacy_cursor_update
5797 */
e7b07cee
HW		 5798
5799 return drm_atomic_helper_commit(dev, state, nonblock);
5800
5801 /*TODO Handle EINTR, reenable IRQ*/
5802}
5803
b8592b48
LL		 5804/**
5805 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
5806 * @state: The atomic state to commit
5807 *
5808 * This will tell DC to commit the constructed DC state from atomic_check,
5809 * programming the hardware. Any failures here implies a hardware failure, since
5810 * atomic check should have filtered anything non-kosher.
5811 */
7578ecda 5812static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 5813{
5814 struct drm_device *dev = state->dev;
5815 struct amdgpu_device *adev = dev->dev_private;
5816 struct amdgpu_display_manager *dm = &adev->dm;
5817 struct dm_atomic_state *dm_state;
eb3dc897 5818 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 5819 uint32_t i, j;
5cc6dcbd 5820 struct drm_crtc *crtc;
0bc9706d 5821 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 5822 unsigned long flags;
5823 bool wait_for_vblank = true;
5824 struct drm_connector *connector;
c2cea706 5825 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 5826 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 5827 int crtc_disable_count = 0;
e7b07cee
HW		 5828
5829 drm_atomic_helper_update_legacy_modeset_state(dev, state);
5830
eb3dc897
NK		 5831 dm_state = dm_atomic_get_new_state(state);
5832 if (dm_state && dm_state->context) {
5833 dc_state = dm_state->context;
5834 } else {
5835 /* No state changes, retain current state. */
813d20dc 5836 dc_state_temp = dc_create_state(dm->dc);
eb3dc897
NK		 5837 ASSERT(dc_state_temp);
5838 dc_state = dc_state_temp;
5839 dc_resource_state_copy_construct_current(dm->dc, dc_state);
5840 }
e7b07cee
HW		 5841
5842 /* update changed items */
0bc9706d 5843 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 5844 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5845
54d76575
LSL		 5846 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5847 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 5848
f1ad2f5e 5849 DRM_DEBUG_DRIVER(
e7b07cee
HW		 5850 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5851 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5852 "connectors_changed:%d\n",
5853 acrtc->crtc_id,
0bc9706d
LSL		 5854 new_crtc_state->enable,
5855 new_crtc_state->active,
5856 new_crtc_state->planes_changed,
5857 new_crtc_state->mode_changed,
5858 new_crtc_state->active_changed,
5859 new_crtc_state->connectors_changed);
e7b07cee 5860
27b3f4fc
LSL		 5861 /* Copy all transient state flags into dc state */
5862 if (dm_new_crtc_state->stream) {
5863 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5864 dm_new_crtc_state->stream);
5865 }
5866
e7b07cee
HW		 5867 /* handles headless hotplug case, updating new_state and
5868 * aconnector as needed
5869 */
5870
54d76575 5871 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 5872
f1ad2f5e 5873 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 5874
54d76575 5875 if (!dm_new_crtc_state->stream) {
e7b07cee 5876 /*
b830ebc9
HW		 5877 * this could happen because of issues with
5878 * userspace notifications delivery.
5879 * In this case userspace tries to set mode on
1f6010a9
DF		 5880 * display which is disconnected in fact.
5881 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 5882 * We expect reset mode will come soon.
5883 *
5884 * This can also happen when unplug is done
5885 * during resume sequence ended
5886 *
5887 * In this case, we want to pretend we still
5888 * have a sink to keep the pipe running so that
5889 * hw state is consistent with the sw state
5890 */
f1ad2f5e 5891 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 5892 __func__, acrtc->base.base.id);
5893 continue;
5894 }
5895
54d76575
LSL		 5896 if (dm_old_crtc_state->stream)
5897 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 5898
97028037
LP		 5899 pm_runtime_get_noresume(dev->dev);
5900
e7b07cee 5901 acrtc->enabled = true;
0bc9706d
LSL		 5902 acrtc->hw_mode = new_crtc_state->mode;
5903 crtc->hwmode = new_crtc_state->mode;
5904 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 5905 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 5906
5907 /* i.e. reset mode */
54d76575
LSL		 5908 if (dm_old_crtc_state->stream)
5909 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 5910 }
5911 } /* for_each_crtc_in_state() */
5912
eb3dc897
NK		 5913 if (dc_state) {
5914 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 5915 mutex_lock(&dm->dc_lock);
eb3dc897 5916 WARN_ON(!dc_commit_state(dm->dc, dc_state));
674e78ac 5917 mutex_unlock(&dm->dc_lock);
fa2123db 5918 }
e7b07cee 5919
0bc9706d 5920 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5921 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5922
54d76575 5923 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5924
54d76575 5925 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 5926 const struct dc_stream_status *status =
54d76575 5927 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5928
eb3dc897 5929 if (!status)
09f609c3
LL		 5930 status = dc_stream_get_status_from_state(dc_state,
5931 dm_new_crtc_state->stream);
eb3dc897 5932
e7b07cee 5933 if (!status)
54d76575 5934 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 5935 else
5936 acrtc->otg_inst = status->primary_otg_inst;
5937 }
5938 }
5939
02d6a6fc 5940 /* Handle connector state changes */
c2cea706 5941 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5942 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5943 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5944 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
19afd799
NC		 5945 struct dc_surface_update dummy_updates[MAX_SURFACES];
5946 struct dc_stream_update stream_update;
b232d4ed 5947 struct dc_info_packet hdr_packet;
e7b07cee 5948 struct dc_stream_status *status = NULL;
b232d4ed 5949 bool abm_changed, hdr_changed, scaling_changed;
e7b07cee 5950
19afd799
NC		 5951 memset(&dummy_updates, 0, sizeof(dummy_updates));
5952 memset(&stream_update, 0, sizeof(stream_update));
5953
44d09c6a 5954 if (acrtc) {
0bc9706d 5955 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 5956 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5957 }
0bc9706d 5958
e7b07cee 5959 /* Skip any modesets/resets */
0bc9706d 5960 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 5961 continue;
5962
54d76575 5963 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 5964 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5965
b232d4ed
NK		 5966 scaling_changed = is_scaling_state_different(dm_new_con_state,
5967 dm_old_con_state);
5968
5969 abm_changed = dm_new_crtc_state->abm_level !=
5970 dm_old_crtc_state->abm_level;
5971
5972 hdr_changed =
5973 is_hdr_metadata_different(old_con_state, new_con_state);
5974
5975 if (!scaling_changed && !abm_changed && !hdr_changed)
c1ee92f9 5976 continue;
e7b07cee 5977
b232d4ed 5978 if (scaling_changed) {
02d6a6fc
DF		 5979 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5980 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 5981
02d6a6fc
DF		 5982 stream_update.src = dm_new_crtc_state->stream->src;
5983 stream_update.dst = dm_new_crtc_state->stream->dst;
5984 }
5985
b232d4ed 5986 if (abm_changed) {
02d6a6fc
DF		 5987 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
5988
5989 stream_update.abm_level = &dm_new_crtc_state->abm_level;
5990 }
70e8ffc5 5991
b232d4ed
NK		 5992 if (hdr_changed) {
5993 fill_hdr_info_packet(new_con_state, &hdr_packet);
5994 stream_update.hdr_static_metadata = &hdr_packet;
5995 }
5996
54d76575 5997 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5998 WARN_ON(!status);
3be5262e 5999 WARN_ON(!status->plane_count);
e7b07cee 6000
02d6a6fc
DF		 6001 /*
6002 * TODO: DC refuses to perform stream updates without a dc_surface_update.
6003 * Here we create an empty update on each plane.
6004 * To fix this, DC should permit updating only stream properties.
6005 */
6006 for (j = 0; j < status->plane_count; j++)
6007 dummy_updates[j].surface = status->plane_states[0];
6008
6009
6010 mutex_lock(&dm->dc_lock);
6011 dc_commit_updates_for_stream(dm->dc,
6012 dummy_updates,
6013 status->plane_count,
6014 dm_new_crtc_state->stream,
6015 &stream_update,
6016 dc_state);
6017 mutex_unlock(&dm->dc_lock);
e7b07cee
HW		 6018 }
6019
b5e83f6f 6020 /* Count number of newly disabled CRTCs for dropping PM refs later. */
e1fc2dca 6021 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
057be086 6022 new_crtc_state, i) {
fe2a1965
LP		 6023 if (old_crtc_state->active && !new_crtc_state->active)
6024 crtc_disable_count++;
6025
54d76575 6026 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca 6027 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
66b0c973 6028
057be086
NK		 6029 /* Update freesync active state. */
6030 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
6031
66b0c973
MK		 6032 /* Handle vrr on->off / off->on transitions */
6033 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
6034 dm_new_crtc_state);
e7b07cee
HW		 6035 }
6036
b5e83f6f
NK		 6037 /* Enable interrupts for CRTCs going through a modeset. */
6038 amdgpu_dm_enable_crtc_interrupts(dev, state, true);
e7b07cee 6039
420cd472
DF		 6040 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
6041 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
6042 wait_for_vblank = false;
6043
e7b07cee 6044 /* update planes when needed per crtc*/
5cc6dcbd 6045 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 6046 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 6047
54d76575 6048 if (dm_new_crtc_state->stream)
eb3dc897 6049 amdgpu_dm_commit_planes(state, dc_state, dev,
420cd472 6050 dm, crtc, wait_for_vblank);
e7b07cee
HW		 6051 }
6052
b5e83f6f
NK		 6053 /* Enable interrupts for CRTCs going from 0 to n active planes. */
6054 amdgpu_dm_enable_crtc_interrupts(dev, state, false);
e7b07cee
HW		 6055
6056 /*
6057 * send vblank event on all events not handled in flip and
6058 * mark consumed event for drm_atomic_helper_commit_hw_done
6059 */
6060 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 6061 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 6062
0bc9706d
LSL		 6063 if (new_crtc_state->event)
6064 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 6065
0bc9706d 6066 new_crtc_state->event = NULL;
e7b07cee
HW		 6067 }
6068 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6069
29c8f234
LL		 6070 /* Signal HW programming completion */
6071 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 6072
6073 if (wait_for_vblank)
320a1274 6074 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 6075
6076 drm_atomic_helper_cleanup_planes(dev, state);
97028037 6077
1f6010a9
DF		 6078 /*
6079 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 6080 * so we can put the GPU into runtime suspend if we're not driving any
6081 * displays anymore
6082 */
fe2a1965
LP		 6083 for (i = 0; i < crtc_disable_count; i++)
6084 pm_runtime_put_autosuspend(dev->dev);
97028037 6085 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 6086
6087 if (dc_state_temp)
6088 dc_release_state(dc_state_temp);
e7b07cee
HW		 6089}
6090
6091
6092static int dm_force_atomic_commit(struct drm_connector *connector)
6093{
6094 int ret = 0;
6095 struct drm_device *ddev = connector->dev;
6096 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
6097 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
6098 struct drm_plane *plane = disconnected_acrtc->base.primary;
6099 struct drm_connector_state *conn_state;
6100 struct drm_crtc_state *crtc_state;
6101 struct drm_plane_state *plane_state;
6102
6103 if (!state)
6104 return -ENOMEM;
6105
6106 state->acquire_ctx = ddev->mode_config.acquire_ctx;
6107
6108 /* Construct an atomic state to restore previous display setting */
6109
6110 /*
6111 * Attach connectors to drm_atomic_state
6112 */
6113 conn_state = drm_atomic_get_connector_state(state, connector);
6114
6115 ret = PTR_ERR_OR_ZERO(conn_state);
6116 if (ret)
6117 goto err;
6118
6119 /* Attach crtc to drm_atomic_state*/
6120 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
6121
6122 ret = PTR_ERR_OR_ZERO(crtc_state);
6123 if (ret)
6124 goto err;
6125
6126 /* force a restore */
6127 crtc_state->mode_changed = true;
6128
6129 /* Attach plane to drm_atomic_state */
6130 plane_state = drm_atomic_get_plane_state(state, plane);
6131
6132 ret = PTR_ERR_OR_ZERO(plane_state);
6133 if (ret)
6134 goto err;
6135
6136
6137 /* Call commit internally with the state we just constructed */
6138 ret = drm_atomic_commit(state);
6139 if (!ret)
6140 return 0;
6141
6142err:
6143 DRM_ERROR("Restoring old state failed with %i\n", ret);
6144 drm_atomic_state_put(state);
6145
6146 return ret;
6147}
6148
6149/*
1f6010a9
DF		 6150 * This function handles all cases when set mode does not come upon hotplug.
6151 * This includes when a display is unplugged then plugged back into the
6152 * same port and when running without usermode desktop manager supprot
e7b07cee 6153 */
3ee6b26b
AD		 6154void dm_restore_drm_connector_state(struct drm_device *dev,
6155 struct drm_connector *connector)
e7b07cee 6156{
c84dec2f 6157 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 6158 struct amdgpu_crtc *disconnected_acrtc;
6159 struct dm_crtc_state *acrtc_state;
6160
6161 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
6162 return;
6163
6164 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 6165 if (!disconnected_acrtc)
6166 return;
e7b07cee 6167
70e8ffc5
HW		 6168 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
6169 if (!acrtc_state->stream)
e7b07cee
HW		 6170 return;
6171
6172 /*
6173 * If the previous sink is not released and different from the current,
6174 * we deduce we are in a state where we can not rely on usermode call
6175 * to turn on the display, so we do it here
6176 */
6177 if (acrtc_state->stream->sink != aconnector->dc_sink)
6178 dm_force_atomic_commit(&aconnector->base);
6179}
6180
1f6010a9 6181/*
e7b07cee
HW		 6182 * Grabs all modesetting locks to serialize against any blocking commits,
6183 * Waits for completion of all non blocking commits.
6184 */
3ee6b26b
AD		 6185static int do_aquire_global_lock(struct drm_device *dev,
6186 struct drm_atomic_state *state)
e7b07cee
HW		 6187{
6188 struct drm_crtc *crtc;
6189 struct drm_crtc_commit *commit;
6190 long ret;
6191
1f6010a9
DF		 6192 /*
6193 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 6194 * ensure that when the framework release it the
6195 * extra locks we are locking here will get released to
6196 */
6197 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
6198 if (ret)
6199 return ret;
6200
6201 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6202 spin_lock(&crtc->commit_lock);
6203 commit = list_first_entry_or_null(&crtc->commit_list,
6204 struct drm_crtc_commit, commit_entry);
6205 if (commit)
6206 drm_crtc_commit_get(commit);
6207 spin_unlock(&crtc->commit_lock);
6208
6209 if (!commit)
6210 continue;
6211
1f6010a9
DF		 6212 /*
6213 * Make sure all pending HW programming completed and
e7b07cee
HW		 6214 * page flips done
6215 */
6216 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
6217
6218 if (ret > 0)
6219 ret = wait_for_completion_interruptible_timeout(
6220 &commit->flip_done, 10*HZ);
6221
6222 if (ret == 0)
6223 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 6224 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 6225
6226 drm_crtc_commit_put(commit);
6227 }
6228
6229 return ret < 0 ? ret : 0;
6230}
6231
bb47de73
NK		 6232static void get_freesync_config_for_crtc(
6233 struct dm_crtc_state *new_crtc_state,
6234 struct dm_connector_state *new_con_state)
98e6436d
AK		 6235{
6236 struct mod_freesync_config config = {0};
98e6436d
AK		 6237 struct amdgpu_dm_connector *aconnector =
6238 to_amdgpu_dm_connector(new_con_state->base.connector);
a057ec46 6239 struct drm_display_mode *mode = &new_crtc_state->base.mode;
0ab925d3 6240 int vrefresh = drm_mode_vrefresh(mode);
98e6436d 6241
a057ec46 6242 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
0ab925d3
NK		 6243 vrefresh >= aconnector->min_vfreq &&
6244 vrefresh <= aconnector->max_vfreq;
bb47de73 6245
a057ec46
IB		 6246 if (new_crtc_state->vrr_supported) {
6247 new_crtc_state->stream->ignore_msa_timing_param = true;
bb47de73 6248 config.state = new_crtc_state->base.vrr_enabled ?
98e6436d
AK		 6249 VRR_STATE_ACTIVE_VARIABLE :
6250 VRR_STATE_INACTIVE;
6251 config.min_refresh_in_uhz =
6252 aconnector->min_vfreq * 1000000;
6253 config.max_refresh_in_uhz =
6254 aconnector->max_vfreq * 1000000;
69ff8845 6255 config.vsif_supported = true;
180db303 6256 config.btr = true;
98e6436d
AK		 6257 }
6258
bb47de73
NK		 6259 new_crtc_state->freesync_config = config;
6260}
98e6436d 6261
bb47de73
NK		 6262static void reset_freesync_config_for_crtc(
6263 struct dm_crtc_state *new_crtc_state)
6264{
6265 new_crtc_state->vrr_supported = false;
98e6436d 6266
180db303
NK		 6267 memset(&new_crtc_state->vrr_params, 0,
6268 sizeof(new_crtc_state->vrr_params));
bb47de73
NK		 6269 memset(&new_crtc_state->vrr_infopacket, 0,
6270 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 6271}
6272
4b9674e5
LL		 6273static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
6274 struct drm_atomic_state *state,
6275 struct drm_crtc *crtc,
6276 struct drm_crtc_state *old_crtc_state,
6277 struct drm_crtc_state *new_crtc_state,
6278 bool enable,
6279 bool *lock_and_validation_needed)
e7b07cee 6280{
eb3dc897 6281 struct dm_atomic_state *dm_state = NULL;
54d76575 6282 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 6283 struct dc_stream_state *new_stream;
62f55537 6284 int ret = 0;
d4d4a645 6285
1f6010a9
DF		 6286 /*
6287 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
6288 * update changed items
6289 */
4b9674e5
LL		 6290 struct amdgpu_crtc *acrtc = NULL;
6291 struct amdgpu_dm_connector *aconnector = NULL;
6292 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
6293 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
e7b07cee 6294
4b9674e5 6295 new_stream = NULL;
9635b754 6296
4b9674e5
LL		 6297 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6298 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6299 acrtc = to_amdgpu_crtc(crtc);
4b9674e5 6300 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 6301
4b9674e5
LL		 6302 /* TODO This hack should go away */
6303 if (aconnector && enable) {
6304 /* Make sure fake sink is created in plug-in scenario */
6305 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
6306 &aconnector->base);
6307 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
6308 &aconnector->base);
19f89e23 6309
4b9674e5
LL		 6310 if (IS_ERR(drm_new_conn_state)) {
6311 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
6312 goto fail;
6313 }
19f89e23 6314
4b9674e5
LL		 6315 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
6316 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 6317
02d35a67
JFZ		 6318 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6319 goto skip_modeset;
6320
4b9674e5
LL		 6321 new_stream = create_stream_for_sink(aconnector,
6322 &new_crtc_state->mode,
6323 dm_new_conn_state,
6324 dm_old_crtc_state->stream);
19f89e23 6325
4b9674e5
LL		 6326 /*
6327 * we can have no stream on ACTION_SET if a display
6328 * was disconnected during S3, in this case it is not an
6329 * error, the OS will be updated after detection, and
6330 * will do the right thing on next atomic commit
6331 */
19f89e23 6332
4b9674e5
LL		 6333 if (!new_stream) {
6334 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6335 __func__, acrtc->base.base.id);
6336 ret = -ENOMEM;
6337 goto fail;
6338 }
e7b07cee 6339
4b9674e5 6340 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 6341
88694af9
NK		 6342 ret = fill_hdr_info_packet(drm_new_conn_state,
6343 &new_stream->hdr_static_metadata);
6344 if (ret)
6345 goto fail;
6346
7e930949
NK		 6347 /*
6348 * If we already removed the old stream from the context
6349 * (and set the new stream to NULL) then we can't reuse
6350 * the old stream even if the stream and scaling are unchanged.
6351 * We'll hit the BUG_ON and black screen.
6352 *
6353 * TODO: Refactor this function to allow this check to work
6354 * in all conditions.
6355 */
6356 if (dm_new_crtc_state->stream &&
6357 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4b9674e5
LL		 6358 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
6359 new_crtc_state->mode_changed = false;
6360 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
6361 new_crtc_state->mode_changed);
62f55537 6362 }
4b9674e5 6363 }
b830ebc9 6364
02d35a67 6365 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 6366 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6367 goto skip_modeset;
e7b07cee 6368
4b9674e5
LL		 6369 DRM_DEBUG_DRIVER(
6370 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6371 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6372 "connectors_changed:%d\n",
6373 acrtc->crtc_id,
6374 new_crtc_state->enable,
6375 new_crtc_state->active,
6376 new_crtc_state->planes_changed,
6377 new_crtc_state->mode_changed,
6378 new_crtc_state->active_changed,
6379 new_crtc_state->connectors_changed);
62f55537 6380
4b9674e5
LL		 6381 /* Remove stream for any changed/disabled CRTC */
6382 if (!enable) {
62f55537 6383
4b9674e5
LL		 6384 if (!dm_old_crtc_state->stream)
6385 goto skip_modeset;
eb3dc897 6386
4b9674e5
LL		 6387 ret = dm_atomic_get_state(state, &dm_state);
6388 if (ret)
6389 goto fail;
e7b07cee 6390
4b9674e5
LL		 6391 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
6392 crtc->base.id);
62f55537 6393
4b9674e5
LL		 6394 /* i.e. reset mode */
6395 if (dc_remove_stream_from_ctx(
6396 dm->dc,
6397 dm_state->context,
6398 dm_old_crtc_state->stream) != DC_OK) {
6399 ret = -EINVAL;
6400 goto fail;
6401 }
62f55537 6402
4b9674e5
LL		 6403 dc_stream_release(dm_old_crtc_state->stream);
6404 dm_new_crtc_state->stream = NULL;
bb47de73 6405
4b9674e5 6406 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 6407
4b9674e5 6408 *lock_and_validation_needed = true;
62f55537 6409
4b9674e5
LL		 6410 } else {/* Add stream for any updated/enabled CRTC */
6411 /*
6412 * Quick fix to prevent NULL pointer on new_stream when
6413 * added MST connectors not found in existing crtc_state in the chained mode
6414 * TODO: need to dig out the root cause of that
6415 */
6416 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
6417 goto skip_modeset;
62f55537 6418
4b9674e5
LL		 6419 if (modereset_required(new_crtc_state))
6420 goto skip_modeset;
62f55537 6421
4b9674e5
LL		 6422 if (modeset_required(new_crtc_state, new_stream,
6423 dm_old_crtc_state->stream)) {
62f55537 6424
4b9674e5 6425 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 6426
4b9674e5
LL		 6427 ret = dm_atomic_get_state(state, &dm_state);
6428 if (ret)
6429 goto fail;
27b3f4fc 6430
4b9674e5 6431 dm_new_crtc_state->stream = new_stream;
62f55537 6432
4b9674e5 6433 dc_stream_retain(new_stream);
1dc90497 6434
4b9674e5
LL		 6435 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
6436 crtc->base.id);
1dc90497 6437
4b9674e5
LL		 6438 if (dc_add_stream_to_ctx(
6439 dm->dc,
6440 dm_state->context,
6441 dm_new_crtc_state->stream) != DC_OK) {
6442 ret = -EINVAL;
6443 goto fail;
9b690ef3
BL		 6444 }
6445
4b9674e5
LL		 6446 *lock_and_validation_needed = true;
6447 }
6448 }
e277adc5 6449
4b9674e5
LL		 6450skip_modeset:
6451 /* Release extra reference */
6452 if (new_stream)
6453 dc_stream_release(new_stream);
e277adc5 6454
4b9674e5
LL		 6455 /*
6456 * We want to do dc stream updates that do not require a
6457 * full modeset below.
6458 */
6459 if (!(enable && aconnector && new_crtc_state->enable &&
6460 new_crtc_state->active))
6461 return 0;
6462 /*
6463 * Given above conditions, the dc state cannot be NULL because:
6464 * 1. We're in the process of enabling CRTCs (just been added
6465 * to the dc context, or already is on the context)
6466 * 2. Has a valid connector attached, and
6467 * 3. Is currently active and enabled.
6468 * => The dc stream state currently exists.
6469 */
6470 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 6471
4b9674e5
LL		 6472 /* Scaling or underscan settings */
6473 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
6474 update_stream_scaling_settings(
6475 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 6476
b05e2c5e
DF		 6477 /* ABM settings */
6478 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6479
4b9674e5
LL		 6480 /*
6481 * Color management settings. We also update color properties
6482 * when a modeset is needed, to ensure it gets reprogrammed.
6483 */
6484 if (dm_new_crtc_state->base.color_mgmt_changed ||
6485 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
6486 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
6487 if (ret)
6488 goto fail;
6489 amdgpu_dm_set_ctm(dm_new_crtc_state);
62f55537 6490 }
e7b07cee 6491
4b9674e5
LL		 6492 /* Update Freesync settings. */
6493 get_freesync_config_for_crtc(dm_new_crtc_state,
6494 dm_new_conn_state);
6495
62f55537 6496 return ret;
9635b754
DS		 6497
6498fail:
6499 if (new_stream)
6500 dc_stream_release(new_stream);
6501 return ret;
62f55537 6502}
9b690ef3 6503
f6ff2a08
NK		 6504static bool should_reset_plane(struct drm_atomic_state *state,
6505 struct drm_plane *plane,
6506 struct drm_plane_state *old_plane_state,
6507 struct drm_plane_state *new_plane_state)
6508{
6509 struct drm_plane *other;
6510 struct drm_plane_state *old_other_state, *new_other_state;
6511 struct drm_crtc_state *new_crtc_state;
6512 int i;
6513
6514 /*
6515 * TODO: Remove this hack once the checks below are sufficient
6516 * enough to determine when we need to reset all the planes on
6517 * the stream.
6518 */
6519 if (state->allow_modeset)
6520 return true;
6521
6522 /* Exit early if we know that we're adding or removing the plane. */
6523 if (old_plane_state->crtc != new_plane_state->crtc)
6524 return true;
6525
6526 /* old crtc == new_crtc == NULL, plane not in context. */
6527 if (!new_plane_state->crtc)
6528 return false;
6529
6530 new_crtc_state =
6531 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
6532
6533 if (!new_crtc_state)
6534 return true;
6535
7316c4ad
NK		 6536 /* CRTC Degamma changes currently require us to recreate planes. */
6537 if (new_crtc_state->color_mgmt_changed)
6538 return true;
6539
f6ff2a08
NK		 6540 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
6541 return true;
6542
6543 /*
6544 * If there are any new primary or overlay planes being added or
6545 * removed then the z-order can potentially change. To ensure
6546 * correct z-order and pipe acquisition the current DC architecture
6547 * requires us to remove and recreate all existing planes.
6548 *
6549 * TODO: Come up with a more elegant solution for this.
6550 */
6551 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
6552 if (other->type == DRM_PLANE_TYPE_CURSOR)
6553 continue;
6554
6555 if (old_other_state->crtc != new_plane_state->crtc &&
6556 new_other_state->crtc != new_plane_state->crtc)
6557 continue;
6558
6559 if (old_other_state->crtc != new_other_state->crtc)
6560 return true;
6561
6562 /* TODO: Remove this once we can handle fast format changes. */
6563 if (old_other_state->fb && new_other_state->fb &&
6564 old_other_state->fb->format != new_other_state->fb->format)
6565 return true;
6566 }
6567
6568 return false;
6569}
6570
9e869063
LL		 6571static int dm_update_plane_state(struct dc *dc,
6572 struct drm_atomic_state *state,
6573 struct drm_plane *plane,
6574 struct drm_plane_state *old_plane_state,
6575 struct drm_plane_state *new_plane_state,
6576 bool enable,
6577 bool *lock_and_validation_needed)
62f55537 6578{
eb3dc897
NK		 6579
6580 struct dm_atomic_state *dm_state = NULL;
62f55537 6581 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 6582 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 6583 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 6584 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
f6ff2a08 6585 bool needs_reset;
62f55537 6586 int ret = 0;
e7b07cee 6587
9b690ef3 6588
9e869063
LL		 6589 new_plane_crtc = new_plane_state->crtc;
6590 old_plane_crtc = old_plane_state->crtc;
6591 dm_new_plane_state = to_dm_plane_state(new_plane_state);
6592 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 6593
9e869063
LL		 6594 /*TODO Implement atomic check for cursor plane */
6595 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6596 return 0;
9b690ef3 6597
f6ff2a08
NK		 6598 needs_reset = should_reset_plane(state, plane, old_plane_state,
6599 new_plane_state);
6600
9e869063
LL		 6601 /* Remove any changed/removed planes */
6602 if (!enable) {
f6ff2a08 6603 if (!needs_reset)
9e869063 6604 return 0;
a7b06724 6605
9e869063
LL		 6606 if (!old_plane_crtc)
6607 return 0;
62f55537 6608
9e869063
LL		 6609 old_crtc_state = drm_atomic_get_old_crtc_state(
6610 state, old_plane_crtc);
6611 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 6612
9e869063
LL		 6613 if (!dm_old_crtc_state->stream)
6614 return 0;
62f55537 6615
9e869063
LL		 6616 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
6617 plane->base.id, old_plane_crtc->base.id);
9b690ef3 6618
9e869063
LL		 6619 ret = dm_atomic_get_state(state, &dm_state);
6620 if (ret)
6621 return ret;
eb3dc897 6622
9e869063
LL		 6623 if (!dc_remove_plane_from_context(
6624 dc,
6625 dm_old_crtc_state->stream,
6626 dm_old_plane_state->dc_state,
6627 dm_state->context)) {
62f55537 6628
9e869063
LL		 6629 ret = EINVAL;
6630 return ret;
6631 }
e7b07cee 6632
9b690ef3 6633
9e869063
LL		 6634 dc_plane_state_release(dm_old_plane_state->dc_state);
6635 dm_new_plane_state->dc_state = NULL;
1dc90497 6636
9e869063 6637 *lock_and_validation_needed = true;
1dc90497 6638
9e869063
LL		 6639 } else { /* Add new planes */
6640 struct dc_plane_state *dc_new_plane_state;
1dc90497 6641
9e869063
LL		 6642 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
6643 return 0;
e7b07cee 6644
9e869063
LL		 6645 if (!new_plane_crtc)
6646 return 0;
e7b07cee 6647
9e869063
LL		 6648 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
6649 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 6650
9e869063
LL		 6651 if (!dm_new_crtc_state->stream)
6652 return 0;
62f55537 6653
f6ff2a08 6654 if (!needs_reset)
9e869063 6655 return 0;
62f55537 6656
9e869063 6657 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 6658
9e869063
LL		 6659 dc_new_plane_state = dc_create_plane_state(dc);
6660 if (!dc_new_plane_state)
6661 return -ENOMEM;
62f55537 6662
9e869063
LL		 6663 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
6664 plane->base.id, new_plane_crtc->base.id);
8c45c5db 6665
695af5f9 6666 ret = fill_dc_plane_attributes(
9e869063
LL		 6667 new_plane_crtc->dev->dev_private,
6668 dc_new_plane_state,
6669 new_plane_state,
6670 new_crtc_state);
6671 if (ret) {
6672 dc_plane_state_release(dc_new_plane_state);
6673 return ret;
6674 }
62f55537 6675
9e869063
LL		 6676 ret = dm_atomic_get_state(state, &dm_state);
6677 if (ret) {
6678 dc_plane_state_release(dc_new_plane_state);
6679 return ret;
6680 }
eb3dc897 6681
9e869063
LL		 6682 /*
6683 * Any atomic check errors that occur after this will
6684 * not need a release. The plane state will be attached
6685 * to the stream, and therefore part of the atomic
6686 * state. It'll be released when the atomic state is
6687 * cleaned.
6688 */
6689 if (!dc_add_plane_to_context(
6690 dc,
6691 dm_new_crtc_state->stream,
6692 dc_new_plane_state,
6693 dm_state->context)) {
62f55537 6694
9e869063
LL		 6695 dc_plane_state_release(dc_new_plane_state);
6696 return -EINVAL;
6697 }
8c45c5db 6698
9e869063 6699 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 6700
9e869063
LL		 6701 /* Tell DC to do a full surface update every time there
6702 * is a plane change. Inefficient, but works for now.
6703 */
6704 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
6705
6706 *lock_and_validation_needed = true;
62f55537 6707 }
e7b07cee
HW		 6708
6709
62f55537
AG		 6710 return ret;
6711}
a87fa993 6712
eb3dc897 6713static int
f843b308 6714dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
eb3dc897
NK		 6715 struct drm_atomic_state *state,
6716 enum surface_update_type *out_type)
6717{
f843b308 6718 struct dc *dc = dm->dc;
eb3dc897
NK		 6719 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
6720 int i, j, num_plane, ret = 0;
a87fa993
BL		 6721 struct drm_plane_state *old_plane_state, *new_plane_state;
6722 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
6723 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
6724 struct drm_plane *plane;
6725
6726 struct drm_crtc *crtc;
6727 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
6728 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
6729 struct dc_stream_status *status = NULL;
6730
fe96b99d 6731 struct dc_surface_update *updates;
a87fa993
BL		 6732 enum surface_update_type update_type = UPDATE_TYPE_FAST;
6733
fe96b99d 6734 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
fe96b99d 6735
f843b308
NK		 6736 if (!updates) {
6737 DRM_ERROR("Failed to allocate plane updates\n");
4f712911
BL		 6738 /* Set type to FULL to avoid crashing in DC*/
6739 update_type = UPDATE_TYPE_FULL;
eb3dc897 6740 goto cleanup;
4f712911 6741 }
a87fa993
BL		 6742
6743 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
004b3938 6744 struct dc_scaling_info scaling_info;
2aa632c5
NK		 6745 struct dc_stream_update stream_update;
6746
6747 memset(&stream_update, 0, sizeof(stream_update));
c448a53a 6748
a87fa993
BL		 6749 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6750 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
6751 num_plane = 0;
6752
6836d239
NK		 6753 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
6754 update_type = UPDATE_TYPE_FULL;
6755 goto cleanup;
6756 }
a87fa993 6757
6836d239 6758 if (!new_dm_crtc_state->stream)
c744e974 6759 continue;
eb3dc897 6760
c744e974
NK		 6761 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
6762 new_plane_crtc = new_plane_state->crtc;
6763 old_plane_crtc = old_plane_state->crtc;
6764 new_dm_plane_state = to_dm_plane_state(new_plane_state);
6765 old_dm_plane_state = to_dm_plane_state(old_plane_state);
eb3dc897 6766
c744e974
NK		 6767 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6768 continue;
eb3dc897 6769
6836d239
NK		 6770 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
6771 update_type = UPDATE_TYPE_FULL;
6772 goto cleanup;
6773 }
6774
c744e974
NK		 6775 if (crtc != new_plane_crtc)
6776 continue;
6777
f843b308 6778 updates[num_plane].surface = new_dm_plane_state->dc_state;
c744e974
NK		 6779
6780 if (new_crtc_state->mode_changed) {
c744e974
NK		 6781 stream_update.dst = new_dm_crtc_state->stream->dst;
6782 stream_update.src = new_dm_crtc_state->stream->src;
6783 }
6784
6785 if (new_crtc_state->color_mgmt_changed) {
6786 updates[num_plane].gamma =
6787 new_dm_plane_state->dc_state->gamma_correction;
6788 updates[num_plane].in_transfer_func =
6789 new_dm_plane_state->dc_state->in_transfer_func;
6790 stream_update.gamut_remap =
6791 &new_dm_crtc_state->stream->gamut_remap_matrix;
6792 stream_update.out_transfer_func =
6793 new_dm_crtc_state->stream->out_transfer_func;
a87fa993
BL		 6794 }
6795
004b3938
NK		 6796 ret = fill_dc_scaling_info(new_plane_state,
6797 &scaling_info);
6798 if (ret)
6799 goto cleanup;
6800
6801 updates[num_plane].scaling_info = &scaling_info;
6802
c744e974
NK		 6803 num_plane++;
6804 }
6805
6806 if (num_plane == 0)
6807 continue;
6808
6809 ret = dm_atomic_get_state(state, &dm_state);
6810 if (ret)
6811 goto cleanup;
6812
6813 old_dm_state = dm_atomic_get_old_state(state);
6814 if (!old_dm_state) {
6815 ret = -EINVAL;
6816 goto cleanup;
6817 }
6818
6819 status = dc_stream_get_status_from_state(old_dm_state->context,
6820 new_dm_crtc_state->stream);
6821
f843b308
NK		 6822 /*
6823 * TODO: DC modifies the surface during this call so we need
6824 * to lock here - find a way to do this without locking.
6825 */
6826 mutex_lock(&dm->dc_lock);
c744e974
NK		 6827 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
6828 &stream_update, status);
f843b308 6829 mutex_unlock(&dm->dc_lock);
c744e974
NK		 6830
6831 if (update_type > UPDATE_TYPE_MED) {
a87fa993 6832 update_type = UPDATE_TYPE_FULL;
eb3dc897 6833 goto cleanup;
a87fa993
BL		 6834 }
6835 }
6836
eb3dc897 6837cleanup:
a87fa993 6838 kfree(updates);
a87fa993 6839
eb3dc897
NK		 6840 *out_type = update_type;
6841 return ret;
a87fa993 6842}
62f55537 6843
b8592b48
LL		 6844/**
6845 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
6846 * @dev: The DRM device
6847 * @state: The atomic state to commit
6848 *
6849 * Validate that the given atomic state is programmable by DC into hardware.
6850 * This involves constructing a &struct dc_state reflecting the new hardware
6851 * state we wish to commit, then querying DC to see if it is programmable. It's
6852 * important not to modify the existing DC state. Otherwise, atomic_check
6853 * may unexpectedly commit hardware changes.
6854 *
6855 * When validating the DC state, it's important that the right locks are
6856 * acquired. For full updates case which removes/adds/updates streams on one
6857 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
6858 * that any such full update commit will wait for completion of any outstanding
6859 * flip using DRMs synchronization events. See
6860 * dm_determine_update_type_for_commit()
6861 *
6862 * Note that DM adds the affected connectors for all CRTCs in state, when that
6863 * might not seem necessary. This is because DC stream creation requires the
6864 * DC sink, which is tied to the DRM connector state. Cleaning this up should
6865 * be possible but non-trivial - a possible TODO item.
6866 *
6867 * Return: -Error code if validation failed.
6868 */
7578ecda
AD		 6869static int amdgpu_dm_atomic_check(struct drm_device *dev,
6870 struct drm_atomic_state *state)
62f55537 6871{
62f55537 6872 struct amdgpu_device *adev = dev->dev_private;
eb3dc897 6873 struct dm_atomic_state *dm_state = NULL;
62f55537 6874 struct dc *dc = adev->dm.dc;
62f55537 6875 struct drm_connector *connector;
c2cea706 6876 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 6877 struct drm_crtc *crtc;
fc9e9920 6878 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 6879 struct drm_plane *plane;
6880 struct drm_plane_state *old_plane_state, *new_plane_state;
a87fa993
BL		 6881 enum surface_update_type update_type = UPDATE_TYPE_FAST;
6882 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
6883
1e88ad0a 6884 int ret, i;
e7b07cee 6885
62f55537
AG		 6886 /*
6887 * This bool will be set for true for any modeset/reset
6888 * or plane update which implies non fast surface update.
6889 */
6890 bool lock_and_validation_needed = false;
6891
6892 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 6893 if (ret)
6894 goto fail;
62f55537 6895
1e88ad0a
S		 6896 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6897 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 6898 !new_crtc_state->color_mgmt_changed &&
a93587b3 6899 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
1e88ad0a 6900 continue;
7bef1af3 6901
1e88ad0a
S		 6902 if (!new_crtc_state->enable)
6903 continue;
fc9e9920 6904
1e88ad0a
S		 6905 ret = drm_atomic_add_affected_connectors(state, crtc);
6906 if (ret)
6907 return ret;
fc9e9920 6908
1e88ad0a
S		 6909 ret = drm_atomic_add_affected_planes(state, crtc);
6910 if (ret)
6911 goto fail;
e7b07cee
HW		 6912 }
6913
2d9e6431
NK		 6914 /*
6915 * Add all primary and overlay planes on the CRTC to the state
6916 * whenever a plane is enabled to maintain correct z-ordering
6917 * and to enable fast surface updates.
6918 */
6919 drm_for_each_crtc(crtc, dev) {
6920 bool modified = false;
6921
6922 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
6923 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6924 continue;
6925
6926 if (new_plane_state->crtc == crtc ||
6927 old_plane_state->crtc == crtc) {
6928 modified = true;
6929 break;
6930 }
6931 }
6932
6933 if (!modified)
6934 continue;
6935
6936 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
6937 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6938 continue;
6939
6940 new_plane_state =
6941 drm_atomic_get_plane_state(state, plane);
6942
6943 if (IS_ERR(new_plane_state)) {
6944 ret = PTR_ERR(new_plane_state);
6945 goto fail;
6946 }
6947 }
6948 }
6949
62f55537 6950 /* Remove exiting planes if they are modified */
9e869063
LL		 6951 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6952 ret = dm_update_plane_state(dc, state, plane,
6953 old_plane_state,
6954 new_plane_state,
6955 false,
6956 &lock_and_validation_needed);
6957 if (ret)
6958 goto fail;
62f55537
AG		 6959 }
6960
6961 /* Disable all crtcs which require disable */
4b9674e5
LL		 6962 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6963 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6964 old_crtc_state,
6965 new_crtc_state,
6966 false,
6967 &lock_and_validation_needed);
6968 if (ret)
6969 goto fail;
62f55537
AG		 6970 }
6971
6972 /* Enable all crtcs which require enable */
4b9674e5
LL		 6973 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6974 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6975 old_crtc_state,
6976 new_crtc_state,
6977 true,
6978 &lock_and_validation_needed);
6979 if (ret)
6980 goto fail;
62f55537
AG		 6981 }
6982
6983 /* Add new/modified planes */
9e869063
LL		 6984 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6985 ret = dm_update_plane_state(dc, state, plane,
6986 old_plane_state,
6987 new_plane_state,
6988 true,
6989 &lock_and_validation_needed);
6990 if (ret)
6991 goto fail;
62f55537
AG		 6992 }
6993
b349f76e
ES		 6994 /* Run this here since we want to validate the streams we created */
6995 ret = drm_atomic_helper_check_planes(dev, state);
6996 if (ret)
6997 goto fail;
62f55537 6998
ebdd27e1 6999 /* Check scaling and underscan changes*/
1f6010a9 7000 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 7001 * new stream into context w\o causing full reset. Need to
7002 * decide how to handle.
7003 */
c2cea706 7004 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 7005 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
7006 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
7007 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 7008
7009 /* Skip any modesets/resets */
0bc9706d
LSL		 7010 if (!acrtc || drm_atomic_crtc_needs_modeset(
7011 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 7012 continue;
7013
b830ebc9 7014 /* Skip any thing not scale or underscan changes */
54d76575 7015 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 7016 continue;
7017
a87fa993 7018 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 7019 lock_and_validation_needed = true;
7020 }
7021
f843b308 7022 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
eb3dc897
NK		 7023 if (ret)
7024 goto fail;
a87fa993
BL		 7025
7026 if (overall_update_type < update_type)
7027 overall_update_type = update_type;
7028
7029 /*
7030 * lock_and_validation_needed was an old way to determine if we need to set
7031 * the global lock. Leaving it in to check if we broke any corner cases
7032 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
7033 * lock_and_validation_needed false = UPDATE_TYPE_FAST
7034 */
7035 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
7036 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
e7b07cee 7037
a87fa993 7038 if (overall_update_type > UPDATE_TYPE_FAST) {
eb3dc897
NK		 7039 ret = dm_atomic_get_state(state, &dm_state);
7040 if (ret)
7041 goto fail;
e7b07cee
HW		 7042
7043 ret = do_aquire_global_lock(dev, state);
7044 if (ret)
7045 goto fail;
1dc90497 7046
afcd526b 7047 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
e7b07cee
HW		 7048 ret = -EINVAL;
7049 goto fail;
7050 }
674e78ac
NK		 7051 } else if (state->legacy_cursor_update) {
7052 /*
7053 * This is a fast cursor update coming from the plane update
7054 * helper, check if it can be done asynchronously for better
7055 * performance.
7056 */
7057 state->async_update = !drm_atomic_helper_async_check(dev, state);
e7b07cee
HW		 7058 }
7059
7060 /* Must be success */
7061 WARN_ON(ret);
7062 return ret;
7063
7064fail:
7065 if (ret == -EDEADLK)
01e28f9c 7066 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 7067 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 7068 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 7069 else
01e28f9c 7070 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 7071
7072 return ret;
7073}
7074
3ee6b26b
AD		 7075static bool is_dp_capable_without_timing_msa(struct dc *dc,
7076 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 7077{
7078 uint8_t dpcd_data;
7079 bool capable = false;
7080
c84dec2f 7081 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 7082 dm_helpers_dp_read_dpcd(
7083 NULL,
c84dec2f 7084 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 7085 DP_DOWN_STREAM_PORT_COUNT,
7086 &dpcd_data,
7087 sizeof(dpcd_data))) {
7088 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
7089 }
7090
7091 return capable;
7092}
98e6436d
AK		 7093void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
7094 struct edid *edid)
e7b07cee
HW		 7095{
7096 int i;
e7b07cee
HW		 7097 bool edid_check_required;
7098 struct detailed_timing *timing;
7099 struct detailed_non_pixel *data;
7100 struct detailed_data_monitor_range *range;
c84dec2f
HW		 7101 struct amdgpu_dm_connector *amdgpu_dm_connector =
7102 to_amdgpu_dm_connector(connector);
bb47de73 7103 struct dm_connector_state *dm_con_state = NULL;
e7b07cee
HW		 7104
7105 struct drm_device *dev = connector->dev;
7106 struct amdgpu_device *adev = dev->dev_private;
bb47de73 7107 bool freesync_capable = false;
b830ebc9 7108
8218d7f1
HW		 7109 if (!connector->state) {
7110 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 7111 goto update;
8218d7f1
HW		 7112 }
7113
98e6436d
AK		 7114 if (!edid) {
7115 dm_con_state = to_dm_connector_state(connector->state);
7116
7117 amdgpu_dm_connector->min_vfreq = 0;
7118 amdgpu_dm_connector->max_vfreq = 0;
7119 amdgpu_dm_connector->pixel_clock_mhz = 0;
7120
bb47de73 7121 goto update;
98e6436d
AK		 7122 }
7123
8218d7f1
HW		 7124 dm_con_state = to_dm_connector_state(connector->state);
7125
e7b07cee 7126 edid_check_required = false;
c84dec2f 7127 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee 7128 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
bb47de73 7129 goto update;
e7b07cee
HW		 7130 }
7131 if (!adev->dm.freesync_module)
bb47de73 7132 goto update;
e7b07cee
HW		 7133 /*
7134 * if edid non zero restrict freesync only for dp and edp
7135 */
7136 if (edid) {
c84dec2f
HW		 7137 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
7138 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 7139 edid_check_required = is_dp_capable_without_timing_msa(
7140 adev->dm.dc,
c84dec2f 7141 amdgpu_dm_connector);
e7b07cee
HW		 7142 }
7143 }
e7b07cee
HW		 7144 if (edid_check_required == true && (edid->version > 1 ||
7145 (edid->version == 1 && edid->revision > 1))) {
7146 for (i = 0; i < 4; i++) {
7147
7148 timing = &edid->detailed_timings[i];
7149 data = &timing->data.other_data;
7150 range = &data->data.range;
7151 /*
7152 * Check if monitor has continuous frequency mode
7153 */
7154 if (data->type != EDID_DETAIL_MONITOR_RANGE)
7155 continue;
7156 /*
7157 * Check for flag range limits only. If flag == 1 then
7158 * no additional timing information provided.
7159 * Default GTF, GTF Secondary curve and CVT are not
7160 * supported
7161 */
7162 if (range->flags != 1)
7163 continue;
7164
c84dec2f
HW		 7165 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
7166 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
7167 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 7168 range->pixel_clock_mhz * 10;
7169 break;
7170 }
7171
c84dec2f 7172 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 7173 amdgpu_dm_connector->min_vfreq > 10) {
7174
bb47de73 7175 freesync_capable = true;
e7b07cee
HW		 7176 }
7177 }
bb47de73
NK		 7178
7179update:
7180 if (dm_con_state)
7181 dm_con_state->freesync_capable = freesync_capable;
7182
7183 if (connector->vrr_capable_property)
7184 drm_connector_set_vrr_capable_property(connector,
7185 freesync_capable);
e7b07cee
HW		 7186}
7187
Linux 6.x block layer and io_uring tree(s)