Commit | Line | Data |
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4562236b HW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
0cf5eb76 DF |
26 | /* The caprices of the preprocessor require that this be declared right here */ |
27 | #define CREATE_TRACE_POINTS | |
28 | ||
4562236b HW |
29 | #include "dm_services_types.h" |
30 | #include "dc.h" | |
f6e03f80 | 31 | #include "link_enc_cfg.h" |
1dc90497 | 32 | #include "dc/inc/core_types.h" |
a7669aff | 33 | #include "dal_asic_id.h" |
cdca3f21 | 34 | #include "dmub/dmub_srv.h" |
743b9786 NK |
35 | #include "dc/inc/hw/dmcu.h" |
36 | #include "dc/inc/hw/abm.h" | |
9a71c7d3 | 37 | #include "dc/dc_dmub_srv.h" |
f9b4f20c | 38 | #include "dc/dc_edid_parser.h" |
81927e28 | 39 | #include "dc/dc_stat.h" |
9d83722d | 40 | #include "amdgpu_dm_trace.h" |
028c4ccf | 41 | #include "dpcd_defs.h" |
bc33f5e5 | 42 | #include "link/protocols/link_dpcd.h" |
028c4ccf | 43 | #include "link_service_types.h" |
1e5d4d8e RL |
44 | #include "link/protocols/link_dp_capability.h" |
45 | #include "link/protocols/link_ddc.h" | |
4562236b HW |
46 | |
47 | #include "vid.h" | |
48 | #include "amdgpu.h" | |
a49dcb88 | 49 | #include "amdgpu_display.h" |
a94d5569 | 50 | #include "amdgpu_ucode.h" |
4562236b HW |
51 | #include "atom.h" |
52 | #include "amdgpu_dm.h" | |
5d945cbc | 53 | #include "amdgpu_dm_plane.h" |
473683a0 | 54 | #include "amdgpu_dm_crtc.h" |
52704fca | 55 | #include "amdgpu_dm_hdcp.h" |
6a99099f | 56 | #include <drm/display/drm_hdcp_helper.h> |
e7b07cee | 57 | #include "amdgpu_pm.h" |
1f579254 | 58 | #include "amdgpu_atombios.h" |
4562236b HW |
59 | |
60 | #include "amd_shared.h" | |
61 | #include "amdgpu_dm_irq.h" | |
62 | #include "dm_helpers.h" | |
e7b07cee | 63 | #include "amdgpu_dm_mst_types.h" |
dc38fd9d DF |
64 | #if defined(CONFIG_DEBUG_FS) |
65 | #include "amdgpu_dm_debugfs.h" | |
66 | #endif | |
f4594cd1 | 67 | #include "amdgpu_dm_psr.h" |
3cce0bfc | 68 | #include "amdgpu_dm_replay.h" |
4562236b HW |
69 | |
70 | #include "ivsrcid/ivsrcid_vislands30.h" | |
71 | ||
a6276e92 | 72 | #include <linux/backlight.h> |
4562236b HW |
73 | #include <linux/module.h> |
74 | #include <linux/moduleparam.h> | |
e7b07cee | 75 | #include <linux/types.h> |
97028037 | 76 | #include <linux/pm_runtime.h> |
09d21852 | 77 | #include <linux/pci.h> |
a94d5569 | 78 | #include <linux/firmware.h> |
6ce8f316 | 79 | #include <linux/component.h> |
57b9f338 | 80 | #include <linux/dmi.h> |
4562236b | 81 | |
da68386d | 82 | #include <drm/display/drm_dp_mst_helper.h> |
4fc8cb47 | 83 | #include <drm/display/drm_hdmi_helper.h> |
4562236b | 84 | #include <drm/drm_atomic.h> |
674e78ac | 85 | #include <drm/drm_atomic_uapi.h> |
4562236b | 86 | #include <drm/drm_atomic_helper.h> |
90bb087f | 87 | #include <drm/drm_blend.h> |
09d21852 | 88 | #include <drm/drm_fourcc.h> |
e7b07cee | 89 | #include <drm/drm_edid.h> |
09d21852 | 90 | #include <drm/drm_vblank.h> |
6ce8f316 | 91 | #include <drm/drm_audio_component.h> |
047de3f1 | 92 | #include <drm/drm_gem_atomic_helper.h> |
30c63715 | 93 | #include <drm/drm_plane_helper.h> |
4562236b | 94 | |
da11ef83 HG |
95 | #include <acpi/video.h> |
96 | ||
5527cd06 | 97 | #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" |
ff5ef992 | 98 | |
ad941f7a FX |
99 | #include "dcn/dcn_1_0_offset.h" |
100 | #include "dcn/dcn_1_0_sh_mask.h" | |
407e7517 | 101 | #include "soc15_hw_ip.h" |
543036a2 | 102 | #include "soc15_common.h" |
407e7517 | 103 | #include "vega10_ip_offset.h" |
ff5ef992 | 104 | |
543036a2 AP |
105 | #include "gc/gc_11_0_0_offset.h" |
106 | #include "gc/gc_11_0_0_sh_mask.h" | |
107 | ||
e7b07cee | 108 | #include "modules/inc/mod_freesync.h" |
bbf854dc | 109 | #include "modules/power/power_helpers.h" |
e7b07cee | 110 | |
743b9786 NK |
111 | #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" |
112 | MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); | |
79037324 BL |
113 | #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" |
114 | MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); | |
5ce868fc BL |
115 | #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" |
116 | MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); | |
71c0fd92 RL |
117 | #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" |
118 | MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); | |
469989ca RL |
119 | #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" |
120 | MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); | |
2a411205 BL |
121 | #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" |
122 | MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); | |
656fe9b6 AP |
123 | #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" |
124 | MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); | |
1ebcaebd NK |
125 | #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" |
126 | MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); | |
e850f6b1 RL |
127 | #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" |
128 | MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); | |
b5b8ed44 QZ |
129 | #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" |
130 | MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); | |
de7cc1b4 PL |
131 | #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" |
132 | MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); | |
2200eb9e | 133 | |
577359ca AP |
134 | #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" |
135 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); | |
136 | #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" | |
137 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); | |
138 | ||
a94d5569 DF |
139 | #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" |
140 | MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); | |
e7b07cee | 141 | |
5ea23931 RL |
142 | #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" |
143 | MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); | |
144 | ||
8c7aea40 NK |
145 | /* Number of bytes in PSP header for firmware. */ |
146 | #define PSP_HEADER_BYTES 0x100 | |
147 | ||
148 | /* Number of bytes in PSP footer for firmware. */ | |
149 | #define PSP_FOOTER_BYTES 0x100 | |
150 | ||
b8592b48 LL |
151 | /** |
152 | * DOC: overview | |
153 | * | |
154 | * The AMDgpu display manager, **amdgpu_dm** (or even simpler, | |
ec5c0ffa | 155 | * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM |
b8592b48 LL |
156 | * requests into DC requests, and DC responses into DRM responses. |
157 | * | |
158 | * The root control structure is &struct amdgpu_display_manager. | |
159 | */ | |
160 | ||
7578ecda AD |
161 | /* basic init/fini API */ |
162 | static int amdgpu_dm_init(struct amdgpu_device *adev); | |
163 | static void amdgpu_dm_fini(struct amdgpu_device *adev); | |
fe8858bb | 164 | static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); |
7578ecda | 165 | |
0f877894 OV |
166 | static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) |
167 | { | |
168 | switch (link->dpcd_caps.dongle_type) { | |
169 | case DISPLAY_DONGLE_NONE: | |
170 | return DRM_MODE_SUBCONNECTOR_Native; | |
171 | case DISPLAY_DONGLE_DP_VGA_CONVERTER: | |
172 | return DRM_MODE_SUBCONNECTOR_VGA; | |
173 | case DISPLAY_DONGLE_DP_DVI_CONVERTER: | |
174 | case DISPLAY_DONGLE_DP_DVI_DONGLE: | |
175 | return DRM_MODE_SUBCONNECTOR_DVID; | |
176 | case DISPLAY_DONGLE_DP_HDMI_CONVERTER: | |
177 | case DISPLAY_DONGLE_DP_HDMI_DONGLE: | |
178 | return DRM_MODE_SUBCONNECTOR_HDMIA; | |
179 | case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: | |
180 | default: | |
181 | return DRM_MODE_SUBCONNECTOR_Unknown; | |
182 | } | |
183 | } | |
184 | ||
185 | static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) | |
186 | { | |
187 | struct dc_link *link = aconnector->dc_link; | |
188 | struct drm_connector *connector = &aconnector->base; | |
189 | enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; | |
190 | ||
191 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
192 | return; | |
193 | ||
194 | if (aconnector->dc_sink) | |
195 | subconnector = get_subconnector_type(link); | |
196 | ||
197 | drm_object_property_set_value(&connector->base, | |
198 | connector->dev->mode_config.dp_subconnector_property, | |
199 | subconnector); | |
200 | } | |
201 | ||
1f6010a9 DF |
202 | /* |
203 | * initializes drm_device display related structures, based on the information | |
7578ecda AD |
204 | * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, |
205 | * drm_encoder, drm_mode_config | |
206 | * | |
207 | * Returns 0 on success | |
208 | */ | |
209 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); | |
210 | /* removes and deallocates the drm structures, created by the above function */ | |
211 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); | |
212 | ||
7578ecda AD |
213 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
214 | struct amdgpu_dm_connector *amdgpu_dm_connector, | |
ae67558b | 215 | u32 link_index, |
7578ecda AD |
216 | struct amdgpu_encoder *amdgpu_encoder); |
217 | static int amdgpu_dm_encoder_init(struct drm_device *dev, | |
218 | struct amdgpu_encoder *aencoder, | |
219 | uint32_t link_index); | |
220 | ||
221 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); | |
222 | ||
7578ecda AD |
223 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); |
224 | ||
225 | static int amdgpu_dm_atomic_check(struct drm_device *dev, | |
226 | struct drm_atomic_state *state); | |
227 | ||
e27c41d5 | 228 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); |
c40a09e5 | 229 | static void handle_hpd_rx_irq(void *param); |
e27c41d5 | 230 | |
a85ba005 NC |
231 | static bool |
232 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, | |
233 | struct drm_crtc_state *new_crtc_state); | |
4562236b HW |
234 | /* |
235 | * dm_vblank_get_counter | |
236 | * | |
237 | * @brief | |
238 | * Get counter for number of vertical blanks | |
239 | * | |
240 | * @param | |
241 | * struct amdgpu_device *adev - [in] desired amdgpu device | |
242 | * int disp_idx - [in] which CRTC to get the counter from | |
243 | * | |
244 | * @return | |
245 | * Counter for vertical blanks | |
246 | */ | |
247 | static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) | |
248 | { | |
53e1db06 SS |
249 | struct amdgpu_crtc *acrtc = NULL; |
250 | ||
4562236b HW |
251 | if (crtc >= adev->mode_info.num_crtc) |
252 | return 0; | |
4562236b | 253 | |
53e1db06 | 254 | acrtc = adev->mode_info.crtcs[crtc]; |
4562236b | 255 | |
53e1db06 SS |
256 | if (!acrtc->dm_irq_params.stream) { |
257 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", | |
258 | crtc); | |
259 | return 0; | |
4562236b | 260 | } |
53e1db06 SS |
261 | |
262 | return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); | |
4562236b HW |
263 | } |
264 | ||
265 | static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, | |
3ee6b26b | 266 | u32 *vbl, u32 *position) |
4562236b | 267 | { |
ae67558b | 268 | u32 v_blank_start, v_blank_end, h_position, v_position; |
0c2d77be | 269 | struct amdgpu_crtc *acrtc = NULL; |
81c50963 | 270 | |
4562236b HW |
271 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
272 | return -EINVAL; | |
4562236b | 273 | |
0c2d77be | 274 | acrtc = adev->mode_info.crtcs[crtc]; |
4562236b | 275 | |
0c2d77be SS |
276 | if (!acrtc->dm_irq_params.stream) { |
277 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", | |
278 | crtc); | |
279 | return 0; | |
4562236b HW |
280 | } |
281 | ||
0c2d77be SS |
282 | /* |
283 | * TODO rework base driver to use values directly. | |
284 | * for now parse it back into reg-format | |
285 | */ | |
286 | dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, | |
287 | &v_blank_start, | |
288 | &v_blank_end, | |
289 | &h_position, | |
290 | &v_position); | |
291 | ||
292 | *position = v_position | (h_position << 16); | |
293 | *vbl = v_blank_start | (v_blank_end << 16); | |
294 | ||
4562236b HW |
295 | return 0; |
296 | } | |
297 | ||
298 | static bool dm_is_idle(void *handle) | |
299 | { | |
300 | /* XXX todo */ | |
301 | return true; | |
302 | } | |
303 | ||
304 | static int dm_wait_for_idle(void *handle) | |
305 | { | |
306 | /* XXX todo */ | |
307 | return 0; | |
308 | } | |
309 | ||
310 | static bool dm_check_soft_reset(void *handle) | |
311 | { | |
312 | return false; | |
313 | } | |
314 | ||
315 | static int dm_soft_reset(void *handle) | |
316 | { | |
317 | /* XXX todo */ | |
318 | return 0; | |
319 | } | |
320 | ||
3ee6b26b AD |
321 | static struct amdgpu_crtc * |
322 | get_crtc_by_otg_inst(struct amdgpu_device *adev, | |
323 | int otg_inst) | |
4562236b | 324 | { |
4a580877 | 325 | struct drm_device *dev = adev_to_drm(adev); |
4562236b HW |
326 | struct drm_crtc *crtc; |
327 | struct amdgpu_crtc *amdgpu_crtc; | |
328 | ||
bcd74374 | 329 | if (WARN_ON(otg_inst == -1)) |
4562236b | 330 | return adev->mode_info.crtcs[0]; |
4562236b HW |
331 | |
332 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
333 | amdgpu_crtc = to_amdgpu_crtc(crtc); | |
334 | ||
335 | if (amdgpu_crtc->otg_inst == otg_inst) | |
336 | return amdgpu_crtc; | |
337 | } | |
338 | ||
339 | return NULL; | |
340 | } | |
341 | ||
a85ba005 NC |
342 | static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, |
343 | struct dm_crtc_state *new_state) | |
344 | { | |
345 | if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) | |
346 | return true; | |
6c5e25a0 | 347 | else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) |
a85ba005 NC |
348 | return true; |
349 | else | |
350 | return false; | |
351 | } | |
352 | ||
bb46a6a9 RS |
353 | static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, |
354 | int planes_count) | |
355 | { | |
356 | int i, j; | |
bb46a6a9 | 357 | |
8866d627 JC |
358 | for (i = 0, j = planes_count - 1; i < j; i++, j--) |
359 | swap(array_of_surface_update[i], array_of_surface_update[j]); | |
bb46a6a9 RS |
360 | } |
361 | ||
81f743a0 RS |
362 | /** |
363 | * update_planes_and_stream_adapter() - Send planes to be updated in DC | |
364 | * | |
365 | * DC has a generic way to update planes and stream via | |
366 | * dc_update_planes_and_stream function; however, DM might need some | |
367 | * adjustments and preparation before calling it. This function is a wrapper | |
368 | * for the dc_update_planes_and_stream that does any required configuration | |
369 | * before passing control to DC. | |
21d81681 SS |
370 | * |
371 | * @dc: Display Core control structure | |
372 | * @update_type: specify whether it is FULL/MEDIUM/FAST update | |
373 | * @planes_count: planes count to update | |
374 | * @stream: stream state | |
375 | * @stream_update: stream update | |
376 | * @array_of_surface_update: dc surface update pointer | |
377 | * | |
81f743a0 RS |
378 | */ |
379 | static inline bool update_planes_and_stream_adapter(struct dc *dc, | |
380 | int update_type, | |
381 | int planes_count, | |
382 | struct dc_stream_state *stream, | |
383 | struct dc_stream_update *stream_update, | |
384 | struct dc_surface_update *array_of_surface_update) | |
385 | { | |
bb46a6a9 RS |
386 | reverse_planes_order(array_of_surface_update, planes_count); |
387 | ||
81f743a0 RS |
388 | /* |
389 | * Previous frame finished and HW is ready for optimization. | |
390 | */ | |
391 | if (update_type == UPDATE_TYPE_FAST) | |
392 | dc_post_update_surfaces_to_stream(dc); | |
393 | ||
394 | return dc_update_planes_and_stream(dc, | |
395 | array_of_surface_update, | |
396 | planes_count, | |
397 | stream, | |
398 | stream_update); | |
399 | } | |
400 | ||
b8e8c934 HW |
401 | /** |
402 | * dm_pflip_high_irq() - Handle pageflip interrupt | |
403 | * @interrupt_params: ignored | |
404 | * | |
405 | * Handles the pageflip interrupt by notifying all interested parties | |
406 | * that the pageflip has been completed. | |
407 | */ | |
4562236b HW |
408 | static void dm_pflip_high_irq(void *interrupt_params) |
409 | { | |
4562236b HW |
410 | struct amdgpu_crtc *amdgpu_crtc; |
411 | struct common_irq_params *irq_params = interrupt_params; | |
412 | struct amdgpu_device *adev = irq_params->adev; | |
413 | unsigned long flags; | |
71bbe51a | 414 | struct drm_pending_vblank_event *e; |
ae67558b | 415 | u32 vpos, hpos, v_blank_start, v_blank_end; |
71bbe51a | 416 | bool vrr_active; |
4562236b HW |
417 | |
418 | amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); | |
419 | ||
420 | /* IRQ could occur when in initial stage */ | |
1f6010a9 | 421 | /* TODO work and BO cleanup */ |
4562236b | 422 | if (amdgpu_crtc == NULL) { |
cb2318b7 | 423 | DC_LOG_PFLIP("CRTC is null, returning.\n"); |
4562236b HW |
424 | return; |
425 | } | |
426 | ||
4a580877 | 427 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
4562236b | 428 | |
c82eddf8 SS |
429 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { |
430 | DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", | |
431 | amdgpu_crtc->pflip_status, | |
432 | AMDGPU_FLIP_SUBMITTED, | |
433 | amdgpu_crtc->crtc_id, | |
434 | amdgpu_crtc); | |
4a580877 | 435 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
4562236b HW |
436 | return; |
437 | } | |
438 | ||
71bbe51a MK |
439 | /* page flip completed. */ |
440 | e = amdgpu_crtc->event; | |
441 | amdgpu_crtc->event = NULL; | |
4562236b | 442 | |
bcd74374 | 443 | WARN_ON(!e); |
1159898a | 444 | |
6c5e25a0 | 445 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); |
71bbe51a MK |
446 | |
447 | /* Fixed refresh rate, or VRR scanout position outside front-porch? */ | |
448 | if (!vrr_active || | |
585d450c | 449 | !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, |
71bbe51a MK |
450 | &v_blank_end, &hpos, &vpos) || |
451 | (vpos < v_blank_start)) { | |
452 | /* Update to correct count and vblank timestamp if racing with | |
453 | * vblank irq. This also updates to the correct vblank timestamp | |
454 | * even in VRR mode, as scanout is past the front-porch atm. | |
455 | */ | |
456 | drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); | |
1159898a | 457 | |
71bbe51a MK |
458 | /* Wake up userspace by sending the pageflip event with proper |
459 | * count and timestamp of vblank of flip completion. | |
460 | */ | |
461 | if (e) { | |
462 | drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); | |
463 | ||
464 | /* Event sent, so done with vblank for this flip */ | |
465 | drm_crtc_vblank_put(&amdgpu_crtc->base); | |
466 | } | |
467 | } else if (e) { | |
468 | /* VRR active and inside front-porch: vblank count and | |
469 | * timestamp for pageflip event will only be up to date after | |
470 | * drm_crtc_handle_vblank() has been executed from late vblank | |
471 | * irq handler after start of back-porch (vline 0). We queue the | |
472 | * pageflip event for send-out by drm_crtc_handle_vblank() with | |
473 | * updated timestamp and count, once it runs after us. | |
474 | * | |
475 | * We need to open-code this instead of using the helper | |
476 | * drm_crtc_arm_vblank_event(), as that helper would | |
477 | * call drm_crtc_accurate_vblank_count(), which we must | |
478 | * not call in VRR mode while we are in front-porch! | |
479 | */ | |
480 | ||
481 | /* sequence will be replaced by real count during send-out. */ | |
482 | e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); | |
483 | e->pipe = amdgpu_crtc->crtc_id; | |
484 | ||
4a580877 | 485 | list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); |
71bbe51a MK |
486 | e = NULL; |
487 | } | |
4562236b | 488 | |
fdd1fe57 MK |
489 | /* Keep track of vblank of this flip for flip throttling. We use the |
490 | * cooked hw counter, as that one incremented at start of this vblank | |
491 | * of pageflip completion, so last_flip_vblank is the forbidden count | |
492 | * for queueing new pageflips if vsync + VRR is enabled. | |
493 | */ | |
5d1c59c4 | 494 | amdgpu_crtc->dm_irq_params.last_flip_vblank = |
e3eff4b5 | 495 | amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); |
fdd1fe57 | 496 | |
54f5499a | 497 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; |
4a580877 | 498 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
4562236b | 499 | |
cb2318b7 VL |
500 | DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", |
501 | amdgpu_crtc->crtc_id, amdgpu_crtc, | |
502 | vrr_active, (int) !e); | |
4562236b HW |
503 | } |
504 | ||
d2574c33 MK |
505 | static void dm_vupdate_high_irq(void *interrupt_params) |
506 | { | |
507 | struct common_irq_params *irq_params = interrupt_params; | |
508 | struct amdgpu_device *adev = irq_params->adev; | |
509 | struct amdgpu_crtc *acrtc; | |
47588233 RS |
510 | struct drm_device *drm_dev; |
511 | struct drm_vblank_crtc *vblank; | |
512 | ktime_t frame_duration_ns, previous_timestamp; | |
09aef2c4 | 513 | unsigned long flags; |
585d450c | 514 | int vrr_active; |
d2574c33 MK |
515 | |
516 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); | |
517 | ||
518 | if (acrtc) { | |
6c5e25a0 | 519 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
47588233 RS |
520 | drm_dev = acrtc->base.dev; |
521 | vblank = &drm_dev->vblank[acrtc->base.index]; | |
522 | previous_timestamp = atomic64_read(&irq_params->previous_timestamp); | |
523 | frame_duration_ns = vblank->time - previous_timestamp; | |
524 | ||
525 | if (frame_duration_ns > 0) { | |
526 | trace_amdgpu_refresh_rate_track(acrtc->base.index, | |
527 | frame_duration_ns, | |
528 | ktime_divns(NSEC_PER_SEC, frame_duration_ns)); | |
529 | atomic64_set(&irq_params->previous_timestamp, vblank->time); | |
530 | } | |
d2574c33 | 531 | |
cb2318b7 | 532 | DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n", |
7f2be468 | 533 | acrtc->crtc_id, |
585d450c | 534 | vrr_active); |
d2574c33 MK |
535 | |
536 | /* Core vblank handling is done here after end of front-porch in | |
537 | * vrr mode, as vblank timestamping will give valid results | |
538 | * while now done after front-porch. This will also deliver | |
539 | * page-flip completion events that have been queued to us | |
540 | * if a pageflip happened inside front-porch. | |
541 | */ | |
585d450c | 542 | if (vrr_active) { |
6c5e25a0 | 543 | amdgpu_dm_crtc_handle_vblank(acrtc); |
09aef2c4 MK |
544 | |
545 | /* BTR processing for pre-DCE12 ASICs */ | |
585d450c | 546 | if (acrtc->dm_irq_params.stream && |
09aef2c4 | 547 | adev->family < AMDGPU_FAMILY_AI) { |
4a580877 | 548 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
09aef2c4 MK |
549 | mod_freesync_handle_v_update( |
550 | adev->dm.freesync_module, | |
585d450c AP |
551 | acrtc->dm_irq_params.stream, |
552 | &acrtc->dm_irq_params.vrr_params); | |
09aef2c4 MK |
553 | |
554 | dc_stream_adjust_vmin_vmax( | |
555 | adev->dm.dc, | |
585d450c AP |
556 | acrtc->dm_irq_params.stream, |
557 | &acrtc->dm_irq_params.vrr_params.adjust); | |
4a580877 | 558 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
09aef2c4 MK |
559 | } |
560 | } | |
d2574c33 MK |
561 | } |
562 | } | |
563 | ||
b8e8c934 HW |
564 | /** |
565 | * dm_crtc_high_irq() - Handles CRTC interrupt | |
2346ef47 | 566 | * @interrupt_params: used for determining the CRTC instance |
b8e8c934 HW |
567 | * |
568 | * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK | |
569 | * event handler. | |
570 | */ | |
4562236b HW |
571 | static void dm_crtc_high_irq(void *interrupt_params) |
572 | { | |
573 | struct common_irq_params *irq_params = interrupt_params; | |
574 | struct amdgpu_device *adev = irq_params->adev; | |
4562236b | 575 | struct amdgpu_crtc *acrtc; |
09aef2c4 | 576 | unsigned long flags; |
585d450c | 577 | int vrr_active; |
4562236b | 578 | |
b57de80a | 579 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); |
16f17eda LL |
580 | if (!acrtc) |
581 | return; | |
582 | ||
6c5e25a0 | 583 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
16f17eda | 584 | |
cb2318b7 | 585 | DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, |
585d450c | 586 | vrr_active, acrtc->dm_irq_params.active_planes); |
16f17eda | 587 | |
2346ef47 NK |
588 | /** |
589 | * Core vblank handling at start of front-porch is only possible | |
590 | * in non-vrr mode, as only there vblank timestamping will give | |
591 | * valid results while done in front-porch. Otherwise defer it | |
592 | * to dm_vupdate_high_irq after end of front-porch. | |
593 | */ | |
585d450c | 594 | if (!vrr_active) |
6c5e25a0 | 595 | amdgpu_dm_crtc_handle_vblank(acrtc); |
2346ef47 NK |
596 | |
597 | /** | |
598 | * Following stuff must happen at start of vblank, for crc | |
599 | * computation and below-the-range btr support in vrr mode. | |
600 | */ | |
16f17eda | 601 | amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); |
2346ef47 NK |
602 | |
603 | /* BTR updates need to happen before VUPDATE on Vega and above. */ | |
604 | if (adev->family < AMDGPU_FAMILY_AI) | |
605 | return; | |
16f17eda | 606 | |
4a580877 | 607 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
16f17eda | 608 | |
585d450c AP |
609 | if (acrtc->dm_irq_params.stream && |
610 | acrtc->dm_irq_params.vrr_params.supported && | |
611 | acrtc->dm_irq_params.freesync_config.state == | |
612 | VRR_STATE_ACTIVE_VARIABLE) { | |
2346ef47 | 613 | mod_freesync_handle_v_update(adev->dm.freesync_module, |
585d450c AP |
614 | acrtc->dm_irq_params.stream, |
615 | &acrtc->dm_irq_params.vrr_params); | |
16f17eda | 616 | |
585d450c AP |
617 | dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, |
618 | &acrtc->dm_irq_params.vrr_params.adjust); | |
16f17eda LL |
619 | } |
620 | ||
2b5aed9a MK |
621 | /* |
622 | * If there aren't any active_planes then DCH HUBP may be clock-gated. | |
623 | * In that case, pageflip completion interrupts won't fire and pageflip | |
624 | * completion events won't get delivered. Prevent this by sending | |
625 | * pending pageflip events from here if a flip is still pending. | |
626 | * | |
627 | * If any planes are enabled, use dm_pflip_high_irq() instead, to | |
628 | * avoid race conditions between flip programming and completion, | |
629 | * which could cause too early flip completion events. | |
630 | */ | |
2346ef47 NK |
631 | if (adev->family >= AMDGPU_FAMILY_RV && |
632 | acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && | |
585d450c | 633 | acrtc->dm_irq_params.active_planes == 0) { |
16f17eda LL |
634 | if (acrtc->event) { |
635 | drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); | |
636 | acrtc->event = NULL; | |
637 | drm_crtc_vblank_put(&acrtc->base); | |
638 | } | |
639 | acrtc->pflip_status = AMDGPU_FLIP_NONE; | |
640 | } | |
641 | ||
4a580877 | 642 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
16f17eda LL |
643 | } |
644 | ||
9e1178ef | 645 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
86bc2219 WL |
646 | /** |
647 | * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for | |
648 | * DCN generation ASICs | |
48e01bf4 | 649 | * @interrupt_params: interrupt parameters |
86bc2219 WL |
650 | * |
651 | * Used to set crc window/read out crc value at vertical line 0 position | |
652 | */ | |
86bc2219 WL |
653 | static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) |
654 | { | |
655 | struct common_irq_params *irq_params = interrupt_params; | |
656 | struct amdgpu_device *adev = irq_params->adev; | |
657 | struct amdgpu_crtc *acrtc; | |
658 | ||
659 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); | |
660 | ||
661 | if (!acrtc) | |
662 | return; | |
663 | ||
664 | amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); | |
665 | } | |
433e5dec | 666 | #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ |
86bc2219 | 667 | |
e27c41d5 | 668 | /** |
03f2abb0 | 669 | * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. |
e27c41d5 JS |
670 | * @adev: amdgpu_device pointer |
671 | * @notify: dmub notification structure | |
672 | * | |
673 | * Dmub AUX or SET_CONFIG command completion processing callback | |
674 | * Copies dmub notification to DM which is to be read by AUX command. | |
675 | * issuing thread and also signals the event to wake up the thread. | |
676 | */ | |
240e6d25 IB |
677 | static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, |
678 | struct dmub_notification *notify) | |
e27c41d5 JS |
679 | { |
680 | if (adev->dm.dmub_notify) | |
681 | memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); | |
682 | if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) | |
683 | complete(&adev->dm.dmub_aux_transfer_done); | |
684 | } | |
685 | ||
686 | /** | |
687 | * dmub_hpd_callback - DMUB HPD interrupt processing callback. | |
688 | * @adev: amdgpu_device pointer | |
689 | * @notify: dmub notification structure | |
690 | * | |
691 | * Dmub Hpd interrupt processing callback. Gets displayindex through the | |
692 | * ink index and calls helper to do the processing. | |
693 | */ | |
240e6d25 IB |
694 | static void dmub_hpd_callback(struct amdgpu_device *adev, |
695 | struct dmub_notification *notify) | |
e27c41d5 JS |
696 | { |
697 | struct amdgpu_dm_connector *aconnector; | |
f6e03f80 | 698 | struct amdgpu_dm_connector *hpd_aconnector = NULL; |
e27c41d5 JS |
699 | struct drm_connector *connector; |
700 | struct drm_connector_list_iter iter; | |
701 | struct dc_link *link; | |
ae67558b | 702 | u8 link_index = 0; |
978ffac8 | 703 | struct drm_device *dev; |
e27c41d5 JS |
704 | |
705 | if (adev == NULL) | |
706 | return; | |
707 | ||
708 | if (notify == NULL) { | |
709 | DRM_ERROR("DMUB HPD callback notification was NULL"); | |
710 | return; | |
711 | } | |
712 | ||
713 | if (notify->link_index > adev->dm.dc->link_count) { | |
714 | DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); | |
715 | return; | |
716 | } | |
717 | ||
e27c41d5 | 718 | link_index = notify->link_index; |
e27c41d5 | 719 | link = adev->dm.dc->links[link_index]; |
978ffac8 | 720 | dev = adev->dm.ddev; |
e27c41d5 JS |
721 | |
722 | drm_connector_list_iter_begin(dev, &iter); | |
723 | drm_for_each_connector_iter(connector, &iter) { | |
724 | aconnector = to_amdgpu_dm_connector(connector); | |
725 | if (link && aconnector->dc_link == link) { | |
c416a9e4 SW |
726 | if (notify->type == DMUB_NOTIFICATION_HPD) |
727 | DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); | |
728 | else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) | |
729 | DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); | |
730 | else | |
731 | DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", | |
732 | notify->type, link_index); | |
733 | ||
f6e03f80 | 734 | hpd_aconnector = aconnector; |
e27c41d5 JS |
735 | break; |
736 | } | |
737 | } | |
738 | drm_connector_list_iter_end(&iter); | |
e27c41d5 | 739 | |
c40a09e5 NK |
740 | if (hpd_aconnector) { |
741 | if (notify->type == DMUB_NOTIFICATION_HPD) | |
742 | handle_hpd_irq_helper(hpd_aconnector); | |
743 | else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) | |
744 | handle_hpd_rx_irq(hpd_aconnector); | |
745 | } | |
e27c41d5 JS |
746 | } |
747 | ||
748 | /** | |
749 | * register_dmub_notify_callback - Sets callback for DMUB notify | |
750 | * @adev: amdgpu_device pointer | |
751 | * @type: Type of dmub notification | |
752 | * @callback: Dmub interrupt callback function | |
753 | * @dmub_int_thread_offload: offload indicator | |
754 | * | |
755 | * API to register a dmub callback handler for a dmub notification | |
756 | * Also sets indicator whether callback processing to be offloaded. | |
757 | * to dmub interrupt handling thread | |
758 | * Return: true if successfully registered, false if there is existing registration | |
759 | */ | |
240e6d25 IB |
760 | static bool register_dmub_notify_callback(struct amdgpu_device *adev, |
761 | enum dmub_notification_type type, | |
762 | dmub_notify_interrupt_callback_t callback, | |
763 | bool dmub_int_thread_offload) | |
e27c41d5 JS |
764 | { |
765 | if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { | |
766 | adev->dm.dmub_callback[type] = callback; | |
767 | adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; | |
768 | } else | |
769 | return false; | |
770 | ||
771 | return true; | |
772 | } | |
773 | ||
774 | static void dm_handle_hpd_work(struct work_struct *work) | |
775 | { | |
776 | struct dmub_hpd_work *dmub_hpd_wrk; | |
777 | ||
778 | dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); | |
779 | ||
780 | if (!dmub_hpd_wrk->dmub_notify) { | |
781 | DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); | |
782 | return; | |
783 | } | |
784 | ||
785 | if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { | |
786 | dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, | |
787 | dmub_hpd_wrk->dmub_notify); | |
788 | } | |
094b21c1 JS |
789 | |
790 | kfree(dmub_hpd_wrk->dmub_notify); | |
e27c41d5 JS |
791 | kfree(dmub_hpd_wrk); |
792 | ||
793 | } | |
794 | ||
e25515e2 | 795 | #define DMUB_TRACE_MAX_READ 64 |
81927e28 JS |
796 | /** |
797 | * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt | |
798 | * @interrupt_params: used for determining the Outbox instance | |
799 | * | |
800 | * Handles the Outbox Interrupt | |
801 | * event handler. | |
802 | */ | |
81927e28 JS |
803 | static void dm_dmub_outbox1_low_irq(void *interrupt_params) |
804 | { | |
805 | struct dmub_notification notify; | |
806 | struct common_irq_params *irq_params = interrupt_params; | |
807 | struct amdgpu_device *adev = irq_params->adev; | |
808 | struct amdgpu_display_manager *dm = &adev->dm; | |
809 | struct dmcub_trace_buf_entry entry = { 0 }; | |
ae67558b | 810 | u32 count = 0; |
e27c41d5 | 811 | struct dmub_hpd_work *dmub_hpd_wrk; |
f6e03f80 | 812 | struct dc_link *plink = NULL; |
81927e28 | 813 | |
f6e03f80 JS |
814 | if (dc_enable_dmub_notifications(adev->dm.dc) && |
815 | irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { | |
e27c41d5 | 816 | |
f6e03f80 JS |
817 | do { |
818 | dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); | |
a35faec3 | 819 | if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { |
f6e03f80 JS |
820 | DRM_ERROR("DM: notify type %d invalid!", notify.type); |
821 | continue; | |
822 | } | |
c40a09e5 NK |
823 | if (!dm->dmub_callback[notify.type]) { |
824 | DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); | |
825 | continue; | |
826 | } | |
f6e03f80 | 827 | if (dm->dmub_thread_offload[notify.type] == true) { |
094b21c1 JS |
828 | dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); |
829 | if (!dmub_hpd_wrk) { | |
830 | DRM_ERROR("Failed to allocate dmub_hpd_wrk"); | |
831 | return; | |
832 | } | |
0e909e4f CJ |
833 | dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), |
834 | GFP_ATOMIC); | |
094b21c1 JS |
835 | if (!dmub_hpd_wrk->dmub_notify) { |
836 | kfree(dmub_hpd_wrk); | |
837 | DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); | |
838 | return; | |
839 | } | |
840 | INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); | |
f6e03f80 JS |
841 | dmub_hpd_wrk->adev = adev; |
842 | if (notify.type == DMUB_NOTIFICATION_HPD) { | |
843 | plink = adev->dm.dc->links[notify.link_index]; | |
844 | if (plink) { | |
845 | plink->hpd_status = | |
b97788e5 | 846 | notify.hpd_status == DP_HPD_PLUG; |
f6e03f80 | 847 | } |
e27c41d5 | 848 | } |
f6e03f80 JS |
849 | queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); |
850 | } else { | |
851 | dm->dmub_callback[notify.type](adev, ¬ify); | |
852 | } | |
853 | } while (notify.pending_notification); | |
81927e28 JS |
854 | } |
855 | ||
856 | ||
857 | do { | |
858 | if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { | |
859 | trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, | |
860 | entry.param0, entry.param1); | |
861 | ||
862 | DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", | |
863 | entry.trace_code, entry.tick_count, entry.param0, entry.param1); | |
864 | } else | |
865 | break; | |
866 | ||
867 | count++; | |
868 | ||
869 | } while (count <= DMUB_TRACE_MAX_READ); | |
870 | ||
f6e03f80 JS |
871 | if (count > DMUB_TRACE_MAX_READ) |
872 | DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); | |
81927e28 | 873 | } |
86bc2219 | 874 | |
4562236b HW |
875 | static int dm_set_clockgating_state(void *handle, |
876 | enum amd_clockgating_state state) | |
877 | { | |
878 | return 0; | |
879 | } | |
880 | ||
881 | static int dm_set_powergating_state(void *handle, | |
882 | enum amd_powergating_state state) | |
883 | { | |
884 | return 0; | |
885 | } | |
886 | ||
887 | /* Prototypes of private functions */ | |
c82eddf8 | 888 | static int dm_early_init(void *handle); |
4562236b | 889 | |
a32e24b4 | 890 | /* Allocate memory for FBC compressed data */ |
3e332d3a | 891 | static void amdgpu_dm_fbc_init(struct drm_connector *connector) |
a32e24b4 | 892 | { |
3e332d3a | 893 | struct drm_device *dev = connector->dev; |
1348969a | 894 | struct amdgpu_device *adev = drm_to_adev(dev); |
4d154b85 | 895 | struct dm_compressor_info *compressor = &adev->dm.compressor; |
3e332d3a RL |
896 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); |
897 | struct drm_display_mode *mode; | |
42e67c3b RL |
898 | unsigned long max_size = 0; |
899 | ||
900 | if (adev->dm.dc->fbc_compressor == NULL) | |
901 | return; | |
a32e24b4 | 902 | |
3e332d3a | 903 | if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) |
42e67c3b RL |
904 | return; |
905 | ||
3e332d3a RL |
906 | if (compressor->bo_ptr) |
907 | return; | |
42e67c3b | 908 | |
42e67c3b | 909 | |
3e332d3a RL |
910 | list_for_each_entry(mode, &connector->modes, head) { |
911 | if (max_size < mode->htotal * mode->vtotal) | |
912 | max_size = mode->htotal * mode->vtotal; | |
42e67c3b RL |
913 | } |
914 | ||
915 | if (max_size) { | |
916 | int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, | |
0e5916ff | 917 | AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, |
42e67c3b | 918 | &compressor->gpu_addr, &compressor->cpu_addr); |
a32e24b4 RL |
919 | |
920 | if (r) | |
42e67c3b RL |
921 | DRM_ERROR("DM: Failed to initialize FBC\n"); |
922 | else { | |
923 | adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; | |
924 | DRM_INFO("DM: FBC alloc %lu\n", max_size*4); | |
925 | } | |
926 | ||
a32e24b4 RL |
927 | } |
928 | ||
929 | } | |
a32e24b4 | 930 | |
6ce8f316 NK |
931 | static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, |
932 | int pipe, bool *enabled, | |
933 | unsigned char *buf, int max_bytes) | |
934 | { | |
935 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 936 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
937 | struct drm_connector *connector; |
938 | struct drm_connector_list_iter conn_iter; | |
939 | struct amdgpu_dm_connector *aconnector; | |
940 | int ret = 0; | |
941 | ||
942 | *enabled = false; | |
943 | ||
944 | mutex_lock(&adev->dm.audio_lock); | |
945 | ||
946 | drm_connector_list_iter_begin(dev, &conn_iter); | |
947 | drm_for_each_connector_iter(connector, &conn_iter) { | |
948 | aconnector = to_amdgpu_dm_connector(connector); | |
949 | if (aconnector->audio_inst != port) | |
950 | continue; | |
951 | ||
952 | *enabled = true; | |
953 | ret = drm_eld_size(connector->eld); | |
954 | memcpy(buf, connector->eld, min(max_bytes, ret)); | |
955 | ||
956 | break; | |
957 | } | |
958 | drm_connector_list_iter_end(&conn_iter); | |
959 | ||
960 | mutex_unlock(&adev->dm.audio_lock); | |
961 | ||
962 | DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); | |
963 | ||
964 | return ret; | |
965 | } | |
966 | ||
967 | static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { | |
968 | .get_eld = amdgpu_dm_audio_component_get_eld, | |
969 | }; | |
970 | ||
971 | static int amdgpu_dm_audio_component_bind(struct device *kdev, | |
972 | struct device *hda_kdev, void *data) | |
973 | { | |
974 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 975 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
976 | struct drm_audio_component *acomp = data; |
977 | ||
978 | acomp->ops = &amdgpu_dm_audio_component_ops; | |
979 | acomp->dev = kdev; | |
980 | adev->dm.audio_component = acomp; | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
985 | static void amdgpu_dm_audio_component_unbind(struct device *kdev, | |
986 | struct device *hda_kdev, void *data) | |
987 | { | |
988 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 989 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
990 | struct drm_audio_component *acomp = data; |
991 | ||
992 | acomp->ops = NULL; | |
993 | acomp->dev = NULL; | |
994 | adev->dm.audio_component = NULL; | |
995 | } | |
996 | ||
997 | static const struct component_ops amdgpu_dm_audio_component_bind_ops = { | |
998 | .bind = amdgpu_dm_audio_component_bind, | |
999 | .unbind = amdgpu_dm_audio_component_unbind, | |
1000 | }; | |
1001 | ||
1002 | static int amdgpu_dm_audio_init(struct amdgpu_device *adev) | |
1003 | { | |
1004 | int i, ret; | |
1005 | ||
1006 | if (!amdgpu_audio) | |
1007 | return 0; | |
1008 | ||
1009 | adev->mode_info.audio.enabled = true; | |
1010 | ||
1011 | adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; | |
1012 | ||
1013 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
1014 | adev->mode_info.audio.pin[i].channels = -1; | |
1015 | adev->mode_info.audio.pin[i].rate = -1; | |
1016 | adev->mode_info.audio.pin[i].bits_per_sample = -1; | |
1017 | adev->mode_info.audio.pin[i].status_bits = 0; | |
1018 | adev->mode_info.audio.pin[i].category_code = 0; | |
1019 | adev->mode_info.audio.pin[i].connected = false; | |
1020 | adev->mode_info.audio.pin[i].id = | |
1021 | adev->dm.dc->res_pool->audios[i]->inst; | |
1022 | adev->mode_info.audio.pin[i].offset = 0; | |
1023 | } | |
1024 | ||
1025 | ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); | |
1026 | if (ret < 0) | |
1027 | return ret; | |
1028 | ||
1029 | adev->dm.audio_registered = true; | |
1030 | ||
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) | |
1035 | { | |
1036 | if (!amdgpu_audio) | |
1037 | return; | |
1038 | ||
1039 | if (!adev->mode_info.audio.enabled) | |
1040 | return; | |
1041 | ||
1042 | if (adev->dm.audio_registered) { | |
1043 | component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); | |
1044 | adev->dm.audio_registered = false; | |
1045 | } | |
1046 | ||
1047 | /* TODO: Disable audio? */ | |
1048 | ||
1049 | adev->mode_info.audio.enabled = false; | |
1050 | } | |
1051 | ||
dfd84d90 | 1052 | static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) |
6ce8f316 NK |
1053 | { |
1054 | struct drm_audio_component *acomp = adev->dm.audio_component; | |
1055 | ||
1056 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { | |
1057 | DRM_DEBUG_KMS("Notify ELD: %d\n", pin); | |
1058 | ||
1059 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, | |
1060 | pin, -1); | |
1061 | } | |
1062 | } | |
1063 | ||
743b9786 NK |
1064 | static int dm_dmub_hw_init(struct amdgpu_device *adev) |
1065 | { | |
743b9786 NK |
1066 | const struct dmcub_firmware_header_v1_0 *hdr; |
1067 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; | |
8c7aea40 | 1068 | struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; |
743b9786 NK |
1069 | const struct firmware *dmub_fw = adev->dm.dmub_fw; |
1070 | struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; | |
1071 | struct abm *abm = adev->dm.dc->res_pool->abm; | |
96182df9 | 1072 | struct dc_context *ctx = adev->dm.dc->ctx; |
743b9786 NK |
1073 | struct dmub_srv_hw_params hw_params; |
1074 | enum dmub_status status; | |
1075 | const unsigned char *fw_inst_const, *fw_bss_data; | |
ae67558b | 1076 | u32 i, fw_inst_const_size, fw_bss_data_size; |
743b9786 NK |
1077 | bool has_hw_support; |
1078 | ||
1079 | if (!dmub_srv) | |
1080 | /* DMUB isn't supported on the ASIC. */ | |
1081 | return 0; | |
1082 | ||
8c7aea40 NK |
1083 | if (!fb_info) { |
1084 | DRM_ERROR("No framebuffer info for DMUB service.\n"); | |
1085 | return -EINVAL; | |
1086 | } | |
1087 | ||
743b9786 NK |
1088 | if (!dmub_fw) { |
1089 | /* Firmware required for DMUB support. */ | |
1090 | DRM_ERROR("No firmware provided for DMUB.\n"); | |
1091 | return -EINVAL; | |
1092 | } | |
1093 | ||
96182df9 AP |
1094 | /* initialize register offsets for ASICs with runtime initialization available */ |
1095 | if (dmub_srv->hw_funcs.init_reg_offsets) | |
1096 | dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx); | |
1097 | ||
743b9786 NK |
1098 | status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); |
1099 | if (status != DMUB_STATUS_OK) { | |
1100 | DRM_ERROR("Error checking HW support for DMUB: %d\n", status); | |
1101 | return -EINVAL; | |
1102 | } | |
1103 | ||
1104 | if (!has_hw_support) { | |
1105 | DRM_INFO("DMUB unsupported on ASIC\n"); | |
1106 | return 0; | |
1107 | } | |
1108 | ||
47e62dbd NK |
1109 | /* Reset DMCUB if it was previously running - before we overwrite its memory. */ |
1110 | status = dmub_srv_hw_reset(dmub_srv); | |
1111 | if (status != DMUB_STATUS_OK) | |
1112 | DRM_WARN("Error resetting DMUB HW: %d\n", status); | |
1113 | ||
743b9786 NK |
1114 | hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; |
1115 | ||
743b9786 NK |
1116 | fw_inst_const = dmub_fw->data + |
1117 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
8c7aea40 | 1118 | PSP_HEADER_BYTES; |
743b9786 NK |
1119 | |
1120 | fw_bss_data = dmub_fw->data + | |
1121 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
1122 | le32_to_cpu(hdr->inst_const_bytes); | |
1123 | ||
1124 | /* Copy firmware and bios info into FB memory. */ | |
8c7aea40 NK |
1125 | fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - |
1126 | PSP_HEADER_BYTES - PSP_FOOTER_BYTES; | |
1127 | ||
1128 | fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); | |
1129 | ||
ddde28a5 HW |
1130 | /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, |
1131 | * amdgpu_ucode_init_single_fw will load dmub firmware | |
1132 | * fw_inst_const part to cw0; otherwise, the firmware back door load | |
1133 | * will be done by dm_dmub_hw_init | |
1134 | */ | |
1135 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
1136 | memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, | |
1137 | fw_inst_const_size); | |
1138 | } | |
1139 | ||
a576b345 NK |
1140 | if (fw_bss_data_size) |
1141 | memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, | |
1142 | fw_bss_data, fw_bss_data_size); | |
ddde28a5 HW |
1143 | |
1144 | /* Copy firmware bios info into FB memory. */ | |
8c7aea40 NK |
1145 | memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, |
1146 | adev->bios_size); | |
1147 | ||
1148 | /* Reset regions that need to be reset. */ | |
1149 | memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, | |
1150 | fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); | |
1151 | ||
1152 | memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, | |
1153 | fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); | |
1154 | ||
1155 | memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, | |
1156 | fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); | |
743b9786 NK |
1157 | |
1158 | /* Initialize hardware. */ | |
1159 | memset(&hw_params, 0, sizeof(hw_params)); | |
1160 | hw_params.fb_base = adev->gmc.fb_start; | |
949933b0 | 1161 | hw_params.fb_offset = adev->vm_manager.vram_base_offset; |
743b9786 | 1162 | |
31a7f4bb HW |
1163 | /* backdoor load firmware and trigger dmub running */ |
1164 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) | |
1165 | hw_params.load_inst_const = true; | |
1166 | ||
743b9786 NK |
1167 | if (dmcu) |
1168 | hw_params.psp_version = dmcu->psp_version; | |
1169 | ||
8c7aea40 NK |
1170 | for (i = 0; i < fb_info->num_fb; ++i) |
1171 | hw_params.fb[i] = &fb_info->fb[i]; | |
743b9786 | 1172 | |
3b36f50d | 1173 | switch (adev->ip_versions[DCE_HWIP][0]) { |
f6aa84b8 RL |
1174 | case IP_VERSION(3, 1, 3): |
1175 | case IP_VERSION(3, 1, 4): | |
3b36f50d | 1176 | hw_params.dpia_supported = true; |
7367540b | 1177 | hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; |
5b109397 JS |
1178 | break; |
1179 | default: | |
1180 | break; | |
1181 | } | |
1182 | ||
743b9786 NK |
1183 | status = dmub_srv_hw_init(dmub_srv, &hw_params); |
1184 | if (status != DMUB_STATUS_OK) { | |
1185 | DRM_ERROR("Error initializing DMUB HW: %d\n", status); | |
1186 | return -EINVAL; | |
1187 | } | |
1188 | ||
1189 | /* Wait for firmware load to finish. */ | |
1190 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); | |
1191 | if (status != DMUB_STATUS_OK) | |
1192 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); | |
1193 | ||
1194 | /* Init DMCU and ABM if available. */ | |
1195 | if (dmcu && abm) { | |
1196 | dmcu->funcs->dmcu_init(dmcu); | |
1197 | abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); | |
1198 | } | |
1199 | ||
051b7887 RL |
1200 | if (!adev->dm.dc->ctx->dmub_srv) |
1201 | adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); | |
9a71c7d3 NK |
1202 | if (!adev->dm.dc->ctx->dmub_srv) { |
1203 | DRM_ERROR("Couldn't allocate DC DMUB server!\n"); | |
1204 | return -ENOMEM; | |
1205 | } | |
1206 | ||
743b9786 NK |
1207 | DRM_INFO("DMUB hardware initialized: version=0x%08X\n", |
1208 | adev->dm.dmcub_fw_version); | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | ||
79d6b935 NK |
1213 | static void dm_dmub_hw_resume(struct amdgpu_device *adev) |
1214 | { | |
1215 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; | |
1216 | enum dmub_status status; | |
1217 | bool init; | |
1218 | ||
1219 | if (!dmub_srv) { | |
1220 | /* DMUB isn't supported on the ASIC. */ | |
1221 | return; | |
1222 | } | |
1223 | ||
1224 | status = dmub_srv_is_hw_init(dmub_srv, &init); | |
1225 | if (status != DMUB_STATUS_OK) | |
1226 | DRM_WARN("DMUB hardware init check failed: %d\n", status); | |
1227 | ||
1228 | if (status == DMUB_STATUS_OK && init) { | |
1229 | /* Wait for firmware load to finish. */ | |
1230 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); | |
1231 | if (status != DMUB_STATUS_OK) | |
1232 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); | |
1233 | } else { | |
1234 | /* Perform the full hardware initialization. */ | |
1235 | dm_dmub_hw_init(adev); | |
1236 | } | |
1237 | } | |
1238 | ||
c0fb85ae | 1239 | static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) |
c44a22b3 | 1240 | { |
ae67558b SS |
1241 | u64 pt_base; |
1242 | u32 logical_addr_low; | |
1243 | u32 logical_addr_high; | |
1244 | u32 agp_base, agp_bot, agp_top; | |
c0fb85ae | 1245 | PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; |
c44a22b3 | 1246 | |
a0f884f5 NK |
1247 | memset(pa_config, 0, sizeof(*pa_config)); |
1248 | ||
c0fb85ae YZ |
1249 | agp_base = 0; |
1250 | agp_bot = adev->gmc.agp_start >> 24; | |
1251 | agp_top = adev->gmc.agp_end >> 24; | |
c44a22b3 | 1252 | |
0294868f AD |
1253 | /* AGP aperture is disabled */ |
1254 | if (agp_bot == agp_top) { | |
4d2c6e89 | 1255 | logical_addr_low = adev->gmc.fb_start >> 18; |
0294868f AD |
1256 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1257 | /* | |
1258 | * Raven2 has a HW issue that it is unable to use the vram which | |
1259 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the | |
1260 | * workaround that increase system aperture high address (add 1) | |
1261 | * to get rid of the VM fault and hardware hang. | |
1262 | */ | |
1263 | logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; | |
1264 | else | |
4d2c6e89 | 1265 | logical_addr_high = adev->gmc.fb_end >> 18; |
0294868f | 1266 | } else { |
4d2c6e89 | 1267 | logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; |
0294868f AD |
1268 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1269 | /* | |
1270 | * Raven2 has a HW issue that it is unable to use the vram which | |
1271 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the | |
1272 | * workaround that increase system aperture high address (add 1) | |
1273 | * to get rid of the VM fault and hardware hang. | |
1274 | */ | |
1275 | logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); | |
1276 | else | |
1277 | logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; | |
1278 | } | |
1279 | ||
1280 | pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); | |
c44a22b3 | 1281 | |
c0fb85ae YZ |
1282 | page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; |
1283 | page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); | |
1284 | page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; | |
1285 | page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); | |
1286 | page_table_base.high_part = upper_32_bits(pt_base) & 0xF; | |
1287 | page_table_base.low_part = lower_32_bits(pt_base); | |
c44a22b3 | 1288 | |
c0fb85ae YZ |
1289 | pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; |
1290 | pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; | |
1291 | ||
c82eddf8 | 1292 | pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; |
c0fb85ae YZ |
1293 | pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; |
1294 | pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; | |
1295 | ||
1296 | pa_config->system_aperture.fb_base = adev->gmc.fb_start; | |
949933b0 | 1297 | pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; |
c0fb85ae YZ |
1298 | pa_config->system_aperture.fb_top = adev->gmc.fb_end; |
1299 | ||
1300 | pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; | |
1301 | pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; | |
1302 | pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; | |
1303 | ||
40e9f3f0 | 1304 | pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; |
c44a22b3 | 1305 | |
c44a22b3 | 1306 | } |
cae5c1ab | 1307 | |
028c4ccf QZ |
1308 | static void force_connector_state( |
1309 | struct amdgpu_dm_connector *aconnector, | |
1310 | enum drm_connector_force force_state) | |
1311 | { | |
1312 | struct drm_connector *connector = &aconnector->base; | |
1313 | ||
1314 | mutex_lock(&connector->dev->mode_config.mutex); | |
1315 | aconnector->base.force = force_state; | |
1316 | mutex_unlock(&connector->dev->mode_config.mutex); | |
1317 | ||
1318 | mutex_lock(&aconnector->hpd_lock); | |
1319 | drm_kms_helper_connector_hotplug_event(connector); | |
1320 | mutex_unlock(&aconnector->hpd_lock); | |
1321 | } | |
1322 | ||
8e794421 WL |
1323 | static void dm_handle_hpd_rx_offload_work(struct work_struct *work) |
1324 | { | |
1325 | struct hpd_rx_irq_offload_work *offload_work; | |
1326 | struct amdgpu_dm_connector *aconnector; | |
1327 | struct dc_link *dc_link; | |
1328 | struct amdgpu_device *adev; | |
1329 | enum dc_connection_type new_connection_type = dc_connection_none; | |
1330 | unsigned long flags; | |
028c4ccf QZ |
1331 | union test_response test_response; |
1332 | ||
1333 | memset(&test_response, 0, sizeof(test_response)); | |
8e794421 WL |
1334 | |
1335 | offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); | |
1336 | aconnector = offload_work->offload_wq->aconnector; | |
1337 | ||
1338 | if (!aconnector) { | |
1339 | DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); | |
1340 | goto skip; | |
1341 | } | |
1342 | ||
1343 | adev = drm_to_adev(aconnector->base.dev); | |
1344 | dc_link = aconnector->dc_link; | |
1345 | ||
1346 | mutex_lock(&aconnector->hpd_lock); | |
54618888 | 1347 | if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) |
8e794421 WL |
1348 | DRM_ERROR("KMS: Failed to detect connector\n"); |
1349 | mutex_unlock(&aconnector->hpd_lock); | |
1350 | ||
1351 | if (new_connection_type == dc_connection_none) | |
1352 | goto skip; | |
1353 | ||
1354 | if (amdgpu_in_reset(adev)) | |
1355 | goto skip; | |
1356 | ||
bb4fa525 WL |
1357 | if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || |
1358 | offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { | |
1359 | dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); | |
1360 | spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); | |
1361 | offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; | |
1362 | spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); | |
1363 | goto skip; | |
1364 | } | |
1365 | ||
8e794421 | 1366 | mutex_lock(&adev->dm.dc_lock); |
028c4ccf | 1367 | if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { |
8e794421 | 1368 | dc_link_dp_handle_automated_test(dc_link); |
028c4ccf QZ |
1369 | |
1370 | if (aconnector->timing_changed) { | |
1371 | /* force connector disconnect and reconnect */ | |
1372 | force_connector_state(aconnector, DRM_FORCE_OFF); | |
1373 | msleep(100); | |
1374 | force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); | |
1375 | } | |
1376 | ||
1377 | test_response.bits.ACK = 1; | |
1378 | ||
1379 | core_link_write_dpcd( | |
1380 | dc_link, | |
1381 | DP_TEST_RESPONSE, | |
1382 | &test_response.raw, | |
1383 | sizeof(test_response)); | |
c82eddf8 | 1384 | } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && |
c5a31f17 | 1385 | dc_link_check_link_loss_status(dc_link, &offload_work->data) && |
8e794421 | 1386 | dc_link_dp_allow_hpd_rx_irq(dc_link)) { |
e322843e HW |
1387 | /* offload_work->data is from handle_hpd_rx_irq-> |
1388 | * schedule_hpd_rx_offload_work.this is defer handle | |
1389 | * for hpd short pulse. upon here, link status may be | |
1390 | * changed, need get latest link status from dpcd | |
1391 | * registers. if link status is good, skip run link | |
1392 | * training again. | |
1393 | */ | |
1394 | union hpd_irq_data irq_data; | |
1395 | ||
1396 | memset(&irq_data, 0, sizeof(irq_data)); | |
1397 | ||
1398 | /* before dc_link_dp_handle_link_loss, allow new link lost handle | |
1399 | * request be added to work queue if link lost at end of dc_link_ | |
1400 | * dp_handle_link_loss | |
1401 | */ | |
8e794421 WL |
1402 | spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); |
1403 | offload_work->offload_wq->is_handling_link_loss = false; | |
1404 | spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); | |
e322843e | 1405 | |
54618888 | 1406 | if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && |
e322843e HW |
1407 | dc_link_check_link_loss_status(dc_link, &irq_data)) |
1408 | dc_link_dp_handle_link_loss(dc_link); | |
8e794421 WL |
1409 | } |
1410 | mutex_unlock(&adev->dm.dc_lock); | |
1411 | ||
1412 | skip: | |
1413 | kfree(offload_work); | |
1414 | ||
1415 | } | |
1416 | ||
1417 | static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) | |
1418 | { | |
1419 | int max_caps = dc->caps.max_links; | |
1420 | int i = 0; | |
1421 | struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; | |
1422 | ||
1423 | hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); | |
1424 | ||
1425 | if (!hpd_rx_offload_wq) | |
1426 | return NULL; | |
1427 | ||
1428 | ||
1429 | for (i = 0; i < max_caps; i++) { | |
1430 | hpd_rx_offload_wq[i].wq = | |
1431 | create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); | |
1432 | ||
1433 | if (hpd_rx_offload_wq[i].wq == NULL) { | |
1434 | DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); | |
7136f956 | 1435 | goto out_err; |
8e794421 WL |
1436 | } |
1437 | ||
1438 | spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); | |
1439 | } | |
1440 | ||
1441 | return hpd_rx_offload_wq; | |
7136f956 RM |
1442 | |
1443 | out_err: | |
1444 | for (i = 0; i < max_caps; i++) { | |
1445 | if (hpd_rx_offload_wq[i].wq) | |
1446 | destroy_workqueue(hpd_rx_offload_wq[i].wq); | |
1447 | } | |
1448 | kfree(hpd_rx_offload_wq); | |
1449 | return NULL; | |
8e794421 WL |
1450 | } |
1451 | ||
3ce51649 AD |
1452 | struct amdgpu_stutter_quirk { |
1453 | u16 chip_vendor; | |
1454 | u16 chip_device; | |
1455 | u16 subsys_vendor; | |
1456 | u16 subsys_device; | |
1457 | u8 revision; | |
1458 | }; | |
1459 | ||
1460 | static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { | |
1461 | /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ | |
1462 | { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, | |
1463 | { 0, 0, 0, 0, 0 }, | |
1464 | }; | |
1465 | ||
1466 | static bool dm_should_disable_stutter(struct pci_dev *pdev) | |
1467 | { | |
1468 | const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; | |
1469 | ||
1470 | while (p && p->chip_device != 0) { | |
1471 | if (pdev->vendor == p->chip_vendor && | |
1472 | pdev->device == p->chip_device && | |
1473 | pdev->subsystem_vendor == p->subsys_vendor && | |
1474 | pdev->subsystem_device == p->subsys_device && | |
1475 | pdev->revision == p->revision) { | |
1476 | return true; | |
1477 | } | |
1478 | ++p; | |
1479 | } | |
1480 | return false; | |
1481 | } | |
1482 | ||
57b9f338 FZ |
1483 | static const struct dmi_system_id hpd_disconnect_quirk_table[] = { |
1484 | { | |
1485 | .matches = { | |
1486 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1487 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), | |
1488 | }, | |
1489 | }, | |
1490 | { | |
1491 | .matches = { | |
1492 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1493 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), | |
1494 | }, | |
1495 | }, | |
1496 | { | |
1497 | .matches = { | |
1498 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1499 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), | |
1500 | }, | |
1501 | }, | |
503dc81c TL |
1502 | { |
1503 | .matches = { | |
1504 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1505 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), | |
1506 | }, | |
1507 | }, | |
1508 | { | |
1509 | .matches = { | |
1510 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1511 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), | |
1512 | }, | |
1513 | }, | |
1514 | { | |
1515 | .matches = { | |
1516 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1517 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), | |
1518 | }, | |
1519 | }, | |
1520 | { | |
1521 | .matches = { | |
1522 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1523 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), | |
1524 | }, | |
1525 | }, | |
1526 | { | |
1527 | .matches = { | |
1528 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1529 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), | |
1530 | }, | |
1531 | }, | |
1532 | { | |
1533 | .matches = { | |
1534 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1535 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), | |
1536 | }, | |
1537 | }, | |
57b9f338 | 1538 | {} |
503dc81c | 1539 | /* TODO: refactor this from a fixed table to a dynamic option */ |
57b9f338 FZ |
1540 | }; |
1541 | ||
1542 | static void retrieve_dmi_info(struct amdgpu_display_manager *dm) | |
1543 | { | |
1544 | const struct dmi_system_id *dmi_id; | |
1545 | ||
1546 | dm->aux_hpd_discon_quirk = false; | |
1547 | ||
1548 | dmi_id = dmi_first_match(hpd_disconnect_quirk_table); | |
1549 | if (dmi_id) { | |
1550 | dm->aux_hpd_discon_quirk = true; | |
1551 | DRM_INFO("aux_hpd_discon_quirk attached\n"); | |
1552 | } | |
1553 | } | |
1554 | ||
7578ecda | 1555 | static int amdgpu_dm_init(struct amdgpu_device *adev) |
4562236b HW |
1556 | { |
1557 | struct dc_init_data init_data; | |
52704fca | 1558 | struct dc_callback_init init_params; |
743b9786 | 1559 | int r; |
52704fca | 1560 | |
4a580877 | 1561 | adev->dm.ddev = adev_to_drm(adev); |
4562236b HW |
1562 | adev->dm.adev = adev; |
1563 | ||
4562236b HW |
1564 | /* Zero all the fields */ |
1565 | memset(&init_data, 0, sizeof(init_data)); | |
52704fca | 1566 | memset(&init_params, 0, sizeof(init_params)); |
4562236b | 1567 | |
ead08b95 | 1568 | mutex_init(&adev->dm.dpia_aux_lock); |
674e78ac | 1569 | mutex_init(&adev->dm.dc_lock); |
6ce8f316 | 1570 | mutex_init(&adev->dm.audio_lock); |
674e78ac | 1571 | |
c82eddf8 | 1572 | if (amdgpu_dm_irq_init(adev)) { |
4562236b HW |
1573 | DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); |
1574 | goto error; | |
1575 | } | |
1576 | ||
1577 | init_data.asic_id.chip_family = adev->family; | |
1578 | ||
2dc31ca1 | 1579 | init_data.asic_id.pci_revision_id = adev->pdev->revision; |
4562236b | 1580 | init_data.asic_id.hw_internal_rev = adev->external_rev_id; |
dae66a04 | 1581 | init_data.asic_id.chip_id = adev->pdev->device; |
4562236b | 1582 | |
770d13b1 | 1583 | init_data.asic_id.vram_width = adev->gmc.vram_width; |
4562236b HW |
1584 | /* TODO: initialize init_data.asic_id.vram_type here!!!! */ |
1585 | init_data.asic_id.atombios_base_address = | |
1586 | adev->mode_info.atom_context->bios; | |
1587 | ||
1588 | init_data.driver = adev; | |
1589 | ||
1590 | adev->dm.cgs_device = amdgpu_cgs_create_device(adev); | |
1591 | ||
1592 | if (!adev->dm.cgs_device) { | |
1593 | DRM_ERROR("amdgpu: failed to create cgs device.\n"); | |
1594 | goto error; | |
1595 | } | |
1596 | ||
1597 | init_data.cgs_device = adev->dm.cgs_device; | |
1598 | ||
4562236b HW |
1599 | init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; |
1600 | ||
fd546bc5 AD |
1601 | switch (adev->ip_versions[DCE_HWIP][0]) { |
1602 | case IP_VERSION(2, 1, 0): | |
1603 | switch (adev->dm.dmcub_fw_version) { | |
1604 | case 0: /* development */ | |
1605 | case 0x1: /* linux-firmware.git hash 6d9f399 */ | |
1606 | case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ | |
1607 | init_data.flags.disable_dmcu = false; | |
1608 | break; | |
1609 | default: | |
1610 | init_data.flags.disable_dmcu = true; | |
1611 | } | |
1612 | break; | |
1613 | case IP_VERSION(2, 0, 3): | |
1614 | init_data.flags.disable_dmcu = true; | |
1615 | break; | |
1616 | default: | |
1617 | break; | |
1618 | } | |
1619 | ||
60fb100b AD |
1620 | switch (adev->asic_type) { |
1621 | case CHIP_CARRIZO: | |
1622 | case CHIP_STONEY: | |
1ebcaebd NK |
1623 | init_data.flags.gpu_vm_support = true; |
1624 | break; | |
60fb100b | 1625 | default: |
1d789535 | 1626 | switch (adev->ip_versions[DCE_HWIP][0]) { |
559f591d AD |
1627 | case IP_VERSION(1, 0, 0): |
1628 | case IP_VERSION(1, 0, 1): | |
a7f520bf AD |
1629 | /* enable S/G on PCO and RV2 */ |
1630 | if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || | |
1631 | (adev->apu_flags & AMD_APU_IS_PICASSO)) | |
1632 | init_data.flags.gpu_vm_support = true; | |
1633 | break; | |
c4029779 | 1634 | case IP_VERSION(2, 1, 0): |
c08182f2 | 1635 | case IP_VERSION(3, 0, 1): |
8f56a0fe AD |
1636 | case IP_VERSION(3, 1, 2): |
1637 | case IP_VERSION(3, 1, 3): | |
69ed0c5d | 1638 | case IP_VERSION(3, 1, 4): |
512e8475 | 1639 | case IP_VERSION(3, 1, 5): |
0fe382fb | 1640 | case IP_VERSION(3, 1, 6): |
c08182f2 AD |
1641 | init_data.flags.gpu_vm_support = true; |
1642 | break; | |
c08182f2 AD |
1643 | default: |
1644 | break; | |
1645 | } | |
60fb100b AD |
1646 | break; |
1647 | } | |
70e64c4d ML |
1648 | if (init_data.flags.gpu_vm_support) |
1649 | init_data.flags.gpu_vm_support = amdgpu_sg_display_supported(adev); | |
6e227308 | 1650 | |
a7f520bf AD |
1651 | if (init_data.flags.gpu_vm_support) |
1652 | adev->mode_info.gpu_vm_support = true; | |
1653 | ||
04b94af4 AD |
1654 | if (amdgpu_dc_feature_mask & DC_FBC_MASK) |
1655 | init_data.flags.fbc_support = true; | |
1656 | ||
d99f38ae AD |
1657 | if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) |
1658 | init_data.flags.multi_mon_pp_mclk_switch = true; | |
1659 | ||
eaf56410 LL |
1660 | if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) |
1661 | init_data.flags.disable_fractional_pwm = true; | |
a5148245 ZL |
1662 | |
1663 | if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) | |
1664 | init_data.flags.edp_no_power_sequencing = true; | |
eaf56410 | 1665 | |
12320274 AP |
1666 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) |
1667 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; | |
1668 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) | |
1669 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; | |
12320274 | 1670 | |
7aba117a | 1671 | init_data.flags.seamless_boot_edp_requested = false; |
78ad75f8 | 1672 | |
1edf5ae1 | 1673 | if (check_seamless_boot_capability(adev)) { |
7aba117a | 1674 | init_data.flags.seamless_boot_edp_requested = true; |
1edf5ae1 ZL |
1675 | init_data.flags.allow_seamless_boot_optimization = true; |
1676 | DRM_INFO("Seamless boot condition check passed\n"); | |
1677 | } | |
1678 | ||
a8201902 LM |
1679 | init_data.flags.enable_mipi_converter_optimization = true; |
1680 | ||
e5028e9f | 1681 | init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; |
2a93292f | 1682 | init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; |
8774029f | 1683 | init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; |
e5028e9f | 1684 | |
0dd79532 | 1685 | INIT_LIST_HEAD(&adev->dm.da_list); |
57b9f338 FZ |
1686 | |
1687 | retrieve_dmi_info(&adev->dm); | |
1688 | ||
4562236b HW |
1689 | /* Display Core create. */ |
1690 | adev->dm.dc = dc_create(&init_data); | |
1691 | ||
423788c7 | 1692 | if (adev->dm.dc) { |
9788d087 | 1693 | DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, |
bf7fda0b | 1694 | dce_version_to_string(adev->dm.dc->ctx->dce_version)); |
423788c7 | 1695 | } else { |
9788d087 AP |
1696 | DRM_INFO("Display Core v%s failed to initialize on %s\n", DC_VER, |
1697 | dce_version_to_string(adev->dm.dc->ctx->dce_version)); | |
423788c7 ES |
1698 | goto error; |
1699 | } | |
4562236b | 1700 | |
8a791dab HW |
1701 | if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { |
1702 | adev->dm.dc->debug.force_single_disp_pipe_split = false; | |
1703 | adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; | |
1704 | } | |
1705 | ||
f99d8762 HW |
1706 | if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) |
1707 | adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; | |
3ce51649 AD |
1708 | if (dm_should_disable_stutter(adev->pdev)) |
1709 | adev->dm.dc->debug.disable_stutter = true; | |
f99d8762 | 1710 | |
8a791dab HW |
1711 | if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) |
1712 | adev->dm.dc->debug.disable_stutter = true; | |
1713 | ||
c82eddf8 | 1714 | if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) |
8a791dab HW |
1715 | adev->dm.dc->debug.disable_dsc = true; |
1716 | ||
1717 | if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) | |
1718 | adev->dm.dc->debug.disable_clock_gate = true; | |
1719 | ||
cfb979f7 AP |
1720 | if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) |
1721 | adev->dm.dc->debug.force_subvp_mclk_switch = true; | |
1722 | ||
792a0cdd LL |
1723 | adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; |
1724 | ||
d1bc26cb FZ |
1725 | /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ |
1726 | adev->dm.dc->debug.ignore_cable_id = true; | |
1727 | ||
3d8fcc67 WL |
1728 | /* TODO: There is a new drm mst change where the freedom of |
1729 | * vc_next_start_slot update is revoked/moved into drm, instead of in | |
1730 | * driver. This forces us to make sure to get vc_next_start_slot updated | |
1731 | * in drm function each time without considering if mst_state is active | |
1732 | * or not. Otherwise, next time hotplug will give wrong start_slot | |
1733 | * number. We are implementing a temporary solution to even notify drm | |
1734 | * mst deallocation when link is no longer of MST type when uncommitting | |
1735 | * the stream so we will have more time to work on a proper solution. | |
1736 | * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we | |
1737 | * should notify drm to do a complete "reset" of its states and stop | |
1738 | * calling further drm mst functions when link is no longer of an MST | |
1739 | * type. This could happen when we unplug an MST hubs/displays. When | |
1740 | * uncommit stream comes later after unplug, we should just reset | |
1741 | * hardware states only. | |
1742 | */ | |
1743 | adev->dm.dc->debug.temp_mst_deallocation_sequence = true; | |
1744 | ||
e3834491 FZ |
1745 | if (adev->dm.dc->caps.dp_hdmi21_pcon_support) |
1746 | DRM_INFO("DP-HDMI FRL PCON supported\n"); | |
1747 | ||
743b9786 NK |
1748 | r = dm_dmub_hw_init(adev); |
1749 | if (r) { | |
1750 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); | |
1751 | goto error; | |
1752 | } | |
1753 | ||
bb6785c1 NK |
1754 | dc_hardware_init(adev->dm.dc); |
1755 | ||
8e794421 WL |
1756 | adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); |
1757 | if (!adev->dm.hpd_rx_offload_wq) { | |
1758 | DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); | |
1759 | goto error; | |
1760 | } | |
1761 | ||
3ca001af | 1762 | if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { |
e6cd859d AD |
1763 | struct dc_phy_addr_space_config pa_config; |
1764 | ||
0b08c54b | 1765 | mmhub_read_system_context(adev, &pa_config); |
c0fb85ae | 1766 | |
0b08c54b YZ |
1767 | // Call the DC init_memory func |
1768 | dc_setup_system_context(adev->dm.dc, &pa_config); | |
1769 | } | |
c0fb85ae | 1770 | |
4562236b HW |
1771 | adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); |
1772 | if (!adev->dm.freesync_module) { | |
1773 | DRM_ERROR( | |
1774 | "amdgpu: failed to initialize freesync_module.\n"); | |
1775 | } else | |
f1ad2f5e | 1776 | DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", |
4562236b HW |
1777 | adev->dm.freesync_module); |
1778 | ||
e277adc5 LSL |
1779 | amdgpu_dm_init_color_mod(); |
1780 | ||
ea3b4242 | 1781 | if (adev->dm.dc->caps.max_links > 0) { |
09a5df6c NK |
1782 | adev->dm.vblank_control_workqueue = |
1783 | create_singlethread_workqueue("dm_vblank_control_workqueue"); | |
1784 | if (!adev->dm.vblank_control_workqueue) | |
ea3b4242 | 1785 | DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); |
ea3b4242 | 1786 | } |
ea3b4242 | 1787 | |
c08182f2 | 1788 | if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { |
e50dc171 | 1789 | adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); |
52704fca | 1790 | |
96a3b32e BL |
1791 | if (!adev->dm.hdcp_workqueue) |
1792 | DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); | |
1793 | else | |
1794 | DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); | |
52704fca | 1795 | |
96a3b32e BL |
1796 | dc_init_callbacks(adev->dm.dc, &init_params); |
1797 | } | |
11d526f1 | 1798 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
81927e28 JS |
1799 | init_completion(&adev->dm.dmub_aux_transfer_done); |
1800 | adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); | |
1801 | if (!adev->dm.dmub_notify) { | |
1802 | DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); | |
1803 | goto error; | |
1804 | } | |
e27c41d5 JS |
1805 | |
1806 | adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); | |
1807 | if (!adev->dm.delayed_hpd_wq) { | |
1808 | DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); | |
1809 | goto error; | |
1810 | } | |
1811 | ||
81927e28 | 1812 | amdgpu_dm_outbox_init(adev); |
e27c41d5 JS |
1813 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, |
1814 | dmub_aux_setconfig_callback, false)) { | |
1815 | DRM_ERROR("amdgpu: fail to register dmub aux callback"); | |
1816 | goto error; | |
1817 | } | |
1818 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) { | |
1819 | DRM_ERROR("amdgpu: fail to register dmub hpd callback"); | |
1820 | goto error; | |
1821 | } | |
c40a09e5 NK |
1822 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) { |
1823 | DRM_ERROR("amdgpu: fail to register dmub hpd callback"); | |
1824 | goto error; | |
1825 | } | |
81927e28 JS |
1826 | } |
1827 | ||
11d526f1 SW |
1828 | /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. |
1829 | * It is expected that DMUB will resend any pending notifications at this point, for | |
1830 | * example HPD from DPIA. | |
1831 | */ | |
7ce34cbf | 1832 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
11d526f1 SW |
1833 | dc_enable_dmub_outbox(adev->dm.dc); |
1834 | ||
7ce34cbf SW |
1835 | /* DPIA trace goes to dmesg logs only if outbox is enabled */ |
1836 | if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) | |
1837 | dc_dmub_srv_enable_dpia_trace(adev->dm.dc); | |
1838 | } | |
1839 | ||
1c43a48b SW |
1840 | if (amdgpu_dm_initialize_drm_device(adev)) { |
1841 | DRM_ERROR( | |
1842 | "amdgpu: failed to initialize sw for display support.\n"); | |
1843 | goto error; | |
1844 | } | |
1845 | ||
f74367e4 AD |
1846 | /* create fake encoders for MST */ |
1847 | dm_dp_create_fake_mst_encoders(adev); | |
1848 | ||
4562236b HW |
1849 | /* TODO: Add_display_info? */ |
1850 | ||
1851 | /* TODO use dynamic cursor width */ | |
4a580877 LT |
1852 | adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; |
1853 | adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; | |
4562236b | 1854 | |
4a580877 | 1855 | if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { |
4562236b HW |
1856 | DRM_ERROR( |
1857 | "amdgpu: failed to initialize sw for display support.\n"); | |
1858 | goto error; | |
1859 | } | |
1860 | ||
f477c7b5 AL |
1861 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
1862 | adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); | |
1863 | if (!adev->dm.secure_display_ctxs) | |
1864 | DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); | |
1865 | #endif | |
c0fb85ae | 1866 | |
f1ad2f5e | 1867 | DRM_DEBUG_DRIVER("KMS initialized.\n"); |
4562236b HW |
1868 | |
1869 | return 0; | |
1870 | error: | |
1871 | amdgpu_dm_fini(adev); | |
1872 | ||
59d0f396 | 1873 | return -EINVAL; |
4562236b HW |
1874 | } |
1875 | ||
e9669fb7 AG |
1876 | static int amdgpu_dm_early_fini(void *handle) |
1877 | { | |
1878 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1879 | ||
1880 | amdgpu_dm_audio_fini(adev); | |
1881 | ||
1882 | return 0; | |
1883 | } | |
1884 | ||
7578ecda | 1885 | static void amdgpu_dm_fini(struct amdgpu_device *adev) |
4562236b | 1886 | { |
f74367e4 AD |
1887 | int i; |
1888 | ||
09a5df6c NK |
1889 | if (adev->dm.vblank_control_workqueue) { |
1890 | destroy_workqueue(adev->dm.vblank_control_workqueue); | |
1891 | adev->dm.vblank_control_workqueue = NULL; | |
1892 | } | |
09a5df6c | 1893 | |
4562236b | 1894 | amdgpu_dm_destroy_drm_device(&adev->dm); |
c8bdf2b6 | 1895 | |
9a65df19 | 1896 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
1b11ff76 | 1897 | if (adev->dm.secure_display_ctxs) { |
c3d74960 | 1898 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
1b11ff76 AL |
1899 | if (adev->dm.secure_display_ctxs[i].crtc) { |
1900 | flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); | |
1901 | flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); | |
1902 | } | |
1903 | } | |
1904 | kfree(adev->dm.secure_display_ctxs); | |
1905 | adev->dm.secure_display_ctxs = NULL; | |
9a65df19 WL |
1906 | } |
1907 | #endif | |
52704fca | 1908 | if (adev->dm.hdcp_workqueue) { |
e96b1b29 | 1909 | hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); |
52704fca BL |
1910 | adev->dm.hdcp_workqueue = NULL; |
1911 | } | |
1912 | ||
1913 | if (adev->dm.dc) | |
1914 | dc_deinit_callbacks(adev->dm.dc); | |
51ba6912 | 1915 | |
52f1783f IA |
1916 | if (adev->dm.dc) |
1917 | dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); | |
9a71c7d3 | 1918 | |
81927e28 JS |
1919 | if (dc_enable_dmub_notifications(adev->dm.dc)) { |
1920 | kfree(adev->dm.dmub_notify); | |
1921 | adev->dm.dmub_notify = NULL; | |
e27c41d5 JS |
1922 | destroy_workqueue(adev->dm.delayed_hpd_wq); |
1923 | adev->dm.delayed_hpd_wq = NULL; | |
81927e28 JS |
1924 | } |
1925 | ||
743b9786 NK |
1926 | if (adev->dm.dmub_bo) |
1927 | amdgpu_bo_free_kernel(&adev->dm.dmub_bo, | |
1928 | &adev->dm.dmub_bo_gpu_addr, | |
1929 | &adev->dm.dmub_bo_cpu_addr); | |
52704fca | 1930 | |
006c26a0 AG |
1931 | if (adev->dm.hpd_rx_offload_wq) { |
1932 | for (i = 0; i < adev->dm.dc->caps.max_links; i++) { | |
1933 | if (adev->dm.hpd_rx_offload_wq[i].wq) { | |
1934 | destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); | |
1935 | adev->dm.hpd_rx_offload_wq[i].wq = NULL; | |
1936 | } | |
1937 | } | |
1938 | ||
1939 | kfree(adev->dm.hpd_rx_offload_wq); | |
1940 | adev->dm.hpd_rx_offload_wq = NULL; | |
1941 | } | |
1942 | ||
c8bdf2b6 ED |
1943 | /* DC Destroy TODO: Replace destroy DAL */ |
1944 | if (adev->dm.dc) | |
1945 | dc_destroy(&adev->dm.dc); | |
4562236b HW |
1946 | /* |
1947 | * TODO: pageflip, vlank interrupt | |
1948 | * | |
1949 | * amdgpu_dm_irq_fini(adev); | |
1950 | */ | |
1951 | ||
1952 | if (adev->dm.cgs_device) { | |
1953 | amdgpu_cgs_destroy_device(adev->dm.cgs_device); | |
1954 | adev->dm.cgs_device = NULL; | |
1955 | } | |
1956 | if (adev->dm.freesync_module) { | |
1957 | mod_freesync_destroy(adev->dm.freesync_module); | |
1958 | adev->dm.freesync_module = NULL; | |
1959 | } | |
674e78ac | 1960 | |
6ce8f316 | 1961 | mutex_destroy(&adev->dm.audio_lock); |
674e78ac | 1962 | mutex_destroy(&adev->dm.dc_lock); |
ead08b95 | 1963 | mutex_destroy(&adev->dm.dpia_aux_lock); |
4562236b HW |
1964 | } |
1965 | ||
a94d5569 | 1966 | static int load_dmcu_fw(struct amdgpu_device *adev) |
4562236b | 1967 | { |
a7669aff | 1968 | const char *fw_name_dmcu = NULL; |
a94d5569 DF |
1969 | int r; |
1970 | const struct dmcu_firmware_header_v1_0 *hdr; | |
1971 | ||
c82eddf8 | 1972 | switch (adev->asic_type) { |
55e56389 MR |
1973 | #if defined(CONFIG_DRM_AMD_DC_SI) |
1974 | case CHIP_TAHITI: | |
1975 | case CHIP_PITCAIRN: | |
1976 | case CHIP_VERDE: | |
1977 | case CHIP_OLAND: | |
1978 | #endif | |
a94d5569 DF |
1979 | case CHIP_BONAIRE: |
1980 | case CHIP_HAWAII: | |
1981 | case CHIP_KAVERI: | |
1982 | case CHIP_KABINI: | |
1983 | case CHIP_MULLINS: | |
1984 | case CHIP_TONGA: | |
1985 | case CHIP_FIJI: | |
1986 | case CHIP_CARRIZO: | |
1987 | case CHIP_STONEY: | |
1988 | case CHIP_POLARIS11: | |
1989 | case CHIP_POLARIS10: | |
1990 | case CHIP_POLARIS12: | |
1991 | case CHIP_VEGAM: | |
1992 | case CHIP_VEGA10: | |
1993 | case CHIP_VEGA12: | |
1994 | case CHIP_VEGA20: | |
1995 | return 0; | |
5ea23931 RL |
1996 | case CHIP_NAVI12: |
1997 | fw_name_dmcu = FIRMWARE_NAVI12_DMCU; | |
1998 | break; | |
a94d5569 | 1999 | case CHIP_RAVEN: |
a7669aff HW |
2000 | if (ASICREV_IS_PICASSO(adev->external_rev_id)) |
2001 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
2002 | else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) | |
2003 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
2004 | else | |
a7669aff | 2005 | return 0; |
a94d5569 DF |
2006 | break; |
2007 | default: | |
1d789535 | 2008 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
2009 | case IP_VERSION(2, 0, 2): |
2010 | case IP_VERSION(2, 0, 3): | |
2011 | case IP_VERSION(2, 0, 0): | |
2012 | case IP_VERSION(2, 1, 0): | |
2013 | case IP_VERSION(3, 0, 0): | |
2014 | case IP_VERSION(3, 0, 2): | |
2015 | case IP_VERSION(3, 0, 3): | |
2016 | case IP_VERSION(3, 0, 1): | |
2017 | case IP_VERSION(3, 1, 2): | |
2018 | case IP_VERSION(3, 1, 3): | |
f3cd57e4 | 2019 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 2020 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 2021 | case IP_VERSION(3, 1, 6): |
577359ca AP |
2022 | case IP_VERSION(3, 2, 0): |
2023 | case IP_VERSION(3, 2, 1): | |
c08182f2 AD |
2024 | return 0; |
2025 | default: | |
2026 | break; | |
2027 | } | |
a94d5569 | 2028 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); |
59d0f396 | 2029 | return -EINVAL; |
a94d5569 DF |
2030 | } |
2031 | ||
2032 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
2033 | DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); | |
2034 | return 0; | |
2035 | } | |
2036 | ||
46fa9075 ML |
2037 | r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); |
2038 | if (r == -ENODEV) { | |
a94d5569 DF |
2039 | /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ |
2040 | DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); | |
2041 | adev->dm.fw_dmcu = NULL; | |
2042 | return 0; | |
2043 | } | |
a94d5569 DF |
2044 | if (r) { |
2045 | dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", | |
2046 | fw_name_dmcu); | |
51526637 | 2047 | amdgpu_ucode_release(&adev->dm.fw_dmcu); |
a94d5569 DF |
2048 | return r; |
2049 | } | |
2050 | ||
2051 | hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; | |
2052 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; | |
2053 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; | |
2054 | adev->firmware.fw_size += | |
2055 | ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
2056 | ||
2057 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; | |
2058 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; | |
2059 | adev->firmware.fw_size += | |
2060 | ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
2061 | ||
ee6e89c0 DF |
2062 | adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); |
2063 | ||
a94d5569 DF |
2064 | DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); |
2065 | ||
4562236b HW |
2066 | return 0; |
2067 | } | |
2068 | ||
743b9786 NK |
2069 | static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) |
2070 | { | |
2071 | struct amdgpu_device *adev = ctx; | |
2072 | ||
2073 | return dm_read_reg(adev->dm.dc->ctx, address); | |
2074 | } | |
2075 | ||
2076 | static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, | |
2077 | uint32_t value) | |
2078 | { | |
2079 | struct amdgpu_device *adev = ctx; | |
2080 | ||
2081 | return dm_write_reg(adev->dm.dc->ctx, address, value); | |
2082 | } | |
2083 | ||
2084 | static int dm_dmub_sw_init(struct amdgpu_device *adev) | |
2085 | { | |
2086 | struct dmub_srv_create_params create_params; | |
8c7aea40 NK |
2087 | struct dmub_srv_region_params region_params; |
2088 | struct dmub_srv_region_info region_info; | |
2089 | struct dmub_srv_fb_params fb_params; | |
2090 | struct dmub_srv_fb_info *fb_info; | |
2091 | struct dmub_srv *dmub_srv; | |
743b9786 | 2092 | const struct dmcub_firmware_header_v1_0 *hdr; |
743b9786 NK |
2093 | enum dmub_asic dmub_asic; |
2094 | enum dmub_status status; | |
2095 | int r; | |
2096 | ||
1d789535 | 2097 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 | 2098 | case IP_VERSION(2, 1, 0): |
743b9786 | 2099 | dmub_asic = DMUB_ASIC_DCN21; |
743b9786 | 2100 | break; |
c08182f2 | 2101 | case IP_VERSION(3, 0, 0): |
35a45d63 | 2102 | dmub_asic = DMUB_ASIC_DCN30; |
79037324 | 2103 | break; |
c08182f2 | 2104 | case IP_VERSION(3, 0, 1): |
469989ca | 2105 | dmub_asic = DMUB_ASIC_DCN301; |
469989ca | 2106 | break; |
c08182f2 | 2107 | case IP_VERSION(3, 0, 2): |
2a411205 | 2108 | dmub_asic = DMUB_ASIC_DCN302; |
2a411205 | 2109 | break; |
c08182f2 | 2110 | case IP_VERSION(3, 0, 3): |
656fe9b6 | 2111 | dmub_asic = DMUB_ASIC_DCN303; |
656fe9b6 | 2112 | break; |
c08182f2 AD |
2113 | case IP_VERSION(3, 1, 2): |
2114 | case IP_VERSION(3, 1, 3): | |
3137f792 | 2115 | dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; |
1ebcaebd | 2116 | break; |
e850f6b1 RL |
2117 | case IP_VERSION(3, 1, 4): |
2118 | dmub_asic = DMUB_ASIC_DCN314; | |
e850f6b1 | 2119 | break; |
b5b8ed44 QZ |
2120 | case IP_VERSION(3, 1, 5): |
2121 | dmub_asic = DMUB_ASIC_DCN315; | |
b5b8ed44 | 2122 | break; |
de7cc1b4 | 2123 | case IP_VERSION(3, 1, 6): |
868f4357 | 2124 | dmub_asic = DMUB_ASIC_DCN316; |
de7cc1b4 | 2125 | break; |
577359ca AP |
2126 | case IP_VERSION(3, 2, 0): |
2127 | dmub_asic = DMUB_ASIC_DCN32; | |
577359ca AP |
2128 | break; |
2129 | case IP_VERSION(3, 2, 1): | |
2130 | dmub_asic = DMUB_ASIC_DCN321; | |
577359ca | 2131 | break; |
743b9786 NK |
2132 | default: |
2133 | /* ASIC doesn't support DMUB. */ | |
2134 | return 0; | |
2135 | } | |
2136 | ||
743b9786 | 2137 | hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; |
72a74a18 | 2138 | adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); |
743b9786 | 2139 | |
9a6ed547 NK |
2140 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
2141 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = | |
2142 | AMDGPU_UCODE_ID_DMCUB; | |
2143 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = | |
2144 | adev->dm.dmub_fw; | |
2145 | adev->firmware.fw_size += | |
2146 | ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); | |
743b9786 | 2147 | |
9a6ed547 NK |
2148 | DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", |
2149 | adev->dm.dmcub_fw_version); | |
2150 | } | |
2151 | ||
743b9786 | 2152 | |
8c7aea40 NK |
2153 | adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); |
2154 | dmub_srv = adev->dm.dmub_srv; | |
2155 | ||
2156 | if (!dmub_srv) { | |
2157 | DRM_ERROR("Failed to allocate DMUB service!\n"); | |
2158 | return -ENOMEM; | |
2159 | } | |
2160 | ||
2161 | memset(&create_params, 0, sizeof(create_params)); | |
2162 | create_params.user_ctx = adev; | |
2163 | create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; | |
2164 | create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; | |
2165 | create_params.asic = dmub_asic; | |
2166 | ||
2167 | /* Create the DMUB service. */ | |
2168 | status = dmub_srv_create(dmub_srv, &create_params); | |
2169 | if (status != DMUB_STATUS_OK) { | |
2170 | DRM_ERROR("Error creating DMUB service: %d\n", status); | |
2171 | return -EINVAL; | |
2172 | } | |
2173 | ||
2174 | /* Calculate the size of all the regions for the DMUB service. */ | |
2175 | memset(®ion_params, 0, sizeof(region_params)); | |
2176 | ||
2177 | region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - | |
2178 | PSP_HEADER_BYTES - PSP_FOOTER_BYTES; | |
2179 | region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); | |
2180 | region_params.vbios_size = adev->bios_size; | |
0922b899 | 2181 | region_params.fw_bss_data = region_params.bss_data_size ? |
1f0674fd NK |
2182 | adev->dm.dmub_fw->data + |
2183 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
0922b899 | 2184 | le32_to_cpu(hdr->inst_const_bytes) : NULL; |
a576b345 NK |
2185 | region_params.fw_inst_const = |
2186 | adev->dm.dmub_fw->data + | |
2187 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
2188 | PSP_HEADER_BYTES; | |
8c7aea40 NK |
2189 | |
2190 | status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, | |
2191 | ®ion_info); | |
2192 | ||
2193 | if (status != DMUB_STATUS_OK) { | |
2194 | DRM_ERROR("Error calculating DMUB region info: %d\n", status); | |
2195 | return -EINVAL; | |
2196 | } | |
2197 | ||
2198 | /* | |
2199 | * Allocate a framebuffer based on the total size of all the regions. | |
2200 | * TODO: Move this into GART. | |
2201 | */ | |
2202 | r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, | |
58ab2c08 CK |
2203 | AMDGPU_GEM_DOMAIN_VRAM | |
2204 | AMDGPU_GEM_DOMAIN_GTT, | |
2205 | &adev->dm.dmub_bo, | |
8c7aea40 NK |
2206 | &adev->dm.dmub_bo_gpu_addr, |
2207 | &adev->dm.dmub_bo_cpu_addr); | |
2208 | if (r) | |
2209 | return r; | |
2210 | ||
2211 | /* Rebase the regions on the framebuffer address. */ | |
2212 | memset(&fb_params, 0, sizeof(fb_params)); | |
2213 | fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; | |
2214 | fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; | |
2215 | fb_params.region_info = ®ion_info; | |
2216 | ||
2217 | adev->dm.dmub_fb_info = | |
2218 | kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); | |
2219 | fb_info = adev->dm.dmub_fb_info; | |
2220 | ||
2221 | if (!fb_info) { | |
2222 | DRM_ERROR( | |
2223 | "Failed to allocate framebuffer info for DMUB service!\n"); | |
2224 | return -ENOMEM; | |
2225 | } | |
2226 | ||
2227 | status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); | |
2228 | if (status != DMUB_STATUS_OK) { | |
2229 | DRM_ERROR("Error calculating DMUB FB info: %d\n", status); | |
2230 | return -EINVAL; | |
2231 | } | |
2232 | ||
743b9786 NK |
2233 | return 0; |
2234 | } | |
2235 | ||
a94d5569 DF |
2236 | static int dm_sw_init(void *handle) |
2237 | { | |
2238 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
743b9786 NK |
2239 | int r; |
2240 | ||
2241 | r = dm_dmub_sw_init(adev); | |
2242 | if (r) | |
2243 | return r; | |
a94d5569 DF |
2244 | |
2245 | return load_dmcu_fw(adev); | |
2246 | } | |
2247 | ||
4562236b HW |
2248 | static int dm_sw_fini(void *handle) |
2249 | { | |
a94d5569 DF |
2250 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2251 | ||
8c7aea40 NK |
2252 | kfree(adev->dm.dmub_fb_info); |
2253 | adev->dm.dmub_fb_info = NULL; | |
2254 | ||
743b9786 NK |
2255 | if (adev->dm.dmub_srv) { |
2256 | dmub_srv_destroy(adev->dm.dmub_srv); | |
2257 | adev->dm.dmub_srv = NULL; | |
2258 | } | |
2259 | ||
51526637 ML |
2260 | amdgpu_ucode_release(&adev->dm.dmub_fw); |
2261 | amdgpu_ucode_release(&adev->dm.fw_dmcu); | |
a94d5569 | 2262 | |
4562236b HW |
2263 | return 0; |
2264 | } | |
2265 | ||
7abcf6b5 | 2266 | static int detect_mst_link_for_all_connectors(struct drm_device *dev) |
4562236b | 2267 | { |
c84dec2f | 2268 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2269 | struct drm_connector *connector; |
f8d2d39e | 2270 | struct drm_connector_list_iter iter; |
7abcf6b5 | 2271 | int ret = 0; |
4562236b | 2272 | |
f8d2d39e LP |
2273 | drm_connector_list_iter_begin(dev, &iter); |
2274 | drm_for_each_connector_iter(connector, &iter) { | |
b349f76e | 2275 | aconnector = to_amdgpu_dm_connector(connector); |
30ec2b97 JFZ |
2276 | if (aconnector->dc_link->type == dc_connection_mst_branch && |
2277 | aconnector->mst_mgr.aux) { | |
f1ad2f5e | 2278 | DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", |
f8d2d39e LP |
2279 | aconnector, |
2280 | aconnector->base.base.id); | |
7abcf6b5 AG |
2281 | |
2282 | ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); | |
2283 | if (ret < 0) { | |
2284 | DRM_ERROR("DM_MST: Failed to start MST\n"); | |
f8d2d39e LP |
2285 | aconnector->dc_link->type = |
2286 | dc_connection_single; | |
3f6752b4 RL |
2287 | ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
2288 | aconnector->dc_link); | |
f8d2d39e | 2289 | break; |
7abcf6b5 | 2290 | } |
f8d2d39e | 2291 | } |
4562236b | 2292 | } |
f8d2d39e | 2293 | drm_connector_list_iter_end(&iter); |
4562236b | 2294 | |
7abcf6b5 AG |
2295 | return ret; |
2296 | } | |
2297 | ||
2298 | static int dm_late_init(void *handle) | |
2299 | { | |
42e67c3b | 2300 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7abcf6b5 | 2301 | |
bbf854dc DF |
2302 | struct dmcu_iram_parameters params; |
2303 | unsigned int linear_lut[16]; | |
2304 | int i; | |
17bdb4a8 | 2305 | struct dmcu *dmcu = NULL; |
bbf854dc | 2306 | |
17bdb4a8 JFZ |
2307 | dmcu = adev->dm.dc->res_pool->dmcu; |
2308 | ||
bbf854dc DF |
2309 | for (i = 0; i < 16; i++) |
2310 | linear_lut[i] = 0xFFFF * i / 15; | |
2311 | ||
2312 | params.set = 0; | |
75068994 | 2313 | params.backlight_ramping_override = false; |
bbf854dc DF |
2314 | params.backlight_ramping_start = 0xCCCC; |
2315 | params.backlight_ramping_reduction = 0xCCCCCCCC; | |
2316 | params.backlight_lut_array_size = 16; | |
2317 | params.backlight_lut_array = linear_lut; | |
2318 | ||
2ad0cdf9 AK |
2319 | /* Min backlight level after ABM reduction, Don't allow below 1% |
2320 | * 0xFFFF x 0.01 = 0x28F | |
2321 | */ | |
2322 | params.min_abm_backlight = 0x28F; | |
5cb32419 | 2323 | /* In the case where abm is implemented on dmcub, |
3335a135 UKK |
2324 | * dmcu object will be null. |
2325 | * ABM 2.4 and up are implemented on dmcub. | |
2326 | */ | |
6e568e43 JW |
2327 | if (dmcu) { |
2328 | if (!dmcu_load_iram(dmcu, params)) | |
2329 | return -EINVAL; | |
2330 | } else if (adev->dm.dc->ctx->dmub_srv) { | |
2331 | struct dc_link *edp_links[MAX_NUM_EDP]; | |
2332 | int edp_num; | |
bbf854dc | 2333 | |
7ae1dbe6 | 2334 | dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); |
6e568e43 JW |
2335 | for (i = 0; i < edp_num; i++) { |
2336 | if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) | |
2337 | return -EINVAL; | |
2338 | } | |
2339 | } | |
bbf854dc | 2340 | |
4a580877 | 2341 | return detect_mst_link_for_all_connectors(adev_to_drm(adev)); |
4562236b HW |
2342 | } |
2343 | ||
2344 | static void s3_handle_mst(struct drm_device *dev, bool suspend) | |
2345 | { | |
c84dec2f | 2346 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2347 | struct drm_connector *connector; |
f8d2d39e | 2348 | struct drm_connector_list_iter iter; |
fe7553be LP |
2349 | struct drm_dp_mst_topology_mgr *mgr; |
2350 | int ret; | |
2351 | bool need_hotplug = false; | |
4562236b | 2352 | |
f8d2d39e LP |
2353 | drm_connector_list_iter_begin(dev, &iter); |
2354 | drm_for_each_connector_iter(connector, &iter) { | |
fe7553be LP |
2355 | aconnector = to_amdgpu_dm_connector(connector); |
2356 | if (aconnector->dc_link->type != dc_connection_mst_branch || | |
f0127cb1 | 2357 | aconnector->mst_root) |
fe7553be LP |
2358 | continue; |
2359 | ||
2360 | mgr = &aconnector->mst_mgr; | |
2361 | ||
2362 | if (suspend) { | |
2363 | drm_dp_mst_topology_mgr_suspend(mgr); | |
2364 | } else { | |
1e5d4d8e RL |
2365 | /* if extended timeout is supported in hardware, |
2366 | * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer | |
2367 | * CTS 4.2.1.1 regression introduced by CTS specs requirement update. | |
2368 | */ | |
2369 | try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); | |
2370 | if (!dp_is_lttpr_present(aconnector->dc_link)) | |
2371 | try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); | |
2372 | ||
6f85f738 | 2373 | ret = drm_dp_mst_topology_mgr_resume(mgr, true); |
fe7553be | 2374 | if (ret < 0) { |
84a8b390 WL |
2375 | dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
2376 | aconnector->dc_link); | |
fe7553be LP |
2377 | need_hotplug = true; |
2378 | } | |
2379 | } | |
4562236b | 2380 | } |
f8d2d39e | 2381 | drm_connector_list_iter_end(&iter); |
fe7553be LP |
2382 | |
2383 | if (need_hotplug) | |
2384 | drm_kms_helper_hotplug_event(dev); | |
4562236b HW |
2385 | } |
2386 | ||
9340dfd3 HW |
2387 | static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) |
2388 | { | |
9340dfd3 HW |
2389 | int ret = 0; |
2390 | ||
9340dfd3 HW |
2391 | /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends |
2392 | * on window driver dc implementation. | |
2393 | * For Navi1x, clock settings of dcn watermarks are fixed. the settings | |
2394 | * should be passed to smu during boot up and resume from s3. | |
2395 | * boot up: dc calculate dcn watermark clock settings within dc_create, | |
2396 | * dcn20_resource_construct | |
2397 | * then call pplib functions below to pass the settings to smu: | |
2398 | * smu_set_watermarks_for_clock_ranges | |
2399 | * smu_set_watermarks_table | |
2400 | * navi10_set_watermarks_table | |
2401 | * smu_write_watermarks_table | |
2402 | * | |
2403 | * For Renoir, clock settings of dcn watermark are also fixed values. | |
2404 | * dc has implemented different flow for window driver: | |
2405 | * dc_hardware_init / dc_set_power_state | |
2406 | * dcn10_init_hw | |
2407 | * notify_wm_ranges | |
2408 | * set_wm_ranges | |
2409 | * -- Linux | |
2410 | * smu_set_watermarks_for_clock_ranges | |
2411 | * renoir_set_watermarks_table | |
2412 | * smu_write_watermarks_table | |
2413 | * | |
2414 | * For Linux, | |
2415 | * dc_hardware_init -> amdgpu_dm_init | |
2416 | * dc_set_power_state --> dm_resume | |
2417 | * | |
2418 | * therefore, this function apply to navi10/12/14 but not Renoir | |
2419 | * * | |
2420 | */ | |
1d789535 | 2421 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
2422 | case IP_VERSION(2, 0, 2): |
2423 | case IP_VERSION(2, 0, 0): | |
9340dfd3 HW |
2424 | break; |
2425 | default: | |
2426 | return 0; | |
2427 | } | |
2428 | ||
13f5dbd6 | 2429 | ret = amdgpu_dpm_write_watermarks_table(adev); |
e7a95eea EQ |
2430 | if (ret) { |
2431 | DRM_ERROR("Failed to update WMTABLE!\n"); | |
2432 | return ret; | |
9340dfd3 HW |
2433 | } |
2434 | ||
9340dfd3 HW |
2435 | return 0; |
2436 | } | |
2437 | ||
b8592b48 LL |
2438 | /** |
2439 | * dm_hw_init() - Initialize DC device | |
28d687ea | 2440 | * @handle: The base driver device containing the amdgpu_dm device. |
b8592b48 LL |
2441 | * |
2442 | * Initialize the &struct amdgpu_display_manager device. This involves calling | |
2443 | * the initializers of each DM component, then populating the struct with them. | |
2444 | * | |
2445 | * Although the function implies hardware initialization, both hardware and | |
2446 | * software are initialized here. Splitting them out to their relevant init | |
2447 | * hooks is a future TODO item. | |
2448 | * | |
2449 | * Some notable things that are initialized here: | |
2450 | * | |
2451 | * - Display Core, both software and hardware | |
2452 | * - DC modules that we need (freesync and color management) | |
2453 | * - DRM software states | |
2454 | * - Interrupt sources and handlers | |
2455 | * - Vblank support | |
2456 | * - Debug FS entries, if enabled | |
2457 | */ | |
4562236b HW |
2458 | static int dm_hw_init(void *handle) |
2459 | { | |
2460 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
2461 | /* Create DAL display manager */ | |
2462 | amdgpu_dm_init(adev); | |
4562236b HW |
2463 | amdgpu_dm_hpd_init(adev); |
2464 | ||
4562236b HW |
2465 | return 0; |
2466 | } | |
2467 | ||
b8592b48 LL |
2468 | /** |
2469 | * dm_hw_fini() - Teardown DC device | |
28d687ea | 2470 | * @handle: The base driver device containing the amdgpu_dm device. |
b8592b48 LL |
2471 | * |
2472 | * Teardown components within &struct amdgpu_display_manager that require | |
2473 | * cleanup. This involves cleaning up the DRM device, DC, and any modules that | |
2474 | * were loaded. Also flush IRQ workqueues and disable them. | |
2475 | */ | |
4562236b HW |
2476 | static int dm_hw_fini(void *handle) |
2477 | { | |
2478 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
2479 | ||
2480 | amdgpu_dm_hpd_fini(adev); | |
2481 | ||
2482 | amdgpu_dm_irq_fini(adev); | |
21de3396 | 2483 | amdgpu_dm_fini(adev); |
4562236b HW |
2484 | return 0; |
2485 | } | |
2486 | ||
cdaae837 | 2487 | |
cdaae837 BL |
2488 | static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, |
2489 | struct dc_state *state, bool enable) | |
2490 | { | |
2491 | enum dc_irq_source irq_source; | |
2492 | struct amdgpu_crtc *acrtc; | |
2493 | int rc = -EBUSY; | |
2494 | int i = 0; | |
2495 | ||
2496 | for (i = 0; i < state->stream_count; i++) { | |
2497 | acrtc = get_crtc_by_otg_inst( | |
2498 | adev, state->stream_status[i].primary_otg_inst); | |
2499 | ||
2500 | if (acrtc && state->stream_status[i].plane_count != 0) { | |
2501 | irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; | |
2502 | rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; | |
cdaae837 BL |
2503 | if (rc) |
2504 | DRM_WARN("Failed to %s pflip interrupts\n", | |
2505 | enable ? "enable" : "disable"); | |
2506 | ||
2507 | if (enable) { | |
cd465a67 AL |
2508 | if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) |
2509 | rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); | |
2510 | } else | |
2511 | rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); | |
cdaae837 | 2512 | |
cd465a67 AL |
2513 | if (rc) |
2514 | DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); | |
cdaae837 | 2515 | |
cd465a67 AL |
2516 | irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; |
2517 | /* During gpu-reset we disable and then enable vblank irq, so | |
2518 | * don't use amdgpu_irq_get/put() to avoid refcount change. | |
2519 | */ | |
2520 | if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) | |
2521 | DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); | |
cdaae837 BL |
2522 | } |
2523 | } | |
2524 | ||
2525 | } | |
2526 | ||
dfd84d90 | 2527 | static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) |
cdaae837 BL |
2528 | { |
2529 | struct dc_state *context = NULL; | |
2530 | enum dc_status res = DC_ERROR_UNEXPECTED; | |
2531 | int i; | |
2532 | struct dc_stream_state *del_streams[MAX_PIPES]; | |
2533 | int del_streams_count = 0; | |
2534 | ||
2535 | memset(del_streams, 0, sizeof(del_streams)); | |
2536 | ||
2537 | context = dc_create_state(dc); | |
2538 | if (context == NULL) | |
2539 | goto context_alloc_fail; | |
2540 | ||
2541 | dc_resource_state_copy_construct_current(dc, context); | |
2542 | ||
2543 | /* First remove from context all streams */ | |
2544 | for (i = 0; i < context->stream_count; i++) { | |
2545 | struct dc_stream_state *stream = context->streams[i]; | |
2546 | ||
2547 | del_streams[del_streams_count++] = stream; | |
2548 | } | |
2549 | ||
2550 | /* Remove all planes for removed streams and then remove the streams */ | |
2551 | for (i = 0; i < del_streams_count; i++) { | |
2552 | if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { | |
2553 | res = DC_FAIL_DETACH_SURFACES; | |
2554 | goto fail; | |
2555 | } | |
2556 | ||
2557 | res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); | |
2558 | if (res != DC_OK) | |
2559 | goto fail; | |
2560 | } | |
2561 | ||
b8272241 | 2562 | res = dc_commit_streams(dc, context->streams, context->stream_count); |
cdaae837 BL |
2563 | |
2564 | fail: | |
2565 | dc_release_state(context); | |
2566 | ||
2567 | context_alloc_fail: | |
2568 | return res; | |
2569 | } | |
2570 | ||
8e794421 WL |
2571 | static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) |
2572 | { | |
2573 | int i; | |
2574 | ||
2575 | if (dm->hpd_rx_offload_wq) { | |
2576 | for (i = 0; i < dm->dc->caps.max_links; i++) | |
2577 | flush_workqueue(dm->hpd_rx_offload_wq[i].wq); | |
2578 | } | |
2579 | } | |
2580 | ||
4562236b HW |
2581 | static int dm_suspend(void *handle) |
2582 | { | |
2583 | struct amdgpu_device *adev = handle; | |
2584 | struct amdgpu_display_manager *dm = &adev->dm; | |
2585 | int ret = 0; | |
4562236b | 2586 | |
53b3f8f4 | 2587 | if (amdgpu_in_reset(adev)) { |
cdaae837 | 2588 | mutex_lock(&dm->dc_lock); |
98ab5f35 | 2589 | |
98ab5f35 | 2590 | dc_allow_idle_optimizations(adev->dm.dc, false); |
98ab5f35 | 2591 | |
cdaae837 BL |
2592 | dm->cached_dc_state = dc_copy_state(dm->dc->current_state); |
2593 | ||
2594 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); | |
2595 | ||
2596 | amdgpu_dm_commit_zero_streams(dm->dc); | |
2597 | ||
2598 | amdgpu_dm_irq_suspend(adev); | |
2599 | ||
8e794421 WL |
2600 | hpd_rx_irq_work_suspend(dm); |
2601 | ||
cdaae837 BL |
2602 | return ret; |
2603 | } | |
4562236b | 2604 | |
d2f0b53b | 2605 | WARN_ON(adev->dm.cached_state); |
4a580877 | 2606 | adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); |
d2f0b53b | 2607 | |
4a580877 | 2608 | s3_handle_mst(adev_to_drm(adev), true); |
4562236b | 2609 | |
4562236b HW |
2610 | amdgpu_dm_irq_suspend(adev); |
2611 | ||
8e794421 WL |
2612 | hpd_rx_irq_work_suspend(dm); |
2613 | ||
32f5062d | 2614 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); |
4562236b | 2615 | |
1c2075d4 | 2616 | return 0; |
4562236b HW |
2617 | } |
2618 | ||
17ce8a69 | 2619 | struct amdgpu_dm_connector * |
1daf8c63 AD |
2620 | amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, |
2621 | struct drm_crtc *crtc) | |
4562236b | 2622 | { |
ae67558b | 2623 | u32 i; |
c2cea706 | 2624 | struct drm_connector_state *new_con_state; |
4562236b HW |
2625 | struct drm_connector *connector; |
2626 | struct drm_crtc *crtc_from_state; | |
2627 | ||
c2cea706 LSL |
2628 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
2629 | crtc_from_state = new_con_state->crtc; | |
4562236b HW |
2630 | |
2631 | if (crtc_from_state == crtc) | |
c84dec2f | 2632 | return to_amdgpu_dm_connector(connector); |
4562236b HW |
2633 | } |
2634 | ||
2635 | return NULL; | |
2636 | } | |
2637 | ||
fbbdadf2 BL |
2638 | static void emulated_link_detect(struct dc_link *link) |
2639 | { | |
2640 | struct dc_sink_init_data sink_init_data = { 0 }; | |
2641 | struct display_sink_capability sink_caps = { 0 }; | |
2642 | enum dc_edid_status edid_status; | |
2643 | struct dc_context *dc_ctx = link->ctx; | |
2644 | struct dc_sink *sink = NULL; | |
2645 | struct dc_sink *prev_sink = NULL; | |
2646 | ||
2647 | link->type = dc_connection_none; | |
2648 | prev_sink = link->local_sink; | |
2649 | ||
30164a16 VL |
2650 | if (prev_sink) |
2651 | dc_sink_release(prev_sink); | |
fbbdadf2 BL |
2652 | |
2653 | switch (link->connector_signal) { | |
2654 | case SIGNAL_TYPE_HDMI_TYPE_A: { | |
2655 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2656 | sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; | |
2657 | break; | |
2658 | } | |
2659 | ||
2660 | case SIGNAL_TYPE_DVI_SINGLE_LINK: { | |
2661 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2662 | sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; | |
2663 | break; | |
2664 | } | |
2665 | ||
2666 | case SIGNAL_TYPE_DVI_DUAL_LINK: { | |
2667 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2668 | sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; | |
2669 | break; | |
2670 | } | |
2671 | ||
2672 | case SIGNAL_TYPE_LVDS: { | |
2673 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2674 | sink_caps.signal = SIGNAL_TYPE_LVDS; | |
2675 | break; | |
2676 | } | |
2677 | ||
2678 | case SIGNAL_TYPE_EDP: { | |
2679 | sink_caps.transaction_type = | |
2680 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
2681 | sink_caps.signal = SIGNAL_TYPE_EDP; | |
2682 | break; | |
2683 | } | |
2684 | ||
2685 | case SIGNAL_TYPE_DISPLAY_PORT: { | |
2686 | sink_caps.transaction_type = | |
2687 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
2688 | sink_caps.signal = SIGNAL_TYPE_VIRTUAL; | |
2689 | break; | |
2690 | } | |
2691 | ||
2692 | default: | |
2693 | DC_ERROR("Invalid connector type! signal:%d\n", | |
2694 | link->connector_signal); | |
2695 | return; | |
2696 | } | |
2697 | ||
2698 | sink_init_data.link = link; | |
2699 | sink_init_data.sink_signal = sink_caps.signal; | |
2700 | ||
2701 | sink = dc_sink_create(&sink_init_data); | |
2702 | if (!sink) { | |
2703 | DC_ERROR("Failed to create sink!\n"); | |
2704 | return; | |
2705 | } | |
2706 | ||
dcd5fb82 | 2707 | /* dc_sink_create returns a new reference */ |
fbbdadf2 BL |
2708 | link->local_sink = sink; |
2709 | ||
2710 | edid_status = dm_helpers_read_local_edid( | |
2711 | link->ctx, | |
2712 | link, | |
2713 | sink); | |
2714 | ||
2715 | if (edid_status != EDID_OK) | |
2716 | DC_ERROR("Failed to read EDID"); | |
2717 | ||
2718 | } | |
2719 | ||
cdaae837 BL |
2720 | static void dm_gpureset_commit_state(struct dc_state *dc_state, |
2721 | struct amdgpu_display_manager *dm) | |
2722 | { | |
2723 | struct { | |
2724 | struct dc_surface_update surface_updates[MAX_SURFACES]; | |
2725 | struct dc_plane_info plane_infos[MAX_SURFACES]; | |
2726 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; | |
2727 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; | |
2728 | struct dc_stream_update stream_update; | |
c82eddf8 | 2729 | } *bundle; |
cdaae837 BL |
2730 | int k, m; |
2731 | ||
2732 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); | |
2733 | ||
2734 | if (!bundle) { | |
2735 | dm_error("Failed to allocate update bundle\n"); | |
2736 | goto cleanup; | |
2737 | } | |
2738 | ||
2739 | for (k = 0; k < dc_state->stream_count; k++) { | |
2740 | bundle->stream_update.stream = dc_state->streams[k]; | |
2741 | ||
2742 | for (m = 0; m < dc_state->stream_status->plane_count; m++) { | |
2743 | bundle->surface_updates[m].surface = | |
2744 | dc_state->stream_status->plane_states[m]; | |
2745 | bundle->surface_updates[m].surface->force_full_update = | |
2746 | true; | |
2747 | } | |
f7511289 | 2748 | |
81f743a0 RS |
2749 | update_planes_and_stream_adapter(dm->dc, |
2750 | UPDATE_TYPE_FULL, | |
2751 | dc_state->stream_status->plane_count, | |
2752 | dc_state->streams[k], | |
2753 | &bundle->stream_update, | |
2754 | bundle->surface_updates); | |
cdaae837 BL |
2755 | } |
2756 | ||
2757 | cleanup: | |
2758 | kfree(bundle); | |
cdaae837 BL |
2759 | } |
2760 | ||
4562236b HW |
2761 | static int dm_resume(void *handle) |
2762 | { | |
2763 | struct amdgpu_device *adev = handle; | |
4a580877 | 2764 | struct drm_device *ddev = adev_to_drm(adev); |
4562236b | 2765 | struct amdgpu_display_manager *dm = &adev->dm; |
c84dec2f | 2766 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2767 | struct drm_connector *connector; |
f8d2d39e | 2768 | struct drm_connector_list_iter iter; |
4562236b | 2769 | struct drm_crtc *crtc; |
c2cea706 | 2770 | struct drm_crtc_state *new_crtc_state; |
fcb4019e LSL |
2771 | struct dm_crtc_state *dm_new_crtc_state; |
2772 | struct drm_plane *plane; | |
2773 | struct drm_plane_state *new_plane_state; | |
2774 | struct dm_plane_state *dm_new_plane_state; | |
113b7a01 | 2775 | struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); |
fbbdadf2 | 2776 | enum dc_connection_type new_connection_type = dc_connection_none; |
cdaae837 BL |
2777 | struct dc_state *dc_state; |
2778 | int i, r, j; | |
4562236b | 2779 | |
53b3f8f4 | 2780 | if (amdgpu_in_reset(adev)) { |
cdaae837 BL |
2781 | dc_state = dm->cached_dc_state; |
2782 | ||
6d63fcc2 NK |
2783 | /* |
2784 | * The dc->current_state is backed up into dm->cached_dc_state | |
2785 | * before we commit 0 streams. | |
2786 | * | |
2787 | * DC will clear link encoder assignments on the real state | |
2788 | * but the changes won't propagate over to the copy we made | |
2789 | * before the 0 streams commit. | |
2790 | * | |
2791 | * DC expects that link encoder assignments are *not* valid | |
32685b32 NK |
2792 | * when committing a state, so as a workaround we can copy |
2793 | * off of the current state. | |
2794 | * | |
2795 | * We lose the previous assignments, but we had already | |
2796 | * commit 0 streams anyway. | |
6d63fcc2 | 2797 | */ |
32685b32 | 2798 | link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); |
6d63fcc2 | 2799 | |
cdaae837 BL |
2800 | r = dm_dmub_hw_init(adev); |
2801 | if (r) | |
2802 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); | |
2803 | ||
2804 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); | |
2805 | dc_resume(dm->dc); | |
2806 | ||
2807 | amdgpu_dm_irq_resume_early(adev); | |
2808 | ||
2809 | for (i = 0; i < dc_state->stream_count; i++) { | |
2810 | dc_state->streams[i]->mode_changed = true; | |
6984fa41 NK |
2811 | for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { |
2812 | dc_state->stream_status[i].plane_states[j]->update_flags.raw | |
cdaae837 BL |
2813 | = 0xffffffff; |
2814 | } | |
2815 | } | |
2816 | ||
11d526f1 SW |
2817 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
2818 | amdgpu_dm_outbox_init(adev); | |
2819 | dc_enable_dmub_outbox(adev->dm.dc); | |
2820 | } | |
2821 | ||
b8272241 | 2822 | WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); |
4562236b | 2823 | |
cdaae837 BL |
2824 | dm_gpureset_commit_state(dm->cached_dc_state, dm); |
2825 | ||
2826 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); | |
2827 | ||
2828 | dc_release_state(dm->cached_dc_state); | |
2829 | dm->cached_dc_state = NULL; | |
2830 | ||
2831 | amdgpu_dm_irq_resume_late(adev); | |
2832 | ||
2833 | mutex_unlock(&dm->dc_lock); | |
2834 | ||
2835 | return 0; | |
2836 | } | |
113b7a01 LL |
2837 | /* Recreate dc_state - DC invalidates it when setting power state to S3. */ |
2838 | dc_release_state(dm_state->context); | |
2839 | dm_state->context = dc_create_state(dm->dc); | |
2840 | /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ | |
2841 | dc_resource_state_construct(dm->dc, dm_state->context); | |
2842 | ||
8c7aea40 | 2843 | /* Before powering on DC we need to re-initialize DMUB. */ |
79d6b935 | 2844 | dm_dmub_hw_resume(adev); |
8c7aea40 | 2845 | |
11d526f1 SW |
2846 | /* Re-enable outbox interrupts for DPIA. */ |
2847 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { | |
2848 | amdgpu_dm_outbox_init(adev); | |
2849 | dc_enable_dmub_outbox(adev->dm.dc); | |
2850 | } | |
2851 | ||
a80aa93d ML |
2852 | /* power on hardware */ |
2853 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); | |
2854 | ||
4562236b HW |
2855 | /* program HPD filter */ |
2856 | dc_resume(dm->dc); | |
2857 | ||
4562236b HW |
2858 | /* |
2859 | * early enable HPD Rx IRQ, should be done before set mode as short | |
2860 | * pulse interrupts are used for MST | |
2861 | */ | |
2862 | amdgpu_dm_irq_resume_early(adev); | |
2863 | ||
d20ebea8 | 2864 | /* On resume we need to rewrite the MSTM control bits to enable MST*/ |
684cd480 LP |
2865 | s3_handle_mst(ddev, false); |
2866 | ||
4562236b | 2867 | /* Do detection*/ |
f8d2d39e LP |
2868 | drm_connector_list_iter_begin(ddev, &iter); |
2869 | drm_for_each_connector_iter(connector, &iter) { | |
c84dec2f | 2870 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b | 2871 | |
7a7175a2 RL |
2872 | if (!aconnector->dc_link) |
2873 | continue; | |
2874 | ||
4562236b HW |
2875 | /* |
2876 | * this is the case when traversing through already created | |
2877 | * MST connectors, should be skipped | |
2878 | */ | |
91b38ca1 | 2879 | if (aconnector && aconnector->mst_root) |
4562236b HW |
2880 | continue; |
2881 | ||
03ea364c | 2882 | mutex_lock(&aconnector->hpd_lock); |
54618888 | 2883 | if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) |
fbbdadf2 BL |
2884 | DRM_ERROR("KMS: Failed to detect connector\n"); |
2885 | ||
15c735e7 | 2886 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
fbbdadf2 | 2887 | emulated_link_detect(aconnector->dc_link); |
15c735e7 WL |
2888 | } else { |
2889 | mutex_lock(&dm->dc_lock); | |
fbbdadf2 | 2890 | dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); |
15c735e7 WL |
2891 | mutex_unlock(&dm->dc_lock); |
2892 | } | |
3eb4eba4 RL |
2893 | |
2894 | if (aconnector->fake_enable && aconnector->dc_link->local_sink) | |
2895 | aconnector->fake_enable = false; | |
2896 | ||
dcd5fb82 MF |
2897 | if (aconnector->dc_sink) |
2898 | dc_sink_release(aconnector->dc_sink); | |
4562236b HW |
2899 | aconnector->dc_sink = NULL; |
2900 | amdgpu_dm_update_connector_after_detect(aconnector); | |
03ea364c | 2901 | mutex_unlock(&aconnector->hpd_lock); |
4562236b | 2902 | } |
f8d2d39e | 2903 | drm_connector_list_iter_end(&iter); |
4562236b | 2904 | |
1f6010a9 | 2905 | /* Force mode set in atomic commit */ |
a80aa93d | 2906 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) |
c2cea706 | 2907 | new_crtc_state->active_changed = true; |
4f346e65 | 2908 | |
fcb4019e LSL |
2909 | /* |
2910 | * atomic_check is expected to create the dc states. We need to release | |
2911 | * them here, since they were duplicated as part of the suspend | |
2912 | * procedure. | |
2913 | */ | |
a80aa93d | 2914 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { |
fcb4019e LSL |
2915 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
2916 | if (dm_new_crtc_state->stream) { | |
2917 | WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); | |
2918 | dc_stream_release(dm_new_crtc_state->stream); | |
2919 | dm_new_crtc_state->stream = NULL; | |
2920 | } | |
2921 | } | |
2922 | ||
a80aa93d | 2923 | for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { |
fcb4019e LSL |
2924 | dm_new_plane_state = to_dm_plane_state(new_plane_state); |
2925 | if (dm_new_plane_state->dc_state) { | |
2926 | WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); | |
2927 | dc_plane_state_release(dm_new_plane_state->dc_state); | |
2928 | dm_new_plane_state->dc_state = NULL; | |
2929 | } | |
2930 | } | |
2931 | ||
2d1af6a1 | 2932 | drm_atomic_helper_resume(ddev, dm->cached_state); |
4562236b | 2933 | |
a80aa93d | 2934 | dm->cached_state = NULL; |
0a214e2f | 2935 | |
9faa4237 | 2936 | amdgpu_dm_irq_resume_late(adev); |
4562236b | 2937 | |
9340dfd3 HW |
2938 | amdgpu_dm_smu_write_watermarks_table(adev); |
2939 | ||
2d1af6a1 | 2940 | return 0; |
4562236b HW |
2941 | } |
2942 | ||
b8592b48 LL |
2943 | /** |
2944 | * DOC: DM Lifecycle | |
2945 | * | |
2946 | * DM (and consequently DC) is registered in the amdgpu base driver as a IP | |
2947 | * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to | |
2948 | * the base driver's device list to be initialized and torn down accordingly. | |
2949 | * | |
2950 | * The functions to do so are provided as hooks in &struct amd_ip_funcs. | |
2951 | */ | |
2952 | ||
4562236b HW |
2953 | static const struct amd_ip_funcs amdgpu_dm_funcs = { |
2954 | .name = "dm", | |
2955 | .early_init = dm_early_init, | |
7abcf6b5 | 2956 | .late_init = dm_late_init, |
4562236b HW |
2957 | .sw_init = dm_sw_init, |
2958 | .sw_fini = dm_sw_fini, | |
e9669fb7 | 2959 | .early_fini = amdgpu_dm_early_fini, |
4562236b HW |
2960 | .hw_init = dm_hw_init, |
2961 | .hw_fini = dm_hw_fini, | |
2962 | .suspend = dm_suspend, | |
2963 | .resume = dm_resume, | |
2964 | .is_idle = dm_is_idle, | |
2965 | .wait_for_idle = dm_wait_for_idle, | |
2966 | .check_soft_reset = dm_check_soft_reset, | |
2967 | .soft_reset = dm_soft_reset, | |
2968 | .set_clockgating_state = dm_set_clockgating_state, | |
2969 | .set_powergating_state = dm_set_powergating_state, | |
2970 | }; | |
2971 | ||
c82eddf8 | 2972 | const struct amdgpu_ip_block_version dm_ip_block = { |
4562236b HW |
2973 | .type = AMD_IP_BLOCK_TYPE_DCE, |
2974 | .major = 1, | |
2975 | .minor = 0, | |
2976 | .rev = 0, | |
2977 | .funcs = &amdgpu_dm_funcs, | |
2978 | }; | |
2979 | ||
ca3268c4 | 2980 | |
b8592b48 LL |
2981 | /** |
2982 | * DOC: atomic | |
2983 | * | |
2984 | * *WIP* | |
2985 | */ | |
0a323b84 | 2986 | |
b3663f70 | 2987 | static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { |
4d4772f6 | 2988 | .fb_create = amdgpu_display_user_framebuffer_create, |
8bf0d9cd | 2989 | .get_format_info = amdgpu_dm_plane_get_format_info, |
4562236b | 2990 | .atomic_check = amdgpu_dm_atomic_check, |
0269764a | 2991 | .atomic_commit = drm_atomic_helper_commit, |
54f5499a AG |
2992 | }; |
2993 | ||
2994 | static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { | |
a5c2c0d1 LP |
2995 | .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, |
2996 | .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, | |
4562236b HW |
2997 | }; |
2998 | ||
94562810 RS |
2999 | static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) |
3000 | { | |
94562810 | 3001 | struct amdgpu_dm_backlight_caps *caps; |
94562810 RS |
3002 | struct drm_connector *conn_base; |
3003 | struct amdgpu_device *adev; | |
a61bb342 | 3004 | struct drm_luminance_range_info *luminance_range; |
94562810 | 3005 | |
f196198c HG |
3006 | if (aconnector->bl_idx == -1 || |
3007 | aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) | |
ec11fe37 | 3008 | return; |
3009 | ||
94562810 | 3010 | conn_base = &aconnector->base; |
1348969a | 3011 | adev = drm_to_adev(conn_base->dev); |
f196198c HG |
3012 | |
3013 | caps = &adev->dm.backlight_caps[aconnector->bl_idx]; | |
94562810 RS |
3014 | caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; |
3015 | caps->aux_support = false; | |
94562810 | 3016 | |
c82eddf8 SS |
3017 | if (caps->ext_caps->bits.oled == 1 |
3018 | /* | |
3019 | * || | |
3020 | * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || | |
3021 | * caps->ext_caps->bits.hdr_aux_backlight_control == 1 | |
3022 | */) | |
94562810 RS |
3023 | caps->aux_support = true; |
3024 | ||
7a46f05e TI |
3025 | if (amdgpu_backlight == 0) |
3026 | caps->aux_support = false; | |
3027 | else if (amdgpu_backlight == 1) | |
3028 | caps->aux_support = true; | |
3029 | ||
a61bb342 | 3030 | luminance_range = &conn_base->display_info.luminance_range; |
932698c8 SP |
3031 | |
3032 | if (luminance_range->max_luminance) { | |
3033 | caps->aux_min_input_signal = luminance_range->min_luminance; | |
3034 | caps->aux_max_input_signal = luminance_range->max_luminance; | |
3035 | } else { | |
3036 | caps->aux_min_input_signal = 0; | |
3037 | caps->aux_max_input_signal = 512; | |
3038 | } | |
94562810 RS |
3039 | } |
3040 | ||
97e51c16 HW |
3041 | void amdgpu_dm_update_connector_after_detect( |
3042 | struct amdgpu_dm_connector *aconnector) | |
4562236b HW |
3043 | { |
3044 | struct drm_connector *connector = &aconnector->base; | |
3045 | struct drm_device *dev = connector->dev; | |
b73a22d3 | 3046 | struct dc_sink *sink; |
4562236b HW |
3047 | |
3048 | /* MST handled by drm_mst framework */ | |
3049 | if (aconnector->mst_mgr.mst_state == true) | |
3050 | return; | |
3051 | ||
4562236b | 3052 | sink = aconnector->dc_link->local_sink; |
dcd5fb82 MF |
3053 | if (sink) |
3054 | dc_sink_retain(sink); | |
4562236b | 3055 | |
1f6010a9 DF |
3056 | /* |
3057 | * Edid mgmt connector gets first update only in mode_valid hook and then | |
4562236b | 3058 | * the connector sink is set to either fake or physical sink depends on link status. |
1f6010a9 | 3059 | * Skip if already done during boot. |
4562236b HW |
3060 | */ |
3061 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED | |
3062 | && aconnector->dc_em_sink) { | |
3063 | ||
1f6010a9 DF |
3064 | /* |
3065 | * For S3 resume with headless use eml_sink to fake stream | |
3066 | * because on resume connector->sink is set to NULL | |
4562236b HW |
3067 | */ |
3068 | mutex_lock(&dev->mode_config.mutex); | |
3069 | ||
3070 | if (sink) { | |
922aa1e1 | 3071 | if (aconnector->dc_sink) { |
98e6436d | 3072 | amdgpu_dm_update_freesync_caps(connector, NULL); |
1f6010a9 DF |
3073 | /* |
3074 | * retain and release below are used to | |
3075 | * bump up refcount for sink because the link doesn't point | |
3076 | * to it anymore after disconnect, so on next crtc to connector | |
922aa1e1 AG |
3077 | * reshuffle by UMD we will get into unwanted dc_sink release |
3078 | */ | |
dcd5fb82 | 3079 | dc_sink_release(aconnector->dc_sink); |
922aa1e1 | 3080 | } |
4562236b | 3081 | aconnector->dc_sink = sink; |
dcd5fb82 | 3082 | dc_sink_retain(aconnector->dc_sink); |
98e6436d AK |
3083 | amdgpu_dm_update_freesync_caps(connector, |
3084 | aconnector->edid); | |
4562236b | 3085 | } else { |
98e6436d | 3086 | amdgpu_dm_update_freesync_caps(connector, NULL); |
dcd5fb82 | 3087 | if (!aconnector->dc_sink) { |
4562236b | 3088 | aconnector->dc_sink = aconnector->dc_em_sink; |
922aa1e1 | 3089 | dc_sink_retain(aconnector->dc_sink); |
dcd5fb82 | 3090 | } |
4562236b HW |
3091 | } |
3092 | ||
3093 | mutex_unlock(&dev->mode_config.mutex); | |
dcd5fb82 MF |
3094 | |
3095 | if (sink) | |
3096 | dc_sink_release(sink); | |
4562236b HW |
3097 | return; |
3098 | } | |
3099 | ||
3100 | /* | |
3101 | * TODO: temporary guard to look for proper fix | |
3102 | * if this sink is MST sink, we should not do anything | |
3103 | */ | |
dcd5fb82 MF |
3104 | if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { |
3105 | dc_sink_release(sink); | |
4562236b | 3106 | return; |
dcd5fb82 | 3107 | } |
4562236b HW |
3108 | |
3109 | if (aconnector->dc_sink == sink) { | |
1f6010a9 DF |
3110 | /* |
3111 | * We got a DP short pulse (Link Loss, DP CTS, etc...). | |
3112 | * Do nothing!! | |
3113 | */ | |
f1ad2f5e | 3114 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", |
4562236b | 3115 | aconnector->connector_id); |
dcd5fb82 MF |
3116 | if (sink) |
3117 | dc_sink_release(sink); | |
4562236b HW |
3118 | return; |
3119 | } | |
3120 | ||
f1ad2f5e | 3121 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", |
4562236b HW |
3122 | aconnector->connector_id, aconnector->dc_sink, sink); |
3123 | ||
3124 | mutex_lock(&dev->mode_config.mutex); | |
3125 | ||
1f6010a9 DF |
3126 | /* |
3127 | * 1. Update status of the drm connector | |
3128 | * 2. Send an event and let userspace tell us what to do | |
3129 | */ | |
4562236b | 3130 | if (sink) { |
1f6010a9 DF |
3131 | /* |
3132 | * TODO: check if we still need the S3 mode update workaround. | |
3133 | * If yes, put it here. | |
3134 | */ | |
c64b0d6b | 3135 | if (aconnector->dc_sink) { |
98e6436d | 3136 | amdgpu_dm_update_freesync_caps(connector, NULL); |
c64b0d6b VL |
3137 | dc_sink_release(aconnector->dc_sink); |
3138 | } | |
4562236b HW |
3139 | |
3140 | aconnector->dc_sink = sink; | |
dcd5fb82 | 3141 | dc_sink_retain(aconnector->dc_sink); |
900b3cb1 | 3142 | if (sink->dc_edid.length == 0) { |
4562236b | 3143 | aconnector->edid = NULL; |
e6142dd5 AP |
3144 | if (aconnector->dc_link->aux_mode) { |
3145 | drm_dp_cec_unset_edid( | |
3146 | &aconnector->dm_dp_aux.aux); | |
3147 | } | |
900b3cb1 | 3148 | } else { |
4562236b | 3149 | aconnector->edid = |
e6142dd5 | 3150 | (struct edid *)sink->dc_edid.raw_edid; |
4562236b | 3151 | |
e6142dd5 AP |
3152 | if (aconnector->dc_link->aux_mode) |
3153 | drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, | |
3154 | aconnector->edid); | |
4562236b | 3155 | } |
e6142dd5 | 3156 | |
025ce392 HW |
3157 | if (!aconnector->timing_requested) { |
3158 | aconnector->timing_requested = | |
3159 | kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); | |
3160 | if (!aconnector->timing_requested) | |
3161 | dm_error("failed to create aconnector->requested_timing\n"); | |
3162 | } | |
028c4ccf | 3163 | |
20543be9 | 3164 | drm_connector_update_edid_property(connector, aconnector->edid); |
98e6436d | 3165 | amdgpu_dm_update_freesync_caps(connector, aconnector->edid); |
94562810 | 3166 | update_connector_ext_caps(aconnector); |
4562236b | 3167 | } else { |
e86e8947 | 3168 | drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); |
98e6436d | 3169 | amdgpu_dm_update_freesync_caps(connector, NULL); |
c555f023 | 3170 | drm_connector_update_edid_property(connector, NULL); |
4562236b | 3171 | aconnector->num_modes = 0; |
dcd5fb82 | 3172 | dc_sink_release(aconnector->dc_sink); |
4562236b | 3173 | aconnector->dc_sink = NULL; |
5326c452 | 3174 | aconnector->edid = NULL; |
028c4ccf QZ |
3175 | kfree(aconnector->timing_requested); |
3176 | aconnector->timing_requested = NULL; | |
0c8620d6 BL |
3177 | /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ |
3178 | if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) | |
3179 | connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
4562236b HW |
3180 | } |
3181 | ||
3182 | mutex_unlock(&dev->mode_config.mutex); | |
dcd5fb82 | 3183 | |
0f877894 OV |
3184 | update_subconnector_property(aconnector); |
3185 | ||
dcd5fb82 MF |
3186 | if (sink) |
3187 | dc_sink_release(sink); | |
4562236b HW |
3188 | } |
3189 | ||
e27c41d5 | 3190 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) |
4562236b | 3191 | { |
4562236b HW |
3192 | struct drm_connector *connector = &aconnector->base; |
3193 | struct drm_device *dev = connector->dev; | |
fbbdadf2 | 3194 | enum dc_connection_type new_connection_type = dc_connection_none; |
1348969a | 3195 | struct amdgpu_device *adev = drm_to_adev(dev); |
97f6c917 | 3196 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); |
15c735e7 | 3197 | bool ret = false; |
4562236b | 3198 | |
b972b4f9 HW |
3199 | if (adev->dm.disable_hpd_irq) |
3200 | return; | |
3201 | ||
1f6010a9 DF |
3202 | /* |
3203 | * In case of failure or MST no need to update connector status or notify the OS | |
3204 | * since (for MST case) MST does this in its own context. | |
4562236b HW |
3205 | */ |
3206 | mutex_lock(&aconnector->hpd_lock); | |
2e0ac3d6 | 3207 | |
97f6c917 | 3208 | if (adev->dm.hdcp_workqueue) { |
96a3b32e | 3209 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); |
97f6c917 BL |
3210 | dm_con_state->update_hdcp = true; |
3211 | } | |
2e0ac3d6 HW |
3212 | if (aconnector->fake_enable) |
3213 | aconnector->fake_enable = false; | |
3214 | ||
028c4ccf QZ |
3215 | aconnector->timing_changed = false; |
3216 | ||
54618888 | 3217 | if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) |
fbbdadf2 BL |
3218 | DRM_ERROR("KMS: Failed to detect connector\n"); |
3219 | ||
3220 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
3221 | emulated_link_detect(aconnector->dc_link); | |
3222 | ||
fbbdadf2 BL |
3223 | drm_modeset_lock_all(dev); |
3224 | dm_restore_drm_connector_state(dev, connector); | |
3225 | drm_modeset_unlock_all(dev); | |
3226 | ||
3227 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) | |
fc320a6f | 3228 | drm_kms_helper_connector_hotplug_event(connector); |
15c735e7 WL |
3229 | } else { |
3230 | mutex_lock(&adev->dm.dc_lock); | |
3231 | ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); | |
3232 | mutex_unlock(&adev->dm.dc_lock); | |
3233 | if (ret) { | |
3234 | amdgpu_dm_update_connector_after_detect(aconnector); | |
fbbdadf2 | 3235 | |
15c735e7 WL |
3236 | drm_modeset_lock_all(dev); |
3237 | dm_restore_drm_connector_state(dev, connector); | |
3238 | drm_modeset_unlock_all(dev); | |
4562236b | 3239 | |
15c735e7 WL |
3240 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) |
3241 | drm_kms_helper_connector_hotplug_event(connector); | |
3242 | } | |
4562236b HW |
3243 | } |
3244 | mutex_unlock(&aconnector->hpd_lock); | |
3245 | ||
3246 | } | |
3247 | ||
e27c41d5 JS |
3248 | static void handle_hpd_irq(void *param) |
3249 | { | |
3250 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; | |
3251 | ||
3252 | handle_hpd_irq_helper(aconnector); | |
3253 | ||
3254 | } | |
3255 | ||
8e794421 WL |
3256 | static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, |
3257 | union hpd_irq_data hpd_irq_data) | |
3258 | { | |
3259 | struct hpd_rx_irq_offload_work *offload_work = | |
3260 | kzalloc(sizeof(*offload_work), GFP_KERNEL); | |
3261 | ||
3262 | if (!offload_work) { | |
3263 | DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); | |
3264 | return; | |
3265 | } | |
3266 | ||
3267 | INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); | |
3268 | offload_work->data = hpd_irq_data; | |
3269 | offload_work->offload_wq = offload_wq; | |
3270 | ||
3271 | queue_work(offload_wq->wq, &offload_work->work); | |
3272 | DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); | |
3273 | } | |
3274 | ||
4562236b HW |
3275 | static void handle_hpd_rx_irq(void *param) |
3276 | { | |
c84dec2f | 3277 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
4562236b HW |
3278 | struct drm_connector *connector = &aconnector->base; |
3279 | struct drm_device *dev = connector->dev; | |
53cbf65c | 3280 | struct dc_link *dc_link = aconnector->dc_link; |
4562236b | 3281 | bool is_mst_root_connector = aconnector->mst_mgr.mst_state; |
c8ea79a8 | 3282 | bool result = false; |
fbbdadf2 | 3283 | enum dc_connection_type new_connection_type = dc_connection_none; |
c8ea79a8 | 3284 | struct amdgpu_device *adev = drm_to_adev(dev); |
2a0f9270 | 3285 | union hpd_irq_data hpd_irq_data; |
8e794421 WL |
3286 | bool link_loss = false; |
3287 | bool has_left_work = false; | |
e322843e | 3288 | int idx = dc_link->link_index; |
8e794421 | 3289 | struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; |
2a0f9270 BL |
3290 | |
3291 | memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); | |
4562236b | 3292 | |
b972b4f9 HW |
3293 | if (adev->dm.disable_hpd_irq) |
3294 | return; | |
3295 | ||
1f6010a9 DF |
3296 | /* |
3297 | * TODO:Temporary add mutex to protect hpd interrupt not have a gpio | |
4562236b HW |
3298 | * conflict, after implement i2c helper, this mutex should be |
3299 | * retired. | |
3300 | */ | |
b86e7eef | 3301 | mutex_lock(&aconnector->hpd_lock); |
4562236b | 3302 | |
8e794421 WL |
3303 | result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, |
3304 | &link_loss, true, &has_left_work); | |
3083a984 | 3305 | |
8e794421 WL |
3306 | if (!has_left_work) |
3307 | goto out; | |
3308 | ||
3309 | if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { | |
3310 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); | |
3311 | goto out; | |
3312 | } | |
3313 | ||
3314 | if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { | |
3315 | if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || | |
3316 | hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { | |
bb4fa525 WL |
3317 | bool skip = false; |
3318 | ||
3319 | /* | |
3320 | * DOWN_REP_MSG_RDY is also handled by polling method | |
3321 | * mgr->cbs->poll_hpd_irq() | |
3322 | */ | |
3323 | spin_lock(&offload_wq->offload_lock); | |
3324 | skip = offload_wq->is_handling_mst_msg_rdy_event; | |
3325 | ||
3326 | if (!skip) | |
3327 | offload_wq->is_handling_mst_msg_rdy_event = true; | |
3328 | ||
3329 | spin_unlock(&offload_wq->offload_lock); | |
3330 | ||
3331 | if (!skip) | |
3332 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); | |
3333 | ||
3083a984 QZ |
3334 | goto out; |
3335 | } | |
3083a984 | 3336 | |
8e794421 WL |
3337 | if (link_loss) { |
3338 | bool skip = false; | |
d2aa1356 | 3339 | |
8e794421 WL |
3340 | spin_lock(&offload_wq->offload_lock); |
3341 | skip = offload_wq->is_handling_link_loss; | |
3342 | ||
3343 | if (!skip) | |
3344 | offload_wq->is_handling_link_loss = true; | |
3345 | ||
3346 | spin_unlock(&offload_wq->offload_lock); | |
3347 | ||
3348 | if (!skip) | |
3349 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); | |
3350 | ||
3351 | goto out; | |
3352 | } | |
3353 | } | |
c8ea79a8 | 3354 | |
3083a984 | 3355 | out: |
c8ea79a8 | 3356 | if (result && !is_mst_root_connector) { |
4562236b | 3357 | /* Downstream Port status changed. */ |
54618888 | 3358 | if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) |
fbbdadf2 BL |
3359 | DRM_ERROR("KMS: Failed to detect connector\n"); |
3360 | ||
3361 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
3362 | emulated_link_detect(dc_link); | |
3363 | ||
3364 | if (aconnector->fake_enable) | |
3365 | aconnector->fake_enable = false; | |
3366 | ||
3367 | amdgpu_dm_update_connector_after_detect(aconnector); | |
3368 | ||
3369 | ||
3370 | drm_modeset_lock_all(dev); | |
3371 | dm_restore_drm_connector_state(dev, connector); | |
3372 | drm_modeset_unlock_all(dev); | |
3373 | ||
fc320a6f | 3374 | drm_kms_helper_connector_hotplug_event(connector); |
15c735e7 WL |
3375 | } else { |
3376 | bool ret = false; | |
88ac3dda | 3377 | |
15c735e7 WL |
3378 | mutex_lock(&adev->dm.dc_lock); |
3379 | ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); | |
3380 | mutex_unlock(&adev->dm.dc_lock); | |
88ac3dda | 3381 | |
15c735e7 WL |
3382 | if (ret) { |
3383 | if (aconnector->fake_enable) | |
3384 | aconnector->fake_enable = false; | |
4562236b | 3385 | |
15c735e7 | 3386 | amdgpu_dm_update_connector_after_detect(aconnector); |
4562236b | 3387 | |
15c735e7 WL |
3388 | drm_modeset_lock_all(dev); |
3389 | dm_restore_drm_connector_state(dev, connector); | |
3390 | drm_modeset_unlock_all(dev); | |
4562236b | 3391 | |
15c735e7 WL |
3392 | drm_kms_helper_connector_hotplug_event(connector); |
3393 | } | |
4562236b HW |
3394 | } |
3395 | } | |
95f247e7 DC |
3396 | if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { |
3397 | if (adev->dm.hdcp_workqueue) | |
3398 | hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); | |
3399 | } | |
4562236b | 3400 | |
b86e7eef | 3401 | if (dc_link->type != dc_connection_mst_branch) |
e86e8947 | 3402 | drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); |
b86e7eef NC |
3403 | |
3404 | mutex_unlock(&aconnector->hpd_lock); | |
4562236b HW |
3405 | } |
3406 | ||
3407 | static void register_hpd_handlers(struct amdgpu_device *adev) | |
3408 | { | |
4a580877 | 3409 | struct drm_device *dev = adev_to_drm(adev); |
4562236b | 3410 | struct drm_connector *connector; |
c84dec2f | 3411 | struct amdgpu_dm_connector *aconnector; |
4562236b HW |
3412 | const struct dc_link *dc_link; |
3413 | struct dc_interrupt_params int_params = {0}; | |
3414 | ||
3415 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3416 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3417 | ||
3418 | list_for_each_entry(connector, | |
3419 | &dev->mode_config.connector_list, head) { | |
3420 | ||
c84dec2f | 3421 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b HW |
3422 | dc_link = aconnector->dc_link; |
3423 | ||
c82eddf8 | 3424 | if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { |
4562236b HW |
3425 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; |
3426 | int_params.irq_source = dc_link->irq_source_hpd; | |
3427 | ||
3428 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3429 | handle_hpd_irq, | |
3430 | (void *) aconnector); | |
3431 | } | |
3432 | ||
c82eddf8 | 3433 | if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { |
4562236b HW |
3434 | |
3435 | /* Also register for DP short pulse (hpd_rx). */ | |
3436 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
3437 | int_params.irq_source = dc_link->irq_source_hpd_rx; | |
3438 | ||
3439 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3440 | handle_hpd_rx_irq, | |
3441 | (void *) aconnector); | |
3442 | } | |
bb4fa525 WL |
3443 | |
3444 | if (adev->dm.hpd_rx_offload_wq) | |
3445 | adev->dm.hpd_rx_offload_wq[connector->index].aconnector = | |
3446 | aconnector; | |
4562236b HW |
3447 | } |
3448 | } | |
3449 | ||
55e56389 MR |
3450 | #if defined(CONFIG_DRM_AMD_DC_SI) |
3451 | /* Register IRQ sources and initialize IRQ callbacks */ | |
3452 | static int dce60_register_irq_handlers(struct amdgpu_device *adev) | |
3453 | { | |
3454 | struct dc *dc = adev->dm.dc; | |
3455 | struct common_irq_params *c_irq_params; | |
3456 | struct dc_interrupt_params int_params = {0}; | |
3457 | int r; | |
3458 | int i; | |
c82eddf8 | 3459 | unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
55e56389 MR |
3460 | |
3461 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3462 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3463 | ||
3464 | /* | |
3465 | * Actions of amdgpu_irq_add_id(): | |
3466 | * 1. Register a set() function with base driver. | |
3467 | * Base driver will call set() function to enable/disable an | |
3468 | * interrupt in DC hardware. | |
3469 | * 2. Register amdgpu_dm_irq_handler(). | |
3470 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3471 | * coming from DC hardware. | |
3472 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
c82eddf8 SS |
3473 | * for acknowledging and handling. |
3474 | */ | |
55e56389 MR |
3475 | |
3476 | /* Use VBLANK interrupt */ | |
3477 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
c82eddf8 | 3478 | r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); |
55e56389 MR |
3479 | if (r) { |
3480 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3481 | return r; | |
3482 | } | |
3483 | ||
3484 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3485 | int_params.irq_source = | |
c82eddf8 | 3486 | dc_interrupt_to_irq_source(dc, i + 1, 0); |
55e56389 MR |
3487 | |
3488 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; | |
3489 | ||
3490 | c_irq_params->adev = adev; | |
3491 | c_irq_params->irq_src = int_params.irq_source; | |
3492 | ||
3493 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3494 | dm_crtc_high_irq, c_irq_params); | |
3495 | } | |
3496 | ||
3497 | /* Use GRPH_PFLIP interrupt */ | |
3498 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; | |
3499 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { | |
3500 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); | |
3501 | if (r) { | |
3502 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3503 | return r; | |
3504 | } | |
3505 | ||
3506 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3507 | int_params.irq_source = | |
3508 | dc_interrupt_to_irq_source(dc, i, 0); | |
3509 | ||
3510 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3511 | ||
3512 | c_irq_params->adev = adev; | |
3513 | c_irq_params->irq_src = int_params.irq_source; | |
3514 | ||
3515 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3516 | dm_pflip_high_irq, c_irq_params); | |
3517 | ||
3518 | } | |
3519 | ||
3520 | /* HPD */ | |
3521 | r = amdgpu_irq_add_id(adev, client_id, | |
3522 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); | |
3523 | if (r) { | |
3524 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3525 | return r; | |
3526 | } | |
3527 | ||
3528 | register_hpd_handlers(adev); | |
3529 | ||
3530 | return 0; | |
3531 | } | |
3532 | #endif | |
3533 | ||
4562236b HW |
3534 | /* Register IRQ sources and initialize IRQ callbacks */ |
3535 | static int dce110_register_irq_handlers(struct amdgpu_device *adev) | |
3536 | { | |
3537 | struct dc *dc = adev->dm.dc; | |
3538 | struct common_irq_params *c_irq_params; | |
3539 | struct dc_interrupt_params int_params = {0}; | |
3540 | int r; | |
3541 | int i; | |
c82eddf8 | 3542 | unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
2c8ad2d5 | 3543 | |
c08182f2 | 3544 | if (adev->family >= AMDGPU_FAMILY_AI) |
3760f76c | 3545 | client_id = SOC15_IH_CLIENTID_DCE; |
4562236b HW |
3546 | |
3547 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3548 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3549 | ||
1f6010a9 DF |
3550 | /* |
3551 | * Actions of amdgpu_irq_add_id(): | |
4562236b HW |
3552 | * 1. Register a set() function with base driver. |
3553 | * Base driver will call set() function to enable/disable an | |
3554 | * interrupt in DC hardware. | |
3555 | * 2. Register amdgpu_dm_irq_handler(). | |
3556 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3557 | * coming from DC hardware. | |
3558 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
c82eddf8 SS |
3559 | * for acknowledging and handling. |
3560 | */ | |
4562236b | 3561 | |
b57de80a | 3562 | /* Use VBLANK interrupt */ |
e9029155 | 3563 | for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { |
2c8ad2d5 | 3564 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); |
4562236b HW |
3565 | if (r) { |
3566 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3567 | return r; | |
3568 | } | |
3569 | ||
3570 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3571 | int_params.irq_source = | |
3d761e79 | 3572 | dc_interrupt_to_irq_source(dc, i, 0); |
4562236b | 3573 | |
b57de80a | 3574 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
4562236b HW |
3575 | |
3576 | c_irq_params->adev = adev; | |
3577 | c_irq_params->irq_src = int_params.irq_source; | |
3578 | ||
3579 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3580 | dm_crtc_high_irq, c_irq_params); | |
3581 | } | |
3582 | ||
d2574c33 MK |
3583 | /* Use VUPDATE interrupt */ |
3584 | for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { | |
3585 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); | |
3586 | if (r) { | |
3587 | DRM_ERROR("Failed to add vupdate irq id!\n"); | |
3588 | return r; | |
3589 | } | |
3590 | ||
3591 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3592 | int_params.irq_source = | |
3593 | dc_interrupt_to_irq_source(dc, i, 0); | |
3594 | ||
3595 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; | |
3596 | ||
3597 | c_irq_params->adev = adev; | |
3598 | c_irq_params->irq_src = int_params.irq_source; | |
3599 | ||
3600 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3601 | dm_vupdate_high_irq, c_irq_params); | |
3602 | } | |
3603 | ||
3d761e79 | 3604 | /* Use GRPH_PFLIP interrupt */ |
4562236b HW |
3605 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; |
3606 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { | |
2c8ad2d5 | 3607 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); |
4562236b HW |
3608 | if (r) { |
3609 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3610 | return r; | |
3611 | } | |
3612 | ||
3613 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3614 | int_params.irq_source = | |
3615 | dc_interrupt_to_irq_source(dc, i, 0); | |
3616 | ||
3617 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3618 | ||
3619 | c_irq_params->adev = adev; | |
3620 | c_irq_params->irq_src = int_params.irq_source; | |
3621 | ||
3622 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3623 | dm_pflip_high_irq, c_irq_params); | |
3624 | ||
3625 | } | |
3626 | ||
3627 | /* HPD */ | |
2c8ad2d5 AD |
3628 | r = amdgpu_irq_add_id(adev, client_id, |
3629 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); | |
4562236b HW |
3630 | if (r) { |
3631 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3632 | return r; | |
3633 | } | |
3634 | ||
3635 | register_hpd_handlers(adev); | |
3636 | ||
3637 | return 0; | |
3638 | } | |
3639 | ||
ff5ef992 AD |
3640 | /* Register IRQ sources and initialize IRQ callbacks */ |
3641 | static int dcn10_register_irq_handlers(struct amdgpu_device *adev) | |
3642 | { | |
3643 | struct dc *dc = adev->dm.dc; | |
3644 | struct common_irq_params *c_irq_params; | |
3645 | struct dc_interrupt_params int_params = {0}; | |
3646 | int r; | |
3647 | int i; | |
660d5406 WL |
3648 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
3649 | static const unsigned int vrtl_int_srcid[] = { | |
3650 | DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, | |
3651 | DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, | |
3652 | DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, | |
3653 | DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, | |
3654 | DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, | |
3655 | DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL | |
3656 | }; | |
3657 | #endif | |
ff5ef992 AD |
3658 | |
3659 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3660 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3661 | ||
1f6010a9 DF |
3662 | /* |
3663 | * Actions of amdgpu_irq_add_id(): | |
ff5ef992 AD |
3664 | * 1. Register a set() function with base driver. |
3665 | * Base driver will call set() function to enable/disable an | |
3666 | * interrupt in DC hardware. | |
3667 | * 2. Register amdgpu_dm_irq_handler(). | |
3668 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3669 | * coming from DC hardware. | |
3670 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
3671 | * for acknowledging and handling. | |
1f6010a9 | 3672 | */ |
ff5ef992 AD |
3673 | |
3674 | /* Use VSTARTUP interrupt */ | |
3675 | for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; | |
3676 | i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; | |
3677 | i++) { | |
3760f76c | 3678 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); |
ff5ef992 AD |
3679 | |
3680 | if (r) { | |
3681 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3682 | return r; | |
3683 | } | |
3684 | ||
3685 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3686 | int_params.irq_source = | |
3687 | dc_interrupt_to_irq_source(dc, i, 0); | |
3688 | ||
3689 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; | |
3690 | ||
3691 | c_irq_params->adev = adev; | |
3692 | c_irq_params->irq_src = int_params.irq_source; | |
3693 | ||
2346ef47 NK |
3694 | amdgpu_dm_irq_register_interrupt( |
3695 | adev, &int_params, dm_crtc_high_irq, c_irq_params); | |
3696 | } | |
3697 | ||
86bc2219 WL |
3698 | /* Use otg vertical line interrupt */ |
3699 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) | |
660d5406 WL |
3700 | for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { |
3701 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, | |
3702 | vrtl_int_srcid[i], &adev->vline0_irq); | |
86bc2219 WL |
3703 | |
3704 | if (r) { | |
3705 | DRM_ERROR("Failed to add vline0 irq id!\n"); | |
3706 | return r; | |
3707 | } | |
3708 | ||
3709 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3710 | int_params.irq_source = | |
660d5406 WL |
3711 | dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); |
3712 | ||
3713 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { | |
3714 | DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); | |
3715 | break; | |
3716 | } | |
86bc2219 WL |
3717 | |
3718 | c_irq_params = &adev->dm.vline0_params[int_params.irq_source | |
3719 | - DC_IRQ_SOURCE_DC1_VLINE0]; | |
3720 | ||
3721 | c_irq_params->adev = adev; | |
3722 | c_irq_params->irq_src = int_params.irq_source; | |
3723 | ||
3724 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3725 | dm_dcn_vertical_interrupt0_high_irq, c_irq_params); | |
3726 | } | |
3727 | #endif | |
3728 | ||
2346ef47 NK |
3729 | /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to |
3730 | * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx | |
3731 | * to trigger at end of each vblank, regardless of state of the lock, | |
3732 | * matching DCE behaviour. | |
3733 | */ | |
3734 | for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; | |
3735 | i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; | |
3736 | i++) { | |
3737 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); | |
3738 | ||
3739 | if (r) { | |
3740 | DRM_ERROR("Failed to add vupdate irq id!\n"); | |
3741 | return r; | |
3742 | } | |
3743 | ||
3744 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3745 | int_params.irq_source = | |
3746 | dc_interrupt_to_irq_source(dc, i, 0); | |
3747 | ||
3748 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; | |
3749 | ||
3750 | c_irq_params->adev = adev; | |
3751 | c_irq_params->irq_src = int_params.irq_source; | |
3752 | ||
ff5ef992 | 3753 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
2346ef47 | 3754 | dm_vupdate_high_irq, c_irq_params); |
d2574c33 MK |
3755 | } |
3756 | ||
ff5ef992 AD |
3757 | /* Use GRPH_PFLIP interrupt */ |
3758 | for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; | |
de95753c | 3759 | i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; |
ff5ef992 | 3760 | i++) { |
3760f76c | 3761 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); |
ff5ef992 AD |
3762 | if (r) { |
3763 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3764 | return r; | |
3765 | } | |
3766 | ||
3767 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3768 | int_params.irq_source = | |
3769 | dc_interrupt_to_irq_source(dc, i, 0); | |
3770 | ||
3771 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3772 | ||
3773 | c_irq_params->adev = adev; | |
3774 | c_irq_params->irq_src = int_params.irq_source; | |
3775 | ||
3776 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3777 | dm_pflip_high_irq, c_irq_params); | |
3778 | ||
3779 | } | |
3780 | ||
81927e28 JS |
3781 | /* HPD */ |
3782 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, | |
3783 | &adev->hpd_irq); | |
3784 | if (r) { | |
3785 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3786 | return r; | |
3787 | } | |
a08f16cf | 3788 | |
81927e28 | 3789 | register_hpd_handlers(adev); |
a08f16cf | 3790 | |
81927e28 JS |
3791 | return 0; |
3792 | } | |
3793 | /* Register Outbox IRQ sources and initialize IRQ callbacks */ | |
3794 | static int register_outbox_irq_handlers(struct amdgpu_device *adev) | |
3795 | { | |
3796 | struct dc *dc = adev->dm.dc; | |
3797 | struct common_irq_params *c_irq_params; | |
3798 | struct dc_interrupt_params int_params = {0}; | |
3799 | int r, i; | |
3800 | ||
3801 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3802 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3803 | ||
3804 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, | |
3805 | &adev->dmub_outbox_irq); | |
3806 | if (r) { | |
3807 | DRM_ERROR("Failed to add outbox irq id!\n"); | |
3808 | return r; | |
3809 | } | |
3810 | ||
3811 | if (dc->ctx->dmub_srv) { | |
3812 | i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; | |
3813 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
a08f16cf | 3814 | int_params.irq_source = |
81927e28 | 3815 | dc_interrupt_to_irq_source(dc, i, 0); |
a08f16cf | 3816 | |
81927e28 | 3817 | c_irq_params = &adev->dm.dmub_outbox_params[0]; |
a08f16cf LHM |
3818 | |
3819 | c_irq_params->adev = adev; | |
3820 | c_irq_params->irq_src = int_params.irq_source; | |
3821 | ||
3822 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
81927e28 | 3823 | dm_dmub_outbox1_low_irq, c_irq_params); |
ff5ef992 AD |
3824 | } |
3825 | ||
ff5ef992 AD |
3826 | return 0; |
3827 | } | |
ff5ef992 | 3828 | |
eb3dc897 NK |
3829 | /* |
3830 | * Acquires the lock for the atomic state object and returns | |
3831 | * the new atomic state. | |
3832 | * | |
3833 | * This should only be called during atomic check. | |
3834 | */ | |
17ce8a69 RL |
3835 | int dm_atomic_get_state(struct drm_atomic_state *state, |
3836 | struct dm_atomic_state **dm_state) | |
eb3dc897 NK |
3837 | { |
3838 | struct drm_device *dev = state->dev; | |
1348969a | 3839 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 NK |
3840 | struct amdgpu_display_manager *dm = &adev->dm; |
3841 | struct drm_private_state *priv_state; | |
eb3dc897 NK |
3842 | |
3843 | if (*dm_state) | |
3844 | return 0; | |
3845 | ||
eb3dc897 NK |
3846 | priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); |
3847 | if (IS_ERR(priv_state)) | |
3848 | return PTR_ERR(priv_state); | |
3849 | ||
3850 | *dm_state = to_dm_atomic_state(priv_state); | |
3851 | ||
3852 | return 0; | |
3853 | } | |
3854 | ||
dfd84d90 | 3855 | static struct dm_atomic_state * |
eb3dc897 NK |
3856 | dm_atomic_get_new_state(struct drm_atomic_state *state) |
3857 | { | |
3858 | struct drm_device *dev = state->dev; | |
1348969a | 3859 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 NK |
3860 | struct amdgpu_display_manager *dm = &adev->dm; |
3861 | struct drm_private_obj *obj; | |
3862 | struct drm_private_state *new_obj_state; | |
3863 | int i; | |
3864 | ||
3865 | for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { | |
3866 | if (obj->funcs == dm->atomic_obj.funcs) | |
3867 | return to_dm_atomic_state(new_obj_state); | |
3868 | } | |
3869 | ||
3870 | return NULL; | |
3871 | } | |
3872 | ||
eb3dc897 NK |
3873 | static struct drm_private_state * |
3874 | dm_atomic_duplicate_state(struct drm_private_obj *obj) | |
3875 | { | |
3876 | struct dm_atomic_state *old_state, *new_state; | |
3877 | ||
3878 | new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); | |
3879 | if (!new_state) | |
3880 | return NULL; | |
3881 | ||
3882 | __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); | |
3883 | ||
813d20dc AW |
3884 | old_state = to_dm_atomic_state(obj->state); |
3885 | ||
3886 | if (old_state && old_state->context) | |
3887 | new_state->context = dc_copy_state(old_state->context); | |
3888 | ||
eb3dc897 NK |
3889 | if (!new_state->context) { |
3890 | kfree(new_state); | |
3891 | return NULL; | |
3892 | } | |
3893 | ||
eb3dc897 NK |
3894 | return &new_state->base; |
3895 | } | |
3896 | ||
3897 | static void dm_atomic_destroy_state(struct drm_private_obj *obj, | |
3898 | struct drm_private_state *state) | |
3899 | { | |
3900 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); | |
3901 | ||
3902 | if (dm_state && dm_state->context) | |
3903 | dc_release_state(dm_state->context); | |
3904 | ||
3905 | kfree(dm_state); | |
3906 | } | |
3907 | ||
3908 | static struct drm_private_state_funcs dm_atomic_state_funcs = { | |
3909 | .atomic_duplicate_state = dm_atomic_duplicate_state, | |
3910 | .atomic_destroy_state = dm_atomic_destroy_state, | |
3911 | }; | |
3912 | ||
4562236b HW |
3913 | static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) |
3914 | { | |
eb3dc897 | 3915 | struct dm_atomic_state *state; |
4562236b HW |
3916 | int r; |
3917 | ||
3918 | adev->mode_info.mode_config_initialized = true; | |
3919 | ||
4a580877 LT |
3920 | adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; |
3921 | adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; | |
4562236b | 3922 | |
4a580877 LT |
3923 | adev_to_drm(adev)->mode_config.max_width = 16384; |
3924 | adev_to_drm(adev)->mode_config.max_height = 16384; | |
4562236b | 3925 | |
4a580877 | 3926 | adev_to_drm(adev)->mode_config.preferred_depth = 24; |
a6250bdb AD |
3927 | if (adev->asic_type == CHIP_HAWAII) |
3928 | /* disable prefer shadow for now due to hibernation issues */ | |
3929 | adev_to_drm(adev)->mode_config.prefer_shadow = 0; | |
3930 | else | |
3931 | adev_to_drm(adev)->mode_config.prefer_shadow = 1; | |
1f6010a9 | 3932 | /* indicates support for immediate flip */ |
4a580877 | 3933 | adev_to_drm(adev)->mode_config.async_page_flip = true; |
4562236b | 3934 | |
eb3dc897 NK |
3935 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
3936 | if (!state) | |
3937 | return -ENOMEM; | |
3938 | ||
813d20dc | 3939 | state->context = dc_create_state(adev->dm.dc); |
eb3dc897 NK |
3940 | if (!state->context) { |
3941 | kfree(state); | |
3942 | return -ENOMEM; | |
3943 | } | |
3944 | ||
3945 | dc_resource_state_copy_construct_current(adev->dm.dc, state->context); | |
3946 | ||
4a580877 | 3947 | drm_atomic_private_obj_init(adev_to_drm(adev), |
8c1a765b | 3948 | &adev->dm.atomic_obj, |
eb3dc897 NK |
3949 | &state->base, |
3950 | &dm_atomic_state_funcs); | |
3951 | ||
3dc9b1ce | 3952 | r = amdgpu_display_modeset_create_props(adev); |
b67a468a DL |
3953 | if (r) { |
3954 | dc_release_state(state->context); | |
3955 | kfree(state); | |
4562236b | 3956 | return r; |
b67a468a | 3957 | } |
4562236b | 3958 | |
6ce8f316 | 3959 | r = amdgpu_dm_audio_init(adev); |
b67a468a DL |
3960 | if (r) { |
3961 | dc_release_state(state->context); | |
3962 | kfree(state); | |
6ce8f316 | 3963 | return r; |
b67a468a | 3964 | } |
6ce8f316 | 3965 | |
4562236b HW |
3966 | return 0; |
3967 | } | |
3968 | ||
206bbafe DF |
3969 | #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 |
3970 | #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 | |
94562810 | 3971 | #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 |
206bbafe | 3972 | |
7fd13bae AD |
3973 | static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, |
3974 | int bl_idx) | |
206bbafe DF |
3975 | { |
3976 | #if defined(CONFIG_ACPI) | |
3977 | struct amdgpu_dm_backlight_caps caps; | |
3978 | ||
58965855 FS |
3979 | memset(&caps, 0, sizeof(caps)); |
3980 | ||
7fd13bae | 3981 | if (dm->backlight_caps[bl_idx].caps_valid) |
206bbafe DF |
3982 | return; |
3983 | ||
f9b7f370 | 3984 | amdgpu_acpi_get_backlight_caps(&caps); |
206bbafe | 3985 | if (caps.caps_valid) { |
7fd13bae | 3986 | dm->backlight_caps[bl_idx].caps_valid = true; |
94562810 RS |
3987 | if (caps.aux_support) |
3988 | return; | |
7fd13bae AD |
3989 | dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; |
3990 | dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; | |
206bbafe | 3991 | } else { |
7fd13bae | 3992 | dm->backlight_caps[bl_idx].min_input_signal = |
206bbafe | 3993 | AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
7fd13bae | 3994 | dm->backlight_caps[bl_idx].max_input_signal = |
206bbafe DF |
3995 | AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; |
3996 | } | |
3997 | #else | |
7fd13bae | 3998 | if (dm->backlight_caps[bl_idx].aux_support) |
94562810 RS |
3999 | return; |
4000 | ||
7fd13bae AD |
4001 | dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
4002 | dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; | |
206bbafe DF |
4003 | #endif |
4004 | } | |
4005 | ||
69d9f427 | 4006 | static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, |
c82eddf8 | 4007 | unsigned int *min, unsigned int *max) |
94562810 | 4008 | { |
94562810 | 4009 | if (!caps) |
69d9f427 | 4010 | return 0; |
94562810 | 4011 | |
69d9f427 AM |
4012 | if (caps->aux_support) { |
4013 | // Firmware limits are in nits, DC API wants millinits. | |
4014 | *max = 1000 * caps->aux_max_input_signal; | |
4015 | *min = 1000 * caps->aux_min_input_signal; | |
94562810 | 4016 | } else { |
69d9f427 AM |
4017 | // Firmware limits are 8-bit, PWM control is 16-bit. |
4018 | *max = 0x101 * caps->max_input_signal; | |
4019 | *min = 0x101 * caps->min_input_signal; | |
94562810 | 4020 | } |
69d9f427 AM |
4021 | return 1; |
4022 | } | |
94562810 | 4023 | |
69d9f427 AM |
4024 | static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, |
4025 | uint32_t brightness) | |
4026 | { | |
c82eddf8 | 4027 | unsigned int min, max; |
94562810 | 4028 | |
69d9f427 AM |
4029 | if (!get_brightness_range(caps, &min, &max)) |
4030 | return brightness; | |
4031 | ||
4032 | // Rescale 0..255 to min..max | |
4033 | return min + DIV_ROUND_CLOSEST((max - min) * brightness, | |
4034 | AMDGPU_MAX_BL_LEVEL); | |
4035 | } | |
4036 | ||
4037 | static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, | |
4038 | uint32_t brightness) | |
4039 | { | |
c82eddf8 | 4040 | unsigned int min, max; |
69d9f427 AM |
4041 | |
4042 | if (!get_brightness_range(caps, &min, &max)) | |
4043 | return brightness; | |
4044 | ||
4045 | if (brightness < min) | |
4046 | return 0; | |
4047 | // Rescale min..max to 0..255 | |
4048 | return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), | |
4049 | max - min); | |
94562810 RS |
4050 | } |
4051 | ||
4052287a | 4052 | static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, |
7fd13bae | 4053 | int bl_idx, |
3d6c9164 | 4054 | u32 user_brightness) |
4562236b | 4055 | { |
206bbafe | 4056 | struct amdgpu_dm_backlight_caps caps; |
7fd13bae AD |
4057 | struct dc_link *link; |
4058 | u32 brightness; | |
94562810 | 4059 | bool rc; |
4562236b | 4060 | |
7fd13bae AD |
4061 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4062 | caps = dm->backlight_caps[bl_idx]; | |
94562810 | 4063 | |
7fd13bae | 4064 | dm->brightness[bl_idx] = user_brightness; |
1f579254 AD |
4065 | /* update scratch register */ |
4066 | if (bl_idx == 0) | |
4067 | amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); | |
7fd13bae AD |
4068 | brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); |
4069 | link = (struct dc_link *)dm->backlight_link[bl_idx]; | |
94562810 | 4070 | |
3d6c9164 | 4071 | /* Change brightness based on AUX property */ |
118b4627 | 4072 | if (caps.aux_support) { |
7fd13bae AD |
4073 | rc = dc_link_set_backlight_level_nits(link, true, brightness, |
4074 | AUX_BL_DEFAULT_TRANSITION_TIME_MS); | |
4075 | if (!rc) | |
4076 | DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); | |
118b4627 | 4077 | } else { |
7fd13bae AD |
4078 | rc = dc_link_set_backlight_level(link, brightness, 0); |
4079 | if (!rc) | |
4080 | DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); | |
118b4627 | 4081 | } |
94562810 | 4082 | |
4052287a S |
4083 | if (rc) |
4084 | dm->actual_brightness[bl_idx] = user_brightness; | |
4562236b HW |
4085 | } |
4086 | ||
3d6c9164 | 4087 | static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) |
4562236b | 4088 | { |
620a0d27 | 4089 | struct amdgpu_display_manager *dm = bl_get_data(bd); |
7fd13bae | 4090 | int i; |
3d6c9164 | 4091 | |
7fd13bae AD |
4092 | for (i = 0; i < dm->num_of_edps; i++) { |
4093 | if (bd == dm->backlight_dev[i]) | |
4094 | break; | |
4095 | } | |
4096 | if (i >= AMDGPU_DM_MAX_NUM_EDP) | |
4097 | i = 0; | |
4098 | amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); | |
3d6c9164 AD |
4099 | |
4100 | return 0; | |
4101 | } | |
4102 | ||
7fd13bae AD |
4103 | static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, |
4104 | int bl_idx) | |
3d6c9164 | 4105 | { |
53e1db06 | 4106 | int ret; |
0ad3e64e | 4107 | struct amdgpu_dm_backlight_caps caps; |
7fd13bae | 4108 | struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; |
0ad3e64e | 4109 | |
7fd13bae AD |
4110 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4111 | caps = dm->backlight_caps[bl_idx]; | |
620a0d27 | 4112 | |
0ad3e64e | 4113 | if (caps.aux_support) { |
0ad3e64e AD |
4114 | u32 avg, peak; |
4115 | bool rc; | |
4116 | ||
4117 | rc = dc_link_get_backlight_level_nits(link, &avg, &peak); | |
4118 | if (!rc) | |
7fd13bae | 4119 | return dm->brightness[bl_idx]; |
0ad3e64e | 4120 | return convert_brightness_to_user(&caps, avg); |
0ad3e64e | 4121 | } |
53e1db06 SS |
4122 | |
4123 | ret = dc_link_get_backlight_level(link); | |
4124 | ||
4125 | if (ret == DC_ERROR_UNEXPECTED) | |
4126 | return dm->brightness[bl_idx]; | |
4127 | ||
4128 | return convert_brightness_to_user(&caps, ret); | |
4562236b HW |
4129 | } |
4130 | ||
3d6c9164 AD |
4131 | static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) |
4132 | { | |
4133 | struct amdgpu_display_manager *dm = bl_get_data(bd); | |
7fd13bae | 4134 | int i; |
3d6c9164 | 4135 | |
7fd13bae AD |
4136 | for (i = 0; i < dm->num_of_edps; i++) { |
4137 | if (bd == dm->backlight_dev[i]) | |
4138 | break; | |
4139 | } | |
4140 | if (i >= AMDGPU_DM_MAX_NUM_EDP) | |
4141 | i = 0; | |
4142 | return amdgpu_dm_backlight_get_level(dm, i); | |
3d6c9164 AD |
4143 | } |
4144 | ||
4562236b | 4145 | static const struct backlight_ops amdgpu_dm_backlight_ops = { |
bb264220 | 4146 | .options = BL_CORE_SUSPENDRESUME, |
4562236b HW |
4147 | .get_brightness = amdgpu_dm_backlight_get_brightness, |
4148 | .update_status = amdgpu_dm_backlight_update_status, | |
4149 | }; | |
4150 | ||
7578ecda | 4151 | static void |
213eca2b | 4152 | amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) |
4562236b | 4153 | { |
213eca2b HG |
4154 | struct drm_device *drm = aconnector->base.dev; |
4155 | struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; | |
4562236b | 4156 | struct backlight_properties props = { 0 }; |
213eca2b | 4157 | char bl_name[16]; |
4562236b | 4158 | |
62f03dad HG |
4159 | if (aconnector->bl_idx == -1) |
4160 | return; | |
4161 | ||
da11ef83 | 4162 | if (!acpi_video_backlight_use_native()) { |
213eca2b | 4163 | drm_info(drm, "Skipping amdgpu DM backlight registration\n"); |
c0f50c5d HG |
4164 | /* Try registering an ACPI video backlight device instead. */ |
4165 | acpi_video_register_backlight(); | |
da11ef83 HG |
4166 | return; |
4167 | } | |
4168 | ||
4562236b | 4169 | props.max_brightness = AMDGPU_MAX_BL_LEVEL; |
53a53f86 | 4170 | props.brightness = AMDGPU_MAX_BL_LEVEL; |
4562236b HW |
4171 | props.type = BACKLIGHT_RAW; |
4172 | ||
4173 | snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", | |
213eca2b | 4174 | drm->primary->index + aconnector->bl_idx); |
4562236b | 4175 | |
213eca2b | 4176 | dm->backlight_dev[aconnector->bl_idx] = |
62f03dad | 4177 | backlight_device_register(bl_name, aconnector->base.kdev, dm, |
213eca2b | 4178 | &amdgpu_dm_backlight_ops, &props); |
4562236b | 4179 | |
213eca2b | 4180 | if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { |
4562236b | 4181 | DRM_ERROR("DM: Backlight registration failed!\n"); |
213eca2b | 4182 | dm->backlight_dev[aconnector->bl_idx] = NULL; |
4db231d7 | 4183 | } else |
f1ad2f5e | 4184 | DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); |
4562236b | 4185 | } |
4562236b | 4186 | |
df534fff | 4187 | static int initialize_plane(struct amdgpu_display_manager *dm, |
b2fddb13 | 4188 | struct amdgpu_mode_info *mode_info, int plane_id, |
cc1fec57 NK |
4189 | enum drm_plane_type plane_type, |
4190 | const struct dc_plane_cap *plane_cap) | |
df534fff | 4191 | { |
f180b4bc | 4192 | struct drm_plane *plane; |
df534fff S |
4193 | unsigned long possible_crtcs; |
4194 | int ret = 0; | |
4195 | ||
f180b4bc | 4196 | plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); |
df534fff S |
4197 | if (!plane) { |
4198 | DRM_ERROR("KMS: Failed to allocate plane\n"); | |
4199 | return -ENOMEM; | |
4200 | } | |
b2fddb13 | 4201 | plane->type = plane_type; |
df534fff S |
4202 | |
4203 | /* | |
b2fddb13 NK |
4204 | * HACK: IGT tests expect that the primary plane for a CRTC |
4205 | * can only have one possible CRTC. Only expose support for | |
4206 | * any CRTC if they're not going to be used as a primary plane | |
4207 | * for a CRTC - like overlay or underlay planes. | |
df534fff S |
4208 | */ |
4209 | possible_crtcs = 1 << plane_id; | |
4210 | if (plane_id >= dm->dc->caps.max_streams) | |
4211 | possible_crtcs = 0xff; | |
4212 | ||
cc1fec57 | 4213 | ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); |
df534fff S |
4214 | |
4215 | if (ret) { | |
4216 | DRM_ERROR("KMS: Failed to initialize plane\n"); | |
54087768 | 4217 | kfree(plane); |
df534fff S |
4218 | return ret; |
4219 | } | |
4220 | ||
54087768 NK |
4221 | if (mode_info) |
4222 | mode_info->planes[plane_id] = plane; | |
4223 | ||
df534fff S |
4224 | return ret; |
4225 | } | |
4226 | ||
89fc8d4e | 4227 | |
618e51cd HG |
4228 | static void setup_backlight_device(struct amdgpu_display_manager *dm, |
4229 | struct amdgpu_dm_connector *aconnector) | |
89fc8d4e | 4230 | { |
f196198c | 4231 | struct dc_link *link = aconnector->dc_link; |
ceb4a561 | 4232 | int bl_idx = dm->num_of_edps; |
89fc8d4e | 4233 | |
ceb4a561 HG |
4234 | if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || |
4235 | link->type == dc_connection_none) | |
4236 | return; | |
4237 | ||
4238 | if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { | |
4239 | drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); | |
4240 | return; | |
89fc8d4e | 4241 | } |
ceb4a561 | 4242 | |
f196198c HG |
4243 | aconnector->bl_idx = bl_idx; |
4244 | ||
618e51cd HG |
4245 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4246 | dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; | |
ceb4a561 HG |
4247 | dm->backlight_link[bl_idx] = link; |
4248 | dm->num_of_edps++; | |
618e51cd HG |
4249 | |
4250 | update_connector_ext_caps(aconnector); | |
89fc8d4e HW |
4251 | } |
4252 | ||
acc96ae0 | 4253 | static void amdgpu_set_panel_orientation(struct drm_connector *connector); |
89fc8d4e | 4254 | |
1f6010a9 DF |
4255 | /* |
4256 | * In this architecture, the association | |
4562236b HW |
4257 | * connector -> encoder -> crtc |
4258 | * id not really requried. The crtc and connector will hold the | |
4259 | * display_index as an abstraction to use with DAL component | |
4260 | * | |
4261 | * Returns 0 on success | |
4262 | */ | |
7578ecda | 4263 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) |
4562236b HW |
4264 | { |
4265 | struct amdgpu_display_manager *dm = &adev->dm; | |
ae67558b | 4266 | s32 i; |
c84dec2f | 4267 | struct amdgpu_dm_connector *aconnector = NULL; |
f2a0f5e6 | 4268 | struct amdgpu_encoder *aencoder = NULL; |
d4e13b0d | 4269 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
ae67558b SS |
4270 | u32 link_cnt; |
4271 | s32 primary_planes; | |
fbbdadf2 | 4272 | enum dc_connection_type new_connection_type = dc_connection_none; |
cc1fec57 | 4273 | const struct dc_plane_cap *plane; |
9470620e | 4274 | bool psr_feature_enabled = false; |
3cce0bfc | 4275 | bool replay_feature_enabled = false; |
35f33086 | 4276 | int max_overlay = dm->dc->caps.max_slave_planes; |
4562236b | 4277 | |
d58159de AD |
4278 | dm->display_indexes_num = dm->dc->caps.max_streams; |
4279 | /* Update the actual used number of crtc */ | |
4280 | adev->mode_info.num_crtc = adev->dm.display_indexes_num; | |
4281 | ||
60971b20 | 4282 | amdgpu_dm_set_irq_funcs(adev); |
4283 | ||
4562236b | 4284 | link_cnt = dm->dc->caps.max_links; |
4562236b HW |
4285 | if (amdgpu_dm_mode_config_init(dm->adev)) { |
4286 | DRM_ERROR("DM: Failed to initialize mode config\n"); | |
59d0f396 | 4287 | return -EINVAL; |
4562236b HW |
4288 | } |
4289 | ||
b2fddb13 NK |
4290 | /* There is one primary plane per CRTC */ |
4291 | primary_planes = dm->dc->caps.max_streams; | |
54087768 | 4292 | ASSERT(primary_planes <= AMDGPU_MAX_PLANES); |
efa6a8b7 | 4293 | |
b2fddb13 NK |
4294 | /* |
4295 | * Initialize primary planes, implicit planes for legacy IOCTLS. | |
4296 | * Order is reversed to match iteration order in atomic check. | |
4297 | */ | |
4298 | for (i = (primary_planes - 1); i >= 0; i--) { | |
cc1fec57 NK |
4299 | plane = &dm->dc->caps.planes[i]; |
4300 | ||
b2fddb13 | 4301 | if (initialize_plane(dm, mode_info, i, |
cc1fec57 | 4302 | DRM_PLANE_TYPE_PRIMARY, plane)) { |
df534fff | 4303 | DRM_ERROR("KMS: Failed to initialize primary plane\n"); |
cd8a2ae8 | 4304 | goto fail; |
d4e13b0d | 4305 | } |
df534fff | 4306 | } |
92f3ac40 | 4307 | |
0d579c7e NK |
4308 | /* |
4309 | * Initialize overlay planes, index starting after primary planes. | |
4310 | * These planes have a higher DRM index than the primary planes since | |
4311 | * they should be considered as having a higher z-order. | |
4312 | * Order is reversed to match iteration order in atomic check. | |
cc1fec57 NK |
4313 | * |
4314 | * Only support DCN for now, and only expose one so we don't encourage | |
4315 | * userspace to use up all the pipes. | |
0d579c7e | 4316 | */ |
cc1fec57 NK |
4317 | for (i = 0; i < dm->dc->caps.max_planes; ++i) { |
4318 | struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; | |
4319 | ||
8813381a LL |
4320 | /* Do not create overlay if MPO disabled */ |
4321 | if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) | |
4322 | break; | |
4323 | ||
cc1fec57 NK |
4324 | if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) |
4325 | continue; | |
4326 | ||
ea36ad34 | 4327 | if (!plane->pixel_format_support.argb8888) |
cc1fec57 NK |
4328 | continue; |
4329 | ||
35f33086 BL |
4330 | if (max_overlay-- == 0) |
4331 | break; | |
4332 | ||
54087768 | 4333 | if (initialize_plane(dm, NULL, primary_planes + i, |
cc1fec57 | 4334 | DRM_PLANE_TYPE_OVERLAY, plane)) { |
0d579c7e | 4335 | DRM_ERROR("KMS: Failed to initialize overlay plane\n"); |
cd8a2ae8 | 4336 | goto fail; |
d4e13b0d AD |
4337 | } |
4338 | } | |
4562236b | 4339 | |
d4e13b0d | 4340 | for (i = 0; i < dm->dc->caps.max_streams; i++) |
f180b4bc | 4341 | if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { |
4562236b | 4342 | DRM_ERROR("KMS: Failed to initialize crtc\n"); |
cd8a2ae8 | 4343 | goto fail; |
4562236b | 4344 | } |
4562236b | 4345 | |
81927e28 | 4346 | /* Use Outbox interrupt */ |
1d789535 | 4347 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
4348 | case IP_VERSION(3, 0, 0): |
4349 | case IP_VERSION(3, 1, 2): | |
4350 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4351 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4352 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4353 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4354 | case IP_VERSION(3, 2, 0): |
4355 | case IP_VERSION(3, 2, 1): | |
c08182f2 | 4356 | case IP_VERSION(2, 1, 0): |
81927e28 JS |
4357 | if (register_outbox_irq_handlers(dm->adev)) { |
4358 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4359 | goto fail; | |
4360 | } | |
4361 | break; | |
4362 | default: | |
c08182f2 | 4363 | DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", |
1d789535 | 4364 | adev->ip_versions[DCE_HWIP][0]); |
81927e28 | 4365 | } |
9470620e NK |
4366 | |
4367 | /* Determine whether to enable PSR support by default. */ | |
4368 | if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { | |
4369 | switch (adev->ip_versions[DCE_HWIP][0]) { | |
4370 | case IP_VERSION(3, 1, 2): | |
4371 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4372 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4373 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4374 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4375 | case IP_VERSION(3, 2, 0): |
4376 | case IP_VERSION(3, 2, 1): | |
9470620e NK |
4377 | psr_feature_enabled = true; |
4378 | break; | |
4379 | default: | |
4380 | psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; | |
4381 | break; | |
4382 | } | |
4383 | } | |
81927e28 | 4384 | |
3cce0bfc BL |
4385 | if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { |
4386 | switch (adev->ip_versions[DCE_HWIP][0]) { | |
4387 | case IP_VERSION(3, 1, 4): | |
4388 | case IP_VERSION(3, 1, 5): | |
4389 | case IP_VERSION(3, 1, 6): | |
4390 | case IP_VERSION(3, 2, 0): | |
4391 | case IP_VERSION(3, 2, 1): | |
4392 | replay_feature_enabled = true; | |
4393 | break; | |
4394 | default: | |
4395 | replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; | |
4396 | break; | |
4397 | } | |
4398 | } | |
4562236b HW |
4399 | /* loops over all connectors on the board */ |
4400 | for (i = 0; i < link_cnt; i++) { | |
89fc8d4e | 4401 | struct dc_link *link = NULL; |
4562236b HW |
4402 | |
4403 | if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { | |
4404 | DRM_ERROR( | |
4405 | "KMS: Cannot support more than %d display indexes\n", | |
4406 | AMDGPU_DM_MAX_DISPLAY_INDEX); | |
4407 | continue; | |
4408 | } | |
4409 | ||
4410 | aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); | |
4411 | if (!aconnector) | |
cd8a2ae8 | 4412 | goto fail; |
4562236b HW |
4413 | |
4414 | aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); | |
8440c304 | 4415 | if (!aencoder) |
cd8a2ae8 | 4416 | goto fail; |
4562236b HW |
4417 | |
4418 | if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { | |
4419 | DRM_ERROR("KMS: Failed to initialize encoder\n"); | |
cd8a2ae8 | 4420 | goto fail; |
4562236b HW |
4421 | } |
4422 | ||
4423 | if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { | |
4424 | DRM_ERROR("KMS: Failed to initialize connector\n"); | |
cd8a2ae8 | 4425 | goto fail; |
4562236b HW |
4426 | } |
4427 | ||
89fc8d4e HW |
4428 | link = dc_get_link_at_index(dm->dc, i); |
4429 | ||
54618888 | 4430 | if (!dc_link_detect_connection_type(link, &new_connection_type)) |
fbbdadf2 BL |
4431 | DRM_ERROR("KMS: Failed to detect connector\n"); |
4432 | ||
4433 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
4434 | emulated_link_detect(link); | |
4435 | amdgpu_dm_update_connector_after_detect(aconnector); | |
15c735e7 WL |
4436 | } else { |
4437 | bool ret = false; | |
fbbdadf2 | 4438 | |
15c735e7 WL |
4439 | mutex_lock(&dm->dc_lock); |
4440 | ret = dc_link_detect(link, DETECT_REASON_BOOT); | |
4441 | mutex_unlock(&dm->dc_lock); | |
4442 | ||
4443 | if (ret) { | |
4444 | amdgpu_dm_update_connector_after_detect(aconnector); | |
618e51cd | 4445 | setup_backlight_device(dm, aconnector); |
89fc8d4e | 4446 | |
3cce0bfc BL |
4447 | /* |
4448 | * Disable psr if replay can be enabled | |
4449 | */ | |
4450 | if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector)) | |
4451 | psr_feature_enabled = false; | |
4452 | ||
15c735e7 WL |
4453 | if (psr_feature_enabled) |
4454 | amdgpu_dm_set_psr_caps(link); | |
89fc8d4e | 4455 | |
15c735e7 WL |
4456 | /* TODO: Fix vblank control helpers to delay PSR entry to allow this when |
4457 | * PSR is also supported. | |
4458 | */ | |
4459 | if (link->psr_settings.psr_feature_enabled) | |
4460 | adev_to_drm(adev)->vblank_disable_immediate = false; | |
4461 | } | |
4462 | } | |
acc96ae0 | 4463 | amdgpu_set_panel_orientation(&aconnector->base); |
4562236b HW |
4464 | } |
4465 | ||
4466 | /* Software is initialized. Now we can register interrupt handlers. */ | |
4467 | switch (adev->asic_type) { | |
55e56389 MR |
4468 | #if defined(CONFIG_DRM_AMD_DC_SI) |
4469 | case CHIP_TAHITI: | |
4470 | case CHIP_PITCAIRN: | |
4471 | case CHIP_VERDE: | |
4472 | case CHIP_OLAND: | |
4473 | if (dce60_register_irq_handlers(dm->adev)) { | |
4474 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4475 | goto fail; | |
4476 | } | |
4477 | break; | |
4478 | #endif | |
4562236b HW |
4479 | case CHIP_BONAIRE: |
4480 | case CHIP_HAWAII: | |
cd4b356f AD |
4481 | case CHIP_KAVERI: |
4482 | case CHIP_KABINI: | |
4483 | case CHIP_MULLINS: | |
4562236b HW |
4484 | case CHIP_TONGA: |
4485 | case CHIP_FIJI: | |
4486 | case CHIP_CARRIZO: | |
4487 | case CHIP_STONEY: | |
4488 | case CHIP_POLARIS11: | |
4489 | case CHIP_POLARIS10: | |
b264d345 | 4490 | case CHIP_POLARIS12: |
7737de91 | 4491 | case CHIP_VEGAM: |
2c8ad2d5 | 4492 | case CHIP_VEGA10: |
2325ff30 | 4493 | case CHIP_VEGA12: |
1fe6bf2f | 4494 | case CHIP_VEGA20: |
4562236b HW |
4495 | if (dce110_register_irq_handlers(dm->adev)) { |
4496 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
cd8a2ae8 | 4497 | goto fail; |
4562236b HW |
4498 | } |
4499 | break; | |
4500 | default: | |
1d789535 | 4501 | switch (adev->ip_versions[DCE_HWIP][0]) { |
559f591d AD |
4502 | case IP_VERSION(1, 0, 0): |
4503 | case IP_VERSION(1, 0, 1): | |
c08182f2 AD |
4504 | case IP_VERSION(2, 0, 2): |
4505 | case IP_VERSION(2, 0, 3): | |
4506 | case IP_VERSION(2, 0, 0): | |
4507 | case IP_VERSION(2, 1, 0): | |
4508 | case IP_VERSION(3, 0, 0): | |
4509 | case IP_VERSION(3, 0, 2): | |
4510 | case IP_VERSION(3, 0, 3): | |
4511 | case IP_VERSION(3, 0, 1): | |
4512 | case IP_VERSION(3, 1, 2): | |
4513 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4514 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4515 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4516 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4517 | case IP_VERSION(3, 2, 0): |
4518 | case IP_VERSION(3, 2, 1): | |
c08182f2 AD |
4519 | if (dcn10_register_irq_handlers(dm->adev)) { |
4520 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4521 | goto fail; | |
4522 | } | |
4523 | break; | |
4524 | default: | |
2cbc6f42 | 4525 | DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", |
1d789535 | 4526 | adev->ip_versions[DCE_HWIP][0]); |
2cbc6f42 | 4527 | goto fail; |
c08182f2 | 4528 | } |
2cbc6f42 | 4529 | break; |
4562236b HW |
4530 | } |
4531 | ||
4562236b | 4532 | return 0; |
cd8a2ae8 | 4533 | fail: |
4562236b | 4534 | kfree(aencoder); |
4562236b | 4535 | kfree(aconnector); |
54087768 | 4536 | |
59d0f396 | 4537 | return -EINVAL; |
4562236b HW |
4538 | } |
4539 | ||
7578ecda | 4540 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) |
4562236b | 4541 | { |
eb3dc897 | 4542 | drm_atomic_private_obj_fini(&dm->atomic_obj); |
4562236b HW |
4543 | } |
4544 | ||
4545 | /****************************************************************************** | |
4546 | * amdgpu_display_funcs functions | |
4547 | *****************************************************************************/ | |
4548 | ||
1f6010a9 | 4549 | /* |
4562236b HW |
4550 | * dm_bandwidth_update - program display watermarks |
4551 | * | |
4552 | * @adev: amdgpu_device pointer | |
4553 | * | |
4554 | * Calculate and program the display watermarks and line buffer allocation. | |
4555 | */ | |
4556 | static void dm_bandwidth_update(struct amdgpu_device *adev) | |
4557 | { | |
49c07a99 | 4558 | /* TODO: implement later */ |
4562236b HW |
4559 | } |
4560 | ||
39cc5be2 | 4561 | static const struct amdgpu_display_funcs dm_display_funcs = { |
4562236b HW |
4562 | .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ |
4563 | .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ | |
7b42573b HW |
4564 | .backlight_set_level = NULL, /* never called for DC */ |
4565 | .backlight_get_level = NULL, /* never called for DC */ | |
4562236b HW |
4566 | .hpd_sense = NULL,/* called unconditionally */ |
4567 | .hpd_set_polarity = NULL, /* called unconditionally */ | |
4568 | .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
4569 | .page_flip_get_scanoutpos = |
4570 | dm_crtc_get_scanoutpos,/* called unconditionally */ | |
4571 | .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ | |
4572 | .add_connector = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
4573 | }; |
4574 | ||
4575 | #if defined(CONFIG_DEBUG_KERNEL_DC) | |
4576 | ||
3ee6b26b AD |
4577 | static ssize_t s3_debug_store(struct device *device, |
4578 | struct device_attribute *attr, | |
4579 | const char *buf, | |
4580 | size_t count) | |
4562236b HW |
4581 | { |
4582 | int ret; | |
4583 | int s3_state; | |
ef1de361 | 4584 | struct drm_device *drm_dev = dev_get_drvdata(device); |
1348969a | 4585 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
4562236b HW |
4586 | |
4587 | ret = kstrtoint(buf, 0, &s3_state); | |
4588 | ||
4589 | if (ret == 0) { | |
4590 | if (s3_state) { | |
4591 | dm_resume(adev); | |
4a580877 | 4592 | drm_kms_helper_hotplug_event(adev_to_drm(adev)); |
4562236b HW |
4593 | } else |
4594 | dm_suspend(adev); | |
4595 | } | |
4596 | ||
4597 | return ret == 0 ? count : 0; | |
4598 | } | |
4599 | ||
4600 | DEVICE_ATTR_WO(s3_debug); | |
4601 | ||
4602 | #endif | |
4603 | ||
a7ab3451 ML |
4604 | static int dm_init_microcode(struct amdgpu_device *adev) |
4605 | { | |
4606 | char *fw_name_dmub; | |
4607 | int r; | |
4608 | ||
4609 | switch (adev->ip_versions[DCE_HWIP][0]) { | |
4610 | case IP_VERSION(2, 1, 0): | |
4611 | fw_name_dmub = FIRMWARE_RENOIR_DMUB; | |
4612 | if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) | |
4613 | fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; | |
4614 | break; | |
4615 | case IP_VERSION(3, 0, 0): | |
4616 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) | |
4617 | fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; | |
4618 | else | |
4619 | fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; | |
4620 | break; | |
4621 | case IP_VERSION(3, 0, 1): | |
4622 | fw_name_dmub = FIRMWARE_VANGOGH_DMUB; | |
4623 | break; | |
4624 | case IP_VERSION(3, 0, 2): | |
4625 | fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; | |
4626 | break; | |
4627 | case IP_VERSION(3, 0, 3): | |
4628 | fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; | |
4629 | break; | |
4630 | case IP_VERSION(3, 1, 2): | |
4631 | case IP_VERSION(3, 1, 3): | |
4632 | fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; | |
4633 | break; | |
4634 | case IP_VERSION(3, 1, 4): | |
4635 | fw_name_dmub = FIRMWARE_DCN_314_DMUB; | |
4636 | break; | |
4637 | case IP_VERSION(3, 1, 5): | |
4638 | fw_name_dmub = FIRMWARE_DCN_315_DMUB; | |
4639 | break; | |
4640 | case IP_VERSION(3, 1, 6): | |
4641 | fw_name_dmub = FIRMWARE_DCN316_DMUB; | |
4642 | break; | |
4643 | case IP_VERSION(3, 2, 0): | |
4644 | fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; | |
4645 | break; | |
4646 | case IP_VERSION(3, 2, 1): | |
4647 | fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; | |
4648 | break; | |
4649 | default: | |
4650 | /* ASIC doesn't support DMUB. */ | |
4651 | return 0; | |
4652 | } | |
4653 | r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); | |
4654 | if (r) | |
4655 | DRM_ERROR("DMUB firmware loading failed: %d\n", r); | |
4656 | return r; | |
4657 | } | |
4658 | ||
4562236b HW |
4659 | static int dm_early_init(void *handle) |
4660 | { | |
4661 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
44900af0 AD |
4662 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
4663 | struct atom_context *ctx = mode_info->atom_context; | |
4664 | int index = GetIndexIntoMasterTable(DATA, Object_Header); | |
4665 | u16 data_offset; | |
4666 | ||
4667 | /* if there is no object header, skip DM */ | |
4668 | if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { | |
4669 | adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; | |
4670 | dev_info(adev->dev, "No object header, skipping DM\n"); | |
4671 | return -ENOENT; | |
4672 | } | |
4562236b | 4673 | |
4562236b | 4674 | switch (adev->asic_type) { |
55e56389 MR |
4675 | #if defined(CONFIG_DRM_AMD_DC_SI) |
4676 | case CHIP_TAHITI: | |
4677 | case CHIP_PITCAIRN: | |
4678 | case CHIP_VERDE: | |
4679 | adev->mode_info.num_crtc = 6; | |
4680 | adev->mode_info.num_hpd = 6; | |
4681 | adev->mode_info.num_dig = 6; | |
4682 | break; | |
4683 | case CHIP_OLAND: | |
4684 | adev->mode_info.num_crtc = 2; | |
4685 | adev->mode_info.num_hpd = 2; | |
4686 | adev->mode_info.num_dig = 2; | |
4687 | break; | |
4688 | #endif | |
4562236b HW |
4689 | case CHIP_BONAIRE: |
4690 | case CHIP_HAWAII: | |
4691 | adev->mode_info.num_crtc = 6; | |
4692 | adev->mode_info.num_hpd = 6; | |
4693 | adev->mode_info.num_dig = 6; | |
4562236b | 4694 | break; |
cd4b356f AD |
4695 | case CHIP_KAVERI: |
4696 | adev->mode_info.num_crtc = 4; | |
4697 | adev->mode_info.num_hpd = 6; | |
4698 | adev->mode_info.num_dig = 7; | |
cd4b356f AD |
4699 | break; |
4700 | case CHIP_KABINI: | |
4701 | case CHIP_MULLINS: | |
4702 | adev->mode_info.num_crtc = 2; | |
4703 | adev->mode_info.num_hpd = 6; | |
4704 | adev->mode_info.num_dig = 6; | |
cd4b356f | 4705 | break; |
4562236b HW |
4706 | case CHIP_FIJI: |
4707 | case CHIP_TONGA: | |
4708 | adev->mode_info.num_crtc = 6; | |
4709 | adev->mode_info.num_hpd = 6; | |
4710 | adev->mode_info.num_dig = 7; | |
4562236b HW |
4711 | break; |
4712 | case CHIP_CARRIZO: | |
4713 | adev->mode_info.num_crtc = 3; | |
4714 | adev->mode_info.num_hpd = 6; | |
4715 | adev->mode_info.num_dig = 9; | |
4562236b HW |
4716 | break; |
4717 | case CHIP_STONEY: | |
4718 | adev->mode_info.num_crtc = 2; | |
4719 | adev->mode_info.num_hpd = 6; | |
4720 | adev->mode_info.num_dig = 9; | |
4562236b HW |
4721 | break; |
4722 | case CHIP_POLARIS11: | |
b264d345 | 4723 | case CHIP_POLARIS12: |
4562236b HW |
4724 | adev->mode_info.num_crtc = 5; |
4725 | adev->mode_info.num_hpd = 5; | |
4726 | adev->mode_info.num_dig = 5; | |
4562236b HW |
4727 | break; |
4728 | case CHIP_POLARIS10: | |
7737de91 | 4729 | case CHIP_VEGAM: |
4562236b HW |
4730 | adev->mode_info.num_crtc = 6; |
4731 | adev->mode_info.num_hpd = 6; | |
4732 | adev->mode_info.num_dig = 6; | |
4562236b | 4733 | break; |
2c8ad2d5 | 4734 | case CHIP_VEGA10: |
2325ff30 | 4735 | case CHIP_VEGA12: |
1fe6bf2f | 4736 | case CHIP_VEGA20: |
2c8ad2d5 AD |
4737 | adev->mode_info.num_crtc = 6; |
4738 | adev->mode_info.num_hpd = 6; | |
4739 | adev->mode_info.num_dig = 6; | |
4740 | break; | |
4562236b | 4741 | default: |
cae5c1ab | 4742 | |
1d789535 | 4743 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
4744 | case IP_VERSION(2, 0, 2): |
4745 | case IP_VERSION(3, 0, 0): | |
4746 | adev->mode_info.num_crtc = 6; | |
4747 | adev->mode_info.num_hpd = 6; | |
4748 | adev->mode_info.num_dig = 6; | |
4749 | break; | |
4750 | case IP_VERSION(2, 0, 0): | |
4751 | case IP_VERSION(3, 0, 2): | |
4752 | adev->mode_info.num_crtc = 5; | |
4753 | adev->mode_info.num_hpd = 5; | |
4754 | adev->mode_info.num_dig = 5; | |
4755 | break; | |
4756 | case IP_VERSION(2, 0, 3): | |
4757 | case IP_VERSION(3, 0, 3): | |
4758 | adev->mode_info.num_crtc = 2; | |
4759 | adev->mode_info.num_hpd = 2; | |
4760 | adev->mode_info.num_dig = 2; | |
4761 | break; | |
559f591d AD |
4762 | case IP_VERSION(1, 0, 0): |
4763 | case IP_VERSION(1, 0, 1): | |
c08182f2 AD |
4764 | case IP_VERSION(3, 0, 1): |
4765 | case IP_VERSION(2, 1, 0): | |
4766 | case IP_VERSION(3, 1, 2): | |
4767 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4768 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4769 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4770 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4771 | case IP_VERSION(3, 2, 0): |
4772 | case IP_VERSION(3, 2, 1): | |
c08182f2 AD |
4773 | adev->mode_info.num_crtc = 4; |
4774 | adev->mode_info.num_hpd = 4; | |
4775 | adev->mode_info.num_dig = 4; | |
4776 | break; | |
4777 | default: | |
2cbc6f42 | 4778 | DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", |
1d789535 | 4779 | adev->ip_versions[DCE_HWIP][0]); |
2cbc6f42 | 4780 | return -EINVAL; |
c08182f2 | 4781 | } |
2cbc6f42 | 4782 | break; |
4562236b HW |
4783 | } |
4784 | ||
39cc5be2 AD |
4785 | if (adev->mode_info.funcs == NULL) |
4786 | adev->mode_info.funcs = &dm_display_funcs; | |
4787 | ||
1f6010a9 DF |
4788 | /* |
4789 | * Note: Do NOT change adev->audio_endpt_rreg and | |
4562236b | 4790 | * adev->audio_endpt_wreg because they are initialised in |
1f6010a9 DF |
4791 | * amdgpu_device_init() |
4792 | */ | |
4562236b HW |
4793 | #if defined(CONFIG_DEBUG_KERNEL_DC) |
4794 | device_create_file( | |
4a580877 | 4795 | adev_to_drm(adev)->dev, |
4562236b HW |
4796 | &dev_attr_s3_debug); |
4797 | #endif | |
d09ef243 | 4798 | adev->dc_enabled = true; |
4562236b | 4799 | |
a7ab3451 | 4800 | return dm_init_microcode(adev); |
4562236b HW |
4801 | } |
4802 | ||
e7b07cee HW |
4803 | static bool modereset_required(struct drm_crtc_state *crtc_state) |
4804 | { | |
2afda735 | 4805 | return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); |
e7b07cee HW |
4806 | } |
4807 | ||
7578ecda | 4808 | static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) |
e7b07cee HW |
4809 | { |
4810 | drm_encoder_cleanup(encoder); | |
4811 | kfree(encoder); | |
4812 | } | |
4813 | ||
4814 | static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { | |
4815 | .destroy = amdgpu_dm_encoder_destroy, | |
4816 | }; | |
4817 | ||
5d945cbc RS |
4818 | static int |
4819 | fill_plane_color_attributes(const struct drm_plane_state *plane_state, | |
4820 | const enum surface_pixel_format format, | |
4821 | enum dc_color_space *color_space) | |
6300b3bd | 4822 | { |
5d945cbc | 4823 | bool full_range; |
6300b3bd | 4824 | |
5d945cbc RS |
4825 | *color_space = COLOR_SPACE_SRGB; |
4826 | ||
4827 | /* DRM color properties only affect non-RGB formats. */ | |
4828 | if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) | |
4829 | return 0; | |
4830 | ||
4831 | full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); | |
4832 | ||
4833 | switch (plane_state->color_encoding) { | |
4834 | case DRM_COLOR_YCBCR_BT601: | |
4835 | if (full_range) | |
4836 | *color_space = COLOR_SPACE_YCBCR601; | |
4837 | else | |
4838 | *color_space = COLOR_SPACE_YCBCR601_LIMITED; | |
6300b3bd MK |
4839 | break; |
4840 | ||
5d945cbc RS |
4841 | case DRM_COLOR_YCBCR_BT709: |
4842 | if (full_range) | |
4843 | *color_space = COLOR_SPACE_YCBCR709; | |
4844 | else | |
4845 | *color_space = COLOR_SPACE_YCBCR709_LIMITED; | |
6300b3bd MK |
4846 | break; |
4847 | ||
5d945cbc RS |
4848 | case DRM_COLOR_YCBCR_BT2020: |
4849 | if (full_range) | |
4850 | *color_space = COLOR_SPACE_2020_YCBCR; | |
4851 | else | |
4852 | return -EINVAL; | |
6300b3bd | 4853 | break; |
6300b3bd | 4854 | |
5d945cbc RS |
4855 | default: |
4856 | return -EINVAL; | |
4857 | } | |
6300b3bd | 4858 | |
5d945cbc | 4859 | return 0; |
6300b3bd MK |
4860 | } |
4861 | ||
5d945cbc RS |
4862 | static int |
4863 | fill_dc_plane_info_and_addr(struct amdgpu_device *adev, | |
4864 | const struct drm_plane_state *plane_state, | |
ae67558b | 4865 | const u64 tiling_flags, |
5d945cbc RS |
4866 | struct dc_plane_info *plane_info, |
4867 | struct dc_plane_address *address, | |
4868 | bool tmz_surface, | |
4869 | bool force_disable_dcc) | |
e7b07cee | 4870 | { |
5d945cbc RS |
4871 | const struct drm_framebuffer *fb = plane_state->fb; |
4872 | const struct amdgpu_framebuffer *afb = | |
4873 | to_amdgpu_framebuffer(plane_state->fb); | |
4874 | int ret; | |
e7b07cee | 4875 | |
5d945cbc | 4876 | memset(plane_info, 0, sizeof(*plane_info)); |
e7b07cee | 4877 | |
5d945cbc RS |
4878 | switch (fb->format->format) { |
4879 | case DRM_FORMAT_C8: | |
4880 | plane_info->format = | |
4881 | SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; | |
4882 | break; | |
4883 | case DRM_FORMAT_RGB565: | |
4884 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; | |
4885 | break; | |
4886 | case DRM_FORMAT_XRGB8888: | |
4887 | case DRM_FORMAT_ARGB8888: | |
4888 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; | |
4889 | break; | |
4890 | case DRM_FORMAT_XRGB2101010: | |
4891 | case DRM_FORMAT_ARGB2101010: | |
4892 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; | |
4893 | break; | |
4894 | case DRM_FORMAT_XBGR2101010: | |
4895 | case DRM_FORMAT_ABGR2101010: | |
4896 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; | |
4897 | break; | |
4898 | case DRM_FORMAT_XBGR8888: | |
4899 | case DRM_FORMAT_ABGR8888: | |
4900 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; | |
4901 | break; | |
4902 | case DRM_FORMAT_NV21: | |
4903 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; | |
4904 | break; | |
4905 | case DRM_FORMAT_NV12: | |
4906 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; | |
4907 | break; | |
4908 | case DRM_FORMAT_P010: | |
4909 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; | |
4910 | break; | |
4911 | case DRM_FORMAT_XRGB16161616F: | |
4912 | case DRM_FORMAT_ARGB16161616F: | |
4913 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; | |
4914 | break; | |
4915 | case DRM_FORMAT_XBGR16161616F: | |
4916 | case DRM_FORMAT_ABGR16161616F: | |
4917 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; | |
4918 | break; | |
4919 | case DRM_FORMAT_XRGB16161616: | |
4920 | case DRM_FORMAT_ARGB16161616: | |
4921 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; | |
4922 | break; | |
4923 | case DRM_FORMAT_XBGR16161616: | |
4924 | case DRM_FORMAT_ABGR16161616: | |
4925 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; | |
4926 | break; | |
4927 | default: | |
4928 | DRM_ERROR( | |
4929 | "Unsupported screen format %p4cc\n", | |
4930 | &fb->format->format); | |
d89f6048 | 4931 | return -EINVAL; |
5d945cbc | 4932 | } |
d89f6048 | 4933 | |
5d945cbc RS |
4934 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { |
4935 | case DRM_MODE_ROTATE_0: | |
4936 | plane_info->rotation = ROTATION_ANGLE_0; | |
4937 | break; | |
4938 | case DRM_MODE_ROTATE_90: | |
4939 | plane_info->rotation = ROTATION_ANGLE_90; | |
4940 | break; | |
4941 | case DRM_MODE_ROTATE_180: | |
4942 | plane_info->rotation = ROTATION_ANGLE_180; | |
4943 | break; | |
4944 | case DRM_MODE_ROTATE_270: | |
4945 | plane_info->rotation = ROTATION_ANGLE_270; | |
4946 | break; | |
4947 | default: | |
4948 | plane_info->rotation = ROTATION_ANGLE_0; | |
4949 | break; | |
4950 | } | |
695af5f9 | 4951 | |
695af5f9 | 4952 | |
5d945cbc RS |
4953 | plane_info->visible = true; |
4954 | plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; | |
e7b07cee | 4955 | |
22c42b0e | 4956 | plane_info->layer_index = plane_state->normalized_zpos; |
e7b07cee | 4957 | |
5d945cbc RS |
4958 | ret = fill_plane_color_attributes(plane_state, plane_info->format, |
4959 | &plane_info->color_space); | |
4960 | if (ret) | |
4961 | return ret; | |
e7b07cee | 4962 | |
8bf0d9cd | 4963 | ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, |
5d945cbc RS |
4964 | plane_info->rotation, tiling_flags, |
4965 | &plane_info->tiling_info, | |
4966 | &plane_info->plane_size, | |
4967 | &plane_info->dcc, address, | |
4968 | tmz_surface, force_disable_dcc); | |
4969 | if (ret) | |
4970 | return ret; | |
e7b07cee | 4971 | |
8bf0d9cd | 4972 | amdgpu_dm_plane_fill_blending_from_plane_state( |
5d945cbc RS |
4973 | plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, |
4974 | &plane_info->global_alpha, &plane_info->global_alpha_value); | |
e7b07cee | 4975 | |
5d945cbc RS |
4976 | return 0; |
4977 | } | |
e7b07cee | 4978 | |
5d945cbc RS |
4979 | static int fill_dc_plane_attributes(struct amdgpu_device *adev, |
4980 | struct dc_plane_state *dc_plane_state, | |
4981 | struct drm_plane_state *plane_state, | |
4982 | struct drm_crtc_state *crtc_state) | |
4983 | { | |
4984 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); | |
4985 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; | |
4986 | struct dc_scaling_info scaling_info; | |
4987 | struct dc_plane_info plane_info; | |
4988 | int ret; | |
4989 | bool force_disable_dcc = false; | |
6300b3bd | 4990 | |
8bf0d9cd | 4991 | ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); |
5d945cbc RS |
4992 | if (ret) |
4993 | return ret; | |
e7b07cee | 4994 | |
5d945cbc RS |
4995 | dc_plane_state->src_rect = scaling_info.src_rect; |
4996 | dc_plane_state->dst_rect = scaling_info.dst_rect; | |
4997 | dc_plane_state->clip_rect = scaling_info.clip_rect; | |
4998 | dc_plane_state->scaling_quality = scaling_info.scaling_quality; | |
6491f0c0 | 4999 | |
5d945cbc RS |
5000 | force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; |
5001 | ret = fill_dc_plane_info_and_addr(adev, plane_state, | |
5002 | afb->tiling_flags, | |
5003 | &plane_info, | |
5004 | &dc_plane_state->address, | |
5005 | afb->tmz_surface, | |
5006 | force_disable_dcc); | |
5007 | if (ret) | |
5008 | return ret; | |
6491f0c0 | 5009 | |
5d945cbc RS |
5010 | dc_plane_state->format = plane_info.format; |
5011 | dc_plane_state->color_space = plane_info.color_space; | |
5012 | dc_plane_state->format = plane_info.format; | |
5013 | dc_plane_state->plane_size = plane_info.plane_size; | |
5014 | dc_plane_state->rotation = plane_info.rotation; | |
5015 | dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; | |
5016 | dc_plane_state->stereo_format = plane_info.stereo_format; | |
5017 | dc_plane_state->tiling_info = plane_info.tiling_info; | |
5018 | dc_plane_state->visible = plane_info.visible; | |
5019 | dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; | |
5020 | dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; | |
5021 | dc_plane_state->global_alpha = plane_info.global_alpha; | |
5022 | dc_plane_state->global_alpha_value = plane_info.global_alpha_value; | |
5023 | dc_plane_state->dcc = plane_info.dcc; | |
22c42b0e | 5024 | dc_plane_state->layer_index = plane_info.layer_index; |
5d945cbc | 5025 | dc_plane_state->flip_int_enabled = true; |
6491f0c0 | 5026 | |
695af5f9 | 5027 | /* |
5d945cbc RS |
5028 | * Always set input transfer function, since plane state is refreshed |
5029 | * every time. | |
695af5f9 | 5030 | */ |
5d945cbc RS |
5031 | ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); |
5032 | if (ret) | |
5033 | return ret; | |
e7b07cee | 5034 | |
695af5f9 | 5035 | return 0; |
4562236b | 5036 | } |
695af5f9 | 5037 | |
30ebe415 HM |
5038 | static inline void fill_dc_dirty_rect(struct drm_plane *plane, |
5039 | struct rect *dirty_rect, int32_t x, | |
ae67558b | 5040 | s32 y, s32 width, s32 height, |
30ebe415 HM |
5041 | int *i, bool ffu) |
5042 | { | |
af22d6a8 | 5043 | WARN_ON(*i >= DC_MAX_DIRTY_RECTS); |
30ebe415 HM |
5044 | |
5045 | dirty_rect->x = x; | |
5046 | dirty_rect->y = y; | |
5047 | dirty_rect->width = width; | |
5048 | dirty_rect->height = height; | |
5049 | ||
5050 | if (ffu) | |
5051 | drm_dbg(plane->dev, | |
5052 | "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", | |
5053 | plane->base.id, width, height); | |
5054 | else | |
5055 | drm_dbg(plane->dev, | |
5056 | "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", | |
5057 | plane->base.id, x, y, width, height); | |
5058 | ||
30ebe415 HM |
5059 | (*i)++; |
5060 | } | |
5061 | ||
5d945cbc RS |
5062 | /** |
5063 | * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates | |
5064 | * | |
5065 | * @plane: DRM plane containing dirty regions that need to be flushed to the eDP | |
5066 | * remote fb | |
5067 | * @old_plane_state: Old state of @plane | |
5068 | * @new_plane_state: New state of @plane | |
5069 | * @crtc_state: New state of CRTC connected to the @plane | |
5070 | * @flip_addrs: DC flip tracking struct, which also tracts dirty rects | |
d6ed6d0d | 5071 | * @dirty_regions_changed: dirty regions changed |
5d945cbc RS |
5072 | * |
5073 | * For PSR SU, DC informs the DMUB uController of dirty rectangle regions | |
5074 | * (referred to as "damage clips" in DRM nomenclature) that require updating on | |
5075 | * the eDP remote buffer. The responsibility of specifying the dirty regions is | |
5076 | * amdgpu_dm's. | |
5077 | * | |
5078 | * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the | |
5079 | * plane with regions that require flushing to the eDP remote buffer. In | |
5080 | * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - | |
5081 | * implicitly provide damage clips without any client support via the plane | |
5082 | * bounds. | |
5d945cbc RS |
5083 | */ |
5084 | static void fill_dc_dirty_rects(struct drm_plane *plane, | |
5085 | struct drm_plane_state *old_plane_state, | |
5086 | struct drm_plane_state *new_plane_state, | |
5087 | struct drm_crtc_state *crtc_state, | |
d6ed6d0d TC |
5088 | struct dc_flip_addrs *flip_addrs, |
5089 | bool *dirty_regions_changed) | |
5d945cbc RS |
5090 | { |
5091 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); | |
5092 | struct rect *dirty_rects = flip_addrs->dirty_rects; | |
ae67558b | 5093 | u32 num_clips; |
30ebe415 | 5094 | struct drm_mode_rect *clips; |
5d945cbc RS |
5095 | bool bb_changed; |
5096 | bool fb_changed; | |
ae67558b | 5097 | u32 i = 0; |
d6ed6d0d | 5098 | *dirty_regions_changed = false; |
e7b07cee | 5099 | |
7cc191ee LL |
5100 | /* |
5101 | * Cursor plane has it's own dirty rect update interface. See | |
5102 | * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data | |
5103 | */ | |
5104 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
5105 | return; | |
5106 | ||
30ebe415 HM |
5107 | num_clips = drm_plane_get_damage_clips_count(new_plane_state); |
5108 | clips = drm_plane_get_damage_clips(new_plane_state); | |
5109 | ||
7cc191ee | 5110 | if (!dm_crtc_state->mpo_requested) { |
30ebe415 HM |
5111 | if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) |
5112 | goto ffu; | |
5113 | ||
5114 | for (; flip_addrs->dirty_rect_count < num_clips; clips++) | |
5115 | fill_dc_dirty_rect(new_plane_state->plane, | |
566b6577 BC |
5116 | &dirty_rects[flip_addrs->dirty_rect_count], |
5117 | clips->x1, clips->y1, | |
5118 | clips->x2 - clips->x1, clips->y2 - clips->y1, | |
30ebe415 HM |
5119 | &flip_addrs->dirty_rect_count, |
5120 | false); | |
7cc191ee LL |
5121 | return; |
5122 | } | |
5123 | ||
5124 | /* | |
5125 | * MPO is requested. Add entire plane bounding box to dirty rects if | |
5126 | * flipped to or damaged. | |
5127 | * | |
5128 | * If plane is moved or resized, also add old bounding box to dirty | |
5129 | * rects. | |
5130 | */ | |
7cc191ee LL |
5131 | fb_changed = old_plane_state->fb->base.id != |
5132 | new_plane_state->fb->base.id; | |
5133 | bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || | |
5134 | old_plane_state->crtc_y != new_plane_state->crtc_y || | |
5135 | old_plane_state->crtc_w != new_plane_state->crtc_w || | |
5136 | old_plane_state->crtc_h != new_plane_state->crtc_h); | |
5137 | ||
30ebe415 HM |
5138 | drm_dbg(plane->dev, |
5139 | "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", | |
5140 | new_plane_state->plane->base.id, | |
5141 | bb_changed, fb_changed, num_clips); | |
7cc191ee | 5142 | |
d6ed6d0d TC |
5143 | *dirty_regions_changed = bb_changed; |
5144 | ||
af22d6a8 HM |
5145 | if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) |
5146 | goto ffu; | |
5147 | ||
7cc191ee | 5148 | if (bb_changed) { |
30ebe415 HM |
5149 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], |
5150 | new_plane_state->crtc_x, | |
5151 | new_plane_state->crtc_y, | |
5152 | new_plane_state->crtc_w, | |
5153 | new_plane_state->crtc_h, &i, false); | |
5154 | ||
5155 | /* Add old plane bounding-box if plane is moved or resized */ | |
5156 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], | |
5157 | old_plane_state->crtc_x, | |
5158 | old_plane_state->crtc_y, | |
5159 | old_plane_state->crtc_w, | |
5160 | old_plane_state->crtc_h, &i, false); | |
5161 | } | |
5162 | ||
5163 | if (num_clips) { | |
5164 | for (; i < num_clips; clips++) | |
5165 | fill_dc_dirty_rect(new_plane_state->plane, | |
5166 | &dirty_rects[i], clips->x1, | |
5167 | clips->y1, clips->x2 - clips->x1, | |
5168 | clips->y2 - clips->y1, &i, false); | |
5169 | } else if (fb_changed && !bb_changed) { | |
5170 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], | |
5171 | new_plane_state->crtc_x, | |
5172 | new_plane_state->crtc_y, | |
5173 | new_plane_state->crtc_w, | |
5174 | new_plane_state->crtc_h, &i, false); | |
5175 | } | |
5176 | ||
7cc191ee | 5177 | flip_addrs->dirty_rect_count = i; |
30ebe415 HM |
5178 | return; |
5179 | ||
5180 | ffu: | |
5181 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, | |
5182 | dm_crtc_state->base.mode.crtc_hdisplay, | |
5183 | dm_crtc_state->base.mode.crtc_vdisplay, | |
5184 | &flip_addrs->dirty_rect_count, true); | |
7cc191ee LL |
5185 | } |
5186 | ||
3ee6b26b AD |
5187 | static void update_stream_scaling_settings(const struct drm_display_mode *mode, |
5188 | const struct dm_connector_state *dm_state, | |
5189 | struct dc_stream_state *stream) | |
e7b07cee HW |
5190 | { |
5191 | enum amdgpu_rmx_type rmx_type; | |
5192 | ||
5193 | struct rect src = { 0 }; /* viewport in composition space*/ | |
5194 | struct rect dst = { 0 }; /* stream addressable area */ | |
5195 | ||
5196 | /* no mode. nothing to be done */ | |
5197 | if (!mode) | |
5198 | return; | |
5199 | ||
5200 | /* Full screen scaling by default */ | |
5201 | src.width = mode->hdisplay; | |
5202 | src.height = mode->vdisplay; | |
5203 | dst.width = stream->timing.h_addressable; | |
5204 | dst.height = stream->timing.v_addressable; | |
5205 | ||
f4791779 HW |
5206 | if (dm_state) { |
5207 | rmx_type = dm_state->scaling; | |
5208 | if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { | |
5209 | if (src.width * dst.height < | |
5210 | src.height * dst.width) { | |
5211 | /* height needs less upscaling/more downscaling */ | |
5212 | dst.width = src.width * | |
5213 | dst.height / src.height; | |
5214 | } else { | |
5215 | /* width needs less upscaling/more downscaling */ | |
5216 | dst.height = src.height * | |
5217 | dst.width / src.width; | |
5218 | } | |
5219 | } else if (rmx_type == RMX_CENTER) { | |
5220 | dst = src; | |
e7b07cee | 5221 | } |
e7b07cee | 5222 | |
f4791779 HW |
5223 | dst.x = (stream->timing.h_addressable - dst.width) / 2; |
5224 | dst.y = (stream->timing.v_addressable - dst.height) / 2; | |
e7b07cee | 5225 | |
f4791779 HW |
5226 | if (dm_state->underscan_enable) { |
5227 | dst.x += dm_state->underscan_hborder / 2; | |
5228 | dst.y += dm_state->underscan_vborder / 2; | |
5229 | dst.width -= dm_state->underscan_hborder; | |
5230 | dst.height -= dm_state->underscan_vborder; | |
5231 | } | |
e7b07cee HW |
5232 | } |
5233 | ||
5234 | stream->src = src; | |
5235 | stream->dst = dst; | |
5236 | ||
4711c033 LT |
5237 | DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", |
5238 | dst.x, dst.y, dst.width, dst.height); | |
e7b07cee HW |
5239 | |
5240 | } | |
5241 | ||
3ee6b26b | 5242 | static enum dc_color_depth |
42ba01fc | 5243 | convert_color_depth_from_display_info(const struct drm_connector *connector, |
cbd14ae7 | 5244 | bool is_y420, int requested_bpc) |
e7b07cee | 5245 | { |
ae67558b | 5246 | u8 bpc; |
01c22997 | 5247 | |
1bc22f20 SW |
5248 | if (is_y420) { |
5249 | bpc = 8; | |
5250 | ||
5251 | /* Cap display bpc based on HDMI 2.0 HF-VSDB */ | |
5252 | if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) | |
5253 | bpc = 16; | |
5254 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) | |
5255 | bpc = 12; | |
5256 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) | |
5257 | bpc = 10; | |
5258 | } else { | |
5259 | bpc = (uint8_t)connector->display_info.bpc; | |
5260 | /* Assume 8 bpc by default if no bpc is specified. */ | |
5261 | bpc = bpc ? bpc : 8; | |
5262 | } | |
e7b07cee | 5263 | |
cbd14ae7 | 5264 | if (requested_bpc > 0) { |
01c22997 NK |
5265 | /* |
5266 | * Cap display bpc based on the user requested value. | |
5267 | * | |
5268 | * The value for state->max_bpc may not correctly updated | |
5269 | * depending on when the connector gets added to the state | |
5270 | * or if this was called outside of atomic check, so it | |
5271 | * can't be used directly. | |
5272 | */ | |
cbd14ae7 | 5273 | bpc = min_t(u8, bpc, requested_bpc); |
01c22997 | 5274 | |
1825fd34 NK |
5275 | /* Round down to the nearest even number. */ |
5276 | bpc = bpc - (bpc & 1); | |
5277 | } | |
07e3a1cf | 5278 | |
e7b07cee HW |
5279 | switch (bpc) { |
5280 | case 0: | |
1f6010a9 DF |
5281 | /* |
5282 | * Temporary Work around, DRM doesn't parse color depth for | |
e7b07cee HW |
5283 | * EDID revision before 1.4 |
5284 | * TODO: Fix edid parsing | |
5285 | */ | |
5286 | return COLOR_DEPTH_888; | |
5287 | case 6: | |
5288 | return COLOR_DEPTH_666; | |
5289 | case 8: | |
5290 | return COLOR_DEPTH_888; | |
5291 | case 10: | |
5292 | return COLOR_DEPTH_101010; | |
5293 | case 12: | |
5294 | return COLOR_DEPTH_121212; | |
5295 | case 14: | |
5296 | return COLOR_DEPTH_141414; | |
5297 | case 16: | |
5298 | return COLOR_DEPTH_161616; | |
5299 | default: | |
5300 | return COLOR_DEPTH_UNDEFINED; | |
5301 | } | |
5302 | } | |
5303 | ||
3ee6b26b AD |
5304 | static enum dc_aspect_ratio |
5305 | get_aspect_ratio(const struct drm_display_mode *mode_in) | |
e7b07cee | 5306 | { |
e11d4147 LSL |
5307 | /* 1-1 mapping, since both enums follow the HDMI spec. */ |
5308 | return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; | |
e7b07cee HW |
5309 | } |
5310 | ||
3ee6b26b | 5311 | static enum dc_color_space |
2e656827 HW |
5312 | get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, |
5313 | const struct drm_connector_state *connector_state) | |
e7b07cee HW |
5314 | { |
5315 | enum dc_color_space color_space = COLOR_SPACE_SRGB; | |
5316 | ||
2e656827 HW |
5317 | switch (connector_state->colorspace) { |
5318 | case DRM_MODE_COLORIMETRY_BT601_YCC: | |
5319 | if (dc_crtc_timing->flags.Y_ONLY) | |
5320 | color_space = COLOR_SPACE_YCBCR601_LIMITED; | |
5321 | else | |
5322 | color_space = COLOR_SPACE_YCBCR601; | |
5323 | break; | |
5324 | case DRM_MODE_COLORIMETRY_BT709_YCC: | |
5325 | if (dc_crtc_timing->flags.Y_ONLY) | |
5326 | color_space = COLOR_SPACE_YCBCR709_LIMITED; | |
5327 | else | |
5328 | color_space = COLOR_SPACE_YCBCR709; | |
5329 | break; | |
5330 | case DRM_MODE_COLORIMETRY_OPRGB: | |
5331 | color_space = COLOR_SPACE_ADOBERGB; | |
5332 | break; | |
5333 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
5334 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
5335 | if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) | |
5336 | color_space = COLOR_SPACE_2020_RGB_FULLRANGE; | |
5337 | else | |
5338 | color_space = COLOR_SPACE_2020_YCBCR; | |
5339 | break; | |
5340 | case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 | |
5341 | default: | |
5342 | if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { | |
5343 | color_space = COLOR_SPACE_SRGB; | |
e7b07cee HW |
5344 | /* |
5345 | * 27030khz is the separation point between HDTV and SDTV | |
5346 | * according to HDMI spec, we use YCbCr709 and YCbCr601 | |
5347 | * respectively | |
5348 | */ | |
2e656827 | 5349 | } else if (dc_crtc_timing->pix_clk_100hz > 270300) { |
e7b07cee HW |
5350 | if (dc_crtc_timing->flags.Y_ONLY) |
5351 | color_space = | |
5352 | COLOR_SPACE_YCBCR709_LIMITED; | |
5353 | else | |
5354 | color_space = COLOR_SPACE_YCBCR709; | |
5355 | } else { | |
5356 | if (dc_crtc_timing->flags.Y_ONLY) | |
5357 | color_space = | |
5358 | COLOR_SPACE_YCBCR601_LIMITED; | |
5359 | else | |
5360 | color_space = COLOR_SPACE_YCBCR601; | |
5361 | } | |
e7b07cee HW |
5362 | break; |
5363 | } | |
5364 | ||
5365 | return color_space; | |
5366 | } | |
5367 | ||
ea117312 TA |
5368 | static bool adjust_colour_depth_from_display_info( |
5369 | struct dc_crtc_timing *timing_out, | |
5370 | const struct drm_display_info *info) | |
400443e8 | 5371 | { |
ea117312 | 5372 | enum dc_color_depth depth = timing_out->display_color_depth; |
400443e8 | 5373 | int normalized_clk; |
c82eddf8 | 5374 | |
400443e8 | 5375 | do { |
380604e2 | 5376 | normalized_clk = timing_out->pix_clk_100hz / 10; |
400443e8 ML |
5377 | /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ |
5378 | if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) | |
5379 | normalized_clk /= 2; | |
5380 | /* Adjusting pix clock following on HDMI spec based on colour depth */ | |
ea117312 TA |
5381 | switch (depth) { |
5382 | case COLOR_DEPTH_888: | |
5383 | break; | |
400443e8 ML |
5384 | case COLOR_DEPTH_101010: |
5385 | normalized_clk = (normalized_clk * 30) / 24; | |
5386 | break; | |
5387 | case COLOR_DEPTH_121212: | |
5388 | normalized_clk = (normalized_clk * 36) / 24; | |
5389 | break; | |
5390 | case COLOR_DEPTH_161616: | |
5391 | normalized_clk = (normalized_clk * 48) / 24; | |
5392 | break; | |
5393 | default: | |
ea117312 TA |
5394 | /* The above depths are the only ones valid for HDMI. */ |
5395 | return false; | |
400443e8 | 5396 | } |
ea117312 TA |
5397 | if (normalized_clk <= info->max_tmds_clock) { |
5398 | timing_out->display_color_depth = depth; | |
5399 | return true; | |
5400 | } | |
5401 | } while (--depth > COLOR_DEPTH_666); | |
5402 | return false; | |
400443e8 | 5403 | } |
e7b07cee | 5404 | |
42ba01fc NK |
5405 | static void fill_stream_properties_from_drm_display_mode( |
5406 | struct dc_stream_state *stream, | |
5407 | const struct drm_display_mode *mode_in, | |
5408 | const struct drm_connector *connector, | |
5409 | const struct drm_connector_state *connector_state, | |
cbd14ae7 SW |
5410 | const struct dc_stream_state *old_stream, |
5411 | int requested_bpc) | |
e7b07cee HW |
5412 | { |
5413 | struct dc_crtc_timing *timing_out = &stream->timing; | |
fe61a2f1 | 5414 | const struct drm_display_info *info = &connector->display_info; |
d4252eee | 5415 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
1cb1d477 WL |
5416 | struct hdmi_vendor_infoframe hv_frame; |
5417 | struct hdmi_avi_infoframe avi_frame; | |
e7b07cee | 5418 | |
acf83f86 WL |
5419 | memset(&hv_frame, 0, sizeof(hv_frame)); |
5420 | memset(&avi_frame, 0, sizeof(avi_frame)); | |
5421 | ||
e7b07cee HW |
5422 | timing_out->h_border_left = 0; |
5423 | timing_out->h_border_right = 0; | |
5424 | timing_out->v_border_top = 0; | |
5425 | timing_out->v_border_bottom = 0; | |
5426 | /* TODO: un-hardcode */ | |
fe61a2f1 | 5427 | if (drm_mode_is_420_only(info, mode_in) |
ceb3dbb4 | 5428 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
fe61a2f1 | 5429 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
d4252eee SW |
5430 | else if (drm_mode_is_420_also(info, mode_in) |
5431 | && aconnector->force_yuv420_output) | |
5432 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; | |
c03d0b52 | 5433 | else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) |
ceb3dbb4 | 5434 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
e7b07cee HW |
5435 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; |
5436 | else | |
5437 | timing_out->pixel_encoding = PIXEL_ENCODING_RGB; | |
5438 | ||
5439 | timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; | |
5440 | timing_out->display_color_depth = convert_color_depth_from_display_info( | |
cbd14ae7 SW |
5441 | connector, |
5442 | (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), | |
5443 | requested_bpc); | |
e7b07cee HW |
5444 | timing_out->scan_type = SCANNING_TYPE_NODATA; |
5445 | timing_out->hdmi_vic = 0; | |
b333730d | 5446 | |
5d945cbc | 5447 | if (old_stream) { |
b333730d BL |
5448 | timing_out->vic = old_stream->timing.vic; |
5449 | timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; | |
5450 | timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; | |
5451 | } else { | |
5452 | timing_out->vic = drm_match_cea_mode(mode_in); | |
5453 | if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) | |
5454 | timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; | |
5455 | if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) | |
5456 | timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; | |
5457 | } | |
e7b07cee | 5458 | |
1cb1d477 WL |
5459 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
5460 | drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); | |
5461 | timing_out->vic = avi_frame.video_code; | |
5462 | drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); | |
5463 | timing_out->hdmi_vic = hv_frame.vic; | |
5464 | } | |
5465 | ||
fe8858bb NC |
5466 | if (is_freesync_video_mode(mode_in, aconnector)) { |
5467 | timing_out->h_addressable = mode_in->hdisplay; | |
5468 | timing_out->h_total = mode_in->htotal; | |
5469 | timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; | |
5470 | timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; | |
5471 | timing_out->v_total = mode_in->vtotal; | |
5472 | timing_out->v_addressable = mode_in->vdisplay; | |
5473 | timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; | |
5474 | timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; | |
5475 | timing_out->pix_clk_100hz = mode_in->clock * 10; | |
5476 | } else { | |
5477 | timing_out->h_addressable = mode_in->crtc_hdisplay; | |
5478 | timing_out->h_total = mode_in->crtc_htotal; | |
5479 | timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; | |
5480 | timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; | |
5481 | timing_out->v_total = mode_in->crtc_vtotal; | |
5482 | timing_out->v_addressable = mode_in->crtc_vdisplay; | |
5483 | timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; | |
5484 | timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; | |
5485 | timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; | |
5486 | } | |
a85ba005 | 5487 | |
e7b07cee | 5488 | timing_out->aspect_ratio = get_aspect_ratio(mode_in); |
e7b07cee | 5489 | |
e43a432c AK |
5490 | stream->out_transfer_func->type = TF_TYPE_PREDEFINED; |
5491 | stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; | |
ea117312 TA |
5492 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
5493 | if (!adjust_colour_depth_from_display_info(timing_out, info) && | |
5494 | drm_mode_is_420_also(info, mode_in) && | |
5495 | timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { | |
5496 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; | |
5497 | adjust_colour_depth_from_display_info(timing_out, info); | |
5498 | } | |
5499 | } | |
766f1792 | 5500 | |
2e656827 | 5501 | stream->output_color_space = get_output_color_space(timing_out, connector_state); |
e7b07cee HW |
5502 | } |
5503 | ||
3ee6b26b AD |
5504 | static void fill_audio_info(struct audio_info *audio_info, |
5505 | const struct drm_connector *drm_connector, | |
5506 | const struct dc_sink *dc_sink) | |
e7b07cee HW |
5507 | { |
5508 | int i = 0; | |
5509 | int cea_revision = 0; | |
5510 | const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; | |
5511 | ||
5512 | audio_info->manufacture_id = edid_caps->manufacturer_id; | |
5513 | audio_info->product_id = edid_caps->product_id; | |
5514 | ||
5515 | cea_revision = drm_connector->display_info.cea_rev; | |
5516 | ||
090afc1e | 5517 | strscpy(audio_info->display_name, |
d2b2562c | 5518 | edid_caps->display_name, |
090afc1e | 5519 | AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); |
e7b07cee | 5520 | |
b830ebc9 | 5521 | if (cea_revision >= 3) { |
e7b07cee HW |
5522 | audio_info->mode_count = edid_caps->audio_mode_count; |
5523 | ||
5524 | for (i = 0; i < audio_info->mode_count; ++i) { | |
5525 | audio_info->modes[i].format_code = | |
5526 | (enum audio_format_code) | |
5527 | (edid_caps->audio_modes[i].format_code); | |
5528 | audio_info->modes[i].channel_count = | |
5529 | edid_caps->audio_modes[i].channel_count; | |
5530 | audio_info->modes[i].sample_rates.all = | |
5531 | edid_caps->audio_modes[i].sample_rate; | |
5532 | audio_info->modes[i].sample_size = | |
5533 | edid_caps->audio_modes[i].sample_size; | |
5534 | } | |
5535 | } | |
5536 | ||
5537 | audio_info->flags.all = edid_caps->speaker_flags; | |
5538 | ||
5539 | /* TODO: We only check for the progressive mode, check for interlace mode too */ | |
b830ebc9 | 5540 | if (drm_connector->latency_present[0]) { |
e7b07cee HW |
5541 | audio_info->video_latency = drm_connector->video_latency[0]; |
5542 | audio_info->audio_latency = drm_connector->audio_latency[0]; | |
5543 | } | |
5544 | ||
5545 | /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ | |
5546 | ||
5547 | } | |
5548 | ||
3ee6b26b AD |
5549 | static void |
5550 | copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, | |
5551 | struct drm_display_mode *dst_mode) | |
e7b07cee HW |
5552 | { |
5553 | dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; | |
5554 | dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; | |
5555 | dst_mode->crtc_clock = src_mode->crtc_clock; | |
5556 | dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; | |
5557 | dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; | |
b830ebc9 | 5558 | dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; |
e7b07cee HW |
5559 | dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; |
5560 | dst_mode->crtc_htotal = src_mode->crtc_htotal; | |
5561 | dst_mode->crtc_hskew = src_mode->crtc_hskew; | |
5562 | dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; | |
5563 | dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; | |
5564 | dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; | |
5565 | dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; | |
5566 | dst_mode->crtc_vtotal = src_mode->crtc_vtotal; | |
5567 | } | |
5568 | ||
3ee6b26b AD |
5569 | static void |
5570 | decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, | |
5571 | const struct drm_display_mode *native_mode, | |
5572 | bool scale_enabled) | |
e7b07cee HW |
5573 | { |
5574 | if (scale_enabled) { | |
5575 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
5576 | } else if (native_mode->clock == drm_mode->clock && | |
5577 | native_mode->htotal == drm_mode->htotal && | |
5578 | native_mode->vtotal == drm_mode->vtotal) { | |
5579 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
5580 | } else { | |
5581 | /* no scaling nor amdgpu inserted, no need to patch */ | |
5582 | } | |
5583 | } | |
5584 | ||
aed15309 ML |
5585 | static struct dc_sink * |
5586 | create_fake_sink(struct amdgpu_dm_connector *aconnector) | |
2e0ac3d6 | 5587 | { |
2e0ac3d6 | 5588 | struct dc_sink_init_data sink_init_data = { 0 }; |
aed15309 | 5589 | struct dc_sink *sink = NULL; |
c82eddf8 | 5590 | |
2e0ac3d6 HW |
5591 | sink_init_data.link = aconnector->dc_link; |
5592 | sink_init_data.sink_signal = aconnector->dc_link->connector_signal; | |
5593 | ||
5594 | sink = dc_sink_create(&sink_init_data); | |
423788c7 | 5595 | if (!sink) { |
2e0ac3d6 | 5596 | DRM_ERROR("Failed to create sink!\n"); |
aed15309 | 5597 | return NULL; |
423788c7 | 5598 | } |
2e0ac3d6 | 5599 | sink->sink_signal = SIGNAL_TYPE_VIRTUAL; |
423788c7 | 5600 | |
aed15309 | 5601 | return sink; |
2e0ac3d6 HW |
5602 | } |
5603 | ||
fa2123db ML |
5604 | static void set_multisync_trigger_params( |
5605 | struct dc_stream_state *stream) | |
5606 | { | |
ec372186 ML |
5607 | struct dc_stream_state *master = NULL; |
5608 | ||
fa2123db | 5609 | if (stream->triggered_crtc_reset.enabled) { |
ec372186 ML |
5610 | master = stream->triggered_crtc_reset.event_source; |
5611 | stream->triggered_crtc_reset.event = | |
5612 | master->timing.flags.VSYNC_POSITIVE_POLARITY ? | |
5613 | CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; | |
5614 | stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; | |
fa2123db ML |
5615 | } |
5616 | } | |
5617 | ||
5618 | static void set_master_stream(struct dc_stream_state *stream_set[], | |
5619 | int stream_count) | |
5620 | { | |
5621 | int j, highest_rfr = 0, master_stream = 0; | |
5622 | ||
5623 | for (j = 0; j < stream_count; j++) { | |
5624 | if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { | |
5625 | int refresh_rate = 0; | |
5626 | ||
380604e2 | 5627 | refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ |
fa2123db ML |
5628 | (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); |
5629 | if (refresh_rate > highest_rfr) { | |
5630 | highest_rfr = refresh_rate; | |
5631 | master_stream = j; | |
5632 | } | |
5633 | } | |
5634 | } | |
5635 | for (j = 0; j < stream_count; j++) { | |
03736f4c | 5636 | if (stream_set[j]) |
fa2123db ML |
5637 | stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; |
5638 | } | |
5639 | } | |
5640 | ||
5641 | static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) | |
5642 | { | |
5643 | int i = 0; | |
ec372186 | 5644 | struct dc_stream_state *stream; |
fa2123db ML |
5645 | |
5646 | if (context->stream_count < 2) | |
5647 | return; | |
5648 | for (i = 0; i < context->stream_count ; i++) { | |
5649 | if (!context->streams[i]) | |
5650 | continue; | |
1f6010a9 DF |
5651 | /* |
5652 | * TODO: add a function to read AMD VSDB bits and set | |
fa2123db | 5653 | * crtc_sync_master.multi_sync_enabled flag |
1f6010a9 | 5654 | * For now it's set to false |
fa2123db | 5655 | */ |
fa2123db | 5656 | } |
ec372186 | 5657 | |
fa2123db | 5658 | set_master_stream(context->streams, context->stream_count); |
ec372186 ML |
5659 | |
5660 | for (i = 0; i < context->stream_count ; i++) { | |
5661 | stream = context->streams[i]; | |
5662 | ||
5663 | if (!stream) | |
5664 | continue; | |
5665 | ||
5666 | set_multisync_trigger_params(stream); | |
5667 | } | |
fa2123db ML |
5668 | } |
5669 | ||
5d945cbc RS |
5670 | /** |
5671 | * DOC: FreeSync Video | |
5672 | * | |
5673 | * When a userspace application wants to play a video, the content follows a | |
5674 | * standard format definition that usually specifies the FPS for that format. | |
5675 | * The below list illustrates some video format and the expected FPS, | |
5676 | * respectively: | |
5677 | * | |
5678 | * - TV/NTSC (23.976 FPS) | |
5679 | * - Cinema (24 FPS) | |
5680 | * - TV/PAL (25 FPS) | |
5681 | * - TV/NTSC (29.97 FPS) | |
5682 | * - TV/NTSC (30 FPS) | |
5683 | * - Cinema HFR (48 FPS) | |
5684 | * - TV/PAL (50 FPS) | |
5685 | * - Commonly used (60 FPS) | |
5686 | * - Multiples of 24 (48,72,96 FPS) | |
5687 | * | |
5688 | * The list of standards video format is not huge and can be added to the | |
5689 | * connector modeset list beforehand. With that, userspace can leverage | |
5690 | * FreeSync to extends the front porch in order to attain the target refresh | |
5691 | * rate. Such a switch will happen seamlessly, without screen blanking or | |
5692 | * reprogramming of the output in any other way. If the userspace requests a | |
5693 | * modesetting change compatible with FreeSync modes that only differ in the | |
5694 | * refresh rate, DC will skip the full update and avoid blink during the | |
5695 | * transition. For example, the video player can change the modesetting from | |
5696 | * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without | |
5697 | * causing any display blink. This same concept can be applied to a mode | |
5698 | * setting change. | |
5699 | */ | |
5700 | static struct drm_display_mode * | |
5701 | get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, | |
5702 | bool use_probed_modes) | |
5703 | { | |
5704 | struct drm_display_mode *m, *m_pref = NULL; | |
5705 | u16 current_refresh, highest_refresh; | |
5706 | struct list_head *list_head = use_probed_modes ? | |
5707 | &aconnector->base.probed_modes : | |
5708 | &aconnector->base.modes; | |
5709 | ||
5710 | if (aconnector->freesync_vid_base.clock != 0) | |
5711 | return &aconnector->freesync_vid_base; | |
5712 | ||
5713 | /* Find the preferred mode */ | |
c82eddf8 | 5714 | list_for_each_entry(m, list_head, head) { |
5d945cbc RS |
5715 | if (m->type & DRM_MODE_TYPE_PREFERRED) { |
5716 | m_pref = m; | |
5717 | break; | |
5718 | } | |
5719 | } | |
5720 | ||
5721 | if (!m_pref) { | |
5722 | /* Probably an EDID with no preferred mode. Fallback to first entry */ | |
5723 | m_pref = list_first_entry_or_null( | |
5724 | &aconnector->base.modes, struct drm_display_mode, head); | |
5725 | if (!m_pref) { | |
5726 | DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); | |
5727 | return NULL; | |
5728 | } | |
5729 | } | |
5730 | ||
5731 | highest_refresh = drm_mode_vrefresh(m_pref); | |
5732 | ||
5733 | /* | |
5734 | * Find the mode with highest refresh rate with same resolution. | |
5735 | * For some monitors, preferred mode is not the mode with highest | |
5736 | * supported refresh rate. | |
5737 | */ | |
c82eddf8 | 5738 | list_for_each_entry(m, list_head, head) { |
5d945cbc RS |
5739 | current_refresh = drm_mode_vrefresh(m); |
5740 | ||
5741 | if (m->hdisplay == m_pref->hdisplay && | |
5742 | m->vdisplay == m_pref->vdisplay && | |
5743 | highest_refresh < current_refresh) { | |
5744 | highest_refresh = current_refresh; | |
5745 | m_pref = m; | |
5746 | } | |
5747 | } | |
5748 | ||
5749 | drm_mode_copy(&aconnector->freesync_vid_base, m_pref); | |
5750 | return m_pref; | |
5751 | } | |
5752 | ||
5753 | static bool is_freesync_video_mode(const struct drm_display_mode *mode, | |
5754 | struct amdgpu_dm_connector *aconnector) | |
5755 | { | |
5756 | struct drm_display_mode *high_mode; | |
5757 | int timing_diff; | |
5758 | ||
5759 | high_mode = get_highest_refresh_rate_mode(aconnector, false); | |
5760 | if (!high_mode || !mode) | |
5761 | return false; | |
5762 | ||
5763 | timing_diff = high_mode->vtotal - mode->vtotal; | |
5764 | ||
5765 | if (high_mode->clock == 0 || high_mode->clock != mode->clock || | |
5766 | high_mode->hdisplay != mode->hdisplay || | |
5767 | high_mode->vdisplay != mode->vdisplay || | |
5768 | high_mode->hsync_start != mode->hsync_start || | |
5769 | high_mode->hsync_end != mode->hsync_end || | |
5770 | high_mode->htotal != mode->htotal || | |
5771 | high_mode->hskew != mode->hskew || | |
5772 | high_mode->vscan != mode->vscan || | |
5773 | high_mode->vsync_start - mode->vsync_start != timing_diff || | |
5774 | high_mode->vsync_end - mode->vsync_end != timing_diff) | |
5775 | return false; | |
5776 | else | |
5777 | return true; | |
5778 | } | |
5779 | ||
998b7ad2 | 5780 | static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, |
5d945cbc RS |
5781 | struct dc_sink *sink, struct dc_stream_state *stream, |
5782 | struct dsc_dec_dpcd_caps *dsc_caps) | |
998b7ad2 FZ |
5783 | { |
5784 | stream->timing.flags.DSC = 0; | |
63ad5371 | 5785 | dsc_caps->is_dsc_supported = false; |
998b7ad2 | 5786 | |
2665f63a | 5787 | if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || |
5d945cbc | 5788 | sink->sink_signal == SIGNAL_TYPE_EDP)) { |
50b1f44e FZ |
5789 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || |
5790 | sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) | |
5791 | dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, | |
5792 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, | |
5793 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, | |
5794 | dsc_caps); | |
998b7ad2 FZ |
5795 | } |
5796 | } | |
5797 | ||
5d945cbc | 5798 | |
2665f63a ML |
5799 | static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, |
5800 | struct dc_sink *sink, struct dc_stream_state *stream, | |
5801 | struct dsc_dec_dpcd_caps *dsc_caps, | |
5802 | uint32_t max_dsc_target_bpp_limit_override) | |
5803 | { | |
5804 | const struct dc_link_settings *verified_link_cap = NULL; | |
ae67558b SS |
5805 | u32 link_bw_in_kbps; |
5806 | u32 edp_min_bpp_x16, edp_max_bpp_x16; | |
2665f63a ML |
5807 | struct dc *dc = sink->ctx->dc; |
5808 | struct dc_dsc_bw_range bw_range = {0}; | |
5809 | struct dc_dsc_config dsc_cfg = {0}; | |
de534c1c MH |
5810 | struct dc_dsc_config_options dsc_options = {0}; |
5811 | ||
5812 | dc_dsc_get_default_config_option(dc, &dsc_options); | |
5813 | dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; | |
2665f63a ML |
5814 | |
5815 | verified_link_cap = dc_link_get_link_cap(stream->link); | |
5816 | link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); | |
5817 | edp_min_bpp_x16 = 8 * 16; | |
5818 | edp_max_bpp_x16 = 8 * 16; | |
5819 | ||
5820 | if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) | |
5821 | edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; | |
5822 | ||
5823 | if (edp_max_bpp_x16 < edp_min_bpp_x16) | |
5824 | edp_min_bpp_x16 = edp_max_bpp_x16; | |
5825 | ||
5826 | if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], | |
5827 | dc->debug.dsc_min_slice_height_override, | |
5828 | edp_min_bpp_x16, edp_max_bpp_x16, | |
5829 | dsc_caps, | |
5830 | &stream->timing, | |
63c0bf99 | 5831 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
2665f63a ML |
5832 | &bw_range)) { |
5833 | ||
5834 | if (bw_range.max_kbps < link_bw_in_kbps) { | |
5835 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], | |
5836 | dsc_caps, | |
de534c1c | 5837 | &dsc_options, |
2665f63a ML |
5838 | 0, |
5839 | &stream->timing, | |
63c0bf99 | 5840 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
2665f63a ML |
5841 | &dsc_cfg)) { |
5842 | stream->timing.dsc_cfg = dsc_cfg; | |
5843 | stream->timing.flags.DSC = 1; | |
5844 | stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; | |
5845 | } | |
5846 | return; | |
5847 | } | |
5848 | } | |
5849 | ||
5850 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], | |
5851 | dsc_caps, | |
de534c1c | 5852 | &dsc_options, |
2665f63a ML |
5853 | link_bw_in_kbps, |
5854 | &stream->timing, | |
63c0bf99 | 5855 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
2665f63a ML |
5856 | &dsc_cfg)) { |
5857 | stream->timing.dsc_cfg = dsc_cfg; | |
5858 | stream->timing.flags.DSC = 1; | |
5859 | } | |
5860 | } | |
5861 | ||
5d945cbc | 5862 | |
998b7ad2 | 5863 | static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, |
5d945cbc RS |
5864 | struct dc_sink *sink, struct dc_stream_state *stream, |
5865 | struct dsc_dec_dpcd_caps *dsc_caps) | |
998b7ad2 FZ |
5866 | { |
5867 | struct drm_connector *drm_connector = &aconnector->base; | |
ae67558b | 5868 | u32 link_bandwidth_kbps; |
2665f63a | 5869 | struct dc *dc = sink->ctx->dc; |
ae67558b SS |
5870 | u32 max_supported_bw_in_kbps, timing_bw_in_kbps; |
5871 | u32 dsc_max_supported_bw_in_kbps; | |
5872 | u32 max_dsc_target_bpp_limit_override = | |
6e5abe94 | 5873 | drm_connector->display_info.max_dsc_bpp; |
de534c1c MH |
5874 | struct dc_dsc_config_options dsc_options = {0}; |
5875 | ||
5876 | dc_dsc_get_default_config_option(dc, &dsc_options); | |
5877 | dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; | |
998b7ad2 FZ |
5878 | |
5879 | link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, | |
5880 | dc_link_get_link_cap(aconnector->dc_link)); | |
de7cc1b4 | 5881 | |
998b7ad2 FZ |
5882 | /* Set DSC policy according to dsc_clock_en */ |
5883 | dc_dsc_policy_set_enable_dsc_when_not_needed( | |
5884 | aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); | |
5885 | ||
c17a34e0 IC |
5886 | if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && |
5887 | !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && | |
2665f63a ML |
5888 | dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { |
5889 | ||
5890 | apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); | |
5891 | ||
5892 | } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { | |
50b1f44e FZ |
5893 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { |
5894 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], | |
998b7ad2 | 5895 | dsc_caps, |
de534c1c | 5896 | &dsc_options, |
998b7ad2 FZ |
5897 | link_bandwidth_kbps, |
5898 | &stream->timing, | |
63c0bf99 | 5899 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
998b7ad2 | 5900 | &stream->timing.dsc_cfg)) { |
50b1f44e | 5901 | stream->timing.flags.DSC = 1; |
5d945cbc | 5902 | DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); |
50b1f44e FZ |
5903 | } |
5904 | } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { | |
63c0bf99 GS |
5905 | timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, |
5906 | dc_link_get_highest_encoding_format(aconnector->dc_link)); | |
50b1f44e FZ |
5907 | max_supported_bw_in_kbps = link_bandwidth_kbps; |
5908 | dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; | |
5909 | ||
5910 | if (timing_bw_in_kbps > max_supported_bw_in_kbps && | |
5911 | max_supported_bw_in_kbps > 0 && | |
5912 | dsc_max_supported_bw_in_kbps > 0) | |
5913 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], | |
5914 | dsc_caps, | |
de534c1c | 5915 | &dsc_options, |
50b1f44e FZ |
5916 | dsc_max_supported_bw_in_kbps, |
5917 | &stream->timing, | |
63c0bf99 | 5918 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
50b1f44e FZ |
5919 | &stream->timing.dsc_cfg)) { |
5920 | stream->timing.flags.DSC = 1; | |
5921 | DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", | |
5922 | __func__, drm_connector->name); | |
5923 | } | |
998b7ad2 FZ |
5924 | } |
5925 | } | |
5926 | ||
5927 | /* Overwrite the stream flag if DSC is enabled through debugfs */ | |
5928 | if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) | |
5929 | stream->timing.flags.DSC = 1; | |
5930 | ||
5d945cbc RS |
5931 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) |
5932 | stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; | |
a85ba005 | 5933 | |
5d945cbc RS |
5934 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) |
5935 | stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; | |
a85ba005 | 5936 | |
5d945cbc RS |
5937 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) |
5938 | stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; | |
a85ba005 NC |
5939 | } |
5940 | ||
f11d9373 | 5941 | static struct dc_stream_state * |
3ee6b26b AD |
5942 | create_stream_for_sink(struct amdgpu_dm_connector *aconnector, |
5943 | const struct drm_display_mode *drm_mode, | |
b333730d | 5944 | const struct dm_connector_state *dm_state, |
cbd14ae7 SW |
5945 | const struct dc_stream_state *old_stream, |
5946 | int requested_bpc) | |
e7b07cee HW |
5947 | { |
5948 | struct drm_display_mode *preferred_mode = NULL; | |
391ef035 | 5949 | struct drm_connector *drm_connector; |
cb841d27 | 5950 | const struct drm_connector_state *con_state = &dm_state->base; |
0971c40e | 5951 | struct dc_stream_state *stream = NULL; |
0a204ce0 | 5952 | struct drm_display_mode mode; |
a85ba005 NC |
5953 | struct drm_display_mode saved_mode; |
5954 | struct drm_display_mode *freesync_mode = NULL; | |
e7b07cee | 5955 | bool native_mode_found = false; |
b0781603 | 5956 | bool recalculate_timing = false; |
cb841d27 | 5957 | bool scale = dm_state->scaling != RMX_OFF; |
b333730d | 5958 | int mode_refresh; |
58124bf8 | 5959 | int preferred_refresh = 0; |
b1a98cf8 | 5960 | enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; |
df2f1015 | 5961 | struct dsc_dec_dpcd_caps dsc_caps; |
5d945cbc | 5962 | |
aed15309 | 5963 | struct dc_sink *sink = NULL; |
a85ba005 | 5964 | |
0a204ce0 | 5965 | drm_mode_init(&mode, drm_mode); |
a85ba005 NC |
5966 | memset(&saved_mode, 0, sizeof(saved_mode)); |
5967 | ||
b830ebc9 | 5968 | if (aconnector == NULL) { |
e7b07cee | 5969 | DRM_ERROR("aconnector is NULL!\n"); |
64245fa7 | 5970 | return stream; |
e7b07cee HW |
5971 | } |
5972 | ||
e7b07cee | 5973 | drm_connector = &aconnector->base; |
2e0ac3d6 | 5974 | |
f4ac176e | 5975 | if (!aconnector->dc_sink) { |
e3fa5c4c JFZ |
5976 | sink = create_fake_sink(aconnector); |
5977 | if (!sink) | |
5978 | return stream; | |
aed15309 ML |
5979 | } else { |
5980 | sink = aconnector->dc_sink; | |
dcd5fb82 | 5981 | dc_sink_retain(sink); |
f4ac176e | 5982 | } |
2e0ac3d6 | 5983 | |
aed15309 | 5984 | stream = dc_create_stream_for_sink(sink); |
4562236b | 5985 | |
b830ebc9 | 5986 | if (stream == NULL) { |
e7b07cee | 5987 | DRM_ERROR("Failed to create stream for sink!\n"); |
aed15309 | 5988 | goto finish; |
e7b07cee HW |
5989 | } |
5990 | ||
ceb3dbb4 JL |
5991 | stream->dm_stream_context = aconnector; |
5992 | ||
4a36fcba WL |
5993 | stream->timing.flags.LTE_340MCSC_SCRAMBLE = |
5994 | drm_connector->display_info.hdmi.scdc.scrambling.low_rates; | |
5995 | ||
e7b07cee HW |
5996 | list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { |
5997 | /* Search for preferred mode */ | |
5998 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { | |
5999 | native_mode_found = true; | |
6000 | break; | |
6001 | } | |
6002 | } | |
6003 | if (!native_mode_found) | |
6004 | preferred_mode = list_first_entry_or_null( | |
6005 | &aconnector->base.modes, | |
6006 | struct drm_display_mode, | |
6007 | head); | |
6008 | ||
b333730d BL |
6009 | mode_refresh = drm_mode_vrefresh(&mode); |
6010 | ||
b830ebc9 | 6011 | if (preferred_mode == NULL) { |
1f6010a9 DF |
6012 | /* |
6013 | * This may not be an error, the use case is when we have no | |
e7b07cee HW |
6014 | * usermode calls to reset and set mode upon hotplug. In this |
6015 | * case, we call set mode ourselves to restore the previous mode | |
c82eddf8 | 6016 | * and the modelist may not be filled in time. |
e7b07cee | 6017 | */ |
f1ad2f5e | 6018 | DRM_DEBUG_DRIVER("No preferred mode found\n"); |
e7b07cee | 6019 | } else { |
11b92df8 | 6020 | recalculate_timing = is_freesync_video_mode(&mode, aconnector); |
a85ba005 NC |
6021 | if (recalculate_timing) { |
6022 | freesync_mode = get_highest_refresh_rate_mode(aconnector, false); | |
426c89aa VS |
6023 | drm_mode_copy(&saved_mode, &mode); |
6024 | drm_mode_copy(&mode, freesync_mode); | |
a85ba005 NC |
6025 | } else { |
6026 | decide_crtc_timing_for_drm_display_mode( | |
5d945cbc | 6027 | &mode, preferred_mode, scale); |
a85ba005 | 6028 | |
b0781603 NK |
6029 | preferred_refresh = drm_mode_vrefresh(preferred_mode); |
6030 | } | |
e7b07cee HW |
6031 | } |
6032 | ||
a85ba005 NC |
6033 | if (recalculate_timing) |
6034 | drm_mode_set_crtcinfo(&saved_mode, 0); | |
95dd6efc | 6035 | else if (!old_stream) |
f783577c JFZ |
6036 | drm_mode_set_crtcinfo(&mode, 0); |
6037 | ||
5d945cbc | 6038 | /* |
c82eddf8 SS |
6039 | * If scaling is enabled and refresh rate didn't change |
6040 | * we copy the vic and polarities of the old timings | |
6041 | */ | |
b0781603 | 6042 | if (!scale || mode_refresh != preferred_refresh) |
a85ba005 NC |
6043 | fill_stream_properties_from_drm_display_mode( |
6044 | stream, &mode, &aconnector->base, con_state, NULL, | |
6045 | requested_bpc); | |
b333730d | 6046 | else |
a85ba005 NC |
6047 | fill_stream_properties_from_drm_display_mode( |
6048 | stream, &mode, &aconnector->base, con_state, old_stream, | |
6049 | requested_bpc); | |
b333730d | 6050 | |
028c4ccf QZ |
6051 | if (aconnector->timing_changed) { |
6052 | DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n", | |
6053 | __func__, | |
6054 | stream->timing.display_color_depth, | |
6055 | aconnector->timing_requested->display_color_depth); | |
6056 | stream->timing = *aconnector->timing_requested; | |
6057 | } | |
6058 | ||
998b7ad2 FZ |
6059 | /* SST DSC determination policy */ |
6060 | update_dsc_caps(aconnector, sink, stream, &dsc_caps); | |
6061 | if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) | |
6062 | apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); | |
39a4eb85 | 6063 | |
e7b07cee HW |
6064 | update_stream_scaling_settings(&mode, dm_state, stream); |
6065 | ||
6066 | fill_audio_info( | |
6067 | &stream->audio_info, | |
6068 | drm_connector, | |
aed15309 | 6069 | sink); |
e7b07cee | 6070 | |
ceb3dbb4 | 6071 | update_stream_signal(stream, sink); |
9182b4cb | 6072 | |
d832fc3b | 6073 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
75f77aaf WL |
6074 | mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); |
6075 | ||
81a7be79 | 6076 | if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) { |
8a488f5d RL |
6077 | // |
6078 | // should decide stream support vsc sdp colorimetry capability | |
6079 | // before building vsc info packet | |
6080 | // | |
6081 | stream->use_vsc_sdp_for_colorimetry = false; | |
6082 | if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { | |
6083 | stream->use_vsc_sdp_for_colorimetry = | |
6084 | aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; | |
6085 | } else { | |
6086 | if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) | |
6087 | stream->use_vsc_sdp_for_colorimetry = true; | |
8c322309 | 6088 | } |
b1a98cf8 MH |
6089 | if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) |
6090 | tf = TRANSFER_FUNC_GAMMA_22; | |
6091 | mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); | |
1a365683 RL |
6092 | aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; |
6093 | ||
8c322309 | 6094 | } |
aed15309 | 6095 | finish: |
dcd5fb82 | 6096 | dc_sink_release(sink); |
9e3efe3e | 6097 | |
e7b07cee HW |
6098 | return stream; |
6099 | } | |
6100 | ||
e7b07cee HW |
6101 | static enum drm_connector_status |
6102 | amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) | |
6103 | { | |
6104 | bool connected; | |
c84dec2f | 6105 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee | 6106 | |
1f6010a9 DF |
6107 | /* |
6108 | * Notes: | |
e7b07cee HW |
6109 | * 1. This interface is NOT called in context of HPD irq. |
6110 | * 2. This interface *is called* in context of user-mode ioctl. Which | |
1f6010a9 DF |
6111 | * makes it a bad place for *any* MST-related activity. |
6112 | */ | |
e7b07cee | 6113 | |
8580d60b HW |
6114 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && |
6115 | !aconnector->fake_enable) | |
e7b07cee HW |
6116 | connected = (aconnector->dc_sink != NULL); |
6117 | else | |
5d945cbc RS |
6118 | connected = (aconnector->base.force == DRM_FORCE_ON || |
6119 | aconnector->base.force == DRM_FORCE_ON_DIGITAL); | |
e7b07cee | 6120 | |
0f877894 OV |
6121 | update_subconnector_property(aconnector); |
6122 | ||
e7b07cee HW |
6123 | return (connected ? connector_status_connected : |
6124 | connector_status_disconnected); | |
6125 | } | |
6126 | ||
3ee6b26b AD |
6127 | int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, |
6128 | struct drm_connector_state *connector_state, | |
6129 | struct drm_property *property, | |
6130 | uint64_t val) | |
e7b07cee HW |
6131 | { |
6132 | struct drm_device *dev = connector->dev; | |
1348969a | 6133 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
6134 | struct dm_connector_state *dm_old_state = |
6135 | to_dm_connector_state(connector->state); | |
6136 | struct dm_connector_state *dm_new_state = | |
6137 | to_dm_connector_state(connector_state); | |
6138 | ||
6139 | int ret = -EINVAL; | |
6140 | ||
6141 | if (property == dev->mode_config.scaling_mode_property) { | |
6142 | enum amdgpu_rmx_type rmx_type; | |
6143 | ||
6144 | switch (val) { | |
6145 | case DRM_MODE_SCALE_CENTER: | |
6146 | rmx_type = RMX_CENTER; | |
6147 | break; | |
6148 | case DRM_MODE_SCALE_ASPECT: | |
6149 | rmx_type = RMX_ASPECT; | |
6150 | break; | |
6151 | case DRM_MODE_SCALE_FULLSCREEN: | |
6152 | rmx_type = RMX_FULL; | |
6153 | break; | |
6154 | case DRM_MODE_SCALE_NONE: | |
6155 | default: | |
6156 | rmx_type = RMX_OFF; | |
6157 | break; | |
6158 | } | |
6159 | ||
6160 | if (dm_old_state->scaling == rmx_type) | |
6161 | return 0; | |
6162 | ||
6163 | dm_new_state->scaling = rmx_type; | |
6164 | ret = 0; | |
6165 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
6166 | dm_new_state->underscan_hborder = val; | |
6167 | ret = 0; | |
6168 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
6169 | dm_new_state->underscan_vborder = val; | |
6170 | ret = 0; | |
6171 | } else if (property == adev->mode_info.underscan_property) { | |
6172 | dm_new_state->underscan_enable = val; | |
6173 | ret = 0; | |
c1ee92f9 DF |
6174 | } else if (property == adev->mode_info.abm_level_property) { |
6175 | dm_new_state->abm_level = val; | |
6176 | ret = 0; | |
e7b07cee HW |
6177 | } |
6178 | ||
6179 | return ret; | |
6180 | } | |
6181 | ||
3ee6b26b AD |
6182 | int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, |
6183 | const struct drm_connector_state *state, | |
6184 | struct drm_property *property, | |
6185 | uint64_t *val) | |
e7b07cee HW |
6186 | { |
6187 | struct drm_device *dev = connector->dev; | |
1348969a | 6188 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
6189 | struct dm_connector_state *dm_state = |
6190 | to_dm_connector_state(state); | |
6191 | int ret = -EINVAL; | |
6192 | ||
6193 | if (property == dev->mode_config.scaling_mode_property) { | |
6194 | switch (dm_state->scaling) { | |
6195 | case RMX_CENTER: | |
6196 | *val = DRM_MODE_SCALE_CENTER; | |
6197 | break; | |
6198 | case RMX_ASPECT: | |
6199 | *val = DRM_MODE_SCALE_ASPECT; | |
6200 | break; | |
6201 | case RMX_FULL: | |
6202 | *val = DRM_MODE_SCALE_FULLSCREEN; | |
6203 | break; | |
6204 | case RMX_OFF: | |
6205 | default: | |
6206 | *val = DRM_MODE_SCALE_NONE; | |
6207 | break; | |
6208 | } | |
6209 | ret = 0; | |
6210 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
6211 | *val = dm_state->underscan_hborder; | |
6212 | ret = 0; | |
6213 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
6214 | *val = dm_state->underscan_vborder; | |
6215 | ret = 0; | |
6216 | } else if (property == adev->mode_info.underscan_property) { | |
6217 | *val = dm_state->underscan_enable; | |
6218 | ret = 0; | |
c1ee92f9 DF |
6219 | } else if (property == adev->mode_info.abm_level_property) { |
6220 | *val = dm_state->abm_level; | |
6221 | ret = 0; | |
e7b07cee | 6222 | } |
c1ee92f9 | 6223 | |
e7b07cee HW |
6224 | return ret; |
6225 | } | |
6226 | ||
526c654a ED |
6227 | static void amdgpu_dm_connector_unregister(struct drm_connector *connector) |
6228 | { | |
6229 | struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); | |
6230 | ||
6231 | drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); | |
6232 | } | |
6233 | ||
7578ecda | 6234 | static void amdgpu_dm_connector_destroy(struct drm_connector *connector) |
e7b07cee | 6235 | { |
c84dec2f | 6236 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
1348969a | 6237 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
e7b07cee | 6238 | struct amdgpu_display_manager *dm = &adev->dm; |
ada8ce15 | 6239 | |
5dff80bd | 6240 | /* |
5d945cbc | 6241 | * Call only if mst_mgr was initialized before since it's not done |
5dff80bd AG |
6242 | * for all connector types. |
6243 | */ | |
6244 | if (aconnector->mst_mgr.dev) | |
6245 | drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); | |
6246 | ||
f196198c HG |
6247 | if (aconnector->bl_idx != -1) { |
6248 | backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); | |
6249 | dm->backlight_dev[aconnector->bl_idx] = NULL; | |
e7b07cee | 6250 | } |
dcd5fb82 MF |
6251 | |
6252 | if (aconnector->dc_em_sink) | |
6253 | dc_sink_release(aconnector->dc_em_sink); | |
6254 | aconnector->dc_em_sink = NULL; | |
6255 | if (aconnector->dc_sink) | |
6256 | dc_sink_release(aconnector->dc_sink); | |
6257 | aconnector->dc_sink = NULL; | |
6258 | ||
e86e8947 | 6259 | drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); |
e7b07cee HW |
6260 | drm_connector_unregister(connector); |
6261 | drm_connector_cleanup(connector); | |
526c654a ED |
6262 | if (aconnector->i2c) { |
6263 | i2c_del_adapter(&aconnector->i2c->base); | |
6264 | kfree(aconnector->i2c); | |
6265 | } | |
7daec99f | 6266 | kfree(aconnector->dm_dp_aux.aux.name); |
526c654a | 6267 | |
e7b07cee HW |
6268 | kfree(connector); |
6269 | } | |
6270 | ||
6271 | void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) | |
6272 | { | |
6273 | struct dm_connector_state *state = | |
6274 | to_dm_connector_state(connector->state); | |
6275 | ||
df099b9b LSL |
6276 | if (connector->state) |
6277 | __drm_atomic_helper_connector_destroy_state(connector->state); | |
6278 | ||
e7b07cee HW |
6279 | kfree(state); |
6280 | ||
6281 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
6282 | ||
6283 | if (state) { | |
6284 | state->scaling = RMX_OFF; | |
6285 | state->underscan_enable = false; | |
6286 | state->underscan_hborder = 0; | |
6287 | state->underscan_vborder = 0; | |
01933ba4 | 6288 | state->base.max_requested_bpc = 8; |
3261e013 ML |
6289 | state->vcpi_slots = 0; |
6290 | state->pbn = 0; | |
5d945cbc | 6291 | |
c3e50f89 NK |
6292 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
6293 | state->abm_level = amdgpu_dm_abm_level; | |
6294 | ||
df099b9b | 6295 | __drm_atomic_helper_connector_reset(connector, &state->base); |
e7b07cee HW |
6296 | } |
6297 | } | |
6298 | ||
3ee6b26b AD |
6299 | struct drm_connector_state * |
6300 | amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) | |
e7b07cee HW |
6301 | { |
6302 | struct dm_connector_state *state = | |
6303 | to_dm_connector_state(connector->state); | |
6304 | ||
6305 | struct dm_connector_state *new_state = | |
6306 | kmemdup(state, sizeof(*state), GFP_KERNEL); | |
6307 | ||
98e6436d AK |
6308 | if (!new_state) |
6309 | return NULL; | |
e7b07cee | 6310 | |
98e6436d AK |
6311 | __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); |
6312 | ||
6313 | new_state->freesync_capable = state->freesync_capable; | |
c1ee92f9 | 6314 | new_state->abm_level = state->abm_level; |
922454c2 NK |
6315 | new_state->scaling = state->scaling; |
6316 | new_state->underscan_enable = state->underscan_enable; | |
6317 | new_state->underscan_hborder = state->underscan_hborder; | |
6318 | new_state->underscan_vborder = state->underscan_vborder; | |
3261e013 ML |
6319 | new_state->vcpi_slots = state->vcpi_slots; |
6320 | new_state->pbn = state->pbn; | |
98e6436d | 6321 | return &new_state->base; |
e7b07cee HW |
6322 | } |
6323 | ||
14f04fa4 AD |
6324 | static int |
6325 | amdgpu_dm_connector_late_register(struct drm_connector *connector) | |
6326 | { | |
6327 | struct amdgpu_dm_connector *amdgpu_dm_connector = | |
6328 | to_amdgpu_dm_connector(connector); | |
00a8037e | 6329 | int r; |
14f04fa4 | 6330 | |
62f03dad HG |
6331 | amdgpu_dm_register_backlight_device(amdgpu_dm_connector); |
6332 | ||
00a8037e AD |
6333 | if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
6334 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
6335 | amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; | |
6336 | r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); | |
6337 | if (r) | |
6338 | return r; | |
6339 | } | |
6340 | ||
6341 | #if defined(CONFIG_DEBUG_FS) | |
14f04fa4 AD |
6342 | connector_debugfs_init(amdgpu_dm_connector); |
6343 | #endif | |
6344 | ||
6345 | return 0; | |
6346 | } | |
6347 | ||
dae343b3 | 6348 | static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) |
0ba4a784 AH |
6349 | { |
6350 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
6351 | struct dc_link *dc_link = aconnector->dc_link; | |
6352 | struct dc_sink *dc_em_sink = aconnector->dc_em_sink; | |
6353 | struct edid *edid; | |
6354 | ||
6355 | if (!connector->edid_override) | |
6356 | return; | |
6357 | ||
6358 | drm_edid_override_connector_update(&aconnector->base); | |
6359 | edid = aconnector->base.edid_blob_ptr->data; | |
6360 | aconnector->edid = edid; | |
6361 | ||
6362 | /* Update emulated (virtual) sink's EDID */ | |
6363 | if (dc_em_sink && dc_link) { | |
6364 | memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); | |
6365 | memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); | |
6366 | dm_helpers_parse_edid_caps( | |
6367 | dc_link, | |
6368 | &dc_em_sink->dc_edid, | |
6369 | &dc_em_sink->edid_caps); | |
6370 | } | |
6371 | } | |
6372 | ||
e7b07cee HW |
6373 | static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { |
6374 | .reset = amdgpu_dm_connector_funcs_reset, | |
6375 | .detect = amdgpu_dm_connector_detect, | |
6376 | .fill_modes = drm_helper_probe_single_connector_modes, | |
6377 | .destroy = amdgpu_dm_connector_destroy, | |
6378 | .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, | |
6379 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
6380 | .atomic_set_property = amdgpu_dm_connector_atomic_set_property, | |
526c654a | 6381 | .atomic_get_property = amdgpu_dm_connector_atomic_get_property, |
14f04fa4 | 6382 | .late_register = amdgpu_dm_connector_late_register, |
0ba4a784 AH |
6383 | .early_unregister = amdgpu_dm_connector_unregister, |
6384 | .force = amdgpu_dm_connector_funcs_force | |
e7b07cee HW |
6385 | }; |
6386 | ||
e7b07cee HW |
6387 | static int get_modes(struct drm_connector *connector) |
6388 | { | |
6389 | return amdgpu_dm_connector_get_modes(connector); | |
6390 | } | |
6391 | ||
c84dec2f | 6392 | static void create_eml_sink(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
6393 | { |
6394 | struct dc_sink_init_data init_params = { | |
6395 | .link = aconnector->dc_link, | |
6396 | .sink_signal = SIGNAL_TYPE_VIRTUAL | |
6397 | }; | |
70e8ffc5 | 6398 | struct edid *edid; |
e7b07cee | 6399 | |
a89ff457 | 6400 | if (!aconnector->base.edid_blob_ptr) { |
550e5d23 HW |
6401 | /* if connector->edid_override valid, pass |
6402 | * it to edid_override to edid_blob_ptr | |
6403 | */ | |
e7b07cee | 6404 | |
8789989b | 6405 | drm_edid_override_connector_update(&aconnector->base); |
550e5d23 HW |
6406 | |
6407 | if (!aconnector->base.edid_blob_ptr) { | |
6408 | DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", | |
6409 | aconnector->base.name); | |
6410 | ||
6411 | aconnector->base.force = DRM_FORCE_OFF; | |
6412 | return; | |
6413 | } | |
e7b07cee HW |
6414 | } |
6415 | ||
70e8ffc5 HW |
6416 | edid = (struct edid *) aconnector->base.edid_blob_ptr->data; |
6417 | ||
e7b07cee HW |
6418 | aconnector->edid = edid; |
6419 | ||
6420 | aconnector->dc_em_sink = dc_link_add_remote_sink( | |
6421 | aconnector->dc_link, | |
6422 | (uint8_t *)edid, | |
6423 | (edid->extensions + 1) * EDID_LENGTH, | |
6424 | &init_params); | |
6425 | ||
dcd5fb82 | 6426 | if (aconnector->base.force == DRM_FORCE_ON) { |
e7b07cee HW |
6427 | aconnector->dc_sink = aconnector->dc_link->local_sink ? |
6428 | aconnector->dc_link->local_sink : | |
6429 | aconnector->dc_em_sink; | |
dcd5fb82 MF |
6430 | dc_sink_retain(aconnector->dc_sink); |
6431 | } | |
e7b07cee HW |
6432 | } |
6433 | ||
c84dec2f | 6434 | static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
6435 | { |
6436 | struct dc_link *link = (struct dc_link *)aconnector->dc_link; | |
6437 | ||
1f6010a9 DF |
6438 | /* |
6439 | * In case of headless boot with force on for DP managed connector | |
e7b07cee HW |
6440 | * Those settings have to be != 0 to get initial modeset |
6441 | */ | |
6442 | if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { | |
6443 | link->verified_link_cap.lane_count = LANE_COUNT_FOUR; | |
6444 | link->verified_link_cap.link_rate = LINK_RATE_HIGH2; | |
6445 | } | |
6446 | ||
e7b07cee HW |
6447 | create_eml_sink(aconnector); |
6448 | } | |
6449 | ||
5468c36d FZ |
6450 | static enum dc_status dm_validate_stream_and_context(struct dc *dc, |
6451 | struct dc_stream_state *stream) | |
6452 | { | |
6453 | enum dc_status dc_result = DC_ERROR_UNEXPECTED; | |
6454 | struct dc_plane_state *dc_plane_state = NULL; | |
6455 | struct dc_state *dc_state = NULL; | |
6456 | ||
6457 | if (!stream) | |
6458 | goto cleanup; | |
6459 | ||
6460 | dc_plane_state = dc_create_plane_state(dc); | |
6461 | if (!dc_plane_state) | |
6462 | goto cleanup; | |
6463 | ||
6464 | dc_state = dc_create_state(dc); | |
6465 | if (!dc_state) | |
6466 | goto cleanup; | |
6467 | ||
6468 | /* populate stream to plane */ | |
6469 | dc_plane_state->src_rect.height = stream->src.height; | |
6470 | dc_plane_state->src_rect.width = stream->src.width; | |
6471 | dc_plane_state->dst_rect.height = stream->src.height; | |
6472 | dc_plane_state->dst_rect.width = stream->src.width; | |
6473 | dc_plane_state->clip_rect.height = stream->src.height; | |
6474 | dc_plane_state->clip_rect.width = stream->src.width; | |
6475 | dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; | |
6476 | dc_plane_state->plane_size.surface_size.height = stream->src.height; | |
6477 | dc_plane_state->plane_size.surface_size.width = stream->src.width; | |
6478 | dc_plane_state->plane_size.chroma_size.height = stream->src.height; | |
6479 | dc_plane_state->plane_size.chroma_size.width = stream->src.width; | |
5468c36d FZ |
6480 | dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; |
6481 | dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; | |
6482 | dc_plane_state->rotation = ROTATION_ANGLE_0; | |
6483 | dc_plane_state->is_tiling_rotated = false; | |
6484 | dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; | |
6485 | ||
6486 | dc_result = dc_validate_stream(dc, stream); | |
6487 | if (dc_result == DC_OK) | |
6488 | dc_result = dc_validate_plane(dc, dc_plane_state); | |
6489 | ||
6490 | if (dc_result == DC_OK) | |
6491 | dc_result = dc_add_stream_to_ctx(dc, dc_state, stream); | |
6492 | ||
6493 | if (dc_result == DC_OK && !dc_add_plane_to_context( | |
6494 | dc, | |
6495 | stream, | |
6496 | dc_plane_state, | |
6497 | dc_state)) | |
6498 | dc_result = DC_FAIL_ATTACH_SURFACES; | |
6499 | ||
6500 | if (dc_result == DC_OK) | |
6501 | dc_result = dc_validate_global_state(dc, dc_state, true); | |
6502 | ||
6503 | cleanup: | |
6504 | if (dc_state) | |
6505 | dc_release_state(dc_state); | |
6506 | ||
6507 | if (dc_plane_state) | |
6508 | dc_plane_state_release(dc_plane_state); | |
6509 | ||
6510 | return dc_result; | |
6511 | } | |
6512 | ||
17ce8a69 | 6513 | struct dc_stream_state * |
cbd14ae7 SW |
6514 | create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, |
6515 | const struct drm_display_mode *drm_mode, | |
6516 | const struct dm_connector_state *dm_state, | |
6517 | const struct dc_stream_state *old_stream) | |
6518 | { | |
6519 | struct drm_connector *connector = &aconnector->base; | |
1348969a | 6520 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
cbd14ae7 | 6521 | struct dc_stream_state *stream; |
4b7da34b SW |
6522 | const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; |
6523 | int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; | |
cbd14ae7 SW |
6524 | enum dc_status dc_result = DC_OK; |
6525 | ||
6526 | do { | |
6527 | stream = create_stream_for_sink(aconnector, drm_mode, | |
6528 | dm_state, old_stream, | |
6529 | requested_bpc); | |
6530 | if (stream == NULL) { | |
6531 | DRM_ERROR("Failed to create stream for sink!\n"); | |
6532 | break; | |
6533 | } | |
6534 | ||
e9a7d236 RS |
6535 | dc_result = dc_validate_stream(adev->dm.dc, stream); |
6536 | if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) | |
f04d275d | 6537 | dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); |
6538 | ||
5468c36d FZ |
6539 | if (dc_result == DC_OK) |
6540 | dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); | |
6541 | ||
cbd14ae7 | 6542 | if (dc_result != DC_OK) { |
74a16675 | 6543 | DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", |
cbd14ae7 SW |
6544 | drm_mode->hdisplay, |
6545 | drm_mode->vdisplay, | |
6546 | drm_mode->clock, | |
74a16675 RS |
6547 | dc_result, |
6548 | dc_status_to_str(dc_result)); | |
cbd14ae7 SW |
6549 | |
6550 | dc_stream_release(stream); | |
6551 | stream = NULL; | |
6552 | requested_bpc -= 2; /* lower bpc to retry validation */ | |
6553 | } | |
6554 | ||
6555 | } while (stream == NULL && requested_bpc >= 6); | |
6556 | ||
68eb3ae3 WS |
6557 | if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { |
6558 | DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); | |
6559 | ||
6560 | aconnector->force_yuv420_output = true; | |
6561 | stream = create_validate_stream_for_sink(aconnector, drm_mode, | |
6562 | dm_state, old_stream); | |
6563 | aconnector->force_yuv420_output = false; | |
6564 | } | |
6565 | ||
cbd14ae7 SW |
6566 | return stream; |
6567 | } | |
6568 | ||
ba9ca088 | 6569 | enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, |
3ee6b26b | 6570 | struct drm_display_mode *mode) |
e7b07cee HW |
6571 | { |
6572 | int result = MODE_ERROR; | |
6573 | struct dc_sink *dc_sink; | |
e7b07cee | 6574 | /* TODO: Unhardcode stream count */ |
0971c40e | 6575 | struct dc_stream_state *stream; |
c84dec2f | 6576 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
6577 | |
6578 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || | |
6579 | (mode->flags & DRM_MODE_FLAG_DBLSCAN)) | |
6580 | return result; | |
6581 | ||
1f6010a9 DF |
6582 | /* |
6583 | * Only run this the first time mode_valid is called to initilialize | |
e7b07cee HW |
6584 | * EDID mgmt |
6585 | */ | |
6586 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && | |
6587 | !aconnector->dc_em_sink) | |
6588 | handle_edid_mgmt(aconnector); | |
6589 | ||
c84dec2f | 6590 | dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; |
e7b07cee | 6591 | |
ad975f44 VL |
6592 | if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && |
6593 | aconnector->base.force != DRM_FORCE_ON) { | |
e7b07cee HW |
6594 | DRM_ERROR("dc_sink is NULL!\n"); |
6595 | goto fail; | |
6596 | } | |
6597 | ||
cb841d27 HW |
6598 | stream = create_validate_stream_for_sink(aconnector, mode, |
6599 | to_dm_connector_state(connector->state), | |
6600 | NULL); | |
cbd14ae7 SW |
6601 | if (stream) { |
6602 | dc_stream_release(stream); | |
e7b07cee | 6603 | result = MODE_OK; |
cbd14ae7 | 6604 | } |
e7b07cee HW |
6605 | |
6606 | fail: | |
6607 | /* TODO: error handling*/ | |
6608 | return result; | |
6609 | } | |
6610 | ||
88694af9 NK |
6611 | static int fill_hdr_info_packet(const struct drm_connector_state *state, |
6612 | struct dc_info_packet *out) | |
6613 | { | |
6614 | struct hdmi_drm_infoframe frame; | |
6615 | unsigned char buf[30]; /* 26 + 4 */ | |
6616 | ssize_t len; | |
6617 | int ret, i; | |
6618 | ||
6619 | memset(out, 0, sizeof(*out)); | |
6620 | ||
6621 | if (!state->hdr_output_metadata) | |
6622 | return 0; | |
6623 | ||
6624 | ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); | |
6625 | if (ret) | |
6626 | return ret; | |
6627 | ||
6628 | len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); | |
6629 | if (len < 0) | |
6630 | return (int)len; | |
6631 | ||
6632 | /* Static metadata is a fixed 26 bytes + 4 byte header. */ | |
6633 | if (len != 30) | |
6634 | return -EINVAL; | |
6635 | ||
6636 | /* Prepare the infopacket for DC. */ | |
6637 | switch (state->connector->connector_type) { | |
6638 | case DRM_MODE_CONNECTOR_HDMIA: | |
6639 | out->hb0 = 0x87; /* type */ | |
6640 | out->hb1 = 0x01; /* version */ | |
6641 | out->hb2 = 0x1A; /* length */ | |
6642 | out->sb[0] = buf[3]; /* checksum */ | |
6643 | i = 1; | |
6644 | break; | |
6645 | ||
6646 | case DRM_MODE_CONNECTOR_DisplayPort: | |
6647 | case DRM_MODE_CONNECTOR_eDP: | |
6648 | out->hb0 = 0x00; /* sdp id, zero */ | |
6649 | out->hb1 = 0x87; /* type */ | |
6650 | out->hb2 = 0x1D; /* payload len - 1 */ | |
6651 | out->hb3 = (0x13 << 2); /* sdp version */ | |
6652 | out->sb[0] = 0x01; /* version */ | |
6653 | out->sb[1] = 0x1A; /* length */ | |
6654 | i = 2; | |
6655 | break; | |
6656 | ||
6657 | default: | |
6658 | return -EINVAL; | |
6659 | } | |
6660 | ||
6661 | memcpy(&out->sb[i], &buf[4], 26); | |
6662 | out->valid = true; | |
6663 | ||
6664 | print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, | |
6665 | sizeof(out->sb), false); | |
6666 | ||
6667 | return 0; | |
6668 | } | |
6669 | ||
88694af9 NK |
6670 | static int |
6671 | amdgpu_dm_connector_atomic_check(struct drm_connector *conn, | |
51e857af | 6672 | struct drm_atomic_state *state) |
88694af9 | 6673 | { |
51e857af SP |
6674 | struct drm_connector_state *new_con_state = |
6675 | drm_atomic_get_new_connector_state(state, conn); | |
88694af9 NK |
6676 | struct drm_connector_state *old_con_state = |
6677 | drm_atomic_get_old_connector_state(state, conn); | |
6678 | struct drm_crtc *crtc = new_con_state->crtc; | |
6679 | struct drm_crtc_state *new_crtc_state; | |
a76eb429 | 6680 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); |
88694af9 NK |
6681 | int ret; |
6682 | ||
e8a98235 RS |
6683 | trace_amdgpu_dm_connector_atomic_check(new_con_state); |
6684 | ||
a76eb429 LP |
6685 | if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { |
6686 | ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); | |
6687 | if (ret < 0) | |
6688 | return ret; | |
6689 | } | |
6690 | ||
88694af9 NK |
6691 | if (!crtc) |
6692 | return 0; | |
6693 | ||
a0b433c8 HW |
6694 | if (new_con_state->colorspace != old_con_state->colorspace) { |
6695 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
6696 | if (IS_ERR(new_crtc_state)) | |
6697 | return PTR_ERR(new_crtc_state); | |
6698 | ||
6699 | new_crtc_state->mode_changed = true; | |
6700 | } | |
6701 | ||
72921cdf | 6702 | if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { |
88694af9 NK |
6703 | struct dc_info_packet hdr_infopacket; |
6704 | ||
6705 | ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); | |
6706 | if (ret) | |
6707 | return ret; | |
6708 | ||
6709 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
6710 | if (IS_ERR(new_crtc_state)) | |
6711 | return PTR_ERR(new_crtc_state); | |
6712 | ||
6713 | /* | |
6714 | * DC considers the stream backends changed if the | |
6715 | * static metadata changes. Forcing the modeset also | |
6716 | * gives a simple way for userspace to switch from | |
b232d4ed NK |
6717 | * 8bpc to 10bpc when setting the metadata to enter |
6718 | * or exit HDR. | |
6719 | * | |
6720 | * Changing the static metadata after it's been | |
6721 | * set is permissible, however. So only force a | |
6722 | * modeset if we're entering or exiting HDR. | |
88694af9 | 6723 | */ |
a0b433c8 | 6724 | new_crtc_state->mode_changed = new_crtc_state->mode_changed || |
b232d4ed NK |
6725 | !old_con_state->hdr_output_metadata || |
6726 | !new_con_state->hdr_output_metadata; | |
88694af9 NK |
6727 | } |
6728 | ||
6729 | return 0; | |
6730 | } | |
6731 | ||
e7b07cee HW |
6732 | static const struct drm_connector_helper_funcs |
6733 | amdgpu_dm_connector_helper_funcs = { | |
6734 | /* | |
1f6010a9 | 6735 | * If hotplugging a second bigger display in FB Con mode, bigger resolution |
b830ebc9 | 6736 | * modes will be filtered by drm_mode_validate_size(), and those modes |
1f6010a9 | 6737 | * are missing after user start lightdm. So we need to renew modes list. |
b830ebc9 HW |
6738 | * in get_modes call back, not just return the modes count |
6739 | */ | |
e7b07cee HW |
6740 | .get_modes = get_modes, |
6741 | .mode_valid = amdgpu_dm_connector_mode_valid, | |
88694af9 | 6742 | .atomic_check = amdgpu_dm_connector_atomic_check, |
e7b07cee HW |
6743 | }; |
6744 | ||
e7b07cee HW |
6745 | static void dm_encoder_helper_disable(struct drm_encoder *encoder) |
6746 | { | |
6747 | ||
6748 | } | |
6749 | ||
f04d275d | 6750 | int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) |
3261e013 ML |
6751 | { |
6752 | switch (display_color_depth) { | |
5d945cbc RS |
6753 | case COLOR_DEPTH_666: |
6754 | return 6; | |
6755 | case COLOR_DEPTH_888: | |
6756 | return 8; | |
6757 | case COLOR_DEPTH_101010: | |
6758 | return 10; | |
6759 | case COLOR_DEPTH_121212: | |
6760 | return 12; | |
6761 | case COLOR_DEPTH_141414: | |
6762 | return 14; | |
6763 | case COLOR_DEPTH_161616: | |
6764 | return 16; | |
6765 | default: | |
6766 | break; | |
6767 | } | |
3261e013 ML |
6768 | return 0; |
6769 | } | |
6770 | ||
3ee6b26b AD |
6771 | static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, |
6772 | struct drm_crtc_state *crtc_state, | |
6773 | struct drm_connector_state *conn_state) | |
e7b07cee | 6774 | { |
3261e013 ML |
6775 | struct drm_atomic_state *state = crtc_state->state; |
6776 | struct drm_connector *connector = conn_state->connector; | |
6777 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
6778 | struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); | |
6779 | const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; | |
6780 | struct drm_dp_mst_topology_mgr *mst_mgr; | |
6781 | struct drm_dp_mst_port *mst_port; | |
4d07b0bc | 6782 | struct drm_dp_mst_topology_state *mst_state; |
3261e013 ML |
6783 | enum dc_color_depth color_depth; |
6784 | int clock, bpp = 0; | |
1bc22f20 | 6785 | bool is_y420 = false; |
3261e013 | 6786 | |
91b38ca1 | 6787 | if (!aconnector->mst_output_port) |
3261e013 ML |
6788 | return 0; |
6789 | ||
f0127cb1 WL |
6790 | mst_port = aconnector->mst_output_port; |
6791 | mst_mgr = &aconnector->mst_root->mst_mgr; | |
3261e013 ML |
6792 | |
6793 | if (!crtc_state->connectors_changed && !crtc_state->mode_changed) | |
6794 | return 0; | |
6795 | ||
4d07b0bc LP |
6796 | mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); |
6797 | if (IS_ERR(mst_state)) | |
6798 | return PTR_ERR(mst_state); | |
6799 | ||
6800 | if (!mst_state->pbn_div) | |
f0127cb1 | 6801 | mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); |
4d07b0bc | 6802 | |
3261e013 | 6803 | if (!state->duplicated) { |
cbd14ae7 | 6804 | int max_bpc = conn_state->max_requested_bpc; |
c82eddf8 | 6805 | |
1bc22f20 | 6806 | is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && |
5d945cbc | 6807 | aconnector->force_yuv420_output; |
cbd14ae7 SW |
6808 | color_depth = convert_color_depth_from_display_info(connector, |
6809 | is_y420, | |
6810 | max_bpc); | |
3261e013 ML |
6811 | bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; |
6812 | clock = adjusted_mode->clock; | |
dc48529f | 6813 | dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); |
3261e013 | 6814 | } |
4d07b0bc LP |
6815 | |
6816 | dm_new_connector_state->vcpi_slots = | |
6817 | drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, | |
6818 | dm_new_connector_state->pbn); | |
3261e013 ML |
6819 | if (dm_new_connector_state->vcpi_slots < 0) { |
6820 | DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); | |
6821 | return dm_new_connector_state->vcpi_slots; | |
6822 | } | |
e7b07cee HW |
6823 | return 0; |
6824 | } | |
6825 | ||
6826 | const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { | |
6827 | .disable = dm_encoder_helper_disable, | |
6828 | .atomic_check = dm_encoder_helper_atomic_check | |
6829 | }; | |
6830 | ||
29b9ba74 | 6831 | static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, |
6513104b HW |
6832 | struct dc_state *dc_state, |
6833 | struct dsc_mst_fairness_vars *vars) | |
29b9ba74 ML |
6834 | { |
6835 | struct dc_stream_state *stream = NULL; | |
6836 | struct drm_connector *connector; | |
5760dcb9 | 6837 | struct drm_connector_state *new_con_state; |
29b9ba74 ML |
6838 | struct amdgpu_dm_connector *aconnector; |
6839 | struct dm_connector_state *dm_conn_state; | |
7cce4cd6 | 6840 | int i, j, ret; |
a550bb16 | 6841 | int vcpi, pbn_div, pbn, slot_num = 0; |
29b9ba74 | 6842 | |
5760dcb9 | 6843 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
29b9ba74 ML |
6844 | |
6845 | aconnector = to_amdgpu_dm_connector(connector); | |
6846 | ||
f0127cb1 | 6847 | if (!aconnector->mst_output_port) |
29b9ba74 ML |
6848 | continue; |
6849 | ||
6850 | if (!new_con_state || !new_con_state->crtc) | |
6851 | continue; | |
6852 | ||
6853 | dm_conn_state = to_dm_connector_state(new_con_state); | |
6854 | ||
6855 | for (j = 0; j < dc_state->stream_count; j++) { | |
6856 | stream = dc_state->streams[j]; | |
6857 | if (!stream) | |
6858 | continue; | |
6859 | ||
5d945cbc | 6860 | if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) |
29b9ba74 ML |
6861 | break; |
6862 | ||
6863 | stream = NULL; | |
6864 | } | |
6865 | ||
6866 | if (!stream) | |
6867 | continue; | |
6868 | ||
29b9ba74 | 6869 | pbn_div = dm_mst_get_pbn_divider(stream->link); |
6513104b HW |
6870 | /* pbn is calculated by compute_mst_dsc_configs_for_state*/ |
6871 | for (j = 0; j < dc_state->stream_count; j++) { | |
6872 | if (vars[j].aconnector == aconnector) { | |
6873 | pbn = vars[j].pbn; | |
6874 | break; | |
6875 | } | |
6876 | } | |
6877 | ||
a550bb16 HW |
6878 | if (j == dc_state->stream_count) |
6879 | continue; | |
6880 | ||
6881 | slot_num = DIV_ROUND_UP(pbn, pbn_div); | |
6882 | ||
6883 | if (stream->timing.flags.DSC != 1) { | |
6884 | dm_conn_state->pbn = pbn; | |
6885 | dm_conn_state->vcpi_slots = slot_num; | |
6886 | ||
f0127cb1 | 6887 | ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, |
7cce4cd6 LP |
6888 | dm_conn_state->pbn, false); |
6889 | if (ret < 0) | |
6890 | return ret; | |
6891 | ||
a550bb16 HW |
6892 | continue; |
6893 | } | |
6894 | ||
f0127cb1 | 6895 | vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); |
29b9ba74 ML |
6896 | if (vcpi < 0) |
6897 | return vcpi; | |
6898 | ||
6899 | dm_conn_state->pbn = pbn; | |
6900 | dm_conn_state->vcpi_slots = vcpi; | |
6901 | } | |
6902 | return 0; | |
6903 | } | |
6904 | ||
e7b07cee HW |
6905 | static int to_drm_connector_type(enum signal_type st) |
6906 | { | |
6907 | switch (st) { | |
6908 | case SIGNAL_TYPE_HDMI_TYPE_A: | |
6909 | return DRM_MODE_CONNECTOR_HDMIA; | |
6910 | case SIGNAL_TYPE_EDP: | |
6911 | return DRM_MODE_CONNECTOR_eDP; | |
11c3ee48 AD |
6912 | case SIGNAL_TYPE_LVDS: |
6913 | return DRM_MODE_CONNECTOR_LVDS; | |
e7b07cee HW |
6914 | case SIGNAL_TYPE_RGB: |
6915 | return DRM_MODE_CONNECTOR_VGA; | |
6916 | case SIGNAL_TYPE_DISPLAY_PORT: | |
6917 | case SIGNAL_TYPE_DISPLAY_PORT_MST: | |
6918 | return DRM_MODE_CONNECTOR_DisplayPort; | |
6919 | case SIGNAL_TYPE_DVI_DUAL_LINK: | |
6920 | case SIGNAL_TYPE_DVI_SINGLE_LINK: | |
6921 | return DRM_MODE_CONNECTOR_DVID; | |
6922 | case SIGNAL_TYPE_VIRTUAL: | |
6923 | return DRM_MODE_CONNECTOR_VIRTUAL; | |
6924 | ||
6925 | default: | |
6926 | return DRM_MODE_CONNECTOR_Unknown; | |
6927 | } | |
6928 | } | |
6929 | ||
2b4c1c05 DV |
6930 | static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) |
6931 | { | |
62afb4ad JRS |
6932 | struct drm_encoder *encoder; |
6933 | ||
6934 | /* There is only one encoder per connector */ | |
6935 | drm_connector_for_each_possible_encoder(connector, encoder) | |
6936 | return encoder; | |
6937 | ||
6938 | return NULL; | |
2b4c1c05 DV |
6939 | } |
6940 | ||
e7b07cee HW |
6941 | static void amdgpu_dm_get_native_mode(struct drm_connector *connector) |
6942 | { | |
e7b07cee HW |
6943 | struct drm_encoder *encoder; |
6944 | struct amdgpu_encoder *amdgpu_encoder; | |
6945 | ||
2b4c1c05 | 6946 | encoder = amdgpu_dm_connector_to_encoder(connector); |
e7b07cee HW |
6947 | |
6948 | if (encoder == NULL) | |
6949 | return; | |
6950 | ||
6951 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
6952 | ||
6953 | amdgpu_encoder->native_mode.clock = 0; | |
6954 | ||
6955 | if (!list_empty(&connector->probed_modes)) { | |
6956 | struct drm_display_mode *preferred_mode = NULL; | |
b830ebc9 | 6957 | |
e7b07cee | 6958 | list_for_each_entry(preferred_mode, |
b830ebc9 HW |
6959 | &connector->probed_modes, |
6960 | head) { | |
6961 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) | |
6962 | amdgpu_encoder->native_mode = *preferred_mode; | |
6963 | ||
e7b07cee HW |
6964 | break; |
6965 | } | |
6966 | ||
6967 | } | |
6968 | } | |
6969 | ||
3ee6b26b AD |
6970 | static struct drm_display_mode * |
6971 | amdgpu_dm_create_common_mode(struct drm_encoder *encoder, | |
6972 | char *name, | |
6973 | int hdisplay, int vdisplay) | |
e7b07cee HW |
6974 | { |
6975 | struct drm_device *dev = encoder->dev; | |
6976 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
6977 | struct drm_display_mode *mode = NULL; | |
6978 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
6979 | ||
6980 | mode = drm_mode_duplicate(dev, native_mode); | |
6981 | ||
b830ebc9 | 6982 | if (mode == NULL) |
e7b07cee HW |
6983 | return NULL; |
6984 | ||
6985 | mode->hdisplay = hdisplay; | |
6986 | mode->vdisplay = vdisplay; | |
6987 | mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
090afc1e | 6988 | strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); |
e7b07cee HW |
6989 | |
6990 | return mode; | |
6991 | ||
6992 | } | |
6993 | ||
6994 | static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, | |
3ee6b26b | 6995 | struct drm_connector *connector) |
e7b07cee HW |
6996 | { |
6997 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
6998 | struct drm_display_mode *mode = NULL; | |
6999 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
c84dec2f HW |
7000 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7001 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
7002 | int i; |
7003 | int n; | |
7004 | struct mode_size { | |
7005 | char name[DRM_DISPLAY_MODE_LEN]; | |
7006 | int w; | |
7007 | int h; | |
b830ebc9 | 7008 | } common_modes[] = { |
e7b07cee HW |
7009 | { "640x480", 640, 480}, |
7010 | { "800x600", 800, 600}, | |
7011 | { "1024x768", 1024, 768}, | |
7012 | { "1280x720", 1280, 720}, | |
7013 | { "1280x800", 1280, 800}, | |
7014 | {"1280x1024", 1280, 1024}, | |
7015 | { "1440x900", 1440, 900}, | |
7016 | {"1680x1050", 1680, 1050}, | |
7017 | {"1600x1200", 1600, 1200}, | |
7018 | {"1920x1080", 1920, 1080}, | |
7019 | {"1920x1200", 1920, 1200} | |
7020 | }; | |
7021 | ||
b830ebc9 | 7022 | n = ARRAY_SIZE(common_modes); |
e7b07cee HW |
7023 | |
7024 | for (i = 0; i < n; i++) { | |
7025 | struct drm_display_mode *curmode = NULL; | |
7026 | bool mode_existed = false; | |
7027 | ||
7028 | if (common_modes[i].w > native_mode->hdisplay || | |
b830ebc9 HW |
7029 | common_modes[i].h > native_mode->vdisplay || |
7030 | (common_modes[i].w == native_mode->hdisplay && | |
7031 | common_modes[i].h == native_mode->vdisplay)) | |
7032 | continue; | |
e7b07cee HW |
7033 | |
7034 | list_for_each_entry(curmode, &connector->probed_modes, head) { | |
7035 | if (common_modes[i].w == curmode->hdisplay && | |
b830ebc9 | 7036 | common_modes[i].h == curmode->vdisplay) { |
e7b07cee HW |
7037 | mode_existed = true; |
7038 | break; | |
7039 | } | |
7040 | } | |
7041 | ||
7042 | if (mode_existed) | |
7043 | continue; | |
7044 | ||
7045 | mode = amdgpu_dm_create_common_mode(encoder, | |
7046 | common_modes[i].name, common_modes[i].w, | |
7047 | common_modes[i].h); | |
588a7017 ZQ |
7048 | if (!mode) |
7049 | continue; | |
7050 | ||
e7b07cee | 7051 | drm_mode_probed_add(connector, mode); |
c84dec2f | 7052 | amdgpu_dm_connector->num_modes++; |
e7b07cee HW |
7053 | } |
7054 | } | |
7055 | ||
d77de788 SS |
7056 | static void amdgpu_set_panel_orientation(struct drm_connector *connector) |
7057 | { | |
7058 | struct drm_encoder *encoder; | |
7059 | struct amdgpu_encoder *amdgpu_encoder; | |
7060 | const struct drm_display_mode *native_mode; | |
7061 | ||
7062 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && | |
7063 | connector->connector_type != DRM_MODE_CONNECTOR_LVDS) | |
7064 | return; | |
7065 | ||
acc96ae0 MW |
7066 | mutex_lock(&connector->dev->mode_config.mutex); |
7067 | amdgpu_dm_connector_get_modes(connector); | |
7068 | mutex_unlock(&connector->dev->mode_config.mutex); | |
7069 | ||
d77de788 SS |
7070 | encoder = amdgpu_dm_connector_to_encoder(connector); |
7071 | if (!encoder) | |
7072 | return; | |
7073 | ||
7074 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
7075 | ||
7076 | native_mode = &amdgpu_encoder->native_mode; | |
7077 | if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) | |
7078 | return; | |
7079 | ||
7080 | drm_connector_set_panel_orientation_with_quirk(connector, | |
7081 | DRM_MODE_PANEL_ORIENTATION_UNKNOWN, | |
7082 | native_mode->hdisplay, | |
7083 | native_mode->vdisplay); | |
7084 | } | |
7085 | ||
3ee6b26b AD |
7086 | static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, |
7087 | struct edid *edid) | |
e7b07cee | 7088 | { |
c84dec2f HW |
7089 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7090 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
7091 | |
7092 | if (edid) { | |
7093 | /* empty probed_modes */ | |
7094 | INIT_LIST_HEAD(&connector->probed_modes); | |
c84dec2f | 7095 | amdgpu_dm_connector->num_modes = |
e7b07cee HW |
7096 | drm_add_edid_modes(connector, edid); |
7097 | ||
f1e5e913 YMM |
7098 | /* sorting the probed modes before calling function |
7099 | * amdgpu_dm_get_native_mode() since EDID can have | |
7100 | * more than one preferred mode. The modes that are | |
7101 | * later in the probed mode list could be of higher | |
7102 | * and preferred resolution. For example, 3840x2160 | |
7103 | * resolution in base EDID preferred timing and 4096x2160 | |
7104 | * preferred resolution in DID extension block later. | |
7105 | */ | |
7106 | drm_mode_sort(&connector->probed_modes); | |
e7b07cee | 7107 | amdgpu_dm_get_native_mode(connector); |
f9b4f20c SW |
7108 | |
7109 | /* Freesync capabilities are reset by calling | |
7110 | * drm_add_edid_modes() and need to be | |
7111 | * restored here. | |
7112 | */ | |
7113 | amdgpu_dm_update_freesync_caps(connector, edid); | |
a8d8d3dc | 7114 | } else { |
c84dec2f | 7115 | amdgpu_dm_connector->num_modes = 0; |
a8d8d3dc | 7116 | } |
e7b07cee HW |
7117 | } |
7118 | ||
a85ba005 NC |
7119 | static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, |
7120 | struct drm_display_mode *mode) | |
7121 | { | |
7122 | struct drm_display_mode *m; | |
7123 | ||
c82eddf8 | 7124 | list_for_each_entry(m, &aconnector->base.probed_modes, head) { |
a85ba005 NC |
7125 | if (drm_mode_equal(m, mode)) |
7126 | return true; | |
7127 | } | |
7128 | ||
7129 | return false; | |
7130 | } | |
7131 | ||
7132 | static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) | |
7133 | { | |
7134 | const struct drm_display_mode *m; | |
7135 | struct drm_display_mode *new_mode; | |
7136 | uint i; | |
ae67558b | 7137 | u32 new_modes_count = 0; |
a85ba005 NC |
7138 | |
7139 | /* Standard FPS values | |
7140 | * | |
12cdff6b | 7141 | * 23.976 - TV/NTSC |
3335a135 UKK |
7142 | * 24 - Cinema |
7143 | * 25 - TV/PAL | |
12cdff6b | 7144 | * 29.97 - TV/NTSC |
3335a135 UKK |
7145 | * 30 - TV/NTSC |
7146 | * 48 - Cinema HFR | |
7147 | * 50 - TV/PAL | |
7148 | * 60 - Commonly used | |
12cdff6b | 7149 | * 48,72,96,120 - Multiples of 24 |
a85ba005 | 7150 | */ |
ae67558b | 7151 | static const u32 common_rates[] = { |
9ce5ed6e | 7152 | 23976, 24000, 25000, 29970, 30000, |
12cdff6b | 7153 | 48000, 50000, 60000, 72000, 96000, 120000 |
9ce5ed6e | 7154 | }; |
a85ba005 NC |
7155 | |
7156 | /* | |
7157 | * Find mode with highest refresh rate with the same resolution | |
7158 | * as the preferred mode. Some monitors report a preferred mode | |
7159 | * with lower resolution than the highest refresh rate supported. | |
7160 | */ | |
7161 | ||
7162 | m = get_highest_refresh_rate_mode(aconnector, true); | |
7163 | if (!m) | |
7164 | return 0; | |
7165 | ||
7166 | for (i = 0; i < ARRAY_SIZE(common_rates); i++) { | |
ae67558b SS |
7167 | u64 target_vtotal, target_vtotal_diff; |
7168 | u64 num, den; | |
a85ba005 NC |
7169 | |
7170 | if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) | |
7171 | continue; | |
7172 | ||
7173 | if (common_rates[i] < aconnector->min_vfreq * 1000 || | |
7174 | common_rates[i] > aconnector->max_vfreq * 1000) | |
7175 | continue; | |
7176 | ||
7177 | num = (unsigned long long)m->clock * 1000 * 1000; | |
7178 | den = common_rates[i] * (unsigned long long)m->htotal; | |
7179 | target_vtotal = div_u64(num, den); | |
7180 | target_vtotal_diff = target_vtotal - m->vtotal; | |
7181 | ||
7182 | /* Check for illegal modes */ | |
7183 | if (m->vsync_start + target_vtotal_diff < m->vdisplay || | |
7184 | m->vsync_end + target_vtotal_diff < m->vsync_start || | |
7185 | m->vtotal + target_vtotal_diff < m->vsync_end) | |
7186 | continue; | |
7187 | ||
7188 | new_mode = drm_mode_duplicate(aconnector->base.dev, m); | |
7189 | if (!new_mode) | |
7190 | goto out; | |
7191 | ||
7192 | new_mode->vtotal += (u16)target_vtotal_diff; | |
7193 | new_mode->vsync_start += (u16)target_vtotal_diff; | |
7194 | new_mode->vsync_end += (u16)target_vtotal_diff; | |
7195 | new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
7196 | new_mode->type |= DRM_MODE_TYPE_DRIVER; | |
7197 | ||
7198 | if (!is_duplicate_mode(aconnector, new_mode)) { | |
7199 | drm_mode_probed_add(&aconnector->base, new_mode); | |
7200 | new_modes_count += 1; | |
7201 | } else | |
7202 | drm_mode_destroy(aconnector->base.dev, new_mode); | |
7203 | } | |
7204 | out: | |
7205 | return new_modes_count; | |
7206 | } | |
7207 | ||
7208 | static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, | |
7209 | struct edid *edid) | |
7210 | { | |
7211 | struct amdgpu_dm_connector *amdgpu_dm_connector = | |
7212 | to_amdgpu_dm_connector(connector); | |
7213 | ||
11b92df8 | 7214 | if (!edid) |
a85ba005 | 7215 | return; |
fe8858bb | 7216 | |
a85ba005 NC |
7217 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) |
7218 | amdgpu_dm_connector->num_modes += | |
7219 | add_fs_modes(amdgpu_dm_connector); | |
7220 | } | |
7221 | ||
7578ecda | 7222 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) |
e7b07cee | 7223 | { |
c84dec2f HW |
7224 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7225 | to_amdgpu_dm_connector(connector); | |
e7b07cee | 7226 | struct drm_encoder *encoder; |
c84dec2f | 7227 | struct edid *edid = amdgpu_dm_connector->edid; |
c32699ca JD |
7228 | struct dc_link_settings *verified_link_cap = |
7229 | &amdgpu_dm_connector->dc_link->verified_link_cap; | |
98ce7d32 | 7230 | const struct dc *dc = amdgpu_dm_connector->dc_link->dc; |
e7b07cee | 7231 | |
2b4c1c05 | 7232 | encoder = amdgpu_dm_connector_to_encoder(connector); |
3e332d3a | 7233 | |
5c0e6840 | 7234 | if (!drm_edid_is_valid(edid)) { |
1b369d3c ML |
7235 | amdgpu_dm_connector->num_modes = |
7236 | drm_add_modes_noedid(connector, 640, 480); | |
98ce7d32 | 7237 | if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) |
c32699ca JD |
7238 | amdgpu_dm_connector->num_modes += |
7239 | drm_add_modes_noedid(connector, 1920, 1080); | |
85ee15d6 ML |
7240 | } else { |
7241 | amdgpu_dm_connector_ddc_get_modes(connector, edid); | |
d6149086 | 7242 | amdgpu_dm_connector_add_common_modes(encoder, connector); |
a85ba005 | 7243 | amdgpu_dm_connector_add_freesync_modes(connector, edid); |
85ee15d6 | 7244 | } |
3e332d3a | 7245 | amdgpu_dm_fbc_init(connector); |
5099114b | 7246 | |
c84dec2f | 7247 | return amdgpu_dm_connector->num_modes; |
e7b07cee HW |
7248 | } |
7249 | ||
15f9dfd5 HW |
7250 | static const u32 supported_colorspaces = |
7251 | BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | | |
7252 | BIT(DRM_MODE_COLORIMETRY_OPRGB) | | |
7253 | BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | | |
7254 | BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); | |
7255 | ||
3ee6b26b AD |
7256 | void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, |
7257 | struct amdgpu_dm_connector *aconnector, | |
7258 | int connector_type, | |
7259 | struct dc_link *link, | |
7260 | int link_index) | |
e7b07cee | 7261 | { |
1348969a | 7262 | struct amdgpu_device *adev = drm_to_adev(dm->ddev); |
e7b07cee | 7263 | |
f04bee34 NK |
7264 | /* |
7265 | * Some of the properties below require access to state, like bpc. | |
7266 | * Allocate some default initial connector state with our reset helper. | |
7267 | */ | |
7268 | if (aconnector->base.funcs->reset) | |
7269 | aconnector->base.funcs->reset(&aconnector->base); | |
7270 | ||
e7b07cee | 7271 | aconnector->connector_id = link_index; |
f196198c | 7272 | aconnector->bl_idx = -1; |
e7b07cee HW |
7273 | aconnector->dc_link = link; |
7274 | aconnector->base.interlace_allowed = false; | |
7275 | aconnector->base.doublescan_allowed = false; | |
7276 | aconnector->base.stereo_allowed = false; | |
7277 | aconnector->base.dpms = DRM_MODE_DPMS_OFF; | |
7278 | aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ | |
6ce8f316 | 7279 | aconnector->audio_inst = -1; |
5b49da02 SJK |
7280 | aconnector->pack_sdp_v1_3 = false; |
7281 | aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; | |
7282 | memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); | |
e7b07cee | 7283 | mutex_init(&aconnector->hpd_lock); |
bb4fa525 | 7284 | mutex_init(&aconnector->handle_mst_msg_ready); |
e7b07cee | 7285 | |
1f6010a9 DF |
7286 | /* |
7287 | * configure support HPD hot plug connector_>polled default value is 0 | |
b830ebc9 HW |
7288 | * which means HPD hot plug not supported |
7289 | */ | |
e7b07cee HW |
7290 | switch (connector_type) { |
7291 | case DRM_MODE_CONNECTOR_HDMIA: | |
7292 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
e7baae1c | 7293 | aconnector->base.ycbcr_420_allowed = |
9ea59d5a | 7294 | link->link_enc->features.hdmi_ycbcr420_supported ? true : false; |
e7b07cee HW |
7295 | break; |
7296 | case DRM_MODE_CONNECTOR_DisplayPort: | |
7297 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
d715c9a2 | 7298 | link->link_enc = link_enc_cfg_get_link_enc(link); |
7b201d53 | 7299 | ASSERT(link->link_enc); |
f6e03f80 JS |
7300 | if (link->link_enc) |
7301 | aconnector->base.ycbcr_420_allowed = | |
9ea59d5a | 7302 | link->link_enc->features.dp_ycbcr420_supported ? true : false; |
e7b07cee HW |
7303 | break; |
7304 | case DRM_MODE_CONNECTOR_DVID: | |
7305 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
7306 | break; | |
7307 | default: | |
7308 | break; | |
7309 | } | |
7310 | ||
7311 | drm_object_attach_property(&aconnector->base.base, | |
7312 | dm->ddev->mode_config.scaling_mode_property, | |
7313 | DRM_MODE_SCALE_NONE); | |
7314 | ||
7315 | drm_object_attach_property(&aconnector->base.base, | |
7316 | adev->mode_info.underscan_property, | |
7317 | UNDERSCAN_OFF); | |
7318 | drm_object_attach_property(&aconnector->base.base, | |
7319 | adev->mode_info.underscan_hborder_property, | |
7320 | 0); | |
7321 | drm_object_attach_property(&aconnector->base.base, | |
7322 | adev->mode_info.underscan_vborder_property, | |
7323 | 0); | |
1825fd34 | 7324 | |
f0127cb1 | 7325 | if (!aconnector->mst_root) |
8c61b31e | 7326 | drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); |
1825fd34 | 7327 | |
e47f1691 | 7328 | aconnector->base.state->max_bpc = 16; |
4a8ca46b | 7329 | aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; |
e7b07cee | 7330 | |
c1ee92f9 | 7331 | if (connector_type == DRM_MODE_CONNECTOR_eDP && |
5cb32419 | 7332 | (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { |
c1ee92f9 DF |
7333 | drm_object_attach_property(&aconnector->base.base, |
7334 | adev->mode_info.abm_level_property, 0); | |
7335 | } | |
bb47de73 | 7336 | |
15f9dfd5 HW |
7337 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
7338 | if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) | |
7339 | drm_connector_attach_colorspace_property(&aconnector->base); | |
69a95961 | 7340 | } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || |
15f9dfd5 HW |
7341 | connector_type == DRM_MODE_CONNECTOR_eDP) { |
7342 | if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) | |
7343 | drm_connector_attach_colorspace_property(&aconnector->base); | |
7344 | } | |
7345 | ||
bb47de73 | 7346 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA || |
7fad8da1 NK |
7347 | connector_type == DRM_MODE_CONNECTOR_DisplayPort || |
7348 | connector_type == DRM_MODE_CONNECTOR_eDP) { | |
e057b52c | 7349 | drm_connector_attach_hdr_output_metadata_property(&aconnector->base); |
88694af9 | 7350 | |
f0127cb1 | 7351 | if (!aconnector->mst_root) |
8c61b31e JFZ |
7352 | drm_connector_attach_vrr_capable_property(&aconnector->base); |
7353 | ||
e22bb562 | 7354 | if (adev->dm.hdcp_workqueue) |
53e108aa | 7355 | drm_connector_attach_content_protection_property(&aconnector->base, true); |
bb47de73 | 7356 | } |
e7b07cee HW |
7357 | } |
7358 | ||
7578ecda AD |
7359 | static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, |
7360 | struct i2c_msg *msgs, int num) | |
e7b07cee HW |
7361 | { |
7362 | struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); | |
7363 | struct ddc_service *ddc_service = i2c->ddc_service; | |
7364 | struct i2c_command cmd; | |
7365 | int i; | |
7366 | int result = -EIO; | |
7367 | ||
b830ebc9 | 7368 | cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); |
e7b07cee HW |
7369 | |
7370 | if (!cmd.payloads) | |
7371 | return result; | |
7372 | ||
7373 | cmd.number_of_payloads = num; | |
7374 | cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; | |
7375 | cmd.speed = 100; | |
7376 | ||
7377 | for (i = 0; i < num; i++) { | |
7378 | cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); | |
7379 | cmd.payloads[i].address = msgs[i].addr; | |
7380 | cmd.payloads[i].length = msgs[i].len; | |
7381 | cmd.payloads[i].data = msgs[i].buf; | |
7382 | } | |
7383 | ||
c85e6e54 DF |
7384 | if (dc_submit_i2c( |
7385 | ddc_service->ctx->dc, | |
22676bc5 | 7386 | ddc_service->link->link_index, |
e7b07cee HW |
7387 | &cmd)) |
7388 | result = num; | |
7389 | ||
7390 | kfree(cmd.payloads); | |
7391 | return result; | |
7392 | } | |
7393 | ||
7578ecda | 7394 | static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) |
e7b07cee HW |
7395 | { |
7396 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
7397 | } | |
7398 | ||
7399 | static const struct i2c_algorithm amdgpu_dm_i2c_algo = { | |
7400 | .master_xfer = amdgpu_dm_i2c_xfer, | |
7401 | .functionality = amdgpu_dm_i2c_func, | |
7402 | }; | |
7403 | ||
3ee6b26b AD |
7404 | static struct amdgpu_i2c_adapter * |
7405 | create_i2c(struct ddc_service *ddc_service, | |
7406 | int link_index, | |
7407 | int *res) | |
e7b07cee HW |
7408 | { |
7409 | struct amdgpu_device *adev = ddc_service->ctx->driver_context; | |
7410 | struct amdgpu_i2c_adapter *i2c; | |
7411 | ||
b830ebc9 | 7412 | i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); |
2a55f096 ES |
7413 | if (!i2c) |
7414 | return NULL; | |
e7b07cee HW |
7415 | i2c->base.owner = THIS_MODULE; |
7416 | i2c->base.class = I2C_CLASS_DDC; | |
7417 | i2c->base.dev.parent = &adev->pdev->dev; | |
7418 | i2c->base.algo = &amdgpu_dm_i2c_algo; | |
b830ebc9 | 7419 | snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); |
e7b07cee HW |
7420 | i2c_set_adapdata(&i2c->base, i2c); |
7421 | i2c->ddc_service = ddc_service; | |
7422 | ||
7423 | return i2c; | |
7424 | } | |
7425 | ||
89fc8d4e | 7426 | |
1f6010a9 DF |
7427 | /* |
7428 | * Note: this function assumes that dc_link_detect() was called for the | |
b830ebc9 HW |
7429 | * dc_link which will be represented by this aconnector. |
7430 | */ | |
7578ecda AD |
7431 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
7432 | struct amdgpu_dm_connector *aconnector, | |
ae67558b | 7433 | u32 link_index, |
7578ecda | 7434 | struct amdgpu_encoder *aencoder) |
e7b07cee HW |
7435 | { |
7436 | int res = 0; | |
7437 | int connector_type; | |
7438 | struct dc *dc = dm->dc; | |
7439 | struct dc_link *link = dc_get_link_at_index(dc, link_index); | |
7440 | struct amdgpu_i2c_adapter *i2c; | |
9a227d26 TSD |
7441 | |
7442 | link->priv = aconnector; | |
e7b07cee | 7443 | |
e7b07cee HW |
7444 | |
7445 | i2c = create_i2c(link->ddc, link->link_index, &res); | |
2a55f096 ES |
7446 | if (!i2c) { |
7447 | DRM_ERROR("Failed to create i2c adapter data\n"); | |
7448 | return -ENOMEM; | |
7449 | } | |
7450 | ||
e7b07cee HW |
7451 | aconnector->i2c = i2c; |
7452 | res = i2c_add_adapter(&i2c->base); | |
7453 | ||
7454 | if (res) { | |
7455 | DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); | |
7456 | goto out_free; | |
7457 | } | |
7458 | ||
7459 | connector_type = to_drm_connector_type(link->connector_signal); | |
7460 | ||
17165de2 | 7461 | res = drm_connector_init_with_ddc( |
e7b07cee HW |
7462 | dm->ddev, |
7463 | &aconnector->base, | |
7464 | &amdgpu_dm_connector_funcs, | |
17165de2 AP |
7465 | connector_type, |
7466 | &i2c->base); | |
e7b07cee HW |
7467 | |
7468 | if (res) { | |
7469 | DRM_ERROR("connector_init failed\n"); | |
7470 | aconnector->connector_id = -1; | |
7471 | goto out_free; | |
7472 | } | |
7473 | ||
7474 | drm_connector_helper_add( | |
7475 | &aconnector->base, | |
7476 | &amdgpu_dm_connector_helper_funcs); | |
7477 | ||
7478 | amdgpu_dm_connector_init_helper( | |
7479 | dm, | |
7480 | aconnector, | |
7481 | connector_type, | |
7482 | link, | |
7483 | link_index); | |
7484 | ||
cde4c44d | 7485 | drm_connector_attach_encoder( |
e7b07cee HW |
7486 | &aconnector->base, &aencoder->base); |
7487 | ||
e7b07cee HW |
7488 | if (connector_type == DRM_MODE_CONNECTOR_DisplayPort |
7489 | || connector_type == DRM_MODE_CONNECTOR_eDP) | |
7daec99f | 7490 | amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); |
e7b07cee | 7491 | |
e7b07cee HW |
7492 | out_free: |
7493 | if (res) { | |
7494 | kfree(i2c); | |
7495 | aconnector->i2c = NULL; | |
7496 | } | |
7497 | return res; | |
7498 | } | |
7499 | ||
7500 | int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) | |
7501 | { | |
7502 | switch (adev->mode_info.num_crtc) { | |
7503 | case 1: | |
7504 | return 0x1; | |
7505 | case 2: | |
7506 | return 0x3; | |
7507 | case 3: | |
7508 | return 0x7; | |
7509 | case 4: | |
7510 | return 0xf; | |
7511 | case 5: | |
7512 | return 0x1f; | |
7513 | case 6: | |
7514 | default: | |
7515 | return 0x3f; | |
7516 | } | |
7517 | } | |
7518 | ||
7578ecda AD |
7519 | static int amdgpu_dm_encoder_init(struct drm_device *dev, |
7520 | struct amdgpu_encoder *aencoder, | |
7521 | uint32_t link_index) | |
e7b07cee | 7522 | { |
1348969a | 7523 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
7524 | |
7525 | int res = drm_encoder_init(dev, | |
7526 | &aencoder->base, | |
7527 | &amdgpu_dm_encoder_funcs, | |
7528 | DRM_MODE_ENCODER_TMDS, | |
7529 | NULL); | |
7530 | ||
7531 | aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); | |
7532 | ||
7533 | if (!res) | |
7534 | aencoder->encoder_id = link_index; | |
7535 | else | |
7536 | aencoder->encoder_id = -1; | |
7537 | ||
7538 | drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); | |
7539 | ||
7540 | return res; | |
7541 | } | |
7542 | ||
3ee6b26b AD |
7543 | static void manage_dm_interrupts(struct amdgpu_device *adev, |
7544 | struct amdgpu_crtc *acrtc, | |
7545 | bool enable) | |
e7b07cee HW |
7546 | { |
7547 | /* | |
8fe684e9 NK |
7548 | * We have no guarantee that the frontend index maps to the same |
7549 | * backend index - some even map to more than one. | |
7550 | * | |
7551 | * TODO: Use a different interrupt or check DC itself for the mapping. | |
e7b07cee HW |
7552 | */ |
7553 | int irq_type = | |
734dd01d | 7554 | amdgpu_display_crtc_idx_to_irq_type( |
e7b07cee HW |
7555 | adev, |
7556 | acrtc->crtc_id); | |
7557 | ||
7558 | if (enable) { | |
7559 | drm_crtc_vblank_on(&acrtc->base); | |
7560 | amdgpu_irq_get( | |
7561 | adev, | |
7562 | &adev->pageflip_irq, | |
7563 | irq_type); | |
86bc2219 WL |
7564 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
7565 | amdgpu_irq_get( | |
7566 | adev, | |
7567 | &adev->vline0_irq, | |
7568 | irq_type); | |
7569 | #endif | |
e7b07cee | 7570 | } else { |
86bc2219 WL |
7571 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
7572 | amdgpu_irq_put( | |
7573 | adev, | |
7574 | &adev->vline0_irq, | |
7575 | irq_type); | |
7576 | #endif | |
e7b07cee HW |
7577 | amdgpu_irq_put( |
7578 | adev, | |
7579 | &adev->pageflip_irq, | |
7580 | irq_type); | |
7581 | drm_crtc_vblank_off(&acrtc->base); | |
7582 | } | |
7583 | } | |
7584 | ||
8fe684e9 NK |
7585 | static void dm_update_pflip_irq_state(struct amdgpu_device *adev, |
7586 | struct amdgpu_crtc *acrtc) | |
7587 | { | |
7588 | int irq_type = | |
7589 | amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); | |
7590 | ||
7591 | /** | |
7592 | * This reads the current state for the IRQ and force reapplies | |
7593 | * the setting to hardware. | |
7594 | */ | |
7595 | amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); | |
7596 | } | |
7597 | ||
3ee6b26b AD |
7598 | static bool |
7599 | is_scaling_state_different(const struct dm_connector_state *dm_state, | |
7600 | const struct dm_connector_state *old_dm_state) | |
e7b07cee HW |
7601 | { |
7602 | if (dm_state->scaling != old_dm_state->scaling) | |
7603 | return true; | |
7604 | if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { | |
7605 | if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) | |
7606 | return true; | |
7607 | } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { | |
7608 | if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) | |
7609 | return true; | |
b830ebc9 HW |
7610 | } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || |
7611 | dm_state->underscan_vborder != old_dm_state->underscan_vborder) | |
7612 | return true; | |
e7b07cee HW |
7613 | return false; |
7614 | } | |
7615 | ||
e8fd3eeb | 7616 | static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, |
7617 | struct drm_crtc_state *old_crtc_state, | |
7618 | struct drm_connector_state *new_conn_state, | |
7619 | struct drm_connector_state *old_conn_state, | |
7620 | const struct drm_connector *connector, | |
7621 | struct hdcp_workqueue *hdcp_w) | |
0c8620d6 BL |
7622 | { |
7623 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
97f6c917 | 7624 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); |
0c8620d6 | 7625 | |
e8fd3eeb | 7626 | pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", |
7627 | connector->index, connector->status, connector->dpms); | |
7628 | pr_debug("[HDCP_DM] state protection old: %x new: %x\n", | |
7629 | old_conn_state->content_protection, new_conn_state->content_protection); | |
7630 | ||
7631 | if (old_crtc_state) | |
7632 | pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
7633 | old_crtc_state->enable, | |
7634 | old_crtc_state->active, | |
7635 | old_crtc_state->mode_changed, | |
7636 | old_crtc_state->active_changed, | |
7637 | old_crtc_state->connectors_changed); | |
7638 | ||
7639 | if (new_crtc_state) | |
7640 | pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
7641 | new_crtc_state->enable, | |
7642 | new_crtc_state->active, | |
7643 | new_crtc_state->mode_changed, | |
7644 | new_crtc_state->active_changed, | |
7645 | new_crtc_state->connectors_changed); | |
7646 | ||
7647 | /* hdcp content type change */ | |
7648 | if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && | |
7649 | new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { | |
7650 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
7651 | pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); | |
53e108aa BL |
7652 | return true; |
7653 | } | |
7654 | ||
e8fd3eeb | 7655 | /* CP is being re enabled, ignore this */ |
7656 | if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && | |
7657 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { | |
7658 | if (new_crtc_state && new_crtc_state->mode_changed) { | |
7659 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
7660 | pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); | |
7661 | return true; | |
0b8f42ab | 7662 | } |
e8fd3eeb | 7663 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; |
7664 | pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); | |
0c8620d6 BL |
7665 | return false; |
7666 | } | |
7667 | ||
31c0ed90 BL |
7668 | /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED |
7669 | * | |
7670 | * Handles: UNDESIRED -> ENABLED | |
7671 | */ | |
e8fd3eeb | 7672 | if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && |
7673 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) | |
7674 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
0c8620d6 | 7675 | |
0d9a947b QZ |
7676 | /* Stream removed and re-enabled |
7677 | * | |
7678 | * Can sometimes overlap with the HPD case, | |
7679 | * thus set update_hdcp to false to avoid | |
7680 | * setting HDCP multiple times. | |
7681 | * | |
7682 | * Handles: DESIRED -> DESIRED (Special case) | |
7683 | */ | |
e8fd3eeb | 7684 | if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && |
7685 | new_conn_state->crtc && new_conn_state->crtc->enabled && | |
0d9a947b QZ |
7686 | connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { |
7687 | dm_con_state->update_hdcp = false; | |
e8fd3eeb | 7688 | pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", |
7689 | __func__); | |
0d9a947b QZ |
7690 | return true; |
7691 | } | |
7692 | ||
7693 | /* Hot-plug, headless s3, dpms | |
7694 | * | |
7695 | * Only start HDCP if the display is connected/enabled. | |
7696 | * update_hdcp flag will be set to false until the next | |
7697 | * HPD comes in. | |
31c0ed90 BL |
7698 | * |
7699 | * Handles: DESIRED -> DESIRED (Special case) | |
0c8620d6 | 7700 | */ |
e8fd3eeb | 7701 | if (dm_con_state->update_hdcp && |
7702 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && | |
7703 | connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { | |
97f6c917 | 7704 | dm_con_state->update_hdcp = false; |
e8fd3eeb | 7705 | pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", |
7706 | __func__); | |
0c8620d6 | 7707 | return true; |
97f6c917 | 7708 | } |
0c8620d6 | 7709 | |
e8fd3eeb | 7710 | if (old_conn_state->content_protection == new_conn_state->content_protection) { |
7711 | if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { | |
7712 | if (new_crtc_state && new_crtc_state->mode_changed) { | |
7713 | pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", | |
7714 | __func__); | |
7715 | return true; | |
0b8f42ab | 7716 | } |
e8fd3eeb | 7717 | pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", |
7718 | __func__); | |
7719 | return false; | |
0b8f42ab | 7720 | } |
e8fd3eeb | 7721 | |
7722 | pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); | |
0c8620d6 | 7723 | return false; |
e8fd3eeb | 7724 | } |
0c8620d6 | 7725 | |
e8fd3eeb | 7726 | if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { |
7727 | pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", | |
7728 | __func__); | |
0c8620d6 | 7729 | return true; |
e8fd3eeb | 7730 | } |
0c8620d6 | 7731 | |
e8fd3eeb | 7732 | pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); |
0c8620d6 BL |
7733 | return false; |
7734 | } | |
e8fd3eeb | 7735 | |
3ee6b26b AD |
7736 | static void remove_stream(struct amdgpu_device *adev, |
7737 | struct amdgpu_crtc *acrtc, | |
7738 | struct dc_stream_state *stream) | |
e7b07cee HW |
7739 | { |
7740 | /* this is the update mode case */ | |
e7b07cee HW |
7741 | |
7742 | acrtc->otg_inst = -1; | |
7743 | acrtc->enabled = false; | |
7744 | } | |
7745 | ||
e7b07cee HW |
7746 | static void prepare_flip_isr(struct amdgpu_crtc *acrtc) |
7747 | { | |
7748 | ||
7749 | assert_spin_locked(&acrtc->base.dev->event_lock); | |
7750 | WARN_ON(acrtc->event); | |
7751 | ||
7752 | acrtc->event = acrtc->base.state->event; | |
7753 | ||
7754 | /* Set the flip status */ | |
7755 | acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; | |
7756 | ||
7757 | /* Mark this event as consumed */ | |
7758 | acrtc->base.state->event = NULL; | |
7759 | ||
cb2318b7 VL |
7760 | DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", |
7761 | acrtc->crtc_id); | |
e7b07cee HW |
7762 | } |
7763 | ||
bb47de73 NK |
7764 | static void update_freesync_state_on_stream( |
7765 | struct amdgpu_display_manager *dm, | |
7766 | struct dm_crtc_state *new_crtc_state, | |
180db303 NK |
7767 | struct dc_stream_state *new_stream, |
7768 | struct dc_plane_state *surface, | |
7769 | u32 flip_timestamp_in_us) | |
bb47de73 | 7770 | { |
09aef2c4 | 7771 | struct mod_vrr_params vrr_params; |
bb47de73 | 7772 | struct dc_info_packet vrr_infopacket = {0}; |
09aef2c4 | 7773 | struct amdgpu_device *adev = dm->adev; |
585d450c | 7774 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); |
09aef2c4 | 7775 | unsigned long flags; |
4cda3243 | 7776 | bool pack_sdp_v1_3 = false; |
5b49da02 SJK |
7777 | struct amdgpu_dm_connector *aconn; |
7778 | enum vrr_packet_type packet_type = PACKET_TYPE_VRR; | |
bb47de73 NK |
7779 | |
7780 | if (!new_stream) | |
7781 | return; | |
7782 | ||
7783 | /* | |
7784 | * TODO: Determine why min/max totals and vrefresh can be 0 here. | |
7785 | * For now it's sufficient to just guard against these conditions. | |
7786 | */ | |
7787 | ||
7788 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) | |
7789 | return; | |
7790 | ||
4a580877 | 7791 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
3335a135 | 7792 | vrr_params = acrtc->dm_irq_params.vrr_params; |
09aef2c4 | 7793 | |
180db303 NK |
7794 | if (surface) { |
7795 | mod_freesync_handle_preflip( | |
7796 | dm->freesync_module, | |
7797 | surface, | |
7798 | new_stream, | |
7799 | flip_timestamp_in_us, | |
7800 | &vrr_params); | |
09aef2c4 MK |
7801 | |
7802 | if (adev->family < AMDGPU_FAMILY_AI && | |
6c5e25a0 | 7803 | amdgpu_dm_crtc_vrr_active(new_crtc_state)) { |
09aef2c4 MK |
7804 | mod_freesync_handle_v_update(dm->freesync_module, |
7805 | new_stream, &vrr_params); | |
e63e2491 EB |
7806 | |
7807 | /* Need to call this before the frame ends. */ | |
7808 | dc_stream_adjust_vmin_vmax(dm->dc, | |
7809 | new_crtc_state->stream, | |
7810 | &vrr_params.adjust); | |
09aef2c4 | 7811 | } |
180db303 | 7812 | } |
bb47de73 | 7813 | |
5b49da02 SJK |
7814 | aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; |
7815 | ||
81a7be79 | 7816 | if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { |
5b49da02 SJK |
7817 | pack_sdp_v1_3 = aconn->pack_sdp_v1_3; |
7818 | ||
7819 | if (aconn->vsdb_info.amd_vsdb_version == 1) | |
7820 | packet_type = PACKET_TYPE_FS_V1; | |
7821 | else if (aconn->vsdb_info.amd_vsdb_version == 2) | |
7822 | packet_type = PACKET_TYPE_FS_V2; | |
7823 | else if (aconn->vsdb_info.amd_vsdb_version == 3) | |
7824 | packet_type = PACKET_TYPE_FS_V3; | |
7825 | ||
7826 | mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, | |
7827 | &new_stream->adaptive_sync_infopacket); | |
7828 | } | |
7829 | ||
bb47de73 NK |
7830 | mod_freesync_build_vrr_infopacket( |
7831 | dm->freesync_module, | |
7832 | new_stream, | |
180db303 | 7833 | &vrr_params, |
5b49da02 | 7834 | packet_type, |
ecd0136b | 7835 | TRANSFER_FUNC_UNKNOWN, |
4cda3243 MT |
7836 | &vrr_infopacket, |
7837 | pack_sdp_v1_3); | |
bb47de73 | 7838 | |
8a48b44c | 7839 | new_crtc_state->freesync_vrr_info_changed |= |
bb47de73 NK |
7840 | (memcmp(&new_crtc_state->vrr_infopacket, |
7841 | &vrr_infopacket, | |
7842 | sizeof(vrr_infopacket)) != 0); | |
7843 | ||
585d450c | 7844 | acrtc->dm_irq_params.vrr_params = vrr_params; |
bb47de73 NK |
7845 | new_crtc_state->vrr_infopacket = vrr_infopacket; |
7846 | ||
bb47de73 | 7847 | new_stream->vrr_infopacket = vrr_infopacket; |
7eaef116 | 7848 | new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); |
bb47de73 NK |
7849 | |
7850 | if (new_crtc_state->freesync_vrr_info_changed) | |
7851 | DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", | |
7852 | new_crtc_state->base.crtc->base.id, | |
7853 | (int)new_crtc_state->base.vrr_enabled, | |
180db303 | 7854 | (int)vrr_params.state); |
09aef2c4 | 7855 | |
4a580877 | 7856 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
bb47de73 NK |
7857 | } |
7858 | ||
585d450c | 7859 | static void update_stream_irq_parameters( |
e854194c MK |
7860 | struct amdgpu_display_manager *dm, |
7861 | struct dm_crtc_state *new_crtc_state) | |
7862 | { | |
7863 | struct dc_stream_state *new_stream = new_crtc_state->stream; | |
09aef2c4 | 7864 | struct mod_vrr_params vrr_params; |
e854194c | 7865 | struct mod_freesync_config config = new_crtc_state->freesync_config; |
09aef2c4 | 7866 | struct amdgpu_device *adev = dm->adev; |
585d450c | 7867 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); |
09aef2c4 | 7868 | unsigned long flags; |
e854194c MK |
7869 | |
7870 | if (!new_stream) | |
7871 | return; | |
7872 | ||
7873 | /* | |
7874 | * TODO: Determine why min/max totals and vrefresh can be 0 here. | |
7875 | * For now it's sufficient to just guard against these conditions. | |
7876 | */ | |
7877 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) | |
7878 | return; | |
7879 | ||
4a580877 | 7880 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
585d450c | 7881 | vrr_params = acrtc->dm_irq_params.vrr_params; |
09aef2c4 | 7882 | |
e854194c MK |
7883 | if (new_crtc_state->vrr_supported && |
7884 | config.min_refresh_in_uhz && | |
7885 | config.max_refresh_in_uhz) { | |
a85ba005 NC |
7886 | /* |
7887 | * if freesync compatible mode was set, config.state will be set | |
7888 | * in atomic check | |
7889 | */ | |
7890 | if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && | |
7891 | (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || | |
7892 | new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { | |
7893 | vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; | |
7894 | vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; | |
7895 | vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; | |
7896 | vrr_params.state = VRR_STATE_ACTIVE_FIXED; | |
7897 | } else { | |
7898 | config.state = new_crtc_state->base.vrr_enabled ? | |
7899 | VRR_STATE_ACTIVE_VARIABLE : | |
7900 | VRR_STATE_INACTIVE; | |
7901 | } | |
e854194c MK |
7902 | } else { |
7903 | config.state = VRR_STATE_UNSUPPORTED; | |
7904 | } | |
7905 | ||
7906 | mod_freesync_build_vrr_params(dm->freesync_module, | |
7907 | new_stream, | |
7908 | &config, &vrr_params); | |
7909 | ||
585d450c AP |
7910 | new_crtc_state->freesync_config = config; |
7911 | /* Copy state for access from DM IRQ handler */ | |
7912 | acrtc->dm_irq_params.freesync_config = config; | |
7913 | acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; | |
7914 | acrtc->dm_irq_params.vrr_params = vrr_params; | |
4a580877 | 7915 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
e854194c MK |
7916 | } |
7917 | ||
66b0c973 MK |
7918 | static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, |
7919 | struct dm_crtc_state *new_state) | |
7920 | { | |
6c5e25a0 DT |
7921 | bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); |
7922 | bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); | |
66b0c973 MK |
7923 | |
7924 | if (!old_vrr_active && new_vrr_active) { | |
7925 | /* Transition VRR inactive -> active: | |
7926 | * While VRR is active, we must not disable vblank irq, as a | |
7927 | * reenable after disable would compute bogus vblank/pflip | |
7928 | * timestamps if it likely happened inside display front-porch. | |
d2574c33 MK |
7929 | * |
7930 | * We also need vupdate irq for the actual core vblank handling | |
7931 | * at end of vblank. | |
66b0c973 | 7932 | */ |
6c5e25a0 | 7933 | WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); |
8799c0be | 7934 | WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); |
66b0c973 MK |
7935 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", |
7936 | __func__, new_state->base.crtc->base.id); | |
7937 | } else if (old_vrr_active && !new_vrr_active) { | |
7938 | /* Transition VRR active -> inactive: | |
7939 | * Allow vblank irq disable again for fixed refresh rate. | |
7940 | */ | |
6c5e25a0 | 7941 | WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); |
66b0c973 MK |
7942 | drm_crtc_vblank_put(new_state->base.crtc); |
7943 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", | |
7944 | __func__, new_state->base.crtc->base.id); | |
7945 | } | |
7946 | } | |
7947 | ||
8ad27806 NK |
7948 | static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) |
7949 | { | |
7950 | struct drm_plane *plane; | |
5760dcb9 | 7951 | struct drm_plane_state *old_plane_state; |
8ad27806 NK |
7952 | int i; |
7953 | ||
7954 | /* | |
7955 | * TODO: Make this per-stream so we don't issue redundant updates for | |
7956 | * commits with multiple streams. | |
7957 | */ | |
5760dcb9 | 7958 | for_each_old_plane_in_state(state, plane, old_plane_state, i) |
8ad27806 | 7959 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
8bf0d9cd | 7960 | amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); |
8ad27806 NK |
7961 | } |
7962 | ||
08da1821 HM |
7963 | static inline uint32_t get_mem_type(struct drm_framebuffer *fb) |
7964 | { | |
7965 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); | |
7966 | ||
7967 | return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; | |
7968 | } | |
7969 | ||
3be5262e | 7970 | static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, |
3ee6b26b AD |
7971 | struct drm_device *dev, |
7972 | struct amdgpu_display_manager *dm, | |
7973 | struct drm_crtc *pcrtc, | |
420cd472 | 7974 | bool wait_for_vblank) |
e7b07cee | 7975 | { |
ae67558b | 7976 | u32 i; |
d6ed6d0d | 7977 | u64 timestamp_ns = ktime_get_ns(); |
e7b07cee | 7978 | struct drm_plane *plane; |
0bc9706d | 7979 | struct drm_plane_state *old_plane_state, *new_plane_state; |
e7b07cee | 7980 | struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); |
0bc9706d LSL |
7981 | struct drm_crtc_state *new_pcrtc_state = |
7982 | drm_atomic_get_new_crtc_state(state, pcrtc); | |
7983 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); | |
44d09c6a HW |
7984 | struct dm_crtc_state *dm_old_crtc_state = |
7985 | to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); | |
74aa7bd4 | 7986 | int planes_count = 0, vpos, hpos; |
e7b07cee | 7987 | unsigned long flags; |
ae67558b | 7988 | u32 target_vblank, last_flip_vblank; |
6c5e25a0 | 7989 | bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); |
cc79950b | 7990 | bool cursor_update = false; |
74aa7bd4 | 7991 | bool pflip_present = false; |
d6ed6d0d | 7992 | bool dirty_rects_changed = false; |
bc7f670e DF |
7993 | struct { |
7994 | struct dc_surface_update surface_updates[MAX_SURFACES]; | |
7995 | struct dc_plane_info plane_infos[MAX_SURFACES]; | |
7996 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; | |
74aa7bd4 | 7997 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; |
bc7f670e | 7998 | struct dc_stream_update stream_update; |
74aa7bd4 | 7999 | } *bundle; |
bc7f670e | 8000 | |
74aa7bd4 | 8001 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); |
8a48b44c | 8002 | |
74aa7bd4 DF |
8003 | if (!bundle) { |
8004 | dm_error("Failed to allocate update bundle\n"); | |
4b510503 NK |
8005 | goto cleanup; |
8006 | } | |
e7b07cee | 8007 | |
8ad27806 NK |
8008 | /* |
8009 | * Disable the cursor first if we're disabling all the planes. | |
8010 | * It'll remain on the screen after the planes are re-enabled | |
8011 | * if we don't. | |
8012 | */ | |
8013 | if (acrtc_state->active_planes == 0) | |
8014 | amdgpu_dm_commit_cursors(state); | |
8015 | ||
e7b07cee | 8016 | /* update planes when needed */ |
efc8278e | 8017 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { |
0bc9706d | 8018 | struct drm_crtc *crtc = new_plane_state->crtc; |
f5ba60fe | 8019 | struct drm_crtc_state *new_crtc_state; |
0bc9706d | 8020 | struct drm_framebuffer *fb = new_plane_state->fb; |
6eed95b0 | 8021 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; |
34bafd27 | 8022 | bool plane_needs_flip; |
c7af5f77 | 8023 | struct dc_plane_state *dc_plane; |
54d76575 | 8024 | struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); |
e7b07cee | 8025 | |
80c218d5 | 8026 | /* Cursor plane is handled after stream updates */ |
cc79950b MD |
8027 | if (plane->type == DRM_PLANE_TYPE_CURSOR) { |
8028 | if ((fb && crtc == pcrtc) || | |
8029 | (old_plane_state->fb && old_plane_state->crtc == pcrtc)) | |
8030 | cursor_update = true; | |
8031 | ||
e7b07cee | 8032 | continue; |
cc79950b | 8033 | } |
e7b07cee | 8034 | |
f5ba60fe DD |
8035 | if (!fb || !crtc || pcrtc != crtc) |
8036 | continue; | |
8037 | ||
8038 | new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); | |
8039 | if (!new_crtc_state->active) | |
e7b07cee HW |
8040 | continue; |
8041 | ||
bc7f670e | 8042 | dc_plane = dm_new_plane_state->dc_state; |
da5e1490 AP |
8043 | if (!dc_plane) |
8044 | continue; | |
e7b07cee | 8045 | |
74aa7bd4 | 8046 | bundle->surface_updates[planes_count].surface = dc_plane; |
bc7f670e | 8047 | if (new_pcrtc_state->color_mgmt_changed) { |
74aa7bd4 DF |
8048 | bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; |
8049 | bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; | |
44efb784 | 8050 | bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; |
bc7f670e | 8051 | } |
8a48b44c | 8052 | |
8bf0d9cd | 8053 | amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, |
695af5f9 | 8054 | &bundle->scaling_infos[planes_count]); |
8a48b44c | 8055 | |
695af5f9 NK |
8056 | bundle->surface_updates[planes_count].scaling_info = |
8057 | &bundle->scaling_infos[planes_count]; | |
8a48b44c | 8058 | |
f5031000 | 8059 | plane_needs_flip = old_plane_state->fb && new_plane_state->fb; |
8a48b44c | 8060 | |
f5031000 | 8061 | pflip_present = pflip_present || plane_needs_flip; |
8a48b44c | 8062 | |
f5031000 DF |
8063 | if (!plane_needs_flip) { |
8064 | planes_count += 1; | |
8065 | continue; | |
8066 | } | |
8a48b44c | 8067 | |
695af5f9 | 8068 | fill_dc_plane_info_and_addr( |
8ce5d842 | 8069 | dm->adev, new_plane_state, |
6eed95b0 | 8070 | afb->tiling_flags, |
695af5f9 | 8071 | &bundle->plane_infos[planes_count], |
87b7ebc2 | 8072 | &bundle->flip_addrs[planes_count].address, |
6eed95b0 | 8073 | afb->tmz_surface, false); |
87b7ebc2 | 8074 | |
9f07550b | 8075 | drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", |
87b7ebc2 RS |
8076 | new_plane_state->plane->index, |
8077 | bundle->plane_infos[planes_count].dcc.enable); | |
695af5f9 NK |
8078 | |
8079 | bundle->surface_updates[planes_count].plane_info = | |
8080 | &bundle->plane_infos[planes_count]; | |
8a48b44c | 8081 | |
d6ed6d0d | 8082 | if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) { |
d852871c HM |
8083 | fill_dc_dirty_rects(plane, old_plane_state, |
8084 | new_plane_state, new_crtc_state, | |
d6ed6d0d TC |
8085 | &bundle->flip_addrs[planes_count], |
8086 | &dirty_rects_changed); | |
8087 | ||
8088 | /* | |
8089 | * If the dirty regions changed, PSR-SU need to be disabled temporarily | |
8090 | * and enabled it again after dirty regions are stable to avoid video glitch. | |
8091 | * PSR-SU will be enabled in vblank_control_worker() if user pause the video | |
8092 | * during the PSR-SU was disabled. | |
8093 | */ | |
8094 | if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && | |
8095 | acrtc_attach->dm_irq_params.allow_psr_entry && | |
8096 | #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY | |
8097 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && | |
8098 | #endif | |
8099 | dirty_rects_changed) { | |
8100 | mutex_lock(&dm->dc_lock); | |
8101 | acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = | |
8102 | timestamp_ns; | |
8103 | if (acrtc_state->stream->link->psr_settings.psr_allow_active) | |
8104 | amdgpu_dm_psr_disable(acrtc_state->stream); | |
8105 | mutex_unlock(&dm->dc_lock); | |
8106 | } | |
8107 | } | |
7cc191ee | 8108 | |
caff0e66 NK |
8109 | /* |
8110 | * Only allow immediate flips for fast updates that don't | |
08da1821 HM |
8111 | * change memory domain, FB pitch, DCC state, rotation or |
8112 | * mirroring. | |
c1e18c44 SS |
8113 | * |
8114 | * dm_crtc_helper_atomic_check() only accepts async flips with | |
8115 | * fast updates. | |
caff0e66 | 8116 | */ |
c1e18c44 | 8117 | if (crtc->state->async_flip && |
a7c0cad0 HM |
8118 | (acrtc_state->update_type != UPDATE_TYPE_FAST || |
8119 | get_mem_type(old_plane_state->fb) != get_mem_type(fb))) | |
c1e18c44 SS |
8120 | drm_warn_once(state->dev, |
8121 | "[PLANE:%d:%s] async flip with non-fast update\n", | |
8122 | plane->base.id, plane->name); | |
a7c0cad0 | 8123 | |
f5031000 | 8124 | bundle->flip_addrs[planes_count].flip_immediate = |
4d85f45c | 8125 | crtc->state->async_flip && |
08da1821 HM |
8126 | acrtc_state->update_type == UPDATE_TYPE_FAST && |
8127 | get_mem_type(old_plane_state->fb) == get_mem_type(fb); | |
8a48b44c | 8128 | |
f5031000 DF |
8129 | timestamp_ns = ktime_get_ns(); |
8130 | bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); | |
8131 | bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; | |
8132 | bundle->surface_updates[planes_count].surface = dc_plane; | |
8a48b44c | 8133 | |
f5031000 DF |
8134 | if (!bundle->surface_updates[planes_count].surface) { |
8135 | DRM_ERROR("No surface for CRTC: id=%d\n", | |
8136 | acrtc_attach->crtc_id); | |
8137 | continue; | |
bc7f670e DF |
8138 | } |
8139 | ||
f5031000 DF |
8140 | if (plane == pcrtc->primary) |
8141 | update_freesync_state_on_stream( | |
8142 | dm, | |
8143 | acrtc_state, | |
8144 | acrtc_state->stream, | |
8145 | dc_plane, | |
8146 | bundle->flip_addrs[planes_count].flip_timestamp_in_us); | |
bc7f670e | 8147 | |
9f07550b | 8148 | drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", |
f5031000 DF |
8149 | __func__, |
8150 | bundle->flip_addrs[planes_count].address.grph.addr.high_part, | |
8151 | bundle->flip_addrs[planes_count].address.grph.addr.low_part); | |
bc7f670e DF |
8152 | |
8153 | planes_count += 1; | |
8154 | ||
8a48b44c DF |
8155 | } |
8156 | ||
74aa7bd4 | 8157 | if (pflip_present) { |
634092b1 MK |
8158 | if (!vrr_active) { |
8159 | /* Use old throttling in non-vrr fixed refresh rate mode | |
8160 | * to keep flip scheduling based on target vblank counts | |
8161 | * working in a backwards compatible way, e.g., for | |
8162 | * clients using the GLX_OML_sync_control extension or | |
8163 | * DRI3/Present extension with defined target_msc. | |
8164 | */ | |
e3eff4b5 | 8165 | last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); |
c82eddf8 | 8166 | } else { |
634092b1 MK |
8167 | /* For variable refresh rate mode only: |
8168 | * Get vblank of last completed flip to avoid > 1 vrr | |
8169 | * flips per video frame by use of throttling, but allow | |
8170 | * flip programming anywhere in the possibly large | |
8171 | * variable vrr vblank interval for fine-grained flip | |
8172 | * timing control and more opportunity to avoid stutter | |
8173 | * on late submission of flips. | |
8174 | */ | |
8175 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
5d1c59c4 | 8176 | last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; |
634092b1 MK |
8177 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
8178 | } | |
8179 | ||
fdd1fe57 | 8180 | target_vblank = last_flip_vblank + wait_for_vblank; |
8a48b44c DF |
8181 | |
8182 | /* | |
8183 | * Wait until we're out of the vertical blank period before the one | |
8184 | * targeted by the flip | |
8185 | */ | |
8186 | while ((acrtc_attach->enabled && | |
8187 | (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, | |
8188 | 0, &vpos, &hpos, NULL, | |
8189 | NULL, &pcrtc->hwmode) | |
8190 | & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == | |
8191 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && | |
8192 | (int)(target_vblank - | |
e3eff4b5 | 8193 | amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { |
8a48b44c DF |
8194 | usleep_range(1000, 1100); |
8195 | } | |
8196 | ||
8fe684e9 NK |
8197 | /** |
8198 | * Prepare the flip event for the pageflip interrupt to handle. | |
8199 | * | |
8200 | * This only works in the case where we've already turned on the | |
8201 | * appropriate hardware blocks (eg. HUBP) so in the transition case | |
8202 | * from 0 -> n planes we have to skip a hardware generated event | |
8203 | * and rely on sending it from software. | |
8204 | */ | |
8205 | if (acrtc_attach->base.state->event && | |
10a36226 | 8206 | acrtc_state->active_planes > 0) { |
8a48b44c DF |
8207 | drm_crtc_vblank_get(pcrtc); |
8208 | ||
8209 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
8210 | ||
8211 | WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); | |
8212 | prepare_flip_isr(acrtc_attach); | |
8213 | ||
8214 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
8215 | } | |
8216 | ||
8217 | if (acrtc_state->stream) { | |
8a48b44c | 8218 | if (acrtc_state->freesync_vrr_info_changed) |
74aa7bd4 | 8219 | bundle->stream_update.vrr_infopacket = |
8a48b44c | 8220 | &acrtc_state->stream->vrr_infopacket; |
e7b07cee | 8221 | } |
cc79950b MD |
8222 | } else if (cursor_update && acrtc_state->active_planes > 0 && |
8223 | acrtc_attach->base.state->event) { | |
8224 | drm_crtc_vblank_get(pcrtc); | |
8225 | ||
8226 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
8227 | ||
8228 | acrtc_attach->event = acrtc_attach->base.state->event; | |
8229 | acrtc_attach->base.state->event = NULL; | |
8230 | ||
8231 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
e7b07cee HW |
8232 | } |
8233 | ||
bc92c065 | 8234 | /* Update the planes if changed or disable if we don't have any. */ |
ed9656fb ES |
8235 | if ((planes_count || acrtc_state->active_planes == 0) && |
8236 | acrtc_state->stream) { | |
58aa1c50 NK |
8237 | /* |
8238 | * If PSR or idle optimizations are enabled then flush out | |
8239 | * any pending work before hardware programming. | |
8240 | */ | |
06dd1888 NK |
8241 | if (dm->vblank_control_workqueue) |
8242 | flush_workqueue(dm->vblank_control_workqueue); | |
58aa1c50 | 8243 | |
b6e881c9 | 8244 | bundle->stream_update.stream = acrtc_state->stream; |
bc7f670e | 8245 | if (new_pcrtc_state->mode_changed) { |
74aa7bd4 DF |
8246 | bundle->stream_update.src = acrtc_state->stream->src; |
8247 | bundle->stream_update.dst = acrtc_state->stream->dst; | |
e7b07cee HW |
8248 | } |
8249 | ||
cf020d49 NK |
8250 | if (new_pcrtc_state->color_mgmt_changed) { |
8251 | /* | |
8252 | * TODO: This isn't fully correct since we've actually | |
8253 | * already modified the stream in place. | |
8254 | */ | |
8255 | bundle->stream_update.gamut_remap = | |
8256 | &acrtc_state->stream->gamut_remap_matrix; | |
8257 | bundle->stream_update.output_csc_transform = | |
8258 | &acrtc_state->stream->csc_color_matrix; | |
8259 | bundle->stream_update.out_transfer_func = | |
8260 | acrtc_state->stream->out_transfer_func; | |
8261 | } | |
bc7f670e | 8262 | |
8a48b44c | 8263 | acrtc_state->stream->abm_level = acrtc_state->abm_level; |
bc7f670e | 8264 | if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) |
74aa7bd4 | 8265 | bundle->stream_update.abm_level = &acrtc_state->abm_level; |
44d09c6a | 8266 | |
f3081166 TC |
8267 | mutex_lock(&dm->dc_lock); |
8268 | if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && | |
8269 | acrtc_state->stream->link->psr_settings.psr_allow_active) | |
8270 | amdgpu_dm_psr_disable(acrtc_state->stream); | |
8271 | mutex_unlock(&dm->dc_lock); | |
8272 | ||
e63e2491 EB |
8273 | /* |
8274 | * If FreeSync state on the stream has changed then we need to | |
8275 | * re-adjust the min/max bounds now that DC doesn't handle this | |
8276 | * as part of commit. | |
8277 | */ | |
a85ba005 | 8278 | if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { |
e63e2491 EB |
8279 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); |
8280 | dc_stream_adjust_vmin_vmax( | |
8281 | dm->dc, acrtc_state->stream, | |
585d450c | 8282 | &acrtc_attach->dm_irq_params.vrr_params.adjust); |
e63e2491 EB |
8283 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
8284 | } | |
bc7f670e | 8285 | mutex_lock(&dm->dc_lock); |
81f743a0 RS |
8286 | update_planes_and_stream_adapter(dm->dc, |
8287 | acrtc_state->update_type, | |
8288 | planes_count, | |
8289 | acrtc_state->stream, | |
8290 | &bundle->stream_update, | |
8291 | bundle->surface_updates); | |
8c322309 | 8292 | |
8fe684e9 NK |
8293 | /** |
8294 | * Enable or disable the interrupts on the backend. | |
8295 | * | |
8296 | * Most pipes are put into power gating when unused. | |
8297 | * | |
8298 | * When power gating is enabled on a pipe we lose the | |
8299 | * interrupt enablement state when power gating is disabled. | |
8300 | * | |
8301 | * So we need to update the IRQ control state in hardware | |
8302 | * whenever the pipe turns on (since it could be previously | |
8303 | * power gated) or off (since some pipes can't be power gated | |
8304 | * on some ASICs). | |
8305 | */ | |
8306 | if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) | |
1348969a LT |
8307 | dm_update_pflip_irq_state(drm_to_adev(dev), |
8308 | acrtc_attach); | |
8fe684e9 | 8309 | |
8c322309 | 8310 | if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && |
1cfbbdde | 8311 | acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && |
d1ebfdd8 | 8312 | !acrtc_state->stream->link->psr_settings.psr_feature_enabled) |
8c322309 | 8313 | amdgpu_dm_link_setup_psr(acrtc_state->stream); |
58aa1c50 NK |
8314 | |
8315 | /* Decrement skip count when PSR is enabled and we're doing fast updates. */ | |
8316 | if (acrtc_state->update_type == UPDATE_TYPE_FAST && | |
8317 | acrtc_state->stream->link->psr_settings.psr_feature_enabled) { | |
8318 | struct amdgpu_dm_connector *aconn = | |
8319 | (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; | |
1a365683 RL |
8320 | |
8321 | if (aconn->psr_skip_count > 0) | |
8322 | aconn->psr_skip_count--; | |
58aa1c50 NK |
8323 | |
8324 | /* Allow PSR when skip count is 0. */ | |
8325 | acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; | |
7cc191ee LL |
8326 | |
8327 | /* | |
8328 | * If sink supports PSR SU, there is no need to rely on | |
8329 | * a vblank event disable request to enable PSR. PSR SU | |
8330 | * can be enabled immediately once OS demonstrates an | |
8331 | * adequate number of fast atomic commits to notify KMD | |
8332 | * of update events. See `vblank_control_worker()`. | |
8333 | */ | |
8334 | if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && | |
8335 | acrtc_attach->dm_irq_params.allow_psr_entry && | |
c0459bdd AL |
8336 | #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY |
8337 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && | |
8338 | #endif | |
d6ed6d0d TC |
8339 | !acrtc_state->stream->link->psr_settings.psr_allow_active && |
8340 | (timestamp_ns - | |
8341 | acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > | |
8342 | 500000000) | |
7cc191ee | 8343 | amdgpu_dm_psr_enable(acrtc_state->stream); |
58aa1c50 NK |
8344 | } else { |
8345 | acrtc_attach->dm_irq_params.allow_psr_entry = false; | |
8c322309 RL |
8346 | } |
8347 | ||
bc7f670e | 8348 | mutex_unlock(&dm->dc_lock); |
e7b07cee | 8349 | } |
4b510503 | 8350 | |
8ad27806 NK |
8351 | /* |
8352 | * Update cursor state *after* programming all the planes. | |
8353 | * This avoids redundant programming in the case where we're going | |
8354 | * to be disabling a single plane - those pipes are being disabled. | |
8355 | */ | |
8356 | if (acrtc_state->active_planes) | |
8357 | amdgpu_dm_commit_cursors(state); | |
80c218d5 | 8358 | |
4b510503 | 8359 | cleanup: |
74aa7bd4 | 8360 | kfree(bundle); |
e7b07cee HW |
8361 | } |
8362 | ||
6ce8f316 NK |
8363 | static void amdgpu_dm_commit_audio(struct drm_device *dev, |
8364 | struct drm_atomic_state *state) | |
8365 | { | |
1348969a | 8366 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
8367 | struct amdgpu_dm_connector *aconnector; |
8368 | struct drm_connector *connector; | |
8369 | struct drm_connector_state *old_con_state, *new_con_state; | |
8370 | struct drm_crtc_state *new_crtc_state; | |
8371 | struct dm_crtc_state *new_dm_crtc_state; | |
8372 | const struct dc_stream_status *status; | |
8373 | int i, inst; | |
8374 | ||
8375 | /* Notify device removals. */ | |
8376 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
8377 | if (old_con_state->crtc != new_con_state->crtc) { | |
8378 | /* CRTC changes require notification. */ | |
8379 | goto notify; | |
8380 | } | |
8381 | ||
8382 | if (!new_con_state->crtc) | |
8383 | continue; | |
8384 | ||
8385 | new_crtc_state = drm_atomic_get_new_crtc_state( | |
8386 | state, new_con_state->crtc); | |
8387 | ||
8388 | if (!new_crtc_state) | |
8389 | continue; | |
8390 | ||
8391 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
8392 | continue; | |
8393 | ||
3335a135 | 8394 | notify: |
6ce8f316 NK |
8395 | aconnector = to_amdgpu_dm_connector(connector); |
8396 | ||
8397 | mutex_lock(&adev->dm.audio_lock); | |
8398 | inst = aconnector->audio_inst; | |
8399 | aconnector->audio_inst = -1; | |
8400 | mutex_unlock(&adev->dm.audio_lock); | |
8401 | ||
8402 | amdgpu_dm_audio_eld_notify(adev, inst); | |
8403 | } | |
8404 | ||
8405 | /* Notify audio device additions. */ | |
8406 | for_each_new_connector_in_state(state, connector, new_con_state, i) { | |
8407 | if (!new_con_state->crtc) | |
8408 | continue; | |
8409 | ||
8410 | new_crtc_state = drm_atomic_get_new_crtc_state( | |
8411 | state, new_con_state->crtc); | |
8412 | ||
8413 | if (!new_crtc_state) | |
8414 | continue; | |
8415 | ||
8416 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
8417 | continue; | |
8418 | ||
8419 | new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); | |
8420 | if (!new_dm_crtc_state->stream) | |
8421 | continue; | |
8422 | ||
8423 | status = dc_stream_get_status(new_dm_crtc_state->stream); | |
8424 | if (!status) | |
8425 | continue; | |
8426 | ||
8427 | aconnector = to_amdgpu_dm_connector(connector); | |
8428 | ||
8429 | mutex_lock(&adev->dm.audio_lock); | |
8430 | inst = status->audio_inst; | |
8431 | aconnector->audio_inst = inst; | |
8432 | mutex_unlock(&adev->dm.audio_lock); | |
8433 | ||
8434 | amdgpu_dm_audio_eld_notify(adev, inst); | |
8435 | } | |
8436 | } | |
8437 | ||
1f6010a9 | 8438 | /* |
27b3f4fc LSL |
8439 | * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC |
8440 | * @crtc_state: the DRM CRTC state | |
8441 | * @stream_state: the DC stream state. | |
8442 | * | |
8443 | * Copy the mirrored transient state flags from DRM, to DC. It is used to bring | |
8444 | * a dc_stream_state's flags in sync with a drm_crtc_state's flags. | |
8445 | */ | |
8446 | static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, | |
8447 | struct dc_stream_state *stream_state) | |
8448 | { | |
b9952f93 | 8449 | stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); |
27b3f4fc | 8450 | } |
e7b07cee | 8451 | |
fff7b95a AL |
8452 | static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, |
8453 | struct dc_state *dc_state) | |
e7b07cee HW |
8454 | { |
8455 | struct drm_device *dev = state->dev; | |
1348969a | 8456 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee | 8457 | struct amdgpu_display_manager *dm = &adev->dm; |
5cc6dcbd | 8458 | struct drm_crtc *crtc; |
0bc9706d | 8459 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
54d76575 | 8460 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
6ee90e88 | 8461 | bool mode_set_reset_required = false; |
fff7b95a | 8462 | u32 i; |
e7b07cee | 8463 | |
c82eddf8 SS |
8464 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, |
8465 | new_crtc_state, i) { | |
6d90a208 AP |
8466 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
8467 | ||
8468 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
8469 | ||
8470 | if (old_crtc_state->active && | |
8471 | (!new_crtc_state->active || | |
8472 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
8473 | manage_dm_interrupts(adev, acrtc, false); | |
8474 | dc_stream_release(dm_old_crtc_state->stream); | |
8475 | } | |
8476 | } | |
8477 | ||
8976f73b RS |
8478 | drm_atomic_helper_calc_timestamping_constants(state); |
8479 | ||
e7b07cee | 8480 | /* update changed items */ |
0bc9706d | 8481 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
e7b07cee | 8482 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 8483 | |
54d76575 LSL |
8484 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
8485 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
e7b07cee | 8486 | |
9f07550b | 8487 | drm_dbg_state(state->dev, |
c82eddf8 | 8488 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", |
e7b07cee | 8489 | acrtc->crtc_id, |
0bc9706d LSL |
8490 | new_crtc_state->enable, |
8491 | new_crtc_state->active, | |
8492 | new_crtc_state->planes_changed, | |
8493 | new_crtc_state->mode_changed, | |
8494 | new_crtc_state->active_changed, | |
8495 | new_crtc_state->connectors_changed); | |
e7b07cee | 8496 | |
5c68c652 VL |
8497 | /* Disable cursor if disabling crtc */ |
8498 | if (old_crtc_state->active && !new_crtc_state->active) { | |
8499 | struct dc_cursor_position position; | |
8500 | ||
8501 | memset(&position, 0, sizeof(position)); | |
8502 | mutex_lock(&dm->dc_lock); | |
8503 | dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); | |
8504 | mutex_unlock(&dm->dc_lock); | |
8505 | } | |
8506 | ||
27b3f4fc LSL |
8507 | /* Copy all transient state flags into dc state */ |
8508 | if (dm_new_crtc_state->stream) { | |
8509 | amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, | |
8510 | dm_new_crtc_state->stream); | |
8511 | } | |
8512 | ||
e7b07cee HW |
8513 | /* handles headless hotplug case, updating new_state and |
8514 | * aconnector as needed | |
8515 | */ | |
8516 | ||
6c5e25a0 | 8517 | if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { |
e7b07cee | 8518 | |
4711c033 | 8519 | DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee | 8520 | |
54d76575 | 8521 | if (!dm_new_crtc_state->stream) { |
e7b07cee | 8522 | /* |
b830ebc9 HW |
8523 | * this could happen because of issues with |
8524 | * userspace notifications delivery. | |
8525 | * In this case userspace tries to set mode on | |
1f6010a9 DF |
8526 | * display which is disconnected in fact. |
8527 | * dc_sink is NULL in this case on aconnector. | |
b830ebc9 HW |
8528 | * We expect reset mode will come soon. |
8529 | * | |
8530 | * This can also happen when unplug is done | |
8531 | * during resume sequence ended | |
8532 | * | |
8533 | * In this case, we want to pretend we still | |
8534 | * have a sink to keep the pipe running so that | |
8535 | * hw state is consistent with the sw state | |
8536 | */ | |
f1ad2f5e | 8537 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", |
e7b07cee HW |
8538 | __func__, acrtc->base.base.id); |
8539 | continue; | |
8540 | } | |
8541 | ||
54d76575 LSL |
8542 | if (dm_old_crtc_state->stream) |
8543 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); | |
e7b07cee | 8544 | |
97028037 LP |
8545 | pm_runtime_get_noresume(dev->dev); |
8546 | ||
e7b07cee | 8547 | acrtc->enabled = true; |
0bc9706d LSL |
8548 | acrtc->hw_mode = new_crtc_state->mode; |
8549 | crtc->hwmode = new_crtc_state->mode; | |
6ee90e88 | 8550 | mode_set_reset_required = true; |
0bc9706d | 8551 | } else if (modereset_required(new_crtc_state)) { |
4711c033 | 8552 | DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee | 8553 | /* i.e. reset mode */ |
6ee90e88 | 8554 | if (dm_old_crtc_state->stream) |
54d76575 | 8555 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); |
a85ba005 | 8556 | |
6ee90e88 | 8557 | mode_set_reset_required = true; |
e7b07cee HW |
8558 | } |
8559 | } /* for_each_crtc_in_state() */ | |
8560 | ||
fff7b95a AL |
8561 | /* if there mode set or reset, disable eDP PSR */ |
8562 | if (mode_set_reset_required) { | |
8563 | if (dm->vblank_control_workqueue) | |
8564 | flush_workqueue(dm->vblank_control_workqueue); | |
cae5c1ab | 8565 | |
fff7b95a AL |
8566 | amdgpu_dm_psr_disable_all(dm); |
8567 | } | |
6ee90e88 | 8568 | |
fff7b95a AL |
8569 | dm_enable_per_frame_crtc_master_sync(dc_state); |
8570 | mutex_lock(&dm->dc_lock); | |
8571 | WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); | |
f3106c94 | 8572 | |
fff7b95a AL |
8573 | /* Allow idle optimization when vblank count is 0 for display off */ |
8574 | if (dm->active_vblank_irq_count == 0) | |
8575 | dc_allow_idle_optimizations(dm->dc, true); | |
8576 | mutex_unlock(&dm->dc_lock); | |
fe8858bb | 8577 | |
0bc9706d | 8578 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 8579 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 8580 | |
54d76575 | 8581 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 8582 | |
54d76575 | 8583 | if (dm_new_crtc_state->stream != NULL) { |
e7b07cee | 8584 | const struct dc_stream_status *status = |
54d76575 | 8585 | dc_stream_get_status(dm_new_crtc_state->stream); |
e7b07cee | 8586 | |
eb3dc897 | 8587 | if (!status) |
09f609c3 LL |
8588 | status = dc_stream_get_status_from_state(dc_state, |
8589 | dm_new_crtc_state->stream); | |
e7b07cee | 8590 | if (!status) |
54d76575 | 8591 | DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); |
e7b07cee HW |
8592 | else |
8593 | acrtc->otg_inst = status->primary_otg_inst; | |
8594 | } | |
8595 | } | |
fff7b95a AL |
8596 | } |
8597 | ||
8598 | /** | |
8599 | * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. | |
8600 | * @state: The atomic state to commit | |
8601 | * | |
8602 | * This will tell DC to commit the constructed DC state from atomic_check, | |
8603 | * programming the hardware. Any failures here implies a hardware failure, since | |
8604 | * atomic check should have filtered anything non-kosher. | |
8605 | */ | |
8606 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) | |
8607 | { | |
8608 | struct drm_device *dev = state->dev; | |
8609 | struct amdgpu_device *adev = drm_to_adev(dev); | |
8610 | struct amdgpu_display_manager *dm = &adev->dm; | |
8611 | struct dm_atomic_state *dm_state; | |
8612 | struct dc_state *dc_state = NULL; | |
8613 | u32 i, j; | |
8614 | struct drm_crtc *crtc; | |
8615 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; | |
8616 | unsigned long flags; | |
8617 | bool wait_for_vblank = true; | |
8618 | struct drm_connector *connector; | |
8619 | struct drm_connector_state *old_con_state, *new_con_state; | |
8620 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; | |
8621 | int crtc_disable_count = 0; | |
8622 | ||
8623 | trace_amdgpu_dm_atomic_commit_tail_begin(state); | |
8624 | ||
8625 | drm_atomic_helper_update_legacy_modeset_state(dev, state); | |
8626 | drm_dp_mst_atomic_wait_for_dependencies(state); | |
8627 | ||
8628 | dm_state = dm_atomic_get_new_state(state); | |
8629 | if (dm_state && dm_state->context) { | |
8630 | dc_state = dm_state->context; | |
8631 | amdgpu_dm_commit_streams(state, dc_state); | |
8632 | } | |
8633 | ||
0c8620d6 BL |
8634 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
8635 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
8636 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
8637 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
8638 | ||
3cf7cd3f HW |
8639 | if (!adev->dm.hdcp_workqueue) |
8640 | continue; | |
8641 | ||
e8fd3eeb | 8642 | pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); |
8643 | ||
8644 | if (!connector) | |
8645 | continue; | |
8646 | ||
8647 | pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", | |
8648 | connector->index, connector->status, connector->dpms); | |
8649 | pr_debug("[HDCP_DM] state protection old: %x new: %x\n", | |
8650 | old_con_state->content_protection, new_con_state->content_protection); | |
8651 | ||
8652 | if (aconnector->dc_sink) { | |
8653 | if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && | |
8654 | aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { | |
8655 | pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", | |
8656 | aconnector->dc_sink->edid_caps.display_name); | |
8657 | } | |
8658 | } | |
8659 | ||
0c8620d6 | 8660 | new_crtc_state = NULL; |
e8fd3eeb | 8661 | old_crtc_state = NULL; |
0c8620d6 | 8662 | |
e8fd3eeb | 8663 | if (acrtc) { |
0c8620d6 | 8664 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
e8fd3eeb | 8665 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
8666 | } | |
8667 | ||
8668 | if (old_crtc_state) | |
8669 | pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
8670 | old_crtc_state->enable, | |
8671 | old_crtc_state->active, | |
8672 | old_crtc_state->mode_changed, | |
8673 | old_crtc_state->active_changed, | |
8674 | old_crtc_state->connectors_changed); | |
8675 | ||
8676 | if (new_crtc_state) | |
8677 | pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
8678 | new_crtc_state->enable, | |
8679 | new_crtc_state->active, | |
8680 | new_crtc_state->mode_changed, | |
8681 | new_crtc_state->active_changed, | |
8682 | new_crtc_state->connectors_changed); | |
8683 | } | |
8684 | ||
8685 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
8686 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
8687 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
8688 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
8689 | ||
3cf7cd3f HW |
8690 | if (!adev->dm.hdcp_workqueue) |
8691 | continue; | |
8692 | ||
e8fd3eeb | 8693 | new_crtc_state = NULL; |
8694 | old_crtc_state = NULL; | |
8695 | ||
8696 | if (acrtc) { | |
8697 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); | |
8698 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); | |
8699 | } | |
0c8620d6 BL |
8700 | |
8701 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
8702 | ||
8703 | if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && | |
8704 | connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { | |
8705 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); | |
8706 | new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
97f6c917 | 8707 | dm_new_con_state->update_hdcp = true; |
0c8620d6 BL |
8708 | continue; |
8709 | } | |
8710 | ||
e8fd3eeb | 8711 | if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, |
8712 | old_con_state, connector, adev->dm.hdcp_workqueue)) { | |
82986fd6 | 8713 | /* when display is unplugged from mst hub, connctor will |
8714 | * be destroyed within dm_dp_mst_connector_destroy. connector | |
8715 | * hdcp perperties, like type, undesired, desired, enabled, | |
8716 | * will be lost. So, save hdcp properties into hdcp_work within | |
8717 | * amdgpu_dm_atomic_commit_tail. if the same display is | |
8718 | * plugged back with same display index, its hdcp properties | |
8719 | * will be retrieved from hdcp_work within dm_dp_mst_get_modes | |
8720 | */ | |
8721 | ||
e8fd3eeb | 8722 | bool enable_encryption = false; |
8723 | ||
8724 | if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) | |
8725 | enable_encryption = true; | |
8726 | ||
82986fd6 | 8727 | if (aconnector->dc_link && aconnector->dc_sink && |
8728 | aconnector->dc_link->type == dc_connection_mst_branch) { | |
8729 | struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; | |
8730 | struct hdcp_workqueue *hdcp_w = | |
8731 | &hdcp_work[aconnector->dc_link->link_index]; | |
8732 | ||
8733 | hdcp_w->hdcp_content_type[connector->index] = | |
8734 | new_con_state->hdcp_content_type; | |
8735 | hdcp_w->content_protection[connector->index] = | |
8736 | new_con_state->content_protection; | |
8737 | } | |
8738 | ||
e8fd3eeb | 8739 | if (new_crtc_state && new_crtc_state->mode_changed && |
8740 | new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) | |
8741 | enable_encryption = true; | |
8742 | ||
8743 | DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); | |
8744 | ||
b1abe558 BL |
8745 | hdcp_update_display( |
8746 | adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, | |
e8fd3eeb | 8747 | new_con_state->hdcp_content_type, enable_encryption); |
8748 | } | |
0c8620d6 | 8749 | } |
e7b07cee | 8750 | |
02d6a6fc | 8751 | /* Handle connector state changes */ |
c2cea706 | 8752 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
8753 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
8754 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); | |
8755 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
135fd1b3 | 8756 | struct dc_surface_update *dummy_updates; |
19afd799 | 8757 | struct dc_stream_update stream_update; |
b232d4ed | 8758 | struct dc_info_packet hdr_packet; |
e7b07cee | 8759 | struct dc_stream_status *status = NULL; |
b232d4ed | 8760 | bool abm_changed, hdr_changed, scaling_changed; |
e7b07cee | 8761 | |
19afd799 NC |
8762 | memset(&stream_update, 0, sizeof(stream_update)); |
8763 | ||
44d09c6a | 8764 | if (acrtc) { |
0bc9706d | 8765 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
44d09c6a HW |
8766 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
8767 | } | |
0bc9706d | 8768 | |
e7b07cee | 8769 | /* Skip any modesets/resets */ |
0bc9706d | 8770 | if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) |
e7b07cee HW |
8771 | continue; |
8772 | ||
54d76575 | 8773 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
c1ee92f9 DF |
8774 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
8775 | ||
b232d4ed NK |
8776 | scaling_changed = is_scaling_state_different(dm_new_con_state, |
8777 | dm_old_con_state); | |
8778 | ||
8779 | abm_changed = dm_new_crtc_state->abm_level != | |
8780 | dm_old_crtc_state->abm_level; | |
8781 | ||
8782 | hdr_changed = | |
72921cdf | 8783 | !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); |
b232d4ed NK |
8784 | |
8785 | if (!scaling_changed && !abm_changed && !hdr_changed) | |
c1ee92f9 | 8786 | continue; |
e7b07cee | 8787 | |
b6e881c9 | 8788 | stream_update.stream = dm_new_crtc_state->stream; |
b232d4ed | 8789 | if (scaling_changed) { |
02d6a6fc | 8790 | update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, |
b6e881c9 | 8791 | dm_new_con_state, dm_new_crtc_state->stream); |
e7b07cee | 8792 | |
02d6a6fc DF |
8793 | stream_update.src = dm_new_crtc_state->stream->src; |
8794 | stream_update.dst = dm_new_crtc_state->stream->dst; | |
8795 | } | |
8796 | ||
b232d4ed | 8797 | if (abm_changed) { |
02d6a6fc DF |
8798 | dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; |
8799 | ||
8800 | stream_update.abm_level = &dm_new_crtc_state->abm_level; | |
8801 | } | |
70e8ffc5 | 8802 | |
b232d4ed NK |
8803 | if (hdr_changed) { |
8804 | fill_hdr_info_packet(new_con_state, &hdr_packet); | |
8805 | stream_update.hdr_static_metadata = &hdr_packet; | |
8806 | } | |
8807 | ||
54d76575 | 8808 | status = dc_stream_get_status(dm_new_crtc_state->stream); |
57738ae4 ND |
8809 | |
8810 | if (WARN_ON(!status)) | |
8811 | continue; | |
8812 | ||
3be5262e | 8813 | WARN_ON(!status->plane_count); |
e7b07cee | 8814 | |
02d6a6fc DF |
8815 | /* |
8816 | * TODO: DC refuses to perform stream updates without a dc_surface_update. | |
8817 | * Here we create an empty update on each plane. | |
8818 | * To fix this, DC should permit updating only stream properties. | |
8819 | */ | |
135fd1b3 | 8820 | dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); |
02d6a6fc | 8821 | for (j = 0; j < status->plane_count; j++) |
efc8278e | 8822 | dummy_updates[j].surface = status->plane_states[0]; |
02d6a6fc DF |
8823 | |
8824 | ||
8825 | mutex_lock(&dm->dc_lock); | |
f7511289 RS |
8826 | dc_update_planes_and_stream(dm->dc, |
8827 | dummy_updates, | |
8828 | status->plane_count, | |
8829 | dm_new_crtc_state->stream, | |
8830 | &stream_update); | |
02d6a6fc | 8831 | mutex_unlock(&dm->dc_lock); |
135fd1b3 | 8832 | kfree(dummy_updates); |
e7b07cee HW |
8833 | } |
8834 | ||
8fe684e9 NK |
8835 | /** |
8836 | * Enable interrupts for CRTCs that are newly enabled or went through | |
8837 | * a modeset. It was intentionally deferred until after the front end | |
8838 | * state was modified to wait until the OTG was on and so the IRQ | |
8839 | * handlers didn't access stale or invalid state. | |
8840 | */ | |
8841 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { | |
8842 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); | |
8e7b6fee WL |
8843 | #ifdef CONFIG_DEBUG_FS |
8844 | enum amdgpu_dm_pipe_crc_source cur_crc_src; | |
8799c0be YL |
8845 | #endif |
8846 | /* Count number of newly disabled CRTCs for dropping PM refs later. */ | |
8847 | if (old_crtc_state->active && !new_crtc_state->active) | |
8848 | crtc_disable_count++; | |
8849 | ||
8850 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
8851 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
8852 | ||
8853 | /* For freesync config update on crtc state and params for irq */ | |
8854 | update_stream_irq_parameters(dm, dm_new_crtc_state); | |
8855 | ||
8856 | #ifdef CONFIG_DEBUG_FS | |
d98af272 WL |
8857 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
8858 | cur_crc_src = acrtc->dm_irq_params.crc_src; | |
8859 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); | |
8e7b6fee | 8860 | #endif |
585d450c | 8861 | |
8fe684e9 NK |
8862 | if (new_crtc_state->active && |
8863 | (!old_crtc_state->active || | |
8864 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
585d450c AP |
8865 | dc_stream_retain(dm_new_crtc_state->stream); |
8866 | acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; | |
8fe684e9 | 8867 | manage_dm_interrupts(adev, acrtc, true); |
8799c0be YL |
8868 | } |
8869 | /* Handle vrr on->off / off->on transitions */ | |
8870 | amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); | |
e2881d6d | 8871 | |
24eb9374 | 8872 | #ifdef CONFIG_DEBUG_FS |
8799c0be YL |
8873 | if (new_crtc_state->active && |
8874 | (!old_crtc_state->active || | |
8875 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
8fe684e9 NK |
8876 | /** |
8877 | * Frontend may have changed so reapply the CRC capture | |
8878 | * settings for the stream. | |
8879 | */ | |
8e7b6fee | 8880 | if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { |
86bc2219 | 8881 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
d98af272 WL |
8882 | if (amdgpu_dm_crc_window_is_activated(crtc)) { |
8883 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); | |
c0459bdd | 8884 | acrtc->dm_irq_params.window_param.update_win = true; |
1b11ff76 AL |
8885 | |
8886 | /** | |
8887 | * It takes 2 frames for HW to stably generate CRC when | |
8888 | * resuming from suspend, so we set skip_frame_cnt 2. | |
8889 | */ | |
c0459bdd | 8890 | acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; |
d98af272 WL |
8891 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
8892 | } | |
86bc2219 | 8893 | #endif |
bbc49fc0 WL |
8894 | if (amdgpu_dm_crtc_configure_crc_source( |
8895 | crtc, dm_new_crtc_state, cur_crc_src)) | |
8896 | DRM_DEBUG_DRIVER("Failed to configure crc source"); | |
8799c0be | 8897 | } |
8fe684e9 | 8898 | } |
2130b87b | 8899 | #endif |
8fe684e9 | 8900 | } |
e7b07cee | 8901 | |
420cd472 | 8902 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) |
4d85f45c | 8903 | if (new_crtc_state->async_flip) |
420cd472 DF |
8904 | wait_for_vblank = false; |
8905 | ||
e7b07cee | 8906 | /* update planes when needed per crtc*/ |
5cc6dcbd | 8907 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { |
54d76575 | 8908 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 8909 | |
54d76575 | 8910 | if (dm_new_crtc_state->stream) |
fff7b95a | 8911 | amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); |
e7b07cee HW |
8912 | } |
8913 | ||
6ce8f316 NK |
8914 | /* Update audio instances for each connector. */ |
8915 | amdgpu_dm_commit_audio(dev, state); | |
8916 | ||
7230362c | 8917 | /* restore the backlight level */ |
7fd13bae AD |
8918 | for (i = 0; i < dm->num_of_edps; i++) { |
8919 | if (dm->backlight_dev[i] && | |
4052287a | 8920 | (dm->actual_brightness[i] != dm->brightness[i])) |
7fd13bae AD |
8921 | amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); |
8922 | } | |
83a3439d | 8923 | |
e7b07cee HW |
8924 | /* |
8925 | * send vblank event on all events not handled in flip and | |
8926 | * mark consumed event for drm_atomic_helper_commit_hw_done | |
8927 | */ | |
4a580877 | 8928 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
0bc9706d | 8929 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 8930 | |
0bc9706d LSL |
8931 | if (new_crtc_state->event) |
8932 | drm_send_event_locked(dev, &new_crtc_state->event->base); | |
e7b07cee | 8933 | |
0bc9706d | 8934 | new_crtc_state->event = NULL; |
e7b07cee | 8935 | } |
4a580877 | 8936 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
e7b07cee | 8937 | |
29c8f234 LL |
8938 | /* Signal HW programming completion */ |
8939 | drm_atomic_helper_commit_hw_done(state); | |
e7b07cee HW |
8940 | |
8941 | if (wait_for_vblank) | |
320a1274 | 8942 | drm_atomic_helper_wait_for_flip_done(dev, state); |
e7b07cee HW |
8943 | |
8944 | drm_atomic_helper_cleanup_planes(dev, state); | |
97028037 | 8945 | |
e6b27cf5 AD |
8946 | /* Don't free the memory if we are hitting this as part of suspend. |
8947 | * This way we don't free any memory during suspend; see | |
8948 | * amdgpu_bo_free_kernel(). The memory will be freed in the first | |
8949 | * non-suspend modeset or when the driver is torn down. | |
8950 | */ | |
8951 | if (!adev->in_suspend) { | |
8952 | /* return the stolen vga memory back to VRAM */ | |
8953 | if (!adev->mman.keep_stolen_vga_memory) | |
8954 | amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); | |
8955 | amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); | |
8956 | } | |
5f6fab24 | 8957 | |
1f6010a9 DF |
8958 | /* |
8959 | * Finally, drop a runtime PM reference for each newly disabled CRTC, | |
97028037 LP |
8960 | * so we can put the GPU into runtime suspend if we're not driving any |
8961 | * displays anymore | |
8962 | */ | |
fe2a1965 LP |
8963 | for (i = 0; i < crtc_disable_count; i++) |
8964 | pm_runtime_put_autosuspend(dev->dev); | |
97028037 | 8965 | pm_runtime_mark_last_busy(dev->dev); |
e7b07cee HW |
8966 | } |
8967 | ||
e7b07cee HW |
8968 | static int dm_force_atomic_commit(struct drm_connector *connector) |
8969 | { | |
8970 | int ret = 0; | |
8971 | struct drm_device *ddev = connector->dev; | |
8972 | struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); | |
8973 | struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
8974 | struct drm_plane *plane = disconnected_acrtc->base.primary; | |
8975 | struct drm_connector_state *conn_state; | |
8976 | struct drm_crtc_state *crtc_state; | |
8977 | struct drm_plane_state *plane_state; | |
8978 | ||
8979 | if (!state) | |
8980 | return -ENOMEM; | |
8981 | ||
8982 | state->acquire_ctx = ddev->mode_config.acquire_ctx; | |
8983 | ||
8984 | /* Construct an atomic state to restore previous display setting */ | |
8985 | ||
8986 | /* | |
8987 | * Attach connectors to drm_atomic_state | |
8988 | */ | |
8989 | conn_state = drm_atomic_get_connector_state(state, connector); | |
8990 | ||
8991 | ret = PTR_ERR_OR_ZERO(conn_state); | |
8992 | if (ret) | |
2dc39051 | 8993 | goto out; |
e7b07cee HW |
8994 | |
8995 | /* Attach crtc to drm_atomic_state*/ | |
8996 | crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); | |
8997 | ||
8998 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
8999 | if (ret) | |
2dc39051 | 9000 | goto out; |
e7b07cee HW |
9001 | |
9002 | /* force a restore */ | |
9003 | crtc_state->mode_changed = true; | |
9004 | ||
9005 | /* Attach plane to drm_atomic_state */ | |
9006 | plane_state = drm_atomic_get_plane_state(state, plane); | |
9007 | ||
9008 | ret = PTR_ERR_OR_ZERO(plane_state); | |
9009 | if (ret) | |
2dc39051 | 9010 | goto out; |
e7b07cee HW |
9011 | |
9012 | /* Call commit internally with the state we just constructed */ | |
9013 | ret = drm_atomic_commit(state); | |
e7b07cee | 9014 | |
2dc39051 | 9015 | out: |
e7b07cee | 9016 | drm_atomic_state_put(state); |
2dc39051 VL |
9017 | if (ret) |
9018 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
e7b07cee HW |
9019 | |
9020 | return ret; | |
9021 | } | |
9022 | ||
9023 | /* | |
1f6010a9 DF |
9024 | * This function handles all cases when set mode does not come upon hotplug. |
9025 | * This includes when a display is unplugged then plugged back into the | |
9026 | * same port and when running without usermode desktop manager supprot | |
e7b07cee | 9027 | */ |
3ee6b26b AD |
9028 | void dm_restore_drm_connector_state(struct drm_device *dev, |
9029 | struct drm_connector *connector) | |
e7b07cee | 9030 | { |
c84dec2f | 9031 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
9032 | struct amdgpu_crtc *disconnected_acrtc; |
9033 | struct dm_crtc_state *acrtc_state; | |
9034 | ||
9035 | if (!aconnector->dc_sink || !connector->state || !connector->encoder) | |
9036 | return; | |
9037 | ||
9038 | disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
70e8ffc5 HW |
9039 | if (!disconnected_acrtc) |
9040 | return; | |
e7b07cee | 9041 | |
70e8ffc5 HW |
9042 | acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); |
9043 | if (!acrtc_state->stream) | |
e7b07cee HW |
9044 | return; |
9045 | ||
9046 | /* | |
9047 | * If the previous sink is not released and different from the current, | |
9048 | * we deduce we are in a state where we can not rely on usermode call | |
9049 | * to turn on the display, so we do it here | |
9050 | */ | |
9051 | if (acrtc_state->stream->sink != aconnector->dc_sink) | |
9052 | dm_force_atomic_commit(&aconnector->base); | |
9053 | } | |
9054 | ||
1f6010a9 | 9055 | /* |
e7b07cee HW |
9056 | * Grabs all modesetting locks to serialize against any blocking commits, |
9057 | * Waits for completion of all non blocking commits. | |
9058 | */ | |
3ee6b26b AD |
9059 | static int do_aquire_global_lock(struct drm_device *dev, |
9060 | struct drm_atomic_state *state) | |
e7b07cee HW |
9061 | { |
9062 | struct drm_crtc *crtc; | |
9063 | struct drm_crtc_commit *commit; | |
9064 | long ret; | |
9065 | ||
1f6010a9 DF |
9066 | /* |
9067 | * Adding all modeset locks to aquire_ctx will | |
e7b07cee HW |
9068 | * ensure that when the framework release it the |
9069 | * extra locks we are locking here will get released to | |
9070 | */ | |
9071 | ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); | |
9072 | if (ret) | |
9073 | return ret; | |
9074 | ||
9075 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9076 | spin_lock(&crtc->commit_lock); | |
9077 | commit = list_first_entry_or_null(&crtc->commit_list, | |
9078 | struct drm_crtc_commit, commit_entry); | |
9079 | if (commit) | |
9080 | drm_crtc_commit_get(commit); | |
9081 | spin_unlock(&crtc->commit_lock); | |
9082 | ||
9083 | if (!commit) | |
9084 | continue; | |
9085 | ||
1f6010a9 DF |
9086 | /* |
9087 | * Make sure all pending HW programming completed and | |
e7b07cee HW |
9088 | * page flips done |
9089 | */ | |
9090 | ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); | |
9091 | ||
9092 | if (ret > 0) | |
9093 | ret = wait_for_completion_interruptible_timeout( | |
9094 | &commit->flip_done, 10*HZ); | |
9095 | ||
9096 | if (ret == 0) | |
c82eddf8 SS |
9097 | DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", |
9098 | crtc->base.id, crtc->name); | |
e7b07cee HW |
9099 | |
9100 | drm_crtc_commit_put(commit); | |
9101 | } | |
9102 | ||
9103 | return ret < 0 ? ret : 0; | |
9104 | } | |
9105 | ||
bb47de73 NK |
9106 | static void get_freesync_config_for_crtc( |
9107 | struct dm_crtc_state *new_crtc_state, | |
9108 | struct dm_connector_state *new_con_state) | |
98e6436d AK |
9109 | { |
9110 | struct mod_freesync_config config = {0}; | |
98e6436d AK |
9111 | struct amdgpu_dm_connector *aconnector = |
9112 | to_amdgpu_dm_connector(new_con_state->base.connector); | |
a057ec46 | 9113 | struct drm_display_mode *mode = &new_crtc_state->base.mode; |
0ab925d3 | 9114 | int vrefresh = drm_mode_vrefresh(mode); |
a85ba005 | 9115 | bool fs_vid_mode = false; |
98e6436d | 9116 | |
a057ec46 | 9117 | new_crtc_state->vrr_supported = new_con_state->freesync_capable && |
0ab925d3 NK |
9118 | vrefresh >= aconnector->min_vfreq && |
9119 | vrefresh <= aconnector->max_vfreq; | |
bb47de73 | 9120 | |
6ffa6799 | 9121 | if (new_crtc_state->vrr_supported) { |
7e5098ab | 9122 | new_crtc_state->stream->ignore_msa_timing_param = true; |
6ffa6799 | 9123 | fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; |
7e5098ab | 9124 | |
a85ba005 NC |
9125 | config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; |
9126 | config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; | |
69ff8845 | 9127 | config.vsif_supported = true; |
180db303 | 9128 | config.btr = true; |
98e6436d | 9129 | |
a85ba005 NC |
9130 | if (fs_vid_mode) { |
9131 | config.state = VRR_STATE_ACTIVE_FIXED; | |
9132 | config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; | |
9133 | goto out; | |
9134 | } else if (new_crtc_state->base.vrr_enabled) { | |
9135 | config.state = VRR_STATE_ACTIVE_VARIABLE; | |
9136 | } else { | |
9137 | config.state = VRR_STATE_INACTIVE; | |
9138 | } | |
9139 | } | |
9140 | out: | |
bb47de73 NK |
9141 | new_crtc_state->freesync_config = config; |
9142 | } | |
98e6436d | 9143 | |
bb47de73 NK |
9144 | static void reset_freesync_config_for_crtc( |
9145 | struct dm_crtc_state *new_crtc_state) | |
9146 | { | |
9147 | new_crtc_state->vrr_supported = false; | |
98e6436d | 9148 | |
bb47de73 NK |
9149 | memset(&new_crtc_state->vrr_infopacket, 0, |
9150 | sizeof(new_crtc_state->vrr_infopacket)); | |
98e6436d AK |
9151 | } |
9152 | ||
a85ba005 NC |
9153 | static bool |
9154 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, | |
9155 | struct drm_crtc_state *new_crtc_state) | |
9156 | { | |
1cbd7887 | 9157 | const struct drm_display_mode *old_mode, *new_mode; |
a85ba005 NC |
9158 | |
9159 | if (!old_crtc_state || !new_crtc_state) | |
9160 | return false; | |
9161 | ||
1cbd7887 VS |
9162 | old_mode = &old_crtc_state->mode; |
9163 | new_mode = &new_crtc_state->mode; | |
9164 | ||
9165 | if (old_mode->clock == new_mode->clock && | |
9166 | old_mode->hdisplay == new_mode->hdisplay && | |
9167 | old_mode->vdisplay == new_mode->vdisplay && | |
9168 | old_mode->htotal == new_mode->htotal && | |
9169 | old_mode->vtotal != new_mode->vtotal && | |
9170 | old_mode->hsync_start == new_mode->hsync_start && | |
9171 | old_mode->vsync_start != new_mode->vsync_start && | |
9172 | old_mode->hsync_end == new_mode->hsync_end && | |
9173 | old_mode->vsync_end != new_mode->vsync_end && | |
9174 | old_mode->hskew == new_mode->hskew && | |
9175 | old_mode->vscan == new_mode->vscan && | |
9176 | (old_mode->vsync_end - old_mode->vsync_start) == | |
9177 | (new_mode->vsync_end - new_mode->vsync_start)) | |
a85ba005 NC |
9178 | return true; |
9179 | ||
9180 | return false; | |
9181 | } | |
9182 | ||
c82eddf8 SS |
9183 | static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) |
9184 | { | |
ae67558b | 9185 | u64 num, den, res; |
a85ba005 NC |
9186 | struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; |
9187 | ||
9188 | dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; | |
9189 | ||
9190 | num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; | |
9191 | den = (unsigned long long)new_crtc_state->mode.htotal * | |
9192 | (unsigned long long)new_crtc_state->mode.vtotal; | |
9193 | ||
9194 | res = div_u64(num, den); | |
9195 | dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; | |
9196 | } | |
9197 | ||
f11d9373 | 9198 | static int dm_update_crtc_state(struct amdgpu_display_manager *dm, |
17ce8a69 RL |
9199 | struct drm_atomic_state *state, |
9200 | struct drm_crtc *crtc, | |
9201 | struct drm_crtc_state *old_crtc_state, | |
9202 | struct drm_crtc_state *new_crtc_state, | |
9203 | bool enable, | |
9204 | bool *lock_and_validation_needed) | |
e7b07cee | 9205 | { |
eb3dc897 | 9206 | struct dm_atomic_state *dm_state = NULL; |
54d76575 | 9207 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
9635b754 | 9208 | struct dc_stream_state *new_stream; |
62f55537 | 9209 | int ret = 0; |
d4d4a645 | 9210 | |
1f6010a9 DF |
9211 | /* |
9212 | * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set | |
9213 | * update changed items | |
9214 | */ | |
4b9674e5 LL |
9215 | struct amdgpu_crtc *acrtc = NULL; |
9216 | struct amdgpu_dm_connector *aconnector = NULL; | |
9217 | struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; | |
9218 | struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; | |
e7b07cee | 9219 | |
4b9674e5 | 9220 | new_stream = NULL; |
9635b754 | 9221 | |
4b9674e5 LL |
9222 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
9223 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
9224 | acrtc = to_amdgpu_crtc(crtc); | |
4b9674e5 | 9225 | aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); |
19f89e23 | 9226 | |
4b9674e5 LL |
9227 | /* TODO This hack should go away */ |
9228 | if (aconnector && enable) { | |
9229 | /* Make sure fake sink is created in plug-in scenario */ | |
9230 | drm_new_conn_state = drm_atomic_get_new_connector_state(state, | |
9231 | &aconnector->base); | |
9232 | drm_old_conn_state = drm_atomic_get_old_connector_state(state, | |
9233 | &aconnector->base); | |
19f89e23 | 9234 | |
4b9674e5 LL |
9235 | if (IS_ERR(drm_new_conn_state)) { |
9236 | ret = PTR_ERR_OR_ZERO(drm_new_conn_state); | |
9237 | goto fail; | |
9238 | } | |
19f89e23 | 9239 | |
4b9674e5 LL |
9240 | dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); |
9241 | dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); | |
19f89e23 | 9242 | |
02d35a67 JFZ |
9243 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9244 | goto skip_modeset; | |
9245 | ||
cbd14ae7 SW |
9246 | new_stream = create_validate_stream_for_sink(aconnector, |
9247 | &new_crtc_state->mode, | |
9248 | dm_new_conn_state, | |
9249 | dm_old_crtc_state->stream); | |
19f89e23 | 9250 | |
4b9674e5 LL |
9251 | /* |
9252 | * we can have no stream on ACTION_SET if a display | |
9253 | * was disconnected during S3, in this case it is not an | |
9254 | * error, the OS will be updated after detection, and | |
9255 | * will do the right thing on next atomic commit | |
9256 | */ | |
19f89e23 | 9257 | |
4b9674e5 LL |
9258 | if (!new_stream) { |
9259 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", | |
9260 | __func__, acrtc->base.base.id); | |
9261 | ret = -ENOMEM; | |
9262 | goto fail; | |
9263 | } | |
e7b07cee | 9264 | |
3d4e52d0 VL |
9265 | /* |
9266 | * TODO: Check VSDB bits to decide whether this should | |
9267 | * be enabled or not. | |
9268 | */ | |
9269 | new_stream->triggered_crtc_reset.enabled = | |
9270 | dm->force_timing_sync; | |
9271 | ||
4b9674e5 | 9272 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; |
98e6436d | 9273 | |
88694af9 NK |
9274 | ret = fill_hdr_info_packet(drm_new_conn_state, |
9275 | &new_stream->hdr_static_metadata); | |
9276 | if (ret) | |
9277 | goto fail; | |
9278 | ||
7e930949 NK |
9279 | /* |
9280 | * If we already removed the old stream from the context | |
9281 | * (and set the new stream to NULL) then we can't reuse | |
9282 | * the old stream even if the stream and scaling are unchanged. | |
9283 | * We'll hit the BUG_ON and black screen. | |
9284 | * | |
9285 | * TODO: Refactor this function to allow this check to work | |
9286 | * in all conditions. | |
9287 | */ | |
11b92df8 | 9288 | if (dm_new_crtc_state->stream && |
a85ba005 NC |
9289 | is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) |
9290 | goto skip_modeset; | |
9291 | ||
7e930949 NK |
9292 | if (dm_new_crtc_state->stream && |
9293 | dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && | |
4b9674e5 LL |
9294 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { |
9295 | new_crtc_state->mode_changed = false; | |
9296 | DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", | |
9297 | new_crtc_state->mode_changed); | |
62f55537 | 9298 | } |
4b9674e5 | 9299 | } |
b830ebc9 | 9300 | |
02d35a67 | 9301 | /* mode_changed flag may get updated above, need to check again */ |
4b9674e5 LL |
9302 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9303 | goto skip_modeset; | |
e7b07cee | 9304 | |
9f07550b | 9305 | drm_dbg_state(state->dev, |
c82eddf8 | 9306 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", |
4b9674e5 LL |
9307 | acrtc->crtc_id, |
9308 | new_crtc_state->enable, | |
9309 | new_crtc_state->active, | |
9310 | new_crtc_state->planes_changed, | |
9311 | new_crtc_state->mode_changed, | |
9312 | new_crtc_state->active_changed, | |
9313 | new_crtc_state->connectors_changed); | |
62f55537 | 9314 | |
4b9674e5 LL |
9315 | /* Remove stream for any changed/disabled CRTC */ |
9316 | if (!enable) { | |
62f55537 | 9317 | |
4b9674e5 LL |
9318 | if (!dm_old_crtc_state->stream) |
9319 | goto skip_modeset; | |
eb3dc897 | 9320 | |
0f5f1ee4 AP |
9321 | /* Unset freesync video if it was active before */ |
9322 | if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { | |
9323 | dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; | |
9324 | dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; | |
9325 | } | |
9326 | ||
9327 | /* Now check if we should set freesync video mode */ | |
11b92df8 | 9328 | if (dm_new_crtc_state->stream && |
b18f05a0 AP |
9329 | dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && |
9330 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && | |
a85ba005 NC |
9331 | is_timing_unchanged_for_freesync(new_crtc_state, |
9332 | old_crtc_state)) { | |
9333 | new_crtc_state->mode_changed = false; | |
9334 | DRM_DEBUG_DRIVER( | |
c82eddf8 | 9335 | "Mode change not required for front porch change, setting mode_changed to %d", |
a85ba005 NC |
9336 | new_crtc_state->mode_changed); |
9337 | ||
9338 | set_freesync_fixed_config(dm_new_crtc_state); | |
9339 | ||
9340 | goto skip_modeset; | |
11b92df8 | 9341 | } else if (aconnector && |
a85ba005 NC |
9342 | is_freesync_video_mode(&new_crtc_state->mode, |
9343 | aconnector)) { | |
e88ebd83 SC |
9344 | struct drm_display_mode *high_mode; |
9345 | ||
9346 | high_mode = get_highest_refresh_rate_mode(aconnector, false); | |
c82eddf8 | 9347 | if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) |
e88ebd83 | 9348 | set_freesync_fixed_config(dm_new_crtc_state); |
a85ba005 NC |
9349 | } |
9350 | ||
4b9674e5 LL |
9351 | ret = dm_atomic_get_state(state, &dm_state); |
9352 | if (ret) | |
9353 | goto fail; | |
e7b07cee | 9354 | |
4b9674e5 LL |
9355 | DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", |
9356 | crtc->base.id); | |
62f55537 | 9357 | |
4b9674e5 LL |
9358 | /* i.e. reset mode */ |
9359 | if (dc_remove_stream_from_ctx( | |
9360 | dm->dc, | |
9361 | dm_state->context, | |
9362 | dm_old_crtc_state->stream) != DC_OK) { | |
9363 | ret = -EINVAL; | |
9364 | goto fail; | |
9365 | } | |
62f55537 | 9366 | |
4b9674e5 LL |
9367 | dc_stream_release(dm_old_crtc_state->stream); |
9368 | dm_new_crtc_state->stream = NULL; | |
bb47de73 | 9369 | |
4b9674e5 | 9370 | reset_freesync_config_for_crtc(dm_new_crtc_state); |
62f55537 | 9371 | |
4b9674e5 | 9372 | *lock_and_validation_needed = true; |
62f55537 | 9373 | |
4b9674e5 LL |
9374 | } else {/* Add stream for any updated/enabled CRTC */ |
9375 | /* | |
9376 | * Quick fix to prevent NULL pointer on new_stream when | |
9377 | * added MST connectors not found in existing crtc_state in the chained mode | |
9378 | * TODO: need to dig out the root cause of that | |
9379 | */ | |
84a8b390 | 9380 | if (!aconnector) |
4b9674e5 | 9381 | goto skip_modeset; |
62f55537 | 9382 | |
4b9674e5 LL |
9383 | if (modereset_required(new_crtc_state)) |
9384 | goto skip_modeset; | |
62f55537 | 9385 | |
6c5e25a0 | 9386 | if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, |
4b9674e5 | 9387 | dm_old_crtc_state->stream)) { |
62f55537 | 9388 | |
4b9674e5 | 9389 | WARN_ON(dm_new_crtc_state->stream); |
eb3dc897 | 9390 | |
4b9674e5 LL |
9391 | ret = dm_atomic_get_state(state, &dm_state); |
9392 | if (ret) | |
9393 | goto fail; | |
27b3f4fc | 9394 | |
4b9674e5 | 9395 | dm_new_crtc_state->stream = new_stream; |
62f55537 | 9396 | |
4b9674e5 | 9397 | dc_stream_retain(new_stream); |
1dc90497 | 9398 | |
4711c033 LT |
9399 | DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", |
9400 | crtc->base.id); | |
1dc90497 | 9401 | |
4b9674e5 LL |
9402 | if (dc_add_stream_to_ctx( |
9403 | dm->dc, | |
9404 | dm_state->context, | |
9405 | dm_new_crtc_state->stream) != DC_OK) { | |
9406 | ret = -EINVAL; | |
9407 | goto fail; | |
9b690ef3 BL |
9408 | } |
9409 | ||
4b9674e5 LL |
9410 | *lock_and_validation_needed = true; |
9411 | } | |
9412 | } | |
e277adc5 | 9413 | |
4b9674e5 LL |
9414 | skip_modeset: |
9415 | /* Release extra reference */ | |
9416 | if (new_stream) | |
3335a135 | 9417 | dc_stream_release(new_stream); |
e277adc5 | 9418 | |
4b9674e5 LL |
9419 | /* |
9420 | * We want to do dc stream updates that do not require a | |
9421 | * full modeset below. | |
9422 | */ | |
2afda735 | 9423 | if (!(enable && aconnector && new_crtc_state->active)) |
4b9674e5 LL |
9424 | return 0; |
9425 | /* | |
9426 | * Given above conditions, the dc state cannot be NULL because: | |
9427 | * 1. We're in the process of enabling CRTCs (just been added | |
9428 | * to the dc context, or already is on the context) | |
9429 | * 2. Has a valid connector attached, and | |
9430 | * 3. Is currently active and enabled. | |
9431 | * => The dc stream state currently exists. | |
9432 | */ | |
9433 | BUG_ON(dm_new_crtc_state->stream == NULL); | |
a9e8d275 | 9434 | |
4b9674e5 | 9435 | /* Scaling or underscan settings */ |
c521fc31 RL |
9436 | if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || |
9437 | drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
4b9674e5 LL |
9438 | update_stream_scaling_settings( |
9439 | &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); | |
98e6436d | 9440 | |
b05e2c5e DF |
9441 | /* ABM settings */ |
9442 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; | |
9443 | ||
4b9674e5 LL |
9444 | /* |
9445 | * Color management settings. We also update color properties | |
9446 | * when a modeset is needed, to ensure it gets reprogrammed. | |
9447 | */ | |
9448 | if (dm_new_crtc_state->base.color_mgmt_changed || | |
9449 | drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
cf020d49 | 9450 | ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); |
4b9674e5 LL |
9451 | if (ret) |
9452 | goto fail; | |
62f55537 | 9453 | } |
e7b07cee | 9454 | |
4b9674e5 LL |
9455 | /* Update Freesync settings. */ |
9456 | get_freesync_config_for_crtc(dm_new_crtc_state, | |
9457 | dm_new_conn_state); | |
9458 | ||
62f55537 | 9459 | return ret; |
9635b754 DS |
9460 | |
9461 | fail: | |
9462 | if (new_stream) | |
9463 | dc_stream_release(new_stream); | |
9464 | return ret; | |
62f55537 | 9465 | } |
9b690ef3 | 9466 | |
f6ff2a08 NK |
9467 | static bool should_reset_plane(struct drm_atomic_state *state, |
9468 | struct drm_plane *plane, | |
9469 | struct drm_plane_state *old_plane_state, | |
9470 | struct drm_plane_state *new_plane_state) | |
9471 | { | |
9472 | struct drm_plane *other; | |
9473 | struct drm_plane_state *old_other_state, *new_other_state; | |
9474 | struct drm_crtc_state *new_crtc_state; | |
9475 | int i; | |
9476 | ||
70a1efac NK |
9477 | /* |
9478 | * TODO: Remove this hack once the checks below are sufficient | |
9479 | * enough to determine when we need to reset all the planes on | |
9480 | * the stream. | |
9481 | */ | |
9482 | if (state->allow_modeset) | |
9483 | return true; | |
9484 | ||
f6ff2a08 NK |
9485 | /* Exit early if we know that we're adding or removing the plane. */ |
9486 | if (old_plane_state->crtc != new_plane_state->crtc) | |
9487 | return true; | |
9488 | ||
9489 | /* old crtc == new_crtc == NULL, plane not in context. */ | |
9490 | if (!new_plane_state->crtc) | |
9491 | return false; | |
9492 | ||
9493 | new_crtc_state = | |
9494 | drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); | |
9495 | ||
9496 | if (!new_crtc_state) | |
9497 | return true; | |
9498 | ||
7316c4ad NK |
9499 | /* CRTC Degamma changes currently require us to recreate planes. */ |
9500 | if (new_crtc_state->color_mgmt_changed) | |
9501 | return true; | |
9502 | ||
f6ff2a08 NK |
9503 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9504 | return true; | |
9505 | ||
9506 | /* | |
9507 | * If there are any new primary or overlay planes being added or | |
9508 | * removed then the z-order can potentially change. To ensure | |
9509 | * correct z-order and pipe acquisition the current DC architecture | |
9510 | * requires us to remove and recreate all existing planes. | |
9511 | * | |
9512 | * TODO: Come up with a more elegant solution for this. | |
9513 | */ | |
9514 | for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { | |
6eed95b0 | 9515 | struct amdgpu_framebuffer *old_afb, *new_afb; |
c82eddf8 | 9516 | |
f6ff2a08 NK |
9517 | if (other->type == DRM_PLANE_TYPE_CURSOR) |
9518 | continue; | |
9519 | ||
9520 | if (old_other_state->crtc != new_plane_state->crtc && | |
9521 | new_other_state->crtc != new_plane_state->crtc) | |
9522 | continue; | |
9523 | ||
9524 | if (old_other_state->crtc != new_other_state->crtc) | |
9525 | return true; | |
9526 | ||
dc4cb30d NK |
9527 | /* Src/dst size and scaling updates. */ |
9528 | if (old_other_state->src_w != new_other_state->src_w || | |
9529 | old_other_state->src_h != new_other_state->src_h || | |
9530 | old_other_state->crtc_w != new_other_state->crtc_w || | |
9531 | old_other_state->crtc_h != new_other_state->crtc_h) | |
9532 | return true; | |
9533 | ||
9534 | /* Rotation / mirroring updates. */ | |
9535 | if (old_other_state->rotation != new_other_state->rotation) | |
9536 | return true; | |
9537 | ||
9538 | /* Blending updates. */ | |
9539 | if (old_other_state->pixel_blend_mode != | |
9540 | new_other_state->pixel_blend_mode) | |
9541 | return true; | |
9542 | ||
9543 | /* Alpha updates. */ | |
9544 | if (old_other_state->alpha != new_other_state->alpha) | |
9545 | return true; | |
9546 | ||
9547 | /* Colorspace changes. */ | |
9548 | if (old_other_state->color_range != new_other_state->color_range || | |
9549 | old_other_state->color_encoding != new_other_state->color_encoding) | |
9550 | return true; | |
9551 | ||
9a81cc60 NK |
9552 | /* Framebuffer checks fall at the end. */ |
9553 | if (!old_other_state->fb || !new_other_state->fb) | |
9554 | continue; | |
9555 | ||
9556 | /* Pixel format changes can require bandwidth updates. */ | |
9557 | if (old_other_state->fb->format != new_other_state->fb->format) | |
9558 | return true; | |
9559 | ||
6eed95b0 BN |
9560 | old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; |
9561 | new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; | |
9a81cc60 NK |
9562 | |
9563 | /* Tiling and DCC changes also require bandwidth updates. */ | |
37384b3f BN |
9564 | if (old_afb->tiling_flags != new_afb->tiling_flags || |
9565 | old_afb->base.modifier != new_afb->base.modifier) | |
f6ff2a08 NK |
9566 | return true; |
9567 | } | |
9568 | ||
9569 | return false; | |
9570 | } | |
9571 | ||
b0455fda SS |
9572 | static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, |
9573 | struct drm_plane_state *new_plane_state, | |
9574 | struct drm_framebuffer *fb) | |
9575 | { | |
e72868c4 SS |
9576 | struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); |
9577 | struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); | |
b0455fda | 9578 | unsigned int pitch; |
e72868c4 | 9579 | bool linear; |
b0455fda SS |
9580 | |
9581 | if (fb->width > new_acrtc->max_cursor_width || | |
9582 | fb->height > new_acrtc->max_cursor_height) { | |
9583 | DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", | |
9584 | new_plane_state->fb->width, | |
9585 | new_plane_state->fb->height); | |
9586 | return -EINVAL; | |
9587 | } | |
9588 | if (new_plane_state->src_w != fb->width << 16 || | |
9589 | new_plane_state->src_h != fb->height << 16) { | |
9590 | DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); | |
9591 | return -EINVAL; | |
9592 | } | |
9593 | ||
9594 | /* Pitch in pixels */ | |
9595 | pitch = fb->pitches[0] / fb->format->cpp[0]; | |
9596 | ||
9597 | if (fb->width != pitch) { | |
9598 | DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", | |
9599 | fb->width, pitch); | |
9600 | return -EINVAL; | |
9601 | } | |
9602 | ||
9603 | switch (pitch) { | |
9604 | case 64: | |
9605 | case 128: | |
9606 | case 256: | |
9607 | /* FB pitch is supported by cursor plane */ | |
9608 | break; | |
9609 | default: | |
9610 | DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); | |
9611 | return -EINVAL; | |
9612 | } | |
9613 | ||
e72868c4 | 9614 | /* Core DRM takes care of checking FB modifiers, so we only need to |
c82eddf8 SS |
9615 | * check tiling flags when the FB doesn't have a modifier. |
9616 | */ | |
e72868c4 SS |
9617 | if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { |
9618 | if (adev->family < AMDGPU_FAMILY_AI) { | |
9619 | linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && | |
c82eddf8 | 9620 | AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && |
e72868c4 SS |
9621 | AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; |
9622 | } else { | |
9623 | linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; | |
9624 | } | |
9625 | if (!linear) { | |
9626 | DRM_DEBUG_ATOMIC("Cursor FB not linear"); | |
9627 | return -EINVAL; | |
9628 | } | |
9629 | } | |
9630 | ||
b0455fda SS |
9631 | return 0; |
9632 | } | |
9633 | ||
9e869063 LL |
9634 | static int dm_update_plane_state(struct dc *dc, |
9635 | struct drm_atomic_state *state, | |
9636 | struct drm_plane *plane, | |
9637 | struct drm_plane_state *old_plane_state, | |
9638 | struct drm_plane_state *new_plane_state, | |
9639 | bool enable, | |
35f33086 BL |
9640 | bool *lock_and_validation_needed, |
9641 | bool *is_top_most_overlay) | |
62f55537 | 9642 | { |
eb3dc897 NK |
9643 | |
9644 | struct dm_atomic_state *dm_state = NULL; | |
62f55537 | 9645 | struct drm_crtc *new_plane_crtc, *old_plane_crtc; |
0bc9706d | 9646 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
54d76575 | 9647 | struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; |
54d76575 | 9648 | struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; |
626bf90f | 9649 | struct amdgpu_crtc *new_acrtc; |
f6ff2a08 | 9650 | bool needs_reset; |
62f55537 | 9651 | int ret = 0; |
e7b07cee | 9652 | |
9b690ef3 | 9653 | |
9e869063 LL |
9654 | new_plane_crtc = new_plane_state->crtc; |
9655 | old_plane_crtc = old_plane_state->crtc; | |
9656 | dm_new_plane_state = to_dm_plane_state(new_plane_state); | |
9657 | dm_old_plane_state = to_dm_plane_state(old_plane_state); | |
62f55537 | 9658 | |
626bf90f SS |
9659 | if (plane->type == DRM_PLANE_TYPE_CURSOR) { |
9660 | if (!enable || !new_plane_crtc || | |
9661 | drm_atomic_plane_disabling(plane->state, new_plane_state)) | |
9662 | return 0; | |
9663 | ||
9664 | new_acrtc = to_amdgpu_crtc(new_plane_crtc); | |
9665 | ||
5f581248 SS |
9666 | if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { |
9667 | DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); | |
9668 | return -EINVAL; | |
9669 | } | |
9670 | ||
24f99d2b | 9671 | if (new_plane_state->fb) { |
b0455fda SS |
9672 | ret = dm_check_cursor_fb(new_acrtc, new_plane_state, |
9673 | new_plane_state->fb); | |
9674 | if (ret) | |
9675 | return ret; | |
24f99d2b SS |
9676 | } |
9677 | ||
9e869063 | 9678 | return 0; |
626bf90f | 9679 | } |
9b690ef3 | 9680 | |
f6ff2a08 NK |
9681 | needs_reset = should_reset_plane(state, plane, old_plane_state, |
9682 | new_plane_state); | |
9683 | ||
9e869063 LL |
9684 | /* Remove any changed/removed planes */ |
9685 | if (!enable) { | |
f6ff2a08 | 9686 | if (!needs_reset) |
9e869063 | 9687 | return 0; |
a7b06724 | 9688 | |
9e869063 LL |
9689 | if (!old_plane_crtc) |
9690 | return 0; | |
62f55537 | 9691 | |
9e869063 LL |
9692 | old_crtc_state = drm_atomic_get_old_crtc_state( |
9693 | state, old_plane_crtc); | |
9694 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
9b690ef3 | 9695 | |
9e869063 LL |
9696 | if (!dm_old_crtc_state->stream) |
9697 | return 0; | |
62f55537 | 9698 | |
9e869063 LL |
9699 | DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", |
9700 | plane->base.id, old_plane_crtc->base.id); | |
9b690ef3 | 9701 | |
9e869063 LL |
9702 | ret = dm_atomic_get_state(state, &dm_state); |
9703 | if (ret) | |
9704 | return ret; | |
eb3dc897 | 9705 | |
9e869063 LL |
9706 | if (!dc_remove_plane_from_context( |
9707 | dc, | |
9708 | dm_old_crtc_state->stream, | |
9709 | dm_old_plane_state->dc_state, | |
9710 | dm_state->context)) { | |
62f55537 | 9711 | |
c3537613 | 9712 | return -EINVAL; |
9e869063 | 9713 | } |
e7b07cee | 9714 | |
da5e1490 AP |
9715 | if (dm_old_plane_state->dc_state) |
9716 | dc_plane_state_release(dm_old_plane_state->dc_state); | |
9b690ef3 | 9717 | |
9e869063 | 9718 | dm_new_plane_state->dc_state = NULL; |
1dc90497 | 9719 | |
9e869063 | 9720 | *lock_and_validation_needed = true; |
1dc90497 | 9721 | |
9e869063 LL |
9722 | } else { /* Add new planes */ |
9723 | struct dc_plane_state *dc_new_plane_state; | |
1dc90497 | 9724 | |
9e869063 LL |
9725 | if (drm_atomic_plane_disabling(plane->state, new_plane_state)) |
9726 | return 0; | |
e7b07cee | 9727 | |
9e869063 LL |
9728 | if (!new_plane_crtc) |
9729 | return 0; | |
e7b07cee | 9730 | |
9e869063 LL |
9731 | new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); |
9732 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
1dc90497 | 9733 | |
9e869063 LL |
9734 | if (!dm_new_crtc_state->stream) |
9735 | return 0; | |
62f55537 | 9736 | |
f6ff2a08 | 9737 | if (!needs_reset) |
9e869063 | 9738 | return 0; |
62f55537 | 9739 | |
8bf0d9cd | 9740 | ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); |
8c44515b AP |
9741 | if (ret) |
9742 | return ret; | |
9743 | ||
9e869063 | 9744 | WARN_ON(dm_new_plane_state->dc_state); |
9b690ef3 | 9745 | |
9e869063 LL |
9746 | dc_new_plane_state = dc_create_plane_state(dc); |
9747 | if (!dc_new_plane_state) | |
9748 | return -ENOMEM; | |
62f55537 | 9749 | |
35f33086 BL |
9750 | /* Block top most plane from being a video plane */ |
9751 | if (plane->type == DRM_PLANE_TYPE_OVERLAY) { | |
9752 | if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay) | |
9753 | return -EINVAL; | |
44a4f50d SS |
9754 | |
9755 | *is_top_most_overlay = false; | |
35f33086 BL |
9756 | } |
9757 | ||
4711c033 LT |
9758 | DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", |
9759 | plane->base.id, new_plane_crtc->base.id); | |
8c45c5db | 9760 | |
695af5f9 | 9761 | ret = fill_dc_plane_attributes( |
1348969a | 9762 | drm_to_adev(new_plane_crtc->dev), |
9e869063 LL |
9763 | dc_new_plane_state, |
9764 | new_plane_state, | |
9765 | new_crtc_state); | |
9766 | if (ret) { | |
9767 | dc_plane_state_release(dc_new_plane_state); | |
9768 | return ret; | |
9769 | } | |
62f55537 | 9770 | |
9e869063 LL |
9771 | ret = dm_atomic_get_state(state, &dm_state); |
9772 | if (ret) { | |
9773 | dc_plane_state_release(dc_new_plane_state); | |
9774 | return ret; | |
9775 | } | |
eb3dc897 | 9776 | |
9e869063 LL |
9777 | /* |
9778 | * Any atomic check errors that occur after this will | |
9779 | * not need a release. The plane state will be attached | |
9780 | * to the stream, and therefore part of the atomic | |
9781 | * state. It'll be released when the atomic state is | |
9782 | * cleaned. | |
9783 | */ | |
9784 | if (!dc_add_plane_to_context( | |
9785 | dc, | |
9786 | dm_new_crtc_state->stream, | |
9787 | dc_new_plane_state, | |
9788 | dm_state->context)) { | |
62f55537 | 9789 | |
9e869063 LL |
9790 | dc_plane_state_release(dc_new_plane_state); |
9791 | return -EINVAL; | |
9792 | } | |
8c45c5db | 9793 | |
9e869063 | 9794 | dm_new_plane_state->dc_state = dc_new_plane_state; |
000b59ea | 9795 | |
214993e1 ML |
9796 | dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); |
9797 | ||
9e869063 LL |
9798 | /* Tell DC to do a full surface update every time there |
9799 | * is a plane change. Inefficient, but works for now. | |
9800 | */ | |
9801 | dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; | |
9802 | ||
9803 | *lock_and_validation_needed = true; | |
62f55537 | 9804 | } |
e7b07cee HW |
9805 | |
9806 | ||
62f55537 AG |
9807 | return ret; |
9808 | } | |
a87fa993 | 9809 | |
69cb5629 VZ |
9810 | static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, |
9811 | int *src_w, int *src_h) | |
9812 | { | |
9813 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { | |
9814 | case DRM_MODE_ROTATE_90: | |
9815 | case DRM_MODE_ROTATE_270: | |
9816 | *src_w = plane_state->src_h >> 16; | |
9817 | *src_h = plane_state->src_w >> 16; | |
9818 | break; | |
9819 | case DRM_MODE_ROTATE_0: | |
9820 | case DRM_MODE_ROTATE_180: | |
9821 | default: | |
9822 | *src_w = plane_state->src_w >> 16; | |
9823 | *src_h = plane_state->src_h >> 16; | |
9824 | break; | |
9825 | } | |
9826 | } | |
9827 | ||
12f4849a SS |
9828 | static int dm_check_crtc_cursor(struct drm_atomic_state *state, |
9829 | struct drm_crtc *crtc, | |
9830 | struct drm_crtc_state *new_crtc_state) | |
9831 | { | |
d1bfbe8a SS |
9832 | struct drm_plane *cursor = crtc->cursor, *underlying; |
9833 | struct drm_plane_state *new_cursor_state, *new_underlying_state; | |
9834 | int i; | |
9835 | int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; | |
69cb5629 VZ |
9836 | int cursor_src_w, cursor_src_h; |
9837 | int underlying_src_w, underlying_src_h; | |
12f4849a SS |
9838 | |
9839 | /* On DCE and DCN there is no dedicated hardware cursor plane. We get a | |
9840 | * cursor per pipe but it's going to inherit the scaling and | |
9841 | * positioning from the underlying pipe. Check the cursor plane's | |
c82eddf8 SS |
9842 | * blending properties match the underlying planes'. |
9843 | */ | |
12f4849a | 9844 | |
d1bfbe8a | 9845 | new_cursor_state = drm_atomic_get_new_plane_state(state, cursor); |
c82eddf8 | 9846 | if (!new_cursor_state || !new_cursor_state->fb) |
12f4849a | 9847 | return 0; |
12f4849a | 9848 | |
69cb5629 VZ |
9849 | dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h); |
9850 | cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w; | |
9851 | cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h; | |
12f4849a | 9852 | |
d1bfbe8a SS |
9853 | for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { |
9854 | /* Narrow down to non-cursor planes on the same CRTC as the cursor */ | |
9855 | if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) | |
9856 | continue; | |
12f4849a | 9857 | |
d1bfbe8a SS |
9858 | /* Ignore disabled planes */ |
9859 | if (!new_underlying_state->fb) | |
9860 | continue; | |
9861 | ||
69cb5629 VZ |
9862 | dm_get_oriented_plane_size(new_underlying_state, |
9863 | &underlying_src_w, &underlying_src_h); | |
9864 | underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w; | |
9865 | underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h; | |
d1bfbe8a SS |
9866 | |
9867 | if (cursor_scale_w != underlying_scale_w || | |
9868 | cursor_scale_h != underlying_scale_h) { | |
9869 | drm_dbg_atomic(crtc->dev, | |
9870 | "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", | |
9871 | cursor->base.id, cursor->name, underlying->base.id, underlying->name); | |
9872 | return -EINVAL; | |
9873 | } | |
9874 | ||
9875 | /* If this plane covers the whole CRTC, no need to check planes underneath */ | |
9876 | if (new_underlying_state->crtc_x <= 0 && | |
9877 | new_underlying_state->crtc_y <= 0 && | |
9878 | new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && | |
9879 | new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) | |
9880 | break; | |
12f4849a SS |
9881 | } |
9882 | ||
9883 | return 0; | |
9884 | } | |
9885 | ||
44be939f ML |
9886 | static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) |
9887 | { | |
9888 | struct drm_connector *connector; | |
128f8ed5 | 9889 | struct drm_connector_state *conn_state, *old_conn_state; |
44be939f ML |
9890 | struct amdgpu_dm_connector *aconnector = NULL; |
9891 | int i; | |
c82eddf8 | 9892 | |
128f8ed5 RL |
9893 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { |
9894 | if (!conn_state->crtc) | |
9895 | conn_state = old_conn_state; | |
9896 | ||
44be939f ML |
9897 | if (conn_state->crtc != crtc) |
9898 | continue; | |
9899 | ||
9900 | aconnector = to_amdgpu_dm_connector(connector); | |
f0127cb1 | 9901 | if (!aconnector->mst_output_port || !aconnector->mst_root) |
44be939f ML |
9902 | aconnector = NULL; |
9903 | else | |
9904 | break; | |
9905 | } | |
9906 | ||
9907 | if (!aconnector) | |
9908 | return 0; | |
9909 | ||
f0127cb1 | 9910 | return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); |
44be939f ML |
9911 | } |
9912 | ||
b8592b48 LL |
9913 | /** |
9914 | * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. | |
c620e79b | 9915 | * |
b8592b48 LL |
9916 | * @dev: The DRM device |
9917 | * @state: The atomic state to commit | |
9918 | * | |
9919 | * Validate that the given atomic state is programmable by DC into hardware. | |
9920 | * This involves constructing a &struct dc_state reflecting the new hardware | |
9921 | * state we wish to commit, then querying DC to see if it is programmable. It's | |
9922 | * important not to modify the existing DC state. Otherwise, atomic_check | |
9923 | * may unexpectedly commit hardware changes. | |
9924 | * | |
9925 | * When validating the DC state, it's important that the right locks are | |
9926 | * acquired. For full updates case which removes/adds/updates streams on one | |
9927 | * CRTC while flipping on another CRTC, acquiring global lock will guarantee | |
9928 | * that any such full update commit will wait for completion of any outstanding | |
f6d7c7fa | 9929 | * flip using DRMs synchronization events. |
b8592b48 LL |
9930 | * |
9931 | * Note that DM adds the affected connectors for all CRTCs in state, when that | |
9932 | * might not seem necessary. This is because DC stream creation requires the | |
9933 | * DC sink, which is tied to the DRM connector state. Cleaning this up should | |
9934 | * be possible but non-trivial - a possible TODO item. | |
9935 | * | |
9936 | * Return: -Error code if validation failed. | |
9937 | */ | |
7578ecda AD |
9938 | static int amdgpu_dm_atomic_check(struct drm_device *dev, |
9939 | struct drm_atomic_state *state) | |
62f55537 | 9940 | { |
1348969a | 9941 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 | 9942 | struct dm_atomic_state *dm_state = NULL; |
62f55537 | 9943 | struct dc *dc = adev->dm.dc; |
62f55537 | 9944 | struct drm_connector *connector; |
c2cea706 | 9945 | struct drm_connector_state *old_con_state, *new_con_state; |
62f55537 | 9946 | struct drm_crtc *crtc; |
fc9e9920 | 9947 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
9e869063 LL |
9948 | struct drm_plane *plane; |
9949 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
74a16675 | 9950 | enum dc_status status; |
1e88ad0a | 9951 | int ret, i; |
62f55537 | 9952 | bool lock_and_validation_needed = false; |
35f33086 | 9953 | bool is_top_most_overlay = true; |
214993e1 | 9954 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
cdf657fc DA |
9955 | struct drm_dp_mst_topology_mgr *mgr; |
9956 | struct drm_dp_mst_topology_state *mst_state; | |
6513104b | 9957 | struct dsc_mst_fairness_vars vars[MAX_PIPES]; |
62f55537 | 9958 | |
e8a98235 | 9959 | trace_amdgpu_dm_atomic_check_begin(state); |
c44a22b3 | 9960 | |
62f55537 | 9961 | ret = drm_atomic_helper_check_modeset(dev, state); |
68ca1c3e S |
9962 | if (ret) { |
9963 | DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); | |
01e28f9c | 9964 | goto fail; |
68ca1c3e | 9965 | } |
62f55537 | 9966 | |
c5892a10 SW |
9967 | /* Check connector changes */ |
9968 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
9969 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); | |
9970 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
9971 | ||
9972 | /* Skip connectors that are disabled or part of modeset already. */ | |
c5892a10 SW |
9973 | if (!new_con_state->crtc) |
9974 | continue; | |
9975 | ||
9976 | new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); | |
9977 | if (IS_ERR(new_crtc_state)) { | |
68ca1c3e | 9978 | DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); |
c5892a10 SW |
9979 | ret = PTR_ERR(new_crtc_state); |
9980 | goto fail; | |
9981 | } | |
9982 | ||
3c6d1aeb | 9983 | if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || |
9984 | dm_old_con_state->scaling != dm_new_con_state->scaling) | |
c5892a10 SW |
9985 | new_crtc_state->connectors_changed = true; |
9986 | } | |
9987 | ||
349a19b2 | 9988 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
44be939f ML |
9989 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
9990 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
9991 | ret = add_affected_mst_dsc_crtcs(state, crtc); | |
68ca1c3e S |
9992 | if (ret) { |
9993 | DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); | |
44be939f | 9994 | goto fail; |
68ca1c3e | 9995 | } |
44be939f ML |
9996 | } |
9997 | } | |
9998 | } | |
1e88ad0a | 9999 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
886876ec EB |
10000 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
10001 | ||
1e88ad0a | 10002 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && |
98e6436d | 10003 | !new_crtc_state->color_mgmt_changed && |
886876ec EB |
10004 | old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && |
10005 | dm_old_crtc_state->dsc_force_changed == false) | |
1e88ad0a | 10006 | continue; |
7bef1af3 | 10007 | |
03fc4cf4 | 10008 | ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); |
68ca1c3e S |
10009 | if (ret) { |
10010 | DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); | |
03fc4cf4 | 10011 | goto fail; |
68ca1c3e | 10012 | } |
03fc4cf4 | 10013 | |
1e88ad0a S |
10014 | if (!new_crtc_state->enable) |
10015 | continue; | |
fc9e9920 | 10016 | |
1e88ad0a | 10017 | ret = drm_atomic_add_affected_connectors(state, crtc); |
68ca1c3e S |
10018 | if (ret) { |
10019 | DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); | |
706bc8c5 | 10020 | goto fail; |
68ca1c3e | 10021 | } |
fc9e9920 | 10022 | |
1e88ad0a | 10023 | ret = drm_atomic_add_affected_planes(state, crtc); |
68ca1c3e S |
10024 | if (ret) { |
10025 | DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); | |
1e88ad0a | 10026 | goto fail; |
68ca1c3e | 10027 | } |
115a385c | 10028 | |
cbac53f7 | 10029 | if (dm_old_crtc_state->dsc_force_changed) |
115a385c | 10030 | new_crtc_state->mode_changed = true; |
e7b07cee HW |
10031 | } |
10032 | ||
2d9e6431 NK |
10033 | /* |
10034 | * Add all primary and overlay planes on the CRTC to the state | |
10035 | * whenever a plane is enabled to maintain correct z-ordering | |
10036 | * and to enable fast surface updates. | |
10037 | */ | |
10038 | drm_for_each_crtc(crtc, dev) { | |
10039 | bool modified = false; | |
10040 | ||
10041 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { | |
10042 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
10043 | continue; | |
10044 | ||
10045 | if (new_plane_state->crtc == crtc || | |
10046 | old_plane_state->crtc == crtc) { | |
10047 | modified = true; | |
10048 | break; | |
10049 | } | |
10050 | } | |
10051 | ||
10052 | if (!modified) | |
10053 | continue; | |
10054 | ||
10055 | drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { | |
10056 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
10057 | continue; | |
10058 | ||
10059 | new_plane_state = | |
10060 | drm_atomic_get_plane_state(state, plane); | |
10061 | ||
10062 | if (IS_ERR(new_plane_state)) { | |
10063 | ret = PTR_ERR(new_plane_state); | |
68ca1c3e | 10064 | DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); |
2d9e6431 NK |
10065 | goto fail; |
10066 | } | |
10067 | } | |
10068 | } | |
10069 | ||
22c42b0e LL |
10070 | /* |
10071 | * DC consults the zpos (layer_index in DC terminology) to determine the | |
10072 | * hw plane on which to enable the hw cursor (see | |
10073 | * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in | |
10074 | * atomic state, so call drm helper to normalize zpos. | |
10075 | */ | |
ac0bb08d LL |
10076 | ret = drm_atomic_normalize_zpos(dev, state); |
10077 | if (ret) { | |
10078 | drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); | |
10079 | goto fail; | |
10080 | } | |
22c42b0e | 10081 | |
62f55537 | 10082 | /* Remove exiting planes if they are modified */ |
9e869063 | 10083 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { |
a7c0cad0 HM |
10084 | if (old_plane_state->fb && new_plane_state->fb && |
10085 | get_mem_type(old_plane_state->fb) != | |
10086 | get_mem_type(new_plane_state->fb)) | |
10087 | lock_and_validation_needed = true; | |
10088 | ||
9e869063 LL |
10089 | ret = dm_update_plane_state(dc, state, plane, |
10090 | old_plane_state, | |
10091 | new_plane_state, | |
10092 | false, | |
35f33086 BL |
10093 | &lock_and_validation_needed, |
10094 | &is_top_most_overlay); | |
68ca1c3e S |
10095 | if (ret) { |
10096 | DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); | |
9e869063 | 10097 | goto fail; |
68ca1c3e | 10098 | } |
62f55537 AG |
10099 | } |
10100 | ||
10101 | /* Disable all crtcs which require disable */ | |
4b9674e5 LL |
10102 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
10103 | ret = dm_update_crtc_state(&adev->dm, state, crtc, | |
10104 | old_crtc_state, | |
10105 | new_crtc_state, | |
10106 | false, | |
10107 | &lock_and_validation_needed); | |
68ca1c3e S |
10108 | if (ret) { |
10109 | DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); | |
4b9674e5 | 10110 | goto fail; |
68ca1c3e | 10111 | } |
62f55537 AG |
10112 | } |
10113 | ||
10114 | /* Enable all crtcs which require enable */ | |
4b9674e5 LL |
10115 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
10116 | ret = dm_update_crtc_state(&adev->dm, state, crtc, | |
10117 | old_crtc_state, | |
10118 | new_crtc_state, | |
10119 | true, | |
10120 | &lock_and_validation_needed); | |
68ca1c3e S |
10121 | if (ret) { |
10122 | DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); | |
4b9674e5 | 10123 | goto fail; |
68ca1c3e | 10124 | } |
62f55537 AG |
10125 | } |
10126 | ||
10127 | /* Add new/modified planes */ | |
9e869063 LL |
10128 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { |
10129 | ret = dm_update_plane_state(dc, state, plane, | |
10130 | old_plane_state, | |
10131 | new_plane_state, | |
10132 | true, | |
35f33086 BL |
10133 | &lock_and_validation_needed, |
10134 | &is_top_most_overlay); | |
68ca1c3e S |
10135 | if (ret) { |
10136 | DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); | |
9e869063 | 10137 | goto fail; |
68ca1c3e | 10138 | } |
62f55537 AG |
10139 | } |
10140 | ||
876fcc42 | 10141 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
7cce4cd6 LP |
10142 | ret = pre_validate_dsc(state, &dm_state, vars); |
10143 | if (ret != 0) | |
876fcc42 | 10144 | goto fail; |
876fcc42 | 10145 | } |
876fcc42 | 10146 | |
b349f76e ES |
10147 | /* Run this here since we want to validate the streams we created */ |
10148 | ret = drm_atomic_helper_check_planes(dev, state); | |
68ca1c3e S |
10149 | if (ret) { |
10150 | DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); | |
b349f76e | 10151 | goto fail; |
68ca1c3e | 10152 | } |
62f55537 | 10153 | |
214993e1 ML |
10154 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
10155 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
10156 | if (dm_new_crtc_state->mpo_requested) | |
10157 | DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); | |
10158 | } | |
10159 | ||
12f4849a SS |
10160 | /* Check cursor planes scaling */ |
10161 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { | |
10162 | ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); | |
68ca1c3e S |
10163 | if (ret) { |
10164 | DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); | |
12f4849a | 10165 | goto fail; |
68ca1c3e | 10166 | } |
12f4849a SS |
10167 | } |
10168 | ||
43d10d30 NK |
10169 | if (state->legacy_cursor_update) { |
10170 | /* | |
10171 | * This is a fast cursor update coming from the plane update | |
10172 | * helper, check if it can be done asynchronously for better | |
10173 | * performance. | |
10174 | */ | |
10175 | state->async_update = | |
10176 | !drm_atomic_helper_async_check(dev, state); | |
10177 | ||
10178 | /* | |
10179 | * Skip the remaining global validation if this is an async | |
10180 | * update. Cursor updates can be done without affecting | |
10181 | * state or bandwidth calcs and this avoids the performance | |
10182 | * penalty of locking the private state object and | |
10183 | * allocating a new dc_state. | |
10184 | */ | |
10185 | if (state->async_update) | |
10186 | return 0; | |
10187 | } | |
10188 | ||
ebdd27e1 | 10189 | /* Check scaling and underscan changes*/ |
1f6010a9 | 10190 | /* TODO Removed scaling changes validation due to inability to commit |
e7b07cee HW |
10191 | * new stream into context w\o causing full reset. Need to |
10192 | * decide how to handle. | |
10193 | */ | |
c2cea706 | 10194 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
10195 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); |
10196 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
10197 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
e7b07cee HW |
10198 | |
10199 | /* Skip any modesets/resets */ | |
0bc9706d LSL |
10200 | if (!acrtc || drm_atomic_crtc_needs_modeset( |
10201 | drm_atomic_get_new_crtc_state(state, &acrtc->base))) | |
e7b07cee HW |
10202 | continue; |
10203 | ||
b830ebc9 | 10204 | /* Skip any thing not scale or underscan changes */ |
54d76575 | 10205 | if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) |
e7b07cee HW |
10206 | continue; |
10207 | ||
10208 | lock_and_validation_needed = true; | |
10209 | } | |
10210 | ||
c689e1e3 LP |
10211 | /* set the slot info for each mst_state based on the link encoding format */ |
10212 | for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { | |
10213 | struct amdgpu_dm_connector *aconnector; | |
10214 | struct drm_connector *connector; | |
10215 | struct drm_connector_list_iter iter; | |
10216 | u8 link_coding_cap; | |
10217 | ||
10218 | drm_connector_list_iter_begin(dev, &iter); | |
10219 | drm_for_each_connector_iter(connector, &iter) { | |
10220 | if (connector->index == mst_state->mgr->conn_base_id) { | |
10221 | aconnector = to_amdgpu_dm_connector(connector); | |
10222 | link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); | |
10223 | drm_dp_mst_update_slots(mst_state, link_coding_cap); | |
10224 | ||
10225 | break; | |
10226 | } | |
10227 | } | |
10228 | drm_connector_list_iter_end(&iter); | |
10229 | } | |
c689e1e3 | 10230 | |
f6d7c7fa NK |
10231 | /** |
10232 | * Streams and planes are reset when there are changes that affect | |
10233 | * bandwidth. Anything that affects bandwidth needs to go through | |
10234 | * DC global validation to ensure that the configuration can be applied | |
10235 | * to hardware. | |
10236 | * | |
10237 | * We have to currently stall out here in atomic_check for outstanding | |
10238 | * commits to finish in this case because our IRQ handlers reference | |
10239 | * DRM state directly - we can end up disabling interrupts too early | |
10240 | * if we don't. | |
10241 | * | |
10242 | * TODO: Remove this stall and drop DM state private objects. | |
a87fa993 | 10243 | */ |
f6d7c7fa | 10244 | if (lock_and_validation_needed) { |
eb3dc897 | 10245 | ret = dm_atomic_get_state(state, &dm_state); |
68ca1c3e S |
10246 | if (ret) { |
10247 | DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); | |
eb3dc897 | 10248 | goto fail; |
68ca1c3e | 10249 | } |
e7b07cee HW |
10250 | |
10251 | ret = do_aquire_global_lock(dev, state); | |
68ca1c3e S |
10252 | if (ret) { |
10253 | DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); | |
e7b07cee | 10254 | goto fail; |
68ca1c3e | 10255 | } |
1dc90497 | 10256 | |
7cce4cd6 LP |
10257 | ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); |
10258 | if (ret) { | |
68ca1c3e | 10259 | DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); |
dd24662d | 10260 | ret = -EINVAL; |
8c20a1ed | 10261 | goto fail; |
68ca1c3e | 10262 | } |
8c20a1ed | 10263 | |
6513104b | 10264 | ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); |
68ca1c3e S |
10265 | if (ret) { |
10266 | DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); | |
29b9ba74 | 10267 | goto fail; |
68ca1c3e | 10268 | } |
29b9ba74 | 10269 | |
ded58c7b ZL |
10270 | /* |
10271 | * Perform validation of MST topology in the state: | |
10272 | * We need to perform MST atomic check before calling | |
10273 | * dc_validate_global_state(), or there is a chance | |
10274 | * to get stuck in an infinite loop and hang eventually. | |
10275 | */ | |
10276 | ret = drm_dp_mst_atomic_check(state); | |
68ca1c3e S |
10277 | if (ret) { |
10278 | DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); | |
ded58c7b | 10279 | goto fail; |
68ca1c3e | 10280 | } |
85fb8bb9 | 10281 | status = dc_validate_global_state(dc, dm_state->context, true); |
74a16675 | 10282 | if (status != DC_OK) { |
68ca1c3e | 10283 | DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", |
74a16675 | 10284 | dc_status_to_str(status), status); |
e7b07cee HW |
10285 | ret = -EINVAL; |
10286 | goto fail; | |
10287 | } | |
bd200d19 | 10288 | } else { |
674e78ac | 10289 | /* |
bd200d19 NK |
10290 | * The commit is a fast update. Fast updates shouldn't change |
10291 | * the DC context, affect global validation, and can have their | |
10292 | * commit work done in parallel with other commits not touching | |
10293 | * the same resource. If we have a new DC context as part of | |
10294 | * the DM atomic state from validation we need to free it and | |
10295 | * retain the existing one instead. | |
fde9f39a MR |
10296 | * |
10297 | * Furthermore, since the DM atomic state only contains the DC | |
10298 | * context and can safely be annulled, we can free the state | |
10299 | * and clear the associated private object now to free | |
10300 | * some memory and avoid a possible use-after-free later. | |
674e78ac | 10301 | */ |
bd200d19 | 10302 | |
fde9f39a MR |
10303 | for (i = 0; i < state->num_private_objs; i++) { |
10304 | struct drm_private_obj *obj = state->private_objs[i].ptr; | |
bd200d19 | 10305 | |
fde9f39a MR |
10306 | if (obj->funcs == adev->dm.atomic_obj.funcs) { |
10307 | int j = state->num_private_objs-1; | |
bd200d19 | 10308 | |
fde9f39a MR |
10309 | dm_atomic_destroy_state(obj, |
10310 | state->private_objs[i].state); | |
10311 | ||
10312 | /* If i is not at the end of the array then the | |
10313 | * last element needs to be moved to where i was | |
10314 | * before the array can safely be truncated. | |
10315 | */ | |
10316 | if (i != j) | |
10317 | state->private_objs[i] = | |
10318 | state->private_objs[j]; | |
bd200d19 | 10319 | |
fde9f39a MR |
10320 | state->private_objs[j].ptr = NULL; |
10321 | state->private_objs[j].state = NULL; | |
10322 | state->private_objs[j].old_state = NULL; | |
10323 | state->private_objs[j].new_state = NULL; | |
10324 | ||
10325 | state->num_private_objs = j; | |
10326 | break; | |
10327 | } | |
bd200d19 | 10328 | } |
e7b07cee HW |
10329 | } |
10330 | ||
caff0e66 | 10331 | /* Store the overall update type for use later in atomic check. */ |
c82eddf8 | 10332 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
caff0e66 NK |
10333 | struct dm_crtc_state *dm_new_crtc_state = |
10334 | to_dm_crtc_state(new_crtc_state); | |
10335 | ||
a7c0cad0 HM |
10336 | /* |
10337 | * Only allow async flips for fast updates that don't change | |
10338 | * the FB pitch, the DCC state, rotation, etc. | |
10339 | */ | |
10340 | if (new_crtc_state->async_flip && lock_and_validation_needed) { | |
10341 | drm_dbg_atomic(crtc->dev, | |
10342 | "[CRTC:%d:%s] async flips are only supported for fast updates\n", | |
10343 | crtc->base.id, crtc->name); | |
10344 | ret = -EINVAL; | |
10345 | goto fail; | |
10346 | } | |
10347 | ||
f6d7c7fa | 10348 | dm_new_crtc_state->update_type = lock_and_validation_needed ? |
a7c0cad0 | 10349 | UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; |
e7b07cee HW |
10350 | } |
10351 | ||
10352 | /* Must be success */ | |
10353 | WARN_ON(ret); | |
e8a98235 RS |
10354 | |
10355 | trace_amdgpu_dm_atomic_check_finish(state, ret); | |
10356 | ||
e7b07cee HW |
10357 | return ret; |
10358 | ||
10359 | fail: | |
10360 | if (ret == -EDEADLK) | |
01e28f9c | 10361 | DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); |
e7b07cee | 10362 | else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) |
01e28f9c | 10363 | DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); |
e7b07cee | 10364 | else |
c82eddf8 | 10365 | DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret); |
e7b07cee | 10366 | |
e8a98235 RS |
10367 | trace_amdgpu_dm_atomic_check_finish(state, ret); |
10368 | ||
e7b07cee HW |
10369 | return ret; |
10370 | } | |
10371 | ||
3ee6b26b AD |
10372 | static bool is_dp_capable_without_timing_msa(struct dc *dc, |
10373 | struct amdgpu_dm_connector *amdgpu_dm_connector) | |
e7b07cee | 10374 | { |
ae67558b | 10375 | u8 dpcd_data; |
e7b07cee HW |
10376 | bool capable = false; |
10377 | ||
c84dec2f | 10378 | if (amdgpu_dm_connector->dc_link && |
e7b07cee HW |
10379 | dm_helpers_dp_read_dpcd( |
10380 | NULL, | |
c84dec2f | 10381 | amdgpu_dm_connector->dc_link, |
e7b07cee HW |
10382 | DP_DOWN_STREAM_PORT_COUNT, |
10383 | &dpcd_data, | |
10384 | sizeof(dpcd_data))) { | |
10385 | capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; | |
10386 | } | |
10387 | ||
10388 | return capable; | |
10389 | } | |
f9b4f20c | 10390 | |
46db138d SW |
10391 | static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, |
10392 | unsigned int offset, | |
10393 | unsigned int total_length, | |
ae67558b | 10394 | u8 *data, |
46db138d SW |
10395 | unsigned int length, |
10396 | struct amdgpu_hdmi_vsdb_info *vsdb) | |
10397 | { | |
10398 | bool res; | |
10399 | union dmub_rb_cmd cmd; | |
10400 | struct dmub_cmd_send_edid_cea *input; | |
10401 | struct dmub_cmd_edid_cea_output *output; | |
10402 | ||
10403 | if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) | |
10404 | return false; | |
10405 | ||
10406 | memset(&cmd, 0, sizeof(cmd)); | |
10407 | ||
10408 | input = &cmd.edid_cea.data.input; | |
10409 | ||
10410 | cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; | |
10411 | cmd.edid_cea.header.sub_type = 0; | |
10412 | cmd.edid_cea.header.payload_bytes = | |
10413 | sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); | |
10414 | input->offset = offset; | |
10415 | input->length = length; | |
eb9e59eb | 10416 | input->cea_total_length = total_length; |
46db138d SW |
10417 | memcpy(input->payload, data, length); |
10418 | ||
e97cc04f | 10419 | res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); |
46db138d SW |
10420 | if (!res) { |
10421 | DRM_ERROR("EDID CEA parser failed\n"); | |
10422 | return false; | |
10423 | } | |
10424 | ||
10425 | output = &cmd.edid_cea.data.output; | |
10426 | ||
10427 | if (output->type == DMUB_CMD__EDID_CEA_ACK) { | |
10428 | if (!output->ack.success) { | |
10429 | DRM_ERROR("EDID CEA ack failed at offset %d\n", | |
10430 | output->ack.offset); | |
10431 | } | |
10432 | } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { | |
10433 | if (!output->amd_vsdb.vsdb_found) | |
10434 | return false; | |
10435 | ||
10436 | vsdb->freesync_supported = output->amd_vsdb.freesync_supported; | |
10437 | vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; | |
10438 | vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; | |
10439 | vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; | |
10440 | } else { | |
b76a8062 | 10441 | DRM_WARN("Unknown EDID CEA parser results\n"); |
46db138d SW |
10442 | return false; |
10443 | } | |
10444 | ||
10445 | return true; | |
10446 | } | |
10447 | ||
10448 | static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, | |
ae67558b | 10449 | u8 *edid_ext, int len, |
f9b4f20c SW |
10450 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10451 | { | |
10452 | int i; | |
f9b4f20c SW |
10453 | |
10454 | /* send extension block to DMCU for parsing */ | |
10455 | for (i = 0; i < len; i += 8) { | |
10456 | bool res; | |
10457 | int offset; | |
10458 | ||
10459 | /* send 8 bytes a time */ | |
46db138d | 10460 | if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) |
f9b4f20c SW |
10461 | return false; |
10462 | ||
10463 | if (i+8 == len) { | |
10464 | /* EDID block sent completed, expect result */ | |
10465 | int version, min_rate, max_rate; | |
10466 | ||
46db138d | 10467 | res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); |
f9b4f20c SW |
10468 | if (res) { |
10469 | /* amd vsdb found */ | |
10470 | vsdb_info->freesync_supported = 1; | |
10471 | vsdb_info->amd_vsdb_version = version; | |
10472 | vsdb_info->min_refresh_rate_hz = min_rate; | |
10473 | vsdb_info->max_refresh_rate_hz = max_rate; | |
10474 | return true; | |
10475 | } | |
10476 | /* not amd vsdb */ | |
10477 | return false; | |
10478 | } | |
10479 | ||
10480 | /* check for ack*/ | |
46db138d | 10481 | res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); |
f9b4f20c SW |
10482 | if (!res) |
10483 | return false; | |
10484 | } | |
10485 | ||
10486 | return false; | |
10487 | } | |
10488 | ||
46db138d | 10489 | static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, |
ae67558b | 10490 | u8 *edid_ext, int len, |
46db138d SW |
10491 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10492 | { | |
10493 | int i; | |
10494 | ||
10495 | /* send extension block to DMCU for parsing */ | |
10496 | for (i = 0; i < len; i += 8) { | |
10497 | /* send 8 bytes a time */ | |
10498 | if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) | |
10499 | return false; | |
10500 | } | |
10501 | ||
10502 | return vsdb_info->freesync_supported; | |
10503 | } | |
10504 | ||
10505 | static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, | |
ae67558b | 10506 | u8 *edid_ext, int len, |
46db138d SW |
10507 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10508 | { | |
10509 | struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); | |
53f4da73 | 10510 | bool ret; |
46db138d | 10511 | |
53f4da73 | 10512 | mutex_lock(&adev->dm.dc_lock); |
46db138d | 10513 | if (adev->dm.dmub_srv) |
53f4da73 | 10514 | ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); |
46db138d | 10515 | else |
53f4da73 SW |
10516 | ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); |
10517 | mutex_unlock(&adev->dm.dc_lock); | |
10518 | return ret; | |
46db138d SW |
10519 | } |
10520 | ||
ec8e59cb BL |
10521 | static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, |
10522 | struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) | |
10523 | { | |
10524 | u8 *edid_ext = NULL; | |
10525 | int i; | |
10526 | int j = 0; | |
10527 | ||
10528 | if (edid == NULL || edid->extensions == 0) | |
10529 | return -ENODEV; | |
10530 | ||
10531 | /* Find DisplayID extension */ | |
10532 | for (i = 0; i < edid->extensions; i++) { | |
10533 | edid_ext = (void *)(edid + (i + 1)); | |
10534 | if (edid_ext[0] == DISPLAYID_EXT) | |
10535 | break; | |
10536 | } | |
10537 | ||
10538 | while (j < EDID_LENGTH) { | |
10539 | struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; | |
10540 | unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); | |
10541 | ||
10542 | if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && | |
10543 | amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { | |
10544 | vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; | |
10545 | vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; | |
10546 | DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); | |
10547 | ||
10548 | return true; | |
10549 | } | |
10550 | j++; | |
10551 | } | |
10552 | ||
10553 | return false; | |
10554 | } | |
10555 | ||
7c7dd774 | 10556 | static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, |
f9b4f20c SW |
10557 | struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10558 | { | |
ae67558b | 10559 | u8 *edid_ext = NULL; |
f9b4f20c SW |
10560 | int i; |
10561 | bool valid_vsdb_found = false; | |
10562 | ||
10563 | /*----- drm_find_cea_extension() -----*/ | |
10564 | /* No EDID or EDID extensions */ | |
10565 | if (edid == NULL || edid->extensions == 0) | |
7c7dd774 | 10566 | return -ENODEV; |
f9b4f20c SW |
10567 | |
10568 | /* Find CEA extension */ | |
10569 | for (i = 0; i < edid->extensions; i++) { | |
10570 | edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); | |
10571 | if (edid_ext[0] == CEA_EXT) | |
10572 | break; | |
10573 | } | |
10574 | ||
10575 | if (i == edid->extensions) | |
7c7dd774 | 10576 | return -ENODEV; |
f9b4f20c SW |
10577 | |
10578 | /*----- cea_db_offsets() -----*/ | |
10579 | if (edid_ext[0] != CEA_EXT) | |
7c7dd774 | 10580 | return -ENODEV; |
f9b4f20c SW |
10581 | |
10582 | valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); | |
7c7dd774 AB |
10583 | |
10584 | return valid_vsdb_found ? i : -ENODEV; | |
f9b4f20c SW |
10585 | } |
10586 | ||
c620e79b RS |
10587 | /** |
10588 | * amdgpu_dm_update_freesync_caps - Update Freesync capabilities | |
10589 | * | |
41ee1f18 AD |
10590 | * @connector: Connector to query. |
10591 | * @edid: EDID from monitor | |
c620e79b RS |
10592 | * |
10593 | * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep | |
10594 | * track of some of the display information in the internal data struct used by | |
10595 | * amdgpu_dm. This function checks which type of connector we need to set the | |
10596 | * FreeSync parameters. | |
10597 | */ | |
98e6436d | 10598 | void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
c620e79b | 10599 | struct edid *edid) |
e7b07cee | 10600 | { |
eb0709ba | 10601 | int i = 0; |
e7b07cee HW |
10602 | struct detailed_timing *timing; |
10603 | struct detailed_non_pixel *data; | |
10604 | struct detailed_data_monitor_range *range; | |
c84dec2f HW |
10605 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
10606 | to_amdgpu_dm_connector(connector); | |
bb47de73 | 10607 | struct dm_connector_state *dm_con_state = NULL; |
9ad54467 | 10608 | struct dc_sink *sink; |
e7b07cee HW |
10609 | |
10610 | struct drm_device *dev = connector->dev; | |
1348969a | 10611 | struct amdgpu_device *adev = drm_to_adev(dev); |
f9b4f20c | 10612 | struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; |
c620e79b | 10613 | bool freesync_capable = false; |
5b49da02 | 10614 | enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; |
b830ebc9 | 10615 | |
8218d7f1 HW |
10616 | if (!connector->state) { |
10617 | DRM_ERROR("%s - Connector has no state", __func__); | |
bb47de73 | 10618 | goto update; |
8218d7f1 HW |
10619 | } |
10620 | ||
9b2fdc33 AP |
10621 | sink = amdgpu_dm_connector->dc_sink ? |
10622 | amdgpu_dm_connector->dc_sink : | |
10623 | amdgpu_dm_connector->dc_em_sink; | |
10624 | ||
10625 | if (!edid || !sink) { | |
98e6436d AK |
10626 | dm_con_state = to_dm_connector_state(connector->state); |
10627 | ||
10628 | amdgpu_dm_connector->min_vfreq = 0; | |
10629 | amdgpu_dm_connector->max_vfreq = 0; | |
10630 | amdgpu_dm_connector->pixel_clock_mhz = 0; | |
9b2fdc33 AP |
10631 | connector->display_info.monitor_range.min_vfreq = 0; |
10632 | connector->display_info.monitor_range.max_vfreq = 0; | |
10633 | freesync_capable = false; | |
98e6436d | 10634 | |
bb47de73 | 10635 | goto update; |
98e6436d AK |
10636 | } |
10637 | ||
8218d7f1 HW |
10638 | dm_con_state = to_dm_connector_state(connector->state); |
10639 | ||
e7b07cee | 10640 | if (!adev->dm.freesync_module) |
bb47de73 | 10641 | goto update; |
f9b4f20c | 10642 | |
9b2fdc33 AP |
10643 | if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT |
10644 | || sink->sink_signal == SIGNAL_TYPE_EDP) { | |
f9b4f20c SW |
10645 | bool edid_check_required = false; |
10646 | ||
10647 | if (edid) { | |
e7b07cee HW |
10648 | edid_check_required = is_dp_capable_without_timing_msa( |
10649 | adev->dm.dc, | |
c84dec2f | 10650 | amdgpu_dm_connector); |
e7b07cee | 10651 | } |
e7b07cee | 10652 | |
f9b4f20c SW |
10653 | if (edid_check_required == true && (edid->version > 1 || |
10654 | (edid->version == 1 && edid->revision > 1))) { | |
10655 | for (i = 0; i < 4; i++) { | |
e7b07cee | 10656 | |
f9b4f20c SW |
10657 | timing = &edid->detailed_timings[i]; |
10658 | data = &timing->data.other_data; | |
10659 | range = &data->data.range; | |
10660 | /* | |
10661 | * Check if monitor has continuous frequency mode | |
10662 | */ | |
10663 | if (data->type != EDID_DETAIL_MONITOR_RANGE) | |
10664 | continue; | |
10665 | /* | |
10666 | * Check for flag range limits only. If flag == 1 then | |
10667 | * no additional timing information provided. | |
10668 | * Default GTF, GTF Secondary curve and CVT are not | |
10669 | * supported | |
10670 | */ | |
10671 | if (range->flags != 1) | |
10672 | continue; | |
a0ffc3fd | 10673 | |
f9b4f20c SW |
10674 | amdgpu_dm_connector->min_vfreq = range->min_vfreq; |
10675 | amdgpu_dm_connector->max_vfreq = range->max_vfreq; | |
10676 | amdgpu_dm_connector->pixel_clock_mhz = | |
10677 | range->pixel_clock_mhz * 10; | |
a0ffc3fd | 10678 | |
f9b4f20c SW |
10679 | connector->display_info.monitor_range.min_vfreq = range->min_vfreq; |
10680 | connector->display_info.monitor_range.max_vfreq = range->max_vfreq; | |
e7b07cee | 10681 | |
f9b4f20c SW |
10682 | break; |
10683 | } | |
98e6436d | 10684 | |
f9b4f20c SW |
10685 | if (amdgpu_dm_connector->max_vfreq - |
10686 | amdgpu_dm_connector->min_vfreq > 10) { | |
98e6436d | 10687 | |
f9b4f20c SW |
10688 | freesync_capable = true; |
10689 | } | |
10690 | } | |
ec8e59cb BL |
10691 | parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); |
10692 | ||
10693 | if (vsdb_info.replay_mode) { | |
10694 | amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; | |
10695 | amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; | |
10696 | amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; | |
10697 | } | |
10698 | ||
9b2fdc33 | 10699 | } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
7c7dd774 AB |
10700 | i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); |
10701 | if (i >= 0 && vsdb_info.freesync_supported) { | |
f9b4f20c SW |
10702 | timing = &edid->detailed_timings[i]; |
10703 | data = &timing->data.other_data; | |
10704 | ||
10705 | amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; | |
5b49da02 SJK |
10706 | amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; |
10707 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) | |
10708 | freesync_capable = true; | |
10709 | ||
10710 | connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; | |
10711 | connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; | |
10712 | } | |
10713 | } | |
10714 | ||
10715 | as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); | |
10716 | ||
10717 | if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { | |
10718 | i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); | |
10719 | if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { | |
10720 | ||
10721 | amdgpu_dm_connector->pack_sdp_v1_3 = true; | |
10722 | amdgpu_dm_connector->as_type = as_type; | |
10723 | amdgpu_dm_connector->vsdb_info = vsdb_info; | |
10724 | ||
10725 | amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; | |
f9b4f20c SW |
10726 | amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; |
10727 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) | |
10728 | freesync_capable = true; | |
10729 | ||
10730 | connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; | |
10731 | connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; | |
e7b07cee HW |
10732 | } |
10733 | } | |
bb47de73 NK |
10734 | |
10735 | update: | |
10736 | if (dm_con_state) | |
10737 | dm_con_state->freesync_capable = freesync_capable; | |
10738 | ||
10739 | if (connector->vrr_capable_property) | |
10740 | drm_connector_set_vrr_capable_property(connector, | |
10741 | freesync_capable); | |
e7b07cee HW |
10742 | } |
10743 | ||
3d4e52d0 VL |
10744 | void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) |
10745 | { | |
1348969a | 10746 | struct amdgpu_device *adev = drm_to_adev(dev); |
3d4e52d0 VL |
10747 | struct dc *dc = adev->dm.dc; |
10748 | int i; | |
10749 | ||
10750 | mutex_lock(&adev->dm.dc_lock); | |
10751 | if (dc->current_state) { | |
10752 | for (i = 0; i < dc->current_state->stream_count; ++i) | |
10753 | dc->current_state->streams[i] | |
10754 | ->triggered_crtc_reset.enabled = | |
10755 | adev->dm.force_timing_sync; | |
10756 | ||
10757 | dm_enable_per_frame_crtc_master_sync(dc->current_state); | |
10758 | dc_trigger_sync(dc, dc->current_state); | |
10759 | } | |
10760 | mutex_unlock(&adev->dm.dc_lock); | |
10761 | } | |
9d83722d RS |
10762 | |
10763 | void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, | |
ae67558b | 10764 | u32 value, const char *func_name) |
9d83722d RS |
10765 | { |
10766 | #ifdef DM_CHECK_ADDR_0 | |
10767 | if (address == 0) { | |
10768 | DC_ERR("invalid register write. address = 0"); | |
10769 | return; | |
10770 | } | |
10771 | #endif | |
10772 | cgs_write_register(ctx->cgs_device, address, value); | |
10773 | trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); | |
10774 | } | |
10775 | ||
10776 | uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, | |
10777 | const char *func_name) | |
10778 | { | |
ae67558b | 10779 | u32 value; |
9d83722d RS |
10780 | #ifdef DM_CHECK_ADDR_0 |
10781 | if (address == 0) { | |
10782 | DC_ERR("invalid register read; address = 0\n"); | |
10783 | return 0; | |
10784 | } | |
10785 | #endif | |
10786 | ||
10787 | if (ctx->dmub_srv && | |
10788 | ctx->dmub_srv->reg_helper_offload.gather_in_progress && | |
10789 | !ctx->dmub_srv->reg_helper_offload.should_burst_write) { | |
10790 | ASSERT(false); | |
10791 | return 0; | |
10792 | } | |
10793 | ||
10794 | value = cgs_read_register(ctx->cgs_device, address); | |
10795 | ||
10796 | trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); | |
10797 | ||
10798 | return value; | |
10799 | } | |
81927e28 | 10800 | |
ead08b95 SW |
10801 | int amdgpu_dm_process_dmub_aux_transfer_sync( |
10802 | struct dc_context *ctx, | |
10803 | unsigned int link_index, | |
10804 | struct aux_payload *payload, | |
10805 | enum aux_return_code_type *operation_result) | |
88f52b1f JS |
10806 | { |
10807 | struct amdgpu_device *adev = ctx->driver_context; | |
88f52b1f | 10808 | struct dmub_notification *p_notify = adev->dm.dmub_notify; |
ead08b95 | 10809 | int ret = -1; |
88f52b1f | 10810 | |
ead08b95 SW |
10811 | mutex_lock(&adev->dm.dpia_aux_lock); |
10812 | if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { | |
10813 | *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; | |
10814 | goto out; | |
3335a135 | 10815 | } |
ead08b95 SW |
10816 | |
10817 | if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { | |
10818 | DRM_ERROR("wait_for_completion_timeout timeout!"); | |
10819 | *operation_result = AUX_RET_ERROR_TIMEOUT; | |
10820 | goto out; | |
10821 | } | |
10822 | ||
10823 | if (p_notify->result != AUX_RET_SUCCESS) { | |
10824 | /* | |
10825 | * Transient states before tunneling is enabled could | |
10826 | * lead to this error. We can ignore this for now. | |
10827 | */ | |
10828 | if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { | |
10829 | DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", | |
10830 | payload->address, payload->length, | |
10831 | p_notify->result); | |
88f52b1f | 10832 | } |
ead08b95 SW |
10833 | *operation_result = AUX_RET_ERROR_INVALID_REPLY; |
10834 | goto out; | |
10835 | } | |
10836 | ||
10837 | ||
10838 | payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; | |
10839 | if (!payload->write && p_notify->aux_reply.length && | |
10840 | (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { | |
10841 | ||
10842 | if (payload->length != p_notify->aux_reply.length) { | |
10843 | DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", | |
10844 | p_notify->aux_reply.length, | |
10845 | payload->address, payload->length); | |
10846 | *operation_result = AUX_RET_ERROR_INVALID_REPLY; | |
10847 | goto out; | |
88f52b1f | 10848 | } |
ead08b95 SW |
10849 | |
10850 | memcpy(payload->data, p_notify->aux_reply.data, | |
10851 | p_notify->aux_reply.length); | |
88f52b1f JS |
10852 | } |
10853 | ||
ead08b95 SW |
10854 | /* success */ |
10855 | ret = p_notify->aux_reply.length; | |
10856 | *operation_result = p_notify->result; | |
10857 | out: | |
0cf8307a | 10858 | reinit_completion(&adev->dm.dmub_aux_transfer_done); |
ead08b95 SW |
10859 | mutex_unlock(&adev->dm.dpia_aux_lock); |
10860 | return ret; | |
88f52b1f JS |
10861 | } |
10862 | ||
ead08b95 SW |
10863 | int amdgpu_dm_process_dmub_set_config_sync( |
10864 | struct dc_context *ctx, | |
10865 | unsigned int link_index, | |
10866 | struct set_config_cmd_payload *payload, | |
10867 | enum set_config_status *operation_result) | |
81927e28 JS |
10868 | { |
10869 | struct amdgpu_device *adev = ctx->driver_context; | |
ead08b95 SW |
10870 | bool is_cmd_complete; |
10871 | int ret; | |
81927e28 | 10872 | |
ead08b95 SW |
10873 | mutex_lock(&adev->dm.dpia_aux_lock); |
10874 | is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, | |
10875 | link_index, payload, adev->dm.dmub_notify); | |
88f52b1f | 10876 | |
ead08b95 SW |
10877 | if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { |
10878 | ret = 0; | |
10879 | *operation_result = adev->dm.dmub_notify->sc_status; | |
10880 | } else { | |
9e3a50d2 | 10881 | DRM_ERROR("wait_for_completion_timeout timeout!"); |
ead08b95 SW |
10882 | ret = -1; |
10883 | *operation_result = SET_CONFIG_UNKNOWN_ERROR; | |
81927e28 JS |
10884 | } |
10885 | ||
0cf8307a SW |
10886 | if (!is_cmd_complete) |
10887 | reinit_completion(&adev->dm.dmub_aux_transfer_done); | |
ead08b95 SW |
10888 | mutex_unlock(&adev->dm.dpia_aux_lock); |
10889 | return ret; | |
81927e28 | 10890 | } |
1edf5ae1 ZL |
10891 | |
10892 | /* | |
10893 | * Check whether seamless boot is supported. | |
10894 | * | |
10895 | * So far we only support seamless boot on CHIP_VANGOGH. | |
10896 | * If everything goes well, we may consider expanding | |
10897 | * seamless boot to other ASICs. | |
10898 | */ | |
10899 | bool check_seamless_boot_capability(struct amdgpu_device *adev) | |
10900 | { | |
20875141 PY |
10901 | switch (adev->ip_versions[DCE_HWIP][0]) { |
10902 | case IP_VERSION(3, 0, 1): | |
1edf5ae1 ZL |
10903 | if (!adev->mman.keep_stolen_vga_memory) |
10904 | return true; | |
10905 | break; | |
10906 | default: | |
10907 | break; | |
10908 | } | |
10909 | ||
10910 | return false; | |
10911 | } | |
e97cc04f JP |
10912 | |
10913 | bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) | |
10914 | { | |
10915 | return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); | |
10916 | } | |
10917 | ||
10918 | bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) | |
10919 | { | |
10920 | return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); | |
10921 | } |