Commit | Line | Data |
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4562236b HW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
0cf5eb76 DF |
26 | /* The caprices of the preprocessor require that this be declared right here */ |
27 | #define CREATE_TRACE_POINTS | |
28 | ||
4562236b HW |
29 | #include "dm_services_types.h" |
30 | #include "dc.h" | |
f6e03f80 | 31 | #include "link_enc_cfg.h" |
1dc90497 | 32 | #include "dc/inc/core_types.h" |
a7669aff | 33 | #include "dal_asic_id.h" |
cdca3f21 | 34 | #include "dmub/dmub_srv.h" |
743b9786 NK |
35 | #include "dc/inc/hw/dmcu.h" |
36 | #include "dc/inc/hw/abm.h" | |
9a71c7d3 | 37 | #include "dc/dc_dmub_srv.h" |
f9b4f20c | 38 | #include "dc/dc_edid_parser.h" |
81927e28 | 39 | #include "dc/dc_stat.h" |
9d83722d | 40 | #include "amdgpu_dm_trace.h" |
028c4ccf | 41 | #include "dpcd_defs.h" |
bc33f5e5 | 42 | #include "link/protocols/link_dpcd.h" |
028c4ccf | 43 | #include "link_service_types.h" |
1e5d4d8e RL |
44 | #include "link/protocols/link_dp_capability.h" |
45 | #include "link/protocols/link_ddc.h" | |
4562236b HW |
46 | |
47 | #include "vid.h" | |
48 | #include "amdgpu.h" | |
a49dcb88 | 49 | #include "amdgpu_display.h" |
a94d5569 | 50 | #include "amdgpu_ucode.h" |
4562236b HW |
51 | #include "atom.h" |
52 | #include "amdgpu_dm.h" | |
5d945cbc | 53 | #include "amdgpu_dm_plane.h" |
473683a0 | 54 | #include "amdgpu_dm_crtc.h" |
52704fca | 55 | #include "amdgpu_dm_hdcp.h" |
6a99099f | 56 | #include <drm/display/drm_hdcp_helper.h> |
e7b07cee | 57 | #include "amdgpu_pm.h" |
1f579254 | 58 | #include "amdgpu_atombios.h" |
4562236b HW |
59 | |
60 | #include "amd_shared.h" | |
61 | #include "amdgpu_dm_irq.h" | |
62 | #include "dm_helpers.h" | |
e7b07cee | 63 | #include "amdgpu_dm_mst_types.h" |
dc38fd9d DF |
64 | #if defined(CONFIG_DEBUG_FS) |
65 | #include "amdgpu_dm_debugfs.h" | |
66 | #endif | |
f4594cd1 | 67 | #include "amdgpu_dm_psr.h" |
4562236b HW |
68 | |
69 | #include "ivsrcid/ivsrcid_vislands30.h" | |
70 | ||
a6276e92 | 71 | #include <linux/backlight.h> |
4562236b HW |
72 | #include <linux/module.h> |
73 | #include <linux/moduleparam.h> | |
e7b07cee | 74 | #include <linux/types.h> |
97028037 | 75 | #include <linux/pm_runtime.h> |
09d21852 | 76 | #include <linux/pci.h> |
a94d5569 | 77 | #include <linux/firmware.h> |
6ce8f316 | 78 | #include <linux/component.h> |
57b9f338 | 79 | #include <linux/dmi.h> |
4562236b | 80 | |
da68386d | 81 | #include <drm/display/drm_dp_mst_helper.h> |
4fc8cb47 | 82 | #include <drm/display/drm_hdmi_helper.h> |
4562236b | 83 | #include <drm/drm_atomic.h> |
674e78ac | 84 | #include <drm/drm_atomic_uapi.h> |
4562236b | 85 | #include <drm/drm_atomic_helper.h> |
90bb087f | 86 | #include <drm/drm_blend.h> |
09d21852 | 87 | #include <drm/drm_fourcc.h> |
e7b07cee | 88 | #include <drm/drm_edid.h> |
09d21852 | 89 | #include <drm/drm_vblank.h> |
6ce8f316 | 90 | #include <drm/drm_audio_component.h> |
047de3f1 | 91 | #include <drm/drm_gem_atomic_helper.h> |
30c63715 | 92 | #include <drm/drm_plane_helper.h> |
4562236b | 93 | |
da11ef83 HG |
94 | #include <acpi/video.h> |
95 | ||
5527cd06 | 96 | #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" |
ff5ef992 | 97 | |
ad941f7a FX |
98 | #include "dcn/dcn_1_0_offset.h" |
99 | #include "dcn/dcn_1_0_sh_mask.h" | |
407e7517 | 100 | #include "soc15_hw_ip.h" |
543036a2 | 101 | #include "soc15_common.h" |
407e7517 | 102 | #include "vega10_ip_offset.h" |
ff5ef992 | 103 | |
543036a2 AP |
104 | #include "gc/gc_11_0_0_offset.h" |
105 | #include "gc/gc_11_0_0_sh_mask.h" | |
106 | ||
e7b07cee | 107 | #include "modules/inc/mod_freesync.h" |
bbf854dc | 108 | #include "modules/power/power_helpers.h" |
e7b07cee | 109 | |
743b9786 NK |
110 | #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" |
111 | MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); | |
79037324 BL |
112 | #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" |
113 | MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); | |
5ce868fc BL |
114 | #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" |
115 | MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); | |
71c0fd92 RL |
116 | #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" |
117 | MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); | |
469989ca RL |
118 | #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" |
119 | MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); | |
2a411205 BL |
120 | #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" |
121 | MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); | |
656fe9b6 AP |
122 | #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" |
123 | MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); | |
1ebcaebd NK |
124 | #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" |
125 | MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); | |
e850f6b1 RL |
126 | #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" |
127 | MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); | |
b5b8ed44 QZ |
128 | #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" |
129 | MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); | |
de7cc1b4 PL |
130 | #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" |
131 | MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); | |
2200eb9e | 132 | |
577359ca AP |
133 | #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" |
134 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); | |
135 | #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" | |
136 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); | |
137 | ||
a94d5569 DF |
138 | #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" |
139 | MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); | |
e7b07cee | 140 | |
5ea23931 RL |
141 | #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" |
142 | MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); | |
143 | ||
8c7aea40 NK |
144 | /* Number of bytes in PSP header for firmware. */ |
145 | #define PSP_HEADER_BYTES 0x100 | |
146 | ||
147 | /* Number of bytes in PSP footer for firmware. */ | |
148 | #define PSP_FOOTER_BYTES 0x100 | |
149 | ||
b8592b48 LL |
150 | /** |
151 | * DOC: overview | |
152 | * | |
153 | * The AMDgpu display manager, **amdgpu_dm** (or even simpler, | |
ec5c0ffa | 154 | * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM |
b8592b48 LL |
155 | * requests into DC requests, and DC responses into DRM responses. |
156 | * | |
157 | * The root control structure is &struct amdgpu_display_manager. | |
158 | */ | |
159 | ||
7578ecda AD |
160 | /* basic init/fini API */ |
161 | static int amdgpu_dm_init(struct amdgpu_device *adev); | |
162 | static void amdgpu_dm_fini(struct amdgpu_device *adev); | |
fe8858bb | 163 | static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); |
7578ecda | 164 | |
0f877894 OV |
165 | static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) |
166 | { | |
167 | switch (link->dpcd_caps.dongle_type) { | |
168 | case DISPLAY_DONGLE_NONE: | |
169 | return DRM_MODE_SUBCONNECTOR_Native; | |
170 | case DISPLAY_DONGLE_DP_VGA_CONVERTER: | |
171 | return DRM_MODE_SUBCONNECTOR_VGA; | |
172 | case DISPLAY_DONGLE_DP_DVI_CONVERTER: | |
173 | case DISPLAY_DONGLE_DP_DVI_DONGLE: | |
174 | return DRM_MODE_SUBCONNECTOR_DVID; | |
175 | case DISPLAY_DONGLE_DP_HDMI_CONVERTER: | |
176 | case DISPLAY_DONGLE_DP_HDMI_DONGLE: | |
177 | return DRM_MODE_SUBCONNECTOR_HDMIA; | |
178 | case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: | |
179 | default: | |
180 | return DRM_MODE_SUBCONNECTOR_Unknown; | |
181 | } | |
182 | } | |
183 | ||
184 | static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) | |
185 | { | |
186 | struct dc_link *link = aconnector->dc_link; | |
187 | struct drm_connector *connector = &aconnector->base; | |
188 | enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; | |
189 | ||
190 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
191 | return; | |
192 | ||
193 | if (aconnector->dc_sink) | |
194 | subconnector = get_subconnector_type(link); | |
195 | ||
196 | drm_object_property_set_value(&connector->base, | |
197 | connector->dev->mode_config.dp_subconnector_property, | |
198 | subconnector); | |
199 | } | |
200 | ||
1f6010a9 DF |
201 | /* |
202 | * initializes drm_device display related structures, based on the information | |
7578ecda AD |
203 | * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, |
204 | * drm_encoder, drm_mode_config | |
205 | * | |
206 | * Returns 0 on success | |
207 | */ | |
208 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); | |
209 | /* removes and deallocates the drm structures, created by the above function */ | |
210 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); | |
211 | ||
7578ecda AD |
212 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
213 | struct amdgpu_dm_connector *amdgpu_dm_connector, | |
ae67558b | 214 | u32 link_index, |
7578ecda AD |
215 | struct amdgpu_encoder *amdgpu_encoder); |
216 | static int amdgpu_dm_encoder_init(struct drm_device *dev, | |
217 | struct amdgpu_encoder *aencoder, | |
218 | uint32_t link_index); | |
219 | ||
220 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); | |
221 | ||
7578ecda AD |
222 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); |
223 | ||
224 | static int amdgpu_dm_atomic_check(struct drm_device *dev, | |
225 | struct drm_atomic_state *state); | |
226 | ||
e27c41d5 | 227 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); |
c40a09e5 | 228 | static void handle_hpd_rx_irq(void *param); |
e27c41d5 | 229 | |
a85ba005 NC |
230 | static bool |
231 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, | |
232 | struct drm_crtc_state *new_crtc_state); | |
4562236b HW |
233 | /* |
234 | * dm_vblank_get_counter | |
235 | * | |
236 | * @brief | |
237 | * Get counter for number of vertical blanks | |
238 | * | |
239 | * @param | |
240 | * struct amdgpu_device *adev - [in] desired amdgpu device | |
241 | * int disp_idx - [in] which CRTC to get the counter from | |
242 | * | |
243 | * @return | |
244 | * Counter for vertical blanks | |
245 | */ | |
246 | static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) | |
247 | { | |
248 | if (crtc >= adev->mode_info.num_crtc) | |
249 | return 0; | |
250 | else { | |
251 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; | |
252 | ||
585d450c | 253 | if (acrtc->dm_irq_params.stream == NULL) { |
0971c40e HW |
254 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", |
255 | crtc); | |
4562236b HW |
256 | return 0; |
257 | } | |
258 | ||
585d450c | 259 | return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); |
4562236b HW |
260 | } |
261 | } | |
262 | ||
263 | static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, | |
3ee6b26b | 264 | u32 *vbl, u32 *position) |
4562236b | 265 | { |
ae67558b | 266 | u32 v_blank_start, v_blank_end, h_position, v_position; |
81c50963 | 267 | |
4562236b HW |
268 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
269 | return -EINVAL; | |
270 | else { | |
271 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; | |
272 | ||
585d450c | 273 | if (acrtc->dm_irq_params.stream == NULL) { |
0971c40e HW |
274 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", |
275 | crtc); | |
4562236b HW |
276 | return 0; |
277 | } | |
278 | ||
81c50963 ST |
279 | /* |
280 | * TODO rework base driver to use values directly. | |
281 | * for now parse it back into reg-format | |
282 | */ | |
585d450c | 283 | dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, |
81c50963 ST |
284 | &v_blank_start, |
285 | &v_blank_end, | |
286 | &h_position, | |
287 | &v_position); | |
288 | ||
e806208d AG |
289 | *position = v_position | (h_position << 16); |
290 | *vbl = v_blank_start | (v_blank_end << 16); | |
4562236b HW |
291 | } |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | static bool dm_is_idle(void *handle) | |
297 | { | |
298 | /* XXX todo */ | |
299 | return true; | |
300 | } | |
301 | ||
302 | static int dm_wait_for_idle(void *handle) | |
303 | { | |
304 | /* XXX todo */ | |
305 | return 0; | |
306 | } | |
307 | ||
308 | static bool dm_check_soft_reset(void *handle) | |
309 | { | |
310 | return false; | |
311 | } | |
312 | ||
313 | static int dm_soft_reset(void *handle) | |
314 | { | |
315 | /* XXX todo */ | |
316 | return 0; | |
317 | } | |
318 | ||
3ee6b26b AD |
319 | static struct amdgpu_crtc * |
320 | get_crtc_by_otg_inst(struct amdgpu_device *adev, | |
321 | int otg_inst) | |
4562236b | 322 | { |
4a580877 | 323 | struct drm_device *dev = adev_to_drm(adev); |
4562236b HW |
324 | struct drm_crtc *crtc; |
325 | struct amdgpu_crtc *amdgpu_crtc; | |
326 | ||
bcd74374 | 327 | if (WARN_ON(otg_inst == -1)) |
4562236b | 328 | return adev->mode_info.crtcs[0]; |
4562236b HW |
329 | |
330 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
331 | amdgpu_crtc = to_amdgpu_crtc(crtc); | |
332 | ||
333 | if (amdgpu_crtc->otg_inst == otg_inst) | |
334 | return amdgpu_crtc; | |
335 | } | |
336 | ||
337 | return NULL; | |
338 | } | |
339 | ||
a85ba005 NC |
340 | static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, |
341 | struct dm_crtc_state *new_state) | |
342 | { | |
343 | if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) | |
344 | return true; | |
6c5e25a0 | 345 | else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) |
a85ba005 NC |
346 | return true; |
347 | else | |
348 | return false; | |
349 | } | |
350 | ||
bb46a6a9 RS |
351 | static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, |
352 | int planes_count) | |
353 | { | |
354 | int i, j; | |
bb46a6a9 | 355 | |
8866d627 JC |
356 | for (i = 0, j = planes_count - 1; i < j; i++, j--) |
357 | swap(array_of_surface_update[i], array_of_surface_update[j]); | |
bb46a6a9 RS |
358 | } |
359 | ||
81f743a0 RS |
360 | /** |
361 | * update_planes_and_stream_adapter() - Send planes to be updated in DC | |
362 | * | |
363 | * DC has a generic way to update planes and stream via | |
364 | * dc_update_planes_and_stream function; however, DM might need some | |
365 | * adjustments and preparation before calling it. This function is a wrapper | |
366 | * for the dc_update_planes_and_stream that does any required configuration | |
367 | * before passing control to DC. | |
21d81681 SS |
368 | * |
369 | * @dc: Display Core control structure | |
370 | * @update_type: specify whether it is FULL/MEDIUM/FAST update | |
371 | * @planes_count: planes count to update | |
372 | * @stream: stream state | |
373 | * @stream_update: stream update | |
374 | * @array_of_surface_update: dc surface update pointer | |
375 | * | |
81f743a0 RS |
376 | */ |
377 | static inline bool update_planes_and_stream_adapter(struct dc *dc, | |
378 | int update_type, | |
379 | int planes_count, | |
380 | struct dc_stream_state *stream, | |
381 | struct dc_stream_update *stream_update, | |
382 | struct dc_surface_update *array_of_surface_update) | |
383 | { | |
bb46a6a9 RS |
384 | reverse_planes_order(array_of_surface_update, planes_count); |
385 | ||
81f743a0 RS |
386 | /* |
387 | * Previous frame finished and HW is ready for optimization. | |
388 | */ | |
389 | if (update_type == UPDATE_TYPE_FAST) | |
390 | dc_post_update_surfaces_to_stream(dc); | |
391 | ||
392 | return dc_update_planes_and_stream(dc, | |
393 | array_of_surface_update, | |
394 | planes_count, | |
395 | stream, | |
396 | stream_update); | |
397 | } | |
398 | ||
b8e8c934 HW |
399 | /** |
400 | * dm_pflip_high_irq() - Handle pageflip interrupt | |
401 | * @interrupt_params: ignored | |
402 | * | |
403 | * Handles the pageflip interrupt by notifying all interested parties | |
404 | * that the pageflip has been completed. | |
405 | */ | |
4562236b HW |
406 | static void dm_pflip_high_irq(void *interrupt_params) |
407 | { | |
4562236b HW |
408 | struct amdgpu_crtc *amdgpu_crtc; |
409 | struct common_irq_params *irq_params = interrupt_params; | |
410 | struct amdgpu_device *adev = irq_params->adev; | |
411 | unsigned long flags; | |
71bbe51a | 412 | struct drm_pending_vblank_event *e; |
ae67558b | 413 | u32 vpos, hpos, v_blank_start, v_blank_end; |
71bbe51a | 414 | bool vrr_active; |
4562236b HW |
415 | |
416 | amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); | |
417 | ||
418 | /* IRQ could occur when in initial stage */ | |
1f6010a9 | 419 | /* TODO work and BO cleanup */ |
4562236b | 420 | if (amdgpu_crtc == NULL) { |
cb2318b7 | 421 | DC_LOG_PFLIP("CRTC is null, returning.\n"); |
4562236b HW |
422 | return; |
423 | } | |
424 | ||
4a580877 | 425 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
4562236b | 426 | |
c82eddf8 SS |
427 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { |
428 | DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", | |
429 | amdgpu_crtc->pflip_status, | |
430 | AMDGPU_FLIP_SUBMITTED, | |
431 | amdgpu_crtc->crtc_id, | |
432 | amdgpu_crtc); | |
4a580877 | 433 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
4562236b HW |
434 | return; |
435 | } | |
436 | ||
71bbe51a MK |
437 | /* page flip completed. */ |
438 | e = amdgpu_crtc->event; | |
439 | amdgpu_crtc->event = NULL; | |
4562236b | 440 | |
bcd74374 | 441 | WARN_ON(!e); |
1159898a | 442 | |
6c5e25a0 | 443 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); |
71bbe51a MK |
444 | |
445 | /* Fixed refresh rate, or VRR scanout position outside front-porch? */ | |
446 | if (!vrr_active || | |
585d450c | 447 | !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, |
71bbe51a MK |
448 | &v_blank_end, &hpos, &vpos) || |
449 | (vpos < v_blank_start)) { | |
450 | /* Update to correct count and vblank timestamp if racing with | |
451 | * vblank irq. This also updates to the correct vblank timestamp | |
452 | * even in VRR mode, as scanout is past the front-porch atm. | |
453 | */ | |
454 | drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); | |
1159898a | 455 | |
71bbe51a MK |
456 | /* Wake up userspace by sending the pageflip event with proper |
457 | * count and timestamp of vblank of flip completion. | |
458 | */ | |
459 | if (e) { | |
460 | drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); | |
461 | ||
462 | /* Event sent, so done with vblank for this flip */ | |
463 | drm_crtc_vblank_put(&amdgpu_crtc->base); | |
464 | } | |
465 | } else if (e) { | |
466 | /* VRR active and inside front-porch: vblank count and | |
467 | * timestamp for pageflip event will only be up to date after | |
468 | * drm_crtc_handle_vblank() has been executed from late vblank | |
469 | * irq handler after start of back-porch (vline 0). We queue the | |
470 | * pageflip event for send-out by drm_crtc_handle_vblank() with | |
471 | * updated timestamp and count, once it runs after us. | |
472 | * | |
473 | * We need to open-code this instead of using the helper | |
474 | * drm_crtc_arm_vblank_event(), as that helper would | |
475 | * call drm_crtc_accurate_vblank_count(), which we must | |
476 | * not call in VRR mode while we are in front-porch! | |
477 | */ | |
478 | ||
479 | /* sequence will be replaced by real count during send-out. */ | |
480 | e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); | |
481 | e->pipe = amdgpu_crtc->crtc_id; | |
482 | ||
4a580877 | 483 | list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); |
71bbe51a MK |
484 | e = NULL; |
485 | } | |
4562236b | 486 | |
fdd1fe57 MK |
487 | /* Keep track of vblank of this flip for flip throttling. We use the |
488 | * cooked hw counter, as that one incremented at start of this vblank | |
489 | * of pageflip completion, so last_flip_vblank is the forbidden count | |
490 | * for queueing new pageflips if vsync + VRR is enabled. | |
491 | */ | |
5d1c59c4 | 492 | amdgpu_crtc->dm_irq_params.last_flip_vblank = |
e3eff4b5 | 493 | amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); |
fdd1fe57 | 494 | |
54f5499a | 495 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; |
4a580877 | 496 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
4562236b | 497 | |
cb2318b7 VL |
498 | DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", |
499 | amdgpu_crtc->crtc_id, amdgpu_crtc, | |
500 | vrr_active, (int) !e); | |
4562236b HW |
501 | } |
502 | ||
d2574c33 MK |
503 | static void dm_vupdate_high_irq(void *interrupt_params) |
504 | { | |
505 | struct common_irq_params *irq_params = interrupt_params; | |
506 | struct amdgpu_device *adev = irq_params->adev; | |
507 | struct amdgpu_crtc *acrtc; | |
47588233 RS |
508 | struct drm_device *drm_dev; |
509 | struct drm_vblank_crtc *vblank; | |
510 | ktime_t frame_duration_ns, previous_timestamp; | |
09aef2c4 | 511 | unsigned long flags; |
585d450c | 512 | int vrr_active; |
d2574c33 MK |
513 | |
514 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); | |
515 | ||
516 | if (acrtc) { | |
6c5e25a0 | 517 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
47588233 RS |
518 | drm_dev = acrtc->base.dev; |
519 | vblank = &drm_dev->vblank[acrtc->base.index]; | |
520 | previous_timestamp = atomic64_read(&irq_params->previous_timestamp); | |
521 | frame_duration_ns = vblank->time - previous_timestamp; | |
522 | ||
523 | if (frame_duration_ns > 0) { | |
524 | trace_amdgpu_refresh_rate_track(acrtc->base.index, | |
525 | frame_duration_ns, | |
526 | ktime_divns(NSEC_PER_SEC, frame_duration_ns)); | |
527 | atomic64_set(&irq_params->previous_timestamp, vblank->time); | |
528 | } | |
d2574c33 | 529 | |
cb2318b7 | 530 | DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n", |
7f2be468 | 531 | acrtc->crtc_id, |
585d450c | 532 | vrr_active); |
d2574c33 MK |
533 | |
534 | /* Core vblank handling is done here after end of front-porch in | |
535 | * vrr mode, as vblank timestamping will give valid results | |
536 | * while now done after front-porch. This will also deliver | |
537 | * page-flip completion events that have been queued to us | |
538 | * if a pageflip happened inside front-porch. | |
539 | */ | |
585d450c | 540 | if (vrr_active) { |
6c5e25a0 | 541 | amdgpu_dm_crtc_handle_vblank(acrtc); |
09aef2c4 MK |
542 | |
543 | /* BTR processing for pre-DCE12 ASICs */ | |
585d450c | 544 | if (acrtc->dm_irq_params.stream && |
09aef2c4 | 545 | adev->family < AMDGPU_FAMILY_AI) { |
4a580877 | 546 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
09aef2c4 MK |
547 | mod_freesync_handle_v_update( |
548 | adev->dm.freesync_module, | |
585d450c AP |
549 | acrtc->dm_irq_params.stream, |
550 | &acrtc->dm_irq_params.vrr_params); | |
09aef2c4 MK |
551 | |
552 | dc_stream_adjust_vmin_vmax( | |
553 | adev->dm.dc, | |
585d450c AP |
554 | acrtc->dm_irq_params.stream, |
555 | &acrtc->dm_irq_params.vrr_params.adjust); | |
4a580877 | 556 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
09aef2c4 MK |
557 | } |
558 | } | |
d2574c33 MK |
559 | } |
560 | } | |
561 | ||
b8e8c934 HW |
562 | /** |
563 | * dm_crtc_high_irq() - Handles CRTC interrupt | |
2346ef47 | 564 | * @interrupt_params: used for determining the CRTC instance |
b8e8c934 HW |
565 | * |
566 | * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK | |
567 | * event handler. | |
568 | */ | |
4562236b HW |
569 | static void dm_crtc_high_irq(void *interrupt_params) |
570 | { | |
571 | struct common_irq_params *irq_params = interrupt_params; | |
572 | struct amdgpu_device *adev = irq_params->adev; | |
4562236b | 573 | struct amdgpu_crtc *acrtc; |
09aef2c4 | 574 | unsigned long flags; |
585d450c | 575 | int vrr_active; |
4562236b | 576 | |
b57de80a | 577 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); |
16f17eda LL |
578 | if (!acrtc) |
579 | return; | |
580 | ||
6c5e25a0 | 581 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
16f17eda | 582 | |
cb2318b7 | 583 | DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, |
585d450c | 584 | vrr_active, acrtc->dm_irq_params.active_planes); |
16f17eda | 585 | |
2346ef47 NK |
586 | /** |
587 | * Core vblank handling at start of front-porch is only possible | |
588 | * in non-vrr mode, as only there vblank timestamping will give | |
589 | * valid results while done in front-porch. Otherwise defer it | |
590 | * to dm_vupdate_high_irq after end of front-porch. | |
591 | */ | |
585d450c | 592 | if (!vrr_active) |
6c5e25a0 | 593 | amdgpu_dm_crtc_handle_vblank(acrtc); |
2346ef47 NK |
594 | |
595 | /** | |
596 | * Following stuff must happen at start of vblank, for crc | |
597 | * computation and below-the-range btr support in vrr mode. | |
598 | */ | |
16f17eda | 599 | amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); |
2346ef47 NK |
600 | |
601 | /* BTR updates need to happen before VUPDATE on Vega and above. */ | |
602 | if (adev->family < AMDGPU_FAMILY_AI) | |
603 | return; | |
16f17eda | 604 | |
4a580877 | 605 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
16f17eda | 606 | |
585d450c AP |
607 | if (acrtc->dm_irq_params.stream && |
608 | acrtc->dm_irq_params.vrr_params.supported && | |
609 | acrtc->dm_irq_params.freesync_config.state == | |
610 | VRR_STATE_ACTIVE_VARIABLE) { | |
2346ef47 | 611 | mod_freesync_handle_v_update(adev->dm.freesync_module, |
585d450c AP |
612 | acrtc->dm_irq_params.stream, |
613 | &acrtc->dm_irq_params.vrr_params); | |
16f17eda | 614 | |
585d450c AP |
615 | dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, |
616 | &acrtc->dm_irq_params.vrr_params.adjust); | |
16f17eda LL |
617 | } |
618 | ||
2b5aed9a MK |
619 | /* |
620 | * If there aren't any active_planes then DCH HUBP may be clock-gated. | |
621 | * In that case, pageflip completion interrupts won't fire and pageflip | |
622 | * completion events won't get delivered. Prevent this by sending | |
623 | * pending pageflip events from here if a flip is still pending. | |
624 | * | |
625 | * If any planes are enabled, use dm_pflip_high_irq() instead, to | |
626 | * avoid race conditions between flip programming and completion, | |
627 | * which could cause too early flip completion events. | |
628 | */ | |
2346ef47 NK |
629 | if (adev->family >= AMDGPU_FAMILY_RV && |
630 | acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && | |
585d450c | 631 | acrtc->dm_irq_params.active_planes == 0) { |
16f17eda LL |
632 | if (acrtc->event) { |
633 | drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); | |
634 | acrtc->event = NULL; | |
635 | drm_crtc_vblank_put(&acrtc->base); | |
636 | } | |
637 | acrtc->pflip_status = AMDGPU_FLIP_NONE; | |
638 | } | |
639 | ||
4a580877 | 640 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
16f17eda LL |
641 | } |
642 | ||
9e1178ef | 643 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
86bc2219 WL |
644 | /** |
645 | * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for | |
646 | * DCN generation ASICs | |
48e01bf4 | 647 | * @interrupt_params: interrupt parameters |
86bc2219 WL |
648 | * |
649 | * Used to set crc window/read out crc value at vertical line 0 position | |
650 | */ | |
86bc2219 WL |
651 | static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) |
652 | { | |
653 | struct common_irq_params *irq_params = interrupt_params; | |
654 | struct amdgpu_device *adev = irq_params->adev; | |
655 | struct amdgpu_crtc *acrtc; | |
656 | ||
657 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); | |
658 | ||
659 | if (!acrtc) | |
660 | return; | |
661 | ||
662 | amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); | |
663 | } | |
433e5dec | 664 | #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ |
86bc2219 | 665 | |
e27c41d5 | 666 | /** |
03f2abb0 | 667 | * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. |
e27c41d5 JS |
668 | * @adev: amdgpu_device pointer |
669 | * @notify: dmub notification structure | |
670 | * | |
671 | * Dmub AUX or SET_CONFIG command completion processing callback | |
672 | * Copies dmub notification to DM which is to be read by AUX command. | |
673 | * issuing thread and also signals the event to wake up the thread. | |
674 | */ | |
240e6d25 IB |
675 | static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, |
676 | struct dmub_notification *notify) | |
e27c41d5 JS |
677 | { |
678 | if (adev->dm.dmub_notify) | |
679 | memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); | |
680 | if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) | |
681 | complete(&adev->dm.dmub_aux_transfer_done); | |
682 | } | |
683 | ||
684 | /** | |
685 | * dmub_hpd_callback - DMUB HPD interrupt processing callback. | |
686 | * @adev: amdgpu_device pointer | |
687 | * @notify: dmub notification structure | |
688 | * | |
689 | * Dmub Hpd interrupt processing callback. Gets displayindex through the | |
690 | * ink index and calls helper to do the processing. | |
691 | */ | |
240e6d25 IB |
692 | static void dmub_hpd_callback(struct amdgpu_device *adev, |
693 | struct dmub_notification *notify) | |
e27c41d5 JS |
694 | { |
695 | struct amdgpu_dm_connector *aconnector; | |
f6e03f80 | 696 | struct amdgpu_dm_connector *hpd_aconnector = NULL; |
e27c41d5 JS |
697 | struct drm_connector *connector; |
698 | struct drm_connector_list_iter iter; | |
699 | struct dc_link *link; | |
ae67558b | 700 | u8 link_index = 0; |
978ffac8 | 701 | struct drm_device *dev; |
e27c41d5 JS |
702 | |
703 | if (adev == NULL) | |
704 | return; | |
705 | ||
706 | if (notify == NULL) { | |
707 | DRM_ERROR("DMUB HPD callback notification was NULL"); | |
708 | return; | |
709 | } | |
710 | ||
711 | if (notify->link_index > adev->dm.dc->link_count) { | |
712 | DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); | |
713 | return; | |
714 | } | |
715 | ||
e27c41d5 | 716 | link_index = notify->link_index; |
e27c41d5 | 717 | link = adev->dm.dc->links[link_index]; |
978ffac8 | 718 | dev = adev->dm.ddev; |
e27c41d5 JS |
719 | |
720 | drm_connector_list_iter_begin(dev, &iter); | |
721 | drm_for_each_connector_iter(connector, &iter) { | |
722 | aconnector = to_amdgpu_dm_connector(connector); | |
723 | if (link && aconnector->dc_link == link) { | |
c416a9e4 SW |
724 | if (notify->type == DMUB_NOTIFICATION_HPD) |
725 | DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); | |
726 | else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) | |
727 | DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); | |
728 | else | |
729 | DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", | |
730 | notify->type, link_index); | |
731 | ||
f6e03f80 | 732 | hpd_aconnector = aconnector; |
e27c41d5 JS |
733 | break; |
734 | } | |
735 | } | |
736 | drm_connector_list_iter_end(&iter); | |
e27c41d5 | 737 | |
c40a09e5 NK |
738 | if (hpd_aconnector) { |
739 | if (notify->type == DMUB_NOTIFICATION_HPD) | |
740 | handle_hpd_irq_helper(hpd_aconnector); | |
741 | else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) | |
742 | handle_hpd_rx_irq(hpd_aconnector); | |
743 | } | |
e27c41d5 JS |
744 | } |
745 | ||
746 | /** | |
747 | * register_dmub_notify_callback - Sets callback for DMUB notify | |
748 | * @adev: amdgpu_device pointer | |
749 | * @type: Type of dmub notification | |
750 | * @callback: Dmub interrupt callback function | |
751 | * @dmub_int_thread_offload: offload indicator | |
752 | * | |
753 | * API to register a dmub callback handler for a dmub notification | |
754 | * Also sets indicator whether callback processing to be offloaded. | |
755 | * to dmub interrupt handling thread | |
756 | * Return: true if successfully registered, false if there is existing registration | |
757 | */ | |
240e6d25 IB |
758 | static bool register_dmub_notify_callback(struct amdgpu_device *adev, |
759 | enum dmub_notification_type type, | |
760 | dmub_notify_interrupt_callback_t callback, | |
761 | bool dmub_int_thread_offload) | |
e27c41d5 JS |
762 | { |
763 | if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { | |
764 | adev->dm.dmub_callback[type] = callback; | |
765 | adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; | |
766 | } else | |
767 | return false; | |
768 | ||
769 | return true; | |
770 | } | |
771 | ||
772 | static void dm_handle_hpd_work(struct work_struct *work) | |
773 | { | |
774 | struct dmub_hpd_work *dmub_hpd_wrk; | |
775 | ||
776 | dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); | |
777 | ||
778 | if (!dmub_hpd_wrk->dmub_notify) { | |
779 | DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); | |
780 | return; | |
781 | } | |
782 | ||
783 | if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { | |
784 | dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, | |
785 | dmub_hpd_wrk->dmub_notify); | |
786 | } | |
094b21c1 JS |
787 | |
788 | kfree(dmub_hpd_wrk->dmub_notify); | |
e27c41d5 JS |
789 | kfree(dmub_hpd_wrk); |
790 | ||
791 | } | |
792 | ||
e25515e2 | 793 | #define DMUB_TRACE_MAX_READ 64 |
81927e28 JS |
794 | /** |
795 | * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt | |
796 | * @interrupt_params: used for determining the Outbox instance | |
797 | * | |
798 | * Handles the Outbox Interrupt | |
799 | * event handler. | |
800 | */ | |
81927e28 JS |
801 | static void dm_dmub_outbox1_low_irq(void *interrupt_params) |
802 | { | |
803 | struct dmub_notification notify; | |
804 | struct common_irq_params *irq_params = interrupt_params; | |
805 | struct amdgpu_device *adev = irq_params->adev; | |
806 | struct amdgpu_display_manager *dm = &adev->dm; | |
807 | struct dmcub_trace_buf_entry entry = { 0 }; | |
ae67558b | 808 | u32 count = 0; |
e27c41d5 | 809 | struct dmub_hpd_work *dmub_hpd_wrk; |
f6e03f80 | 810 | struct dc_link *plink = NULL; |
81927e28 | 811 | |
f6e03f80 JS |
812 | if (dc_enable_dmub_notifications(adev->dm.dc) && |
813 | irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { | |
e27c41d5 | 814 | |
f6e03f80 JS |
815 | do { |
816 | dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); | |
a35faec3 | 817 | if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { |
f6e03f80 JS |
818 | DRM_ERROR("DM: notify type %d invalid!", notify.type); |
819 | continue; | |
820 | } | |
c40a09e5 NK |
821 | if (!dm->dmub_callback[notify.type]) { |
822 | DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); | |
823 | continue; | |
824 | } | |
f6e03f80 | 825 | if (dm->dmub_thread_offload[notify.type] == true) { |
094b21c1 JS |
826 | dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); |
827 | if (!dmub_hpd_wrk) { | |
828 | DRM_ERROR("Failed to allocate dmub_hpd_wrk"); | |
829 | return; | |
830 | } | |
0e909e4f CJ |
831 | dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), |
832 | GFP_ATOMIC); | |
094b21c1 JS |
833 | if (!dmub_hpd_wrk->dmub_notify) { |
834 | kfree(dmub_hpd_wrk); | |
835 | DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); | |
836 | return; | |
837 | } | |
838 | INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); | |
f6e03f80 JS |
839 | dmub_hpd_wrk->adev = adev; |
840 | if (notify.type == DMUB_NOTIFICATION_HPD) { | |
841 | plink = adev->dm.dc->links[notify.link_index]; | |
842 | if (plink) { | |
843 | plink->hpd_status = | |
b97788e5 | 844 | notify.hpd_status == DP_HPD_PLUG; |
f6e03f80 | 845 | } |
e27c41d5 | 846 | } |
f6e03f80 JS |
847 | queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); |
848 | } else { | |
849 | dm->dmub_callback[notify.type](adev, ¬ify); | |
850 | } | |
851 | } while (notify.pending_notification); | |
81927e28 JS |
852 | } |
853 | ||
854 | ||
855 | do { | |
856 | if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { | |
857 | trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, | |
858 | entry.param0, entry.param1); | |
859 | ||
860 | DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", | |
861 | entry.trace_code, entry.tick_count, entry.param0, entry.param1); | |
862 | } else | |
863 | break; | |
864 | ||
865 | count++; | |
866 | ||
867 | } while (count <= DMUB_TRACE_MAX_READ); | |
868 | ||
f6e03f80 JS |
869 | if (count > DMUB_TRACE_MAX_READ) |
870 | DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); | |
81927e28 | 871 | } |
86bc2219 | 872 | |
4562236b HW |
873 | static int dm_set_clockgating_state(void *handle, |
874 | enum amd_clockgating_state state) | |
875 | { | |
876 | return 0; | |
877 | } | |
878 | ||
879 | static int dm_set_powergating_state(void *handle, | |
880 | enum amd_powergating_state state) | |
881 | { | |
882 | return 0; | |
883 | } | |
884 | ||
885 | /* Prototypes of private functions */ | |
c82eddf8 | 886 | static int dm_early_init(void *handle); |
4562236b | 887 | |
a32e24b4 | 888 | /* Allocate memory for FBC compressed data */ |
3e332d3a | 889 | static void amdgpu_dm_fbc_init(struct drm_connector *connector) |
a32e24b4 | 890 | { |
3e332d3a | 891 | struct drm_device *dev = connector->dev; |
1348969a | 892 | struct amdgpu_device *adev = drm_to_adev(dev); |
4d154b85 | 893 | struct dm_compressor_info *compressor = &adev->dm.compressor; |
3e332d3a RL |
894 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); |
895 | struct drm_display_mode *mode; | |
42e67c3b RL |
896 | unsigned long max_size = 0; |
897 | ||
898 | if (adev->dm.dc->fbc_compressor == NULL) | |
899 | return; | |
a32e24b4 | 900 | |
3e332d3a | 901 | if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) |
42e67c3b RL |
902 | return; |
903 | ||
3e332d3a RL |
904 | if (compressor->bo_ptr) |
905 | return; | |
42e67c3b | 906 | |
42e67c3b | 907 | |
3e332d3a RL |
908 | list_for_each_entry(mode, &connector->modes, head) { |
909 | if (max_size < mode->htotal * mode->vtotal) | |
910 | max_size = mode->htotal * mode->vtotal; | |
42e67c3b RL |
911 | } |
912 | ||
913 | if (max_size) { | |
914 | int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, | |
0e5916ff | 915 | AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, |
42e67c3b | 916 | &compressor->gpu_addr, &compressor->cpu_addr); |
a32e24b4 RL |
917 | |
918 | if (r) | |
42e67c3b RL |
919 | DRM_ERROR("DM: Failed to initialize FBC\n"); |
920 | else { | |
921 | adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; | |
922 | DRM_INFO("DM: FBC alloc %lu\n", max_size*4); | |
923 | } | |
924 | ||
a32e24b4 RL |
925 | } |
926 | ||
927 | } | |
a32e24b4 | 928 | |
6ce8f316 NK |
929 | static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, |
930 | int pipe, bool *enabled, | |
931 | unsigned char *buf, int max_bytes) | |
932 | { | |
933 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 934 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
935 | struct drm_connector *connector; |
936 | struct drm_connector_list_iter conn_iter; | |
937 | struct amdgpu_dm_connector *aconnector; | |
938 | int ret = 0; | |
939 | ||
940 | *enabled = false; | |
941 | ||
942 | mutex_lock(&adev->dm.audio_lock); | |
943 | ||
944 | drm_connector_list_iter_begin(dev, &conn_iter); | |
945 | drm_for_each_connector_iter(connector, &conn_iter) { | |
946 | aconnector = to_amdgpu_dm_connector(connector); | |
947 | if (aconnector->audio_inst != port) | |
948 | continue; | |
949 | ||
950 | *enabled = true; | |
951 | ret = drm_eld_size(connector->eld); | |
952 | memcpy(buf, connector->eld, min(max_bytes, ret)); | |
953 | ||
954 | break; | |
955 | } | |
956 | drm_connector_list_iter_end(&conn_iter); | |
957 | ||
958 | mutex_unlock(&adev->dm.audio_lock); | |
959 | ||
960 | DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); | |
961 | ||
962 | return ret; | |
963 | } | |
964 | ||
965 | static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { | |
966 | .get_eld = amdgpu_dm_audio_component_get_eld, | |
967 | }; | |
968 | ||
969 | static int amdgpu_dm_audio_component_bind(struct device *kdev, | |
970 | struct device *hda_kdev, void *data) | |
971 | { | |
972 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 973 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
974 | struct drm_audio_component *acomp = data; |
975 | ||
976 | acomp->ops = &amdgpu_dm_audio_component_ops; | |
977 | acomp->dev = kdev; | |
978 | adev->dm.audio_component = acomp; | |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
983 | static void amdgpu_dm_audio_component_unbind(struct device *kdev, | |
984 | struct device *hda_kdev, void *data) | |
985 | { | |
986 | struct drm_device *dev = dev_get_drvdata(kdev); | |
1348969a | 987 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
988 | struct drm_audio_component *acomp = data; |
989 | ||
990 | acomp->ops = NULL; | |
991 | acomp->dev = NULL; | |
992 | adev->dm.audio_component = NULL; | |
993 | } | |
994 | ||
995 | static const struct component_ops amdgpu_dm_audio_component_bind_ops = { | |
996 | .bind = amdgpu_dm_audio_component_bind, | |
997 | .unbind = amdgpu_dm_audio_component_unbind, | |
998 | }; | |
999 | ||
1000 | static int amdgpu_dm_audio_init(struct amdgpu_device *adev) | |
1001 | { | |
1002 | int i, ret; | |
1003 | ||
1004 | if (!amdgpu_audio) | |
1005 | return 0; | |
1006 | ||
1007 | adev->mode_info.audio.enabled = true; | |
1008 | ||
1009 | adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; | |
1010 | ||
1011 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
1012 | adev->mode_info.audio.pin[i].channels = -1; | |
1013 | adev->mode_info.audio.pin[i].rate = -1; | |
1014 | adev->mode_info.audio.pin[i].bits_per_sample = -1; | |
1015 | adev->mode_info.audio.pin[i].status_bits = 0; | |
1016 | adev->mode_info.audio.pin[i].category_code = 0; | |
1017 | adev->mode_info.audio.pin[i].connected = false; | |
1018 | adev->mode_info.audio.pin[i].id = | |
1019 | adev->dm.dc->res_pool->audios[i]->inst; | |
1020 | adev->mode_info.audio.pin[i].offset = 0; | |
1021 | } | |
1022 | ||
1023 | ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); | |
1024 | if (ret < 0) | |
1025 | return ret; | |
1026 | ||
1027 | adev->dm.audio_registered = true; | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
1032 | static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) | |
1033 | { | |
1034 | if (!amdgpu_audio) | |
1035 | return; | |
1036 | ||
1037 | if (!adev->mode_info.audio.enabled) | |
1038 | return; | |
1039 | ||
1040 | if (adev->dm.audio_registered) { | |
1041 | component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); | |
1042 | adev->dm.audio_registered = false; | |
1043 | } | |
1044 | ||
1045 | /* TODO: Disable audio? */ | |
1046 | ||
1047 | adev->mode_info.audio.enabled = false; | |
1048 | } | |
1049 | ||
dfd84d90 | 1050 | static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) |
6ce8f316 NK |
1051 | { |
1052 | struct drm_audio_component *acomp = adev->dm.audio_component; | |
1053 | ||
1054 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { | |
1055 | DRM_DEBUG_KMS("Notify ELD: %d\n", pin); | |
1056 | ||
1057 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, | |
1058 | pin, -1); | |
1059 | } | |
1060 | } | |
1061 | ||
743b9786 NK |
1062 | static int dm_dmub_hw_init(struct amdgpu_device *adev) |
1063 | { | |
743b9786 NK |
1064 | const struct dmcub_firmware_header_v1_0 *hdr; |
1065 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; | |
8c7aea40 | 1066 | struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; |
743b9786 NK |
1067 | const struct firmware *dmub_fw = adev->dm.dmub_fw; |
1068 | struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; | |
1069 | struct abm *abm = adev->dm.dc->res_pool->abm; | |
743b9786 NK |
1070 | struct dmub_srv_hw_params hw_params; |
1071 | enum dmub_status status; | |
1072 | const unsigned char *fw_inst_const, *fw_bss_data; | |
ae67558b | 1073 | u32 i, fw_inst_const_size, fw_bss_data_size; |
743b9786 NK |
1074 | bool has_hw_support; |
1075 | ||
1076 | if (!dmub_srv) | |
1077 | /* DMUB isn't supported on the ASIC. */ | |
1078 | return 0; | |
1079 | ||
8c7aea40 NK |
1080 | if (!fb_info) { |
1081 | DRM_ERROR("No framebuffer info for DMUB service.\n"); | |
1082 | return -EINVAL; | |
1083 | } | |
1084 | ||
743b9786 NK |
1085 | if (!dmub_fw) { |
1086 | /* Firmware required for DMUB support. */ | |
1087 | DRM_ERROR("No firmware provided for DMUB.\n"); | |
1088 | return -EINVAL; | |
1089 | } | |
1090 | ||
1091 | status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); | |
1092 | if (status != DMUB_STATUS_OK) { | |
1093 | DRM_ERROR("Error checking HW support for DMUB: %d\n", status); | |
1094 | return -EINVAL; | |
1095 | } | |
1096 | ||
1097 | if (!has_hw_support) { | |
1098 | DRM_INFO("DMUB unsupported on ASIC\n"); | |
1099 | return 0; | |
1100 | } | |
1101 | ||
47e62dbd NK |
1102 | /* Reset DMCUB if it was previously running - before we overwrite its memory. */ |
1103 | status = dmub_srv_hw_reset(dmub_srv); | |
1104 | if (status != DMUB_STATUS_OK) | |
1105 | DRM_WARN("Error resetting DMUB HW: %d\n", status); | |
1106 | ||
743b9786 NK |
1107 | hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; |
1108 | ||
743b9786 NK |
1109 | fw_inst_const = dmub_fw->data + |
1110 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
8c7aea40 | 1111 | PSP_HEADER_BYTES; |
743b9786 NK |
1112 | |
1113 | fw_bss_data = dmub_fw->data + | |
1114 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
1115 | le32_to_cpu(hdr->inst_const_bytes); | |
1116 | ||
1117 | /* Copy firmware and bios info into FB memory. */ | |
8c7aea40 NK |
1118 | fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - |
1119 | PSP_HEADER_BYTES - PSP_FOOTER_BYTES; | |
1120 | ||
1121 | fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); | |
1122 | ||
ddde28a5 HW |
1123 | /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, |
1124 | * amdgpu_ucode_init_single_fw will load dmub firmware | |
1125 | * fw_inst_const part to cw0; otherwise, the firmware back door load | |
1126 | * will be done by dm_dmub_hw_init | |
1127 | */ | |
1128 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
1129 | memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, | |
1130 | fw_inst_const_size); | |
1131 | } | |
1132 | ||
a576b345 NK |
1133 | if (fw_bss_data_size) |
1134 | memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, | |
1135 | fw_bss_data, fw_bss_data_size); | |
ddde28a5 HW |
1136 | |
1137 | /* Copy firmware bios info into FB memory. */ | |
8c7aea40 NK |
1138 | memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, |
1139 | adev->bios_size); | |
1140 | ||
1141 | /* Reset regions that need to be reset. */ | |
1142 | memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, | |
1143 | fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); | |
1144 | ||
1145 | memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, | |
1146 | fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); | |
1147 | ||
1148 | memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, | |
1149 | fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); | |
743b9786 NK |
1150 | |
1151 | /* Initialize hardware. */ | |
1152 | memset(&hw_params, 0, sizeof(hw_params)); | |
1153 | hw_params.fb_base = adev->gmc.fb_start; | |
949933b0 | 1154 | hw_params.fb_offset = adev->vm_manager.vram_base_offset; |
743b9786 | 1155 | |
31a7f4bb HW |
1156 | /* backdoor load firmware and trigger dmub running */ |
1157 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) | |
1158 | hw_params.load_inst_const = true; | |
1159 | ||
743b9786 NK |
1160 | if (dmcu) |
1161 | hw_params.psp_version = dmcu->psp_version; | |
1162 | ||
8c7aea40 NK |
1163 | for (i = 0; i < fb_info->num_fb; ++i) |
1164 | hw_params.fb[i] = &fb_info->fb[i]; | |
743b9786 | 1165 | |
3b36f50d | 1166 | switch (adev->ip_versions[DCE_HWIP][0]) { |
f6aa84b8 RL |
1167 | case IP_VERSION(3, 1, 3): |
1168 | case IP_VERSION(3, 1, 4): | |
3b36f50d | 1169 | hw_params.dpia_supported = true; |
7367540b | 1170 | hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; |
5b109397 JS |
1171 | break; |
1172 | default: | |
1173 | break; | |
1174 | } | |
1175 | ||
743b9786 NK |
1176 | status = dmub_srv_hw_init(dmub_srv, &hw_params); |
1177 | if (status != DMUB_STATUS_OK) { | |
1178 | DRM_ERROR("Error initializing DMUB HW: %d\n", status); | |
1179 | return -EINVAL; | |
1180 | } | |
1181 | ||
1182 | /* Wait for firmware load to finish. */ | |
1183 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); | |
1184 | if (status != DMUB_STATUS_OK) | |
1185 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); | |
1186 | ||
1187 | /* Init DMCU and ABM if available. */ | |
1188 | if (dmcu && abm) { | |
1189 | dmcu->funcs->dmcu_init(dmcu); | |
1190 | abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); | |
1191 | } | |
1192 | ||
051b7887 RL |
1193 | if (!adev->dm.dc->ctx->dmub_srv) |
1194 | adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); | |
9a71c7d3 NK |
1195 | if (!adev->dm.dc->ctx->dmub_srv) { |
1196 | DRM_ERROR("Couldn't allocate DC DMUB server!\n"); | |
1197 | return -ENOMEM; | |
1198 | } | |
1199 | ||
743b9786 NK |
1200 | DRM_INFO("DMUB hardware initialized: version=0x%08X\n", |
1201 | adev->dm.dmcub_fw_version); | |
1202 | ||
1203 | return 0; | |
1204 | } | |
1205 | ||
79d6b935 NK |
1206 | static void dm_dmub_hw_resume(struct amdgpu_device *adev) |
1207 | { | |
1208 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; | |
1209 | enum dmub_status status; | |
1210 | bool init; | |
1211 | ||
1212 | if (!dmub_srv) { | |
1213 | /* DMUB isn't supported on the ASIC. */ | |
1214 | return; | |
1215 | } | |
1216 | ||
1217 | status = dmub_srv_is_hw_init(dmub_srv, &init); | |
1218 | if (status != DMUB_STATUS_OK) | |
1219 | DRM_WARN("DMUB hardware init check failed: %d\n", status); | |
1220 | ||
1221 | if (status == DMUB_STATUS_OK && init) { | |
1222 | /* Wait for firmware load to finish. */ | |
1223 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); | |
1224 | if (status != DMUB_STATUS_OK) | |
1225 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); | |
1226 | } else { | |
1227 | /* Perform the full hardware initialization. */ | |
1228 | dm_dmub_hw_init(adev); | |
1229 | } | |
1230 | } | |
1231 | ||
c0fb85ae | 1232 | static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) |
c44a22b3 | 1233 | { |
ae67558b SS |
1234 | u64 pt_base; |
1235 | u32 logical_addr_low; | |
1236 | u32 logical_addr_high; | |
1237 | u32 agp_base, agp_bot, agp_top; | |
c0fb85ae | 1238 | PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; |
c44a22b3 | 1239 | |
a0f884f5 NK |
1240 | memset(pa_config, 0, sizeof(*pa_config)); |
1241 | ||
c0fb85ae YZ |
1242 | agp_base = 0; |
1243 | agp_bot = adev->gmc.agp_start >> 24; | |
1244 | agp_top = adev->gmc.agp_end >> 24; | |
c44a22b3 | 1245 | |
0294868f AD |
1246 | /* AGP aperture is disabled */ |
1247 | if (agp_bot == agp_top) { | |
4d2c6e89 | 1248 | logical_addr_low = adev->gmc.fb_start >> 18; |
0294868f AD |
1249 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1250 | /* | |
1251 | * Raven2 has a HW issue that it is unable to use the vram which | |
1252 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the | |
1253 | * workaround that increase system aperture high address (add 1) | |
1254 | * to get rid of the VM fault and hardware hang. | |
1255 | */ | |
1256 | logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; | |
1257 | else | |
4d2c6e89 | 1258 | logical_addr_high = adev->gmc.fb_end >> 18; |
0294868f | 1259 | } else { |
4d2c6e89 | 1260 | logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; |
0294868f AD |
1261 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
1262 | /* | |
1263 | * Raven2 has a HW issue that it is unable to use the vram which | |
1264 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the | |
1265 | * workaround that increase system aperture high address (add 1) | |
1266 | * to get rid of the VM fault and hardware hang. | |
1267 | */ | |
1268 | logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); | |
1269 | else | |
1270 | logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; | |
1271 | } | |
1272 | ||
1273 | pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); | |
c44a22b3 | 1274 | |
c0fb85ae YZ |
1275 | page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; |
1276 | page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); | |
1277 | page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; | |
1278 | page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); | |
1279 | page_table_base.high_part = upper_32_bits(pt_base) & 0xF; | |
1280 | page_table_base.low_part = lower_32_bits(pt_base); | |
c44a22b3 | 1281 | |
c0fb85ae YZ |
1282 | pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; |
1283 | pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; | |
1284 | ||
c82eddf8 | 1285 | pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; |
c0fb85ae YZ |
1286 | pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; |
1287 | pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; | |
1288 | ||
1289 | pa_config->system_aperture.fb_base = adev->gmc.fb_start; | |
949933b0 | 1290 | pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; |
c0fb85ae YZ |
1291 | pa_config->system_aperture.fb_top = adev->gmc.fb_end; |
1292 | ||
1293 | pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; | |
1294 | pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; | |
1295 | pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; | |
1296 | ||
40e9f3f0 | 1297 | pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; |
c44a22b3 | 1298 | |
c44a22b3 | 1299 | } |
cae5c1ab | 1300 | |
028c4ccf QZ |
1301 | static void force_connector_state( |
1302 | struct amdgpu_dm_connector *aconnector, | |
1303 | enum drm_connector_force force_state) | |
1304 | { | |
1305 | struct drm_connector *connector = &aconnector->base; | |
1306 | ||
1307 | mutex_lock(&connector->dev->mode_config.mutex); | |
1308 | aconnector->base.force = force_state; | |
1309 | mutex_unlock(&connector->dev->mode_config.mutex); | |
1310 | ||
1311 | mutex_lock(&aconnector->hpd_lock); | |
1312 | drm_kms_helper_connector_hotplug_event(connector); | |
1313 | mutex_unlock(&aconnector->hpd_lock); | |
1314 | } | |
1315 | ||
8e794421 WL |
1316 | static void dm_handle_hpd_rx_offload_work(struct work_struct *work) |
1317 | { | |
1318 | struct hpd_rx_irq_offload_work *offload_work; | |
1319 | struct amdgpu_dm_connector *aconnector; | |
1320 | struct dc_link *dc_link; | |
1321 | struct amdgpu_device *adev; | |
1322 | enum dc_connection_type new_connection_type = dc_connection_none; | |
1323 | unsigned long flags; | |
028c4ccf QZ |
1324 | union test_response test_response; |
1325 | ||
1326 | memset(&test_response, 0, sizeof(test_response)); | |
8e794421 WL |
1327 | |
1328 | offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); | |
1329 | aconnector = offload_work->offload_wq->aconnector; | |
1330 | ||
1331 | if (!aconnector) { | |
1332 | DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); | |
1333 | goto skip; | |
1334 | } | |
1335 | ||
1336 | adev = drm_to_adev(aconnector->base.dev); | |
1337 | dc_link = aconnector->dc_link; | |
1338 | ||
1339 | mutex_lock(&aconnector->hpd_lock); | |
54618888 | 1340 | if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) |
8e794421 WL |
1341 | DRM_ERROR("KMS: Failed to detect connector\n"); |
1342 | mutex_unlock(&aconnector->hpd_lock); | |
1343 | ||
1344 | if (new_connection_type == dc_connection_none) | |
1345 | goto skip; | |
1346 | ||
1347 | if (amdgpu_in_reset(adev)) | |
1348 | goto skip; | |
1349 | ||
1350 | mutex_lock(&adev->dm.dc_lock); | |
028c4ccf | 1351 | if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { |
8e794421 | 1352 | dc_link_dp_handle_automated_test(dc_link); |
028c4ccf QZ |
1353 | |
1354 | if (aconnector->timing_changed) { | |
1355 | /* force connector disconnect and reconnect */ | |
1356 | force_connector_state(aconnector, DRM_FORCE_OFF); | |
1357 | msleep(100); | |
1358 | force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); | |
1359 | } | |
1360 | ||
1361 | test_response.bits.ACK = 1; | |
1362 | ||
1363 | core_link_write_dpcd( | |
1364 | dc_link, | |
1365 | DP_TEST_RESPONSE, | |
1366 | &test_response.raw, | |
1367 | sizeof(test_response)); | |
c82eddf8 | 1368 | } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && |
c5a31f17 | 1369 | dc_link_check_link_loss_status(dc_link, &offload_work->data) && |
8e794421 | 1370 | dc_link_dp_allow_hpd_rx_irq(dc_link)) { |
e322843e HW |
1371 | /* offload_work->data is from handle_hpd_rx_irq-> |
1372 | * schedule_hpd_rx_offload_work.this is defer handle | |
1373 | * for hpd short pulse. upon here, link status may be | |
1374 | * changed, need get latest link status from dpcd | |
1375 | * registers. if link status is good, skip run link | |
1376 | * training again. | |
1377 | */ | |
1378 | union hpd_irq_data irq_data; | |
1379 | ||
1380 | memset(&irq_data, 0, sizeof(irq_data)); | |
1381 | ||
1382 | /* before dc_link_dp_handle_link_loss, allow new link lost handle | |
1383 | * request be added to work queue if link lost at end of dc_link_ | |
1384 | * dp_handle_link_loss | |
1385 | */ | |
8e794421 WL |
1386 | spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); |
1387 | offload_work->offload_wq->is_handling_link_loss = false; | |
1388 | spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); | |
e322843e | 1389 | |
54618888 | 1390 | if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && |
e322843e HW |
1391 | dc_link_check_link_loss_status(dc_link, &irq_data)) |
1392 | dc_link_dp_handle_link_loss(dc_link); | |
8e794421 WL |
1393 | } |
1394 | mutex_unlock(&adev->dm.dc_lock); | |
1395 | ||
1396 | skip: | |
1397 | kfree(offload_work); | |
1398 | ||
1399 | } | |
1400 | ||
1401 | static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) | |
1402 | { | |
1403 | int max_caps = dc->caps.max_links; | |
1404 | int i = 0; | |
1405 | struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; | |
1406 | ||
1407 | hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); | |
1408 | ||
1409 | if (!hpd_rx_offload_wq) | |
1410 | return NULL; | |
1411 | ||
1412 | ||
1413 | for (i = 0; i < max_caps; i++) { | |
1414 | hpd_rx_offload_wq[i].wq = | |
1415 | create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); | |
1416 | ||
1417 | if (hpd_rx_offload_wq[i].wq == NULL) { | |
1418 | DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); | |
7136f956 | 1419 | goto out_err; |
8e794421 WL |
1420 | } |
1421 | ||
1422 | spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); | |
1423 | } | |
1424 | ||
1425 | return hpd_rx_offload_wq; | |
7136f956 RM |
1426 | |
1427 | out_err: | |
1428 | for (i = 0; i < max_caps; i++) { | |
1429 | if (hpd_rx_offload_wq[i].wq) | |
1430 | destroy_workqueue(hpd_rx_offload_wq[i].wq); | |
1431 | } | |
1432 | kfree(hpd_rx_offload_wq); | |
1433 | return NULL; | |
8e794421 WL |
1434 | } |
1435 | ||
3ce51649 AD |
1436 | struct amdgpu_stutter_quirk { |
1437 | u16 chip_vendor; | |
1438 | u16 chip_device; | |
1439 | u16 subsys_vendor; | |
1440 | u16 subsys_device; | |
1441 | u8 revision; | |
1442 | }; | |
1443 | ||
1444 | static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { | |
1445 | /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ | |
1446 | { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, | |
1447 | { 0, 0, 0, 0, 0 }, | |
1448 | }; | |
1449 | ||
1450 | static bool dm_should_disable_stutter(struct pci_dev *pdev) | |
1451 | { | |
1452 | const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; | |
1453 | ||
1454 | while (p && p->chip_device != 0) { | |
1455 | if (pdev->vendor == p->chip_vendor && | |
1456 | pdev->device == p->chip_device && | |
1457 | pdev->subsystem_vendor == p->subsys_vendor && | |
1458 | pdev->subsystem_device == p->subsys_device && | |
1459 | pdev->revision == p->revision) { | |
1460 | return true; | |
1461 | } | |
1462 | ++p; | |
1463 | } | |
1464 | return false; | |
1465 | } | |
1466 | ||
57b9f338 FZ |
1467 | static const struct dmi_system_id hpd_disconnect_quirk_table[] = { |
1468 | { | |
1469 | .matches = { | |
1470 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1471 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), | |
1472 | }, | |
1473 | }, | |
1474 | { | |
1475 | .matches = { | |
1476 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1477 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), | |
1478 | }, | |
1479 | }, | |
1480 | { | |
1481 | .matches = { | |
1482 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1483 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), | |
1484 | }, | |
1485 | }, | |
503dc81c TL |
1486 | { |
1487 | .matches = { | |
1488 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1489 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), | |
1490 | }, | |
1491 | }, | |
1492 | { | |
1493 | .matches = { | |
1494 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1495 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), | |
1496 | }, | |
1497 | }, | |
1498 | { | |
1499 | .matches = { | |
1500 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1501 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), | |
1502 | }, | |
1503 | }, | |
1504 | { | |
1505 | .matches = { | |
1506 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1507 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), | |
1508 | }, | |
1509 | }, | |
1510 | { | |
1511 | .matches = { | |
1512 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1513 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), | |
1514 | }, | |
1515 | }, | |
1516 | { | |
1517 | .matches = { | |
1518 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
1519 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), | |
1520 | }, | |
1521 | }, | |
57b9f338 | 1522 | {} |
503dc81c | 1523 | /* TODO: refactor this from a fixed table to a dynamic option */ |
57b9f338 FZ |
1524 | }; |
1525 | ||
1526 | static void retrieve_dmi_info(struct amdgpu_display_manager *dm) | |
1527 | { | |
1528 | const struct dmi_system_id *dmi_id; | |
1529 | ||
1530 | dm->aux_hpd_discon_quirk = false; | |
1531 | ||
1532 | dmi_id = dmi_first_match(hpd_disconnect_quirk_table); | |
1533 | if (dmi_id) { | |
1534 | dm->aux_hpd_discon_quirk = true; | |
1535 | DRM_INFO("aux_hpd_discon_quirk attached\n"); | |
1536 | } | |
1537 | } | |
1538 | ||
7578ecda | 1539 | static int amdgpu_dm_init(struct amdgpu_device *adev) |
4562236b HW |
1540 | { |
1541 | struct dc_init_data init_data; | |
52704fca | 1542 | struct dc_callback_init init_params; |
743b9786 | 1543 | int r; |
52704fca | 1544 | |
4a580877 | 1545 | adev->dm.ddev = adev_to_drm(adev); |
4562236b HW |
1546 | adev->dm.adev = adev; |
1547 | ||
4562236b HW |
1548 | /* Zero all the fields */ |
1549 | memset(&init_data, 0, sizeof(init_data)); | |
52704fca | 1550 | memset(&init_params, 0, sizeof(init_params)); |
4562236b | 1551 | |
ead08b95 | 1552 | mutex_init(&adev->dm.dpia_aux_lock); |
674e78ac | 1553 | mutex_init(&adev->dm.dc_lock); |
6ce8f316 | 1554 | mutex_init(&adev->dm.audio_lock); |
674e78ac | 1555 | |
c82eddf8 | 1556 | if (amdgpu_dm_irq_init(adev)) { |
4562236b HW |
1557 | DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); |
1558 | goto error; | |
1559 | } | |
1560 | ||
1561 | init_data.asic_id.chip_family = adev->family; | |
1562 | ||
2dc31ca1 | 1563 | init_data.asic_id.pci_revision_id = adev->pdev->revision; |
4562236b | 1564 | init_data.asic_id.hw_internal_rev = adev->external_rev_id; |
dae66a04 | 1565 | init_data.asic_id.chip_id = adev->pdev->device; |
4562236b | 1566 | |
770d13b1 | 1567 | init_data.asic_id.vram_width = adev->gmc.vram_width; |
4562236b HW |
1568 | /* TODO: initialize init_data.asic_id.vram_type here!!!! */ |
1569 | init_data.asic_id.atombios_base_address = | |
1570 | adev->mode_info.atom_context->bios; | |
1571 | ||
1572 | init_data.driver = adev; | |
1573 | ||
1574 | adev->dm.cgs_device = amdgpu_cgs_create_device(adev); | |
1575 | ||
1576 | if (!adev->dm.cgs_device) { | |
1577 | DRM_ERROR("amdgpu: failed to create cgs device.\n"); | |
1578 | goto error; | |
1579 | } | |
1580 | ||
1581 | init_data.cgs_device = adev->dm.cgs_device; | |
1582 | ||
4562236b HW |
1583 | init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; |
1584 | ||
fd546bc5 AD |
1585 | switch (adev->ip_versions[DCE_HWIP][0]) { |
1586 | case IP_VERSION(2, 1, 0): | |
1587 | switch (adev->dm.dmcub_fw_version) { | |
1588 | case 0: /* development */ | |
1589 | case 0x1: /* linux-firmware.git hash 6d9f399 */ | |
1590 | case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ | |
1591 | init_data.flags.disable_dmcu = false; | |
1592 | break; | |
1593 | default: | |
1594 | init_data.flags.disable_dmcu = true; | |
1595 | } | |
1596 | break; | |
1597 | case IP_VERSION(2, 0, 3): | |
1598 | init_data.flags.disable_dmcu = true; | |
1599 | break; | |
1600 | default: | |
1601 | break; | |
1602 | } | |
1603 | ||
60fb100b AD |
1604 | switch (adev->asic_type) { |
1605 | case CHIP_CARRIZO: | |
1606 | case CHIP_STONEY: | |
1ebcaebd NK |
1607 | init_data.flags.gpu_vm_support = true; |
1608 | break; | |
60fb100b | 1609 | default: |
1d789535 | 1610 | switch (adev->ip_versions[DCE_HWIP][0]) { |
559f591d AD |
1611 | case IP_VERSION(1, 0, 0): |
1612 | case IP_VERSION(1, 0, 1): | |
a7f520bf AD |
1613 | /* enable S/G on PCO and RV2 */ |
1614 | if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || | |
1615 | (adev->apu_flags & AMD_APU_IS_PICASSO)) | |
1616 | init_data.flags.gpu_vm_support = true; | |
1617 | break; | |
c4029779 | 1618 | case IP_VERSION(2, 1, 0): |
c08182f2 | 1619 | case IP_VERSION(3, 0, 1): |
8f56a0fe AD |
1620 | case IP_VERSION(3, 1, 2): |
1621 | case IP_VERSION(3, 1, 3): | |
69ed0c5d | 1622 | case IP_VERSION(3, 1, 4): |
512e8475 | 1623 | case IP_VERSION(3, 1, 5): |
0fe382fb | 1624 | case IP_VERSION(3, 1, 6): |
c08182f2 AD |
1625 | init_data.flags.gpu_vm_support = true; |
1626 | break; | |
c08182f2 AD |
1627 | default: |
1628 | break; | |
1629 | } | |
60fb100b AD |
1630 | break; |
1631 | } | |
bf0207e1 AD |
1632 | if (init_data.flags.gpu_vm_support && |
1633 | (amdgpu_sg_display == 0)) | |
1634 | init_data.flags.gpu_vm_support = false; | |
6e227308 | 1635 | |
a7f520bf AD |
1636 | if (init_data.flags.gpu_vm_support) |
1637 | adev->mode_info.gpu_vm_support = true; | |
1638 | ||
04b94af4 AD |
1639 | if (amdgpu_dc_feature_mask & DC_FBC_MASK) |
1640 | init_data.flags.fbc_support = true; | |
1641 | ||
d99f38ae AD |
1642 | if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) |
1643 | init_data.flags.multi_mon_pp_mclk_switch = true; | |
1644 | ||
eaf56410 LL |
1645 | if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) |
1646 | init_data.flags.disable_fractional_pwm = true; | |
a5148245 ZL |
1647 | |
1648 | if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) | |
1649 | init_data.flags.edp_no_power_sequencing = true; | |
eaf56410 | 1650 | |
12320274 AP |
1651 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) |
1652 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; | |
1653 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) | |
1654 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; | |
12320274 | 1655 | |
7aba117a | 1656 | init_data.flags.seamless_boot_edp_requested = false; |
78ad75f8 | 1657 | |
1edf5ae1 | 1658 | if (check_seamless_boot_capability(adev)) { |
7aba117a | 1659 | init_data.flags.seamless_boot_edp_requested = true; |
1edf5ae1 ZL |
1660 | init_data.flags.allow_seamless_boot_optimization = true; |
1661 | DRM_INFO("Seamless boot condition check passed\n"); | |
1662 | } | |
1663 | ||
a8201902 LM |
1664 | init_data.flags.enable_mipi_converter_optimization = true; |
1665 | ||
e5028e9f | 1666 | init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; |
2a93292f | 1667 | init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; |
e5028e9f | 1668 | |
0dd79532 | 1669 | INIT_LIST_HEAD(&adev->dm.da_list); |
57b9f338 FZ |
1670 | |
1671 | retrieve_dmi_info(&adev->dm); | |
1672 | ||
4562236b HW |
1673 | /* Display Core create. */ |
1674 | adev->dm.dc = dc_create(&init_data); | |
1675 | ||
423788c7 | 1676 | if (adev->dm.dc) { |
9788d087 | 1677 | DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, |
bf7fda0b | 1678 | dce_version_to_string(adev->dm.dc->ctx->dce_version)); |
423788c7 | 1679 | } else { |
9788d087 AP |
1680 | DRM_INFO("Display Core v%s failed to initialize on %s\n", DC_VER, |
1681 | dce_version_to_string(adev->dm.dc->ctx->dce_version)); | |
423788c7 ES |
1682 | goto error; |
1683 | } | |
4562236b | 1684 | |
8a791dab HW |
1685 | if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { |
1686 | adev->dm.dc->debug.force_single_disp_pipe_split = false; | |
1687 | adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; | |
1688 | } | |
1689 | ||
f99d8762 HW |
1690 | if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) |
1691 | adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; | |
3ce51649 AD |
1692 | if (dm_should_disable_stutter(adev->pdev)) |
1693 | adev->dm.dc->debug.disable_stutter = true; | |
f99d8762 | 1694 | |
8a791dab HW |
1695 | if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) |
1696 | adev->dm.dc->debug.disable_stutter = true; | |
1697 | ||
c82eddf8 | 1698 | if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) |
8a791dab HW |
1699 | adev->dm.dc->debug.disable_dsc = true; |
1700 | ||
1701 | if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) | |
1702 | adev->dm.dc->debug.disable_clock_gate = true; | |
1703 | ||
cfb979f7 AP |
1704 | if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) |
1705 | adev->dm.dc->debug.force_subvp_mclk_switch = true; | |
1706 | ||
792a0cdd LL |
1707 | adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; |
1708 | ||
d1bc26cb FZ |
1709 | /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ |
1710 | adev->dm.dc->debug.ignore_cable_id = true; | |
1711 | ||
3d8fcc67 WL |
1712 | /* TODO: There is a new drm mst change where the freedom of |
1713 | * vc_next_start_slot update is revoked/moved into drm, instead of in | |
1714 | * driver. This forces us to make sure to get vc_next_start_slot updated | |
1715 | * in drm function each time without considering if mst_state is active | |
1716 | * or not. Otherwise, next time hotplug will give wrong start_slot | |
1717 | * number. We are implementing a temporary solution to even notify drm | |
1718 | * mst deallocation when link is no longer of MST type when uncommitting | |
1719 | * the stream so we will have more time to work on a proper solution. | |
1720 | * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we | |
1721 | * should notify drm to do a complete "reset" of its states and stop | |
1722 | * calling further drm mst functions when link is no longer of an MST | |
1723 | * type. This could happen when we unplug an MST hubs/displays. When | |
1724 | * uncommit stream comes later after unplug, we should just reset | |
1725 | * hardware states only. | |
1726 | */ | |
1727 | adev->dm.dc->debug.temp_mst_deallocation_sequence = true; | |
1728 | ||
e3834491 FZ |
1729 | if (adev->dm.dc->caps.dp_hdmi21_pcon_support) |
1730 | DRM_INFO("DP-HDMI FRL PCON supported\n"); | |
1731 | ||
743b9786 NK |
1732 | r = dm_dmub_hw_init(adev); |
1733 | if (r) { | |
1734 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); | |
1735 | goto error; | |
1736 | } | |
1737 | ||
bb6785c1 NK |
1738 | dc_hardware_init(adev->dm.dc); |
1739 | ||
8e794421 WL |
1740 | adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); |
1741 | if (!adev->dm.hpd_rx_offload_wq) { | |
1742 | DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); | |
1743 | goto error; | |
1744 | } | |
1745 | ||
3ca001af | 1746 | if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { |
e6cd859d AD |
1747 | struct dc_phy_addr_space_config pa_config; |
1748 | ||
0b08c54b | 1749 | mmhub_read_system_context(adev, &pa_config); |
c0fb85ae | 1750 | |
0b08c54b YZ |
1751 | // Call the DC init_memory func |
1752 | dc_setup_system_context(adev->dm.dc, &pa_config); | |
1753 | } | |
c0fb85ae | 1754 | |
4562236b HW |
1755 | adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); |
1756 | if (!adev->dm.freesync_module) { | |
1757 | DRM_ERROR( | |
1758 | "amdgpu: failed to initialize freesync_module.\n"); | |
1759 | } else | |
f1ad2f5e | 1760 | DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", |
4562236b HW |
1761 | adev->dm.freesync_module); |
1762 | ||
e277adc5 LSL |
1763 | amdgpu_dm_init_color_mod(); |
1764 | ||
ea3b4242 | 1765 | if (adev->dm.dc->caps.max_links > 0) { |
09a5df6c NK |
1766 | adev->dm.vblank_control_workqueue = |
1767 | create_singlethread_workqueue("dm_vblank_control_workqueue"); | |
1768 | if (!adev->dm.vblank_control_workqueue) | |
ea3b4242 | 1769 | DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); |
ea3b4242 | 1770 | } |
ea3b4242 | 1771 | |
c08182f2 | 1772 | if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { |
e50dc171 | 1773 | adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); |
52704fca | 1774 | |
96a3b32e BL |
1775 | if (!adev->dm.hdcp_workqueue) |
1776 | DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); | |
1777 | else | |
1778 | DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); | |
52704fca | 1779 | |
96a3b32e BL |
1780 | dc_init_callbacks(adev->dm.dc, &init_params); |
1781 | } | |
11d526f1 | 1782 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
81927e28 JS |
1783 | init_completion(&adev->dm.dmub_aux_transfer_done); |
1784 | adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); | |
1785 | if (!adev->dm.dmub_notify) { | |
1786 | DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); | |
1787 | goto error; | |
1788 | } | |
e27c41d5 JS |
1789 | |
1790 | adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); | |
1791 | if (!adev->dm.delayed_hpd_wq) { | |
1792 | DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); | |
1793 | goto error; | |
1794 | } | |
1795 | ||
81927e28 | 1796 | amdgpu_dm_outbox_init(adev); |
e27c41d5 JS |
1797 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, |
1798 | dmub_aux_setconfig_callback, false)) { | |
1799 | DRM_ERROR("amdgpu: fail to register dmub aux callback"); | |
1800 | goto error; | |
1801 | } | |
1802 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) { | |
1803 | DRM_ERROR("amdgpu: fail to register dmub hpd callback"); | |
1804 | goto error; | |
1805 | } | |
c40a09e5 NK |
1806 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) { |
1807 | DRM_ERROR("amdgpu: fail to register dmub hpd callback"); | |
1808 | goto error; | |
1809 | } | |
81927e28 JS |
1810 | } |
1811 | ||
11d526f1 SW |
1812 | /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. |
1813 | * It is expected that DMUB will resend any pending notifications at this point, for | |
1814 | * example HPD from DPIA. | |
1815 | */ | |
1816 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) | |
1817 | dc_enable_dmub_outbox(adev->dm.dc); | |
1818 | ||
1c43a48b SW |
1819 | if (amdgpu_dm_initialize_drm_device(adev)) { |
1820 | DRM_ERROR( | |
1821 | "amdgpu: failed to initialize sw for display support.\n"); | |
1822 | goto error; | |
1823 | } | |
1824 | ||
f74367e4 AD |
1825 | /* create fake encoders for MST */ |
1826 | dm_dp_create_fake_mst_encoders(adev); | |
1827 | ||
4562236b HW |
1828 | /* TODO: Add_display_info? */ |
1829 | ||
1830 | /* TODO use dynamic cursor width */ | |
4a580877 LT |
1831 | adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; |
1832 | adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; | |
4562236b | 1833 | |
4a580877 | 1834 | if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { |
4562236b HW |
1835 | DRM_ERROR( |
1836 | "amdgpu: failed to initialize sw for display support.\n"); | |
1837 | goto error; | |
1838 | } | |
1839 | ||
f477c7b5 AL |
1840 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
1841 | adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); | |
1842 | if (!adev->dm.secure_display_ctxs) | |
1843 | DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); | |
1844 | #endif | |
c0fb85ae | 1845 | |
f1ad2f5e | 1846 | DRM_DEBUG_DRIVER("KMS initialized.\n"); |
4562236b HW |
1847 | |
1848 | return 0; | |
1849 | error: | |
1850 | amdgpu_dm_fini(adev); | |
1851 | ||
59d0f396 | 1852 | return -EINVAL; |
4562236b HW |
1853 | } |
1854 | ||
e9669fb7 AG |
1855 | static int amdgpu_dm_early_fini(void *handle) |
1856 | { | |
1857 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1858 | ||
1859 | amdgpu_dm_audio_fini(adev); | |
1860 | ||
1861 | return 0; | |
1862 | } | |
1863 | ||
7578ecda | 1864 | static void amdgpu_dm_fini(struct amdgpu_device *adev) |
4562236b | 1865 | { |
f74367e4 AD |
1866 | int i; |
1867 | ||
09a5df6c NK |
1868 | if (adev->dm.vblank_control_workqueue) { |
1869 | destroy_workqueue(adev->dm.vblank_control_workqueue); | |
1870 | adev->dm.vblank_control_workqueue = NULL; | |
1871 | } | |
09a5df6c | 1872 | |
4562236b | 1873 | amdgpu_dm_destroy_drm_device(&adev->dm); |
c8bdf2b6 | 1874 | |
9a65df19 | 1875 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
1b11ff76 | 1876 | if (adev->dm.secure_display_ctxs) { |
c3d74960 | 1877 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
1b11ff76 AL |
1878 | if (adev->dm.secure_display_ctxs[i].crtc) { |
1879 | flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); | |
1880 | flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); | |
1881 | } | |
1882 | } | |
1883 | kfree(adev->dm.secure_display_ctxs); | |
1884 | adev->dm.secure_display_ctxs = NULL; | |
9a65df19 WL |
1885 | } |
1886 | #endif | |
52704fca | 1887 | if (adev->dm.hdcp_workqueue) { |
e96b1b29 | 1888 | hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); |
52704fca BL |
1889 | adev->dm.hdcp_workqueue = NULL; |
1890 | } | |
1891 | ||
1892 | if (adev->dm.dc) | |
1893 | dc_deinit_callbacks(adev->dm.dc); | |
51ba6912 | 1894 | |
52f1783f IA |
1895 | if (adev->dm.dc) |
1896 | dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); | |
9a71c7d3 | 1897 | |
81927e28 JS |
1898 | if (dc_enable_dmub_notifications(adev->dm.dc)) { |
1899 | kfree(adev->dm.dmub_notify); | |
1900 | adev->dm.dmub_notify = NULL; | |
e27c41d5 JS |
1901 | destroy_workqueue(adev->dm.delayed_hpd_wq); |
1902 | adev->dm.delayed_hpd_wq = NULL; | |
81927e28 JS |
1903 | } |
1904 | ||
743b9786 NK |
1905 | if (adev->dm.dmub_bo) |
1906 | amdgpu_bo_free_kernel(&adev->dm.dmub_bo, | |
1907 | &adev->dm.dmub_bo_gpu_addr, | |
1908 | &adev->dm.dmub_bo_cpu_addr); | |
52704fca | 1909 | |
006c26a0 AG |
1910 | if (adev->dm.hpd_rx_offload_wq) { |
1911 | for (i = 0; i < adev->dm.dc->caps.max_links; i++) { | |
1912 | if (adev->dm.hpd_rx_offload_wq[i].wq) { | |
1913 | destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); | |
1914 | adev->dm.hpd_rx_offload_wq[i].wq = NULL; | |
1915 | } | |
1916 | } | |
1917 | ||
1918 | kfree(adev->dm.hpd_rx_offload_wq); | |
1919 | adev->dm.hpd_rx_offload_wq = NULL; | |
1920 | } | |
1921 | ||
c8bdf2b6 ED |
1922 | /* DC Destroy TODO: Replace destroy DAL */ |
1923 | if (adev->dm.dc) | |
1924 | dc_destroy(&adev->dm.dc); | |
4562236b HW |
1925 | /* |
1926 | * TODO: pageflip, vlank interrupt | |
1927 | * | |
1928 | * amdgpu_dm_irq_fini(adev); | |
1929 | */ | |
1930 | ||
1931 | if (adev->dm.cgs_device) { | |
1932 | amdgpu_cgs_destroy_device(adev->dm.cgs_device); | |
1933 | adev->dm.cgs_device = NULL; | |
1934 | } | |
1935 | if (adev->dm.freesync_module) { | |
1936 | mod_freesync_destroy(adev->dm.freesync_module); | |
1937 | adev->dm.freesync_module = NULL; | |
1938 | } | |
674e78ac | 1939 | |
6ce8f316 | 1940 | mutex_destroy(&adev->dm.audio_lock); |
674e78ac | 1941 | mutex_destroy(&adev->dm.dc_lock); |
ead08b95 | 1942 | mutex_destroy(&adev->dm.dpia_aux_lock); |
4562236b HW |
1943 | } |
1944 | ||
a94d5569 | 1945 | static int load_dmcu_fw(struct amdgpu_device *adev) |
4562236b | 1946 | { |
a7669aff | 1947 | const char *fw_name_dmcu = NULL; |
a94d5569 DF |
1948 | int r; |
1949 | const struct dmcu_firmware_header_v1_0 *hdr; | |
1950 | ||
c82eddf8 | 1951 | switch (adev->asic_type) { |
55e56389 MR |
1952 | #if defined(CONFIG_DRM_AMD_DC_SI) |
1953 | case CHIP_TAHITI: | |
1954 | case CHIP_PITCAIRN: | |
1955 | case CHIP_VERDE: | |
1956 | case CHIP_OLAND: | |
1957 | #endif | |
a94d5569 DF |
1958 | case CHIP_BONAIRE: |
1959 | case CHIP_HAWAII: | |
1960 | case CHIP_KAVERI: | |
1961 | case CHIP_KABINI: | |
1962 | case CHIP_MULLINS: | |
1963 | case CHIP_TONGA: | |
1964 | case CHIP_FIJI: | |
1965 | case CHIP_CARRIZO: | |
1966 | case CHIP_STONEY: | |
1967 | case CHIP_POLARIS11: | |
1968 | case CHIP_POLARIS10: | |
1969 | case CHIP_POLARIS12: | |
1970 | case CHIP_VEGAM: | |
1971 | case CHIP_VEGA10: | |
1972 | case CHIP_VEGA12: | |
1973 | case CHIP_VEGA20: | |
1974 | return 0; | |
5ea23931 RL |
1975 | case CHIP_NAVI12: |
1976 | fw_name_dmcu = FIRMWARE_NAVI12_DMCU; | |
1977 | break; | |
a94d5569 | 1978 | case CHIP_RAVEN: |
a7669aff HW |
1979 | if (ASICREV_IS_PICASSO(adev->external_rev_id)) |
1980 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
1981 | else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) | |
1982 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
1983 | else | |
a7669aff | 1984 | return 0; |
a94d5569 DF |
1985 | break; |
1986 | default: | |
1d789535 | 1987 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
1988 | case IP_VERSION(2, 0, 2): |
1989 | case IP_VERSION(2, 0, 3): | |
1990 | case IP_VERSION(2, 0, 0): | |
1991 | case IP_VERSION(2, 1, 0): | |
1992 | case IP_VERSION(3, 0, 0): | |
1993 | case IP_VERSION(3, 0, 2): | |
1994 | case IP_VERSION(3, 0, 3): | |
1995 | case IP_VERSION(3, 0, 1): | |
1996 | case IP_VERSION(3, 1, 2): | |
1997 | case IP_VERSION(3, 1, 3): | |
f3cd57e4 | 1998 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 1999 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 2000 | case IP_VERSION(3, 1, 6): |
577359ca AP |
2001 | case IP_VERSION(3, 2, 0): |
2002 | case IP_VERSION(3, 2, 1): | |
c08182f2 AD |
2003 | return 0; |
2004 | default: | |
2005 | break; | |
2006 | } | |
a94d5569 | 2007 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); |
59d0f396 | 2008 | return -EINVAL; |
a94d5569 DF |
2009 | } |
2010 | ||
2011 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
2012 | DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); | |
2013 | return 0; | |
2014 | } | |
2015 | ||
46fa9075 ML |
2016 | r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); |
2017 | if (r == -ENODEV) { | |
a94d5569 DF |
2018 | /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ |
2019 | DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); | |
2020 | adev->dm.fw_dmcu = NULL; | |
2021 | return 0; | |
2022 | } | |
a94d5569 DF |
2023 | if (r) { |
2024 | dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", | |
2025 | fw_name_dmcu); | |
51526637 | 2026 | amdgpu_ucode_release(&adev->dm.fw_dmcu); |
a94d5569 DF |
2027 | return r; |
2028 | } | |
2029 | ||
2030 | hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; | |
2031 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; | |
2032 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; | |
2033 | adev->firmware.fw_size += | |
2034 | ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
2035 | ||
2036 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; | |
2037 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; | |
2038 | adev->firmware.fw_size += | |
2039 | ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
2040 | ||
ee6e89c0 DF |
2041 | adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); |
2042 | ||
a94d5569 DF |
2043 | DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); |
2044 | ||
4562236b HW |
2045 | return 0; |
2046 | } | |
2047 | ||
743b9786 NK |
2048 | static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) |
2049 | { | |
2050 | struct amdgpu_device *adev = ctx; | |
2051 | ||
2052 | return dm_read_reg(adev->dm.dc->ctx, address); | |
2053 | } | |
2054 | ||
2055 | static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, | |
2056 | uint32_t value) | |
2057 | { | |
2058 | struct amdgpu_device *adev = ctx; | |
2059 | ||
2060 | return dm_write_reg(adev->dm.dc->ctx, address, value); | |
2061 | } | |
2062 | ||
2063 | static int dm_dmub_sw_init(struct amdgpu_device *adev) | |
2064 | { | |
2065 | struct dmub_srv_create_params create_params; | |
8c7aea40 NK |
2066 | struct dmub_srv_region_params region_params; |
2067 | struct dmub_srv_region_info region_info; | |
2068 | struct dmub_srv_fb_params fb_params; | |
2069 | struct dmub_srv_fb_info *fb_info; | |
2070 | struct dmub_srv *dmub_srv; | |
743b9786 | 2071 | const struct dmcub_firmware_header_v1_0 *hdr; |
743b9786 NK |
2072 | enum dmub_asic dmub_asic; |
2073 | enum dmub_status status; | |
2074 | int r; | |
2075 | ||
1d789535 | 2076 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 | 2077 | case IP_VERSION(2, 1, 0): |
743b9786 | 2078 | dmub_asic = DMUB_ASIC_DCN21; |
743b9786 | 2079 | break; |
c08182f2 | 2080 | case IP_VERSION(3, 0, 0): |
35a45d63 | 2081 | dmub_asic = DMUB_ASIC_DCN30; |
79037324 | 2082 | break; |
c08182f2 | 2083 | case IP_VERSION(3, 0, 1): |
469989ca | 2084 | dmub_asic = DMUB_ASIC_DCN301; |
469989ca | 2085 | break; |
c08182f2 | 2086 | case IP_VERSION(3, 0, 2): |
2a411205 | 2087 | dmub_asic = DMUB_ASIC_DCN302; |
2a411205 | 2088 | break; |
c08182f2 | 2089 | case IP_VERSION(3, 0, 3): |
656fe9b6 | 2090 | dmub_asic = DMUB_ASIC_DCN303; |
656fe9b6 | 2091 | break; |
c08182f2 AD |
2092 | case IP_VERSION(3, 1, 2): |
2093 | case IP_VERSION(3, 1, 3): | |
3137f792 | 2094 | dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; |
1ebcaebd | 2095 | break; |
e850f6b1 RL |
2096 | case IP_VERSION(3, 1, 4): |
2097 | dmub_asic = DMUB_ASIC_DCN314; | |
e850f6b1 | 2098 | break; |
b5b8ed44 QZ |
2099 | case IP_VERSION(3, 1, 5): |
2100 | dmub_asic = DMUB_ASIC_DCN315; | |
b5b8ed44 | 2101 | break; |
de7cc1b4 | 2102 | case IP_VERSION(3, 1, 6): |
868f4357 | 2103 | dmub_asic = DMUB_ASIC_DCN316; |
de7cc1b4 | 2104 | break; |
577359ca AP |
2105 | case IP_VERSION(3, 2, 0): |
2106 | dmub_asic = DMUB_ASIC_DCN32; | |
577359ca AP |
2107 | break; |
2108 | case IP_VERSION(3, 2, 1): | |
2109 | dmub_asic = DMUB_ASIC_DCN321; | |
577359ca | 2110 | break; |
743b9786 NK |
2111 | default: |
2112 | /* ASIC doesn't support DMUB. */ | |
2113 | return 0; | |
2114 | } | |
2115 | ||
743b9786 | 2116 | hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; |
72a74a18 | 2117 | adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); |
743b9786 | 2118 | |
9a6ed547 NK |
2119 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
2120 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = | |
2121 | AMDGPU_UCODE_ID_DMCUB; | |
2122 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = | |
2123 | adev->dm.dmub_fw; | |
2124 | adev->firmware.fw_size += | |
2125 | ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); | |
743b9786 | 2126 | |
9a6ed547 NK |
2127 | DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", |
2128 | adev->dm.dmcub_fw_version); | |
2129 | } | |
2130 | ||
743b9786 | 2131 | |
8c7aea40 NK |
2132 | adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); |
2133 | dmub_srv = adev->dm.dmub_srv; | |
2134 | ||
2135 | if (!dmub_srv) { | |
2136 | DRM_ERROR("Failed to allocate DMUB service!\n"); | |
2137 | return -ENOMEM; | |
2138 | } | |
2139 | ||
2140 | memset(&create_params, 0, sizeof(create_params)); | |
2141 | create_params.user_ctx = adev; | |
2142 | create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; | |
2143 | create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; | |
2144 | create_params.asic = dmub_asic; | |
2145 | ||
2146 | /* Create the DMUB service. */ | |
2147 | status = dmub_srv_create(dmub_srv, &create_params); | |
2148 | if (status != DMUB_STATUS_OK) { | |
2149 | DRM_ERROR("Error creating DMUB service: %d\n", status); | |
2150 | return -EINVAL; | |
2151 | } | |
2152 | ||
2153 | /* Calculate the size of all the regions for the DMUB service. */ | |
2154 | memset(®ion_params, 0, sizeof(region_params)); | |
2155 | ||
2156 | region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - | |
2157 | PSP_HEADER_BYTES - PSP_FOOTER_BYTES; | |
2158 | region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); | |
2159 | region_params.vbios_size = adev->bios_size; | |
0922b899 | 2160 | region_params.fw_bss_data = region_params.bss_data_size ? |
1f0674fd NK |
2161 | adev->dm.dmub_fw->data + |
2162 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
0922b899 | 2163 | le32_to_cpu(hdr->inst_const_bytes) : NULL; |
a576b345 NK |
2164 | region_params.fw_inst_const = |
2165 | adev->dm.dmub_fw->data + | |
2166 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + | |
2167 | PSP_HEADER_BYTES; | |
8c7aea40 NK |
2168 | |
2169 | status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, | |
2170 | ®ion_info); | |
2171 | ||
2172 | if (status != DMUB_STATUS_OK) { | |
2173 | DRM_ERROR("Error calculating DMUB region info: %d\n", status); | |
2174 | return -EINVAL; | |
2175 | } | |
2176 | ||
2177 | /* | |
2178 | * Allocate a framebuffer based on the total size of all the regions. | |
2179 | * TODO: Move this into GART. | |
2180 | */ | |
2181 | r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, | |
58ab2c08 CK |
2182 | AMDGPU_GEM_DOMAIN_VRAM | |
2183 | AMDGPU_GEM_DOMAIN_GTT, | |
2184 | &adev->dm.dmub_bo, | |
8c7aea40 NK |
2185 | &adev->dm.dmub_bo_gpu_addr, |
2186 | &adev->dm.dmub_bo_cpu_addr); | |
2187 | if (r) | |
2188 | return r; | |
2189 | ||
2190 | /* Rebase the regions on the framebuffer address. */ | |
2191 | memset(&fb_params, 0, sizeof(fb_params)); | |
2192 | fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; | |
2193 | fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; | |
2194 | fb_params.region_info = ®ion_info; | |
2195 | ||
2196 | adev->dm.dmub_fb_info = | |
2197 | kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); | |
2198 | fb_info = adev->dm.dmub_fb_info; | |
2199 | ||
2200 | if (!fb_info) { | |
2201 | DRM_ERROR( | |
2202 | "Failed to allocate framebuffer info for DMUB service!\n"); | |
2203 | return -ENOMEM; | |
2204 | } | |
2205 | ||
2206 | status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); | |
2207 | if (status != DMUB_STATUS_OK) { | |
2208 | DRM_ERROR("Error calculating DMUB FB info: %d\n", status); | |
2209 | return -EINVAL; | |
2210 | } | |
2211 | ||
743b9786 NK |
2212 | return 0; |
2213 | } | |
2214 | ||
a94d5569 DF |
2215 | static int dm_sw_init(void *handle) |
2216 | { | |
2217 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
743b9786 NK |
2218 | int r; |
2219 | ||
2220 | r = dm_dmub_sw_init(adev); | |
2221 | if (r) | |
2222 | return r; | |
a94d5569 DF |
2223 | |
2224 | return load_dmcu_fw(adev); | |
2225 | } | |
2226 | ||
4562236b HW |
2227 | static int dm_sw_fini(void *handle) |
2228 | { | |
a94d5569 DF |
2229 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2230 | ||
8c7aea40 NK |
2231 | kfree(adev->dm.dmub_fb_info); |
2232 | adev->dm.dmub_fb_info = NULL; | |
2233 | ||
743b9786 NK |
2234 | if (adev->dm.dmub_srv) { |
2235 | dmub_srv_destroy(adev->dm.dmub_srv); | |
2236 | adev->dm.dmub_srv = NULL; | |
2237 | } | |
2238 | ||
51526637 ML |
2239 | amdgpu_ucode_release(&adev->dm.dmub_fw); |
2240 | amdgpu_ucode_release(&adev->dm.fw_dmcu); | |
a94d5569 | 2241 | |
4562236b HW |
2242 | return 0; |
2243 | } | |
2244 | ||
7abcf6b5 | 2245 | static int detect_mst_link_for_all_connectors(struct drm_device *dev) |
4562236b | 2246 | { |
c84dec2f | 2247 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2248 | struct drm_connector *connector; |
f8d2d39e | 2249 | struct drm_connector_list_iter iter; |
7abcf6b5 | 2250 | int ret = 0; |
4562236b | 2251 | |
f8d2d39e LP |
2252 | drm_connector_list_iter_begin(dev, &iter); |
2253 | drm_for_each_connector_iter(connector, &iter) { | |
b349f76e | 2254 | aconnector = to_amdgpu_dm_connector(connector); |
30ec2b97 JFZ |
2255 | if (aconnector->dc_link->type == dc_connection_mst_branch && |
2256 | aconnector->mst_mgr.aux) { | |
f1ad2f5e | 2257 | DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", |
f8d2d39e LP |
2258 | aconnector, |
2259 | aconnector->base.base.id); | |
7abcf6b5 AG |
2260 | |
2261 | ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); | |
2262 | if (ret < 0) { | |
2263 | DRM_ERROR("DM_MST: Failed to start MST\n"); | |
f8d2d39e LP |
2264 | aconnector->dc_link->type = |
2265 | dc_connection_single; | |
3f6752b4 RL |
2266 | ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
2267 | aconnector->dc_link); | |
f8d2d39e | 2268 | break; |
7abcf6b5 | 2269 | } |
f8d2d39e | 2270 | } |
4562236b | 2271 | } |
f8d2d39e | 2272 | drm_connector_list_iter_end(&iter); |
4562236b | 2273 | |
7abcf6b5 AG |
2274 | return ret; |
2275 | } | |
2276 | ||
2277 | static int dm_late_init(void *handle) | |
2278 | { | |
42e67c3b | 2279 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7abcf6b5 | 2280 | |
bbf854dc DF |
2281 | struct dmcu_iram_parameters params; |
2282 | unsigned int linear_lut[16]; | |
2283 | int i; | |
17bdb4a8 | 2284 | struct dmcu *dmcu = NULL; |
bbf854dc | 2285 | |
17bdb4a8 JFZ |
2286 | dmcu = adev->dm.dc->res_pool->dmcu; |
2287 | ||
bbf854dc DF |
2288 | for (i = 0; i < 16; i++) |
2289 | linear_lut[i] = 0xFFFF * i / 15; | |
2290 | ||
2291 | params.set = 0; | |
75068994 | 2292 | params.backlight_ramping_override = false; |
bbf854dc DF |
2293 | params.backlight_ramping_start = 0xCCCC; |
2294 | params.backlight_ramping_reduction = 0xCCCCCCCC; | |
2295 | params.backlight_lut_array_size = 16; | |
2296 | params.backlight_lut_array = linear_lut; | |
2297 | ||
2ad0cdf9 AK |
2298 | /* Min backlight level after ABM reduction, Don't allow below 1% |
2299 | * 0xFFFF x 0.01 = 0x28F | |
2300 | */ | |
2301 | params.min_abm_backlight = 0x28F; | |
5cb32419 | 2302 | /* In the case where abm is implemented on dmcub, |
3335a135 UKK |
2303 | * dmcu object will be null. |
2304 | * ABM 2.4 and up are implemented on dmcub. | |
2305 | */ | |
6e568e43 JW |
2306 | if (dmcu) { |
2307 | if (!dmcu_load_iram(dmcu, params)) | |
2308 | return -EINVAL; | |
2309 | } else if (adev->dm.dc->ctx->dmub_srv) { | |
2310 | struct dc_link *edp_links[MAX_NUM_EDP]; | |
2311 | int edp_num; | |
bbf854dc | 2312 | |
7ae1dbe6 | 2313 | dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); |
6e568e43 JW |
2314 | for (i = 0; i < edp_num; i++) { |
2315 | if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) | |
2316 | return -EINVAL; | |
2317 | } | |
2318 | } | |
bbf854dc | 2319 | |
4a580877 | 2320 | return detect_mst_link_for_all_connectors(adev_to_drm(adev)); |
4562236b HW |
2321 | } |
2322 | ||
2323 | static void s3_handle_mst(struct drm_device *dev, bool suspend) | |
2324 | { | |
c84dec2f | 2325 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2326 | struct drm_connector *connector; |
f8d2d39e | 2327 | struct drm_connector_list_iter iter; |
fe7553be LP |
2328 | struct drm_dp_mst_topology_mgr *mgr; |
2329 | int ret; | |
2330 | bool need_hotplug = false; | |
4562236b | 2331 | |
f8d2d39e LP |
2332 | drm_connector_list_iter_begin(dev, &iter); |
2333 | drm_for_each_connector_iter(connector, &iter) { | |
fe7553be LP |
2334 | aconnector = to_amdgpu_dm_connector(connector); |
2335 | if (aconnector->dc_link->type != dc_connection_mst_branch || | |
f0127cb1 | 2336 | aconnector->mst_root) |
fe7553be LP |
2337 | continue; |
2338 | ||
2339 | mgr = &aconnector->mst_mgr; | |
2340 | ||
2341 | if (suspend) { | |
2342 | drm_dp_mst_topology_mgr_suspend(mgr); | |
2343 | } else { | |
1e5d4d8e RL |
2344 | /* if extended timeout is supported in hardware, |
2345 | * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer | |
2346 | * CTS 4.2.1.1 regression introduced by CTS specs requirement update. | |
2347 | */ | |
2348 | try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); | |
2349 | if (!dp_is_lttpr_present(aconnector->dc_link)) | |
2350 | try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); | |
2351 | ||
6f85f738 | 2352 | ret = drm_dp_mst_topology_mgr_resume(mgr, true); |
fe7553be | 2353 | if (ret < 0) { |
84a8b390 WL |
2354 | dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
2355 | aconnector->dc_link); | |
fe7553be LP |
2356 | need_hotplug = true; |
2357 | } | |
2358 | } | |
4562236b | 2359 | } |
f8d2d39e | 2360 | drm_connector_list_iter_end(&iter); |
fe7553be LP |
2361 | |
2362 | if (need_hotplug) | |
2363 | drm_kms_helper_hotplug_event(dev); | |
4562236b HW |
2364 | } |
2365 | ||
9340dfd3 HW |
2366 | static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) |
2367 | { | |
9340dfd3 HW |
2368 | int ret = 0; |
2369 | ||
9340dfd3 HW |
2370 | /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends |
2371 | * on window driver dc implementation. | |
2372 | * For Navi1x, clock settings of dcn watermarks are fixed. the settings | |
2373 | * should be passed to smu during boot up and resume from s3. | |
2374 | * boot up: dc calculate dcn watermark clock settings within dc_create, | |
2375 | * dcn20_resource_construct | |
2376 | * then call pplib functions below to pass the settings to smu: | |
2377 | * smu_set_watermarks_for_clock_ranges | |
2378 | * smu_set_watermarks_table | |
2379 | * navi10_set_watermarks_table | |
2380 | * smu_write_watermarks_table | |
2381 | * | |
2382 | * For Renoir, clock settings of dcn watermark are also fixed values. | |
2383 | * dc has implemented different flow for window driver: | |
2384 | * dc_hardware_init / dc_set_power_state | |
2385 | * dcn10_init_hw | |
2386 | * notify_wm_ranges | |
2387 | * set_wm_ranges | |
2388 | * -- Linux | |
2389 | * smu_set_watermarks_for_clock_ranges | |
2390 | * renoir_set_watermarks_table | |
2391 | * smu_write_watermarks_table | |
2392 | * | |
2393 | * For Linux, | |
2394 | * dc_hardware_init -> amdgpu_dm_init | |
2395 | * dc_set_power_state --> dm_resume | |
2396 | * | |
2397 | * therefore, this function apply to navi10/12/14 but not Renoir | |
2398 | * * | |
2399 | */ | |
1d789535 | 2400 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
2401 | case IP_VERSION(2, 0, 2): |
2402 | case IP_VERSION(2, 0, 0): | |
9340dfd3 HW |
2403 | break; |
2404 | default: | |
2405 | return 0; | |
2406 | } | |
2407 | ||
13f5dbd6 | 2408 | ret = amdgpu_dpm_write_watermarks_table(adev); |
e7a95eea EQ |
2409 | if (ret) { |
2410 | DRM_ERROR("Failed to update WMTABLE!\n"); | |
2411 | return ret; | |
9340dfd3 HW |
2412 | } |
2413 | ||
9340dfd3 HW |
2414 | return 0; |
2415 | } | |
2416 | ||
b8592b48 LL |
2417 | /** |
2418 | * dm_hw_init() - Initialize DC device | |
28d687ea | 2419 | * @handle: The base driver device containing the amdgpu_dm device. |
b8592b48 LL |
2420 | * |
2421 | * Initialize the &struct amdgpu_display_manager device. This involves calling | |
2422 | * the initializers of each DM component, then populating the struct with them. | |
2423 | * | |
2424 | * Although the function implies hardware initialization, both hardware and | |
2425 | * software are initialized here. Splitting them out to their relevant init | |
2426 | * hooks is a future TODO item. | |
2427 | * | |
2428 | * Some notable things that are initialized here: | |
2429 | * | |
2430 | * - Display Core, both software and hardware | |
2431 | * - DC modules that we need (freesync and color management) | |
2432 | * - DRM software states | |
2433 | * - Interrupt sources and handlers | |
2434 | * - Vblank support | |
2435 | * - Debug FS entries, if enabled | |
2436 | */ | |
4562236b HW |
2437 | static int dm_hw_init(void *handle) |
2438 | { | |
2439 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
2440 | /* Create DAL display manager */ | |
2441 | amdgpu_dm_init(adev); | |
4562236b HW |
2442 | amdgpu_dm_hpd_init(adev); |
2443 | ||
4562236b HW |
2444 | return 0; |
2445 | } | |
2446 | ||
b8592b48 LL |
2447 | /** |
2448 | * dm_hw_fini() - Teardown DC device | |
28d687ea | 2449 | * @handle: The base driver device containing the amdgpu_dm device. |
b8592b48 LL |
2450 | * |
2451 | * Teardown components within &struct amdgpu_display_manager that require | |
2452 | * cleanup. This involves cleaning up the DRM device, DC, and any modules that | |
2453 | * were loaded. Also flush IRQ workqueues and disable them. | |
2454 | */ | |
4562236b HW |
2455 | static int dm_hw_fini(void *handle) |
2456 | { | |
2457 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
2458 | ||
2459 | amdgpu_dm_hpd_fini(adev); | |
2460 | ||
2461 | amdgpu_dm_irq_fini(adev); | |
21de3396 | 2462 | amdgpu_dm_fini(adev); |
4562236b HW |
2463 | return 0; |
2464 | } | |
2465 | ||
cdaae837 | 2466 | |
cdaae837 BL |
2467 | static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, |
2468 | struct dc_state *state, bool enable) | |
2469 | { | |
2470 | enum dc_irq_source irq_source; | |
2471 | struct amdgpu_crtc *acrtc; | |
2472 | int rc = -EBUSY; | |
2473 | int i = 0; | |
2474 | ||
2475 | for (i = 0; i < state->stream_count; i++) { | |
2476 | acrtc = get_crtc_by_otg_inst( | |
2477 | adev, state->stream_status[i].primary_otg_inst); | |
2478 | ||
2479 | if (acrtc && state->stream_status[i].plane_count != 0) { | |
2480 | irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; | |
2481 | rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; | |
cdaae837 BL |
2482 | if (rc) |
2483 | DRM_WARN("Failed to %s pflip interrupts\n", | |
2484 | enable ? "enable" : "disable"); | |
2485 | ||
2486 | if (enable) { | |
cd465a67 AL |
2487 | if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) |
2488 | rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); | |
2489 | } else | |
2490 | rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); | |
cdaae837 | 2491 | |
cd465a67 AL |
2492 | if (rc) |
2493 | DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); | |
cdaae837 | 2494 | |
cd465a67 AL |
2495 | irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; |
2496 | /* During gpu-reset we disable and then enable vblank irq, so | |
2497 | * don't use amdgpu_irq_get/put() to avoid refcount change. | |
2498 | */ | |
2499 | if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) | |
2500 | DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); | |
cdaae837 BL |
2501 | } |
2502 | } | |
2503 | ||
2504 | } | |
2505 | ||
dfd84d90 | 2506 | static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) |
cdaae837 BL |
2507 | { |
2508 | struct dc_state *context = NULL; | |
2509 | enum dc_status res = DC_ERROR_UNEXPECTED; | |
2510 | int i; | |
2511 | struct dc_stream_state *del_streams[MAX_PIPES]; | |
2512 | int del_streams_count = 0; | |
2513 | ||
2514 | memset(del_streams, 0, sizeof(del_streams)); | |
2515 | ||
2516 | context = dc_create_state(dc); | |
2517 | if (context == NULL) | |
2518 | goto context_alloc_fail; | |
2519 | ||
2520 | dc_resource_state_copy_construct_current(dc, context); | |
2521 | ||
2522 | /* First remove from context all streams */ | |
2523 | for (i = 0; i < context->stream_count; i++) { | |
2524 | struct dc_stream_state *stream = context->streams[i]; | |
2525 | ||
2526 | del_streams[del_streams_count++] = stream; | |
2527 | } | |
2528 | ||
2529 | /* Remove all planes for removed streams and then remove the streams */ | |
2530 | for (i = 0; i < del_streams_count; i++) { | |
2531 | if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { | |
2532 | res = DC_FAIL_DETACH_SURFACES; | |
2533 | goto fail; | |
2534 | } | |
2535 | ||
2536 | res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); | |
2537 | if (res != DC_OK) | |
2538 | goto fail; | |
2539 | } | |
2540 | ||
b8272241 | 2541 | res = dc_commit_streams(dc, context->streams, context->stream_count); |
cdaae837 BL |
2542 | |
2543 | fail: | |
2544 | dc_release_state(context); | |
2545 | ||
2546 | context_alloc_fail: | |
2547 | return res; | |
2548 | } | |
2549 | ||
8e794421 WL |
2550 | static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) |
2551 | { | |
2552 | int i; | |
2553 | ||
2554 | if (dm->hpd_rx_offload_wq) { | |
2555 | for (i = 0; i < dm->dc->caps.max_links; i++) | |
2556 | flush_workqueue(dm->hpd_rx_offload_wq[i].wq); | |
2557 | } | |
2558 | } | |
2559 | ||
4562236b HW |
2560 | static int dm_suspend(void *handle) |
2561 | { | |
2562 | struct amdgpu_device *adev = handle; | |
2563 | struct amdgpu_display_manager *dm = &adev->dm; | |
2564 | int ret = 0; | |
4562236b | 2565 | |
53b3f8f4 | 2566 | if (amdgpu_in_reset(adev)) { |
cdaae837 | 2567 | mutex_lock(&dm->dc_lock); |
98ab5f35 | 2568 | |
98ab5f35 | 2569 | dc_allow_idle_optimizations(adev->dm.dc, false); |
98ab5f35 | 2570 | |
cdaae837 BL |
2571 | dm->cached_dc_state = dc_copy_state(dm->dc->current_state); |
2572 | ||
2573 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); | |
2574 | ||
2575 | amdgpu_dm_commit_zero_streams(dm->dc); | |
2576 | ||
2577 | amdgpu_dm_irq_suspend(adev); | |
2578 | ||
8e794421 WL |
2579 | hpd_rx_irq_work_suspend(dm); |
2580 | ||
cdaae837 BL |
2581 | return ret; |
2582 | } | |
4562236b | 2583 | |
d2f0b53b | 2584 | WARN_ON(adev->dm.cached_state); |
4a580877 | 2585 | adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); |
d2f0b53b | 2586 | |
4a580877 | 2587 | s3_handle_mst(adev_to_drm(adev), true); |
4562236b | 2588 | |
4562236b HW |
2589 | amdgpu_dm_irq_suspend(adev); |
2590 | ||
8e794421 WL |
2591 | hpd_rx_irq_work_suspend(dm); |
2592 | ||
32f5062d | 2593 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); |
4562236b | 2594 | |
1c2075d4 | 2595 | return 0; |
4562236b HW |
2596 | } |
2597 | ||
17ce8a69 | 2598 | struct amdgpu_dm_connector * |
1daf8c63 AD |
2599 | amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, |
2600 | struct drm_crtc *crtc) | |
4562236b | 2601 | { |
ae67558b | 2602 | u32 i; |
c2cea706 | 2603 | struct drm_connector_state *new_con_state; |
4562236b HW |
2604 | struct drm_connector *connector; |
2605 | struct drm_crtc *crtc_from_state; | |
2606 | ||
c2cea706 LSL |
2607 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
2608 | crtc_from_state = new_con_state->crtc; | |
4562236b HW |
2609 | |
2610 | if (crtc_from_state == crtc) | |
c84dec2f | 2611 | return to_amdgpu_dm_connector(connector); |
4562236b HW |
2612 | } |
2613 | ||
2614 | return NULL; | |
2615 | } | |
2616 | ||
fbbdadf2 BL |
2617 | static void emulated_link_detect(struct dc_link *link) |
2618 | { | |
2619 | struct dc_sink_init_data sink_init_data = { 0 }; | |
2620 | struct display_sink_capability sink_caps = { 0 }; | |
2621 | enum dc_edid_status edid_status; | |
2622 | struct dc_context *dc_ctx = link->ctx; | |
2623 | struct dc_sink *sink = NULL; | |
2624 | struct dc_sink *prev_sink = NULL; | |
2625 | ||
2626 | link->type = dc_connection_none; | |
2627 | prev_sink = link->local_sink; | |
2628 | ||
30164a16 VL |
2629 | if (prev_sink) |
2630 | dc_sink_release(prev_sink); | |
fbbdadf2 BL |
2631 | |
2632 | switch (link->connector_signal) { | |
2633 | case SIGNAL_TYPE_HDMI_TYPE_A: { | |
2634 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2635 | sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; | |
2636 | break; | |
2637 | } | |
2638 | ||
2639 | case SIGNAL_TYPE_DVI_SINGLE_LINK: { | |
2640 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2641 | sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; | |
2642 | break; | |
2643 | } | |
2644 | ||
2645 | case SIGNAL_TYPE_DVI_DUAL_LINK: { | |
2646 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2647 | sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; | |
2648 | break; | |
2649 | } | |
2650 | ||
2651 | case SIGNAL_TYPE_LVDS: { | |
2652 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
2653 | sink_caps.signal = SIGNAL_TYPE_LVDS; | |
2654 | break; | |
2655 | } | |
2656 | ||
2657 | case SIGNAL_TYPE_EDP: { | |
2658 | sink_caps.transaction_type = | |
2659 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
2660 | sink_caps.signal = SIGNAL_TYPE_EDP; | |
2661 | break; | |
2662 | } | |
2663 | ||
2664 | case SIGNAL_TYPE_DISPLAY_PORT: { | |
2665 | sink_caps.transaction_type = | |
2666 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
2667 | sink_caps.signal = SIGNAL_TYPE_VIRTUAL; | |
2668 | break; | |
2669 | } | |
2670 | ||
2671 | default: | |
2672 | DC_ERROR("Invalid connector type! signal:%d\n", | |
2673 | link->connector_signal); | |
2674 | return; | |
2675 | } | |
2676 | ||
2677 | sink_init_data.link = link; | |
2678 | sink_init_data.sink_signal = sink_caps.signal; | |
2679 | ||
2680 | sink = dc_sink_create(&sink_init_data); | |
2681 | if (!sink) { | |
2682 | DC_ERROR("Failed to create sink!\n"); | |
2683 | return; | |
2684 | } | |
2685 | ||
dcd5fb82 | 2686 | /* dc_sink_create returns a new reference */ |
fbbdadf2 BL |
2687 | link->local_sink = sink; |
2688 | ||
2689 | edid_status = dm_helpers_read_local_edid( | |
2690 | link->ctx, | |
2691 | link, | |
2692 | sink); | |
2693 | ||
2694 | if (edid_status != EDID_OK) | |
2695 | DC_ERROR("Failed to read EDID"); | |
2696 | ||
2697 | } | |
2698 | ||
cdaae837 BL |
2699 | static void dm_gpureset_commit_state(struct dc_state *dc_state, |
2700 | struct amdgpu_display_manager *dm) | |
2701 | { | |
2702 | struct { | |
2703 | struct dc_surface_update surface_updates[MAX_SURFACES]; | |
2704 | struct dc_plane_info plane_infos[MAX_SURFACES]; | |
2705 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; | |
2706 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; | |
2707 | struct dc_stream_update stream_update; | |
c82eddf8 | 2708 | } *bundle; |
cdaae837 BL |
2709 | int k, m; |
2710 | ||
2711 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); | |
2712 | ||
2713 | if (!bundle) { | |
2714 | dm_error("Failed to allocate update bundle\n"); | |
2715 | goto cleanup; | |
2716 | } | |
2717 | ||
2718 | for (k = 0; k < dc_state->stream_count; k++) { | |
2719 | bundle->stream_update.stream = dc_state->streams[k]; | |
2720 | ||
2721 | for (m = 0; m < dc_state->stream_status->plane_count; m++) { | |
2722 | bundle->surface_updates[m].surface = | |
2723 | dc_state->stream_status->plane_states[m]; | |
2724 | bundle->surface_updates[m].surface->force_full_update = | |
2725 | true; | |
2726 | } | |
f7511289 | 2727 | |
81f743a0 RS |
2728 | update_planes_and_stream_adapter(dm->dc, |
2729 | UPDATE_TYPE_FULL, | |
2730 | dc_state->stream_status->plane_count, | |
2731 | dc_state->streams[k], | |
2732 | &bundle->stream_update, | |
2733 | bundle->surface_updates); | |
cdaae837 BL |
2734 | } |
2735 | ||
2736 | cleanup: | |
2737 | kfree(bundle); | |
cdaae837 BL |
2738 | } |
2739 | ||
4562236b HW |
2740 | static int dm_resume(void *handle) |
2741 | { | |
2742 | struct amdgpu_device *adev = handle; | |
4a580877 | 2743 | struct drm_device *ddev = adev_to_drm(adev); |
4562236b | 2744 | struct amdgpu_display_manager *dm = &adev->dm; |
c84dec2f | 2745 | struct amdgpu_dm_connector *aconnector; |
4562236b | 2746 | struct drm_connector *connector; |
f8d2d39e | 2747 | struct drm_connector_list_iter iter; |
4562236b | 2748 | struct drm_crtc *crtc; |
c2cea706 | 2749 | struct drm_crtc_state *new_crtc_state; |
fcb4019e LSL |
2750 | struct dm_crtc_state *dm_new_crtc_state; |
2751 | struct drm_plane *plane; | |
2752 | struct drm_plane_state *new_plane_state; | |
2753 | struct dm_plane_state *dm_new_plane_state; | |
113b7a01 | 2754 | struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); |
fbbdadf2 | 2755 | enum dc_connection_type new_connection_type = dc_connection_none; |
cdaae837 BL |
2756 | struct dc_state *dc_state; |
2757 | int i, r, j; | |
4562236b | 2758 | |
53b3f8f4 | 2759 | if (amdgpu_in_reset(adev)) { |
cdaae837 BL |
2760 | dc_state = dm->cached_dc_state; |
2761 | ||
6d63fcc2 NK |
2762 | /* |
2763 | * The dc->current_state is backed up into dm->cached_dc_state | |
2764 | * before we commit 0 streams. | |
2765 | * | |
2766 | * DC will clear link encoder assignments on the real state | |
2767 | * but the changes won't propagate over to the copy we made | |
2768 | * before the 0 streams commit. | |
2769 | * | |
2770 | * DC expects that link encoder assignments are *not* valid | |
32685b32 NK |
2771 | * when committing a state, so as a workaround we can copy |
2772 | * off of the current state. | |
2773 | * | |
2774 | * We lose the previous assignments, but we had already | |
2775 | * commit 0 streams anyway. | |
6d63fcc2 | 2776 | */ |
32685b32 | 2777 | link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); |
6d63fcc2 | 2778 | |
cdaae837 BL |
2779 | r = dm_dmub_hw_init(adev); |
2780 | if (r) | |
2781 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); | |
2782 | ||
2783 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); | |
2784 | dc_resume(dm->dc); | |
2785 | ||
2786 | amdgpu_dm_irq_resume_early(adev); | |
2787 | ||
2788 | for (i = 0; i < dc_state->stream_count; i++) { | |
2789 | dc_state->streams[i]->mode_changed = true; | |
6984fa41 NK |
2790 | for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { |
2791 | dc_state->stream_status[i].plane_states[j]->update_flags.raw | |
cdaae837 BL |
2792 | = 0xffffffff; |
2793 | } | |
2794 | } | |
2795 | ||
11d526f1 SW |
2796 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
2797 | amdgpu_dm_outbox_init(adev); | |
2798 | dc_enable_dmub_outbox(adev->dm.dc); | |
2799 | } | |
2800 | ||
b8272241 | 2801 | WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); |
4562236b | 2802 | |
cdaae837 BL |
2803 | dm_gpureset_commit_state(dm->cached_dc_state, dm); |
2804 | ||
2805 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); | |
2806 | ||
2807 | dc_release_state(dm->cached_dc_state); | |
2808 | dm->cached_dc_state = NULL; | |
2809 | ||
2810 | amdgpu_dm_irq_resume_late(adev); | |
2811 | ||
2812 | mutex_unlock(&dm->dc_lock); | |
2813 | ||
2814 | return 0; | |
2815 | } | |
113b7a01 LL |
2816 | /* Recreate dc_state - DC invalidates it when setting power state to S3. */ |
2817 | dc_release_state(dm_state->context); | |
2818 | dm_state->context = dc_create_state(dm->dc); | |
2819 | /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ | |
2820 | dc_resource_state_construct(dm->dc, dm_state->context); | |
2821 | ||
8c7aea40 | 2822 | /* Before powering on DC we need to re-initialize DMUB. */ |
79d6b935 | 2823 | dm_dmub_hw_resume(adev); |
8c7aea40 | 2824 | |
11d526f1 SW |
2825 | /* Re-enable outbox interrupts for DPIA. */ |
2826 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { | |
2827 | amdgpu_dm_outbox_init(adev); | |
2828 | dc_enable_dmub_outbox(adev->dm.dc); | |
2829 | } | |
2830 | ||
a80aa93d ML |
2831 | /* power on hardware */ |
2832 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); | |
2833 | ||
4562236b HW |
2834 | /* program HPD filter */ |
2835 | dc_resume(dm->dc); | |
2836 | ||
4562236b HW |
2837 | /* |
2838 | * early enable HPD Rx IRQ, should be done before set mode as short | |
2839 | * pulse interrupts are used for MST | |
2840 | */ | |
2841 | amdgpu_dm_irq_resume_early(adev); | |
2842 | ||
d20ebea8 | 2843 | /* On resume we need to rewrite the MSTM control bits to enable MST*/ |
684cd480 LP |
2844 | s3_handle_mst(ddev, false); |
2845 | ||
4562236b | 2846 | /* Do detection*/ |
f8d2d39e LP |
2847 | drm_connector_list_iter_begin(ddev, &iter); |
2848 | drm_for_each_connector_iter(connector, &iter) { | |
c84dec2f | 2849 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b | 2850 | |
7a7175a2 RL |
2851 | if (!aconnector->dc_link) |
2852 | continue; | |
2853 | ||
4562236b HW |
2854 | /* |
2855 | * this is the case when traversing through already created | |
2856 | * MST connectors, should be skipped | |
2857 | */ | |
91b38ca1 | 2858 | if (aconnector && aconnector->mst_root) |
4562236b HW |
2859 | continue; |
2860 | ||
03ea364c | 2861 | mutex_lock(&aconnector->hpd_lock); |
54618888 | 2862 | if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) |
fbbdadf2 BL |
2863 | DRM_ERROR("KMS: Failed to detect connector\n"); |
2864 | ||
15c735e7 | 2865 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
fbbdadf2 | 2866 | emulated_link_detect(aconnector->dc_link); |
15c735e7 WL |
2867 | } else { |
2868 | mutex_lock(&dm->dc_lock); | |
fbbdadf2 | 2869 | dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); |
15c735e7 WL |
2870 | mutex_unlock(&dm->dc_lock); |
2871 | } | |
3eb4eba4 RL |
2872 | |
2873 | if (aconnector->fake_enable && aconnector->dc_link->local_sink) | |
2874 | aconnector->fake_enable = false; | |
2875 | ||
dcd5fb82 MF |
2876 | if (aconnector->dc_sink) |
2877 | dc_sink_release(aconnector->dc_sink); | |
4562236b HW |
2878 | aconnector->dc_sink = NULL; |
2879 | amdgpu_dm_update_connector_after_detect(aconnector); | |
03ea364c | 2880 | mutex_unlock(&aconnector->hpd_lock); |
4562236b | 2881 | } |
f8d2d39e | 2882 | drm_connector_list_iter_end(&iter); |
4562236b | 2883 | |
1f6010a9 | 2884 | /* Force mode set in atomic commit */ |
a80aa93d | 2885 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) |
c2cea706 | 2886 | new_crtc_state->active_changed = true; |
4f346e65 | 2887 | |
fcb4019e LSL |
2888 | /* |
2889 | * atomic_check is expected to create the dc states. We need to release | |
2890 | * them here, since they were duplicated as part of the suspend | |
2891 | * procedure. | |
2892 | */ | |
a80aa93d | 2893 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { |
fcb4019e LSL |
2894 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
2895 | if (dm_new_crtc_state->stream) { | |
2896 | WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); | |
2897 | dc_stream_release(dm_new_crtc_state->stream); | |
2898 | dm_new_crtc_state->stream = NULL; | |
2899 | } | |
2900 | } | |
2901 | ||
a80aa93d | 2902 | for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { |
fcb4019e LSL |
2903 | dm_new_plane_state = to_dm_plane_state(new_plane_state); |
2904 | if (dm_new_plane_state->dc_state) { | |
2905 | WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); | |
2906 | dc_plane_state_release(dm_new_plane_state->dc_state); | |
2907 | dm_new_plane_state->dc_state = NULL; | |
2908 | } | |
2909 | } | |
2910 | ||
2d1af6a1 | 2911 | drm_atomic_helper_resume(ddev, dm->cached_state); |
4562236b | 2912 | |
a80aa93d | 2913 | dm->cached_state = NULL; |
0a214e2f | 2914 | |
9faa4237 | 2915 | amdgpu_dm_irq_resume_late(adev); |
4562236b | 2916 | |
9340dfd3 HW |
2917 | amdgpu_dm_smu_write_watermarks_table(adev); |
2918 | ||
2d1af6a1 | 2919 | return 0; |
4562236b HW |
2920 | } |
2921 | ||
b8592b48 LL |
2922 | /** |
2923 | * DOC: DM Lifecycle | |
2924 | * | |
2925 | * DM (and consequently DC) is registered in the amdgpu base driver as a IP | |
2926 | * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to | |
2927 | * the base driver's device list to be initialized and torn down accordingly. | |
2928 | * | |
2929 | * The functions to do so are provided as hooks in &struct amd_ip_funcs. | |
2930 | */ | |
2931 | ||
4562236b HW |
2932 | static const struct amd_ip_funcs amdgpu_dm_funcs = { |
2933 | .name = "dm", | |
2934 | .early_init = dm_early_init, | |
7abcf6b5 | 2935 | .late_init = dm_late_init, |
4562236b HW |
2936 | .sw_init = dm_sw_init, |
2937 | .sw_fini = dm_sw_fini, | |
e9669fb7 | 2938 | .early_fini = amdgpu_dm_early_fini, |
4562236b HW |
2939 | .hw_init = dm_hw_init, |
2940 | .hw_fini = dm_hw_fini, | |
2941 | .suspend = dm_suspend, | |
2942 | .resume = dm_resume, | |
2943 | .is_idle = dm_is_idle, | |
2944 | .wait_for_idle = dm_wait_for_idle, | |
2945 | .check_soft_reset = dm_check_soft_reset, | |
2946 | .soft_reset = dm_soft_reset, | |
2947 | .set_clockgating_state = dm_set_clockgating_state, | |
2948 | .set_powergating_state = dm_set_powergating_state, | |
2949 | }; | |
2950 | ||
c82eddf8 | 2951 | const struct amdgpu_ip_block_version dm_ip_block = { |
4562236b HW |
2952 | .type = AMD_IP_BLOCK_TYPE_DCE, |
2953 | .major = 1, | |
2954 | .minor = 0, | |
2955 | .rev = 0, | |
2956 | .funcs = &amdgpu_dm_funcs, | |
2957 | }; | |
2958 | ||
ca3268c4 | 2959 | |
b8592b48 LL |
2960 | /** |
2961 | * DOC: atomic | |
2962 | * | |
2963 | * *WIP* | |
2964 | */ | |
0a323b84 | 2965 | |
b3663f70 | 2966 | static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { |
4d4772f6 | 2967 | .fb_create = amdgpu_display_user_framebuffer_create, |
8bf0d9cd | 2968 | .get_format_info = amdgpu_dm_plane_get_format_info, |
4562236b | 2969 | .atomic_check = amdgpu_dm_atomic_check, |
0269764a | 2970 | .atomic_commit = drm_atomic_helper_commit, |
54f5499a AG |
2971 | }; |
2972 | ||
2973 | static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { | |
a5c2c0d1 LP |
2974 | .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, |
2975 | .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, | |
4562236b HW |
2976 | }; |
2977 | ||
94562810 RS |
2978 | static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) |
2979 | { | |
94562810 | 2980 | struct amdgpu_dm_backlight_caps *caps; |
94562810 RS |
2981 | struct drm_connector *conn_base; |
2982 | struct amdgpu_device *adev; | |
a61bb342 | 2983 | struct drm_luminance_range_info *luminance_range; |
94562810 | 2984 | |
f196198c HG |
2985 | if (aconnector->bl_idx == -1 || |
2986 | aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) | |
ec11fe37 | 2987 | return; |
2988 | ||
94562810 | 2989 | conn_base = &aconnector->base; |
1348969a | 2990 | adev = drm_to_adev(conn_base->dev); |
f196198c HG |
2991 | |
2992 | caps = &adev->dm.backlight_caps[aconnector->bl_idx]; | |
94562810 RS |
2993 | caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; |
2994 | caps->aux_support = false; | |
94562810 | 2995 | |
c82eddf8 SS |
2996 | if (caps->ext_caps->bits.oled == 1 |
2997 | /* | |
2998 | * || | |
2999 | * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || | |
3000 | * caps->ext_caps->bits.hdr_aux_backlight_control == 1 | |
3001 | */) | |
94562810 RS |
3002 | caps->aux_support = true; |
3003 | ||
7a46f05e TI |
3004 | if (amdgpu_backlight == 0) |
3005 | caps->aux_support = false; | |
3006 | else if (amdgpu_backlight == 1) | |
3007 | caps->aux_support = true; | |
3008 | ||
a61bb342 | 3009 | luminance_range = &conn_base->display_info.luminance_range; |
932698c8 SP |
3010 | |
3011 | if (luminance_range->max_luminance) { | |
3012 | caps->aux_min_input_signal = luminance_range->min_luminance; | |
3013 | caps->aux_max_input_signal = luminance_range->max_luminance; | |
3014 | } else { | |
3015 | caps->aux_min_input_signal = 0; | |
3016 | caps->aux_max_input_signal = 512; | |
3017 | } | |
94562810 RS |
3018 | } |
3019 | ||
97e51c16 HW |
3020 | void amdgpu_dm_update_connector_after_detect( |
3021 | struct amdgpu_dm_connector *aconnector) | |
4562236b HW |
3022 | { |
3023 | struct drm_connector *connector = &aconnector->base; | |
3024 | struct drm_device *dev = connector->dev; | |
b73a22d3 | 3025 | struct dc_sink *sink; |
4562236b HW |
3026 | |
3027 | /* MST handled by drm_mst framework */ | |
3028 | if (aconnector->mst_mgr.mst_state == true) | |
3029 | return; | |
3030 | ||
4562236b | 3031 | sink = aconnector->dc_link->local_sink; |
dcd5fb82 MF |
3032 | if (sink) |
3033 | dc_sink_retain(sink); | |
4562236b | 3034 | |
1f6010a9 DF |
3035 | /* |
3036 | * Edid mgmt connector gets first update only in mode_valid hook and then | |
4562236b | 3037 | * the connector sink is set to either fake or physical sink depends on link status. |
1f6010a9 | 3038 | * Skip if already done during boot. |
4562236b HW |
3039 | */ |
3040 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED | |
3041 | && aconnector->dc_em_sink) { | |
3042 | ||
1f6010a9 DF |
3043 | /* |
3044 | * For S3 resume with headless use eml_sink to fake stream | |
3045 | * because on resume connector->sink is set to NULL | |
4562236b HW |
3046 | */ |
3047 | mutex_lock(&dev->mode_config.mutex); | |
3048 | ||
3049 | if (sink) { | |
922aa1e1 | 3050 | if (aconnector->dc_sink) { |
98e6436d | 3051 | amdgpu_dm_update_freesync_caps(connector, NULL); |
1f6010a9 DF |
3052 | /* |
3053 | * retain and release below are used to | |
3054 | * bump up refcount for sink because the link doesn't point | |
3055 | * to it anymore after disconnect, so on next crtc to connector | |
922aa1e1 AG |
3056 | * reshuffle by UMD we will get into unwanted dc_sink release |
3057 | */ | |
dcd5fb82 | 3058 | dc_sink_release(aconnector->dc_sink); |
922aa1e1 | 3059 | } |
4562236b | 3060 | aconnector->dc_sink = sink; |
dcd5fb82 | 3061 | dc_sink_retain(aconnector->dc_sink); |
98e6436d AK |
3062 | amdgpu_dm_update_freesync_caps(connector, |
3063 | aconnector->edid); | |
4562236b | 3064 | } else { |
98e6436d | 3065 | amdgpu_dm_update_freesync_caps(connector, NULL); |
dcd5fb82 | 3066 | if (!aconnector->dc_sink) { |
4562236b | 3067 | aconnector->dc_sink = aconnector->dc_em_sink; |
922aa1e1 | 3068 | dc_sink_retain(aconnector->dc_sink); |
dcd5fb82 | 3069 | } |
4562236b HW |
3070 | } |
3071 | ||
3072 | mutex_unlock(&dev->mode_config.mutex); | |
dcd5fb82 MF |
3073 | |
3074 | if (sink) | |
3075 | dc_sink_release(sink); | |
4562236b HW |
3076 | return; |
3077 | } | |
3078 | ||
3079 | /* | |
3080 | * TODO: temporary guard to look for proper fix | |
3081 | * if this sink is MST sink, we should not do anything | |
3082 | */ | |
dcd5fb82 MF |
3083 | if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { |
3084 | dc_sink_release(sink); | |
4562236b | 3085 | return; |
dcd5fb82 | 3086 | } |
4562236b HW |
3087 | |
3088 | if (aconnector->dc_sink == sink) { | |
1f6010a9 DF |
3089 | /* |
3090 | * We got a DP short pulse (Link Loss, DP CTS, etc...). | |
3091 | * Do nothing!! | |
3092 | */ | |
f1ad2f5e | 3093 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", |
4562236b | 3094 | aconnector->connector_id); |
dcd5fb82 MF |
3095 | if (sink) |
3096 | dc_sink_release(sink); | |
4562236b HW |
3097 | return; |
3098 | } | |
3099 | ||
f1ad2f5e | 3100 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", |
4562236b HW |
3101 | aconnector->connector_id, aconnector->dc_sink, sink); |
3102 | ||
3103 | mutex_lock(&dev->mode_config.mutex); | |
3104 | ||
1f6010a9 DF |
3105 | /* |
3106 | * 1. Update status of the drm connector | |
3107 | * 2. Send an event and let userspace tell us what to do | |
3108 | */ | |
4562236b | 3109 | if (sink) { |
1f6010a9 DF |
3110 | /* |
3111 | * TODO: check if we still need the S3 mode update workaround. | |
3112 | * If yes, put it here. | |
3113 | */ | |
c64b0d6b | 3114 | if (aconnector->dc_sink) { |
98e6436d | 3115 | amdgpu_dm_update_freesync_caps(connector, NULL); |
c64b0d6b VL |
3116 | dc_sink_release(aconnector->dc_sink); |
3117 | } | |
4562236b HW |
3118 | |
3119 | aconnector->dc_sink = sink; | |
dcd5fb82 | 3120 | dc_sink_retain(aconnector->dc_sink); |
900b3cb1 | 3121 | if (sink->dc_edid.length == 0) { |
4562236b | 3122 | aconnector->edid = NULL; |
e6142dd5 AP |
3123 | if (aconnector->dc_link->aux_mode) { |
3124 | drm_dp_cec_unset_edid( | |
3125 | &aconnector->dm_dp_aux.aux); | |
3126 | } | |
900b3cb1 | 3127 | } else { |
4562236b | 3128 | aconnector->edid = |
e6142dd5 | 3129 | (struct edid *)sink->dc_edid.raw_edid; |
4562236b | 3130 | |
e6142dd5 AP |
3131 | if (aconnector->dc_link->aux_mode) |
3132 | drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, | |
3133 | aconnector->edid); | |
4562236b | 3134 | } |
e6142dd5 | 3135 | |
025ce392 HW |
3136 | if (!aconnector->timing_requested) { |
3137 | aconnector->timing_requested = | |
3138 | kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); | |
3139 | if (!aconnector->timing_requested) | |
3140 | dm_error("failed to create aconnector->requested_timing\n"); | |
3141 | } | |
028c4ccf | 3142 | |
20543be9 | 3143 | drm_connector_update_edid_property(connector, aconnector->edid); |
98e6436d | 3144 | amdgpu_dm_update_freesync_caps(connector, aconnector->edid); |
94562810 | 3145 | update_connector_ext_caps(aconnector); |
4562236b | 3146 | } else { |
e86e8947 | 3147 | drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); |
98e6436d | 3148 | amdgpu_dm_update_freesync_caps(connector, NULL); |
c555f023 | 3149 | drm_connector_update_edid_property(connector, NULL); |
4562236b | 3150 | aconnector->num_modes = 0; |
dcd5fb82 | 3151 | dc_sink_release(aconnector->dc_sink); |
4562236b | 3152 | aconnector->dc_sink = NULL; |
5326c452 | 3153 | aconnector->edid = NULL; |
028c4ccf QZ |
3154 | kfree(aconnector->timing_requested); |
3155 | aconnector->timing_requested = NULL; | |
0c8620d6 BL |
3156 | /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ |
3157 | if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) | |
3158 | connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
4562236b HW |
3159 | } |
3160 | ||
3161 | mutex_unlock(&dev->mode_config.mutex); | |
dcd5fb82 | 3162 | |
0f877894 OV |
3163 | update_subconnector_property(aconnector); |
3164 | ||
dcd5fb82 MF |
3165 | if (sink) |
3166 | dc_sink_release(sink); | |
4562236b HW |
3167 | } |
3168 | ||
e27c41d5 | 3169 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) |
4562236b | 3170 | { |
4562236b HW |
3171 | struct drm_connector *connector = &aconnector->base; |
3172 | struct drm_device *dev = connector->dev; | |
fbbdadf2 | 3173 | enum dc_connection_type new_connection_type = dc_connection_none; |
1348969a | 3174 | struct amdgpu_device *adev = drm_to_adev(dev); |
97f6c917 | 3175 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); |
15c735e7 | 3176 | bool ret = false; |
4562236b | 3177 | |
b972b4f9 HW |
3178 | if (adev->dm.disable_hpd_irq) |
3179 | return; | |
3180 | ||
1f6010a9 DF |
3181 | /* |
3182 | * In case of failure or MST no need to update connector status or notify the OS | |
3183 | * since (for MST case) MST does this in its own context. | |
4562236b HW |
3184 | */ |
3185 | mutex_lock(&aconnector->hpd_lock); | |
2e0ac3d6 | 3186 | |
97f6c917 | 3187 | if (adev->dm.hdcp_workqueue) { |
96a3b32e | 3188 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); |
97f6c917 BL |
3189 | dm_con_state->update_hdcp = true; |
3190 | } | |
2e0ac3d6 HW |
3191 | if (aconnector->fake_enable) |
3192 | aconnector->fake_enable = false; | |
3193 | ||
028c4ccf QZ |
3194 | aconnector->timing_changed = false; |
3195 | ||
54618888 | 3196 | if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) |
fbbdadf2 BL |
3197 | DRM_ERROR("KMS: Failed to detect connector\n"); |
3198 | ||
3199 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
3200 | emulated_link_detect(aconnector->dc_link); | |
3201 | ||
fbbdadf2 BL |
3202 | drm_modeset_lock_all(dev); |
3203 | dm_restore_drm_connector_state(dev, connector); | |
3204 | drm_modeset_unlock_all(dev); | |
3205 | ||
3206 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) | |
fc320a6f | 3207 | drm_kms_helper_connector_hotplug_event(connector); |
15c735e7 WL |
3208 | } else { |
3209 | mutex_lock(&adev->dm.dc_lock); | |
3210 | ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); | |
3211 | mutex_unlock(&adev->dm.dc_lock); | |
3212 | if (ret) { | |
3213 | amdgpu_dm_update_connector_after_detect(aconnector); | |
fbbdadf2 | 3214 | |
15c735e7 WL |
3215 | drm_modeset_lock_all(dev); |
3216 | dm_restore_drm_connector_state(dev, connector); | |
3217 | drm_modeset_unlock_all(dev); | |
4562236b | 3218 | |
15c735e7 WL |
3219 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) |
3220 | drm_kms_helper_connector_hotplug_event(connector); | |
3221 | } | |
4562236b HW |
3222 | } |
3223 | mutex_unlock(&aconnector->hpd_lock); | |
3224 | ||
3225 | } | |
3226 | ||
e27c41d5 JS |
3227 | static void handle_hpd_irq(void *param) |
3228 | { | |
3229 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; | |
3230 | ||
3231 | handle_hpd_irq_helper(aconnector); | |
3232 | ||
3233 | } | |
3234 | ||
8e794421 | 3235 | static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) |
4562236b | 3236 | { |
ae67558b SS |
3237 | u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; |
3238 | u8 dret; | |
4562236b HW |
3239 | bool new_irq_handled = false; |
3240 | int dpcd_addr; | |
3241 | int dpcd_bytes_to_read; | |
3242 | ||
3243 | const int max_process_count = 30; | |
3244 | int process_count = 0; | |
3245 | ||
3246 | const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); | |
3247 | ||
3248 | if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { | |
3249 | dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; | |
3250 | /* DPCD 0x200 - 0x201 for downstream IRQ */ | |
3251 | dpcd_addr = DP_SINK_COUNT; | |
3252 | } else { | |
3253 | dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; | |
3254 | /* DPCD 0x2002 - 0x2005 for downstream IRQ */ | |
3255 | dpcd_addr = DP_SINK_COUNT_ESI; | |
3256 | } | |
3257 | ||
3258 | dret = drm_dp_dpcd_read( | |
3259 | &aconnector->dm_dp_aux.aux, | |
3260 | dpcd_addr, | |
3261 | esi, | |
3262 | dpcd_bytes_to_read); | |
3263 | ||
3264 | while (dret == dpcd_bytes_to_read && | |
3265 | process_count < max_process_count) { | |
72f1de49 | 3266 | u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {}; |
ae67558b | 3267 | u8 retry; |
c82eddf8 | 3268 | |
4562236b HW |
3269 | dret = 0; |
3270 | ||
3271 | process_count++; | |
3272 | ||
f1ad2f5e | 3273 | DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
4562236b HW |
3274 | /* handle HPD short pulse irq */ |
3275 | if (aconnector->mst_mgr.mst_state) | |
72f1de49 WL |
3276 | drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, |
3277 | esi, | |
3278 | ack, | |
3279 | &new_irq_handled); | |
4562236b HW |
3280 | |
3281 | if (new_irq_handled) { | |
3282 | /* ACK at DPCD to notify down stream */ | |
4562236b | 3283 | for (retry = 0; retry < 3; retry++) { |
72f1de49 WL |
3284 | ssize_t wret; |
3285 | ||
3286 | wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux, | |
3287 | dpcd_addr + 1, | |
3288 | ack[1]); | |
3289 | if (wret == 1) | |
4562236b HW |
3290 | break; |
3291 | } | |
3292 | ||
72f1de49 WL |
3293 | if (retry == 3) { |
3294 | DRM_ERROR("Failed to ack MST event.\n"); | |
3295 | return; | |
3296 | } | |
3297 | ||
3298 | drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); | |
1f6010a9 | 3299 | /* check if there is new irq to be handled */ |
4562236b HW |
3300 | dret = drm_dp_dpcd_read( |
3301 | &aconnector->dm_dp_aux.aux, | |
3302 | dpcd_addr, | |
3303 | esi, | |
3304 | dpcd_bytes_to_read); | |
3305 | ||
3306 | new_irq_handled = false; | |
d4a6e8a9 | 3307 | } else { |
4562236b | 3308 | break; |
d4a6e8a9 | 3309 | } |
4562236b HW |
3310 | } |
3311 | ||
3312 | if (process_count == max_process_count) | |
f1ad2f5e | 3313 | DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); |
4562236b HW |
3314 | } |
3315 | ||
8e794421 WL |
3316 | static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, |
3317 | union hpd_irq_data hpd_irq_data) | |
3318 | { | |
3319 | struct hpd_rx_irq_offload_work *offload_work = | |
3320 | kzalloc(sizeof(*offload_work), GFP_KERNEL); | |
3321 | ||
3322 | if (!offload_work) { | |
3323 | DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); | |
3324 | return; | |
3325 | } | |
3326 | ||
3327 | INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); | |
3328 | offload_work->data = hpd_irq_data; | |
3329 | offload_work->offload_wq = offload_wq; | |
3330 | ||
3331 | queue_work(offload_wq->wq, &offload_work->work); | |
3332 | DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); | |
3333 | } | |
3334 | ||
4562236b HW |
3335 | static void handle_hpd_rx_irq(void *param) |
3336 | { | |
c84dec2f | 3337 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
4562236b HW |
3338 | struct drm_connector *connector = &aconnector->base; |
3339 | struct drm_device *dev = connector->dev; | |
53cbf65c | 3340 | struct dc_link *dc_link = aconnector->dc_link; |
4562236b | 3341 | bool is_mst_root_connector = aconnector->mst_mgr.mst_state; |
c8ea79a8 | 3342 | bool result = false; |
fbbdadf2 | 3343 | enum dc_connection_type new_connection_type = dc_connection_none; |
c8ea79a8 | 3344 | struct amdgpu_device *adev = drm_to_adev(dev); |
2a0f9270 | 3345 | union hpd_irq_data hpd_irq_data; |
8e794421 WL |
3346 | bool link_loss = false; |
3347 | bool has_left_work = false; | |
e322843e | 3348 | int idx = dc_link->link_index; |
8e794421 | 3349 | struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; |
2a0f9270 BL |
3350 | |
3351 | memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); | |
4562236b | 3352 | |
b972b4f9 HW |
3353 | if (adev->dm.disable_hpd_irq) |
3354 | return; | |
3355 | ||
1f6010a9 DF |
3356 | /* |
3357 | * TODO:Temporary add mutex to protect hpd interrupt not have a gpio | |
4562236b HW |
3358 | * conflict, after implement i2c helper, this mutex should be |
3359 | * retired. | |
3360 | */ | |
b86e7eef | 3361 | mutex_lock(&aconnector->hpd_lock); |
4562236b | 3362 | |
8e794421 WL |
3363 | result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, |
3364 | &link_loss, true, &has_left_work); | |
3083a984 | 3365 | |
8e794421 WL |
3366 | if (!has_left_work) |
3367 | goto out; | |
3368 | ||
3369 | if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { | |
3370 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); | |
3371 | goto out; | |
3372 | } | |
3373 | ||
3374 | if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { | |
3375 | if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || | |
3376 | hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { | |
3377 | dm_handle_mst_sideband_msg(aconnector); | |
3083a984 QZ |
3378 | goto out; |
3379 | } | |
3083a984 | 3380 | |
8e794421 WL |
3381 | if (link_loss) { |
3382 | bool skip = false; | |
d2aa1356 | 3383 | |
8e794421 WL |
3384 | spin_lock(&offload_wq->offload_lock); |
3385 | skip = offload_wq->is_handling_link_loss; | |
3386 | ||
3387 | if (!skip) | |
3388 | offload_wq->is_handling_link_loss = true; | |
3389 | ||
3390 | spin_unlock(&offload_wq->offload_lock); | |
3391 | ||
3392 | if (!skip) | |
3393 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); | |
3394 | ||
3395 | goto out; | |
3396 | } | |
3397 | } | |
c8ea79a8 | 3398 | |
3083a984 | 3399 | out: |
c8ea79a8 | 3400 | if (result && !is_mst_root_connector) { |
4562236b | 3401 | /* Downstream Port status changed. */ |
54618888 | 3402 | if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) |
fbbdadf2 BL |
3403 | DRM_ERROR("KMS: Failed to detect connector\n"); |
3404 | ||
3405 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
3406 | emulated_link_detect(dc_link); | |
3407 | ||
3408 | if (aconnector->fake_enable) | |
3409 | aconnector->fake_enable = false; | |
3410 | ||
3411 | amdgpu_dm_update_connector_after_detect(aconnector); | |
3412 | ||
3413 | ||
3414 | drm_modeset_lock_all(dev); | |
3415 | dm_restore_drm_connector_state(dev, connector); | |
3416 | drm_modeset_unlock_all(dev); | |
3417 | ||
fc320a6f | 3418 | drm_kms_helper_connector_hotplug_event(connector); |
15c735e7 WL |
3419 | } else { |
3420 | bool ret = false; | |
88ac3dda | 3421 | |
15c735e7 WL |
3422 | mutex_lock(&adev->dm.dc_lock); |
3423 | ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); | |
3424 | mutex_unlock(&adev->dm.dc_lock); | |
88ac3dda | 3425 | |
15c735e7 WL |
3426 | if (ret) { |
3427 | if (aconnector->fake_enable) | |
3428 | aconnector->fake_enable = false; | |
4562236b | 3429 | |
15c735e7 | 3430 | amdgpu_dm_update_connector_after_detect(aconnector); |
4562236b | 3431 | |
15c735e7 WL |
3432 | drm_modeset_lock_all(dev); |
3433 | dm_restore_drm_connector_state(dev, connector); | |
3434 | drm_modeset_unlock_all(dev); | |
4562236b | 3435 | |
15c735e7 WL |
3436 | drm_kms_helper_connector_hotplug_event(connector); |
3437 | } | |
4562236b HW |
3438 | } |
3439 | } | |
95f247e7 DC |
3440 | if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { |
3441 | if (adev->dm.hdcp_workqueue) | |
3442 | hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); | |
3443 | } | |
4562236b | 3444 | |
b86e7eef | 3445 | if (dc_link->type != dc_connection_mst_branch) |
e86e8947 | 3446 | drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); |
b86e7eef NC |
3447 | |
3448 | mutex_unlock(&aconnector->hpd_lock); | |
4562236b HW |
3449 | } |
3450 | ||
3451 | static void register_hpd_handlers(struct amdgpu_device *adev) | |
3452 | { | |
4a580877 | 3453 | struct drm_device *dev = adev_to_drm(adev); |
4562236b | 3454 | struct drm_connector *connector; |
c84dec2f | 3455 | struct amdgpu_dm_connector *aconnector; |
4562236b HW |
3456 | const struct dc_link *dc_link; |
3457 | struct dc_interrupt_params int_params = {0}; | |
3458 | ||
3459 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3460 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3461 | ||
3462 | list_for_each_entry(connector, | |
3463 | &dev->mode_config.connector_list, head) { | |
3464 | ||
c84dec2f | 3465 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b HW |
3466 | dc_link = aconnector->dc_link; |
3467 | ||
c82eddf8 | 3468 | if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { |
4562236b HW |
3469 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; |
3470 | int_params.irq_source = dc_link->irq_source_hpd; | |
3471 | ||
3472 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3473 | handle_hpd_irq, | |
3474 | (void *) aconnector); | |
3475 | } | |
3476 | ||
c82eddf8 | 3477 | if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { |
4562236b HW |
3478 | |
3479 | /* Also register for DP short pulse (hpd_rx). */ | |
3480 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
3481 | int_params.irq_source = dc_link->irq_source_hpd_rx; | |
3482 | ||
3483 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3484 | handle_hpd_rx_irq, | |
3485 | (void *) aconnector); | |
8e794421 WL |
3486 | |
3487 | if (adev->dm.hpd_rx_offload_wq) | |
e322843e | 3488 | adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector = |
8e794421 | 3489 | aconnector; |
4562236b HW |
3490 | } |
3491 | } | |
3492 | } | |
3493 | ||
55e56389 MR |
3494 | #if defined(CONFIG_DRM_AMD_DC_SI) |
3495 | /* Register IRQ sources and initialize IRQ callbacks */ | |
3496 | static int dce60_register_irq_handlers(struct amdgpu_device *adev) | |
3497 | { | |
3498 | struct dc *dc = adev->dm.dc; | |
3499 | struct common_irq_params *c_irq_params; | |
3500 | struct dc_interrupt_params int_params = {0}; | |
3501 | int r; | |
3502 | int i; | |
c82eddf8 | 3503 | unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
55e56389 MR |
3504 | |
3505 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3506 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3507 | ||
3508 | /* | |
3509 | * Actions of amdgpu_irq_add_id(): | |
3510 | * 1. Register a set() function with base driver. | |
3511 | * Base driver will call set() function to enable/disable an | |
3512 | * interrupt in DC hardware. | |
3513 | * 2. Register amdgpu_dm_irq_handler(). | |
3514 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3515 | * coming from DC hardware. | |
3516 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
c82eddf8 SS |
3517 | * for acknowledging and handling. |
3518 | */ | |
55e56389 MR |
3519 | |
3520 | /* Use VBLANK interrupt */ | |
3521 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
c82eddf8 | 3522 | r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); |
55e56389 MR |
3523 | if (r) { |
3524 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3525 | return r; | |
3526 | } | |
3527 | ||
3528 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3529 | int_params.irq_source = | |
c82eddf8 | 3530 | dc_interrupt_to_irq_source(dc, i + 1, 0); |
55e56389 MR |
3531 | |
3532 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; | |
3533 | ||
3534 | c_irq_params->adev = adev; | |
3535 | c_irq_params->irq_src = int_params.irq_source; | |
3536 | ||
3537 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3538 | dm_crtc_high_irq, c_irq_params); | |
3539 | } | |
3540 | ||
3541 | /* Use GRPH_PFLIP interrupt */ | |
3542 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; | |
3543 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { | |
3544 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); | |
3545 | if (r) { | |
3546 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3547 | return r; | |
3548 | } | |
3549 | ||
3550 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3551 | int_params.irq_source = | |
3552 | dc_interrupt_to_irq_source(dc, i, 0); | |
3553 | ||
3554 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3555 | ||
3556 | c_irq_params->adev = adev; | |
3557 | c_irq_params->irq_src = int_params.irq_source; | |
3558 | ||
3559 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3560 | dm_pflip_high_irq, c_irq_params); | |
3561 | ||
3562 | } | |
3563 | ||
3564 | /* HPD */ | |
3565 | r = amdgpu_irq_add_id(adev, client_id, | |
3566 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); | |
3567 | if (r) { | |
3568 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3569 | return r; | |
3570 | } | |
3571 | ||
3572 | register_hpd_handlers(adev); | |
3573 | ||
3574 | return 0; | |
3575 | } | |
3576 | #endif | |
3577 | ||
4562236b HW |
3578 | /* Register IRQ sources and initialize IRQ callbacks */ |
3579 | static int dce110_register_irq_handlers(struct amdgpu_device *adev) | |
3580 | { | |
3581 | struct dc *dc = adev->dm.dc; | |
3582 | struct common_irq_params *c_irq_params; | |
3583 | struct dc_interrupt_params int_params = {0}; | |
3584 | int r; | |
3585 | int i; | |
c82eddf8 | 3586 | unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
2c8ad2d5 | 3587 | |
c08182f2 | 3588 | if (adev->family >= AMDGPU_FAMILY_AI) |
3760f76c | 3589 | client_id = SOC15_IH_CLIENTID_DCE; |
4562236b HW |
3590 | |
3591 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3592 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3593 | ||
1f6010a9 DF |
3594 | /* |
3595 | * Actions of amdgpu_irq_add_id(): | |
4562236b HW |
3596 | * 1. Register a set() function with base driver. |
3597 | * Base driver will call set() function to enable/disable an | |
3598 | * interrupt in DC hardware. | |
3599 | * 2. Register amdgpu_dm_irq_handler(). | |
3600 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3601 | * coming from DC hardware. | |
3602 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
c82eddf8 SS |
3603 | * for acknowledging and handling. |
3604 | */ | |
4562236b | 3605 | |
b57de80a | 3606 | /* Use VBLANK interrupt */ |
e9029155 | 3607 | for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { |
2c8ad2d5 | 3608 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); |
4562236b HW |
3609 | if (r) { |
3610 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3611 | return r; | |
3612 | } | |
3613 | ||
3614 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3615 | int_params.irq_source = | |
3d761e79 | 3616 | dc_interrupt_to_irq_source(dc, i, 0); |
4562236b | 3617 | |
b57de80a | 3618 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
4562236b HW |
3619 | |
3620 | c_irq_params->adev = adev; | |
3621 | c_irq_params->irq_src = int_params.irq_source; | |
3622 | ||
3623 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3624 | dm_crtc_high_irq, c_irq_params); | |
3625 | } | |
3626 | ||
d2574c33 MK |
3627 | /* Use VUPDATE interrupt */ |
3628 | for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { | |
3629 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); | |
3630 | if (r) { | |
3631 | DRM_ERROR("Failed to add vupdate irq id!\n"); | |
3632 | return r; | |
3633 | } | |
3634 | ||
3635 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3636 | int_params.irq_source = | |
3637 | dc_interrupt_to_irq_source(dc, i, 0); | |
3638 | ||
3639 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; | |
3640 | ||
3641 | c_irq_params->adev = adev; | |
3642 | c_irq_params->irq_src = int_params.irq_source; | |
3643 | ||
3644 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3645 | dm_vupdate_high_irq, c_irq_params); | |
3646 | } | |
3647 | ||
3d761e79 | 3648 | /* Use GRPH_PFLIP interrupt */ |
4562236b HW |
3649 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; |
3650 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { | |
2c8ad2d5 | 3651 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); |
4562236b HW |
3652 | if (r) { |
3653 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3654 | return r; | |
3655 | } | |
3656 | ||
3657 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3658 | int_params.irq_source = | |
3659 | dc_interrupt_to_irq_source(dc, i, 0); | |
3660 | ||
3661 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3662 | ||
3663 | c_irq_params->adev = adev; | |
3664 | c_irq_params->irq_src = int_params.irq_source; | |
3665 | ||
3666 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3667 | dm_pflip_high_irq, c_irq_params); | |
3668 | ||
3669 | } | |
3670 | ||
3671 | /* HPD */ | |
2c8ad2d5 AD |
3672 | r = amdgpu_irq_add_id(adev, client_id, |
3673 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); | |
4562236b HW |
3674 | if (r) { |
3675 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3676 | return r; | |
3677 | } | |
3678 | ||
3679 | register_hpd_handlers(adev); | |
3680 | ||
3681 | return 0; | |
3682 | } | |
3683 | ||
ff5ef992 AD |
3684 | /* Register IRQ sources and initialize IRQ callbacks */ |
3685 | static int dcn10_register_irq_handlers(struct amdgpu_device *adev) | |
3686 | { | |
3687 | struct dc *dc = adev->dm.dc; | |
3688 | struct common_irq_params *c_irq_params; | |
3689 | struct dc_interrupt_params int_params = {0}; | |
3690 | int r; | |
3691 | int i; | |
660d5406 WL |
3692 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
3693 | static const unsigned int vrtl_int_srcid[] = { | |
3694 | DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, | |
3695 | DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, | |
3696 | DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, | |
3697 | DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, | |
3698 | DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, | |
3699 | DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL | |
3700 | }; | |
3701 | #endif | |
ff5ef992 AD |
3702 | |
3703 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3704 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3705 | ||
1f6010a9 DF |
3706 | /* |
3707 | * Actions of amdgpu_irq_add_id(): | |
ff5ef992 AD |
3708 | * 1. Register a set() function with base driver. |
3709 | * Base driver will call set() function to enable/disable an | |
3710 | * interrupt in DC hardware. | |
3711 | * 2. Register amdgpu_dm_irq_handler(). | |
3712 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
3713 | * coming from DC hardware. | |
3714 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
3715 | * for acknowledging and handling. | |
1f6010a9 | 3716 | */ |
ff5ef992 AD |
3717 | |
3718 | /* Use VSTARTUP interrupt */ | |
3719 | for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; | |
3720 | i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; | |
3721 | i++) { | |
3760f76c | 3722 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); |
ff5ef992 AD |
3723 | |
3724 | if (r) { | |
3725 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
3726 | return r; | |
3727 | } | |
3728 | ||
3729 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3730 | int_params.irq_source = | |
3731 | dc_interrupt_to_irq_source(dc, i, 0); | |
3732 | ||
3733 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; | |
3734 | ||
3735 | c_irq_params->adev = adev; | |
3736 | c_irq_params->irq_src = int_params.irq_source; | |
3737 | ||
2346ef47 NK |
3738 | amdgpu_dm_irq_register_interrupt( |
3739 | adev, &int_params, dm_crtc_high_irq, c_irq_params); | |
3740 | } | |
3741 | ||
86bc2219 WL |
3742 | /* Use otg vertical line interrupt */ |
3743 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) | |
660d5406 WL |
3744 | for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { |
3745 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, | |
3746 | vrtl_int_srcid[i], &adev->vline0_irq); | |
86bc2219 WL |
3747 | |
3748 | if (r) { | |
3749 | DRM_ERROR("Failed to add vline0 irq id!\n"); | |
3750 | return r; | |
3751 | } | |
3752 | ||
3753 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3754 | int_params.irq_source = | |
660d5406 WL |
3755 | dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); |
3756 | ||
3757 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { | |
3758 | DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); | |
3759 | break; | |
3760 | } | |
86bc2219 WL |
3761 | |
3762 | c_irq_params = &adev->dm.vline0_params[int_params.irq_source | |
3763 | - DC_IRQ_SOURCE_DC1_VLINE0]; | |
3764 | ||
3765 | c_irq_params->adev = adev; | |
3766 | c_irq_params->irq_src = int_params.irq_source; | |
3767 | ||
3768 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3769 | dm_dcn_vertical_interrupt0_high_irq, c_irq_params); | |
3770 | } | |
3771 | #endif | |
3772 | ||
2346ef47 NK |
3773 | /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to |
3774 | * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx | |
3775 | * to trigger at end of each vblank, regardless of state of the lock, | |
3776 | * matching DCE behaviour. | |
3777 | */ | |
3778 | for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; | |
3779 | i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; | |
3780 | i++) { | |
3781 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); | |
3782 | ||
3783 | if (r) { | |
3784 | DRM_ERROR("Failed to add vupdate irq id!\n"); | |
3785 | return r; | |
3786 | } | |
3787 | ||
3788 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3789 | int_params.irq_source = | |
3790 | dc_interrupt_to_irq_source(dc, i, 0); | |
3791 | ||
3792 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; | |
3793 | ||
3794 | c_irq_params->adev = adev; | |
3795 | c_irq_params->irq_src = int_params.irq_source; | |
3796 | ||
ff5ef992 | 3797 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
2346ef47 | 3798 | dm_vupdate_high_irq, c_irq_params); |
d2574c33 MK |
3799 | } |
3800 | ||
ff5ef992 AD |
3801 | /* Use GRPH_PFLIP interrupt */ |
3802 | for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; | |
de95753c | 3803 | i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; |
ff5ef992 | 3804 | i++) { |
3760f76c | 3805 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); |
ff5ef992 AD |
3806 | if (r) { |
3807 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
3808 | return r; | |
3809 | } | |
3810 | ||
3811 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
3812 | int_params.irq_source = | |
3813 | dc_interrupt_to_irq_source(dc, i, 0); | |
3814 | ||
3815 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
3816 | ||
3817 | c_irq_params->adev = adev; | |
3818 | c_irq_params->irq_src = int_params.irq_source; | |
3819 | ||
3820 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
3821 | dm_pflip_high_irq, c_irq_params); | |
3822 | ||
3823 | } | |
3824 | ||
81927e28 JS |
3825 | /* HPD */ |
3826 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, | |
3827 | &adev->hpd_irq); | |
3828 | if (r) { | |
3829 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
3830 | return r; | |
3831 | } | |
a08f16cf | 3832 | |
81927e28 | 3833 | register_hpd_handlers(adev); |
a08f16cf | 3834 | |
81927e28 JS |
3835 | return 0; |
3836 | } | |
3837 | /* Register Outbox IRQ sources and initialize IRQ callbacks */ | |
3838 | static int register_outbox_irq_handlers(struct amdgpu_device *adev) | |
3839 | { | |
3840 | struct dc *dc = adev->dm.dc; | |
3841 | struct common_irq_params *c_irq_params; | |
3842 | struct dc_interrupt_params int_params = {0}; | |
3843 | int r, i; | |
3844 | ||
3845 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3846 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
3847 | ||
3848 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, | |
3849 | &adev->dmub_outbox_irq); | |
3850 | if (r) { | |
3851 | DRM_ERROR("Failed to add outbox irq id!\n"); | |
3852 | return r; | |
3853 | } | |
3854 | ||
3855 | if (dc->ctx->dmub_srv) { | |
3856 | i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; | |
3857 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
a08f16cf | 3858 | int_params.irq_source = |
81927e28 | 3859 | dc_interrupt_to_irq_source(dc, i, 0); |
a08f16cf | 3860 | |
81927e28 | 3861 | c_irq_params = &adev->dm.dmub_outbox_params[0]; |
a08f16cf LHM |
3862 | |
3863 | c_irq_params->adev = adev; | |
3864 | c_irq_params->irq_src = int_params.irq_source; | |
3865 | ||
3866 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
81927e28 | 3867 | dm_dmub_outbox1_low_irq, c_irq_params); |
ff5ef992 AD |
3868 | } |
3869 | ||
ff5ef992 AD |
3870 | return 0; |
3871 | } | |
ff5ef992 | 3872 | |
eb3dc897 NK |
3873 | /* |
3874 | * Acquires the lock for the atomic state object and returns | |
3875 | * the new atomic state. | |
3876 | * | |
3877 | * This should only be called during atomic check. | |
3878 | */ | |
17ce8a69 RL |
3879 | int dm_atomic_get_state(struct drm_atomic_state *state, |
3880 | struct dm_atomic_state **dm_state) | |
eb3dc897 NK |
3881 | { |
3882 | struct drm_device *dev = state->dev; | |
1348969a | 3883 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 NK |
3884 | struct amdgpu_display_manager *dm = &adev->dm; |
3885 | struct drm_private_state *priv_state; | |
eb3dc897 NK |
3886 | |
3887 | if (*dm_state) | |
3888 | return 0; | |
3889 | ||
eb3dc897 NK |
3890 | priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); |
3891 | if (IS_ERR(priv_state)) | |
3892 | return PTR_ERR(priv_state); | |
3893 | ||
3894 | *dm_state = to_dm_atomic_state(priv_state); | |
3895 | ||
3896 | return 0; | |
3897 | } | |
3898 | ||
dfd84d90 | 3899 | static struct dm_atomic_state * |
eb3dc897 NK |
3900 | dm_atomic_get_new_state(struct drm_atomic_state *state) |
3901 | { | |
3902 | struct drm_device *dev = state->dev; | |
1348969a | 3903 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 NK |
3904 | struct amdgpu_display_manager *dm = &adev->dm; |
3905 | struct drm_private_obj *obj; | |
3906 | struct drm_private_state *new_obj_state; | |
3907 | int i; | |
3908 | ||
3909 | for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { | |
3910 | if (obj->funcs == dm->atomic_obj.funcs) | |
3911 | return to_dm_atomic_state(new_obj_state); | |
3912 | } | |
3913 | ||
3914 | return NULL; | |
3915 | } | |
3916 | ||
eb3dc897 NK |
3917 | static struct drm_private_state * |
3918 | dm_atomic_duplicate_state(struct drm_private_obj *obj) | |
3919 | { | |
3920 | struct dm_atomic_state *old_state, *new_state; | |
3921 | ||
3922 | new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); | |
3923 | if (!new_state) | |
3924 | return NULL; | |
3925 | ||
3926 | __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); | |
3927 | ||
813d20dc AW |
3928 | old_state = to_dm_atomic_state(obj->state); |
3929 | ||
3930 | if (old_state && old_state->context) | |
3931 | new_state->context = dc_copy_state(old_state->context); | |
3932 | ||
eb3dc897 NK |
3933 | if (!new_state->context) { |
3934 | kfree(new_state); | |
3935 | return NULL; | |
3936 | } | |
3937 | ||
eb3dc897 NK |
3938 | return &new_state->base; |
3939 | } | |
3940 | ||
3941 | static void dm_atomic_destroy_state(struct drm_private_obj *obj, | |
3942 | struct drm_private_state *state) | |
3943 | { | |
3944 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); | |
3945 | ||
3946 | if (dm_state && dm_state->context) | |
3947 | dc_release_state(dm_state->context); | |
3948 | ||
3949 | kfree(dm_state); | |
3950 | } | |
3951 | ||
3952 | static struct drm_private_state_funcs dm_atomic_state_funcs = { | |
3953 | .atomic_duplicate_state = dm_atomic_duplicate_state, | |
3954 | .atomic_destroy_state = dm_atomic_destroy_state, | |
3955 | }; | |
3956 | ||
4562236b HW |
3957 | static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) |
3958 | { | |
eb3dc897 | 3959 | struct dm_atomic_state *state; |
4562236b HW |
3960 | int r; |
3961 | ||
3962 | adev->mode_info.mode_config_initialized = true; | |
3963 | ||
4a580877 LT |
3964 | adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; |
3965 | adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; | |
4562236b | 3966 | |
4a580877 LT |
3967 | adev_to_drm(adev)->mode_config.max_width = 16384; |
3968 | adev_to_drm(adev)->mode_config.max_height = 16384; | |
4562236b | 3969 | |
4a580877 | 3970 | adev_to_drm(adev)->mode_config.preferred_depth = 24; |
a6250bdb AD |
3971 | if (adev->asic_type == CHIP_HAWAII) |
3972 | /* disable prefer shadow for now due to hibernation issues */ | |
3973 | adev_to_drm(adev)->mode_config.prefer_shadow = 0; | |
3974 | else | |
3975 | adev_to_drm(adev)->mode_config.prefer_shadow = 1; | |
1f6010a9 | 3976 | /* indicates support for immediate flip */ |
4a580877 | 3977 | adev_to_drm(adev)->mode_config.async_page_flip = true; |
4562236b | 3978 | |
eb3dc897 NK |
3979 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
3980 | if (!state) | |
3981 | return -ENOMEM; | |
3982 | ||
813d20dc | 3983 | state->context = dc_create_state(adev->dm.dc); |
eb3dc897 NK |
3984 | if (!state->context) { |
3985 | kfree(state); | |
3986 | return -ENOMEM; | |
3987 | } | |
3988 | ||
3989 | dc_resource_state_copy_construct_current(adev->dm.dc, state->context); | |
3990 | ||
4a580877 | 3991 | drm_atomic_private_obj_init(adev_to_drm(adev), |
8c1a765b | 3992 | &adev->dm.atomic_obj, |
eb3dc897 NK |
3993 | &state->base, |
3994 | &dm_atomic_state_funcs); | |
3995 | ||
3dc9b1ce | 3996 | r = amdgpu_display_modeset_create_props(adev); |
b67a468a DL |
3997 | if (r) { |
3998 | dc_release_state(state->context); | |
3999 | kfree(state); | |
4562236b | 4000 | return r; |
b67a468a | 4001 | } |
4562236b | 4002 | |
6ce8f316 | 4003 | r = amdgpu_dm_audio_init(adev); |
b67a468a DL |
4004 | if (r) { |
4005 | dc_release_state(state->context); | |
4006 | kfree(state); | |
6ce8f316 | 4007 | return r; |
b67a468a | 4008 | } |
6ce8f316 | 4009 | |
4562236b HW |
4010 | return 0; |
4011 | } | |
4012 | ||
206bbafe DF |
4013 | #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 |
4014 | #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 | |
94562810 | 4015 | #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 |
206bbafe | 4016 | |
7fd13bae AD |
4017 | static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, |
4018 | int bl_idx) | |
206bbafe DF |
4019 | { |
4020 | #if defined(CONFIG_ACPI) | |
4021 | struct amdgpu_dm_backlight_caps caps; | |
4022 | ||
58965855 FS |
4023 | memset(&caps, 0, sizeof(caps)); |
4024 | ||
7fd13bae | 4025 | if (dm->backlight_caps[bl_idx].caps_valid) |
206bbafe DF |
4026 | return; |
4027 | ||
f9b7f370 | 4028 | amdgpu_acpi_get_backlight_caps(&caps); |
206bbafe | 4029 | if (caps.caps_valid) { |
7fd13bae | 4030 | dm->backlight_caps[bl_idx].caps_valid = true; |
94562810 RS |
4031 | if (caps.aux_support) |
4032 | return; | |
7fd13bae AD |
4033 | dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; |
4034 | dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; | |
206bbafe | 4035 | } else { |
7fd13bae | 4036 | dm->backlight_caps[bl_idx].min_input_signal = |
206bbafe | 4037 | AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
7fd13bae | 4038 | dm->backlight_caps[bl_idx].max_input_signal = |
206bbafe DF |
4039 | AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; |
4040 | } | |
4041 | #else | |
7fd13bae | 4042 | if (dm->backlight_caps[bl_idx].aux_support) |
94562810 RS |
4043 | return; |
4044 | ||
7fd13bae AD |
4045 | dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
4046 | dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; | |
206bbafe DF |
4047 | #endif |
4048 | } | |
4049 | ||
69d9f427 | 4050 | static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, |
c82eddf8 | 4051 | unsigned int *min, unsigned int *max) |
94562810 | 4052 | { |
94562810 | 4053 | if (!caps) |
69d9f427 | 4054 | return 0; |
94562810 | 4055 | |
69d9f427 AM |
4056 | if (caps->aux_support) { |
4057 | // Firmware limits are in nits, DC API wants millinits. | |
4058 | *max = 1000 * caps->aux_max_input_signal; | |
4059 | *min = 1000 * caps->aux_min_input_signal; | |
94562810 | 4060 | } else { |
69d9f427 AM |
4061 | // Firmware limits are 8-bit, PWM control is 16-bit. |
4062 | *max = 0x101 * caps->max_input_signal; | |
4063 | *min = 0x101 * caps->min_input_signal; | |
94562810 | 4064 | } |
69d9f427 AM |
4065 | return 1; |
4066 | } | |
94562810 | 4067 | |
69d9f427 AM |
4068 | static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, |
4069 | uint32_t brightness) | |
4070 | { | |
c82eddf8 | 4071 | unsigned int min, max; |
94562810 | 4072 | |
69d9f427 AM |
4073 | if (!get_brightness_range(caps, &min, &max)) |
4074 | return brightness; | |
4075 | ||
4076 | // Rescale 0..255 to min..max | |
4077 | return min + DIV_ROUND_CLOSEST((max - min) * brightness, | |
4078 | AMDGPU_MAX_BL_LEVEL); | |
4079 | } | |
4080 | ||
4081 | static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, | |
4082 | uint32_t brightness) | |
4083 | { | |
c82eddf8 | 4084 | unsigned int min, max; |
69d9f427 AM |
4085 | |
4086 | if (!get_brightness_range(caps, &min, &max)) | |
4087 | return brightness; | |
4088 | ||
4089 | if (brightness < min) | |
4090 | return 0; | |
4091 | // Rescale min..max to 0..255 | |
4092 | return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), | |
4093 | max - min); | |
94562810 RS |
4094 | } |
4095 | ||
4052287a | 4096 | static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, |
7fd13bae | 4097 | int bl_idx, |
3d6c9164 | 4098 | u32 user_brightness) |
4562236b | 4099 | { |
206bbafe | 4100 | struct amdgpu_dm_backlight_caps caps; |
7fd13bae AD |
4101 | struct dc_link *link; |
4102 | u32 brightness; | |
94562810 | 4103 | bool rc; |
4562236b | 4104 | |
7fd13bae AD |
4105 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4106 | caps = dm->backlight_caps[bl_idx]; | |
94562810 | 4107 | |
7fd13bae | 4108 | dm->brightness[bl_idx] = user_brightness; |
1f579254 AD |
4109 | /* update scratch register */ |
4110 | if (bl_idx == 0) | |
4111 | amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); | |
7fd13bae AD |
4112 | brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); |
4113 | link = (struct dc_link *)dm->backlight_link[bl_idx]; | |
94562810 | 4114 | |
3d6c9164 | 4115 | /* Change brightness based on AUX property */ |
118b4627 | 4116 | if (caps.aux_support) { |
7fd13bae AD |
4117 | rc = dc_link_set_backlight_level_nits(link, true, brightness, |
4118 | AUX_BL_DEFAULT_TRANSITION_TIME_MS); | |
4119 | if (!rc) | |
4120 | DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); | |
118b4627 | 4121 | } else { |
7fd13bae AD |
4122 | rc = dc_link_set_backlight_level(link, brightness, 0); |
4123 | if (!rc) | |
4124 | DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); | |
118b4627 | 4125 | } |
94562810 | 4126 | |
4052287a S |
4127 | if (rc) |
4128 | dm->actual_brightness[bl_idx] = user_brightness; | |
4562236b HW |
4129 | } |
4130 | ||
3d6c9164 | 4131 | static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) |
4562236b | 4132 | { |
620a0d27 | 4133 | struct amdgpu_display_manager *dm = bl_get_data(bd); |
7fd13bae | 4134 | int i; |
3d6c9164 | 4135 | |
7fd13bae AD |
4136 | for (i = 0; i < dm->num_of_edps; i++) { |
4137 | if (bd == dm->backlight_dev[i]) | |
4138 | break; | |
4139 | } | |
4140 | if (i >= AMDGPU_DM_MAX_NUM_EDP) | |
4141 | i = 0; | |
4142 | amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); | |
3d6c9164 AD |
4143 | |
4144 | return 0; | |
4145 | } | |
4146 | ||
7fd13bae AD |
4147 | static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, |
4148 | int bl_idx) | |
3d6c9164 | 4149 | { |
0ad3e64e | 4150 | struct amdgpu_dm_backlight_caps caps; |
7fd13bae | 4151 | struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; |
0ad3e64e | 4152 | |
7fd13bae AD |
4153 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4154 | caps = dm->backlight_caps[bl_idx]; | |
620a0d27 | 4155 | |
0ad3e64e | 4156 | if (caps.aux_support) { |
0ad3e64e AD |
4157 | u32 avg, peak; |
4158 | bool rc; | |
4159 | ||
4160 | rc = dc_link_get_backlight_level_nits(link, &avg, &peak); | |
4161 | if (!rc) | |
7fd13bae | 4162 | return dm->brightness[bl_idx]; |
0ad3e64e AD |
4163 | return convert_brightness_to_user(&caps, avg); |
4164 | } else { | |
7fd13bae | 4165 | int ret = dc_link_get_backlight_level(link); |
0ad3e64e AD |
4166 | |
4167 | if (ret == DC_ERROR_UNEXPECTED) | |
7fd13bae | 4168 | return dm->brightness[bl_idx]; |
0ad3e64e AD |
4169 | return convert_brightness_to_user(&caps, ret); |
4170 | } | |
4562236b HW |
4171 | } |
4172 | ||
3d6c9164 AD |
4173 | static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) |
4174 | { | |
4175 | struct amdgpu_display_manager *dm = bl_get_data(bd); | |
7fd13bae | 4176 | int i; |
3d6c9164 | 4177 | |
7fd13bae AD |
4178 | for (i = 0; i < dm->num_of_edps; i++) { |
4179 | if (bd == dm->backlight_dev[i]) | |
4180 | break; | |
4181 | } | |
4182 | if (i >= AMDGPU_DM_MAX_NUM_EDP) | |
4183 | i = 0; | |
4184 | return amdgpu_dm_backlight_get_level(dm, i); | |
3d6c9164 AD |
4185 | } |
4186 | ||
4562236b | 4187 | static const struct backlight_ops amdgpu_dm_backlight_ops = { |
bb264220 | 4188 | .options = BL_CORE_SUSPENDRESUME, |
4562236b HW |
4189 | .get_brightness = amdgpu_dm_backlight_get_brightness, |
4190 | .update_status = amdgpu_dm_backlight_update_status, | |
4191 | }; | |
4192 | ||
7578ecda | 4193 | static void |
213eca2b | 4194 | amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) |
4562236b | 4195 | { |
213eca2b HG |
4196 | struct drm_device *drm = aconnector->base.dev; |
4197 | struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; | |
4562236b | 4198 | struct backlight_properties props = { 0 }; |
213eca2b | 4199 | char bl_name[16]; |
4562236b | 4200 | |
62f03dad HG |
4201 | if (aconnector->bl_idx == -1) |
4202 | return; | |
4203 | ||
da11ef83 | 4204 | if (!acpi_video_backlight_use_native()) { |
213eca2b | 4205 | drm_info(drm, "Skipping amdgpu DM backlight registration\n"); |
c0f50c5d HG |
4206 | /* Try registering an ACPI video backlight device instead. */ |
4207 | acpi_video_register_backlight(); | |
da11ef83 HG |
4208 | return; |
4209 | } | |
4210 | ||
4562236b | 4211 | props.max_brightness = AMDGPU_MAX_BL_LEVEL; |
53a53f86 | 4212 | props.brightness = AMDGPU_MAX_BL_LEVEL; |
4562236b HW |
4213 | props.type = BACKLIGHT_RAW; |
4214 | ||
4215 | snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", | |
213eca2b | 4216 | drm->primary->index + aconnector->bl_idx); |
4562236b | 4217 | |
213eca2b | 4218 | dm->backlight_dev[aconnector->bl_idx] = |
62f03dad | 4219 | backlight_device_register(bl_name, aconnector->base.kdev, dm, |
213eca2b | 4220 | &amdgpu_dm_backlight_ops, &props); |
4562236b | 4221 | |
213eca2b | 4222 | if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { |
4562236b | 4223 | DRM_ERROR("DM: Backlight registration failed!\n"); |
213eca2b | 4224 | dm->backlight_dev[aconnector->bl_idx] = NULL; |
4db231d7 | 4225 | } else |
f1ad2f5e | 4226 | DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); |
4562236b | 4227 | } |
4562236b | 4228 | |
df534fff | 4229 | static int initialize_plane(struct amdgpu_display_manager *dm, |
b2fddb13 | 4230 | struct amdgpu_mode_info *mode_info, int plane_id, |
cc1fec57 NK |
4231 | enum drm_plane_type plane_type, |
4232 | const struct dc_plane_cap *plane_cap) | |
df534fff | 4233 | { |
f180b4bc | 4234 | struct drm_plane *plane; |
df534fff S |
4235 | unsigned long possible_crtcs; |
4236 | int ret = 0; | |
4237 | ||
f180b4bc | 4238 | plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); |
df534fff S |
4239 | if (!plane) { |
4240 | DRM_ERROR("KMS: Failed to allocate plane\n"); | |
4241 | return -ENOMEM; | |
4242 | } | |
b2fddb13 | 4243 | plane->type = plane_type; |
df534fff S |
4244 | |
4245 | /* | |
b2fddb13 NK |
4246 | * HACK: IGT tests expect that the primary plane for a CRTC |
4247 | * can only have one possible CRTC. Only expose support for | |
4248 | * any CRTC if they're not going to be used as a primary plane | |
4249 | * for a CRTC - like overlay or underlay planes. | |
df534fff S |
4250 | */ |
4251 | possible_crtcs = 1 << plane_id; | |
4252 | if (plane_id >= dm->dc->caps.max_streams) | |
4253 | possible_crtcs = 0xff; | |
4254 | ||
cc1fec57 | 4255 | ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); |
df534fff S |
4256 | |
4257 | if (ret) { | |
4258 | DRM_ERROR("KMS: Failed to initialize plane\n"); | |
54087768 | 4259 | kfree(plane); |
df534fff S |
4260 | return ret; |
4261 | } | |
4262 | ||
54087768 NK |
4263 | if (mode_info) |
4264 | mode_info->planes[plane_id] = plane; | |
4265 | ||
df534fff S |
4266 | return ret; |
4267 | } | |
4268 | ||
89fc8d4e | 4269 | |
618e51cd HG |
4270 | static void setup_backlight_device(struct amdgpu_display_manager *dm, |
4271 | struct amdgpu_dm_connector *aconnector) | |
89fc8d4e | 4272 | { |
f196198c | 4273 | struct dc_link *link = aconnector->dc_link; |
ceb4a561 | 4274 | int bl_idx = dm->num_of_edps; |
89fc8d4e | 4275 | |
ceb4a561 HG |
4276 | if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || |
4277 | link->type == dc_connection_none) | |
4278 | return; | |
4279 | ||
4280 | if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { | |
4281 | drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); | |
4282 | return; | |
89fc8d4e | 4283 | } |
ceb4a561 | 4284 | |
f196198c HG |
4285 | aconnector->bl_idx = bl_idx; |
4286 | ||
618e51cd HG |
4287 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
4288 | dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; | |
ceb4a561 HG |
4289 | dm->backlight_link[bl_idx] = link; |
4290 | dm->num_of_edps++; | |
618e51cd HG |
4291 | |
4292 | update_connector_ext_caps(aconnector); | |
89fc8d4e HW |
4293 | } |
4294 | ||
acc96ae0 | 4295 | static void amdgpu_set_panel_orientation(struct drm_connector *connector); |
89fc8d4e | 4296 | |
1f6010a9 DF |
4297 | /* |
4298 | * In this architecture, the association | |
4562236b HW |
4299 | * connector -> encoder -> crtc |
4300 | * id not really requried. The crtc and connector will hold the | |
4301 | * display_index as an abstraction to use with DAL component | |
4302 | * | |
4303 | * Returns 0 on success | |
4304 | */ | |
7578ecda | 4305 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) |
4562236b HW |
4306 | { |
4307 | struct amdgpu_display_manager *dm = &adev->dm; | |
ae67558b | 4308 | s32 i; |
c84dec2f | 4309 | struct amdgpu_dm_connector *aconnector = NULL; |
f2a0f5e6 | 4310 | struct amdgpu_encoder *aencoder = NULL; |
d4e13b0d | 4311 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
ae67558b SS |
4312 | u32 link_cnt; |
4313 | s32 primary_planes; | |
fbbdadf2 | 4314 | enum dc_connection_type new_connection_type = dc_connection_none; |
cc1fec57 | 4315 | const struct dc_plane_cap *plane; |
9470620e | 4316 | bool psr_feature_enabled = false; |
35f33086 | 4317 | int max_overlay = dm->dc->caps.max_slave_planes; |
4562236b | 4318 | |
d58159de AD |
4319 | dm->display_indexes_num = dm->dc->caps.max_streams; |
4320 | /* Update the actual used number of crtc */ | |
4321 | adev->mode_info.num_crtc = adev->dm.display_indexes_num; | |
4322 | ||
60971b20 | 4323 | amdgpu_dm_set_irq_funcs(adev); |
4324 | ||
4562236b | 4325 | link_cnt = dm->dc->caps.max_links; |
4562236b HW |
4326 | if (amdgpu_dm_mode_config_init(dm->adev)) { |
4327 | DRM_ERROR("DM: Failed to initialize mode config\n"); | |
59d0f396 | 4328 | return -EINVAL; |
4562236b HW |
4329 | } |
4330 | ||
b2fddb13 NK |
4331 | /* There is one primary plane per CRTC */ |
4332 | primary_planes = dm->dc->caps.max_streams; | |
54087768 | 4333 | ASSERT(primary_planes <= AMDGPU_MAX_PLANES); |
efa6a8b7 | 4334 | |
b2fddb13 NK |
4335 | /* |
4336 | * Initialize primary planes, implicit planes for legacy IOCTLS. | |
4337 | * Order is reversed to match iteration order in atomic check. | |
4338 | */ | |
4339 | for (i = (primary_planes - 1); i >= 0; i--) { | |
cc1fec57 NK |
4340 | plane = &dm->dc->caps.planes[i]; |
4341 | ||
b2fddb13 | 4342 | if (initialize_plane(dm, mode_info, i, |
cc1fec57 | 4343 | DRM_PLANE_TYPE_PRIMARY, plane)) { |
df534fff | 4344 | DRM_ERROR("KMS: Failed to initialize primary plane\n"); |
cd8a2ae8 | 4345 | goto fail; |
d4e13b0d | 4346 | } |
df534fff | 4347 | } |
92f3ac40 | 4348 | |
0d579c7e NK |
4349 | /* |
4350 | * Initialize overlay planes, index starting after primary planes. | |
4351 | * These planes have a higher DRM index than the primary planes since | |
4352 | * they should be considered as having a higher z-order. | |
4353 | * Order is reversed to match iteration order in atomic check. | |
cc1fec57 NK |
4354 | * |
4355 | * Only support DCN for now, and only expose one so we don't encourage | |
4356 | * userspace to use up all the pipes. | |
0d579c7e | 4357 | */ |
cc1fec57 NK |
4358 | for (i = 0; i < dm->dc->caps.max_planes; ++i) { |
4359 | struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; | |
4360 | ||
8813381a LL |
4361 | /* Do not create overlay if MPO disabled */ |
4362 | if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) | |
4363 | break; | |
4364 | ||
cc1fec57 NK |
4365 | if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) |
4366 | continue; | |
4367 | ||
ea36ad34 | 4368 | if (!plane->pixel_format_support.argb8888) |
cc1fec57 NK |
4369 | continue; |
4370 | ||
35f33086 BL |
4371 | if (max_overlay-- == 0) |
4372 | break; | |
4373 | ||
54087768 | 4374 | if (initialize_plane(dm, NULL, primary_planes + i, |
cc1fec57 | 4375 | DRM_PLANE_TYPE_OVERLAY, plane)) { |
0d579c7e | 4376 | DRM_ERROR("KMS: Failed to initialize overlay plane\n"); |
cd8a2ae8 | 4377 | goto fail; |
d4e13b0d AD |
4378 | } |
4379 | } | |
4562236b | 4380 | |
d4e13b0d | 4381 | for (i = 0; i < dm->dc->caps.max_streams; i++) |
f180b4bc | 4382 | if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { |
4562236b | 4383 | DRM_ERROR("KMS: Failed to initialize crtc\n"); |
cd8a2ae8 | 4384 | goto fail; |
4562236b | 4385 | } |
4562236b | 4386 | |
81927e28 | 4387 | /* Use Outbox interrupt */ |
1d789535 | 4388 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
4389 | case IP_VERSION(3, 0, 0): |
4390 | case IP_VERSION(3, 1, 2): | |
4391 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4392 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4393 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4394 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4395 | case IP_VERSION(3, 2, 0): |
4396 | case IP_VERSION(3, 2, 1): | |
c08182f2 | 4397 | case IP_VERSION(2, 1, 0): |
81927e28 JS |
4398 | if (register_outbox_irq_handlers(dm->adev)) { |
4399 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4400 | goto fail; | |
4401 | } | |
4402 | break; | |
4403 | default: | |
c08182f2 | 4404 | DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", |
1d789535 | 4405 | adev->ip_versions[DCE_HWIP][0]); |
81927e28 | 4406 | } |
9470620e NK |
4407 | |
4408 | /* Determine whether to enable PSR support by default. */ | |
4409 | if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { | |
4410 | switch (adev->ip_versions[DCE_HWIP][0]) { | |
4411 | case IP_VERSION(3, 1, 2): | |
4412 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4413 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4414 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4415 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4416 | case IP_VERSION(3, 2, 0): |
4417 | case IP_VERSION(3, 2, 1): | |
9470620e NK |
4418 | psr_feature_enabled = true; |
4419 | break; | |
4420 | default: | |
4421 | psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; | |
4422 | break; | |
4423 | } | |
4424 | } | |
81927e28 | 4425 | |
4562236b HW |
4426 | /* loops over all connectors on the board */ |
4427 | for (i = 0; i < link_cnt; i++) { | |
89fc8d4e | 4428 | struct dc_link *link = NULL; |
4562236b HW |
4429 | |
4430 | if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { | |
4431 | DRM_ERROR( | |
4432 | "KMS: Cannot support more than %d display indexes\n", | |
4433 | AMDGPU_DM_MAX_DISPLAY_INDEX); | |
4434 | continue; | |
4435 | } | |
4436 | ||
4437 | aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); | |
4438 | if (!aconnector) | |
cd8a2ae8 | 4439 | goto fail; |
4562236b HW |
4440 | |
4441 | aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); | |
8440c304 | 4442 | if (!aencoder) |
cd8a2ae8 | 4443 | goto fail; |
4562236b HW |
4444 | |
4445 | if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { | |
4446 | DRM_ERROR("KMS: Failed to initialize encoder\n"); | |
cd8a2ae8 | 4447 | goto fail; |
4562236b HW |
4448 | } |
4449 | ||
4450 | if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { | |
4451 | DRM_ERROR("KMS: Failed to initialize connector\n"); | |
cd8a2ae8 | 4452 | goto fail; |
4562236b HW |
4453 | } |
4454 | ||
89fc8d4e HW |
4455 | link = dc_get_link_at_index(dm->dc, i); |
4456 | ||
54618888 | 4457 | if (!dc_link_detect_connection_type(link, &new_connection_type)) |
fbbdadf2 BL |
4458 | DRM_ERROR("KMS: Failed to detect connector\n"); |
4459 | ||
4460 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
4461 | emulated_link_detect(link); | |
4462 | amdgpu_dm_update_connector_after_detect(aconnector); | |
15c735e7 WL |
4463 | } else { |
4464 | bool ret = false; | |
fbbdadf2 | 4465 | |
15c735e7 WL |
4466 | mutex_lock(&dm->dc_lock); |
4467 | ret = dc_link_detect(link, DETECT_REASON_BOOT); | |
4468 | mutex_unlock(&dm->dc_lock); | |
4469 | ||
4470 | if (ret) { | |
4471 | amdgpu_dm_update_connector_after_detect(aconnector); | |
618e51cd | 4472 | setup_backlight_device(dm, aconnector); |
89fc8d4e | 4473 | |
15c735e7 WL |
4474 | if (psr_feature_enabled) |
4475 | amdgpu_dm_set_psr_caps(link); | |
89fc8d4e | 4476 | |
15c735e7 WL |
4477 | /* TODO: Fix vblank control helpers to delay PSR entry to allow this when |
4478 | * PSR is also supported. | |
4479 | */ | |
4480 | if (link->psr_settings.psr_feature_enabled) | |
4481 | adev_to_drm(adev)->vblank_disable_immediate = false; | |
4482 | } | |
4483 | } | |
acc96ae0 | 4484 | amdgpu_set_panel_orientation(&aconnector->base); |
4562236b HW |
4485 | } |
4486 | ||
4487 | /* Software is initialized. Now we can register interrupt handlers. */ | |
4488 | switch (adev->asic_type) { | |
55e56389 MR |
4489 | #if defined(CONFIG_DRM_AMD_DC_SI) |
4490 | case CHIP_TAHITI: | |
4491 | case CHIP_PITCAIRN: | |
4492 | case CHIP_VERDE: | |
4493 | case CHIP_OLAND: | |
4494 | if (dce60_register_irq_handlers(dm->adev)) { | |
4495 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4496 | goto fail; | |
4497 | } | |
4498 | break; | |
4499 | #endif | |
4562236b HW |
4500 | case CHIP_BONAIRE: |
4501 | case CHIP_HAWAII: | |
cd4b356f AD |
4502 | case CHIP_KAVERI: |
4503 | case CHIP_KABINI: | |
4504 | case CHIP_MULLINS: | |
4562236b HW |
4505 | case CHIP_TONGA: |
4506 | case CHIP_FIJI: | |
4507 | case CHIP_CARRIZO: | |
4508 | case CHIP_STONEY: | |
4509 | case CHIP_POLARIS11: | |
4510 | case CHIP_POLARIS10: | |
b264d345 | 4511 | case CHIP_POLARIS12: |
7737de91 | 4512 | case CHIP_VEGAM: |
2c8ad2d5 | 4513 | case CHIP_VEGA10: |
2325ff30 | 4514 | case CHIP_VEGA12: |
1fe6bf2f | 4515 | case CHIP_VEGA20: |
4562236b HW |
4516 | if (dce110_register_irq_handlers(dm->adev)) { |
4517 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
cd8a2ae8 | 4518 | goto fail; |
4562236b HW |
4519 | } |
4520 | break; | |
4521 | default: | |
1d789535 | 4522 | switch (adev->ip_versions[DCE_HWIP][0]) { |
559f591d AD |
4523 | case IP_VERSION(1, 0, 0): |
4524 | case IP_VERSION(1, 0, 1): | |
c08182f2 AD |
4525 | case IP_VERSION(2, 0, 2): |
4526 | case IP_VERSION(2, 0, 3): | |
4527 | case IP_VERSION(2, 0, 0): | |
4528 | case IP_VERSION(2, 1, 0): | |
4529 | case IP_VERSION(3, 0, 0): | |
4530 | case IP_VERSION(3, 0, 2): | |
4531 | case IP_VERSION(3, 0, 3): | |
4532 | case IP_VERSION(3, 0, 1): | |
4533 | case IP_VERSION(3, 1, 2): | |
4534 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4535 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4536 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4537 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4538 | case IP_VERSION(3, 2, 0): |
4539 | case IP_VERSION(3, 2, 1): | |
c08182f2 AD |
4540 | if (dcn10_register_irq_handlers(dm->adev)) { |
4541 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
4542 | goto fail; | |
4543 | } | |
4544 | break; | |
4545 | default: | |
2cbc6f42 | 4546 | DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", |
1d789535 | 4547 | adev->ip_versions[DCE_HWIP][0]); |
2cbc6f42 | 4548 | goto fail; |
c08182f2 | 4549 | } |
2cbc6f42 | 4550 | break; |
4562236b HW |
4551 | } |
4552 | ||
4562236b | 4553 | return 0; |
cd8a2ae8 | 4554 | fail: |
4562236b | 4555 | kfree(aencoder); |
4562236b | 4556 | kfree(aconnector); |
54087768 | 4557 | |
59d0f396 | 4558 | return -EINVAL; |
4562236b HW |
4559 | } |
4560 | ||
7578ecda | 4561 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) |
4562236b | 4562 | { |
eb3dc897 | 4563 | drm_atomic_private_obj_fini(&dm->atomic_obj); |
4562236b HW |
4564 | } |
4565 | ||
4566 | /****************************************************************************** | |
4567 | * amdgpu_display_funcs functions | |
4568 | *****************************************************************************/ | |
4569 | ||
1f6010a9 | 4570 | /* |
4562236b HW |
4571 | * dm_bandwidth_update - program display watermarks |
4572 | * | |
4573 | * @adev: amdgpu_device pointer | |
4574 | * | |
4575 | * Calculate and program the display watermarks and line buffer allocation. | |
4576 | */ | |
4577 | static void dm_bandwidth_update(struct amdgpu_device *adev) | |
4578 | { | |
49c07a99 | 4579 | /* TODO: implement later */ |
4562236b HW |
4580 | } |
4581 | ||
39cc5be2 | 4582 | static const struct amdgpu_display_funcs dm_display_funcs = { |
4562236b HW |
4583 | .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ |
4584 | .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ | |
7b42573b HW |
4585 | .backlight_set_level = NULL, /* never called for DC */ |
4586 | .backlight_get_level = NULL, /* never called for DC */ | |
4562236b HW |
4587 | .hpd_sense = NULL,/* called unconditionally */ |
4588 | .hpd_set_polarity = NULL, /* called unconditionally */ | |
4589 | .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
4590 | .page_flip_get_scanoutpos = |
4591 | dm_crtc_get_scanoutpos,/* called unconditionally */ | |
4592 | .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ | |
4593 | .add_connector = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
4594 | }; |
4595 | ||
4596 | #if defined(CONFIG_DEBUG_KERNEL_DC) | |
4597 | ||
3ee6b26b AD |
4598 | static ssize_t s3_debug_store(struct device *device, |
4599 | struct device_attribute *attr, | |
4600 | const char *buf, | |
4601 | size_t count) | |
4562236b HW |
4602 | { |
4603 | int ret; | |
4604 | int s3_state; | |
ef1de361 | 4605 | struct drm_device *drm_dev = dev_get_drvdata(device); |
1348969a | 4606 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
4562236b HW |
4607 | |
4608 | ret = kstrtoint(buf, 0, &s3_state); | |
4609 | ||
4610 | if (ret == 0) { | |
4611 | if (s3_state) { | |
4612 | dm_resume(adev); | |
4a580877 | 4613 | drm_kms_helper_hotplug_event(adev_to_drm(adev)); |
4562236b HW |
4614 | } else |
4615 | dm_suspend(adev); | |
4616 | } | |
4617 | ||
4618 | return ret == 0 ? count : 0; | |
4619 | } | |
4620 | ||
4621 | DEVICE_ATTR_WO(s3_debug); | |
4622 | ||
4623 | #endif | |
4624 | ||
a7ab3451 ML |
4625 | static int dm_init_microcode(struct amdgpu_device *adev) |
4626 | { | |
4627 | char *fw_name_dmub; | |
4628 | int r; | |
4629 | ||
4630 | switch (adev->ip_versions[DCE_HWIP][0]) { | |
4631 | case IP_VERSION(2, 1, 0): | |
4632 | fw_name_dmub = FIRMWARE_RENOIR_DMUB; | |
4633 | if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) | |
4634 | fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; | |
4635 | break; | |
4636 | case IP_VERSION(3, 0, 0): | |
4637 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) | |
4638 | fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; | |
4639 | else | |
4640 | fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; | |
4641 | break; | |
4642 | case IP_VERSION(3, 0, 1): | |
4643 | fw_name_dmub = FIRMWARE_VANGOGH_DMUB; | |
4644 | break; | |
4645 | case IP_VERSION(3, 0, 2): | |
4646 | fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; | |
4647 | break; | |
4648 | case IP_VERSION(3, 0, 3): | |
4649 | fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; | |
4650 | break; | |
4651 | case IP_VERSION(3, 1, 2): | |
4652 | case IP_VERSION(3, 1, 3): | |
4653 | fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; | |
4654 | break; | |
4655 | case IP_VERSION(3, 1, 4): | |
4656 | fw_name_dmub = FIRMWARE_DCN_314_DMUB; | |
4657 | break; | |
4658 | case IP_VERSION(3, 1, 5): | |
4659 | fw_name_dmub = FIRMWARE_DCN_315_DMUB; | |
4660 | break; | |
4661 | case IP_VERSION(3, 1, 6): | |
4662 | fw_name_dmub = FIRMWARE_DCN316_DMUB; | |
4663 | break; | |
4664 | case IP_VERSION(3, 2, 0): | |
4665 | fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; | |
4666 | break; | |
4667 | case IP_VERSION(3, 2, 1): | |
4668 | fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; | |
4669 | break; | |
4670 | default: | |
4671 | /* ASIC doesn't support DMUB. */ | |
4672 | return 0; | |
4673 | } | |
4674 | r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); | |
4675 | if (r) | |
4676 | DRM_ERROR("DMUB firmware loading failed: %d\n", r); | |
4677 | return r; | |
4678 | } | |
4679 | ||
4562236b HW |
4680 | static int dm_early_init(void *handle) |
4681 | { | |
4682 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
44900af0 AD |
4683 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
4684 | struct atom_context *ctx = mode_info->atom_context; | |
4685 | int index = GetIndexIntoMasterTable(DATA, Object_Header); | |
4686 | u16 data_offset; | |
4687 | ||
4688 | /* if there is no object header, skip DM */ | |
4689 | if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { | |
4690 | adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; | |
4691 | dev_info(adev->dev, "No object header, skipping DM\n"); | |
4692 | return -ENOENT; | |
4693 | } | |
4562236b | 4694 | |
4562236b | 4695 | switch (adev->asic_type) { |
55e56389 MR |
4696 | #if defined(CONFIG_DRM_AMD_DC_SI) |
4697 | case CHIP_TAHITI: | |
4698 | case CHIP_PITCAIRN: | |
4699 | case CHIP_VERDE: | |
4700 | adev->mode_info.num_crtc = 6; | |
4701 | adev->mode_info.num_hpd = 6; | |
4702 | adev->mode_info.num_dig = 6; | |
4703 | break; | |
4704 | case CHIP_OLAND: | |
4705 | adev->mode_info.num_crtc = 2; | |
4706 | adev->mode_info.num_hpd = 2; | |
4707 | adev->mode_info.num_dig = 2; | |
4708 | break; | |
4709 | #endif | |
4562236b HW |
4710 | case CHIP_BONAIRE: |
4711 | case CHIP_HAWAII: | |
4712 | adev->mode_info.num_crtc = 6; | |
4713 | adev->mode_info.num_hpd = 6; | |
4714 | adev->mode_info.num_dig = 6; | |
4562236b | 4715 | break; |
cd4b356f AD |
4716 | case CHIP_KAVERI: |
4717 | adev->mode_info.num_crtc = 4; | |
4718 | adev->mode_info.num_hpd = 6; | |
4719 | adev->mode_info.num_dig = 7; | |
cd4b356f AD |
4720 | break; |
4721 | case CHIP_KABINI: | |
4722 | case CHIP_MULLINS: | |
4723 | adev->mode_info.num_crtc = 2; | |
4724 | adev->mode_info.num_hpd = 6; | |
4725 | adev->mode_info.num_dig = 6; | |
cd4b356f | 4726 | break; |
4562236b HW |
4727 | case CHIP_FIJI: |
4728 | case CHIP_TONGA: | |
4729 | adev->mode_info.num_crtc = 6; | |
4730 | adev->mode_info.num_hpd = 6; | |
4731 | adev->mode_info.num_dig = 7; | |
4562236b HW |
4732 | break; |
4733 | case CHIP_CARRIZO: | |
4734 | adev->mode_info.num_crtc = 3; | |
4735 | adev->mode_info.num_hpd = 6; | |
4736 | adev->mode_info.num_dig = 9; | |
4562236b HW |
4737 | break; |
4738 | case CHIP_STONEY: | |
4739 | adev->mode_info.num_crtc = 2; | |
4740 | adev->mode_info.num_hpd = 6; | |
4741 | adev->mode_info.num_dig = 9; | |
4562236b HW |
4742 | break; |
4743 | case CHIP_POLARIS11: | |
b264d345 | 4744 | case CHIP_POLARIS12: |
4562236b HW |
4745 | adev->mode_info.num_crtc = 5; |
4746 | adev->mode_info.num_hpd = 5; | |
4747 | adev->mode_info.num_dig = 5; | |
4562236b HW |
4748 | break; |
4749 | case CHIP_POLARIS10: | |
7737de91 | 4750 | case CHIP_VEGAM: |
4562236b HW |
4751 | adev->mode_info.num_crtc = 6; |
4752 | adev->mode_info.num_hpd = 6; | |
4753 | adev->mode_info.num_dig = 6; | |
4562236b | 4754 | break; |
2c8ad2d5 | 4755 | case CHIP_VEGA10: |
2325ff30 | 4756 | case CHIP_VEGA12: |
1fe6bf2f | 4757 | case CHIP_VEGA20: |
2c8ad2d5 AD |
4758 | adev->mode_info.num_crtc = 6; |
4759 | adev->mode_info.num_hpd = 6; | |
4760 | adev->mode_info.num_dig = 6; | |
4761 | break; | |
4562236b | 4762 | default: |
cae5c1ab | 4763 | |
1d789535 | 4764 | switch (adev->ip_versions[DCE_HWIP][0]) { |
c08182f2 AD |
4765 | case IP_VERSION(2, 0, 2): |
4766 | case IP_VERSION(3, 0, 0): | |
4767 | adev->mode_info.num_crtc = 6; | |
4768 | adev->mode_info.num_hpd = 6; | |
4769 | adev->mode_info.num_dig = 6; | |
4770 | break; | |
4771 | case IP_VERSION(2, 0, 0): | |
4772 | case IP_VERSION(3, 0, 2): | |
4773 | adev->mode_info.num_crtc = 5; | |
4774 | adev->mode_info.num_hpd = 5; | |
4775 | adev->mode_info.num_dig = 5; | |
4776 | break; | |
4777 | case IP_VERSION(2, 0, 3): | |
4778 | case IP_VERSION(3, 0, 3): | |
4779 | adev->mode_info.num_crtc = 2; | |
4780 | adev->mode_info.num_hpd = 2; | |
4781 | adev->mode_info.num_dig = 2; | |
4782 | break; | |
559f591d AD |
4783 | case IP_VERSION(1, 0, 0): |
4784 | case IP_VERSION(1, 0, 1): | |
c08182f2 AD |
4785 | case IP_VERSION(3, 0, 1): |
4786 | case IP_VERSION(2, 1, 0): | |
4787 | case IP_VERSION(3, 1, 2): | |
4788 | case IP_VERSION(3, 1, 3): | |
e850f6b1 | 4789 | case IP_VERSION(3, 1, 4): |
b5b8ed44 | 4790 | case IP_VERSION(3, 1, 5): |
de7cc1b4 | 4791 | case IP_VERSION(3, 1, 6): |
577359ca AP |
4792 | case IP_VERSION(3, 2, 0): |
4793 | case IP_VERSION(3, 2, 1): | |
c08182f2 AD |
4794 | adev->mode_info.num_crtc = 4; |
4795 | adev->mode_info.num_hpd = 4; | |
4796 | adev->mode_info.num_dig = 4; | |
4797 | break; | |
4798 | default: | |
2cbc6f42 | 4799 | DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", |
1d789535 | 4800 | adev->ip_versions[DCE_HWIP][0]); |
2cbc6f42 | 4801 | return -EINVAL; |
c08182f2 | 4802 | } |
2cbc6f42 | 4803 | break; |
4562236b HW |
4804 | } |
4805 | ||
39cc5be2 AD |
4806 | if (adev->mode_info.funcs == NULL) |
4807 | adev->mode_info.funcs = &dm_display_funcs; | |
4808 | ||
1f6010a9 DF |
4809 | /* |
4810 | * Note: Do NOT change adev->audio_endpt_rreg and | |
4562236b | 4811 | * adev->audio_endpt_wreg because they are initialised in |
1f6010a9 DF |
4812 | * amdgpu_device_init() |
4813 | */ | |
4562236b HW |
4814 | #if defined(CONFIG_DEBUG_KERNEL_DC) |
4815 | device_create_file( | |
4a580877 | 4816 | adev_to_drm(adev)->dev, |
4562236b HW |
4817 | &dev_attr_s3_debug); |
4818 | #endif | |
d09ef243 | 4819 | adev->dc_enabled = true; |
4562236b | 4820 | |
a7ab3451 | 4821 | return dm_init_microcode(adev); |
4562236b HW |
4822 | } |
4823 | ||
e7b07cee HW |
4824 | static bool modereset_required(struct drm_crtc_state *crtc_state) |
4825 | { | |
2afda735 | 4826 | return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); |
e7b07cee HW |
4827 | } |
4828 | ||
7578ecda | 4829 | static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) |
e7b07cee HW |
4830 | { |
4831 | drm_encoder_cleanup(encoder); | |
4832 | kfree(encoder); | |
4833 | } | |
4834 | ||
4835 | static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { | |
4836 | .destroy = amdgpu_dm_encoder_destroy, | |
4837 | }; | |
4838 | ||
5d945cbc RS |
4839 | static int |
4840 | fill_plane_color_attributes(const struct drm_plane_state *plane_state, | |
4841 | const enum surface_pixel_format format, | |
4842 | enum dc_color_space *color_space) | |
6300b3bd | 4843 | { |
5d945cbc | 4844 | bool full_range; |
6300b3bd | 4845 | |
5d945cbc RS |
4846 | *color_space = COLOR_SPACE_SRGB; |
4847 | ||
4848 | /* DRM color properties only affect non-RGB formats. */ | |
4849 | if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) | |
4850 | return 0; | |
4851 | ||
4852 | full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); | |
4853 | ||
4854 | switch (plane_state->color_encoding) { | |
4855 | case DRM_COLOR_YCBCR_BT601: | |
4856 | if (full_range) | |
4857 | *color_space = COLOR_SPACE_YCBCR601; | |
4858 | else | |
4859 | *color_space = COLOR_SPACE_YCBCR601_LIMITED; | |
6300b3bd MK |
4860 | break; |
4861 | ||
5d945cbc RS |
4862 | case DRM_COLOR_YCBCR_BT709: |
4863 | if (full_range) | |
4864 | *color_space = COLOR_SPACE_YCBCR709; | |
4865 | else | |
4866 | *color_space = COLOR_SPACE_YCBCR709_LIMITED; | |
6300b3bd MK |
4867 | break; |
4868 | ||
5d945cbc RS |
4869 | case DRM_COLOR_YCBCR_BT2020: |
4870 | if (full_range) | |
4871 | *color_space = COLOR_SPACE_2020_YCBCR; | |
4872 | else | |
4873 | return -EINVAL; | |
6300b3bd | 4874 | break; |
6300b3bd | 4875 | |
5d945cbc RS |
4876 | default: |
4877 | return -EINVAL; | |
4878 | } | |
6300b3bd | 4879 | |
5d945cbc | 4880 | return 0; |
6300b3bd MK |
4881 | } |
4882 | ||
5d945cbc RS |
4883 | static int |
4884 | fill_dc_plane_info_and_addr(struct amdgpu_device *adev, | |
4885 | const struct drm_plane_state *plane_state, | |
ae67558b | 4886 | const u64 tiling_flags, |
5d945cbc RS |
4887 | struct dc_plane_info *plane_info, |
4888 | struct dc_plane_address *address, | |
4889 | bool tmz_surface, | |
4890 | bool force_disable_dcc) | |
e7b07cee | 4891 | { |
5d945cbc RS |
4892 | const struct drm_framebuffer *fb = plane_state->fb; |
4893 | const struct amdgpu_framebuffer *afb = | |
4894 | to_amdgpu_framebuffer(plane_state->fb); | |
4895 | int ret; | |
e7b07cee | 4896 | |
5d945cbc | 4897 | memset(plane_info, 0, sizeof(*plane_info)); |
e7b07cee | 4898 | |
5d945cbc RS |
4899 | switch (fb->format->format) { |
4900 | case DRM_FORMAT_C8: | |
4901 | plane_info->format = | |
4902 | SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; | |
4903 | break; | |
4904 | case DRM_FORMAT_RGB565: | |
4905 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; | |
4906 | break; | |
4907 | case DRM_FORMAT_XRGB8888: | |
4908 | case DRM_FORMAT_ARGB8888: | |
4909 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; | |
4910 | break; | |
4911 | case DRM_FORMAT_XRGB2101010: | |
4912 | case DRM_FORMAT_ARGB2101010: | |
4913 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; | |
4914 | break; | |
4915 | case DRM_FORMAT_XBGR2101010: | |
4916 | case DRM_FORMAT_ABGR2101010: | |
4917 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; | |
4918 | break; | |
4919 | case DRM_FORMAT_XBGR8888: | |
4920 | case DRM_FORMAT_ABGR8888: | |
4921 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; | |
4922 | break; | |
4923 | case DRM_FORMAT_NV21: | |
4924 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; | |
4925 | break; | |
4926 | case DRM_FORMAT_NV12: | |
4927 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; | |
4928 | break; | |
4929 | case DRM_FORMAT_P010: | |
4930 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; | |
4931 | break; | |
4932 | case DRM_FORMAT_XRGB16161616F: | |
4933 | case DRM_FORMAT_ARGB16161616F: | |
4934 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; | |
4935 | break; | |
4936 | case DRM_FORMAT_XBGR16161616F: | |
4937 | case DRM_FORMAT_ABGR16161616F: | |
4938 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; | |
4939 | break; | |
4940 | case DRM_FORMAT_XRGB16161616: | |
4941 | case DRM_FORMAT_ARGB16161616: | |
4942 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; | |
4943 | break; | |
4944 | case DRM_FORMAT_XBGR16161616: | |
4945 | case DRM_FORMAT_ABGR16161616: | |
4946 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; | |
4947 | break; | |
4948 | default: | |
4949 | DRM_ERROR( | |
4950 | "Unsupported screen format %p4cc\n", | |
4951 | &fb->format->format); | |
d89f6048 | 4952 | return -EINVAL; |
5d945cbc | 4953 | } |
d89f6048 | 4954 | |
5d945cbc RS |
4955 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { |
4956 | case DRM_MODE_ROTATE_0: | |
4957 | plane_info->rotation = ROTATION_ANGLE_0; | |
4958 | break; | |
4959 | case DRM_MODE_ROTATE_90: | |
4960 | plane_info->rotation = ROTATION_ANGLE_90; | |
4961 | break; | |
4962 | case DRM_MODE_ROTATE_180: | |
4963 | plane_info->rotation = ROTATION_ANGLE_180; | |
4964 | break; | |
4965 | case DRM_MODE_ROTATE_270: | |
4966 | plane_info->rotation = ROTATION_ANGLE_270; | |
4967 | break; | |
4968 | default: | |
4969 | plane_info->rotation = ROTATION_ANGLE_0; | |
4970 | break; | |
4971 | } | |
695af5f9 | 4972 | |
695af5f9 | 4973 | |
5d945cbc RS |
4974 | plane_info->visible = true; |
4975 | plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; | |
e7b07cee | 4976 | |
22c42b0e | 4977 | plane_info->layer_index = plane_state->normalized_zpos; |
e7b07cee | 4978 | |
5d945cbc RS |
4979 | ret = fill_plane_color_attributes(plane_state, plane_info->format, |
4980 | &plane_info->color_space); | |
4981 | if (ret) | |
4982 | return ret; | |
e7b07cee | 4983 | |
8bf0d9cd | 4984 | ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, |
5d945cbc RS |
4985 | plane_info->rotation, tiling_flags, |
4986 | &plane_info->tiling_info, | |
4987 | &plane_info->plane_size, | |
4988 | &plane_info->dcc, address, | |
4989 | tmz_surface, force_disable_dcc); | |
4990 | if (ret) | |
4991 | return ret; | |
e7b07cee | 4992 | |
8bf0d9cd | 4993 | amdgpu_dm_plane_fill_blending_from_plane_state( |
5d945cbc RS |
4994 | plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, |
4995 | &plane_info->global_alpha, &plane_info->global_alpha_value); | |
e7b07cee | 4996 | |
5d945cbc RS |
4997 | return 0; |
4998 | } | |
e7b07cee | 4999 | |
5d945cbc RS |
5000 | static int fill_dc_plane_attributes(struct amdgpu_device *adev, |
5001 | struct dc_plane_state *dc_plane_state, | |
5002 | struct drm_plane_state *plane_state, | |
5003 | struct drm_crtc_state *crtc_state) | |
5004 | { | |
5005 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); | |
5006 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; | |
5007 | struct dc_scaling_info scaling_info; | |
5008 | struct dc_plane_info plane_info; | |
5009 | int ret; | |
5010 | bool force_disable_dcc = false; | |
6300b3bd | 5011 | |
8bf0d9cd | 5012 | ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); |
5d945cbc RS |
5013 | if (ret) |
5014 | return ret; | |
e7b07cee | 5015 | |
5d945cbc RS |
5016 | dc_plane_state->src_rect = scaling_info.src_rect; |
5017 | dc_plane_state->dst_rect = scaling_info.dst_rect; | |
5018 | dc_plane_state->clip_rect = scaling_info.clip_rect; | |
5019 | dc_plane_state->scaling_quality = scaling_info.scaling_quality; | |
6491f0c0 | 5020 | |
5d945cbc RS |
5021 | force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; |
5022 | ret = fill_dc_plane_info_and_addr(adev, plane_state, | |
5023 | afb->tiling_flags, | |
5024 | &plane_info, | |
5025 | &dc_plane_state->address, | |
5026 | afb->tmz_surface, | |
5027 | force_disable_dcc); | |
5028 | if (ret) | |
5029 | return ret; | |
6491f0c0 | 5030 | |
5d945cbc RS |
5031 | dc_plane_state->format = plane_info.format; |
5032 | dc_plane_state->color_space = plane_info.color_space; | |
5033 | dc_plane_state->format = plane_info.format; | |
5034 | dc_plane_state->plane_size = plane_info.plane_size; | |
5035 | dc_plane_state->rotation = plane_info.rotation; | |
5036 | dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; | |
5037 | dc_plane_state->stereo_format = plane_info.stereo_format; | |
5038 | dc_plane_state->tiling_info = plane_info.tiling_info; | |
5039 | dc_plane_state->visible = plane_info.visible; | |
5040 | dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; | |
5041 | dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; | |
5042 | dc_plane_state->global_alpha = plane_info.global_alpha; | |
5043 | dc_plane_state->global_alpha_value = plane_info.global_alpha_value; | |
5044 | dc_plane_state->dcc = plane_info.dcc; | |
22c42b0e | 5045 | dc_plane_state->layer_index = plane_info.layer_index; |
5d945cbc | 5046 | dc_plane_state->flip_int_enabled = true; |
6491f0c0 | 5047 | |
695af5f9 | 5048 | /* |
5d945cbc RS |
5049 | * Always set input transfer function, since plane state is refreshed |
5050 | * every time. | |
695af5f9 | 5051 | */ |
5d945cbc RS |
5052 | ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); |
5053 | if (ret) | |
5054 | return ret; | |
e7b07cee | 5055 | |
695af5f9 | 5056 | return 0; |
4562236b | 5057 | } |
695af5f9 | 5058 | |
30ebe415 HM |
5059 | static inline void fill_dc_dirty_rect(struct drm_plane *plane, |
5060 | struct rect *dirty_rect, int32_t x, | |
ae67558b | 5061 | s32 y, s32 width, s32 height, |
30ebe415 HM |
5062 | int *i, bool ffu) |
5063 | { | |
af22d6a8 | 5064 | WARN_ON(*i >= DC_MAX_DIRTY_RECTS); |
30ebe415 HM |
5065 | |
5066 | dirty_rect->x = x; | |
5067 | dirty_rect->y = y; | |
5068 | dirty_rect->width = width; | |
5069 | dirty_rect->height = height; | |
5070 | ||
5071 | if (ffu) | |
5072 | drm_dbg(plane->dev, | |
5073 | "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", | |
5074 | plane->base.id, width, height); | |
5075 | else | |
5076 | drm_dbg(plane->dev, | |
5077 | "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", | |
5078 | plane->base.id, x, y, width, height); | |
5079 | ||
30ebe415 HM |
5080 | (*i)++; |
5081 | } | |
5082 | ||
5d945cbc RS |
5083 | /** |
5084 | * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates | |
5085 | * | |
5086 | * @plane: DRM plane containing dirty regions that need to be flushed to the eDP | |
5087 | * remote fb | |
5088 | * @old_plane_state: Old state of @plane | |
5089 | * @new_plane_state: New state of @plane | |
5090 | * @crtc_state: New state of CRTC connected to the @plane | |
5091 | * @flip_addrs: DC flip tracking struct, which also tracts dirty rects | |
d6ed6d0d | 5092 | * @dirty_regions_changed: dirty regions changed |
5d945cbc RS |
5093 | * |
5094 | * For PSR SU, DC informs the DMUB uController of dirty rectangle regions | |
5095 | * (referred to as "damage clips" in DRM nomenclature) that require updating on | |
5096 | * the eDP remote buffer. The responsibility of specifying the dirty regions is | |
5097 | * amdgpu_dm's. | |
5098 | * | |
5099 | * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the | |
5100 | * plane with regions that require flushing to the eDP remote buffer. In | |
5101 | * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - | |
5102 | * implicitly provide damage clips without any client support via the plane | |
5103 | * bounds. | |
5d945cbc RS |
5104 | */ |
5105 | static void fill_dc_dirty_rects(struct drm_plane *plane, | |
5106 | struct drm_plane_state *old_plane_state, | |
5107 | struct drm_plane_state *new_plane_state, | |
5108 | struct drm_crtc_state *crtc_state, | |
d6ed6d0d TC |
5109 | struct dc_flip_addrs *flip_addrs, |
5110 | bool *dirty_regions_changed) | |
5d945cbc RS |
5111 | { |
5112 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); | |
5113 | struct rect *dirty_rects = flip_addrs->dirty_rects; | |
ae67558b | 5114 | u32 num_clips; |
30ebe415 | 5115 | struct drm_mode_rect *clips; |
5d945cbc RS |
5116 | bool bb_changed; |
5117 | bool fb_changed; | |
ae67558b | 5118 | u32 i = 0; |
d6ed6d0d | 5119 | *dirty_regions_changed = false; |
e7b07cee | 5120 | |
7cc191ee LL |
5121 | /* |
5122 | * Cursor plane has it's own dirty rect update interface. See | |
5123 | * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data | |
5124 | */ | |
5125 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
5126 | return; | |
5127 | ||
30ebe415 HM |
5128 | num_clips = drm_plane_get_damage_clips_count(new_plane_state); |
5129 | clips = drm_plane_get_damage_clips(new_plane_state); | |
5130 | ||
7cc191ee | 5131 | if (!dm_crtc_state->mpo_requested) { |
30ebe415 HM |
5132 | if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) |
5133 | goto ffu; | |
5134 | ||
5135 | for (; flip_addrs->dirty_rect_count < num_clips; clips++) | |
5136 | fill_dc_dirty_rect(new_plane_state->plane, | |
566b6577 BC |
5137 | &dirty_rects[flip_addrs->dirty_rect_count], |
5138 | clips->x1, clips->y1, | |
5139 | clips->x2 - clips->x1, clips->y2 - clips->y1, | |
30ebe415 HM |
5140 | &flip_addrs->dirty_rect_count, |
5141 | false); | |
7cc191ee LL |
5142 | return; |
5143 | } | |
5144 | ||
5145 | /* | |
5146 | * MPO is requested. Add entire plane bounding box to dirty rects if | |
5147 | * flipped to or damaged. | |
5148 | * | |
5149 | * If plane is moved or resized, also add old bounding box to dirty | |
5150 | * rects. | |
5151 | */ | |
7cc191ee LL |
5152 | fb_changed = old_plane_state->fb->base.id != |
5153 | new_plane_state->fb->base.id; | |
5154 | bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || | |
5155 | old_plane_state->crtc_y != new_plane_state->crtc_y || | |
5156 | old_plane_state->crtc_w != new_plane_state->crtc_w || | |
5157 | old_plane_state->crtc_h != new_plane_state->crtc_h); | |
5158 | ||
30ebe415 HM |
5159 | drm_dbg(plane->dev, |
5160 | "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", | |
5161 | new_plane_state->plane->base.id, | |
5162 | bb_changed, fb_changed, num_clips); | |
7cc191ee | 5163 | |
d6ed6d0d TC |
5164 | *dirty_regions_changed = bb_changed; |
5165 | ||
af22d6a8 HM |
5166 | if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) |
5167 | goto ffu; | |
5168 | ||
7cc191ee | 5169 | if (bb_changed) { |
30ebe415 HM |
5170 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], |
5171 | new_plane_state->crtc_x, | |
5172 | new_plane_state->crtc_y, | |
5173 | new_plane_state->crtc_w, | |
5174 | new_plane_state->crtc_h, &i, false); | |
5175 | ||
5176 | /* Add old plane bounding-box if plane is moved or resized */ | |
5177 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], | |
5178 | old_plane_state->crtc_x, | |
5179 | old_plane_state->crtc_y, | |
5180 | old_plane_state->crtc_w, | |
5181 | old_plane_state->crtc_h, &i, false); | |
5182 | } | |
5183 | ||
5184 | if (num_clips) { | |
5185 | for (; i < num_clips; clips++) | |
5186 | fill_dc_dirty_rect(new_plane_state->plane, | |
5187 | &dirty_rects[i], clips->x1, | |
5188 | clips->y1, clips->x2 - clips->x1, | |
5189 | clips->y2 - clips->y1, &i, false); | |
5190 | } else if (fb_changed && !bb_changed) { | |
5191 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], | |
5192 | new_plane_state->crtc_x, | |
5193 | new_plane_state->crtc_y, | |
5194 | new_plane_state->crtc_w, | |
5195 | new_plane_state->crtc_h, &i, false); | |
5196 | } | |
5197 | ||
7cc191ee | 5198 | flip_addrs->dirty_rect_count = i; |
30ebe415 HM |
5199 | return; |
5200 | ||
5201 | ffu: | |
5202 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, | |
5203 | dm_crtc_state->base.mode.crtc_hdisplay, | |
5204 | dm_crtc_state->base.mode.crtc_vdisplay, | |
5205 | &flip_addrs->dirty_rect_count, true); | |
7cc191ee LL |
5206 | } |
5207 | ||
3ee6b26b AD |
5208 | static void update_stream_scaling_settings(const struct drm_display_mode *mode, |
5209 | const struct dm_connector_state *dm_state, | |
5210 | struct dc_stream_state *stream) | |
e7b07cee HW |
5211 | { |
5212 | enum amdgpu_rmx_type rmx_type; | |
5213 | ||
5214 | struct rect src = { 0 }; /* viewport in composition space*/ | |
5215 | struct rect dst = { 0 }; /* stream addressable area */ | |
5216 | ||
5217 | /* no mode. nothing to be done */ | |
5218 | if (!mode) | |
5219 | return; | |
5220 | ||
5221 | /* Full screen scaling by default */ | |
5222 | src.width = mode->hdisplay; | |
5223 | src.height = mode->vdisplay; | |
5224 | dst.width = stream->timing.h_addressable; | |
5225 | dst.height = stream->timing.v_addressable; | |
5226 | ||
f4791779 HW |
5227 | if (dm_state) { |
5228 | rmx_type = dm_state->scaling; | |
5229 | if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { | |
5230 | if (src.width * dst.height < | |
5231 | src.height * dst.width) { | |
5232 | /* height needs less upscaling/more downscaling */ | |
5233 | dst.width = src.width * | |
5234 | dst.height / src.height; | |
5235 | } else { | |
5236 | /* width needs less upscaling/more downscaling */ | |
5237 | dst.height = src.height * | |
5238 | dst.width / src.width; | |
5239 | } | |
5240 | } else if (rmx_type == RMX_CENTER) { | |
5241 | dst = src; | |
e7b07cee | 5242 | } |
e7b07cee | 5243 | |
f4791779 HW |
5244 | dst.x = (stream->timing.h_addressable - dst.width) / 2; |
5245 | dst.y = (stream->timing.v_addressable - dst.height) / 2; | |
e7b07cee | 5246 | |
f4791779 HW |
5247 | if (dm_state->underscan_enable) { |
5248 | dst.x += dm_state->underscan_hborder / 2; | |
5249 | dst.y += dm_state->underscan_vborder / 2; | |
5250 | dst.width -= dm_state->underscan_hborder; | |
5251 | dst.height -= dm_state->underscan_vborder; | |
5252 | } | |
e7b07cee HW |
5253 | } |
5254 | ||
5255 | stream->src = src; | |
5256 | stream->dst = dst; | |
5257 | ||
4711c033 LT |
5258 | DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", |
5259 | dst.x, dst.y, dst.width, dst.height); | |
e7b07cee HW |
5260 | |
5261 | } | |
5262 | ||
3ee6b26b | 5263 | static enum dc_color_depth |
42ba01fc | 5264 | convert_color_depth_from_display_info(const struct drm_connector *connector, |
cbd14ae7 | 5265 | bool is_y420, int requested_bpc) |
e7b07cee | 5266 | { |
ae67558b | 5267 | u8 bpc; |
01c22997 | 5268 | |
1bc22f20 SW |
5269 | if (is_y420) { |
5270 | bpc = 8; | |
5271 | ||
5272 | /* Cap display bpc based on HDMI 2.0 HF-VSDB */ | |
5273 | if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) | |
5274 | bpc = 16; | |
5275 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) | |
5276 | bpc = 12; | |
5277 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) | |
5278 | bpc = 10; | |
5279 | } else { | |
5280 | bpc = (uint8_t)connector->display_info.bpc; | |
5281 | /* Assume 8 bpc by default if no bpc is specified. */ | |
5282 | bpc = bpc ? bpc : 8; | |
5283 | } | |
e7b07cee | 5284 | |
cbd14ae7 | 5285 | if (requested_bpc > 0) { |
01c22997 NK |
5286 | /* |
5287 | * Cap display bpc based on the user requested value. | |
5288 | * | |
5289 | * The value for state->max_bpc may not correctly updated | |
5290 | * depending on when the connector gets added to the state | |
5291 | * or if this was called outside of atomic check, so it | |
5292 | * can't be used directly. | |
5293 | */ | |
cbd14ae7 | 5294 | bpc = min_t(u8, bpc, requested_bpc); |
01c22997 | 5295 | |
1825fd34 NK |
5296 | /* Round down to the nearest even number. */ |
5297 | bpc = bpc - (bpc & 1); | |
5298 | } | |
07e3a1cf | 5299 | |
e7b07cee HW |
5300 | switch (bpc) { |
5301 | case 0: | |
1f6010a9 DF |
5302 | /* |
5303 | * Temporary Work around, DRM doesn't parse color depth for | |
e7b07cee HW |
5304 | * EDID revision before 1.4 |
5305 | * TODO: Fix edid parsing | |
5306 | */ | |
5307 | return COLOR_DEPTH_888; | |
5308 | case 6: | |
5309 | return COLOR_DEPTH_666; | |
5310 | case 8: | |
5311 | return COLOR_DEPTH_888; | |
5312 | case 10: | |
5313 | return COLOR_DEPTH_101010; | |
5314 | case 12: | |
5315 | return COLOR_DEPTH_121212; | |
5316 | case 14: | |
5317 | return COLOR_DEPTH_141414; | |
5318 | case 16: | |
5319 | return COLOR_DEPTH_161616; | |
5320 | default: | |
5321 | return COLOR_DEPTH_UNDEFINED; | |
5322 | } | |
5323 | } | |
5324 | ||
3ee6b26b AD |
5325 | static enum dc_aspect_ratio |
5326 | get_aspect_ratio(const struct drm_display_mode *mode_in) | |
e7b07cee | 5327 | { |
e11d4147 LSL |
5328 | /* 1-1 mapping, since both enums follow the HDMI spec. */ |
5329 | return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; | |
e7b07cee HW |
5330 | } |
5331 | ||
3ee6b26b | 5332 | static enum dc_color_space |
2e656827 HW |
5333 | get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, |
5334 | const struct drm_connector_state *connector_state) | |
e7b07cee HW |
5335 | { |
5336 | enum dc_color_space color_space = COLOR_SPACE_SRGB; | |
5337 | ||
2e656827 HW |
5338 | switch (connector_state->colorspace) { |
5339 | case DRM_MODE_COLORIMETRY_BT601_YCC: | |
5340 | if (dc_crtc_timing->flags.Y_ONLY) | |
5341 | color_space = COLOR_SPACE_YCBCR601_LIMITED; | |
5342 | else | |
5343 | color_space = COLOR_SPACE_YCBCR601; | |
5344 | break; | |
5345 | case DRM_MODE_COLORIMETRY_BT709_YCC: | |
5346 | if (dc_crtc_timing->flags.Y_ONLY) | |
5347 | color_space = COLOR_SPACE_YCBCR709_LIMITED; | |
5348 | else | |
5349 | color_space = COLOR_SPACE_YCBCR709; | |
5350 | break; | |
5351 | case DRM_MODE_COLORIMETRY_OPRGB: | |
5352 | color_space = COLOR_SPACE_ADOBERGB; | |
5353 | break; | |
5354 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
5355 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
5356 | if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) | |
5357 | color_space = COLOR_SPACE_2020_RGB_FULLRANGE; | |
5358 | else | |
5359 | color_space = COLOR_SPACE_2020_YCBCR; | |
5360 | break; | |
5361 | case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 | |
5362 | default: | |
5363 | if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { | |
5364 | color_space = COLOR_SPACE_SRGB; | |
e7b07cee HW |
5365 | /* |
5366 | * 27030khz is the separation point between HDTV and SDTV | |
5367 | * according to HDMI spec, we use YCbCr709 and YCbCr601 | |
5368 | * respectively | |
5369 | */ | |
2e656827 | 5370 | } else if (dc_crtc_timing->pix_clk_100hz > 270300) { |
e7b07cee HW |
5371 | if (dc_crtc_timing->flags.Y_ONLY) |
5372 | color_space = | |
5373 | COLOR_SPACE_YCBCR709_LIMITED; | |
5374 | else | |
5375 | color_space = COLOR_SPACE_YCBCR709; | |
5376 | } else { | |
5377 | if (dc_crtc_timing->flags.Y_ONLY) | |
5378 | color_space = | |
5379 | COLOR_SPACE_YCBCR601_LIMITED; | |
5380 | else | |
5381 | color_space = COLOR_SPACE_YCBCR601; | |
5382 | } | |
e7b07cee HW |
5383 | break; |
5384 | } | |
5385 | ||
5386 | return color_space; | |
5387 | } | |
5388 | ||
ea117312 TA |
5389 | static bool adjust_colour_depth_from_display_info( |
5390 | struct dc_crtc_timing *timing_out, | |
5391 | const struct drm_display_info *info) | |
400443e8 | 5392 | { |
ea117312 | 5393 | enum dc_color_depth depth = timing_out->display_color_depth; |
400443e8 | 5394 | int normalized_clk; |
c82eddf8 | 5395 | |
400443e8 | 5396 | do { |
380604e2 | 5397 | normalized_clk = timing_out->pix_clk_100hz / 10; |
400443e8 ML |
5398 | /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ |
5399 | if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) | |
5400 | normalized_clk /= 2; | |
5401 | /* Adjusting pix clock following on HDMI spec based on colour depth */ | |
ea117312 TA |
5402 | switch (depth) { |
5403 | case COLOR_DEPTH_888: | |
5404 | break; | |
400443e8 ML |
5405 | case COLOR_DEPTH_101010: |
5406 | normalized_clk = (normalized_clk * 30) / 24; | |
5407 | break; | |
5408 | case COLOR_DEPTH_121212: | |
5409 | normalized_clk = (normalized_clk * 36) / 24; | |
5410 | break; | |
5411 | case COLOR_DEPTH_161616: | |
5412 | normalized_clk = (normalized_clk * 48) / 24; | |
5413 | break; | |
5414 | default: | |
ea117312 TA |
5415 | /* The above depths are the only ones valid for HDMI. */ |
5416 | return false; | |
400443e8 | 5417 | } |
ea117312 TA |
5418 | if (normalized_clk <= info->max_tmds_clock) { |
5419 | timing_out->display_color_depth = depth; | |
5420 | return true; | |
5421 | } | |
5422 | } while (--depth > COLOR_DEPTH_666); | |
5423 | return false; | |
400443e8 | 5424 | } |
e7b07cee | 5425 | |
42ba01fc NK |
5426 | static void fill_stream_properties_from_drm_display_mode( |
5427 | struct dc_stream_state *stream, | |
5428 | const struct drm_display_mode *mode_in, | |
5429 | const struct drm_connector *connector, | |
5430 | const struct drm_connector_state *connector_state, | |
cbd14ae7 SW |
5431 | const struct dc_stream_state *old_stream, |
5432 | int requested_bpc) | |
e7b07cee HW |
5433 | { |
5434 | struct dc_crtc_timing *timing_out = &stream->timing; | |
fe61a2f1 | 5435 | const struct drm_display_info *info = &connector->display_info; |
d4252eee | 5436 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
1cb1d477 WL |
5437 | struct hdmi_vendor_infoframe hv_frame; |
5438 | struct hdmi_avi_infoframe avi_frame; | |
e7b07cee | 5439 | |
acf83f86 WL |
5440 | memset(&hv_frame, 0, sizeof(hv_frame)); |
5441 | memset(&avi_frame, 0, sizeof(avi_frame)); | |
5442 | ||
e7b07cee HW |
5443 | timing_out->h_border_left = 0; |
5444 | timing_out->h_border_right = 0; | |
5445 | timing_out->v_border_top = 0; | |
5446 | timing_out->v_border_bottom = 0; | |
5447 | /* TODO: un-hardcode */ | |
fe61a2f1 | 5448 | if (drm_mode_is_420_only(info, mode_in) |
ceb3dbb4 | 5449 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
fe61a2f1 | 5450 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
d4252eee SW |
5451 | else if (drm_mode_is_420_also(info, mode_in) |
5452 | && aconnector->force_yuv420_output) | |
5453 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; | |
c03d0b52 | 5454 | else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) |
ceb3dbb4 | 5455 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
e7b07cee HW |
5456 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; |
5457 | else | |
5458 | timing_out->pixel_encoding = PIXEL_ENCODING_RGB; | |
5459 | ||
5460 | timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; | |
5461 | timing_out->display_color_depth = convert_color_depth_from_display_info( | |
cbd14ae7 SW |
5462 | connector, |
5463 | (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), | |
5464 | requested_bpc); | |
e7b07cee HW |
5465 | timing_out->scan_type = SCANNING_TYPE_NODATA; |
5466 | timing_out->hdmi_vic = 0; | |
b333730d | 5467 | |
5d945cbc | 5468 | if (old_stream) { |
b333730d BL |
5469 | timing_out->vic = old_stream->timing.vic; |
5470 | timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; | |
5471 | timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; | |
5472 | } else { | |
5473 | timing_out->vic = drm_match_cea_mode(mode_in); | |
5474 | if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) | |
5475 | timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; | |
5476 | if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) | |
5477 | timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; | |
5478 | } | |
e7b07cee | 5479 | |
1cb1d477 WL |
5480 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
5481 | drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); | |
5482 | timing_out->vic = avi_frame.video_code; | |
5483 | drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); | |
5484 | timing_out->hdmi_vic = hv_frame.vic; | |
5485 | } | |
5486 | ||
fe8858bb NC |
5487 | if (is_freesync_video_mode(mode_in, aconnector)) { |
5488 | timing_out->h_addressable = mode_in->hdisplay; | |
5489 | timing_out->h_total = mode_in->htotal; | |
5490 | timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; | |
5491 | timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; | |
5492 | timing_out->v_total = mode_in->vtotal; | |
5493 | timing_out->v_addressable = mode_in->vdisplay; | |
5494 | timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; | |
5495 | timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; | |
5496 | timing_out->pix_clk_100hz = mode_in->clock * 10; | |
5497 | } else { | |
5498 | timing_out->h_addressable = mode_in->crtc_hdisplay; | |
5499 | timing_out->h_total = mode_in->crtc_htotal; | |
5500 | timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; | |
5501 | timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; | |
5502 | timing_out->v_total = mode_in->crtc_vtotal; | |
5503 | timing_out->v_addressable = mode_in->crtc_vdisplay; | |
5504 | timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; | |
5505 | timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; | |
5506 | timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; | |
5507 | } | |
a85ba005 | 5508 | |
e7b07cee | 5509 | timing_out->aspect_ratio = get_aspect_ratio(mode_in); |
e7b07cee | 5510 | |
e43a432c AK |
5511 | stream->out_transfer_func->type = TF_TYPE_PREDEFINED; |
5512 | stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; | |
ea117312 TA |
5513 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
5514 | if (!adjust_colour_depth_from_display_info(timing_out, info) && | |
5515 | drm_mode_is_420_also(info, mode_in) && | |
5516 | timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { | |
5517 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; | |
5518 | adjust_colour_depth_from_display_info(timing_out, info); | |
5519 | } | |
5520 | } | |
766f1792 | 5521 | |
2e656827 | 5522 | stream->output_color_space = get_output_color_space(timing_out, connector_state); |
e7b07cee HW |
5523 | } |
5524 | ||
3ee6b26b AD |
5525 | static void fill_audio_info(struct audio_info *audio_info, |
5526 | const struct drm_connector *drm_connector, | |
5527 | const struct dc_sink *dc_sink) | |
e7b07cee HW |
5528 | { |
5529 | int i = 0; | |
5530 | int cea_revision = 0; | |
5531 | const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; | |
5532 | ||
5533 | audio_info->manufacture_id = edid_caps->manufacturer_id; | |
5534 | audio_info->product_id = edid_caps->product_id; | |
5535 | ||
5536 | cea_revision = drm_connector->display_info.cea_rev; | |
5537 | ||
090afc1e | 5538 | strscpy(audio_info->display_name, |
d2b2562c | 5539 | edid_caps->display_name, |
090afc1e | 5540 | AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); |
e7b07cee | 5541 | |
b830ebc9 | 5542 | if (cea_revision >= 3) { |
e7b07cee HW |
5543 | audio_info->mode_count = edid_caps->audio_mode_count; |
5544 | ||
5545 | for (i = 0; i < audio_info->mode_count; ++i) { | |
5546 | audio_info->modes[i].format_code = | |
5547 | (enum audio_format_code) | |
5548 | (edid_caps->audio_modes[i].format_code); | |
5549 | audio_info->modes[i].channel_count = | |
5550 | edid_caps->audio_modes[i].channel_count; | |
5551 | audio_info->modes[i].sample_rates.all = | |
5552 | edid_caps->audio_modes[i].sample_rate; | |
5553 | audio_info->modes[i].sample_size = | |
5554 | edid_caps->audio_modes[i].sample_size; | |
5555 | } | |
5556 | } | |
5557 | ||
5558 | audio_info->flags.all = edid_caps->speaker_flags; | |
5559 | ||
5560 | /* TODO: We only check for the progressive mode, check for interlace mode too */ | |
b830ebc9 | 5561 | if (drm_connector->latency_present[0]) { |
e7b07cee HW |
5562 | audio_info->video_latency = drm_connector->video_latency[0]; |
5563 | audio_info->audio_latency = drm_connector->audio_latency[0]; | |
5564 | } | |
5565 | ||
5566 | /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ | |
5567 | ||
5568 | } | |
5569 | ||
3ee6b26b AD |
5570 | static void |
5571 | copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, | |
5572 | struct drm_display_mode *dst_mode) | |
e7b07cee HW |
5573 | { |
5574 | dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; | |
5575 | dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; | |
5576 | dst_mode->crtc_clock = src_mode->crtc_clock; | |
5577 | dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; | |
5578 | dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; | |
b830ebc9 | 5579 | dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; |
e7b07cee HW |
5580 | dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; |
5581 | dst_mode->crtc_htotal = src_mode->crtc_htotal; | |
5582 | dst_mode->crtc_hskew = src_mode->crtc_hskew; | |
5583 | dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; | |
5584 | dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; | |
5585 | dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; | |
5586 | dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; | |
5587 | dst_mode->crtc_vtotal = src_mode->crtc_vtotal; | |
5588 | } | |
5589 | ||
3ee6b26b AD |
5590 | static void |
5591 | decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, | |
5592 | const struct drm_display_mode *native_mode, | |
5593 | bool scale_enabled) | |
e7b07cee HW |
5594 | { |
5595 | if (scale_enabled) { | |
5596 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
5597 | } else if (native_mode->clock == drm_mode->clock && | |
5598 | native_mode->htotal == drm_mode->htotal && | |
5599 | native_mode->vtotal == drm_mode->vtotal) { | |
5600 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
5601 | } else { | |
5602 | /* no scaling nor amdgpu inserted, no need to patch */ | |
5603 | } | |
5604 | } | |
5605 | ||
aed15309 ML |
5606 | static struct dc_sink * |
5607 | create_fake_sink(struct amdgpu_dm_connector *aconnector) | |
2e0ac3d6 | 5608 | { |
2e0ac3d6 | 5609 | struct dc_sink_init_data sink_init_data = { 0 }; |
aed15309 | 5610 | struct dc_sink *sink = NULL; |
c82eddf8 | 5611 | |
2e0ac3d6 HW |
5612 | sink_init_data.link = aconnector->dc_link; |
5613 | sink_init_data.sink_signal = aconnector->dc_link->connector_signal; | |
5614 | ||
5615 | sink = dc_sink_create(&sink_init_data); | |
423788c7 | 5616 | if (!sink) { |
2e0ac3d6 | 5617 | DRM_ERROR("Failed to create sink!\n"); |
aed15309 | 5618 | return NULL; |
423788c7 | 5619 | } |
2e0ac3d6 | 5620 | sink->sink_signal = SIGNAL_TYPE_VIRTUAL; |
423788c7 | 5621 | |
aed15309 | 5622 | return sink; |
2e0ac3d6 HW |
5623 | } |
5624 | ||
fa2123db ML |
5625 | static void set_multisync_trigger_params( |
5626 | struct dc_stream_state *stream) | |
5627 | { | |
ec372186 ML |
5628 | struct dc_stream_state *master = NULL; |
5629 | ||
fa2123db | 5630 | if (stream->triggered_crtc_reset.enabled) { |
ec372186 ML |
5631 | master = stream->triggered_crtc_reset.event_source; |
5632 | stream->triggered_crtc_reset.event = | |
5633 | master->timing.flags.VSYNC_POSITIVE_POLARITY ? | |
5634 | CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; | |
5635 | stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; | |
fa2123db ML |
5636 | } |
5637 | } | |
5638 | ||
5639 | static void set_master_stream(struct dc_stream_state *stream_set[], | |
5640 | int stream_count) | |
5641 | { | |
5642 | int j, highest_rfr = 0, master_stream = 0; | |
5643 | ||
5644 | for (j = 0; j < stream_count; j++) { | |
5645 | if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { | |
5646 | int refresh_rate = 0; | |
5647 | ||
380604e2 | 5648 | refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ |
fa2123db ML |
5649 | (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); |
5650 | if (refresh_rate > highest_rfr) { | |
5651 | highest_rfr = refresh_rate; | |
5652 | master_stream = j; | |
5653 | } | |
5654 | } | |
5655 | } | |
5656 | for (j = 0; j < stream_count; j++) { | |
03736f4c | 5657 | if (stream_set[j]) |
fa2123db ML |
5658 | stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; |
5659 | } | |
5660 | } | |
5661 | ||
5662 | static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) | |
5663 | { | |
5664 | int i = 0; | |
ec372186 | 5665 | struct dc_stream_state *stream; |
fa2123db ML |
5666 | |
5667 | if (context->stream_count < 2) | |
5668 | return; | |
5669 | for (i = 0; i < context->stream_count ; i++) { | |
5670 | if (!context->streams[i]) | |
5671 | continue; | |
1f6010a9 DF |
5672 | /* |
5673 | * TODO: add a function to read AMD VSDB bits and set | |
fa2123db | 5674 | * crtc_sync_master.multi_sync_enabled flag |
1f6010a9 | 5675 | * For now it's set to false |
fa2123db | 5676 | */ |
fa2123db | 5677 | } |
ec372186 | 5678 | |
fa2123db | 5679 | set_master_stream(context->streams, context->stream_count); |
ec372186 ML |
5680 | |
5681 | for (i = 0; i < context->stream_count ; i++) { | |
5682 | stream = context->streams[i]; | |
5683 | ||
5684 | if (!stream) | |
5685 | continue; | |
5686 | ||
5687 | set_multisync_trigger_params(stream); | |
5688 | } | |
fa2123db ML |
5689 | } |
5690 | ||
5d945cbc RS |
5691 | /** |
5692 | * DOC: FreeSync Video | |
5693 | * | |
5694 | * When a userspace application wants to play a video, the content follows a | |
5695 | * standard format definition that usually specifies the FPS for that format. | |
5696 | * The below list illustrates some video format and the expected FPS, | |
5697 | * respectively: | |
5698 | * | |
5699 | * - TV/NTSC (23.976 FPS) | |
5700 | * - Cinema (24 FPS) | |
5701 | * - TV/PAL (25 FPS) | |
5702 | * - TV/NTSC (29.97 FPS) | |
5703 | * - TV/NTSC (30 FPS) | |
5704 | * - Cinema HFR (48 FPS) | |
5705 | * - TV/PAL (50 FPS) | |
5706 | * - Commonly used (60 FPS) | |
5707 | * - Multiples of 24 (48,72,96 FPS) | |
5708 | * | |
5709 | * The list of standards video format is not huge and can be added to the | |
5710 | * connector modeset list beforehand. With that, userspace can leverage | |
5711 | * FreeSync to extends the front porch in order to attain the target refresh | |
5712 | * rate. Such a switch will happen seamlessly, without screen blanking or | |
5713 | * reprogramming of the output in any other way. If the userspace requests a | |
5714 | * modesetting change compatible with FreeSync modes that only differ in the | |
5715 | * refresh rate, DC will skip the full update and avoid blink during the | |
5716 | * transition. For example, the video player can change the modesetting from | |
5717 | * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without | |
5718 | * causing any display blink. This same concept can be applied to a mode | |
5719 | * setting change. | |
5720 | */ | |
5721 | static struct drm_display_mode * | |
5722 | get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, | |
5723 | bool use_probed_modes) | |
5724 | { | |
5725 | struct drm_display_mode *m, *m_pref = NULL; | |
5726 | u16 current_refresh, highest_refresh; | |
5727 | struct list_head *list_head = use_probed_modes ? | |
5728 | &aconnector->base.probed_modes : | |
5729 | &aconnector->base.modes; | |
5730 | ||
5731 | if (aconnector->freesync_vid_base.clock != 0) | |
5732 | return &aconnector->freesync_vid_base; | |
5733 | ||
5734 | /* Find the preferred mode */ | |
c82eddf8 | 5735 | list_for_each_entry(m, list_head, head) { |
5d945cbc RS |
5736 | if (m->type & DRM_MODE_TYPE_PREFERRED) { |
5737 | m_pref = m; | |
5738 | break; | |
5739 | } | |
5740 | } | |
5741 | ||
5742 | if (!m_pref) { | |
5743 | /* Probably an EDID with no preferred mode. Fallback to first entry */ | |
5744 | m_pref = list_first_entry_or_null( | |
5745 | &aconnector->base.modes, struct drm_display_mode, head); | |
5746 | if (!m_pref) { | |
5747 | DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); | |
5748 | return NULL; | |
5749 | } | |
5750 | } | |
5751 | ||
5752 | highest_refresh = drm_mode_vrefresh(m_pref); | |
5753 | ||
5754 | /* | |
5755 | * Find the mode with highest refresh rate with same resolution. | |
5756 | * For some monitors, preferred mode is not the mode with highest | |
5757 | * supported refresh rate. | |
5758 | */ | |
c82eddf8 | 5759 | list_for_each_entry(m, list_head, head) { |
5d945cbc RS |
5760 | current_refresh = drm_mode_vrefresh(m); |
5761 | ||
5762 | if (m->hdisplay == m_pref->hdisplay && | |
5763 | m->vdisplay == m_pref->vdisplay && | |
5764 | highest_refresh < current_refresh) { | |
5765 | highest_refresh = current_refresh; | |
5766 | m_pref = m; | |
5767 | } | |
5768 | } | |
5769 | ||
5770 | drm_mode_copy(&aconnector->freesync_vid_base, m_pref); | |
5771 | return m_pref; | |
5772 | } | |
5773 | ||
5774 | static bool is_freesync_video_mode(const struct drm_display_mode *mode, | |
5775 | struct amdgpu_dm_connector *aconnector) | |
5776 | { | |
5777 | struct drm_display_mode *high_mode; | |
5778 | int timing_diff; | |
5779 | ||
5780 | high_mode = get_highest_refresh_rate_mode(aconnector, false); | |
5781 | if (!high_mode || !mode) | |
5782 | return false; | |
5783 | ||
5784 | timing_diff = high_mode->vtotal - mode->vtotal; | |
5785 | ||
5786 | if (high_mode->clock == 0 || high_mode->clock != mode->clock || | |
5787 | high_mode->hdisplay != mode->hdisplay || | |
5788 | high_mode->vdisplay != mode->vdisplay || | |
5789 | high_mode->hsync_start != mode->hsync_start || | |
5790 | high_mode->hsync_end != mode->hsync_end || | |
5791 | high_mode->htotal != mode->htotal || | |
5792 | high_mode->hskew != mode->hskew || | |
5793 | high_mode->vscan != mode->vscan || | |
5794 | high_mode->vsync_start - mode->vsync_start != timing_diff || | |
5795 | high_mode->vsync_end - mode->vsync_end != timing_diff) | |
5796 | return false; | |
5797 | else | |
5798 | return true; | |
5799 | } | |
5800 | ||
998b7ad2 | 5801 | static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, |
5d945cbc RS |
5802 | struct dc_sink *sink, struct dc_stream_state *stream, |
5803 | struct dsc_dec_dpcd_caps *dsc_caps) | |
998b7ad2 FZ |
5804 | { |
5805 | stream->timing.flags.DSC = 0; | |
63ad5371 | 5806 | dsc_caps->is_dsc_supported = false; |
998b7ad2 | 5807 | |
2665f63a | 5808 | if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || |
5d945cbc | 5809 | sink->sink_signal == SIGNAL_TYPE_EDP)) { |
50b1f44e FZ |
5810 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || |
5811 | sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) | |
5812 | dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, | |
5813 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, | |
5814 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, | |
5815 | dsc_caps); | |
998b7ad2 FZ |
5816 | } |
5817 | } | |
5818 | ||
5d945cbc | 5819 | |
2665f63a ML |
5820 | static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, |
5821 | struct dc_sink *sink, struct dc_stream_state *stream, | |
5822 | struct dsc_dec_dpcd_caps *dsc_caps, | |
5823 | uint32_t max_dsc_target_bpp_limit_override) | |
5824 | { | |
5825 | const struct dc_link_settings *verified_link_cap = NULL; | |
ae67558b SS |
5826 | u32 link_bw_in_kbps; |
5827 | u32 edp_min_bpp_x16, edp_max_bpp_x16; | |
2665f63a ML |
5828 | struct dc *dc = sink->ctx->dc; |
5829 | struct dc_dsc_bw_range bw_range = {0}; | |
5830 | struct dc_dsc_config dsc_cfg = {0}; | |
de534c1c MH |
5831 | struct dc_dsc_config_options dsc_options = {0}; |
5832 | ||
5833 | dc_dsc_get_default_config_option(dc, &dsc_options); | |
5834 | dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; | |
2665f63a ML |
5835 | |
5836 | verified_link_cap = dc_link_get_link_cap(stream->link); | |
5837 | link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); | |
5838 | edp_min_bpp_x16 = 8 * 16; | |
5839 | edp_max_bpp_x16 = 8 * 16; | |
5840 | ||
5841 | if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) | |
5842 | edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; | |
5843 | ||
5844 | if (edp_max_bpp_x16 < edp_min_bpp_x16) | |
5845 | edp_min_bpp_x16 = edp_max_bpp_x16; | |
5846 | ||
5847 | if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], | |
5848 | dc->debug.dsc_min_slice_height_override, | |
5849 | edp_min_bpp_x16, edp_max_bpp_x16, | |
5850 | dsc_caps, | |
5851 | &stream->timing, | |
5852 | &bw_range)) { | |
5853 | ||
5854 | if (bw_range.max_kbps < link_bw_in_kbps) { | |
5855 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], | |
5856 | dsc_caps, | |
de534c1c | 5857 | &dsc_options, |
2665f63a ML |
5858 | 0, |
5859 | &stream->timing, | |
5860 | &dsc_cfg)) { | |
5861 | stream->timing.dsc_cfg = dsc_cfg; | |
5862 | stream->timing.flags.DSC = 1; | |
5863 | stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; | |
5864 | } | |
5865 | return; | |
5866 | } | |
5867 | } | |
5868 | ||
5869 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], | |
5870 | dsc_caps, | |
de534c1c | 5871 | &dsc_options, |
2665f63a ML |
5872 | link_bw_in_kbps, |
5873 | &stream->timing, | |
5874 | &dsc_cfg)) { | |
5875 | stream->timing.dsc_cfg = dsc_cfg; | |
5876 | stream->timing.flags.DSC = 1; | |
5877 | } | |
5878 | } | |
5879 | ||
5d945cbc | 5880 | |
998b7ad2 | 5881 | static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, |
5d945cbc RS |
5882 | struct dc_sink *sink, struct dc_stream_state *stream, |
5883 | struct dsc_dec_dpcd_caps *dsc_caps) | |
998b7ad2 FZ |
5884 | { |
5885 | struct drm_connector *drm_connector = &aconnector->base; | |
ae67558b | 5886 | u32 link_bandwidth_kbps; |
2665f63a | 5887 | struct dc *dc = sink->ctx->dc; |
ae67558b SS |
5888 | u32 max_supported_bw_in_kbps, timing_bw_in_kbps; |
5889 | u32 dsc_max_supported_bw_in_kbps; | |
5890 | u32 max_dsc_target_bpp_limit_override = | |
6e5abe94 | 5891 | drm_connector->display_info.max_dsc_bpp; |
de534c1c MH |
5892 | struct dc_dsc_config_options dsc_options = {0}; |
5893 | ||
5894 | dc_dsc_get_default_config_option(dc, &dsc_options); | |
5895 | dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; | |
998b7ad2 FZ |
5896 | |
5897 | link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, | |
5898 | dc_link_get_link_cap(aconnector->dc_link)); | |
de7cc1b4 | 5899 | |
998b7ad2 FZ |
5900 | /* Set DSC policy according to dsc_clock_en */ |
5901 | dc_dsc_policy_set_enable_dsc_when_not_needed( | |
5902 | aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); | |
5903 | ||
c17a34e0 IC |
5904 | if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && |
5905 | !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && | |
2665f63a ML |
5906 | dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { |
5907 | ||
5908 | apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); | |
5909 | ||
5910 | } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { | |
50b1f44e FZ |
5911 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { |
5912 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], | |
998b7ad2 | 5913 | dsc_caps, |
de534c1c | 5914 | &dsc_options, |
998b7ad2 FZ |
5915 | link_bandwidth_kbps, |
5916 | &stream->timing, | |
5917 | &stream->timing.dsc_cfg)) { | |
50b1f44e | 5918 | stream->timing.flags.DSC = 1; |
5d945cbc | 5919 | DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); |
50b1f44e FZ |
5920 | } |
5921 | } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { | |
5922 | timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); | |
5923 | max_supported_bw_in_kbps = link_bandwidth_kbps; | |
5924 | dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; | |
5925 | ||
5926 | if (timing_bw_in_kbps > max_supported_bw_in_kbps && | |
5927 | max_supported_bw_in_kbps > 0 && | |
5928 | dsc_max_supported_bw_in_kbps > 0) | |
5929 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], | |
5930 | dsc_caps, | |
de534c1c | 5931 | &dsc_options, |
50b1f44e FZ |
5932 | dsc_max_supported_bw_in_kbps, |
5933 | &stream->timing, | |
5934 | &stream->timing.dsc_cfg)) { | |
5935 | stream->timing.flags.DSC = 1; | |
5936 | DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", | |
5937 | __func__, drm_connector->name); | |
5938 | } | |
998b7ad2 FZ |
5939 | } |
5940 | } | |
5941 | ||
5942 | /* Overwrite the stream flag if DSC is enabled through debugfs */ | |
5943 | if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) | |
5944 | stream->timing.flags.DSC = 1; | |
5945 | ||
5d945cbc RS |
5946 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) |
5947 | stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; | |
a85ba005 | 5948 | |
5d945cbc RS |
5949 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) |
5950 | stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; | |
a85ba005 | 5951 | |
5d945cbc RS |
5952 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) |
5953 | stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; | |
a85ba005 NC |
5954 | } |
5955 | ||
f11d9373 | 5956 | static struct dc_stream_state * |
3ee6b26b AD |
5957 | create_stream_for_sink(struct amdgpu_dm_connector *aconnector, |
5958 | const struct drm_display_mode *drm_mode, | |
b333730d | 5959 | const struct dm_connector_state *dm_state, |
cbd14ae7 SW |
5960 | const struct dc_stream_state *old_stream, |
5961 | int requested_bpc) | |
e7b07cee HW |
5962 | { |
5963 | struct drm_display_mode *preferred_mode = NULL; | |
391ef035 | 5964 | struct drm_connector *drm_connector; |
cb841d27 | 5965 | const struct drm_connector_state *con_state = &dm_state->base; |
0971c40e | 5966 | struct dc_stream_state *stream = NULL; |
0a204ce0 | 5967 | struct drm_display_mode mode; |
a85ba005 NC |
5968 | struct drm_display_mode saved_mode; |
5969 | struct drm_display_mode *freesync_mode = NULL; | |
e7b07cee | 5970 | bool native_mode_found = false; |
b0781603 | 5971 | bool recalculate_timing = false; |
cb841d27 | 5972 | bool scale = dm_state->scaling != RMX_OFF; |
b333730d | 5973 | int mode_refresh; |
58124bf8 | 5974 | int preferred_refresh = 0; |
b1a98cf8 | 5975 | enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; |
df2f1015 | 5976 | struct dsc_dec_dpcd_caps dsc_caps; |
5d945cbc | 5977 | |
aed15309 | 5978 | struct dc_sink *sink = NULL; |
a85ba005 | 5979 | |
0a204ce0 | 5980 | drm_mode_init(&mode, drm_mode); |
a85ba005 NC |
5981 | memset(&saved_mode, 0, sizeof(saved_mode)); |
5982 | ||
b830ebc9 | 5983 | if (aconnector == NULL) { |
e7b07cee | 5984 | DRM_ERROR("aconnector is NULL!\n"); |
64245fa7 | 5985 | return stream; |
e7b07cee HW |
5986 | } |
5987 | ||
e7b07cee | 5988 | drm_connector = &aconnector->base; |
2e0ac3d6 | 5989 | |
f4ac176e | 5990 | if (!aconnector->dc_sink) { |
e3fa5c4c JFZ |
5991 | sink = create_fake_sink(aconnector); |
5992 | if (!sink) | |
5993 | return stream; | |
aed15309 ML |
5994 | } else { |
5995 | sink = aconnector->dc_sink; | |
dcd5fb82 | 5996 | dc_sink_retain(sink); |
f4ac176e | 5997 | } |
2e0ac3d6 | 5998 | |
aed15309 | 5999 | stream = dc_create_stream_for_sink(sink); |
4562236b | 6000 | |
b830ebc9 | 6001 | if (stream == NULL) { |
e7b07cee | 6002 | DRM_ERROR("Failed to create stream for sink!\n"); |
aed15309 | 6003 | goto finish; |
e7b07cee HW |
6004 | } |
6005 | ||
ceb3dbb4 JL |
6006 | stream->dm_stream_context = aconnector; |
6007 | ||
4a36fcba WL |
6008 | stream->timing.flags.LTE_340MCSC_SCRAMBLE = |
6009 | drm_connector->display_info.hdmi.scdc.scrambling.low_rates; | |
6010 | ||
e7b07cee HW |
6011 | list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { |
6012 | /* Search for preferred mode */ | |
6013 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { | |
6014 | native_mode_found = true; | |
6015 | break; | |
6016 | } | |
6017 | } | |
6018 | if (!native_mode_found) | |
6019 | preferred_mode = list_first_entry_or_null( | |
6020 | &aconnector->base.modes, | |
6021 | struct drm_display_mode, | |
6022 | head); | |
6023 | ||
b333730d BL |
6024 | mode_refresh = drm_mode_vrefresh(&mode); |
6025 | ||
b830ebc9 | 6026 | if (preferred_mode == NULL) { |
1f6010a9 DF |
6027 | /* |
6028 | * This may not be an error, the use case is when we have no | |
e7b07cee HW |
6029 | * usermode calls to reset and set mode upon hotplug. In this |
6030 | * case, we call set mode ourselves to restore the previous mode | |
c82eddf8 | 6031 | * and the modelist may not be filled in time. |
e7b07cee | 6032 | */ |
f1ad2f5e | 6033 | DRM_DEBUG_DRIVER("No preferred mode found\n"); |
e7b07cee | 6034 | } else { |
11b92df8 | 6035 | recalculate_timing = is_freesync_video_mode(&mode, aconnector); |
a85ba005 NC |
6036 | if (recalculate_timing) { |
6037 | freesync_mode = get_highest_refresh_rate_mode(aconnector, false); | |
426c89aa VS |
6038 | drm_mode_copy(&saved_mode, &mode); |
6039 | drm_mode_copy(&mode, freesync_mode); | |
a85ba005 NC |
6040 | } else { |
6041 | decide_crtc_timing_for_drm_display_mode( | |
5d945cbc | 6042 | &mode, preferred_mode, scale); |
a85ba005 | 6043 | |
b0781603 NK |
6044 | preferred_refresh = drm_mode_vrefresh(preferred_mode); |
6045 | } | |
e7b07cee HW |
6046 | } |
6047 | ||
a85ba005 NC |
6048 | if (recalculate_timing) |
6049 | drm_mode_set_crtcinfo(&saved_mode, 0); | |
bd49f190 | 6050 | else |
f783577c JFZ |
6051 | drm_mode_set_crtcinfo(&mode, 0); |
6052 | ||
5d945cbc | 6053 | /* |
c82eddf8 SS |
6054 | * If scaling is enabled and refresh rate didn't change |
6055 | * we copy the vic and polarities of the old timings | |
6056 | */ | |
b0781603 | 6057 | if (!scale || mode_refresh != preferred_refresh) |
a85ba005 NC |
6058 | fill_stream_properties_from_drm_display_mode( |
6059 | stream, &mode, &aconnector->base, con_state, NULL, | |
6060 | requested_bpc); | |
b333730d | 6061 | else |
a85ba005 NC |
6062 | fill_stream_properties_from_drm_display_mode( |
6063 | stream, &mode, &aconnector->base, con_state, old_stream, | |
6064 | requested_bpc); | |
b333730d | 6065 | |
028c4ccf QZ |
6066 | if (aconnector->timing_changed) { |
6067 | DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n", | |
6068 | __func__, | |
6069 | stream->timing.display_color_depth, | |
6070 | aconnector->timing_requested->display_color_depth); | |
6071 | stream->timing = *aconnector->timing_requested; | |
6072 | } | |
6073 | ||
998b7ad2 FZ |
6074 | /* SST DSC determination policy */ |
6075 | update_dsc_caps(aconnector, sink, stream, &dsc_caps); | |
6076 | if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) | |
6077 | apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); | |
39a4eb85 | 6078 | |
e7b07cee HW |
6079 | update_stream_scaling_settings(&mode, dm_state, stream); |
6080 | ||
6081 | fill_audio_info( | |
6082 | &stream->audio_info, | |
6083 | drm_connector, | |
aed15309 | 6084 | sink); |
e7b07cee | 6085 | |
ceb3dbb4 | 6086 | update_stream_signal(stream, sink); |
9182b4cb | 6087 | |
d832fc3b | 6088 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
75f77aaf WL |
6089 | mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); |
6090 | ||
8a488f5d RL |
6091 | if (stream->link->psr_settings.psr_feature_enabled) { |
6092 | // | |
6093 | // should decide stream support vsc sdp colorimetry capability | |
6094 | // before building vsc info packet | |
6095 | // | |
6096 | stream->use_vsc_sdp_for_colorimetry = false; | |
6097 | if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { | |
6098 | stream->use_vsc_sdp_for_colorimetry = | |
6099 | aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; | |
6100 | } else { | |
6101 | if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) | |
6102 | stream->use_vsc_sdp_for_colorimetry = true; | |
8c322309 | 6103 | } |
b1a98cf8 MH |
6104 | if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) |
6105 | tf = TRANSFER_FUNC_GAMMA_22; | |
6106 | mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); | |
1a365683 RL |
6107 | aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; |
6108 | ||
8c322309 | 6109 | } |
aed15309 | 6110 | finish: |
dcd5fb82 | 6111 | dc_sink_release(sink); |
9e3efe3e | 6112 | |
e7b07cee HW |
6113 | return stream; |
6114 | } | |
6115 | ||
e7b07cee HW |
6116 | static enum drm_connector_status |
6117 | amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) | |
6118 | { | |
6119 | bool connected; | |
c84dec2f | 6120 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee | 6121 | |
1f6010a9 DF |
6122 | /* |
6123 | * Notes: | |
e7b07cee HW |
6124 | * 1. This interface is NOT called in context of HPD irq. |
6125 | * 2. This interface *is called* in context of user-mode ioctl. Which | |
1f6010a9 DF |
6126 | * makes it a bad place for *any* MST-related activity. |
6127 | */ | |
e7b07cee | 6128 | |
8580d60b HW |
6129 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && |
6130 | !aconnector->fake_enable) | |
e7b07cee HW |
6131 | connected = (aconnector->dc_sink != NULL); |
6132 | else | |
5d945cbc RS |
6133 | connected = (aconnector->base.force == DRM_FORCE_ON || |
6134 | aconnector->base.force == DRM_FORCE_ON_DIGITAL); | |
e7b07cee | 6135 | |
0f877894 OV |
6136 | update_subconnector_property(aconnector); |
6137 | ||
e7b07cee HW |
6138 | return (connected ? connector_status_connected : |
6139 | connector_status_disconnected); | |
6140 | } | |
6141 | ||
3ee6b26b AD |
6142 | int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, |
6143 | struct drm_connector_state *connector_state, | |
6144 | struct drm_property *property, | |
6145 | uint64_t val) | |
e7b07cee HW |
6146 | { |
6147 | struct drm_device *dev = connector->dev; | |
1348969a | 6148 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
6149 | struct dm_connector_state *dm_old_state = |
6150 | to_dm_connector_state(connector->state); | |
6151 | struct dm_connector_state *dm_new_state = | |
6152 | to_dm_connector_state(connector_state); | |
6153 | ||
6154 | int ret = -EINVAL; | |
6155 | ||
6156 | if (property == dev->mode_config.scaling_mode_property) { | |
6157 | enum amdgpu_rmx_type rmx_type; | |
6158 | ||
6159 | switch (val) { | |
6160 | case DRM_MODE_SCALE_CENTER: | |
6161 | rmx_type = RMX_CENTER; | |
6162 | break; | |
6163 | case DRM_MODE_SCALE_ASPECT: | |
6164 | rmx_type = RMX_ASPECT; | |
6165 | break; | |
6166 | case DRM_MODE_SCALE_FULLSCREEN: | |
6167 | rmx_type = RMX_FULL; | |
6168 | break; | |
6169 | case DRM_MODE_SCALE_NONE: | |
6170 | default: | |
6171 | rmx_type = RMX_OFF; | |
6172 | break; | |
6173 | } | |
6174 | ||
6175 | if (dm_old_state->scaling == rmx_type) | |
6176 | return 0; | |
6177 | ||
6178 | dm_new_state->scaling = rmx_type; | |
6179 | ret = 0; | |
6180 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
6181 | dm_new_state->underscan_hborder = val; | |
6182 | ret = 0; | |
6183 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
6184 | dm_new_state->underscan_vborder = val; | |
6185 | ret = 0; | |
6186 | } else if (property == adev->mode_info.underscan_property) { | |
6187 | dm_new_state->underscan_enable = val; | |
6188 | ret = 0; | |
c1ee92f9 DF |
6189 | } else if (property == adev->mode_info.abm_level_property) { |
6190 | dm_new_state->abm_level = val; | |
6191 | ret = 0; | |
e7b07cee HW |
6192 | } |
6193 | ||
6194 | return ret; | |
6195 | } | |
6196 | ||
3ee6b26b AD |
6197 | int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, |
6198 | const struct drm_connector_state *state, | |
6199 | struct drm_property *property, | |
6200 | uint64_t *val) | |
e7b07cee HW |
6201 | { |
6202 | struct drm_device *dev = connector->dev; | |
1348969a | 6203 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
6204 | struct dm_connector_state *dm_state = |
6205 | to_dm_connector_state(state); | |
6206 | int ret = -EINVAL; | |
6207 | ||
6208 | if (property == dev->mode_config.scaling_mode_property) { | |
6209 | switch (dm_state->scaling) { | |
6210 | case RMX_CENTER: | |
6211 | *val = DRM_MODE_SCALE_CENTER; | |
6212 | break; | |
6213 | case RMX_ASPECT: | |
6214 | *val = DRM_MODE_SCALE_ASPECT; | |
6215 | break; | |
6216 | case RMX_FULL: | |
6217 | *val = DRM_MODE_SCALE_FULLSCREEN; | |
6218 | break; | |
6219 | case RMX_OFF: | |
6220 | default: | |
6221 | *val = DRM_MODE_SCALE_NONE; | |
6222 | break; | |
6223 | } | |
6224 | ret = 0; | |
6225 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
6226 | *val = dm_state->underscan_hborder; | |
6227 | ret = 0; | |
6228 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
6229 | *val = dm_state->underscan_vborder; | |
6230 | ret = 0; | |
6231 | } else if (property == adev->mode_info.underscan_property) { | |
6232 | *val = dm_state->underscan_enable; | |
6233 | ret = 0; | |
c1ee92f9 DF |
6234 | } else if (property == adev->mode_info.abm_level_property) { |
6235 | *val = dm_state->abm_level; | |
6236 | ret = 0; | |
e7b07cee | 6237 | } |
c1ee92f9 | 6238 | |
e7b07cee HW |
6239 | return ret; |
6240 | } | |
6241 | ||
526c654a ED |
6242 | static void amdgpu_dm_connector_unregister(struct drm_connector *connector) |
6243 | { | |
6244 | struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); | |
6245 | ||
6246 | drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); | |
6247 | } | |
6248 | ||
7578ecda | 6249 | static void amdgpu_dm_connector_destroy(struct drm_connector *connector) |
e7b07cee | 6250 | { |
c84dec2f | 6251 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
1348969a | 6252 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
e7b07cee | 6253 | struct amdgpu_display_manager *dm = &adev->dm; |
ada8ce15 | 6254 | |
5dff80bd | 6255 | /* |
5d945cbc | 6256 | * Call only if mst_mgr was initialized before since it's not done |
5dff80bd AG |
6257 | * for all connector types. |
6258 | */ | |
6259 | if (aconnector->mst_mgr.dev) | |
6260 | drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); | |
6261 | ||
f196198c HG |
6262 | if (aconnector->bl_idx != -1) { |
6263 | backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); | |
6264 | dm->backlight_dev[aconnector->bl_idx] = NULL; | |
e7b07cee | 6265 | } |
dcd5fb82 MF |
6266 | |
6267 | if (aconnector->dc_em_sink) | |
6268 | dc_sink_release(aconnector->dc_em_sink); | |
6269 | aconnector->dc_em_sink = NULL; | |
6270 | if (aconnector->dc_sink) | |
6271 | dc_sink_release(aconnector->dc_sink); | |
6272 | aconnector->dc_sink = NULL; | |
6273 | ||
e86e8947 | 6274 | drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); |
e7b07cee HW |
6275 | drm_connector_unregister(connector); |
6276 | drm_connector_cleanup(connector); | |
526c654a ED |
6277 | if (aconnector->i2c) { |
6278 | i2c_del_adapter(&aconnector->i2c->base); | |
6279 | kfree(aconnector->i2c); | |
6280 | } | |
7daec99f | 6281 | kfree(aconnector->dm_dp_aux.aux.name); |
526c654a | 6282 | |
e7b07cee HW |
6283 | kfree(connector); |
6284 | } | |
6285 | ||
6286 | void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) | |
6287 | { | |
6288 | struct dm_connector_state *state = | |
6289 | to_dm_connector_state(connector->state); | |
6290 | ||
df099b9b LSL |
6291 | if (connector->state) |
6292 | __drm_atomic_helper_connector_destroy_state(connector->state); | |
6293 | ||
e7b07cee HW |
6294 | kfree(state); |
6295 | ||
6296 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
6297 | ||
6298 | if (state) { | |
6299 | state->scaling = RMX_OFF; | |
6300 | state->underscan_enable = false; | |
6301 | state->underscan_hborder = 0; | |
6302 | state->underscan_vborder = 0; | |
01933ba4 | 6303 | state->base.max_requested_bpc = 8; |
3261e013 ML |
6304 | state->vcpi_slots = 0; |
6305 | state->pbn = 0; | |
5d945cbc | 6306 | |
c3e50f89 NK |
6307 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
6308 | state->abm_level = amdgpu_dm_abm_level; | |
6309 | ||
df099b9b | 6310 | __drm_atomic_helper_connector_reset(connector, &state->base); |
e7b07cee HW |
6311 | } |
6312 | } | |
6313 | ||
3ee6b26b AD |
6314 | struct drm_connector_state * |
6315 | amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) | |
e7b07cee HW |
6316 | { |
6317 | struct dm_connector_state *state = | |
6318 | to_dm_connector_state(connector->state); | |
6319 | ||
6320 | struct dm_connector_state *new_state = | |
6321 | kmemdup(state, sizeof(*state), GFP_KERNEL); | |
6322 | ||
98e6436d AK |
6323 | if (!new_state) |
6324 | return NULL; | |
e7b07cee | 6325 | |
98e6436d AK |
6326 | __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); |
6327 | ||
6328 | new_state->freesync_capable = state->freesync_capable; | |
c1ee92f9 | 6329 | new_state->abm_level = state->abm_level; |
922454c2 NK |
6330 | new_state->scaling = state->scaling; |
6331 | new_state->underscan_enable = state->underscan_enable; | |
6332 | new_state->underscan_hborder = state->underscan_hborder; | |
6333 | new_state->underscan_vborder = state->underscan_vborder; | |
3261e013 ML |
6334 | new_state->vcpi_slots = state->vcpi_slots; |
6335 | new_state->pbn = state->pbn; | |
98e6436d | 6336 | return &new_state->base; |
e7b07cee HW |
6337 | } |
6338 | ||
14f04fa4 AD |
6339 | static int |
6340 | amdgpu_dm_connector_late_register(struct drm_connector *connector) | |
6341 | { | |
6342 | struct amdgpu_dm_connector *amdgpu_dm_connector = | |
6343 | to_amdgpu_dm_connector(connector); | |
00a8037e | 6344 | int r; |
14f04fa4 | 6345 | |
62f03dad HG |
6346 | amdgpu_dm_register_backlight_device(amdgpu_dm_connector); |
6347 | ||
00a8037e AD |
6348 | if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
6349 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
6350 | amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; | |
6351 | r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); | |
6352 | if (r) | |
6353 | return r; | |
6354 | } | |
6355 | ||
6356 | #if defined(CONFIG_DEBUG_FS) | |
14f04fa4 AD |
6357 | connector_debugfs_init(amdgpu_dm_connector); |
6358 | #endif | |
6359 | ||
6360 | return 0; | |
6361 | } | |
6362 | ||
dae343b3 | 6363 | static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) |
0ba4a784 AH |
6364 | { |
6365 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
6366 | struct dc_link *dc_link = aconnector->dc_link; | |
6367 | struct dc_sink *dc_em_sink = aconnector->dc_em_sink; | |
6368 | struct edid *edid; | |
6369 | ||
6370 | if (!connector->edid_override) | |
6371 | return; | |
6372 | ||
6373 | drm_edid_override_connector_update(&aconnector->base); | |
6374 | edid = aconnector->base.edid_blob_ptr->data; | |
6375 | aconnector->edid = edid; | |
6376 | ||
6377 | /* Update emulated (virtual) sink's EDID */ | |
6378 | if (dc_em_sink && dc_link) { | |
6379 | memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); | |
6380 | memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); | |
6381 | dm_helpers_parse_edid_caps( | |
6382 | dc_link, | |
6383 | &dc_em_sink->dc_edid, | |
6384 | &dc_em_sink->edid_caps); | |
6385 | } | |
6386 | } | |
6387 | ||
e7b07cee HW |
6388 | static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { |
6389 | .reset = amdgpu_dm_connector_funcs_reset, | |
6390 | .detect = amdgpu_dm_connector_detect, | |
6391 | .fill_modes = drm_helper_probe_single_connector_modes, | |
6392 | .destroy = amdgpu_dm_connector_destroy, | |
6393 | .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, | |
6394 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
6395 | .atomic_set_property = amdgpu_dm_connector_atomic_set_property, | |
526c654a | 6396 | .atomic_get_property = amdgpu_dm_connector_atomic_get_property, |
14f04fa4 | 6397 | .late_register = amdgpu_dm_connector_late_register, |
0ba4a784 AH |
6398 | .early_unregister = amdgpu_dm_connector_unregister, |
6399 | .force = amdgpu_dm_connector_funcs_force | |
e7b07cee HW |
6400 | }; |
6401 | ||
e7b07cee HW |
6402 | static int get_modes(struct drm_connector *connector) |
6403 | { | |
6404 | return amdgpu_dm_connector_get_modes(connector); | |
6405 | } | |
6406 | ||
c84dec2f | 6407 | static void create_eml_sink(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
6408 | { |
6409 | struct dc_sink_init_data init_params = { | |
6410 | .link = aconnector->dc_link, | |
6411 | .sink_signal = SIGNAL_TYPE_VIRTUAL | |
6412 | }; | |
70e8ffc5 | 6413 | struct edid *edid; |
e7b07cee | 6414 | |
a89ff457 | 6415 | if (!aconnector->base.edid_blob_ptr) { |
550e5d23 HW |
6416 | /* if connector->edid_override valid, pass |
6417 | * it to edid_override to edid_blob_ptr | |
6418 | */ | |
e7b07cee | 6419 | |
8789989b | 6420 | drm_edid_override_connector_update(&aconnector->base); |
550e5d23 HW |
6421 | |
6422 | if (!aconnector->base.edid_blob_ptr) { | |
6423 | DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", | |
6424 | aconnector->base.name); | |
6425 | ||
6426 | aconnector->base.force = DRM_FORCE_OFF; | |
6427 | return; | |
6428 | } | |
e7b07cee HW |
6429 | } |
6430 | ||
70e8ffc5 HW |
6431 | edid = (struct edid *) aconnector->base.edid_blob_ptr->data; |
6432 | ||
e7b07cee HW |
6433 | aconnector->edid = edid; |
6434 | ||
6435 | aconnector->dc_em_sink = dc_link_add_remote_sink( | |
6436 | aconnector->dc_link, | |
6437 | (uint8_t *)edid, | |
6438 | (edid->extensions + 1) * EDID_LENGTH, | |
6439 | &init_params); | |
6440 | ||
dcd5fb82 | 6441 | if (aconnector->base.force == DRM_FORCE_ON) { |
e7b07cee HW |
6442 | aconnector->dc_sink = aconnector->dc_link->local_sink ? |
6443 | aconnector->dc_link->local_sink : | |
6444 | aconnector->dc_em_sink; | |
dcd5fb82 MF |
6445 | dc_sink_retain(aconnector->dc_sink); |
6446 | } | |
e7b07cee HW |
6447 | } |
6448 | ||
c84dec2f | 6449 | static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
6450 | { |
6451 | struct dc_link *link = (struct dc_link *)aconnector->dc_link; | |
6452 | ||
1f6010a9 DF |
6453 | /* |
6454 | * In case of headless boot with force on for DP managed connector | |
e7b07cee HW |
6455 | * Those settings have to be != 0 to get initial modeset |
6456 | */ | |
6457 | if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { | |
6458 | link->verified_link_cap.lane_count = LANE_COUNT_FOUR; | |
6459 | link->verified_link_cap.link_rate = LINK_RATE_HIGH2; | |
6460 | } | |
6461 | ||
e7b07cee HW |
6462 | create_eml_sink(aconnector); |
6463 | } | |
6464 | ||
5468c36d FZ |
6465 | static enum dc_status dm_validate_stream_and_context(struct dc *dc, |
6466 | struct dc_stream_state *stream) | |
6467 | { | |
6468 | enum dc_status dc_result = DC_ERROR_UNEXPECTED; | |
6469 | struct dc_plane_state *dc_plane_state = NULL; | |
6470 | struct dc_state *dc_state = NULL; | |
6471 | ||
6472 | if (!stream) | |
6473 | goto cleanup; | |
6474 | ||
6475 | dc_plane_state = dc_create_plane_state(dc); | |
6476 | if (!dc_plane_state) | |
6477 | goto cleanup; | |
6478 | ||
6479 | dc_state = dc_create_state(dc); | |
6480 | if (!dc_state) | |
6481 | goto cleanup; | |
6482 | ||
6483 | /* populate stream to plane */ | |
6484 | dc_plane_state->src_rect.height = stream->src.height; | |
6485 | dc_plane_state->src_rect.width = stream->src.width; | |
6486 | dc_plane_state->dst_rect.height = stream->src.height; | |
6487 | dc_plane_state->dst_rect.width = stream->src.width; | |
6488 | dc_plane_state->clip_rect.height = stream->src.height; | |
6489 | dc_plane_state->clip_rect.width = stream->src.width; | |
6490 | dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; | |
6491 | dc_plane_state->plane_size.surface_size.height = stream->src.height; | |
6492 | dc_plane_state->plane_size.surface_size.width = stream->src.width; | |
6493 | dc_plane_state->plane_size.chroma_size.height = stream->src.height; | |
6494 | dc_plane_state->plane_size.chroma_size.width = stream->src.width; | |
5468c36d FZ |
6495 | dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; |
6496 | dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; | |
6497 | dc_plane_state->rotation = ROTATION_ANGLE_0; | |
6498 | dc_plane_state->is_tiling_rotated = false; | |
6499 | dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; | |
6500 | ||
6501 | dc_result = dc_validate_stream(dc, stream); | |
6502 | if (dc_result == DC_OK) | |
6503 | dc_result = dc_validate_plane(dc, dc_plane_state); | |
6504 | ||
6505 | if (dc_result == DC_OK) | |
6506 | dc_result = dc_add_stream_to_ctx(dc, dc_state, stream); | |
6507 | ||
6508 | if (dc_result == DC_OK && !dc_add_plane_to_context( | |
6509 | dc, | |
6510 | stream, | |
6511 | dc_plane_state, | |
6512 | dc_state)) | |
6513 | dc_result = DC_FAIL_ATTACH_SURFACES; | |
6514 | ||
6515 | if (dc_result == DC_OK) | |
6516 | dc_result = dc_validate_global_state(dc, dc_state, true); | |
6517 | ||
6518 | cleanup: | |
6519 | if (dc_state) | |
6520 | dc_release_state(dc_state); | |
6521 | ||
6522 | if (dc_plane_state) | |
6523 | dc_plane_state_release(dc_plane_state); | |
6524 | ||
6525 | return dc_result; | |
6526 | } | |
6527 | ||
17ce8a69 | 6528 | struct dc_stream_state * |
cbd14ae7 SW |
6529 | create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, |
6530 | const struct drm_display_mode *drm_mode, | |
6531 | const struct dm_connector_state *dm_state, | |
6532 | const struct dc_stream_state *old_stream) | |
6533 | { | |
6534 | struct drm_connector *connector = &aconnector->base; | |
1348969a | 6535 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
cbd14ae7 | 6536 | struct dc_stream_state *stream; |
4b7da34b SW |
6537 | const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; |
6538 | int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; | |
cbd14ae7 SW |
6539 | enum dc_status dc_result = DC_OK; |
6540 | ||
6541 | do { | |
6542 | stream = create_stream_for_sink(aconnector, drm_mode, | |
6543 | dm_state, old_stream, | |
6544 | requested_bpc); | |
6545 | if (stream == NULL) { | |
6546 | DRM_ERROR("Failed to create stream for sink!\n"); | |
6547 | break; | |
6548 | } | |
6549 | ||
e9a7d236 RS |
6550 | dc_result = dc_validate_stream(adev->dm.dc, stream); |
6551 | if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) | |
f04d275d | 6552 | dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); |
6553 | ||
5468c36d FZ |
6554 | if (dc_result == DC_OK) |
6555 | dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); | |
6556 | ||
cbd14ae7 | 6557 | if (dc_result != DC_OK) { |
74a16675 | 6558 | DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", |
cbd14ae7 SW |
6559 | drm_mode->hdisplay, |
6560 | drm_mode->vdisplay, | |
6561 | drm_mode->clock, | |
74a16675 RS |
6562 | dc_result, |
6563 | dc_status_to_str(dc_result)); | |
cbd14ae7 SW |
6564 | |
6565 | dc_stream_release(stream); | |
6566 | stream = NULL; | |
6567 | requested_bpc -= 2; /* lower bpc to retry validation */ | |
6568 | } | |
6569 | ||
6570 | } while (stream == NULL && requested_bpc >= 6); | |
6571 | ||
68eb3ae3 WS |
6572 | if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { |
6573 | DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); | |
6574 | ||
6575 | aconnector->force_yuv420_output = true; | |
6576 | stream = create_validate_stream_for_sink(aconnector, drm_mode, | |
6577 | dm_state, old_stream); | |
6578 | aconnector->force_yuv420_output = false; | |
6579 | } | |
6580 | ||
cbd14ae7 SW |
6581 | return stream; |
6582 | } | |
6583 | ||
ba9ca088 | 6584 | enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, |
3ee6b26b | 6585 | struct drm_display_mode *mode) |
e7b07cee HW |
6586 | { |
6587 | int result = MODE_ERROR; | |
6588 | struct dc_sink *dc_sink; | |
e7b07cee | 6589 | /* TODO: Unhardcode stream count */ |
0971c40e | 6590 | struct dc_stream_state *stream; |
c84dec2f | 6591 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
6592 | |
6593 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || | |
6594 | (mode->flags & DRM_MODE_FLAG_DBLSCAN)) | |
6595 | return result; | |
6596 | ||
1f6010a9 DF |
6597 | /* |
6598 | * Only run this the first time mode_valid is called to initilialize | |
e7b07cee HW |
6599 | * EDID mgmt |
6600 | */ | |
6601 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && | |
6602 | !aconnector->dc_em_sink) | |
6603 | handle_edid_mgmt(aconnector); | |
6604 | ||
c84dec2f | 6605 | dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; |
e7b07cee | 6606 | |
ad975f44 VL |
6607 | if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && |
6608 | aconnector->base.force != DRM_FORCE_ON) { | |
e7b07cee HW |
6609 | DRM_ERROR("dc_sink is NULL!\n"); |
6610 | goto fail; | |
6611 | } | |
6612 | ||
cb841d27 HW |
6613 | stream = create_validate_stream_for_sink(aconnector, mode, |
6614 | to_dm_connector_state(connector->state), | |
6615 | NULL); | |
cbd14ae7 SW |
6616 | if (stream) { |
6617 | dc_stream_release(stream); | |
e7b07cee | 6618 | result = MODE_OK; |
cbd14ae7 | 6619 | } |
e7b07cee HW |
6620 | |
6621 | fail: | |
6622 | /* TODO: error handling*/ | |
6623 | return result; | |
6624 | } | |
6625 | ||
88694af9 NK |
6626 | static int fill_hdr_info_packet(const struct drm_connector_state *state, |
6627 | struct dc_info_packet *out) | |
6628 | { | |
6629 | struct hdmi_drm_infoframe frame; | |
6630 | unsigned char buf[30]; /* 26 + 4 */ | |
6631 | ssize_t len; | |
6632 | int ret, i; | |
6633 | ||
6634 | memset(out, 0, sizeof(*out)); | |
6635 | ||
6636 | if (!state->hdr_output_metadata) | |
6637 | return 0; | |
6638 | ||
6639 | ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); | |
6640 | if (ret) | |
6641 | return ret; | |
6642 | ||
6643 | len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); | |
6644 | if (len < 0) | |
6645 | return (int)len; | |
6646 | ||
6647 | /* Static metadata is a fixed 26 bytes + 4 byte header. */ | |
6648 | if (len != 30) | |
6649 | return -EINVAL; | |
6650 | ||
6651 | /* Prepare the infopacket for DC. */ | |
6652 | switch (state->connector->connector_type) { | |
6653 | case DRM_MODE_CONNECTOR_HDMIA: | |
6654 | out->hb0 = 0x87; /* type */ | |
6655 | out->hb1 = 0x01; /* version */ | |
6656 | out->hb2 = 0x1A; /* length */ | |
6657 | out->sb[0] = buf[3]; /* checksum */ | |
6658 | i = 1; | |
6659 | break; | |
6660 | ||
6661 | case DRM_MODE_CONNECTOR_DisplayPort: | |
6662 | case DRM_MODE_CONNECTOR_eDP: | |
6663 | out->hb0 = 0x00; /* sdp id, zero */ | |
6664 | out->hb1 = 0x87; /* type */ | |
6665 | out->hb2 = 0x1D; /* payload len - 1 */ | |
6666 | out->hb3 = (0x13 << 2); /* sdp version */ | |
6667 | out->sb[0] = 0x01; /* version */ | |
6668 | out->sb[1] = 0x1A; /* length */ | |
6669 | i = 2; | |
6670 | break; | |
6671 | ||
6672 | default: | |
6673 | return -EINVAL; | |
6674 | } | |
6675 | ||
6676 | memcpy(&out->sb[i], &buf[4], 26); | |
6677 | out->valid = true; | |
6678 | ||
6679 | print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, | |
6680 | sizeof(out->sb), false); | |
6681 | ||
6682 | return 0; | |
6683 | } | |
6684 | ||
88694af9 NK |
6685 | static int |
6686 | amdgpu_dm_connector_atomic_check(struct drm_connector *conn, | |
51e857af | 6687 | struct drm_atomic_state *state) |
88694af9 | 6688 | { |
51e857af SP |
6689 | struct drm_connector_state *new_con_state = |
6690 | drm_atomic_get_new_connector_state(state, conn); | |
88694af9 NK |
6691 | struct drm_connector_state *old_con_state = |
6692 | drm_atomic_get_old_connector_state(state, conn); | |
6693 | struct drm_crtc *crtc = new_con_state->crtc; | |
6694 | struct drm_crtc_state *new_crtc_state; | |
a76eb429 | 6695 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); |
88694af9 NK |
6696 | int ret; |
6697 | ||
e8a98235 RS |
6698 | trace_amdgpu_dm_connector_atomic_check(new_con_state); |
6699 | ||
a76eb429 LP |
6700 | if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { |
6701 | ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); | |
6702 | if (ret < 0) | |
6703 | return ret; | |
6704 | } | |
6705 | ||
88694af9 NK |
6706 | if (!crtc) |
6707 | return 0; | |
6708 | ||
a0b433c8 HW |
6709 | if (new_con_state->colorspace != old_con_state->colorspace) { |
6710 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
6711 | if (IS_ERR(new_crtc_state)) | |
6712 | return PTR_ERR(new_crtc_state); | |
6713 | ||
6714 | new_crtc_state->mode_changed = true; | |
6715 | } | |
6716 | ||
72921cdf | 6717 | if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { |
88694af9 NK |
6718 | struct dc_info_packet hdr_infopacket; |
6719 | ||
6720 | ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); | |
6721 | if (ret) | |
6722 | return ret; | |
6723 | ||
6724 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
6725 | if (IS_ERR(new_crtc_state)) | |
6726 | return PTR_ERR(new_crtc_state); | |
6727 | ||
6728 | /* | |
6729 | * DC considers the stream backends changed if the | |
6730 | * static metadata changes. Forcing the modeset also | |
6731 | * gives a simple way for userspace to switch from | |
b232d4ed NK |
6732 | * 8bpc to 10bpc when setting the metadata to enter |
6733 | * or exit HDR. | |
6734 | * | |
6735 | * Changing the static metadata after it's been | |
6736 | * set is permissible, however. So only force a | |
6737 | * modeset if we're entering or exiting HDR. | |
88694af9 | 6738 | */ |
a0b433c8 | 6739 | new_crtc_state->mode_changed = new_crtc_state->mode_changed || |
b232d4ed NK |
6740 | !old_con_state->hdr_output_metadata || |
6741 | !new_con_state->hdr_output_metadata; | |
88694af9 NK |
6742 | } |
6743 | ||
6744 | return 0; | |
6745 | } | |
6746 | ||
e7b07cee HW |
6747 | static const struct drm_connector_helper_funcs |
6748 | amdgpu_dm_connector_helper_funcs = { | |
6749 | /* | |
1f6010a9 | 6750 | * If hotplugging a second bigger display in FB Con mode, bigger resolution |
b830ebc9 | 6751 | * modes will be filtered by drm_mode_validate_size(), and those modes |
1f6010a9 | 6752 | * are missing after user start lightdm. So we need to renew modes list. |
b830ebc9 HW |
6753 | * in get_modes call back, not just return the modes count |
6754 | */ | |
e7b07cee HW |
6755 | .get_modes = get_modes, |
6756 | .mode_valid = amdgpu_dm_connector_mode_valid, | |
88694af9 | 6757 | .atomic_check = amdgpu_dm_connector_atomic_check, |
e7b07cee HW |
6758 | }; |
6759 | ||
e7b07cee HW |
6760 | static void dm_encoder_helper_disable(struct drm_encoder *encoder) |
6761 | { | |
6762 | ||
6763 | } | |
6764 | ||
f04d275d | 6765 | int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) |
3261e013 ML |
6766 | { |
6767 | switch (display_color_depth) { | |
5d945cbc RS |
6768 | case COLOR_DEPTH_666: |
6769 | return 6; | |
6770 | case COLOR_DEPTH_888: | |
6771 | return 8; | |
6772 | case COLOR_DEPTH_101010: | |
6773 | return 10; | |
6774 | case COLOR_DEPTH_121212: | |
6775 | return 12; | |
6776 | case COLOR_DEPTH_141414: | |
6777 | return 14; | |
6778 | case COLOR_DEPTH_161616: | |
6779 | return 16; | |
6780 | default: | |
6781 | break; | |
6782 | } | |
3261e013 ML |
6783 | return 0; |
6784 | } | |
6785 | ||
3ee6b26b AD |
6786 | static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, |
6787 | struct drm_crtc_state *crtc_state, | |
6788 | struct drm_connector_state *conn_state) | |
e7b07cee | 6789 | { |
3261e013 ML |
6790 | struct drm_atomic_state *state = crtc_state->state; |
6791 | struct drm_connector *connector = conn_state->connector; | |
6792 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
6793 | struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); | |
6794 | const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; | |
6795 | struct drm_dp_mst_topology_mgr *mst_mgr; | |
6796 | struct drm_dp_mst_port *mst_port; | |
4d07b0bc | 6797 | struct drm_dp_mst_topology_state *mst_state; |
3261e013 ML |
6798 | enum dc_color_depth color_depth; |
6799 | int clock, bpp = 0; | |
1bc22f20 | 6800 | bool is_y420 = false; |
3261e013 | 6801 | |
91b38ca1 | 6802 | if (!aconnector->mst_output_port) |
3261e013 ML |
6803 | return 0; |
6804 | ||
f0127cb1 WL |
6805 | mst_port = aconnector->mst_output_port; |
6806 | mst_mgr = &aconnector->mst_root->mst_mgr; | |
3261e013 ML |
6807 | |
6808 | if (!crtc_state->connectors_changed && !crtc_state->mode_changed) | |
6809 | return 0; | |
6810 | ||
4d07b0bc LP |
6811 | mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); |
6812 | if (IS_ERR(mst_state)) | |
6813 | return PTR_ERR(mst_state); | |
6814 | ||
6815 | if (!mst_state->pbn_div) | |
f0127cb1 | 6816 | mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); |
4d07b0bc | 6817 | |
3261e013 | 6818 | if (!state->duplicated) { |
cbd14ae7 | 6819 | int max_bpc = conn_state->max_requested_bpc; |
c82eddf8 | 6820 | |
1bc22f20 | 6821 | is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && |
5d945cbc | 6822 | aconnector->force_yuv420_output; |
cbd14ae7 SW |
6823 | color_depth = convert_color_depth_from_display_info(connector, |
6824 | is_y420, | |
6825 | max_bpc); | |
3261e013 ML |
6826 | bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; |
6827 | clock = adjusted_mode->clock; | |
dc48529f | 6828 | dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); |
3261e013 | 6829 | } |
4d07b0bc LP |
6830 | |
6831 | dm_new_connector_state->vcpi_slots = | |
6832 | drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, | |
6833 | dm_new_connector_state->pbn); | |
3261e013 ML |
6834 | if (dm_new_connector_state->vcpi_slots < 0) { |
6835 | DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); | |
6836 | return dm_new_connector_state->vcpi_slots; | |
6837 | } | |
e7b07cee HW |
6838 | return 0; |
6839 | } | |
6840 | ||
6841 | const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { | |
6842 | .disable = dm_encoder_helper_disable, | |
6843 | .atomic_check = dm_encoder_helper_atomic_check | |
6844 | }; | |
6845 | ||
29b9ba74 | 6846 | static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, |
6513104b HW |
6847 | struct dc_state *dc_state, |
6848 | struct dsc_mst_fairness_vars *vars) | |
29b9ba74 ML |
6849 | { |
6850 | struct dc_stream_state *stream = NULL; | |
6851 | struct drm_connector *connector; | |
5760dcb9 | 6852 | struct drm_connector_state *new_con_state; |
29b9ba74 ML |
6853 | struct amdgpu_dm_connector *aconnector; |
6854 | struct dm_connector_state *dm_conn_state; | |
7cce4cd6 | 6855 | int i, j, ret; |
a550bb16 | 6856 | int vcpi, pbn_div, pbn, slot_num = 0; |
29b9ba74 | 6857 | |
5760dcb9 | 6858 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
29b9ba74 ML |
6859 | |
6860 | aconnector = to_amdgpu_dm_connector(connector); | |
6861 | ||
f0127cb1 | 6862 | if (!aconnector->mst_output_port) |
29b9ba74 ML |
6863 | continue; |
6864 | ||
6865 | if (!new_con_state || !new_con_state->crtc) | |
6866 | continue; | |
6867 | ||
6868 | dm_conn_state = to_dm_connector_state(new_con_state); | |
6869 | ||
6870 | for (j = 0; j < dc_state->stream_count; j++) { | |
6871 | stream = dc_state->streams[j]; | |
6872 | if (!stream) | |
6873 | continue; | |
6874 | ||
5d945cbc | 6875 | if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) |
29b9ba74 ML |
6876 | break; |
6877 | ||
6878 | stream = NULL; | |
6879 | } | |
6880 | ||
6881 | if (!stream) | |
6882 | continue; | |
6883 | ||
29b9ba74 | 6884 | pbn_div = dm_mst_get_pbn_divider(stream->link); |
6513104b HW |
6885 | /* pbn is calculated by compute_mst_dsc_configs_for_state*/ |
6886 | for (j = 0; j < dc_state->stream_count; j++) { | |
6887 | if (vars[j].aconnector == aconnector) { | |
6888 | pbn = vars[j].pbn; | |
6889 | break; | |
6890 | } | |
6891 | } | |
6892 | ||
a550bb16 HW |
6893 | if (j == dc_state->stream_count) |
6894 | continue; | |
6895 | ||
6896 | slot_num = DIV_ROUND_UP(pbn, pbn_div); | |
6897 | ||
6898 | if (stream->timing.flags.DSC != 1) { | |
6899 | dm_conn_state->pbn = pbn; | |
6900 | dm_conn_state->vcpi_slots = slot_num; | |
6901 | ||
f0127cb1 | 6902 | ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, |
7cce4cd6 LP |
6903 | dm_conn_state->pbn, false); |
6904 | if (ret < 0) | |
6905 | return ret; | |
6906 | ||
a550bb16 HW |
6907 | continue; |
6908 | } | |
6909 | ||
f0127cb1 | 6910 | vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); |
29b9ba74 ML |
6911 | if (vcpi < 0) |
6912 | return vcpi; | |
6913 | ||
6914 | dm_conn_state->pbn = pbn; | |
6915 | dm_conn_state->vcpi_slots = vcpi; | |
6916 | } | |
6917 | return 0; | |
6918 | } | |
6919 | ||
e7b07cee HW |
6920 | static int to_drm_connector_type(enum signal_type st) |
6921 | { | |
6922 | switch (st) { | |
6923 | case SIGNAL_TYPE_HDMI_TYPE_A: | |
6924 | return DRM_MODE_CONNECTOR_HDMIA; | |
6925 | case SIGNAL_TYPE_EDP: | |
6926 | return DRM_MODE_CONNECTOR_eDP; | |
11c3ee48 AD |
6927 | case SIGNAL_TYPE_LVDS: |
6928 | return DRM_MODE_CONNECTOR_LVDS; | |
e7b07cee HW |
6929 | case SIGNAL_TYPE_RGB: |
6930 | return DRM_MODE_CONNECTOR_VGA; | |
6931 | case SIGNAL_TYPE_DISPLAY_PORT: | |
6932 | case SIGNAL_TYPE_DISPLAY_PORT_MST: | |
6933 | return DRM_MODE_CONNECTOR_DisplayPort; | |
6934 | case SIGNAL_TYPE_DVI_DUAL_LINK: | |
6935 | case SIGNAL_TYPE_DVI_SINGLE_LINK: | |
6936 | return DRM_MODE_CONNECTOR_DVID; | |
6937 | case SIGNAL_TYPE_VIRTUAL: | |
6938 | return DRM_MODE_CONNECTOR_VIRTUAL; | |
6939 | ||
6940 | default: | |
6941 | return DRM_MODE_CONNECTOR_Unknown; | |
6942 | } | |
6943 | } | |
6944 | ||
2b4c1c05 DV |
6945 | static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) |
6946 | { | |
62afb4ad JRS |
6947 | struct drm_encoder *encoder; |
6948 | ||
6949 | /* There is only one encoder per connector */ | |
6950 | drm_connector_for_each_possible_encoder(connector, encoder) | |
6951 | return encoder; | |
6952 | ||
6953 | return NULL; | |
2b4c1c05 DV |
6954 | } |
6955 | ||
e7b07cee HW |
6956 | static void amdgpu_dm_get_native_mode(struct drm_connector *connector) |
6957 | { | |
e7b07cee HW |
6958 | struct drm_encoder *encoder; |
6959 | struct amdgpu_encoder *amdgpu_encoder; | |
6960 | ||
2b4c1c05 | 6961 | encoder = amdgpu_dm_connector_to_encoder(connector); |
e7b07cee HW |
6962 | |
6963 | if (encoder == NULL) | |
6964 | return; | |
6965 | ||
6966 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
6967 | ||
6968 | amdgpu_encoder->native_mode.clock = 0; | |
6969 | ||
6970 | if (!list_empty(&connector->probed_modes)) { | |
6971 | struct drm_display_mode *preferred_mode = NULL; | |
b830ebc9 | 6972 | |
e7b07cee | 6973 | list_for_each_entry(preferred_mode, |
b830ebc9 HW |
6974 | &connector->probed_modes, |
6975 | head) { | |
6976 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) | |
6977 | amdgpu_encoder->native_mode = *preferred_mode; | |
6978 | ||
e7b07cee HW |
6979 | break; |
6980 | } | |
6981 | ||
6982 | } | |
6983 | } | |
6984 | ||
3ee6b26b AD |
6985 | static struct drm_display_mode * |
6986 | amdgpu_dm_create_common_mode(struct drm_encoder *encoder, | |
6987 | char *name, | |
6988 | int hdisplay, int vdisplay) | |
e7b07cee HW |
6989 | { |
6990 | struct drm_device *dev = encoder->dev; | |
6991 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
6992 | struct drm_display_mode *mode = NULL; | |
6993 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
6994 | ||
6995 | mode = drm_mode_duplicate(dev, native_mode); | |
6996 | ||
b830ebc9 | 6997 | if (mode == NULL) |
e7b07cee HW |
6998 | return NULL; |
6999 | ||
7000 | mode->hdisplay = hdisplay; | |
7001 | mode->vdisplay = vdisplay; | |
7002 | mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
090afc1e | 7003 | strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); |
e7b07cee HW |
7004 | |
7005 | return mode; | |
7006 | ||
7007 | } | |
7008 | ||
7009 | static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, | |
3ee6b26b | 7010 | struct drm_connector *connector) |
e7b07cee HW |
7011 | { |
7012 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
7013 | struct drm_display_mode *mode = NULL; | |
7014 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
c84dec2f HW |
7015 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7016 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
7017 | int i; |
7018 | int n; | |
7019 | struct mode_size { | |
7020 | char name[DRM_DISPLAY_MODE_LEN]; | |
7021 | int w; | |
7022 | int h; | |
b830ebc9 | 7023 | } common_modes[] = { |
e7b07cee HW |
7024 | { "640x480", 640, 480}, |
7025 | { "800x600", 800, 600}, | |
7026 | { "1024x768", 1024, 768}, | |
7027 | { "1280x720", 1280, 720}, | |
7028 | { "1280x800", 1280, 800}, | |
7029 | {"1280x1024", 1280, 1024}, | |
7030 | { "1440x900", 1440, 900}, | |
7031 | {"1680x1050", 1680, 1050}, | |
7032 | {"1600x1200", 1600, 1200}, | |
7033 | {"1920x1080", 1920, 1080}, | |
7034 | {"1920x1200", 1920, 1200} | |
7035 | }; | |
7036 | ||
b830ebc9 | 7037 | n = ARRAY_SIZE(common_modes); |
e7b07cee HW |
7038 | |
7039 | for (i = 0; i < n; i++) { | |
7040 | struct drm_display_mode *curmode = NULL; | |
7041 | bool mode_existed = false; | |
7042 | ||
7043 | if (common_modes[i].w > native_mode->hdisplay || | |
b830ebc9 HW |
7044 | common_modes[i].h > native_mode->vdisplay || |
7045 | (common_modes[i].w == native_mode->hdisplay && | |
7046 | common_modes[i].h == native_mode->vdisplay)) | |
7047 | continue; | |
e7b07cee HW |
7048 | |
7049 | list_for_each_entry(curmode, &connector->probed_modes, head) { | |
7050 | if (common_modes[i].w == curmode->hdisplay && | |
b830ebc9 | 7051 | common_modes[i].h == curmode->vdisplay) { |
e7b07cee HW |
7052 | mode_existed = true; |
7053 | break; | |
7054 | } | |
7055 | } | |
7056 | ||
7057 | if (mode_existed) | |
7058 | continue; | |
7059 | ||
7060 | mode = amdgpu_dm_create_common_mode(encoder, | |
7061 | common_modes[i].name, common_modes[i].w, | |
7062 | common_modes[i].h); | |
588a7017 ZQ |
7063 | if (!mode) |
7064 | continue; | |
7065 | ||
e7b07cee | 7066 | drm_mode_probed_add(connector, mode); |
c84dec2f | 7067 | amdgpu_dm_connector->num_modes++; |
e7b07cee HW |
7068 | } |
7069 | } | |
7070 | ||
d77de788 SS |
7071 | static void amdgpu_set_panel_orientation(struct drm_connector *connector) |
7072 | { | |
7073 | struct drm_encoder *encoder; | |
7074 | struct amdgpu_encoder *amdgpu_encoder; | |
7075 | const struct drm_display_mode *native_mode; | |
7076 | ||
7077 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && | |
7078 | connector->connector_type != DRM_MODE_CONNECTOR_LVDS) | |
7079 | return; | |
7080 | ||
acc96ae0 MW |
7081 | mutex_lock(&connector->dev->mode_config.mutex); |
7082 | amdgpu_dm_connector_get_modes(connector); | |
7083 | mutex_unlock(&connector->dev->mode_config.mutex); | |
7084 | ||
d77de788 SS |
7085 | encoder = amdgpu_dm_connector_to_encoder(connector); |
7086 | if (!encoder) | |
7087 | return; | |
7088 | ||
7089 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
7090 | ||
7091 | native_mode = &amdgpu_encoder->native_mode; | |
7092 | if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) | |
7093 | return; | |
7094 | ||
7095 | drm_connector_set_panel_orientation_with_quirk(connector, | |
7096 | DRM_MODE_PANEL_ORIENTATION_UNKNOWN, | |
7097 | native_mode->hdisplay, | |
7098 | native_mode->vdisplay); | |
7099 | } | |
7100 | ||
3ee6b26b AD |
7101 | static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, |
7102 | struct edid *edid) | |
e7b07cee | 7103 | { |
c84dec2f HW |
7104 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7105 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
7106 | |
7107 | if (edid) { | |
7108 | /* empty probed_modes */ | |
7109 | INIT_LIST_HEAD(&connector->probed_modes); | |
c84dec2f | 7110 | amdgpu_dm_connector->num_modes = |
e7b07cee HW |
7111 | drm_add_edid_modes(connector, edid); |
7112 | ||
f1e5e913 YMM |
7113 | /* sorting the probed modes before calling function |
7114 | * amdgpu_dm_get_native_mode() since EDID can have | |
7115 | * more than one preferred mode. The modes that are | |
7116 | * later in the probed mode list could be of higher | |
7117 | * and preferred resolution. For example, 3840x2160 | |
7118 | * resolution in base EDID preferred timing and 4096x2160 | |
7119 | * preferred resolution in DID extension block later. | |
7120 | */ | |
7121 | drm_mode_sort(&connector->probed_modes); | |
e7b07cee | 7122 | amdgpu_dm_get_native_mode(connector); |
f9b4f20c SW |
7123 | |
7124 | /* Freesync capabilities are reset by calling | |
7125 | * drm_add_edid_modes() and need to be | |
7126 | * restored here. | |
7127 | */ | |
7128 | amdgpu_dm_update_freesync_caps(connector, edid); | |
a8d8d3dc | 7129 | } else { |
c84dec2f | 7130 | amdgpu_dm_connector->num_modes = 0; |
a8d8d3dc | 7131 | } |
e7b07cee HW |
7132 | } |
7133 | ||
a85ba005 NC |
7134 | static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, |
7135 | struct drm_display_mode *mode) | |
7136 | { | |
7137 | struct drm_display_mode *m; | |
7138 | ||
c82eddf8 | 7139 | list_for_each_entry(m, &aconnector->base.probed_modes, head) { |
a85ba005 NC |
7140 | if (drm_mode_equal(m, mode)) |
7141 | return true; | |
7142 | } | |
7143 | ||
7144 | return false; | |
7145 | } | |
7146 | ||
7147 | static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) | |
7148 | { | |
7149 | const struct drm_display_mode *m; | |
7150 | struct drm_display_mode *new_mode; | |
7151 | uint i; | |
ae67558b | 7152 | u32 new_modes_count = 0; |
a85ba005 NC |
7153 | |
7154 | /* Standard FPS values | |
7155 | * | |
12cdff6b | 7156 | * 23.976 - TV/NTSC |
3335a135 UKK |
7157 | * 24 - Cinema |
7158 | * 25 - TV/PAL | |
12cdff6b | 7159 | * 29.97 - TV/NTSC |
3335a135 UKK |
7160 | * 30 - TV/NTSC |
7161 | * 48 - Cinema HFR | |
7162 | * 50 - TV/PAL | |
7163 | * 60 - Commonly used | |
12cdff6b | 7164 | * 48,72,96,120 - Multiples of 24 |
a85ba005 | 7165 | */ |
ae67558b | 7166 | static const u32 common_rates[] = { |
9ce5ed6e | 7167 | 23976, 24000, 25000, 29970, 30000, |
12cdff6b | 7168 | 48000, 50000, 60000, 72000, 96000, 120000 |
9ce5ed6e | 7169 | }; |
a85ba005 NC |
7170 | |
7171 | /* | |
7172 | * Find mode with highest refresh rate with the same resolution | |
7173 | * as the preferred mode. Some monitors report a preferred mode | |
7174 | * with lower resolution than the highest refresh rate supported. | |
7175 | */ | |
7176 | ||
7177 | m = get_highest_refresh_rate_mode(aconnector, true); | |
7178 | if (!m) | |
7179 | return 0; | |
7180 | ||
7181 | for (i = 0; i < ARRAY_SIZE(common_rates); i++) { | |
ae67558b SS |
7182 | u64 target_vtotal, target_vtotal_diff; |
7183 | u64 num, den; | |
a85ba005 NC |
7184 | |
7185 | if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) | |
7186 | continue; | |
7187 | ||
7188 | if (common_rates[i] < aconnector->min_vfreq * 1000 || | |
7189 | common_rates[i] > aconnector->max_vfreq * 1000) | |
7190 | continue; | |
7191 | ||
7192 | num = (unsigned long long)m->clock * 1000 * 1000; | |
7193 | den = common_rates[i] * (unsigned long long)m->htotal; | |
7194 | target_vtotal = div_u64(num, den); | |
7195 | target_vtotal_diff = target_vtotal - m->vtotal; | |
7196 | ||
7197 | /* Check for illegal modes */ | |
7198 | if (m->vsync_start + target_vtotal_diff < m->vdisplay || | |
7199 | m->vsync_end + target_vtotal_diff < m->vsync_start || | |
7200 | m->vtotal + target_vtotal_diff < m->vsync_end) | |
7201 | continue; | |
7202 | ||
7203 | new_mode = drm_mode_duplicate(aconnector->base.dev, m); | |
7204 | if (!new_mode) | |
7205 | goto out; | |
7206 | ||
7207 | new_mode->vtotal += (u16)target_vtotal_diff; | |
7208 | new_mode->vsync_start += (u16)target_vtotal_diff; | |
7209 | new_mode->vsync_end += (u16)target_vtotal_diff; | |
7210 | new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
7211 | new_mode->type |= DRM_MODE_TYPE_DRIVER; | |
7212 | ||
7213 | if (!is_duplicate_mode(aconnector, new_mode)) { | |
7214 | drm_mode_probed_add(&aconnector->base, new_mode); | |
7215 | new_modes_count += 1; | |
7216 | } else | |
7217 | drm_mode_destroy(aconnector->base.dev, new_mode); | |
7218 | } | |
7219 | out: | |
7220 | return new_modes_count; | |
7221 | } | |
7222 | ||
7223 | static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, | |
7224 | struct edid *edid) | |
7225 | { | |
7226 | struct amdgpu_dm_connector *amdgpu_dm_connector = | |
7227 | to_amdgpu_dm_connector(connector); | |
7228 | ||
11b92df8 | 7229 | if (!edid) |
a85ba005 | 7230 | return; |
fe8858bb | 7231 | |
a85ba005 NC |
7232 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) |
7233 | amdgpu_dm_connector->num_modes += | |
7234 | add_fs_modes(amdgpu_dm_connector); | |
7235 | } | |
7236 | ||
7578ecda | 7237 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) |
e7b07cee | 7238 | { |
c84dec2f HW |
7239 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7240 | to_amdgpu_dm_connector(connector); | |
e7b07cee | 7241 | struct drm_encoder *encoder; |
c84dec2f | 7242 | struct edid *edid = amdgpu_dm_connector->edid; |
c32699ca JD |
7243 | struct dc_link_settings *verified_link_cap = |
7244 | &amdgpu_dm_connector->dc_link->verified_link_cap; | |
98ce7d32 | 7245 | const struct dc *dc = amdgpu_dm_connector->dc_link->dc; |
e7b07cee | 7246 | |
2b4c1c05 | 7247 | encoder = amdgpu_dm_connector_to_encoder(connector); |
3e332d3a | 7248 | |
5c0e6840 | 7249 | if (!drm_edid_is_valid(edid)) { |
1b369d3c ML |
7250 | amdgpu_dm_connector->num_modes = |
7251 | drm_add_modes_noedid(connector, 640, 480); | |
98ce7d32 | 7252 | if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) |
c32699ca JD |
7253 | amdgpu_dm_connector->num_modes += |
7254 | drm_add_modes_noedid(connector, 1920, 1080); | |
85ee15d6 ML |
7255 | } else { |
7256 | amdgpu_dm_connector_ddc_get_modes(connector, edid); | |
d6149086 | 7257 | amdgpu_dm_connector_add_common_modes(encoder, connector); |
a85ba005 | 7258 | amdgpu_dm_connector_add_freesync_modes(connector, edid); |
85ee15d6 | 7259 | } |
3e332d3a | 7260 | amdgpu_dm_fbc_init(connector); |
5099114b | 7261 | |
c84dec2f | 7262 | return amdgpu_dm_connector->num_modes; |
e7b07cee HW |
7263 | } |
7264 | ||
15f9dfd5 HW |
7265 | static const u32 supported_colorspaces = |
7266 | BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | | |
7267 | BIT(DRM_MODE_COLORIMETRY_OPRGB) | | |
7268 | BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | | |
7269 | BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); | |
7270 | ||
3ee6b26b AD |
7271 | void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, |
7272 | struct amdgpu_dm_connector *aconnector, | |
7273 | int connector_type, | |
7274 | struct dc_link *link, | |
7275 | int link_index) | |
e7b07cee | 7276 | { |
1348969a | 7277 | struct amdgpu_device *adev = drm_to_adev(dm->ddev); |
e7b07cee | 7278 | |
f04bee34 NK |
7279 | /* |
7280 | * Some of the properties below require access to state, like bpc. | |
7281 | * Allocate some default initial connector state with our reset helper. | |
7282 | */ | |
7283 | if (aconnector->base.funcs->reset) | |
7284 | aconnector->base.funcs->reset(&aconnector->base); | |
7285 | ||
e7b07cee | 7286 | aconnector->connector_id = link_index; |
f196198c | 7287 | aconnector->bl_idx = -1; |
e7b07cee HW |
7288 | aconnector->dc_link = link; |
7289 | aconnector->base.interlace_allowed = false; | |
7290 | aconnector->base.doublescan_allowed = false; | |
7291 | aconnector->base.stereo_allowed = false; | |
7292 | aconnector->base.dpms = DRM_MODE_DPMS_OFF; | |
7293 | aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ | |
6ce8f316 | 7294 | aconnector->audio_inst = -1; |
5b49da02 SJK |
7295 | aconnector->pack_sdp_v1_3 = false; |
7296 | aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; | |
7297 | memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); | |
e7b07cee HW |
7298 | mutex_init(&aconnector->hpd_lock); |
7299 | ||
1f6010a9 DF |
7300 | /* |
7301 | * configure support HPD hot plug connector_>polled default value is 0 | |
b830ebc9 HW |
7302 | * which means HPD hot plug not supported |
7303 | */ | |
e7b07cee HW |
7304 | switch (connector_type) { |
7305 | case DRM_MODE_CONNECTOR_HDMIA: | |
7306 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
e7baae1c | 7307 | aconnector->base.ycbcr_420_allowed = |
9ea59d5a | 7308 | link->link_enc->features.hdmi_ycbcr420_supported ? true : false; |
e7b07cee HW |
7309 | break; |
7310 | case DRM_MODE_CONNECTOR_DisplayPort: | |
7311 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
d715c9a2 | 7312 | link->link_enc = link_enc_cfg_get_link_enc(link); |
7b201d53 | 7313 | ASSERT(link->link_enc); |
f6e03f80 JS |
7314 | if (link->link_enc) |
7315 | aconnector->base.ycbcr_420_allowed = | |
9ea59d5a | 7316 | link->link_enc->features.dp_ycbcr420_supported ? true : false; |
e7b07cee HW |
7317 | break; |
7318 | case DRM_MODE_CONNECTOR_DVID: | |
7319 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
7320 | break; | |
7321 | default: | |
7322 | break; | |
7323 | } | |
7324 | ||
7325 | drm_object_attach_property(&aconnector->base.base, | |
7326 | dm->ddev->mode_config.scaling_mode_property, | |
7327 | DRM_MODE_SCALE_NONE); | |
7328 | ||
7329 | drm_object_attach_property(&aconnector->base.base, | |
7330 | adev->mode_info.underscan_property, | |
7331 | UNDERSCAN_OFF); | |
7332 | drm_object_attach_property(&aconnector->base.base, | |
7333 | adev->mode_info.underscan_hborder_property, | |
7334 | 0); | |
7335 | drm_object_attach_property(&aconnector->base.base, | |
7336 | adev->mode_info.underscan_vborder_property, | |
7337 | 0); | |
1825fd34 | 7338 | |
f0127cb1 | 7339 | if (!aconnector->mst_root) |
8c61b31e | 7340 | drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); |
1825fd34 | 7341 | |
e47f1691 | 7342 | aconnector->base.state->max_bpc = 16; |
4a8ca46b | 7343 | aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; |
e7b07cee | 7344 | |
c1ee92f9 | 7345 | if (connector_type == DRM_MODE_CONNECTOR_eDP && |
5cb32419 | 7346 | (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { |
c1ee92f9 DF |
7347 | drm_object_attach_property(&aconnector->base.base, |
7348 | adev->mode_info.abm_level_property, 0); | |
7349 | } | |
bb47de73 | 7350 | |
15f9dfd5 HW |
7351 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
7352 | if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) | |
7353 | drm_connector_attach_colorspace_property(&aconnector->base); | |
7354 | } else if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
7355 | connector_type == DRM_MODE_CONNECTOR_eDP) { | |
7356 | if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) | |
7357 | drm_connector_attach_colorspace_property(&aconnector->base); | |
7358 | } | |
7359 | ||
bb47de73 | 7360 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA || |
7fad8da1 NK |
7361 | connector_type == DRM_MODE_CONNECTOR_DisplayPort || |
7362 | connector_type == DRM_MODE_CONNECTOR_eDP) { | |
e057b52c | 7363 | drm_connector_attach_hdr_output_metadata_property(&aconnector->base); |
88694af9 | 7364 | |
f0127cb1 | 7365 | if (!aconnector->mst_root) |
8c61b31e JFZ |
7366 | drm_connector_attach_vrr_capable_property(&aconnector->base); |
7367 | ||
e22bb562 | 7368 | if (adev->dm.hdcp_workqueue) |
53e108aa | 7369 | drm_connector_attach_content_protection_property(&aconnector->base, true); |
bb47de73 | 7370 | } |
e7b07cee HW |
7371 | } |
7372 | ||
7578ecda AD |
7373 | static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, |
7374 | struct i2c_msg *msgs, int num) | |
e7b07cee HW |
7375 | { |
7376 | struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); | |
7377 | struct ddc_service *ddc_service = i2c->ddc_service; | |
7378 | struct i2c_command cmd; | |
7379 | int i; | |
7380 | int result = -EIO; | |
7381 | ||
b830ebc9 | 7382 | cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); |
e7b07cee HW |
7383 | |
7384 | if (!cmd.payloads) | |
7385 | return result; | |
7386 | ||
7387 | cmd.number_of_payloads = num; | |
7388 | cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; | |
7389 | cmd.speed = 100; | |
7390 | ||
7391 | for (i = 0; i < num; i++) { | |
7392 | cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); | |
7393 | cmd.payloads[i].address = msgs[i].addr; | |
7394 | cmd.payloads[i].length = msgs[i].len; | |
7395 | cmd.payloads[i].data = msgs[i].buf; | |
7396 | } | |
7397 | ||
c85e6e54 DF |
7398 | if (dc_submit_i2c( |
7399 | ddc_service->ctx->dc, | |
22676bc5 | 7400 | ddc_service->link->link_index, |
e7b07cee HW |
7401 | &cmd)) |
7402 | result = num; | |
7403 | ||
7404 | kfree(cmd.payloads); | |
7405 | return result; | |
7406 | } | |
7407 | ||
7578ecda | 7408 | static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) |
e7b07cee HW |
7409 | { |
7410 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
7411 | } | |
7412 | ||
7413 | static const struct i2c_algorithm amdgpu_dm_i2c_algo = { | |
7414 | .master_xfer = amdgpu_dm_i2c_xfer, | |
7415 | .functionality = amdgpu_dm_i2c_func, | |
7416 | }; | |
7417 | ||
3ee6b26b AD |
7418 | static struct amdgpu_i2c_adapter * |
7419 | create_i2c(struct ddc_service *ddc_service, | |
7420 | int link_index, | |
7421 | int *res) | |
e7b07cee HW |
7422 | { |
7423 | struct amdgpu_device *adev = ddc_service->ctx->driver_context; | |
7424 | struct amdgpu_i2c_adapter *i2c; | |
7425 | ||
b830ebc9 | 7426 | i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); |
2a55f096 ES |
7427 | if (!i2c) |
7428 | return NULL; | |
e7b07cee HW |
7429 | i2c->base.owner = THIS_MODULE; |
7430 | i2c->base.class = I2C_CLASS_DDC; | |
7431 | i2c->base.dev.parent = &adev->pdev->dev; | |
7432 | i2c->base.algo = &amdgpu_dm_i2c_algo; | |
b830ebc9 | 7433 | snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); |
e7b07cee HW |
7434 | i2c_set_adapdata(&i2c->base, i2c); |
7435 | i2c->ddc_service = ddc_service; | |
7436 | ||
7437 | return i2c; | |
7438 | } | |
7439 | ||
89fc8d4e | 7440 | |
1f6010a9 DF |
7441 | /* |
7442 | * Note: this function assumes that dc_link_detect() was called for the | |
b830ebc9 HW |
7443 | * dc_link which will be represented by this aconnector. |
7444 | */ | |
7578ecda AD |
7445 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
7446 | struct amdgpu_dm_connector *aconnector, | |
ae67558b | 7447 | u32 link_index, |
7578ecda | 7448 | struct amdgpu_encoder *aencoder) |
e7b07cee HW |
7449 | { |
7450 | int res = 0; | |
7451 | int connector_type; | |
7452 | struct dc *dc = dm->dc; | |
7453 | struct dc_link *link = dc_get_link_at_index(dc, link_index); | |
7454 | struct amdgpu_i2c_adapter *i2c; | |
9a227d26 TSD |
7455 | |
7456 | link->priv = aconnector; | |
e7b07cee | 7457 | |
e7b07cee HW |
7458 | |
7459 | i2c = create_i2c(link->ddc, link->link_index, &res); | |
2a55f096 ES |
7460 | if (!i2c) { |
7461 | DRM_ERROR("Failed to create i2c adapter data\n"); | |
7462 | return -ENOMEM; | |
7463 | } | |
7464 | ||
e7b07cee HW |
7465 | aconnector->i2c = i2c; |
7466 | res = i2c_add_adapter(&i2c->base); | |
7467 | ||
7468 | if (res) { | |
7469 | DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); | |
7470 | goto out_free; | |
7471 | } | |
7472 | ||
7473 | connector_type = to_drm_connector_type(link->connector_signal); | |
7474 | ||
17165de2 | 7475 | res = drm_connector_init_with_ddc( |
e7b07cee HW |
7476 | dm->ddev, |
7477 | &aconnector->base, | |
7478 | &amdgpu_dm_connector_funcs, | |
17165de2 AP |
7479 | connector_type, |
7480 | &i2c->base); | |
e7b07cee HW |
7481 | |
7482 | if (res) { | |
7483 | DRM_ERROR("connector_init failed\n"); | |
7484 | aconnector->connector_id = -1; | |
7485 | goto out_free; | |
7486 | } | |
7487 | ||
7488 | drm_connector_helper_add( | |
7489 | &aconnector->base, | |
7490 | &amdgpu_dm_connector_helper_funcs); | |
7491 | ||
7492 | amdgpu_dm_connector_init_helper( | |
7493 | dm, | |
7494 | aconnector, | |
7495 | connector_type, | |
7496 | link, | |
7497 | link_index); | |
7498 | ||
cde4c44d | 7499 | drm_connector_attach_encoder( |
e7b07cee HW |
7500 | &aconnector->base, &aencoder->base); |
7501 | ||
e7b07cee HW |
7502 | if (connector_type == DRM_MODE_CONNECTOR_DisplayPort |
7503 | || connector_type == DRM_MODE_CONNECTOR_eDP) | |
7daec99f | 7504 | amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); |
e7b07cee | 7505 | |
e7b07cee HW |
7506 | out_free: |
7507 | if (res) { | |
7508 | kfree(i2c); | |
7509 | aconnector->i2c = NULL; | |
7510 | } | |
7511 | return res; | |
7512 | } | |
7513 | ||
7514 | int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) | |
7515 | { | |
7516 | switch (adev->mode_info.num_crtc) { | |
7517 | case 1: | |
7518 | return 0x1; | |
7519 | case 2: | |
7520 | return 0x3; | |
7521 | case 3: | |
7522 | return 0x7; | |
7523 | case 4: | |
7524 | return 0xf; | |
7525 | case 5: | |
7526 | return 0x1f; | |
7527 | case 6: | |
7528 | default: | |
7529 | return 0x3f; | |
7530 | } | |
7531 | } | |
7532 | ||
7578ecda AD |
7533 | static int amdgpu_dm_encoder_init(struct drm_device *dev, |
7534 | struct amdgpu_encoder *aencoder, | |
7535 | uint32_t link_index) | |
e7b07cee | 7536 | { |
1348969a | 7537 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
7538 | |
7539 | int res = drm_encoder_init(dev, | |
7540 | &aencoder->base, | |
7541 | &amdgpu_dm_encoder_funcs, | |
7542 | DRM_MODE_ENCODER_TMDS, | |
7543 | NULL); | |
7544 | ||
7545 | aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); | |
7546 | ||
7547 | if (!res) | |
7548 | aencoder->encoder_id = link_index; | |
7549 | else | |
7550 | aencoder->encoder_id = -1; | |
7551 | ||
7552 | drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); | |
7553 | ||
7554 | return res; | |
7555 | } | |
7556 | ||
3ee6b26b AD |
7557 | static void manage_dm_interrupts(struct amdgpu_device *adev, |
7558 | struct amdgpu_crtc *acrtc, | |
7559 | bool enable) | |
e7b07cee HW |
7560 | { |
7561 | /* | |
8fe684e9 NK |
7562 | * We have no guarantee that the frontend index maps to the same |
7563 | * backend index - some even map to more than one. | |
7564 | * | |
7565 | * TODO: Use a different interrupt or check DC itself for the mapping. | |
e7b07cee HW |
7566 | */ |
7567 | int irq_type = | |
734dd01d | 7568 | amdgpu_display_crtc_idx_to_irq_type( |
e7b07cee HW |
7569 | adev, |
7570 | acrtc->crtc_id); | |
7571 | ||
7572 | if (enable) { | |
7573 | drm_crtc_vblank_on(&acrtc->base); | |
7574 | amdgpu_irq_get( | |
7575 | adev, | |
7576 | &adev->pageflip_irq, | |
7577 | irq_type); | |
86bc2219 WL |
7578 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
7579 | amdgpu_irq_get( | |
7580 | adev, | |
7581 | &adev->vline0_irq, | |
7582 | irq_type); | |
7583 | #endif | |
e7b07cee | 7584 | } else { |
86bc2219 WL |
7585 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
7586 | amdgpu_irq_put( | |
7587 | adev, | |
7588 | &adev->vline0_irq, | |
7589 | irq_type); | |
7590 | #endif | |
e7b07cee HW |
7591 | amdgpu_irq_put( |
7592 | adev, | |
7593 | &adev->pageflip_irq, | |
7594 | irq_type); | |
7595 | drm_crtc_vblank_off(&acrtc->base); | |
7596 | } | |
7597 | } | |
7598 | ||
8fe684e9 NK |
7599 | static void dm_update_pflip_irq_state(struct amdgpu_device *adev, |
7600 | struct amdgpu_crtc *acrtc) | |
7601 | { | |
7602 | int irq_type = | |
7603 | amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); | |
7604 | ||
7605 | /** | |
7606 | * This reads the current state for the IRQ and force reapplies | |
7607 | * the setting to hardware. | |
7608 | */ | |
7609 | amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); | |
7610 | } | |
7611 | ||
3ee6b26b AD |
7612 | static bool |
7613 | is_scaling_state_different(const struct dm_connector_state *dm_state, | |
7614 | const struct dm_connector_state *old_dm_state) | |
e7b07cee HW |
7615 | { |
7616 | if (dm_state->scaling != old_dm_state->scaling) | |
7617 | return true; | |
7618 | if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { | |
7619 | if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) | |
7620 | return true; | |
7621 | } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { | |
7622 | if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) | |
7623 | return true; | |
b830ebc9 HW |
7624 | } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || |
7625 | dm_state->underscan_vborder != old_dm_state->underscan_vborder) | |
7626 | return true; | |
e7b07cee HW |
7627 | return false; |
7628 | } | |
7629 | ||
e8fd3eeb | 7630 | static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, |
7631 | struct drm_crtc_state *old_crtc_state, | |
7632 | struct drm_connector_state *new_conn_state, | |
7633 | struct drm_connector_state *old_conn_state, | |
7634 | const struct drm_connector *connector, | |
7635 | struct hdcp_workqueue *hdcp_w) | |
0c8620d6 BL |
7636 | { |
7637 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
97f6c917 | 7638 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); |
0c8620d6 | 7639 | |
e8fd3eeb | 7640 | pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", |
7641 | connector->index, connector->status, connector->dpms); | |
7642 | pr_debug("[HDCP_DM] state protection old: %x new: %x\n", | |
7643 | old_conn_state->content_protection, new_conn_state->content_protection); | |
7644 | ||
7645 | if (old_crtc_state) | |
7646 | pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
7647 | old_crtc_state->enable, | |
7648 | old_crtc_state->active, | |
7649 | old_crtc_state->mode_changed, | |
7650 | old_crtc_state->active_changed, | |
7651 | old_crtc_state->connectors_changed); | |
7652 | ||
7653 | if (new_crtc_state) | |
7654 | pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
7655 | new_crtc_state->enable, | |
7656 | new_crtc_state->active, | |
7657 | new_crtc_state->mode_changed, | |
7658 | new_crtc_state->active_changed, | |
7659 | new_crtc_state->connectors_changed); | |
7660 | ||
7661 | /* hdcp content type change */ | |
7662 | if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && | |
7663 | new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { | |
7664 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
7665 | pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); | |
53e108aa BL |
7666 | return true; |
7667 | } | |
7668 | ||
e8fd3eeb | 7669 | /* CP is being re enabled, ignore this */ |
7670 | if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && | |
7671 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { | |
7672 | if (new_crtc_state && new_crtc_state->mode_changed) { | |
7673 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
7674 | pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); | |
7675 | return true; | |
0b8f42ab | 7676 | } |
e8fd3eeb | 7677 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; |
7678 | pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); | |
0c8620d6 BL |
7679 | return false; |
7680 | } | |
7681 | ||
31c0ed90 BL |
7682 | /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED |
7683 | * | |
7684 | * Handles: UNDESIRED -> ENABLED | |
7685 | */ | |
e8fd3eeb | 7686 | if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && |
7687 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) | |
7688 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
0c8620d6 | 7689 | |
0d9a947b QZ |
7690 | /* Stream removed and re-enabled |
7691 | * | |
7692 | * Can sometimes overlap with the HPD case, | |
7693 | * thus set update_hdcp to false to avoid | |
7694 | * setting HDCP multiple times. | |
7695 | * | |
7696 | * Handles: DESIRED -> DESIRED (Special case) | |
7697 | */ | |
e8fd3eeb | 7698 | if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && |
7699 | new_conn_state->crtc && new_conn_state->crtc->enabled && | |
0d9a947b QZ |
7700 | connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { |
7701 | dm_con_state->update_hdcp = false; | |
e8fd3eeb | 7702 | pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", |
7703 | __func__); | |
0d9a947b QZ |
7704 | return true; |
7705 | } | |
7706 | ||
7707 | /* Hot-plug, headless s3, dpms | |
7708 | * | |
7709 | * Only start HDCP if the display is connected/enabled. | |
7710 | * update_hdcp flag will be set to false until the next | |
7711 | * HPD comes in. | |
31c0ed90 BL |
7712 | * |
7713 | * Handles: DESIRED -> DESIRED (Special case) | |
0c8620d6 | 7714 | */ |
e8fd3eeb | 7715 | if (dm_con_state->update_hdcp && |
7716 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && | |
7717 | connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { | |
97f6c917 | 7718 | dm_con_state->update_hdcp = false; |
e8fd3eeb | 7719 | pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", |
7720 | __func__); | |
0c8620d6 | 7721 | return true; |
97f6c917 | 7722 | } |
0c8620d6 | 7723 | |
e8fd3eeb | 7724 | if (old_conn_state->content_protection == new_conn_state->content_protection) { |
7725 | if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { | |
7726 | if (new_crtc_state && new_crtc_state->mode_changed) { | |
7727 | pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", | |
7728 | __func__); | |
7729 | return true; | |
0b8f42ab | 7730 | } |
e8fd3eeb | 7731 | pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", |
7732 | __func__); | |
7733 | return false; | |
0b8f42ab | 7734 | } |
e8fd3eeb | 7735 | |
7736 | pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); | |
0c8620d6 | 7737 | return false; |
e8fd3eeb | 7738 | } |
0c8620d6 | 7739 | |
e8fd3eeb | 7740 | if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { |
7741 | pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", | |
7742 | __func__); | |
0c8620d6 | 7743 | return true; |
e8fd3eeb | 7744 | } |
0c8620d6 | 7745 | |
e8fd3eeb | 7746 | pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); |
0c8620d6 BL |
7747 | return false; |
7748 | } | |
e8fd3eeb | 7749 | |
3ee6b26b AD |
7750 | static void remove_stream(struct amdgpu_device *adev, |
7751 | struct amdgpu_crtc *acrtc, | |
7752 | struct dc_stream_state *stream) | |
e7b07cee HW |
7753 | { |
7754 | /* this is the update mode case */ | |
e7b07cee HW |
7755 | |
7756 | acrtc->otg_inst = -1; | |
7757 | acrtc->enabled = false; | |
7758 | } | |
7759 | ||
e7b07cee HW |
7760 | static void prepare_flip_isr(struct amdgpu_crtc *acrtc) |
7761 | { | |
7762 | ||
7763 | assert_spin_locked(&acrtc->base.dev->event_lock); | |
7764 | WARN_ON(acrtc->event); | |
7765 | ||
7766 | acrtc->event = acrtc->base.state->event; | |
7767 | ||
7768 | /* Set the flip status */ | |
7769 | acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; | |
7770 | ||
7771 | /* Mark this event as consumed */ | |
7772 | acrtc->base.state->event = NULL; | |
7773 | ||
cb2318b7 VL |
7774 | DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", |
7775 | acrtc->crtc_id); | |
e7b07cee HW |
7776 | } |
7777 | ||
bb47de73 NK |
7778 | static void update_freesync_state_on_stream( |
7779 | struct amdgpu_display_manager *dm, | |
7780 | struct dm_crtc_state *new_crtc_state, | |
180db303 NK |
7781 | struct dc_stream_state *new_stream, |
7782 | struct dc_plane_state *surface, | |
7783 | u32 flip_timestamp_in_us) | |
bb47de73 | 7784 | { |
09aef2c4 | 7785 | struct mod_vrr_params vrr_params; |
bb47de73 | 7786 | struct dc_info_packet vrr_infopacket = {0}; |
09aef2c4 | 7787 | struct amdgpu_device *adev = dm->adev; |
585d450c | 7788 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); |
09aef2c4 | 7789 | unsigned long flags; |
4cda3243 | 7790 | bool pack_sdp_v1_3 = false; |
5b49da02 SJK |
7791 | struct amdgpu_dm_connector *aconn; |
7792 | enum vrr_packet_type packet_type = PACKET_TYPE_VRR; | |
bb47de73 NK |
7793 | |
7794 | if (!new_stream) | |
7795 | return; | |
7796 | ||
7797 | /* | |
7798 | * TODO: Determine why min/max totals and vrefresh can be 0 here. | |
7799 | * For now it's sufficient to just guard against these conditions. | |
7800 | */ | |
7801 | ||
7802 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) | |
7803 | return; | |
7804 | ||
4a580877 | 7805 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
3335a135 | 7806 | vrr_params = acrtc->dm_irq_params.vrr_params; |
09aef2c4 | 7807 | |
180db303 NK |
7808 | if (surface) { |
7809 | mod_freesync_handle_preflip( | |
7810 | dm->freesync_module, | |
7811 | surface, | |
7812 | new_stream, | |
7813 | flip_timestamp_in_us, | |
7814 | &vrr_params); | |
09aef2c4 MK |
7815 | |
7816 | if (adev->family < AMDGPU_FAMILY_AI && | |
6c5e25a0 | 7817 | amdgpu_dm_crtc_vrr_active(new_crtc_state)) { |
09aef2c4 MK |
7818 | mod_freesync_handle_v_update(dm->freesync_module, |
7819 | new_stream, &vrr_params); | |
e63e2491 EB |
7820 | |
7821 | /* Need to call this before the frame ends. */ | |
7822 | dc_stream_adjust_vmin_vmax(dm->dc, | |
7823 | new_crtc_state->stream, | |
7824 | &vrr_params.adjust); | |
09aef2c4 | 7825 | } |
180db303 | 7826 | } |
bb47de73 | 7827 | |
5b49da02 SJK |
7828 | aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; |
7829 | ||
7830 | if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { | |
7831 | pack_sdp_v1_3 = aconn->pack_sdp_v1_3; | |
7832 | ||
7833 | if (aconn->vsdb_info.amd_vsdb_version == 1) | |
7834 | packet_type = PACKET_TYPE_FS_V1; | |
7835 | else if (aconn->vsdb_info.amd_vsdb_version == 2) | |
7836 | packet_type = PACKET_TYPE_FS_V2; | |
7837 | else if (aconn->vsdb_info.amd_vsdb_version == 3) | |
7838 | packet_type = PACKET_TYPE_FS_V3; | |
7839 | ||
7840 | mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, | |
7841 | &new_stream->adaptive_sync_infopacket); | |
7842 | } | |
7843 | ||
bb47de73 NK |
7844 | mod_freesync_build_vrr_infopacket( |
7845 | dm->freesync_module, | |
7846 | new_stream, | |
180db303 | 7847 | &vrr_params, |
5b49da02 | 7848 | packet_type, |
ecd0136b | 7849 | TRANSFER_FUNC_UNKNOWN, |
4cda3243 MT |
7850 | &vrr_infopacket, |
7851 | pack_sdp_v1_3); | |
bb47de73 | 7852 | |
8a48b44c | 7853 | new_crtc_state->freesync_vrr_info_changed |= |
bb47de73 NK |
7854 | (memcmp(&new_crtc_state->vrr_infopacket, |
7855 | &vrr_infopacket, | |
7856 | sizeof(vrr_infopacket)) != 0); | |
7857 | ||
585d450c | 7858 | acrtc->dm_irq_params.vrr_params = vrr_params; |
bb47de73 NK |
7859 | new_crtc_state->vrr_infopacket = vrr_infopacket; |
7860 | ||
bb47de73 | 7861 | new_stream->vrr_infopacket = vrr_infopacket; |
7eaef116 | 7862 | new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); |
bb47de73 NK |
7863 | |
7864 | if (new_crtc_state->freesync_vrr_info_changed) | |
7865 | DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", | |
7866 | new_crtc_state->base.crtc->base.id, | |
7867 | (int)new_crtc_state->base.vrr_enabled, | |
180db303 | 7868 | (int)vrr_params.state); |
09aef2c4 | 7869 | |
4a580877 | 7870 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
bb47de73 NK |
7871 | } |
7872 | ||
585d450c | 7873 | static void update_stream_irq_parameters( |
e854194c MK |
7874 | struct amdgpu_display_manager *dm, |
7875 | struct dm_crtc_state *new_crtc_state) | |
7876 | { | |
7877 | struct dc_stream_state *new_stream = new_crtc_state->stream; | |
09aef2c4 | 7878 | struct mod_vrr_params vrr_params; |
e854194c | 7879 | struct mod_freesync_config config = new_crtc_state->freesync_config; |
09aef2c4 | 7880 | struct amdgpu_device *adev = dm->adev; |
585d450c | 7881 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); |
09aef2c4 | 7882 | unsigned long flags; |
e854194c MK |
7883 | |
7884 | if (!new_stream) | |
7885 | return; | |
7886 | ||
7887 | /* | |
7888 | * TODO: Determine why min/max totals and vrefresh can be 0 here. | |
7889 | * For now it's sufficient to just guard against these conditions. | |
7890 | */ | |
7891 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) | |
7892 | return; | |
7893 | ||
4a580877 | 7894 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
585d450c | 7895 | vrr_params = acrtc->dm_irq_params.vrr_params; |
09aef2c4 | 7896 | |
e854194c MK |
7897 | if (new_crtc_state->vrr_supported && |
7898 | config.min_refresh_in_uhz && | |
7899 | config.max_refresh_in_uhz) { | |
a85ba005 NC |
7900 | /* |
7901 | * if freesync compatible mode was set, config.state will be set | |
7902 | * in atomic check | |
7903 | */ | |
7904 | if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && | |
7905 | (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || | |
7906 | new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { | |
7907 | vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; | |
7908 | vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; | |
7909 | vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; | |
7910 | vrr_params.state = VRR_STATE_ACTIVE_FIXED; | |
7911 | } else { | |
7912 | config.state = new_crtc_state->base.vrr_enabled ? | |
7913 | VRR_STATE_ACTIVE_VARIABLE : | |
7914 | VRR_STATE_INACTIVE; | |
7915 | } | |
e854194c MK |
7916 | } else { |
7917 | config.state = VRR_STATE_UNSUPPORTED; | |
7918 | } | |
7919 | ||
7920 | mod_freesync_build_vrr_params(dm->freesync_module, | |
7921 | new_stream, | |
7922 | &config, &vrr_params); | |
7923 | ||
585d450c AP |
7924 | new_crtc_state->freesync_config = config; |
7925 | /* Copy state for access from DM IRQ handler */ | |
7926 | acrtc->dm_irq_params.freesync_config = config; | |
7927 | acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; | |
7928 | acrtc->dm_irq_params.vrr_params = vrr_params; | |
4a580877 | 7929 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
e854194c MK |
7930 | } |
7931 | ||
66b0c973 MK |
7932 | static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, |
7933 | struct dm_crtc_state *new_state) | |
7934 | { | |
6c5e25a0 DT |
7935 | bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); |
7936 | bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); | |
66b0c973 MK |
7937 | |
7938 | if (!old_vrr_active && new_vrr_active) { | |
7939 | /* Transition VRR inactive -> active: | |
7940 | * While VRR is active, we must not disable vblank irq, as a | |
7941 | * reenable after disable would compute bogus vblank/pflip | |
7942 | * timestamps if it likely happened inside display front-porch. | |
d2574c33 MK |
7943 | * |
7944 | * We also need vupdate irq for the actual core vblank handling | |
7945 | * at end of vblank. | |
66b0c973 | 7946 | */ |
6c5e25a0 | 7947 | WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); |
8799c0be | 7948 | WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); |
66b0c973 MK |
7949 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", |
7950 | __func__, new_state->base.crtc->base.id); | |
7951 | } else if (old_vrr_active && !new_vrr_active) { | |
7952 | /* Transition VRR active -> inactive: | |
7953 | * Allow vblank irq disable again for fixed refresh rate. | |
7954 | */ | |
6c5e25a0 | 7955 | WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); |
66b0c973 MK |
7956 | drm_crtc_vblank_put(new_state->base.crtc); |
7957 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", | |
7958 | __func__, new_state->base.crtc->base.id); | |
7959 | } | |
7960 | } | |
7961 | ||
8ad27806 NK |
7962 | static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) |
7963 | { | |
7964 | struct drm_plane *plane; | |
5760dcb9 | 7965 | struct drm_plane_state *old_plane_state; |
8ad27806 NK |
7966 | int i; |
7967 | ||
7968 | /* | |
7969 | * TODO: Make this per-stream so we don't issue redundant updates for | |
7970 | * commits with multiple streams. | |
7971 | */ | |
5760dcb9 | 7972 | for_each_old_plane_in_state(state, plane, old_plane_state, i) |
8ad27806 | 7973 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
8bf0d9cd | 7974 | amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); |
8ad27806 NK |
7975 | } |
7976 | ||
08da1821 HM |
7977 | static inline uint32_t get_mem_type(struct drm_framebuffer *fb) |
7978 | { | |
7979 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); | |
7980 | ||
7981 | return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; | |
7982 | } | |
7983 | ||
3be5262e | 7984 | static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, |
eb3dc897 | 7985 | struct dc_state *dc_state, |
3ee6b26b AD |
7986 | struct drm_device *dev, |
7987 | struct amdgpu_display_manager *dm, | |
7988 | struct drm_crtc *pcrtc, | |
420cd472 | 7989 | bool wait_for_vblank) |
e7b07cee | 7990 | { |
ae67558b | 7991 | u32 i; |
d6ed6d0d | 7992 | u64 timestamp_ns = ktime_get_ns(); |
e7b07cee | 7993 | struct drm_plane *plane; |
0bc9706d | 7994 | struct drm_plane_state *old_plane_state, *new_plane_state; |
e7b07cee | 7995 | struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); |
0bc9706d LSL |
7996 | struct drm_crtc_state *new_pcrtc_state = |
7997 | drm_atomic_get_new_crtc_state(state, pcrtc); | |
7998 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); | |
44d09c6a HW |
7999 | struct dm_crtc_state *dm_old_crtc_state = |
8000 | to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); | |
74aa7bd4 | 8001 | int planes_count = 0, vpos, hpos; |
e7b07cee | 8002 | unsigned long flags; |
ae67558b | 8003 | u32 target_vblank, last_flip_vblank; |
6c5e25a0 | 8004 | bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); |
cc79950b | 8005 | bool cursor_update = false; |
74aa7bd4 | 8006 | bool pflip_present = false; |
d6ed6d0d | 8007 | bool dirty_rects_changed = false; |
bc7f670e DF |
8008 | struct { |
8009 | struct dc_surface_update surface_updates[MAX_SURFACES]; | |
8010 | struct dc_plane_info plane_infos[MAX_SURFACES]; | |
8011 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; | |
74aa7bd4 | 8012 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; |
bc7f670e | 8013 | struct dc_stream_update stream_update; |
74aa7bd4 | 8014 | } *bundle; |
bc7f670e | 8015 | |
74aa7bd4 | 8016 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); |
8a48b44c | 8017 | |
74aa7bd4 DF |
8018 | if (!bundle) { |
8019 | dm_error("Failed to allocate update bundle\n"); | |
4b510503 NK |
8020 | goto cleanup; |
8021 | } | |
e7b07cee | 8022 | |
8ad27806 NK |
8023 | /* |
8024 | * Disable the cursor first if we're disabling all the planes. | |
8025 | * It'll remain on the screen after the planes are re-enabled | |
8026 | * if we don't. | |
8027 | */ | |
8028 | if (acrtc_state->active_planes == 0) | |
8029 | amdgpu_dm_commit_cursors(state); | |
8030 | ||
e7b07cee | 8031 | /* update planes when needed */ |
efc8278e | 8032 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { |
0bc9706d | 8033 | struct drm_crtc *crtc = new_plane_state->crtc; |
f5ba60fe | 8034 | struct drm_crtc_state *new_crtc_state; |
0bc9706d | 8035 | struct drm_framebuffer *fb = new_plane_state->fb; |
6eed95b0 | 8036 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; |
34bafd27 | 8037 | bool plane_needs_flip; |
c7af5f77 | 8038 | struct dc_plane_state *dc_plane; |
54d76575 | 8039 | struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); |
e7b07cee | 8040 | |
80c218d5 | 8041 | /* Cursor plane is handled after stream updates */ |
cc79950b MD |
8042 | if (plane->type == DRM_PLANE_TYPE_CURSOR) { |
8043 | if ((fb && crtc == pcrtc) || | |
8044 | (old_plane_state->fb && old_plane_state->crtc == pcrtc)) | |
8045 | cursor_update = true; | |
8046 | ||
e7b07cee | 8047 | continue; |
cc79950b | 8048 | } |
e7b07cee | 8049 | |
f5ba60fe DD |
8050 | if (!fb || !crtc || pcrtc != crtc) |
8051 | continue; | |
8052 | ||
8053 | new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); | |
8054 | if (!new_crtc_state->active) | |
e7b07cee HW |
8055 | continue; |
8056 | ||
bc7f670e | 8057 | dc_plane = dm_new_plane_state->dc_state; |
da5e1490 AP |
8058 | if (!dc_plane) |
8059 | continue; | |
e7b07cee | 8060 | |
74aa7bd4 | 8061 | bundle->surface_updates[planes_count].surface = dc_plane; |
bc7f670e | 8062 | if (new_pcrtc_state->color_mgmt_changed) { |
74aa7bd4 DF |
8063 | bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; |
8064 | bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; | |
44efb784 | 8065 | bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; |
bc7f670e | 8066 | } |
8a48b44c | 8067 | |
8bf0d9cd | 8068 | amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, |
695af5f9 | 8069 | &bundle->scaling_infos[planes_count]); |
8a48b44c | 8070 | |
695af5f9 NK |
8071 | bundle->surface_updates[planes_count].scaling_info = |
8072 | &bundle->scaling_infos[planes_count]; | |
8a48b44c | 8073 | |
f5031000 | 8074 | plane_needs_flip = old_plane_state->fb && new_plane_state->fb; |
8a48b44c | 8075 | |
f5031000 | 8076 | pflip_present = pflip_present || plane_needs_flip; |
8a48b44c | 8077 | |
f5031000 DF |
8078 | if (!plane_needs_flip) { |
8079 | planes_count += 1; | |
8080 | continue; | |
8081 | } | |
8a48b44c | 8082 | |
695af5f9 | 8083 | fill_dc_plane_info_and_addr( |
8ce5d842 | 8084 | dm->adev, new_plane_state, |
6eed95b0 | 8085 | afb->tiling_flags, |
695af5f9 | 8086 | &bundle->plane_infos[planes_count], |
87b7ebc2 | 8087 | &bundle->flip_addrs[planes_count].address, |
6eed95b0 | 8088 | afb->tmz_surface, false); |
87b7ebc2 | 8089 | |
9f07550b | 8090 | drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", |
87b7ebc2 RS |
8091 | new_plane_state->plane->index, |
8092 | bundle->plane_infos[planes_count].dcc.enable); | |
695af5f9 NK |
8093 | |
8094 | bundle->surface_updates[planes_count].plane_info = | |
8095 | &bundle->plane_infos[planes_count]; | |
8a48b44c | 8096 | |
d6ed6d0d | 8097 | if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) { |
d852871c HM |
8098 | fill_dc_dirty_rects(plane, old_plane_state, |
8099 | new_plane_state, new_crtc_state, | |
d6ed6d0d TC |
8100 | &bundle->flip_addrs[planes_count], |
8101 | &dirty_rects_changed); | |
8102 | ||
8103 | /* | |
8104 | * If the dirty regions changed, PSR-SU need to be disabled temporarily | |
8105 | * and enabled it again after dirty regions are stable to avoid video glitch. | |
8106 | * PSR-SU will be enabled in vblank_control_worker() if user pause the video | |
8107 | * during the PSR-SU was disabled. | |
8108 | */ | |
8109 | if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && | |
8110 | acrtc_attach->dm_irq_params.allow_psr_entry && | |
8111 | #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY | |
8112 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && | |
8113 | #endif | |
8114 | dirty_rects_changed) { | |
8115 | mutex_lock(&dm->dc_lock); | |
8116 | acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = | |
8117 | timestamp_ns; | |
8118 | if (acrtc_state->stream->link->psr_settings.psr_allow_active) | |
8119 | amdgpu_dm_psr_disable(acrtc_state->stream); | |
8120 | mutex_unlock(&dm->dc_lock); | |
8121 | } | |
8122 | } | |
7cc191ee | 8123 | |
caff0e66 NK |
8124 | /* |
8125 | * Only allow immediate flips for fast updates that don't | |
08da1821 HM |
8126 | * change memory domain, FB pitch, DCC state, rotation or |
8127 | * mirroring. | |
caff0e66 | 8128 | */ |
f5031000 | 8129 | bundle->flip_addrs[planes_count].flip_immediate = |
4d85f45c | 8130 | crtc->state->async_flip && |
08da1821 HM |
8131 | acrtc_state->update_type == UPDATE_TYPE_FAST && |
8132 | get_mem_type(old_plane_state->fb) == get_mem_type(fb); | |
8a48b44c | 8133 | |
f5031000 DF |
8134 | timestamp_ns = ktime_get_ns(); |
8135 | bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); | |
8136 | bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; | |
8137 | bundle->surface_updates[planes_count].surface = dc_plane; | |
8a48b44c | 8138 | |
f5031000 DF |
8139 | if (!bundle->surface_updates[planes_count].surface) { |
8140 | DRM_ERROR("No surface for CRTC: id=%d\n", | |
8141 | acrtc_attach->crtc_id); | |
8142 | continue; | |
bc7f670e DF |
8143 | } |
8144 | ||
f5031000 DF |
8145 | if (plane == pcrtc->primary) |
8146 | update_freesync_state_on_stream( | |
8147 | dm, | |
8148 | acrtc_state, | |
8149 | acrtc_state->stream, | |
8150 | dc_plane, | |
8151 | bundle->flip_addrs[planes_count].flip_timestamp_in_us); | |
bc7f670e | 8152 | |
9f07550b | 8153 | drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", |
f5031000 DF |
8154 | __func__, |
8155 | bundle->flip_addrs[planes_count].address.grph.addr.high_part, | |
8156 | bundle->flip_addrs[planes_count].address.grph.addr.low_part); | |
bc7f670e DF |
8157 | |
8158 | planes_count += 1; | |
8159 | ||
8a48b44c DF |
8160 | } |
8161 | ||
74aa7bd4 | 8162 | if (pflip_present) { |
634092b1 MK |
8163 | if (!vrr_active) { |
8164 | /* Use old throttling in non-vrr fixed refresh rate mode | |
8165 | * to keep flip scheduling based on target vblank counts | |
8166 | * working in a backwards compatible way, e.g., for | |
8167 | * clients using the GLX_OML_sync_control extension or | |
8168 | * DRI3/Present extension with defined target_msc. | |
8169 | */ | |
e3eff4b5 | 8170 | last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); |
c82eddf8 | 8171 | } else { |
634092b1 MK |
8172 | /* For variable refresh rate mode only: |
8173 | * Get vblank of last completed flip to avoid > 1 vrr | |
8174 | * flips per video frame by use of throttling, but allow | |
8175 | * flip programming anywhere in the possibly large | |
8176 | * variable vrr vblank interval for fine-grained flip | |
8177 | * timing control and more opportunity to avoid stutter | |
8178 | * on late submission of flips. | |
8179 | */ | |
8180 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
5d1c59c4 | 8181 | last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; |
634092b1 MK |
8182 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
8183 | } | |
8184 | ||
fdd1fe57 | 8185 | target_vblank = last_flip_vblank + wait_for_vblank; |
8a48b44c DF |
8186 | |
8187 | /* | |
8188 | * Wait until we're out of the vertical blank period before the one | |
8189 | * targeted by the flip | |
8190 | */ | |
8191 | while ((acrtc_attach->enabled && | |
8192 | (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, | |
8193 | 0, &vpos, &hpos, NULL, | |
8194 | NULL, &pcrtc->hwmode) | |
8195 | & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == | |
8196 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && | |
8197 | (int)(target_vblank - | |
e3eff4b5 | 8198 | amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { |
8a48b44c DF |
8199 | usleep_range(1000, 1100); |
8200 | } | |
8201 | ||
8fe684e9 NK |
8202 | /** |
8203 | * Prepare the flip event for the pageflip interrupt to handle. | |
8204 | * | |
8205 | * This only works in the case where we've already turned on the | |
8206 | * appropriate hardware blocks (eg. HUBP) so in the transition case | |
8207 | * from 0 -> n planes we have to skip a hardware generated event | |
8208 | * and rely on sending it from software. | |
8209 | */ | |
8210 | if (acrtc_attach->base.state->event && | |
10a36226 | 8211 | acrtc_state->active_planes > 0) { |
8a48b44c DF |
8212 | drm_crtc_vblank_get(pcrtc); |
8213 | ||
8214 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
8215 | ||
8216 | WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); | |
8217 | prepare_flip_isr(acrtc_attach); | |
8218 | ||
8219 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
8220 | } | |
8221 | ||
8222 | if (acrtc_state->stream) { | |
8a48b44c | 8223 | if (acrtc_state->freesync_vrr_info_changed) |
74aa7bd4 | 8224 | bundle->stream_update.vrr_infopacket = |
8a48b44c | 8225 | &acrtc_state->stream->vrr_infopacket; |
e7b07cee | 8226 | } |
cc79950b MD |
8227 | } else if (cursor_update && acrtc_state->active_planes > 0 && |
8228 | acrtc_attach->base.state->event) { | |
8229 | drm_crtc_vblank_get(pcrtc); | |
8230 | ||
8231 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
8232 | ||
8233 | acrtc_attach->event = acrtc_attach->base.state->event; | |
8234 | acrtc_attach->base.state->event = NULL; | |
8235 | ||
8236 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
e7b07cee HW |
8237 | } |
8238 | ||
bc92c065 | 8239 | /* Update the planes if changed or disable if we don't have any. */ |
ed9656fb ES |
8240 | if ((planes_count || acrtc_state->active_planes == 0) && |
8241 | acrtc_state->stream) { | |
58aa1c50 NK |
8242 | /* |
8243 | * If PSR or idle optimizations are enabled then flush out | |
8244 | * any pending work before hardware programming. | |
8245 | */ | |
06dd1888 NK |
8246 | if (dm->vblank_control_workqueue) |
8247 | flush_workqueue(dm->vblank_control_workqueue); | |
58aa1c50 | 8248 | |
b6e881c9 | 8249 | bundle->stream_update.stream = acrtc_state->stream; |
bc7f670e | 8250 | if (new_pcrtc_state->mode_changed) { |
74aa7bd4 DF |
8251 | bundle->stream_update.src = acrtc_state->stream->src; |
8252 | bundle->stream_update.dst = acrtc_state->stream->dst; | |
e7b07cee HW |
8253 | } |
8254 | ||
cf020d49 NK |
8255 | if (new_pcrtc_state->color_mgmt_changed) { |
8256 | /* | |
8257 | * TODO: This isn't fully correct since we've actually | |
8258 | * already modified the stream in place. | |
8259 | */ | |
8260 | bundle->stream_update.gamut_remap = | |
8261 | &acrtc_state->stream->gamut_remap_matrix; | |
8262 | bundle->stream_update.output_csc_transform = | |
8263 | &acrtc_state->stream->csc_color_matrix; | |
8264 | bundle->stream_update.out_transfer_func = | |
8265 | acrtc_state->stream->out_transfer_func; | |
8266 | } | |
bc7f670e | 8267 | |
8a48b44c | 8268 | acrtc_state->stream->abm_level = acrtc_state->abm_level; |
bc7f670e | 8269 | if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) |
74aa7bd4 | 8270 | bundle->stream_update.abm_level = &acrtc_state->abm_level; |
44d09c6a | 8271 | |
f3081166 TC |
8272 | mutex_lock(&dm->dc_lock); |
8273 | if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && | |
8274 | acrtc_state->stream->link->psr_settings.psr_allow_active) | |
8275 | amdgpu_dm_psr_disable(acrtc_state->stream); | |
8276 | mutex_unlock(&dm->dc_lock); | |
8277 | ||
e63e2491 EB |
8278 | /* |
8279 | * If FreeSync state on the stream has changed then we need to | |
8280 | * re-adjust the min/max bounds now that DC doesn't handle this | |
8281 | * as part of commit. | |
8282 | */ | |
a85ba005 | 8283 | if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { |
e63e2491 EB |
8284 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); |
8285 | dc_stream_adjust_vmin_vmax( | |
8286 | dm->dc, acrtc_state->stream, | |
585d450c | 8287 | &acrtc_attach->dm_irq_params.vrr_params.adjust); |
e63e2491 EB |
8288 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
8289 | } | |
bc7f670e | 8290 | mutex_lock(&dm->dc_lock); |
81f743a0 RS |
8291 | update_planes_and_stream_adapter(dm->dc, |
8292 | acrtc_state->update_type, | |
8293 | planes_count, | |
8294 | acrtc_state->stream, | |
8295 | &bundle->stream_update, | |
8296 | bundle->surface_updates); | |
8c322309 | 8297 | |
8fe684e9 NK |
8298 | /** |
8299 | * Enable or disable the interrupts on the backend. | |
8300 | * | |
8301 | * Most pipes are put into power gating when unused. | |
8302 | * | |
8303 | * When power gating is enabled on a pipe we lose the | |
8304 | * interrupt enablement state when power gating is disabled. | |
8305 | * | |
8306 | * So we need to update the IRQ control state in hardware | |
8307 | * whenever the pipe turns on (since it could be previously | |
8308 | * power gated) or off (since some pipes can't be power gated | |
8309 | * on some ASICs). | |
8310 | */ | |
8311 | if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) | |
1348969a LT |
8312 | dm_update_pflip_irq_state(drm_to_adev(dev), |
8313 | acrtc_attach); | |
8fe684e9 | 8314 | |
8c322309 | 8315 | if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && |
1cfbbdde | 8316 | acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && |
d1ebfdd8 | 8317 | !acrtc_state->stream->link->psr_settings.psr_feature_enabled) |
8c322309 | 8318 | amdgpu_dm_link_setup_psr(acrtc_state->stream); |
58aa1c50 NK |
8319 | |
8320 | /* Decrement skip count when PSR is enabled and we're doing fast updates. */ | |
8321 | if (acrtc_state->update_type == UPDATE_TYPE_FAST && | |
8322 | acrtc_state->stream->link->psr_settings.psr_feature_enabled) { | |
8323 | struct amdgpu_dm_connector *aconn = | |
8324 | (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; | |
1a365683 RL |
8325 | |
8326 | if (aconn->psr_skip_count > 0) | |
8327 | aconn->psr_skip_count--; | |
58aa1c50 NK |
8328 | |
8329 | /* Allow PSR when skip count is 0. */ | |
8330 | acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; | |
7cc191ee LL |
8331 | |
8332 | /* | |
8333 | * If sink supports PSR SU, there is no need to rely on | |
8334 | * a vblank event disable request to enable PSR. PSR SU | |
8335 | * can be enabled immediately once OS demonstrates an | |
8336 | * adequate number of fast atomic commits to notify KMD | |
8337 | * of update events. See `vblank_control_worker()`. | |
8338 | */ | |
8339 | if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && | |
8340 | acrtc_attach->dm_irq_params.allow_psr_entry && | |
c0459bdd AL |
8341 | #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY |
8342 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && | |
8343 | #endif | |
d6ed6d0d TC |
8344 | !acrtc_state->stream->link->psr_settings.psr_allow_active && |
8345 | (timestamp_ns - | |
8346 | acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > | |
8347 | 500000000) | |
7cc191ee | 8348 | amdgpu_dm_psr_enable(acrtc_state->stream); |
58aa1c50 NK |
8349 | } else { |
8350 | acrtc_attach->dm_irq_params.allow_psr_entry = false; | |
8c322309 RL |
8351 | } |
8352 | ||
bc7f670e | 8353 | mutex_unlock(&dm->dc_lock); |
e7b07cee | 8354 | } |
4b510503 | 8355 | |
8ad27806 NK |
8356 | /* |
8357 | * Update cursor state *after* programming all the planes. | |
8358 | * This avoids redundant programming in the case where we're going | |
8359 | * to be disabling a single plane - those pipes are being disabled. | |
8360 | */ | |
8361 | if (acrtc_state->active_planes) | |
8362 | amdgpu_dm_commit_cursors(state); | |
80c218d5 | 8363 | |
4b510503 | 8364 | cleanup: |
74aa7bd4 | 8365 | kfree(bundle); |
e7b07cee HW |
8366 | } |
8367 | ||
6ce8f316 NK |
8368 | static void amdgpu_dm_commit_audio(struct drm_device *dev, |
8369 | struct drm_atomic_state *state) | |
8370 | { | |
1348969a | 8371 | struct amdgpu_device *adev = drm_to_adev(dev); |
6ce8f316 NK |
8372 | struct amdgpu_dm_connector *aconnector; |
8373 | struct drm_connector *connector; | |
8374 | struct drm_connector_state *old_con_state, *new_con_state; | |
8375 | struct drm_crtc_state *new_crtc_state; | |
8376 | struct dm_crtc_state *new_dm_crtc_state; | |
8377 | const struct dc_stream_status *status; | |
8378 | int i, inst; | |
8379 | ||
8380 | /* Notify device removals. */ | |
8381 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
8382 | if (old_con_state->crtc != new_con_state->crtc) { | |
8383 | /* CRTC changes require notification. */ | |
8384 | goto notify; | |
8385 | } | |
8386 | ||
8387 | if (!new_con_state->crtc) | |
8388 | continue; | |
8389 | ||
8390 | new_crtc_state = drm_atomic_get_new_crtc_state( | |
8391 | state, new_con_state->crtc); | |
8392 | ||
8393 | if (!new_crtc_state) | |
8394 | continue; | |
8395 | ||
8396 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
8397 | continue; | |
8398 | ||
3335a135 | 8399 | notify: |
6ce8f316 NK |
8400 | aconnector = to_amdgpu_dm_connector(connector); |
8401 | ||
8402 | mutex_lock(&adev->dm.audio_lock); | |
8403 | inst = aconnector->audio_inst; | |
8404 | aconnector->audio_inst = -1; | |
8405 | mutex_unlock(&adev->dm.audio_lock); | |
8406 | ||
8407 | amdgpu_dm_audio_eld_notify(adev, inst); | |
8408 | } | |
8409 | ||
8410 | /* Notify audio device additions. */ | |
8411 | for_each_new_connector_in_state(state, connector, new_con_state, i) { | |
8412 | if (!new_con_state->crtc) | |
8413 | continue; | |
8414 | ||
8415 | new_crtc_state = drm_atomic_get_new_crtc_state( | |
8416 | state, new_con_state->crtc); | |
8417 | ||
8418 | if (!new_crtc_state) | |
8419 | continue; | |
8420 | ||
8421 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
8422 | continue; | |
8423 | ||
8424 | new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); | |
8425 | if (!new_dm_crtc_state->stream) | |
8426 | continue; | |
8427 | ||
8428 | status = dc_stream_get_status(new_dm_crtc_state->stream); | |
8429 | if (!status) | |
8430 | continue; | |
8431 | ||
8432 | aconnector = to_amdgpu_dm_connector(connector); | |
8433 | ||
8434 | mutex_lock(&adev->dm.audio_lock); | |
8435 | inst = status->audio_inst; | |
8436 | aconnector->audio_inst = inst; | |
8437 | mutex_unlock(&adev->dm.audio_lock); | |
8438 | ||
8439 | amdgpu_dm_audio_eld_notify(adev, inst); | |
8440 | } | |
8441 | } | |
8442 | ||
1f6010a9 | 8443 | /* |
27b3f4fc LSL |
8444 | * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC |
8445 | * @crtc_state: the DRM CRTC state | |
8446 | * @stream_state: the DC stream state. | |
8447 | * | |
8448 | * Copy the mirrored transient state flags from DRM, to DC. It is used to bring | |
8449 | * a dc_stream_state's flags in sync with a drm_crtc_state's flags. | |
8450 | */ | |
8451 | static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, | |
8452 | struct dc_stream_state *stream_state) | |
8453 | { | |
b9952f93 | 8454 | stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); |
27b3f4fc | 8455 | } |
e7b07cee | 8456 | |
b8592b48 LL |
8457 | /** |
8458 | * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. | |
8459 | * @state: The atomic state to commit | |
8460 | * | |
8461 | * This will tell DC to commit the constructed DC state from atomic_check, | |
8462 | * programming the hardware. Any failures here implies a hardware failure, since | |
8463 | * atomic check should have filtered anything non-kosher. | |
8464 | */ | |
7578ecda | 8465 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) |
e7b07cee HW |
8466 | { |
8467 | struct drm_device *dev = state->dev; | |
1348969a | 8468 | struct amdgpu_device *adev = drm_to_adev(dev); |
e7b07cee HW |
8469 | struct amdgpu_display_manager *dm = &adev->dm; |
8470 | struct dm_atomic_state *dm_state; | |
eb3dc897 | 8471 | struct dc_state *dc_state = NULL, *dc_state_temp = NULL; |
ae67558b | 8472 | u32 i, j; |
5cc6dcbd | 8473 | struct drm_crtc *crtc; |
0bc9706d | 8474 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
e7b07cee HW |
8475 | unsigned long flags; |
8476 | bool wait_for_vblank = true; | |
8477 | struct drm_connector *connector; | |
c2cea706 | 8478 | struct drm_connector_state *old_con_state, *new_con_state; |
54d76575 | 8479 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
fe2a1965 | 8480 | int crtc_disable_count = 0; |
6ee90e88 | 8481 | bool mode_set_reset_required = false; |
047de3f1 | 8482 | int r; |
e7b07cee | 8483 | |
e8a98235 RS |
8484 | trace_amdgpu_dm_atomic_commit_tail_begin(state); |
8485 | ||
047de3f1 CK |
8486 | r = drm_atomic_helper_wait_for_fences(dev, state, false); |
8487 | if (unlikely(r)) | |
8488 | DRM_ERROR("Waiting for fences timed out!"); | |
8489 | ||
e7b07cee | 8490 | drm_atomic_helper_update_legacy_modeset_state(dev, state); |
a5c2c0d1 | 8491 | drm_dp_mst_atomic_wait_for_dependencies(state); |
e7b07cee | 8492 | |
eb3dc897 NK |
8493 | dm_state = dm_atomic_get_new_state(state); |
8494 | if (dm_state && dm_state->context) { | |
8495 | dc_state = dm_state->context; | |
8496 | } else { | |
8497 | /* No state changes, retain current state. */ | |
813d20dc | 8498 | dc_state_temp = dc_create_state(dm->dc); |
eb3dc897 NK |
8499 | ASSERT(dc_state_temp); |
8500 | dc_state = dc_state_temp; | |
8501 | dc_resource_state_copy_construct_current(dm->dc, dc_state); | |
8502 | } | |
e7b07cee | 8503 | |
c82eddf8 SS |
8504 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, |
8505 | new_crtc_state, i) { | |
6d90a208 AP |
8506 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
8507 | ||
8508 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
8509 | ||
8510 | if (old_crtc_state->active && | |
8511 | (!new_crtc_state->active || | |
8512 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
8513 | manage_dm_interrupts(adev, acrtc, false); | |
8514 | dc_stream_release(dm_old_crtc_state->stream); | |
8515 | } | |
8516 | } | |
8517 | ||
8976f73b RS |
8518 | drm_atomic_helper_calc_timestamping_constants(state); |
8519 | ||
e7b07cee | 8520 | /* update changed items */ |
0bc9706d | 8521 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
e7b07cee | 8522 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 8523 | |
54d76575 LSL |
8524 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
8525 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
e7b07cee | 8526 | |
9f07550b | 8527 | drm_dbg_state(state->dev, |
c82eddf8 | 8528 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", |
e7b07cee | 8529 | acrtc->crtc_id, |
0bc9706d LSL |
8530 | new_crtc_state->enable, |
8531 | new_crtc_state->active, | |
8532 | new_crtc_state->planes_changed, | |
8533 | new_crtc_state->mode_changed, | |
8534 | new_crtc_state->active_changed, | |
8535 | new_crtc_state->connectors_changed); | |
e7b07cee | 8536 | |
5c68c652 VL |
8537 | /* Disable cursor if disabling crtc */ |
8538 | if (old_crtc_state->active && !new_crtc_state->active) { | |
8539 | struct dc_cursor_position position; | |
8540 | ||
8541 | memset(&position, 0, sizeof(position)); | |
8542 | mutex_lock(&dm->dc_lock); | |
8543 | dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); | |
8544 | mutex_unlock(&dm->dc_lock); | |
8545 | } | |
8546 | ||
27b3f4fc LSL |
8547 | /* Copy all transient state flags into dc state */ |
8548 | if (dm_new_crtc_state->stream) { | |
8549 | amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, | |
8550 | dm_new_crtc_state->stream); | |
8551 | } | |
8552 | ||
e7b07cee HW |
8553 | /* handles headless hotplug case, updating new_state and |
8554 | * aconnector as needed | |
8555 | */ | |
8556 | ||
6c5e25a0 | 8557 | if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { |
e7b07cee | 8558 | |
4711c033 | 8559 | DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee | 8560 | |
54d76575 | 8561 | if (!dm_new_crtc_state->stream) { |
e7b07cee | 8562 | /* |
b830ebc9 HW |
8563 | * this could happen because of issues with |
8564 | * userspace notifications delivery. | |
8565 | * In this case userspace tries to set mode on | |
1f6010a9 DF |
8566 | * display which is disconnected in fact. |
8567 | * dc_sink is NULL in this case on aconnector. | |
b830ebc9 HW |
8568 | * We expect reset mode will come soon. |
8569 | * | |
8570 | * This can also happen when unplug is done | |
8571 | * during resume sequence ended | |
8572 | * | |
8573 | * In this case, we want to pretend we still | |
8574 | * have a sink to keep the pipe running so that | |
8575 | * hw state is consistent with the sw state | |
8576 | */ | |
f1ad2f5e | 8577 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", |
e7b07cee HW |
8578 | __func__, acrtc->base.base.id); |
8579 | continue; | |
8580 | } | |
8581 | ||
54d76575 LSL |
8582 | if (dm_old_crtc_state->stream) |
8583 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); | |
e7b07cee | 8584 | |
97028037 LP |
8585 | pm_runtime_get_noresume(dev->dev); |
8586 | ||
e7b07cee | 8587 | acrtc->enabled = true; |
0bc9706d LSL |
8588 | acrtc->hw_mode = new_crtc_state->mode; |
8589 | crtc->hwmode = new_crtc_state->mode; | |
6ee90e88 | 8590 | mode_set_reset_required = true; |
0bc9706d | 8591 | } else if (modereset_required(new_crtc_state)) { |
4711c033 | 8592 | DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee | 8593 | /* i.e. reset mode */ |
6ee90e88 | 8594 | if (dm_old_crtc_state->stream) |
54d76575 | 8595 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); |
a85ba005 | 8596 | |
6ee90e88 | 8597 | mode_set_reset_required = true; |
e7b07cee HW |
8598 | } |
8599 | } /* for_each_crtc_in_state() */ | |
8600 | ||
eb3dc897 | 8601 | if (dc_state) { |
6ee90e88 | 8602 | /* if there mode set or reset, disable eDP PSR */ |
58aa1c50 | 8603 | if (mode_set_reset_required) { |
06dd1888 NK |
8604 | if (dm->vblank_control_workqueue) |
8605 | flush_workqueue(dm->vblank_control_workqueue); | |
cae5c1ab | 8606 | |
6ee90e88 | 8607 | amdgpu_dm_psr_disable_all(dm); |
58aa1c50 | 8608 | } |
6ee90e88 | 8609 | |
eb3dc897 | 8610 | dm_enable_per_frame_crtc_master_sync(dc_state); |
674e78ac | 8611 | mutex_lock(&dm->dc_lock); |
b8272241 | 8612 | WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count)); |
f3106c94 JC |
8613 | |
8614 | /* Allow idle optimization when vblank count is 0 for display off */ | |
8615 | if (dm->active_vblank_irq_count == 0) | |
8616 | dc_allow_idle_optimizations(dm->dc, true); | |
674e78ac | 8617 | mutex_unlock(&dm->dc_lock); |
fa2123db | 8618 | } |
fe8858bb | 8619 | |
0bc9706d | 8620 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 8621 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 8622 | |
54d76575 | 8623 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 8624 | |
54d76575 | 8625 | if (dm_new_crtc_state->stream != NULL) { |
e7b07cee | 8626 | const struct dc_stream_status *status = |
54d76575 | 8627 | dc_stream_get_status(dm_new_crtc_state->stream); |
e7b07cee | 8628 | |
eb3dc897 | 8629 | if (!status) |
09f609c3 LL |
8630 | status = dc_stream_get_status_from_state(dc_state, |
8631 | dm_new_crtc_state->stream); | |
e7b07cee | 8632 | if (!status) |
54d76575 | 8633 | DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); |
e7b07cee HW |
8634 | else |
8635 | acrtc->otg_inst = status->primary_otg_inst; | |
8636 | } | |
8637 | } | |
0c8620d6 BL |
8638 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
8639 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
8640 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
8641 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
8642 | ||
3cf7cd3f HW |
8643 | if (!adev->dm.hdcp_workqueue) |
8644 | continue; | |
8645 | ||
e8fd3eeb | 8646 | pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); |
8647 | ||
8648 | if (!connector) | |
8649 | continue; | |
8650 | ||
8651 | pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", | |
8652 | connector->index, connector->status, connector->dpms); | |
8653 | pr_debug("[HDCP_DM] state protection old: %x new: %x\n", | |
8654 | old_con_state->content_protection, new_con_state->content_protection); | |
8655 | ||
8656 | if (aconnector->dc_sink) { | |
8657 | if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && | |
8658 | aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { | |
8659 | pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", | |
8660 | aconnector->dc_sink->edid_caps.display_name); | |
8661 | } | |
8662 | } | |
8663 | ||
0c8620d6 | 8664 | new_crtc_state = NULL; |
e8fd3eeb | 8665 | old_crtc_state = NULL; |
0c8620d6 | 8666 | |
e8fd3eeb | 8667 | if (acrtc) { |
0c8620d6 | 8668 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
e8fd3eeb | 8669 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
8670 | } | |
8671 | ||
8672 | if (old_crtc_state) | |
8673 | pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
8674 | old_crtc_state->enable, | |
8675 | old_crtc_state->active, | |
8676 | old_crtc_state->mode_changed, | |
8677 | old_crtc_state->active_changed, | |
8678 | old_crtc_state->connectors_changed); | |
8679 | ||
8680 | if (new_crtc_state) | |
8681 | pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", | |
8682 | new_crtc_state->enable, | |
8683 | new_crtc_state->active, | |
8684 | new_crtc_state->mode_changed, | |
8685 | new_crtc_state->active_changed, | |
8686 | new_crtc_state->connectors_changed); | |
8687 | } | |
8688 | ||
8689 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
8690 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
8691 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
8692 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | |
8693 | ||
3cf7cd3f HW |
8694 | if (!adev->dm.hdcp_workqueue) |
8695 | continue; | |
8696 | ||
e8fd3eeb | 8697 | new_crtc_state = NULL; |
8698 | old_crtc_state = NULL; | |
8699 | ||
8700 | if (acrtc) { | |
8701 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); | |
8702 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); | |
8703 | } | |
0c8620d6 BL |
8704 | |
8705 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
8706 | ||
8707 | if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && | |
8708 | connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { | |
8709 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); | |
8710 | new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
97f6c917 | 8711 | dm_new_con_state->update_hdcp = true; |
0c8620d6 BL |
8712 | continue; |
8713 | } | |
8714 | ||
e8fd3eeb | 8715 | if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, |
8716 | old_con_state, connector, adev->dm.hdcp_workqueue)) { | |
82986fd6 | 8717 | /* when display is unplugged from mst hub, connctor will |
8718 | * be destroyed within dm_dp_mst_connector_destroy. connector | |
8719 | * hdcp perperties, like type, undesired, desired, enabled, | |
8720 | * will be lost. So, save hdcp properties into hdcp_work within | |
8721 | * amdgpu_dm_atomic_commit_tail. if the same display is | |
8722 | * plugged back with same display index, its hdcp properties | |
8723 | * will be retrieved from hdcp_work within dm_dp_mst_get_modes | |
8724 | */ | |
8725 | ||
e8fd3eeb | 8726 | bool enable_encryption = false; |
8727 | ||
8728 | if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) | |
8729 | enable_encryption = true; | |
8730 | ||
82986fd6 | 8731 | if (aconnector->dc_link && aconnector->dc_sink && |
8732 | aconnector->dc_link->type == dc_connection_mst_branch) { | |
8733 | struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; | |
8734 | struct hdcp_workqueue *hdcp_w = | |
8735 | &hdcp_work[aconnector->dc_link->link_index]; | |
8736 | ||
8737 | hdcp_w->hdcp_content_type[connector->index] = | |
8738 | new_con_state->hdcp_content_type; | |
8739 | hdcp_w->content_protection[connector->index] = | |
8740 | new_con_state->content_protection; | |
8741 | } | |
8742 | ||
e8fd3eeb | 8743 | if (new_crtc_state && new_crtc_state->mode_changed && |
8744 | new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) | |
8745 | enable_encryption = true; | |
8746 | ||
8747 | DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); | |
8748 | ||
b1abe558 BL |
8749 | hdcp_update_display( |
8750 | adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, | |
e8fd3eeb | 8751 | new_con_state->hdcp_content_type, enable_encryption); |
8752 | } | |
0c8620d6 | 8753 | } |
e7b07cee | 8754 | |
02d6a6fc | 8755 | /* Handle connector state changes */ |
c2cea706 | 8756 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
8757 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
8758 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); | |
8759 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
efc8278e | 8760 | struct dc_surface_update dummy_updates[MAX_SURFACES]; |
19afd799 | 8761 | struct dc_stream_update stream_update; |
b232d4ed | 8762 | struct dc_info_packet hdr_packet; |
e7b07cee | 8763 | struct dc_stream_status *status = NULL; |
b232d4ed | 8764 | bool abm_changed, hdr_changed, scaling_changed; |
e7b07cee | 8765 | |
efc8278e | 8766 | memset(&dummy_updates, 0, sizeof(dummy_updates)); |
19afd799 NC |
8767 | memset(&stream_update, 0, sizeof(stream_update)); |
8768 | ||
44d09c6a | 8769 | if (acrtc) { |
0bc9706d | 8770 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
44d09c6a HW |
8771 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
8772 | } | |
0bc9706d | 8773 | |
e7b07cee | 8774 | /* Skip any modesets/resets */ |
0bc9706d | 8775 | if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) |
e7b07cee HW |
8776 | continue; |
8777 | ||
54d76575 | 8778 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
c1ee92f9 DF |
8779 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
8780 | ||
b232d4ed NK |
8781 | scaling_changed = is_scaling_state_different(dm_new_con_state, |
8782 | dm_old_con_state); | |
8783 | ||
8784 | abm_changed = dm_new_crtc_state->abm_level != | |
8785 | dm_old_crtc_state->abm_level; | |
8786 | ||
8787 | hdr_changed = | |
72921cdf | 8788 | !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); |
b232d4ed NK |
8789 | |
8790 | if (!scaling_changed && !abm_changed && !hdr_changed) | |
c1ee92f9 | 8791 | continue; |
e7b07cee | 8792 | |
b6e881c9 | 8793 | stream_update.stream = dm_new_crtc_state->stream; |
b232d4ed | 8794 | if (scaling_changed) { |
02d6a6fc | 8795 | update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, |
b6e881c9 | 8796 | dm_new_con_state, dm_new_crtc_state->stream); |
e7b07cee | 8797 | |
02d6a6fc DF |
8798 | stream_update.src = dm_new_crtc_state->stream->src; |
8799 | stream_update.dst = dm_new_crtc_state->stream->dst; | |
8800 | } | |
8801 | ||
b232d4ed | 8802 | if (abm_changed) { |
02d6a6fc DF |
8803 | dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; |
8804 | ||
8805 | stream_update.abm_level = &dm_new_crtc_state->abm_level; | |
8806 | } | |
70e8ffc5 | 8807 | |
b232d4ed NK |
8808 | if (hdr_changed) { |
8809 | fill_hdr_info_packet(new_con_state, &hdr_packet); | |
8810 | stream_update.hdr_static_metadata = &hdr_packet; | |
8811 | } | |
8812 | ||
54d76575 | 8813 | status = dc_stream_get_status(dm_new_crtc_state->stream); |
57738ae4 ND |
8814 | |
8815 | if (WARN_ON(!status)) | |
8816 | continue; | |
8817 | ||
3be5262e | 8818 | WARN_ON(!status->plane_count); |
e7b07cee | 8819 | |
02d6a6fc DF |
8820 | /* |
8821 | * TODO: DC refuses to perform stream updates without a dc_surface_update. | |
8822 | * Here we create an empty update on each plane. | |
8823 | * To fix this, DC should permit updating only stream properties. | |
8824 | */ | |
8825 | for (j = 0; j < status->plane_count; j++) | |
efc8278e | 8826 | dummy_updates[j].surface = status->plane_states[0]; |
02d6a6fc DF |
8827 | |
8828 | ||
8829 | mutex_lock(&dm->dc_lock); | |
f7511289 RS |
8830 | dc_update_planes_and_stream(dm->dc, |
8831 | dummy_updates, | |
8832 | status->plane_count, | |
8833 | dm_new_crtc_state->stream, | |
8834 | &stream_update); | |
02d6a6fc | 8835 | mutex_unlock(&dm->dc_lock); |
e7b07cee HW |
8836 | } |
8837 | ||
8fe684e9 NK |
8838 | /** |
8839 | * Enable interrupts for CRTCs that are newly enabled or went through | |
8840 | * a modeset. It was intentionally deferred until after the front end | |
8841 | * state was modified to wait until the OTG was on and so the IRQ | |
8842 | * handlers didn't access stale or invalid state. | |
8843 | */ | |
8844 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { | |
8845 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); | |
8e7b6fee WL |
8846 | #ifdef CONFIG_DEBUG_FS |
8847 | enum amdgpu_dm_pipe_crc_source cur_crc_src; | |
8799c0be YL |
8848 | #endif |
8849 | /* Count number of newly disabled CRTCs for dropping PM refs later. */ | |
8850 | if (old_crtc_state->active && !new_crtc_state->active) | |
8851 | crtc_disable_count++; | |
8852 | ||
8853 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
8854 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
8855 | ||
8856 | /* For freesync config update on crtc state and params for irq */ | |
8857 | update_stream_irq_parameters(dm, dm_new_crtc_state); | |
8858 | ||
8859 | #ifdef CONFIG_DEBUG_FS | |
d98af272 WL |
8860 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
8861 | cur_crc_src = acrtc->dm_irq_params.crc_src; | |
8862 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); | |
8e7b6fee | 8863 | #endif |
585d450c | 8864 | |
8fe684e9 NK |
8865 | if (new_crtc_state->active && |
8866 | (!old_crtc_state->active || | |
8867 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
585d450c AP |
8868 | dc_stream_retain(dm_new_crtc_state->stream); |
8869 | acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; | |
8fe684e9 | 8870 | manage_dm_interrupts(adev, acrtc, true); |
8799c0be YL |
8871 | } |
8872 | /* Handle vrr on->off / off->on transitions */ | |
8873 | amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); | |
e2881d6d | 8874 | |
24eb9374 | 8875 | #ifdef CONFIG_DEBUG_FS |
8799c0be YL |
8876 | if (new_crtc_state->active && |
8877 | (!old_crtc_state->active || | |
8878 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
8fe684e9 NK |
8879 | /** |
8880 | * Frontend may have changed so reapply the CRC capture | |
8881 | * settings for the stream. | |
8882 | */ | |
8e7b6fee | 8883 | if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { |
86bc2219 | 8884 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
d98af272 WL |
8885 | if (amdgpu_dm_crc_window_is_activated(crtc)) { |
8886 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); | |
c0459bdd | 8887 | acrtc->dm_irq_params.window_param.update_win = true; |
1b11ff76 AL |
8888 | |
8889 | /** | |
8890 | * It takes 2 frames for HW to stably generate CRC when | |
8891 | * resuming from suspend, so we set skip_frame_cnt 2. | |
8892 | */ | |
c0459bdd | 8893 | acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; |
d98af272 WL |
8894 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
8895 | } | |
86bc2219 | 8896 | #endif |
bbc49fc0 WL |
8897 | if (amdgpu_dm_crtc_configure_crc_source( |
8898 | crtc, dm_new_crtc_state, cur_crc_src)) | |
8899 | DRM_DEBUG_DRIVER("Failed to configure crc source"); | |
8799c0be | 8900 | } |
8fe684e9 | 8901 | } |
2130b87b | 8902 | #endif |
8fe684e9 | 8903 | } |
e7b07cee | 8904 | |
420cd472 | 8905 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) |
4d85f45c | 8906 | if (new_crtc_state->async_flip) |
420cd472 DF |
8907 | wait_for_vblank = false; |
8908 | ||
e7b07cee | 8909 | /* update planes when needed per crtc*/ |
5cc6dcbd | 8910 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { |
54d76575 | 8911 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 8912 | |
54d76575 | 8913 | if (dm_new_crtc_state->stream) |
eb3dc897 | 8914 | amdgpu_dm_commit_planes(state, dc_state, dev, |
420cd472 | 8915 | dm, crtc, wait_for_vblank); |
e7b07cee HW |
8916 | } |
8917 | ||
6ce8f316 NK |
8918 | /* Update audio instances for each connector. */ |
8919 | amdgpu_dm_commit_audio(dev, state); | |
8920 | ||
7230362c | 8921 | /* restore the backlight level */ |
7fd13bae AD |
8922 | for (i = 0; i < dm->num_of_edps; i++) { |
8923 | if (dm->backlight_dev[i] && | |
4052287a | 8924 | (dm->actual_brightness[i] != dm->brightness[i])) |
7fd13bae AD |
8925 | amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); |
8926 | } | |
83a3439d | 8927 | |
e7b07cee HW |
8928 | /* |
8929 | * send vblank event on all events not handled in flip and | |
8930 | * mark consumed event for drm_atomic_helper_commit_hw_done | |
8931 | */ | |
4a580877 | 8932 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
0bc9706d | 8933 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 8934 | |
0bc9706d LSL |
8935 | if (new_crtc_state->event) |
8936 | drm_send_event_locked(dev, &new_crtc_state->event->base); | |
e7b07cee | 8937 | |
0bc9706d | 8938 | new_crtc_state->event = NULL; |
e7b07cee | 8939 | } |
4a580877 | 8940 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
e7b07cee | 8941 | |
29c8f234 LL |
8942 | /* Signal HW programming completion */ |
8943 | drm_atomic_helper_commit_hw_done(state); | |
e7b07cee HW |
8944 | |
8945 | if (wait_for_vblank) | |
320a1274 | 8946 | drm_atomic_helper_wait_for_flip_done(dev, state); |
e7b07cee HW |
8947 | |
8948 | drm_atomic_helper_cleanup_planes(dev, state); | |
97028037 | 8949 | |
e6b27cf5 AD |
8950 | /* Don't free the memory if we are hitting this as part of suspend. |
8951 | * This way we don't free any memory during suspend; see | |
8952 | * amdgpu_bo_free_kernel(). The memory will be freed in the first | |
8953 | * non-suspend modeset or when the driver is torn down. | |
8954 | */ | |
8955 | if (!adev->in_suspend) { | |
8956 | /* return the stolen vga memory back to VRAM */ | |
8957 | if (!adev->mman.keep_stolen_vga_memory) | |
8958 | amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); | |
8959 | amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); | |
8960 | } | |
5f6fab24 | 8961 | |
1f6010a9 DF |
8962 | /* |
8963 | * Finally, drop a runtime PM reference for each newly disabled CRTC, | |
97028037 LP |
8964 | * so we can put the GPU into runtime suspend if we're not driving any |
8965 | * displays anymore | |
8966 | */ | |
fe2a1965 LP |
8967 | for (i = 0; i < crtc_disable_count; i++) |
8968 | pm_runtime_put_autosuspend(dev->dev); | |
97028037 | 8969 | pm_runtime_mark_last_busy(dev->dev); |
eb3dc897 NK |
8970 | |
8971 | if (dc_state_temp) | |
8972 | dc_release_state(dc_state_temp); | |
e7b07cee HW |
8973 | } |
8974 | ||
e7b07cee HW |
8975 | static int dm_force_atomic_commit(struct drm_connector *connector) |
8976 | { | |
8977 | int ret = 0; | |
8978 | struct drm_device *ddev = connector->dev; | |
8979 | struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); | |
8980 | struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
8981 | struct drm_plane *plane = disconnected_acrtc->base.primary; | |
8982 | struct drm_connector_state *conn_state; | |
8983 | struct drm_crtc_state *crtc_state; | |
8984 | struct drm_plane_state *plane_state; | |
8985 | ||
8986 | if (!state) | |
8987 | return -ENOMEM; | |
8988 | ||
8989 | state->acquire_ctx = ddev->mode_config.acquire_ctx; | |
8990 | ||
8991 | /* Construct an atomic state to restore previous display setting */ | |
8992 | ||
8993 | /* | |
8994 | * Attach connectors to drm_atomic_state | |
8995 | */ | |
8996 | conn_state = drm_atomic_get_connector_state(state, connector); | |
8997 | ||
8998 | ret = PTR_ERR_OR_ZERO(conn_state); | |
8999 | if (ret) | |
2dc39051 | 9000 | goto out; |
e7b07cee HW |
9001 | |
9002 | /* Attach crtc to drm_atomic_state*/ | |
9003 | crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); | |
9004 | ||
9005 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
9006 | if (ret) | |
2dc39051 | 9007 | goto out; |
e7b07cee HW |
9008 | |
9009 | /* force a restore */ | |
9010 | crtc_state->mode_changed = true; | |
9011 | ||
9012 | /* Attach plane to drm_atomic_state */ | |
9013 | plane_state = drm_atomic_get_plane_state(state, plane); | |
9014 | ||
9015 | ret = PTR_ERR_OR_ZERO(plane_state); | |
9016 | if (ret) | |
2dc39051 | 9017 | goto out; |
e7b07cee HW |
9018 | |
9019 | /* Call commit internally with the state we just constructed */ | |
9020 | ret = drm_atomic_commit(state); | |
e7b07cee | 9021 | |
2dc39051 | 9022 | out: |
e7b07cee | 9023 | drm_atomic_state_put(state); |
2dc39051 VL |
9024 | if (ret) |
9025 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
e7b07cee HW |
9026 | |
9027 | return ret; | |
9028 | } | |
9029 | ||
9030 | /* | |
1f6010a9 DF |
9031 | * This function handles all cases when set mode does not come upon hotplug. |
9032 | * This includes when a display is unplugged then plugged back into the | |
9033 | * same port and when running without usermode desktop manager supprot | |
e7b07cee | 9034 | */ |
3ee6b26b AD |
9035 | void dm_restore_drm_connector_state(struct drm_device *dev, |
9036 | struct drm_connector *connector) | |
e7b07cee | 9037 | { |
c84dec2f | 9038 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
9039 | struct amdgpu_crtc *disconnected_acrtc; |
9040 | struct dm_crtc_state *acrtc_state; | |
9041 | ||
9042 | if (!aconnector->dc_sink || !connector->state || !connector->encoder) | |
9043 | return; | |
9044 | ||
9045 | disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
70e8ffc5 HW |
9046 | if (!disconnected_acrtc) |
9047 | return; | |
e7b07cee | 9048 | |
70e8ffc5 HW |
9049 | acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); |
9050 | if (!acrtc_state->stream) | |
e7b07cee HW |
9051 | return; |
9052 | ||
9053 | /* | |
9054 | * If the previous sink is not released and different from the current, | |
9055 | * we deduce we are in a state where we can not rely on usermode call | |
9056 | * to turn on the display, so we do it here | |
9057 | */ | |
9058 | if (acrtc_state->stream->sink != aconnector->dc_sink) | |
9059 | dm_force_atomic_commit(&aconnector->base); | |
9060 | } | |
9061 | ||
1f6010a9 | 9062 | /* |
e7b07cee HW |
9063 | * Grabs all modesetting locks to serialize against any blocking commits, |
9064 | * Waits for completion of all non blocking commits. | |
9065 | */ | |
3ee6b26b AD |
9066 | static int do_aquire_global_lock(struct drm_device *dev, |
9067 | struct drm_atomic_state *state) | |
e7b07cee HW |
9068 | { |
9069 | struct drm_crtc *crtc; | |
9070 | struct drm_crtc_commit *commit; | |
9071 | long ret; | |
9072 | ||
1f6010a9 DF |
9073 | /* |
9074 | * Adding all modeset locks to aquire_ctx will | |
e7b07cee HW |
9075 | * ensure that when the framework release it the |
9076 | * extra locks we are locking here will get released to | |
9077 | */ | |
9078 | ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); | |
9079 | if (ret) | |
9080 | return ret; | |
9081 | ||
9082 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9083 | spin_lock(&crtc->commit_lock); | |
9084 | commit = list_first_entry_or_null(&crtc->commit_list, | |
9085 | struct drm_crtc_commit, commit_entry); | |
9086 | if (commit) | |
9087 | drm_crtc_commit_get(commit); | |
9088 | spin_unlock(&crtc->commit_lock); | |
9089 | ||
9090 | if (!commit) | |
9091 | continue; | |
9092 | ||
1f6010a9 DF |
9093 | /* |
9094 | * Make sure all pending HW programming completed and | |
e7b07cee HW |
9095 | * page flips done |
9096 | */ | |
9097 | ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); | |
9098 | ||
9099 | if (ret > 0) | |
9100 | ret = wait_for_completion_interruptible_timeout( | |
9101 | &commit->flip_done, 10*HZ); | |
9102 | ||
9103 | if (ret == 0) | |
c82eddf8 SS |
9104 | DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", |
9105 | crtc->base.id, crtc->name); | |
e7b07cee HW |
9106 | |
9107 | drm_crtc_commit_put(commit); | |
9108 | } | |
9109 | ||
9110 | return ret < 0 ? ret : 0; | |
9111 | } | |
9112 | ||
bb47de73 NK |
9113 | static void get_freesync_config_for_crtc( |
9114 | struct dm_crtc_state *new_crtc_state, | |
9115 | struct dm_connector_state *new_con_state) | |
98e6436d AK |
9116 | { |
9117 | struct mod_freesync_config config = {0}; | |
98e6436d AK |
9118 | struct amdgpu_dm_connector *aconnector = |
9119 | to_amdgpu_dm_connector(new_con_state->base.connector); | |
a057ec46 | 9120 | struct drm_display_mode *mode = &new_crtc_state->base.mode; |
0ab925d3 | 9121 | int vrefresh = drm_mode_vrefresh(mode); |
a85ba005 | 9122 | bool fs_vid_mode = false; |
98e6436d | 9123 | |
a057ec46 | 9124 | new_crtc_state->vrr_supported = new_con_state->freesync_capable && |
0ab925d3 NK |
9125 | vrefresh >= aconnector->min_vfreq && |
9126 | vrefresh <= aconnector->max_vfreq; | |
bb47de73 | 9127 | |
6ffa6799 | 9128 | if (new_crtc_state->vrr_supported) { |
7e5098ab | 9129 | new_crtc_state->stream->ignore_msa_timing_param = true; |
6ffa6799 | 9130 | fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; |
7e5098ab | 9131 | |
a85ba005 NC |
9132 | config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; |
9133 | config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; | |
69ff8845 | 9134 | config.vsif_supported = true; |
180db303 | 9135 | config.btr = true; |
98e6436d | 9136 | |
a85ba005 NC |
9137 | if (fs_vid_mode) { |
9138 | config.state = VRR_STATE_ACTIVE_FIXED; | |
9139 | config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; | |
9140 | goto out; | |
9141 | } else if (new_crtc_state->base.vrr_enabled) { | |
9142 | config.state = VRR_STATE_ACTIVE_VARIABLE; | |
9143 | } else { | |
9144 | config.state = VRR_STATE_INACTIVE; | |
9145 | } | |
9146 | } | |
9147 | out: | |
bb47de73 NK |
9148 | new_crtc_state->freesync_config = config; |
9149 | } | |
98e6436d | 9150 | |
bb47de73 NK |
9151 | static void reset_freesync_config_for_crtc( |
9152 | struct dm_crtc_state *new_crtc_state) | |
9153 | { | |
9154 | new_crtc_state->vrr_supported = false; | |
98e6436d | 9155 | |
bb47de73 NK |
9156 | memset(&new_crtc_state->vrr_infopacket, 0, |
9157 | sizeof(new_crtc_state->vrr_infopacket)); | |
98e6436d AK |
9158 | } |
9159 | ||
a85ba005 NC |
9160 | static bool |
9161 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, | |
9162 | struct drm_crtc_state *new_crtc_state) | |
9163 | { | |
1cbd7887 | 9164 | const struct drm_display_mode *old_mode, *new_mode; |
a85ba005 NC |
9165 | |
9166 | if (!old_crtc_state || !new_crtc_state) | |
9167 | return false; | |
9168 | ||
1cbd7887 VS |
9169 | old_mode = &old_crtc_state->mode; |
9170 | new_mode = &new_crtc_state->mode; | |
9171 | ||
9172 | if (old_mode->clock == new_mode->clock && | |
9173 | old_mode->hdisplay == new_mode->hdisplay && | |
9174 | old_mode->vdisplay == new_mode->vdisplay && | |
9175 | old_mode->htotal == new_mode->htotal && | |
9176 | old_mode->vtotal != new_mode->vtotal && | |
9177 | old_mode->hsync_start == new_mode->hsync_start && | |
9178 | old_mode->vsync_start != new_mode->vsync_start && | |
9179 | old_mode->hsync_end == new_mode->hsync_end && | |
9180 | old_mode->vsync_end != new_mode->vsync_end && | |
9181 | old_mode->hskew == new_mode->hskew && | |
9182 | old_mode->vscan == new_mode->vscan && | |
9183 | (old_mode->vsync_end - old_mode->vsync_start) == | |
9184 | (new_mode->vsync_end - new_mode->vsync_start)) | |
a85ba005 NC |
9185 | return true; |
9186 | ||
9187 | return false; | |
9188 | } | |
9189 | ||
c82eddf8 SS |
9190 | static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) |
9191 | { | |
ae67558b | 9192 | u64 num, den, res; |
a85ba005 NC |
9193 | struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; |
9194 | ||
9195 | dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; | |
9196 | ||
9197 | num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; | |
9198 | den = (unsigned long long)new_crtc_state->mode.htotal * | |
9199 | (unsigned long long)new_crtc_state->mode.vtotal; | |
9200 | ||
9201 | res = div_u64(num, den); | |
9202 | dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; | |
9203 | } | |
9204 | ||
f11d9373 | 9205 | static int dm_update_crtc_state(struct amdgpu_display_manager *dm, |
17ce8a69 RL |
9206 | struct drm_atomic_state *state, |
9207 | struct drm_crtc *crtc, | |
9208 | struct drm_crtc_state *old_crtc_state, | |
9209 | struct drm_crtc_state *new_crtc_state, | |
9210 | bool enable, | |
9211 | bool *lock_and_validation_needed) | |
e7b07cee | 9212 | { |
eb3dc897 | 9213 | struct dm_atomic_state *dm_state = NULL; |
54d76575 | 9214 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
9635b754 | 9215 | struct dc_stream_state *new_stream; |
62f55537 | 9216 | int ret = 0; |
d4d4a645 | 9217 | |
1f6010a9 DF |
9218 | /* |
9219 | * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set | |
9220 | * update changed items | |
9221 | */ | |
4b9674e5 LL |
9222 | struct amdgpu_crtc *acrtc = NULL; |
9223 | struct amdgpu_dm_connector *aconnector = NULL; | |
9224 | struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; | |
9225 | struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; | |
e7b07cee | 9226 | |
4b9674e5 | 9227 | new_stream = NULL; |
9635b754 | 9228 | |
4b9674e5 LL |
9229 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
9230 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
9231 | acrtc = to_amdgpu_crtc(crtc); | |
4b9674e5 | 9232 | aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); |
19f89e23 | 9233 | |
4b9674e5 LL |
9234 | /* TODO This hack should go away */ |
9235 | if (aconnector && enable) { | |
9236 | /* Make sure fake sink is created in plug-in scenario */ | |
9237 | drm_new_conn_state = drm_atomic_get_new_connector_state(state, | |
9238 | &aconnector->base); | |
9239 | drm_old_conn_state = drm_atomic_get_old_connector_state(state, | |
9240 | &aconnector->base); | |
19f89e23 | 9241 | |
4b9674e5 LL |
9242 | if (IS_ERR(drm_new_conn_state)) { |
9243 | ret = PTR_ERR_OR_ZERO(drm_new_conn_state); | |
9244 | goto fail; | |
9245 | } | |
19f89e23 | 9246 | |
4b9674e5 LL |
9247 | dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); |
9248 | dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); | |
19f89e23 | 9249 | |
02d35a67 JFZ |
9250 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9251 | goto skip_modeset; | |
9252 | ||
cbd14ae7 SW |
9253 | new_stream = create_validate_stream_for_sink(aconnector, |
9254 | &new_crtc_state->mode, | |
9255 | dm_new_conn_state, | |
9256 | dm_old_crtc_state->stream); | |
19f89e23 | 9257 | |
4b9674e5 LL |
9258 | /* |
9259 | * we can have no stream on ACTION_SET if a display | |
9260 | * was disconnected during S3, in this case it is not an | |
9261 | * error, the OS will be updated after detection, and | |
9262 | * will do the right thing on next atomic commit | |
9263 | */ | |
19f89e23 | 9264 | |
4b9674e5 LL |
9265 | if (!new_stream) { |
9266 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", | |
9267 | __func__, acrtc->base.base.id); | |
9268 | ret = -ENOMEM; | |
9269 | goto fail; | |
9270 | } | |
e7b07cee | 9271 | |
3d4e52d0 VL |
9272 | /* |
9273 | * TODO: Check VSDB bits to decide whether this should | |
9274 | * be enabled or not. | |
9275 | */ | |
9276 | new_stream->triggered_crtc_reset.enabled = | |
9277 | dm->force_timing_sync; | |
9278 | ||
4b9674e5 | 9279 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; |
98e6436d | 9280 | |
88694af9 NK |
9281 | ret = fill_hdr_info_packet(drm_new_conn_state, |
9282 | &new_stream->hdr_static_metadata); | |
9283 | if (ret) | |
9284 | goto fail; | |
9285 | ||
7e930949 NK |
9286 | /* |
9287 | * If we already removed the old stream from the context | |
9288 | * (and set the new stream to NULL) then we can't reuse | |
9289 | * the old stream even if the stream and scaling are unchanged. | |
9290 | * We'll hit the BUG_ON and black screen. | |
9291 | * | |
9292 | * TODO: Refactor this function to allow this check to work | |
9293 | * in all conditions. | |
9294 | */ | |
11b92df8 | 9295 | if (dm_new_crtc_state->stream && |
a85ba005 NC |
9296 | is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) |
9297 | goto skip_modeset; | |
9298 | ||
7e930949 NK |
9299 | if (dm_new_crtc_state->stream && |
9300 | dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && | |
4b9674e5 LL |
9301 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { |
9302 | new_crtc_state->mode_changed = false; | |
9303 | DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", | |
9304 | new_crtc_state->mode_changed); | |
62f55537 | 9305 | } |
4b9674e5 | 9306 | } |
b830ebc9 | 9307 | |
02d35a67 | 9308 | /* mode_changed flag may get updated above, need to check again */ |
4b9674e5 LL |
9309 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9310 | goto skip_modeset; | |
e7b07cee | 9311 | |
9f07550b | 9312 | drm_dbg_state(state->dev, |
c82eddf8 | 9313 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", |
4b9674e5 LL |
9314 | acrtc->crtc_id, |
9315 | new_crtc_state->enable, | |
9316 | new_crtc_state->active, | |
9317 | new_crtc_state->planes_changed, | |
9318 | new_crtc_state->mode_changed, | |
9319 | new_crtc_state->active_changed, | |
9320 | new_crtc_state->connectors_changed); | |
62f55537 | 9321 | |
4b9674e5 LL |
9322 | /* Remove stream for any changed/disabled CRTC */ |
9323 | if (!enable) { | |
62f55537 | 9324 | |
4b9674e5 LL |
9325 | if (!dm_old_crtc_state->stream) |
9326 | goto skip_modeset; | |
eb3dc897 | 9327 | |
0f5f1ee4 AP |
9328 | /* Unset freesync video if it was active before */ |
9329 | if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { | |
9330 | dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; | |
9331 | dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; | |
9332 | } | |
9333 | ||
9334 | /* Now check if we should set freesync video mode */ | |
11b92df8 | 9335 | if (dm_new_crtc_state->stream && |
b18f05a0 AP |
9336 | dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && |
9337 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && | |
a85ba005 NC |
9338 | is_timing_unchanged_for_freesync(new_crtc_state, |
9339 | old_crtc_state)) { | |
9340 | new_crtc_state->mode_changed = false; | |
9341 | DRM_DEBUG_DRIVER( | |
c82eddf8 | 9342 | "Mode change not required for front porch change, setting mode_changed to %d", |
a85ba005 NC |
9343 | new_crtc_state->mode_changed); |
9344 | ||
9345 | set_freesync_fixed_config(dm_new_crtc_state); | |
9346 | ||
9347 | goto skip_modeset; | |
11b92df8 | 9348 | } else if (aconnector && |
a85ba005 NC |
9349 | is_freesync_video_mode(&new_crtc_state->mode, |
9350 | aconnector)) { | |
e88ebd83 SC |
9351 | struct drm_display_mode *high_mode; |
9352 | ||
9353 | high_mode = get_highest_refresh_rate_mode(aconnector, false); | |
c82eddf8 | 9354 | if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) |
e88ebd83 | 9355 | set_freesync_fixed_config(dm_new_crtc_state); |
a85ba005 NC |
9356 | } |
9357 | ||
4b9674e5 LL |
9358 | ret = dm_atomic_get_state(state, &dm_state); |
9359 | if (ret) | |
9360 | goto fail; | |
e7b07cee | 9361 | |
4b9674e5 LL |
9362 | DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", |
9363 | crtc->base.id); | |
62f55537 | 9364 | |
4b9674e5 LL |
9365 | /* i.e. reset mode */ |
9366 | if (dc_remove_stream_from_ctx( | |
9367 | dm->dc, | |
9368 | dm_state->context, | |
9369 | dm_old_crtc_state->stream) != DC_OK) { | |
9370 | ret = -EINVAL; | |
9371 | goto fail; | |
9372 | } | |
62f55537 | 9373 | |
4b9674e5 LL |
9374 | dc_stream_release(dm_old_crtc_state->stream); |
9375 | dm_new_crtc_state->stream = NULL; | |
bb47de73 | 9376 | |
4b9674e5 | 9377 | reset_freesync_config_for_crtc(dm_new_crtc_state); |
62f55537 | 9378 | |
4b9674e5 | 9379 | *lock_and_validation_needed = true; |
62f55537 | 9380 | |
4b9674e5 LL |
9381 | } else {/* Add stream for any updated/enabled CRTC */ |
9382 | /* | |
9383 | * Quick fix to prevent NULL pointer on new_stream when | |
9384 | * added MST connectors not found in existing crtc_state in the chained mode | |
9385 | * TODO: need to dig out the root cause of that | |
9386 | */ | |
84a8b390 | 9387 | if (!aconnector) |
4b9674e5 | 9388 | goto skip_modeset; |
62f55537 | 9389 | |
4b9674e5 LL |
9390 | if (modereset_required(new_crtc_state)) |
9391 | goto skip_modeset; | |
62f55537 | 9392 | |
6c5e25a0 | 9393 | if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, |
4b9674e5 | 9394 | dm_old_crtc_state->stream)) { |
62f55537 | 9395 | |
4b9674e5 | 9396 | WARN_ON(dm_new_crtc_state->stream); |
eb3dc897 | 9397 | |
4b9674e5 LL |
9398 | ret = dm_atomic_get_state(state, &dm_state); |
9399 | if (ret) | |
9400 | goto fail; | |
27b3f4fc | 9401 | |
4b9674e5 | 9402 | dm_new_crtc_state->stream = new_stream; |
62f55537 | 9403 | |
4b9674e5 | 9404 | dc_stream_retain(new_stream); |
1dc90497 | 9405 | |
4711c033 LT |
9406 | DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", |
9407 | crtc->base.id); | |
1dc90497 | 9408 | |
4b9674e5 LL |
9409 | if (dc_add_stream_to_ctx( |
9410 | dm->dc, | |
9411 | dm_state->context, | |
9412 | dm_new_crtc_state->stream) != DC_OK) { | |
9413 | ret = -EINVAL; | |
9414 | goto fail; | |
9b690ef3 BL |
9415 | } |
9416 | ||
4b9674e5 LL |
9417 | *lock_and_validation_needed = true; |
9418 | } | |
9419 | } | |
e277adc5 | 9420 | |
4b9674e5 LL |
9421 | skip_modeset: |
9422 | /* Release extra reference */ | |
9423 | if (new_stream) | |
3335a135 | 9424 | dc_stream_release(new_stream); |
e277adc5 | 9425 | |
4b9674e5 LL |
9426 | /* |
9427 | * We want to do dc stream updates that do not require a | |
9428 | * full modeset below. | |
9429 | */ | |
2afda735 | 9430 | if (!(enable && aconnector && new_crtc_state->active)) |
4b9674e5 LL |
9431 | return 0; |
9432 | /* | |
9433 | * Given above conditions, the dc state cannot be NULL because: | |
9434 | * 1. We're in the process of enabling CRTCs (just been added | |
9435 | * to the dc context, or already is on the context) | |
9436 | * 2. Has a valid connector attached, and | |
9437 | * 3. Is currently active and enabled. | |
9438 | * => The dc stream state currently exists. | |
9439 | */ | |
9440 | BUG_ON(dm_new_crtc_state->stream == NULL); | |
a9e8d275 | 9441 | |
4b9674e5 | 9442 | /* Scaling or underscan settings */ |
c521fc31 RL |
9443 | if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || |
9444 | drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
4b9674e5 LL |
9445 | update_stream_scaling_settings( |
9446 | &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); | |
98e6436d | 9447 | |
b05e2c5e DF |
9448 | /* ABM settings */ |
9449 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; | |
9450 | ||
4b9674e5 LL |
9451 | /* |
9452 | * Color management settings. We also update color properties | |
9453 | * when a modeset is needed, to ensure it gets reprogrammed. | |
9454 | */ | |
9455 | if (dm_new_crtc_state->base.color_mgmt_changed || | |
9456 | drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
cf020d49 | 9457 | ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); |
4b9674e5 LL |
9458 | if (ret) |
9459 | goto fail; | |
62f55537 | 9460 | } |
e7b07cee | 9461 | |
4b9674e5 LL |
9462 | /* Update Freesync settings. */ |
9463 | get_freesync_config_for_crtc(dm_new_crtc_state, | |
9464 | dm_new_conn_state); | |
9465 | ||
62f55537 | 9466 | return ret; |
9635b754 DS |
9467 | |
9468 | fail: | |
9469 | if (new_stream) | |
9470 | dc_stream_release(new_stream); | |
9471 | return ret; | |
62f55537 | 9472 | } |
9b690ef3 | 9473 | |
f6ff2a08 NK |
9474 | static bool should_reset_plane(struct drm_atomic_state *state, |
9475 | struct drm_plane *plane, | |
9476 | struct drm_plane_state *old_plane_state, | |
9477 | struct drm_plane_state *new_plane_state) | |
9478 | { | |
9479 | struct drm_plane *other; | |
9480 | struct drm_plane_state *old_other_state, *new_other_state; | |
9481 | struct drm_crtc_state *new_crtc_state; | |
9482 | int i; | |
9483 | ||
70a1efac NK |
9484 | /* |
9485 | * TODO: Remove this hack once the checks below are sufficient | |
9486 | * enough to determine when we need to reset all the planes on | |
9487 | * the stream. | |
9488 | */ | |
9489 | if (state->allow_modeset) | |
9490 | return true; | |
9491 | ||
f6ff2a08 NK |
9492 | /* Exit early if we know that we're adding or removing the plane. */ |
9493 | if (old_plane_state->crtc != new_plane_state->crtc) | |
9494 | return true; | |
9495 | ||
9496 | /* old crtc == new_crtc == NULL, plane not in context. */ | |
9497 | if (!new_plane_state->crtc) | |
9498 | return false; | |
9499 | ||
9500 | new_crtc_state = | |
9501 | drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); | |
9502 | ||
9503 | if (!new_crtc_state) | |
9504 | return true; | |
9505 | ||
7316c4ad NK |
9506 | /* CRTC Degamma changes currently require us to recreate planes. */ |
9507 | if (new_crtc_state->color_mgmt_changed) | |
9508 | return true; | |
9509 | ||
f6ff2a08 NK |
9510 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9511 | return true; | |
9512 | ||
9513 | /* | |
9514 | * If there are any new primary or overlay planes being added or | |
9515 | * removed then the z-order can potentially change. To ensure | |
9516 | * correct z-order and pipe acquisition the current DC architecture | |
9517 | * requires us to remove and recreate all existing planes. | |
9518 | * | |
9519 | * TODO: Come up with a more elegant solution for this. | |
9520 | */ | |
9521 | for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { | |
6eed95b0 | 9522 | struct amdgpu_framebuffer *old_afb, *new_afb; |
c82eddf8 | 9523 | |
f6ff2a08 NK |
9524 | if (other->type == DRM_PLANE_TYPE_CURSOR) |
9525 | continue; | |
9526 | ||
9527 | if (old_other_state->crtc != new_plane_state->crtc && | |
9528 | new_other_state->crtc != new_plane_state->crtc) | |
9529 | continue; | |
9530 | ||
9531 | if (old_other_state->crtc != new_other_state->crtc) | |
9532 | return true; | |
9533 | ||
dc4cb30d NK |
9534 | /* Src/dst size and scaling updates. */ |
9535 | if (old_other_state->src_w != new_other_state->src_w || | |
9536 | old_other_state->src_h != new_other_state->src_h || | |
9537 | old_other_state->crtc_w != new_other_state->crtc_w || | |
9538 | old_other_state->crtc_h != new_other_state->crtc_h) | |
9539 | return true; | |
9540 | ||
9541 | /* Rotation / mirroring updates. */ | |
9542 | if (old_other_state->rotation != new_other_state->rotation) | |
9543 | return true; | |
9544 | ||
9545 | /* Blending updates. */ | |
9546 | if (old_other_state->pixel_blend_mode != | |
9547 | new_other_state->pixel_blend_mode) | |
9548 | return true; | |
9549 | ||
9550 | /* Alpha updates. */ | |
9551 | if (old_other_state->alpha != new_other_state->alpha) | |
9552 | return true; | |
9553 | ||
9554 | /* Colorspace changes. */ | |
9555 | if (old_other_state->color_range != new_other_state->color_range || | |
9556 | old_other_state->color_encoding != new_other_state->color_encoding) | |
9557 | return true; | |
9558 | ||
9a81cc60 NK |
9559 | /* Framebuffer checks fall at the end. */ |
9560 | if (!old_other_state->fb || !new_other_state->fb) | |
9561 | continue; | |
9562 | ||
9563 | /* Pixel format changes can require bandwidth updates. */ | |
9564 | if (old_other_state->fb->format != new_other_state->fb->format) | |
9565 | return true; | |
9566 | ||
6eed95b0 BN |
9567 | old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; |
9568 | new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; | |
9a81cc60 NK |
9569 | |
9570 | /* Tiling and DCC changes also require bandwidth updates. */ | |
37384b3f BN |
9571 | if (old_afb->tiling_flags != new_afb->tiling_flags || |
9572 | old_afb->base.modifier != new_afb->base.modifier) | |
f6ff2a08 NK |
9573 | return true; |
9574 | } | |
9575 | ||
9576 | return false; | |
9577 | } | |
9578 | ||
b0455fda SS |
9579 | static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, |
9580 | struct drm_plane_state *new_plane_state, | |
9581 | struct drm_framebuffer *fb) | |
9582 | { | |
e72868c4 SS |
9583 | struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); |
9584 | struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); | |
b0455fda | 9585 | unsigned int pitch; |
e72868c4 | 9586 | bool linear; |
b0455fda SS |
9587 | |
9588 | if (fb->width > new_acrtc->max_cursor_width || | |
9589 | fb->height > new_acrtc->max_cursor_height) { | |
9590 | DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", | |
9591 | new_plane_state->fb->width, | |
9592 | new_plane_state->fb->height); | |
9593 | return -EINVAL; | |
9594 | } | |
9595 | if (new_plane_state->src_w != fb->width << 16 || | |
9596 | new_plane_state->src_h != fb->height << 16) { | |
9597 | DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); | |
9598 | return -EINVAL; | |
9599 | } | |
9600 | ||
9601 | /* Pitch in pixels */ | |
9602 | pitch = fb->pitches[0] / fb->format->cpp[0]; | |
9603 | ||
9604 | if (fb->width != pitch) { | |
9605 | DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", | |
9606 | fb->width, pitch); | |
9607 | return -EINVAL; | |
9608 | } | |
9609 | ||
9610 | switch (pitch) { | |
9611 | case 64: | |
9612 | case 128: | |
9613 | case 256: | |
9614 | /* FB pitch is supported by cursor plane */ | |
9615 | break; | |
9616 | default: | |
9617 | DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); | |
9618 | return -EINVAL; | |
9619 | } | |
9620 | ||
e72868c4 | 9621 | /* Core DRM takes care of checking FB modifiers, so we only need to |
c82eddf8 SS |
9622 | * check tiling flags when the FB doesn't have a modifier. |
9623 | */ | |
e72868c4 SS |
9624 | if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { |
9625 | if (adev->family < AMDGPU_FAMILY_AI) { | |
9626 | linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && | |
c82eddf8 | 9627 | AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && |
e72868c4 SS |
9628 | AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; |
9629 | } else { | |
9630 | linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; | |
9631 | } | |
9632 | if (!linear) { | |
9633 | DRM_DEBUG_ATOMIC("Cursor FB not linear"); | |
9634 | return -EINVAL; | |
9635 | } | |
9636 | } | |
9637 | ||
b0455fda SS |
9638 | return 0; |
9639 | } | |
9640 | ||
9e869063 LL |
9641 | static int dm_update_plane_state(struct dc *dc, |
9642 | struct drm_atomic_state *state, | |
9643 | struct drm_plane *plane, | |
9644 | struct drm_plane_state *old_plane_state, | |
9645 | struct drm_plane_state *new_plane_state, | |
9646 | bool enable, | |
35f33086 BL |
9647 | bool *lock_and_validation_needed, |
9648 | bool *is_top_most_overlay) | |
62f55537 | 9649 | { |
eb3dc897 NK |
9650 | |
9651 | struct dm_atomic_state *dm_state = NULL; | |
62f55537 | 9652 | struct drm_crtc *new_plane_crtc, *old_plane_crtc; |
0bc9706d | 9653 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
54d76575 | 9654 | struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; |
54d76575 | 9655 | struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; |
626bf90f | 9656 | struct amdgpu_crtc *new_acrtc; |
f6ff2a08 | 9657 | bool needs_reset; |
62f55537 | 9658 | int ret = 0; |
e7b07cee | 9659 | |
9b690ef3 | 9660 | |
9e869063 LL |
9661 | new_plane_crtc = new_plane_state->crtc; |
9662 | old_plane_crtc = old_plane_state->crtc; | |
9663 | dm_new_plane_state = to_dm_plane_state(new_plane_state); | |
9664 | dm_old_plane_state = to_dm_plane_state(old_plane_state); | |
62f55537 | 9665 | |
626bf90f SS |
9666 | if (plane->type == DRM_PLANE_TYPE_CURSOR) { |
9667 | if (!enable || !new_plane_crtc || | |
9668 | drm_atomic_plane_disabling(plane->state, new_plane_state)) | |
9669 | return 0; | |
9670 | ||
9671 | new_acrtc = to_amdgpu_crtc(new_plane_crtc); | |
9672 | ||
5f581248 SS |
9673 | if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { |
9674 | DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); | |
9675 | return -EINVAL; | |
9676 | } | |
9677 | ||
24f99d2b | 9678 | if (new_plane_state->fb) { |
b0455fda SS |
9679 | ret = dm_check_cursor_fb(new_acrtc, new_plane_state, |
9680 | new_plane_state->fb); | |
9681 | if (ret) | |
9682 | return ret; | |
24f99d2b SS |
9683 | } |
9684 | ||
9e869063 | 9685 | return 0; |
626bf90f | 9686 | } |
9b690ef3 | 9687 | |
f6ff2a08 NK |
9688 | needs_reset = should_reset_plane(state, plane, old_plane_state, |
9689 | new_plane_state); | |
9690 | ||
9e869063 LL |
9691 | /* Remove any changed/removed planes */ |
9692 | if (!enable) { | |
f6ff2a08 | 9693 | if (!needs_reset) |
9e869063 | 9694 | return 0; |
a7b06724 | 9695 | |
9e869063 LL |
9696 | if (!old_plane_crtc) |
9697 | return 0; | |
62f55537 | 9698 | |
9e869063 LL |
9699 | old_crtc_state = drm_atomic_get_old_crtc_state( |
9700 | state, old_plane_crtc); | |
9701 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
9b690ef3 | 9702 | |
9e869063 LL |
9703 | if (!dm_old_crtc_state->stream) |
9704 | return 0; | |
62f55537 | 9705 | |
9e869063 LL |
9706 | DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", |
9707 | plane->base.id, old_plane_crtc->base.id); | |
9b690ef3 | 9708 | |
9e869063 LL |
9709 | ret = dm_atomic_get_state(state, &dm_state); |
9710 | if (ret) | |
9711 | return ret; | |
eb3dc897 | 9712 | |
9e869063 LL |
9713 | if (!dc_remove_plane_from_context( |
9714 | dc, | |
9715 | dm_old_crtc_state->stream, | |
9716 | dm_old_plane_state->dc_state, | |
9717 | dm_state->context)) { | |
62f55537 | 9718 | |
c3537613 | 9719 | return -EINVAL; |
9e869063 | 9720 | } |
e7b07cee | 9721 | |
da5e1490 AP |
9722 | if (dm_old_plane_state->dc_state) |
9723 | dc_plane_state_release(dm_old_plane_state->dc_state); | |
9b690ef3 | 9724 | |
9e869063 | 9725 | dm_new_plane_state->dc_state = NULL; |
1dc90497 | 9726 | |
9e869063 | 9727 | *lock_and_validation_needed = true; |
1dc90497 | 9728 | |
9e869063 LL |
9729 | } else { /* Add new planes */ |
9730 | struct dc_plane_state *dc_new_plane_state; | |
1dc90497 | 9731 | |
9e869063 LL |
9732 | if (drm_atomic_plane_disabling(plane->state, new_plane_state)) |
9733 | return 0; | |
e7b07cee | 9734 | |
9e869063 LL |
9735 | if (!new_plane_crtc) |
9736 | return 0; | |
e7b07cee | 9737 | |
9e869063 LL |
9738 | new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); |
9739 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
1dc90497 | 9740 | |
9e869063 LL |
9741 | if (!dm_new_crtc_state->stream) |
9742 | return 0; | |
62f55537 | 9743 | |
f6ff2a08 | 9744 | if (!needs_reset) |
9e869063 | 9745 | return 0; |
62f55537 | 9746 | |
8bf0d9cd | 9747 | ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); |
8c44515b AP |
9748 | if (ret) |
9749 | return ret; | |
9750 | ||
9e869063 | 9751 | WARN_ON(dm_new_plane_state->dc_state); |
9b690ef3 | 9752 | |
9e869063 LL |
9753 | dc_new_plane_state = dc_create_plane_state(dc); |
9754 | if (!dc_new_plane_state) | |
9755 | return -ENOMEM; | |
62f55537 | 9756 | |
35f33086 BL |
9757 | /* Block top most plane from being a video plane */ |
9758 | if (plane->type == DRM_PLANE_TYPE_OVERLAY) { | |
9759 | if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay) | |
9760 | return -EINVAL; | |
44a4f50d SS |
9761 | |
9762 | *is_top_most_overlay = false; | |
35f33086 BL |
9763 | } |
9764 | ||
4711c033 LT |
9765 | DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", |
9766 | plane->base.id, new_plane_crtc->base.id); | |
8c45c5db | 9767 | |
695af5f9 | 9768 | ret = fill_dc_plane_attributes( |
1348969a | 9769 | drm_to_adev(new_plane_crtc->dev), |
9e869063 LL |
9770 | dc_new_plane_state, |
9771 | new_plane_state, | |
9772 | new_crtc_state); | |
9773 | if (ret) { | |
9774 | dc_plane_state_release(dc_new_plane_state); | |
9775 | return ret; | |
9776 | } | |
62f55537 | 9777 | |
9e869063 LL |
9778 | ret = dm_atomic_get_state(state, &dm_state); |
9779 | if (ret) { | |
9780 | dc_plane_state_release(dc_new_plane_state); | |
9781 | return ret; | |
9782 | } | |
eb3dc897 | 9783 | |
9e869063 LL |
9784 | /* |
9785 | * Any atomic check errors that occur after this will | |
9786 | * not need a release. The plane state will be attached | |
9787 | * to the stream, and therefore part of the atomic | |
9788 | * state. It'll be released when the atomic state is | |
9789 | * cleaned. | |
9790 | */ | |
9791 | if (!dc_add_plane_to_context( | |
9792 | dc, | |
9793 | dm_new_crtc_state->stream, | |
9794 | dc_new_plane_state, | |
9795 | dm_state->context)) { | |
62f55537 | 9796 | |
9e869063 LL |
9797 | dc_plane_state_release(dc_new_plane_state); |
9798 | return -EINVAL; | |
9799 | } | |
8c45c5db | 9800 | |
9e869063 | 9801 | dm_new_plane_state->dc_state = dc_new_plane_state; |
000b59ea | 9802 | |
214993e1 ML |
9803 | dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); |
9804 | ||
9e869063 LL |
9805 | /* Tell DC to do a full surface update every time there |
9806 | * is a plane change. Inefficient, but works for now. | |
9807 | */ | |
9808 | dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; | |
9809 | ||
9810 | *lock_and_validation_needed = true; | |
62f55537 | 9811 | } |
e7b07cee HW |
9812 | |
9813 | ||
62f55537 AG |
9814 | return ret; |
9815 | } | |
a87fa993 | 9816 | |
69cb5629 VZ |
9817 | static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, |
9818 | int *src_w, int *src_h) | |
9819 | { | |
9820 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { | |
9821 | case DRM_MODE_ROTATE_90: | |
9822 | case DRM_MODE_ROTATE_270: | |
9823 | *src_w = plane_state->src_h >> 16; | |
9824 | *src_h = plane_state->src_w >> 16; | |
9825 | break; | |
9826 | case DRM_MODE_ROTATE_0: | |
9827 | case DRM_MODE_ROTATE_180: | |
9828 | default: | |
9829 | *src_w = plane_state->src_w >> 16; | |
9830 | *src_h = plane_state->src_h >> 16; | |
9831 | break; | |
9832 | } | |
9833 | } | |
9834 | ||
12f4849a SS |
9835 | static int dm_check_crtc_cursor(struct drm_atomic_state *state, |
9836 | struct drm_crtc *crtc, | |
9837 | struct drm_crtc_state *new_crtc_state) | |
9838 | { | |
d1bfbe8a SS |
9839 | struct drm_plane *cursor = crtc->cursor, *underlying; |
9840 | struct drm_plane_state *new_cursor_state, *new_underlying_state; | |
9841 | int i; | |
9842 | int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; | |
69cb5629 VZ |
9843 | int cursor_src_w, cursor_src_h; |
9844 | int underlying_src_w, underlying_src_h; | |
12f4849a SS |
9845 | |
9846 | /* On DCE and DCN there is no dedicated hardware cursor plane. We get a | |
9847 | * cursor per pipe but it's going to inherit the scaling and | |
9848 | * positioning from the underlying pipe. Check the cursor plane's | |
c82eddf8 SS |
9849 | * blending properties match the underlying planes'. |
9850 | */ | |
12f4849a | 9851 | |
d1bfbe8a | 9852 | new_cursor_state = drm_atomic_get_new_plane_state(state, cursor); |
c82eddf8 | 9853 | if (!new_cursor_state || !new_cursor_state->fb) |
12f4849a | 9854 | return 0; |
12f4849a | 9855 | |
69cb5629 VZ |
9856 | dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h); |
9857 | cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w; | |
9858 | cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h; | |
12f4849a | 9859 | |
d1bfbe8a SS |
9860 | for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { |
9861 | /* Narrow down to non-cursor planes on the same CRTC as the cursor */ | |
9862 | if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) | |
9863 | continue; | |
12f4849a | 9864 | |
d1bfbe8a SS |
9865 | /* Ignore disabled planes */ |
9866 | if (!new_underlying_state->fb) | |
9867 | continue; | |
9868 | ||
69cb5629 VZ |
9869 | dm_get_oriented_plane_size(new_underlying_state, |
9870 | &underlying_src_w, &underlying_src_h); | |
9871 | underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w; | |
9872 | underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h; | |
d1bfbe8a SS |
9873 | |
9874 | if (cursor_scale_w != underlying_scale_w || | |
9875 | cursor_scale_h != underlying_scale_h) { | |
9876 | drm_dbg_atomic(crtc->dev, | |
9877 | "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", | |
9878 | cursor->base.id, cursor->name, underlying->base.id, underlying->name); | |
9879 | return -EINVAL; | |
9880 | } | |
9881 | ||
9882 | /* If this plane covers the whole CRTC, no need to check planes underneath */ | |
9883 | if (new_underlying_state->crtc_x <= 0 && | |
9884 | new_underlying_state->crtc_y <= 0 && | |
9885 | new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && | |
9886 | new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) | |
9887 | break; | |
12f4849a SS |
9888 | } |
9889 | ||
9890 | return 0; | |
9891 | } | |
9892 | ||
44be939f ML |
9893 | static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) |
9894 | { | |
9895 | struct drm_connector *connector; | |
128f8ed5 | 9896 | struct drm_connector_state *conn_state, *old_conn_state; |
44be939f ML |
9897 | struct amdgpu_dm_connector *aconnector = NULL; |
9898 | int i; | |
c82eddf8 | 9899 | |
128f8ed5 RL |
9900 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { |
9901 | if (!conn_state->crtc) | |
9902 | conn_state = old_conn_state; | |
9903 | ||
44be939f ML |
9904 | if (conn_state->crtc != crtc) |
9905 | continue; | |
9906 | ||
9907 | aconnector = to_amdgpu_dm_connector(connector); | |
f0127cb1 | 9908 | if (!aconnector->mst_output_port || !aconnector->mst_root) |
44be939f ML |
9909 | aconnector = NULL; |
9910 | else | |
9911 | break; | |
9912 | } | |
9913 | ||
9914 | if (!aconnector) | |
9915 | return 0; | |
9916 | ||
f0127cb1 | 9917 | return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); |
44be939f ML |
9918 | } |
9919 | ||
b8592b48 LL |
9920 | /** |
9921 | * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. | |
c620e79b | 9922 | * |
b8592b48 LL |
9923 | * @dev: The DRM device |
9924 | * @state: The atomic state to commit | |
9925 | * | |
9926 | * Validate that the given atomic state is programmable by DC into hardware. | |
9927 | * This involves constructing a &struct dc_state reflecting the new hardware | |
9928 | * state we wish to commit, then querying DC to see if it is programmable. It's | |
9929 | * important not to modify the existing DC state. Otherwise, atomic_check | |
9930 | * may unexpectedly commit hardware changes. | |
9931 | * | |
9932 | * When validating the DC state, it's important that the right locks are | |
9933 | * acquired. For full updates case which removes/adds/updates streams on one | |
9934 | * CRTC while flipping on another CRTC, acquiring global lock will guarantee | |
9935 | * that any such full update commit will wait for completion of any outstanding | |
f6d7c7fa | 9936 | * flip using DRMs synchronization events. |
b8592b48 LL |
9937 | * |
9938 | * Note that DM adds the affected connectors for all CRTCs in state, when that | |
9939 | * might not seem necessary. This is because DC stream creation requires the | |
9940 | * DC sink, which is tied to the DRM connector state. Cleaning this up should | |
9941 | * be possible but non-trivial - a possible TODO item. | |
9942 | * | |
9943 | * Return: -Error code if validation failed. | |
9944 | */ | |
7578ecda AD |
9945 | static int amdgpu_dm_atomic_check(struct drm_device *dev, |
9946 | struct drm_atomic_state *state) | |
62f55537 | 9947 | { |
1348969a | 9948 | struct amdgpu_device *adev = drm_to_adev(dev); |
eb3dc897 | 9949 | struct dm_atomic_state *dm_state = NULL; |
62f55537 | 9950 | struct dc *dc = adev->dm.dc; |
62f55537 | 9951 | struct drm_connector *connector; |
c2cea706 | 9952 | struct drm_connector_state *old_con_state, *new_con_state; |
62f55537 | 9953 | struct drm_crtc *crtc; |
fc9e9920 | 9954 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
9e869063 LL |
9955 | struct drm_plane *plane; |
9956 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
74a16675 | 9957 | enum dc_status status; |
1e88ad0a | 9958 | int ret, i; |
62f55537 | 9959 | bool lock_and_validation_needed = false; |
35f33086 | 9960 | bool is_top_most_overlay = true; |
214993e1 | 9961 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
cdf657fc DA |
9962 | struct drm_dp_mst_topology_mgr *mgr; |
9963 | struct drm_dp_mst_topology_state *mst_state; | |
6513104b | 9964 | struct dsc_mst_fairness_vars vars[MAX_PIPES]; |
62f55537 | 9965 | |
e8a98235 | 9966 | trace_amdgpu_dm_atomic_check_begin(state); |
c44a22b3 | 9967 | |
62f55537 | 9968 | ret = drm_atomic_helper_check_modeset(dev, state); |
68ca1c3e S |
9969 | if (ret) { |
9970 | DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); | |
01e28f9c | 9971 | goto fail; |
68ca1c3e | 9972 | } |
62f55537 | 9973 | |
c5892a10 SW |
9974 | /* Check connector changes */ |
9975 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
9976 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); | |
9977 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
9978 | ||
9979 | /* Skip connectors that are disabled or part of modeset already. */ | |
c5892a10 SW |
9980 | if (!new_con_state->crtc) |
9981 | continue; | |
9982 | ||
9983 | new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); | |
9984 | if (IS_ERR(new_crtc_state)) { | |
68ca1c3e | 9985 | DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); |
c5892a10 SW |
9986 | ret = PTR_ERR(new_crtc_state); |
9987 | goto fail; | |
9988 | } | |
9989 | ||
3c6d1aeb | 9990 | if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || |
9991 | dm_old_con_state->scaling != dm_new_con_state->scaling) | |
c5892a10 SW |
9992 | new_crtc_state->connectors_changed = true; |
9993 | } | |
9994 | ||
349a19b2 | 9995 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
44be939f ML |
9996 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
9997 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
9998 | ret = add_affected_mst_dsc_crtcs(state, crtc); | |
68ca1c3e S |
9999 | if (ret) { |
10000 | DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); | |
44be939f | 10001 | goto fail; |
68ca1c3e | 10002 | } |
44be939f ML |
10003 | } |
10004 | } | |
10005 | } | |
1e88ad0a | 10006 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
886876ec EB |
10007 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
10008 | ||
1e88ad0a | 10009 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && |
98e6436d | 10010 | !new_crtc_state->color_mgmt_changed && |
886876ec EB |
10011 | old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && |
10012 | dm_old_crtc_state->dsc_force_changed == false) | |
1e88ad0a | 10013 | continue; |
7bef1af3 | 10014 | |
03fc4cf4 | 10015 | ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); |
68ca1c3e S |
10016 | if (ret) { |
10017 | DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); | |
03fc4cf4 | 10018 | goto fail; |
68ca1c3e | 10019 | } |
03fc4cf4 | 10020 | |
1e88ad0a S |
10021 | if (!new_crtc_state->enable) |
10022 | continue; | |
fc9e9920 | 10023 | |
1e88ad0a | 10024 | ret = drm_atomic_add_affected_connectors(state, crtc); |
68ca1c3e S |
10025 | if (ret) { |
10026 | DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); | |
706bc8c5 | 10027 | goto fail; |
68ca1c3e | 10028 | } |
fc9e9920 | 10029 | |
1e88ad0a | 10030 | ret = drm_atomic_add_affected_planes(state, crtc); |
68ca1c3e S |
10031 | if (ret) { |
10032 | DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); | |
1e88ad0a | 10033 | goto fail; |
68ca1c3e | 10034 | } |
115a385c | 10035 | |
cbac53f7 | 10036 | if (dm_old_crtc_state->dsc_force_changed) |
115a385c | 10037 | new_crtc_state->mode_changed = true; |
e7b07cee HW |
10038 | } |
10039 | ||
2d9e6431 NK |
10040 | /* |
10041 | * Add all primary and overlay planes on the CRTC to the state | |
10042 | * whenever a plane is enabled to maintain correct z-ordering | |
10043 | * and to enable fast surface updates. | |
10044 | */ | |
10045 | drm_for_each_crtc(crtc, dev) { | |
10046 | bool modified = false; | |
10047 | ||
10048 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { | |
10049 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
10050 | continue; | |
10051 | ||
10052 | if (new_plane_state->crtc == crtc || | |
10053 | old_plane_state->crtc == crtc) { | |
10054 | modified = true; | |
10055 | break; | |
10056 | } | |
10057 | } | |
10058 | ||
10059 | if (!modified) | |
10060 | continue; | |
10061 | ||
10062 | drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { | |
10063 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
10064 | continue; | |
10065 | ||
10066 | new_plane_state = | |
10067 | drm_atomic_get_plane_state(state, plane); | |
10068 | ||
10069 | if (IS_ERR(new_plane_state)) { | |
10070 | ret = PTR_ERR(new_plane_state); | |
68ca1c3e | 10071 | DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); |
2d9e6431 NK |
10072 | goto fail; |
10073 | } | |
10074 | } | |
10075 | } | |
10076 | ||
22c42b0e LL |
10077 | /* |
10078 | * DC consults the zpos (layer_index in DC terminology) to determine the | |
10079 | * hw plane on which to enable the hw cursor (see | |
10080 | * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in | |
10081 | * atomic state, so call drm helper to normalize zpos. | |
10082 | */ | |
ac0bb08d LL |
10083 | ret = drm_atomic_normalize_zpos(dev, state); |
10084 | if (ret) { | |
10085 | drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); | |
10086 | goto fail; | |
10087 | } | |
22c42b0e | 10088 | |
62f55537 | 10089 | /* Remove exiting planes if they are modified */ |
9e869063 LL |
10090 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { |
10091 | ret = dm_update_plane_state(dc, state, plane, | |
10092 | old_plane_state, | |
10093 | new_plane_state, | |
10094 | false, | |
35f33086 BL |
10095 | &lock_and_validation_needed, |
10096 | &is_top_most_overlay); | |
68ca1c3e S |
10097 | if (ret) { |
10098 | DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); | |
9e869063 | 10099 | goto fail; |
68ca1c3e | 10100 | } |
62f55537 AG |
10101 | } |
10102 | ||
10103 | /* Disable all crtcs which require disable */ | |
4b9674e5 LL |
10104 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
10105 | ret = dm_update_crtc_state(&adev->dm, state, crtc, | |
10106 | old_crtc_state, | |
10107 | new_crtc_state, | |
10108 | false, | |
10109 | &lock_and_validation_needed); | |
68ca1c3e S |
10110 | if (ret) { |
10111 | DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); | |
4b9674e5 | 10112 | goto fail; |
68ca1c3e | 10113 | } |
62f55537 AG |
10114 | } |
10115 | ||
10116 | /* Enable all crtcs which require enable */ | |
4b9674e5 LL |
10117 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
10118 | ret = dm_update_crtc_state(&adev->dm, state, crtc, | |
10119 | old_crtc_state, | |
10120 | new_crtc_state, | |
10121 | true, | |
10122 | &lock_and_validation_needed); | |
68ca1c3e S |
10123 | if (ret) { |
10124 | DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); | |
4b9674e5 | 10125 | goto fail; |
68ca1c3e | 10126 | } |
62f55537 AG |
10127 | } |
10128 | ||
10129 | /* Add new/modified planes */ | |
9e869063 LL |
10130 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { |
10131 | ret = dm_update_plane_state(dc, state, plane, | |
10132 | old_plane_state, | |
10133 | new_plane_state, | |
10134 | true, | |
35f33086 BL |
10135 | &lock_and_validation_needed, |
10136 | &is_top_most_overlay); | |
68ca1c3e S |
10137 | if (ret) { |
10138 | DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); | |
9e869063 | 10139 | goto fail; |
68ca1c3e | 10140 | } |
62f55537 AG |
10141 | } |
10142 | ||
876fcc42 | 10143 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
7cce4cd6 LP |
10144 | ret = pre_validate_dsc(state, &dm_state, vars); |
10145 | if (ret != 0) | |
876fcc42 | 10146 | goto fail; |
876fcc42 | 10147 | } |
876fcc42 | 10148 | |
b349f76e ES |
10149 | /* Run this here since we want to validate the streams we created */ |
10150 | ret = drm_atomic_helper_check_planes(dev, state); | |
68ca1c3e S |
10151 | if (ret) { |
10152 | DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); | |
b349f76e | 10153 | goto fail; |
68ca1c3e | 10154 | } |
62f55537 | 10155 | |
214993e1 ML |
10156 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
10157 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
10158 | if (dm_new_crtc_state->mpo_requested) | |
10159 | DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); | |
10160 | } | |
10161 | ||
12f4849a SS |
10162 | /* Check cursor planes scaling */ |
10163 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { | |
10164 | ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); | |
68ca1c3e S |
10165 | if (ret) { |
10166 | DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); | |
12f4849a | 10167 | goto fail; |
68ca1c3e | 10168 | } |
12f4849a SS |
10169 | } |
10170 | ||
43d10d30 NK |
10171 | if (state->legacy_cursor_update) { |
10172 | /* | |
10173 | * This is a fast cursor update coming from the plane update | |
10174 | * helper, check if it can be done asynchronously for better | |
10175 | * performance. | |
10176 | */ | |
10177 | state->async_update = | |
10178 | !drm_atomic_helper_async_check(dev, state); | |
10179 | ||
10180 | /* | |
10181 | * Skip the remaining global validation if this is an async | |
10182 | * update. Cursor updates can be done without affecting | |
10183 | * state or bandwidth calcs and this avoids the performance | |
10184 | * penalty of locking the private state object and | |
10185 | * allocating a new dc_state. | |
10186 | */ | |
10187 | if (state->async_update) | |
10188 | return 0; | |
10189 | } | |
10190 | ||
ebdd27e1 | 10191 | /* Check scaling and underscan changes*/ |
1f6010a9 | 10192 | /* TODO Removed scaling changes validation due to inability to commit |
e7b07cee HW |
10193 | * new stream into context w\o causing full reset. Need to |
10194 | * decide how to handle. | |
10195 | */ | |
c2cea706 | 10196 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
10197 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); |
10198 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
10199 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
e7b07cee HW |
10200 | |
10201 | /* Skip any modesets/resets */ | |
0bc9706d LSL |
10202 | if (!acrtc || drm_atomic_crtc_needs_modeset( |
10203 | drm_atomic_get_new_crtc_state(state, &acrtc->base))) | |
e7b07cee HW |
10204 | continue; |
10205 | ||
b830ebc9 | 10206 | /* Skip any thing not scale or underscan changes */ |
54d76575 | 10207 | if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) |
e7b07cee HW |
10208 | continue; |
10209 | ||
10210 | lock_and_validation_needed = true; | |
10211 | } | |
10212 | ||
c689e1e3 LP |
10213 | /* set the slot info for each mst_state based on the link encoding format */ |
10214 | for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { | |
10215 | struct amdgpu_dm_connector *aconnector; | |
10216 | struct drm_connector *connector; | |
10217 | struct drm_connector_list_iter iter; | |
10218 | u8 link_coding_cap; | |
10219 | ||
10220 | drm_connector_list_iter_begin(dev, &iter); | |
10221 | drm_for_each_connector_iter(connector, &iter) { | |
10222 | if (connector->index == mst_state->mgr->conn_base_id) { | |
10223 | aconnector = to_amdgpu_dm_connector(connector); | |
10224 | link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); | |
10225 | drm_dp_mst_update_slots(mst_state, link_coding_cap); | |
10226 | ||
10227 | break; | |
10228 | } | |
10229 | } | |
10230 | drm_connector_list_iter_end(&iter); | |
10231 | } | |
c689e1e3 | 10232 | |
f6d7c7fa NK |
10233 | /** |
10234 | * Streams and planes are reset when there are changes that affect | |
10235 | * bandwidth. Anything that affects bandwidth needs to go through | |
10236 | * DC global validation to ensure that the configuration can be applied | |
10237 | * to hardware. | |
10238 | * | |
10239 | * We have to currently stall out here in atomic_check for outstanding | |
10240 | * commits to finish in this case because our IRQ handlers reference | |
10241 | * DRM state directly - we can end up disabling interrupts too early | |
10242 | * if we don't. | |
10243 | * | |
10244 | * TODO: Remove this stall and drop DM state private objects. | |
a87fa993 | 10245 | */ |
f6d7c7fa | 10246 | if (lock_and_validation_needed) { |
eb3dc897 | 10247 | ret = dm_atomic_get_state(state, &dm_state); |
68ca1c3e S |
10248 | if (ret) { |
10249 | DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); | |
eb3dc897 | 10250 | goto fail; |
68ca1c3e | 10251 | } |
e7b07cee HW |
10252 | |
10253 | ret = do_aquire_global_lock(dev, state); | |
68ca1c3e S |
10254 | if (ret) { |
10255 | DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); | |
e7b07cee | 10256 | goto fail; |
68ca1c3e | 10257 | } |
1dc90497 | 10258 | |
7cce4cd6 LP |
10259 | ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); |
10260 | if (ret) { | |
68ca1c3e | 10261 | DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); |
dd24662d | 10262 | ret = -EINVAL; |
8c20a1ed | 10263 | goto fail; |
68ca1c3e | 10264 | } |
8c20a1ed | 10265 | |
6513104b | 10266 | ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); |
68ca1c3e S |
10267 | if (ret) { |
10268 | DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); | |
29b9ba74 | 10269 | goto fail; |
68ca1c3e | 10270 | } |
29b9ba74 | 10271 | |
ded58c7b ZL |
10272 | /* |
10273 | * Perform validation of MST topology in the state: | |
10274 | * We need to perform MST atomic check before calling | |
10275 | * dc_validate_global_state(), or there is a chance | |
10276 | * to get stuck in an infinite loop and hang eventually. | |
10277 | */ | |
10278 | ret = drm_dp_mst_atomic_check(state); | |
68ca1c3e S |
10279 | if (ret) { |
10280 | DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); | |
ded58c7b | 10281 | goto fail; |
68ca1c3e | 10282 | } |
85fb8bb9 | 10283 | status = dc_validate_global_state(dc, dm_state->context, true); |
74a16675 | 10284 | if (status != DC_OK) { |
68ca1c3e | 10285 | DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", |
74a16675 | 10286 | dc_status_to_str(status), status); |
e7b07cee HW |
10287 | ret = -EINVAL; |
10288 | goto fail; | |
10289 | } | |
bd200d19 | 10290 | } else { |
674e78ac | 10291 | /* |
bd200d19 NK |
10292 | * The commit is a fast update. Fast updates shouldn't change |
10293 | * the DC context, affect global validation, and can have their | |
10294 | * commit work done in parallel with other commits not touching | |
10295 | * the same resource. If we have a new DC context as part of | |
10296 | * the DM atomic state from validation we need to free it and | |
10297 | * retain the existing one instead. | |
fde9f39a MR |
10298 | * |
10299 | * Furthermore, since the DM atomic state only contains the DC | |
10300 | * context and can safely be annulled, we can free the state | |
10301 | * and clear the associated private object now to free | |
10302 | * some memory and avoid a possible use-after-free later. | |
674e78ac | 10303 | */ |
bd200d19 | 10304 | |
fde9f39a MR |
10305 | for (i = 0; i < state->num_private_objs; i++) { |
10306 | struct drm_private_obj *obj = state->private_objs[i].ptr; | |
bd200d19 | 10307 | |
fde9f39a MR |
10308 | if (obj->funcs == adev->dm.atomic_obj.funcs) { |
10309 | int j = state->num_private_objs-1; | |
bd200d19 | 10310 | |
fde9f39a MR |
10311 | dm_atomic_destroy_state(obj, |
10312 | state->private_objs[i].state); | |
10313 | ||
10314 | /* If i is not at the end of the array then the | |
10315 | * last element needs to be moved to where i was | |
10316 | * before the array can safely be truncated. | |
10317 | */ | |
10318 | if (i != j) | |
10319 | state->private_objs[i] = | |
10320 | state->private_objs[j]; | |
bd200d19 | 10321 | |
fde9f39a MR |
10322 | state->private_objs[j].ptr = NULL; |
10323 | state->private_objs[j].state = NULL; | |
10324 | state->private_objs[j].old_state = NULL; | |
10325 | state->private_objs[j].new_state = NULL; | |
10326 | ||
10327 | state->num_private_objs = j; | |
10328 | break; | |
10329 | } | |
bd200d19 | 10330 | } |
e7b07cee HW |
10331 | } |
10332 | ||
caff0e66 | 10333 | /* Store the overall update type for use later in atomic check. */ |
c82eddf8 | 10334 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
caff0e66 NK |
10335 | struct dm_crtc_state *dm_new_crtc_state = |
10336 | to_dm_crtc_state(new_crtc_state); | |
10337 | ||
f6d7c7fa NK |
10338 | dm_new_crtc_state->update_type = lock_and_validation_needed ? |
10339 | UPDATE_TYPE_FULL : | |
10340 | UPDATE_TYPE_FAST; | |
e7b07cee HW |
10341 | } |
10342 | ||
10343 | /* Must be success */ | |
10344 | WARN_ON(ret); | |
e8a98235 RS |
10345 | |
10346 | trace_amdgpu_dm_atomic_check_finish(state, ret); | |
10347 | ||
e7b07cee HW |
10348 | return ret; |
10349 | ||
10350 | fail: | |
10351 | if (ret == -EDEADLK) | |
01e28f9c | 10352 | DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); |
e7b07cee | 10353 | else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) |
01e28f9c | 10354 | DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); |
e7b07cee | 10355 | else |
c82eddf8 | 10356 | DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret); |
e7b07cee | 10357 | |
e8a98235 RS |
10358 | trace_amdgpu_dm_atomic_check_finish(state, ret); |
10359 | ||
e7b07cee HW |
10360 | return ret; |
10361 | } | |
10362 | ||
3ee6b26b AD |
10363 | static bool is_dp_capable_without_timing_msa(struct dc *dc, |
10364 | struct amdgpu_dm_connector *amdgpu_dm_connector) | |
e7b07cee | 10365 | { |
ae67558b | 10366 | u8 dpcd_data; |
e7b07cee HW |
10367 | bool capable = false; |
10368 | ||
c84dec2f | 10369 | if (amdgpu_dm_connector->dc_link && |
e7b07cee HW |
10370 | dm_helpers_dp_read_dpcd( |
10371 | NULL, | |
c84dec2f | 10372 | amdgpu_dm_connector->dc_link, |
e7b07cee HW |
10373 | DP_DOWN_STREAM_PORT_COUNT, |
10374 | &dpcd_data, | |
10375 | sizeof(dpcd_data))) { | |
10376 | capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; | |
10377 | } | |
10378 | ||
10379 | return capable; | |
10380 | } | |
f9b4f20c | 10381 | |
46db138d SW |
10382 | static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, |
10383 | unsigned int offset, | |
10384 | unsigned int total_length, | |
ae67558b | 10385 | u8 *data, |
46db138d SW |
10386 | unsigned int length, |
10387 | struct amdgpu_hdmi_vsdb_info *vsdb) | |
10388 | { | |
10389 | bool res; | |
10390 | union dmub_rb_cmd cmd; | |
10391 | struct dmub_cmd_send_edid_cea *input; | |
10392 | struct dmub_cmd_edid_cea_output *output; | |
10393 | ||
10394 | if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) | |
10395 | return false; | |
10396 | ||
10397 | memset(&cmd, 0, sizeof(cmd)); | |
10398 | ||
10399 | input = &cmd.edid_cea.data.input; | |
10400 | ||
10401 | cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; | |
10402 | cmd.edid_cea.header.sub_type = 0; | |
10403 | cmd.edid_cea.header.payload_bytes = | |
10404 | sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); | |
10405 | input->offset = offset; | |
10406 | input->length = length; | |
eb9e59eb | 10407 | input->cea_total_length = total_length; |
46db138d SW |
10408 | memcpy(input->payload, data, length); |
10409 | ||
e97cc04f | 10410 | res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); |
46db138d SW |
10411 | if (!res) { |
10412 | DRM_ERROR("EDID CEA parser failed\n"); | |
10413 | return false; | |
10414 | } | |
10415 | ||
10416 | output = &cmd.edid_cea.data.output; | |
10417 | ||
10418 | if (output->type == DMUB_CMD__EDID_CEA_ACK) { | |
10419 | if (!output->ack.success) { | |
10420 | DRM_ERROR("EDID CEA ack failed at offset %d\n", | |
10421 | output->ack.offset); | |
10422 | } | |
10423 | } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { | |
10424 | if (!output->amd_vsdb.vsdb_found) | |
10425 | return false; | |
10426 | ||
10427 | vsdb->freesync_supported = output->amd_vsdb.freesync_supported; | |
10428 | vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; | |
10429 | vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; | |
10430 | vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; | |
10431 | } else { | |
b76a8062 | 10432 | DRM_WARN("Unknown EDID CEA parser results\n"); |
46db138d SW |
10433 | return false; |
10434 | } | |
10435 | ||
10436 | return true; | |
10437 | } | |
10438 | ||
10439 | static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, | |
ae67558b | 10440 | u8 *edid_ext, int len, |
f9b4f20c SW |
10441 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10442 | { | |
10443 | int i; | |
f9b4f20c SW |
10444 | |
10445 | /* send extension block to DMCU for parsing */ | |
10446 | for (i = 0; i < len; i += 8) { | |
10447 | bool res; | |
10448 | int offset; | |
10449 | ||
10450 | /* send 8 bytes a time */ | |
46db138d | 10451 | if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) |
f9b4f20c SW |
10452 | return false; |
10453 | ||
10454 | if (i+8 == len) { | |
10455 | /* EDID block sent completed, expect result */ | |
10456 | int version, min_rate, max_rate; | |
10457 | ||
46db138d | 10458 | res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); |
f9b4f20c SW |
10459 | if (res) { |
10460 | /* amd vsdb found */ | |
10461 | vsdb_info->freesync_supported = 1; | |
10462 | vsdb_info->amd_vsdb_version = version; | |
10463 | vsdb_info->min_refresh_rate_hz = min_rate; | |
10464 | vsdb_info->max_refresh_rate_hz = max_rate; | |
10465 | return true; | |
10466 | } | |
10467 | /* not amd vsdb */ | |
10468 | return false; | |
10469 | } | |
10470 | ||
10471 | /* check for ack*/ | |
46db138d | 10472 | res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); |
f9b4f20c SW |
10473 | if (!res) |
10474 | return false; | |
10475 | } | |
10476 | ||
10477 | return false; | |
10478 | } | |
10479 | ||
46db138d | 10480 | static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, |
ae67558b | 10481 | u8 *edid_ext, int len, |
46db138d SW |
10482 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10483 | { | |
10484 | int i; | |
10485 | ||
10486 | /* send extension block to DMCU for parsing */ | |
10487 | for (i = 0; i < len; i += 8) { | |
10488 | /* send 8 bytes a time */ | |
10489 | if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) | |
10490 | return false; | |
10491 | } | |
10492 | ||
10493 | return vsdb_info->freesync_supported; | |
10494 | } | |
10495 | ||
10496 | static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, | |
ae67558b | 10497 | u8 *edid_ext, int len, |
46db138d SW |
10498 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10499 | { | |
10500 | struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); | |
53f4da73 | 10501 | bool ret; |
46db138d | 10502 | |
53f4da73 | 10503 | mutex_lock(&adev->dm.dc_lock); |
46db138d | 10504 | if (adev->dm.dmub_srv) |
53f4da73 | 10505 | ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); |
46db138d | 10506 | else |
53f4da73 SW |
10507 | ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); |
10508 | mutex_unlock(&adev->dm.dc_lock); | |
10509 | return ret; | |
46db138d SW |
10510 | } |
10511 | ||
7c7dd774 | 10512 | static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, |
f9b4f20c SW |
10513 | struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) |
10514 | { | |
ae67558b | 10515 | u8 *edid_ext = NULL; |
f9b4f20c SW |
10516 | int i; |
10517 | bool valid_vsdb_found = false; | |
10518 | ||
10519 | /*----- drm_find_cea_extension() -----*/ | |
10520 | /* No EDID or EDID extensions */ | |
10521 | if (edid == NULL || edid->extensions == 0) | |
7c7dd774 | 10522 | return -ENODEV; |
f9b4f20c SW |
10523 | |
10524 | /* Find CEA extension */ | |
10525 | for (i = 0; i < edid->extensions; i++) { | |
10526 | edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); | |
10527 | if (edid_ext[0] == CEA_EXT) | |
10528 | break; | |
10529 | } | |
10530 | ||
10531 | if (i == edid->extensions) | |
7c7dd774 | 10532 | return -ENODEV; |
f9b4f20c SW |
10533 | |
10534 | /*----- cea_db_offsets() -----*/ | |
10535 | if (edid_ext[0] != CEA_EXT) | |
7c7dd774 | 10536 | return -ENODEV; |
f9b4f20c SW |
10537 | |
10538 | valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); | |
7c7dd774 AB |
10539 | |
10540 | return valid_vsdb_found ? i : -ENODEV; | |
f9b4f20c SW |
10541 | } |
10542 | ||
c620e79b RS |
10543 | /** |
10544 | * amdgpu_dm_update_freesync_caps - Update Freesync capabilities | |
10545 | * | |
41ee1f18 AD |
10546 | * @connector: Connector to query. |
10547 | * @edid: EDID from monitor | |
c620e79b RS |
10548 | * |
10549 | * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep | |
10550 | * track of some of the display information in the internal data struct used by | |
10551 | * amdgpu_dm. This function checks which type of connector we need to set the | |
10552 | * FreeSync parameters. | |
10553 | */ | |
98e6436d | 10554 | void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
c620e79b | 10555 | struct edid *edid) |
e7b07cee | 10556 | { |
eb0709ba | 10557 | int i = 0; |
e7b07cee HW |
10558 | struct detailed_timing *timing; |
10559 | struct detailed_non_pixel *data; | |
10560 | struct detailed_data_monitor_range *range; | |
c84dec2f HW |
10561 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
10562 | to_amdgpu_dm_connector(connector); | |
bb47de73 | 10563 | struct dm_connector_state *dm_con_state = NULL; |
9ad54467 | 10564 | struct dc_sink *sink; |
e7b07cee HW |
10565 | |
10566 | struct drm_device *dev = connector->dev; | |
1348969a | 10567 | struct amdgpu_device *adev = drm_to_adev(dev); |
f9b4f20c | 10568 | struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; |
c620e79b | 10569 | bool freesync_capable = false; |
5b49da02 | 10570 | enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; |
b830ebc9 | 10571 | |
8218d7f1 HW |
10572 | if (!connector->state) { |
10573 | DRM_ERROR("%s - Connector has no state", __func__); | |
bb47de73 | 10574 | goto update; |
8218d7f1 HW |
10575 | } |
10576 | ||
9b2fdc33 AP |
10577 | sink = amdgpu_dm_connector->dc_sink ? |
10578 | amdgpu_dm_connector->dc_sink : | |
10579 | amdgpu_dm_connector->dc_em_sink; | |
10580 | ||
10581 | if (!edid || !sink) { | |
98e6436d AK |
10582 | dm_con_state = to_dm_connector_state(connector->state); |
10583 | ||
10584 | amdgpu_dm_connector->min_vfreq = 0; | |
10585 | amdgpu_dm_connector->max_vfreq = 0; | |
10586 | amdgpu_dm_connector->pixel_clock_mhz = 0; | |
9b2fdc33 AP |
10587 | connector->display_info.monitor_range.min_vfreq = 0; |
10588 | connector->display_info.monitor_range.max_vfreq = 0; | |
10589 | freesync_capable = false; | |
98e6436d | 10590 | |
bb47de73 | 10591 | goto update; |
98e6436d AK |
10592 | } |
10593 | ||
8218d7f1 HW |
10594 | dm_con_state = to_dm_connector_state(connector->state); |
10595 | ||
e7b07cee | 10596 | if (!adev->dm.freesync_module) |
bb47de73 | 10597 | goto update; |
f9b4f20c | 10598 | |
9b2fdc33 AP |
10599 | if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT |
10600 | || sink->sink_signal == SIGNAL_TYPE_EDP) { | |
f9b4f20c SW |
10601 | bool edid_check_required = false; |
10602 | ||
10603 | if (edid) { | |
e7b07cee HW |
10604 | edid_check_required = is_dp_capable_without_timing_msa( |
10605 | adev->dm.dc, | |
c84dec2f | 10606 | amdgpu_dm_connector); |
e7b07cee | 10607 | } |
e7b07cee | 10608 | |
f9b4f20c SW |
10609 | if (edid_check_required == true && (edid->version > 1 || |
10610 | (edid->version == 1 && edid->revision > 1))) { | |
10611 | for (i = 0; i < 4; i++) { | |
e7b07cee | 10612 | |
f9b4f20c SW |
10613 | timing = &edid->detailed_timings[i]; |
10614 | data = &timing->data.other_data; | |
10615 | range = &data->data.range; | |
10616 | /* | |
10617 | * Check if monitor has continuous frequency mode | |
10618 | */ | |
10619 | if (data->type != EDID_DETAIL_MONITOR_RANGE) | |
10620 | continue; | |
10621 | /* | |
10622 | * Check for flag range limits only. If flag == 1 then | |
10623 | * no additional timing information provided. | |
10624 | * Default GTF, GTF Secondary curve and CVT are not | |
10625 | * supported | |
10626 | */ | |
10627 | if (range->flags != 1) | |
10628 | continue; | |
a0ffc3fd | 10629 | |
f9b4f20c SW |
10630 | amdgpu_dm_connector->min_vfreq = range->min_vfreq; |
10631 | amdgpu_dm_connector->max_vfreq = range->max_vfreq; | |
10632 | amdgpu_dm_connector->pixel_clock_mhz = | |
10633 | range->pixel_clock_mhz * 10; | |
a0ffc3fd | 10634 | |
f9b4f20c SW |
10635 | connector->display_info.monitor_range.min_vfreq = range->min_vfreq; |
10636 | connector->display_info.monitor_range.max_vfreq = range->max_vfreq; | |
e7b07cee | 10637 | |
f9b4f20c SW |
10638 | break; |
10639 | } | |
98e6436d | 10640 | |
f9b4f20c SW |
10641 | if (amdgpu_dm_connector->max_vfreq - |
10642 | amdgpu_dm_connector->min_vfreq > 10) { | |
98e6436d | 10643 | |
f9b4f20c SW |
10644 | freesync_capable = true; |
10645 | } | |
10646 | } | |
9b2fdc33 | 10647 | } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
7c7dd774 AB |
10648 | i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); |
10649 | if (i >= 0 && vsdb_info.freesync_supported) { | |
f9b4f20c SW |
10650 | timing = &edid->detailed_timings[i]; |
10651 | data = &timing->data.other_data; | |
10652 | ||
10653 | amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; | |
5b49da02 SJK |
10654 | amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; |
10655 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) | |
10656 | freesync_capable = true; | |
10657 | ||
10658 | connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; | |
10659 | connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; | |
10660 | } | |
10661 | } | |
10662 | ||
10663 | as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); | |
10664 | ||
10665 | if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { | |
10666 | i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); | |
10667 | if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { | |
10668 | ||
10669 | amdgpu_dm_connector->pack_sdp_v1_3 = true; | |
10670 | amdgpu_dm_connector->as_type = as_type; | |
10671 | amdgpu_dm_connector->vsdb_info = vsdb_info; | |
10672 | ||
10673 | amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; | |
f9b4f20c SW |
10674 | amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; |
10675 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) | |
10676 | freesync_capable = true; | |
10677 | ||
10678 | connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; | |
10679 | connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; | |
e7b07cee HW |
10680 | } |
10681 | } | |
bb47de73 NK |
10682 | |
10683 | update: | |
10684 | if (dm_con_state) | |
10685 | dm_con_state->freesync_capable = freesync_capable; | |
10686 | ||
10687 | if (connector->vrr_capable_property) | |
10688 | drm_connector_set_vrr_capable_property(connector, | |
10689 | freesync_capable); | |
e7b07cee HW |
10690 | } |
10691 | ||
3d4e52d0 VL |
10692 | void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) |
10693 | { | |
1348969a | 10694 | struct amdgpu_device *adev = drm_to_adev(dev); |
3d4e52d0 VL |
10695 | struct dc *dc = adev->dm.dc; |
10696 | int i; | |
10697 | ||
10698 | mutex_lock(&adev->dm.dc_lock); | |
10699 | if (dc->current_state) { | |
10700 | for (i = 0; i < dc->current_state->stream_count; ++i) | |
10701 | dc->current_state->streams[i] | |
10702 | ->triggered_crtc_reset.enabled = | |
10703 | adev->dm.force_timing_sync; | |
10704 | ||
10705 | dm_enable_per_frame_crtc_master_sync(dc->current_state); | |
10706 | dc_trigger_sync(dc, dc->current_state); | |
10707 | } | |
10708 | mutex_unlock(&adev->dm.dc_lock); | |
10709 | } | |
9d83722d RS |
10710 | |
10711 | void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, | |
ae67558b | 10712 | u32 value, const char *func_name) |
9d83722d RS |
10713 | { |
10714 | #ifdef DM_CHECK_ADDR_0 | |
10715 | if (address == 0) { | |
10716 | DC_ERR("invalid register write. address = 0"); | |
10717 | return; | |
10718 | } | |
10719 | #endif | |
10720 | cgs_write_register(ctx->cgs_device, address, value); | |
10721 | trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); | |
10722 | } | |
10723 | ||
10724 | uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, | |
10725 | const char *func_name) | |
10726 | { | |
ae67558b | 10727 | u32 value; |
9d83722d RS |
10728 | #ifdef DM_CHECK_ADDR_0 |
10729 | if (address == 0) { | |
10730 | DC_ERR("invalid register read; address = 0\n"); | |
10731 | return 0; | |
10732 | } | |
10733 | #endif | |
10734 | ||
10735 | if (ctx->dmub_srv && | |
10736 | ctx->dmub_srv->reg_helper_offload.gather_in_progress && | |
10737 | !ctx->dmub_srv->reg_helper_offload.should_burst_write) { | |
10738 | ASSERT(false); | |
10739 | return 0; | |
10740 | } | |
10741 | ||
10742 | value = cgs_read_register(ctx->cgs_device, address); | |
10743 | ||
10744 | trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); | |
10745 | ||
10746 | return value; | |
10747 | } | |
81927e28 | 10748 | |
ead08b95 SW |
10749 | int amdgpu_dm_process_dmub_aux_transfer_sync( |
10750 | struct dc_context *ctx, | |
10751 | unsigned int link_index, | |
10752 | struct aux_payload *payload, | |
10753 | enum aux_return_code_type *operation_result) | |
88f52b1f JS |
10754 | { |
10755 | struct amdgpu_device *adev = ctx->driver_context; | |
88f52b1f | 10756 | struct dmub_notification *p_notify = adev->dm.dmub_notify; |
ead08b95 | 10757 | int ret = -1; |
88f52b1f | 10758 | |
ead08b95 SW |
10759 | mutex_lock(&adev->dm.dpia_aux_lock); |
10760 | if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { | |
10761 | *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; | |
10762 | goto out; | |
3335a135 | 10763 | } |
ead08b95 SW |
10764 | |
10765 | if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { | |
10766 | DRM_ERROR("wait_for_completion_timeout timeout!"); | |
10767 | *operation_result = AUX_RET_ERROR_TIMEOUT; | |
10768 | goto out; | |
10769 | } | |
10770 | ||
10771 | if (p_notify->result != AUX_RET_SUCCESS) { | |
10772 | /* | |
10773 | * Transient states before tunneling is enabled could | |
10774 | * lead to this error. We can ignore this for now. | |
10775 | */ | |
10776 | if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { | |
10777 | DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", | |
10778 | payload->address, payload->length, | |
10779 | p_notify->result); | |
88f52b1f | 10780 | } |
ead08b95 SW |
10781 | *operation_result = AUX_RET_ERROR_INVALID_REPLY; |
10782 | goto out; | |
10783 | } | |
10784 | ||
10785 | ||
10786 | payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; | |
10787 | if (!payload->write && p_notify->aux_reply.length && | |
10788 | (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { | |
10789 | ||
10790 | if (payload->length != p_notify->aux_reply.length) { | |
10791 | DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", | |
10792 | p_notify->aux_reply.length, | |
10793 | payload->address, payload->length); | |
10794 | *operation_result = AUX_RET_ERROR_INVALID_REPLY; | |
10795 | goto out; | |
88f52b1f | 10796 | } |
ead08b95 SW |
10797 | |
10798 | memcpy(payload->data, p_notify->aux_reply.data, | |
10799 | p_notify->aux_reply.length); | |
88f52b1f JS |
10800 | } |
10801 | ||
ead08b95 SW |
10802 | /* success */ |
10803 | ret = p_notify->aux_reply.length; | |
10804 | *operation_result = p_notify->result; | |
10805 | out: | |
0cf8307a | 10806 | reinit_completion(&adev->dm.dmub_aux_transfer_done); |
ead08b95 SW |
10807 | mutex_unlock(&adev->dm.dpia_aux_lock); |
10808 | return ret; | |
88f52b1f JS |
10809 | } |
10810 | ||
ead08b95 SW |
10811 | int amdgpu_dm_process_dmub_set_config_sync( |
10812 | struct dc_context *ctx, | |
10813 | unsigned int link_index, | |
10814 | struct set_config_cmd_payload *payload, | |
10815 | enum set_config_status *operation_result) | |
81927e28 JS |
10816 | { |
10817 | struct amdgpu_device *adev = ctx->driver_context; | |
ead08b95 SW |
10818 | bool is_cmd_complete; |
10819 | int ret; | |
81927e28 | 10820 | |
ead08b95 SW |
10821 | mutex_lock(&adev->dm.dpia_aux_lock); |
10822 | is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, | |
10823 | link_index, payload, adev->dm.dmub_notify); | |
88f52b1f | 10824 | |
ead08b95 SW |
10825 | if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { |
10826 | ret = 0; | |
10827 | *operation_result = adev->dm.dmub_notify->sc_status; | |
10828 | } else { | |
9e3a50d2 | 10829 | DRM_ERROR("wait_for_completion_timeout timeout!"); |
ead08b95 SW |
10830 | ret = -1; |
10831 | *operation_result = SET_CONFIG_UNKNOWN_ERROR; | |
81927e28 JS |
10832 | } |
10833 | ||
0cf8307a SW |
10834 | if (!is_cmd_complete) |
10835 | reinit_completion(&adev->dm.dmub_aux_transfer_done); | |
ead08b95 SW |
10836 | mutex_unlock(&adev->dm.dpia_aux_lock); |
10837 | return ret; | |
81927e28 | 10838 | } |
1edf5ae1 ZL |
10839 | |
10840 | /* | |
10841 | * Check whether seamless boot is supported. | |
10842 | * | |
10843 | * So far we only support seamless boot on CHIP_VANGOGH. | |
10844 | * If everything goes well, we may consider expanding | |
10845 | * seamless boot to other ASICs. | |
10846 | */ | |
10847 | bool check_seamless_boot_capability(struct amdgpu_device *adev) | |
10848 | { | |
20875141 PY |
10849 | switch (adev->ip_versions[DCE_HWIP][0]) { |
10850 | case IP_VERSION(3, 0, 1): | |
1edf5ae1 ZL |
10851 | if (!adev->mman.keep_stolen_vga_memory) |
10852 | return true; | |
10853 | break; | |
10854 | default: | |
10855 | break; | |
10856 | } | |
10857 | ||
10858 | return false; | |
10859 | } | |
e97cc04f JP |
10860 | |
10861 | bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) | |
10862 | { | |
10863 | return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); | |
10864 | } | |
10865 | ||
10866 | bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) | |
10867 | { | |
10868 | return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); | |
10869 | } |